SBAS052

SBAS052 TI1 | Alldatasheet

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© 1996 Burr-Brown Corporation PDS-1333B Printed in U.S.A. August, 1996 Serial Input I/F Mode Control I/F 8X Oversampling Digital Filter with Function Controller SCKI 256fS/384fS VCC AGND Multi-level Delta-Sigma Modulator VOUT L CAP Open Drain DAC Multi-level Delta-Sigma Modulator Low-pass Filter Low-pass Filter BPZ-Cont. VOUT R ZERO DAC MC MD ML LRCIN DIN BCKIN RSTB Power Supply VDD DGND Stereo Audio DIGITAL-TO-ANALOG CONVERTER MPEG2/AC-3 COMPATIBLE TM 49% FPO PCM1720

DESCRIPTION

The PCM1720 is a complete low cost stereo audio digital-to-analog converter (DAC), operating off of a 256fS or 384fS system clock. The DAC contains a 3rd- order ΔΣ modulator, a digital interpolation filter, and an analog output amplifier. The PCM1720 can accept 16-, 20-, or 24-bit input data in either normal or I2S formats. The digital filter performs an 8X interpolation func- tion and includes selectable features such as soft mute, digital attenuation and digital de-emphasis. The PCM1720 can accept standard digital audio sampling frequencies as well as one-half and double sampling frequencies. The PCM1720 is ideal for applications which combine compressed audio and video data such as DVD, DVD- ROM, set-top boxes and MPEG sound cards.

FEATURES

l ACCEPTS 16-, 20-, OR 24-BIT INPUT DATA l COMPLETE STEREO DAC: Includes Digital Filter and Output Amp l DYNAMIC RANGE: 96dB l MULTIPLE SAMPLING FREQUENCIES: 16kHz to 96kHz 8X Oversampling at All Sampling Frequencies l SYSTEM CLOCK: 256f S/384fS l NORMAL OR I 2S DATA INPUT FORMATS l SELECTABLE FUNCTIONS: Soft Mute Digital Attenuator (256 Steps) Digital De-emphasis l OUTPUT MODE: Left, Right, Mono, Mute International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ®PCM1720 SBAS052 Not Recommended For New Designs

All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, and 16-bit input data, SYSCLK = 384fS, unless otherwise noted. PCM1720 PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 16 24 Bits DATA FORMAT Audio Data Format Standard/I2S Data Bit Length 16/20/24 Selectable Sampling Frequency (fS) Standard fS 32 44.1 48 kHz One-half fS 16 22.05 24 kHz Double fS 64 88.2 96 kHz Internal System Clock Frequency 256fS /384fS DIGITAL INPUT/OUTPUT LOGIC LEVEL TTL DYNAMIC PERFORMANCE (1) THD+N at fS (0dB) fS = 44.1kHz –90 –80 dB fS = 96kHz –88 dB THD+N at –60dB fS = 44.1kHz –34 dB fS = 96kHz –31 dB Dynamic Range fS = 44.1kHz 90 96 dB fS = 96kHz 93 dB Signal-to-Noise Ratio(2) fS = 44.1kHz 92 100 dB fS = 96kHz 97 dB Channel Separation fS = 44.1kHz 90 97 dB DC ACCURACY Gain Error ±1.0 ±5.0 % of FSR Gain Mismatch, Channel-to-Channel ±1.0 ±5.0 % of FSR Bipolar Zero Error V OUT = VCC /2 at BPZ ±30 mV ANALOG OUTPUT Output Voltage Full Scale (0dB) 0.62 x V CC Vp-p Center Voltage VCC /2 VDC Load Impedance AC Load 5 kΩ DIGITAL FILTER PERFORMANCE Passband 0.445 f S Stopband 0.555 f S Passband Ripple ±0.17 dB Stopband Attenuation –35 dB Delay Time 11.125/fS sec De-emphasis Error –0.2 +0.55 dB INTERNAL ANALOG FILTER –3dB Bandwidth 100 kHz Passband Response f = 20kHz –0.16 dB POWER SUPPLY REQUIREMENTS Voltage Range V DD , VCC 4.5 5 5.5 VDC Supply Current: ICC + IDD VCC = VDD = 5V, fS = 44.1kHz 18 25 mA VCC = VDD = 5V, fS = 96kHz 25 35 mA TEMPERATURE RANGE Operation –25 +85 °C Storage –55 +100 °C NOTES: (1) Dynamic performance specs are tested with 20kHz low pass filter and THD+N specs are tested with 30kHz LPF, 400Hz HPF, Average-Mode. (2) SNR is tested with Infinite Zero Detection off. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. Not Recommended For New Designs

1 NC — No Connection. 2 SCKI IN System Clock Input: 256f S or 384fS. 3 TEST OUT Reserved for Factory Use. 4* ML IN Latch Enable for Serial Control Data. 5* MC IN Clock for Serial Control Data. 6* MD IN Data Input for Serial Control. 7* RSTB IN Reset Input. When this pin is low, the digital filters and modulators are held in reset. 8 ZERO OUT Zero Data Flag. This pin is low when the data is continuously zero for more than 65,535 cycles of BCKIN. OUT R OUT Right Channel Analog Output. 10 AGND PWR Analog Ground. 11 V CC PWR Analog Power Supply (+5V). 12 V OUT L OUT Left Channel Analog Output. 13 CAP — Common Pin for Analog Output Amplifiers. 14* BCKIN IN Bit Clock for Clocking in the Audio Data. 15* DIN IN Serial Audio Data Input. 16* LRCIN IN Left/Right Word Clock. Frequency is equal to fs. 17 GND PWR Ground. 18 NC — No Connection. 19 V DD PWR Digital Power Supply (+5V). Recommended con- nection is to the analog power supply. 20 DGND PWR Digital Ground. Recommended connection is to the digital ground plane. * These pins include internal pull-up resistors. PIN CONFIGURATION TOP VIEW SSOP

PACKAGE INFORMATION

PRODUCT PACKAGE NUMBER (1) PCM1720 20-Pin SSOP 334-1 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ABSOLUTE MAXIMUM RATINGS Thermal Resistance, NC SCKI TEST ML MC MD RSTB ZERO VOUT R AGND DGND V DD NC GND LRCIN DIN BCKIN CAP V OUT L VCC ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Not Recommended For New Designs

TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = +5V, fS = 44.1kHz, 16-bit input data, unless otherwise noted. Measurement bandwidth is 20kHz DYNAMIC PERFORMANCE THD+N vs VCC , VDD VCC , VDD (V) THD+N at FS (dB) THD+N at –60dB (dB) –84 –86 –88 –90 –92 –94 –30 –34 –38 4.5 5.0 5.5 f S = 96kHz fS = 44.1kHz DYNAMIC RANGE and SNR vs V CC , VDD VCC , VDD (dB) 100 SNR Dynamic Range THD+N vs TEMPERATURE Temperature (°C) THD+N at FS (dB) –84 –86 –88 –90 –92 –90 –25 0 25 50 75 85 100 f S = 96kHz fS = 44.1kHz THD+N and DYNAMIC RANGE vs f S Sampling Frequency, fS (kHz) THD+N (dB) Dynamic Range (dB) –86 –88 –90 –92 –94 44.1 48 88.2 96 Dynamic Range THD+N Not Recommended For New Designs

DE-EMPHASIS ERROR (3kHz) 0 3628 7256 10884 14512 0 4999.8375 9999.675 14999.5125 19999.35 0 5442 10884 16326 21768 Frequency (Hz) 0.6 0.4 0.2 –0.2 –0.4 –0.6 0.6 0.4 0.2 –0.2 –0.4 –0.6 0.6 0.4 0.2 –0.2 –0.4 –0.6 DE-EMPHASIS ERROR (44.1kHz) Frequency (Hz) DE-EMPHASIS ERROR (48kHz) Frequency (Hz) Error (dB) Error (dB) Error (dB) PASSBAND RIPPLE CHARACTERISTIC –0.2 –0.4 –0.6 –0.8 0 0.1134f S 0.2268fS 0.3402fS 0.4535fS dB Frequency (Hz) TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = +5V, RL = 44.1kHz, fSYS = 384fS , and 16-bit input data, unless otherwise noted. DIGITAL FILTER –20 –40 –60 –80 –100 dB OVERALL FREQUENCY CHARACTERISTIC Frequency (Hz) DE-EMPHASIS FREQUENCY RESPONSE (3kHz) 0 5k 10k 15k 20k 25k Frequency (Hz) –10 –12 DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz) 0 5k 10k 15k 20k 25k Frequency (Hz) –10 –12 DE-EMPHASIS FREQUENCY RESPONSE (48kHz) 0 5k 10k 15k 20k 25k Frequency (Hz) –10 –12 Level (dB) Level (dB) Level (dB) Not Recommended For New Designs

MAPPING OF PROGRAM REGISTERS ATTENUATION DATA LOAD CONTROL, LCH Bit 8 (LDL) is used to simultaneously set analog outputs of Lch and Rch. An output level is controlled by AL[0:7] attenuation data when this bit is set to 1. When set to 0, an output level is not controlled and remains at the previous attenuation level. A LDR bit in Register 1 has an equivalent function as the LDL. When one of LDL or LDR is set to 1, the output level of the left and right channel is simulta- neously controlled. The attenuation level is given by: ATT = 20 log (y/256) (dB), where y = x, when 0 ≤ x ≤ 254 y = x + 1, when x = 255 X is the user-determined step number, an integer value between 0 and 255. Example: let x = 255 let x = 254 let x = 1 let x = 0 REGISTER 1 (A1 = 0, A0 = 1) B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 Register 1 is used to control right channel attenuation. As in Register 1, bits 0 - 7 (AR0 - AR7) control the level of attenuation. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 0 res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 REGISTER 1 res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 REGISTER 2 res res res res res A1 A0 PL3 PL2 PL1 PL0 IW1 IW0 OPE DEM MUT REGISTER 3 res res res res res A1 A0 IZD SF1 SF0 res res res ATC LRP I 2S PROGRAM REGISTER BIT MAPPING PCM1720’s special functions are controlled using four pro- gram registers which are 16 bits long. These registers are all loaded using MD. After the 16 data bits are clocked in, ML is used to latch in the data to the appropriate register. Table III shows the complete mapping of the four registers and Figure 6 illustrates the data input timing. ATT = 20 log 255 + 1 256  = 0dB ATT = 20 log 254 256  = ±0.068dB ATT = 20 log 1 256  = ±48.16dB ATT = 20 log 0 256  = ±∞ REGISTER 0 (A1 = 0, A0 = 0) B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 REGISTER BIT NAME NAME DESCRIPTION Register 0 AL (7:0) DAC Attenuation Data for Lch LDL Attenuation Data Load Control for Lch A (1:0) Register Address res Reserved Register 1 AR (7:0) DAC Attentuation Data for Rch LDL Attenuation Data Load Control for Rch A (1:0) Register Address res Reserved Register 2 MUT Left and Right DACs Soft Mute Control DEM De-emphasis Control OPE Left and Right DACs Operation Control IW (1:0) Input Audio Data Bit Select PL (3:0) Output Mode Select A (1:0) Register Address res Reserved Register 3 I 2S Audio Data Format Select LRP Polarity of LRCIN (pin 7) Select ATC Attenuator Control SYS System Clock Select SF (1:0) Sampling Rate Select IZD Infinite Zero Detection Circuit Control A (1:0) Register Address res Reserved Register 0 is used to control left channel attenuation. Bits 0 - 7 (AL0 - AL7) are used to determine the attenuation level. The level of attenuation is given by: ATT = [20 log10 (ATT_DATA/255)] dB TABLE III. Internal Register Mapping. Not Recommended For New Designs

REGISTER 2 (A1 = 1, A0 = 0) B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 res res res res res A1 A0 PL3 PL2 PL1 PL0 IW1 IW0 OPE DEM MUTE Register 2 is used to control soft mute, de-emphasis, opera- tion enable, input resolution, and output format. Bit 0 is used for soft mute: a “HIGH” level on bit 0 will cause the output to be muted (this is ramped down in the digital domain, so no “click” is audible). Bit 1 is used to control de-emphasis. A “LOW” level on bit 1 disables de-emphasis, while a “HIGH” level enables de-emphasis. Bit 2, (OPE) is used for operational control. Table IV illustrates the features controlled by OPE. SOFTWARE MODE DATA INPUT DAC OUTPUT INPUT Zero Forced to BPZ (1) Enabled Other Forced to BPZ (1) Enabled Zero Controlled by IZD Enabled Other Normal Enabled OPE = 1 OPE = 0 TABLE IV. Output Enable (OPE) Function. OPE controls the operation of the DAC: when OPE is “LOW”, the DAC will convert all non-zero input data. If the input data is continuously zero for 65, 536 cycles of BCKIN, the output will be forced to zero only if IZD is “HIGH”. When OPE is “HIGH”, the output of the DAC will be forced to bipolar zero, irrespective of any input data. IZD = 1 IZD = 0 DATA INPUT DAC OUTPUT Zero Forced to BPZ (1) Other Normal Zero Zero(2) Other Normal TABLE V. Infinite Zero Detection (IZD) Function. RSTB = “HIGH” RSTB = “LOW” SOFTWARE MODE DATA INPUT DAC OUTPUT INPUT Zero Controlled by OPE and IZD Enabled Other Controlled by OPE and IZD Enabled Zero Forced to BPZ (1) Disabled Other Forced to BPZ (1) Disabled TABLE VI. Reset (RSTB) Function. NOTE: (1) Δ∑ is disconnected from output amplifier. (2) Δ∑ is connected to output amplifier. Bits 3 (IW0) and 4 (IW1) are used to determine input word resolution. PCM1720 can be set up for input word resolu- tions of 16, 20, or 24 bits: Bit 4 (IW1) Bit 3 (IW0) Input Resolution 0 0 16-bit Data Word 0 1 20-bit Data Word 1 0 24-bit Data Word 0 0 Reserved Bits 5, 6, 7, and 8 (PL0:3) are used to control output format. The output of PCM1720 can be programmed for 16 different states, as shown in Table VII. PL0 PL1 PL2 PL3 Lch OUTPUT Rch OUTPUT NOTE 0 0 0 0 MUTE MUTE MUTE 0 0 0 1 MUTE R 0 0 1 0 MUTE L 0 0 1 1 MUTE (L + R)/2 0 1 0 0 R MUTE 0 101 R R 0 1 1 0 R L REVERSE 0 1 1 1 R (L + R)/2 1 0 0 0 L MUTE 1 0 0 1 L R STEREO 1 010 L L 1 0 1 1 L (L + R)/2 1 1 0 0 (L + R)/2 MUTE 1 1 0 1 (L + R)/2 R 1 1 1 0 (L + R)/2 L 1 1 1 1 (L + R)/2 (L + R)/2 MONO TABLE VII. Programmable Output Format. REGISTER 3 (A1 = 1, A0 = 1) B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 res res res res res A1 A0 IZD SF1 SF0 res res res ATC LRP I 2S Register 3 is used to control input data format and polarity, attenuation channel control, system clock frequency, sam- pling frequency and infinite zero detection. Bits 0 (I2S) and 1 (LRP) are used to control the input data format. A “LOW” on bit 0 sets the format to “Normal” (MSB-first, right-justified Japanese format) and a “HIGH” sets the format to I2S (Philips serial data protocol). Bit 1 (LRP) is used to select the polarity of LRCIN (sample rate clock). When bit 1 is “LOW”, left channel data is assumed when LRCIN is in a “HIGH” phase and right channel data is assumed when LRCIN is in a “LOW” phase. When bit 1 is “HIGH”, the polarity assumption is reversed. Bit 2 (ATC) is used for controlling the attenuator. When bit 2 is “HIGH”, the attenuation data loaded in program Register 0 is used for both left and right channels. When bit 2 is “LOW”, the attenuation data for each register is applied separately to left and right channels. Bits 6 (SF0) and 7 (SF1) are used to select the sampling frequency: SF1 SF0 Sampling Frequency 0 0 44.1kHz group 22.05/44.1/88.2kHz 0 1 48kHz group 24/48/96kHz 1 0 32kHz group 16/32/64kHz 1 1 Reserved Not Defined Bit 8 is used to control the infinite zero detection function (IZD). Not Recommended For New Designs

www.ti.com 27-Aug-2011 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) PCM1720E NRND SSOP DB 20 65 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1720E/2K NRND SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1720E/2KG4 NRND SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1720EG4 NRND SSOP DB 20 65 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM1720E/2K SSOP DB 20 2000 336.6 336.6 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 Pack Materials-Page 2

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