SB0800

MC34SB0800 NXP | Alldatasheet

Document overview

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• PDF pages: 68

Technical content

Features

• Operating voltage 6.0 V to 36 V
• Eight valves control
• Four current regulated valves up to 2.25 A (5.0 kHz)
• Four PWMed valves up to 5.0 A (5.0 kHz)
• High-side predriver for valves protection
• Pump motor predriver up to 500 Hz PWM
• 16-bit SPI interface with watchdog
• Three 10-bit ADC channels
• High-side driver for general purpose (RDS(on) 1.0 Ω)
• Low-side driver for resistive charge (RDS(on) 14.0 Ω)
• Die temperature warning
• Supervision

Figure 1. SB0800 simplified 5.0 V application diagram

Applications

• Spot Welding • Dialysis machines
• Fluid Coating • Blood pressure
• Temperature Control • Soda dispensers
• Brake Pressure
• Laser Cutting
• Heavy equipment and construction machinery
• Bottle Moulding • Fork lifts
• Filling Pressure
• 3 D P r i n t e r
• Oxygen Concentrator
• Water control system for irrigation (connected to farm tractor)
• Medical test equipment • Food control in animal farm MC34SB0800 DOSV P53_CFG VPWR GND_P0,1...5 GND_A GND_D LSD1 LSD2 LSD3 LSD4 Solenoid coil PD_D PD_G PD_S M VCC5 External 5.0V RegulatorVPWR NC LD ADINx CP HD_D HD_G HD_S LSD5 LSD6 LSD7 LSD8 Solenoid coil SO SI CSB SCLK RSTB MCU HS VINT_A VINT_D VPWR VPWR VPWR VPWR

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1 Orderable parts

Table 1. Orderable part variations

• Four PWMed valve controls and four current regulated valve controls
• Safe switch control
• Pump motor control up to 500 Hz
• High-side driver for general purpose
• Low-side FET for resistive loads (1) Notes 1. To order parts in Tape & Reel, add the R2 suffix to the part number.

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2 Internal block diagram

Figure 2. SB0800 simplified internal block diagram

16 Bit SPI

3 Pin connections

3.1 Pinout diagram

Figure 3. SB0800 64-pin LQFP-EP pinout diagram

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3.2 Pin definitions

Table 2. SB0800 pin definitions

3.3 V Notes

1 RSTB Reset Reset PIN external pull-up

2 GND_P0 Supply Power Ground 0 (4) no no

4 GND_P1 Supply Power Ground 1 no no (4)

13 GND_P2 Supply Power Ground 2 no no (4)

14 SCLK SPI SPI Interface Clock Input no no

15 SI SPI SPI Interface Digital Input no no

16 CSB SPI SPI Interface Chip Interface no no

18 LD Low-side Driver Open Drain Output for Low-side no no

25 VPWR Supply Supply PIN connect to battery through reverse

26 HS High-side Driver for General Purpose

28 PD_G Motor Pump Driver Gate Output to Control Pump Motor FET

29 PD_S Motor Pump Driver Source Feedback Pump Motor FET

30 PD_D Motor Pump Driver Drain Feedback Pump Motor FET

31 HD_G High-side Driver for Valve’s Fail-safe

32 HD_S High-side Driver for Valve’s Fail-safe

33 HD_D High-side Driver for Valve’s Fail-safe

37 GND_P3 Supply Power Ground 3 no no (4)

46 GND_P4 Supply Power Ground 4 no no (4)

48 ADIN3 ADC Analog to Digital Input 3 no no

49 ADIN2 ADC Analog to Digital Input 2 no no

50 ADIN1 ADC Analog to Digital Input 1 no no

51 GND_A Supply Analog Ground no no

54 GND_D Supply Digital Ground no no

56 DOSV Supply Digital Output Voltage Supply, DOSV under

57 SO SPI SPI Interface Digital Output DOSV bias

3.3 V) no no

1. Pins must be shorted together
2. 220 nF/10 V capacitor needed
3. All GND_Px pins must be shorted together at the PCB level.

Table 2. SB0800 pin definitions (continued)

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4 General product characteristics

4.1 Maximum ratings

Table 3. Maximum ratings cause a malfunction or permanent damage to the device.

4.2 Operating conditions

• LSD1—4, with 20 mH load —3 0 mJ ELSD5—8 Energy capability (EAR) at 125 °C
• LSD5—8, with 20 mH load —4 0 mJ EHS Energy capability (EAR) at 125 °C
• HS, with 20 mH load —1 3 mJ Currents ILSDX(POS) Drain continuous current; during on state
• L S D x —5 . 0 A ILSDX(NEG) Maximum negative current for 5.0 ms without being destroyed
• L S D x -6.0 — A IDIG Input current
• P53_CFG, SI, CSB, SCLK, RSTB -20 20 mA

Table 4. Operating conditions Functional operating supply voltage. Device is fully functional.

• All features are operating 6.0 — 36 V VCC5 Functional operating supply voltage. Device is fully functional.
• All features are operating. 4.75 — 5.25 V VDOSV Functional operating supply voltage. Device is fully functional.
• All features are operating. 3.13 — 5.25 V

Table 3. Maximum ratings (continued) cause a malfunction or permanent damage to the device.

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4.3 Supply currents

4.4 Thermal ratings

Table 5. Supply currents under nominal conditions, unless otherwise noted. Table 6. Thermal data

1. Lead soldering temperature limit is for 10 seconds maximum duration . Lead soldering can be done twice. Device must be delivered in dry pack.
2. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and

orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

4.5 Logical inputs and outputs

Table 7. Logical inputs/outputs

• P53_CFG, RSTB, SI, CSB, SCLK, ADIN1, ADIN2, ADIN3 —2 . 0V VIL_X Input Low-voltage
• P53_CFG, RSTB, SI, CSB, SCLK, ADIN1, ADIN2, ADIN3 0.8 — V Logical outputs VOH_X Input High-voltage, with 1.0 mA
• S O 0.8 x DOSV — V VOL_X Input Low-voltage, with 1.0 mA
• S O —0 . 4V VOL_RSTB RSTB Low-voltage, with 1.0 mA
• R S T B —0 . 4V

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5 General description

5.1 Block diagram

Figure 4. SB0800 functional block diagram

5.2 Functional description

The SB0800 device is a valves and pump controller, designed for use in harsh industrial environments, requiring few external components.

5.3 Features

This section presents the detailed features of SB0800. Table 8. Device features set

• High-side Fail-safe FET driver
• Overcurrent shutdown
• Load leakage detection High-side Driver for general purpose
• High-side switch connected to VPWR (1.0 Ω max Rds(on) at 125 °C)
• Open load detection
• V DS state monitoring
• Overcurrent shutdown
• Overtemperature shutdown Pump Driver • Pump motor driver up to 500 Hz PWM frequency controllable through SPI command or a digital signal
• Overcurrent shutdown between external FET drain and source Four Valves Low-side (PWM) Four Valves Low-side One Three Analog to Motor Pump Predriver (500 Hz) SPI Registers (regulated) Supervision Digital Converter (16 Bits) High-side Driver

• Solenoid driver (300 mΩ max. RDS(on) at 125 °C) works either as current regulator or as PWM
• Current regulation deviation: ±2.0%
• Configurable PWM frequency from 3.0 kHz to 5.0 kHz
• PWM duty cycle 10-bit resolution
• Open load detection
• V DS state monitoring
• Overcurrent shutdown
• Overtemperature shutdown
• Send current regulation error flag ( only for current regulation modules) Low-side solenoid driver (x4)
• Solenoid driver (225 mΩ max RDS(ON) at 125 °C) are PWM low-side driver
• Configurable PWM frequency from 3.0 kHz to 5.0 kHz
• PWM duty cycle resolution 0.39%
• Open load detection
• V DS state monitoring
• Overcurrent shutdown
• Overtemperature shutdown
• Max switch-off energy 40 mJ Low-side resistive Driver
• Low-side driver (20 mA max, RDS(on) 8.0 Ω)
• Open load detection
• V DS state monitoring
• Overcurrent shutdown
• Overtemperature shutdown Low-side Driver
• Low-side driver (350 mA max, RDS(on) 1.0 Ω)
• Open load detection
• V DS state monitoring
• Overcurrent shutdown
• Overtemperature shutdown Analog to Digital Converter (x3)
• 1 0 - b i t A D C
• External ADINx pins
• Internal voltages and temperature information
• Allow to control the pump by a MCU
• Allow to control the low-side resistive driver by a MCU Supervision
• VINT_x undervoltage (internal regulator)
• VCC5 & DOSV undervoltage (supply voltage from external)
• Watchdog fault
• ALU check counter overflow
• External reset fault
• VPWR undervoltage and overvoltage detections
• Mismatch MAIN-AUX OSC CLK
• Temperature warning
• SPI failure
• Charge pump issue
• GND supervision

Table 8. Device features set (continued)

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6 Functional block description

6.1 Error handling

Table 9. Error handling

1. If xxx_clr_flt is written “1” by SPI, all SPI flags are set “0”, so SW engineer has to read the SPI flag first and then write xxx_clr_flt to default value “0”.
2. SW engineering can monitor inter nal supply voltage in real time with ADC reading, and can use fail-safe function. If these ADC results are not in

a certain range, uC can reset the SB0800 (see ADC section).

1. Fail-safe switch off until power is off

Table 9. Error handling (continued)

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6.2 High-side driver

6.2.1 Function description

The high-side driver is intended to control the fail-safe switch for the overall solenoid path, and HD_G is controlled by the SPI command. Figure 5. High-side driver

6.2.2 High-side driver and fault protection

6.2.2.1 Overcurrent

1 to the “HD_clr_flt” register, and then turned on by a SPI command.

6.2.2.2 Load leakage detection

the FET is discharged by a constant current, which is controlled fast and slow by a SPI command (HPD_sr).

6.2.2.3 External component s of high-side driver

For protection, external resistors RHD_D, RHD_G, and RHD_S are required (for example: RHD_D = 100 Ω, RHD_G = 100 Ω, RHD_S = 100 Ω).

6.3 Pump motor pre-driver

6.3.1 Function description

a SPI command (pd_on) or through the ADIN1 pin by selecting Adin1_dis bit at “1”. Figure 6. Pump motor predriver Table 10. High-side driver electrical characteristics

• 5 . 5 V ≤ VPWR < 6.0 V
• 6 . 0 V ≤ VPWR < 7.0V
• 7 . 0 V ≤ VPWR < 10 V
• 1 0 V ≤ VPWR < 36 V VPWR+ 4 VPWR+5 VPWR+7 VPWR+10 VPWR+ 15 VPWR+15 VPWR+15 VPWR+15 V VHD_OFF HD_G switch-off voltage —— 1 V tHD_ON Turn-on time - After tHD_LC —— 1 . 4 m s IHD_OFF_SLOW Turn-off current slow - VHD_G > 2.0 V. HPD_sr = 0 70 100 200 μA IHD_OFF_FAST Turn-off current fast - VHD_G > 2.0 V, HPD_sr = 1 1.0 2.0 4.5 mA HD_S lLEAK_HD_SRC Leakage current - 0 ≤ VHD_S ≤ 36 V, 6.0 ≤ VPWR ≤ 36 V ——5 0 μA HD_D LLEAK_HD_DRN Leakage current - VCC5 = DOSV = 0 V, HD_D = PD_D = VPWR = 36 V ——1 0 μA Overcurrent detection VHD_OC Overcurrent detection threshold - VHD_D-VHD_S, RDRN, RSRC = 100 Ω -15% 1.0 +15% V Load leakage current detection IHD LC HD_S source current —1 . 5—m A Logic Gate Driver Vbat PGND Status / Fault (Trough SPI) Overcurrent Adin1_dis (SPI) ADIN1 pd_on (SPI) PD_mt_cfg OCF_pd M PD_D PD_G PD_S

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6.3.2 Fault Detection

6.3.2.1 Overcurrent

the output PD_G is switched off. Overcurrent detection logic has a masking time from pd_on turn-on against malfunctions in transient time. register, and then turned on by a SPI command. slow by a SPI command (HPD_sr).

6.3.2.2 External compone nts of pump predriver

Table 11. Pump motor predriver electrical characteristics

• 5 . 5 V ≤ VPWR < 6.0 V
• 6 . 0 V ≤ VPWR < 7.0V
• 7 . 0 V ≤ VPWR < 10 V
• 1 0 V ≤ VPWR < 36 V VPWR+ 4 VPWR+5 VPWR+7 VPWR+10 VPWR+ 15 VPWR+15 VPWR+15 VPWR+15 V VPD_OFF PD_G switch-off voltage - pull-up current < 20 μA —— 1 V tPD_ON Turn-on time —0 . 5—m s IPD_OFF_SLOW Turn-off current slow - PD_G > 2.0 V. HPD_sr = 0 70 100 200 μA IPD_OFF_FAST Turn-off current fast - PD_G >2.0 V, HPD_sr = 1 1.0 2.0 4.5 nA PD_S lLEAK_PD_SRC Leakage current - 0 ≤ VPD_src ≤ 36 V, 6.0 ≤ VPWR ≤ 36 V ——1 0 μA PD_D ILEAK_PD_DRN Leakage current - VCC5 = DOSV = 0 V, HD_D = PD_D = VPWR = 36 V ——1 0 μA Overcurrent detection VPD_OC Overcurrent detection threshold - VPD_D - VPD_SRC, RDRN, RSRC = 2.0 kΩ -15% 1.0 +15% V tPD_OC1 Overcurrent detection filter time - OCF_pd = 0 —T 2— μs tPD_OC2 Overcurrent detection filter time - OCF_pd = 1 —4 * T 1— μs

6.4 Low-side driver

6.4.1 Functional description

against short-circuit and overtemperature at the outputs. Figure 7. PWM low-side driver current slopes are controlled by a SPI command to reduce switching loss. necessary voltage on the output transistor gate to minimize the On-resistance of the output switch. and the LSB of the 8 bits is weighted with an 0.39% duty. Each channel has an 8-bit SPI register of PWM duty cycle. The PWM low-side driver uses each channel as a digital low-side switch. The SB0800 provides interleaved phase shift switching to minimize switching noise of the solenoid coil. Each LSD1 to 4 have this cycle.

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Figure 8. PWM valve control interleave Table 12. Low-side driver electrical characteristics VPWR = 6.0 to 36 V, DOSV = 3.13 to 5.25 V, TJ = -40 to 125 °C, unless otherwise specified.

• T J = 125 °C; 9.0 V ≤ VPWR ≤ 36 V; ILOAD = 2.0 A — — 0.255 Ω RON_LSD14_E On Resistance Channel 1 to 4: CR (extended mode)
• T J = 125 °C; 5.5 V ≤ VPWR ≤ 9.0 V; ILOAD = 2.0 A — — 0.33 Ω I LEAK_LSD Drain Leakage Current
• L S D = 3 6 V — — 10 μA VCL_LSD Active Clamp Voltage — 38 45 V Timings tR_CR1 tF_CR1 Rise Time/Fall Time
• 10% to 90%, ILOAD = 1.0 A, VPWR =24 V; no capacitor didt = 0 (SPI bit) 1.0 0.1 1.7 1.35 3.0 3.0 μs tR_CR2 tF_CR2 Rise Time/Fall Time
• 10% to 90%, ILOAD = 1.0 A, VPWR = 24 V; no capacitor didt = 1 (SPI bit) 0.05 0.1 0.5 1.0 1.0 3.0 μs tD on CR tD off CR Turn on/off Delay Time
• Digital 1 to 10% or 90%, ILOAD = 1.0 A, VPWR = 24 V, no capacitor 0.0 — 3.0 µs (10) 250 Ms (4.0 kHz PWM Frequency) Ch 1 Ch 2 Ch 3 Ch 4 SPI

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6.4.2 LSD1 to LSD4 curre nt regulation driver

Figure 9. PWM low-side driver (current regulated) duty cycle of the low-side power switch. The PI regulator characteristic can be adjusted via the SPI.

• LF_PWM xx = 111
• LF_PWM xx = 110
• LF_PWM xx = 101
• LF_PWM xx = 100
• LF_PWM xx = 000 (default)
• LF_PWM xx = 011
• LF_PWM xx = 001
• LF_PWM xx = 010 -20% 3.0 3.2 3.4 3.6 3.9 4.2 4.5 5.0 20% kHz 0000 0000 0000 0001 1111 1110 1111 1111 PWM Duty Cycle Programming (8-bits)
• Can be used for digital low-side driver OFF 0.39 99.61 ON Notes 10. Digital: internal digital signal delivered by interleave synchronization block. See Figure 8.

Table 12. Low-side driver electrical characteristics (continued) VPWR = 6.0 to 36 V, DOSV = 3.13 to 5.25 V, TJ = -40 to 125 °C, unless otherwise specified.

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6.4.2.1 Target current

6.4.2.2 Current measurement

“current mirror” circuit) generates across an internal resistance a voltage relative to ground, this being proportional to the output current.

6.4.3 PI characteristics

Digital PI-regulator with the Transfer function is programmed via the SPI register. feedback and provides a faster settling of the regulated current after disturbances like battery voltage surge. 0 1 current regulation Read output duty cycle value for gate driver.

10 P W M Read programmed PWM duty cycle (to check SPI write)

11 P W M Read hardware ADC current value

Table 13. Duty cycle descriptions The duty cycle of PWM output is clamped minimum by options and maximum 100% (see 6.10, “SPI and data register").

• the measurement is done at tON/2 by consequence
• the regulation current will be set at tON/2 101 3.12%
• for a duty cycle > 10%, the measurement is done at tON/2
• for a duty cycle 3.2% < DC < 10%, the measurement is done at tON/2 for 10% of duty cycle up at tON for 3.2% of duty cycle KI

Current – ADC result > “error threshold” during tCR_ERR then LSDx_crer is set to 1. duty is controlled by the SPI bit FDCL (See SPI and data register).

• for a duty cycle > 10%, the measurement is done at tON/2
• for a duty cycle 3.2% < DC < 10%, the measurement is done at tON/2 for 10% of duty cycle up at tON for 3.2% of duty cycle
• for a duty cycle set at 1.56%, no measurement is done 311 3.12% + skip min duty cycle every two cycles
• for a duty cycle > 10%, the measurement is done at tON/2 by consequence the regulation current will be set at tON/2
• for a duty cycle 3.2% < DC < 10%, the measurement is done at tON/2 for 10% of duty cycle up at tON for 3.2% of duty cycle
• no measurement is done during the skipping mode

Table 14. LSD1 to LSD4 current regulation driver electrical characteristics

• 0 mA ≤ ITARGET < 50 mA, includes ADC error
• 5 0 mA ≤ ITARGET < 100 mA, includes ADC error
• 100 mA ≤ ITARGET < 250 mA, includes ADC error
• 250 mA ≤ ITARGET < 400 mA, includes ADC error
• 400 mA ≤ ITARGET < 2.25 A, includes ADC error ±10 ±2.0 mA (11) Notes 11. Maximum regulation deviation performances no ted in the table depend on external conditions (VPWR, load (R,L)).

The duty cycle of PWM output is clamped minimum by options and maximum 100% (see 6.10, “SPI and data register").

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6.5 Low-side driver for resistive load

6.5.1 Power output stages

Figure 10. Low-side driver for resistive load diagram block current path, LD has no sink current. Table 15. Low-side driver electrical characteristics

• TJ = 125 °C, 6.0 V ≤ VPWR ≤ 36 V — — 14 Ω DC Current Capability — — 20 mA ILEAK_LD Drain Leakage Current
• V PWR = 0, VCC5 = 0, LD = 30 V, no sink current — — 5.0 μA Timings tD_ON_LD Turn On Delay Time for LD — — 1.0 μs (12) tD_OFF_LD Turn Off Delay Time for LD — — 1.0 μs (12) Notes 12. From Digital Signal to 50% (turn ON) or 50% (turn OFF). R L = 1.0 kΩ, VPWR = 30V, no capacitor Logic Open VDS Monitoring Gate Driver Overcurrent Overtemperature Vbat GND Controlled by SPI Status / Fault (Through SPI) No Sink Current LD

6.5.2 Fault detection

(SPI error flag only). This function only operates during the off state. bit. If the VDS voltage is higher than OPLD with a filter time (T1), vds_ld is set to “1”. turned on by a SPI command (LD_on). to the normal state, a SPI write “1” to “LD_clr_flt”, then turning on a SPI command (LD_on). Table 16. Low-side driver electrical characteristics

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6.6 Analog to digital converter (x3ch)

• Three analog input pins: ADINx
• Internal voltage supplies (VINT_A, VINT_D, VPRE10, VPRE12, VCP_VPWR)
• Average temperature of die, which is used by the temperature warning detection circuit (TEMP). Refer to the SPI Message Structure, Message #9.
• Allows to read the current drain by the LSD1-4 in PWM mode. Also, it is possible to use ADIN1 and / or ADIN2 to control respectively the motor pump and / or the low-side driver for resistive load directly by the MCU.

Table 17. Direct control of pump and low-side

0 Pd_on bit (SPI command)

1 Ld_on (SPI command)

Table 18. ADC electrical characteristics

1. If ADINx voltage is between VCC5 to max_rating, the ADC val ue does not change. Also between VCC5 min and GND, the ADC value does not
2. SW engineer can monitor internal supply voltage in real time with ADC, SPI reading, and can use fail-safe function.

6.7 High-side

6.7.1 Function description

Figure 11. High-side driver

6.7.2 Fault detection

6.7.2.1 Ground shift

& the high-side output) without damage to the SB0800 (see Figure 11).

6.7.2.2 Open load

bit is set HS_op (SPI error flag only). The function only operates during the off state.

6.7.2.3 V DS state monitoring

vds_HS bit. If the HS output is lower than OP_hs with a filter time (T1), vds_HS is set to “1”.

6.7.2.4 Overcurrent

then a turn on by the SPI command (HS_on).

6.7.2.5 Overtemperature

returns to a normal state, a SPI write “1” to “HS_clr_flt”, and then a turn on by the SPI command (HS_on).

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Table 19. High-side electrical characteristics

• T J = 125 °C, 9.0 V ≤ VPWR ≤ 36 V
• T J = 125 °C, 6.0 V ≤ VPWR ≤ 9.0 V 1.0 1.5 Ω DC current capability — 270 — mA ILEAK_HS Drain leakage current - VPWR = 14 V, VCC5 = 0 —— 2 . 0 μA V_BVDSS _HS Breakdown Voltage 40 — — V Timing tD_ON_HS/ tD_OFF_HS Turn on/off delay time ——2 0 μs (15) Overcurrent shutdown OC_HS Overcurrent shutdown threshold current — 650 — mA tOC_HS Overcurrent shutdown filter time - measured by sense FET —T 1— μs Open load detection OP_HS Open load detection threshold - include GND shift = 2.0 V, also used for VDS monitoring —4 . 0— V VDS monitoring tVDS_HS VDS state filter time —T 1— μs (16) Overtemperature shutdown OT_HS Overtemperature detection threshold 180 195 210 °C tOT_HS Overtemperature detection filter time —T 1— μs Notes 15. From digital signal to 50% (turn ON) or 50% (turn OFF). R L=1.0 KΩ, VPWR = 30 V, no capacitor 16. Used open load detection comparator rise & fall edge filter time

6.8 Monitoring module

Figure 12. Block diagram of SB0800 monitoring module and MCU calculates the expected correct result, which is compared to the actual result from MCU. by a write of MR, with the next MR written within in a fixed time window. A new cycle time is started automatically by a write of MR. Figure 13. Timing diagram of SB0800 monitoring module and MCU by one. The ERR_CNT 3-bit can be read by the SPI interface.

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6.8.1 ERR_CNT behavior

window (tWD) counter is reset to zero.

6.8.2 Linear feedback shift register (LFSR)

pseudo-random number. The FF hex-value cannot be used for the SEED. Figure 14. Diagram of linear feedback shift register (LFSR)

6.8.3 ALU checker

Both the SB0800 monitoring module and the MCU have an ALU checker. The ALU checker work in parallel with the SB0800 and MCU. The 8-bit input of the ALU checker is the 8-bit output of LFSR. The ALU checker proceeds on five sequential calculations. Figure 15. Diagram of ALU checker

Check when the pin reset goes high. Figure 16. Watchdog sequence example

6.9 Supervision

Table 20. Monitoring module electrical characteristics

1. The maximum setting window for the watchdog can be dec reased to a SPI timing access. The range given in Table 33 shows the typical use case.

Table 21. Reaction to supply fault and reset condition reset to 1. After first read of Vint_uv, it is set back to 0. RST_clk, it is set back to 0.

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RST_CLK) and hd_on (tLSDx_HD_G timing). RST_CLK) and hd_on (tLSDx_HD_G timing).

• hd_on (tLSDx_HD_G timing).
• hd_on (tLSDx_HD_G timing).

A. LSDx Duty cycle or current set point. A. LSDx Duty cycle or current set point.

1. State defines for the duration of the fault and the following reset recovery time period.

SPI write message #0 has first to be executed to clear any reset or fault flags. Then new SPI command can be sent. Table 22. Start point of reset recovery time Table 21. Reaction to supply fault and reset condition (continued)

6.9.1 Additional safety functions

6.9.1.1 VINT_A or VINT_D undervoltage supervision

The SB0800 uses an internal supply for analog functions (VINT_A) and digital functions (VINT_D). The supply voltage VINT_A and VINT_D are supervised for undervoltage. When the voltage becomes lower than each threshold VINT_A_uv and VINT_D_uv, the RSTB pin is asserted low after detection filter time (tVINT). This reset state will continue until the voltage at pin VINT raises again. And if VINT becomes higher than each threshold VINT_A_uv and VINT_D_uv for same filter time (tVINT), the RSTB Pin goes high after reset recovery time (tRST_REC) and the related flag of the SPI register is set to high. For stabilization the internal supply VINT_A & VINT_D requires external capacitors. Two band-gaps are included in the SB0800, one is for the voltage reference and the other is for the diagnostic. The VINT_A and VINT_D voltages are sending through the SPI.

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6.9.1.2 VCC5 supervision

See Table 21 Reset condition and reaction.

6.9.1.3 DOSV supervision

flag of the SPI register is set to high. The P53_CFG pin decides the DOSV pin undervoltage threshold. Figure 17. Configuration of VCC5 and DOSV for 5.0 V or 3.3 V application

6.9.1.4 Charge pump

The charge pump generates a voltage of typically 12 V above the supply VPWR. The charge pump voltage is intended for internal use only. No additional load shall be connected to the CP pin. The charge pump requires a capacitor for energy storage and to cover transients. The voltage difference between CP and VPWR can be read by the SPI.

6.9.1.5 Internal clock supervis ion (mismatch MAIN-AUX CLK)

fault and if a fault is detected, the SB0800 resets with the RST_CLK function (Table 21). This function starts when RSTB is in a high state. flag (RST_CLK) is cleared on the first SPI message. reference, therefore if the CLK1 frequency changes, the time window T2 cannot be guaranteed.

improves electromagnetic compatibility (EMC) performance. reset is detected during reset recovery time and the CLK_RST (reading message #0) flag should read in a normal condition.

6.9.1.6 Die temperature warning

overtemperature. In case of a temperature warning, outputs are not shutdown and the SPI-Bit shows the actual status at accessing time.

6.9.1.7 Ground supervision

1. Connection degraded (resistive path)
2. Disconnection (open physically) during a sequence (in Normal mode), the logic embedded will be frozen, because the voltage

Table 23. Electrical characteristics

• P53_CFG = Low (< 0.8 V)
• P53_CFG = High (> 2.0 V) 4.5 2.9 V tDVUV Undervoltage Reset Filter Time —T 1— μs VCC5 undervoltage VCC5_UV Undervoltage Threshold —4 . 5— V tVCUV Undervoltage Filter Time —T 1— μs VCC5 supply I_VCC5 I_DOSV Consumption Current
• VCC5 = 5.0 V; HD,PD = on; RSTB = high
• During SPI communication mA

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Table 23. Electrical characteristics (continued)

goes to “0” after 1 clock from fault flag reset. Figure 18. Timing diagram of xxx_clr_flt

6.10 SPI and data register

6.10.1 Function description

• Full duplex, four-wire synchronous communication
• Slave mode operation only
• Fixed SCLK polarity and phase requirements
• Fixed 16-bit command word
• SCLK operation up to 10.0 MHz The Serial Peripheral Interface (SPI) is used to transmit and receive data synchronously with the MCU. Communication occurs over a full- duplex, four-wire SPI bus. The 34SB0800 device operates only as a slave device to the master, and requires four external pins; SI, SO, SCLK, and CSB. All words are 16 bits long and MSB is sent first. The SPI simultaneously turns on the serial output SO and returns the MISO return bits. When receiving, valid data is latched on the rising edge of each SCLK pulse. The serial output data is available on the rising edge of SCLK, and transitions on the falling edge of SCLK. The number of clock cycles occurring on the pin SCLK while the CSB pin is asserted low must be 16. If the number of clock pulses is not 16 or a parity fault, the SPI MOSI data is ignored. The SB0800 takes even parity. On next data read SO message, “Fmsg” bit sets to 1, and other data bits sets to 0. The parity bit sets to 1. On the first SPI communication after reset, the read SO message sets to 1010101010101010. Timing T1 Logic time base T1 14.4 18.2 22 μs T2 Logic time base T2 232 293 360 μs Notes 19. The t CLK parameter is decided by a frequency checker and comparing two clocks. If either main clock or AUX clock frequency disappears longer than T1, the SB0800 goes to reset by the clock frequency checker and the CLK_RST flag will be detected. Meanwhile, comparing the main clock and AUX clock is done during T2 and the SB0800 is possible to go to reset every T2. Because measurement and reset activation are asynchronous, tCLK can reach 2*T2 in the worst case by comparing two clocks. 20. For more details, refer to the HD_G & PD_G parameters

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transferred to the shift register after the corresponding MOSI command is received from the MCU. Figure 19. SPI timing diagram Table 24. SPI timing electrical characteristics

1. The inputs of the SPI module (SCLK, CSB, SI) are driven between 0 V and DOSV voltage.

6.10.2 SPI message structure

DEC BIN 9 8 7 6 5 4 3 2 1 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 00000 SED<7:0> HPD_s r PD_mt _cfg Version dosv_u v Vcc_ uv Vint_ uv RST_ cl k RST_ ext RST_ alu RST_ wd X HPD_s r PD_mt _cfg 1 00001 P charac I charac lsd_sin k_dis 1 0 Manufacturing data P charac I charac lsd_sin k_dis XX 20 0 0 1 0 Reserved 3 00011 0 0 0 0 FM_ amp FM_ EN StopC L K2 Adin2_ en Adin1_ dis OCF_p d SB0800_CLK_CNT<7:0> Vpwr_ ov X Vpwr_ uv FGND OTW X 40 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X TE MP< 9:0> 50 0 1 0 1 0 0 0 0 pd_on hd_on 0 0 HS_on LD_on PD_oc HD_oc X X VINT_D<9:0> 6 00110 HS_clr _flt 0 0 0 HD_clr _flt 0 0 LD_cl r_flt PD_clr _flt LSD_c lr_flt ld_oc ld_op ld_ot vds _l d vpr e10 < 9: 0 > 7 00111 0 0 Iclamp didt FDCL LLC <1> LLC <0> CR_fb CR_dis CR_dis

34 X CR_fb CR_dis

CR_dis 34 vpr e12 < 9: 0 > 8 01000 0 0 0 0 0 0 0 0 0 0 lsd1_c r er lsd2_c r er lsd3_c r er lsd4_c r er vc p_vpwr< 9 : 0> 90 1 0 0 1 0 0 0 0 LF_PWM_14 LF_PWM_58 X X X X VINT_A<9:0> 10 01010 LSD1 duty cycle (8-bit) or current set point (10-bit) lsd1_o c lsd1_o p lsd1_ot vds_LS D1 LSD1 duty cycle (8bit) or current read (10 bit) 11 01011 LSD2 duty cycle (8-bit) or current set point (10-bit) lsd2_o c lsd2_o p lsd2_ot vds_LS D2 LSD2 duty cycle (8bit) or current read (10 bit) 12 01100 LSD3 duty cycle (8-bit) or current set point (10-bit) lsd3_ oc lsd3_o p lsd3_ot vds_LS D3 LSD3 duty cycle (8bit) or current read (10 bit) 13 01101 LSD4 duty cycle (8-bit) or current set point (10-bit) lsd4_ oc lsd4_o p lsd4_ot vds_LS D4 LSD4 duty cycle (8bit) or current read (10 bit) 14 01110 LSD5 duty cycle 0 0 lsd5_ oc lsd5_o p lsd5_ot vds_LS D5 LSD5 duty cycle 0 0 15 01111 LSD6 duty cycle 0 0 lsd6_ oc lsd6_o p lsd6_ot vds_LS D6 LSD6 duty cycle 0 0 16 10000 LSD7 duty cycle 0 0 lsd7_ oc lsd7_o p lsd7_ot vds_LS D7 LSD7 duty cycle 0 0 17 10001 LSD8 duty cycle 0 0 lsd8_ oc lsd8_o p lsd8_ot vds_LS D8 LSD8 duty cycle 0 0 18 10010 0 0 MR<7:0> X X HD_lkg ERR_CNT AR<7:0> 2 4 1 1 0 0 0 0000000000 H S _ o c H S _ o p H S _ o t v d s _ H S ADIN1<9:0> 2 5 1 1 0 0 1 0000000000XXXX ADIN2<9:0> 2 6 1 1 0 1 0 0000000000XXXX ADIN3<9:0> Notes 22. MSB(B15) of both write and read messages is parity bit, wherea s only B14 of read message is Fmsg, which show previous write message fault. 23. The ‘X’ bit is used for tests manufacturing.

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6.10.3 SPI messa ge description

6.10.3.1 Message #0

Table 25. Write message Table 26. Read message Bit = 1 SB0800 internal clock fault was detected.

6.10.3.2 Message #1

Table 27. Write message

0000 Factor of P-characteristic = 1

1000 Factor of P-characteristic = 1

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6.10.3.3 Message #2

Table 28. Read message Bit = 0 Previous transfer was valid. Bit = 1 Parity bit is not correct. Error detected during previous transfer.

6.10.3.4 Message #3

Table 29. Write message Table 30. Read message Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Er ror detected during previous transfer.

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6.10.3.5 Message #4

Table 31. Write message Table 32. Read message Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Er ror detected during previous transfer.

6.10.3.6 Message #5

Table 33. Write message Table 34. Read message Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Er ror detected during previous transfer.

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6.10.3.7 Message #6

Table 35. Write message Table 36. Read message Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. E rror detected during previous transfer.

6.10.3.8 Message #7

Table 37. Write message First duty cycle from off state to a target value is limited to a fixed duty cycle. For DC > 10%, the measurement is done at Ton/2. For DC > 10%, the measurement is done at Ton/2. DC are forced every two cycles and no measurement is done during 1.56% of DC. For DC > 10%, the measurement is done at Ton/2. no measurement is done during the skipping mode.

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6.10.3.9 Message #8

Table 38. Read message Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Er ror detected during previous transfer. Table 39. Write message Table 40. Read message

Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Er ror detected during previous transfer. lsd1_crer 13 Bit = 0 Normal Bit = 1 Current regulation error detection of LSD1 lsd2_crer 12 Bit = 0 Normal Bit = 1 Current regulation error detection of LSD2 lsd3_crer 11 Bit = 0 Normal Bit = 1 Current regulation error detection of LSD3 lsd4_crer 10 Bit = 0 Normal Bit = 1 Current regulation error detection of LSD4 vcp_vpwr<9:0> 09:00 10-bit ADC of vcp_vpwr

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6.10.3.10 Message #9

Table 41. Write message Table 42. Read message Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Er ror detected during previous transfer.

6.10.3.11 Message #10

Table 43. Write message Table 44. Read message Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Er ror detected during previous transfer.

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6.10.3.12 Message #11

Table 45. Write message Table 46. Read message Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Erro r detected during previous transfer.

6.10.3.13 Message #12

Table 47. Write message Table 48. Read message

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6.10.3.14 Message #13

Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Erro r detected during previous transfer. Table 49. Write message

6.10.3.15 Message #14

Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Er ror detected during previous transfer. Table 50. Write message

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6.10.3.16 Message #15

Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. E rror detected during previous transfer. Table 51. Write message

6.10.3.17 Message #16

Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Erro r detected during previous transfer. Table 52. Write message

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6.10.3.18 Message #17

Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. E rror detected during previous transfer. Table 53. Write message

6.10.3.19 Message #18

Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Erro r detected during previous transfer. Table 54. Write message Table 55. Read message Fmsg 14 Bit = 0 Parity bit is correct. Previous transfer was valid.

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6.10.3.20 Message #19 to 23

6.10.3.21 Message #24

6.10.3.22 Message #25

Table 56. Write message Table 57. Read message Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. E rror detected during previous transfer. Table 58. Write message

6.10.3.23 Message #26

Table 59. Read message Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Er ror detected during previous transfer. Table 60. Write message Table 61. Read message Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. E rror detected during previous transfer.

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7 Typical applications

7.1 Application diagrams

This section presents a typical Industrial applications schematic using SB0800, as shown in Figure 20. Figure 20. Industrial valves and pump control unit simplified diagram

8 Packaging

8.1 Package mechanical dimensions

Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and perform a keyword search for the drawing’s document number. Package Suffix Package outline drawing number 10 x 10, 64-Pin LQFP Exposed Pad, with 0.5 mm pitch, and a 6.1 x 6.1 exposed pad AE 98ASA10763D

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9 Revision history

Revision Date Description of changes 1.0 5/2014 • Initial release 2.0 11/2014 • Increased the operating voltage of the device to 36 V

• Updated the parameters with new operating value 4/2015 • Changed doc classification from Product Preview to Advance Information
• Corrected form and style 5/2015 • Updated document title 3.0 5/2015 • Added tVAM to Table 20
• Added Figure 16 8/2016 • Updated document to NXP form and style

NXP , the NXP logo, Freescale, the Freescale logo, SafeAssure, the SafeAssure logo, and SMARTMOS are trademarks of NXP B.V. All other product or service names are the property of their respective owners. All rights reserved. © 2016 NXP B.V. Information in this document is provided solely to enable system and software implementers to use NXP products. There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. How to Reach Us: Home Page: NXP.com Web Support: http://www.nxp.com/support Document Number: MC34SB0800 Rev. 3.0