Microcontroller

SAMV71Q21RT-DHB-E

Microchip Technology

Radiation-Tolerant 32-bit Arm짰 Cortex짰-M7 MCU 2021

Manufacturer: Microchip Technology

Document: 1879 Pages / 20Mb

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Technical content

Features

Arm Cortex-M7 running at up to 300 MHz
16 Kbytes of ICache and 16 Kbytes of DCache with Error Code Correction (ECC)
Single- and double-precision HW Floating Point Unit (FPU)
Memory Protection Unit (MPU) with 16 zones
DSP Instructions, Thumb ®-2 Instruction Set
Embedded Trace Module (ETM) with instruction trace stream, including Trace Port Interface Unit (TPIU) Memories
2048 Kbytes embedded Flash with unique identifier and user signature for user-defined data
384 Kbytes embedded Multi-port SRAM
Tightly Coupled Memory (TCM) interface with four configurations (disabled, 2 x 32 Kbytes, 2 x 64 Kbytes, 2 x 128 Kbytes)
16 Kbytes ROM with embedded Bootloader routines (UART0, USB) and IAP routines
16-bit Static Memory Controller (SMC) with support for SRAM, PSRAM, LCD module, NOR and NAND Flash with on-the-fly scrambling
16-bit SDRAM Controller (SDRAMC) interfacing up to 256 MB and with on-the-fly scrambling
Flash Write/Erase Cycles (Ground Level only): 10K Cycles
Flash Data Retention: – 12 years with T A = 125°C – 26 years with T A = 110°C – 62 years with T A = 95°C System
Embedded voltage regulator for single-supply operation
Power-on-Reset (POR), Brown-out Detector (BOD) and Dual Watchdog for safe operation
Quartz or ceramic resonator oscillators: 3 to 20 MHz main oscillator with failure detection, 12 MHz or 16 MHz needed for USB operations. Optional low-power 32.768 kHz for RTC or device clock
RTC with Gregorian Calendar mode, waveform generation in low-power modes
RTC counter calibration circuitry compensates for 32.768 kHz crystal frequency variations
32-bit low-power Real-time Timer (RTT)
High-precision Main RC oscillator with 12 MHz default frequency for device start-up. In-application trimming access for frequency adjustment. 8/12 MHz are factory-trimmed. © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 1

32.768 kHz crystal oscillator or Slow RC oscillator as source of Low-Power mode device clock (SLCK)
One 500 MHz PLL for system clock
Temperature Sensor
One dual-port 24-channel central DMA Controller (XDMAC) Low-Power Features
Low-power Sleep, Wait and Backup modes, with typical power consumption down to 1.1 μA in Backup mode with RTC, RTT and wake-up logic enabled
Ultra low-power RTC and RTT
1 Kbyte of backup RAM (BRAM) with dedicated regulator Peripherals
One Ethernet MAC (GMAC) 10/100 Mbps in MII mode and RMII mode with dedicated DMA. IEEE ®1588 PTP frames and 802.3az Energy-efficiency support. Ethernet AVB support with IEEE802.1AS Timestamping and IEEE802.1Qav credit-based traffic-shaping hardware support.
12-bit ITU-R BT. 601/656 Image Sensor Interface (ISI)
Two master Controller Area Networks (MCAN) with Flexible Data Rate (CAN-FD) with SRAM-based mailboxes, time- and event-triggered transmission
MediaLB ® device with 3-wire mode, up to 1024 x Fs speed, supporting MOST25 and MOST50 networks
Three USARTs. USART0/1/2 support LIN mode, ISO7816, IrDA ®, RS-485, SPI, Manchester and Modem modes; USART1 supports LON mode.
Five 2-wire UARTs with SleepWalking ™ support
Three Two-Wire Interfaces (TWIHS) (I 2C-compatible) with SleepWalking support
Quad I/O Serial Peripheral Interface (QSPI) interfacing up to 256 MB Flash and with eXecute-In-Place and on-the-fly scrambling
Two Serial Peripheral Interfaces (SPI)
One Serial Synchronous Controller (SSC) with I2S and TDM support
Two Inter-IC Sound Controllers (I2SC)
One High-speed Multimedia Card Interface (HSMCI) (SDIO/SD Card/e.MMC)
Four Three-Channel 16-bit Timer/Counters (TC) with Capture, Waveform, Compare and PWM modes, constant on time. Quadrature decoder logic and 2-bit Gray Up/Down Counter for stepper motor
Two 4-channel 16-bit PWMs with complementary outputs, Dead Time Generator and eight fault inputs per PWM for motor control, two external triggers to manage power factor correction (PFC), DC-DC and lighting control.
Two Analog Front-End Controllers (AFEC), each supporting up to 12 channels with differential input mode and programmable gain stage, allowing dual sample-and-hold at up to 1.7 Msps. Offset and gain error correction feature.
One 2-channel 12-bit 1 Msps-per-channel Digital-to-Analog Converter (DAC) with Differential and Over Sampling modes
One Analog Comparator Controller (ACC) with flexible input selection, selectable input hysteresis Cryptography
True Random Number Generator (TRNG)
AES: 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB-197 Specifications
Integrity Check Monitor (ICM). Supports Secure Hash Algorithm SHA1, SHA224 and SHA256. I/O
114 I/O Lines with external interrupt capability (edge- or level-sensitivity), debouncing, glitch filtering and On-die Series Resistor Termination
Five Parallel Input/Output Controllers (PIO) Operating Range
Temperature: -55°C to +125°C
Single Supply Voltage: 3.0V to 3.6V
Dual Supply Voltage – VDDIO: 3.0V to 3.6V SAMV71Q21RT © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 2

– VDDCORE: 1.2V to 1.32V Packages

CQFP144, 144-lead CQFP, 22 x 22 mm, pitch 0.5 mm
LQFP144, 144-lead LQFP, 20 x 20 mm, pitch 0.5 mm Radiation Performance
No Single Event Latch-up Below an LET Threshold of 60 MeV.cm 2/mg @125°C
Total Ionizing Dose of 30 krad(Si) RHA ESD
HBM 3000V
CDM 750V Mass
CQFP144: 6187 mg
LQFP144: 1365 mg SAMV71Q21RT © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 3

Configuration Summary Table 1-1. Configuration Summary Feature SAM V71Q21RT Flash (Kbytes) 2048 Multi-port SRAM (Kbytes) 384 Cache(I/D) (Kbytes) LQFP144 Number of PIOs 114 External Bus Interface 16-bit data, 4 chip selects, 24-bit address SDRAM Interface Yes Media LB Interface Yes Central DMA 24 12-bit ADC 24 ch. (see Note 1) 12-bit DAC 2 ch. Timer Counter Channels 12 Timer Counter Channels I/O 36 USART/UART 3/5(see Note 2) QSPI Yes SPI0 Yes SPI1 Yes USART SPI 3 TWI 3 HSMCI 1 port 4 bits CAN 2 ports GMAC MII, RMII ISI 12-bit SSC Yes I2SC 2 SAMV71Q21RT Configuration Summary © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 14

Embedded Trace Macrocell (ETM) Yes Notes: 1. One channel is reserved for internal temperature sensor. 2. LON support on USART1 only. SAMV71Q21RT Configuration Summary © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 15

Ordering Information Ordering Code Speed (MHz) Power Supply Package Flow SAMV71Q21RT-DHB-E 300 3.0–3.6V CQFP144 Engineering Samples SAMV71Q21RT-DHB-HC Hirel Ceramic SAMV71Q21RT-DHB-MQ QML-Q Equivalent SAMV71Q21RT-DHB-SV QML-V Equivalent SAMV71Q21RT-H8X-HP LQFP144 Hirel Plastic SAMV71Q21RT-H8X-SN QML-N Equivalent SAMV71Q21RT

Ordering Information

Block Diagram Figure 3-1. SAMV71Q21RT Block Diagram 12-layer Bus Matrix fMAX150 MHz PCK0..2 XIN32 XOUT32 ERASE VDDCORE VDDIOVDDOUT Voltage Regulator TST WKUP0..13 VDDIO XIN XOUT VDDPLL RTCOUT0 RTCOUT1 S MM M M M S SS S S M M M M M S System Controller S In-Circuit Emulator MPU Cortex-M7 Processor fMAX300 MHz NVIC FPU TPIU ETM

16 Kbytes ICache + ECC 16 Kbytes DCache + ECC

2048 Kbytes

URXD0..4UTXD0..4 CANRX0..1CANTX0..1 ICM/SHA PIODCCLKPIODCEN1..2PIODC0..7 TFTKTDRD RK RF MCDA0..3MCCDAMCCK SPIx_NPCS0..3 SPIx_MISOSPIx_MOSISPIx_SPCK PWMCx_PWMEXTRG0..1 AFEx_ADTRGAFEx_AD0..11 MLBSIGMLBCLKMLBDAT 2 x MCAN DMA DMA DMA Temp Sensor XDMAXDMAXDMAXDMAXDMAXDMAXDMAXDMAXDMA XDMA FIFO XDMA TRNGAES DMA VREFNVREFP XDMA M TCK/SWCLKTDI TDO/TRACESWOJTAGSEL Serial Wire Debug/JTAG Boundary Scan TRACECLKTRACED0..3 TMS/SWDIO Multi-port SRAM ITCM DTCM TCM SRAM System RAM Static Memory Controller (SMC) SDRAM Controller (SDRAMC) NAND Flash Logic 2 x I2SC I2SCx_DII2SCx_MCKI2SCx_CKI2SCx_WS XDMA I2SCx_DO PMC RSTC SM POR RTTRTC WDT UPLL PLLA Backup RAM

1 Kbyte

(GPBR) Backup RSWDT

384 Kbytes

Signal Description The following table provides details on signal names classified by peripheral. Table 4-1. Signal Description List Signal Name Function Type Active Level Voltage Reference Comments Power Supplies VDDIO Peripherals I/O Lines Power Supply Power – – – VDDIN Voltage Regulator Input, AFE, DAC and Analog Comparator Power Supply (see Note) Power – – – VDDOUT Voltage Regulator Output Power – – – VDDPLL PLLA Power Supply Power – – – VDDPLLUSB USB PLL and Oscillator Power Supply Power – – – VDDCORE Powers the core, the embedded memories and the peripherals Power – – – GND, GNDPLL, GNDPLLUSB, GNDANA, GNDUTMI Ground Ground – – – VDDUTMII USB Transceiver Power Supply Power – – – VDDUTMIC USB Core Power Supply Power – – – GNDUTMI USB Ground Ground – – – Clocks, Oscillators and PLLs XIN Main Oscillator Input Input – VDDIO – XOUT Main Oscillator Output Output – – XIN32 Slow Clock Oscillator Input Input – – XOUT32 Slow Clock Oscillator Output Output – – PCK0–PCK2 Programmable Clock Output Output – – Real Time Clock RTCOUT0 Programmable RTC Waveform Output Output – VDDIO – RTCOUT1 Programmable RTC Waveform Output Output – – Serial Wire Debug/JTAG Boundary Scan SAMV71Q21RT Signal Description © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 18

Signal Name Function Type Active Level Voltage Reference Comments SWCLK/TCK Serial Wire Clock / Test Clock (Boundary scan mode only) Input – VDDIO – TDI Test Data In (Boundary scan mode only) Input – – TDO/TRACESWO Test Data Out (Boundary scan mode only) Output – – SWDIO/TMS Serial Wire Input/Output / Test Mode Select (Boundary scan mode only) I/O / Input – – JTAGSEL JTAG Selection Input High – Trace Debug Port TRACECLK Trace Clock Output – VDDIO PCK3 is used for ETM TRACED0– TRACED3 Trace Data Output – – Flash Memory ERASE Flash and NVM Configuration Bits Erase Command Input High VDDIO – Reset/Test NRST Synchronous Microcontroller Reset I/O Low VDDIO – TST Test Select Input – – Universal Asynchronous Receiver Transceiver - UART(x=[0:4]) URXDx UART Receive Data Input – – PCK4 can be used to generate the baud rateUTXDx UART Transmit Data Output – – PIO Controller - PIOA - PIOB - PIOC - PIOD - PIOE PA0–PA31 Parallel IO Controller A I/O – VDDIO – PB0–PB9, PB12– PB13 Parallel IO Controller B I/O – – PC0– PC31 Parallel IO Controller C I/O – – PD0–PD31 Parallel IO Controller D I/O – – – PE0–PE5 Parallel IO Controller E I/O – – – PIO Controller - Parallel Capture Mode SAMV71Q21RT Signal Description © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 19

Signal Name Function Type Active Level Voltage Reference Comments PIODC0–PIODC7 Parallel Capture Mode Data Input – VDDIO – PIODCCLK Parallel Capture Mode Clock Input – – PIODCEN1– PIODCEN2 Parallel Capture Mode Enable Input – – External Bus Interface D[15:0] Data Bus I/O – – – A[23:0] Address Bus Output – – – NWAIT External Wait Signal Input Low – – Static Memory Controller - SMC NCS0–NCS3 Chip Select Lines Output Low – – NRD Read Signal Output Low – – NWE Write Enable Output Low – – NWR0–NWR1 Write Signal Output Low – – NBS0–NBS1 Byte Mask Signal Output Low – Used also for SDRAMC NAND Flash Logic NANDOE NAND Flash Output Enable Output Low – – NANDWE NAND Flash Write Enable Output Low – – SDR-SDRAM Controller Logic SDCK SDRAM Clock Output – – – SDCKE SDRAM Clock Enable Output – – – SDCS SDRAM Controller Chip Select Output – – – BA0–BA1 Bank Select Output – – – SDWE SDRAM Write Enable Output – – – RAS–CAS Row and Column Signal Output – – – SDA10 SDRAM Address 10 Line Output – – – High Speed Multimedia Card Interface - HSMCI MCCK Multimedia Card Clock O – – – MCCDA Multimedia Card Slot A Command I/O – – – MCDA0–MCDA3 Multimedia Card Slot A Data I/O – – – Universal Synchronous Asynchronous Receiver Transmitter USART(x=[0:2]) SAMV71Q21RT Signal Description © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 20

Signal Name Function Type Active Level Voltage Reference Comments SCKx USARTx Serial Clock I/O – – PCK4 can be used to generate the baud rateTXDx USARTx Transmit Data I/O – – RXDx USARTx Receive Data Input – – RTSx USARTx Request To Send Output – – CTSx USARTx Clear To Send Input – – DTRx USARTx Data Terminal Ready Output – – DSRx USARTx Data Set Ready Input – – DCDx USARTx Data Carrier Detect Input – – RIx USARTx Ring Indicator Input – – LONCOL1 LON Collision Detection Input – – Synchronous Serial Controller - SSC TD SSC Transmit Data Output – – – RD SSC Receive Data Input – – – TK SSC Transmit Clock I/O – – – RK SSC Receive Clock I/O – – – TF SSC Transmit Frame Sync I/O – – – RF SSC Receive Frame Sync I/O – – – Inter-IC Sound Controller - I2SC[1..0] I2SCx_MCK Master Clock Output – VDDIO GCLK[PID] can be used to generate the baud rateI2SCx_CK Serial Clock I/O – VDDIO I2SCx_WS I2S Word Select I/O – VDDIO I2SCx_DI Serial Data Input Input – VDDIO I2SCx_DO Serial Data Output Output – VDDIO Image Sensor Interface - ISI ISI_D0–ISI_D11 Image Sensor Data Input – – – ISI_MCK Image sensor Reference clock. No dedicated signal, PCK1 can be used. Output – – – ISI_HSYNC Image Sensor Horizontal Synchro Input – – – ISI_VSYNC Image Sensor Vertical Synchro Input – – – ISI_PCK Image Sensor Data clock Input – – – SAMV71Q21RT Signal Description © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 21

Signal Name Function Type Active Level Voltage Reference Comments Timer Counter - TC(x=[0:11]) TCLKx TC Channel x External Clock Input Input – – PCK6 can be used as an input clock PCK7 can be used as an input clock for TC0 only TIOAx TC Channel x I/O Line A I/O – – TIOBx TC Channel x I/O Line B I/O – – Pulse Width Modulation Controller- PWMC(x=[0..1]) PWMCx_PWMH0– PWMCx_PWMH3 Waveform Output High for Channel 0–3 Output – – – PWMCx_PWML0– PWMCx_PWML3 Waveform Output Low for Channel 0–3 Output – – Only output in complementary mode when dead time insertion is enabled. PWMCx_PWMFI0– PWMCx_PWMFI2 Fault Input Input – – – PWMCx_PWMEXT RG0– PWMCx_PWMEXT RG1 External Trigger Input Input – – – Serial Peripheral Interface - SPI(x=[0..1]) SPIx_MISO Master In Slave Out I/O – – – SPIx_MOSI Master Out Slave In I/O – – – SPIx_SPCK SPI Serial Clock I/O – – – SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low – – SPIx_NPCS1– SPIx_NPCS3 SPI Peripheral Chip Select Output Low – – Quad IO SPI - QSPI QSCK QSPI Serial Clock Output – – – QCS QSPI Chip Select Output – – – QIO0–QIO3 QSPI I/O QIO0 is QMOSI Master Out Slave In QIO1 is QMISO Master In Slave Out I/O – – – Two-Wire Interface - TWIHS (x=0..2) TWDx TWIx Two-wire Serial Data I/O – – – TWCKx TWIx Two-wire Serial Clock I/O – – – SAMV71Q21RT Signal Description © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 22

Signal Name Function Type Active Level Voltage Reference Comments Analog VREFP ADC, DAC and Analog Comparator Positive Reference Analog – – – VREFN ADC, DAC and Analog Comparator Negative Reference Must be connected to GND or GNDANA. Analog – – – 12-bit Analog Front End - (x=[0..1]) AFEx_AD0– AFEx_AD11 Analog Inputs Analog, Digital – – – AFEx_ADTRG ADC Trigger Input – VDDIO – 12-bit Digital-to-Analog Converter - DAC DAC0–DAC1 Analog Output Analog, Digital – – – DATRG DAC Trigger Input – VDDIO – Fast Flash Programming Interface - FFPI PGMEN0–PGMEN1 Programming Enabling Input – VDDIO – PGMM0–PGMM3 Programming Mode Input – VDDIO – PGMD0–PGMD15 Programming Data I/O – – PGMRDY Programming Ready Output High – PGMNVALID Data Direction Output Low – PGMNOE Programming Read Input Low – PGMNCMD Programming Command Input Low – USB High Speed - USBHS HSDM USB High Speed Data - Analog, Digital – VDDUTMII – HSDP USB High Speed Data + – – VBG Bias Voltage Reference for USB Analog – – – Ethernet MAC 10/100 - GMAC GREFCK Reference Clock Input – – RMII only GTXCK Transmit Clock Input – – MII only GRXCK Receive Clock Input – – MII only GTXEN Transmit Enable Output – – – GTX0 - GTX3 Transmit Data Output – – GTX0–GTX1 only in RMII GTXER Transmit Coding Error Output – – MII only SAMV71Q21RT Signal Description © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 23

Signal Name Function Type Active Level Voltage Reference Comments GRXDV Receive Data Valid Input – – MII only GRX0 - GRX3 Receive Data Input – – GRX0–GRX1 only in RMII GRXER Receive Error Input – – – GCRS Carrier Sense Input – – MII only GCOL Collision Detected Input – – MII only GMDC Management Data Clock Output – – – GMDIO Management Data Input/ Output I/O – – – GTSUCOMP TSU timer comparison valid Output – – – Controller Area Network - MCAN (x=[0:1]) CANRXx CAN Receive Input – – CANRX1 is available on PD28 for 100-pin only CANRX1 is available on PC12 for 144-pin only CANTXx CAN Transmit Output – – PCK5 can be used for CAN clock PCK6 and PCK7 can be used for CAN timestamping MediaLB - MLB MLBCLK MLB Clock input – – – MLBSIG MLB Signal I/O – – – MLBDAT MLB Data I/O – – – Note: Refer to the “Active Mode” section in the Power Considerations chapter for restrictions on the voltage range of analog cells. SAMV71Q21RT Signal Description © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 24

Space Quality Grade The hermetic SAMV71Q21RT is manufactured in compliance with MIL class Q or class V requirements (screening testing, qualification testing, and TCI/SCI-specifications) as well as in Hirel Ceramic. The plastic SAMV71Q21RT is qualified in compliance with the AEC-Q100 automotive requirements, with specific additional tests necessary for space applications. Screening and qualification flows are described in Aerospace & Defense AEQA0242 specification, available on Microchip web site. SAMV71Q21RT Space Quality Grade © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 25

Package and Pinout In the tables that follow, the column “Reset State” indicates the reset state of the line with mnemonics. Indicates whether the PIO Line resets in I/O mode or in peripheral mode. If “PIO” is mentioned, the PIO line is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name is mentioned in the “Reset State” column, the PIO line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Indicates whether the signal is input or output state. Indicates whether pullup, pulldown or nothing is enabled.

“ST” Indicates if Schmitt Trigger is enabled.

6.1 CQFP Package Outline

6.2 LQFP Package Outline

Figure 6-2. Orientation of the 144-pin LQFP Package 144

6.3 Pinout

Table 6-1. CQFP/LQFP Package Pinout Pin No. Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C PIO Peripheral D Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST

102 VDDIO GPIO_AD PA0 I/O WKUP0(1) I PWMC0_ PWMH0 O TIOA0 I/O A17/BA1 O I2SC0_MCK O PIO, I, PU, ST

99 VDDIO GPIO_AD PA1 I/O WKUP1(1) I PWMC0_ PWML0 O TIOB0 I/O A18 O I2SC0_CK I/O PIO, I, PU, ST

93 VDDIO GPIO PA2 I/O WKUP2(1) I PWMC0_ PWMH1 O – – DATRG I – – PIO, I, PU, ST

91 VDDIO GPIO_AD PA3 I/O PIODC0(2) I TWD0 I/O LONCOL1 I PCK2 O – – PIO, I, PU, ST

77 VDDIO GPIO PA4 I/O WKUP3/P IODC1(3) I TWCK0 O TCLK0 I UTXD1 O – – PIO, I, PU, ST

73 VDDIO GPIO_AD PA5 I/O WKUP4/P IODC2(3) I PWMC1_ PWML3 O ISI_D4 I URXD1 I – – PIO, I, PU, ST

114 VDDIO GPIO_AD PA6 I/O – – – – PCK0 O UTXD1 O – – PIO, I, PU, ST

35 VDDIO CLOCK PA7 I/O XIN32(4) I – – PWMC0_ PWMH3 O – – – – PIO, HiZ

36 VDDIO CLOCK PA8 I/O XIN32(4) O PWMC1_ PWMH3 O AFE0_ADTRG I – – – – PIO, HiZ

75 VDDIO GPIO_AD PA9 I/O WKUP6/P IODC3(3) I URXD0 I ISI_D3 I PWMC0_ PWMFI0 I – – PIO, I, PU, ST

66 VDDIO GPIO_AD PA10 I/O PIODC4(2) I UTXD0 O PWMC0_ PWMEXTRG0 I RD I – – PIO, I, PU, ST

64 VDDIO GPIO_AD PA11 I/O WKUP7/P IODC5(3) I QCS O PWMC0_ PWMH0 O PWMC1_ PWML0 O – – PIO, I, PU, ST

68 VDDIO GPIO_AD PA12 I/O PIODC6(2) I QIO1 I/O PWMC0_ PWMH1 O PWMC1_ PWMH0 O – – PIO, I, PU, ST

42 VDDIO GPIO_AD PA13 I/O PIODC7(2) I QIO0 I/O PWMC0_ PWMH2 O PWMC1_ PWML1 O – – PIO, I, PU, ST

51 VDDIO GPIO_CLK PA14 I/O WKUP8/P IODCEN1(3) I QSCK O PWMC0_ PWMH3 O PWMC1_ PWMH1 O – – PIO, I, PU, ST

49 VDDIO GPIO_AD PA15 I/O – – D14 I/O TIOA1 I/O PWMC0_ PWML3 O I2SC0_WS I/O PIO, I, PU, ST

45 VDDIO GPIO_AD PA16 I/O – – D15 I/O TIOB1 I/O PWMC0_ PWML2 O I2SC0_DI I PIO, I, PU, ST

25 VDDIO GPIO_AD PA17 I/O AFE0_AD 6(5) I QIO2 I/O PCK1 O PWMC0_ PWMH3 O – – PIO, I, PU, ST

24 VDDIO GPIO_AD PA18 I/O AFE0_AD 7(5) I PWMC1_ PWMEXTRG1 I PCK2 O A14 O – – PIO, I, PU, ST

23 VDDIO GPIO_AD PA19 I/O AFE0_AD 8/WKUP9(6) I – – PWMC0_ PWML0 O A15 O I2SC1_MCK O PIO, I, PU, ST

22 VDDIO GPIO_AD PA20 I/O AFE0_AD 9/WKUP10(6) I – – PWMC0_ PWML1 O A16/BA0 O I2SC1_CK I/O PIO, I, PU, ST

32 VDDIO GPIO_AD PA21 I/O AFE0_AD 1/ PIODCEN 2(8) I RXD1 I PCK1 O PWMC1_ PWMFI0 I – – PIO, I, PU, ST

37 VDDIO GPIO_AD PA22 I/O PIODCCL K(2) I RK I/O PWMC0_ PWMEXTRG1 I NCS2 O – – PIO, I, PU, ST

46 VDDIO GPIO_AD PA23 I/O – – SCK1 I/O PWMC0_ PWMH0 O A19 O PWMC1_ PWML2 O PIO, I, PU, ST

56 VDDIO GPIO_AD PA24 I/O – – RTS1 O PWMC0_ PWMH1 O A20 O ISI_PCK I PIO, I, PU, ST

59 VDDIO GPIO_AD PA25 I/O – – CTS1 I PWMC0_ PWMH2 O A23 O MCCK O PIO, I, PU, ST

62 VDDIO GPIO PA26 I/O – – DCD1 I TIOA2 O MCDA2 I/O PWMC1_ PWMFI1 I PIO, I, PU, ST

70 VDDIO GPIO_AD PA27 I/O – – DTR1 O TIOB2 I/O MCDA3 I/O ISI_D7 I PIO, I, PU, ST

112 VDDIO GPIO PA28 I/O – – DSR1 I TCLK1 I MCCDA I/O PWMC1_ PWMFI2 I PIO, I, PU, ST

129 VDDIO GPIO PA29 I/O – – RI1 I TCLK2 I – – – – PIO, I, PU, ST

116 VDDIO GPIO PA30 I/O WKUP11(1) I PWMC0_ PWML2 O PWMC1_ PWMEXTRG0 I MCDA0 I/O I2SC0_DO O PIO, I, PU, ST

118 VDDIO GPIO_AD PA31 I/O – – SPI0_NPCS1 I/O PCK2 O MCDA1 I/O PWMC1_ PWMH2 O PIO, I, PU, ST

21 VDDIO GPIO PB0 I/O AFE0_AD10/ RTCOUT0(7) I PWMC0_ PWMH0 O – – RXD0 I TF I/O PIO, I, PU, ST

20 VDDIO GPIO PB1 I/O AFE1_AD 0/ RTCOUT 1(7) I PWMC0_ PWMH1 O GTSUCOMP O TXD0 I/O TK I/O PIO, I, PU, ST

26 VDDIO GPIO PB2 I/O AFE0_AD5(5) I CANTX0 O – – CTS0 I SPI0_NPCS0 I/O PIO, I, PU, ST

31 VDDIO GPIO_AD PB3 I/O AFE0_AD2/WKUP12(6) I CANRX0 I PCK2 O RTS0 O ISI_D2 I PIO, I, PU, ST

105 VDDIO GPIO_MLB PB4 I/O TDI(9) I TWD1 I/O PWMC0_ PWMH2 O MLBCLK I TXD1 I/O PIO, I, PD, ST

109 VDDIO GPIO_MLB PB5 I/O TDO/TRACESWO/ WKUP13(9) O TWCK1 O PWMC0_ PWML0 O MLBDAT I/O TD O O, PU

79 VDDIO GPIO PB6 I/O SWDIO/TMS(9) I – – – – – – – – PIO, I, ST

Pin No. Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C PIO Peripheral D Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST

89 VDDIO GPIO PB7 I/O SWCLK/TCK(9) I – – – – – – – – PIO, I, ST

141 VDDIO CLOCK PB8 I/O XOUT(10) O – – – – – – – – PIO, HiZ

142 VDDIO CLOCK PB9 I/O XIN(10) I – – – – – – – – PIO, HiZ

87 VDDIO GPIO PB12 I/O ERASE(9) I PWMC0_ PWML1 O GTSUCOMP O – – PCK0 O PIO, I, PD, ST

144 VDDIO GPIO_AD PB13 I/O DAC0(11) O PWMC0_ PWML2 O PCK0 O SCK0 I/O – – PIO, I, PU, ST

11 VDDIO GPIO_AD PC0 I/O AFE1_AD9(5) I D0 I/O PWMC0_ PWML0 O – – – – PIO, I, PU, ST

38 VDDIO GPIO_AD PC1 I/O – – D1 I/O PWMC0_ PWML1 O – – – – PIO, I, PU, ST

39 VDDIO GPIO_AD PC2 I/O – – D2 I/O PWMC0_ PWML2 O – – – – PIO, I, PU, ST

40 VDDIO GPIO_AD PC3 I/O – – D3 I/O PWMC0_ PWML3 O – – – – PIO, I, PU, ST

41 VDDIO GPIO_AD PC4 I/O – – D4 I/O – – – – – – PIO, I, PU, ST

58 VDDIO GPIO_AD PC5 I/O – – D5 I/O TIOA6 I/O – – – – PIO, I, PU, ST

54 VDDIO GPIO_AD PC6 I/O – – D6 I/O TIOB6 I/O – – – – PIO, I, PU, ST

48 VDDIO GPIO_AD PC7 I/O – – D7 I/O TCLK6 I – – – – PIO, I, PU, ST

82 VDDIO GPIO_AD PC8 I/O – – NWR0/NWE O TIOA7 I/O – – – – PIO, I, PU, ST

86 VDDIO GPIO_AD PC9 I/O – – NANDOE O TIOB7 I/O – – – – PIO, I, PU, ST

90 VDDIO GPIO_AD PC10 I/O – – NANDWE O TCLK7 I – – – – PIO, I, PU, ST

94 VDDIO GPIO_AD PC11 I/O – – NRD O TIOA8 I/O – – – – PIO, I, PU, ST

17 VDDIO GPIO_AD PC12 I/O AFE1_AD3(5) I NCS3 O TIOB8 I/O CANRX1 I – – PIO, I, PU, ST

19 VDDIO GPIO_AD PC13 I/O AFE1_AD1(5) I NWAIT I PWMC0_ PWMH3 O SDA10 O – – PIO, I, PU, ST

97 VDDIO GPIO_AD PC14 I/O – – NCS0 O TCLK8 I CANTX1 O – – PIO, I, PU, ST

18 VDDIO GPIO_AD PC15 I/O AFE1_AD2(5) I NCS1/SDCS O PWMC0_ PWML3 O – – – – PIO, I, PU, ST

100 VDDIO GPIO_AD PC16 I/O – – A21/NANDALE O – – – – – – PIO, I, PU, ST

103 VDDIO GPIO_AD PC17 I/O – – A22/NANDCLE O – – – – – – PIO, I, PU, ST

111 VDDIO GPIO_AD PC18 I/O – – A0/NBS0 O PWMC0_ PWML1 O – – – – PIO, I, PU, ST

117 VDDIO GPIO_AD PC19 I/O – – A1 O PWMC0_ PWMH2 O – – – – PIO, I, PU, ST

120 VDDIO GPIO_AD PC20 I/O – – A2 O PWMC0_ PWML2 O – – – – PIO, I, PU, ST

122 VDDIO GPIO_AD PC21 I/O – – A3 O PWMC0_ PWMH3 O – – – – PIO, I, PU, ST

124 VDDIO GPIO_AD PC22 I/O – – A4 O PWMC0_ PWML3 O – – – – PIO, I, PU, ST

127 VDDIO GPIO_AD PC23 I/O – – A5 O TIOA3 I/O – – – – PIO, I, PU, ST

130 VDDIO GPIO_AD PC24 I/O – – A6 O TIOB3 I/O SPI1_SPCK O – – PIO, I, PU, ST

133 VDDIO GPIO_AD PC25 I/O – – A7 O TCLK3 I SPI1_NPCS0 I/O – – PIO, I, PU, ST

13 VDDIO GPIO_AD PC26 I/O AFE1_AD 7(5) I A8 O TIOA4 I/O SPI1_MISO I – – PIO, I, PU, ST

12 VDDIO GPIO_AD PC27 I/O AFE1_AD8(5) I A9 O TIOB4 I/O SPI1_MOSI O – – PIO, I, PU, ST

76 VDDIO GPIO_AD PC28 I/O – – A10 O TCLK4 I SPI1_NPCS1 I/O – – PIO, I, PU, ST

16 VDDIO GPIO_AD PC29 I/O AFE1_AD4(5) I A11 O TIOA5 I/O SPI1_NPCS2 O – – PIO, I, PU, ST

15 VDDIO GPIO_AD PC30 I/O AFE1_AD5(5) I A12 O TIOB5 I/O SPI1_NPCS3 O – – PIO, I, PU, ST

14 VDDIO GPIO_AD PC31 I/O AFE1_AD6(5) I A13 O TCLK5 I – – – – PIO, I, PU, ST

1 VDDIO GPIO_AD PD0 I/O DAC1(11) I GTXCK I PWMC1_ PWML0 O SPI1_NPCS1 I/O DCD0 I PIO, I, PU, ST

132 VDDIO GPIO PD1 I/O – – GTXEN O PWMC1_ PWMH0 O SPI1_NPCS2 I/O DTR0 O PIO, I, PU, ST

131 VDDIO GPIO PD2 I/O – – GTX0 O PWMC1_ PWML1 O SPI1_NPCS3 I/O DSR0 I PIO, I, PU, ST

128 VDDIO GPIO PD3 I/O – – GTX1 O PWMC1_ PWMH1 O UTXD4 O RI0 I PIO, I, PU, ST

126 VDDIO GPIO_CLK PD4 I/O – – GRXDV I PWMC1_ PWML2 O TRACED0 O DCD2 I PIO, I, PU, ST

125 VDDIO GPIO_CLK PD5 I/O – – GRX0 I PWMC1_ PWMH2 O TRACED1 O DTR2 O PIO, I, PU, ST

121 VDDIO GPIO_CLK PD6 I/O – – GRX1 I PWMC1_ PWML3 O TRACED2 O DSR2 I PIO, I, PU, ST

119 VDDIO GPIO_CLK PD7 I/O – – GRXER I PWMC1_ PWMH3 O TRACED3 O RI2 I PIO, I, PU, ST

113 VDDIO GPIO_CLK PD8 I/O – – GMDC O PWMC0_ PWMFI1 I – – TRACECLK O PIO, I, PU, ST

110 VDDIO GPIO_CLK PD9 I/O – – GMDIO I/O PWMC0_ PWMFI2 I AFE1_ADTRG I – – PIO, I, PU, ST

101 VDDIO GPIO_MLB PD10 I/O – – GCRS I PWMC0_ PWML0 O TD O MLBSIG I/O PIO, I, PD, ST

98 VDDIO GPIO_AD PD11 I/O – – GRX2 I PWMC0_ PWMH0 O GTSUCOMP O ISI_D5 I PIO, I, PU, ST

92 VDDIO GPIO_AD PD12 I/O – – GRX3 I CANTX1 O SPI0_NPCS2 O ISI_D6 I PIO, I, PU, ST

88 VDDIO GPIO_CLK PD13 I/O – – GCOL I – – SDA10 O – – PIO, I, PU, ST

84 VDDIO GPIO_AD PD14 I/O – – GRXCK I – – SDCKE O – – PIO, I, PU, ST

106 VDDIO GPIO_AD PD15 I/O – – GTX2 O RXD2 I NWR1/NBS1 O – – PIO, I, PU, ST

78 VDDIO GPIO_AD PD16 I/O – – GTX3 O TXD2 I/O RAS O – – PIO, I, PU, ST

74 VDDIO GPIO_AD PD17 I/O – – GTXER O SCK2 I/O CAS O – – PIO, I, PU, ST

69 VDDIO GPIO_AD PD18 I/O – – NCS1/SDCS O RTS2 O URXD4 I – – PIO, I, PU, ST

67 VDDIO GPIO_AD PD19 I/O – – NCS3 O CTS2 I UTXD4 O – – PIO, I, PU, ST

65 VDDIO GPIO PD20 I/O – – PWMC0_ PWMH0 O SPI0_MIS O I/O GTSUCOMP O – – PIO, I, PU, ST

63 VDDIO GPIO_AD PD21 I/O – – PWMC0_ PWMH1 O SPI0_MOSI I/O TIOA11 I/O ISI_D1 I PIO, I, PU, ST

60 VDDIO GPIO_AD PD22 I/O – – PWMC0_ PWMH2 O SPI0_SPCK O TIOB11 I/O ISI_D0 I PIO, I, PU, ST

57 VDDIO GPIO_CLK PD23 I/O – – PWMC0_ PWMH3 O – – SDCK O – – PIO, I, PU, ST

55 VDDIO GPIO_AD PD24 I/O – – PWMC0_ PWML0 O RF I/O TCLK11 I ISI_HSYNC I PIO, I, PU, ST

52 VDDIO GPIO_AD PD25 I/O – – PWMC0_ PWML1 O SPI0_NPCS1 I/O URXD2 I ISI_VSYNC I PIO, I, PU, ST

53 VDDIO GPIO PD26 I/O – – PWMC0_ PWML2 O TD O UTXD2 O UTXD1 O PIO, I, PU, ST

47 VDDIO GPIO_AD PD27 I/O – – PWMC0_ PWML3 O SPI0_NPCS3 O TWD2 O ISI_D8 I PIO, I, PU, ST

71 VDDIO GPIO_AD PD28 I/O WKUP5(1) I URXD3 I – – TWCK2 O ISI_D9 I PIO, I, PU, ST

108 VDDIO GPIO_AD PD29 I/O – – – – – – SDWE O – – PIO, I, PU, ST

34 VDDIO GPIO_AD PD30 I/O AFE0_AD0(5) I UTXD3 0 – – – – ISI_D10 I PIO, I, PU, ST

2 VDDIO GPIO_AD PD31 I/O – – QIO3 I/O UTXD3 O PCK2 O ISI_D11 I PIO, I, PU, ST

4 VDDIO GPIO_AD PE0 I/O AFE1_AD 11(5) I D8 I/O TIOA9 I/O I2SC1_WS I/O – – PIO, I, PU, ST

6 VDDIO GPIO_AD PE1 I/O – – D9 I/O TIOB9 I/O I2SC1_DO O – – PIO, I, PU, ST

7 VDDIO GPIO_AD PE2 I/O – – D10 I/O TCLK9 I I2SC1_DI I – – PIO, I, PU, ST

10 VDDIO GPIO_AD PE3 I/O AFE1_AD10(5) I D11 I/O TIOA10 I/O – – – – PIO, I, PU, ST

27 VDDIO GPIO_AD PE4 I/O AFE0_AD4(5) I D12 I/O TIOB10 I/O – – – – PIO, I, PU, ST

28 VDDIO GPIO_AD PE5 I/O AFE0_AD3(5) I D13 I/O TCLK10 I/O – – – – PIO, I, PU, ST

30,43, 72, 80,

104 VDDIO TEST JTAGSEL I – – – – – – – – – – I, PD

29,33, 50, 81, 107 44,61, 95, 115, 135,1 38 Notes: 1. WKUPx can be used if the PIO Controller defines the I/O line as “input”. 2. To select this extra function, refer to the 32.5.14 Parallel Capture Mode section in the Parallel Input/Output Controller (PIO) chapter. 3. PIODCEN1/PIODCx has priority over WKUPx. Refer to the 32.5.14 Parallel Capture Mode section in the PIO chapter. 4. Refer to the 23.4.2 Slow Clock Generator section in the Supply Controller (SUPC) chapter. This selection is independent of the PIO line configuration. PIO lines must be configured according to required settings (PU or PD). the EBI chapter. WKUPx can be used if the PIO controller defines the I/O line as “input”. in the EBI chapter. Refer to the Waveform Generation section in the Real-Time Clock (RTC) chapter to select RTCOUTx. the EBI chapter. To select PIODCEN2, refer to the 32.5.14 Parallel Capture Mode in the PIO chapter. 9. Refer to the System I/O Configuration Register ( 19.4.7 CCFG_SYSIO) in the Bus Matrix (MATRIX) chapter. 10. Refer to the 30.5.3 Main Crystal Oscillator section in the Clock Generator chapter. This selection is independent of the PIO line configuration. PIO lines must be configured according to XINxx (I) and XOUTxx (O). the DACC Channel Enable Register in the Digital-to-Analog Converter Controller (DACC) chapter. SAMV71Q21RT Package and Pinout © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 29

Power Considerations

7.1 Power Supplies

The following table defines the power supply rails of the SAMV71Q21RT and the estimated power consumption at typical voltage. Table 7-1. Power Supplies Name Associated Ground Powers VDDCORE GND Core, embedded memories and peripherals. VDDIO GND Peripheral I/O lines (Input/Output Buffers), backup part, 1 Kbytes of backup SRAM, 32 kHz crystal oscillator, oscillator pads. For USB operations, VDDIO voltage range must be between 3.0V and 3.6V. VDDIN GND, GNDANA Voltage regulator input. Also supplies the ADC, DAC and analog voltage comparator. VDDPLL GND, GNDPLL PLLA and the fast RC oscillator. VDDPLLUSB GND, GNDPLLUSB UTMI PLL and the 3 to 20 MHz oscillator. VDDUTMII GNDUTMI USB transceiver interface. Must be connected to VDDIO. VDDUTMIC GNDUTMI USB transceiver core.

7.2 Power Constraints

The following power constraints are applied to SAMV71Q21RT devices. Deviating from these constraints may lead to unpredictable results.

VDDIN and VDDIO must have the same level
VDDIN and VDDIO must always be higher than or equal to VDDCORE
VDDCORE, VDDPLL and VDDUTMIC voltage levels must not vary by more than 0.6V
For the USB to be operational, VDDUTMII, VDDPLLUSB, VDDIN and VDDIO must be higher than or equal to 3.0V

7.2.1 Powerup

VDDIO and VDDIN must rise simultaneously, prior to VDDCORE, VDDPLL and VDDUTMIC rising. This is respected if VDDCORE, VDDPLL and VDDUTMIC are supplied by the embedded voltage regulator. If VDDCORE is powered by an external voltage regulator, VDDIO and VDDIN must reach their minimum operating voltage before VDDCORE has reached VDDCOREmin. The minimum slope for VDDCORE is defined by: VDDCORE min − V T+min / t RESmin If VDDCORE rises at the same time as VDDIO and VDDIN, the minimum and maximum rising slopes of VDDIO and VDDIN must be respected. Refer to the section “DC Characteristics”. In order to prevent any overcurrent at powerup, it is required that VREFP rises simultaneously with VDDIO and VDDIN. SAMV71Q21RT Power Considerations © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 30

Figure 7-1. Powerup Sequence Supply (V) Time (t) VDDIO VDDIN VDDPLLUSB VDDUTMII VDDCORE VDDPLL VDDUTMIC V DDx(min) V T+ V DDy(min) tRST Related Links

23.4.6 Backup Power Supply Reset

23.4.6.1 Raising the Backup Power Supply

7.2.2 Powerdown

If VDDCORE, VDDPLL and VDDUTMIC are not supplied by the embedded voltage regulator, VDDIO, VDDIN, VDDPLLUSB and VDDUTMII should fall simultaneously, prior to VDDCORE, VDDPLL and VDDUTMIC falling. The VDDCORE falling slope must not be faster than 20V/ms. In order to prevent any overcurrent at powerdown, it is required that VREFP falls simultaneously with VDDIO and VDDIN. Figure 7-2. Powerdown Sequence Supply (V) Time (t) VDDIO VDDIN VDDPLLUSB VDDUTMII VDDCORE VDDPLL VDDUTMIC VDDx(min) VDDy(min)

7.3 Voltage Regulator

The SAMV71Q21RT embeds a voltage regulator that is managed by the Supply Controller. For adequate input and output power supply decoupling/bypassing, refer to the DC Characteristics in the Electrical Characteristics chapter.

7.4 Backup SRAM Power Switch

The SAMV71Q21RT embeds a power switch to supply the 1 Kbyte of backup SRAM. It is activated only when VDDCORE is switched off to ensure retention of the contents of the backup SRAM. When VDDCORE is switched on, the backup SRAM is powered with VDDCORE. SAMV71Q21RT Power Considerations © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 31

To save the power consumption of the backup SRAM, the user can disable the backup SRAM power switch by clearing the bit SRAMON in the Supply Controller Mode Register (SUPC_MR). By default, after VDDIO rises, the backup SRAM power switch is enabled.

7.5 Active Mode

Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The Power Management Controller can be used to adapt the core, bus and peripheral frequencies and to enable and/or disable the peripheral clocks.

7.6 Low-power Modes

The SAMV71Q21RT features the following three Low-Power modes:

Backup mode
Wait mode
Sleep mode

7.6.1 Backup Mode

The purpose of Backup mode is to achieve the lowest power consumption possible in a system which is performing periodic wake-ups to perform tasks but not requiring fast startup time. The Supply Controller, zero-power Power-On Reset (POR), RTT, RTC, backup SRAM, backup registers and 32 kHz oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The regulator and the core supply are off. Backup mode is based on the Cortex-M7 Deep-Sleep mode with the voltage regulator disabled. Wake-up from Backup mode is done through WKUP0–13 pins, the supply monitor (SM), the RTT, or an RTC wake-up event. Backup mode is entered by using the VROFF bit in the Supply Controller Control Register (SUPC_CR) and the SLEEPDEEP bit in the Cortex-M7 System Control Register set to 1. Refer to information on Power Management in the" Arm Cortex-M7 documentation", which is available for download at www.arm.com. To enter Backup mode, follow the steps below: 1. Set the SLEEPDEEP bit of the Cortex-M7 processor. 2. Set the VROFF bit of SUPC_CR. Exit from Backup mode occurs as a result of one of the following enabled wake-up events:

WKUP0–13 pins (level transition, configurable debouncing)
Supply Monitor alarm
RTC alarm
RTT alarm

7.6.2 Wait Mode

The purpose of Wait mode is to achieve very low-power consumption while maintaining the whole device in a powered state for a startup time of less than 10 μs. In Wait mode, the clocks of the core, peripherals and memories are stopped. However, the core, peripherals and memories power supplies are still powered. Wait mode is entered when the WAITMODE bit is set in CKGR_MOR and the field FLPM is configured to 00 or 01 in the PMC Fast Startup Mode register (PMC_FSMR). The Cortex-M is able to handle external events or internal events to wake up the core. This is done by configuring the external lines WKUP0–13 as fast startup wake-up pins (refer to the “Fast Startup” section). RTC or RTT alarms or USB wake-up events can be used to wake up the processor. Resume from Wait mode is also achieved when a debug request occurs and the bit CDBGPWRUPREQ is set in the processor. SAMV71Q21RT Power Considerations © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 32

To enter Wait mode, first, select the Main RC oscillator as Main Clock and perform the following steps: 1. Configure the FLPM field in the PMC_FSMR. 2. Set Flash Wait State at 0. 3. Set HCLK = MCK by configuring MDIV to 0 in the PMC Master Clock register (PMC_MCKR). 4. Set the WAITMODE bit in the PMC Clock Generator Main Oscillator register (CKGR_MOR). 5. Wait for MCKRDY = 1 in the PMC Status register (PMC_SR). Note: Internal main clock resynchronization cycles are necessary between writing the MOSCRCEN bit and the entry in Wait mode. Depending on the user application, waiting for the MOSCRCEN bit to be cleared is recommended to ensure that the core will not execute undesired instructions.

7.6.3 Sleep Mode

The purpose of Sleep mode is to optimize power consumption of the device versus response time. In this mode, only the core clock is stopped. The peripheral clocks can be enabled. The current consumption in this mode is application-dependent. This mode is entered using the instruction Wait for Interrupt (WFI). Processor wakeup is triggered by an interrupt if the WFI instruction of the Cortex-M processor is used.

7.6.4 Low-Power Mode Summary Table

The modes detailed above are the main low-power modes. Each part can be set to on or off separately and wake up sources can be individually configured. The following table provides a summary of the configurations of the low-power modes. SAMV71Q21RT Power Considerations © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 33

Table 7-2. Low-power Mode Configuration Summary Moderotatethispage90 SUPC, 32 kHz Oscillator, RTC, RTT Backup SRAM (BRAM), Backup Registers (GPBR), POR (Backup Area) Regulator Core Memory Peripherals Mode Entry Configuration Potential Wakeup Sources Core at Wakeup PIO State while in Low-Power Mode PIO State at Wakeup Wakeup Time (see Note 2) Backup Mode ON OFF OFF (Not powered) SUPC_CR.VROFF = 1 SLEEPDEEP = 1 (see Note 1) WKUP0–13 pins Supply Monitor RTC alarm RTT alarm Reset Previous state maintained PIOA, PIOB, PIOC, PIOD & PIOE inputs with pullups < 2 ms Wait Mode w/Flash in Deep Power- down Mode ON ON Powered (Not clocked) PMC_MCKR.MDIV = 0 CKGR_MOR.WAIT MODE =1 SLEEPDEEP = 0 PMC_FSMR.LPM = 1 PMC_FSMR.FLPM = 1 (see Note 1) WKUP0–13 pins RTC RTT USBHS Processor debug (see Note 6) GMAC Wake on LAN event Wakeup from CAN (see Note 7) Clocked back (see Note 3) Previous state maintained Unchanged < 10 μs Wait Mode w/Flash in Standby Mode ON ON Powered (Not clocked) PMC_MCKR.MDIV = 0 CKGR_MOR.WAIT MODE =1 SLEEPDEEP = 0 PMC_FSMR.LPM = 1 PMC_FSMR.FLPM = 0 (see Note 1) WKUP0–13 pins RTC RTT USBHS Processor debug (see Note 6) GMAC Wake on LAN Wakeup from CAN (see Note 7) Clocked back (see Note 3) Previous state maintained Unchanged < 10 μs SAMV71Q21RT Power Considerations © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 34

SUPC, 32 kHz Oscillator, RTC, RTT Backup SRAM (BRAM), Backup Registers (GPBR), POR (Backup Area) Regulator Core Memory Peripherals Mode Entry Configuration Potential Wakeup Sources Core at Wakeup PIO State while in Low-Power Mode PIO State at Wakeup Wakeup Time (see Note 2) Sleep Mode ON ON Powered (Not clocked) (see Note 4) WFI SLEEPDEEP = 0 PMC_FSMR.LPM = 0 (see Note 1) Any enabled Interrupt Clocked back Previous state maintained Unchanged (see Note 5) SAMV71Q21RT Power Considerations © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 35

Notes: 1. The bit SLEEPDEEP is in the Cortex-M7 System Control Register. 2. When considering wakeup time, the time required to start the PLL is not taken into account. Once started, the device works with the Main RC oscillator. The user has to add the PLL startup time if it is needed in the system. The wakeup time is defined as the time taken for wakeup until the first instruction is fetched. 3. HCLK = MCK. The user may need to revert back to the previous clock configuration. 4. Depends on MCK frequency. 5. In this mode, the core is supplied and not clocked. Some peripherals can be clocked. 6. Resume from Wait mode if a debug request occurs (CDBGPWRUPREQ is set in the processor). 7. CAN wake-up requires the use of any WKUP0–13 pin.

7.7 Wakeup Sources

Wakeup events allow the device to exit Backup mode. When a wakeup event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they are not already enabled.

7.8 Fast Startup

The SAMV71Q21RT allows the processor to restart in a few microseconds while the processor is in Wait mode or in Sleep mode. A fast startup can occur upon detection of a low level on any of the following wake-up sources:

WKUP0 to WKUP13 pins
Supply Monitor
RTC alarm
RTT alarm
USBHS interrupt line (WAKEUP)
Processor debug request (CDBGPWRUPREQ)
GMAC wake on LAN event Note: CAN wake-up requires the use of any WKUP0–13 pin. The fast restart circuitry is fully asynchronous and provides a fast startup signal to the Power Management Controller. As soon as the fast startup signal is asserted, the PMC automatically restarts the Main RC oscillator, switches the Master clock on this clock and re-enables the processor clock. SAMV71Q21RT Power Considerations © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 36

Input/Output Lines The SAMV71Q21RT features both general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be used, whether in I/O mode or by the multiplexed peripherals. System I/Os include pins such as test pins, oscillators, erase or analog inputs.

8.1 General-Purpose I/O Lines

General-purpose (GPIO) lines are managed by PIO Controllers. All I/Os have several input or output modes such as pull-up or pull-down, input Schmitt triggers, multi-drive (open-drain), glitch filters, debouncing or input change interrupt. Programming of these modes is performed independently for each I/O line through the PIO controller user interface. For more details, refer to 32. Parallel Input/Output Controller (PIO). The input/output buffers of the PIO lines are supplied through VDDIO power supply rail. The SAMV71Q21RT embeds high-speed pads able to handle the high-speed clocks for HSMCI, SPI and QSPI (MCK/2). Refer to Electrical Characteristics for more details. Typical pull-up and pull-down value is 100 kΩ for all I/Os. Each I/O line also embeds an RSERIAL (On-die Serial Resistor), as shown in the following figure. It consists of an internal series resistor termination scheme for impedance matching between the driver output (SAMV71Q21RT) and the PCB trace impedance preventing signal reflection. The series resistor helps to reduce I/Os switching current (di/dt), thereby reducing EMI. It also decreases overshoot and undershoot (ringing) due to inductance of interconnect between devices or between boards. Finally, RSERIAL helps diminish signal integrity issues. Figure 8-1. On-Die Termination (ODT) PCB Trace Z0 ~ 50 Ohms Receiver Driver with RSERIAL ZOUT ~ 10 Ohms Z0 ~ ZOUT + RODT On-die Serial Resistor

36 Ohms typ

8.2 System I/O Lines

System I/O lines are pins used by oscillators, Test mode, reset, JTAG and other features. The following table lists the SAMV71Q21RT system I/O lines shared with PIO lines. These pins are software-configurable as general-purpose I/Os or system pins. At startup, the default function of these pins is always used. Table 8-1. System I/O Configuration Pin List CCFG_SYSIO Bit Number Default Function After Reset Other Function Constraints for Normal Start Configuration

12 ERASE PB12 Low Level at startup

(see Note 1) In Matrix User Interface Registers (Refer to the 19.4.7 CCFG_SYSIO register)7 TCK/SWCLK PB7 –

6 TMS/SWDIO PB6 –

5 TDO/TRACESWO PB5 –

4 TDI PB4 –

CCFG_SYSIO Bit Number Default Function After Reset Other Function Constraints for Normal Start Configuration – PA7 XIN32 – (see Note 2) – PA8 XOUT32 – – PB9 XIN – (see Note 3) – PB8 XOUT – Notes: 1. If PB12 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash erase before the user application sets PB12 into PIO mode. 2. Refer to 23.4.2 Slow Clock Generator. 3. Refer to 30.5.3 Main Crystal Oscillator.

8.2.1 Serial Wire Debug Port (SW-DP) Pins

The SW-DP pins SWCLK and SWDIO are commonly provided on a standard 20-pin JTAG connector defined by ARM. For more details about voltage reference and reset state, refer to Table 4-1. At startup, SW-DP pins are configured in SW-DP mode to allow connection with debugging probe. For more details, refer to 16. Debug and Test Features. SW-DP pins can be used as standard I/Os to provide users more general input/output pins when the debug port is not needed in the end application. Mode selection between SW-DP mode (System IO mode) and general IO mode is performed through the AHB Matrix Special Function Registers (MATRIX_SFR). Configuration of the pad for pull-up, triggers, debouncing and glitch filters is possible regardless of the mode. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pulldown resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. The JTAG Debug Port TDI, TDO, TMS and TCK is inactive. It is provided for Boundary Scan Manufacturing Test purpose only.

8.2.2 Embedded Trace Module (ETM) Pins

The Embedded Trace Module (ETM) depends on the Trace Port Interface Unit (TPIU) to export data out of the system. The TPUI features the following pins:

TRACECLK is always exported to enable synchronization with the data.
TRACED0–TRACED3 is the instruction trace stream.

8.3 NRST Pin

The NRST pin is bidirectional. It is handled by the on-chip Reset Controller (RSTC) and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. It resets the core and the peripherals, with the exception of the Backup area (RTC, RTT, Backup SRAM and Supply Controller). The NRST pin integrates a permanent pullup resistor to VDDIO of about 100 kΩ. By default, the pin is configured as an input.

8.4 ERASE Pin

The ERASE pin is used to reinitialize the Flash content and some of its NVM bits to an erased state (all bits read as logic level 1). The ERASE pin and the ROM code ensure an in-situ reprogrammability of the Flash content without the use of a debug tool. When the security bit is activated, the ERASE pin provides the capability to reprogram the Flash content. The ERASE pin integrates a pull-down resistor of about 100 kΩ to GND, so that it can be left unconnected for normal operations. SAMV71Q21RT Input/Output Lines © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 38

The ERASE pin is a system I/O pin that can be used as a standard I/O. At startup, this system I/O pin defaults to the ERASE function. This pin is debounced by SLCK to improve the glitch tolerance. To avoid unexpected erase at power-up due to glitches, a minimum ERASE pin assertion time is required. This time is defined in the section "Embedded Flash Characteristics". The erase operation cannot be performed when the system is in Wait mode. If the ERASE pin is used as a standard I/O in Input or Output mode, note the following considerations and behavior:

I/O Input mode: at startup of the device, the logic level of the pin must be low to prevent unwanted erasing until the user application has reconfigured this system I/O pin to a standard I/O pin.
I/O Output mode: asserting the pin to low does not erase the Flash During software application development, faulty software may put the device into a deadlock. This may be due to:
Programming an incorrect clock switching sequence
Using this system I/O pin as a standard I/O pin
Entering Wait mode without any wake-up events programmed To recover normal behavior, the Flash must be erased by following the steps below: 1. Apply a logic “1” level on the ERASE pin. 2. Apply a logic “0” level on the NRST pin. 3. Maintain the ERASE pin to logic “1” level for at least the minimum assertion time after releasing the NRST pin to logic “1” level. SAMV71Q21RT Input/Output Lines © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 39

Interconnect The system architecture is based on the ARM Cortex-M7 processor connected to the main AHB Bus Matrix, the embedded Flash, the multi-port SRAM and the ROM. The 32-bit AHBP interface is a single 32-bit wide interface that accesses the peripherals connected on the main Bus Matrix. It is used only for data access. Instruction fetches are never performed on the AHBP interface. The bus, AHBP or AXIM, accessing the peripheral memory area [0x40000000 to 0x60000000] is selected in the AHBP control register. The 32-bit AHBS interface provides system access to the ITCM, D1TCM, and D0TCM. It is connected on the main Bus Matrix and allows the XDMA to transfer from memory or peripherals to the instruction or data TCMs. The 64-bit AXIM interface is a single 64-bit wide interface connected through two ports of the AXI Bridge to the main AHB Bus Matrix and to two ports of the multi-port SRAM. The AXIM interface allows:

Instruction fetches
Data cache linefills and evictions
Non-cacheable normal-type memory data accesses
Device and strongly-ordered type data accesses, generally to peripherals The interleaved multi-port SRAM optimizes the Cortex-M7 accesses to the internal SRAM. The interconnect of the other masters and slaves is described in 19. Bus Matrix (MATRIX). The figure below shows the connections of the different Cortex-M7 ports. Figure 9-1. Interconnect Block Diagram 12-layer AHB Bus Matrix fMAX 150 MHz In-Circuit Emulator MPU Cortex-M7 Processor fMAX 300 MHz NVIC FPU TPIU ETM

16 Kbytes

M MM S AXIMAHBP S AHBS AXI Bridge ROM Multi-Port SRAM Flash ITCM DTCM TCM SRAM System SRAM 64-bit 32-bit 32-bit 2 x 32-bit 64-bit 32-bit32-bit 32-bit 32-bit SAMV71Q21RT Interconnect © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 40

Product Mapping Figure 10-1. SAMV71Q21RT Product Mapping Address memory space Code 0x00000000 Internal SRAM 0x20000000 Peripherals 0x40000000 Memories 0x60000000 QSPI MEM 0x80000000 0xA0000000 USBHS RAM 0xA0100000 Reserved 0xA0200000 System 0xE0000000 0xFFFFFFFF Code ITCM or Boot Memory 0x00000000 Internal Flash 0x00400000 ROM 0x00800000 Reserved 0x00C00000 0x1FFFFFFF Internal SRAM DTCM 0x20000000 SRAM 0x20400000 Reserved 0x20C00000 0x3FFFFFFF Peripherals HSMCI 0x40000000 SSC 0x40004000 SPI0 0x40008000 TC0_CH0 0x4000C000 TC0_CH1 +0x40 TC0_CH2 +0x80 TC1_CH0 0x40010000 TC1_CH1 +0x40 TC1_CH2 +0x80 TC2_CH0 0x40014000 TC2_CH1 +0x40 TC2_CH2 +0x80 TWIHS0 0x40018000 TWIHS1 0x4001C000 PWM0 0x40020000 USART0 0x40024000 USART1 0x40028000 USART2 0x4002C000 MCAN0 0x40030000 MCAN1 0x40034000 USBHS 0x40038000 AFEC0 0x4003C000 DACC 0x40040000 ACC 0x40044000 ICM 0x40048000 ISI 0x4004C000 GMAC 0x40050000 TC3_CH0 0x40054000 TC3_CH1 +0x40 TC3_CH2 +0x80 SPI1 0x40058000 PWM1 0x4005C000 TWIHS2 0x40060000 AFEC1 0x40064000 MLB 0x40068000 AES 0x4006C000 TRNG 0x40070000 BRAM 0x40074000 XDMAC 0x40078000 QSPI 0x4007C000 SMC 0x40080000 SDRAMC 0x40084000 MATRIX 0x40088000 UTMI 0x40090000 PMC 0x400E0600 UART0 0x400E0800 CHIPID 0x400E0940 UART1 0x400E0A00 EFC 0x400E0C00 PIOA 0x400E0E00 PIOB 0x400E1000 PIOC 0x400E1200 PIOD 0x400E1400 PIOE 0x400E1600 0x400E1800 memories EBI Chip Select 0 0x60000000 EBI Chip Select 1 0x61000000 EBI Chip Select 2 0x62000000 EBI Chip Select 3 0x63000000 SDRAM Chip Select 0x70000000 0x7FFFFFFF offset ID (+ : wired-or) peripheralblock I2SC0 I2SC1 0x400E0400 0x4008C000 Peripherals SYSC RSTC 0x400E1800 SYSC SUPC +0x10 SYSC RTT +0x30 SYSC WDT0 +0x50 SYSC RTC +0x60 SYSC GPBR +0x90 SYSC WDT1 +0x100 UART2 0x400E1A00 UART3 0x400E1C00 UART4 0x400E1E00 Reserved 0x400E2000 0x5FFFFFFF Peripherals Reserved SAMV71Q21RT Product Mapping © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 41

Memories

11.1 Embedded Memories

11.1.1 Internal SRAM

The SAMV71Q21RT embeds 384 Kbytes of high-speed SRAM. The SRAM is accessible over the system Cortex-M bus at address 0x2040 0000. The SAMV71Q21RT embeds a Multi-Port SRAM with four ports to optimize the bandwidth and latency. The priorities, defined in the Bus Matrix for each SRAM port slave are propagated, for each request, up to the SRAM slaves. The Bus Matrix supports four priority levels: Normal, Bandwidth-sensitive, Latency-sensitive and Latency-critical in order to increase the overall processor performance while securing the high-priority latency-critical requests from the peripherals. The SRAM controller manages interleaved addressing of SRAM blocks to minimize access latencies. It uses Bus Matrix priorities to give the priority to the most urgent request. The less urgent request is performed no later than the next cycle. Two SRAM slave ports are dedicated to the Cortex-M7 while two ports are shared by the AHB masters.

11.1.2 Tightly Coupled Memory (TCM) Interface

The SAMV71Q21RT embeds Tightly Coupled Memory (TCM) running at processor speed.

ITCM is a single 64-bit interface, based at 0x0000 0000 (code region).
DTCM is composed of dual 32-bit interfaces interleaved, based at 0x2000 0000 (data region). ICTM and DTCM are enabled/disabled in the ITCMR and DTCMR registers in Arm SCB. DTCM is enabled at reset by default. ITCM is disabled by default at reset. There are four TCM configurations controlled by software. When enabled, ITCM is located at 0x0000 0000, overlapping ROM or Flash depending on the general-purpose NVM bit 1 (GPNVM). The configuration is done with GPNVM bits [8:7]. Table 11-1. TCM Configurations in Kbytes ITCM DTCM SRAM for 384K RAM-based GPNVM Bits [8:7] 0 0 384 0 32 32 320 1 64 64 256 2 128 128 128 3 Accesses made to TCM regions when the relevant TCM is disabled and accesses made to the Code and SRAM region above the TCM size limit are performed on the AHB matrix, i.e., on internal Flash or on ROM depending on remap GPNVM bit. Accesses made to the SRAM above the size limit will not generate aborts. The Memory Protection Unit (MPU) can to be used to protect these areas.

11.1.3 Internal ROM

The SAMV71Q21RT embeds an Internal ROM for the SAM Boot Assistant (SAM-BA®), In Application Programming functions (IAP) and Fast Flash Programming Interface (FFPI). At any time, the ROM is mapped at address 0x0080 0000. The ROM may also be mapped at 0x00000000 depending on GPNVM bit setting and ITCM use. SAMV71Q21RT Memories © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 42

11.1.4 Backup SRAM

The SAMV71Q21RT embeds 1 Kbytes of backup SRAM located at 0x4007 4000. The backup SRAM is accessible in 32-bit words only. Byte or half-word accesses are not supported. The backup SRAM is supplied by VDDCORE in Normal mode. In Backup mode, the backup SRAM supply is automatically switched to VDDIO through the backup SRAM power switch when VDDCORE falls. For more details, see the “Backup SRAM Power Switch” section.

11.1.5 Flash Memories

The SAMV71Q21RT embeds 2084 Kbytes of internal Flash mapped at address 0x00400000. The device features a Quad SPI (QSPI) interface, mapped at address 0x80000000, that extends the Flash size by adding an external SPI or QSPI Flash. When accessed by the Cortex-M7 processor for programming operations, the QSPI and internal Flash address spaces must be defined in the Cortex-M7 memory protection unit (MPU) with the attribute 'Device' or 'Strongly Ordered'. For fetch or read operations, the attribute ‘Normal memory’ must be set to benefit from the internal cache. Refer to the Arm Cortex-M7 Technical Reference Manual (ARM DDI 0489) available on www.arm.com. Some precautions must be taken when the accesses are performed by the central DMA. Refer to 22. Enhanced Embedded Flash Controller (EEFC) and 42. Quad Serial Peripheral Interface (QSPI).

11.1.5.1 Embedded Flash Overview

The memory is organized in sectors. Each sector has a size of 128 Kbytes. The first sector is divided into three smaller sectors. The three smaller sectors are organized in two sectors of 8 Kbytes and one sector of 112 Kbytes. Refer to the figure below. SAMV71Q21RT Memories © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 43

Figure 11-1. Global Flash Organization 0x000 Small Sector 08 Kbytes Small Sector 18 Kbytes Larger Sector 112 Kbytes Sector 1128 Kbytes

128 Kbytes Sector n

Address Sector size Sector Name Each sector is organized in pages of 512 bytes. For sector 0:

The smaller sector 0 has 16 pages of 512 bytes
The smaller sector 1 has 16 pages of 512 bytes
The larger sector has 224 pages of 512 bytes The rest of the array is composed of 128-Kbyte sectors of 256 pages of 512 bytes each. See below. Figure 11-2. Flash Sector Organization 224 pages of 512 bytes Sector 0 Sector n Smaller sector 0 Smaller sector 1 Larger sector 256 pages of 512 bytes Sector size is 128 Kbytes 16 pages of 512 bytes 16 pages of 512 bytes The figure below illustrates the organization of the Flash depending on its size. SAMV71Q21RT Memories © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 44

Figure 11-3. Flash Size 2 * 8 Kbytes 1 * 112 Kbytes 7 * 128 Kbytes 2 * 8 Kbytes 1 * 112 Kbytes 3 * 128 Kbytes 2 * 8 Kbytes 1 * 112 Kbytes 15 * 128 Kbytes Flash 2 Mbytes Flash 1 Mbyte Flash 512 Kbytes Erasing the memory can be performed:

Chip Erase
By block of 8 Kbytes
By sector of 128 Kbytes
By 512-byte page – Erase memory by page is possible only in an 8 Kbyte sector – EWP and EWPL commands can be only used in 8 Kbyte sectors The memory has one additional reprogrammable page that can be used as page signature by the user. It is accessible through specific modes, for erase, write and read operations. Erase pin assertion will not erase the User Signature page.

11.1.5.2 Enhanced Embedded Flash Controller

Each Enhanced Embedded Flash Controller manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped on the APB. The Enhanced Embedded Flash Controller ensures the interface of the Flash block. It manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash organization, thus making the software generic.

11.1.5.3 Flash Speed

The user must set the number of wait states depending on the system frequency. For more details, refer to Embedded Flash Characteristics in the Electrical Characteristics section.

11.1.5.4 Lock Regions

Several lock bits are used to protect write and erase operations on lock regions. A lock region is composed of several consecutive pages, and each lock region has its associated lock bit. Table 11-2. Flash Lock Bits Flash Size (Kbytes) Number of Lock Bits Lock Region Size 2048 128 16 Kbytes SAMV71Q21RT Memories © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 45

Flash Size (Kbytes) Number of Lock Bits Lock Region Size 1024 64 16 Kbytes 512 32 16 Kbytes Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

11.1.5.5 Security Bit Feature

The SAMV71Q21RT features a security bit based on the GPNVM bit 0. When security is enabled, any access to the Flash, SRAM, core registers and internal peripherals, either through the SW-DP, the ETM interface or the Fast Flash Programming Interface, is blocked. This ensures the confidentiality of the code programmed in the Flash. This security bit can only be enabled through the command “Set General-purpose NVM Bit 0” of the EEFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated, all accesses to the Flash, SRAM, Core registers, Internal Peripherals are permitted.

11.1.5.6 Unique Identifier

The device contains a unique identifier of 2 pages of 512 bytes. These 2 pages are read-only and cannot be erased even by the ERASE pin. The sequence to read the unique identifier area is described in 22.4.3.8 Unique Identifier Area. The mapping is as follows:

Bytes [0..15]: 128 bits for unique identifier
Bytes[16..1023]: Reserved

11.1.5.7 User Signature

Each device contains a user signature of 512 bytes that is available to the user. The user signature can be used to store information such as trimming, keys, etc., that the user does not want to be erased by asserting the ERASE pin or by software ERASE command. Read, write and erase of this area is allowed.

11.1.5.8 Fast Flash Programming Interface (FFPI)

The Fast Flash Programming Interface (FFPI) allows programming the device through a multiplexed fully- handshaked parallel port. It allows gang programming with market-standard industrial programmers. The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The FFPI is enabled and the Fast Programming mode is entered when TST and PA3 and PA4 are tied low. Table 11-3. FFPI on PIO Controller A (PIOA) I/O Line System Function PD10 PGMEN0 PD11 PGMEN1 PB0 PGMM0 PB1 PGMM1 PB2 PGMM2 PB3 PGMM3 PA3 PGMNCMD PA4 PGMRDY PA5 PGMNOE PA21 PGMNVALID SAMV71Q21RT Memories © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 46

11.1.5.9 SAM-BA Boot

The SAM-BA Boot is a default boot program which provides an easy way to program in-situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication via the UART0 and USB1. The SAM-BA Boot provides an interface with SAM-BA computer application. The SAM-BA Boot is in ROM at address 0x0 when the bit GPNVM1 is set to 0. Note: 1. USB is not supported on this device.

11.1.5.10 General-purpose NVM (GPNVM) Bits

All SAMV71Q21RT devices feature nine general-purpose NVM (GPNVM) bits that can be cleared or set, through the “Clear GPNVM Bit” and “Set GPNVM Bit” commands of the EEFC User Interface. The GPNVM0 bit is the security bit. The GPNVM1 bit is used to select the Boot mode (Boot always at 0x00) on ROM or Flash. Table 11-4. General-purpose Non volatile Memory Bits GPNVM Bit Function

0 Security bit

1 Boot mode selection

0: ROM (default) 1: Flash 5:2 Free

6 Reserved

8:7 TCM configuration 00: 0 Kbytes DTCM + 0 Kbytes ITCM (default) 01: 32 Kbytes DTCM + 32 Kbytes ITCM 10: 64 Kbytes DTCM + 64 Kbytes ITCM 11: 128 Kbytes DTCM + 128 Kbytes ITCM Note: After programming, reboot must be done.

11.1.6 Boot Strategies

The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed using GPNVM bits. A GPNVM bit is used to boot either on the ROM (default) or from the Flash. The GPNVM bit can be cleared or set, respectively, through the commands “Clear General-purpose NVM Bit” and “Set General-purpose NVM Bit” of the EEFC User Interface. Setting the bit GPNVM1 selects boot from the Flash. Clearing it selects boot from the ROM. Asserting ERASE resets the bit GPNVM1 and thus selects boot from ROM.

11.2 External Memories

The SAMV71Q21RT features one External Bus Interface to provide an interface to a wide range of external memories and to any parallel peripheral. SAMV71Q21RT Memories © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 48

Event System The events generated by peripherals (source) are designed to be directly routed to peripherals (destination) using these events without processor intervention. The trigger source can be programmed in the destination peripheral.

12.1 Embedded Characteristics

Timers, PWM, I/Os and peripherals generate event triggers which are directly routed to destination peripherals, such as AFEC or DACC to start measurement/conversion without processor intervention.
UART, USART, QSPI, SPI, TWI, PWM, HSMCI, AES, AFEC, DACC, PIO, TC (Capture mode) also generate event triggers directly connected to the DMA Controller for data transfer without processor intervention.
Parallel capture logic is directly embedded in the PIO and generates trigger events to the DMA Controller to capture data without processor intervention.
PWM safety events (faults) are in combinational form and directly routed from event generators (AFEC, ACC, PMC, TC) to the PWM module.
PWM output comparators (OCx) generate events directly connected to the TC.
PMC safety event (clock failure detection) can be programmed to switch the MCK on reliable main RC internal clock without processor intervention. SAMV71Q21RT Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 49

12.2 Real-time Event Mapping

Table 12-1. Real-time Event Mapping List Function Application Description Event Source Event Destination Safety General- purpose Automatic switch to reliable main RC oscillator in case of main crystal clock failure (see Note 1) Power Management Controller (PMC) PMC General- purpose, motor control, power factor correction (PFC) Puts the PWM outputs in Safe mode in case of main crystal clock failure (see Notes 1, 2) PMC Pulse Width Modulation 0 and 1 (PWM0 and PWM1) Motor control, PFC Puts the PWM outputs in Safe mode (overcurrent detection, etc.) (see Notes 2, 3) Analog Comparator Controller (ACC) PWM0 and PWM1 Motor control, PFC Puts the PWM outputs in Safe mode (overspeed, overcurrent detection, etc.) (see Notes 2, 4) Analog Front-End Controller (AFEC0) PWM0 and PWM1 AFEC1 PWM0 and PWM1 Motor control Puts the PWM outputs in Safe mode (overspeed detection through timer quadrature decoder) (see Notes 2, 6) TC0 PWM0 TC1 PWM1 General- purpose, motor control, power factor correction (PFC) Puts the PWM outputs in Safe mode (general-purpose fault inputs) (see Note 2) PIO PA9, PD8, PD9 PWM0 PIO PA21, PA26, PA28 PWM1 Security General- purpose Immediate GPBR clear (asynchronous) on tamper detection through WKUP0/1 IO pins (see Note 5) PIO WKUP0/1 GPBR SAMV71Q21RT Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 50

Function Application Description Event Source Event Destination Measurement trigger Power factor correction (DC-DC, lighting, etc.) Duty cycle output waveform correction Trigger source selection in PWM (see Notes 7, 8) ACC PWM0 PIO PA10, PA22 PWM0 ACC PWM1 PIO PA30, PA18 PWM1 General- purpose Trigger source selection in AFEC (see Note 9) PIO AFE0_ADTRG AFEC0 TC0 TIOA0 AFEC0 TC0 TIOA1 AFEC0 TC0 TIOA2 AFEC0 ACC AFEC0 Motor control ADC-PWM synchronization (see Notes 12, 14) Trigger source selection in AFEC (see Note 9) PWM0 Event Line 0 and 1 AFEC0 General- purpose Trigger source selection in AFEC (see Note 9) PIO AFE1_ADTRG AFEC1 TC1 TIOA3 AFEC1 TC1 TIOA4 AFEC1 TC1 TIOA5 AFEC1 ACC AFEC1 Motor control ADC-PWM synchronization (see Notes 12, 14) Trigger source selection in AFEC (see Note 9) PWM1 Event Line 0 and 1 AFEC1 General- purpose Temperature sensor Low-speed measurement (see Notes 10, 11) RTC RTCOUT0 AFEC0 and AFEC1 Conversion trigger General- purpose Trigger source selection in DACC (Digital-to-Analog Converter Controller) (see Note 13) TC0 TIOA0, TIOA1, TIOA2 DACC PIO DATRG DACC PWM0 Event Line 0 and 1(14) DACC PWM1 Event Line 0 and 1(14) DACC Image capture Low-cost image sensor Direct image transfer from sensor to system memory via DMA(15) PIO PA22, PA14, PA21 DMA SAMV71Q21RT Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 51

Function Application Description Event Source Event Destination Delay measurement Motor control Propagation delay of external components (IOs, power transistor bridge driver, etc.) See Notes 16, 17) PWM0 Comparator Output OC0 TC0 TIOA0 and TIOB0 PWM0 Comparator Output OC1 TC0 TIOA1 and TIOB1 PWM0 Comparator Output OC2 TC0 TIOA2 and TIOB2 PWM1 Comparator Output OC0 TC1 TIOA3 and TIOB3 PWM1 Comparator Output OC1 TC1 TIOA4 and TIOB4 PWM1 Comparator Output OC2 TC1 TIOA5 and TIOB5 PWM0 Comparator Output OC0 TC2 TIOA6 and TIOB6 PWM0 Comparator Output OC1 TC2 TIOA7 and TIOB7 PWM0 Comparator Output OC2 TC2 TIOA8 and TIOB8 PWM1 Comparator Output OC0 TC3 TIOA9 and TIOB9 PWM1 Comparator Output OC1 TC3 TIOA10 and TIOB10 Audio clock recovery from Ethernet Audio GMAC GTSUCOMP signal adaptation via TC (TC_EMR.TRIGSRCB) in order to drive the clock reference of the external PLL for the audio clock GMAC GTSUCOMP TC3 TIOB11 Direct Memory Access General- purpose Peripheral trigger event generation to transfer data to/from system memory (see Note 18) USART, UART, TWIHS, SPI, QSPI, AFEC, TC (Capture), SSC, HSMCI, DAC, AES, PWM, PIO, I2SC XDMA SAMV71Q21RT Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 52

Notes: 1. Refer to 31.15 Main Crystal Oscillator Failure Detection. 3. Refer to 54.6.4 Fault Mode. 4. Refer to 54.5.4 Fault Output. 6. Refer to 50.6.18 Fault Mode. 7. Refer to 51.7.49 PWM_ETRGx. 8. Refer to 51.6.5 PWM External Trigger Mode. 10. Refer to Temperature Sensor. 11. Refer to 27.5.8 Waveform Generation. 13. Refer to 53.7.3 DACC_TRIGR. 15. Refer to 32.5.14 Parallel Capture Mode. 17. Refer to 50.6.14 Synchronization with PWM. 18. Refer to 36. DMA Controller (XDMAC). SAMV71Q21RT Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 53

System Controller The System Controller is a set of peripherals that handles key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, and so on.

13.1 System Controller and Peripherals Mapping

Refer to the Product Mapping section.

13.2 Power-on-Reset, Brownout and Supply Monitor

The SAMV71Q21RT embeds three features to monitor, warn and/or reset the chip:

Power-on-Reset (POR) on VDDIO
POR on VDDCORE
Brown-out-Detector (BOD) on VDDCORE
Supply Monitor on VDDIO

13.2.1 Power-on-Reset

The Power-on-Reset monitors VDDIO and VDDCORE. It is always activated and monitors voltage at start up but also during power down. If VDDIO or VDDCORE goes below the threshold voltage, the entire chip is Reset. For more information, refer to Electrical Characteristics.

13.2.2 Brownout Detector on VDDCORE

The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by software through the Supply Controller (SUPC_MR). It is especially recommended to disable it during low-power modes such as wait or sleep modes. If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For more information, refer to 23. Supply Controller (SUPC) and Electrical Characteristics.

13.2.3 Supply Monitor on VDDIO

The Supply Monitor monitors VDDIO. It is not active by default. It can be activated by software and is fully programmable with 16 steps for the threshold (between 1.6V to 3.4V). It is controlled by the Supply Controller (SUPC). A sample mode is possible, which allows the supply monitor power consumption to be divided by a factor of up to 2048. For more information, refer to 23. Supply Controller (SUPC) and Electrical Characteristics.

13.3 Reset Controller

The Reset Controller is based on two POR cells, one on VDDIO and one on VDDCORE, and a Supply Monitor on VDDIO. The Reset Controller returns the source of the last reset to the software. This may be a general reset, a wakeup reset, a software reset, a user reset or a watchdog reset. The Reset Controller controls the internal resets of the system and the pin input/output. It can shape a reset signal for the external devices, simplifying the connection of a push-button on the NRST pin to implement a manual reset. The configuration of the Reset Controller is saved as supplied on VDDIO. SAMV71Q21RT System Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 54

Peripherals

14.1 Peripheral Identifiers

The following table defines the peripheral identifiers of the SAMV71Q21RT. A peripheral identifier is required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and control of the peripheral clock with the Power Management Controller. Table 14-1. Peripheral Identifiers Instance ID Instance Name NVIC Interrupt PMC Clock Control

Description

0 SUPC X – Supply Controller

1 RSTC X – Reset Controller

2 RTC X – Real Time Clock

3 RTT X – Real Time Timer

4 WDT X – Watchdog Timer

5 PMC X – Power Management Controller

6 EFC X – Enhanced Embedded Flash Controller

7 UART0 X X Universal Asynchronous Receiver/Transmitter

8 UART1 X X Universal Asynchronous Receiver/Transmitter

9 SMC – X Static Memory Controller

10 PIOA X X Parallel I/O Controller A

11 PIOB X X Parallel I/O Controller B

12 PIOC X X Parallel I/O Controller C

13 USART0 X X Universal Synchronous/Asynchronous Receiver/

14 USART1 X X Universal Synchronous/Asynchronous Receiver/

15 USART2 X X Universal Synchronous/Asynchronous Receiver/

16 PIOD X X Parallel I/O Controller D

17 PIOE X X Parallel I/O Controller E

18 HSMCI X X Multimedia Card Interface

19 TWIHS0 X X Two-wire Interface (I2C-compatible)

20 TWIHS1 X X Two-wire Interface (I2C-compatible)

21 SPI0 X X Serial Peripheral Interface

22 SSC X X Synchronous Serial Controller

23 TC0_CHANNEL0 X X 16-bit Timer Counter 0, Channel 0

24 TC0_CHANNEL1 X X 16-bit Timer Counter 0, Channel 1

25 TC0_CHANNEL2 X X 16-bit Timer Counter 0, Channel 2

Instance ID Instance Name NVIC Interrupt PMC Clock Control

26 TC1_CHANNEL0 X X 16-bit Timer Counter 1, Channel 0

27 TC1_CHANNEL1 X X 16-bit Timer Counter 1, Channel 1

28 TC1_CHANNEL2 X X 16-bit Timer Counter 1, Channel 2

29 AFEC0 X X Analog Front-End Controller

30 DACC X X Digital-to-Analog Converter

31 PWM0 X X Pulse Width Modulation Controller

32 ICM X X Integrity Check Monitor

33 ACC X X Analog Comparator Controller

34 USBHS X X USB Host / Device Controller

35 MCAN0 X X CAN IRQ Line 0

36 MCAN0 INT1 – CAN IRQ Line 1

37 MCAN1 X X CAN IRQ Line 0

38 MCAN1 INT1 – CAN IRQ Line 1

39 GMAC X X Ethernet MAC

40 AFEC1 X X Analog Front End Controller

41 TWIHS2 X X Two-wire Interface

42 SPI1 X X Serial Peripheral Interface

43 QSPI X X Quad I/O Serial Peripheral Interface

44 UART2 X X Universal Asynchronous Receiver/Transmitter

45 UART3 X X Universal Asynchronous Receiver/Transmitter

46 UART4 X X Universal Asynchronous Receiver/Transmitter

47 TC2_CHANNEL0 X X 16-bit Timer Counter 2, Channel 0

48 TC2_CHANNEL1 X X 16-bit Timer Counter 2, Channel 1

49 TC2_CHANNEL2 X X 16-bit Timer Counter 2, Channel 2

50 TC3_CHANNEL0 X X 16-bit Timer Counter 3, Channel 0

51 TC3_CHANNEL1 X X 16-bit Timer Counter 3, Channel 1

52 TC3_CHANNEL2 X X 16-bit Timer Counter 3, Channel 2

53 MLB X X MediaLB IRQ 0

54 MLB X – MediaLB IRQ 1

55 – X – Reserved

56 AES X X Advanced Encryption Standard

57 TRNG X X True Random Number Generator

58 XDMAC X X DMA Controller

59 ISI X X Image Sensor Interface

Instance ID Instance Name NVIC Interrupt PMC Clock Control

60 PWM1 X X Pulse Width Modulation Controller

61 ARM FPU – Arm Floating Point Unit interrupt associated with

OFC, UFC, IOC, DZC and IDC bits

62 SDRAMC X – SDRAM Controller

63 RSWDT X – Reinforced Safety Watchdog Timer

64 ARM CCW – Arm Cache ECC Warning

65 ARM CCF – Arm Cache ECC Fault

66 GMAC Q1 – GMAC Queue 1 Interrupt signal toggled on a

DMA write to the first word of each DMA data buffer associated with queue 1

67 GMAC Q2 – GMAC Queue 2 Interrupt signal toggled on a

DMA write to the first word of each DMA data buffer associated with queue 2

68 ARM IXC – Floating Point Unit Interrupt IXC associated with

FPU cumulative exception bit

69 I2SC0 X X Inter-IC Sound Controller

70 I2SC1 X X Inter-IC Sound Controller

71 GMAC Q3 – GMAC Queue 3 Interrupt signal toggled on a

DMA write to the first word of each DMA data buffer associated with queue 3

72 GMAC Q4 – GMAC Queue 4 Interrupt signal toggled on a

DMA write to the first word of each DMA data buffer associated with queue 4

73 GMAC Q5 – GMAC Queue 5 Interrupt signal toggled on a

DMA write to the first word of each DMA data buffer associated with queue 5

14.2 Peripheral Signal Multiplexing on I/O Lines

Two PIO controllers on 64-pin versions (PIOA and PIOB)
Three PIO controllers on the 100-pin version (PIOA, PIOB and PIOD)
Five PIO controllers on the 144-pin version (PIOA, PIOB, PIOC, PIOD and PIOE), that multiplex the I/O lines of the peripheral set. The SAMV71Q21RT PIO Controllers control up to 32 lines and each line can be assigned to one of four peripheral functions: A, B, C or D. For more information on multiplexed signals, refer to the Package and Pinout chapter. SAMV71Q21RT Peripherals © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 57

ARM Cortex-M7 (ARM) Refer to ARM reference documents Cortex-M7 Processor User Guide (ARM DUI 0644) and Cortex-M7 Technical Reference Manual (ARM DDI 0489), available on www.arm.com.

15.1 ARM Cortex-M7 Configuration

The following table provides the configuration for the ARM Cortex-M7 processor in SAMV71Q21RT devices. Table 15-1. ARM Cortex-M7 Configuration Features Configuration Debug Comparator set Full comparator set: 4 DWT and 8 FPB comparators ETM support Instruction ETM interface Internal Trace support (ITM) ITM and DWT trace functionality implemented CTI and WIC Not embedded TCM ITCM max size 128 KB DTCM max size 256 KB Cache Cache size 16 KB for instruction cache, 16 KB for data cache Number of sets 256 for instruction cache, 128 for data cache Number of ways 2 for instruction cache, 4 for data cache Number of words per cache line 8 words (32 bytes) ECC on Cache Embedded NVIC IRQ number 74 IRQ priority levels 8 MPU Number of regions 16 FPU FPU precision Single and double precision AHB Port AHBP addressing size 512 MB SAMV71Q21RT ARM Cortex-M7 (ARM) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 58

Debug and Test Features

16.1 Description

The device features a number of complementary debug and test capabilities. The Serial Wire Debug Port (SW-DP) is used for standard debugging functions, such as downloading code and single-stepping through programs. It also embeds a serial wire trace.

16.2 Embedded Characteristics

Debug access to all memory and registers in the system, including Cortex-M register bank, when the core is running, halted, or held in reset.
Serial Wire Debug Port (SW-DP) debug access
Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches
Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling
Instrumentation Trace Macrocell (ITM) for support of printf style debugging
6-pin Embedded Trace Macrocell (ETM) for instruction trace stream, including CoreSight ™ Trace Port Interface Unit (TPIU)
IEEE1149.1 JTAG Boundary scan on All Digital Pins

16.3 Associated Documents

The SAMV71Q21RT implements the standard ARM CoreSight macrocell. For information on CoreSight, the following reference documents are available from the ARM web site (www.arm.com):

Cortex-M7 User Guide Reference Manual (ARM DUI 0644)
Cortex-M7 Technical Reference Manual (ARM DDI 0489)
CoreSight Technology System Design Guide (ARM DGI 0012)
CoreSight Components Technical Reference Manual (ARM DDI 0314)
ARM Debug Interface v5 Architecture Specification (Doc. ARM IHI 0031)
ARMv7-M Architecture Reference Manual (ARM DDI 0403) SAMV71Q21RT Debug and Test Features © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 59

16.4 Debug and Test Block Diagram

Figure 16-1. Debug and Test Block Diagram TST TMS/SWDIO TCK/SWCLK TDI JTAGSEL TDO/TRACESWO Boundary Test Access Port (TAP) Serial Wire Debug Port Reset and Test POR Embedded Trace Macrocell PIO TRACED0–3 Cortex-M7 PCK3 TRACECLK

16.5 Debug and Test Pin Description

Table 16-1. Debug and Test Signal List Signal Name Function Type Active Level Reset/Test NRST Microcontroller Reset Input/Output Low TST Test Select Input – Serial Wire Debug Port/JTAG Boundary Scan TCK/SWCLK Test Clock/Serial Wire Clock Input – TDI Test Data In Input – TDO/TRACESWO Test Data Out/Trace Asynchronous Data Out Output – TMS/SWDIO Test Mode Select/Serial Wire Input/Output Input – JTAGSEL JTAG Selection Input High Trace Debug Port TRACECLK Trace Clock Output – TRACED0–3 Trace Data Output – SAMV71Q21RT Debug and Test Features © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 60

16.6 Application Examples

16.6.1 Debug Environment

The figure below shows a complete debug environment example. The SW-DP interface is used for standard debugging functions, such as downloading code and single-stepping through the program and viewing core and peripheral registers. Figure 16-2. Application Debug Environment Example Microchip MCU Host Debugger PC Cortex-M7-based Application Board Serial Wire Debug Port Connector Serial Wire Debug Port Emulator/Probe

16.6.2 Test Environment

The figure below shows a test environment example (JTAG Boundary scan). Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 16-3. Application Test Environment Example Chip 2Chip n Chip 1Microchip MCU Cortex-M7-based Application Board In Test JTAG Connector Tester Test Adaptor JTAG Probe SAMV71Q21RT Debug and Test Features © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 61

16.7 Functional Description

16.7.1 Test Pin

The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash Programming mode. The TST pin integrates a permanent pulldown resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. To enable Fast Flash Programming mode, refer to 18. Fast Flash Programming Interface (FFPI).

16.7.2 Debug Architecture

Figure 16-4 shows the debug architecture used. The Cortex-M7 embeds six functional units for debug:

Serial Wire Debug Port (SW-DP) debug access
FPB (Flash Patch Breakpoint)
DWT (Data Watchpoint and Trace)
ITM (Instrumentation Trace Macrocell)
6-pin Embedded Trace Macrocell (ETM) for instruction trace stream, including CoreSight Trace Port Interface Unit (TPIU)
IEEE1149.1 JTAG Boundary scan on all digital pins The debug architecture information that follows is mainly dedicated to developers of SW-DP Emulators/Probes and debugging tool vendors for Cortex-M7-based microcontrollers. For further details on SW-DP, see the Cortex - M7 Technical Reference Manual. Figure 16-4. Debug Architecture

4 Watchpoints

6 Breakpoints

Instrumentation Trace Macrocell Serial Wire Debug Serial Wire Debug Port Serial Wire Output Trace Instruction Trace Time Stamping Embedded Trace Macrocell Trace Port

16.7.3 Serial Wire Debug Port (SW-DP) Pins

The SW-DP pins SWCLK and SWDIO are commonly provided on a standard 20-pin JTAG connector defined by ARM. For more details on voltage reference and reset state, refer to the "Signal Description" chapter. At startup, SW-DP pins are configured in SW-DP mode to allow connection with debugging probe. SW-DP pins can be used as standard I/Os to provide users more general input/output pins when the debug port is not needed in the end application. Mode selection between SW-DP mode (System I/O mode) and general I/O mode is performed through the AHB Matrix Chip Configuration registers (CCFG_SYSIO). Configuration of the pad for pullup, triggers, debouncing and glitch filters is possible regardless of the mode. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pulldown resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. The JTAG debug ports TDI, TDO, TMS and TCK are inactive. They are provided for Boundary Scan Manufacturing Test purposes only. By default the SW-DP is active; TDO/TRACESWO can be used for trace. SAMV71Q21RT Debug and Test Features © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 62

Table 16-2. SW-DP Pin List Pin Name JTAG Boundary Scan Serial Wire Debug Port TMS/SWDIO TMS SWDIO TCK/SWCLK TCK SWCLK TDI TDI – TDO/TRACESWO TDO TRACESWO (optional: trace) SW-DP is selected when JTAGSEL is low. It is not possible to switch directly between SW-DP and JTAG boundary scan operations. A chip reset must be performed after JTAGSEL is changed.

16.7.4 Embedded Trace Module (ETM) Pins

The Embedded Trace Module (ETM) uses the Trace Port Interface Unit (TPIU) to export data out of the system. The TPUI features the pins:

TRACECLK–always exported to enable synchronization back with the data. PCK3 is used internally.
TRACED0–3–the instruction trace stream.

16.7.5 Flash Patch Breakpoint (FPB)

The FPB implements hardware breakpoints.

16.7.6 Data Watchpoint and Trace (DWT)

The DWT contains four comparators which can be configured to generate:

PC sampling packets at set intervals
PC or Data watchpoint packets
Watchpoint event to halt core The DWT contains counters for:
Clock cycle (CYCCNT)
Folded instructions
Load Store Unit (LSU) operations
Sleep cycles
CPI (all instruction cycles except for the first cycle)
Interrupt overhead

16.7.7 Instrumentation Trace Macrocell (ITM)

The ITM is an application driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets which can be generated by three different sources with several priority levels:

Software trace: Software can write directly to ITM stimulus registers. This can be done using the printf function. For more information, refer to 16.7.5 Flash Patch Breakpoint (FPB).
Hardware trace: The ITM emits packets generated by the DWT.
Timestamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate the timestamp.

16.7.7.1 How to Configure the ITM

The following example describes how to output trace data in asynchronous trace mode. 1. Enable the write accesses into the ITM registers by writing “0xC5ACCE55” into the Lock Access Register (Address: 0xE0000FB0) 2. Write 0x00010015 into the Trace Control register: SAMV71Q21RT Debug and Test Features © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 63

– Enable ITM. – Enable Synchronization packets. – Enable SWO behavior. – Fix the ATB ID to 1. 3. Write 0x1 into the Trace Enable register: – Enable the Stimulus port 0. 4. Write 0x1 into the Trace Privilege register: – Stimulus port 0 only accessed in privileged mode (Clearing a bit in this register will result in the corresponding stimulus port being accessible in user mode.) 5. Write into the Stimulus port 0 register: TPIU (Trace Port Interface Unit) The TPIU acts as a bridge between the on-chip trace data and the Instruction Trace Macrocell (ITM). The TPIU formats and transmits trace data off-chip at frequencies asynchronous to the core.

16.7.7.2 Asynchronous Mode

The TPIU is configured in asynchronous mode, trace data are output using the single TRACESWO pin. The TRACESWO signal is multiplexed with the TDO signal. As a consequence, asynchronous trace mode is only available when the Serial Wire Debug mode is selected. Two encoding formats are available for the single pin output:

Manchester encoded stream. This is the reset value.
NRZ_based UART byte structure

16.7.7.3 How to Configure the TPIU

This example only concerns the asynchronous trace mode. Set the TRCENA bit to 1 into the Debug Exception and Monitor Register (0xE000EDFC) to enable the use of trace and debug blocks. 1. Write 0x2 into the Selected Pin Protocol Register. – Select the Serial Wire output – NRZ 2. Write 0x100 into the Formatter and Flush Control Register. 3. Set the suitable clock prescaler value into the Async Clock Prescaler Register to scale the baud rate of the asynchronous output (this can be done automatically by the debugging tool). 16.7.8 IEEE1149.1 JTAG Boundary Scan IEEE1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE1149.1 JTAG Boundary Scan is enabled when TST is tied to high, PD0 tied to low, and JTAGSEL tied to high during powerup. These pins must be maintained in their respective states for the duration of the boundary scan operation. The SAMPLE, EXTEST and BYPASS functions are implemented. In Serial Wire Debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor. This is not IEEE1149.1 JTAG-compliant. It is not possible to switch directly between JTAG Boundary Scan and SWJ Debug Port operations. A chip reset must be performed after JTAGSEL is changed. A Boundary Scan Descriptor Language (BSDL) file to set up the test is provided on www.microchip.com.

16.7.8.1 JTAG Boundary Scan Register

The Boundary Scan Register (BSR) contains a number of bits which correspond to active pins and associated control signals. Each input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. For more information, refer to BDSL files available on www.microchip.com.

16.7.9 ID Code Register

PART NUMBER MANUFACTURER IDENTITY 7 6 5 4 3 2 1 0 MANUFACTURER IDENTITY 1

VERSION[31:28]: Product Version Number Set to 0x0.
PART NUMBER[27:12]: Product Part Number Set to 0x0. PART NUMBER 0x5B3D
MANUFACTURER IDENTITY[11:1]: Manufacturer ID Set to 0x01F.
Bit[0]: Required by IEEE Std. 1149.1 Set to 0x1. JTAG ID Code 0x5B3D_D03F SAMV71Q21RT Debug and Test Features © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 65

SAM-BA Boot Program

17.1 Description

The SAM-BA Boot Program integrates an array of programs permitting download and/or upload into the different memories of the product.

17.2 Embedded Characteristics

Default Boot Program
Interface with SAM-BA Graphic User Interface
SAM-BA Boot – Supports several communication media
Serial Communication on UART0
USB device port communication up to 1Mbyte/s – USB Requirements
Not supported

17.3 Hardware and Software Constraints

SAM-BA Boot uses the first 2048 bytes of the SRAM for variables and stacks. The remaining available bytes can be used for user code.
USB Requirements: – Not supported
UART0 Requirements: – None. If no accurate external clock source is available, the internal 12 MHz RC meets RS-232 standards. Table 17-1. Pins Driven during Boot Program Execution Peripheral Pin PIO Line UART0 URXD0 PA9 UART0 UTXD0 PA10

17.4 Flow Diagram

The boot program implements the algorithm below. Figure 17-1. Boot Program Algorithm Flow Diagram Device Setup Character # received from UART0? Run SAM-BA Monitor USB Enumeration Successful ? Y es Run SAM-BA Monitor Y es No No The SAM-BA boot program looks for a source clock, either from the embedded main oscillator with external crystal (main oscillator enabled) or from a supported frequency signal applied to the XIN pin (Main oscillator in bypass mode). SAMV71Q21RT SAM-BA Boot Program © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 66

If a clock is supplied by one of the two sources, the boot program checks that the frequency is one of the supported external frequencies. If the frequency is supported, USB activation is allowed. If no clock is supplied, or if a clock is supplied but the frequency is not a supported external frequency, the internal 12 MHz RC oscillator is used as the main clock. In this case, the USB is not activated due to the frequency drift of the 12 MHz RC oscillator.

17.5 Device Initialization

Initialization by the boot program follows the steps described below: Stack setup. 1. Embedded Flash Controller setup. 2. External clock (crystal or external clock on XIN) detection. 3. External crystal or clock with supported frequency supplied. a. If yes, USB activation is allowed. b. If no, USB activation is not allowed. The internal 12 MHz RC oscillator is used. 4. Master clock switch to main oscillator. 5. C variable initialization. 6. PLLA setup: PLLA is initialized to generate a 48 MHz clock. 7. Watchdog disable. 8. Initialization of UART0 (115200 bauds, 8, N, 1). 9. Initialization of the USB Device Port (only if USB activation is allowed; see Step 4.). 10. Wait for one of the following events: a. Check if USB device enumeration has occurred. b. Check if characters have been received in UART0. 11. Jump to SAM-BA Monitor (refer to 17.6 SAM-BA Monitor)

17.6 SAM-BA Monitor

Once the communication interface is identified, the monitor runs in an infinite loop, waiting for different commands, as shown in the following table. Table 17-2. Commands Available through the SAM-BA Boot Command Action Arguments Example N Set Normal mode No argument N# T Set Terminal mode No argument T# O Write a byte Address, Value# O200001,CA# o Read a byte Address,# o200001,# H Write a half word Address, Value# H200002,CAFE# h Read a half word Address,# h200002,# W Write a word Address, Value# W200000,CAFEDECA# w Read a word Address,# w200000,# S Send a file Address,# S200000,# R Receive a file Address, NbOfBytes# R200000,1234# G Go Address# G200200# V Display version No argument V# SAMV71Q21RT SAM-BA Boot Program © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 67

Mode commands: – Normal mode configures SAM-BA Monitor to send/receive data in binary format – Terminal mode configures SAM-BA Monitor to send/receive data in ASCII format
Write commands: Write a byte (O), a halfword (H) or a word (W) to the target – Address: Address in hexadecimal – Value: Byte, halfword or word to write in hexadecimal
Read commands: Read a byte (o), a halfword (h) or a word (w) from the target – Address: Address in hexadecimal – Output: The byte, halfword or word read in hexadecimal
Send a file (S): Send a file to a specified address – Address: Address in hexadecimal Note: There is a timeout on this command which is reached when the prompt ‘>’ appears before the end of the command execution.
Receive a file (R): Receive data into a file from a specified address – Address: Address in hexadecimal – NbOfBytes: Number of bytes in hexadecimal to receive
Go (G): Jump to a specified address and execute the code – Address: Address to jump in hexadecimal
Get Version (V): Return the SAM-BA boot version Note: In Terminal mode, when the requested command is performed, SAM-BA Monitor adds the following prompt sequence to its answer: <LF>+<CR>+'>'.

17.6.1 UART0 Serial Port

Communication is performed through the UART0 initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be smaller than the SRAM size because the Xmodem protocol requires some SRAM memory to work. Refer to the "Hardware and Software Constraints" section.

17.6.2 Xmodem Protocol

The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to guarantee detection of a maximum bit error. The Xmodem protocol with CRC is accurate if both sender and receiver report successful transmission. Each block of the transfer has the following format: <SOH><blk #><255-blk #><--128 data bytes--><checksum> in which:

<SOH> = 01 hex
<blk #> = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01)
<255-blk #> = 1’s complement of the blk#.
<checksum> = 2 bytes CRC16 The figure below shows a transmission using this protocol. SAMV71Q21RT SAM-BA Boot Program © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 68

Figure 17-2. Xmodem Transfer Example Host Device SOH 01 FE Data[128] CRC CRC C ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK

17.6.3 USB Device Port

The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows®, beginning with Windows 98SE. The CDC document, available at www.usb.org, describes a way to implement devices such as ISDN modems and virtual COM ports. The Vendor ID (VID) is the Atmel vendor ID 0x03EB. The product ID (PID) is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. For more details on VID/PID for end product/systems, refer to the Vendor ID form available from the USB Implementers Forum found at http://www.usb.org/. WARNINGUnauthorized use of assigned or unassigned USB Vendor ID Numbers and associated Product ID Numbers is strictly prohibited.

17.6.3.1 Enumeration Process

The USB protocol is a master/slave protocol. This is the host that starts the enumeration sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. Table 17-3. Handled Standard Requests Request Definition GET_DESCRIPTOR Returns the current device configuration value. SET_ADDRESS Sets the device address for all future device access. SET_CONFIGURATION Sets the device configuration. GET_CONFIGURATION Returns the current device configuration value. GET_STATUS Returns status for the specified recipient. SET_FEATURE Set or Enable a specific feature. CLEAR_FEATURE Clear or Disable a specific feature. The device also handles some class requests defined in the CDC class. SAMV71Q21RT SAM-BA Boot Program © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 69

Table 17-4. Handled Class Requests Request Definition SET_LINE_CODING Configures DTE rate, stop bits, parity and number of character bits. GET_LINE_CODING Requests current DTE rate, stop bits, parity and number of character bits. SET_CONTROL_LINE_STATE RS-232 signal used to tell the DCE device the DTE device is now present. Unhandled requests are STALLed.

17.6.3.2 Communication Endpoints

There are two communication endpoints. Endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-byte Bulk OUT endpoint. Endpoint 2 is a 64-byte Bulk IN endpoint. SAM-BA Boot commands are sent by the host through endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response.

17.6.4 In Application Programming (IAP) Feature

The IAP feature is a function located in ROM that can be called by any software application. When called, this function sends the desired FLASH command to the EEFC and waits for the Flash to be ready (looping while the FRDY bit is not set in the MC_FSR register). Since this function is executed from ROM, this allows Flash programming (such as sector write) to be done by code running in Flash. The IAP function entry point is retrieved by reading the NMI vector in ROM (0x00800008). This function takes two arguments as parameters:

the index of the Flash bank to be programmed: 0 for EEFC0, 1 for EEFC1. For devices with only one bank, this parameter has no effect and can be either 0 or 1, only EEFC0 will be accessed.
the command to be sent to the EEFC Command register. This function returns the value of the EEFC_FSR register. An example of IAP software code follows: // Example: How to write data in page 200 of the flash memory using ROM IAP function flash_page_num = 200 flash_cmd = 0 flash_status = 0 eefc_index = 0 (0 for EEFC0, 1 for EEFC1) // Initialize the function pointer (retrieve function address from NMI vector)*/ iap_function_address = 0x00800008 // Fill the Flash page buffer at address 200 with the data to be written for i=0, i < page_size, i++ do flash_sector_200_address[i] = your_data[i] // Prepare the command to be sent to the EEFC Command register: key, page number and write command flash_cmd = (0x5A << 24) | (flash_page_num << 8) | flash_write_command; // Call the IAP function with the right parameters and retrieve the status in flash_status after completion flash_status = iap_function (eefc_index, flash_cmd); SAMV71Q21RT SAM-BA Boot Program © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 70

Fast Flash Programming Interface (FFPI)

18.1 Description

The Fast Flash Programming Interface (FFPI) provides parallel high-volume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is considered to be a standard EEPROM. Additionally, the parallel protocol offers an optimized access to all the embedded Flash functionalities. Although the Fast Flash Programming mode is a dedicated mode for high volume programming, this mode is not designed for in-situ programming.

18.2 Embedded Characteristics

Programming Mode for High-volume Flash Programming Using Gang Programmer – Offers Read and Write Access to the Flash Memory Plane – Enables Control of Lock Bits and General-purpose NVM Bits – Enables Security Bit Activation – Disabled Once Security Bit is Set
Parallel Fast Flash Programming Interface – Provides a 16-bit Parallel Interface to Program the Embedded Flash – Full Handshake Protocol

18.3 Parallel Fast Flash Programming

18.3.1 Device Configuration

In Fast Flash Programming mode, the device is in a specific test mode. Only a certain set of pins is significant. The rest of the PIOs are used as inputs with a pullup. The crystal oscillator is in Bypass mode. Other pins must be left unconnected. Figure 18-1. 16-bit Parallel Programming Interface NCMD PGMNCMD RDY PGMRDY NOE PGMNOE NVALID PGMNVALID MODE[3:0] PGMM[3:0] DATA[15:0] PGMD[15:0] XIN TSTVDDIO PGMEN0 PGMEN1 External Clock VDDIO VDDCORE VDDIO VDDPLL GND VDDIO Table 18-1. Signal Description List Signal Name Function Type Active Level Comments Power SAMV71Q21RT Fast Flash Programming Interface (FFPI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 71

Signal Name Function Type Active Level Comments VDDIO I/O Lines Power Supply Power – – VDDCORE Core Power Supply Power – – VDDPLL PLL Power Supply Power – – GND Ground Ground – – Clocks XIN Main Clock Input Input – – Test TST Test Mode Select Input High Must be connected to VDDIO PGMEN0 Test Mode Select Input Low Must be connected to GND PGMEN1 Test Mode Select Input High Must be connected to VDDIO PIO PGMNCMD Valid command available Input Low Pulled-up input at reset PGMRDY 0: Device is busy 1: Device is ready for a new command Output High Pulled-up input at reset PGMNOE Output Enable (active high) Input Low Pulled-up input at reset PGMNVALID 0: DATA[15:0] is in input mode 1: DATA[15:0] is in output mode Output Low Pulled-up input at reset PGMM[3:0] Specifies DATA type (see Table 18-2) Input – Pulled-up input at reset PGMD[15:0] Bidirectional data bus Input/Output – Pulled-up input at reset

18.3.2 Signal Names

Depending on the MODE settings, DATA is latched in different internal registers. Table 18-2. Mode Coding MODE[3:0] Symbol Data

0000 CMDE Command Register

0001 ADDR0 Address Register LSBs

0010 ADDR1 –

0011 ADDR2 –

0100 ADDR3 Address Register MSBs

0101 DATA Data Register

When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] signals) is stored in the command register. Table 18-3. Command Bit Coding DATA[15:0] Symbol Command Executed 0x0011 READ Read Flash SAMV71Q21RT Fast Flash Programming Interface (FFPI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 72

DATA[15:0] Symbol Command Executed 0x0012 WP Write Page Flash 0x0022 WPL Write Page and Lock Flash 0x0032 EWP Erase Page and Write Page 0x0042 EWPL Erase Page and Write Page then Lock 0x0013 EA Erase All 0x0014 SLB Set Lock Bit 0x0024 CLB Clear Lock Bit 0x0015 GLB Get Lock Bit 0x0034 SGPB Set General Purpose NVM bit 0x0044 CGPB Clear General Purpose NVM bit 0x0025 GGPB Get General Purpose NVM bit 0x0054 SSE Set Security Bit 0x0035 GSE Get Security Bit 0x001F WRAM Write Memory 0x001E GVE Get Version

18.3.3 Entering Parallel Programming Mode

The following algorithm puts the device in Parallel Programming mode: 1. Apply the supplies as described in table Signal Description List. 2. If an external clock is available, apply it to XIN within the VDDCORE POR reset time-out period, as defined in the section “Electrical Characteristics”. 3. Wait for the end of this reset period. 4. Start a read or write handshaking.

18.3.4 Programmer Handshaking

A handshake is defined for read and write operations. When the device is ready to start a new operation (RDY signal set), the programmer starts the handshake by clearing the NCMD signal. The handshaking is completed once the NCMD signal is high and RDY is high.

18.3.4.1 Write Handshaking

For details on the write handshaking sequence, refer to the following figure and table. SAMV71Q21RT Fast Flash Programming Interface (FFPI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 73

Figure 18-2. Parallel Programming Timing, Write Sequence NCMD RDY NOE NVALID DATA[15:0] M ODE[3:0] Table 18-4. Write Handshake Step Programmer Action Device Action Data I/O

1 Sets MODE and DATA signals Waits for NCMD low Input

2 Clears NCMD signal Latches MODE and DATA Input

3 Waits for RDY low Clears RDY signal Input

4 Releases MODE and DATA signals Executes command and polls NCMD high Input

5 Sets NCMD signal Executes command and polls NCMD high Input

6 Waits for RDY high Sets RDY Input

18.3.4.2 Read Handshaking

For details on the read handshaking sequence, refer to the following figure and table. Figure 18-3. Parallel Programming Timing, Read Sequence NCMD RDY NOE NVALID DATA[15:0] M ODE[3:0] ADDR Adress IN Z Data OUT X IN Table 18-5. Read Handshake Step Programmer Action Device Action DATA I/O

2 Clears NCMD signal Latch MODE and DATA Input

Step Programmer Action Device Action DATA I/O

4 Sets DATA signal in tristate Waits for NOE Low Input

5 Clears NOE signal – Tristate

6 Waits for NVALID low Sets DATA bus in output mode and outputs the flash contents. Output 7 – Clears NVALID signal Output

8 Reads value on DATA Bus Waits for NOE high Output

9 Sets NOE signal – Output

10 Waits for NVALID high Sets DATA bus in input mode X

11 Sets DATA in output mode Sets NVALID signal Input

12 Sets NCMD signal Waits for NCMD high Input

13 Waits for RDY high Sets RDY signal Input

18.3.5 Device Operations

Several commands on the Flash memory are available. These commands are summarized in table Command Bit Coding. Each command is driven by the programmer through the parallel interface running several read/write handshaking sequences. When a new command is executed, the previous one is automatically achieved. Thus, chaining a read command after a write automatically flushes the load buffer in the Flash.

18.3.5.1 Flash Read Command

This command is used to read the contents of the Flash memory. The read command can start at any valid address in the memory plane and is optimized for consecutive reads. Read handshaking can be chained; an internal address buffer is automatically increased. Table 18-6. Read Command Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE READ

2 Write handshaking ADDR0 Memory Address LSB

3 Write handshaking ADDR1 Memory Address

4 Read handshaking DATA *Memory Address++

5 Read handshaking DATA *Memory Address++

n Write handshaking ADDR0 Memory Address LSB n+1 Write handshaking ADDR1 Memory Address n+2 Read handshaking DATA *Memory Address++ n+3 Read handshaking DATA *Memory Address++

18.3.5.2 Flash Write Command

This command is used to write the Flash contents. The Flash memory plane is organized into several pages. Data to be written are stored in a load buffer that corresponds to a Flash memory page. The load buffer is automatically flushed to the Flash: SAMV71Q21RT Fast Flash Programming Interface (FFPI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 75

before access to any page other than the current one
when a new command is validated (MODE = CMDE) The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 18-7. Write Command Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE WP or WPL or EWP or EWPL

4 Write handshaking DATA *Memory Address++

5 Write handshaking DATA *Memory Address++

n Write handshaking ADDR0 Memory Address LSB n+1 Write handshaking ADDR1 Memory Address n+2 Write handshaking DATA *Memory Address++ n+3 Write handshaking DATA *Memory Address++ The Flash command Write Page and Lock (WPL) is equivalent to the Flash Write Command. However, the lock bit is automatically set at the end of the Flash write operation. As a lock region is composed of several pages, the programmer writes to the first pages of the lock region using Flash write commands and writes to the last page of the lock region using a Flash write and lock command. The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command. However, before programming the load buffer, the page is erased. The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL commands.

18.3.5.3 Flash Full Erase Command

This command is used to erase the Flash memory planes. All lock regions must be unlocked before the Full Erase command by using the CLB command. Otherwise, the erase command is aborted and no page is erased. Table 18-8. Full Erase Command Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE EA

2 Write handshaking DATA 0

18.3.5.4 Flash Lock Commands

Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command (SLB). With this command, several lock bits can be activated. A Bit Mask is provided as argument to the command. When bit 0 of the bit mask is set, then the first lock bit is activated. In the same way, the Clear Lock command (CLB) is used to clear lock bits. Table 18-9. Set and Clear Lock Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE SLB or CLB

Step Handshake Sequence MODE[3:0] DATA[15:0]

2 Write handshaking DATA Bit Mask

Lock bits can be read using Get Lock Bit command (GLB). The nth lock bit is active when the bit n of the bit mask is set. Table 18-10. Get Lock Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE GLB

2 Read handshaking DATA Lock Bit Mask Status

0 = Lock bit is cleared 1 = Lock bit is set

18.3.5.5 Flash General-purpose NVM Commands

General-purpose NVM bits (GP NVM bits) can be set using the Set GPNVM command (SGPB). This command also activates GP NVM bits. A bit mask is provided as argument to the command. When bit 0 of the bit mask is set, then the first GP NVM bit is activated. In the same way, the Clear GPNVM command (CGPB) is used to clear general-purpose NVM bits. The general- purpose NVM bit is deactivated when the corresponding bit in the pattern value is set to 1. Table 18-11. Set/Clear GP NVM Command Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE SGPB or CGPB

2 Write handshaking DATA GP NVM bit pattern value

General-purpose NVM bits can be read using the Get GPNVM Bit command (GGPB). The nth GP NVM bit is active when bit n of the bit mask is set. Table 18-12. Get GP NVM Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE GGPB

2 Read handshaking DATA GP NVM Bit Mask Status

0 = GP NVM bit is cleared 1 = GP NVM bit is set

18.3.5.6 Flash Security Bit Command

A security bit can be set using the Set Security Bit command (SSE). Once the security bit is active, the Fast Flash programming is disabled. No other command can be run. An event on the Erase signal can erase the security bit once the contents of the Flash have been erased. Table 18-13. Set Security Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE SSE

Once the security bit is set, it is not possible to access FFPI. The only way to erase the security bit is to erase the Flash. SAMV71Q21RT Fast Flash Programming Interface (FFPI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 77

To erase the Flash, perform the following steps: 1. Power off the chip. 2. Power on the chip with TST = 0. 3. Assert the ERASE signal for at least the ERASE pin assertion time as defined in the section “Electrical Characteristics”. 4. Power off the chip. Return to FFPI mode to check that the Flash is erased.

18.3.5.7 Memory Write Command

This command is used to perform a write access to any memory location. The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 18-14. Write Command Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE WRAM

n Write handshaking ADDR0 Memory Address LSB n+1 Write handshaking ADDR1 Memory Address n+2 Write handshaking DATA *Memory Address++ n+3 Write handshaking DATA *Memory Address++

18.3.5.8 Get Version Command

The Get Version (GVE) command retrieves the version of the FFPI interface. Table 18-15. Get Version Command Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE GVE

2 Read handshaking DATA Version

Bus Matrix (MATRIX)

19.1 Description

The Bus Matrix (MATRIX) implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The MATRIX interconnects 13 AHB masters to 9 AHB slaves. The normal latency to connect a master to a slave is one cycle. The exception is the default master of the accessed slave which is connected directly (zero cycle latency). The MATRIX user interface is compliant with ARM Advanced Peripheral Bus.

19.2 Embedded Characteristics

13 Masters
9 Slaves
One Decoder for Each Master
Several Possible Boot Memories for Each Master before Remap
One Remap Function for Each Master
Support for Long Bursts of 32, 64, 128 and up to the 256-beat Word Burst AHB Limit
Enhanced Programmable Mixed Arbitration for Each Slave – Round-Robin – Fixed Priority
Programmable Default Master for Each Slave – No Default Master – Last Accessed Default Master – Fixed Default Master
Deterministic Maximum Access Latency for Masters
Zero or One Cycle Arbitration Latency for the First Access of a Burst
Bus Lock Forwarding to Slaves
Master Number Forwarding to Slaves
Configurable Automatic Clock-off Mode for Power Reduction
One Special Function Register for Each Slave (not dedicated)
Register Write Protection

19.2.1 Matrix Masters

The MATRIX manages the masters listed in he following table. Each master can perform an access to an available slave concurrently with other masters. lists the available masters. Each master has its own specifically-defined decoder. To simplify addressing, all the masters have the same decodings. Table 19-1. Bus Matrix Masters Master Index Name

0 Cortex-M7

1 Cortex-M7

2 Cortex-M7 Peripheral Port

3 Integrated Check Monitor

6 ISI DMA

7 Media LB

8 USB DMA

9 Ethernet MAC DMA

10 CAN0 DMA

11 CAN1 DMA

12 Cortex-M7

Note: Master 12 (Cortex-M7) is only on revision B.

19.2.2 Matrix Slaves

The MATRIX manages the slaves listed in the following table. Each slave has its own arbiter, providing a different arbitration per slave. Table 19-2. Bus Matrix Slaves Slave Index Name

0 Internal SRAM

1 Internal SRAM

2 Internal ROM

3 Internal Flash

4 USB High Speed Dual Port RAM (DPR)

5 External Bus Interface

6 QSPI

7 Peripheral Bridge

8 AHB Slave

19.2.3 Master to Slave Access

The following table provides valid paths for master to slave accesses. The paths shown as “-” are forbidden or not wired. Table 19-3. Master to Slave Access Masters 0 1 2 3 4 5 6 7 8 9 10 11 12 Slaves Cortex- Cortex- Cortex-M7 Peripheral Port ICM Central DMA IF0 Central DMA IF1 ISI DMA MediaLB DMA USB DMA GMAC DMA CAN0 DMA CAN1 DMA Cortex-

0 Internal

1 Internal

3 Internal Flash X – – X – X – – X X – – –

Masters 0 1 2 3 4 5 6 7 8 9 10 11 12

4 USB HS

5 External Bus

– X – X X X X X X X X X –

7 Peripheral

8 Cortex-M7

(AHBS) (see Note) – – – X X – X X X X X X – Note: For the connection of the Cortex-M7 processor to the SRAM, refer to the sections “Interconnect” and “Memories”, sub-section “Embedded Memories”. Related Links

19.3 Functional Description

19.3.1 Memory Mapping

The MATRIX provides one decoder for every AHB master interface. The decoder offers each AHB master several memory mappings. Each memory area may be assigned to several slaves. Thus booting at the same address while using different AHB slaves (i.e., external RAM, internal ROM or internal Flash, etc.) is possible. The MATRIX user interface provides the Master Remap Control Register (MATRIX_MRCR) that performs remap action for every master independently.

19.3.2 Special Bus Granting Mechanism

The MATRIX provides some speculative bus granting techniques in order to anticipate access requests from masters. This technique reduces latency at the first access of a burst, or for a single transfer, as long as the slave is free from any other master access. Bus granting sets a different default master for every slave. At the end of the current access, if no other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters:

No default master
Last access master
Fixed default master To change from one type of default master to another, the MATRIX user interface provides the Slave Configuration registers, one for every slave, that set a default master for each slave. The Slave Configuration register contains the fields DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field selects the default master type (no default, last access master, fixed default master), whereas the 4-bit FIXED_DEFMSTR field selects a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Please refer to the "Bus Matrix Slave Configuration Registers" section.

19.3.2.1 No Default Master

After the end of the current access, if no other request is pending, the slave is disconnected from all masters. This configuration incurs one latency clock cycle for the first access of a burst after bus Idle. Arbitration without default master may be used for masters that perform significant bursts or several transfers with no Idle in between, or if the slave bus bandwidth is widely used by one or more masters. This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput whatever the number of requesting masters. SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 81

19.3.2.2 Last Access Master

After the end of the current access, if no other request is pending, the slave remains connected to the last master that performed an access request. This allows the MATRIX to remove the one latency cycle for the last master that accessed the slave. Other non privileged masters still get one latency clock cycle if they want to access the same slave. This technique is useful for masters that mainly perform single accesses or short bursts with some Idle cycles in between. This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput whatever is the number of requesting masters.

19.3.2.3 Fixed Default Master

At the end of the current access, if no other request is pending, the slave connects to its fixed default master. Unlike the last access master, the fixed default master does not change unless the user modifies it by software (FIXED_DEFMSTR field of the related MATRIX_SCFG). This allows the MATRIX arbiters to remove the one latency clock cycle for the fixed default master of the slave. All requests attempted by the fixed default master do not cause any arbitration latency, whereas other non-privileged masters will get one latency cycle. This technique is useful for a master that mainly performs single accesses or short bursts with Idle cycles in between. This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput, regardless of the number of requesting masters.

19.3.3 Arbitration

The MATRIX provides an arbitration technique that reduces latency when conflicting cases occur; for example. when two or more masters try to access the same slave at the same time. One arbiter per AHB slave is provided, so that each slave is arbitrated differently. The MATRIX provides the user with two arbitration types for each slave: 1. Round-robin Arbitration (default) 2. Fixed Priority Arbitration Each algorithm may be complemented by selecting a default master configuration for each slave. When re-arbitration is required, specific conditions apply. Refer to the "Arbitration Rules" section.

19.3.3.1 Arbitration Rules

Each arbiter has the ability to arbitrate between requests from two or more masters. To avoid burst breaking and to provide maximum throughput for slave interfaces, arbitration should take place during the following cycles:

Idle cycles: When a slave is not connected to any master or is connected to a master which is not currently accessing it
Single cycles: When a slave is performing a single access
End of Burst cycles: When the current cycle is the last cycle of a burst transfer. For a defined length burst, predicted end of burst matches the size of the transfer but is managed differently for undefined length burst. Refer to the "Undefined Length Burst Arbitration" section.
Slot cycle limit: When the slot cycle counter has reached the limit value indicating that the current master access is too long and must be broken. Refer to the "Slot Cycle Limit Arbitration" section.

19.3.3.1.1 Undefined Length Burst Arbitration

In order to prevent slave handling during undefined length bursts, the user can trigger the re-arbitration before the end of the incremental bursts. The re-arbitration period can be selected from the following Undefined Length Burst Type (ULBT) possibilities: 1. Unlimited: no predetermined end of burst is generated. This value enables 1-Kbyte burst lengths. 2. 1-beat bursts: predetermined end of burst is generated at each single transfer during the INCR transfer. 3. 4-beat bursts: predetermined end of burst is generated at the end of each 4-beat boundary during INCR transfer. 4. 8-beat bursts: predetermined end of burst is generated at the end of each 8-beat boundary during INCR transfer. SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 82

16-beat bursts: predetermined end of burst is generated at the end of each 16-beat boundary during INCR transfer. 6. 32-beat bursts: predetermined end of burst is generated at the end of each 32-beat boundary during INCR transfer. 7. 64-beat bursts: predetermined end of burst is generated at the end of each 64-beat boundary during INCR transfer. 8. 128-beat bursts: predetermined end of burst is generated at the end of each 128-beat boundary during INCR transfer. The use of undefined length16-beat bursts, or less, is discouraged since this decreases the overall bus bandwidth due to arbitration and slave latencies at each first access of a burst. If the master does not permanently and continuously request the same slave or has an intrinsically limited average throughput, the ULBT should be left at its default unlimited value, knowing that the AHB specification natively limits all word bursts to 256 beats and double-word bursts to 128 beats because of its 1-Kbyte address boundaries. Unless duly needed, the ULBT should be left at its default value of 0 for power saving. This selection is made through the ULBT field of the Master Configuration Registers (MATRIX_MCFG).

19.3.3.1.2 Slot Cycle Limit Arbitration

The MATRIX contains specific logic to break long accesses, such as very long bursts on a very slow slave (e.g., an external low speed memory). At each arbitration time, a counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave Configuration Register (MATRIX_SCFG) and decreased at each clock cycle. When the counter elapses, the arbiter has the ability to rearbitrate at the end of the current AHB bus access cycle. Unless a master has a very tight access latency constraint, which could lead to data overflow or underflow due to a badly undersized internal FIFO with respect to its throughput, the Slot Cycle Limit should be disabled (SLOT_CYCLE = 0) or set to its default maximum value in order not to inefficiently break long bursts performed by some bus masters. In most cases, this feature is not needed and should be disabled for power saving. WARNINGThis feature does not prevent a slave from locking its access indefinitely.

19.3.3.2 Arbitration Priority Scheme

The MATRIX arbitration scheme is organized in priority pools. Round-robin priority is used in the highest and lowest priority pools, whereas fixed level priority is used between priority pools and in the intermediate priority pools. For each slave, each master is assigned to one of the slave priority pools through the priority registers for slaves (MxPR fields of MATRIX_PRAS and MATRIX_PRBS). When evaluating master requests, this programmed priority level always takes precedence. After reset, all the masters except those of the Cortex-M7 belong to the lowest priority pool (MxPR = 0) and are therefore granted bus access in a true round-robin order. The highest priority pool must be specifically reserved for masters requiring very low access latency. If more than one master belongs to this pool, they will be granted bus access in a biased round-robin manner which allows tight and deterministic maximum access latency from AHB bus requests. In the worst case, any currently occurring high-priority master request will be granted after the current bus master access has ended and other high priority pool master requests, if any, have been granted once each. The lowest priority pool shares the remaining bus bandwidth between AHB Masters. Intermediate priority pools allow fine priority tuning. Typically, a moderately latency-critical master or a bandwidth-only critical master will use such a priority level. The higher the priority level (MxPR value), the higher the master priority. All combinations of MxPR values are allowed for all masters and slaves. For example, some masters might be assigned the highest priority pool (round-robin), and remaining masters the lowest priority pool (round-robin), with no master for intermediate fix priority levels. SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 83

If more than one master requests the slave bus, regardless of the respective masters priorities, no master will be granted the slave bus for two consecutive runs. A master can only get back-to-back grants so long as it is the only requesting master.

19.3.3.2.1 Fixed Priority Arbitration

The fixed priority arbitration algorithm is the first and only arbitration algorithm applied between masters from distinct priority pools. It is also used in priority pools other than the highest and lowest priority pools (intermediate priority pools). Fixed priority arbitration is used by the MATRIX arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user. If requests from two or more masters are active at the same time, the master with the highest priority number is serviced first. If requests from two or more masters with the same priority are active at the same time, the master with the highest number is serviced first. For each slave, the priority of each master is defined in the MxPR field in the Priority Registers, MATRIX_PRAS and MATRIX_PRBS.

19.3.3.2.2 Round-Robin Arbitration

Round-robin arbitration is only used in the highest and lowest priority pools. It allows the MATRIX arbiters to properly dispatch requests from different masters to the same slave. If two or more master requests are active at the same time in the priority pool, they are serviced in a round-robin increasing master number order.

19.3.4 System I/O Configuration

The System I/O Configuration register (CCFG_SYSIO) configures I/O lines in System I/O mode (such as JTAG, ERASE, USB, etc.) or as general purpose I/O lines. Enabling or disabling the corresponding I/O lines in peripheral mode or in PIO mode (PIO_PER or PIO_PDR registers) in the PIO controller as no effect. However, the direction (input or output), pull-up, pull-down and other mode control is still managed by the PIO controller.

19.3.5 SMC NAND Flash Chip Select Configuration

The SMC Nand Flash Chip Select Configuration Register (CCFG_SMCNFCS) manages the chip select signal (NCSx) and its assignment to NAND Flash. Each NCSx may or may not be individually assigned to NAND Flash. When the NCSx is assigned to NAND Flash, the signals NANDOE and NANDWE are used for the NCSx signals selected.

19.3.6 Configuration of Automatic Clock-off Mode

To reduce power consumption, MATRIX, Bridge and EFC automatic clock gating can be enabled by writing a ‘1’ to bits MATCKG, BRIDCKG and EFCCKG, respectively, in the Dynamic Clock Gating register (CCFG_DYNCKG).

19.3.7 Register Write Protection

To prevent any single software error from corrupting MATRIX behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the Write Protection Mode Register (MATRIX_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the Write Protection Status Register (MATRIX_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS flag is reset by writing the Bus Matrix Write Protect Mode Register (MATRIX_WPMR) with the appropriate access key WPKEY. The following registers can be write-protected:

Bus Matrix Master Configuration Registers
Bus Matrix Slave Configuration Registers
Bus Matrix Priority Registers A For Slaves
Bus Matrix Priority Registers B For Slaves
Bus Matrix Master Remap Control Register SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 84

19.4 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 MATRIX_MCFG0 7:0 ULBT[2:0] 15:8 23:16 31:24 ... 0x30 MATRIX_MCFG12 7:0 ULBT[2:0] 15:8 23:16 31:24 0x34 ... 0x3F Reserved 0x40 MATRIX_SCFG0 7:0 SLOT_CYCLE[6:0] 15:8 SLOT_CYCLE[8:7] 23:16 FIXED_DEFMSTR[3:0] DEFMSTR_TYPE[1:0] 31:24 0x44 MATRIX_SCFG1 7:0 SLOT_CYCLE[6:0] 15:8 SLOT_CYCLE[8:7] 23:16 FIXED_DEFMSTR[3:0] DEFMSTR_TYPE[1:0] 31:24 0x48 MATRIX_SCFG2 7:0 SLOT_CYCLE[6:0] 15:8 SLOT_CYCLE[8:7] 23:16 FIXED_DEFMSTR[3:0] DEFMSTR_TYPE[1:0] 31:24 0x4C MATRIX_SCFG3 7:0 SLOT_CYCLE[6:0] 15:8 SLOT_CYCLE[8:7] 23:16 FIXED_DEFMSTR[3:0] DEFMSTR_TYPE[1:0] 31:24 0x50 MATRIX_SCFG4 7:0 SLOT_CYCLE[6:0] 15:8 SLOT_CYCLE[8:7] 23:16 FIXED_DEFMSTR[3:0] DEFMSTR_TYPE[1:0] 31:24 0x54 MATRIX_SCFG5 7:0 SLOT_CYCLE[6:0] 15:8 SLOT_CYCLE[8:7] 23:16 FIXED_DEFMSTR[3:0] DEFMSTR_TYPE[1:0] 31:24 0x58 MATRIX_SCFG6 7:0 SLOT_CYCLE[6:0] 15:8 SLOT_CYCLE[8:7] 23:16 FIXED_DEFMSTR[3:0] DEFMSTR_TYPE[1:0] 31:24 0x5C MATRIX_SCFG7 7:0 SLOT_CYCLE[6:0] 15:8 SLOT_CYCLE[8:7] 23:16 FIXED_DEFMSTR[3:0] DEFMSTR_TYPE[1:0] 31:24 0x60 MATRIX_SCFG8 7:0 SLOT_CYCLE[6:0] 15:8 SLOT_CYCLE[8:7] 23:16 FIXED_DEFMSTR[3:0] DEFMSTR_TYPE[1:0] 31:24 0x64 ... 0x7F Reserved 0x80 MATRIX_PRAS0 7:0 M1PR[1:0] M0PR[1:0] 15:8 M3PR[1:0] M2PR[1:0] SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 85

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x84 MATRIX_PRBS0 7:0 M9PR[1:0] M8PR[1:0] 23:16 M12PR[1:0] 31:24 0x88 MATRIX_PRAS1 7:0 M1PR[1:0] M0PR[1:0] 15:8 M3PR[1:0] M2PR[1:0] 0x8C MATRIX_PRBS1 7:0 M9PR[1:0] M8PR[1:0] 23:16 M12PR[1:0] 31:24 0x90 MATRIX_PRAS2 7:0 M1PR[1:0] M0PR[1:0] 15:8 M3PR[1:0] M2PR[1:0] 0x94 MATRIX_PRBS2 7:0 M9PR[1:0] M8PR[1:0] 23:16 M12PR[1:0] 31:24 0x98 MATRIX_PRAS3 7:0 M1PR[1:0] M0PR[1:0] 15:8 M3PR[1:0] M2PR[1:0] 0x9C MATRIX_PRBS3 7:0 M9PR[1:0] M8PR[1:0] 23:16 M12PR[1:0] 31:24 0xA0 MATRIX_PRAS4 7:0 M1PR[1:0] M0PR[1:0] 15:8 M3PR[1:0] M2PR[1:0] 0xA4 MATRIX_PRBS4 7:0 M9PR[1:0] M8PR[1:0] 23:16 M12PR[1:0] 31:24 0xA8 MATRIX_PRAS5 7:0 M1PR[1:0] M0PR[1:0] 15:8 M3PR[1:0] M2PR[1:0] 0xAC MATRIX_PRBS5 7:0 M9PR[1:0] M8PR[1:0] 23:16 M12PR[1:0] 31:24 0xB0 MATRIX_PRAS6 7:0 M1PR[1:0] M0PR[1:0] 15:8 M3PR[1:0] M2PR[1:0] 0xB4 MATRIX_PRBS6 7:0 M9PR[1:0] M8PR[1:0] 23:16 M12PR[1:0] 31:24 0xB8 MATRIX_PRAS7 7:0 M1PR[1:0] M0PR[1:0] 15:8 M3PR[1:0] M2PR[1:0] SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 86

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0xBC MATRIX_PRBS7 7:0 M9PR[1:0] M8PR[1:0] 23:16 M12PR[1:0] 31:24 0xC0 MATRIX_PRAS8 7:0 M1PR[1:0] M0PR[1:0] 15:8 M3PR[1:0] M2PR[1:0] 0xC4 MATRIX_PRBS8 7:0 M9PR[1:0] M8PR[1:0] 23:16 M12PR[1:0] 31:24 0xC8 ... 0xFF Reserved 0x0100 MATRIX_MRCR 7:0 RCB7 RCB6 RCB5 RCB4 RCB3 RCB2 RCB1 RCB0 15:8 RCB12 RCB11 RCB10 RCB9 RCB8 23:16 31:24 0x0104 ... 0x010F Reserved 0x0110 CCFG_CAN0 7:0 Reserved[7:0] 15:8 Reserved[8] 23:16 CAN0DMABA[7:0] 31:24 CAN0DMABA[15:8] 0x0114 CCFG_SYSIO 7:0 SYSIO7 SYSIO6 SYSIO5 SYSIO4 15:8 SYSIO12 23:16 CAN1DMABA[7:0] 31:24 CAN1DMABA[15:8] 0x0118 CCFG_PCCR 7:0 15:8 23:16 I2SC1CC I2SC0CC TC0CC 31:24 0x011C CCFG_DYNCKG 7:0 EFCCKG BRIDCKG MATCKG 15:8 23:16 31:24 0x0120 ... 0x0123 Reserved 0x0124 CCFG_SMCNFCS 7:0 SDRAMEN SMC_NFCS3 SMC_NFCS2 SMC_NFCS1 SMC_NFCS0 15:8 23:16 31:24 0x0128 ... 0x01E3 Reserved 0x01E4 MATRIX_WPMR 7:0 WPEN 15:8 WPKEY[7:0] 23:16 WPKEY[15:8] 31:24 WPKEY[23:16] 0x01E8 MATRIX_WPSR 7:0 WPVS 15:8 WPVSRC[7:0] 23:16 WPVSRC[15:8] 31:24 SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 87

19.4.1 Bus Matrix Master Configuration Registers

Name: MATRIX_MCFGx Offset: 0x00 + x*0x04 [x=0..12] Reset: 0x00000000 Property: Read/Write This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ULBT[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 2:0 – ULBT[2:0] Undefined Length Burst Type Value Name Description

0 UNLTD_LENGTH Unlimited Length Burst—No predicted end of burst is generated, therefore INCR

bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts. This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

1 SINGLE_ACCESS Single Access—The undefined length burst is treated as a succession of single

accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 2 4BEAT_BURST 4-beat Burst—The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 3 8BEAT_BURST 8-beat Burst—The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 4 16BEAT_BURST 16-beat Burst—The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 5 32BEAT_BURST 32-beat Burst —The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 6 64BEAT_BURST 64-beat Burst—The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 88

7 128BEAT_BURST 128-beat Burst—The undefined length burst or bursts sequence is split into 128- beat bursts or less, allowing re-arbitration every 128 beats. Note: Unless duly needed, the ULBT should be left at its default 0 value for power saving. SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 89

19.4.2 Bus Matrix Slave Configuration Registers

Name: MATRIX_SCFGx Offset: 0x40 + x*0x04 [x=0..8] Reset: 0x000001FF Property: Read/Write This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 FIXED_DEFMSTR[3:0] DEFMSTR_TYPE[1:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SLOT_CYCLE[8:7] Access R/W R/W Reset 0 1 Bit 7 6 5 4 3 2 1 0 SLOT_CYCLE[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 Bits 21:18 – FIXED_DEFMSTR[3:0] Fixed Default Master Number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0. Bits 17:16 – DEFMSTR_TYPE[1:0] Default Master Type Value Name Description

0 NONE No Default Master—At the end of the current slave access, if no other master request is

pending, the slave is disconnected from all masters. This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

1 LAST Last Default Master—At the end of the current slave access, if no other master request is

pending, the slave stays connected to the last master having accessed it. This results in not having one clock cycle latency when the last master tries to access the slave again.

2 FIXED Fixed Default Master—At the end of the current slave access, if no other master request

is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field. This results in not having one clock cycle latency when the fixed master tries to access the slave again. Bits 9:1 – SLOT_CYCLE[8:0] Maximum Bus Grant Duration for Masters When SLOT_CYCLE AHB clock cycles have elapsed since the last arbitration, a new arbitration takes place to let another master access this slave. If another master is requesting the slave bus, then the current master burst is broken. If SLOT_CYCLE = 0, the slot cycle limit feature is disabled and bursts always complete unless broken according to the ULBT. SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 90

This limit has been placed in order to enforce arbitration so as to meet potential latency constraints of masters waiting for slave access. This limit must not be too small. Unreasonably small values break every burst and the MATRIX arbitrates without performing any data transfer. The default maximum value is usually an optimal conservative choice. In most cases, this feature is not needed and should be disabled for power saving. See “Slot Cycle Limit Arbitration” for details. SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 91

19.4.3 Bus Matrix Priority Registers A For Slaves

Name: MATRIX_PRASx Offset: 0x80 + x*0x08 [x=0..8] Reset: 0x00000222 Property: Read/Write This register can only be written if the WPE bit is cleared in the Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 M7PR[1:0] M6PR[1:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 23 22 21 20 19 18 17 16 M5PR[1:0] M4PR[1:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 M3PR[1:0] M2PR[1:0] Access R/W R/W R/W R/W Reset 0 0 1 0 Bit 7 6 5 4 3 2 1 0 M1PR[1:0] M0PR[1:0] Access R/W R/W R/W R/W Reset 1 0 1 0 Bits 0:1, 4:5, 8:9, 12:13, 16:17, 20:21, 24:25, 28:29 – MxPR Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. All the masters programmed with the same MxPR value for the slave make up a priority pool. Round-robin arbitration is used in the lowest (MxPR = 0) and highest (MxPR = 3) priority pools. Fixed priority is used in intermediate priority pools (MxPR = 1) and (MxPR = 2). See “Arbitration Priority Scheme” for details. SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 92

19.4.4 Bus Matrix Priority Registers B For Slaves

Name: MATRIX_PRBSx Offset: 0x84 + x*0x08 [x=0..8] Reset: 0x00000222 Property: Read/Write This register can only be written if the WPE bit is cleared in the Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 M12PR[1:0] Access R/W R/W Reset 0 0 Bit 15 14 13 12 11 10 9 8 M11PR[1:0] M10PR[1:0] Access R/W R/W R/W R/W Reset 0 0 1 0 Bit 7 6 5 4 3 2 1 0 M9PR[1:0] M8PR[1:0] Access R/W R/W R/W R/W Reset 1 0 1 0 Bits 0:1, 4:5, 8:9, 12:13, 16:17 – MxPR Master 8 Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. All the masters programmed with the same MxPR value for the slave make up a priority pool. Round-robin arbitration is used in the lowest (MxPR = 0) and highest (MxPR = 3) priority pools. Fixed priority is used in intermediate priority pools (MxPR = 1) and (MxPR = 2). See “Arbitration Priority Scheme” for details. SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 93

19.4.5 Bus Matrix Master Remap Control Register

Name: MATRIX_MRCR Offset: 0x0100 Reset: 0x00000000 Property: Read/Write This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 RCB12 RCB11 RCB10 RCB9 RCB8 Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RCB7 RCB6 RCB5 RCB4 RCB3 RCB2 RCB1 RCB0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 – RCBx Remap Command Bit for Master x Value Description 0 Disables remapped address decoding for the selected Master. 1 Enables remapped address decoding for the selected Master. SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 94

19.4.6 CAN0 Configuration Register

Name: CCFG_CAN0 Offset: 0x0110 Reset: 0x2040019D Property: Read/Write Bit 31 30 29 28 27 26 25 24 CAN0DMABA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 1 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CAN0DMABA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Reserved[8] Access R/W Reset 1 Bit 7 6 5 4 3 2 1 0 Reserved[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 0 0 1 1 1 0 1 Bits 31:16 – CAN0DMABA[15:0] CAN0 DMA Base Address Gives the 16-bit MSB of the CAN0 DMA base address. The 16-bit LSB must be programmed into CAN0 user interface. Default address is 0x20400000. Bits 8:0 – Reserved[8:0] Do not change the reset value SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 95

19.4.7 System I/O and CAN1 Configuration Register

Name: CCFG_SYSIO Offset: 0x0114 Reset: 0x20400000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 CAN1DMABA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 1 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CAN1DMABA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SYSIO12 Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 SYSIO7 SYSIO6 SYSIO5 SYSIO4 Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 31:16 – CAN1DMABA[15:0] CAN1 DMA Base Address Give the 16-bit MSB of the CAN1 DMA base address. The 16-bit LSB must be programmed into CAN1 User interface. Default address is 0x20400000. Bit 12 – SYSIO12 PB12 or ERASE Assignment Value Description 0 ERASE function selected. 1 PB12 function selected. Bit 7 – SYSIO7 PB7 or TCK/SWCLK Assignment Value Description 0 TCK/SWCLK function selected. 1 PB7 function selected. Bit 6 – SYSIO6 PB6 or TMS/SWDIO Assignment Value Description 0 TMS/SWDIO function selected. 1 PB6 function selected. Bit 5 – SYSIO5 PB5 or TDO/TRACESWO Assignment Value Description 0 TDO/TRACESWO function selected. 1 PB5 function selected. Bit 4 – SYSIO4 PB4 or TDI Assignment Value Description 0 TDI function selected. 1 PB4 function selected. SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 96

19.4.8 Peripheral Clock Configuration Register

Name: CCFG_PCCR Offset: 0x0118 Reset: 0x00022224 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 I2SC1CC I2SC0CC TC0CC Access R/W R/W R/W Reset 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 Access Reset Bit 22 – I2SC1CC I2SC1 Clock Configuration Value Description 0 Peripheral clock of I2SC1 is used. 1 GCLK is used. Bit 21 – I2SC0CC I2SC0 Clock Configuration Value Description 0 Peripheral clock of I2SC0 is used. 1 GCLK is used. Bit 20 – TC0CC TC0 Clock Configuration Value Description 0 PCK6 is used (default). 1 PCK7 is used. SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 97

19.4.9 Dynamic Clock Gating Register

Name: CCFG_DYNCKG Offset: 0x011C Reset: 0 Property: Read/Write Note: Clearing this register optimizes the power consumption of the system bus circuitry. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 EFCCKG BRIDCKG MATCKG Access R/W R/W R/W Reset 0 0 0 Bit 2 – EFCCKG EFC Dynamic Clock Gating Enable Value Description 0 EFC dynamic clock gating enabled. The Embedded Flash Controller circuitry is driven by the clock only when an access to the Flash memory is being performed. Power consumption is optimized. 1 EFC dynamic clock gating disabled. The Embedded Flash Controller is always driven by the clock in Active mode. Bit 1 – BRIDCKG Bridge Dynamic Clock Gating Enable Value Description 0 Bridge dynamic clock gating enabled. The peripheral bridge circuitry is driven by the clock only when a transfer to/from any peripheral located on the APB bus is being performed. Power consumption is optimized. 1 Bridge dynamic clock gating disabled. The peripheral bridge circuitry is always driven by the clock in Active mode. Bit 0 – MATCKG MATRIX Dynamic Clock Gating Value Description 0 MATRIX dynamic clock gating enabled. The MATRIX circuitry is driven by the clock only when a transfer to a peripheral is being performed. Power consumption is optimized. 1 MATRIX dynamic clock gating disabled. The MATRIX circuitry is always driven by the clock in Active mode. SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 98

19.4.10 SMC NAND Flash Chip Select Configuration Register

Name: CCFG_SMCNFCS Offset: 0x0124 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 SDRAMEN SMC_NFCS3 SMC_NFCS2 SMC_NFCS1 SMC_NFCS0 Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 4 – SDRAMEN SDRAM Enable WARNINGThis bit must not be used if SMC_NFCS1 is set. WARNING: This must not be used if SMC_NFCS1 is set. Value Description 0 NCS1 is not assigned to SDRAM. 1 NCS1 is assigned to SDRAM. Bit 3 – SMC_NFCS3 SMC NAND Flash Chip Select 3 Assignment Value Description 0 NCS3 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS3). 1 NCS3 is assigned to a NAND Flash (NANDOE and NANWE used for NCS3). Bit 2 – SMC_NFCS2 SMC NAND Flash Chip Select 2 Assignment Value Description 0 NCS2 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS2). 1 NCS2 is assigned to a NAND Flash (NANDOE and NANWE used for NCS2). Bit 1 – SMC_NFCS1 SMC NAND Flash Chip Select 1 Assignment WARNINGThis bit must not be used if SDRAMEN is set. SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 99

0 NCS1 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS1). 1 NCS1 is assigned to a NAND Flash (NANDOE and NANWE used for NCS1). Bit 0 – SMC_NFCS0 SMC NAND Flash Chip Select 0 Assignment Value Description 0 NCS0 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS0). 1 NCS0 is assigned to a NAND Flash (NANDOE and NANWE used for NCS0). SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 100

19.4.11 Write Protection Mode Register

Name: MATRIX_WPMR Offset: 0x01E4 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 WPKEY[23:16] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 WPKEY[15:8] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 WPKEY[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WPEN Access R/W Reset 0 Bits 31:8 – WPKEY[23:0] Write Protection Key Value Name Description 0x4D4154 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Bit 0 – WPEN Write Protection Enable Refer to the "Register Write Protection" section for the list of registers that can be write-protected. Value Description 0 Disables the write protection if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII). 1 Enables the write protection if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII). SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 101

19.4.12 Write Protection Status Register

Name: MATRIX_WPSR Offset: 0x01E8 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 WPVSRC[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 WPVSRC[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WPVS Access R Reset 0 Bits 23:8 – WPVSRC[15:0] Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. Bit 0 – WPVS Write Protection Violation Status Value Description 0 No write protection violation has occurred since the last write of the MATRIX_WPMR. 1 A write protection violation has occurred since the last write of the MATRIX_WPMR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. SAMV71Q21RT Bus Matrix (MATRIX) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 102

USB Transmitter Macrocell Interface (UTMI) Important: This module is not supported. Refer to the section Errata for more information.

20.1 Description

The USB Transmitter Macrocell Interface (UTMI) registers manage specific aspects of the integrated USB transmitter macrocell functionality not controlled in USB sections.

20.2 Embedded Characteristics

32-bit UTMI Registers Control Product-specific Behavior SAMV71Q21RT USB Transmitter Macrocell Interface (UTMI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 103

20.3 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 ... 0x0F Reserved 0x10 UTMI_OHCIICR 7:0 APPSTART ARIE RESx 15:8 23:16 UDPPUDIS 31:24 0x14 ... 0x2F Reserved 0x30 UTMI_CKTRIM 7:0 FREQ[1:0] 15:8 23:16 31:24 SAMV71Q21RT USB Transmitter Macrocell Interface (UTMI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 104

20.3.1 OHCI Interrupt Configuration Register

Name: UTMI_OHCIICR Offset: 0x10 Reset: 0x0 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 UDPPUDIS Access Reset 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 APPSTART ARIE RESx Access Reset 0 0 0 Bit 23 – UDPPUDIS USB Device Pull-up Disable Value Description 0 USB device pull-up connection is enabled. 1 USB device pull-up connection is disabled. Bit 5 – APPSTART Reserved Value Description 0 Must write 0. Bit 4 – ARIE OHCI Asynchronous Resume Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled. Bit 0 – RESx USB PORTx Reset Value Description 0 Resets USB port. 1 Usable USB port. SAMV71Q21RT USB Transmitter Macrocell Interface (UTMI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 105

20.3.2 UTMI Clock Trimming Register

Name: UTMI_CKTRIM Offset: 0x30 Reset: 0x00010000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 FREQ[1:0] Access Reset 0 0 Bits 1:0 – FREQ[1:0] UTMI Reference Clock Frequency Value Name Description

0 XTAL12 12 MHz reference clock

1 XTAL16 16 MHz reference clock

Chip Identifier (CHIPID)

21.1 Description

Chip Identifier (CHIPID) registers are used to recognize the device and its revision. These registers provide the sizes and types of the on-chip memories, as well as the set of embedded peripherals. Two CHIPID registers are embedded: Chip ID register (CHIPID_CIDR) and Chip ID Extension register (CHIPID_EXID). Both registers contain a hard-wired value that is read-only. The CHIPID_CIDR register contains the following fields:

VERSION: Identifies the revision of the silicon
EPROC: Indicates the embedded ARM processor
NVPTYP and NVPSIZ: Identify the type of embedded non-volatile memory and the size
SRAMSIZ: Indicates the size of the embedded SRAM
ARCH: Identifies the set of embedded peripherals
EXT: Shows the use of the extension identifier register The CHIPID_EXID register is device-dependent and reads ‘0’ if CHIPID_CIDR.EXT = 0.

21.2 Embedded Characteristics

Chip ID Registers – Identification of the Device Revision, Sizes of the Embedded Memories, Set of Peripherals, Embedded Processor SAMV71Q21RT Chip Identifier (CHIPID) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 107

21.3 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CHIPID_CIDR 7:0 EPROC[2:0] VERSION[4:0] 15:8 NVPSIZ2[3:0] NVPSIZ[3:0] 23:16 ARCH[3:0] SRAMSIZ[3:0] 31:24 EXT NVPTYP[2:0] ARCH[7:4] 0x04 CHIPID_EXID 7:0 EXID[7:0] 15:8 EXID[15:8] 23:16 EXID[23:16] 31:24 EXID[31:24] SAMV71Q21RT Chip Identifier (CHIPID) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 108

21.3.1 Chip ID Register

Name: CHIPID_CIDR Offset: 0x0 Reset: 0xA1220E01 Property: Read-only Values not listed for bitfields must be considered as “reserved” Bit 31 30 29 28 27 26 25 24 EXT NVPTYP[2:0] ARCH[7:4] Access R R R R R R R R Reset 1 0 1 0 0 0 0 1 Bit 23 22 21 20 19 18 17 16 ARCH[3:0] SRAMSIZ[3:0] Access R R R R R R R R Reset 0 0 1 0 0 0 1 0 Bit 15 14 13 12 11 10 9 8 NVPSIZ2[3:0] NVPSIZ[3:0] Access R R R R R R R R Reset 0 0 0 0 1 1 1 0 Bit 7 6 5 4 3 2 1 0 EPROC[2:0] VERSION[4:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 1 Bit 31 – EXT Extension Flag Value Description 0 Chip ID has a single register definition without extension. 1 An extended Chip ID exists. Bits 30:28 – NVPTYP[2:0] Non-volatile Program Memory Type Value Name Description

2 FLASH Embedded Flash Memory

Bits 27:20 – ARCH[7:0] Architecture Identifier Value Name Description

18 SAMV71 SAMV71

Bits 19:16 – SRAMSIZ[3:0] Internal SRAM Size Value Name Description 2 384K 384 Kbytes Bits 15:12 – NVPSIZ2[3:0] Second Non-volatile Program Memory Size Value Name Description

0 NONE None

Bits 11:8 – NVPSIZ[3:0] Non-volatile Program Memory Size Value Name Description 14 2048K 2048 Kbytes Bits 7:5 – EPROC[2:0] Embedded Processor Value Name Description

0 SAM x7 Cortex-M7

Bits 4:0 – VERSION[4:0] Version of the Device Current version of the device. SAMV71Q21RT Chip Identifier (CHIPID) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 110

21.3.2 Chip ID Extension Register

Name: CHIPID_EXID Offset: 0x4 Reset: 0x00000002 Property: Read-only Bit 31 30 29 28 27 26 25 24 EXID[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 EXID[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 EXID[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EXID[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 1 0 Bits 31:0 – EXID[31:0] Chip ID Extension This field is cleared if CHIPID_CIDR.EXT = 0. SAMV71Q21RT Chip Identifier (CHIPID) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 111

Enhanced Embedded Flash Controller (EEFC)

22.1 Description

The Enhanced Embedded Flash Controller (EEFC) provides the interface of the Flash block with the 32-bit internal bus. Its 128-bit wide memory interface increases performance. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash organization, thus making the software generic.

22.2 Embedded Characteristics

Increases Performance in Thumb-2 Mode with 128-bit-wide Memory Interface up to 150 MHz
Code Loop Optimization
128 Lock Bits, Each Protecting a Lock Region
9 General-purpose GPNVM Bits
One-by-one Lock Bit Programming
Commands Protected by a Keyword
Erase the Entire Flash
Erase by Sector
Erase by Page
Provides Unique Identifier
Provides 512-byte User Signature Area
Supports Erasing before Programming
Locking and Unlocking Operations
ECC Single and Multiple Error Flags Report
Supports Read of the Calibration Bits
Register Write Protection

22.3 Product Dependencies

22.3.1 Power Management

The Enhanced Embedded Flash Controller (EEFC) is continuously clocked. The Power Management Controller has no effect on its behavior.

22.3.2 Interrupt Sources

The EEFC interrupt line is connected to the interrupt controller. Using the EEFC interrupt requires the interrupt controller to be programmed first. The EEFC interrupt is generated only if the value of EEFC_FMR.FRDY is ‘1’.

22.4 Functional Description

22.4.1 Embedded Flash Organization

The embedded Flash interfaces directly with the internal bus. The embedded Flash is composed of:

One memory plane organized in several pages of the same size for the code
A separate 2 x 512-byte memory area which includes the unique chip identifier
A separate 512-byte memory area for the user signature SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 112

Two 128-bit read buffers used for code read optimization
One 128-bit read buffer used for data read optimization
One write buffer that manages page programming. The write buffer size is equal to the page size. This buffer is write-only and accessible all along the 1 Mbyte address space, so that each word can be written to its final address.
Several lock bits used to protect write/erase operation on several pages (lock region). A lock bit is associated with a lock region composed of several pages in the memory plane.
Several bits that may be set and cleared through the EEFC interface, called general-purpose non-volatile memory bits (GPNVM bits) The embedded Flash size, the page size, the organization of lock regions and the definition of GPNVM bits are specific to the device. The EEFC returns a descriptor of the Flash controller after a ‘Get Flash Descriptor’ command has been issued by the application (see the “Get Flash Descriptor Command” section). Figure 22-1. Flash Memory Areas @FBA+0x000User Signature Area Unique Identifier Area Unique Identifier Code Area @FBA+0x1FF @FBA+0x000 @FBA+0x3FF @FBA+0x000 Write “Start Unique Identifier” (Flash Command STUI) Write “Start User Signature” (Flash Command STUS) @FBA+0x010 @FBA+0x010 Write “Stop Unique Identifier” (Flash Command SPUI) Write “Stop User signature” (Flash Command SPUS) FBA = Flash Base Address SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 113

Figure 22-2. Organization of Embedded Flash for Code Start Address Page 0 Lock Region 0 Lock Region 1 Memory Plane Page (m-1) Lock Region (n-1) Page (n*m-1)Start Address + Flash size -1 Lock Bit 0 Lock Bit 1 Lock Bit (n-1)

22.4.2 Read Operations

An optimized controller manages embedded Flash reads, thus increasing performance when the processor is running in Thumb-2 mode by means of the 128-bit-wide memory interface. The Flash memory is accessible through 8-, 16- and 32-bit reads. As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded Flash wraps around the address space and appears to be repeated within it. The read operations can be performed with or without wait states. Wait states must be programmed in the field FWS in the Flash Mode register (EEFC_FMR). Defining FWS as 0 enables the single-cycle access of the embedded Flash. For more details, refer to the section “Electrical Characteristics” of this datasheet.

22.4.2.1 Code Read Optimization

Code read optimization is enabled if the bit EEFC_FMR.SCOD is cleared. A system of 2 x 128-bit buffers is added in order to optimize sequential code fetch. Note: Immediate consecutive code read accesses are not mandatory to benefit from this optimization. The sequential code read optimization is enabled by default. If the bit EEFC_FMR.SCOD is set, these buffers are disabled and the sequential code read is no longer optimized. Another system of 2 x 128-bit buffers is added in order to optimize loop code fetch. Refer to the “Code Loop Optimization” section for more details. SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 114

Figure 22-3. Code Read Optimization for FWS = 0 Flash Access Buffer 0 (128 bits) Master Clock ARM Request (32-bit) XXX Data to ARM Bytes 0–15 Bytes 16–31 Bytes 32–47 Bytes 0–15 Buffer 1 (128 bits) Bytes 32–47 Bytes 0–3 Bytes 4–7 Bytes 8–11 Bytes 12–15 Bytes 16–19 Bytes 20–23 Bytes 24–27XXX XXX Bytes 16–31 Bytes 28–31 anticipation of @16-31 Note: When FWS is equal to '0', all the accesses are performed in a single-cycle access. Figure 22-4. Code Read Optimization for FWS = 3 Flash Access Buffer 0 (128 bits) Master Clock ARM Request (32-bit) Data to ARM Buffer 1 (128 bits) 0–3 XXX XXX Bytes 16–31 @ 0 @+4 @+8 Bytes 0–15 Bytes 16–31 Bytes 32–47 Bytes 48–63 Bytes 0–15 4–7 8–11 12–15 @+12 @+16 @+20 24–27 28–31 32–35 36–39 16–19 20–23 40–43 44–47 Bytes 32–47 48–51 anticipation of @16-31 anticipation of @32-47 wait 3 cycles before 128-bit data is stable @0/4/8/12 are ready @16/20/24/28 are ready Note: When FWS is between 1 and 3, in case of sequential reads, the first access takes (FWS + 1) cycles. The following accesses take only one cycle.

22.4.2.2 Code Loop Optimization

Code loop optimization is enabled when the bit EEFC_FMR.CLOE is set. When a backward jump is inserted in the code, the pipeline of the sequential optimization is broken and becomes inefficient. In this case, the loop code read optimization takes over from the sequential code read optimization to prevent the insertion of wait states. The loop code read optimization is enabled by default. In EEFC_FMR, if the bit CLOE is reset to 0 or the bit SCOD is set, these buffers are disabled and the loop code read is not optimized. When code loop optimization is enabled, if inner loop body instructions L0 to Ln are positioned from the 128-bit Flash memory cell Mb0 to the memory cell Mp1, after recognition of a first backward branch, the first two Flash memory cells Mb0 and Mb1 targeted by this branch are cached for fast access from the processor at the next loop iteration. Then by combining the sequential prefetch (described in the “Code Read Optimization” section) through the loop body with the fast read access to the loop entry cache, the entire loop can be iterated with no wait state. The following figure illustrates code loop optimization. SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 115

Figure 22-5. Code Loop Optimization LnLn-1Ln-2Ln-3Ln-4Ln-5L5L4L3L2L1L0 B1 B2 B3 B4 B5 B6 B7B0 P1 P2 P3 P4 P5 P6 P7P0 Mb0Mb0 Mb1 Mp0 Mp1 Backward address jump 2x128-bit loop entry cache 2x128-bit prefetch buffer L0 Loop Entry instruction Ln Loop End instruction Flash Memory 128-bit words Mb0 Branch Cache 0 Mb1 Branch Cache 1 Mp0 Prefetch Buffer 0 Mp1 Prefetch Buffer 1

22.4.2.3 Data Read Optimization

The organization of the Flash in 128 bits is associated with two 128-bit prefetch buffers and one 128-bit data read buffer, thus providing maximum system performance. This buffer is added in order to store the requested data plus all the data contained in the 128-bit aligned data. This speeds up sequential data reads if, for example, FWS is equal to 1 (see Figure 22-6). The data read optimization is enabled by default. If the bit EEFC_FMR.SCOD is set, this buffer is disabled and the data read is no longer optimized. Note: No consecutive data read accesses are mandatory to benefit from this optimization. Figure 22-6. Data Read Optimization for FWS = 1 Flash Access Buffer (128 bits) Master Clock ARM Request (32-bit) XXX Data to ARM Bytes 0–15 Bytes 16–31 Bytes 0–15 Bytes 0–3 4–7 8–11 12–15 16–19 20–23XXX Bytes 16–31 @Byte 0 @ 4 @ 8 @ 12 @ 16 @ 20 @ 24 @ 28 @ 32 @ 36 XXX Bytes 32–47 24–27 28–31 32–35

22.4.3 Flash Commands

The EEFC offers a set of commands to manage programming the Flash memory, locking and unlocking lock regions, consecutive programming, locking and full Flash erasing, etc. The commands are listed in the following table. Table 22-1. Set of Commands Command Value Mnemonic Get Flash Descriptor 0x00 GETD Write Page 0x01 WP Write Page and Lock 0x02 WPL Erase Page and Write Page 0x03 EWP Erase Page and Write Page and then Lock 0x04 EWPL Erase All 0x05 EA SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 116

Start Read Unique Identifier 0x0E STUI Stop Read Unique Identifier 0x0F SPUI Get CALIB Bit 0x10 GCALB Erase Sector 0x11 ES Write User Signature 0x12 WUS Erase User Signature 0x13 EUS Start Read User Signature 0x14 STUS Stop Read User Signature 0x15 SPUS To execute one of these commands, select the required command using the FCMD field in the Flash Command register (EEFC_FCR). As soon as EEFC_FCR is written, the FRDY flag and the FVALUE field in the Flash Result register (EEFC_FRR) are automatically cleared. Once the current command has completed, the FRDY flag is automatically set. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the corresponding interrupt line of the interrupt controller is activated. (Note that this is true for all commands except for the STUI command. The FRDY flag is not set when the STUI command has completed.) All the commands are protected by the same keyword, which must be written in the eight highest bits of EEFC_FCR. Writing EEFC_FCR with data that does not contain the correct key and/or with an invalid command has no effect on the whole memory plane, but the FCMDE flag is set in the Flash Status register (EEFC_FSR). This flag is automatically cleared by a read access to EEFC_FSR. When the current command writes or erases a page in a locked region, the command has no effect on the whole memory plane, but the FLOCKE flag is set in EEFC_FSR. This flag is automatically cleared by a read access to EEFC_FSR. SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 117

Figure 22-7. Command State Chart Check if FRDY flag Set No Yes Read Status: EEFC_FSR Write FCMD and PAGENB in Flash Command Register Check if FLOCKE flag Set Check if FRDY flag Set No Read Status: EEFC_FSR Yes Yes Locking region violation No Check if FCMDE flag Set Yes No Bad keyword violation Command Successful

22.4.3.1 Get Flash Descriptor Command

This command provides the system with information on the Flash organization. The system can take full advantage of this information. For instance, a device could be replaced by one with more Flash capacity, and so the software is able to adapt itself to the new configuration. To get the embedded Flash descriptor, the application writes the GETD command in EEFC_FCR. The first word of the descriptor can be read by the software application in EEFC_FRR as soon as the FRDY flag in EEFC_FSR rises. The next reads of EEFC_FRR provide the following word of the descriptor. If extra read operations to EEFC_FRR are done after the last word of the descriptor has been returned, the EEFC_FRR value is 0 until the next valid command. Table 22-2. Flash Descriptor Definition Symbol Word Index Description FL_ID 0 Flash interface description FL_SIZE 1 Flash size in bytes FL_PAGE_SIZE 2 Page size in bytes SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 118

Symbol Word Index Description FL_NB_PLANE 3 Number of planes FL_PLANE[0] 4 Number of bytes in the plane FL_NB_LOCK 4 + FL_NB_PLANE Number of lock bits. A bit is associated with a lock region. A lock bit is used to prevent write or erase operations in the lock region. FL_LOCK[0] 4 + FL_NB_PLANE + 1 Number of bytes in the first lock region

22.4.3.2 Write Commands

DMA write accesses must be 32-bit aligned. If a single byte has to be written in a 32-bit word, the rest of the word must be written with ones. Several commands are used to program the Flash. Only ‘0’ values can be programmed using Flash technology; ‘1’ is the erased value. In order to program words in a page, the page must first be erased. Commands are available to erase the entire Flash or a given number of pages. With the EWP and EWPL commands, a page erase is done automatically before a page programming. After programming, the page (the entire lock region) can be locked to prevent miscellaneous write or erase sequences. The lock bit can be automatically set after page programming using WPL or EWPL commands. Data to be programmed in the Flash must be written in an internal latch buffer before writing the programming command in EEFC_FCR. Data can be written at their final destination address, as the latch buffer is mapped into the Flash memory address space and wraps around within this Flash address space. Byte and half-word AHB accesses to the latch buffer are not allowed. Only 32-bit word accesses are supported. 32-bit words must be written continuously, in either ascending or descending order. Writing the latch buffer in a random order is not permitted. This prevents mapping a C-code structure to the latch buffer and accessing the data of the structure in any order. It is instead recommended to fill in a C-code structure in SRAM and copy it in the latch buffer in a continuous order. Write operations in the latch buffer are performed with the number of wait states programmed for reading the Flash. The latch buffer is automatically re-initialized, that is, written with logical ‘1’, after execution of each programming command. The programming sequence is as follows: 1. Write the data to be programmed in the latch buffer. 2. Write the programming command in EEFC_FCR. This automatically clears the EEFC_FSR.FRDY bit. 3. When Flash programming is completed, the EEFC_FSR.FRDY bit rises. If an interrupt has been enabled by setting the EEFC_FMR.FRDY bit, the interrupt line of the EEFC is activated. Three errors can be detected in EEFC_FSR after a programming sequence:

Command Error: A bad keyword has been written in EEFC_FCR.
Lock Error: The page to be programmed belongs to a locked region. A command must be run previously to unlock the corresponding region.
Flash Error: When programming is completed, the WriteVerify test of the Flash memory has failed. Only one page can be programmed at a time. It is possible to program all the bits of a page (full page programming) or only some of the bits of the page (partial page programming). Depending on the number of bits to be programmed within the page, the EEFC adapts the write operations required to program the Flash. When a ‘Write Page’ (WP) command is issued, the EEFC starts the programming sequence and all the bits written at ‘0’ in the latch buffer are cleared in the Flash memory array. During programming, that is, until EEFC_FSR.FDRY rises, access to the Flash is not allowed. SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 119

22.4.3.2.1 Full Page Programming

To program a full page, all the bits of the page must be erased before writing the latch buffer and issuing the WP command. The latch buffer must be written in ascending order, starting from the first address of the page. See Figure 22-8.

22.4.3.2.2 Partial Page Programming

To program only part of a page using the WP command, the following constraints must be respected:

Data to be programmed must be contained in integer multiples of 128-bit address-aligned words.
128-bit words can be programmed only if all the corresponding bits in the Flash array are erased (at logical value ‘1’).

22.4.3.2.3 Optimized Partial Page Programming

The EEFC automatically detects the number of 128-bit words to be programmed. If only one 128-bit aligned word is to be programmed in the Flash array, the process is optimized to reduce the time needed for programming. If several 128-bit words are to be programmed, a standard page programming operation is performed. See Figure 22-10.

22.4.3.2.4 Programming Bytes

Individual bytes can be programmed using the Partial Page Programming mode. In this case, an area of 128 bits must be reserved for each byte. Refer to Figure 22-11 SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 120

Figure 22-8. Full Page Programming FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C Before programming: Unerased page in Flash array CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE Step 1: Flash array after page erase FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF address space for Page N address space for latch buffer Step 2: Writing a page in the latch buffer DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA CA FE CA FE 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C address space for Page N Step 3: Page in Flash array after issuing WP command and FRDY=1 DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA FF FF FF FF 32 bits wide 32 bits wide SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 121

Figure 22-9. Partial Page Programming 32 bits wide 32 bits wide FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C Step 2: Flash array after programming 128-bit at address 0xX00 (write latch buffer + WP) CA FE CA FE CA FE CA FE address space for Page N FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF Step 1: Flash array after page erase C A FE C A F E C A FE C A F E 32 bits wide 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C Step 3: Flash array after programming a second 128-bit data at address 0xX10 (write latch buffer + WP) CA FE CA FE CA FE CA FE FF FF FF FF FF FF FF FF FF FF FF FF CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 122

Figure 22-10. Optimized Partial Page Programming 32 bits wide FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 32 bits wide FF FF FF FF Case 2: 2 x 32 bits modified, not crossing 128-bit boundary User programs WP, Flash Controller sends Write Word => Only 1 word programmed => programming period reduced FF FF FF FF FF FF FF FF FF FF FF FF CA FE FF FF FF FF CA FE CA FE FF F F FF FF CA F E 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C 32 bits wide FF FF FF FF Case 3: 4 x 32 bits modified across 128-bit boundary User programs WP, Flash Controller sends WP => Whole page programmed FF FF FF FF FF FF FF FF FF FF FF FF 32 bits wide FF FF FF FF Case 4: 4 x 32 bits modified, not crossing 128-bit boundary User programs WP, Flash Controller sends Write Word => Only 1 word programmed => programming period reduced FF FF FF FF FF FF FF FF FF FF FF FF CA FE CA FE 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE FF FF FF FF CA FE CA FE Case 1: 2 x 32 bits modified, not crossing 128-bit boundary User programs WP, Flash Controller sends Write Word => Only 1 word programmed => programming period reduced CA FE CA FE FF FF FF FF FF FF FF FF 4 x 32 bits 4 x 32 bits 4 x 32 bits 4 x 32 bits SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 123

Figure 22-11. Programming Bytes in the Flash 32 bits wide FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C address space for Page N Step 1: Flash array after programming first byte (0xAA) 128-bit used at address 0xX00 (write latch buffer + WP) FF FF FF FF xx xx xx xx xx xx xx AA 32 bits wide 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C FF FF FF FF xx xx xx xx xx xx xx AA Step 2: Flash array after programming second byte (0x55) 128-bit used at address 0xX10 (write latch buffer + WP) xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx 55 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx Note: The byte location shown here is for example only, it can be any byte location within a 64-bit word 4 x 32 bits =

1 Flash word

4 x 32 bits =

22.4.3.3 Erase Commands

Erase commands are allowed only on unlocked regions. Depending on the Flash memory, several commands can be used to erase the Flash:

Erase All Memory (EA): All memory is erased. The processor must not fetch code from the Flash memory.
Erase Pages (EPA): 4, 8, 16, or 32 pages are erased in the Flash sector selected. The first page to be erased is specified in the FARG[15:2] field of the EEFC_FCR. The first page number must be a multiple of 8, 16, or 32 depending on the number of pages to erase simultaneously.
Erase Sector (ES): A full memory sector is erased. Sector size depends on the Flash memory. EEFC_FCR.FARG must be set with a page number that is in the sector to be erased. Note: If one sub-sector is locked within the first sector, the Erase Sector (ES) command cannot be processed on non-locked sub-sectors of the first sector. All the lock bits of the first sector must be cleared prior to issuing an ES command on the first sector. After the ES command has been issued, the first sector lock bits must be reverted to the state before clearing them. If the processor is fetching code from the Flash memory while the EPA or ES command is being executed, the processor accesses are stalled until the EPA command is completed. To avoid stalling the processor, the code can be run out of internal SRAM. The following are the erase sequence: 1. Erase starts immediately one of the erase commands and the FARG field are written in EEFC_FCR. For the EPA command, the two lowest bits of the FARG field define the number of pages to be erased (FARG[1:0]), see table below. Table 22-3. EEFC_FCR.FARG Field for EPA Command FARG[1:0] Number of pages to be erased with EPA command 0 4 pages (only valid for small 8-KB sectors) 1 8 pages (only valid for small 8-KB sectors) 2 16 pages SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 124

FARG[1:0] Number of pages to be erased with EPA command 3 32 pages (not valid for small 8-KB sectors) 2. When erasing is completed, the EEFC_FSR.FRDY bit rises. If an interrupt has been enabled by setting the EEFC_FMR.FRDY bit, the interrupt line of the interrupt controller is activated. Three errors can be detected in EEFC_FSR after an erasing sequence:

Command Error: A bad keyword has been written in EEFC_FCR.
Lock Error: At least one page to be erased belongs to a locked region. The erase command has been refused, no page has been erased. A command must be run previously to unlock the corresponding region.
Flash Error: At the end of the erase period, the EraseVerify test of the Flash memory has failed.

22.4.3.4 Lock Bit Protection

Lock bits are associated with several pages in the embedded Flash memory plane. This defines lock regions in the embedded Flash memory plane. They prevent writing/erasing protected pages. The lock sequence is the following: 1. Execute the ‘Set Lock Bit’ command by writing EEFC_FCR.FCMD with the SLB command and EEFC_FCR.FARG with a page number to be protected. 2. When the locking completes, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. 3. The result of the SLB command can be checked running a ‘Get Lock Bit’ (GLB) command. Note: The value of the FARG argument passed together with SLB command must not exceed the higher lock bit index available in the product. Two errors can be detected in EEFC_FSR after a programming sequence:

Command Error: A bad keyword has been written in EEFC_FCR.
Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. It is possible to clear lock bits previously set. After the lock bits are cleared, the locked region can be erased or programmed. The unlock sequence is the following: 1. Execute the ‘Clear Lock Bit’ command by writing EEFC_FCR.FCMD with the CLB command and EEFC_FCR.FARG with a page number to be unprotected. 2. When the unlock completes, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. Note: The value of the FARG argument passed together with CLB command must not exceed the higher lock bit index available in the product. Two errors can be detected in EEFC_FSR after a programming sequence:
Command Error: A bad keyword has been written in EEFC_FCR.
Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. The status of lock bits can be returned by the EEFC. The ‘Get Lock Bit’ sequence is the following: 1. Execute the ‘Get Lock Bit’ command by writing EEFC_FCR.FCMD with the GLB command. Field EEFC_FCR.FARG is meaningless. 2. Lock bits can be read by the software application in EEFC_FRR. The first word read corresponds to the 32 first lock bits, next reads providing the next 32 lock bits as long as it is meaningful. Extra reads to EEFC_FRR return 0. For example, if the third bit of the first word read in EEFC_FRR is set, the third lock region is locked. Two errors can be detected in EEFC_FSR after a programming sequence:
Command Error: A bad keyword has been written in EEFC_FCR.
Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. Note: Access to the Flash in read is permitted when a ‘Set Lock Bit’, ‘Clear Lock Bit’ or ‘Get Lock Bit’ command is executed. SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 125

22.4.3.5 GPNVM Bit

GPNVM bits do not interfere with the embedded Flash memory plane. For more details, refer to the section "Memories". The ‘Set GPNVM Bit’ sequence is the following: 1. Execute the ‘Set GPNVM Bit’ command by writing EEFC_FCR.FCMD with the SGPB command and EEFC_FCR.FARG with the number of GPNVM bits to be set. 2. When the GPNVM bit is set, the bit EEFC_FSR.FRDY rises. If an interrupt was enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. 3. The result of the SGPB command can be checked by running a ‘Get GPNVM Bit’ (GGPB) command. Note: The value of the FARG argument passed together with SGPB command must not exceed the higher GPNVM index available in the product. Flash data content is not altered if FARG exceeds the limit. Command Error is detected only if FARG is greater than 8. Two errors can be detected in EEFC_FSR after a programming sequence:

Command Error: A bad keyword has been written in EEFC_FCR.
Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. It is possible to clear GPNVM bits previously set. The ‘Clear GPNVM Bit’ sequence is the following: 1. Execute the ‘Clear GPNVM Bit’ command by writing EEFC_FCR.FCMD with the CGPB command and EEFC_FCR.FARG with the number of GPNVM bits to be cleared. 2. When the clear completes, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. Note: The value of the FARG argument passed together with CGPB command must not exceed the higher GPNVM index available in the product. Flash data content is not altered if FARG exceeds the limit. Command Error is detected only if FARG is greater than 8. Two errors can be detected in EEFC_FSR after a programming sequence:
Command Error: A bad keyword has been written in EEFC_FCR.
Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. The status of GPNVM bits can be returned by the EEFC. The sequence is the following: 1. Execute the ‘Get GPNVM Bit’ command by writing EEFC_FCR.FCMD with the GGPB command. Field EEFC_FCR.FARG is meaningless. 2. GPNVM bits can be read by the software application in EEFC_FRR. The first word read corresponds to the 32 first GPNVM bits, following reads provide the next 32 GPNVM bits as long as it is meaningful. Extra reads to EEFC_FRR return 0. For example, if the third bit of the first word read in EEFC_FRR is set, the third GPNVM bit is active. One error can be detected in EEFC_FSR after a programming sequence:
Command Error: A bad keyword has been written in EEFC_FCR. Note: Access to the Flash in read is permitted when a ‘Set GPNVM Bit’, ‘Clear GPNVM Bit’ or ‘Get GPNVM Bit’ command is executed. Related Links 11. Memories

22.4.3.6 Calibration Bit

Calibration bits do not interfere with the embedded Flash memory plane. The calibration bits cannot be modified. The status of calibration bits are returned by the EEFC. The sequence is as follows: 1. Execute the ‘Get CALIB Bit’ command by writing EEFC_FCR.FCMD with the GCALB command. Field EEFC_FCR.FARG is meaningless. SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 126

Calibration bits can be read by the software application in EEFC_FRR. The first word read corresponds to the first 32 calibration bits. The following reads provide the next 32 calibration bits as long as it is meaningful. Extra reads to EEFC_FRR return 0. The 8/12 MHz internal RC oscillator is calibrated in production. This calibration can be read through the GCALB command. Table 22-4 shows the bit implementation. The RC calibration for the 4 MHz is set to ‘1000000’. Table 22-4. Calibration Bit Indexes Description EEFC_FRR Bits

8 MHz RC calibration output [28–22]

12 MHz RC calibration output [38–32]

22.4.3.7 Security Bit Protection

When the security bit is enabled, the Embedded Trace Macrocell (ETM) is disabled and access to the Flash through the SWD interface or through the Fast Flash Programming interface is forbidden. This ensures the confidentiality of the code programmed in the Flash. The security bit is GPNVM0. Disabling the security bit can only be achieved by asserting the ERASE signal at ‘1’, and after a full Flash erase is performed. When the security bit is deactivated, all accesses to the Flash are permitted.

22.4.3.8 Unique Identifier Area

Each device is programmed with a 128-bit unique identifier area . See Figure 22-1. The sequence to read the unique identifier area is the following: 1. Execute the ‘Start Read Unique Identifier’ command by writing EEFC_FCR.FCMD with the STUI command. Field EEFC_FCR.FARG is meaningless. 2. Wait until the bit EEFC_FSR.FRDY falls to read the unique identifier area. The unique identifier field is located in the first 128 bits of the Flash memory mapping. The ‘Start Read Unique Identifier’ command reuses some addresses of the memory plane for code, but the unique identifier area is physically different from the memory plane for code. 3. To stop reading the unique identifier area, execute the ‘Stop Read Unique Identifier’ command by writing EEFC_FCR.FCMD with the SPUI command. Field EEFC_FCR.FARG is meaningless. 4. When the SPUI command has been executed, the bit EEFC_FSR.FRDY rises. If an interrupt was enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. Note: During the sequence, the software cannot be fetched from the Flash.

22.4.3.9 User Signature Area

Each product contains a user signature area of 512 bytes. It can be used for storage. Read, write and erase of this area is allowed. See Figure 22-1. The sequence to read the user signature area is the following: 1. Execute the ‘Start Read User Signature’ command by writing EEFC_FCR.FCMD with the STUS command. Field EEFC_FCR.FARG is meaningless. 2. Wait until the bit EEFC_FSR.FRDY falls to read the user signature area. The user signature area is located in the first 512 bytes of the Flash memory mapping. The ‘Start Read User Signature’ command reuses some addresses of the memory plane but the user signature area is physically different from the memory plane 3. To stop reading the user signature area, execute the ‘Stop Read User Signature’ command by writing EEFC_FCR.FCMD with the SPUS command. Field EEFC_FCR.FARG is meaningless. 4. When the SPUI command has been executed, the bit EEFC_FSR.FRDY rises. If an interrupt was enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 127

Note: During the sequence, the software cannot be fetched from the Flash or from the second plane in case of dual plane. One error can be detected in EEFC_FSR after this sequence:

Command Error: A bad keyword has been written in EEFC_FCR. The sequence to write the user signature area is the following: 1. Write the full page, at any page address, within the internal memory area address space. 2. Execute the ‘Write User Signature’ command by writing EEFC_FCR.FCMD with the WUS command. Field EEFC_FCR.FARG is meaningless. 3. When programming is completed, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the corresponding interrupt line of the interrupt controller is activated. Two errors can be detected in EEFC_FSR after this sequence:
Command Error: A bad keyword has been written in EEFC_FCR.
Flash Error: At the end of the programming, the WriteVerify test of the Flash memory has failed. The sequence to erase the user signature area is the following: 1. Execute the ‘Erase User Signature’ command by writing EEFC_FCR.FCMD with the EUS command. Field EEFC_FCR.FARG is meaningless. 2. When programming is completed, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the corresponding interrupt line of the interrupt controller is activated. Two errors can be detected in EEFC_FSR after this sequence:
Command Error: A bad keyword has been written in EEFC_FCR.
Flash Error: At the end of the programming, the EraseVerify test of the Flash memory has failed.

22.4.3.10 ECC Errors and Corrections

The Flash embeds an ECC module able to correct one unique error and able to detect two errors. The errors are detected while a read access is performed into memory array and stored in EEFC_FSR (see “EEFC Flash Status Register”). The error report is kept until EEFC_FSR is read. There is one flag for a unique error on lower half part of the Flash word (64 LSB) and one flag for the upper half part (MSB). The multiple errors are reported in the same way. Due to the anticipation technique to improve bandwidth throughput on instruction fetch, a reported error can be located in the next sequential Flash word compared to the location of the instruction being executed, which is located in the previously fetched Flash word. If a software routine processes the error detection independently from the main software routine, the entire Flash located software must be rewritten because there is no storage of the error location. If only a software routine is running to program and check pages by reading EEFC_FSR, the situation differs from the previous case. Performing a check for ECC unique errors just after page programming completion involves a read of the newly programmed page. This read sequence is viewed as data accesses and is not optimized by the Flash controller. Thus, in case of unique error, only the current page must be reprogrammed.

22.4.4 Register Write Protection

To prevent any single software error from corrupting EEFC behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the “EEFC Write Protection Mode Register” (EEFC_WPMR). The following register can be write-protected:

“EEFC Flash Mode Register” SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 128

22.5 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 EEFC_FMR 7:0 FRDY 15:8 FWS[3:0] 23:16 SCOD 31:24 CLOE 0x04 EEFC_FCR 7:0 FCMD[7:0] 15:8 FARG[7:0] 23:16 FARG[15:8] 31:24 FKEY[7:0] 0x08 EEFC_FSR 7:0 FLERR FLOCKE FCMDE FRDY 15:8 23:16 MECCEMSB UECCEMSB MECCELSB UECCELSB 31:24 0x0C EEFC_FRR 7:0 FVALUE[7:0] 15:8 FVALUE[15:8] 23:16 FVALUE[23:16] 31:24 FVALUE[31:24] 0x10 ... 0xE3 Reserved 0xE4 EEFC_WPMR 7:0 WPEN 15:8 WPKEY[7:0] 23:16 WPKEY[15:8] 31:24 WPKEY[23:16] SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 129

22.5.1 EEFC Flash Mode Register

Name: EEFC_FMR Offset: 0x00 Reset: 0x04000000 Property: Read/Write This register can only be written if the WPEN bit is cleared in the “EEFC Write Protection Mode Register” . Bit 31 30 29 28 27 26 25 24 CLOE Access R/W Reset 1 Bit 23 22 21 20 19 18 17 16 SCOD Access R/W Reset 0 Bit 15 14 13 12 11 10 9 8 FWS[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FRDY Access R/W Reset 0 Bit 26 – CLOE Code Loop Optimization Enable No Flash read should be done during change of this field. Value Description 0 The opcode loop optimization is disabled. 1 The opcode loop optimization is enabled. Bit 16 – SCOD Sequential Code Optimization Disable No Flash read should be done during change of this field. Value Description 0 The sequential code optimization is enabled. 1 The sequential code optimization is disabled. Bits 11:8 – FWS[3:0] Flash Wait State This field defines the number of wait states for read and write operations: FWS = Number of cycles for Read/Write operations - 1 Bit 0 – FRDY Flash Ready Interrupt Enable Value Description 0 Flash ready does not generate an interrupt. 1 Flash ready (to accept a new command) generates an interrupt. SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 130

22.5.2 EEFC Flash Command Register

Name: EEFC_FCR Offset: 0x04 Reset: – Property: Write-only Bit 31 30 29 28 27 26 25 24 FKEY[7:0] Access W W W W W W W W Bit 23 22 21 20 19 18 17 16 FARG[15:8] Access W W W W W W W W Bit 15 14 13 12 11 10 9 8 FARG[7:0] Access W W W W W W W W Bit 7 6 5 4 3 2 1 0 FCMD[7:0] Access Bits 31:24 – FKEY[7:0] Flash Write Protection Key Value Name Description 0x5A PASSWD The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. Bits 23:8 – FARG[15:0] Flash Command Argument GETD, GLB, GGPB, STUI, SPUI, GCALB, WUS, EUS, STUS, SPUS, EA Commands requiring no argument, including Erase all command FARG is meaningless, must be written with 0 ES Erase sector command FARG must be written with any page number within the sector to be erased EPA Erase pages command FARG[1:0] defines the number of pages to be erased The start page must be written in FARG[15:2]. FARG[1:0] = 0: Four pages to be erased. FARG[15:2] = Page_Number / FARG[1:0] = 1: Eight pages to be erased. FARG[15:3] = Page_Number / 8, FARG[2]=0 FARG[1:0] = 2: Sixteen pages to be erased. FARG[15:4] = Page_Number / 16, FARG[3:2]=0 FARG[1:0] = 3: Thirty-two pages to be erased. FARG[15:5] = Page_Number / 32, FARG[4:2]=0 Refer to “EEFC_FCR.FARG Field for EPA Command”. SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 131

WP, WPL, EWP, EWPL Programming commands FARG must be written with the page number to be programmed SLB, CLB Lock bit commands FARG defines the page number to be locked or unlocked SGPB, CGPB GPNVM commands FARG defines the GPNVM number to be programmed Bits 7:0 – FCMD[7:0] Flash Command Value Name Description 0x00 GETD Get Flash descriptor 0x01 WP Write page 0x02 WPL Write page and lock 0x03 EWP Erase page and write page 0x04 EWPL Erase page and write page then lock 0x05 EA Erase all 0x07 EPA Erase pages 0x08 SLB Set lock bit 0x09 CLB Clear lock bit 0x0A GLB Get lock bit 0x0B SGPB Set GPNVM bit 0x0C CGPB Clear GPNVM bit 0x0D GGPB Get GPNVM bit 0x0E STUI Start read unique identifier 0x0F SPUI Stop read unique identifier 0x10 GCALB Get CALIB bit 0x11 ES Erase sector 0x12 WUS Write user signature 0x13 EUS Erase user signature 0x14 STUS Start read user signature 0x15 SPUS Stop read user signature SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 132

22.5.3 EEFC Flash Status Register

Name: EEFC_FSR Offset: 0x08 Reset: 0x00000001 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 MECCEMSB UECCEMSB MECCELSB UECCELSB Access R R R R Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 FLERR FLOCKE FCMDE FRDY Access R R R R Reset 0 0 0 1 Bit 19 – MECCEMSB Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Value Description

0 No multiple error detected on 64 MSB part of the Flash memory data bus since the last read of

EEFC_FSR.

1 Multiple errors detected and NOT corrected on 64 MSB part of the Flash memory data bus since the

last read of EEFC_FSR. Bit 18 – UECCEMSB Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Value Description 0 No unique error detected on 64 MSB data bus of the Flash memory since the last read of EEFC_FSR.

1 One unique error detected but corrected on 64 MSB data bus of the Flash memory since the last read

of EEFC_FSR. Bit 17 – MECCELSB Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Value Description

0 No multiple error detected on 64 LSB part of the Flash memory data bus since the last read of

EEFC_FSR.

1 Multiple errors detected and NOT corrected on 64 LSB part of the Flash memory data bus since the

last read of EEFC_FSR. Bit 16 – UECCELSB Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Value Description 0 No unique error detected on 64 LSB data bus of the Flash memory since the last read of EEFC_FSR.

1 One unique error detected but corrected on 64 LSB data bus of the Flash memory since the last read

of EEFC_FSR. Bit 3 – FLERR Flash Error Status (cleared when a programming operation starts) SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 133

0 No Flash memory error occurred at the end of programming (EraseVerify or WriteVerify test has

passed). 1 A Flash memory error occurred at the end of programming (EraseVerify or WriteVerify test has failed). Bit 2 – FLOCKE Flash Lock Error Status (cleared on read) This flag is automatically cleared when EEFC_FSR is read or EEFC_FCR is written. Value Description 0 No programming/erase of at least one locked region has happened since the last read of EEFC_FSR. 1 Programming/erase of at least one locked region has happened since the last read of EEFC_FSR. Bit 1 – FCMDE Flash Command Error Status (cleared on read or by writing EEFC_FCR) Value Description 0 No invalid commands and no bad keywords were written in EEFC_FCR. 1 An invalid command and/or a bad keyword was/were written in EEFC_FCR. Bit 0 – FRDY Flash Ready Status (cleared when Flash is busy) When set, this flag triggers an interrupt if the FRDY flag is set in EEFC_FMR. This flag is automatically cleared when the EEFC is busy. Value Description 0 The EEFC is busy. 1 The EEFC is ready to start a new command. SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 134

22.5.4 EEFC Flash Result Register

Name: EEFC_FRR Offset: 0x0C Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 FVALUE[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 FVALUE[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 FVALUE[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FVALUE[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – FVALUE[31:0] Flash Result Value The result of a Flash command is returned in this register. If the size of the result is greater than 32 bits, the next resulting value is accessible at the next register read. SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 135

22.5.5 EEFC Write Protection Mode Register

Name: EEFC_WPMR Offset: 0xE4 Property: Read/Write Bit 31 30 29 28 27 26 25 24 WPKEY[23:16] Access Reset Bit 23 22 21 20 19 18 17 16 WPKEY[15:8] Access Reset Bit 15 14 13 12 11 10 9 8 WPKEY[7:0] Access Reset Bit 7 6 5 4 3 2 1 0 WPEN Access Reset Bits 31:8 – WPKEY[23:0] Write Protection Key See “Register Write Protection” for the list of registers that can be protected. Value Name Description 0x454643 PASSWD Writing any other value in this field aborts the write operation. Always reads as 0. Bit 0 – WPEN Write Protection Enable See “Register Write Protection” for the list of registers that can be protected. Value Description 0 Disables the write protection if WPKEY corresponds to 0x454643 (EFC in ASCII). 1 Enables the write protection if WPKEY corresponds to 0x454643 (EFC in ASCII). SAMV71Q21RT Enhanced Embedded Flash Controller (EEFC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 136

Supply Controller (SUPC)

23.1 Description

The Supply Controller (SUPC) controls the supply voltages of the system and manages the Backup mode. In this mode, current consumption is reduced to a few microamps for backup power retention. Exit from this mode is possible on multiple wakeup sources. The SUPC also generates the slow clock by selecting either the slow RC oscillator or the 32.768 kHz crystal oscillator.

23.2 Embedded Characteristics

Management of the Core Power Supply VDDCORE and Backup Mode via the Embedded Voltage Regulator
Supply Monitor Detection on VDDIO or a Brownout Detection on VDDCORE Triggers a Core Reset
Generates the Slow Clock SLCK by selecting either the 22-42 kHz Slow RC Oscillator or the 32.768 kHz Crystal Oscillator
Backup SRAM
Low-power Tamper Detection on Two Inputs
Anti-tampering by Immediate Clear of the General-purpose Backup Registers
Support of Multiple Wakeup Sources for Exit from Backup Mode – 14 Wakeup Inputs with Programmable Debouncing – Real-Time Clock Alarm – Real-Time Timer Alarm – Supply Monitor Detection on VDDIO, with Programmable Scan Period and Voltage Threshold SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 137

23.3 Block Diagram

Figure 23-1. Supply Controller Block Diagram Backup Area VDDOUT VDDIN on/off Reset Controller vddcore_nreset supc_irqPower-On Reset VDDCORE Brown-Out Detector VDDCORE por_core_out bod_out sm_out por_io_out Real-Time Clock WKUP0-WKUP13 Voltage Regulator Controller Real-Time Timer rtc_alarm VROFF Supply Monitor Controller BODDIS SMSMPL SMTH OSCBYPASS SMRSTEN BODRSTEN XTALSEL Slow Clock Controller SMIEN Supply Controller SMEN Wakeup Controller RTCEN rtt_alarm RTTEN RTCOUT0 RTCOUT1 sm_out LPDBCEN0 LPDBCEN1 LPDBCCLR WKUPEN0..15 WKUPT0..15 WKUPDBC LPDBC General-Purpose Backup Registers clear wake_up SLCK XIN32 XOUT32 Programmable Supply Monitor VDDIO Zero-Power Power-On Reset VDDIO 32.768 kHz Crystal Oscillator Slow RC Oscillator Interrupt Controller ONREG proc_nreset periph_nreset ice_nreset Backup SRAM BKUPRETON Power SwitchVDDIO Core Voltage Regulator SLCK VDDCORE Backup Mode NRST SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 138

23.4 Functional Description

23.4.1 Overview

The device is divided into two power supply areas:

VDDIO power supply: includes the Supply Controller, part of the Reset Controller, the slow clock switch, the general-purpose backup registers, the supply monitor and the clock which includes the Real-time Timer and the Real-time Clock.
Core power supply: includes part of the Reset Controller, the Brownout Detector, the processor, the SRAM memory, the Flash memory and the peripherals. The Supply Controller (SUPC) controls the supply voltage of the core power supply. The SUPC intervenes when the VDDIO power supply rises (when the system is starting) or when Backup mode is entered. The SUPC also integrates the slow clock generator, which is based on a 32.768 kHz crystal oscillator, and a slow RC oscillator. The slow clock defaults to the slow RC oscillator, but the software can enable the 32.768 kHz crystal oscillator and select it as the slow clock source. The SUPC and the VDDIO power supply have a reset circuitry based on a zero-power power-on reset cell. The zero-power power-on reset allows the SUPC to start correctly as soon as the VDDIO voltage becomes valid. At startup of the system, once the backup voltage VDDIO is valid and the slow RC oscillator is stabilized, the SUPC starts up the core by sequentially enabling the internal voltage regulator. The SUPC waits until the core voltage VDDCORE is valid, then releases the reset signal of the core vddcore_nreset signal. Once the system has started, the user can program a supply monitor and/or a brownout detector. If the supply monitor detects a voltage level on VDDIO that is too low, the SUPC asserts the reset signal of the core vddcore_nreset signal until VDDIO is valid. Likewise, if the brownout detector detects a core voltage level VDDCORE that is too low, the SUPC asserts the reset signal vddcore_nreset until VDDCORE is valid. When Backup mode is entered, the SUPC sequentially asserts the reset signal of the core power supply vddcore_nreset and disables the voltage regulator, in order to supply only the VDDIO power supply. Current consumption is reduced to a few microamps for the backup part retention. Exit from this mode is possible on multiple wakeup sources including an event on WKUP pins, or a clock alarm. To exit this mode, the SUPC operates in the same way as system startup.

23.4.2 Slow Clock Generator

The SUPC embeds a slow clock generator that is supplied with the VDDIO power supply. As soon as the VDDIO is supplied, both the 32.768 kHz crystal oscillator and the slow RC oscillator are powered up, but only the slow RC oscillator is enabled. When the slow RC oscillator is selected as the slow clock source, the slow clock stabilizes more quickly than when the 32.768 kHz crystal oscillator is selected. The user can select the 32.768 kHz crystal oscillator to be the source of the slow clock, as it provides a more accurate frequency than the slow RC oscillator. The 32.768 kHz crystal oscillator is selected by setting the XTALSEL bit in the SUPC Control register (SUPC_CR). The following sequence must be used to switch from the slow RC oscillator to the 32.768 kHz crystal oscillator: 1. The PIO lines multiplexed with XIN32 and XOUT32 are configured to be driven by the oscillator. 2. The 32.768 kHz crystal oscillator is enabled. 3. A number of slow RC oscillator clock periods is counted to cover the startup time of the 32.768 kHz crystal oscillator. Refer to the section “Electrical Characteristics” for information on the 32.768 kHz crystal oscillator startup time. 4. The slow clock is switched to the output of the 32.768 kHz crystal oscillator. 5. The slow RC oscillator is disabled to save power. The switching time may vary depending on the slow RC oscillator clock frequency range. The switch of the slow clock source is glitch-free. The OSCSEL bit of the SUPC Status register (SUPC_SR) indicates when the switch sequence is finished. Reverting to the slow RC oscillator as a slow clock source is only possible by shutting down the VDDIO power supply. If the user does not need the 32.768 kHz crystal oscillator, the XIN32 and XOUT32 pins should be left unconnected. SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 139

The user can also set the 32.768 kHz crystal oscillator in Bypass mode instead of connecting a crystal. In this case, the user has to provide the external clock signal on XIN32. The input characteristics of the XIN32 pin are given in the section “Electrical Characteristics”. To enter Bypass mode, the OSCBYPASS bit in the Mode register (SUPC_MR) must be set before setting XTALSEL.

23.4.3 Core Voltage Regulator Control/Backup Low-power Mode

The SUPC controls the embedded voltage regulator. The voltage regulator automatically adapts its quiescent current depending on the required load current. Refer to the section “Electrical Characteristics”. The user can switch off the voltage regulator, and thus put the device in Backup mode, by writing a ‘1’ to SUPC_CR.VROFF. This asserts the vddcore_nreset signal after the write resynchronization time, which lasts two slow clock cycles (worst case). Once the vddcore_nreset signal is asserted, the processor and the peripherals are stopped one slow clock cycle before the core power supply shuts off. When the internal voltage regulator is not used and VDDCORE is supplied by an external supply, the voltage regulator can be disabled by writing a ‘0’ to SUPC_MR.ONREG.

23.4.4 Using Backup Batteries/Backup Supply

When backup batteries or, more generally, a separate backup supply is used, only VDDIO is present in Backup mode. No other external supply is applied. Figure 23-2. Separate Backup Supply Powering Scheme Main Supply V DDCORE Supply ADC, DAC Analog Comp . USB Transceivers VDDIN Voltage Regulator VDDOUT VDDCORE VDDIO VDDPLL VDDUTMIC VDDUTMII Note: Restrictions With main supply < 3.0V, USB is not usable. With main supply < 2.7V, MediaLB is not usable. With main supply < 2.0V, ADC, DAC and Analog comparator are not usable. With main supply and VDDIN > 3V, all peripherals are usable. When no separate backup supply for VDDIO is used, since the external voltage applied on VDDIO is kept, all of the I/O configurations (i.e., WKUP pin configuration) are maintained in Backup mode. When not using backup batteries, VDDIORDY is set so the user does not need to program it. SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 140

23.4.5 Supply Monitor

The SUPC embeds a supply monitor located in the VDDIO power supply and which monitors VDDIO power supply. The supply monitor can be used to prevent the processor from falling into an unpredictable state if the main power supply drops below a certain level. The threshold of the supply monitor is programmable in the SMTH field of the Supply Monitor Mode register (SUPC_SMMR). Refer to the section “Electrical Characteristics”. The supply monitor can also be enabled during one slow clock period on every one of either 32, 256 or 2048 slow clock periods, depending on the user selection. This is configured in the SUPC_SMMR.SMSMPL. Enabling the supply monitor for such reduced times divides the typical supply monitor power consumption by factors of 2, 16 and 128, respectively, if continuous monitoring of the VDDIO power supply is not required. A supply monitor detection generates either a reset of the core power supply or a wakeup of the core power supply. Generating a core reset when a supply monitor detection occurs is enabled by setting SUPC_SMMR.SMRSTEN. Waking up the core power supply when a supply monitor detection occurs can be enabled by setting the SMEN bit in the Wakeup Mode register (SUPC_WUMR). The SUPC provides two status bits in the SUPC_SR for the supply monitor that determine whether the last wakeup was due to the supply monitor:

SUPC_SR.SMOS provides real-time information, updated at each measurement cycle or updated at each slow clock cycle, if the measurement is continuous.
SUPC_SR.SMS provides saved information and shows a supply monitor detection has occurred since the last read of SUPC_SR. The SMS flag generates an interrupt if SUPC_SMMR.SMIEN is set. Figure 23-5. Supply Monitor Status Bit and Associated Interrupt Supply Monitor ON 3.3 V 0 V Threshold SMS and SUPC Interrupt Read SUPC_SR Periodic Sampling Continuous Sampling (SMSMPL = 1)

When the backup voltage VDDIO rises, the slow RC oscillator is powered up and the zero-power power-on reset cell maintains its output low as long as VDDIO has not reached its target voltage. During this period, the SUPC is reset. When the VDDIO voltage becomes valid and the zero-power power-on reset signal is released, a counter is started for five slow clock cycles. This is the time required for the slow RC oscillator to stabilize. After this time, the voltage regulator is enabled. The core power supply rises and the brownout detector provides the bodcore_in signal as soon as the core voltage VDDCORE is valid. This results in releasing the vddcore_nreset signal to the Reset Controller after the bodcore_in signal has been confirmed as being valid for at least one slow clock cycle. SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 142

Figure 23-6. Raising the VDDIO Power Supply Zero-Power Power-On Reset Cell output 22 - 42 kHz Slow RC Oscillator output Fast RC Oscillator output Backup Power Supply vr_on bodcore_in vddcore_nreset NRST (no ext. drive assumed) proc_nreset Note: After “proc_nreset” rising, the core starts fetching instructions from Flash. periph_nreset 7 x Slow Clock Cycles 3 x Slow Clock Cycles 2 x Slow Clock Cycles 6.5 x Slow Clock Cycles TON Voltage Regulator Zero-Power POR Core Power Supply RSTC.ERSTL (5 for startup slow RC + 2 for synchro.) default = 2

23.4.7 Core Reset

The Supply Controller manages the vddcore_nreset signal to the Reset Controller, as described in the "Backup Power Supply Reset" section. The vddcore_nreset signal is normally asserted before shutting down the core power supply and released as soon as the core power supply is correctly regulated. There are two additional sources which can be programmed to activate vddcore_nreset:

a supply monitor detection
a brownout detection

23.4.7.1 Supply Monitor Reset

The supply monitor is capable of generating a reset of the system. This is enabled by setting SUPC_SMMR.SMRSTEN. If SUPC_SMMR.SMRSTEN is set and if a supply monitor detection occurs, the vddcore_nreset signal is immediately activated for a minimum of one slow clock cycle.

23.4.7.2 Brownout Detector Reset

The brownout detector provides the bodcore_in signal to the SUPC. This signal indicates that the voltage regulation is operating as programmed. If this signal is lost for longer than 1 slow clock period while the voltage regulator is enabled, the SUPC asserts vddcore_nreset if SUPC_MR.BODRSTEN is written to ‘1’. If SUPC_MR.BODRSTEN is set and the voltage regulation is lost (output voltage of the regulator too low), the vddcore_nreset signal is asserted for a minimum of one slow clock cycle and then released if bodcore_in has been reactivated. SUPC_SR.BODRSTS indicates the source of the last reset. Until bodcore_in is deactivated, the vddcore_nreset signal remains active. SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 143

23.4.8 Controlling the SRAM Power Supply

The SUPC can be used to switch on or off the power supply of the backup SRAM by opening or closing the SRAM power switch. This power switch is controlled by SUPC_MR.BKUPRETON. However, the battery backup SRAM is automatically switched on when the core power supply is enabled, as the processor requires the SRAM as data memory space.

If SUPC_MR.BKUPRETON is written to ‘1’, there is no immediate effect, but the SRAM will be left powered when the SUPC enters Backup mode, thus retaining its content.
If SUPC_MR.BKUPRETON is written to ‘0’, there is no immediate effect, but the SRAM will be switched off when the SUPC enters Backup mode. The SRAM is automatically switched on when Backup mode is exited.

23.4.9 Wakeup Sources

The wakeup events allow the device to exit Backup mode. When a wakeup event is detected, the SUPC performs a sequence that automatically reenables the core power supply. Figure 23-7. Wakeup Sources WKUP13 WKUPEN13WKUPT13 WKUPEN1 WKUPEN0 Debouncer SLCK WKUPDBC WKUPS RTCEN rtc_alarm SMEN sm_out Core Supply Restart WKUPIS0 WKUPIS1 WKUPIS13 WKUPT0 WKUPT1 WKUP0 WKUP1 RTTEN rtt_alarm Debouncer RTCOUT0 LPDBC Debouncer LPDBC RTCOUT0 LPDBCS0 LPDBCS1LPDBCEN1 WKUPT1 LPDBCEN0 WKUPT0 Falling/Rising Edge Detect Low-power Tamper Detection Logic GPBR Clear LPDBCCLR LPDBCS1 LPDBCS0 Falling/Rising Edge Detect Falling/Rising Edge Detect Falling/Rising Edge Detect Falling/Rising Edge Detect

23.4.9.1 Wakeup Inputs

The wakeup inputs, WKUPx, can be programmed to perform a wakeup of the core power supply. Each input can be enabled by writing a ‘1’ to the corresponding bit, WKUPENx, in the Wakeup Inputs register (SUPC_WUIR). The wakeup level can be selected with the corresponding polarity bit, WKUPTx, also located in SUPC_WUIR. The resulting signals are wired-ORed to trigger a debounce counter, which is programmed with SUPC_WUMR.WKUPDBC. This field selects a debouncing period of 3, 32, 512, 4,096 or 32,768 slow clock cycles. The duration of these periods corresponds, respectively, to about 100 μs, about 1 ms, about 16 ms, about 128 ms and about 1 second (for a typical slow clock frequency of 32 kHz). Programming SUPC_WUMR.WKUPDBC to 0 selects an immediate wakeup, i.e., an enabled WKUP pin must be active according to its polarity during a minimum of one slow clock period to wake up the core power supply. SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 144

If an enabled WKUP pin is asserted for a duration longer than the debouncing period, a wakeup of the core power supply is started and the signals, WKUP0 to WKUPx as shown in “Wakeup Sources”, are latched in SUPC_SR. This allows the user to identify the source of the wakeup. However, if a new wakeup condition occurs, the primary information is lost. No new wakeup can be detected since the primary wakeup condition has disappeared. Before instructing the system to enter Backup mode, if the field SUPC_WUMR.WKUPDBC > 0, it must be checked that none of the WKUPx pins that are enabled for a wakeup (exit from Backup mode) holds an active polarity. This is checked by reading the pin status in the PIO Controller. If SUPC_WUIR.WKUPENx=1 and the pin WKUPx holds an active polarity, the system must not be instructed to enter Backup mode. Figure 23-8. Entering and Exiting Backup Mode with a WKUP Pin WKUPx WKUPTx=0 Active BACKUP Active BACKUP Active BACKUPSystem Edge detect + debounce time Edge detect + debounce time active runtime active runtime VROFF=1VROFF=1 Check WKUPx status Check WKUPx status WKUPDBC > 0

23.4.9.2 Low-power Tamper Detection and Anti-Tampering

Low-power debouncer inputs (WKUP0, WKUP1) can be used for tamper detection. If the tamper sensor is biased through a resistor and constantly driven by the power supply, this leads to power consumption as long as the tamper detection switch is in its active state. To prevent power consumption when the switch is in active state, the tamper sensor circuitry must be intermittently powered, and thus a specific waveform must be applied to the sensor circuitry. The waveform is generated using RTCOUTx in all modes including Backup mode. Refer to the section “Real-Time Clock (RTC)” for waveform generation. Separate debouncers are embedded, one for WKUP0 input, one for WKUP1 input. The WKUP0 and/or WKUP1 inputs perform a system wakeup upon tamper detection. This is enabled by setting SUPC_WUMR.LPDBCEN0/1. WKUP0 and/or WKUP1 inputs can also be used when VDDCORE is powered to detect a tamper. When SUPC_WUMR.LPDBCENx is written to ‘1’, WKUPx pins must not be configured to act as a debouncing source for the WKUPDBC counter (WKUPENx must be cleared in SUPC_WUIR). Low-power tamper detection or debounce requires RTC output (RTCOUTx) to be configured to generate a duty cycle programmable pulse (i.e., OUT0 = 0x7 in RTC_MR) in order to create the sampling points of both debouncers. The sampling point is the falling edge of the RTCOUTx waveform. The following figure shows an example of an application where two tamper switches are used. RTCOUTx powers the external pull-up used by the tamper sensor circuitry. SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 145

Figure 23-11. Using WKUP Pins Without RTCOUTx Pins MCU WKUP0 WKUP1 VDDIO Pull-up Resistor Pull-up Resistor GND GND GND Related Links 27. Real-time Clock (RTC)

23.4.9.3 Clock Alarms

The RTC and the RTT alarms can generate a wakeup of the core power supply. This can be enabled by setting, respectively, SUPC_WUMR.RTCEN and SUPC_WUMR.RTTEN. The Supply Controller does not provide any status as the information is available in the user interface of either the Real-Time Timer or the Real-Time Clock.

23.4.9.4 Supply Monitor Detection

The supply monitor can generate a wakeup of the core power supply. See "Supply Monitor".

23.4.10 Register Write Protection

To prevent any single software error from corrupting SYSC behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the ”System Controller Write Protection Mode Register” (SYSC_WPMR). The following registers can be write-protected:

RSTC Mode Register (1)
RTT Mode Register (2)
RTT Alarm Register (2)
RTC Control Register (3)
RTC Mode Register (3)
RTC Time Alarm Register (3)
RTC Calendar Alarm Register (3)
General Purpose Backup Registers (4)
Supply Controller Control Register
Supply Controller Supply Monitor Mode Register
Supply Controller Mode Register
Supply Controller Wakeup Mode Register
Supply Controller Wakeup Inputs Register SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 147

Notes: 1. See the section "Reset Controller (RSTC)". 2. See the section "Real Time Timer (RTT)". 3. See the section "Real Time Clock (RTC)". 4. See the section "General Purpose Backup Registers (GPBR)".

23.4.11 Register Bits in Backup Domain (VDDIO)

The following configuration registers, or certain bits of the registers, are physically located in the product backup domain:

RSTC Mode Register (all bits) (1)
RTT Mode Register (all bits) (2)
RTT Alarm Register (all bits) (2)
RTC Control Register (all bits) (3)
RTC Mode Register (all bits) (3)
RTC Time Alarm Register (all bits) (3)
RTC Calendar Alarm Register (all bits) (3)
General Purpose Backup Registers (all bits) (4)
Supply Controller Control Register (see register description for details)
Supply Controller Supply Monitor Mode Register (all bits)
Supply Controller Mode Register (see register description for details)
Supply Controller Wakeup Mode Register (all bits)
Supply Controller Wakeup Inputs Register (all bits)
Supply Controller Status Register (all bits) Notes: 1. See the section "Reset Controller (RSTC)". 2. See the section "Real Time Timer (RTT)". 3. See the section "Real Time Clock (RTC)". 4. See the section "General Purpose Backup Registers (GPBR)". SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 148

23.5 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 SUPC_CR 7:0 XTALSEL VROFF 15:8 23:16 31:24 KEY[7:0] 0x04 SUPC_SMMR 7:0 SMTH[3:0] 15:8 SMIEN SMRSTEN SMSMPL[2:0] 23:16 31:24 0x08 SUPC_MR 7:0 15:8 ONREG BODDIS BODRSTEN 23:16 OSCBYPASS BKUPRETON 31:24 KEY[7:0] 0x0C SUPC_WUMR 7:0 LPDBCCLR LPDBCEN1 LPDBCEN0 RTCEN RTTEN SMEN 15:8 WKUPDBC[2:0] 23:16 LPDBC[2:0] 31:24 0x10 SUPC_WUIR 7:0 WKUPEN[7:0] 15:8 WKUPEN[13:8] 23:16 WKUPT[7:0] 31:24 WKUPT[13:8] 0x14 SUPC_SR 7:0 OSCSEL SMOS SMS SMRSTS BODRSTS SMWS WKUPS 15:8 LPDBCS1 LPDBCS0 23:16 WKUPIS[7:0] 31:24 WKUPIS[13:8] 0x18 ... 0xD3 Reserved 0xD4 SYSC_WPMR 7:0 WPEN 15:8 WPKEY[7:0] 23:16 WPKEY[15:8] 31:24 WPKEY[23:16] SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 149

23.5.1 Supply Controller Control Register

Name: SUPC_CR Offset: 0x00 Property: Write-only Bit 31 30 29 28 27 26 25 24 KEY[7:0] Access W W W W W W W W Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 XTALSEL VROFF Access W W Reset Bits 31:24 – KEY[7:0] Password Value Name Description 0xA5 PASSWD Writing any other value in this field aborts the write operation. Bit 3 – XTALSEL Crystal Oscillator Select Note: This bit is located in the VDDIO domain. Value Description 0 (NO_EFFECT): No effect. 1 (CRYSTAL_SEL): If KEY is correct, XTALSEL switches the slow clock on the 32.768 kHz crystal oscillator output. Bit 2 – VROFF Voltage Regulator Off Note: This bit is located in the VDDIO domain. Value Description 0 (NO_EFFECT): No effect. 1 (STOP_VREG): If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 150

23.5.2 Supply Controller Supply Monitor Mode Register

Name: SUPC_SMMR Offset: 0x04 Reset: 0x00000000 Property: Read/Write This register is located in the VDDIO domain. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 SMIEN SMRSTEN SMSMPL[2:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SMTH[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 13 – SMIEN Supply Monitor Interrupt Enable Value Description 0 (NOT_ENABLE): The SUPC interrupt signal is not affected when a supply monitor detection occurs. 1 (ENABLE): The SUPC interrupt signal is asserted when a supply monitor detection occurs. Bit 12 – SMRSTEN Supply Monitor Reset Enable Value Description 0 (NOT_ENABLE): The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. 1 (ENABLE): The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. Bits 10:8 – SMSMPL[2:0] Supply Monitor Sampling Period Value Name Description 0x0 SMD Supply Monitor disabled 0x1 CSM Continuous Supply Monitor 0x2 32SLCK Supply Monitor enabled one SLCK period every 32 SLCK periods 0x3 256SLCK Supply Monitor enabled one SLCK period every 256 SLCK periods 0x4 2048SLCK Supply Monitor enabled one SLCK period every 2,048 SLCK periods Bits 3:0 – SMTH[3:0] Supply Monitor Threshold Selects the threshold voltage of the supply monitor. Refer to the section “Electrical Characteristics” for voltage values. SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 151

23.5.3 Supply Controller Mode Register

Name: SUPC_MR Offset: 0x08 Reset: 0x00005A00 Property: Read/Write Bit 31 30 29 28 27 26 25 24 KEY[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OSCBYPASS BKUPRETON Access R/W R/W Reset 0 0 Bit 15 14 13 12 11 10 9 8 ONREG BODDIS BODRSTEN Access R/W R/W R/W Reset 1 0 1 Bit 7 6 5 4 3 2 1 0 Access Reset Bits 31:24 – KEY[7:0] Password Key Value Name Description 0xA5 PASSWD Writing any other value in this field aborts the write operation. Bit 20 – OSCBYPASS Oscillator Bypass Note: This bit is located in the VDDIO domain. Value Description 0 (NO_EFFECT): No effect. Clock selection depends on the value of SUPC_CR.XTALSEL. 1 (BYPASS): The 32.768 kHz crystal oscillator is bypassed if SUPC_CR.XTALSEL is set. OSCBYPASS must be set prior to setting XTALSEL. Bit 17 – BKUPRETON SRAM On In Backup Mode Value Description 0 SRAM (Backup) switched off in Backup mode. 1 SRAM (Backup) switched on in Backup mode. Note: This bit is located in the VDDIO domain. Bit 14 – ONREG Voltage Regulator Enable Note: This bit is located in the VDDIO domain. Value Description 0 (ONREG_UNUSED): Internal voltage regulator is not used (external power supply is used). 1 (ONREG_USED): Internal voltage regulator is used. Bit 13 – BODDIS Brownout Detector Disable Note: This bit is located in the VDDIO domain. Value Description 0 (ENABLE): The core brownout detector is enabled. SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 152

1 (DISABLE): The core brownout detector is disabled. Bit 12 – BODRSTEN Brownout Detector Reset Enable Note: This bit is located in the VDDIO domain. Value Description 0 (NOT_ENABLE): The core reset signal vddcore_nreset is not affected when a brownout detection occurs. 1 (ENABLE): The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 153

23.5.4 Supply Controller Wakeup Mode Register

Name: SUPC_WUMR Offset: 0x0C Reset: 0x00000000 Property: Read/Write This register is located in the VDDIO domain. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 LPDBC[2:0] Access R/W R/W R/W Reset 0 0 0 Bit 15 14 13 12 11 10 9 8 WKUPDBC[2:0] Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 LPDBCCLR LPDBCEN1 LPDBCEN0 RTCEN RTTEN SMEN Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bits 18:16 – LPDBC[2:0] Low-power Debouncer Period Value Name Description 0 DISABLE Disables the low-power debouncers. 1 2_RTCOUT WKUP0/1 in active state for at least 2 RTCOUTx clock periods 2 3_RTCOUT WKUP0/1 in active state for at least 3 RTCOUTx clock periods 3 4_RTCOUT WKUP0/1 in active state for at least 4 RTCOUTx clock periods 4 5_RTCOUT WKUP0/1 in active state for at least 5 RTCOUTx clock periods 5 6_RTCOUT WKUP0/1 in active state for at least 6 RTCOUTx clock periods 6 7_RTCOUT WKUP0/1 in active state for at least 7 RTCOUTx clock periods 7 8_RTCOUT WKUP0/1 in active state for at least 8 RTCOUTx clock periods Bits 14:12 – WKUPDBC[2:0] Wakeup Inputs Debouncer Period Value Name Description 0 IMMEDIATE Immediate, no debouncing, detected active at least on one Slow Clock edge. 1 3_SLCK WKUPx shall be in its active state for at least 3 SLCK periods 2 32_SLCK WKUPx shall be in its active state for at least 32 SLCK periods 3 512_SLCK WKUPx shall be in its active state for at least 512 SLCK periods 4 4096_SLCK WKUPx shall be in its active state for at least 4,096 SLCK periods 5 32768_SLCK WKUPx shall be in its active state for at least 32,768 SLCK periods Bit 7 – LPDBCCLR Low-power Debouncer Clear Value Description 0 (NOT_ENABLE): A low-power debounce event does not create an immediate clear on the first half of GPBR registers. 1 (ENABLE): A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 154

Bit 6 – LPDBCEN1 Low-power Debouncer Enable WKUP1 Value Description 0 (NOT_ENABLE): The WKUP1 input pin is not connected to the low-power debouncer. 1 (ENABLE): The WKUP1 input pin is connected to the low-power debouncer and forces a system wakeup. Bit 5 – LPDBCEN0 Low-power Debouncer Enable WKUP0 Value Description 0 (NOT_ENABLE): The WKUP0 input pin is not connected to the low-power debouncer. 1 (ENABLE): The WKUP0 input pin is connected to the low-power debouncer and forces a system wakeup. Bit 3 – RTCEN Real-time Clock Wakeup Enable Value Description 0 (NOT_ENABLE): The RTC alarm signal has no wakeup effect. 1 (ENABLE): The RTC alarm signal forces the wakeup of the core power supply. Bit 2 – RTTEN Real-time Timer Wakeup Enable Value Description 0 (NOT_ENABLE): The RTT alarm signal has no wakeup effect. 1 (ENABLE): The RTT alarm signal forces the wakeup of the core power supply. Bit 1 – SMEN Supply Monitor Wakeup Enable Value Description 0 (NOT_ENABLE): The supply monitor detection has no wakeup effect. 1 (ENABLE): The supply monitor detection forces the wakeup of the core power supply. SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 155

23.5.5 Supply Controller Wakeup Inputs Register

Name: SUPC_WUIR Offset: 0x10 Reset: 0x00000000 Property: Read/Write This register is located in the VDDIO domain. This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). Bit 31 30 29 28 27 26 25 24 WKUPT[13:8] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 WKUPT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 – Bit 15 14 13 12 11 10 9 8 WKUPEN[13:8] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WKUPEN[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 – Bits 29:16 – WKUPT[13:0] Wakeup Input Type ('x' = 0-13) Value Description 0 (LOW): A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding wakeup input forces the wakeup of the core power supply. 1 (HIGH): A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding wakeup input forces the wakeup of the core power supply. Bits 13:0 – WKUPEN[13:0] Wakeup Input Enablex ('x' = 0-13) Value Description 0 (DISABLE): The corresponding wakeup input has no wakeup effect. 1 (ENABLE): The corresponding wakeup input is enabled for a wakeup of the core power supply. SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 156

23.5.6 Supply Controller Status Register

Name: SUPC_SR Offset: 0x14 Reset: 0x00000000 Property: Read-only Note: Because of the asynchronism between the Slow Clock (SLCK) and the System Clock (MCK), the status register flag reset is taken into account only 2 slow clock cycles after the read of the SUPC_SR. This register is located in the VDDIO domain. Bit 31 30 29 28 27 26 25 24 WKUPIS[13:8] Access R R R R R R Reset 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 WKUPIS[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 LPDBCS1 LPDBCS0 Access R R Reset 0 0 Bit 7 6 5 4 3 2 1 0 OSCSEL SMOS SMS SMRSTS BODRSTS SMWS WKUPS Access R R R R R R R Reset 0 0 0 0 0 0 0 Bits 29:16 – WKUPIS[13:0] WKUPx ('x' = 0-13) Input Status (cleared on read) Value Description 0 (DIS): The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. 1 (EN): The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. Bit 14 – LPDBCS1 Low-power Debouncer Wakeup Status on WKUP1 (cleared on read) Value Description 0 (NO): No wakeup due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. 1 (PRESENT): At least one wakeup due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. Bit 13 – LPDBCS0 Low-power Debouncer Wakeup Status on WKUP0 (cleared on read) Value Description 0 (NO): No wakeup due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. 1 (PRESENT): At least one wakeup due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. Bit 7 – OSCSEL 32-kHz Oscillator Selection Status Value Description 0 (RC): The slow clock, SLCK, is generated by the slow RC oscillator. 1 (CRYST): The slow clock, SLCK, is generated by the 32.768 kHz crystal oscillator. SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 157

Bit 6 – SMOS Supply Monitor Output Status Value Description 0 (HIGH): The supply monitor detected VDDIO higher than its threshold at its last measurement. 1 (LOW): The supply monitor detected VDDIO lower than its threshold at its last measurement. Bit 5 – SMS Supply Monitor Status (cleared on read) Value Description 0 (NO): No supply monitor detection since the last read of SUPC_SR. 1 (PRESENT): At least one supply monitor detection since the last read of SUPC_SR. Bit 4 – SMRSTS Supply Monitor Reset Status (cleared on read) Value Description 0 (NO): No supply monitor detection has generated a core reset since the last read of the SUPC_SR. 1 (PRESENT): At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. Bit 3 – BODRSTS Brownout Detector Reset Status (cleared on read) When the voltage remains below the defined threshold, there is no rising edge event at the output of the brownout detection cell. The rising edge event occurs only when there is a voltage transition below the threshold. Value Description 0 (NO): No core brownout rising edge event has been detected since the last read of the SUPC_SR. 1 (PRESENT): At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. Bit 2 – SMWS Supply Monitor Detection Wakeup Status (cleared on read) Value Description 0 (NO): No wakeup due to a supply monitor detection has occurred since the last read of SUPC_SR. 1 (PRESENT): At least one wakeup due to a supply monitor detection has occurred since the last read of SUPC_SR. Bit 1 – WKUPS WKUP Wakeup Status (cleared on read) Value Description 0 (NO): No wakeup due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. 1 (PRESENT): At least one wakeup due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 158

23.5.7 System Controller Write Protection Mode Register

Name: SYSC_WPMR Offset: 0xD4 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 WPKEY[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 WPKEY[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 WPKEY[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WPEN Access R?W Reset 0 Bits 31:8 – WPKEY[23:0] Write Protection Key. Value Name Description 0x525443 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Bit 0 – WPEN Write Protection Enable See "Register Write Protection" for the list of registers that can be write-protected. Value Description 0 Disables the write protection if WPKEY corresponds to 0x525443 (“RTC” in ASCII). 1 Enables the write protection if WPKEY corresponds to 0x525443 (“RTC” in ASCII). SAMV71Q21RT Supply Controller (SUPC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 159

Watchdog Timer (WDT)

24.1 Description

The Watchdog Timer (WDT) is used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock around 32 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in Debug mode or Sleep mode (Idle mode).

24.2 Embedded Characteristics

12-bit Key-protected Programmable Counter
Watchdog Clock is Independent from Processor Clock
Provides Reset or Interrupt Signals to the System
Counter May Be Stopped while the Processor is in Debug State or in Idle Mode

24.3 Block Diagram

Figure 24-1. Watchdog Timer Block Diagram = 0 set resetread WDT_SR or reset wdt_fault (to Reset Controller) set reset WDFIEN wdt_int WDT_MR SLCK1/128 12-bit Down Counter Current Value WDD WDT_MR <= WDD WDV WDRSTT WDT_MR WDT_CR reload WDUNF WDERR reload write WDT_MR WDT_MR WDRSTEN SAMV71Q21RT Watchdog Timer (WDT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 160

24.4 Functional Description

The Watchdog Timer is used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the slow clock divided by 128 to establish the maximum watchdog period to be 16 seconds (with a typical slow clock of 32.768 kHz). After a processor reset, the value of WDV is 0xFFF, corresponding to the maximum value of the counter with the external reset generation enabled (field WDRSTEN at 1 after a backup reset). This means that a default watchdog is running at reset, i.e., at power-up. The user can either disable the WDT by setting bit WDT_MR.WDDIS or reprogram the WDT to meet the maximum watchdog period the application requires. When setting the WDDIS bit, and while it is set, the fields WDV and WDD must not be modified. If the watchdog is restarted by writing into the Control Register (WDT_CR), WDT_MR must not be programmed during a period of time of three slow clock periods following the WDT_CR write access. In any case, programming a new value in WDT_MR automatically initiates a restart instruction. WDT_MR can be written only once. Only a processor reset resets it. Writing WDT_MR reloads the timer with the newly programmed mode parameters. In normal operation, the user reloads the watchdog at regular intervals before the timer underflow occurs, by setting bit WDT_CR.WDRSTT. The watchdog counter is then immediately reloaded from WDT_MR and restarted, and the slow clock 128 divider is reset and restarted. WDT_CR is write-protected. As a result, writing WDT_CR without the correct hard-coded key has no effect. If an underflow does occur, the “wdt_fault” signal to the Reset Controller is asserted if bit WDT_MR.WDRSTEN is set. Moreover, the bit WDUNF is set in the Status Register (WDT_SR). The reload of the watchdog must occur while the watchdog counter is within a window between 0 and WDD. WDD is defined in WDT_MR. Any attempt to restart the watchdog while the watchdog counter is between WDV and WDD results in a watchdog error, even if the watchdog is disabled. The bit WDT_SR.WDERR is updated and the “wdt_fault” signal to the Reset Controller is asserted. Note that this feature can be disabled by programming a WDD value greater than or equal to the WDV value. In such a configuration, restarting the Watchdog Timer is permitted in the whole range [0; WDV] and does not generate an error. This is the default configuration on reset (the WDD and WDV values are equal). The status bits WDUNF (Watchdog Underflow) and WDERR (Watchdog Error) trigger an interrupt, provided the bit WDT_MR.WDFIEN is set. The signal “wdt_fault” to the Reset Controller causes a watchdog reset if the WDRSTEN bit is set as already explained in the Reset Controller documentation. In this case, the processor and the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset. If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault” signal to the reset controller is deasserted. Writing WDT_MR reloads and restarts the down counter. While the processor is in debug state or in Sleep mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in WDT_MR. SAMV71Q21RT Watchdog Timer (WDT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 161

Figure 24-2. Watchdog Behavior WDV WDD WDT_CR.WDRSTT=1 Watchdog Fault Normal behavior Watchdog Error Watchdog Underflow FFF if WDRSTEN is 1 if WDRSTEN is 0 Forbidden Window Permitted Window SAMV71Q21RT Watchdog Timer (WDT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 162

24.5 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 WDT_CR 7:0 WDRSTT 15:8 23:16 31:24 KEY[7:0] 0x04 WDT_MR 7:0 WDV[7:0] 15:8 WDDIS WDRSTEN WDFIEN WDV[11:8] 23:16 WDD[7:0] 31:24 WDIDLEHLT WDDBGHLT WDD[11:8] 0x08 WDT_SR 7:0 WDERR WDUNF 15:8 23:16 31:24 SAMV71Q21RT Watchdog Timer (WDT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 163

24.5.1 Watchdog Timer Control Register

Name: WDT_CR Offset: 0x00 Reset: – Property: Write-only The WDT_CR register values must not be modified within three slow clock periods following a restart of the watchdog performed by a write access in WDT_CR. Any modification will cause the watchdog to trigger an end of period earlier than expected. Bit 31 30 29 28 27 26 25 24 KEY[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 – Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 WDRSTT Access W Reset – Bits 31:24 – KEY[7:0] Password Value Name Description 0xA5 PASSWD Writing any other value in this field aborts the write operation. Bit 0 – WDRSTT Watchdog Restart Value Description 0 No effect. 1 Restarts the watchdog if KEY is written to 0xA5. SAMV71Q21RT Watchdog Timer (WDT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 164

24.5.2 Watchdog Timer Mode Register

Name: WDT_MR Offset: 0x04 Reset: 0x3FFF2FFF Property: Read/Write Once The first write access prevents any further modification of the value of this register. Read accesses remain possible. The WDT_MR register values must not be modified within three slow clock periods following a restart of the watchdog performed by a write access in WDT_CR. Any modification will cause the watchdog to trigger an end of period earlier than expected. Bit 31 30 29 28 27 26 25 24 WDIDLEHLT WDDBGHLT WDD[11:8] Access R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 Bit 23 22 21 20 19 18 17 16 WDD[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 WDDIS WDRSTEN WDFIEN WDV[11:8] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 1 0 1 1 1 1 Bit 7 6 5 4 3 2 1 0 WDV[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 29 – WDIDLEHLT Watchdog Idle Halt Value Description 0 The watchdog runs when the system is in idle state. 1 The watchdog stops when the system is in idle state. Bit 28 – WDDBGHLT Watchdog Debug Halt Value Description 0 The watchdog runs when the processor is in debug state. 1 The watchdog stops when the processor is in debug state. Bits 27:16 – WDD[11:0] Watchdog Delta Value Defines the permitted range for reloading the Watchdog Timer. If the Watchdog Timer value is less than or equal to WDD, setting bit WDT_CR.WDRSTT restarts the timer. If the Watchdog Timer value is greater than WDD, setting bit WDT_CR.WDRSTT causes a watchdog error. Bit 15 – WDDIS Watchdog Disable When setting the WDDIS bit, and while it is set, the fields WDV and WDD must not be modified. Value Description 0 Enables the Watchdog Timer. 1 Disables the Watchdog Timer. Bit 13 – WDRSTEN Watchdog Reset Enable Value Description 0 A watchdog fault (underflow or error) has no effect on the resets. SAMV71Q21RT Watchdog Timer (WDT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 165

1 A watchdog fault (underflow or error) triggers a watchdog reset. Bit 12 – WDFIEN Watchdog Fault Interrupt Enable Value Description 0 A watchdog fault (underflow or error) has no effect on interrupt. 1 A watchdog fault (underflow or error) asserts interrupt. Bits 11:0 – WDV[11:0] Watchdog Counter Value Defines the value loaded in the 12-bit watchdog counter. SAMV71Q21RT Watchdog Timer (WDT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 166

24.5.3 Watchdog Timer Status Register

Name: WDT_SR Offset: 0x08 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 WDERR WDUNF Access R R Reset 0 0 Bit 1 – WDERR Watchdog Error (cleared on read) Value Description 0 No watchdog error occurred since the last read of WDT_SR. 1 At least one watchdog error occurred since the last read of WDT_SR. Bit 0 – WDUNF Watchdog Underflow (cleared on read) Value Description 0 No watchdog underflow occurred since the last read of WDT_SR. 1 At least one watchdog underflow occurred since the last read of WDT_SR. SAMV71Q21RT Watchdog Timer (WDT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 167

Reinforced Safety Watchdog Timer (RSWDT)

25.1 Description

The Reinforced Safety Watchdog Timer (RSWDT) works in parallel with the Watchdog Timer (WDT) to reinforce safe watchdog operations. The RSWDT can be used to reinforce the safety level provided by the WDT in order to prevent system lock-up if the software becomes trapped in a deadlock. The RSWDT works in a fully operable mode, independent of the WDT. Its clock source is automatically selected from either the Slow RC oscillator clock, or from the Main RC oscillator divided clock to get an equivalent Slow RC oscillator clock. If the WDT clock source (for example, the 32 kHz crystal oscillator) fails, the system lock-up is no longer monitored by the WDT because the RSWDT performs the monitoring. Thus, there is no lack of safety regardless of the external operating conditions. The RSWDT shares the same features as the WDT (i.e., a 12-bit down counter that allows a watchdog period of up to 16 seconds with slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in Debug mode or Idle mode.

25.2 Embedded Characteristics

Automatically Selected Reliable RSWDT Clock Source (independent of WDT clock source)
12-bit Key-protected Programmable Counter
Provides Reset or Interrupt Signals to the System
Counter may be Stopped While Processor is in Debug State or Idle Mode SAMV71Q21RT Reinforced Safety Watchdog Timer (RSWDT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 168

25.3 Block Diagram

Figure 25-1. Reinforced Safety Watchdog Timer Block Diagram = 0 1 0 read RSWDT_SR or reset set reset slow RC clock 12-bit Down Counter Current Value WDV WDRSTT RSWDT_MR RSWDT_CR reload WDUNF reload write RSWDT_MR main RC clock divider main RC frequency Automatic selection [CKGR_MOR.MOSCRCEN = 0 and (WDT_MR.WDDIS or SUPC_MR.XTALSEL = 1)] rswdt_fault (to Reset Controller) (ORed with wdt_fault) WDFIEN rswdt_int RSWDT_MR RSWDT_MR WDRSTEN

25.4 Functional Description

The RSWDT is supplied by VDDCORE. The RSWDT is initialized with default values on processor reset or on a power-on sequence and is disabled (its default mode) under such conditions. The RSWDT must not be enabled if the WDT is disabled. The Main RC oscillator divided clock is selected if the Main RC oscillator is already enabled by the application (CKGR_MOR.MOSCRCEN = 1) or if the WDT is driven by the Slow RC oscillator. The RSWDT is built around a 12-bit down counter, which is loaded with a slow clock value other than that of the slow clock in the WDT, defined in the WDV (Watchdog Counter Value) field of the Mode Register (RSWDT_MR). The RSWDT uses the slow clock divided by 128 to establish the maximum watchdog period to be 16 seconds (with a typical slow clock of 32.768 kHz). After a processor reset, the value of RSWDT_MR.WDV is 0xFFF, corresponding to the maximum value of the counter with the external reset generation enabled (RSWDT_MR.WDRSTEN = 1 after a backup reset). This means that a default watchdog is running at reset, i.e., at power-up. If the watchdog is restarted by writing into the Control Register (RSWDT_CR), the RSWDT_MR must not be programmed during a period of time of three slow clock periods following the RSWDT_CR write access. Programming a new value in the RSWDT_MR automatically initiates a restart instruction. RSWDT_MR can be written only once. Only a processor reset resets it. Writing RSWDT_MR reloads the timer with the newly programmed mode parameters. SAMV71Q21RT Reinforced Safety Watchdog Timer (RSWDT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 169

In normal operation, the user reloads the watchdog at regular intervals before the timer underflow occurs, by setting bit RSWDT_CR.WDRSTT. The watchdog counter is then immediately reloaded from the RSWDT_MR and restarted, and the slow clock 128 divider is reset and restarted. The RSWDT_CR is write-protected. As a result, writing RSWDT_CR without the correct hard-coded key has no effect. If an underflow does occur, the “wdt_fault” signal to the Reset Controller is asserted if RSWDT_MR.WDRSTEN is set. Moreover, WDUNF (Watchdog Underflow) is set in the Status Register (RSWDT_SR). The status bits WDUNF and WDERR trigger an interrupt, provided the WDFIEN bit is set in the RSWDT_MR. The signal “wdt_fault” to the Reset Controller causes a Watchdog reset if the WDRSTEN bit. For details, refer to the section “Reset Controller (RSTC)”. In this case, the processor and the RSWDT are reset, and the WDUNF and WDERR flags are reset. If a reset is generated, or if RSWDT_SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault” signal to the reset controller is deasserted Writing RSWDT_MR reloads and restarts the down counter. The RSWDT is disabled after any power-on sequence. While the processor is in Debug state or in Idle mode, the counter may be stopped depending on the value programmed for the WDIDLEHLT and WDDBGHLT bits in the RSWDT_MR. Figure 25-2. Watchdog Behavior WDV RSWDT_CR.WDRSTT = 1 Watchdog Fault Normal behavior Watchdog Underflow 0xFFF if WDRSTEN is 1 if WDRSTEN is 0 Related Links 26. Reset Controller (RSTC) SAMV71Q21RT Reinforced Safety Watchdog Timer (RSWDT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 170

25.5 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 RSWDT_CR 7:0 WDRSTT 15:8 23:16 31:24 KEY[7:0] 0x04 RSWDT_MR 7:0 WDV[7:0] 15:8 WDDIS WDRSTEN WDFIEN WDV[11:8] 23:16 ALLONES[7:0] 31:24 WDIDLEHLT WDDBGHLT ALLONES[11:8] 0x08 RSWDT_SR 7:0 WDUNF 15:8 23:16 31:24 SAMV71Q21RT Reinforced Safety Watchdog Timer (RSWDT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 171

25.5.1 Reinforced Safety Watchdog Timer Control Register

Name: RSWDT_CR Offset: 0x00 Property: Write-only Bit 31 30 29 28 27 26 25 24 KEY[7:0] Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 WDRSTT Access Reset Bits 31:24 – KEY[7:0] Password Value Name Description 0xC4 PASSWD Writing any other value in this field aborts the write operation. Bit 0 – WDRSTT Watchdog Restart Value Description 0 No effect. 1 Restarts the watchdog. SAMV71Q21RT Reinforced Safety Watchdog Timer (RSWDT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 172

25.5.2 Reinforced Safety Watchdog Timer Mode Register

Name: RSWDT_MR Offset: 0x04 Reset: 0x3FFFAFFF Property: Read/Write Once Note: The first write access prevents any further modification of the value of this register; read accesses remain possible. The WDV value must not be modified within three slow clock periods following a restart of the watchdog performed by means of a write access in the RSWDT_CR, else the watchdog may trigger an end of period earlier than expected. Bit 31 30 29 28 27 26 25 24 WDIDLEHLT WDDBGHLT ALLONES[11:8] Access Reset 1 1 1 1 1 1 Bit 23 22 21 20 19 18 17 16 ALLONES[7:0] Access Reset 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 WDDIS WDRSTEN WDFIEN WDV[11:8] Access Reset 1 1 0 1 1 1 1 Bit 7 6 5 4 3 2 1 0 WDV[7:0] Access Reset 1 1 1 1 1 1 1 1 Bit 29 – WDIDLEHLT Watchdog Idle Halt Value Description 0 The RSWDT runs when the system is in idle mode. 1 The RSWDT stops when the system is in idle state. Bit 28 – WDDBGHLT Watchdog Debug Halt Value Description 0 The RSWDT runs when the processor is in debug state. 1 The RSWDT stops when the processor is in debug state. Bits 27:16 – ALLONES[11:0] Must Always Be Written with 0xFFF Bit 15 – WDDIS Watchdog Disable Value Description 0 Enables the RSWDT. 1 Disables the RSWDT. Bit 13 – WDRSTEN Watchdog Reset Enable Value Description 0 A Watchdog fault (underflow or error) has no effect on the resets. 1 A Watchdog fault (underflow or error) triggers a watchdog reset. Bit 12 – WDFIEN Watchdog Fault Interrupt Enable Value Description 0 A Watchdog fault (underflow or error) has no effect on interrupt. SAMV71Q21RT Reinforced Safety Watchdog Timer (RSWDT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 173

1 A Watchdog fault (underflow or error) asserts interrupt. Bits 11:0 – WDV[11:0] Watchdog Counter Value Defines the value loaded in the 12-bit watchdog counter. SAMV71Q21RT Reinforced Safety Watchdog Timer (RSWDT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 174

25.5.3 Reinforced Safety Watchdog Timer Status Register

Name: RSWDT_SR Offset: 0x08 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 WDUNF Access Reset 0 Bit 0 – WDUNF Watchdog Underflow Value Description 0 No watchdog underflow occurred since the last read of RSWDT_SR. 1 At least one watchdog underflow occurred since the last read of RSWDT_SR. SAMV71Q21RT Reinforced Safety Watchdog Timer (RSWDT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 175

Reset Controller (RSTC)

26.1 Description

The Reset Controller (RSTC), driven by Power-On Reset (POR) cells, software, external reset pin and peripheral events, handles all the resets of the system without any external components. It reports which reset occurred last. The RSTC also drives simultaneously the external reset and the peripheral and processor resets.

26.2 Embedded Characteristics

Driven by embedded POR, software, external reset pin and peripheral events
Management of all system resets, including: – External devices through the NRST pin – Processor – Peripheral set
Reset source status: – Status of the last reset – Either VDDCORE and VDDIO POR, Software Reset, User Reset, Watchdog Reset
External reset signal control and shaping

26.3 Block Diagram

Figure 26-1. Reset Controller Block Diagram NRST Pin wd_fault SLCK Reset State Manager Reset Controller NRST Manager exter_nreset nrst_out user_reset From watchdog Processor and peripherals reset line RSTC interrupt line POR Backup Backup area reset SUPC VDDCORE reset SM Backup POR VDDCORE BOD VDDCORE SAMV71Q21RT Reset Controller (RSTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 176

26.4 Functional Description

26.4.1 Overview

The RSTC is made up of an NRST manager and a reset state manager. It runs at SLCK frequency and generates the following reset signals:

proc_nreset: Processor reset line (also resets the Watchdog Timer)
periph_nreset: Affects the whole set of embedded peripherals
nrst_out: Drives the NRST pin Note: proc_nreset and periph_nreset are driven in the same way. These reset signals are asserted by the RSTC, either on events generated by peripherals, events on the NRST pin, or on a software action. The reset state manager controls the generation of reset signals and provides a signal to the NRST manager when an assertion of the NRST pin is required. The NRST manager shapes the NRST assertion during a programmable time, thus controlling external device resets. The RSTC Mode register (RSTC_MR), used to configure the RSTC, is powered with VDDIO, so that its configuration is saved as long as VDDIO is on.

26.4.2 NRST Manager

The NRST manager samples the NRST input pin and drives this pin low when required by the reset state manager. The figure below shows the block diagram of the NRST manager. Figure 26-2. NRST Manager External Reset Timer URSTS URSTEN ERSTL exter_nreset URSTIEN RSTC_MR RSTC_MR RSTC_MR RSTC_SR NRSTL nrst_out NRST Other interrupt sources user_reset RSTC Interrupt line

26.4.2.1 NRST Signal or Interrupt

The NRST manager samples the NRST pin at SLCK speed. When the NRST line is low for more than three clock cycles, a User Reset is reported to the reset state manager. The NRST pin must be asserted for at least 1 SLCK clock cycle to ensure execution of a user reset. However, the NRST manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing a ‘0’ to RSTC_MR.URSTEN disables the User Reset trigger. The level of the pin NRST can be read at any time in the bit NRSTL in the RSTC Status Register (RSTC_SR). As soon as the NRST pin is asserted, RSTC_SR. URSTS is written to ‘1’. This bit is cleared only when the RSTC_SR is read. The RSTC can also be programmed to generate an interrupt instead of generating a reset. To do so, RSTC_MR.URSTIEN must be set.

26.4.2.2 NRST External Reset Control

The reset state manager asserts the signal exter_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST manager for a time programmed by RSTC_MR.ERSTL. This assertion duration, named External Reset Length, lasts 2(ERSTL+1) SLCK cycles. This gives the approximate duration of an assertion between 60 μs and 2 seconds. Note that ERSTL at ‘0’ defines a two-cycle duration for the NRST pulse. SAMV71Q21RT Reset Controller (RSTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 177

This feature allows the RSTC to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. RSTC_MR is backed up, making it possible to use the value of ERSTL to shape the system powerup reset for devices requiring a longer startup time than that of the MCU.

26.4.3 Reset States

The reset state manager handles the different reset sources and generates the internal reset signals. It reports the reset status in RSTTYP of the Status Register (RSTC_SR). The update of RSTC_SR.RSTTYP is performed when the processor reset is released.

26.4.3.1 General Reset

A general reset occurs when a VDDIO POR is detected, a brown out or a voltage regulation loss is detected by the Supply Controller. The vddcore_nreset signal is asserted by the Supply Controller when a general reset occurs. All the reset signals are released and RSTC_SR.RSTTYP reports a general reset. As the RSTC_MR is written to ‘0’, the NRST line rises two cycles after the vddcore_nreset, as ERSTL defaults at value 0x0. The figure below ilustrates how the general reset affects the reset signals. Figure 26-3. General Reset Timing Diagram SLCK Processor and Peripherals Reset Line NRST (nrst_out)

3 SLCK cycles

Freq. RSTTYP XXX 0x0 = General Reset XXX

6.5 SLCK cycles + 2 Main RC cycles

5 Main RC cycles

5 SLCK

2 SLCK cycles

26.4.3.2 Backup Reset

A backup reset occurs when the chip exits from Backup mode. While exiting Backup mode, the vddcore_nreset signal is asserted by the Supply Controller. Field RSTC_SR.RSTTYP is updated to report a backup reset.

26.4.3.3 Watchdog Reset

The watchdog reset is entered when a watchdog fault occurs. This reset lasts three SLCK cycles. When in watchdog reset, the processor reset and the peripheral reset are asserted. The NRST line is also asserted, depending on the value of RSTC_MR.ERSTL. However, the resulting low level on NRST does not result in a user reset state. SAMV71Q21RT Reset Controller (RSTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 178

The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDT_MR.WDRSTEN is written to ‘1’, the Watchdog Timer is always reset after a watchdog reset, and the Watchdog is enabled by default and with a period set to a maximum. When WDT_MR.WDRSTEN is written to ‘0’, the watchdog fault has no impact on the RSTC. After a watchdog overflow occurs, the report on the RSTC_SR.RSTTYP may differ (either WDT_RST or USER_RST) depending on the external components driving the NRST pin. For example, if the NRST line is driven through a resistor and a capacitor (NRST pin debouncer), the reported value is USER_RST if the low to high transition is greater than one SLCK cycle. Figure 26-4. Watchdog Reset Timing Diagram 0x2 = Watchdog Reset SLCK Processor and Peripherals Reset Line NRST (nrst_out) MCK Any Frequency. RSTTYP XXX Main RC Oscillator

3 SLCK cycles + 2 MCK cycles

Frequency. Inactive Inactive WDT Fault Min = 2 SLCK cycles if ERSTL=0 (e.g. 8 if ERSTL=2)

26.4.3.4 Software Reset

The RSTC offers commands to assert the different reset signals. These commands are performed by writing the Control register (RSTC_CR) with the following bits at ‘1’:

RSTC_CR.PROCRST: Writing a ‘1’ to PROCRST resets the processor and all the embedded peripherals, including the memory system and, in particular, the Remap Command.
RSTC_CR.EXTRST: Writing a ‘1’ to EXTRST asserts low the NRST pin during a time defined by the field RSTC_MR.ERSTL. The software reset is entered if at least one of these bits is written to ‘1’ by the software. All these commands can be performed independently or simultaneously. The software reset lasts three SLCK cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset has ended, i.e., synchronously to SLCK. If EXTRST is written to ‘1’, the nrst_out signal is asserted depending on the configuration of RSTC_MR.ERSTL. However, the resulting falling edge on NRST does not lead to a user reset. If and only if the RSTC_CR.PROCRST is written to ‘1’, the RSTC reports the software status in field RSTC_SR.RSTTYP. Other software resets are not reported in RSTTYP. As soon as a software operation is detected, RSTC_SR.SRCMP is written to ‘1’. SRCMP is cleared at the end of the software reset. No other software reset can be performed while SRCMP is written to ‘1’, and writing any value in the RSTC_CR has no effect. SAMV71Q21RT Reset Controller (RSTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 179

Figure 26-5. Software Reset Timing Diagram Write RSTC_CR NRST (nrst_out) if EXTRST=1 0x3 = Software Reset SLCK Processor and Peripherals Reset Line MCK Any Frequency. RSTTYP XXX Main RC Oscillator Frequency. Inactive Inactive Min = 2 SLCK cycles if ERSTL=0 (e.g. 8 if ERSTL=2) Up to 1 SLCK cycle RSTC_SR.SRCMP

26.4.3.5 User Reset

A user reset is generated when a low level is detected on the NRST pin and RSTC_MR.URSTEN is at ‘1’. The NRST input signal is resynchronized with SLCK to ensure proper behavior of the system. Thus, the NRST pin must be asserted for at least 1 SLCK clock cycle to ensure execution of a user reset. The user reset is triggered 2 SLCK cycles after a low level is detected on NRST. The processor reset and the peripheral reset are asserted. The user reset ends when NRST rises, after a two-cycle resynchronization time and a three-cycle processor startup. The processor clock is reenabled as soon as NRST is confirmed high. When the processor reset signal is released, RSTC_SR.RSTTYP is loaded with the value ‘4’, indicating a user reset. The NRST manager guarantees that the NRST line is asserted for External Reset Length SLCK cycles, as configured in RSTC_MR.ERSTL. However, if NRST does not rise after External Reset Length because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. SAMV71Q21RT Reset Controller (RSTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 180

Figure 26-6. User Reset Timing Diagram SLCK Processor and Peripherals Reset Line NRST (nrst_out) MCK Any Frequency. RSTTYP XXX Main RC Oscillator Active Active Inactive Inactive Any Frequency. Inactive Inactive NRST pin Min = 2 SLCK cycles if ERSTL=0 (e.g. 8 if ERSTL=2) 0x4 = User Reset

6 SLCK cycles

26.4.4 Reset State Priorities

The reset state manager manages the priorities among the different reset sources. The resets are listed in order of priority as follows: 1. General reset 2. Backup reset 3. Watchdog reset 4. Software reset 5. User reset Specific cases are listed below:

When in user reset: – A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. – A software reset is impossible, since the processor reset is being activated.
When in software reset: – A watchdog event has priority over the current state. – The NRST has no effect.
When in watchdog reset: – The processor reset is active and so a software reset cannot be programmed. – A user reset cannot be entered. SAMV71Q21RT Reset Controller (RSTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 181

26.4.5 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 RSTC_CR 7:0 EXTRST PROCRST 15:8 23:16 31:24 KEY[7:0] 0x04 RSTC_SR 7:0 URSTS 15:8 RSTTYP[2:0] 23:16 SRCMP NRSTL 31:24 0x08 RSTC_MR 7:0 URSTIEN URSTEN 15:8 ERSTL[3:0] 23:16 31:24 KEY[7:0] SAMV71Q21RT Reset Controller (RSTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 182

26.4.5.1 RSTC Control Register

Name: RSTC_CR Offset: 0x00 Property: Write-only Bit 31 30 29 28 27 26 25 24 KEY[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 – Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 EXTRST PROCRST Access W W Reset – – Bits 31:24 – KEY[7:0] System Reset Key Value Name Description 0xA5 PASSWD Writing any other value in this field aborts the write operation. Bit 3 – EXTRST External Reset Value Description 0 No effect. 1 If KEY = 0xA5, asserts the NRST pin. Bit 0 – PROCRST Processor Reset Value Description 0 No effect. 1 If KEY = 0xA5, resets the processor and all the embedded peripherals. SAMV71Q21RT Reset Controller (RSTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 183

26.4.5.2 RSTC Status Register

Name: RSTC_SR Offset: 0x04 Reset: 0x00000000 Property: Read-only The register reset value assumes that a general reset has been performed; it is subject to change if other types of reset are generated. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 SRCMP NRSTL Access R R Reset 0 0 Bit 15 14 13 12 11 10 9 8 RSTTYP[2:0] Access R R R Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 URSTS Access R Reset 0 Bit 17 – SRCMP Software Reset Command in Progress When set, this bit indicates that a software reset command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset. Value Description 0 No software command is being performed by the RSTC. The RSTC is ready for a software command. 1 A software reset command is being performed by the RSTC. The RSTC is busy. Bit 16 – NRSTL NRST Pin Level Registers the NRST pin level sampled on each MCK rising edge. Bits 10:8 – RSTTYP[2:0] Reset Type This field reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field. Value Name Description

0 GENERAL_RST First powerup reset

1 BACKUP_RST Return from Backup mode

2 WDT_RST Watchdog fault occurred

3 SOFT_RST Processor reset required by the software

4 USER_RST NRST pin detected low

5 – Reserved 6 – Reserved 7 – Reserved Bit 0 – URSTS User Reset Status A high-to-low transition of the NRST pin sets the URSTS. This transition is also detected on the MCK rising edge. If the user reset is disabled (URSTEN = 0 in RSTC_MR) and if the interrupt is enabled by RSTC_MR.URSTIEN, URSTS triggers an interrupt. Reading the RSTC_SR resets URSTS and clears the interrupt. SAMV71Q21RT Reset Controller (RSTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 184

0 No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. SAMV71Q21RT Reset Controller (RSTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 185

26.4.5.3 RSTC Mode Register

Name: RSTC_MR Offset: 0x08 Reset: 0x00000001 Property: Read/Write This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). Bit 31 30 29 28 27 26 25 24 KEY[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 ERSTL[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 URSTIEN URSTEN Access R/W R/W Reset 0 1 Bits 31:24 – KEY[7:0] Write Access Password Value Name Description 0xA5 PASSWD Writing any other value in this field aborts the write operation. Always reads as 0. Bits 11:8 – ERSTL[3:0] External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) SLCK cycles. This allows assertion duration to be programmed between 60 μs and 2 seconds. Note that synchronization cycles must also be considered when calculating the actual reset length as previously described. Bit 4 – URSTIEN User Reset Interrupt Enable Value Description 0 RSTC_SR.USRTS at ‘1’ has no effect on the RSTC interrupt line. 1 RSTC_SR.USRTS at ‘1’ asserts the RSTC interrupt line if URSTEN = 0. Bit 0 – URSTEN User Reset Enable Value Description 0 The detection of a low level on the NRST pin does not generate a user reset. 1 The detection of a low level on the NRST pin triggers a user reset. SAMV71Q21RT Reset Controller (RSTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 186

Real-time Clock (RTC)

27.1 Description

The Real-time Clock (RTC) peripheral is designed for very low power consumption. For optimal functionality, the RTC requires an accurate external 32.768 kHz clock, which can be provided by a crystal oscillator. It combines a complete time-of-day clock with alarm and a Gregorian or Persian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus. The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator. Updating time and calendar fields and configuring the alarm fields are performed by a parallel capture on the 32-bit data bus. An entry control is performed to avoid loading registers with incompatible BCD format data or with an incompatible date according to the current month/year/century. A clock divider calibration circuitry can be used to compensate for crystal oscillator frequency variations. An RTC output can be programmed to generate several waveforms, including a prescaled clock derived from 32.768 kHz.

27.2 Embedded Characteristics

Full Asynchronous Design for Ultra Low Power Consumption
Gregorian and Persian Modes Supported
Programmable Periodic Interrupt
Safety/security Features: – Valid Time and Date Programming Check – On-The-Fly Time and Date Validity Check
Counters Calibration Circuitry to Compensate for Crystal Oscillator Variations
Waveform Generation
Register Write Protection

27.3 Block Diagram

Figure 27-1. Real-time Clock Block Diagram User Interface

32768 Divider

TimeSlow Clock: SLCK System Bus Date RTC InterruptEntry Control Interrupt Control Clock Calibration RTCOUT0 RTCOUT1 Wave Generator Alarm SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 187

27.4 Product Dependencies

27.4.1 Power Management

The Real-time Clock is continuously clocked at 32.768 kHz. The Power Management Controller has no effect on RTC behavior.

27.4.2 Interrupt

Within the System Controller, the RTC interrupt is OR-wired with all the other module interrupts. Only one System Controller interrupt line is connected on one of the internal sources of the interrupt controller. RTC interrupt requires the interrupt controller to be programmed first. When a System Controller interrupt occurs, the service routine must first determine the cause of the interrupt. This is done by reading each status register of the System Controller peripherals successively.

27.5 Functional Description

The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds reported in RTC Time Register (RTC_TIMR). The valid year range is up to 2099 in Gregorian mode (or 1300 to 1499 in Persian mode). The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator. Corrections for leap years are included (all years divisible by 4 being leap years except 1900). This is correct up to the year 2099. The RTC can generate configurable waveforms on RTCOUT0/1 outputs.

27.5.1 Reference Clock

The reference clock is the Slow Clock (SLCK) which can be driven internally or by an external 32.768 kHz crystal. During low-power modes of the processor, the oscillator runs and power consumption is critical. The crystal selection must consider the current consumption for power saving and the frequency drift due to temperature effect on the circuit for time accuracy.

27.5.2 Timing

The RTC is updated in real time at one-second intervals in Normal mode for the counters of seconds, at one-minute intervals for the counter of minutes and so on. Due to the asynchronous operation of the RTC with respect to the rest of the chip, to be certain that the value read in the RTC registers (century, year, month, date, day, hours, minutes, seconds) are valid and stable, it is necessary to read these registers twice. If the data is the same both times, then it is valid. Therefore, a minimum of two and a maximum of three accesses are required.

27.5.3 Alarm

The RTC has five programmable fields: month, date, hours, minutes and seconds. Each of these fields can be enabled or disabled to match the alarm condition:

If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled) at a given month, date, hour/minute/second.
If only the “seconds” field is enabled, then an alarm is generated every minute. Depending on the combination of fields enabled, a large number of possibilities are available to the user ranging from minutes to 365/366 days. Hour, minute and second matching alarms (SECEN, MINEN, HOUREN) can be enabled independently of SEC, MIN, HOUR fields. SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 188

Note: To change one of the SEC, MIN, HOUR, DATE, MONTH fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to three accesses to the RTC_TIMALR or RTC_CALALR. The first access clears the enable corresponding to the field to change (SECEN, MINEN, HOUREN, DATEEN, MTHEN). If the field is already cleared, this access is not required. The second access performs the change of the value (SEC, MIN, HOUR, DATE, MONTH). The third access is required to re-enable the field by writing 1 in SECEN, MINEN, HOUREn, DATEEN, MTHEN fields.

27.5.4 Error Checking when Programming

Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year and century configured. If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed. This avoids any further side effects in the hardware. The same procedure is followed for the alarm. The following checks are performed: 1. Century (check if it is in range 19–20 or 13–14 in Persian mode) 2. Year (BCD entry check) 3. Date (check range 01–31) 4. Month (check if it is in BCD range 01–12, check validity regarding “date”) 5. Day (check range 1–7) 6. Hour (BCD checks: in 24-hour mode, check range 00–23 and check that AM/PM flag is not set if RTC is set in 24-hour mode; in 12-hour mode check range 01–12) 7. Minute (check BCD and range 00–59) 8. Second (check BCD and range 00–59) Note: If the 12-hour mode is selected by means of the RTC Mode Register (RTC_MR), a 12-hour value can be programmed and the returned value on RTC_TIMR will be the corresponding 24-hour value. The entry control checks the value of the AM/PM indicator (bit 22 of RTC_TIMR) to determine the range to be checked.

27.5.5 RTC Internal Free Running Counter Error Checking

To improve the reliability and security of the RTC, a permanent check is performed on the internal free running counters to report non-BCD or invalid date/time values. An error is reported by TDERR bit in the status register (RTC_SR) if an incorrect value has been detected. The flag can be cleared by setting the TDERRCLR bit in the Status Clear Command Register (RTC_SCCR). The TDERR error flag will be set again if the source of the error has not been cleared before clearing the TDERR flag. The clearing of the source of such error can be done by reprogramming a correct value on RTC_CALR and/or RTC_TIMR. The RTC internal free running counters may automatically clear the source of TDERR due to their roll-over (i.e., every 10 seconds for SECONDS[3:0] field in RTC_TIMR). In this case the TDERR is held high until a clear command is asserted by TDERRCLR bit in RTC_SCCR.

27.5.6 Updating Time/Calendar

27.5.6.1 Description

The update of the time/calendar must be synchronized on a second periodic event by either polling the RTC_SR.SEC status bit or by enabling the SECEN interrupt in the RTC_IER register. Once the second event occurs, the user must stop the RTC by setting the corresponding field in the Control Register (RTC_CR). Bit UPDTIM must be set to update time fields (hour, minute, second) and bit UPDCAL must be set to update calendar fields (century, year, month, date, day). The ACKUPD bit must then be read to 1 by either polling the RTC_SR or by enabling the ACKUPD interrupt in the RTC_IER. Once ACKUPD is read to 1, it is mandatory to clear this flag by writing the corresponding bit in the RTC_SCCR, after which the user can write to the Time Register, the Calendar Register, or both. Once the update is finished, the user must write UPDTIM and/or UPDCAL to 0 in the RTC_CR. SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 189

The timing sequence of the time/calendar update is described in the figure below. When entering the programming mode of the calendar fields, the time fields remain enabled and both the time and the calendar fields are stopped. This is due to the location of the calendar logical circuity (downstream for low-power considerations). It is highly recommended to prepare all the fields to be updated before entering programming mode. In successive update operations, the user must wait for at least one second after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these bits again. This is done by waiting for the SEC flag in the RTC_SR before setting the UPDTIM/UPDCAL bit. After resetting UPDTIM/UPDCAL, the SEC flag must also be cleared. Figure 27-2. Time/Calendar Update Timing Diagram 20 (counter stopped) 15 16 Clear ACKUPD bit Update request from SW Clear UPDTIM bit Update RTC_TIMR.SEC to 15 Sofware Time Line 1 2 43 RTC_SR.ACKUPD SEC Event Flag RTC_CR.UPDTIM RTC_TIMR.SEC 1Hz RTC Clock RTC BACK TO NORMAL MODE //// // // SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 190

Figure 27-3. Gregorian and Persian Modes Update Sequence Prepare Time or Calendar Fields Set UPDTIM and/or UPDCAL bit(s) in RTC_CR Read RTC_SR ACKUPD = 1? Clear ACKUPD bit in RTC_SCCR Update Time and/or Calendar values in RTC_TIMR/RTC_CALR Clear UPDTIM and/or UPDCAL bit in RTC_CR No Yes Begin End Polling or IRQ (if enabled) Wait for second periodic event SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 191

27.5.7 RTC Accurate Clock Calibration

The crystal oscillator that drives the RTC may not be as accurate as expected mainly due to temperature variation. The RTC is equipped with circuitry able to correct slow clock crystal drift. To compensate for possible temperature variations over time, this accurate clock calibration circuitry can be programmed on-the-fly and also programmed during application manufacturing, in order to correct the crystal frequency accuracy at room temperature (20–25°C). The typical clock drift range at room temperature is ±20 ppm. In the device operating temperature range, the 32.768 kHz crystal oscillator clock inaccuracy can be up to -200 ppm. The RTC clock calibration circuitry allows positive or negative correction in a range of 1.5 ppm to 1950 ppm. The calibration circuitry is fully digital. Thus, the configured correction is independent of temperature, voltage, process, etc., and no additional measurement is required to check that the correction is effective. If the correction value configured in the calibration circuitry results from an accurate crystal frequency measure, the remaining accuracy is bounded by the values listed below:

Below 1 ppm, for an initial crystal drift between 1.5 ppm up to 20 ppm, and from 30 ppm to 90 ppm
Below 2 ppm, for an initial crystal drift between 20 ppm up to 30 ppm, and from 90 ppm to 130 ppm
Below 5 ppm, for an initial crystal drift between 130 ppm up to 200 ppm The calibration circuitry does not modify the 32.768 kHz crystal oscillator clock frequency but it acts by slightly modifying the 1 Hz clock period from time to time. The correction event occurs every 1 + [(20 - (19 x HIGHPPM)) x CORRECTION] seconds. When the period is modified, depending on the sign of the correction, the 1 Hz clock period increases or reduces by around 4 ms. Depending on the CORRECTION, NEGPPM and HIGHPPM values configured in RTC_MR, the period interval between two correction events differs. Figure 27-4. Calibration Circuitry 32.768 kHz Oscillator Other Logic RTC Time/Calendar1Hz CORRECTION, HIGHPPMIntegrator Comparator Divider by 32768 Add 32.768 kHz NEGPPM Suppress SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 192

Figure 27-5. Calibration Circuitry Waveforms Time Monotonic 1 Hz Counter value 32.768 kHz -50 ppm 32.768 kHz +50 ppm Crystal frequency remains unadjusted Internal 1 Hz clock is adjusted Phase adjustment (~4 ms) User configurable period (integer multiple of 1s or 20s) Time -50 ppm -25 ppm -50 ppm correction period -25 ppm correction period Nominal 32.768 kHz Crystal clock Internally divided clock (256 Hz) Internally divided clock (128 Hz) Clock pulse periodically suppressed when correction period elapses 128 Hz clock edge delayed by 3.906 ms when correction period elapsesInternally divided clock (256 Hz) Internally divided clock (128 Hz) Internally divided clock (64 Hz) 128 Hz clock edge delayed by 3.906 ms when correction period elapses Clock edge periodically added when correction period elapses 1.000 second 1.003906 second 1.000 second 0.996094 second NEGATIVE CORRECTIONPOSITIVE CORRECTION dashed lines = no correction The inaccuracy of a crystal oscillator at typical room temperature (±20 ppm at 20–25 °C) can be compensated if a reference clock/signal is used to measure such inaccuracy. This kind of calibration operation can be set up during the final product manufacturing by means of measurement equipment embedding such a reference clock. The correction of value must be programmed into the (RTC_MR), and this value is kept as long as the circuitry is powered (backup area). Removing the backup power supply cancels this calibration. This room temperature calibration can be further processed by means of the networking capability of the target application. To ease the comparison of the inherent crystal accuracy with the reference clock/signal during manufacturing, an internal prescaled 32.768 kHz clock derivative signal can be assigned to drive RTC output. To accommodate the measure, several clock frequencies can be selected among 1 Hz, 32 Hz, 64 Hz, 512 Hz. SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 193

The clock calibration correction drives the internal RTC counters but can also be observed in the RTC output when one of the following three frequencies 1 Hz, 32 Hz or 64 Hz is configured. The correction is not visible in the RTC output if 512 Hz frequency is configured. Note: This adjustment does not consider the temperature variation. The frequency drift (up to -200 ppm) due to temperature variation can be compensated using a reference time if the application can access such a reference. If a reference time cannot be used, a temperature sensor can be placed close to the crystal oscillator in order to get the operating temperature of the crystal oscillator. Once obtained, the temperature may be converted using a lookup table (describing the accuracy/temperature curve of the crystal oscillator used) and RTC_MR configured accordingly. The calibration can be performed on-the-fly. This adjustment method is not based on a measurement of the crystal frequency/drift and therefore can be improved by means of the networking capability of the target application. If no crystal frequency adjustment has been done during manufacturing, it is still possible to do it. In the case where a reference time of the day can be obtained through LAN/WAN network, it is possible to calculate the drift of the application crystal oscillator by comparing the values read on RTC Time Register (RTC_TIMR) and programming the HIGHPPM and CORRECTION fields on RTC_MR according to the difference measured between the reference time and those of RTC_TIMR.

27.5.8 Waveform Generation

Waveforms can be generated in order to take advantage of the RTC inherent prescalers while the RTC is the only powered circuitry (Low-power mode of operation, Backup mode) or in any active mode. Entering Backup or Low-power operating modes does not affect the waveform generation outputs. The outputs RTCOUT0 and RTCOUT1 can be configured to provide several types of waveforms. The figure below illustrates the different signals available to generate RTCOUT0 and RTCOUT1. SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 194

Figure 27-6. Waveform Generation RTCOUT1 ‘0’ 1 Hz 32 Hz 64 Hz 512 Hz toggle_alarm flag_alarm pulse RTC_MR(OUT1) RTCOUT0 ‘0’ 1 Hz 32 Hz 64 Hz 512 Hz toggle_alarm flag_alarm pulse RTC_MR(OUT0) flag_alarm alarm match event 1 RTC_SCCR(ALRCLR) alarm match event 2 RTC_SCCR(ALRCLR) toggle_alarm pulse Tperiod Tperiod Thigh SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 195

27.6 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 RTC_CR 7:0 UPDCAL UPDTIM 15:8 TIMEVSEL[1:0] 23:16 CALEVSEL[1:0] 31:24 0x04 RTC_MR 7:0 NEGPPM PERSIAN HRMOD 15:8 HIGHPPM CORRECTION[6:0] 31:24 TPERIOD[1:0] THIGH[2:0] 0x08 RTC_TIMR 7:0 SEC[6:0] 15:8 MIN[6:0] 23:16 AMPM HOUR[5:0] 31:24 0x0C RTC_CALR 7:0 CENT[6:0] 15:8 YEAR[7:0] 23:16 DAY[2:0] MONTH[4:0] 31:24 DATE[5:0] 0x10 RTC_TIMALR 7:0 SECEN SEC[6:0] 15:8 MINEN MIN[6:0] 23:16 HOUREN AMPM HOUR[5:0] 31:24 0x14 RTC_CALALR 7:0 15:8 23:16 MTHEN MONTH[4:0] 31:24 DATEEN DATE[5:0] 0x18 RTC_SR 7:0 TDERR CALEV TIMEV SEC ALARM ACKUPD 15:8 23:16 31:24 0x1C RTC_SCCR 7:0 TDERRCLR CALCLR TIMCLR SECCLR ALRCLR ACKCLR 15:8 23:16 31:24 0x20 RTC_IER 7:0 TDERREN CALEN TIMEN SECEN ALREN ACKEN 15:8 23:16 31:24 0x24 RTC_IDR 7:0 TDERRDIS CALDIS TIMDIS SECDIS ALRDIS ACKDIS 15:8 23:16 31:24 0x28 RTC_IMR 7:0 TDERR CAL TIM SEC ALR ACK 15:8 23:16 31:24 0x2C RTC_VER 7:0 NVCALALR NVTIMALR NVCAL NVTIM 15:8 23:16 31:24 SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 196

27.6.1 RTC Control Register

Name: RTC_CR Offset: 0x00 Reset: 0x00000000 Property: Read/Write This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 CALEVSEL[1:0] Access R/W R/W Reset 0 0 Bit 15 14 13 12 11 10 9 8 TIMEVSEL[1:0] Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 UPDCAL UPDTIM Access R/W R/W Reset 0 0 Bits 17:16 – CALEVSEL[1:0] Calendar Event Selection The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL Value Name Description

0 WEEK Week change (every Monday at time 00:00:00)

1 MONTH Month change (every 01 of each month at time 00:00:00)

2 YEAR Year change (every January 1 at time 00:00:00)

3 YEAR Reserved

Bits 9:8 – TIMEVSEL[1:0] Time Event Selection The event that generates the flag TIMEV in RTC_SR depends on the value of TIMEVSEL. Value Name Description

0 MINUTE Minute change

1 HOUR Hour change

2 MIDNIGHT Every day at midnight

3 NOON Every day at noon

Bit 1 – UPDCAL Update Request Calendar Register Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once this bit is set and acknowledged by the bit ACKUPD of the RTC_SR. Value Description 0 No effect or, if UPDCAL has been previously written to 1, stops the update procedure. 1 Stops the RTC calendar counting. Bit 0 – UPDTIM Update Request Time Register Time counting consists of second, minute and hour counters. Time counters can be programmed once this bit is set and acknowledged by the bit ACKUPD of the RTC_SR. SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 197

0 No effect or, if UPDTIM has been previously written to 1, stops the update procedure. 1 Stops the RTC time counting. SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 198

27.6.2 RTC Mode Register

Name: RTC_MR Offset: 0x04 Reset: 0x00000000 Property: Read/Write This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). Bit 31 30 29 28 27 26 25 24 TPERIOD[1:0] THIGH[2:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OUT1[2:0] OUT0[2:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 HIGHPPM CORRECTION[6:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NEGPPM PERSIAN HRMOD Access R/W R/W R/W Reset 0 0 0 Bits 29:28 – TPERIOD[1:0] Period of the Output Pulse Value Name Description

0 P_1S 1 second

1 P_500MS 500 ms

2 P_250MS 250 ms

3 P_125MS 125 ms

Bits 26:24 – THIGH[2:0] High Duration of the Output Pulse Value Name Description 0 H_31MS 31.2 ms 1 H_16MS 15.6 ms 2 H_4MS 3.91 ms

3 H_976US 976 μs

4 H_488US 488 μs

5 H_122US 122 μs

6 H_30US 30.5 μs 7 H_15US 15.2 μs Bits 22:20 – OUT1[2:0] RTCOUT1 Output Source Selection Value Name Description

0 NO_WAVE No waveform, stuck at ‘0’

1 FREQ1HZ 1 Hz square wave

2 FREQ32HZ 32 Hz square wave

3 FREQ64HZ 64 Hz square wave

4 FREQ512HZ 512 Hz square wave

5 ALARM_TOGGLE Output toggles when alarm flag rises

6 ALARM_FLAG Output is a copy of the alarm flag

7 PROG_PULSE Duty cycle programmable pulse

Bits 18:16 – OUT0[2:0] RTCOUT0 Output Source Selection Value Name Description Bit 15 – HIGHPPM HIGH PPM Correction If the absolute value of the correction to be applied is lower than 30 ppm, it is recommended to clear HIGHPPM. HIGHPPM set to 1 is recommended for 30 ppm correction and above. Formula: If HIGHPPM = 0, then the clock frequency correction range is from 1.5 ppm up to 98 ppm. The RTC accuracy is less than 1 ppm for a range correction from 1.5 ppm up to 30 ppm. The correction field must be programmed according to the required correction in ppm; the formula is as follows: CORRECTION = 3906 20 × ppm − 1 The value obtained must be rounded to the nearest integer prior to being programmed into CORRECTION field. If HIGHPPM = 1, then the clock frequency correction range is from 30.5 ppm up to 1950 ppm. The RTC accuracy is less than 1 ppm for a range correction from 30.5 ppm up to 90 ppm. The correction field must be programmed according to the required correction in ppm; the formula is as follows: CORRECTION = 3906 ppm − 1 The value obtained must be rounded to the nearest integer prior to be programmed into CORRECTION field. If NEGPPM is set to 1, the ppm correction is negative (used to correct crystals that are faster than the nominal 32.768 kHz). Value Description 0 Lower range ppm correction with accurate correction. 1 Higher range ppm correction with accurate correction. Bits 14:8 – CORRECTION[6:0] Slow Clock Correction Value Description

0 No correction

1–127 The slow clock will be corrected according to the formula given in HIGHPPM description. Bit 4 – NEGPPM Negative PPM Correction See CORRECTION and HIGHPPM field descriptions. NEGPPM must be cleared to correct a crystal slower than 32.768 kHz. Value Description 0 Positive correction (the divider will be slightly higher than 32768). 1 Negative correction (the divider will be slightly lower than 32768). Bit 1 – PERSIAN PERSIAN Calendar Value Description 0 Gregorian calendar. 1 Persian calendar. Bit 0 – HRMOD 12-/24-hour Mode Value Description 0 24-hour mode is selected. SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 200

27.6.3 RTC Time Register

Name: RTC_TIMR Offset: 0x08 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 AMPM HOUR[5:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 MIN[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SEC[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 22 – AMPM Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode. Value Description 0 AM. 1 PM. Bits 21:16 – HOUR[5:0] Current Hour The range that can be set is 1–12 (BCD) in 12-hour mode or 0–23 (BCD) in 24-hour mode. Bits 14:8 – MIN[6:0] Current Minute The range that can be set is 0–59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. Bits 6:0 – SEC[6:0] Current Second The range that can be set is 0–59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 202

27.6.4 RTC Calendar Register

Name: RTC_CALR Offset: 0x0C Reset: 0x01E11320 Property: Read/Write Bit 31 30 29 28 27 26 25 24 DATE[5:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 1 Bit 23 22 21 20 19 18 17 16 DAY[2:0] MONTH[4:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 0 0 0 0 1 Bit 15 14 13 12 11 10 9 8 YEAR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 1 0 0 1 1 Bit 7 6 5 4 3 2 1 0 CENT[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 1 0 0 0 0 0 Bits 29:24 – DATE[5:0] Current Day in Current Month The range that can be set is 01–31 (BCD). The lowest four bits encode the units. The higher bits encode the tens. Bits 23:21 – DAY[2:0] Current Day in Current Week The range that can be set is 1–7 (BCD). The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter. Bits 20:16 – MONTH[4:0] Current Month The range that can be set is 01–12 (BCD). The lowest four bits encode the units. The higher bits encode the tens. Bits 15:8 – YEAR[7:0] Current Year The range that can be set is 00–99 (BCD). The lowest four bits encode the units. The higher bits encode the tens. Bits 6:0 – CENT[6:0] Current Century The range that can be set is 19–20 (Gregorian) or 13–14 (Persian) (BCD). The lowest four bits encode the units. The higher bits encode the tens. SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 203

27.6.5 RTC Time Alarm Register

Name: RTC_TIMALR Offset: 0x10 Reset: 0x00000000 Property: Read/Write This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). To change one of the SEC, MIN, HOUR fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to three accesses to the RTC_TIMALR. The first access clears the enable corresponding to the field to change (SECEN, MINEN, HOUREN). If the field is already cleared, this access is not required. The second access performs the change of the value (SEC, MIN, HOUR). The third access is required to re-enable the field by writing 1 in SECEN, MINEN, HOUREN fields. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 HOUREN AMPM HOUR[5:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 MINEN MIN[6:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SECEN SEC[6:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 – HOUREN Hour Alarm Enable Value Description 0 The hour-matching alarm is disabled. 1 The hour-matching alarm is enabled. Bit 22 – AMPM AM/PM Indicator This field is the alarm field corresponding to the BCD-coded hour counter. Bits 21:16 – HOUR[5:0] Hour Alarm This field is the alarm field corresponding to the BCD-coded hour counter. Bit 15 – MINEN Minute Alarm Enable Value Description 0 The minute-matching alarm is disabled. 1 The minute-matching alarm is enabled. Bits 14:8 – MIN[6:0] Minute Alarm This field is the alarm field corresponding to the BCD-coded minute counter. Bit 7 – SECEN Second Alarm Enable SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 204

0 The second-matching alarm is disabled. 1 The second-matching alarm is enabled. Bits 6:0 – SEC[6:0] Second Alarm This field is the alarm field corresponding to the BCD-coded second counter. SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 205

27.6.6 RTC Calendar Alarm Register

Name: RTC_CALALR Offset: 0x14 Reset: 0x01010000 Property: Read/Write This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). To change one of the DATE, MONTH fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to three accesses to the RTC_CALALR. The first access clears the enable corresponding to the field to change (DATEEN, MTHEN). If the field is already cleared, this access is not required. The second access performs the change of the value (DATE, MONTH). The third access is required to re-enable the field by writing 1 in DATEEN, MTHEN fields. Bit 31 30 29 28 27 26 25 24 DATEEN DATE[5:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 1 Bit 23 22 21 20 19 18 17 16 MTHEN MONTH[4:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 1 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 Access Reset Bit 31 – DATEEN Date Alarm Enable Value Description 0 The date-matching alarm is disabled. 1 The date-matching alarm is enabled. Bits 29:24 – DATE[5:0] Date Alarm This field is the alarm field corresponding to the BCD-coded date counter. Bit 23 – MTHEN Month Alarm Enable Value Description 0 The month-matching alarm is disabled. 1 The month-matching alarm is enabled. Bits 20:16 – MONTH[4:0] Month Alarm This field is the alarm field corresponding to the BCD-coded month counter. SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 206

27.6.7 RTC Status Register

Name: RTC_SR Offset: 0x18 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 TDERR CALEV TIMEV SEC ALARM ACKUPD Access R R R R R R Reset 0 0 0 0 0 0 Bit 5 – TDERR Time and/or Date Free Running Error Value Name Description

0 CORRECT The internal free running counters are carrying valid values since the last read of the

Status Register (RTC_SR).

1 ERR_TIMEDATE The internal free running counters have been corrupted (invalid date or time, non-

BCD values) since the last read and/or they are still invalid. Bit 4 – CALEV Calendar Event The calendar event is selected in the CALEVSEL field in the Control Register (RTC_CR) and can be any one of the following events: week change, month change and year change. Value Name Description 0 NO_CALEVENT No calendar event has occurred since the last clear. 1 CALEVENT At least one calendar event has occurred since the last clear. Bit 3 – TIMEV Time Event The time event is selected in the TIMEVSEL field in the Control Register (RTC_CR) and can be any one of the following events: minute change, hour change, noon, midnight (day change). Value Name Description 0 NO_TIMEVENT No time event has occurred since the last clear. 1 TIMEVENT At least one time event has occurred since the last clear. Bit 2 – SEC Second Event Value Name Description 0 NO_SECEVENT No second event has occurred since the last clear. 1 SECEVENT At least one second event has occurred since the last clear. Bit 1 – ALARM Alarm Flag Value Name Description 0 NO_ALARMEVENT No alarm matching condition occurred. SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 207

1 ALARMEVENT An alarm matching condition has occurred. Bit 0 – ACKUPD Acknowledge for Update Value Name Description 0 FREERUN Time and calendar registers cannot be updated. 1 UPDATE Time and calendar registers can be updated. SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 208

27.6.8 RTC Status Clear Command Register

Name: RTC_SCCR Offset: 0x1C Reset: – Property: Write-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 TDERRCLR CALCLR TIMCLR SECCLR ALRCLR ACKCLR Access W W W W W W Bit 5 – TDERRCLR Time and/or Date Free Running Error Clear Value Description 0 No effect. 1 Clears corresponding status flag in the Status Register (RTC_SR). Bit 4 – CALCLR Calendar Clear Value Description 0 No effect. 1 Clears corresponding status flag in the Status Register (RTC_SR). Bit 3 – TIMCLR Time Clear Value Description 0 No effect. 1 Clears corresponding status flag in the Status Register (RTC_SR). Bit 2 – SECCLR Second Clear Value Description 0 No effect. 1 Clears corresponding status flag in the Status Register (RTC_SR). Bit 1 – ALRCLR Alarm Clear Value Description 0 No effect. 1 Clears corresponding status flag in the Status Register (RTC_SR). Bit 0 – ACKCLR Acknowledge Clear Value Description 0 No effect. 1 Clears corresponding status flag in the Status Register (RTC_SR). SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 209

27.6.9 RTC Interrupt Enable Register

Name: RTC_IER Offset: 0x20 Reset: – Property: Write-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 TDERREN CALEN TIMEN SECEN ALREN ACKEN Access W W W W W W Bit 5 – TDERREN Time and/or Date Error Interrupt Enable Value Description 0 No effect. 1 The time and date error interrupt is enabled. Bit 4 – CALEN Calendar Event Interrupt Enable Value Description 0 No effect. 1 The selected calendar event interrupt is enabled. Bit 3 – TIMEN Time Event Interrupt Enable Value Description 0 No effect. 1 The selected time event interrupt is enabled. Bit 2 – SECEN Second Event Interrupt Enable Value Description 0 No effect. 1 The second periodic interrupt is enabled. Bit 1 – ALREN Alarm Interrupt Enable Value Description 0 No effect. 1 The alarm interrupt is enabled. Bit 0 – ACKEN Acknowledge Update Interrupt Enable Value Description 0 No effect. 1 The acknowledge for update interrupt is enabled. SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 210

27.6.10 RTC Interrupt Disable Register

Name: RTC_IDR Offset: 0x24 Reset: – Property: Write-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 TDERRDIS CALDIS TIMDIS SECDIS ALRDIS ACKDIS Access W W W W W W Bit 5 – TDERRDIS Time and/or Date Error Interrupt Disable Value Description 0 No effect. 1 The time and date error interrupt is disabled. Bit 4 – CALDIS Calendar Event Interrupt Disable Value Description 0 No effect. 1 The selected calendar event interrupt is disabled. Bit 3 – TIMDIS Time Event Interrupt Disable Value Description 0 No effect. 1 The selected time event interrupt is disabled. Bit 2 – SECDIS Second Event Interrupt Disable Value Description 0 No effect. 1 The second periodic interrupt is disabled. Bit 1 – ALRDIS Alarm Interrupt Disable Value Description 0 No effect. 1 The alarm interrupt is disabled. Bit 0 – ACKDIS Acknowledge Update Interrupt Disable Value Description 0 No effect. 1 The acknowledge for update interrupt is disabled. SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 211

27.6.11 RTC Interrupt Mask Register

Name: RTC_IMR Offset: 0x28 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 TDERR CAL TIM SEC ALR ACK Access R R R R R R Reset 0 0 0 0 0 0 Bit 5 – TDERR Time and/or Date Error Mask Value Description 0 The time and/or date error event is disabled. 1 The time and/or date error event is enabled. Bit 4 – CAL Calendar Event Interrupt Mask Value Description 0 The selected calendar event interrupt is disabled. 1 The selected calendar event interrupt is enabled. Bit 3 – TIM Time Event Interrupt Mask Value Description 0 The selected time event interrupt is disabled. 1 The selected time event interrupt is enabled. Bit 2 – SEC Second Event Interrupt Mask Value Description 0 The second periodic interrupt is disabled. 1 The second periodic interrupt is enabled. Bit 1 – ALR Alarm Interrupt Mask Value Description 0 The alarm interrupt is disabled. 1 The alarm interrupt is enabled. Bit 0 – ACK Acknowledge Update Interrupt Mask Value Description 0 The acknowledge for update interrupt is disabled. 1 The acknowledge for update interrupt is enabled. SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 212

27.6.12 RTC Valid Entry Register

Name: RTC_VER Offset: 0x2C Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 NVCALALR NVTIMALR NVCAL NVTIM Access R R R R Reset 0 0 0 0 Bit 3 – NVCALALR Non-valid Calendar Alarm Value Description 0 No invalid data has been detected in RTC_CALALR (Calendar Alarm Register). 1 RTC_CALALR has contained invalid data since it was last programmed. Bit 2 – NVTIMALR Non-valid Time Alarm Value Description 0 No invalid data has been detected in RTC_TIMALR (Time Alarm Register). 1 RTC_TIMALR has contained invalid data since it was last programmed. Bit 1 – NVCAL Non-valid Calendar Value Description 0 No invalid data has been detected in RTC_CALR (Calendar Register). 1 RTC_CALR has contained invalid data since it was last programmed. Bit 0 – NVTIM Non-valid Time Value Description 0 No invalid data has been detected in RTC_TIMR (Time Register). 1 RTC_TIMR has contained invalid data since it was last programmed. SAMV71Q21RT Real-time Clock (RTC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 213

Real-time Timer (RTT)

28.1 Description

The Real-Time Timer (RTT) is built around a 32-bit counter used to count roll-over events of the programmable 16-bit prescaler driven from the 32-kHz slow clock source. It generates a periodic interrupt and/or triggers an alarm on a programmed value. The RTT can also be configured to be driven by the 1Hz RTC signal, thus taking advantage of a calibrated 1Hz clock. The slow clock source can be fully disabled to reduce power consumption when only an elapsed seconds count is required.

28.2 Embedded Characteristics

32-bit Free-running Counter on prescaled slow clock or RTC calibrated 1Hz clock
16-bit Configurable Prescaler
Interrupt on Alarm or Counter Increment

28.3 Block Diagram

Figure 28-1. Real-time Timer Block Diagram SLCK RTPRES RTTINC ALMS 16-bit Prescaler 32-bit Counter ALMV CRTV RTT_MR RTT_VR RTT_AR RTT_SR RTTINCIEN RTT_MR 1 0 ALMIEN rtt_int RTT_MR set set RTT_SR read RTT_SR reset reset RTT_MR reload rtt_alarm RTTRST RTT_MR RTTRST RTT_MR RTTDIS 1 0 RTT_MR RTC1HZ RTC 1Hz

28.4 Functional Description

The programmable 16-bit prescaler value can be configured through the RTPRES field in the RTT Mode register (RTT_MR). Configuring the RTPRES field value to 0x8000 (default value) corresponds to feeding the real-time counter with a 1Hz signal (if the slow clock is 32.768 kHz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0. Bit RTTINC in the RTT Status Register (RTT_SR) is set each time there is a prescaler roll-over. SAMV71Q21RT Real-time Timer (RTT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 214

The real-time 32-bit counter can also be supplied by the 1Hz RTC clock. This mode is interesting when the RTC 1Hz is calibrated (CORRECTION field ≠ 0 in RTC_MR) in order to guaranty the synchronism between RTC and RTT counters. Setting the RTC1HZ bit in the RTT_MR drives the 32-bit RTT counter from the 1Hz RTC clock. In this mode, the RTPRES field has no effect on the 32-bit counter. The prescaler roll-over generates an increment of the real-time timer counter if RTC1HZ = 0. Otherwise, if RTC1HZ = 1, the RTT counter is incremented every second. The RTTINC bit is set independently from the 32-bit counter increment. The RTT can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3 in RTT_MR. Programming RTPRES to 1 or 2 is forbidden. If the RTT is configured to trigger an interrupt, the interrupt occurs two slow clock cycles after reading the RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the RTT_SR is cleared. The CRTV field can be read at any time in the RTT Value register (RTT_VR). As this value can be updated asynchronously with the Master Clock, the CRTV field must be read twice at the same value to read a correct value. The current value of the counter is compared with the value written in the RTT Alarm register (RTT_AR). If the counter value matches the alarm, the ALMS bit in the RTT_SR is set. The RTT_AR is set to its maximum value (0xFFFFFFFF) after a reset. The ALMS flag is always a source of the RTT alarm signal that may be used to exit the system from low power modes (see the Real-time Timer Block Diagram above). The alarm interrupt must be disabled (ALMIEN must be cleared in RTT_MR) when writing a new ALMV value in the RTT_AR. The RTTINC bit can be used to start a periodic interrupt, the period being one second when the RTPRES field value = 0x8000 and the slow clock = 32.768 kHz. The RTTINCIEN bit must be cleared prior to writing a new RTPRES value in the RTT_MR. Reading the RTT_SR automatically clears the RTTINC and ALMS bits. Writing the RTTRST bit in the RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. When not used, the RTT can be disabled in order to suppress dynamic power consumption in this module. This can be achieved by setting the RTTDIS bit in the RTT_MR. SAMV71Q21RT Real-time Timer (RTT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 215

Figure 28-2. RTT Counting Prescaler ALMV ALMV-1 0 ALMV+1 RTPRES - 1 CRTV read RTT_SR ALMS (RTT_SR) APB Interface SLCK RTTINC (RTT_SR) ALMV+2 ALMV+3... APB cycleAPB cycle SAMV71Q21RT Real-time Timer (RTT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 216

28.5 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 RTT_MR 7:0 RTPRES[7:0] 15:8 RTPRES[15:8] 23:16 RTTDIS RTTRST RTTINCIEN ALMIEN 31:24 RTC1HZ 0x04 RTT_AR 7:0 ALMV[7:0] 15:8 ALMV[15:8] 23:16 ALMV[23:16] 31:24 ALMV[31:24] 0x08 RTT_VR 7:0 CRTV[7:0] 15:8 CRTV[15:8] 23:16 CRTV[23:16] 31:24 CRTV[31:24] 0x0C RTT_SR 7:0 RTTINC ALMS 15:8 23:16 31:24 SAMV71Q21RT Real-time Timer (RTT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 217

28.5.1 Real-time Timer Mode Register

Name: RTT_MR Offset: 0x00 Reset: 0x00008000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 RTC1HZ Access Reset 0 Bit 23 22 21 20 19 18 17 16 RTTDIS RTTRST RTTINCIEN ALMIEN Access R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 RTPRES[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RTPRES[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 24 – RTC1HZ Real-Time Clock 1Hz Clock Selection Value Description 0 The RTT 32-bit counter is driven by the 16-bit prescaler roll-over events. 1 The RTT 32-bit counter is driven by the 1Hz RTC clock. Bit 20 – RTTDIS Real-time Timer Disable Value Description 0 The RTT is enabled. 1 The RTT is disabled (no dynamic power consumption). Bit 18 – RTTRST Real-time Timer Restart Value Description 0 No effect. 1 Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. Bit 17 – RTTINCIEN Real-time Timer Increment Interrupt Enable Value Description 0 The bit RTTINC in RTT_SR has no effect on interrupt. 1 The bit RTTINC in RTT_SR asserts interrupt. Bit 16 – ALMIEN Alarm Interrupt Enable Value Description 0 The bit ALMS in RTT_SR has no effect on interrupt. 1 The bit ALMS in RTT_SR asserts interrupt. Bits 15:0 – RTPRES[15:0] Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the RTT. The RTTINCIEN bit must be cleared prior to writing a new RTPRES value. SAMV71Q21RT Real-time Timer (RTT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 218

RTPRES is defined as follows:

RTPRES = 0: The prescaler period is equal to 2 16 * SLCK periods.
RTPRES = 1 or 2: forbidden.
RTPRES ≠ 0,1 or 2: The prescaler period is equal to RTPRES * SLCK periods. SAMV71Q21RT Real-time Timer (RTT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 219

28.5.2 Real-time Timer Alarm Register

Name: RTT_AR Offset: 0x04 Reset: 0xFFFFFFFF Property: Read/Write The alarm interrupt must be disabled (ALMIEN must be cleared in RTT_MR) when writing a new ALMV value. Bit 31 30 29 28 27 26 25 24 ALMV[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 23 22 21 20 19 18 17 16 ALMV[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 ALMV[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 ALMV[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bits 31:0 – ALMV[31:0] Alarm Value When the CRTV value in RTT_VR equals the ALMV field, the ALMS flag is set in RTT_SR. As soon as the ALMS flag rises, the CRTV value equals ALMV+1 (refer to the figure RTT Counting above). SAMV71Q21RT Real-time Timer (RTT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 220

28.5.3 Real-time Timer Value Register

Name: RTT_VR Offset: 0x08 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 CRTV[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CRTV[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CRTV[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRTV[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – CRTV[31:0] Current Real-time Value Returns the current value of the RTT. As CRTV can be updated asynchronously, it must be read twice at the same value. SAMV71Q21RT Real-time Timer (RTT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 221

28.5.4 Real-time Timer Status Register

Name: RTT_SR Offset: 0x0C Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 RTTINC ALMS Access R R Reset 0 0 Bit 1 – RTTINC Prescaler Roll-over Status (cleared on read) Value Description 0 No prescaler roll-over occurred since the last read of the RTT_SR. 1 Prescaler roll-over occurred since the last read of the RTT_SR. Bit 0 – ALMS Real-time Alarm Status (cleared on read) Value Description 0 The Real-time Alarm has not occurred since the last read of RTT_SR. 1 The Real-time Alarm occurred since the last read of RTT_SR. SAMV71Q21RT Real-time Timer (RTT) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 222

General Purpose Backup Registers (GPBR)

29.1 Description

The System Controller embeds 128 bits of General Purpose Backup registers organized as 8 32-bit registers. It is possible to generate an immediate clear of the content of General Purpose Backup registers 0 to 3 (first half) if a Low-power Debounce event is detected on one of the wakeup pins, WKUP0 or WKUP1. The content of the other General Purpose Backup registers (second half) remains unchanged. The Supply Controller module must be programmed accordingly. In the register SUPC_WUMR in the Supply Controller module, LPDBCCLR, LPDBCEN0 and/or LPDBCEN1 bit must be configured to 1 and LPDBC must be other than 0. If a Tamper event has been detected, it is not possible to write to the General Purpose Backup registers while the LPDBCS0 or LPDBCS1 flags are not cleared in the Supply Controller Status Register (SUPC_SR).

29.2 Embedded Characteristics

128 bits of General Purpose Backup Registers
Immediate Clear on Tamper Event SAMV71Q21RT General Purpose Backup Registers (GPBR) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 223

29.3 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 SYS_GPBRx 7:0 GPBR_VALUE[7:0] 15:8 GPBR_VALUE[15:8] 23:16 GPBR_VALUE[23:16] 31:24 GPBR_VALUE[31:24] SAMV71Q21RT General Purpose Backup Registers (GPBR) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 224

29.3.1 General Purpose Backup Register x

Name: SYS_GPBRx Offset: 0x00 Reset: 0 Property: R/W These registers are reset at first power-up and on each loss of VDDIO. Bit 31 30 29 28 27 26 25 24 GPBR_VALUE[31:24] Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 GPBR_VALUE[23:16] Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 GPBR_VALUE[15:8] Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GPBR_VALUE[7:0] Access Reset 0 0 0 0 0 0 0 0 Bits 31:0 – GPBR_VALUE[31:0] Value of GPBR x If a Tamper event has been detected, it is not possible to write GPBR_VALUE as long as the LPDBCS0 or LPDBCS1 flag has not been cleared in the Supply Controller Status Register (SUPC_SR). SAMV71Q21RT General Purpose Backup Registers (GPBR) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 225

Clock Generator

30.1 Description

The Clock Generator user interface is embedded within the Power Management Controller and is described in Power Management Controller (PMC) User Interface. However, the Clock Generator registers are named CKGR_.

30.2 Embedded Characteristics

The Clock Generator is comprised of the following:

A low-power 32.768 kHz crystal oscillator with Bypass mode
A low-power Slow RC oscillator (32 kHz typical)
A 3 to 20 MHz Main crystal oscillator with Bypass mode
A Main RC oscillator. Three output frequencies can be selected: 4/8/12 MHz. By default 12 MHz is selected. 8 MHz and 12 MHz are factory-trimmed.
A 480 MHz UTMI PLL, providing a clock for the USB high-speed controller
A 160 to 500 MHz programmable PLL (input from 8 to 32 MHz) It provides the following clocks:
SLCK — Slow clock. The only permanent clock within the system
MAINCK — output of the Main clock oscillator selection: either the Main crystal oscillator or Main RC oscillator
PLLACK — output of the divider and 160 to 500 MHz programmable PLL (PLLA)
UPLLCK — output of the 480 MHz UTMI PLL (UPLL) SAMV71Q21RT Clock Generator © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 226

30.3 Block Diagram

Figure 30-1. Clock Generator Block Diagram Power Management Controller User Interface Main Clock (MAINCK) PLLA Clock (PLLACK) Control Status Main Crystal Oscillator MOSCSEL Clock Generator PLLA and Divider Main RC Oscillator XIN XOUT XIN32 XOUT32 Slow Clock (SLCK) SUPC_CR.XTALSEL Slow RC Oscillator 32.768 kHz Crystal Oscillator UPLL Clock (UPLLCK) USB UTMI PLL CKGR_MOR CKGR_MOR.MOSCXTBY SUPC_MR.OSCBYPASS

30.4 Slow Clock

The Supply Controller embeds a slow clock generator that is supplied with the VDDIO power supply. As soon as VDDIO is supplied, both the 32.768 kHz crystal oscillator and the Slow RC oscillator are powered, but only the Slow RC oscillator is enabled. This allows the Slow clock (SLCK) to be valid in a short time (about 100 μs). SLCK is generated either by the 32.768 kHz crystal oscillator or by the Slow RC oscillator. To select the clock source, the selection is made via the XTALSEL bit in the Supply Controller Control Register (SUPC_CR).

30.4.1 Slow RC Oscillator (32 kHz typical)

By default, the Slow RC oscillator is enabled and selected as a source of SLCK. SAMV71Q21RT Clock Generator © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 227

Compared to the 32.768 kHz crystal oscillator, this oscillator offers a faster startup time and is less exposed to the external environment, as it is fully integrated. However, its output frequency is subject to larger variations with supply voltage, temperature and manufacturing process. Therefore, the user must take these variations into account when this oscillator is used as a time base (startup counter, frequency monitor, etc.). Refer to the section “Electrical Characteristics”. This oscillator is disabled by clearing the SUPC_CR.XTALSEL. 30.4.2 32.768 kHz Crystal Oscillator By default, the 32.768 kHz oscillator is disabled. To use this oscillator, the XIN32 and XOUT32 pins must be connected to a 32.768 kHz crystal or to a ceramic resonator. Refer to the section “Electrical Characteristics” for appropriate loading capacitors selection on XIN32 and XOUT32. Note that the user is not obliged to use the 32.768 kHz crystal oscillator and can use the Slow RC oscillator instead. Using the 32.768 kHz crystal oscillator provides a more accurate frequency than the Slow RC oscillator. To select the 32.768 kHz crystal oscillator as the source of SLCK, the bit SUPC_CR.XTALSEL must be set. This results in a sequence which first configures the PIO lines multiplexed with XIN32 and XOUT32 to be driven by the crystal oscillator, then enables the 32.768 kHz crystal oscillator and then disables the Slow RC oscillator to save power. The switch of SLCK source is glitch-free. Reverting to the Slow RC oscillator is only possible by shutting down the VDDIO power supply. If the user does not need the 32.768 kHz crystal oscillator, the XIN32 and XOUT32 pins can be left unconnected since by default the XIN32 and XOUT32 system I/O pins are in PIO input mode with pullup after reset. The user can also set the 32.768 kHz crystal oscillator in Bypass mode instead of connecting a crystal. In this case, the user must provide the external clock signal on XIN32. For input characteristics of the XIN32 pin, refer to the section “Electrical Characteristics”. To enter Bypass mode, the OSCBYPASS bit of the Supply Controller Mode register (SUPC_MR) must be set prior to setting SUPC_CR.XTALSEL.

30.5 Main Clock

The Main clock (MAINCK) has two sources:

A Main RC oscillator (4/8/12 MHz) with a fast startup time and that is selected by default to start the system
A Main crystal oscillator with Bypass mode Figure 30-2. Main Clock (MAINCK) Block Diagram XIN X OUT MOSCXTEN Main Crystal Oscillator MOSCRCEN Main RC Oscillator MOSCRCS MOSCRCF MOSCSEL MOSCSELS MAINCK Main Cloc k CKGR_MOR CKGR_MOR CKGR_MOR PMC_SR PMC_SR CKGR_MOR

30.5.1 Main RC Oscillator

After reset, the Main RC oscillator is enabled with the 12 MHz frequency selected. This oscillator is selected as the source of MAINCK. MAINCK is the default clock selected to start the system. SAMV71Q21RT Clock Generator © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 228

Only the 8/12 MHz RC oscillator frequencies are calibrated in production. Refer to the section “Electrical Characteristics”. The software can disable or enable the Main RC oscillator with the MOSCRCEN bit in the Clock Generator Main Oscillator Register (CKGR_MOR). The output frequency of the Main RC oscillator can be selected among 4, 8 or 12 MHz. Selection is done by configuring the field MOSCRCF in CKGR_MOR. When changing the frequency selection, the MOSCRCS bit in the Power Management Controller Status Register (PMC_SR) is automatically cleared and MAINCK is stopped until the oscillator is stabilized. Once the oscillator is stabilized, MAINCK restarts and PMC_SR.MOSCRCS is set. Note that enabling the Main RC oscillator (MOSCRCEN = 1) and changing its frequency (MOSCRCF) at the same time is not allowed. This oscillator must be enabled first and its frequency changed in a second step. When disabling the Main RC oscillator by clearing the CKGR_MOR.MOSCRCEN bit, the PMC_SR.MOSCRCS bit is automatically cleared, indicating that the oscillator is OFF. Setting the MOSCRCS bit in the Power Management Controller Interrupt Enable Register (PMC_IER) triggers an interrupt to the processor.

30.5.2 Main RC Oscillator Frequency Adjustment

The 8 MHz and 12 MHz frequencies are factory-centered to the typical values by using Flash calibration bits (refer to the “Electrical Characteristics” chapter). The Flash calibration bits setting the Main RC oscillator frequency to 8 MHz and 12 MHz vary from device to device. To get a starting point when changing the CAL8 or CAL12 fields, it is recommended to first read their corresponding Flash calibration bits in the Flash Controller. The user can adjust the value of the Main RC oscillator frequency by modifying the trimming values done in production on 8 MHz and 12 MHz. This may be used to compensate frequency drifts due to temperature or voltage. The values stored in the Flash cannot be erased by a Flash erase command or by the ERASE signal. Values written by the user application in the Oscillator Calibration Register (PMC_OCR) are reset after each power-up or peripheral reset. By default, SEL4/SEL8/SEL12 are cleared, so the Main RC oscillator is driven with the factory-programmed Flash calibration bits which are programmed during chip production. In order to calibrate the oscillator lower frequency, SEL4 must be set to ‘1’ and a valid frequency value must be configured in CAL4. Likewise, SEL8/12 must be set to ‘1’ and a trim value must be configured in CAL8/12 in order to adjust the other frequencies of the oscillator. It is possible to adjust the oscillator frequency while operating from this oscillator. For example, when running on lowest frequency, it is possible to change the CAL4 value if SEL4 is set in PMC_OCR. At any time, the user can measure the main RC oscillator output frequency by means of the Main Frequency Counter (refer to "Main Frequency Counter"). Once the frequency measurement is done, the main RC oscillator calibration field (CALx) can be adjusted accordingly to correct this oscillator output frequency.

30.5.3 Main Crystal Oscillator

After reset, the Main crystal oscillator is disabled and is not selected as the source of MAINCK. As the source of MAINCK, the Main crystal oscillator provides a very precise frequency. The software enables or disables this oscillator in order to reduce power consumption via CKGR_MOR.MOSCXTEN. When disabling this oscillator by clearing the CKGR_MOR.MOSCXTEN, PMC_SR.MOSCXTS is automatically cleared, indicating the oscillator is off. When enabling this oscillator, the user must initiate the startup time counter. The startup time depends on the characteristics of the external device connected to this oscillator. When CKGR_MOR.MOSCXTEN and CKGR_MOR.MOSCXTST are written to enable this oscillator, the PIO lines multiplexed with XIN and XOUT are driven by the Main crystal oscillator. PMC_SR.MOSCXTS is cleared and the counter starts counting down on SLCK divided by 8 from the CKGR_MOR.MOSCXTST value. Since the CKGR_MOR.MOSCXTST value is coded with 8 bits, the startup time can be programmed up to 65536 SLCKperiods, corresponding to about 62 ms when running at 32.768 kHz. SAMV71Q21RT Clock Generator © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 229

When the startup time counter reaches ‘0’, PMC_SR.MOSCXTS is set, indicating that the oscillator is stabilized. Setting the MOSCXTS bit in the Interrupt Mask Register (PMC_IMR) can trigger an interrupt to the processor.

30.5.4 Main Clock Source Selection

The source of MAINCK can be selected from the following:

The Main RC oscillator
The Main crystal oscillator
An external clock signal provided on the XIN input (Bypass mode of the Main crystal oscillator) The advantage of the Main RC oscillator is its fast startup time. By default, this oscillator is selected to start the system and it must be selected prior to entering Wait mode. The advantage of the Main crystal oscillator is its high level of accuracy. The selection of the oscillator is made with bit CKGR_MOR.MOSCSEL. The switchover of the MAINCK source is glitch-free, so there is no need to run MCK out of SLCK, PLLACK or UPLLCK in order to change the selection. PMC_SR.MOSCSELS indicates when the switch sequence is done. Setting PMC_IMR.MOSCSELS triggers an interrupt to the processor. MAINCK Switching Sequence When switching the Main Clock MAINCK source from the Main Crystal oscillator to the Main RC oscillator it is mandatory to follow the below steps:
Start the Main RC oscillator and keep MAINCK on the Main Crystal Oscillator (this step is optional at startup as it is the default configuration)
Switch MAINCK to the Main RC oscillator and keep the Main Crystal Oscillator on
Switch off the Main Crystal Oscillator is a third separate step

30.5.5 Bypassing the Main Crystal Oscillator

Prior to bypassing the Main crystal oscillator, the external clock frequency provided on the XIN pin must be stable and within the values specified in the XIN Clock characteristics in the section “Electrical Characteristics”. The sequence is as follows: 1. Ensure that an external clock is connected on XIN. 2. Enable the bypass by setting CKGR_MOR.MOSCXTBY. 3. Disable the Main crystal oscillator by clearing CKGR_MOR.MOSCXTEN.

30.5.6 Main Frequency Counter

The Main frequency counter measures the Main RC oscillator and the Main crystal oscillator against the SLCK and is managed by CKGR_MCFR. During the measurement period, the Main frequency counter increments at the speed of the clock defined by the bit CKGR_MCFR.CCSS. A measurement is started in the following cases:

When CKGR_MCFR.RCMEAS is written to ‘1’.
When the Main RC oscillator is selected as the source of MAINCK and when this oscillator is stable (i.e., when the MOSCRCS bit is set)
When the Main crystal oscillator is selected as the source of MAINCK and when this oscillator is stable (i.e., when the MOSCXTS bit is set)
When MAINCK source selection is modified The measurement period ends at the 16th falling edge of SLCK, the MAINFRDY bit in CKGR_MCFR is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of clock cycles during 16 periods of SLCK, so that the frequency of the Main RC oscillator or Main crystal oscillator can be determined. If switching the source of MAINCK to the Main crystal oscillator from the Main RC oscillator, follow the programming sequence below to ensure that the oscillator is present and that its frequency is valid: SAMV71Q21RT Clock Generator © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 230

Enable the Main crystal oscillator by setting CKGR_MOR.MOSCXTEN. Configure the CKGR_MOR. MOSCXTST field with the Main crystal oscillator startup time as defined in the section “Electrical Characteristics”. 2. Wait for PMC_SR.MOSCXTS flag to rise, indicating the end of a startup period of the Main crystal oscillator. 3. Select the Main crystal oscillator as the source clock of the Main frequency counter by setting CKGR_MCFR.CCSS. 4. Initiate a frequency measurement by setting CKGR_MCFR.RCMEAS. 5. Read CKGR_MCFR.MAINFRDY until its value equals 1. 6. Read CKGR_MCFR.MAINF and compute the value of the Main crystal frequency. If the MAINF value is valid, software can switch MAINCK to the Main crystal oscillator. Refer to "Main Clock Source Selection". Figure 30-3. Main Frequency Counter Block Diagram MOSCXTST MOSCXTS Main Frequency Counter MAINF SLCK Main Crystal Oscillator Startup Counter MOSCRCEN MOSCXTEN MOSCSEL Reference Clock RCMEAS CKGR_MCF R CKGR_MOR CKGR_MOR CKGR_MOR CKGR_MCF R PMC_SR CKGR_MCFR MAINFRDY Main Crystal Oscillator Main RC Oscillator CCSS CKGR_MCFR

30.6 PLLA Clock

The PLLA clock (PLLACK) is generated from MAINCK by the PLLA and a predivider. This combination allows a wide range of frequencies to be selected on either MCK, HCLK or the PCKx outputs. The following figure shows the block diagram of the dividers and PLLA blocks. Figure 30-4. Divider and PLLA Block Diagram Divider DIVA PLLA MULA PLLACOUNT LOCKASLCK MAINCK PLLACK PLLA Counter CKGR_PLLAR CKGR_PLLAR CKGR_PLLAR PMC_SR SAMV71Q21RT Clock Generator © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 231

30.6.1 Divider and Phase Lock Loop Programming

The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is cleared, the output of the corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is cleared, thus the corresponding PLL input clock is stuck at ‘0’. The PLL (PLLA) allows multiplication of the divider’s outputs. The PLL clock signal has a frequency that depends on the respective source signal frequency and on the parameters DIV (DIVA) and MUL (MULA). The factor applied to the source signal frequency is (MUL + 1)/DIV. When MUL is written to ‘0’ or DIV = 0, the PLL is disabled and its power consumption is saved. Note that there is a delay of two SLCK clock cycles between the disable command and the real disable of the PLL. Re-enabling the PLL can be performed by writing a value higher than ‘0’ in the MUL field and DIV higher than ‘0’. Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK (LOCKA) bit in PMC_SR is automatically cleared. The values written in the PLLCOUNT field (PLLACOUNT) in CKGR_PLLR (CKGR_PLLAR) are loaded in the PLL counter. The PLL counter then decrements at the speed of SLCK until it reaches ‘0’. At this time, PMC_SR.LOCK is set and can trigger an interrupt to the processor. The user has to load the number of SLCK cycles required to cover the PLL transient time into the PLLCOUNT field. To avoid programming the PLL with a multiplication factor that is too high, the user can saturate the multiplication factor value sent to the PLL by setting the PLLA_MMAX field in the PLL Maximum Multiplier Value Register (PMC_PMMR). It is forbidden to change the MAINCK characteristics (oscillator selection, frequency adjustment of the Main RC oscillator) when:

MAINCK is selected as the PLLA clock source, and
MCK is sourced from PLLA. To change the MAINCK characteristics, the user must: 1. Switch the MCK source to MAINCK by writing a ‘1’ to PMC_MCKR.CSS. 2. Change the Main RC oscillator frequency (MOSCRCF) or oscillator selection (MOSCSEL) in CKGR_MOR. 3. Wait for MOSCRCS (if frequency changes) or MOSCSELS (if oscillator selection changes) in PMC_SR. 4. Disable and then enable the PLL. 5. Wait for the LOCK flag in PMC_SR. 6. Switch back MCK to the PLLA by writing the appropriate value to PMC_MCKR.CSS.

30.7 UTMI PLL Clock

The source of the UTMI PLL (UPLL) is the Main Crystal oscillator. The UPLL provides the UTMI PLL Clock (UPLLCK) and UPLLCKDIV clock signals. The UPLL has two possible multiplying factors: x40 and x30. To generate UPLLCK at 480 MHz (typical USB case), this leads to two possible crystal oscillator frequencies: 12 or 16 MHz. The crystal oscillator frequency (12 or 16 MHz) must be programmed in UTMI_CKTRIM.FREQ prior to enabling the UPLL. When the UPLL is enabled by writing a ‘1’ to bit UPLLEN in the UTMI Clock Register (CKGR_UCKR), the LOCKU bit in PMC_SR is automatically cleared. The values written in the PLLCOUNT field in CKGR_UCKR are loaded in the UTMI PLL counter. The UTMI PLL counter then decrements at the speed of SLCK divided by 8 until it reaches ‘0’. At this time, the LOCKU bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of SLCK cycles required to cover the UTMI PLL transient time into the PLLCOUNT field. SAMV71Q21RT Clock Generator © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 232

Figure 30-5. UTMI PLL Block Diagram UTMI PLL UPLLEN UPLLCOUNT LOCKUSLCK Main Crystal Oscillator Output UPLLCK UTMI PLL Counter CKGR_UCKR PMC_SR CKGR_UCKR SAMV71Q21RT Clock Generator © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 233

Power Management Controller (PMC)

31.1 Description

The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Cortex-M7 processor. The Supply Controller selects either the Slow RC oscillator or the 32.768 kHz crystal oscillator as the source of SLCK. The unused oscillator is disabled automatically so that power consumption is optimized. By default, at startup, the chip runs out of MCK using the Main RC oscillator running at 12 MHz.

31.2 Embedded Characteristics

The Power Management Controller provides the following clocks:

Master Clock (MCK), programmable from a few hundred Hz to the maximum operating frequency of the device. It is available to the modules running permanently, such as the Enhanced Embedded Flash Controller
Processor Clock (HCLK), automatically switched off when entering the processor in Sleep mode
Free-running processor Clock (FCLK)
The Cortex-M7 SysTick external clock
USB Clock (USB_48M), required by the USB peripheral
Peripheral Clocks with independent ON/OFF control, provided to the peripherals
Programmable Clock Outputs (PCKx), selected from the clock generator outputs to drive the device PCK pins
Clock sources independent of MCK and HCLK, provided by internal PCKx for USART, UART, TC, Embedded Trace Macrocell (ETM) and CAN Clocks
Generic Clock (GCLK) with controllable division and ON/OFF control, independent of MCK and HCLK. Provided to selected peripherals. The Power Management Controller also provides the following features on clocks:
A Main crystal oscillator failure detector
A 32.768 kHz crystal oscillator frequency monitor
A frequency counter on Main crystal oscillator or Main RC oscillator
An on-the-fly adjustable Main RC oscillator frequency SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 234

31.3 Block Diagram

Figure 31-1. General Clock Distribution Block Diagram Power Management Controller User Interface ControlStatus Main Crystal Oscillator PLLA XIN XOUT XIN32 XOUT32 Slow RC Oscillator int SLCK MAINCK PLLACK Prescaler /1,/2,/3,/4,/8, /16,/32,/64 Processor Clock Controller Sleep Mode Master Clock Controller (PMC_MCKR) Prescaler PCK[..] (to I/O pins and peripherals) SysTick External Clock Divider SLCK MAINCK PLLACK USB UTMI PLL Main RC Oscillator Programmable Clock Controller (PMC_PCKx) PRES PRESCSS CSS Divider /1, /2UPLLDIV2 Divider /1,/2,/3,...,/16 USB Clock Controller (PMC_USB) USBDIVUSBS UPLLCKDIV PLLACK MCK Slow Clock (SLCK) Clock Generator SUPC_CR.XTALSEL PMC_MCKR MOSCSEL CKGR_MOR (PMC_SCER/SCDR) /1 to /256 granularity=1 /1, /2, /3, /4 Divider MDIV periph_clk[PID] (to peripherals) Peripheral Clock Controller (PMC_PCR) EN(PID) PCKx USBCLK UPLLCKDIV UPLLCKDIV MCK PLLACK UPLLCKDIV MAINCK SLCK GCLKCSS(PID) Prescaler /1,/2,/3,...,/256 GCLKDIV(PID) GCLK[PID] (to peripherals) GCLKEN(PID) 32.768 kHz Crystal Oscillator Main Clock (MAINCK) PLLA Clock (PLLACK) UPLL Clock (UPLLCK) USB FS Clock (USB_48M) Processor Clock (HCLK) Free Running Clock (FCLK) Master Clock (MCK) USB HS Clock (USB_480M)

31.4 Master Clock Controller

The Master Clock Controller provides the Master Clock (MCK) with the selection and division of the clock generator's output signals. MCK is the source clock of the peripheral clocks. The clock to be selected between SLCK, MAINCK, PLLACK and UPLLCKDIV is configured in PMC_MCKR.CSS. The prescaler supports the 1, 2, 3, 4, 8, 16, 32, 64 division factors and is configured using PMC_MCKR.PRES. Each time PMC_MCKR is configured to define a new MCK, the MCKRDY bit is cleared in PMC_SR. It reads ‘0’ until MCK is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is completed. Note: Users cannot modify MDIV and CSS at the same access. Each field must be modified separately with a wait for the MCKRDY flag between the first field modification and the second field modification.

31.5 Processor Clock Controller

The PMC features a Processor Clock (HCLK) Controller that implements the processor Sleep mode. HCLK can be disabled by executing the WFI (WaitForInterrupt) or the WFE (WaitForEvent) processor instruction while the LPM bit is at ‘0’ in the PMC Fast Startup Mode register (PMC_FSMR). HCLK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The processor Sleep mode is entered by disabling HCLK, which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product. When processor Sleep mode is entered, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus.

31.6 SysTick External Clock

When the processor selects the SysTick external clock, the calibration value is fixed to 150000. This allows the generation of a time base of 1 ms with the SysTick clock at the maximum frequency on MCK divided by 2. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 235

Refer to the section “ARM Cortex-M7 Processor” for details on selecting the SysTick external clock. Related Links 15. ARM Cortex-M7 (ARM)

31.7 USB Full-speed Clock Controller

The user can select the PLLA or the UPLL output as the USB FS clock (USB_48M) by writing a ‘1’ to the USBS bit in the USB Clock Register (PMC_USB). The user then must program the corresponding PLL to generate an appropriate frequency depending on the USBDIV bit in PMC_USB. When PMC_SR.LOCKA and PMC_SR.LOCKU are set to ‘1’, the PLLA and UPLL are stable. Then, USB_48M can be enabled by setting the USBCLK bit in the System Clock Enable register (PMC_SCER). To save power on this peripheral when not used, the user can set the USBCLK bit in the System Clock Disable register (PMC_SCDR). The USBCLK bit in the System Clock Status register (PMC_SCSR) gives the status of this clock. The USB port requires both the USB clock signal and the peripheral clock. The USB peripheral clock is controlled by means of the Master Clock Controller.

31.8 Core and Bus Independent Clocks for Peripherals

The following table lists the peripherals that require a PCKx clock to operate while the core, bus and peripheral clock frequencies are modified, thus providing communications at a bit rate which is independent for the core/bus/ peripheral clock. This mode of operation is possible by using the internally generated independent clock sources. Internal clocks can be independently selected between SLCK, MAINCK, any available PLL clock, and MCK by configuring PMC_PCKx.CSS. The independent clock sources can be also divided by configuring PMC_PCKx.PRES. Each internal clock signal (PCKx) can be enabled and disabled by writing a ‘1’ to the corresponding PMC_SCER.PCKx and PMC_SCDR.PCKx, respectively. The status of the internal clocks are given in PMC_SCSR.PCKx. The status flag PMC_SR.PCKRDYx indicates that the programmable internal clock has been programmed in the Programmable clock registers. The independent clock source must also be selected in each peripheral in the Clock Assignments table to operate communications, timings, etc without influencing the frequency of the core/bus/peripherals (except frequency limitations listed in each peripheral). Table 31-1. Clock Assignments Clock Name Peripheral PCK3 ETM PCK4 UARTx/USARTx PCK5 MCANx PCK6 TCx PCK7 TC0 Note: USB, GMAC and MLB do not require PCKx to operate independently of core and bus peripherals.

31.9 Peripheral and Generic Clock Controller

The PMC controls the clocks of the embedded peripherals by means of the Peripheral Control register (PMC_PCR). With this register, the user can enable and disable the different clocks used by the peripherals:

Peripheral clocks (periph_clk[PID]), routed to every peripheral and derived from the master clock (MCK), and
Generic clocks (GCLK[PID]), routed to I2SC0 and I2SC1. These clocks are independent of the core and bus clocks (HCLK, MCK and periph_clk[PID]). They are generated by selection and division of the following sources: SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 236

SLCK, MAINCK, UPLLCKDIV, PLLACK and MCK. Refer to the description of each peripheral for the limitation to be applied to GCLK[PID] compared to periph_clk[PID]. To configure a peripheral’s clocks, PMC_PCR.CMD must be written to ‘1’ and PMC_PCR.PID must be written with the index of the corresponding peripheral. All other configuration fields must be correctly set. To read the current clock configuration of a peripheral, PMC_PCR.CMD must be written to ‘0’ and PMC_PCR.PID must be written with the index of the corresponding peripheral regardless of the values of other fields. This write does not modify the configuration of the peripheral. The PMC_PCR can then be read to know the configuration status of the corresponding PID. The user can also enable and disable these clocks by configuring the Peripheral Clock Enable (PMC_PCERx) and Peripheral Clock Disable (PMC_PCDRx) registers. The status of the peripheral clock activity can be read in the Peripheral Clock Status registers (PMC_PCSRx). When a peripheral or a generic clock is disabled, it is immediately stopped. These clocks are disabled after a reset. To stop a peripheral clock, it is recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system. The bit number in PMC_PCERx, PMC_PCDRx, and PMC_PCSRx is the Peripheral Identifier defined at the product level. The bit number corresponds to the interrupt source number assigned to the peripheral.

31.10 Asynchronous Partial Wakeup

31.10.1 Description

The asynchronous partial wakeup wakes up a peripheral in a fully asynchronous way when activity is detected on the communication line. The asynchronous partial wakeup function automatically manages the peripheral clock. It reduces overall power consumption of the system by clocking peripherals only when needed. Asynchronous partial wakeup can be enabled in Wait mode (SleepWalking), or in Active mode. Only the following peripherals can be configured with asynchronous partial wakeup: UARTx and TWIHSx. The peripheral selected for asynchronous partial wakeup must first be configured so that its clock is enabled. To do so, write a ‘1’ to the appropriate PIDx bit in PMC_PCER registers.

31.10.2 Asynchronous Partial Wakeup in Wait Mode (SleepWalking)

When the system is in Wait mode, all clocks of the system except SLCK are stopped. When an asynchronous clock request from a peripheral occurs, the PMC partially wakes up the system to feed the clock only to this peripheral. The rest of the system is not fed with the clock, thus optimizing power consumption. Finally, depending on user-configurable conditions, the peripheral either wakes up the whole system if these conditions are met or stops the peripheral clock until the next clock request. If a wakeup request occurs, SleepWalking is automatically disabled until the user instructs the PMC to enable SleepWalking. This is done by writing a ‘1’ to PIDx in the PMC SleepWalking Enable register (PMC_SLPWK_ER). Figure 31-2. SleepWalking Waveforms system_clock peripheral_clock peripheral clock request peripheral wakeup request peripheral sleepwalking status The wakeup request wakes up the system and resets the sleepwalking status of the peripheral The system is in wait mode. No clock is fed to the system. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 237

31.10.2.1 Configuration Procedure

Before configuring SleepWalking for a peripheral, check that the PIDx bit in PMC_PCSR is set. This ensures that the peripheral clock is enabled. The steps to enable SleepWalking for a peripheral are the following: 1. Check that the corresponding PIDx bit in the PMC SleepWalking Activity Status register (PMC_SLPWK_ASR) is set to ‘0’. This ensures that the peripheral has no activity in progress. 2. Enable SleepWalking for the peripheral by writing a ‘1’ to the corresponding PIDx bit in the PMC_SLPWK_ER. 3. Check that the corresponding PIDx bit in PMC_SLPWK_ASR is set to ‘0’. This ensures that no activity has started during the enable phase. 4. In the PMC_SLPWK_ASR, if the corresponding PIDx bit is set, SleepWalking must be immediately disabled by writing a ‘1’ to the PIDx bit in the PMC SleepWalking Disable register (PMC_SLPWK_DR). Wait for the end of peripheral activity before reinitializing the procedure. If the corresponding PIDx bit is set to ‘0’, then the peripheral clock is disabled and the system can then be placed in Wait mode. Before entering Wait mode, check that the AIP bit in the PMC SleepWalking Activity In Progress Register (PMC_SLPWK_AIPR) is cleared. This ensures that none of the peripherals is currently active. Note: When SleepWalking for a peripheral is enabled and the core is running (system not in Wait mode), the peripheral must not be accessed before a wakeup of the peripheral is performed.

31.10.3 Asynchronous Partial Wakeup in Active Mode

When the system is in Active mode, peripherals enabled for asynchronous partial wakeup have their respective clocks stopped until the peripherals request a clock. When a peripheral requests the clock, the PMC provides the clock without processor intervention. The triggering of the peripheral clock request depends on conditions which can be configured for each peripheral. If these conditions are met, the peripheral asserts a request to the PMC. The PMC disables the Asynchronous Partial Wakeup mode of the peripheral and provides the clock to the peripheral until the user instructs the PMC to re-enable partial wakeup on the peripheral. This is done by setting PMC_SLPWK_ER.PIDx. If the conditions are not met, the peripheral clears the clock request and the PMC stops the peripheral clock until the clock request is reasserted by the peripheral. Note: Configuring Asynchronous Partial Wake-up mode requires the same registers as Sleep-Walking mode. Figure 31-3. Asynchronous Partial Wake-up in Active Mode system_clock peripheral_clock Peripheral clock request Peripheral wakeup request Peripheral SleepWalking status The wakeup request resets the SleepWalking status of the peripheral

31.10.3.1 Configuration Procedure

Before configuring the asynchronous partial wakeup function of a peripheral, check that the PIDx bit in PMC_PCSR is set. This ensures that the peripheral clock is enabled. The steps to enable the asynchronous partial wakeup function of a peripheral are the following: 1. Check that the corresponding PIDx bit in the PMC SleepWalking Activity Status register (PMC_SLPWK_ASR) is set to ‘0’. This ensures that the peripheral has no activity in progress. 2. Enable the asynchronous partial wakeup function of the peripheral by writing a ‘1’ to the corresponding PIDx bit in the PMC_SLPWK_ER. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 238

Check that the corresponding PIDx bit in PMC_SLPWK_ASR is set to ‘0’. This ensures that no activity has started during the enable phase. If an activity has started during the enable phase, the asynchronous partial wakeup function must be immediately disabled by writing a ‘1’ to the PIDx bit in the PMC SleepWalking Disable register (PMC_SLPWK_DR). Wait for the end of peripheral activity before reinitializing the procedure.

31.11 Free-running Processor Clock

The free-running Processor clock (FCLK) used for sampling interrupts and clocking debug blocks ensures that interrupts can be sampled, and sleep events can be traced, while the processor is sleeping.

31.12 Programmable Clock Output Controller

The PMC controls three signals to be output on the external pins PCKx. Each signal can be independently programmed via the Programmable Clock registers (PMC_PCKx). PCKx can be independently selected between SLCK, MAINCK, PLLACK, UPLLCKDIV and MCK by configuring PMC_PCKx.CSS. Each output signal can also be divided by 1 to 256 by configuring PMC_PCKx.PRES. Each output signal can be enabled and disabled by writing a ‘1’ to the corresponding bits PMC_SCER.PCKx and PMC_SCDR.PCKx, respectively. The status of the active programmable output clocks is given in PMC_SCSR.PCKx. The status flag PMC_SR.PCKRDYx indicates that PCKx is actually what has been programmed in registers PMC_PCKx. As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable PCKx before any configuration change and to re-enable it after the change is performed.

31.13 Fast Startup

At exit from Wait mode, the device allows the processor to restart in several microseconds only if the C-code function that manages the Wait mode entry and exit is linked to and executed from on-chip SRAM. The fast startup time cannot be achieved if the first instruction after an exit is located in the embedded Flash. If fast startup is not required, or if the first instruction after exit from Wait mode is located in embedded Flash, see "Startup from Embedded Flash". To instruct the device to enter Wait mode, refer to section “Power Considerations”. A fast startup occurs upon the detection of a programmed level on one of the 14 wakeup inputs (WKUP) or upon an active alarm from the RTC, RTT and USB Controller. The polarity of each of the 14 wakeup inputs is programmable in the PMC Fast Startup Polarity Register (PMC_FSPR). WARNINGThe duration of the WKUPx pins active level must be greater than four MAINCK cycles. The fast startup circuitry, as shown in the following figure, is fully asynchronous and provides a fast startup signal to the PMC. As soon as the fast startup signal is asserted, the Main RC oscillator restarts automatically. When entering Wait mode, the embedded Flash can be placed in one of the low-power modes (Deep-powerdown or Standby mode) with PMC_FSMR.FLPM. FLPM can be configured at any time and its value will be applied to the next Wait mode period. The power consumption reduction is optimal when PMC_FSMR.FLPM is configured to ‘1’ (Deep-powerdown mode). If the field is configured to ‘0’ (Standby mode), the power consumption is slightly higher than in Deep-powerdown mode. When PMC_FSMR.FLPM is configured to ‘2’, the Wait mode Flash power consumption is equivalent to that of the Active mode when there is no read access on the Flash. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 239

Figure 31-4. Fast Startup Circuitry fast_resta rt GMAC Wake on LAN event FSTT14 FSTP14 WKUP13 FSTT13 FSTP13 WKUP0 FSTT0 FSTP0 RTTAL RTCAL USBAL RTT Alarm RTC Alarm FSTT15 FSTP15 Processor CDBGPWRUPREQ USBHS Interrupt Line Each wakeup input pin and alarm can be enabled to generate a fast startup event by setting the corresponding bit in PMC_FSMR. The user interface does not provide any status for fast startup. The status can be read in the PIO Controller and the status registers of the RTC, RTTand USB Controller. Related Links 7. Power Considerations

31.14 Startup from Embedded Flash

The inherent startup time of the embedded Flash cannot provide a fast startup of the system. If system fast startup time is not required, the first instruction after a Wait mode exit can be located in the embedded Flash. Under these conditions, prior to entering Wait mode, the Flash controller must be programmed to perform access in 0 wait-state (refer to the embedded Flash controller section). The procedure and conditions to enter Wait mode and the circuitry to exit Wait mode are strictly the same as fast startup (see "Fast Startup"). Related Links 22. Enhanced Embedded Flash Controller (EEFC)

31.15 Main Crystal Oscillator Failure Detection

The Main crystal oscillator failure detector monitors the Main crystal oscillator against the Slow RC oscillator and provides an automatic switchover of the MAINCK source to the Main RC oscillator in case of failure detection. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 240

The failure detector can be enabled or disabled by configuring the CKGR_MOR.CFDEN, and it can also be disabled in either of the following cases:

After a VDDCORE reset
When the Main crystal oscillator is disabled (MOSCXTEN = 0) A failure is detected by means of a counter incrementing on the Main crystal oscillator output and detection logic is triggered by the Slow RC oscillator which is automatically enabled when CFDEN = 1. The counter is cleared when the Slow RC oscillator clock signal is low and enabled when the signal is high. Thus, the failure detection time is one Slow RC oscillator period. If, during the high level period of the Slow RC oscillator clock signal, less than eight Main crystal oscillator clock periods have been counted, then a failure is reported. Note that when enabling the failure detector, up to two cycles of the Slow RC oscillator are needed to detect a failure of the Main crystal oscillator. If a failure of Main crystal oscillator is detected, PMC_SR.CFDEV and PMC_SR.FOS both indicate a failure event. PMC_SR.CFDEV is cleared on read of PMC_SR, and PMC_SR.FOS is cleared by writing a ‘1’ to the FOCLR bit in the PMC Fault Output Clear Register (PMC_FOCR). Only PMC_SR.CFDEV can generate an interrupt if the corresponding interrupt source is enabled in PMC_IER. The current status of the clock failure detection can be read at any time from PMC_SR.CFDS. Figure 31-5. Clock Failure Detection Example Main Crystal Oscillator Output Slow Clock Note: Ratio of clock periods is for illustration purposes only. CFDEV CFDS Read PMC_SR If the Main crystal oscillator is selected as the source clock of MAINCK (CKGR_MOR.MOSCSEL = 1), and if the MCK source is PLLACK or UPLLCKDIV (CSS = 2 or 3), a clock failure detection automatically forces MAINCK to be the source clock for MCK. Then, regardless of the PMC configuration, a clock failure detection automatically forces the Main RC oscillator to be the source clock for MAINCK. If the Main RC oscillator is disabled when a clock failure detection occurs, it is automatically re-enabled by the clock failure detection mechanism. Two Slow RC oscillator clock cycles are necessary to detect and switch from the Main crystal oscillator to the Main RC oscillator if the source of MCK is MAINCK, or three Slow RC oscillator clock cycles if the source of MCK is PLLACK or UPLLCKDIV. A clock failure detection activates a fault output that is connected to the Pulse Width Modulator (PWM) Controller. With this connection, the PWM controller is able to force its outputs and to protect the driven device, if a clock failure is detected. 31.16 32.768 kHz Crystal Oscillator Frequency Monitor The frequency of the 32.768 kHz crystal oscillator can be monitored by means of logic driven by the Main RC oscillator known as a reliable clock source. This function is enabled by configuring the XT32KFME bit of CKGR_MOR. Prior to enabling this frequency monitor, the 32.768 kHz crystal oscillator must be started and its startup time be elapsed. Refer to details on the Slow clock generator in the section “Supply Controller (SUPC)”. An error flag (XT32KERR in PMC_SR) is asserted when the 32.768 kHz crystal oscillator frequency is out of the ±10% nominal frequency value (i.e., 32.768 kHz). The error flag can be cleared only if the frequency monitor is disabled. When the Main RC oscillator frequency is set to 4 MHz, the accuracy of the measurement is ±40% as this frequency is not trimmed during production. Therefore, ±10% accuracy is obtained only if the Main RC oscillator frequency is configured for 8 or 12 MHz. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 241

The monitored clock frequency is declared invalid if at least 4 consecutive clock period measurement results are over the nominal period ±10%. Note that modifying the trimming values of the Main RC oscillator (PMC_OCR) may impact the monitor accuracy and lead to inappropriate failure detection. Due to the possible frequency variation of the Main RC oscillator acting as reference clock for the monitor logic, any 32.768 kHz crystal frequency deviation over ±10% of the nominal frequency is systematically reported as an error by means of PMC_SR.XT32KERR. Between -1% and -10% and +1% and +10%, the error is not systematically reported. Thus only a crystal running at 32.768 kHz frequency ensures that the error flag will not be asserted. The permitted drift of the crystal is 10000 ppm (1%), which allows any standard crystal to be used. If the Main RC oscillator frequency range needs to be changed while the frequency monitor is operating, the monitoring must be stopped prior to change the Main RC oscillator frequency. Then it can be re-enabled as soon as PMC_SR.MOSCRCS is set. The error flag can be defined as an interrupt source of the PMC by setting PMC_IER.XT32KERR. This flag is also routed to the RSTC and may generate a reset of the device. Related Links 23. Supply Controller (SUPC)

31.17 Recommended Programming Sequence

Follow the steps below to program the PMC: 1. If the Main crystal oscillator is not required, the PLL and divider can be directly configured ( Step 6.) else this oscillator must be started (Step 2.). 2. Enable the Main crystal oscillator by setting CKGR_MOR.MOSCXTEN. The user can define a startup time. This can be done by configuring the appropriate value in CKGR_MOR.MOSCXTST. Once this register has been correctly configured, the user must wait for PMC_SR.MOSCXTS to be set. This can be done either by polling PMC_SR.MOSCXTS, or by waiting for the interrupt line to be raised if the associated interrupt source (MOSCXTS) has been enabled in PMC_IER. 3. Switch MAINCK to the Main crystal oscillator by setting CKGR_MOR.MOSCSEL. 4. Wait for PMC_SR.MOSCSELS to be set to ensure the switch is complete. 5. Check MAINCK frequency: This frequency can be measured via CKGR_MCFR. Read CKGR_MCFR until the MAINFRDY field is set, after which the user can read CKGR_MCFR.MAINF by performing an additional read. This provides the number of Main clock cycles that have been counted during a period of 16 SLCK cycles. If MAINF = 0, switch MAINCK to the Main RC Oscillator by clearing CKGR_MOR.MOSCSEL. If MAINF ≠ 0, proceed to Step 6. 6. Set PLLA and Divider (if not required, proceed to Step 7.): All parameters needed to configure PLLA and the divider are located in CKGR_PLLAR. CKGR_PLLAR.DIVA is used to control the divider. This parameter can be programmed between 0 and 127. Divider output is divider input divided by DIVA parameter. By default, DIVA field is cleared which means that the divider and PLLA are turned off. CKGR_PLLAR.MULA is the PLLA multiplier factor. This parameter can be programmed between 0 and 62. If MULA is cleared, PLLA will be turned off, otherwise the PLLA output frequency is PLLA input frequency multiplied by (MULA + 1). CKGR_PLLAR.PLLACOUNT specifies the number of SLCK cycles before PMC_SR.LOCKA is set after CKGR_PLLAR has been written. Once CKGR_PLLAR has been written, the user must wait for PMC_SR.LOCKA to be set. This can be done either by polling PMC_SR.LOCKA or by waiting for the interrupt line to be raised if the associated interrupt source (LOCKA) has been enabled in PMC_IER. All fields in CKGR_PLLAR can be programmed in a single write operation. If MULA or DIVA is modified, the LOCKA bit goes low to indicate that PLLA is not yet ready. When PLLA is locked, LOCKA is set again. The user must wait for the LOCKA bit to be set before using the PLLA output clock. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 242

Select MCK and HCLK: MCK and HCLK are configurable via PMC_MCKR. CSS is used to select the clock source of MCK and HCLK. By default, the selected clock source is MAINCK. PRES is used to define the HCLK and MCK prescaler.s The user can choose between different values (1, 2, 3, 4, 8, 16, 32, 64). Prescaler output is the selected clock source frequency divided by the PRES value. MDIV is used to define the MCK divider. It is possible to choose between different values (0, 1, 2, 3). MCK output is the HCLK frequency divided by 1, 2, 3 or 4, depending on the value programmed in MDIV. By default, MDIV is cleared, which indicates that the HCLK is equal to MCK. Once the PMC_MCKR has been written, the user must wait for PMC_SR.MCKRDY to be set. This can be done either by polling PMC_SR.MCKRDY or by waiting for the interrupt line to be raised if the associated interrupt source (MCKRDY) has been enabled in PMC_IER. PMC_MCKR must not be programmed in a single write operation. The programming sequence for PMC_MCKR is as follows: If a new value for PMC_MCKR.CSS corresponds to any of the available PLL clocks: a. Program PMC_MCKR.PRES. b. Wait for PMC_SR.MCKRDY to be set. c. Program PMC_MCKR.MDIV. d. Wait for PMC_SR.MCKRDY to be set. e. Program PMC_MCKR.CSS. f. Wait for PMC_SR.MCKRDY to be set. If a new value for PMC_MCKR.CSS corresponds to MAINCK or SLCK: a. Program PMC_MCKR.CSS. b. Wait for PMC_SR.MCKRDY to be set. c. Program PMC_MCKR.PRES. d. Wait for PMC_SR.MCKRDY to be set. If CSS, MDIV or PRES are modified at any stage, the MCKRDY bit goes low to indicate that MCK and HCLK are not yet ready. The user must wait for MCKRDY bit to be set again before using MCK and HCLK. Note: If PLLA clock was selected as MCK and the user decides to modify it by writing a new value into CKGR_PLLAR, the MCKRDY flag will go low while PLLA is unlocked. Once PLLA is locked again, LOCKA goes high and MCKRDY is set. While PLLA is unlocked, MCK selection is automatically changed to SLCK for PLLA. For further information, see "Clock Switching Waveforms". MCK is MAINCK divided by 2. 8. Select the Programmable clocks (PCKx): PCKx are controlled via registers PMC_SCER, PMC_SCDR and PMC_SCSR. PCKx can be enabled and/or disabled via PMC_SCER and PMC_SCDR. Three PCKx can be used. PMC_SCSR indicates which PCKx is enabled. By default all PCKx are disabled. PMC_PCKx registers are used to configure PCKx. PMC_PCKx.CSS is used to select the PCKx divider source. Several clock options are available: – MAINCK – SLCK – MCK – PLLACK – UPLLCKDIV SLCK is the default clock source. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 243

PMC_PCKx.PRES is used to control the PCKx prescaler. It is possible to choose between different values (1 to 256). PCKx output is prescaler input divided by PRES. By default, the PRES value is cleared which means that PCKx is equal to Slow clock. Once PMC_PCKx has been configured, the corresponding PCKx must be enabled and the user must wait for PMC_SR.PCKRDYx to be set. This can be done either by polling PMC_SR.PCKRDYx or by waiting for the interrupt line to be raised if the associated interrupt source (PCKRDYx) has been enabled in PMC_IER. All parameters in PMC_PCKx can be programmed in a single write operation. If the PMC_PCKx.CSS and PMC_PCKx.PRES parameters are to be modified, the corresponding PCKx must be disabled first. The parameters can then be modified. Once this has been done, the user must re-enable PCKx and wait for the PCKRDYx bit to be set. 9. Enable the peripheral clocks Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers PMC_PCERx and PMC_PCDRx.

31.18 Clock Switching Details

31.18.1 Master Clock Switching Timings

The following two tables, Clock Switching Timings (Worst Case) and Clock Switching Timings Between Two PLLs (Worst Case) give the worst case timings required for MCK to switch from one selected clock to another one. This is in the event that the prescaler is deactivated. When the prescaler is activated, an additional time of 64 clock cycles of the newly selected clock has to be added. Table 31-2. Clock Switching Timings (Worst Case) From MAINCK SLCK PLL Clock To MAINCK – 4 x SLCK + 2.5 x MAINCK 3 x PLL Clock + 4 x SLCK + 1 x MAINCK SLCK 0.5 x MAINCK + 4.5 x SLCK – 3 x PLL Clock + 5 x SLCK PLL Clock 0.5 x MAINCK + 4 x SLCK + PLLCOUNT x SLCK + 2.5 x PLL Clock 2.5 x PLL Clock + 5 x SLCK + PLLCOUNT x SLCK See the following table. Notes: 1. PLL designates any available PLL of the Clock Generator. 2. PLLCOUNT designates either PLLACOUNT or UPLLCOUNT. Table 31-3. Clock Switching Timings Between Two PLLs (Worst Case) From PLLACK UPLL Clock To PLLACK – 3 x PLLACK + 4 x SLCK + 1.5 x PLLACK UPLLCKDIV 3 x UPLLCKDIV + 4 x SLCK + 1.5 x UPLLCKDIV SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 244

31.18.2 Clock Switching Waveforms

Figure 31-6. Switch Master Clock (MCK) from Slow Clock to PLLx Clock Slow Clock LOCK MCKRDY MCK Write PMC_MCKR PLLx Clock Figure 31-7. Switch Master Clock (MCK) from Main Clock (MAINCK) to Slow Clock Slow Clock MAINCK MCKRDY MCK Write PMC_MCKR SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 245

Figure 31-8. Change PLLA Programming Slow Clock Slow Clock PLLA Clock LOCKA MCKRDY MCK Write CKGR_PLLAR Figure 31-9. Programmable Clock Output Programming Any PLL Clock PCKRDY PCKx Output Write PMC_PCKx Write PMC_SCER Write PMC_SCDR PCKx is disabled PCKx is enabled PLL Clock is selected

31.19 Register Write Protection

To prevent any single software error from corrupting PMC behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the PMC Write Protection Mode Register (PMC_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the PMC Write Protection Status Register (PMC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS bit is automatically cleared after reading the PMC_WPSR. The following registers are write-protected when the WPEN bit is set in PMC_WPMR:

PMC System Clock Disable Register SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 246

PMC Peripheral Clock Enable Register 0
PMC Peripheral Clock Disable Register 0
PMC Clock Generator Main Oscillator Register
PMC Clock Generator Main Clock Frequency Register
PMC Clock Generator PLLA Register
PMC UTMI Clock Configuration Register
PMC Master Clock Register
PMC USB Clock Register
PMC Programmable Clock Register
PMC Fast Startup Mode Register
PMC Fast Startup Polarity Register
PMC Peripheral Clock Enable Register 1
PMC Peripheral Clock Disable Register 1
PMC Oscillator Calibration Register
PMC SleepWalking Enable Register 0
PMC SleepWalking Disable Register 0
PLL Maximum Multiplier Value Register
PMC SleepWalking Enable Register 1
PMC SleepWalking Disable Register 1 SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 247

31.20 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 PMC_SCER 7:0 USBCLK 15:8 PCK7 PCK6 PCK5 PCK4 PCK3 PCK2 PCK1 PCK0 23:16 31:24 0x04 PMC_SCDR 7:0 USBCLK 15:8 PCK7 PCK6 PCK5 PCK4 PCK3 PCK2 PCK1 PCK0 23:16 31:24 0x08 PMC_SCSR 7:0 USBCLK HCLKS 15:8 PCK7 PCK6 PCK5 PCK4 PCK3 PCK2 PCK1 PCK0 23:16 31:24 0x0C ... 0x0F Reserved 0x10 PMC_PCER0 7:0 PID7 15:8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 23:16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 31:24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 0x14 PMC_PCDR0 7:0 PID7 15:8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 23:16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 31:24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 0x18 PMC_PCSR0 7:0 PID7 15:8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 23:16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 31:24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 0x1C CKGR_UCKR 7:0 15:8 23:16 UPLLCOUNT[3:0] UPLLEN 31:24 0x20 CKGR_MOR 7:0 MOSCRCF[2:0] MOSCRCEN WAITMODE MOSCXTBY MOSCXTEN 15:8 MOSCXTST[7:0] 23:16 KEY[7:0] 31:24 XT32KFME CFDEN MOSCSEL 0x24 CKGR_MCFR 7:0 MAINF[7:0] 15:8 MAINF[15:8] 23:16 RCMEAS MAINFRDY 31:24 CCSS 0x28 CKGR_PLLAR 7:0 DIVA[7:0] 15:8 PLLACOUNT[5:0] 23:16 MULA[7:0] 31:24 ONE MULA[10:8] 0x2C ... 0x2F Reserved 0x30 PMC_MCKR 7:0 PRES[2:0] CSS[1:0] 15:8 UPLLDIV2 MDIV[1:0] 23:16 31:24 0x34 ... 0x37 Reserved SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 248

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x38 PMC_USB 7:0 USBS 15:8 USBDIV[3:0] 23:16 31:24 0x3C ... 0x3F Reserved 0x40 PMC_PCKx0 7:0 PRES[3:0] CSS[2:0] 15:8 PRES[7:4] 23:16 31:24 0x44 PMC_PCKx1 7:0 PRES[3:0] CSS[2:0] 15:8 PRES[7:4] 23:16 31:24 0x48 PMC_PCKx2 7:0 PRES[3:0] CSS[2:0] 15:8 PRES[7:4] 23:16 31:24 0x4C PMC_PCKx3 7:0 PRES[3:0] CSS[2:0] 15:8 PRES[7:4] 23:16 31:24 0x50 PMC_PCKx4 7:0 PRES[3:0] CSS[2:0] 15:8 PRES[7:4] 23:16 31:24 0x54 PMC_PCKx5 7:0 PRES[3:0] CSS[2:0] 15:8 PRES[7:4] 23:16 31:24 0x58 PMC_PCKx6 7:0 PRES[3:0] CSS[2:0] 15:8 PRES[7:4] 23:16 31:24 0x5C PMC_PCKx7 7:0 PRES[3:0] CSS[2:0] 15:8 PRES[7:4] 23:16 31:24 0x60 PMC_IER 7:0 LOCKU MCKRDY LOCKA MOSCXTS 15:8 PCKRDY7 PCKRDY6 PCKRDY5 PCKRDY4 PCKRDY3 PCKRDY2 PCKRDY1 PCKRDY0 23:16 XT32KERR CFDEV MOSCRCS MOSCSELS 31:24 0x64 PMC_IDR 7:0 LOCKU MCKRDY LOCKA MOSCXTS 15:8 PCKRDY7 PCKRDY6 PCKRDY5 PCKRDY4 PCKRDY3 PCKRDY2 PCKRDY1 PCKRDY0 23:16 XT32KERR CFDEV MOSCRCS MOSCSELS 31:24 0x68 PMC_SR 7:0 OSCSELS LOCKU MCKRDY LOCKA MOSCXTS 15:8 PCKRDY7 PCKRDY6 PCKRDY5 PCKRDY4 PCKRDY3 PCKRDY2 PCKRDY1 PCKRDY0 23:16 XT32KERR FOS CFDS CFDEV MOSCRCS MOSCSELS 31:24 0x6C PMC_IMR 7:0 LOCKU MCKRDY LOCKA MOSCXTS 15:8 PCKRDY7 PCKRDY6 PCKRDY5 PCKRDY4 PCKRDY3 PCKRDY2 PCKRDY1 PCKRDY0 23:16 XT32KERR CFDEV MOSCRCS MOSCSELS 31:24 0x70 PMC_FSMR 7:0 FSTT7 FSTT6 FSTT5 FSTT4 FSTT3 FSTT2 FSTT1 FSTT0 15:8 FSTT15 FSTT14 FSTT13 FSTT12 FSTT11 FSTT10 FSTT9 FSTT8 23:16 FFLPM FLPM[1:0] LPM USBAL RTCAL RTTAL 31:24 SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 249

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x74 PMC_FSPR 7:0 FSTP7 FSTP6 FSTP5 FSTP4 FSTP3 FSTP2 FSTP1 FSTP0 15:8 FSTP15 FSTP14 FSTP13 FSTP12 FSTP11 FSTP10 FSTP9 FSTP8 23:16 31:24 0x78 PMC_FOCR 7:0 FOCLR 15:8 23:16 31:24 0x7C ... 0xE3 Reserved 0xE4 PMC_WPMR 7:0 WPEN 15:8 WPKEY[7:0] 23:16 WPKEY[15:8] 31:24 WPKEY[23:16] 0xE8 PMC_WPSR 7:0 WPVS 15:8 WPVSRC[7:0] 23:16 WPVSRC[15:8] 31:24 0xEC ... 0xFF Reserved 0x0100 PMC_PCER1 7:0 PID[0] PID PID[3:0] 15:8 PID[8:1] 23:16 PID[16:9] 31:24 PID PID[21:17] 0x0104 PMC_PCDR1 7:0 PID[0] PID PID[3:0] 15:8 PID[8:1] 23:16 PID[16:9] 31:24 PID PID[21:17] 0x0108 PMC_PCSR1 7:0 PID0 15:8 PID8 PID7 PID6 PID5 PID4 PID3 PID2 PID1 23:16 PID16 PID15 PID14 PID13 PID12 PID11 PID10 PID9 31:24 PID24 PID23 PID22 PID21 PID20 PID19 PID18 PID17 0x010C PMC_PCR 7:0 PID[6:0] 15:8 CMD GCLKCSS[2:0] 23:16 GCLKDIV[3:0] 31:24 GCLKEN EN GCLKDIV[7:4] 0x0110 PMC_OCR 7:0 SEL4 CAL4[6:0] 15:8 SEL8 CAL8[6:0] 23:16 SEL12 CAL12[6:0] 31:24 0x0114 PMC_SLPWK_ER0 7:0 PID7 15:8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 23:16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 31:24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 0x0118 PMC_SLPWK_DR0 7:0 PID7 15:8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 23:16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 31:24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 0x011C PMC_SLPWK_SR0 7:0 PID7 15:8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 23:16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 31:24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 0x0120 PMC_SLPWK_ASR 7:0 PID7 15:8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 23:16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 31:24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 250

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x0124 ... 0x012F Reserved 0x0130 PMC_PMMR 7:0 PLLA_MMAX[7:0] 15:8 PLLA_MMAX[10:8] 23:16 31:24 0x0134 PMC_SLPWK_ER1 7:0 PID[0] PID PID[3:0] 15:8 PID[8:1] 23:16 PID[16:9] 31:24 PID PID[21:17] 0x0138 PMC_SLPWK_DR1 7:0 PID[0] PID PID[3:0] 15:8 PID[8:1] 23:16 PID[16:9] 31:24 PID PID[21:17] 0x013C PMC_SLPWK_SR1 7:0 PID[0] PID PID[3:0] 15:8 PID[8:1] 23:16 PID[16:9] 31:24 PID PID[21:17] 0x0140 PMC_SLPWK_ASR 7:0 PID[0] PID PID[3:0] 15:8 PID[8:1] 23:16 PID[16:9] 31:24 PID PID[21:17] 0x0144 PMC_SLPWK_AIPR 7:0 AIP 15:8 23:16 31:24 SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 251

31.20.1 PMC System Clock Enable Register

Name: PMC_SCER Offset: 0x0000 Reset: – Property: Write-only This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 PCK7 PCK6 PCK5 PCK4 PCK3 PCK2 PCK1 PCK0 Access W W W W W W W W Bit 7 6 5 4 3 2 1 0 USBCLK Access W Reset – Bits 8, 9, 10, 11, 12, 13, 14, 15 – PCK Programmable Clock x Output Enable Value Description 0 No effect. 1 Enables the corresponding Programmable Clock output. Bit 5 – USBCLK Enable USB FS Clock Value Description 0 No effect. 1 Enables USB FS clock. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 252

31.20.2 PMC System Clock Disable Register

Name: PMC_SCDR Offset: 0x0004 Reset: – Property: Write-only This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 PCK7 PCK6 PCK5 PCK4 PCK3 PCK2 PCK1 PCK0 Access W W W W W W W W Bit 7 6 5 4 3 2 1 0 USBCLK Access W Reset – Bits 8, 9, 10, 11, 12, 13, 14, 15 – PCK Programmable Clock x Output Disable Value Description 0 No effect. 1 Disables the corresponding Programmable Clock output. Bit 5 – USBCLK Disable USB FS Clock Value Description 0 No effect. 1 Disables USB FS clock. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 253

31.20.3 PMC System Clock Status Register

Name: PMC_SCSR Offset: 0x0008 Reset: 0x00000001 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 PCK7 PCK6 PCK5 PCK4 PCK3 PCK2 PCK1 PCK0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 USBCLK HCLKS Access R R Reset 0 1 Bits 8, 9, 10, 11, 12, 13, 14, 15 – PCK Programmable Clock x Output Status Value Description 0 The corresponding Programmable Clock output is disabled. 1 The corresponding Programmable Clock output is enabled. Bit 5 – USBCLK USB FS Clock Status Value Description 0 The USB FS clock is disabled. 1 The USB FS clock is enabled. Bit 0 – HCLKS HCLK Status Value Description 0 HCLK is disabled. 1 HCLK is enabled. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 254

31.20.4 PMC Peripheral Clock Enable Register 0

Name: PMC_PCER0 Offset: 0x0010 Reset: – Property: Write-only This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. PIDx refers to identifiers defined in the section “Peripheral Identifiers”. Other peripherals can be enabled in PMC_PCER1 (see "PMC Peripheral Clock Enable Register 1"). Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC. Bit 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 Access W W W W W W W W Bit 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 Access W W W W W W W W Bit 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 Access W W W W W W W W Bit 7 6 5 4 3 2 1 0 PID7 Access W Reset – Bits 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – PIDx Peripheral Clock x Enable Value Description 0 No effect. 1 Enables the corresponding peripheral clock. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 255

31.20.5 PMC Peripheral Clock Disable Register 0

Name: PMC_PCDR0 Offset: 0x0014 Reset: – Property: Write-only This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 Access W W W W W W W W Bit 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 Access W W W W W W W W Bit 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 Access W W W W W W W W Bit 7 6 5 4 3 2 1 0 PID7 Access W Reset – Bits 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – PIDx Peripheral Clock x Disable PIDx refers to identifiers defined in the section “Peripheral Identifiers”. Other peripherals can be disabled in PMC_PCDR1 (see "PMC Peripheral Clock Disable Register 1"). Value Description 0 No effect. 1 Disables the corresponding peripheral clock. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 256

31.20.6 PMC Peripheral Clock Status Register 0

Name: PMC_PCSR0 Offset: 0x0018 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PID7 Access R Reset 0 Bits 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – PIDx Peripheral Clock x Status PIDx refers to identifiers defined in the section “Peripheral Identifiers”. Other peripherals status can be read in PMC_PCSR1 (see "PMC Peripheral Clock Status Register 1"). Value Description 0 The corresponding peripheral clock is disabled. 1 The corresponding peripheral clock is enabled. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 257

31.20.7 PMC UTMI Clock Configuration Register

Name: CKGR_UCKR Offset: 0x001C Reset: 0x10200800 Property: Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 UPLLCOUNT[3:0] UPLLEN Access R/W R/W R/W R/W R/W Reset 0 0 1 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 Access Reset Bits 23:20 – UPLLCOUNT[3:0] UTMI PLL Startup Time Specifies the number of SLCK cycles multiplied by 8 for the UTMI PLL startup time. Bit 16 – UPLLEN UTMI PLL Enable When UPLLEN is set, the LOCKU flag is set once the UTMI PLL startup time is achieved. Value Description 0 The UTMI PLL is disabled. 1 The UTMI PLL is enabled. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 258

31.20.8 PMC Clock Generator Main Oscillator Register

Name: CKGR_MOR Offset: 0x0020 Reset: 0x00000008 Property: Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 XT32KFME CFDEN MOSCSEL Access R/W R/W R/W Reset 0 0 0 Bit 23 22 21 20 19 18 17 16 KEY[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 MOSCXTST[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MOSCRCF[2:0] MOSCRCEN WAITMODE MOSCXTBY MOSCXTEN Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 1 0 0 0 Bit 26 – XT32KFME 32.768 kHz Crystal Oscillator Frequency Monitoring Enable Value Description 0 The 32.768 kHz crystal oscillator frequency monitoring is disabled. 1 The 32.768 kHz crystal oscillator frequency monitoring is enabled. Bit 25 – CFDEN Clock Failure Detector Enable Value Description 0 The clock failure detector is disabled. 1 The clock failure detector is enabled. Bit 24 – MOSCSEL Main Clock Oscillator Selection Value Description 0 The Main RC oscillator is selected. 1 The Main crystal oscillator is selected. Bits 23:16 – KEY[7:0] Write Access Password Value Name Description 0x37 PASSWD Writing any other value in this field aborts the write operation. Always reads as 0. Bits 15:8 – MOSCXTST[7:0] Main Crystal Oscillator Startup Time Specifies the number of SLCK cycles multiplied by 8 for the main crystal oscillator startup time. Bits 6:4 – MOSCRCF[2:0] Main RC Oscillator Frequency Selection At startup, the Main RC oscillator frequency is 12 MHz. MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR. Therefore, MOSCRCF and MOSCRCEN cannot be changed at the same time. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 259

0 4_MHz The RC oscillator frequency is at 4 MHz 1 8_MHz The RC oscillator frequency is at 8 MHz 2 12_MHz The RC oscillator frequency is at 12 MHz Bit 3 – MOSCRCEN Main RC Oscillator Enable When MOSCRCEN is set, the MOSCRCS flag is set once the Main RC oscillator startup time is achieved. Value Description 0 The Main RC oscillator is disabled. 1 The Main RC oscillator is enabled. Bit 2 – WAITMODE Wait Mode Command (write-only) Value Description 0 No effect. 1 Puts the device in Wait mode. Bit 1 – MOSCXTBY Main Crystal Oscillator Bypass When MOSCXTBY is set, the MOSCXTS flag in PMC_SR is automatically set. Clearing MOSCXTEN and MOSCXTBY bits clears the MOSCXTS flag. When the crystal oscillator bypass is disabled (MOSCXTBY = 0), the MOSCXTS flag must be read at ‘0’ in PMC_SR before enabling the crystal oscillator (MOSCXTEN = 1). Value Description 0 No effect. 1 The Main crystal oscillator is bypassed. MOSCXTEN must be cleared. An external clock must be connected on XIN. Bit 0 – MOSCXTEN Main Crystal Oscillator Enable A crystal must be connected between XIN and XOUT. When MOSCXTEN is set, the MOSCXTS flag is set once the Main crystal oscillator startup time is achieved. Value Description 0 The Main crystal oscillator is disabled. 1 The Main crystal oscillator is enabled. MOSCXTBY must be cleared. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 260

31.20.9 PMC Clock Generator Main Clock Frequency Register

Name: CKGR_MCFR Offset: 0x0024 Reset: 0x00000000 Property: Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 CCSS Access R/W Reset 0 Bit 23 22 21 20 19 18 17 16 RCMEAS MAINFRDY Access R/W R/W Reset 0 0 Bit 15 14 13 12 11 10 9 8 MAINF[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MAINF[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 24 – CCSS Counter Clock Source Selection Value Description 0 The measured clock of the MAINF counter is the Main RC oscillator. 1 The measured clock of the MAINF counter is the Main crystal oscillator. Bit 20 – RCMEAS RC Oscillator Frequency Measure (write-only) The measurement is performed on the main frequency (i.e., not limited to the Main RC oscillator only). If the source of MAINCK is the Main crystal oscillator, the restart of measurement may not be required because of the stability of crystal oscillators. Value Description 0 No effect. 1 Restarts measuring of the frequency of MAINCK. MAINF carries the new frequency as soon as a low-to-high transition occurs on the MAINFRDY flag. Bit 16 – MAINFRDY Main Clock Frequency Measure Ready To ensure that a correct value is read on the MAINF field, the MAINFRDY flag must be read at ‘1’ then another read access must be performed on the register to get a stable value on the MAINF field. Value Description

0 MAINF value is not valid or the measured oscillator is disabled or a measure has just been started by

means of RCMEAS. 1 The measured oscillator has been enabled previously and MAINF value is available. Bits 15:0 – MAINF[15:0] Main Clock Frequency Gives the number of cycles of the clock selected by the bit CCSS within 16 SLCK periods. To calculate the frequency of the measured clock: fSELCLK = (MAINF x fSLCK)/16 where frequency is in MHz. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 261

31.20.10 PMC Clock Generator PLLA Register

Name: CKGR_PLLAR Offset: 0x0028 Reset: 0x00003F00 Property: Read/Write Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC. WARNINGBit 29 must always be set to ‘1’ when programming the CKGR_PLLAR. This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 ONE MULA[10:8] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 23 22 21 20 19 18 17 16 MULA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 PLLACOUNT[5:0] Access R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 DIVA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 29 – ONE Must Be Set to 1 Bit 29 must always be set to ‘1’ when programming the CKGR_PLLAR. Bits 26:16 – MULA[10:0] PLLA Multiplier 1 up to 62 = PLLCK frequency is the PLLA input frequency multiplied by MULA + 1. Unlisted values are forbidden. Value Description 0 The PLLA is disabled (PLLA also disabled if DIVA = 0). Bits 13:8 – PLLACOUNT[5:0] PLLA Counter Specifies the number of SLCK cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written. Bits 7:0 – DIVA[7:0] PLLA Front End Divider Value Name Description 0 0 PLLA is disabled. 1 BYPASS Divider is bypassed (divide by 1) and PLLA is enabled. 2–255 – Divider output is the selected clock divided by DIVA. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 262

31.20.11 PMC Master Clock Register

Name: PMC_MCKR Offset: 0x0030 Reset: 0x00000001 Property: Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 UPLLDIV2 MDIV[1:0] Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 PRES[2:0] CSS[1:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 1 Bit 13 – UPLLDIV2 UPLL Divider by 2 Value Description 0 UPLLCK frequency is divided by 1. 1 UPLLCK frequency is divided by 2. Bits 9:8 – MDIV[1:0] Master Clock Division Value Name Description 0 EQ_PCK MCK is FCLK divided by 1. 1 PCK_DIV2 MCK is FCLK divided by 2. 2 PCK_DIV4 MCK is FCLK divided by 4. 3 PCK_DIV3 MCK is FCLK divided by 3. Bits 6:4 – PRES[2:0] Processor Clock Prescaler Value Name Description

0 CLK_1 Selected clock

1 CLK_2 Selected clock divided by 2

2 CLK_4 Selected clock divided by 4

3 CLK_8 Selected clock divided by 8

4 CLK_16 Selected clock divided by 16

5 CLK_32 Selected clock divided by 32

6 CLK_64 Selected clock divided by 64

7 CLK_3 Selected clock divided by 3

Bits 1:0 – CSS[1:0] Master Clock Source Selection Value Name Description

0 SLOW_CLK SLCK is selected

1 MAIN_CLK MAINCK is selected

2 PLLA_CLK PLLACK is selected

3 UPLL_CLK UPPLLCKDIV is selected

31.20.12 PMC USB Clock Register

Name: PMC_USB Offset: 0x0038 Reset: 0x00000000 Property: Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 USBDIV[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 USBS Access R/W Reset 0 Bits 11:8 – USBDIV[3:0] Divider for USB_48M USB_48M is input clock divided by USBDIV+1. Bit 0 – USBS USB Input Clock Selection Value Description 0 USB_48M input is PLLA. 1 USB_48M input is UPLL. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 265

31.20.13 PMC Programmable Clock Register

Name: PMC_PCKx Offset: 0x40 + x*0x04 [x=0..7] Reset: 0x00000000 Property: Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 PRES[7:4] Access Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PRES[3:0] CSS[2:0] Access R/W R/W R/W Reset 0 0 0 0 0 0 0 Bits 11:4 – PRES[7:0] Programmable Clock Prescaler Value Description 0–255 Selected clock is divided by PRES+1. Bits 2:0 – CSS[2:0] Programmable Clock Source Selection Value Name Description

3 UPLL_CLK UPLLCKDIV is selected

4 MCK MCK is selected

31.20.14 PMC Interrupt Enable Register

Name: PMC_IER Offset: 0x0060 Property: Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 XT32KERR CFDEV MOSCRCS MOSCSELS Access W W W W Reset Bit 15 14 13 12 11 10 9 8 PCKRDY7 PCKRDY6 PCKRDY5 PCKRDY4 PCKRDY3 PCKRDY2 PCKRDY1 PCKRDY0 Access W W W W W W W W Reset Bit 7 6 5 4 3 2 1 0 LOCKU MCKRDY LOCKA MOSCXTS Access W W W Reset Bit 21 – XT32KERR 32.768 kHz Crystal Oscillator Error Interrupt Enable Bit 18 – CFDEV Clock Failure Detector Event Interrupt Enable Bit 17 – MOSCRCS Main RC Oscillator Status Interrupt Enable Bit 16 – MOSCSELS Main Clock Source Oscillator Selection Status Interrupt Enable Bits 8, 9, 10, 11, 12, 13, 14, 15 – PCKRDY Programmable Clock Ready x Interrupt Enable Bit 6 – LOCKU UTMI PLL Lock Interrupt Enable Bit 3 – MCKRDY Master Clock Ready Interrupt Enable Bit 1 – LOCKA PLLA Lock Interrupt Enable Bit 0 – MOSCXTS Main Crystal Oscillator Status Interrupt Enable SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 267

31.20.15 PMC Interrupt Disable Register

Name: PMC_IDR Offset: 0x0064 Property: Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 XT32KERR CFDEV MOSCRCS MOSCSELS Access W W W W Reset Bit 15 14 13 12 11 10 9 8 PCKRDY7 PCKRDY6 PCKRDY5 PCKRDY4 PCKRDY3 PCKRDY2 PCKRDY1 PCKRDY0 Access W W W W W W W W Reset Bit 7 6 5 4 3 2 1 0 LOCKU MCKRDY LOCKA MOSCXTS Access W W W W Reset Bit 21 – XT32KERR 32.768 kHz Crystal Oscillator Error Interrupt Disable Bit 18 – CFDEV Clock Failure Detector Event Interrupt Disable Bit 17 – MOSCRCS Main RC Status Interrupt Disable Bit 16 – MOSCSELS Main Clock Source Oscillator Selection Status Interrupt Disable Bits 8, 9, 10, 11, 12, 13, 14, 15 – PCKRDY Programmable Clock Ready x Interrupt Disable Bit 6 – LOCKU UTMI PLL Lock Interrupt Disable Bit 3 – MCKRDY Master Clock Ready Interrupt Disable Bit 1 – LOCKA PLLA Lock Interrupt Disable Bit 0 – MOSCXTS Main Crystal Oscillator Status Interrupt Disable SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 268

31.20.16 PMC Status Register

Name: PMC_SR Offset: 0x0068 Reset: 0x00030008 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 XT32KERR FOS CFDS CFDEV MOSCRCS MOSCSELS Access R R R R R R Reset 0 0 0 0 1 1 Bit 15 14 13 12 11 10 9 8 PCKRDY7 PCKRDY6 PCKRDY5 PCKRDY4 PCKRDY3 PCKRDY2 PCKRDY1 PCKRDY0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OSCSELS LOCKU MCKRDY LOCKA MOSCXTS Access R R R R Reset 0 0 1 0 0 Bit 21 – XT32KERR Slow Crystal Oscillator Error Value Description 0 The frequency of the 32.768 kHz crystal oscillator is correct (32.768 kHz ±1%) or the monitoring is disabled. 1 The frequency of the 32.768 kHz crystal oscillator is incorrect or has been incorrect for an elapsed period of time since the monitoring has been enabled. Bit 20 – FOS Clock Failure Detector Fault Output Status Value Description 0 The fault output of the clock failure detector is inactive. 1 The fault output of the clock failure detector is active. This status is cleared by writing a ‘1’ to FOCLR in PMC_FOCR. Bit 19 – CFDS Clock Failure Detector Status Value Description 0 A clock failure of the Main crystal oscillator clock is not detected. 1 A clock failure of the Main crystal oscillator clock is detected. Bit 18 – CFDEV Clock Failure Detector Event Value Description

0 No clock failure detection of the Main crystal oscillator clock has occurred since the last read of

PMC_SR. 1 At least one clock failure detection of the Main crystal oscillator clock has occurred since the last read of PMC_SR. Bit 17 – MOSCRCS Main RC Oscillator Status Value Description 0 Main RC oscillator is not stabilized. 1 Main RC oscillator is stabilized. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 269

Bit 16 – MOSCSELS Main Clock Source Oscillator Selection Status Value Description 0 Selection is in progress. 1 Selection is done. Bits 8, 9, 10, 11, 12, 13, 14, 15 – PCKRDY Programmable Clock Ready Status Value Description 0 Programmable Clock x is not ready. 1 Programmable Clock x is ready. Bit 7 – OSCSELS Slow Clock Source Oscillator Selection Value Description 0 Slow RC oscillator is selected. 1 32.768 kHz crystal oscillator is selected. Bit 6 – LOCKU UTMI PLL Lock Status Value Description

0 UTMI PLL is not locked

1 UTMI PLL is locked. Bit 3 – MCKRDY Master Clock Status Value Description 0 Master Clock is not ready. 1 Master Clock is ready. Bit 1 – LOCKA PLLA Lock Status Value Description

0 PLLA is not locked

1 PLLA is locked. Bit 0 – MOSCXTS Main Crystal Oscillator Status Value Description 0 Main crystal oscillator is not stabilized. 1 Main crystal oscillator is stabilized. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 270

31.20.17 PMC Interrupt Mask Register

Name: PMC_IMR Offset: 0x006C Reset: 0x00000000 Property: Read-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 XT32KERR CFDEV MOSCRCS MOSCSELS Access R R R R Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 PCKRDY7 PCKRDY6 PCKRDY5 PCKRDY4 PCKRDY3 PCKRDY2 PCKRDY1 PCKRDY0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LOCKU MCKRDY LOCKA MOSCXTS Access R R R R Reset 0 0 0 0 Bit 21 – XT32KERR 32.768 kHz Crystal Oscillator Error Interrupt Mask Bit 18 – CFDEV Clock Failure Detector Event Interrupt Mask Bit 17 – MOSCRCS Main RC Status Interrupt Mask Bit 16 – MOSCSELS Main Clock Source Oscillator Selection Status Interrupt Mask Bits 8, 9, 10, 11, 12, 13, 14, 15 – PCKRDY Programmable Clock Ready x Interrupt Mask Bit 6 – LOCKU UTMI PLL Lock Interrupt Mask Bit 3 – MCKRDY Master Clock Ready Interrupt Mask Bit 1 – LOCKA PLLA Lock Interrupt Mask Bit 0 – MOSCXTS Main Crystal Oscillator Status Interrupt Mask SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 271

31.20.18 PMC Fast Startup Mode Register

Name: PMC_FSMR Offset: 0x0070 Reset: 0x00000000 Property: Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 FFLPM FLPM[1:0] LPM USBAL RTCAL RTTAL Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 FSTT15 FSTT14 FSTT13 FSTT12 FSTT11 FSTT10 FSTT9 FSTT8 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FSTT7 FSTT6 FSTT5 FSTT4 FSTT3 FSTT2 FSTT1 FSTT0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 – FFLPM Force Flash Low-power Mode Value Description

0 The Flash Low-power mode, defined in the FLPM field, is automatically applied when in Wait mode and

released when going back to Active mode. 1 The Flash Low-power mode is user defined by the FLPM field and immediately applied. Bits 22:21 – FLPM[1:0] Flash Low-power Mode Value Name Description

0 FLASH_STANDBY Flash is in Standby Mode when system enters Wait Mode

1 FLASH_DEEP_POWERDOWN Flash is in Deep-powerdown mode when system enters Wait Mode

2 FLASH_IDLE Idle mode

Bit 20 – LPM Low-power Mode Value Description

0 The WaitForInterrupt (WFI) or the WaitForEvent (WFE) instruction of the processor makes the

processor enter Sleep mode. 1 The WaitForEvent (WFE) instruction of the processor makes the system enter Wait mode. Bit 18 – USBAL USB Alarm Enable Value Description 0 The USB alarm has no effect on the PMC. 1 The USB alarm enables a fast restart signal to the PMC. Bit 17 – RTCAL RTC Alarm Enable Value Description 0 The RTC alarm has no effect on the PMC. 1 The RTC alarm enables a fast restart signal to the PMC. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 272

Bit 16 – RTTAL RTT Alarm Enable Value Description 0 The RTT alarm has no effect on the PMC. 1 The RTT alarm enables a fast restart signal to the PMC. Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – FSTT Fast Startup Input Enable Value Description 0 The corresponding wake-up input has no effect on the PMC. 1 The corresponding wake-up input enables a fast restart signal to the PMC. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 273

31.20.19 PMC Fast Startup Polarity Register

Name: PMC_FSPR Offset: 0x0074 Reset: 0x00000000 Property: Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 FSTP15 FSTP14 FSTP13 FSTP12 FSTP11 FSTP10 FSTP9 FSTP8 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FSTP7 FSTP6 FSTP5 FSTP4 FSTP3 FSTP2 FSTP1 FSTP0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – FSTP Fast Startup Input Polarity x bits Defines the active polarity of the corresponding wake-up input. If the corresponding wake-up input is enabled and at the FSTP level, it enables a fast restart signal. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 274

31.20.20 PMC Fault Output Clear Register

Name: PMC_FOCR Offset: 0x0078 Property: Write-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 FOCLR Access W Reset Bit 0 – FOCLR Fault Output Clear Clears the clock failure detector fault output. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 275

31.20.21 PMC Write Protection Mode Register

Name: PMC_WPMR Offset: 0x00E4 Reset: 0x000000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 WPKEY[23:16] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 WPKEY[15:8] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 WPKEY[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WPEN Access R/W Reset 0 Bits 31:8 – WPKEY[23:0] Write Protection Key Value Name Description 0x504D43 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Bit 0 – WPEN Write Protection Enable See "Register Write Protection" for the list of registers that can be write-protected. Value Description 0 Disables the write protection if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). 1 Enables the write protection if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 276

31.20.22 PMC Write Protection Status Register

Name: PMC_WPSR Offset: 0x00E8 Reset: 0x0 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 WPVSRC[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 WPVSRC[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WPVS Access R Reset 0 Bits 23:8 – WPVSRC[15:0] Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. Bit 0 – WPVS Write Protection Violation Status Value Description 0 No write protection violation has occurred since the last read of the PMC_WPSR. 1 A write protection violation has occurred since the last read of the PMC_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 277

31.20.23 PMC Peripheral Clock Enable Register 1

Name: PMC_PCER1 Offset: 0x0100 Property: Write-only This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 PID62 PID60 PID59 PID58 PID57 PID56 Access Reset Bit 23 22 21 20 19 18 17 16 PID53 PID52 PID51 PID50 PID49 PID48 Access Reset Bit 15 14 13 12 11 10 9 8 PID47 PID46 PID45 PID44 PID43 PID42 PID41 PID40 Access Reset Bit 7 6 5 4 3 2 1 0 PID39 PID37 PID35 PID34 PID33 PID32 Access Reset Bits 0:3,5,7:28,30 – PID Peripheral Clock x Enable Value Description 0 No effect. 1 Enables the corresponding peripheral clock. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 278

31.20.24 PMC Peripheral Clock Disable Register 1

Name: PMC_PCDR1 Offset: 0x104 Property: Write-only This register can only be written if the WPEN bit is cleared in the PCM Write Protection Mode Register Bit 31 30 29 28 27 26 25 24 PID62 PID60 PID59 PID58 PID57 PID56 Access Reset Bit 23 22 21 20 19 18 17 16 PID53 PID52 PID51 PID50 PID49 PID48 Access Reset Bit 15 14 13 12 11 10 9 8 PID47 PID46 PID45 PID44 PID43 PID42 PID41 PID40 Access Reset Bit 7 6 5 4 3 2 1 0 PID39 PID37 PID35 PID34 PID33 PID32 Access Reset Bits 0:3,5,7:28,30 – PID Peripheral Clock x Disable Value Description 0 No effect. 1 Disables the corresponding peripheral clock. Note: “PIDx” refers to identifiers as defined in the section “Peripheral Identifiers”. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 279

31.20.25 PMC Peripheral Clock Status Register 1

Name: PMC_PCSR1 Offset: 0x0108 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 PID24 PID23 PID22 PID21 PID20 PID19 PID18 PID17 Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 PID16 PID15 PID14 PID13 PID12 PID11 PID10 PID9 Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 PID8 PID7 PID6 PID5 PID4 PID3 PID2 PID1 Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PID0 Access Reset 0 Bits 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – PIDx Peripheral Clock x Status Value Description 0 The corresponding peripheral clock is disabled. 1 The corresponding peripheral clock is enabled. Note: “PIDx” refers to identifiers as defined in the section “Peripheral Identifiers”. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 280

31.20.26 PMC Peripheral Control Register

Name: PMC_PCR Offset: 0x010C Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 GCLKEN EN GCLKDIV[7:4] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 GCLKDIV[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CMD GCLKCSS[2:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PID[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 29 – GCLKEN Generic Clock Enable Value Description 0 The selected generic clock is disabled. 1 The selected generic clock is enabled. Bit 28 – EN Enable Value Description 0 Selected Peripheral clock is disabled. 1 Selected Peripheral clock is enabled. Bits 27:20 – GCLKDIV[7:0] Generic Clock Division Ratio Generic clock is the selected clock period divided by GCLKDIV + 1. GCLKDIV must not be changed while the peripheral selects GCLKx (e.g., bit rate, etc.). Bit 12 – CMD Command Value Description 0 Read mode. 1 Write mode. Bits 10:8 – GCLKCSS[2:0] Generic Clock Source Selection Value Name Description

3 UPLL_CLK UPLLCK is selected

4 MCK_CLK MCK is selected

Bits 6:0 – PID[6:0] Peripheral ID Peripheral ID selection from PID2 to PID127. “PID2 to PID127” refers to identifiers as defined in section “Peripheral Identifiers”. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 282

31.20.27 PMC Oscillator Calibration Register

Name: PMC_OCR Offset: 0x0110 Reset: 0x00404040 Property: Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 SEL12 CAL12[6:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SEL8 CAL8[6:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SEL4 CAL4[6:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 0 0 0 0 0 0 Bit 23 – SEL12 Selection of Main RC Oscillator Calibration Bits for 12 MHz Value Description 0 Factory-determined value stored in Flash memory. 1 Value written by user in CAL12 field of this register. Bits 22:16 – CAL12[6:0] Main RC Oscillator Calibration Bits for 12 MHz Calibration bits applied to the RC Oscillator when SEL12 is set. Bit 15 – SEL8 Selection of Main RC Oscillator Calibration Bits for 8 MHz Value Description 0 Factory-determined value stored in Flash memory. 1 Value written by user in CAL8 field of this register. Bits 14:8 – CAL8[6:0] Main RC Oscillator Calibration Bits for 8 MHz Calibration bits applied to the RC Oscillator when SEL8 is set. Bit 7 – SEL4 Selection of Main RC Oscillator Calibration Bits for 4 MHz Value Description 0 Default value stored in Flash memory. 1 Value written by user in CAL4 field of this register. Bits 6:0 – CAL4[6:0] Main RC Oscillator Calibration Bits for 4 MHz Calibration bits applied to the RC Oscillator when SEL4 is set. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 283

31.20.28 PMC SleepWalking Enable Register 0

Name: PMC_SLPWK_ER0 Offset: 0x0114 Property: Write-only This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 Access Reset Bit 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 Access Reset Bit 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 Access Reset Bit 7 6 5 4 3 2 1 0 PID7 Access Reset Bits 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – PIDx Peripheral x SleepWalking Enable Not all PIDs can be configured with asynchronous partial wake-up. Only the following PID can be configured with asynchronous partial wake-up: UARTx and TWIHSx. The clock of the peripheral must be enabled before using its asynchronous partial wake-up (SleepWalking) function (its associated PIDx field in PMC Peripheral Clock Status Register 0 or PMC Peripheral Clock Status Register 1 is set to ‘1’). Value Description 0 No effect. 1 The asynchronous partial wakeup (SleepWalking) function of the corresponding peripheral is enabled. Note: “PIDx” refers to identifiers as defined in the section “Peripheral Identifiers” SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 284

31.20.29 PMC SleepWalking Enable Register 1

Name: PMC_SLPWK_ER1 Offset: 0x0134 Property: Write-only This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 PID62 PID60 PID59 PID58 PID57 PID56 Access Reset Bit 23 22 21 20 19 18 17 16 PID53 PID52 PID51 PID50 PID49 PID48 Access Reset Bit 15 14 13 12 11 10 9 8 PID47 PID46 PID45 PID44 PID43 PID42 PID41 PID40 Access Reset Bit 7 6 5 4 3 2 1 0 PID39 PID37 PID35 PID34 PID33 PID32 Access Reset Bits 0:3,5,7:28,30 – PID Peripheral Clock x Enable Value Description 0 No effect. 1 Enables the corresponding peripheral clock. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 285

31.20.30 PMC SleepWalking Disable Register 0

Name: PMC_SLPWK_DR0 Offset: 0x0118 Property: Write-only This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 Access Reset Bit 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 Access Reset Bit 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 Access Reset Bit 7 6 5 4 3 2 1 0 PID7 Access Reset Bits 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – PIDx Peripheral x SleepWalking Disable Not all PIDs can be configured with asynchronous partial wake-up. Only the following PIDs can be configured with asynchronous partial wake-up: UARTx and TWIHSx. Value Description 0 No effect. 1 The asynchronous partial wakeup (SleepWalking) function of the corresponding peripheral is disabled. Note: “PIDx” refers to identifiers as defined in the section “Peripheral Identifiers”. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 286

31.20.31 PMC SleepWalking Disable Register 1

Name: PMC_SLPWK_DR1 Offset: 0x0138 Property: Write-only This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 PID62 PID60 PID59 PID58 PID57 PID56 Access Reset Bit 23 22 21 20 19 18 17 16 PID53 PID52 PID51 PID50 PID49 PID48 Access Reset Bit 15 14 13 12 11 10 9 8 PID47 PID46 PID45 PID44 PID43 PID42 PID41 PID40 Access Reset Bit 7 6 5 4 3 2 1 0 PID39 PID37 PID35 PID34 PID33 PID32 Access Reset Bits 0:3,5,7:28,30 – PID Peripheral Clock x Disable Value Description 0 No effect. 1 Disables the corresponding peripheral clock. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 287

31.20.32 PMC SleepWalking Status Register 0

Name: PMC_SLPWK_SR0 Offset: 0x011C Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PID7 Access Reset 0 Bits 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – PIDx Peripheral x SleepWalking Status Not all PIDs can be configured with asynchronous partial wake-up. Only the following PIDs can be configured with asynchronous partial wake-up: UARTx and TWIHSx. Value Description

0 The asynchronous partial wake-up (SleepWalking) function of the peripheral is currently disabled or

the peripheral enabled for asynchronous partial wake-up (SleepWalking) cleared the PIDn bit upon detection of a wake-up condition. 1 The asynchronous partial wake-up (SleepWalking) function of the peripheral is currently enabled. Note: “PIDx” refers to identifiers as defined in the section “Peripheral Identifiers”. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 288

31.20.33 PMC SleepWalking Status Register 1

Name: PMC_SLPWK_SR1 Offset: 0x013C Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 PID62 PID60 PID59 PID58 PID57 PID56 Access Reset Bit 23 22 21 20 19 18 17 16 PID53 PID52 PID51 PID50 PID49 PID48 Access Reset Bit 15 14 13 12 11 10 9 8 PID47 PID46 PID45 PID44 PID43 PID42 PID41 PID40 Access Reset Bit 7 6 5 4 3 2 1 0 PID39 PID37 PID35 PID34 PID33 PID32 Access Reset Bits 0:3,5,7:28,30 – PID Peripheral Clock x Disable Value Description 0 No effect. 1 Disables the corresponding peripheral clock. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 289

31.20.34 PMC SleepWalking Activity Status Register 0

Name: PMC_SLPWK_ASR0 Offset: 0x0120 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PID7 Access Reset 0 Bits 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – PIDx Peripheral x Activity Status Only the following PIDs can be configured with asynchronous partial wake-up: UARTx and TWIHSx. All other PIDs are always read at ‘0’. Value Description 0 The peripheral x is not currently active. The asynchronous partial wake-up (SleepWalking) function can be activated. 1 The peripheral x is currently active. The asynchronous partial wake-up (SleepWalking) function must not be activated. Note: “PIDx” refers to identifiers as defined in the section “Peripheral Identifiers”. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 290

31.20.35 PLL Maximum Multiplier Value Register

Name: PMC_PMMR Offset: 0x0130 Reset: 0x000007FF Property: Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 PLLA_MMAX[10:8] Access R/W R/W R/W Reset 1 1 1 Bit 7 6 5 4 3 2 1 0 PLLA_MMAX[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bits 10:0 – PLLA_MMAX[10:0] PLLA Maximum Allowed Multiplier Value Defines the maximum value of multiplication factor that can be sent to PLLA. Any value of the MULA field (see PMC Clock Generator PLLA Register) above PLLA_MMAX is saturated to PLLA_MMAX. PLLA_MMAX write operation is cancelled in the following cases:

The value of MULA is currently saturated by PLLA_MMAX.
The user is trying to write a value of PLLA_MMAX that is smaller than the current value of MULA. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 291

31.20.36 PMC SleepWalking Activity Status Register 1

Name: PMC_SLPWK_ASR1 Offset: 0x0140 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 PID62 PID60 PID59 PID58 PID57 PID56 Access Reset Bit 23 22 21 20 19 18 17 16 PID53 PID52 PID51 PID50 PID49 PID48 Access Reset Bit 15 14 13 12 11 10 9 8 PID47 PID46 PID45 PID44 PID43 PID42 PID41 PID40 Access Reset Bit 7 6 5 4 3 2 1 0 PID39 PID37 PID35 PID34 PID33 PID32 Access Reset Bits 0:3,5,7:28,30 – PID Peripheral Clock x Disable Value Description 0 No effect. 1 Disables the corresponding peripheral clock. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 292

31.20.37 PMC SleepWalking Activity In Progress Register

Name: PMC_SLPWK_AIPR Offset: 0x0144 Reset: 0x400E0744 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 AIP Access R Reset 0 Bit 0 – AIP Activity In Progress Only the following PIDs can be configured with asynchronous partial wakeup: UARTx and TWIHSx. Value Description 0 There is no activity on peripherals. The asynchronous partial wakeup (SleepWalking) function can be activated on one or more peripherals. The device can enter Wait mode. 1 One or more peripherals are currently active. The device must not enter Wait mode if the asynchronous partial wakeup is enabled for one of the following PIDs: UARTx and TWIHSx. SAMV71Q21RT Power Management Controller (PMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 293

Parallel Input/Output Controller (PIO)

32.1 Description

The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This ensures effective optimization of the pins of the product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface. Each I/O line of the PIO Controller features the following:

An input change interrupt enabling level change detection on any I/O line
Additional Interrupt modes enabling rising edge, falling edge, low-level or high-level detection on any I/O line
A glitch filter providing rejection of glitches lower than one-half of peripheral clock cycle
A debouncing filter providing rejection of unwanted pulses from key or push button operations
Multi-drive capability similar to an open drain I/O line
Control of the I/O line pullup and pulldown
Input visibility and output control The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation. An 8-bit Parallel Capture mode is also available which can be used to interface a CMOS digital image sensor, an ADC, a DSP synchronous port in Synchronous mode, etc.

32.2 Embedded Characteristics

Up to 32 Programmable I/O Lines
Fully Programmable through Set/Clear Registers
Multiplexing of Four Peripheral Functions per I/O Line
For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O) – Input Change Interrupt – Programmable Glitch Filter – Programmable Debouncing Filter – Multi-drive Option Enables Driving in Open Drain – Programmable Pullup on Each I/O Line – Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time – Additional Interrupt Modes on a Programmable Event: Rising Edge, Falling Edge, Low-Level or High-Level – Lock of the Configuration by the Connected Peripheral
Synchronous Output, Provides Set and Clear of Several I/O Lines in a Single Write
Register Write Protection
Programmable Schmitt Trigger Inputs
Programmable I/O Drive
Parallel Capture Mode – Can Be Used to Interface a CMOS Digital Image Sensor, an ADC, etc. – One Clock, 8-bit Parallel Data and Two Data Enable on I/O Lines – Data Can be Sampled Every Other Time (For Chrominance Sampling Only) – Supports Connection of One DMA Controller Channel Which Offers Buffer Reception Without Processor Intervention SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 294

32.3 Block Diagram

Figure 32-1. Block Diagram Embedded Peripheral Embedded Peripheral PIO Interrupt PIO Controller Parallel Capture Mode PMC Up to x peripheral IOs Up to x peripheral IOs Peripheral Clock APB Data, Enable PIN x-1 PIN 1 PIN 0 Data, Enable DMA Data Events PIODCCLK PIODC[7:0] PIODCEN1 PIODCEN2 Interrupt Controller x is an integer representing the maximum number of IOs managed by one PIO controller. Table 32-1. Signal Description Signal Name Signal Description Signal Type PIODCCLK Parallel Capture Mode Clock Input PIODC[7:0] Parallel Capture Mode Data Input PIODCEN1 Parallel Capture Mode Data Enable 1 Input PIODCEN2 Parallel Capture Mode Data Enable 2 Input

32.4 Product Dependencies

32.4.1 Pin Multiplexing

Each pin is configurable, depending on the product, as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware defined and thus product-dependent, SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 295

the hardware designer and programmer must carefully determine the configuration of the PIO Controllers required by their application. When an I/O line is general-purpose only, i.e., not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product.

32.4.2 External Interrupt Lines

When the WKUPx input pins must be used as external interrupt lines, the PIO Controller must be configured to disable the peripheral control on these IOs, and the corresponding IO lines must be set to Input mode.

32.4.3 Power Management

The Power Management Controller controls the peripheral clock in order to save power. Writing any of the registers of the user interface does not require the peripheral clock to be enabled. This means that the configuration of the I/O lines does not require the peripheral clock to be enabled. However, when the clock is disabled, not all of the features of the PIO Controller are available, including glitch filtering. Note that the input change interrupt, the interrupt modes on a programmable event and the read of the pin level require the clock to be validated. After a hardware reset, the peripheral clock is disabled by default. The user must configure the Power Management Controller before any access to the input line information.

32.4.4 Interrupt Sources

For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources. Refer to the PIO Controller peripheral identifier in the Peripheral Identifiers table to identify the interrupt sources dedicated to the PIO Controllers. Using the PIO Controller requires the Interrupt Controller to be programmed first. The PIO Controller interrupt can be generated only if the peripheral clock is enabled. Related Links

32.5 Functional Description

The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in the following figure. In this description each signal shown represents one of up to 32 possible indexes. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 296

Figure 32-2. I/O Line Control Logic D Q D Q DFF Programmable Glitch or Debouncing Filter PIO_PDSR[0] PIO_ISR[0] PIO_IDR[0] PIO_IMR[0] PIO_IER[0] PIO Interrupt (Up to 32 possible inputs) PIO_ISR[31] PIO_IDR[31] PIO_IMR[31] PIO_IER[31] Pad PIO_PUDR[0] PIO_PUSR[0] PIO_PUER[0] PIO_MDDR[0] PIO_MDSR[0] PIO_MDER[0] PIO_CODR[0] PIO_ODSR[0] PIO_SODR[0] PIO_PDR[0] PIO_PSR[0] PIO_PER[0] PIO_ABCDSR1[0] PIO_ODR[0] PIO_OSR[0] PIO_OER[0] Peripheral Clock Resynchronization Stage Peripheral A Input Peripheral D Output Enable Peripheral A Output Enable EVENT DETECTORDFF PIO_IFDR[0] PIO_IFSR[0] PIO_IFER[0] Peripheral Clock Clock Divider PIO_IFSCSR[0] PIO_IFSCER[0] PIO_IFSCDR[0] PIO_SCDR Slow Clock Peripheral B Output Enable Peripheral C Output Enable Peripheral D Output Peripheral A Output Peripheral B Output Peripheral C Output PIO_ABCDSR2[0] Peripheral B Input Peripheral C Input Peripheral D Input PIO_PPDDR[0] PIO_PPDSR[0] PIO_PPDER[0] VDD GND Integrated Pull-Down Resistor Integrated Pull-Up Resistor div_slck

32.5.1 Pullup and Pulldown Resistor Control

Each I/O line is designed with an embedded pullup resistor and an embedded pulldown resistor. The pullup resistor can be enabled or disabled by writing to the Pull-Up Enable Register (PIO_PUER) or Pull-Up Disable Register (PIO_PUDR), respectively. Writing to these registers results in setting or clearing the corresponding bit in the Pull-Up Status Register (PIO_PUSR). Reading a one in PIO_PUSR means the pullup is disabled and reading a zero means the pullup is enabled. The pulldown resistor can be enabled or disabled by writing the Pull-Down Enable Register (PIO_PPDER) or the Pull-Down Disable Register (PIO_PPDDR), respectively. Writing in these registers results in setting or clearing the corresponding bit in the Pull-Down Status Register (PIO_PPDSR). Reading a one in PIO_PPDSR means the pullup is disabled and reading a zero means the pulldown is enabled. Enabling the pulldown resistor while the pullup resistor is still enabled is not possible. In this case, the write of PIO_PPDER for the relevant I/O line is discarded. Likewise, enabling the pullup resistor while the pulldown resistor is still enabled is not possible. In this case, the write of PIO_PUER for the relevant I/O line is discarded. Control of the pullup resistor is possible regardless of the configuration of the I/O line. After reset, depending on the I/O, pullup or pulldown can be set. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 297

32.5.2 I/O Line or Peripheral Function Selection

When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the Enable Register (PIO_PER) and the Disable Register (PIO_PDR). The Status Register (PIO_PSR) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of zero indicates that the pin is controlled by the corresponding on-chip peripheral selected in the Peripheral ABCD Select registers (PIO_ABCDSR1 and PIO_ABCDSR2). A value of one indicates the pin is controlled by the PIO Controller. If a pin is used as a general-purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns a one for the corresponding bit. After reset, the I/O lines are controlled by the PIO Controller, i.e., PIO_PSR resets at one. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset, or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level and depends on the multiplexing of the device.

32.5.3 Peripheral A or B or C or D Selection

Enter a short description of your topic here (optional). The PIO Controller provides multiplexing of up to four peripheral functions on a single pin. The selection is performed by writing PIO_ABCDSR1 and PIO_ABCDSR2. For each pin:

The corresponding bit at level zero in PIO_ABCDSR1 and the corresponding bit at level zero in PIO_ABCDSR2 means peripheral A is selected.
The corresponding bit at level one in PIO_ABCDSR1 and the corresponding bit at level zero in PIO_ABCDSR2 means peripheral B is selected.
The corresponding bit at level zero in PIO_ABCDSR1 and the corresponding bit at level one in PIO_ABCDSR2 means peripheral C is selected.
The corresponding bit at level one in PIO_ABCDSR1 and the corresponding bit at level one in PIO_ABCDSR2 means peripheral D is selected. Note that multiplexing of peripheral lines A, B, C and D only affects the output line. The peripheral input lines are always connected to the pin input (see I/O Line Control Logic ). Writing in PIO_ABCDSR1 and PIO_ABCDSR2 manages the multiplexing regardless of the configuration of the pin. However, assignment of a pin to a peripheral function requires a write in PIO_ABCDSR1 and PIO_ABCDSR2 in addition to a write in PIO_PDR. After reset, PIO_ABCDSR1 and PIO_ABCDSR2 are zero, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O Line mode. If the software selects a peripheral A, B, C or D which does not exist for a pin, no alternate functions are enabled for this pin and the selection is taken into account. The PIO Controller does not carry out checks to prevent selection of a peripheral which does not exist.

32.5.4 Output Control

When the I/O line is assigned to a peripheral function, i.e., the corresponding bit in PIO_PSR is at zero, the drive of the I/O line is controlled by the peripheral. Peripheral A or B or C or D depending on the value in PIO_ABCDSR1 and PIO_ABCDSR2 determines whether the pin is driven or not. When the I/O line is controlled by the PIO Controller, the pin can be configured to be driven. This is done by writing the Output Enable Register (PIO_OER) and Output Disable Register (PIO_ODR). The results of these write operations are detected in the Output Status Register (PIO_OSR). When a bit in this register is at zero, the corresponding I/O line is used as an input only. When the bit is at one, the corresponding I/O line is driven by the PIO Controller. The level driven on an I/O line can be determined by writing in the Set Output Data Register (PIO_SODR) and the Clear Output Data Register (PIO_CODR). These write operations, respectively, set and clear the Output Data Status Register (PIO_ODSR), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO Controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 298

Similarly, writing in PIO_SODR and PIO_CODR affects PIO_ODSR. This is important as it defines the first level driven on the I/O line.

32.5.5 Synchronous Data Output

Clearing one or more PIO line(s) and setting another one or more PIO line(s) synchronously cannot be done by using PIO_SODR and PIO_CODR. It requires two successive write operations into two different registers. To overcome this, the PIO Controller offers a direct control of PIO outputs by single write access to PIO_ODSR. Only bits unmasked by the Output Write Status Register (PIO_OWSR) are written. The mask bits in PIO_OWSR are set by writing to the Output Write Enable Register (PIO_OWER) and cleared by writing to the Output Write Disable Register (PIO_OWDR). After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0.

32.5.6 Multi-Drive Control (Open Drain)

Each I/O can be independently programmed in open drain by using the multi-drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pullup resistor (or enabling of the internal one) is generally required to guarantee a high level on the line. The multi-drive feature is controlled by the Multi-driver Enable Register (PIO_MDER) and the Multi-driver Disable Register (PIO_MDDR). The multi-drive can be selected whether the I/O line is controlled by the PIO Controller or assigned to a peripheral function. The Multi-driver Status Register (PIO_MDSR) indicates the pins that are configured to support external drivers. After reset, the multi-drive feature is disabled on all pins, i.e., PIO_MDSR resets at value 0x0.

32.5.7 Output Line Timings

The following figure shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. The Output Line Timings figure also shows when the feedback in the Pin Data Status Register (PIO_PDSR) is available. Figure 32-3. Output Line Timings 2 cycles APB Access 2 cycles APB Access Peripheral clock Write PIO_SODR Write PIO_ODSR at 1 PIO_ODSR PIO_PDSR Write PIO_CODR Write PIO_ODSR at 0

32.5.8 Inputs

The level on each I/O line can be read through PIO_PDSR. This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input, or driven by the PIO Controller, or driven by a peripheral. Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.

32.5.9 Input Glitch and Debouncing Filters

Optional input glitch and debouncing filters are independently programmable on each I/O line. The glitch filter can filter a glitch with a duration of less than 1/2 peripheral clock and the debouncing filter can filter a pulse of less than 1/2 period of a programmable divided slow clock. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 299

32.5.10 Input Edge/Level Interrupt

The PIO Controller can be programmed to generate an interrupt when it detects an edge or a level on an I/O line. The Input Edge/Level interrupt is controlled by writing the Interrupt Enable Register (PIO_IER) and the Interrupt Disable Register (PIO_IDR), which enable and disable the input change interrupt respectively by setting and clearing the corresponding bit in the Interrupt Mask Register (PIO_IMR). As input change detection is possible only by comparing two successive samplings of the input of the I/O line, the peripheral clock must be enabled. The Input Change interrupt is available regardless of the configuration of the I/O line, i.e., configured as an input only, controlled by the PIO Controller or assigned to a peripheral function. By default, the interrupt can be generated at any time an edge is detected on the input. Some additional interrupt modes can be enabled/disabled by writing in the Additional Interrupt Modes Enable Register (PIO_AIMER) and Additional Interrupt Modes Disable Register (PIO_AIMDR). The current state of this selection can be read through the Additional Interrupt Modes Mask Register (PIO_AIMMR). These additional modes are:

Rising edge detection
Falling edge detection
Low-level detection
High-level detection In order to select an additional interrupt mode:
The type of event detection (edge or level) must be selected by writing in the Edge Select Register (PIO_ESR) and Level Select Register (PIO_LSR) which select, respectively, the edge and level detection. The current status of this selection is accessible through the Edge/Level Status Register (PIO_ELSR).
The polarity of the event detection (rising/falling edge or high/low-level) must be selected by writing in the Falling Edge/Low-Level Select Register (PIO_FELLSR) and Rising Edge/High-Level Select Register (PIO_REHLSR) which allow to select falling or rising edge (if edge is selected in PIO_ELSR) edge or high- or low-level detection (if level is selected in PIO_ELSR). The current status of this selection is accessible through the Fall/Rise - Low/High Status Register (PIO_FRLHSR). When an input edge or level is detected on an I/O line, the corresponding bit in the Interrupt Status Register (PIO_ISR) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted.The interrupt signals of the 32 channels are ORed-wired together to generate a single interrupt signal to the interrupt controller. When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled. When an Interrupt is enabled on a “level”, the interrupt is generated as long as the interrupt source is not cleared, even if some read accesses in PIO_ISR are performed. Figure 32-6. Event Detector on Input Lines (Figure Represents Line 0) Event Detector Edge Detector Falling Edge Detector Rising Edge Detector PIO_FELLSR[0] PIO_FRLHSR[0] PIO_REHLSR[0] Low Level Detector High Level Detector PIO_ESR[0] PIO_ELSR[0] PIO_LSR[0] PIO_AIMDR[0] PIO_AIMMR[0] PIO_AIMER[0] Event detection on line 0 Resynchronized input on line 0 Example of interrupt generation on following lines: SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 301

Rising edge on PIO line 0
Falling edge on PIO line 1
Rising edge on PIO line 2
Low-level on PIO line 3
High-level on PIO line 4
High-level on PIO line 5
Falling edge on PIO line 6
Rising edge on PIO line 7
Any edge on the other lines The following table provides the required configuration for this example. Table 32-2. Configuration for Example Interrupt Generation Configuration Description Interrupt Mode All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER. Then the additional Interrupt mode is enabled for lines 0 to 7 by writing 32’h0000_00FF in PIO_AIMER. Edge or Level Detection Lines 3, 4 and 5 are configured in level detection by writing 32’h0000_0038 in PIO_LSR. The other lines are configured in edge detection by default, if they have not been previously configured. Otherwise, lines 0, 1, 2, 6 and 7 must be configured in edge detection by writing 32’h0000_00C7 in PIO_ESR. Falling/Rising Edge or Low/High-Level Detection Lines 0, 2, 4, 5 and 7 are configured in rising edge or high-level detection by writing 32’h0000_00B5 in PIO_REHLSR. The other lines are configured in falling edge or low-level detection by default if they have not been previously configured. Otherwise, lines 1, 3 and 6 must be configured in falling edge/low-level detection by writing 32’h0000_004A in PIO_FELLSR. Figure 32-7. Input Change Interrupt Timings When No Additional Interrupt Modes Peripheral clock Pin Level Read PIO_ISR APB Access PIO_ISR APB Access

32.5.11 I/O Lines Lock

When an I/O line is controlled by a peripheral (particularly the Pulse Width Modulation Controller PWM), it can become locked by the action of this peripheral via an input of the PIO Controller. When an I/O line is locked, the write of the corresponding bit in PIO_PER, PIO_PDR, PIO_MDER, PIO_MDDR, PIO_PUDR, PIO_PUER, PIO_ABCDSR1 and PIO_ABCDSR2 is discarded in order to lock its configuration. The user can know at any time which I/O line is locked by reading the PIO Lock Status Register (PIO_LOCKSR). Once an I/O line is locked, the only way to unlock it is to apply a hardware reset to the PIO Controller.

32.5.12 Programmable I/O Drive

It is possible to configure the I/O drive for pads PA0-31, PB0-9, PB12-13, PC0-31, PD0-31 and PE0-5. Refer to the section “Electrical Characteristics”. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 302

32.5.13 Programmable Schmitt Trigger

It is possible to configure each input for the Schmitt trigger. By default the Schmitt trigger is active. Disabling the Schmitt trigger is requested when using the QTouch® Library.

32.5.14 Parallel Capture Mode

32.5.14.1 Overview

The PIO Controller integrates an interface able to read data from a CMOS digital image sensor, a high-speed parallel ADC, a DSP synchronous port in Synchronous mode, etc. For better understanding and to ease reading, the following description uses an example with a CMOS digital image sensor.

32.5.14.2 Functional Description

The CMOS digital image sensor provides a sensor clock, an 8-bit data synchronous with the sensor clock and two data enables which are also synchronous with the sensor clock. Figure 32-8. PIO Controller Connection with CMOS Digital Image Sensor PIO Controller Parallel Capture Mode CMOS Digital Image Sensor DMA Data Events PIODCCLK PIODC[7:0] PIODCEN1 PIODCEN2 PCLK DATA[7:0] VSYNC HSYNC Figure 32-9. PIO Controller Parallel Capture Mode CMOS Digital Image Sensor PDC Data Status PIODCCLK PIODC[7:0] PIODCEN1 PIODCEN2 PCLK DATA[7:0] VSYNC HSYNC Events As soon as the Parallel Capture mode is enabled by writing a one to the PCEN bit in PIO_PCMR, the I/O lines connected to the sensor clock (PIODCCLK), the sensor data (PIODC[7:0]) and the sensor data enable signals (PIODCEN1 and PIODCEN2) are configured automatically as inputs. To know which I/O lines are associated with the sensor clock, the sensor data and the sensor data enable signals, refer to the I/O multiplexing table(s) in the section “Package and Pinout”. Once enabled, the Parallel Capture mode samples the data at rising edge of the sensor clock and resynchronizes it with the peripheral clock domain. The size of the data which can be read in PIO_PCRHR can be programmed using the DSIZE field in PIO_PCMR. If this data size is larger than 8 bits, then the Parallel Capture mode samples several sensor data to form a concatenated data of size defined by DSIZE. Then this data is stored in PIO_PCRHR and the flag DRDY is set to one in PIO_PCISR. The Parallel Capture mode can be associated with a reception channel of the DMA Controller. This performs reception transfer from Parallel Capture mode to a memory buffer without any intervention from the CPU. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 303

Figure 32-12. Parallel Capture Mode Waveforms (DSIZE = 2, ALWYS = 0, HALFS = 1, FRSTS = 0) 0x23 0x34 0x45 0x12 0x56 0x67 0x78 0x89 0x6745_2301 PIODCLK PIODC[7:0] PIODCEN1 PIODCEN2 DRDY (PIO_PCISR) RDATA (PIO_PCRHR) 0x01 Read of PIO_PCISR MCK Figure 32-13. Parallel Capture Mode Waveforms (DSIZE = 2, ALWYS = 0, HALFS = 1, FRSTS = 1) 0x23 0x34 0x45 0x12 0x56 0x67 0x78 0x89 0x7856_3412 0x01 PIODCLK PIODC[7:0] PIODCEN1 PIODCEN2 DRDY (PIO_PCISR) RDATA (PIO_PCRHR) Read of PIO_PCISR MCK

32.5.14.3 Restrictions

Configuration fields DSIZE, ALWYS, HALFS and FRSTS in PIO_PCMR can be changed ONLY if the Parallel Capture mode is disabled at this time (PCEN = 0 in PIO_PCMR).
The frequency of peripheral clock must be strictly superior to two times the frequency of the clock of the device which generates the parallel data.

32.5.14.4 Programming Sequence

32.5.14.4.1 Without DMA

Write PIO_PCIDR and PIO_PCIER in order to configure the Parallel Capture mode interrupt mask. 2. Write PIO_PCMR to set the fields DSIZE, ALWYS, HALFS and FRSTS in order to configure the Parallel Capture mode WITHOUT enabling the Parallel Capture mode. 3. Write PIO_PCMR to set the PCEN bit to one in order to enable the Parallel Capture mode WITHOUT changing the previous configuration. 4. Wait for a data ready by polling the DRDY flag in PIO_PCISR or by waiting for the corresponding interrupt. 5. Check OVRE flag in PIO_PCISR. 6. Read the data in PIO_PCRHR. 7. If new data are expected, go to step 4. 8. Write PIO_PCMR to set the PCEN bit to zero in order to disable the Parallel Capture mode WITHOUT changing the previous configuration. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 305

32.5.14.4.2 With DMA

Write PIO_PCIDR and PIO_PCIER in order to configure the Parallel Capture mode interrupt mask. 2. Configure DMA transfer in DMA registers. 3. Write PIO_PCMR to set the fields DSIZE, ALWYS, HALFS and FRSTS in order to configure the Parallel Capture mode WITHOUT enabling the Parallel Capture mode. 4. Write PIO_PCMR to set PCEN bit to one in order to enable the Parallel Capture mode WITHOUT changing the previous configuration. 5. Wait for the DMA status flag to indicate that the buffer transfer is complete. 6. Check OVRE flag in PIO_PCISR. 7. If a new buffer transfer is expected, go to step 5. 8. Write PIO_PCMR to set the PCEN bit to zero in order to disable the Parallel Capture mode WITHOUT changing the previous configuration.

32.5.15 I/O Lines Programming Example

The programming example shown in the following table is used to obtain the following configuration:

4-bit output port on I/O lines 0 to 3 (should be written in a single write operation), open-drain, with pullup resistor
Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pullup resistor, no pulldown resistor
Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pullup resistors, glitch filters and input change interrupts
Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pullup resistor, no glitch filter
I/O lines 16 to 19 assigned to peripheral A functions with pullup resistor
I/O lines 20 to 23 assigned to peripheral B functions with pulldown resistor
I/O lines 24 to 27 assigned to peripheral C with input change interrupt, no pullup resistor and no pulldown resistor
I/O lines 28 to 31 assigned to peripheral D, no pullup resistor and no pulldown resistor Table 32-3. Programming Example Register Value to be Written PIO_PER 0x0000_FFFF PIO_PDR 0xFFFF_0000 PIO_OER 0x0000_00FF PIO_ODR 0xFFFF_FF00 PIO_IFER 0x0000_0F00 PIO_IFDR 0xFFFF_F0FF PIO_SODR 0x0000_0000 PIO_CODR 0x0FFF_FFFF PIO_IER 0x0F00_0F00 PIO_IDR 0xF0FF_F0FF PIO_MDER 0x0000_000F PIO_MDDR 0xFFFF_FFF0 PIO_PUDR 0xFFF0_00F0 PIO_PUER 0x000F_FF0F PIO_PPDDR 0xFF0F_FFFF SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 306

Register Value to be Written PIO_PPDER 0x00F0_0000 PIO_ABCDSR1 0xF0F0_0000 PIO_ABCDSR2 0xFF00_0000 PIO_OWER 0x0000_000F PIO_OWDR 0x0FFF_FFF0

32.5.16 Register Write Protection

To prevent any single software error from corrupting PIO behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the PIO Write Protection Mode Register (PIO_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the PIO Write Protection Status Register (PIO_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS bit is automatically cleared after reading the PIO_WPSR. The following registers can be write-protected:

PIO Enable Register
PIO Disable Register
PIO Output Enable Register
PIO Output Disable Register
PIO Input Filter Enable Register
PIO Input Filter Disable Register
PIO Multi-driver Enable Register
PIO Multi-driver Disable Register
PIO Pull-Up Disable Register
PIO Pull-Up Enable Register
PIO Peripheral ABCD Select Register 1
PIO Peripheral ABCD Select Register 2
PIO Output Write Enable Register
PIO Output Write Disable Register
PIO Pad Pull-Down Disable Register
PIO Pad Pull-Down Enable Register
PIO Parallel Capture Mode Register SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 307

32.6 Register Summary

Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns one systematically. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 PIO_PER 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x04 PIO_PDR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x08 PIO_PSR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x0C ... 0x0F Reserved 0x10 PIO_OER 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x14 PIO_ODR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x18 PIO_OSR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x1C ... 0x1F Reserved 0x20 PIO_IFER 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x24 PIO_IFDR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x28 PIO_IFSR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x2C ... 0x2F Reserved 0x30 PIO_SODR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 308

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x34 PIO_CODR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x38 PIO_ODSR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x3C PIO_PDSR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x40 PIO_IER 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x44 PIO_IDR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x48 PIO_IMR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x4C PIO_ISR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x50 PIO_MDER 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x54 PIO_MDDR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x58 PIO_MDSR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x5C ... 0x5F Reserved 0x60 PIO_PUDR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x64 PIO_PUER 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x68 PIO_PUSR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x6C ... 0x6F Reserved SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 309

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x70 PIO_ABCDSR1 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x74 PIO_ABCDSR2 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x78 ... 0x7F Reserved 0x80 PIO_IFSCDR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x84 PIO_IFSCER 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x88 PIO_IFSCSR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x8C PIO_SCDR 7:0 DIV[7:0] 15:8 DIV[13:8] 23:16 31:24 0x90 PIO_PPDDR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x94 PIO_PPDER 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x98 PIO_PPDSR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0x9C ... 0x9F Reserved 0xA0 PIO_OWER 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0xA4 PIO_OWDR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0xA8 PIO_OWSR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0xAC ... 0xAF Reserved SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 310

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0xB0 PIO_AIMER 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0xB4 PIO_AIMDR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0xB8 PIO_AIMMR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0xBC ... 0xBF Reserved 0xC0 PIO_ESR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0xC4 PIO_LSR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0xC8 PIO_ELSR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0xCC ... 0xCF Reserved 0xD0 PIO_FELLSR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0xD4 PIO_REHLSR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0xD8 PIO_FRLHSR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0xDC ... 0xDF Reserved 0xE0 PIO_LOCKSR 7:0 P7 P6 P5 P4 P3 P2 P1 P0 15:8 P15 P14 P13 P12 P11 P10 P9 P8 23:16 P23 P22 P21 P20 P19 P18 P17 P16 31:24 P31 P30 P29 P28 P27 P26 P25 P24 0xE4 PIO_WPMR 7:0 WPEN 15:8 WPKEY[7:0] 23:16 WPKEY[15:8] 31:24 WPKEY[23:16] 0xE8 PIO_WPSR 7:0 WPVS 15:8 WPVSRC[7:0] 23:16 WPVSRC[15:8] 31:24 SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 311

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0xEC ... 0xFF Reserved 0x0100 PIO_SCHMITT 7:0 SCHMITT7 SCHMITT6 SCHMITT5 SCHMITT4 SCHMITT3 SCHMITT2 SCHMITT1 SCHMITT0 15:8 SCHMITT15 SCHMITT14 SCHMITT13 SCHMITT12 SCHMITT11 SCHMITT10 SCHMITT9 SCHMITT8 23:16 SCHMITT23 SCHMITT22 SCHMITT21 SCHMITT20 SCHMITT19 SCHMITT18 SCHMITT17 SCHMITT16 31:24 SCHMITT31 SCHMITT30 SCHMITT29 SCHMITT28 SCHMITT27 SCHMITT26 SCHMITT25 SCHMITT24 0x0104 ... 0x0117 Reserved 0x0118 PIO_DRIVER1 7:0 LINE7 LINE6 LINE5 LINE4 LINE3 LINE2 LINE1 LINE0 15:8 LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 23:16 LINE23 LINE22 LINE21 LINE20 LINE19 LINE18 LINE17 LINE16 31:24 LINE31 LINE30 LINE29 LINE28 LINE27 LINE26 LINE25 LINE24 0x011C ... 0x014F Reserved 0x0150 PIO_PCMR 7:0 DSIZE[1:0] PCEN 15:8 FRSTS HALFS ALWYS 23:16 31:24 0x0154 PIO_PCIER 7:0 RXBUFF ENDRX OVRE DRDY 15:8 23:16 31:24 0x0158 PIO_PCIDR 7:0 RXBUFF ENDRX OVRE DRDY 15:8 23:16 31:24 0x015C PIO_PCIMR 7:0 RXBUFF ENDRX OVRE DRDY 15:8 23:16 31:24 0x0160 PIO_PCISR 7:0 OVRE DRDY 15:8 23:16 31:24 0x0164 PIO_PCRHR 7:0 RDATA[7:0] 15:8 RDATA[15:8] 23:16 RDATA[23:16] 31:24 RDATA[31:24] SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 312

32.6.1 PIO Enable Register

Name: PIO_PER Offset: 0x0000 Property: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Enable Value Description 0 No effect. 1 Enables the PIO to control the corresponding pin (disables peripheral control of the pin). SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 313

32.6.2 PIO Disable Register

Name: PIO_PDR Offset: 0x0004 Property: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Disable Value Description 0 No effect. 1 Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin). SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 314

32.6.3 PIO Status Register

Name: PIO_PSR Offset: 0x0008 Property: Read-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Status Value Description 0 PIO is inactive on the corresponding I/O line (peripheral is active). 1 PIO is active on the corresponding I/O line (peripheral is inactive). SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 315

32.6.4 PIO Output Enable Register

Name: PIO_OER Offset: 0x0010 Property: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Output Enable Value Description 0 No effect. 1 Enables the output on the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 316

32.6.5 PIO Output Disable Register

Name: PIO_ODR Offset: 0x0014 Property: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Output Disable Value Description 0 No effect. 1 Disables the output on the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 317

32.6.6 PIO Output Status Register

Name: PIO_OSR Offset: 0x0018 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset 0 0 0 0 0 0 0 0 PIO Output Status Value Description 0 The I/O line is a pure input. 1 The I/O line is enabled in output. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 318

32.6.7 PIO Input Filter Enable Register

Name: PIO_IFER Offset: 0x0020 Property: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Input Filter Enable Value Description 0 No effect. 1 Enables the input glitch filter on the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 319

32.6.8 PIO Input Filter Disable Register

Name: PIO_IFDR Offset: 0x0024 Property: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Input Filter Disable Value Description 0 No effect. 1 Disables the input glitch filter on the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 320

32.6.9 PIO Input Filter Status Register

Name: PIO_IFSR Offset: 0x0028 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset 0 0 0 0 0 0 0 0 PIO Input Filter Status Value Description 0 The input glitch filter is disabled on the I/O line. 1 The input glitch filter is enabled on the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 321

32.6.10 PIO Set Output Data Register

Name: PIO_SODR Offset: 0x0030 Property: Write-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Set Output Data Value Description 0 No effect. 1 Sets the data to be driven on the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 322

32.6.11 PIO Clear Output Data Register

Name: PIO_CODR Offset: 0x0034 Property: Write-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Clear Output Data Value Description 0 No effect. 1 Clears the data to be driven on the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 323

32.6.12 PIO Output Data Status Register

Name: PIO_ODSR Offset: 0x0038 Property: Read-only or Read/Write Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Output Data Status Value Description 0 The data to be driven on the I/O line is 0. 1 The data to be driven on the I/O line is 1. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 324

32.6.13 PIO Pin Data Status Register

Name: PIO_PDSR Offset: 0x003C Property: Read-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Output Data Status Value Description 0 The I/O line is at level 0. 1 The I/O line is at level 1. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 325

32.6.14 PIO Interrupt Enable Register

Name: PIO_IER Offset: 0x0040 Property: Write-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Input Change Interrupt Enable Value Description 0 No effect. 1 Enables the input change interrupt on the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 326

32.6.15 PIO Interrupt Disable Register

Name: PIO_IDR Offset: 0x0044 Property: Write-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Input Change Interrupt Disable Value Description 0 No effect. 1 Disables the input change interrupt on the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 327

32.6.16 PIO Interrupt Mask Register

Name: PIO_IMR Offset: 0x0048 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset 0 0 0 0 0 0 0 0 PIO Input Change Interrupt Mask Value Description 0 Input change interrupt is disabled on the I/O line. 1 Input change interrupt is enabled on the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 328

32.6.17 PIO Interrupt Status Register

Name: PIO_ISR Offset: 0x004C Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset 0 0 0 0 0 0 0 0 PIO Input Change Interrupt Status Value Description 0 No input change has been detected on the I/O line since PIO_ISR was last read or since reset.

1 At least one input change has been detected on the I/O line since PIO_ISR was last read or since

32.6.18 PIO Multi-driver Enable Register

Name: PIO_MDER Offset: 0x0050 Property: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Multi-drive Enable Value Description 0 No effect. 1 Enables multi-drive on the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 330

32.6.19 PIO Multi-driver Disable Register

Name: PIO_MDDR Offset: 0x0054 Property: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Multi-drive Disable Value Description 0 No effect. 1 Disables multi-drive on the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 331

32.6.20 PIO Multi-driver Status Register

Name: PIO_MDSR Offset: 0x0058 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset 0 0 0 0 0 0 0 0 PIO Multi-drive Status Value Description 0 The multi-drive is disabled on the I/O line. The pin is driven at high- and low-level. 1 The multi-drive is enabled on the I/O line. The pin is driven at low-level only. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 332

32.6.21 PIO Pull-Up Disable Register

Name: PIO_PUDR Offset: 0x0060 Property: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Pull-Up Disable Value Description 0 No effect. 1 Disables the pullup resistor on the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 333

32.6.22 PIO Pull-Up Enable Register

Name: PIO_PUER Offset: 0x0064 Property: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Pull-Up Enable Value Description 0 No effect. 1 Enables the pullup resistor on the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 334

32.6.23 PIO Pull-Up Status Register

Name: PIO_PUSR Offset: 0x0068 Property: Read-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Pull-Up Status Value Description 0 Pullup resistor is enabled on the I/O line. 1 Pullup resistor is disabled on the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 335

32.6.24 PIO Peripheral ABCD Select Register 1

Name: PIO_ABCDSR1 Offset: 0x0070 Reset: 0x00000000 Property: Read/Write This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset 0 0 0 0 0 0 0 0 PIO Peripheral Select If the same bit is set to '0' in PIO_ABCDSR2: 0: Assigns the I/O line to the Peripheral A function. 1: Assigns the I/O line to the Peripheral B function. If the same bit is set to '1' in PIO_ABCDSR2: 0: Assigns the I/O line to the Peripheral C function. 1: Assigns the I/O line to the Peripheral D function. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 336

32.6.25 PIO Peripheral ABCD Select Register 2

Name: PIO_ABCDSR2 Offset: 0x0074 Reset: 0x00000000 Property: Read/Write This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset 0 0 0 0 0 0 0 0 PIO Peripheral Select If the same bit is set to '0' in PIO_ABCDSR1: 0: Assigns the I/O line to the Peripheral A function. 1: Assigns the I/O line to the Peripheral C function. If the same bit is set to '1' in PIO_ABCDSR1: 0: Assigns the I/O line to the Peripheral B function. 1: Assigns the I/O line to the Peripheral D function. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 337

32.6.26 PIO Input Filter Slow Clock Disable Register

Name: PIO_IFSCDR Offset: 0x0080 Property: Write-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Peripheral Clock Glitch Filtering Select Value Description 0 No effect. 1 The glitch filter is able to filter glitches with a duration < tperipheral clock/2. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 338

32.6.27 PIO Input Filter Slow Clock Enable Register

Name: PIO_IFSCER Offset: 0x0084 Property: Write-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Slow Clock Debouncing Filtering Select Value Description 0 No effect. 1 The debouncing filter is able to filter pulses with a duration < tdiv_slck/2. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 339

32.6.28 PIO Input Filter Slow Clock Status Register

Name: PIO_IFSCSR Offset: 0x0088 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset 0 0 0 0 0 0 0 0 PIO Glitch or Debouncing Filter Selection Status Value Description 0 The glitch filter is able to filter glitches with a duration < tperipheral clock/2. 1 The debouncing filter is able to filter pulses with a duration < tdiv_slck/2. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 340

32.6.29 PIO Slow Clock Divider Debouncing Register

Name: PIO_SCDR Offset: 0x008C Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 DIV[13:8] Access Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIV[7:0] Access Reset 0 0 0 0 0 0 0 0 Bits 13:0 – DIV[13:0] Slow Clock Divider Selection for Debouncing tdiv_slck = ((DIV + 1) × 2) × tslck SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 341

32.6.30 PIO Pad Pull-Down Disable Register

Name: PIO_PPDDR Offset: 0x0090 Property: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Pull-Down Disable Value Description 0 No effect. 1 Disables the pull-down resistor on the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 342

32.6.31 PIO Pad Pull-Down Enable Register

Name: PIO_PPDER Offset: 0x0094 Property: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Pull-Down Enable Value Description 0 No effect. 1 Enables the pull-down resistor on the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 343

32.6.32 PIO Pad Pull-Down Status Register

Name: PIO_PPDSR Offset: 0x0098 Property: Read-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Pull-Down Status Value Description 0 Pull-down resistor is enabled on the I/O line. 1 Pull-down resistor is disabled on the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 344

32.6.33 PIO Output Write Enable Register

Name: PIO_OWER Offset: 0x00A0 Property: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Output Write Enable Value Description 0 No effect. 1 Enables writing PIO_ODSR for the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 345

32.6.34 PIO Output Write Disable Register

Name: PIO_OWDR Offset: 0x00A4 Property: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Output Write Disable Value Description 0 No effect. 1 Disables writing PIO_ODSR for the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 346

32.6.35 PIO Output Write Status Register

Name: PIO_OWSR Offset: 0x00A8 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset 0 0 0 0 0 0 0 0 PIO Output Write Status Value Description 0 Writing PIO_ODSR does not affect the I/O line. 1 Writing PIO_ODSR affects the I/O line. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 347

32.6.36 PIO Additional Interrupt Modes Enable Register

Name: PIO_AIMER Offset: 0x00B0 Property: Write-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Additional Interrupt Modes Enable Value Description 0 No effect. 1 The interrupt source is the event described in PIO_ELSR and PIO_FRLHSR. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 348

32.6.37 PIO Additional Interrupt Modes Disable Register

Name: PIO_AIMDR Offset: 0x00B4 Property: Write-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Additional Interrupt Modes Disable Value Description 0 No effect. 1 The Interrupt mode is set to the default Interrupt mode (Both-edge Detection). SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 349

32.6.38 PIO Additional Interrupt Modes Mask Register

Name: PIO_AIMMR Offset: 0x00B8 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset 0 0 0 0 0 0 0 0 PIO I/O Line Index Selects the I/O event type triggering an interrupt. Value Description 0 The interrupt source is a both-edge detection event. 1 The interrupt source is described by the registers PIO_ELSR and PIO_FRLHSR. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 350

32.6.39 PIO Edge Select Register

Name: PIO_ESR Offset: 0x00C0 Property: Write-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Edge Interrupt Selection Value Description 0 No effect. 1 The interrupt source is an edge-detection event. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 351

32.6.40 PIO Level Select Register

Name: PIO_LSR Offset: 0x00C4 Property: Write-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Level Interrupt Selection Value Description 0 No effect. 1 The interrupt source is a level-detection event. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 352

32.6.41 PIO Edge/Level Status Register

Name: PIO_ELSR Offset: 0x00C8 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset 0 0 0 0 0 0 0 0 PIO Edge/Level Interrupt Source Selection Value Description 0 The interrupt source is an edge-detection event. 1 The interrupt source is a level-detection event. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 353

32.6.42 PIO Falling Edge/Low-Level Select Register

Name: PIO_FELLSR Offset: 0x00D0 Property: Write-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Falling Edge/Low-Level Interrupt Selection Value Description 0 No effect.

1 The interrupt source is set to a falling edge detection or low-level detection event, depending on

32.6.43 PIO Rising Edge/High-Level Select Register

Name: PIO_REHLSR Offset: 0x00D4 Property: Write-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset PIO Rising Edge/High-Level Interrupt Selection Value Description 0 No effect.

1 The interrupt source is set to a rising edge detection or high-level detection event, depending on

32.6.44 PIO Fall/Rise - Low/High Status Register

Name: PIO_FRLHSR Offset: 0x00D8 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset 0 0 0 0 0 0 0 0 PIO Edge/Level Interrupt Source Selection Value Description

0 The interrupt source is a falling edge detection (if PIO_ELSR = 0) or low-level detection event (if

PIO_ELSR = 1).

1 The interrupt source is a rising edge detection (if PIO_ELSR = 0) or high-level detection event (if

32.6.45 PIO Lock Status Register

Name: PIO_LOCKSR Offset: 0x00E0 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 Access Reset 0 0 0 0 0 0 0 0 PIO Lock Status Value Description 0 The I/O line is not locked. 1 The I/O line is locked. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 357

32.6.46 PIO Write Protection Mode Register

Name: PIO_WPMR Offset: 0x00E4 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 WPKEY[23:16] Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 WPKEY[15:8] Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 WPKEY[7:0] Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WPEN Access Reset 0 Bits 31:8 – WPKEY[23:0] Write Protection Key Value Name Description 0x50494F PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Bit 0 – WPEN Write Protection Enable Refer to “Register Write Protection” for the list of registers that can be protected. Value Description 0 Disables the write protection if WPKEY corresponds to 0x50494F (“PIO” in ASCII). 1 Enables the write protection if WPKEY corresponds to 0x50494F (“PIO” in ASCII). SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 358

32.6.47 PIO Write Protection Status Register

Name: PIO_WPSR Offset: 0x00E8 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 WPVSRC[15:8] Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 WPVSRC[7:0] Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WPVS Access Reset 0 Bits 23:8 – WPVSRC[15:0] Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. Bit 0 – WPVS Write Protection Violation Status Value Description 0 No write protection violation has occurred since the last read of the PIO_WPSR. 1 A write protection violation has occurred since the last read of the PIO_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 359

32.6.48 PIO Schmitt Trigger Register

Name: PIO_SCHMITT Offset: 0x0100 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 SCHMITT31 SCHMITT30 SCHMITT29 SCHMITT28 SCHMITT27 SCHMITT26 SCHMITT25 SCHMITT24 Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SCHMITT23 SCHMITT22 SCHMITT21 SCHMITT20 SCHMITT19 SCHMITT18 SCHMITT17 SCHMITT16 Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SCHMITT15 SCHMITT14 SCHMITT13 SCHMITT12 SCHMITT11 SCHMITT10 SCHMITT9 SCHMITT8 Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SCHMITT7 SCHMITT6 SCHMITT5 SCHMITT4 SCHMITT3 SCHMITT2 SCHMITT1 SCHMITT0 Access Reset 0 0 0 0 0 0 0 0 SCHMITT PIO Schmitt Trigger Control Value Description 0 Schmitt trigger is enabled. 1 Schmitt trigger is disabled. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 360

32.6.49 PIO I/O Drive Register 1

Name: PIO_DRIVER1 Offset: 0x0118 Property: Read/Write Register Reset value: 0x000000000xAAAAAAAA Bit 31 30 29 28 27 26 25 24 LINE31 LINE30 LINE29 LINE28 LINE27 LINE26 LINE25 LINE24 Access Reset Bit 23 22 21 20 19 18 17 16 LINE23 LINE22 LINE21 LINE20 LINE19 LINE18 LINE17 LINE16 Access Reset Bit 15 14 13 12 11 10 9 8 LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 Access Reset Bit 7 6 5 4 3 2 1 0 LINE7 LINE6 LINE5 LINE4 LINE3 LINE2 LINE1 LINE0 Access Reset LINE Drive of PIO Line Value Name Description

0 LOW_DRIVE Lowest drive

1 HIGH_DRIVE Highest drive

32.6.50 PIO Parallel Capture Mode Register

Name: PIO_PCMR Offset: 0x0150 Reset: 0x00000000 Property: Read/Write This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 FRSTS HALFS ALWYS Access Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 DSIZE[1:0] PCEN Access Reset 0 0 0 Bit 11 – FRSTS Parallel Capture Mode First Sample This bit is useful only if the HALFS bit is set to 1. If data are numbered in the order that they are received with an index from 0 to n: Value Description 0 Only data with an even index are sampled. 1 Only data with an odd index are sampled. Bit 10 – HALFS Parallel Capture Mode Half Sampling Independently from the ALWYS bit: Value Description 0 The Parallel Capture mode samples all the data. 1 The Parallel Capture mode samples the data only every other time. Bit 9 – ALWYS Parallel Capture Mode Always Sampling Value Description 0 The Parallel Capture mode samples the data when both data enables are active. 1 The Parallel Capture mode samples the data whatever the data enables are. Bits 5:4 – DSIZE[1:0] Parallel Capture Mode Data Size Value Name Description

0 BYTE The reception data in the PIO_PCRHR is a byte (8-bit)

1 HALF-WORD The reception data in the PIO_PCRHR is a half-word (16-bit)

2 WORD The reception data in the PIO_PCRHR is a word (32-bit)

3 Reserved Reserved

Bit 0 – PCEN Parallel Capture Mode Enable Value Description 0 The Parallel Capture mode is disabled. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 362

32.6.51 PIO Parallel Capture Interrupt Enable Register

Name: PIO_PCIER Offset: 0x0154 Property: Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Enables the corresponding interrupt Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 RXBUFF ENDRX OVRE DRDY Access Reset Bit 3 – RXBUFF Reception Buffer Full Interrupt Enable Bit 2 – ENDRX End of Reception Transfer Interrupt Enable Bit 1 – OVRE Parallel Capture Mode Overrun Error Interrupt Enable Bit 0 – DRDY Parallel Capture Mode Data Ready Interrupt Enable SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 364

32.6.52 PIO Parallel Capture Interrupt Disable Register

Name: PIO_PCIDR Offset: 0x0158 Property: Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Disables the corresponding interrupt Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 RXBUFF ENDRX OVRE DRDY Access Reset Bit 3 – RXBUFF Reception Buffer Full Interrupt Disable Bit 2 – ENDRX End of Reception Transfer Interrupt Disable Bit 1 – OVRE Parallel Capture Mode Overrun Error Interrupt Disable Bit 0 – DRDY Parallel Capture Mode Data Ready Interrupt Disable SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 365

32.6.53 PIO Parallel Capture Interrupt Mask Register

Name: PIO_PCIMR Offset: 0x015C Reset: 0x00000000 Property: Read-only The following configuration values are valid for all listed bit names of this register: 0: Corresponding interrupt is not enabled. 1: Corresponding interrupt is enabled. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 RXBUFF ENDRX OVRE DRDY Access Reset 0 0 0 0 Bit 3 – RXBUFF Reception Buffer Full Interrupt Mask Bit 2 – ENDRX End of Reception Transfer Interrupt Mask Bit 1 – OVRE Parallel Capture Mode Overrun Error Interrupt Mask Bit 0 – DRDY Parallel Capture Mode Data Ready Interrupt Mask SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 366

32.6.54 PIO Parallel Capture Interrupt Status Register

Name: PIO_PCISR Offset: 0x0160 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 OVRE DRDY Access Reset 0 0 Bit 1 – OVRE Parallel Capture Mode Overrun Error The OVRE flag is automatically reset when this register is read or when the Parallel Capture mode is disabled. Value Description 0 No overrun error occurred since the last read of this register. 1 At least one overrun error occurred since the last read of this register. Bit 0 – DRDY Parallel Capture Mode Data Ready The DRDY flag is automatically reset when PIO_PCRHR is read or when the Parallel Capture mode is disabled. Value Description 0 No new data is ready to be read since the last read of PIO_PCRHR. 1 A new data is ready to be read since the last read of PIO_PCRHR. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 367

32.6.55 PIO Parallel Capture Reception Holding Register

Name: PIO_PCRHR Offset: 0x0164 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 RDATA[31:24] Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 RDATA[23:16] Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 RDATA[15:8] Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RDATA[7:0] Access Reset 0 0 0 0 0 0 0 0 Bits 31:0 – RDATA[31:0] Parallel Capture Mode Reception Data If DSIZE = 0 in PIO_PCMR, only the 8 LSBs of RDATA are useful. If DSIZE = 1 in PIO_PCMR, only the 16 LSBs of RDATA are useful. SAMV71Q21RT Parallel Input/Output Controller (PIO) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 368

External Bus Interface (EBI)

33.1 Description

The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory and SDRAM Controllers are all featured external Memory Controllers on the EBI. These external Memory Controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash and SDR-SDRAM. The EBI operates with a 3.3V power supply (VDDIO). The EBI also supports the NAND Flash protocols via integrated circuitry that greatly reduces the requirements for external components. Furthermore, the EBI handles data transfers with up to six external devices, each assigned to six address spaces defined by the embedded Memory Controller. Data transfers are performed through a 16-bit or 32-bit data bus, an address bus of up to 24 bits, up to four chip select lines (NCS[3:0]) and several control pins that are generally multiplexed between the different external Memory Controllers.

33.2 Embedded Characteristics

Integrates two External Memory Controllers – Static Memory Controller – SDR-SDRAM Controller
Integrates NAND Flash Logic
Up to 24-bit Address Bus (up to 16 Mbytes linear per chip select)
Up to four Chip Selects, Configurable Assignment – Static Memory Controller on NCS0, NCS1, NCS2, NCS3 – SDR-SDRAM Controller (SDCS) or Static Memory Controller on NCS1 – NAND Flash support on NCS0, NCS1, NSCS2 and NCS3 SAMV71Q21RT External Bus Interface (EBI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 369

33.3 EBI Block Diagram

Figure 33-1. Organization of the External Bus Interface External Bus Interface D[15:0] A[15:2], A19 PIOMUX Logic User Interface Chip Select Assignor Static Memory Controller SDR-SDRAM Controller Bus Matrix APB AHB Address Decoders A16/BA0 A0/NBS0 A17/BA1 NCS0 NRD NCS1/SDCS NWR0/NWE NWR1/NBS1 SDCK, SDCKE DQM[1:0] RAS, CAS SDWE, SDA10 A[23:20] NCS2 NWAIT NANDOE NANDWE NAND Flash Logic A21/NANDALE A22/NANDCLE NCS3/NANDCS A18

33.4 I/O Lines Description

Table 33-1. EBI I/O Lines Description Name Function Type Active Level EBI D0–D15 Data Bus I/O A0–A23 Address Bus Output NWAIT External Wait Signal Input Low SAMV71Q21RT External Bus Interface (EBI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 370

Name Function Type Active Level SMC NCS0–EBI_NCS3 Chip Select Lines Output Low NWR0–NWR1 Write Signals Output Low NRD Read Signal Output Low NWE Write Enable Output Low NBS0–NBS1 Byte Mask Signals Output Low EBI for NAND Flash Support NANDCS NAND Flash Chip Select Line Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low SDRAM Controller SDCK (see Note) SDR-SDRAM Clock Output SDCKE SDR-SDRAM Clock Enable Output High SDCS SDR-SDRAM Controller Chip Select Line Output Low BA0–1 Bank Select Output SDWE SDR-SDRAM Write Enable Output Low RAS - CAS Row and Column Signal Output Low SDA10 SDRAM Address 10 Line Output Note: SDCK is the MCK clock for EBI, SDRAM Controller and SMC interfaces. The connection of some signals through the MUX logic is not direct and depends on the Memory Controller in use at the moment. The following table details the connections between the two Memory Controllers and the EBI pins. Table 33-2. EBI Pins and Memory Controllers I/O Lines Connections EBIx Pins SDRAM I/O Lines SMC I/O Lines NWR1/NBS1 NBS1 NWR1 A0/NBS0 NBS0 SMC_A0 A1 Not Supported SMC_A1 A[11:2] SDRAMC_A[9:0] SMC_A[11:2] SDA10 SDRAMC_A10 Not Supported A12 Not Supported SMC_A12 A[15:13] SDRAMC_A[13:11] SMC_A[15:13] A[25:16] Not Supported SMC_A[25:16] SAMV71Q21RT External Bus Interface (EBI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 371

33.5 Application Example

33.5.1 Hardware Interface

The following table details the connections to be applied between the EBI pins and the external devices for each Memory Controller. Table 33-3. EBI Pins and External Static Device Connections Signals: EBI_ Pins of the Interfaced Device 8-bit Static Device 2 x 8-bit Static Devices 16-bit Static Device Controller SMC D0–D7 D0–D7 D0–D7 D0–D7 D8–D15 – D8–D15 D8–D15 A0/NBS0 A0 – NLB A1 A1 A0 A0 NCS0 CS CS CS NCS1/DDRSDCS CS CS CS NCS2 CS CS CS NCS3/NANDCS CS CS CS NRD OE OE OE NWR0/NWE WE WE (see Note) WE NWR1/NBS1 – WE (see Note) NUB Note: NWR1 enables upper byte writes. NWR0 enables lower byte writes. Table 33-4. EBI Pins and External Device Connections Signals: EBI_ Power supply Pins of the Interfaced Device SDR/LPSDR NAND Flash Controller SDRAMC NFC D0–D15 VDDIO D0–D15 D0–D15 A0/NBS0 VDDIO DQM0 – A1 VDDIO – – A2–A10 VDDIO A[0:8] – A11 VDDIO A9 – SDA10 VDDIO A10 – A12 VDDIO – – A13–A14 VDDIO A[11:12] – A15 VDDIO A13 – A16/BA0 VDDIO BA0 – SAMV71Q21RT External Bus Interface (EBI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 372

Signals: EBI_ Power supply Pins of the Interfaced Device SDR/LPSDR NAND Flash Controller SDRAMC NFC A17/BA1 VDDIO BA1 – A18 VDDIO – – A19 VDDIO – – A20 VDDIO – – A21/NANDALE VDDIO – ALE A22/NANDCLE VDDIO – CLE A23 VDDIO – – NCS0 VDDIO – – NCS1/SDCS VDDIO SDCS – NCS2 VDDIO – – NCS3/NANDCS VDDIO – CE NANDOE VDDIO – OE NANDWE VDDIO – WE NRD VDDIO – – NWR0/NWE VDDIO – – NWR1/NBS1 VDDIO DQM1 – SDCK VDDIO CK – SDCKE VDDIO CKE – RAS VDDIO RAS – CAS VDDIO CAS – SDWE VDDIO WE – Pxx VDDIO – CE Pxx VDDIO – RDY

33.5.2 Product Dependencies

33.5.2.1 I/O Lines

The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the External Bus Interface are not used by the application, they can be used for other purposes by the PIO Controller.

33.5.3 Functional Description

The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the external memories or peripheral devices. It controls the waveforms and the parameters of the external address, data and control buses and is composed of the following elements:

Static Memory Controller (SMC)
SDR-SDRAM Controller (SDRC)
A chip select assignment feature that assigns an AHB address space to the external devices SAMV71Q21RT External Bus Interface (EBI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 373

A multiplex controller circuit that shares the pins between the different Memory Controllers
Programmable NAND Flash support logic

33.5.3.1 Bus Multiplexing

The EBI offers a complete set of control signals that share the 16-bit data lines, the address lines of up to 24 bits and the control signals through a multiplex logic operating in function of the memory area requests. Multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines at a stable state while no external access is being performed. Multiplexing is also designed to respect the data float times defined in the Memory Controllers. Furthermore, refresh cycles of the SDR-SDRAM are executed independently by the SDR Controller without delaying the other external Memory Controller accesses.

33.5.3.2 Static Memory Controller

For information on the Static Memory Controller, refer to 35. Static Memory Controller (SMC)

33.5.3.3 SDRAM Controller

For information on the SDR Controller, refer to 34. SDRAM Controller (SDRAMC).

33.5.3.4 NAND Flash Support

External Bus Interfaces integrate circuitry that interfaces to NAND Flash devices. To ensure that the processor preserves transaction order and thus the correct NAND Flash behavior, the NAND Flash address space is to be declared in the Memory Protection Unit (MPU) as “Device” or “Strongly-ordered” memory. Refer to the ARM Cortex-M7 Technical Reference Manual (ARM DDI 0489) available on www.arm.com. External Bus Interface The NAND Flash Chip Select (NANDCS) is driven by the Static Memory Controller on the NCS0, NCS1, NCS2 or NCS3 address space depending on value of SMC_SMCSx bits. For example, programming the SMC_NFC3 field in the CCFG_SMCNFCS Register in the Chip Configuration User Interface to the appropriate value enables the NAND Flash logic. For details on this register, refer to 19. Bus Matrix (MATRIX). Access to an external NAND Flash device is then made by accessing the address space reserved to NCS3 (i.e., between 0x6300 0000 and 0x6FFF FFFF). The NAND Flash logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals when the required SMC_NFCSx signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address fails to lie in the selected NCSx address space. For details on these waveforms, refer to 35. Static Memory Controller (SMC). NAND Flash Signals The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the EBI address bus. The command, address or data words on the data bus of the NAND Flash device are distinguished by using their address within the NCSx address space. The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even when NCSx is not selected, preventing the device from returning to standby mode.

33.5.4 Implementation Examples

The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer web site to check current device availability. SAMV71Q21RT External Bus Interface (EBI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 374

33.5.4.1 16-bit SDRAM on NCS1 Figure 33-2. Hardware Configuration Software Configuration The following configuration has to be performed:

Enable the SDRAM support by setting the bit SDRAMEN field in the CCFG_SMCNFCS Register in the Bus Matrix.
Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width is to be programmed to 16 bits. The SDRAM initialization sequence is described in 34.5.1 SDRAM Device Initialization. SAMV71Q21RT External Bus Interface (EBI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 375

SDRAM Controller (SDRAMC)

34.1 Description

The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the interface to external 16-bit DRAM devices. The page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. The SDRAMC supports a read or write burst length of one location. It keeps track of the active row in each bank, thus maximizing SDRAM performance, for example, the application may be placed in one bank and data in the other banks. For optimized performance, it is advisable to avoid accessing different rows in the same bank. The SDRAMC supports a CAS latency of 2 or 3 and optimizes the read access depending on the frequency. The available different modes, such as Self-refresh, Powerdown and Deep Powerdown modes, minimizes the power consumption on the SDRAM device.

34.2 Embedded Characteristics

Numerous Configurations Supported – 2K, 4K, 8K row address memory parts – SDRAM with two or four internal banks – SDRAM with 16-bit data path
Programming Facilities – Word, half-word, byte access – Automatic Page break when memory boundary has been reached – Multibank ping-pong access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable – Automatic update of DS, TCR and PASR parameters (mobile SDRAM devices)
Energy-Saving Capabilities – Self-refresh, Powerdown and Deep Power modes Supported – Supports mobile SDRAM devices
Error Detection – Refresh error interrupt
SDRAM Power-up Initialization by Software
CAS Latency of 2, 3 Supported
Auto Precharge Command Not Used
Zero Wait State Scrambling/Unscrambling Function with User Key

34.3 Signal Description

Table 34-1. Signal Description Name Description Type Active Level SDCK SDRAM Clock Output – SDCKE SDRAM Clock Enable Output High SDCS SDRAMC Chip Select Output Low BA[1:0] Bank Select Signals Output – SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 376

Name Description Type Active Level RAS Row Signal Output Low CAS Column Signal Output Low SDWE SDRAM Write Enable Output Low NBS[1:0] Data Mask Enable Signals Output Low SDRAMC_A[12:0] Address Bus Output – D[15:0] Data Bus I/O –

34.4 Software Interface/SDRAM Organization, Address Mapping

The SDRAM address space is organized into banks, rows, and columns. The SDRAMC allows mapping different memory types according to the values set in the Configuration register (SDRAMC_CR). The SDRAMC makes the SDRAM device access protocol transparent to the user. The following tables illustrate the SDRAM device memory mapping seen by the user in correlation with the device structure. Various configurations are illustrated.

34.4.1 SDRAM Address Mapping for 16-bit Memory Data Bus Width

Table 34-2. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[10:0] Column[7:0] M0 Bk[1:0] Row[10:0] Column[8:0] M0 Bk[1:0] Row[10:0] Column[9:0] M0 Bk[1:0] Row[10:0] Column[10:0] M0 Note: M0 is the byte address inside a 16-bit half-word and Bk[1] = BA1, Bk[0] = BA0. Table 34-3. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[11:0] Column[7:0] M0 Bk[1:0] Row[11:0] Column[8:0] M0 Bk[1:0] Row[11:0] Column[9:0] M0 Bk[1:0] Row[11:0] Column[10:0] M0 Note: M0 is the byte address inside a 16-bit half-word and Bk[1] = BA1, Bk[0] = BA0. Table 34-4. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[12:0] Column[7:0] M0 Bk[1:0] Row[12:0] Column[8:0] M0 SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 377

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[12:0] Column[9:0] M0 Bk[1:0] Row[12:0] Column[10:0] M0 Note: M0 is the byte address inside a 16-bit half-word and Bk[1] = BA1, Bk[0] = BA0.

34.5 Product Dependencies

34.5.1 SDRAM Device Initialization

The initialization sequence is generated by software. The sequence to initialize SDRAM devices is the following: 1. Set the SDRAM features in the SDRAMC_CR: asynchronous timings (TRC, TRAS, etc.), number of columns, number of rows, CAS latency and data bus width. Set UNAL bit in SDRAMC_CFR1. 2. For mobile SDRAM, configure temperature-compensated self-refresh (TCSR), drive strength (DS) and partial array self-refresh (PASR) in the Low Power register (SDRAMC_LPR). 3. Select the SDRAM memory device type in the Memory Device register (SDRAMC_MDR). 4. A pause of at least 200 μs must be observed before a signal toggle. 5. A NOP command is issued to the SDRAM devices. The application must write a 1 to the MODE field in the Mode register (SDRAMC_MR) (see Note). Read the SDRAMC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to any SDRAM address. 6. An All Banks Precharge command is issued to the SDRAM. The application must write a 2 to the MODE field in the SDRAMC_MR. Read the SDRAMC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to any SDRAM address. 7. Eight autorefresh (CBR) cycles are provided. The application must set the MODE field to 4 in the SDRAMC_MR. Read the SDRAMC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to any SDRAM location eight times. 8. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRAM, in particular CAS latency and burst length. The application must write a 3 to the MODE field in the SDRAMC_MR. Read the SDRAMC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to the SDRAM. The write address must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at the address 0x70000000. 9. For mobile SDRAM initialization, an Extended Mode Register set (EMRS) cycle is issued to program the SDRAM parameters (TCSR, PASR, DS). The application must set the MODE field to 5 in the SDRAMC_MR. Read the SDRAMC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to the SDRAM. The write address must be chosen so that BA[1] or BA[0] are set to 1. For example, with a 16-bit 128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at address 0x70800000 or 0x70400000. 10. The application must go into Normal mode. Configure MODE to 0 in the SDRAMC_MR. Read the SDRAMC_MR and add a memory barrier assembler instruction just after the read. Perform a write access at any location in the SDRAM. 11. Write the refresh rate into the COUNT field in the Refresh Timer register (SDRAMC_TR). (Refresh rate = delay between refresh cycles). The SDRAM device requires a refresh every 15.625 μs or 7.81 μs. With a 100 MHz frequency, the Refresh Timer register must be set with the value 1562 (15.625 μs x 100 MHz) or 781 (7.81 μs x 100 MHz). After initialization, the SDRAM devices are fully functional. Note: The instructions stated in Step 5 of the initialization process must be respected to make sure the subsequent commands issued by the SDRAMC are taken into account. SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 378

Figure 34-1. SDRAM Device Initialization Sequence SDCK SDRAMC_A[9:0] A10 SDRAMC_A[12:11] SDCS RAS CAS SDWE NBS Inputs stable for 200 μ s Precharge All Banks 1st Autorefresh 8th Autorefresh MRS Command Valid Command SDCKE tRP tRFC tMRD

34.5.2 I/O Lines

The pins used for interfacing the SDRAMC may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the SDRAMC pins to their peripheral function. If I/O lines of the SDRAMC are not used by the application, they can be used for other purposes by the PIO Controller.

34.5.3 Power Management

The SDRAMC may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SDRAMC clock. The SDRAM clock on pin SDCK is output as soon as the first access to the SDRAM is made during the initialization phase. To stop the SDRAM clock signal, the SDRAMC_LPR must be programmed with the self-refresh command.

34.5.4 Interrupt Sources

The SDRAMC interrupt (Refresh Error notification) is connected to the memory controller. This interrupt may be ORed with other system peripheral interrupt lines and is finally provided as the system interrupt source (Source 1) to the interrupt controller. Using the SDRAMC interrupt requires the interrupt controller to be programmed first.

34.6 Functional Description

34.6.1 SDRAM Controller Write Cycle

The SDRAMC allows burst access or single access. In both cases, the SDRAMC keeps track of the active row in each bank, thus maximizing performance. To initiate a burst access, the SDRAMC uses the transfer type signal provided by the master requesting the access. If the next access is a sequential write access, writing to the SDRAM device is carried out. If the next access is a write-sequential access, but the current access is to a boundary page, or if the next access is in another row, then the SDRAMC generates a precharge command, activates the new row and initiates a write command. To comply with SDRAM timing parameters, additional clock cycles are inserted between precharge and active commands (tRP), and between active and write commands (tRCD). For definition of these timing parameters, refer to the SDRAMC Configuration Register. Refer to the following figure. SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 379

Figure 34-2. Write Burst SDRAM Access SDCK SDCS RAS CAS SDRAMC_A[12:0] DATA tRCD Dna SDWE Dnb Dnc Dnd Dne Dnf Dng Dnh Dni Dnj Dnk Dnl Row n col a col b col c col d col e col f col g col h col i col j col k col l

34.6.2 SDRAM Controller Read Cycle

The SDRAMC allows burst access, incremental burst of unspecified length or single access. In all cases, the SDRAMC keeps track of the active row in each bank, thus maximizing performance of the SDRAM. If row and bank addresses do not match the previous row/bank address, then the SDRAMC automatically generates a precharge command, activates the new row and starts the read command. To comply with the SDRAM timing parameters, additional clock cycles on SDCK are inserted between precharge and active commands (tRP), and between active and read commands (tRCD). These two parameters are set in the SDRAMC_CR. After a read command, additional wait states are generated to comply with the CAS latency ( 2 or 3 clock delays specified in the SDRAMC_CR). For a single access or an incremented burst of unspecified length, the SDRAMC anticipates the next access. While the last value of the column is returned by the SDRAMC on the bus, the SDRAMC anticipates the read to the next column and thus anticipates the CAS latency. This reduces the effect of the CAS latency on the internal bus. For burst access of specified length (4, 8, 16 words), access is not anticipated. This case leads to the best performance. If the burst is broken (border, Busy mode, etc.), the next access is handled as an incrementing burst of unspecified length. SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 380

Figure 34-3. Read Burst SDRAM Access SDCK SDCS RAS CAS S DRAMC_A[12:0] DATA (Input) tRCD Dna SDWE Dnb Dnc Dnd Dne Dnf Row n col a col b col c col d col e col f CAS

34.6.3 Border Management

When the memory row boundary has been reached, an automatic page break is inserted. In this case, the SDRAMC generates a precharge command, activates the new row and initiates a read or write command. To comply with SDRAM timing parameters, an additional clock cycle is inserted between the precharge and the active command (tRP) and between the active and the read command (tRCD). Refer to the following figure. Figure 34-4. Read Burst with Boundary Row Access SDCK SDCS RAS CAS SDRAMC_A[12:0] DATA tRP SDWE Row mcol a col a col b col c col d col e Dna Dnb Dnc Dnd tRCD CAS col b col c col d Dma Dmb Dmc Dmd Row n Dme

34.6.4 SDRAM Controller Refresh Cycles

An autorefresh command is used to refresh the SDRAM device. Refresh addresses are generated internally by the SDRAM device and incremented after each autorefresh automatically. The SDRAMC generates these autorefresh commands periodically. An internal timer is loaded with the value in SDRAMC_TR that indicates the number of clock cycles between refresh cycles. SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 381

A refresh error interrupt is generated when the previous autorefresh command did not perform. It is acknowledged by reading the Interrupt Status register (SDRAMC_ISR). When the SDRAMC initiates a refresh of the SDRAM device, internal memory accesses are not delayed. However, if the processor tries to access the SDRAM, the slave indicates that the device is busy and the master is held by a wait signal. Refer to the following figure. Figure 34-5. Refresh Cycle Followed by a Read Access SDCK SDCS RAS CAS SDRAMC_A[12:0] DATA (input) tRP SDWE Dnb Dnc Dnd col c col d CAS Row m col a tRFC tRCD Dma Row n

34.6.5 Power Management

Three low-power modes are available:

Self-refresh mode: The SDRAM executes its own Autorefresh cycle without control of the SDRAMC. Current drained by the SDRAM is very low.
Powerdown mode: Autorefresh cycles are controlled by the SDRAMC. Between autorefresh cycles, the SDRAM is in powerdown. Current drained in Powerdown mode is higher than in Self-refresh Mode.
Deep Powerdown mode (only available with Mobile SDRAM): The SDRAM contents are lost, but the SDRAM does not drain any current. The SDRAMC activates one low-power mode as soon as the SDRAM device is not selected. It is possible to delay the entry in Self-refresh and Powerdown modes after the last access by programming a timeout value in the SDRAMC_LPR.

34.6.5.1 Self-refresh Mode

This mode is selected by configuring SDRAMC_LPR.LPCB to 1. In Self-refresh mode, the SDRAM device retains data without external clocking and provides its own internal clocking, thus performing its own autorefresh cycles. All the inputs to the SDRAM device become “don’t care” except SDCKE, which remains low. As soon as the SDRAM device is selected, the SDRAMC provides a sequence of commands and exits Self-refresh mode. Some low-power SDRAMs (e.g., mobile SDRAM) can refresh only one-quarter or a half quarter or all banks of the SDRAM array. This feature reduces the self-refresh current. To configure this feature, Temperature Compensated Self-Refresh (TCSR), Partial Array Self-Refresh (PASR) and Drive Strength (DS) must be set in the SDRAMC_LPR and transmitted to the low-power SDRAM during initialization. After initialization, as soon as the PASR/DS/TCSR fields are modified and Self-refresh mode is activated, the Extended Mode register is accessed automatically and the PASR/DS/TCSR bits are updated before entry into Self-refresh mode. This feature is not supported when SDRAMC shares an external bus with another controller. The SDRAM device must remain in Self-refresh mode for a minimum period of tRAS and may remain in Self-refresh mode for an indefinite period. Refer to the following figure. Note: Some SDRAM providers impose some cycles of burst autorefresh immediately before self-refresh entry and immediately after self-refresh exit. For example, a SDRAM with 4096 rows will impose 4096 cycles of burst autorefresh. This constraint is not supported. SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 382

Figure 34-6. Self-refresh Mode Behavior SDCK SDCS RAS CAS SDRAMC_A[12:0] Self-refresh Mode SDWE Row tXSR SDCKE Write SDRAMC_LPR LPCB = 1 Access Request to the SDRAM Controller

34.6.5.2 Low-power Mode

This mode is selected by configuring SDRAMC_LPR.LPCB to 2. Power consumption is greater than in Self-refresh mode. All the input and output buffers of the SDRAM device are deactivated except SDCKE, which remains low. In contrast to Self-refresh mode, the SDRAM device cannot remain in Low-power mode longer than the refresh period (64 ms for a whole device refresh operation). As no autorefresh operations are performed by the SDRAM itself, the SDRAMC carries out the refresh operation. The exit procedure is faster than in Self-refresh mode. Refer to the following figure. Figure 34-7. Low-power Mode Behavior SDCK SDCS RAS CAS SDRAMC_A[12:0] DATA (input) tRCD Dna Dnb Dnc Dnd Dne Dnf Row n col a col b col c col d col e col f CAS SDCKE Low-power Mod e SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 383

34.6.5.3 Deep Powerdown Mode

This mode is selected by configuring SDRAMC_LPR.LPCB to 3. When this mode is activated, all internal voltage generators inside the SDRAM are stopped and all data is lost. When this mode is enabled, the application must not access the SDRAM until a new initialization sequence is done (see “SDRAM Device Initialization”). Refer to the following figure. Figure 34-8. Deep Powerdown Mode Behavior SDCK SDCS RAS CAS SDRAMC_A[12:0] DATA (input) tRP SDWE Dnb Dnc Dnd col c col d Row n CKE

34.6.6 Scrambling/Unscrambling Function

The external data bus can be scrambled in order to prevent intellectual property data located in off-chip memories from being easily recovered by analyzing data at the package pin level of either microcontroller or memory device. The scrambling and unscrambling are performed on-the-fly without additional wait states. The scrambling/unscrambling function can be enabled or disabled by configuring the SDR_SE bit in the OCMS register (SDRAMC_OCMS). This bit cannot be reconfigured as long as the external memory device is powered. The scrambling method depends on two user-configurable key registers, SDRAMC_OCMS_KEY1 and SDRAMC_OCMS_KEY2 plus a random value depending on device processing characteristics. These key registers are only accessible in Write mode. The scrambling user key or the seed for key generation must be securely stored in a reliable nonvolatile memory in order to recover data from the off-chip memory. Any data scrambled with a given key cannot be recovered if the key is lost. When multiple chip selects are handled, it is possible to configure the scrambling function per chip select using the OCMS field in the SDRAMC_OCMS registers. SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 384

34.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 SDRAMC_MR 7:0 MODE[2:0] 15:8 23:16 31:24 0x04 SDRAMC_TR 7:0 COUNT[7:0] 15:8 COUNT[11:8] 23:16 31:24 0x08 SDRAMC_CR 7:0 DBW CAS[1:0] NB NR[1:0] NC[1:0] 15:8 TRC_TRFC[3:0] TWR[3:0] 23:16 TRCD[3:0] TRP[3:0] 31:24 TXSR[3:0] TRAS[3:0] 0x0C ... 0x0F Reserved 0x10 SDRAMC_LPR 7:0 PASR[2:0] LPCB[1:0] 15:8 TIMEOUT[1:0] DS[1:0] TCSR[1:0] 23:16 31:24 0x14 SDRAMC_IER 7:0 RES 15:8 23:16 31:24 0x18 SDRAMC_IDR 7:0 RES 15:8 23:16 31:24 0x1C SDRAMC_IMR 7:0 RES 15:8 23:16 31:24 0x20 SDRAMC_ISR 7:0 RES 15:8 23:16 31:24 0x24 SDRAMC_MDR 7:0 MD[1:0] 15:8 23:16 31:24 0x28 SDRAMC_CFR1 7:0 TMRD[3:0] 15:8 UNAL 23:16 31:24 0x2C SDRAMC_OCMS 7:0 SDR_SE 15:8 23:16 31:24 0x30 SDRAMC_OCMS_K EY1 7:0 KEY1[7:0] 15:8 KEY1[15:8] 23:16 KEY1[23:16] 31:24 KEY1[31:24] 0x34 SDRAMC_OCMS_K EY2 7:0 KEY2[7:0] 15:8 KEY2[15:8] 23:16 KEY2[23:16] 31:24 KEY2[31:24] SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 385

34.7.1 SDRAMC Mode Register

Name: SDRAMC_MR Offset: 0x00 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 MODE[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 2:0 – MODE[2:0] SDRAMC Command Mode This field defines the command issued by the SDRAMC when the SDRAM device is accessed. Value Name Description 0 NORMAL Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, the command must be followed by a write to the SDRAM.

1 NOP The SDRAMC issues a NOP command when the SDRAM device is

accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM.

2 ALLBANKS_PRECHARGE The SDRAMC issues an “All Banks Precharge” command when the

SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM.

3 LOAD_MODEREG The SDRAMC issues a “Load Mode Register” command when the

SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM.

4 AUTO_REFRESH The SDRAMC issues an “Autorefresh” Command when the SDRAM

device is accessed regardless of the cycle. Previously, an “All Banks Precharge” command must be issued. To activate this mode, the command must be followed by a write to the SDRAM.

5 EXT_LOAD_MODEREG The SDRAMC issues an “Extended Load Mode Register” command when

the SDRAM device is accessed regardless of the cycle. To activate this mode, the “Extended Load Mode Register” command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. 6 DEEP_POWERDOWN Deep Powerdown mode. Enters Deep Powerdown mode. SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 386

34.7.2 SDRAMC Refresh Timer Register

Name: SDRAMC_TR Offset: 0x04 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 COUNT[11:8] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 11:0 – COUNT[11:0] SDRAMC Refresh Timer Count This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated. The SDRAM device requires a refresh every 15.625 μs or 7.81 μs. With a 100 MHz frequency, the Refresh Timer Counter Register must be set with the value 1562 (15.625 μs x 100 MHz) or 781 (7.81 μs x 100 MHz). To refresh the SDRAM device, this 12-bit field must be written. If this condition is not satisfied, no refresh command is issued and no refresh of the SDRAM device is carried out. SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 387

34.7.3 SDRAMC Configuration Register

Name: SDRAMC_CR Offset: 0x08 Reset: 0x852372C0 Property: Read/Write WARNINGBit 7 (DBW) must always be set when programming the SDRAMC_CR. Bit 31 30 29 28 27 26 25 24 TXSR[3:0] TRAS[3:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 0 0 0 0 1 0 1 Bit 23 22 21 20 19 18 17 16 TRCD[3:0] TRP[3:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 1 0 0 0 1 1 Bit 15 14 13 12 11 10 9 8 TRC_TRFC[3:0] TWR[3:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 1 1 0 0 1 0 Bit 7 6 5 4 3 2 1 0 DBW CAS[1:0] NB NR[1:0] NC[1:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 0 0 0 0 0 0 Bits 31:28 – TXSR[3:0] Exit Self-Refresh to Active Delay Reset value is eight cycles. This field defines the delay between SCKE set high and an Activate Command in number of cycles. Number of cycles is between 0 and 15. Bits 27:24 – TRAS[3:0] Active to Precharge Delay Reset value is five cycles. This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of cycles is between 0 and 15. Bits 23:20 – TRCD[3:0] Row to Column Delay Reset value is two cycles. This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of cycles is between 0 and 15. Bits 19:16 – TRP[3:0] Row Precharge Delay Reset value is three cycles. This field defines the delay between a Precharge Command and another Command in number of cycles. Number of cycles is between 0 and 15. Bits 15:12 – TRC_TRFC[3:0] Row Cycle Delay and Row Refresh Cycle Reset value is seven cycles. This field defines two timings:

the delay (t RFC) between two Refresh commands and between a Refresh command and an Activate command
the delay (t RC) between two Active commands in number of cycles. SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 388

The number of cycles is between 0 and 15. The end user must program max {tRC, tRFC}. Bits 11:8 – TWR[3:0] Write Recovery Delay Reset value is two cycles. This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15. Bit 7 – DBW Data Bus Width Reset value is 16 bits. This bit defines the Data Bus Width, which is 16 bits. It must be set to 1. Value Description 0 Data bus width is 32 bits. 1 Data bus width is 16 bits. Bits 6:5 – CAS[1:0] CAS Latency Reset value is two cycles. In the SDRAMC, only a CAS latency of two and three cycles is managed. Value Name Description

0 Reserved –

1 Reserved –

1 LATENCY1 1 cycle latency

2 LATENCY2 2 cycle latency

3 LATENCY3 3 cycle latency

Bit 4 – NB Number of Banks Reset value is two banks. Value Name Description

0 BANK2 2 banks

1 BANK4 4 banks

Bits 3:2 – NR[1:0] Number of Row Bits Reset value is 11 row bits. Value Name Description

0 ROW11 11 bits to define the row number, up to 2048 rows

1 ROW12 12 bits to define the row number, up to 4096 rows

2 ROW13 13 bits to define the row number, up to 8192 rows

3 Reserved

Bits 1:0 – NC[1:0] Number of Column Bits Reset value is 8 column bits. Value Name Description 0 COL8 8 bits to define the column number, up to 256 columns. 1 COL9 9 bits to define the column number, up to 512 columns. 2 COL10 10 bits to define the column number, up to 1024 columns. 3 COL11 11 bits to define the column number, up to 2048 columns. SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 389

34.7.4 SDRAMC Low-Power Register

Name: SDRAMC_LPR Offset: 0x10 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 TIMEOUT[1:0] DS[1:0] TCSR[1:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PASR[2:0] LPCB[1:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bits 13:12 – TIMEOUT[1:0] Time to Define When Low-power Mode Is Enabled Value Name Description

0 LP_LAST_XFER The SDRAMC activates the SDRAM Low-power mode immediately after the

end of the last transfer.

1 LP_LAST_XFER_64 The SDRAMC activates the SDRAM Low-power mode 64 clock cycles after the

end of the last transfer.

2 LP_LAST_XFER_128 The SDRAMC activates the SDRAM Low-power mode 128 clock cycles after

the end of the last transfer. Bits 11:10 – DS[1:0] Drive Strength (only for low-power SDRAM) DS is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parameter must be set according to the SDRAM device specification. After initialization, as soon as the DS field is modified and Self-refresh mode is activated, the Extended Mode Register is accessed automatically and DS bits are updated before entry in Self-refresh mode. This feature is not supported when SDRAMC shares an external bus with another controller. Bits 9:8 – TCSR[1:0] Temperature Compensated Self-Refresh (only for low-power SDRAM) TCSR is transmitted to the SDRAM during initialization to set the refresh interval during Self-refresh mode depending on the temperature of the low-power SDRAM. This parameter must be set according to the SDRAM device specification. After initialization, as soon as the TCSR field is modified and Self-refresh mode is activated, the Extended Mode Register is accessed automatically and TCSR bits are updated before entry in Self-refresh mode. This feature is not supported when SDRAMC shares an external bus with another controller. Bits 6:4 – PASR[2:0] Partial Array Self-refresh (only for low-power SDRAM) PASR is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks of the SDRAM array are enabled. Disabled banks are not refreshed in Self-refresh mode. This parameter must be set according to the SDRAM device specification. SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 390

After initialization, as soon as the PASR field is modified and Self-refresh mode is activated, the Extended Mode Register is accessed automatically and PASR bits are updated before entry in Self-refresh mode. This feature is not supported when SDRAMC shares an external bus with another controller. Bits 1:0 – LPCB[1:0] Low-power Configuration Bits Value Name Description

0 DISABLED The low-power feature is inhibited: no Powerdown, Self-refresh or Deep

Powerdown command is issued to the SDRAM device.

1 SELF_REFRESH The SDRAMC issues a Self-refresh command to the SDRAM device, the

SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self-refresh mode when accessed and enters it after the access.

2 POWER_DOWN The SDRAMC issues a Powerdown Command to the SDRAM device after

each access, the SDCKE signal is set to low. The SDRAM device leaves the Powerdown mode when accessed and enters it after the access. 3 DEEP_POWER_DOWN The SDRAMC issues a Deep Powerdown command to the SDRAM device. This mode is unique to low-power SDRAM. SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 391

34.7.5 SDRAMC Interrupt Enable Register

Name: SDRAMC_IER Offset: 0x14 Property: Write-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 RES Access W Reset Bit 0 – RES Refresh Error Interrupt Enable Value Description 0 No effect. 1 Enables the refresh error interrupt. SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 392

34.7.6 SDRAMC Interrupt Disable Register

Name: SDRAMC_IDR Offset: 0x18 Property: Write-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 RES Access W Reset Bit 0 – RES Refresh Error Interrupt Disable Value Description 0 No effect. 1 Disables the refresh error interrupt. SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 393

34.7.7 SDRAMC Interrupt Mask Register

Name: SDRAMC_IMR Offset: 0x1C Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 RES Access R Reset 0 Bit 0 – RES Refresh Error Interrupt Mask Value Description 0 The refresh error interrupt is disabled. 1 The refresh error interrupt is enabled. SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 394

34.7.8 SDRAMC Interrupt Status Register

Name: SDRAMC_ISR Offset: 0x20 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 RES Access R Reset 0 Bit 0 – RES Refresh Error Status (cleared on read) Value Description 0 No refresh error has been detected since the register was last read. 1 A refresh error has been detected since the register was last read. SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 395

34.7.9 SDRAMC Memory Device Register

Name: SDRAMC_MDR Offset: 0x24 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 MD[1:0] Access R/W R/W Reset 0 0 Bits 1:0 – MD[1:0] Memory Device Type Value Name Description

0 SDRAM SDRAM

1 LPSDRAM Low-power SDRAM

34.7.10 SDRAMC Configuration Register 1

Name: SDRAMC_CFR1 Offset: 0x28 Reset: 0x00000002 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 UNAL Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 TMRD[3:0] Access R/W R/W R/W R/W Reset 0 0 1 0 Bit 8 – UNAL Support Unaligned Access This mode is enabled with masters which have an AXI interface. Value Name Description 0 UNSUPPORTED Unaligned access is not supported. 1 SUPPORTED Unaligned access is supported. Bits 3:0 – TMRD[3:0] Load Mode Register Command to Active or Refresh Command Reset value is 2 cycles. This field defines the delay between a “Load Mode Register” command and an active or refresh command in number of cycles. Number of cycles is between 0 and 15. SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 397

34.7.11 SDRAMC OCMS Register

Name: SDRAMC_OCMS Offset: 0x2C Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 SDR_SE Access R/W Reset 0 Bit 0 – SDR_SE SDRAM Memory Controller Scrambling Enable Value Description 0 Disables off-chip scrambling for SDR-SDRAM access. 1 Enables off-chip scrambling for SDR-SDRAM access. SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 398

34.7.12 SDRAMC OCMS KEY1 Register

Name: SDRAMC_OCMS_KEY1 Offset: 0x30 Property: Write-only Bit 31 30 29 28 27 26 25 24 KEY1[31:24] Access W W W W W W W W Reset Bit 23 22 21 20 19 18 17 16 KEY1[23:16] Access W W W W W W W W Reset Bit 15 14 13 12 11 10 9 8 KEY1[15:8] Access W W W W W W W W Reset Bit 7 6 5 4 3 2 1 0 KEY1[7:0] Access W W W W W W W W Reset Bits 31:0 – KEY1[31:0] Off-chip Memory Scrambling (OCMS) Key Part 1 When off-chip memory scrambling is enabled, the data scrambling depends on KEY1 and KEY2 values. SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 399

34.7.13 SDRAMC OCMS KEY2 Register

Name: SDRAMC_OCMS_KEY2 Offset: 0x34 Reset: – Property: Write-only Bit 31 30 29 28 27 26 25 24 KEY2[31:24] Access W W W W W W W W Bit 23 22 21 20 19 18 17 16 KEY2[23:16] Access W W W W W W W W Bit 15 14 13 12 11 10 9 8 KEY2[15:8] Access W W W W W W W W Bit 7 6 5 4 3 2 1 0 KEY2[7:0] Access W W W W W W W W Bits 31:0 – KEY2[31:0] Off-chip Memory Scrambling (OCMS) Key Part 2 When off-chip memory scrambling is enabled, the data scrambling depends on KEY1 and KEY2 values. SAMV71Q21RT SDRAM Controller (SDRAMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 400

Static Memory Controller (SMC)

35.1 Description

The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the ARM-based microcontroller. The Static Memory Controller (SMC) is part of the EBI. The SMC handles several types of external memory and peripheral devices, such as SRAM, PSRAM, PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash. The SMC generates the signals that control the access to the external memory devices or peripheral devices. It has 4 chip selects, a 24-bit address bus, and a configurable 8 or 16-bit data bus. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully adjustable. The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with an automatic Slow clock mode. In Slow clock mode, it switches from user-programmed waveforms to slow-rate specific waveforms on read and write signals. The SMC supports asynchronous burst read in Page mode access for page sizes up to 32 bytes. The external data bus can be scrambled/unscrambled by means of user keys.

35.2 Embedded Characteristics

Four Chip Selects Available
16-Mbyte Address Space per Chip Select
8-bit or 16-bit Data Bus
Zero Wait State Scrambling/Unscrambling Function with User Key
Word, Halfword, Byte Transfers
Byte Write or Byte Select Lines
Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
Programmable Data Float Time per Chip Select
External Wait Request
Automatic Switch to Slow Clock Mode
Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
Register Write Protection

35.3 I/O Lines Description

Table 35-1. I/O Line Description Name Description Type Active Level NCS[3:0] Static Memory Controller Chip Select Lines Output Low NRD Read Signal Output Low NWR0/NWE Write 0/Write Enable Signal Output Low NWR1/NBS1 Write 1/Byte 1 Select Signal Output Low A0/NBS0 Address Bit 0/Byte 0 Select Signal Output Low A[23:1] Address Bus Output – D[15:0] Data Bus I/O – SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 401

Name Description Type Active Level NWAIT External Wait Signal Input Low NANDCS NAND Flash Chip Select Line Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low NANDALE NAND Flash Address Latch Enable Output – NANDCLE NAND Flash Command Latch Enable Output –

35.4 Multiplexed Signals

Table 35-2. Static Memory Controller (SMC) Multiplexed Signals Multiplexed Signals Related Function NWR0 NWE Byte-write or Byte-select access. See ”Byte Write Access” and ”Byte Select Access” A0 NBS0 8-bit or 16-bit data bus. See ”Data Bus Width” NWR1 NBS1 Byte-write or Byte-select access. See ”Byte Write Access” and ”Byte Select Access” A22 NANDCLE NAND Flash Command Latch Enable A21 NANDALE NAND Flash Address Latch Enable

35.5 Product Dependencies

35.5.1 I/O Lines

The pins used for interfacing the SMC are multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the SMC pins to their peripheral function. If I/O lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller.

35.5.2 Power Management

The SMC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SMC clock.

35.6 External Memory Mapping

The SMC provides up to 24 address lines, A[23:0]. This allows each chip select line to address up to 16 Mbytes of memory. If the physical memory device connected on one chip select is smaller than 16 Mbytes, it wraps around and appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see the following figure). SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 402

Figure 35-1. Memory Connections for Four External Devices NRD NWE A[23:0] D[15:0] 16 or 8 Memory Enable Memory Enable Memory Enable Memory Enable Output Enable Write Enable A[23:0] D[15:0] or D[7:0] NCS3 NCS0 NCS1 NCS2 NCS[0] - NCS[3] SMC

35.7 Connection to External Devices

35.7.1 Data Bus Width

A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by the bit DBW in the Mode register (SMC_MODE) for the corresponding chip select. Figure 35-2 shows how to connect a 512-Kbyte × 8-bit memory on NCS2. Figure 35-3 shows how to connect a 512-Kbyte × 16-bit memory on NCS2. Figure 35-2. Memory Connection for an 8-bit Data Bus SMC NWE NRD NCS[2] Write Enable Output Enable Memory Enable D[7:0] D[7:0] A[18:2]A[18:2] A0 A0 Figure 35-3. Memory Connection for a 16-bit Data Bus SMC NBS0 NWE NRD NCS[2] Low Byte Enable Write Enable Output Enable Memory Enable NBS1 High Byte Enable D[15:0] D[15:0] A[19:2] A[18:1] A[0] A1 SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 403

35.7.2 Byte Write or Byte Select Access

Each chip select with a 16-bit data bus can operate with one of two different types of write access: byte write or byte select. This is controlled by the BAT field of the SMC_MODE register for the corresponding chip select.

35.7.2.1 Byte Write Access

Byte write access is used to connect 2 × 8-bit devices as a 16-bit memory, and supports one write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in Byte write access mode. For 16-bit devices, the SMC provides NWR0 and NWR1 write signals for respectively Byte0 (lower byte) and Byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided.

35.7.2.2 Byte Select Access

Byte select access is used to connect one 16-bit device. In this mode, read/write operations can be enabled/disabled at byte level. One byte-select line per byte of the data bus is provided. One NRD and one NWE signal control read and write. For 16-bit devices, the SMC provides NBS0 and NBS1 selection signals for respectively Byte0 (lower byte) and Byte1 (upper byte) of a 16-bit bus. Figure 35-4. Connection of 2 × 8-bit Devices on a 16-bit Bus: Byte Write Option SMC A1 NWR0 NRD NCS[3] Write Enable Read Enable Memory Enable NWR1 Write Enable Read Enable Memory Enable D[7:0] D[7:0] D[15:8] D[15:8] A[24:2] A[23:1] A[23:1] A[0] A[0]

35.7.2.3 Signal Multiplexing

Depending on the byte access type (BAT), only the byte write signals or the byte select signals are used. To save I/Os at the external bus interface, control signals at the SMC interface are multiplexed. The following table shows signal multiplexing depending on the data bus width and the byte access type. For 16-bit devices, bit A0 of address is unused. When the Byte Select option is selected, NWR1 is unused. When the Byte Write option is selected, NBS0 is unused. SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 404

Table 35-3. SMC Multiplexed Signal Translation Device Type Signal Name 16-bit Bus 8-bit Bus 1 x 16-bit 2 x 8-bit 1 x 8-bit Byte Access Type (BAT) Byte Select Byte Write – NBS0_A0 NBS0 – A0 NWE_NWR0 NWE NWR0 NWE NBS1_NWR1 NBS1 NWR1 – A1 A1 A1 A1

35.7.3 NAND Flash Support

The SMC integrates circuitry that interfaces to NAND Flash devices. The NAND Flash logic is driven by the SMC. Configuration is done via the SMC_NFCSx field in the CCFG_SMCNFCS register in the Bus Matrix. For details on this register, refer to the section “Bus Matrix (MATRIX)” of this datasheet. The external NAND Flash device is accessed via the address space reserved for the chip select programmed. The user can connect up to four NAND Flash devices with separate chip selects. The NAND Flash logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals when the NCSx programmed is active. NANDOE and NANDWE are disabled as soon as the transfer address fails to lie in the NCSx programmed address space. Figure 35-5. NAND Flash Signal Multiplexing on SMC Pins SMC NRD NWE NANDOE NANDWE NAND Flash Logic NCSx NANDW E NANDO E Note: 1. NCSx is active when CCFG_SMCNFCS.SMC_NFCSx=1. Note: 2. When the NAND Flash logic is activated, (SMC_NFCSx=1), the NWE pin can be used only in Peripheral mode (NWE function). If the NWE function is not used for other external memories (SRAM, LCD), it must be configured in one of the following modes: PIO input with pull-up enabled (default state after reset) and PIO output set at level 1. The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21of the address bus. Any bit of the address bus can also be used for this purpose. The command, address or data words on the data bus of the NAND Flash device use their own addresses within the NCSx address space (configured in the register CCFG_SMCNFCS in the Bus Matrixe). The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even when NAND Flash chip select is not selected, preventing the device from returning to Standby mode. The NANDCS output signal should be used in accordance with the external NAND Flash device type. Two types of CE behavior exist depending on the NAND Flash device:

Standard NAND Flash devices require that the CE pin remains asserted low continuously during the read busy period to prevent the device from returning to Standby mode. Since the SMC asserts the NCSx signal high, it is necessary to connect the CE pin of the NAND Flash device to a GPIO line, in order to hold it low during the busy period preceding data read out. SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 405

This restriction has been removed for “CE don’t care” NAND Flash devices. The NCSx signal can be directly connected to the CE pin of the NAND Flash device. The following figure illustrates both topologies: Standard and “CE don’t care” NAND Flash. Figure 35-6. Standard and “CE don’t care” NAND Flash Application Examples D[7:0] ALE NANDWE NOE NWE A[22:21] CLE AD[7:0] PIO R/B SMC CE NAND Flash PIO NCSx Not Connected NANDOE D[7:0] ALE NANDWE NOE NWE A[22:21] CLE AD[7:0] PIO R/B SMC CE “CE don’t care ” NAND Flash NCSx NANDOE Related Links 19. Bus Matrix (MATRIX)

35.8 Application Example

35.8.1 Implementation Examples

Hardware configurations are given for illustration only. The user should refer to the manufacturer web site to check for memory device availability. For hardware implementation examples, refer to the evaluation kit schematics for this microcontroller, which show examples of a connection to an LCD module and NAND Flash. SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 406

35.8.1.1 8-bit NAND Flash Hardware Configuration Figure 35-7. 8-bit NAND Flash NANDOE NANDWE (ANY PIO) (ANY PIO) ALE CLE D[0..7] 3V3 3V3 2 Gb TSOP48 PACKAGE U1 K9F2G08U0MU1 K9F2G08U0M WE18 N.C6 VCC 37 CE9 RE8 N.C20 WP19 N.C5 N.C1 N.C2 N.C3 N.C4 N.C21 N.C22 N.C23 N.C24 R/B7 N.C26 N.C 27N.C 28 I/O0 29 N.C 34N.C 35 VSS 36 PRE 38N.C 39 VCC 12 VSS 13 ALE17 N.C11 N.C10 N.C14 N.C15 CLE16 N.C25 N.C 33 I/O1 30 I/O3 32I/O2 31 N.C 47 N.C 46 N.C 45 I/O7 44I/O6 43I/O5 42I/O4 41 N.C 40 N.C 48R2 10KR2 10K 100NF 100NF R1 10KR1 10K 100NF 100NF Software Configuration Perform the following configuration: 1. Select the chip select used to drive the NAND Flash by setting the bit CCFG_SMCNFCS.SMC_NFCSx. 2. Reserve A21 / A22 for ALE / CLE functions. Address and Command Latches are controlled by setting the address bits A21 and A22, respectively, during accesses. 3. NANDOE and NANDWE signals are multiplexed with PIO lines. Thus, the dedicated PIOs must be programmed in Peripheral mode in the PIO controller. 4. Configure a PIO line as an input to manage the Ready/Busy signal. 5. Configure SMC CS3 Setup, Pulse, Cycle and Mode according to NAND Flash timings, the data bus width and the system bus frequency. In this example, the NAND Flash is not addressed as a “CE don’t care”. To address it as a “CE don’t care”, connect NCS3 (if SMC_NFCS3 is set) to the NAND Flash CE. SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 407

35.8.1.2 NOR Flash

Figure 35-8. NOR Flash A21 A15 A12 A13 A11 A10 A14 A16 A17 A20 A18 A19 D[0..7] A [0..21] NRST NWE NCS0 NRD 3V3 3V3 100NF 100NF 100NF 100NF U1U1 A10 A11 A12 A13 A14 A15 A16 A17 A18 A21 A20 A19 WE RESET WP OE CE VPP DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCCQ VSS VSS VCC Software Configuration Configure the SMC CS0 Setup, Pulse, Cycle, and Mode, depending on Flash timings and system bus frequency.

35.9 Standard Read and Write Protocols

In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS1) always have the same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the byte write lines (NWR0 to NWR1) in byte write access type. NWR0 to NWR1 have the same timings and protocol as NWE. If D[15:8] are used, they have the same timing as D[7:0]. In the same way, NCS represents one of the NCS[0..3] chip select lines.

35.9.1 Read Waveforms

The read cycle is shown in the following figure. The read cycle starts with the address setting on the memory address bus. SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 408

Figure 35-9. Standard Read Cycle A[23:0] NCS NRD_SETUP NRD_PULSE NRD_HOLD MCK NRD D[7:0] NCS_RD_SETUP NCS_RD_PULSE NCS_RD_HOLD NRD_CYCLE

35.9.1.1 NRD Waveform

The NRD signal is characterized by a setup timing, a pulse width and a hold timing.

nrd_setup— NRD setup time is defined as the setup of address before the NRD falling edge;
nrd_pulse—NRD pulse length is the time between NRD falling edge and NRD rising edge;
nrd_hold—NRD hold time is defined as the hold time of address after the NRD rising edge.

35.9.1.2 NCS Waveform

The NCS signal can be divided into a setup time, pulse length and hold time:

ncs_rd_setup—NCS setup time is defined as the setup time of address before the NCS falling edge.
ncs_rd_pulse—NCS pulse length is the time between NCS falling edge and NCS rising edge;
ncs_rd_hold—NCS hold time is defined as the hold time of address after the NCS rising edge.

35.9.1.3 Read Cycle

The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. The total read cycle time is defined as: NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD, as well as NRD_CYCLE = NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles. The NRD_CYCLE field is common to both the NRD and NCS signals, thus the timing period is of the same duration. NRD_CYCLE, NRD_SETUP, and NRD_PULSE implicitly define the NRD_HOLD value as: NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE NRD_CYCLE, NCS_RD_SETUP, and NCS_RD_PULSE implicitly define the NCS_RD_HOLD value as: NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE

35.9.1.4 Null Delay Setup and Hold

If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in case of consecutive read cycles in the same memory (see the following figure). SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 409

Figure 35-10. No Setup, No Hold on NRD and NCS Read Signals MCK NRD_PULSE NCS_RD_PULSE NRD_CYCLE NRD_PULSE NRD_PULSE NCS_RD_PULSE NCS_RD_PULSE NRD_CYCLE NRD_CYCLE A[23:0] NCS NRD D[7:0]

35.9.1.5 Null Pulse

Programming a null pulse is not permitted. The pulse must be at least set to 1. A null value leads to unpredictable behavior.

35.9.2 Read Mode

As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is available on the data bus. The SMC does not compare NCS and NRD timings to know which signal rises first. The READ_MODE bit in the SMC_MODE register of the corresponding chip select indicates which signal of NRD and NCS controls the read operation. 35.9.2.1 Read is Controlled by NRD (SMC_MODE.READ_MODE = 1): The following figure shows the waveforms of a read operation of a typical asynchronous RAM. The read data is available tPACC after the falling edge of NRD, and turns to ‘Z’ after the rising edge of NRD. In this case, SMC_MODE.READ_MODE must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD, whatever the programmed waveform of NCS may be. SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 410

Figure 35-11. SMC_MODE.READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD Data Sampling tPACC MCK A[23:0] NCS NRD D[7:0] 35.9.2.2 Read is Controlled by NCS (SMC_MODE.READ_MODE = 0) The following figure shows the typical read cycle of an LCD module. The read data is valid tPACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised. In this case, the SMC_MODE.READ_MODE must be set to 0 (read is controlled by NCS): the SMC internally samples the data on the rising edge of Master Clock that generates the rising edge of NCS, whatever the programmed waveform of NRD may be. Figure 35-12. SMC_MODE.READ_MODE = 0: Data is Sampled by SMC Before the Rising Edge of NCS Data Sampling tPACC MCK D[7:0] A[23:0] NCS NRD

35.9.3 Write Waveforms

The write protocol is similar to the read protocol. It is depicted in Figure 35-13. The write cycle starts with the address setting on the memory address bus.

35.9.3.1 NWE Waveforms

The NWE signal is characterized by a setup timing, a pulse width and a hold timing.

NWE_SETUP—the NWE setup time is defined as the setup of address and data before the NWE falling edge;
NWE_PULSE—the NWE pulse length is the time between NWE falling edge and NWE rising edge;
NWE_HOLD—the NWE hold time is defined as the hold time of address and data after the NWE rising edge. SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 411

35.9.3.2 NCS Waveforms

The NCS signal waveforms in write operation are not the same that those applied in read operations, but are separately defined:

ncs_wr_setup—the NCS setup time is defined as the setup time of address before the NCS falling edge.
ncs_wr_pulse—the NCS pulse length is the time between NCS falling edge and NCS rising edge;
ncs_wr_hold—the NCS hold time is defined as the hold time of address after the NCS rising edge. Figure 35-13. Write Cycle A [23:0] NCS NWE_SETUP NWE_PULSE NWE_HOLD MCK NWE NCS_WR_SETUP NCS_WR_PULSE NCS_WR_HOLD NWE_CYCLE

35.9.3.3 Write Cycle

The write_cycle time is defined as the total duration of the write cycle; that is, from the time where address is set on the address bus to the point where address may change. The total write cycle time is defined as: NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD, as well as NWE_CYCLE = NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock cycles. The NWE_CYCLE field is common to both the NWE and NCS signals, thus the timing period is of the same duration. NWE_CYCLE, NWE_SETUP, and NWE_PULSE implicitly define the NWE_HOLD value as: NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE NWE_CYCLE, NCS_WR_SETUP, and NCS_WR_PULSE implicitly define the NCS_WR_HOLD value as: NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE

35.9.3.4 Null Delay Setup and Hold

If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of consecutive write cycles in the same memory (see the following figure). However, for devices that perform write operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed. SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 412

Figure 35-14. Null Setup and Hold Values of NCS and NWE in Write Cycle NCS MCK NWE D[7:0] NWE_PULSE NCS_WR_PULSE NWE_CYCLE NWE_PULSE NCS_WR_PULSE NWE_CYCLE NWE_PULSE NCS_WR_PULSE NWE_CYCLE A [23:0]

35.9.3.5 Null Pulse

Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior.

35.9.4 Write Mode

The bit WRITE_MODE in the SMC_MODE register of the corresponding chip select indicates which signal controls the write operation. The following figure shows the waveforms of a write operation with SMC_MODE.WRITE_MODE set . The data is put on the bus during the pulse and hold steps of the NWE signal. The internal data buffers are switched to Output mode after the NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS. Figure 35-15. SMC_MODE.WRITE_MODE = 1. Write Operation is Controlled by NWE MCK D[7:0] NCS A [23:0] NWE SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 413

The following figure shows the waveforms of a write operation with SMC_MODE.WRITE_MODE cleared. The data is put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are switched to Output mode after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. Figure 35-16. WRITE_MODE = 0. Write Operation is Controlled by NCS MCK D[7:0] NCS NWE A [23:0]

35.9.5 Register Write Protection

To prevent any single software error that may corrupt SMC behavior, the registers listed below can be write-protected by setting the WPEN bit in the SMC Write Protection Mode register (SMC_WPMR). If a write access in a write-protected register is detected, the WPVS flag in the SMC Write Protection Status register (SMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. The WPVS flag is automatically cleared after reading the SSMC_WPSR. The following registers can be write-protected:

“SMC Setup Register”
“SMC Pulse Register”
“SMC Cycle Register”
“SMC Mode Register”
"SMC Off-chip Memory Scrambling Register"

35.9.6 Coding Timing Parameters

All timing parameters are defined for one chip select and are grouped together in one register according to their type. The SMC_SETUP register groups the definition of all setup parameters:

NRD_SETUP
NCS_RD_SETUP
NWE_SETUP
NCS_WR_SETUP The SMC_PULSE register groups the definition of all pulse parameters:
NRD_PULSE
NCS_RD_PULSE
NWE_PULSE
NCS_WR_PULSE The SMC_CYCLE register groups the definition of all cycle parameters:
NRD_CYCLE SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 414

NWE_CYCLE The following table shows how the timing parameters are coded and their permitted range. Table 35-4. Coding and Range of Timing Parameters Coded Value Number of Bits Effective Value Permitted Range Coded Value Effective Value setup [5:0] 6 128 × setup[5] + setup[4:0] 0 ≤ 31 0 ≤ 128+31 pulse [6:0] 7 256 × pulse[6] + pulse[5:0] 0 ≤ 63 0 ≤ 256+63 cycle [8:0] 9 256 × cycle[8:7] + cycle[6:0] 0 ≤ 127 0 ≤ 256+127 0 ≤ 512+127 0 ≤ 768+127

35.9.7 Reset Values of Timing Parameters

The following table provides the default value of timing parameters at reset. Table 35-5. Reset Values of Timing Parameters Parameter Reset Value Definition SMC_SETUP 0x01010101 All setup timings are set to 1. SMC_PULSE 0x01010101 All pulse timings are set to 1. SMC_CYCLE 0x00030003 The read and write operations continue for 3 Master Clock cycles and provide one hold cycle. WRITE_MODE 1 Write is controlled with NWE. READ_MODE 1 Read is controlled with NRD.

35.9.8 Usage Restriction

The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE parameters is larger than the corresponding CYCLE parameter, this leads to unpredictable behavior of the SMC.

For read operations: Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the memory interface because of the propagation delay of theses signals through external logic and pads. If positive setup and hold values must be verified, then it is strictly recommended to program non-null values so as to cover possible skews between address, NCS and NRD signals.
For write operations: If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address and NCS signal after the rising edge of NWE. This is true for SMC_MODE.WRITE_MODE = 1 only. See ”Early Read Wait State”.
For read and write operations: A null value for pulse parameters is forbidden and may lead to unpredictable behavior. In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For external devices that require setup and hold time between NCS and NRD signals (read), or between NCS and NWE signals (write), these setup and hold times must be converted into setup and hold times in reference to the address bus.

35.10 Scrambling/Unscrambling Function

The external data bus can be scrambled to protect intellectual property data located in off-chip memories by means of data analysis at the package pin level of either the microcontroller or the memory device. The scrambling and unscrambling are performed on-the-fly without additional wait states. SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 415

The scrambling/unscrambling function can be enabled or disabled by configuring the CSxSE bits in the SMC Off-Chip Memory Scrambling Register (SMC_OCMS). When multiple chip selects are handled, the scrambling function per chip select is configurable using the CSxSE bits in the SMC_OCMS register. The scrambling method depends on two user-configurable key registers, SMC_KEY1 and SMC_KEY2 plus a random value depending on device processing characteristics. These key registers cannot be read. They can be written once after a system reset. The scrambling user key or the seed for key generation must be securely stored in a reliable non-volatile memory in order to recover data from the off-chip memory. Any data scrambled with a given key cannot be recovered if the key is lost.

35.11 Automatic Wait States

Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or operation conflict.

35.11.1 Chip Select Wait States

The SMC always inserts an idle cycle between two transfers on separate Chip Selects. This idle cycle ensures that there is no bus contention between the deactivation of one device and the activation of the next one. During Chip Select Wait state, all control lines are turned inactive: NWR, NCS[0..3], NRD lines are all set to 1. The following figure illustrates a Chip Select Wait state between access on Chip Select 0 and Chip Select 2. Figure 35-17. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2 A[23:0] NCS0 NRD_CYCLE Chip Select Wait State NWE_CYCLE MCK NCS2 NRD NWE D[7:0] Read to Write Wait State

35.11.2 Early Read Wait State

In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state. The early read cycle thus only occurs between a write and read access to the same memory device (same chip select). An early read wait state is automatically inserted if at least one of the following conditions is valid: SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 416

Figure 35-20. Early Read Wait State: NWE-controlled write with no hold followed by a read with one set-up cycle A[25:2] write cycle (WRITE_MODE = 1) Early Read wait state MCK NRD internal write controlling signal external write controlling signal (NWE) D[7:0] read cycle no hold read setup = 1 (READ_MODE = 0 or READ_MODE = 1)

35.11.3 Reload User Configuration Wait State

The user may change any of the configuration parameters by writing the SMC user interface. When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state before starting the next access. This “reload user configuration wait state” is used by the SMC to load the new set of parameters to apply to next accesses. The reload configuration wait state is not applied in addition to the chip select wait state. If accesses before and after re-programming the user interface are made to different devices (chip selects), then one single chip select wait state is applied. On the other hand, if accesses before and after writing the user interface are made to the same device, a reload configuration wait state is inserted, even if the change does not concern the current chip select.

35.11.3.1 User Procedure

To insert a reload configuration wait state, the SMC detects a write access to any SMC_MODE register of the user interface. If the user only modifies timing registers (SMC_SETUP, SMC_PULSE, SMC_CYCLE registers) in the user interface, he must validate the modification by writing the SMC_MODE, even if no change was made on the mode parameters. The user must not change the configuration parameters of an SMC chip select (Setup, Pulse, Cycle, Mode) if accesses are performed on this CS during the modification. Any change of the chip select parameters, while fetching the code from a memory connected on this CS, may lead to unpredictable behavior. The instructions used to modify the parameters of an SMC chip select can be executed from the internal RAM or from a memory connected to another CS.

35.11.3.2 Slow Clock Mode Transition

A reload configuration wait state is also inserted when the Slow Clock mode is entered or exited, after the end of the current transfer (see ”Slow Clock Mode”).

35.11.4 Read to Write Wait State

Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred to as a read to write wait state in this document. This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted. See Figure 12-1. SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 418

35.12 Data Float Wait States

Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data float wait states) after a read access:

before starting a read access to a different external memory
before starting a write access to the same device or to a different external one. The data float output time (tDF) for each external memory device is programmed in the SMC_MODE.TDF_CYCLES field for the corresponding chip select. The value of SMC_MODE.TDF_CYCLES indicates the number of data float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed for the data output to go to high impedance after the memory is disabled. Data float wait states do not delay internal memory accesses. Hence, a single access to an external memory with long tDF will not slow down the execution of a program from internal memory. The data float wait states management depends on SMC_MODE.READ_MODE and the SMC_MODE.TDF_MODE fields for the corresponding chip select. 35.12.1 SMC_MODE.READ_MODE Setting SMC_MODE.READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turning off the tri-state buffers of the external memory device. The Data Float Period then begins after the rising edge of the NRD signal and lasts SMC_MODE.TDF_CYCLES MCK cycles. When the read operation is controlled by the NCS signal (SMC_MODE.READ_MODE = 0), the TDF field gives the number of MCK cycles during which the data bus remains busy after the rising edge of NCS. Figure 35-21 illustrates the Data Float Period in NRD-controlled mode (SMC_MODE.READ_MODE =1), assuming a data float period of 2 cycles (SMC_MODE.TDF_CYCLES = 2). Figure 35-22 shows the read operation when controlled by NCS (SMC_MODE.READ_MODE = 0) and SMC_MODE.TDF_CYCLES = 3. Figure 35-21. TDF Period in NRD Controlled Read Access (TDF = 2) NCS NRD controlled read operation tpacc MCK NRD D[7:0] TDF = 2 clock cycles A[23:0] SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 419

35.12.3 TDF Optimization Disabled (SMC_MODE.TDF_MODE = 0) When optimization is disabled, TDF Wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins. If the hold period of the read1 controlling signal overlaps the data float period, no additional TDF Wait states will be inserted. Figure 35-24, Figure 35-25 and Figure 35-26 illustrate the cases:

read access followed by a read access on another Chip Select,
read access followed by a write access on another Chip Select,
read access followed by a write access on the same Chip Select, with no TDF optimization. Figure 35-24. TDF Optimization Disabled (TDF Mode = 0): TDF wait states between 2 read accesses on different chip selects TDF_CYCLES = 6 TDF_CYCLES = 6 TDF_MODE = 0 A[23:0] read1 cycle Chip Select Wait State MCK read1 controlling signal (NRD) read2 controlling signal (NRD) D[7:0] read1 hold = 1 read 2 cycle read2 setup = 1

5 TDF WAIT STATES

(optimization disabled) Figure 35-25. TDF Mode = 0: TDF wait states between a read and a write access on different chip selects TDF_CYCLES = 4 TDF_CYCLES = 4 TDF_MODE = 0 (optimization disabled) A[23:0] read1 cycle Chip Select Wait State Read to Write Wait State MCK read1 controlling signal (NRD) write2 controlling signal (NWE) D[7:0] read1 hold = 1 write2 cycle write2 setup = 1

2 TDF WAIT STATES

Figure 35-26. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select TDF_CYCLES = 5 TDF_CYCLES = 5 TDF_MODE = 0 (optimization disabled) A[23:0] read1 cycle Read to Write Wait State MCK read1 controlling signal (NRD) write2 controlling signal (NWE) D[7:0] read1 hold = 1 write2 cycle write2 setup = 1

4 TDF WAIT STATES

35.13 External Wait

Any access can be extended by an external device using the NWAIT input signal of the SMC. The SMC_MODE.EXNW_MODE field on the corresponding chip select must be set either to “10” (Frozen mode) or “11” (Ready mode). When SMC_MODE.EXNW_MODE is set to “00” (disabled), the NWAIT signal is simply ignored on the corresponding chip select. The NWAIT signal delays the read or write operation in regards to the read or write controlling signal, depending on the Read and Write modes of the corresponding chip select.

35.13.1 Restriction

When SMC_MODE.EXNW_MODE is enabled, it is mandatory to program at least one hold cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be used in Page mode (35.15 Asynchronous Page Mode), or in Slow clock mode (”Slow Clock Mode”). The NWAIT signal is assumed to be a response of the external device to the read/write request of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write controlling signal. The assertion of the NWAIT signal outside the expected period has no impact on SMC behavior.

35.13.2 Frozen Mode

When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See Figure 35-27. This mode must be selected when the external device uses the NWAIT signal to delay the access and to freeze the SMC. The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure 35-28. SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 422

Figure 35-27. Write Access with NWAIT Assertion in Frozen Mode (SMC_MODE.EXNW_MODE = 10) E XNW_MODE = 10 (Frozen) WR ITE _MODE = 1 (NWE _controlled) NWE _P ULS E = 5 NC S _WR _P ULS E = 7 A[23:0] MC K NWE NC S 4 3 2 1 1 1 0 1 4 5 6 3 2 2 2 2 1 0 Write cycle D[7:0] NWAIT FR OZE N S TATE internally synchronized NWAIT signal Figure 35-28. Read Access with NWAIT Assertion in Frozen Mode (SMC_MODE.EXNW_MODE = 10) EXNW_MODE = 10 (Frozen) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 2, NRD_HOLD = 6 NCS_RD_PULSE =5, NCS_RD_HOLD =3 A[23:0] MCK NCS NRD 1 0 4 3 4 3 5 5 5 2 2 0 2 1 0 2 1 0 Read cycle Assertion is ignored NWAIT internally synchronized NWAIT signal FROZEN STATE

35.13.3 Ready Mode

In Ready mode (SMC_MODE.EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 423

If asserted, the SMC suspends the access as shown in Figure 35-29 and Figure 35-30. After deassertion, the access is completed: the hold step of the access is performed. This mode must be selected when the external device uses deassertion of the NWAIT signal to indicate its ability to complete the read or write operation. If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling read/write signal, it has no impact on the access length as shown in Figure 35-30. Figure 35-29. NWAIT Assertion in Write Access: Ready Mode (SMC_MODE.EXNW_MODE = 11) E XNW_MODE = 11 (R eady mode) WR ITE _MODE = 1 (NWE _controlled) NWE _P ULS E = 5 NC S _WR _P ULS E = 7 A[23:0] MC K NWE NC S 4 3 2 1 0 0 0 4 5 6 3 2 1 1 1 0 Write cycle D[7:0] NWAIT internally synchronized NWAIT signal Wait S TATE SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 424

Figure 35-30. NWAIT Assertion in Read Access: Ready Mode (SMC_MODE.EXNW_MODE = 11) EXNW_MODE = 11(Ready mode) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 7 NCS_RD_PULSE =7 A[23:0] MCK NCS NRD 4 5 6 3 2 0 0 4 5 6 3 2 1 1 Read cycle Assertion is ignored NWAIT internally synchronized NWAIT signal Wait STATE Assertion is ignored

35.13.4 NWAIT Latency and Read/Write Timings

There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + one cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in Frozen mode as well as in Ready mode. This is illustrated in the following figure. When SMC_MODE.EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the read and write controlling signal of at least: Minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 425

Figure 35-31. NWAIT Latency E XNW_MODE = 10 or 11 R E AD_MODE = 1 (NR D_controlled) NR D_P ULS E = 5 A[23:0] MC K NR D 4 3 2 1 0 0 0 R ead cycle minimal pulse length NWAIT latency NWAIT intenally synchronized NWAIT signal WAIT S TATE 2 cycle resynchronization

35.14 Slow Clock Mode

The SMC is able to automatically apply a set of “Slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32kHz clock rate). In this mode, the user-programmed waveforms are ignored and the Slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at a very slow clock rate. When activated, the Slow clock mode is active on all chip selects.

35.14.1 Slow Clock Mode Waveforms

Figure 35-32 illustrates the read and write operations in Slow Clock mode. They are valid on all Chip Selects. Table 35-6 indicates the value of read and write parameters in Slow Clock mode. Figure 35-32. Read/Write Cycles in Slow Clock Mode A[ 23:0] NCS MCK NWE 1 NWE_CYCLE = 3 A [23:0] MCK NRD NRD_CYCLE = 2 NCS SLOW CLOCK MODE WRITE SLOW CLOCK MODE READ SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 426

Table 35-6. Read and Write Timing Parameters in Slow Clock Mode Read Parameters Duration (cycles) Write Parameters Duration (cycles) NRD_SETUP 1 NWE_SETUP 1 NRD_PULSE 1 NWE_PULSE 1 NCS_RD_SETUP 0 NCS_WR_SETUP 0 NCS_RD_PULSE 2 NCS_WR_PULSE 3 NRD_CYCLE 2 NWE_CYCLE 3

35.14.2 Switching from (to) Slow Clock Mode to (from) Normal Mode

When switching from Slow clock mode to Normal mode, the current Slow clock mode transfer is completed at a high clock rate, with the set of Slow clock mode parameters (see Figure 35-33). The external device may not be fast enough to support such timings. Figure 35-34 illustrates the recommended procedure to switch from one mode to the other. Figure 35-33. Clock Rate Transition Occurs while the SMC is Performing a Write Operation A [23:0] NCS MCK NWE NWE_CYCLE = 3 SLOW CLOCK MODE WRITE Slow Clock Mode internal signal from PMC 1 1 1 2 3 2 NWE_CYCLE = 7 NORMAL MODE WRITE Slow clock mode transition is detected: Reload Confi guration Wait State This write cycle finishes with the slow clock mode set of parameters after the clock rate transition SLOW CLOCK MODE WRITE SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 427

Figure 35-34. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode A[23:0] NC S MC K NWE S LOW C LOC K MODE WR ITE S low C lock Mode internal signal from P MC 2 3 2 NOR MAL MODE WR ITE IDLE S TATE R eload C onf guration Wait S tate

35.15 Asynchronous Page Mode

The SMC supports asynchronous burst reads in Page mode, provided that the Page mode is enabled (SMC_MODE.PMEN =1). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes. The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the address of the page in memory, the LSB of address define the address of the data in the page as detailed in the following table. With Page mode memory devices, the first access to one page (tpa) takes longer than the subsequent accesses to the page (tsa) as shown in Page Mode Read Protocol. When in Page mode, the SMC enables the user to define different read timings for the first access within one page, and next accesses within the page. Table 35-7. Page Address and Data Address within a Page Page Size Page Address (see Note) Data Address in the Page 4 bytes A[23:2] A[1:0] 8 bytes A[23:3] A[2:0] 16 bytes A[23:4] A[3:0] 32 bytes A[23:5] A[4:0] Note: “A” denotes the address bus of the memory device.

35.15.1 Protocol and Timings in Page Mode

The following figure shows the NRD and NCS timings in Page mode access. SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 428

Figure 35-35. Page Mode Read Protocol (Address MSB and LSB are defined in Table 35-7) A[MSB] NCS MCK NRD D[7:0] NCS_RD_PULSE NRD_PULSENRD_PULSE tsa tpa tsa A[LSB] The NRD and NCS signals are held low during all read transfers, whatever the programmed values of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS timings are identical. The pulse length of the first access to the page is defined with the NCS_RD_PULSE field of the SMC_PULSE register. The pulse length of subsequent accesses within the page are defined using the NRD_PULSE parameter. In Page mode, the programming of the read timings is described in the following table: Table 35-8. Programming of Read Timings in Page Mode Parameter Value Definition READ_MODE 'x' No impact. NCS_RD_SETUP 'x' No impact. NCS_RD_PULSE tpa Access time of first access to the page. NRD_SETUP 'x' No impact. NRD_PULSE tsa Access time of subsequent accesses in the page. NRD_CYCLE 'x' No impact. The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE timings as page access timing (tpa) and the NRD_PULSE for accesses to the page (tsa), even if the programmed value for tpa is shorter than the programmed value for tsa.

35.15.2 Page Mode Restriction

The Page mode is not compatible with the use of the NWAIT signal. Using the Page mode and the NWAIT signal may lead to unpredictable behavior.

35.15.3 Sequential and Non-sequential Accesses

If the chip select and the MSB of addresses as defined in Table 35-7 are identical, then the current access lies in the same page as the previous one, and no page break occurs. Using this information, all data within the same page, sequential or not sequential, are accessed with a minimum access time (tsa). The following figure illustrates access to an 8-bit memory device in Page mode, with 8-byte pages. Access to D1 causes a page access with a long access time (tpa). Accesses to D3 and D7, though they are not sequential accesses, only require a short access time (tsa). SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 429

If the MSB of addresses are different, the SMC performs the access of a new page. In the same way, if the chip select is different from the previous access, a page break occurs. If two sequential accesses are made to the Page mode memory, but separated by an other internal or external peripheral access, a page break occurs on the second access because the chip select of the device was deasserted between both accesses. Figure 35-36. Access to Non-Sequential Data within the Same Page A[23:3] A[2], A1, A0 NC S MC K NR D P age address A1 A3 A7 D[7:0] NC S _R D_P ULS E NR D_P ULS ENR D_P ULS E D1 D3 D7 SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 430

35.16 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 SMC_SETUP[0..3] 7:0 NWE_SETUP[5:0] 15:8 NCS_WR_SETUP[5:0] 23:16 NRD_SETUP[5:0] 31:24 NCS_RD_SETUP[5:0] 0x00 SMC_PULSE[0..3] 7:0 NWE_PULSE[6:0] 15:8 NCS_WR_PULSE[6:0] 23:16 NRD_PULSE[6:0] 31:24 NCS_RD_PULSE[6:0] 0x00 SMC_CYCLE[0..3] 7:0 NWE_CYCLE[7:0] 15:8 NWE_CYCLE[ 23:16 NRD_CYCLE[7:0] 31:24 NRD_CYCLE[ 0x00 SMC_MODE[0..3] 7:0 EXNW_MODE[1:0] WRITE_MOD E READ_MODE 15:8 DBW BAT 23:16 TDF_MODE TDF_CYCLES[3:0] 31:24 PS[1:0] PMEN 0x04 ... 0x7F Reserved 0x80 SMC_OCMS 7:0 SMSE 15:8 CS3SE CS2SE CS1SE CS0SE 23:16 31:24 0x84 SMC_KEY1 7:0 KEY1[7:0] 15:8 KEY1[15:8] 23:16 KEY1[23:16] 31:24 KEY1[31:24] 0x88 SMC_KEY2 7:0 KEY2[7:0] 15:8 KEY2[15:8] 23:16 KEY2[23:16] 31:24 KEY2[31:24] 0x8C ... 0xE3 Reserved 0xE4 SMC_WPMR 7:0 WPEN 15:8 WPKEY[7:0] 23:16 WPKEY[15:8] 31:24 WPKEY[23:16] 0xE8 SMC_WPSR 7:0 WPVS 15:8 WPVSRC[7:0] 23:16 WPVSRC[15:8] 31:24

35.16.1 Static Memory Controller (SMC) User Interface

The SMC is programmed using the registers listed in the following table. For each Chip Select, a set of four registers is used to program the parameters of the external device connected on it. In the Register Summary, “CS_number” denotes the Chip Select number. 16 bytes (0x10) are required per Chip Select. SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 431

35.16.1.1 SMC Setup Register

Name: SMC_SETUP[0..3] Offset: 0x00 Reset: 0 Property: R/W This register can only be written if the WPEN bit is cleared in the “SMC Write Protection Mode Register” . Bit 31 30 29 28 27 26 25 24 NCS_RD_SETUP[5:0] Access Reset 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 NRD_SETUP[5:0] Access Reset 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 NCS_WR_SETUP[5:0] Access Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NWE_SETUP[5:0] Access Reset 0 0 0 0 0 0 Bits 29:24 – NCS_RD_SETUP[5:0] NCS Setup Length in READ Access In read access, the NCS signal setup length is defined as: NCS setup length = (128* NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles Bits 21:16 – NRD_SETUP[5:0] NRD Setup Length The NRD signal setup length is defined in clock cycles as: NRD setup length = (128* NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles Bits 13:8 – NCS_WR_SETUP[5:0] NCS Setup Length in WRITE Access In write access, the NCS signal setup length is defined as: NCS setup length = (128* NCS_WR_SETUP[5] + NCS_WR_SETUP[4:0]) clock cycles Bits 5:0 – NWE_SETUP[5:0] NWE Setup Length The NWE signal setup length is defined as: NWE setup length = (128* NWE_SETUP[5] + NWE_SETUP[4:0]) clock cycles SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 432

35.16.1.2 SMC Pulse Register

Name: SMC_PULSE[0..3] Offset: 0x00 Reset: 0 Property: R/W This register can only be written if the WPEN bit is cleared in the “SMC Write Protection Mode Register” . Bit 31 30 29 28 27 26 25 24 NCS_RD_PULSE[6:0] Access Reset 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 NRD_PULSE[6:0] Access Reset 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 NCS_WR_PULSE[6:0] Access Reset 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NWE_PULSE[6:0] Access Reset 0 0 0 0 0 0 0 Bits 30:24 – NCS_RD_PULSE[6:0] NCS Pulse Length in READ Access In standard read access, the NCS signal pulse length is defined as: NCS pulse length = (256* NCS_RD_PULSE[6] + NCS_RD_PULSE[5:0]) clock cycles The NCS pulse length must be at least 1 clock cycle. In Page mode read access, the NCS_RD_PULSE parameter defines the duration of the first access to one page. Bits 22:16 – NRD_PULSE[6:0] NRD Pulse Length In standard read access, the NRD signal pulse length is defined in clock cycles as: NRD pulse length = (256* NRD_PULSE[6] + NRD_PULSE[5:0]) clock cycles The NRD pulse length must be at least 1 clock cycle. In Page mode read access, the NRD_PULSE parameter defines the duration of the subsequent accesses in the page. Bits 14:8 – NCS_WR_PULSE[6:0] NCS Pulse Length in WRITE Access In write access, the NCS signal pulse length is defined as: NCS pulse length = (256* NCS_WR_PULSE[6] + NCS_WR_PULSE[5:0]) clock cycles The NCS pulse length must be at least 1 clock cycle. Bits 6:0 – NWE_PULSE[6:0] NWE Pulse Length The NWE signal pulse length is defined as: NWE pulse length = (256* NWE_PULSE[6] + NWE_PULSE[5:0]) clock cycles The NWE pulse length must be at least 1 clock cycle. SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 433

35.16.1.3 SMC Cycle Register

Name: SMC_CYCLE[0..3] Offset: 0x00 Reset: 0 Property: R/W This register can only be written if the WPEN bit is cleared in the “SMC Write Protection Mode Register” . Bit 31 30 29 28 27 26 25 24 NRD_CYCLE[8] Access Reset 0 Bit 23 22 21 20 19 18 17 16 NRD_CYCLE[7:0] Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 NWE_CYCLE[8 Access Reset 0 Bit 7 6 5 4 3 2 1 0 NWE_CYCLE[7:0] Access Reset 0 0 0 0 0 0 0 0 Bits 24:16 – NRD_CYCLE[8:0] Total Read Cycle Length The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse and hold steps of the NRD and NCS signals. It is defined as: Read cycle length = (NRD_CYCLE[8:7]*256 + NRD_CYCLE[6:0]) clock cycles Bits 8:0 – NWE_CYCLE[8:0] Total Write Cycle Length The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pulse and hold steps of the NWE and NCS signals. It is defined as: Write cycle length = (NWE_CYCLE[8:7]*256 + NWE_CYCLE[6:0]) clock cycles SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 434

35.16.1.4 SMC Mode Register

Name: SMC_MODE[0..3] Offset: 0x00 Reset: 0 Property: R/W This register can only be written if the WPEN bit is cleared in the “SMC Write Protection Mode Register” . The user must confirm the SMC configuration by writing any one of the SMC_MODE registers. Bit 31 30 29 28 27 26 25 24 PS[1:0] PMEN Access Reset 0 0 0 Bit 23 22 21 20 19 18 17 16 TDF_MODE TDF_CYCLES[3:0] Access Reset 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DBW BAT Access Reset 0 0 Bit 7 6 5 4 3 2 1 0 EXNW_MODE[1:0] WRITE_MODE READ_MODE Access Reset 0 0 0 0 Bits 29:28 – PS[1:0] Page Size If page mode is enabled, this field indicates the size of the page in bytes. Value Name Description 0 4_BYTE 4-byte page 1 8_BYTE 8-byte page 2 16_BYTE 16-byte page 3 32_BYTE 32-byte page Bit 24 – PMEN Page Mode Enabled Value Description 0 Standard read is applied. 1 Asynchronous burst read in page mode is applied on the corresponding chip select. Bit 20 – TDF_MODE TDF Optimization Value Description 0 TDF optimization disabled–the number of TDF wait states is inserted before the next access begins.

1 TDF optimization enabled–the number of TDF wait states is optimized using the setup period of the

next read/write access. Bits 19:16 – TDF_CYCLES[3:0] Data Float Time This field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF_CYCLES period. The external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can be set. Bit 12 – DBW Data Bus Width SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 435

0 8_BIT 8-bit Data Bus 1 16_BIT 16-bit Data Bus Bit 8 – BAT Byte Access Type This field is used only if DBW defines a 16-bit data bus. Value Name Description

0 BYTE_SELECT Byte select access type:

Write operation is controlled using NCS, NWE, NBS0, NBS1. - Read operation is controlled using NCS, NRD, NBS0, NBS1.

1 BYTE_WRITE Byte write access type:

Write operation is controlled using NCS, NWR0, NWR1. - Read operation is controlled using NCS and NRD. Bits 5:4 – EXNW_MODE[1:0] NWAIT Mode The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of the read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be programmed for the read and write controlling signal. Value Name Description 0 DISABLED Disabled–The NWAIT input signal is ignored on the corresponding chip select.

1 Reserved

2 FROZEN Frozen Mode–If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped.

3 READY Ready Mode–The NWAIT signal indicates the availability of the external device at the end

of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. Bit 1 – WRITE_MODE Write Mode Value Description 0 The write operation is controlled by the NCS signal. – If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NCS. 1 The write operation is controlled by the NWE signal. – If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NWE. Bit 0 – READ_MODE Read Mode Value Description 0 The read operation is controlled by the NCS signal. – If TDF cycles are programmed, the external bus is marked busy after the rising edge of NCS. – If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NCS. 1 The read operation is controlled by the NRD signal. – If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD. – If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NRD. SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 436

35.16.1.5 SMC Off-Chip Memory Scrambling Register

Name: SMC_OCMS Offset: 0x80 Reset: 0x00000000 Property: Read/Write Note: This register can only be written if the WPEN bit is cleared in the SMC Write Protection Mode Register (35.16.1.8 SMC_WPMR). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 CS3SE CS2SE CS1SE CS0SE Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SMSE Access R/W Reset 0 Bits 8, 9, 10, 11 – CSSE Chip Select x Scrambling Enable Value Description 0 Disable scrambling for CSx. 1 Enable scrambling for CSx. Bit 0 – SMSE Static Memory Controller Scrambling Enable Value Description 0 Disable scrambling for SMC access. 1 Enable scrambling for SMC access. SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 437

35.16.1.6 SMC Off-Chip Memory Scrambling Key1 Register

Name: SMC_KEY1 Offset: 0x84 Reset: 0x00000000 Property: Write-once Note: 1. ‘Write-once’ access indicates that the first write access after a system reset prevents any further modification of the value of this register. Bit 31 30 29 28 27 26 25 24 KEY1[31:24] Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 KEY1[23:16] Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 KEY1[15:8] Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 KEY1[7:0] Access Reset 0 0 0 0 0 0 0 0 Bits 31:0 – KEY1[31:0] Off-Chip Memory Scrambling (OCMS) Key Part 1 When off-chip memory scrambling is enabled, KEY1 and KEY2 values determine data scrambling. SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 438

35.16.1.7 SMC Off-Chip Memory Scrambling Key2 Register

Name: SMC_KEY2 Offset: 0x88 Reset: 0x00000000 Property: Write-once Note: ‘Write-once’ access indicates that the first write access after a system reset prevents any further modification of the value of this register. Bit 31 30 29 28 27 26 25 24 KEY2[31:24] Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 KEY2[23:16] Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 KEY2[15:8] Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 KEY2[7:0] Access Reset 0 0 0 0 0 0 0 0 Bits 31:0 – KEY2[31:0] Off-Chip Memory Scrambling (OCMS) Key Part 2 When off-chip memory scrambling is enabled, KEY1 and KEY2 values determine data scrambling. SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 439

35.16.1.8 SMC Write Protection Mode Register

Name: SMC_WPMR Offset: 0xE4 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 WPKEY[23:16] Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 WPKEY[15:8] Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 WPKEY[7:0] Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WPEN Access Reset 0 Bits 31:8 – WPKEY[23:0] Write Protection Key Value Name Description 0x534D43 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Bit 0 – WPEN Write Protect Enable See ”Register Write Protection” for the list of registers that can be write-protected. Value Description 0 Disables the write protection if WPKEY corresponds to 0x534D43 (“SMC” in ASCII). 1 Enables the write protection if WPKEY corresponds to 0x534D43 (“SMC” in ASCII). SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 440

35.16.1.9 SMC Write Protection Status Register

Name: SMC_WPSR Offset: 0xE8 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 WPVSRC[15:8] Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 WPVSRC[7:0] Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WPVS Access Reset 0 Bits 23:8 – WPVSRC[15:0] Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. Bit 0 – WPVS Write Protection Violation Status Value Description 0 No write protection violation has occurred since the last read of the SMC_WPSR register. 1 A write protection violation has occurred since the last read of the SMC_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. SAMV71Q21RT Static Memory Controller (SMC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 441

DMA Controller (XDMAC)

36.1 Description

The DMA Controller (XDMAC) is a AHB-protocol central direct memory access controller. It performs peripheral data transfer and memory move operations over one or two bus ports through the unidirectional communication channel. Each channel is fully programmable and provides both peripheral or memory-to-memory transfers. The channel features are configurable at implementation.

36.2 Embedded Characteristics

2 AHB Master Interfaces
24 DMA Channels
43 Hardware Requests
3.1 Kbytes Embedded FIFO
Supports Peripheral-to-Memory, Memory-to-Peripheral, or Memory-to-Memory Transfer Operations
Peripheral DMA Operation Runs on Bytes (8-bit), Half-Word (16-bit) and Word (32-bit)
Memory DMA Operation Runs on Bytes (8 bit), Half-Word (16-bit) and Word (32 -bit)
Supports Hardware and Software Initiated Transfers
Supports Linked List Operations
Supports Incrementing or Fixed Addressing Mode
Supports Programmable Independent Data Striding for Source and Destination
Supports Programmable Independent Microblock Striding for Source and Destination
Configurable Priority Group and Arbitration Policy
Programmable AHB Burst Length
Configuration Interface Accessible through APB Interface
XDMAC Architecture Includes Multiport FIFO
Supports Multiple View Channel Descriptor
Automatic Flush of Channel Trailing Bytes
Automatic Coarse-Grain and Fine-Grain Clock Gating
Hardware Acceleration of Memset Pattern SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 442

36.3 Block Diagram

Figure 36-1. DMA Controller (XDMAC) Block Diagram Status Registers Configuration Registers APB Interface DMA Interrupt Dual Master AHB Interface Request Arbiter Hardware Request InterfaceControl and Data Steering Request Pool DMA Read/Write Datapath AMBA AHB Layer APB Interface DMA Interrupt Peripheral Hardware Requests DMA ChannelData FIFO Destination FSM Source FSM DMA System Controller AMBA AHB Layer

36.4 DMA Controller Peripheral Connections

Table 36-1. Peripheral Hardware Requests Peripheral Name Transfer Type HW Interface Number (XDMAC_CC.PERID) HSMCI Transmit/Receive 0 SPI0 Transmit 1 SPI0 Receive 2 SPI1 Transmit 3 SPI1 Receive 4 QSPI Transmit 5 QSPI Receive 6 USART0 Transmit 7 USART0 Receive 8 USART1 Transmit 9 USART1 Receive 10 USART2 Transmit 11 USART2 Receive 12 SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 443

Peripheral Name Transfer Type HW Interface Number (XDMAC_CC.PERID) PWM0 Transmit 13 TWIHS0 Transmit 14 TWIHS0 Receive 15 TWIHS1 Transmit 16 TWIHS1 Receive 17 TWIHS2 Transmit 18 TWIHS2 Receive 19 UART0 Transmit 20 UART0 Receive 21 UART1 Transmit 22 UART1 Receive 23 UART2 Transmit 24 UART2 Receive 25 UART3 Transmit 26 UART3 Receive 27 UART4 Transmit 28 UART4 Receive 29 DACC Transmit 30 SSC Transmit 32 SSC Receive 33 PIOA Receive 34 AFEC0 Receive 35 AFEC1 Receive 36 AES Transmit 37 AES Receive 38 PWM1 Transmit 39 TC0 Receive 40 TC3 Receive 41 TC6 Receive 42 TC9 Receive 43 I2SC0 Transmit Left 44 I2SC0 Receive Left 45 I2SC1 Transmit Left 46 I2SC1 Receive Left 47 I2SC0 Transmit Right 48 SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 444

Peripheral Name Transfer Type HW Interface Number (XDMAC_CC.PERID) I2SC0 Receive Right 49 I2SC1 Transmit Right 50 I2SC1 Receive Right 51

36.5 Functional Description

36.5.1 Basic Definitions

Source Peripheral: Slave device, memory mapped on the interconnection network, from where the XDMAC reads data. The source peripheral teams up with a destination peripheral to form a channel. A data read operation is scheduled when the peripheral transfer request is asserted. Destination Peripheral: Slave device, memory mapped on the interconnection network, to which the XDMAC writes. A write data operation is scheduled when the peripheral transfer request is asserted. Channel: The data movement between source and destination creates a logical channel. Transfer Type: The transfer is hardware-synchronized when it is paced by the peripheral hardware request, otherwise the transfer is self-triggered (memory to memory transfer).

36.5.2 Transfer Hierarchy Diagram

XDMAC Master Transfer: The Master Transfer is composed of a linked list of blocks. The channel address, control and configuration registers can be modified at the inter block boundary. The descriptor structure modifies the channel registers conditionally. Interrupts can be generated on a per block basis or when the end of linked list event occurs. XDMAC Block: An XDMAC block is composed of a programmable number of microblocks. The channel configuration registers remain unchanged at the inter microblock boundary. The source and destination addresses are conditionally updated with a programmable signed number. XDMAC Microblock: The microblock is composed of a programmable number of data. The channel configuration registers remain unchanged at the data boundary. The data address may be fixed (a FIFO location, a peripheral transmit or receive register), incrementing (a memory-mapped area) by a programmable signed number. XDMAC Burst and Incomplete Burst: In order to improve the overall performance when accessing dynamic external memory, burst access is mandatory. Each data of the microblock is considered as a part of a memory burst. The programmable burst value indicates the largest memory burst allowed on a per channel basis. When the microblock length is not an integral multiple of the burst size, an incomplete burst is performed to read or write the last trailing bytes. XDMAC Chunk and Incomplete Chunk: When a peripheral synchronized transfer is activated, the microblock splits into a number of data chunks. The chunk size is programmable. The larger the chunk is, the better the performance is. When the transfer size is not a multiple of the chunk size, the last chunk may be incomplete. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 445

Figure 36-2. XDMAC Memory Transfer Hierarchy Master Transfer BLK 0 BLK 1 BLK (N-1) μBLK 0 μBLK 1 μBLK (M-1) MB 0 MB (p-1) iMB Memory Burst Level Micro Block Level Block Level Figure 36-3. XDAMC Peripheral Transfer Hierarchy Master Transfer BLK 0 BLK 1 BLK (N-1) μBLK 0 μBLK 1 μBLK (M-1) CHK 0 CHK (p-1) iCHK Chunk Level Micro Block Level Block Level

36.5.3 Peripheral Synchronized Transfer

A peripheral hardware request interface is used to control the pace of the chunk transfer. When a peripheral is ready to transmit or receive a chunk of data, it asserts its request line and the DMA Controller transfers a data to or from the memory to the peripheral.

36.5.3.1 Software Triggered Synchronized Transfer

The Peripheral hardware request can be software controlled using the SWREQ field of the XDMAC Global Channel Software Request Register (XDMAC_GSWR). The peripheral synchronized transfer is paced using a processor write access in the XDMAC_GSWR. Each bit of that register triggers a transfer request. The XDMAC Global Channel Software Request Status Register (XDMAC_GSWS) indicates the status of the request; when set, the request is still pending. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 446

36.5.4 XDMAC Transfer Software Operation

36.5.4.1 Single Block Transfer With Single Microblock

Read the XDMAC Global Channel Status Register (XDMAC_GS) to select a free channel. 2. Clear the pending Interrupt Status bit(s) by reading the selected XDMAC Channel x Interrupt Status Register (XDMAC_CISx). 3. Write the XDMAC Channel x Source Address Register (XDMAC_CSAx) for channel x. 4. Write the XDMAC Channel x Destination Address Register (XDMAC_CDAx) for channel x. 5. Program field UBLEN in the XDMAC Channel x Microblock Control Register (XDMAC_CUBCx) with the number of data. 6. Program the XDMAC Channel x Configuration Register (XDMAC_CCx): 6.1. Clear XDMAC_CCx.TYPE for a memory-to-memory transfer, otherwise set this bit. 6.2. Configure XDMAC_CCx.MBSIZE to the memory burst size used. 6.3. Configure XDMAC_CCx.SAM and DAM to Memory Addressing mode. 6.4. Configure XDMAC_CCx.DSYNC to select the peripheral transfer direction. 6.5. Configure XDMAC_CCx.CSIZE to configure the channel chunk size (only relevant for peripheral synchronized transfer). 6.6. Configure XDMAC_CCx.DWIDTH to configure the transfer data width. 6.7. Configure XDMAC_CCx.SIF, XDMAC_CCx.DIF to configure the master interface used to read data and write data, respectively. 6.8. Configure XDMAC_CCx.PERID to select the active hardware request line (only relevant for a peripheral synchronized transfer). 6.9. Set XDMAC_CCx.SWREQ to use a software request (only relevant for a peripheral synchronized transfer). 7. Clear the following five registers: – XDMAC Channel x Next Descriptor Control Register (XDMAC_CNDCx) – XDMAC Channel x Block Control Register (XDMAC_CBCx) – XDMAC Channel x Data Stride Memory Set Pattern Register (XDMAC_CDS_MSPx) – XDMAC Channel x Source Microblock Stride Register (XDMAC_CSUSx) – XDMAC Channel x Destination Microblock Stride Register (XDMAC_CDUSx) This indicates that the linked list is disabled, there is only one block and striding is disabled. 8. Enable the Microblock interrupt by writing a ‘1’ to bit BIE in the XDMAC Channel x Interrupt Enable Register (XDMAC_CIEx). Enable the Channel x Interrupt Enable bit by writing a ‘1’ to bit IEx in the XDMAC Global Interrupt Enable Register (XDMAC_GIE). 9. Enable channel x by writing a ‘1’ to bit ENx in the XDMAC Global Channel Enable Register (XDMAC_GE). XDMAC_GS.STx (XDMAC Channel x Status bit) is set by hardware. 10. Once completed, the DMA channel sets XDMAC_CISx.BIS (End of Block Interrupt Status bit) and generates an interrupt. XDMAC_GS.STx is cleared by hardware. The software can either wait for an interrupt or poll the channel status bit.

36.5.4.2 Single Block Transfer With Multiple Microblock

Read the XDMAC_GS register to choose a free channel. 2. Clear the pending Interrupt Status bit by reading the chosen XDMAC_CISx register. 3. Write the XDMAC_CSAx register for channel x. 4. Write the XDMAC_CDAx register for channel x. 5. Program XDMAC_CUBCx.UBLEN with the number of data. 6. Program XDMAC_CCx register (see “Single Block Transfer With Single Microblock”). 7. Program XDMAC_CBCx.BLEN with the number of microblocks of data. 8. Clear the following registers: – XDMAC_CNDCx – XDMAC_CDS_MSPx – XDMAC_CSUSx XDMAC_CDUSx SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 447

This indicates that the linked list is disabled and striding is disabled. 9. Enable the Block interrupt by writing a ‘1’ to XDMAC_CIEx.BIE, enable the Channel x Interrupt Enable bit by writing a ‘1’ to XDMAC_GIEx.IEx. 11. Once completed, the DMA channel sets XDMAC_CISx.BIS (End of Block Interrupt Status bit) and generates an interrupt. XDMAC_GS.STx is cleared by hardware. The software can either wait for an interrupt or poll the channel status bit.

36.5.4.3 Master Transfer

Read the XDMAC_GS register to choose a free channel. 2. Clear the pending Interrupt Status bit by reading the chosen XDMAC_CISx register. 3. Build a linked list of transfer descriptors in memory. The descriptor view is programmable on a per descriptor basis. The linked list items structure must be word aligned. MBR_UBC.NDE must be configured to 0 in the last descriptor to terminate the list. 4. Configure field NDA in the XDMAC Channel x Next Descriptor Address Register (XDMAC_CNDAx) with the first descriptor address and bit XDMAC_CNDAx.NDAIF with the master interface identifier. 5. Configure the XDMAC_CNDCx register: 5.1. Set XDMAC_CNDCx.NDE to enable the descriptor fetch. 5.2. Set XDMAC_CNDCx.NDSUP to update the source address at the descriptor fetch time, otherwise clear this bit. 5.3. Set XDMAC_CNDCx.NDDUP to update the destination address at the descriptor fetch time, otherwise clear this bit. 5.4. Configure XDMAC_CNDCx.NDVIEW to define the length of the first descriptor. 6. Enable the End of Linked List interrupt by writing a ‘1’ to XDMAC_CIEx.LIE. 8. Once completed, the DMA channel sets XDMAC_CISx.BIS (End of Block Interrupt Status bit) and generates an interrupt. XDMAC_GS.STx is cleared by hardware. The software can either wait for an interrupt or poll the channel status bit.

36.5.4.4 Disabling A Channel Before Transfer Completion

Under normal operation, the software enables a channel by writing a ‘1’ to XDMAC_GE.ENx, then the hardware disables a channel on transfer completion by clearing bit XDMAC_GS.STx. To disable a channel, write a ‘1’ to bit XDMAC_GD.DIx and poll the XDMAC_GS register.

36.6 Linked List Descriptor Operation

36.6.1 Linked List Descriptor View

36.6.1.1 Channel Next Descriptor View 0–3 Structures

Table 36-2. Channel Next Descriptor View 0–3 Structures Channel Next Descriptor Offset Structure member Name View 0 Structure DSCR_ADDR+0x00 Next Descriptor Address Member MBR_NDA DSCR_ADDR+0x04 Microblock Control Member MBR_UBC DSCR_ADDR+0x08 Transfer Address Member MBR_TA View 1 Structure DSCR_ADDR+0x00 Next Descriptor Address Member MBR_NDA DSCR_ADDR+0x04 Microblock Control Member MBR_UBC DSCR_ADDR+0x08 Source Address Member MBR_SA DSCR_ADDR+0x0C Destination Address Member MBR_DA SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 448

Channel Next Descriptor Offset Structure member Name View 2 Structure DSCR_ADDR+0x00 Next Descriptor Address Member MBR_NDA DSCR_ADDR+0x04 Microblock Control Member MBR_UBC DSCR_ADDR+0x08 Source Address Member MBR_SA DSCR_ADDR+0x0C Destination Address Member MBR_DA DSCR_ADDR+0x10 Configuration Register MBR_CFG View 3 Structure DSCR_ADDR+0x00 Next Descriptor Address Member MBR_NDA DSCR_ADDR+0x04 Microblock Control Member MBR_UBC DSCR_ADDR+0x08 Source Address Member MBR_SA DSCR_ADDR+0x0C Destination Address Member MBR_DA DSCR_ADDR+0x10 Configuration Member MBR_CFG DSCR_ADDR+0x14 Block Control Member MBR_BC DSCR_ADDR+0x18 Data Stride Member MBR_DS DSCR_ADDR+0x1C Source Microblock Stride Member MBR_SUS DSCR_ADDR+0x20 Destination Microblock Stride Member MBR_DUS

36.6.2 Descriptor Structure Members Description

36.6.2.1 Descriptor Structure Microblock Control Member

Name: MBR_UBC Property: Read-only Bit 31 30 29 28 27 26 25 24 NVIEW[1:0] NDEN NSEN NDE Access R R R R R Reset Bit 23 22 21 20 19 18 17 16 UBLEN[23:16] Access R R R R R R R R Reset Bit 15 14 13 12 11 10 9 8 UBLEN[15:8] Access R R R R R R R R Reset Bit 7 6 5 4 3 2 1 0 UBLEN[7:0] Access R R R R R R R R Reset Bits 28:27 – NVIEW[1:0] Next Descriptor View Value Name Description

0 NDV0 Next Descriptor View 0

1 NDV1 Next Descriptor View 1

2 NDV2 Next Descriptor View 2

3 NDV3 Next Descriptor View 3

Bit 26 – NDEN Next Descriptor Destination Update Value Description 0 Destination parameters remain unchanged. 1 Destination parameters are updated when the descriptor is retrieved. Bit 25 – NSEN Next Descriptor Source Update Value Description 0 Source parameters remain unchanged. 1 Source parameters are updated when the descriptor is retrieved. Bit 24 – NDE Next Descriptor Enable Value Description 0 Descriptor fetch is disabled. 1 Descriptor fetch is enabled. Bits 23:0 – UBLEN[23:0] Microblock Length This field indicates the number of data in the microblock. The microblock contains UBLEN data. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 450

36.7 XDMAC Maintenance Software Operations

36.7.1 Disabling a Channel

A disable channel request occurs when a write operation is performed in the XDMAC_GD register. If the channel is source peripheral synchronized (bit XDMAC_CCx.TYPE is set and bit XDMAC_CCx.DSYNC is cleared), then pending bytes (bytes located in the FIFO) are written to memory and bit XDMAC_CISx.DIS is set. If the channel is not source peripheral synchronized, the current channel transaction (read or write) is terminated and XDMAC_CISx.DIS is set. XDMAC_GS.STx is cleared by hardware when the current transfer is completed. The channel is no longer active and can be reused.

36.7.2 Suspending a Channel

36.7.3 Flushing a Channel

A FIFO flush command is issued by writing to the XDMAC_SWF register. The content of the FIFO is written to memory. XDMAC_CISx.FIS (End of Flush Interrupt Status bit) is set when the last byte is successfully transferred to memory. The channel is not disabled. The flush operation is not blocking, meaning that read operation can be scheduled during the flush write operation. The flush operation is only relevant for peripheral to memory transfer where pending peripheral bytes are buffered into the channel FIFO.

36.7.4 Maintenance Operation Priority

36.7.4.1 Disable Operation Priority

When a disable request occurs on a suspended channel, the XDMAC_GWS.WSx (Channel x Write Suspend bit) is cleared. If the transfer is source peripheral synchronized, the pending bytes are drained to memory. The bit XDMAC_CISx.DIS is set.
When a disable request follows a flush request, if the flush last transaction is not yet scheduled, the flush request is discarded and the disable procedure is applied. Bit XDMAC_CISx.FIS is not set. Bit XDMAC_CISx.DIS is set when the disable request is completed. If the flush request transaction is already scheduled, the XDMAC_CISx.FIS is set. XDMAC_CISx.DIS is also set when the disable request is completed.

36.7.4.2 Flush Operation Priority

When a flush request occurs on a suspended channel, if there are pending bytes in the FIFO, they are written out to memory, XDMAC_CISx.FIS is set. If the FIFO is empty, XDMAC_CISx.FIS is also set.
If the flush operation is performed after a disable request, the flush command is ignored. XDMAC_CISx.FIS is not set.

36.7.4.3 Suspend Operation Priority

If the suspend operation is performed after a disable request, the write suspend operation is ignored.

36.8 XDMAC Software Requirements

Write operations to channel registers are not be performed in an active channel after the channel is enabled. If any channel parameters must be reprogrammed, this can only be done after disabling the XDMAC channel.
XDMAC_CSAx and XDMAC_CDAx channel registers are to be programmed with a byte, half-word or word aligned address depending on the Channel x Data Width field (DWIDTH) of the XDMAC Channel x Configuration Register. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 451

When XDMAC_CC.INITD is set to 0, XDMAC_CUBC.UBLEN and XDMAC_CNDA.NDA field values are unreliable when the descriptor is being updated. The following procedure applies to get the buffer descriptor identifier and the residual bytes: Read XDMAC_CNDAx.NDA(nda0) Read XDMAC_CCx.INITD(initd0) Read XDMAC_CCx.INITD(initd0) Read XDMAC_CUBCx.UBLEN(ublen) Read XDMAC_CCx.INITD(initd1) Read XDMA_CNDAx.NDA(nda1) If (nda0 == nda1 && initd0 == 1 && initd1 == 1). Then the ublen is correct, the buffer id is nda. Else retry See the figure below. Figure 36-4. INITD Timing Diagram buffer0 buffer1 buffer0 buffer1 buffer0 XDMAC_CUBCx.UBLEN XDMAC_CCx.INITD XDMAC_CUBCx.UBLEN XDMAC_CNDAx.NDA 0 buffer1.ublen buffer0.ublen buffer1.nda buffer0.nda bu ffe r1. ub len 1 .n da SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 452

36.9 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 XDMAC_GTYPE 7:0 FIFO_SZ[2:0] NB_CH[4:0] 15:8 FIFO_SZ[10:3] 23:16 NB_REQ[6:0] 31:24 0x04 XDMAC_GCFG 7:0 CGDISIF CGDISFIFO CGDISPIPE CGDISREG 15:8 BXKBEN 23:16 31:24 0x08 XDMAC_GWAC 23:16 31:24 0x0C XDMAC_GIE 7:0 IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0 15:8 IE15 IE14 IE13 IE12 IE11 IE10 IE9 IE8 23:16 IE23 IE22 IE21 IE20 IE19 IE18 IE17 IE16 31:24 0x10 XDMAC_GID 7:0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 15:8 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 23:16 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 31:24 0x14 XDMAC_GIM 7:0 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0 15:8 IM15 IM14 IM13 IM12 IM11 IM10 IM9 IM8 23:16 IM23 IM22 IM21 IM20 IM19 IM18 IM17 IM16 31:24 0x18 XDMAC_GIS 7:0 IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0 15:8 IS15 IS14 IS13 IS12 IS11 IS10 IS9 IS8 23:16 IS23 IS22 IS21 IS20 IS19 IS18 IS17 IS16 31:24 0x1C XDMAC_GE 7:0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 15:8 EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 23:16 EN23 EN22 EN21 EN20 EN19 EN18 EN17 EN16 31:24 0x20 XDMAC_GD 7:0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 15:8 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 23:16 DI23 DI22 DI21 DI20 DI19 DI18 DI17 DI16 31:24 0x24 XDMAC_GS 7:0 ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0 15:8 ST15 ST14 ST13 ST12 ST11 ST10 ST9 ST8 23:16 ST23 ST22 ST21 ST20 ST19 ST18 ST17 ST16 31:24 0x28 XDMAC_GRS 7:0 RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 15:8 RS15 RS14 RS13 RS12 RS11 RS10 RS9 RS8 23:16 RS23 RS22 RS21 RS20 RS19 RS18 RS17 RS16 31:24 0x2C XDMAC_GWS 7:0 WS7 WS6 WS5 WS4 WS3 WS2 WS1 WS0 15:8 WS15 WS14 WS13 WS12 WS11 WS10 WS9 WS8 23:16 WS23 WS22 WS21 WS20 WS19 WS18 WS17 WS16 31:24 0x30 XDMAC_GRWS 7:0 RWS7 RWS6 RWS5 RWS4 RWS3 RWS2 RWS1 RWS0 15:8 RWS15 RWS14 RWS13 RWS12 RWS11 RWS10 RWS9 RWS8 23:16 RWS23 RWS22 RWS21 RWS20 RWS19 RWS18 RWS17 RWS16 31:24 0x34 XDMAC_GRWR 7:0 RWR7 RWR6 RWR5 RWR4 RWR3 RWR2 RWR1 RWR0 15:8 RWR15 RWR14 RWR13 RWR12 RWR11 RWR10 RWR9 RWR8 23:16 RWR23 RWR22 RWR21 RWR20 RWR19 RWR18 RWR17 RWR16 31:24 SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 453

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x38 XDMAC_GSWR 7:0 SWREQ7 SWREQ6 SWREQ5 SWREQ4 SWREQ3 SWREQ2 SWREQ1 SWREQ0 15:8 SWREQ15 SWREQ14 SWREQ13 SWREQ12 SWREQ11 SWREQ10 SWREQ9 SWREQ8 23:16 SWREQ23 SWREQ22 SWREQ21 SWREQ20 SWREQ19 SWREQ18 SWREQ17 SWREQ16 31:24 0x3C XDMAC_GSWS 7:0 SWRS7 SWRS6 SWRS5 SWRS4 SWRS3 SWRS2 SWRS1 SWRS0 15:8 SWRS15 SWRS14 SWRS13 SWRS12 SWRS11 SWRS10 SWRS9 SWRS8 23:16 SWRS23 SWRS22 SWRS21 SWRS20 SWRS19 SWRS18 SWRS17 SWRS16 31:24 0x40 XDMAC_GSWF 7:0 SWF7 SWF6 SWF5 SWF4 SWF3 SWF2 SWF1 SWF0 15:8 SWF15 SWF14 SWF13 SWF12 SWF11 SWF10 SWF9 SWF8 23:16 SWF23 SWF22 SWF21 SWF20 SWF19 SWF18 SWF17 SWF16 31:24 0x44 ... 0x4F Reserved 0x50 XDMAC_CIE0 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x54 XDMAC_CID0 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x58 XDMAC_CIM0 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x5C XDMAC_CIS0 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x60 XDMAC_CSA0 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x64 XDMAC_CDA0 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x68 XDMAC_CNDA0 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x6C XDMAC_CNDC0 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x70 XDMAC_CUBC0 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x74 XDMAC_CBC0 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x78 XDMAC_CC0 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 454

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x7C XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x80 XDMAC_CSUS0 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x84 XDMAC_CDUS0 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x88 ... 0x8F Reserved 0x90 XDMAC_CIE1 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x94 XDMAC_CID1 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x98 XDMAC_CIM1 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x9C XDMAC_CIS1 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0xA0 XDMAC_CSA1 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0xA4 XDMAC_CDA1 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0xA8 XDMAC_CNDA1 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0xAC XDMAC_CNDC1 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0xB0 XDMAC_CUBC1 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0xB4 XDMAC_CBC1 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0xB8 XDMAC_CC1 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 455

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0xBC XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0xC0 XDMAC_CSUS1 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0xC4 XDMAC_CDUS1 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0xC8 ... 0xCF Reserved 0xD0 XDMAC_CIE2 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0xD4 XDMAC_CID2 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0xD8 XDMAC_CIM2 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0xDC XDMAC_CIS2 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0xE0 XDMAC_CSA2 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0xE4 XDMAC_CDA2 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0xE8 XDMAC_CNDA2 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0xEC XDMAC_CNDC2 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0xF0 XDMAC_CUBC2 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0xF4 XDMAC_CBC2 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0xF8 XDMAC_CC2 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 456

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0xFC XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x0100 XDMAC_CSUS2 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x0104 XDMAC_CDUS2 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x0108 ... 0x010F Reserved 0x0110 XDMAC_CIE3 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x0114 XDMAC_CID3 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x0118 XDMAC_CIM3 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x011C XDMAC_CIS3 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x0120 XDMAC_CSA3 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x0124 XDMAC_CDA3 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x0128 XDMAC_CNDA3 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x012C XDMAC_CNDC3 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x0130 XDMAC_CUBC3 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x0134 XDMAC_CBC3 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x0138 XDMAC_CC3 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 457

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x013C XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x0140 XDMAC_CSUS3 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x0144 XDMAC_CDUS3 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x0148 ... 0x014F Reserved 0x0150 XDMAC_CIE4 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x0154 XDMAC_CID4 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x0158 XDMAC_CIM4 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x015C XDMAC_CIS4 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x0160 XDMAC_CSA4 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x0164 XDMAC_CDA4 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x0168 XDMAC_CNDA4 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x016C XDMAC_CNDC4 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x0170 XDMAC_CUBC4 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x0174 XDMAC_CBC4 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x0178 XDMAC_CC4 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 458

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x017C XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x0180 XDMAC_CSUS4 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x0184 XDMAC_CDUS4 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x0188 ... 0x018F Reserved 0x0190 XDMAC_CIE5 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x0194 XDMAC_CID5 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x0198 XDMAC_CIM5 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x019C XDMAC_CIS5 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x01A0 XDMAC_CSA5 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x01A4 XDMAC_CDA5 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x01A8 XDMAC_CNDA5 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x01AC XDMAC_CNDC5 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x01B0 XDMAC_CUBC5 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x01B4 XDMAC_CBC5 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x01B8 XDMAC_CC5 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 459

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x01BC XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x01C0 XDMAC_CSUS5 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x01C4 XDMAC_CDUS5 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x01C8 ... 0x01CF Reserved 0x01D0 XDMAC_CIE6 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x01D4 XDMAC_CID6 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x01D8 XDMAC_CIM6 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x01DC XDMAC_CIS6 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x01E0 XDMAC_CSA6 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x01E4 XDMAC_CDA6 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x01E8 XDMAC_CNDA6 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x01EC XDMAC_CNDC6 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x01F0 XDMAC_CUBC6 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x01F4 XDMAC_CBC6 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x01F8 XDMAC_CC6 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 460

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x01FC XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x0200 XDMAC_CSUS6 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x0204 XDMAC_CDUS6 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x0208 ... 0x020F Reserved 0x0210 XDMAC_CIE7 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x0214 XDMAC_CID7 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x0218 XDMAC_CIM7 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x021C XDMAC_CIS7 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x0220 XDMAC_CSA7 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x0224 XDMAC_CDA7 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x0228 XDMAC_CNDA7 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x022C XDMAC_CNDC7 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x0230 XDMAC_CUBC7 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x0234 XDMAC_CBC7 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x0238 XDMAC_CC7 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 461

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x023C XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x0240 XDMAC_CSUS7 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x0244 XDMAC_CDUS7 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x0248 ... 0x024F Reserved 0x0250 XDMAC_CIE8 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x0254 XDMAC_CID8 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x0258 XDMAC_CIM8 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x025C XDMAC_CIS8 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x0260 XDMAC_CSA8 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x0264 XDMAC_CDA8 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x0268 XDMAC_CNDA8 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x026C XDMAC_CNDC8 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x0270 XDMAC_CUBC8 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x0274 XDMAC_CBC8 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x0278 XDMAC_CC8 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 462

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x027C XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x0280 XDMAC_CSUS8 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x0284 XDMAC_CDUS8 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x0288 ... 0x028F Reserved 0x0290 XDMAC_CIE9 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x0294 XDMAC_CID9 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x0298 XDMAC_CIM9 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x029C XDMAC_CIS9 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x02A0 XDMAC_CSA9 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x02A4 XDMAC_CDA9 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x02A8 XDMAC_CNDA9 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x02AC XDMAC_CNDC9 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x02B0 XDMAC_CUBC9 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x02B4 XDMAC_CBC9 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x02B8 XDMAC_CC9 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 463

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x02BC XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x02C0 XDMAC_CSUS9 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x02C4 XDMAC_CDUS9 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x02C8 ... 0x02CF Reserved 0x02D0 XDMAC_CIE10 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x02D4 XDMAC_CID10 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x02D8 XDMAC_CIM10 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x02DC XDMAC_CIS10 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x02E0 XDMAC_CSA10 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x02E4 XDMAC_CDA10 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x02E8 XDMAC_CNDA10 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x02EC XDMAC_CNDC10 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x02F0 XDMAC_CUBC10 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x02F4 XDMAC_CBC10 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x02F8 XDMAC_CC10 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 464

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x02FC XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x0300 XDMAC_CSUS10 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x0304 XDMAC_CDUS10 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x0308 ... 0x030F Reserved 0x0310 XDMAC_CIE11 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x0314 XDMAC_CID11 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x0318 XDMAC_CIM11 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x031C XDMAC_CIS11 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x0320 XDMAC_CSA11 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x0324 XDMAC_CDA11 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x0328 XDMAC_CNDA11 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x032C XDMAC_CNDC11 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x0330 XDMAC_CUBC11 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x0334 XDMAC_CBC11 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x0338 XDMAC_CC11 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 465

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x033C XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x0340 XDMAC_CSUS11 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x0344 XDMAC_CDUS11 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x0348 ... 0x034F Reserved 0x0350 XDMAC_CIE12 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x0354 XDMAC_CID12 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x0358 XDMAC_CIM12 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x035C XDMAC_CIS12 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x0360 XDMAC_CSA12 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x0364 XDMAC_CDA12 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x0368 XDMAC_CNDA12 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x036C XDMAC_CNDC12 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x0370 XDMAC_CUBC12 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x0374 XDMAC_CBC12 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x0378 XDMAC_CC12 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 466

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x037C XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x0380 XDMAC_CSUS12 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x0384 XDMAC_CDUS12 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x0388 ... 0x038F Reserved 0x0390 XDMAC_CIE13 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x0394 XDMAC_CID13 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x0398 XDMAC_CIM13 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x039C XDMAC_CIS13 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x03A0 XDMAC_CSA13 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x03A4 XDMAC_CDA13 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x03A8 XDMAC_CNDA13 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x03AC XDMAC_CNDC13 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x03B0 XDMAC_CUBC13 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x03B4 XDMAC_CBC13 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x03B8 XDMAC_CC13 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 467

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x03BC XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x03C0 XDMAC_CSUS13 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x03C4 XDMAC_CDUS13 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x03C8 ... 0x03CF Reserved 0x03D0 XDMAC_CIE14 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x03D4 XDMAC_CID14 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x03D8 XDMAC_CIM14 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x03DC XDMAC_CIS14 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x03E0 XDMAC_CSA14 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x03E4 XDMAC_CDA14 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x03E8 XDMAC_CNDA14 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x03EC XDMAC_CNDC14 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x03F0 XDMAC_CUBC14 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x03F4 XDMAC_CBC14 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x03F8 XDMAC_CC14 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 468

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x03FC XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x0400 XDMAC_CSUS14 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x0404 XDMAC_CDUS14 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x0408 ... 0x040F Reserved 0x0410 XDMAC_CIE15 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x0414 XDMAC_CID15 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x0418 XDMAC_CIM15 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x041C XDMAC_CIS15 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x0420 XDMAC_CSA15 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x0424 XDMAC_CDA15 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x0428 XDMAC_CNDA15 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x042C XDMAC_CNDC15 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x0430 XDMAC_CUBC15 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x0434 XDMAC_CBC15 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x0438 XDMAC_CC15 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 469

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x043C XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x0440 XDMAC_CSUS15 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x0444 XDMAC_CDUS15 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x0448 ... 0x044F Reserved 0x0450 XDMAC_CIE16 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x0454 XDMAC_CID16 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x0458 XDMAC_CIM16 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x045C XDMAC_CIS16 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x0460 XDMAC_CSA16 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x0464 XDMAC_CDA16 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x0468 XDMAC_CNDA16 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x046C XDMAC_CNDC16 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x0470 XDMAC_CUBC16 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x0474 XDMAC_CBC16 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x0478 XDMAC_CC16 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 470

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x047C XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x0480 XDMAC_CSUS16 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x0484 XDMAC_CDUS16 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x0488 ... 0x048F Reserved 0x0490 XDMAC_CIE17 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x0494 XDMAC_CID17 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x0498 XDMAC_CIM17 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x049C XDMAC_CIS17 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x04A0 XDMAC_CSA17 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x04A4 XDMAC_CDA17 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x04A8 XDMAC_CNDA17 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x04AC XDMAC_CNDC17 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x04B0 XDMAC_CUBC17 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x04B4 XDMAC_CBC17 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x04B8 XDMAC_CC17 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 471

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x04BC XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x04C0 XDMAC_CSUS17 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x04C4 XDMAC_CDUS17 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x04C8 ... 0x04CF Reserved 0x04D0 XDMAC_CIE18 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x04D4 XDMAC_CID18 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x04D8 XDMAC_CIM18 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x04DC XDMAC_CIS18 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x04E0 XDMAC_CSA18 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x04E4 XDMAC_CDA18 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x04E8 XDMAC_CNDA18 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x04EC XDMAC_CNDC18 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x04F0 XDMAC_CUBC18 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x04F4 XDMAC_CBC18 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x04F8 XDMAC_CC18 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 472

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x04FC XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x0500 XDMAC_CSUS18 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x0504 XDMAC_CDUS18 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x0508 ... 0x050F Reserved 0x0510 XDMAC_CIE19 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x0514 XDMAC_CID19 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x0518 XDMAC_CIM19 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x051C XDMAC_CIS19 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x0520 XDMAC_CSA19 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x0524 XDMAC_CDA19 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x0528 XDMAC_CNDA19 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x052C XDMAC_CNDC19 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x0530 XDMAC_CUBC19 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x0534 XDMAC_CBC19 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x0538 XDMAC_CC19 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 473

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x053C XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x0540 XDMAC_CSUS19 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x0544 XDMAC_CDUS19 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x0548 ... 0x054F Reserved 0x0550 XDMAC_CIE20 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x0554 XDMAC_CID20 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x0558 XDMAC_CIM20 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x055C XDMAC_CIS20 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x0560 XDMAC_CSA20 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x0564 XDMAC_CDA20 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x0568 XDMAC_CNDA20 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x056C XDMAC_CNDC20 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x0570 XDMAC_CUBC20 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x0574 XDMAC_CBC20 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x0578 XDMAC_CC20 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 474

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x057C XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x0580 XDMAC_CSUS20 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x0584 XDMAC_CDUS20 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x0588 ... 0x058F Reserved 0x0590 XDMAC_CIE21 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x0594 XDMAC_CID21 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x0598 XDMAC_CIM21 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x059C XDMAC_CIS21 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x05A0 XDMAC_CSA21 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x05A4 XDMAC_CDA21 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x05A8 XDMAC_CNDA21 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x05AC XDMAC_CNDC21 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x05B0 XDMAC_CUBC21 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x05B4 XDMAC_CBC21 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x05B8 XDMAC_CC21 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 475

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x05BC XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x05C0 XDMAC_CSUS21 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x05C4 XDMAC_CDUS21 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x05C8 ... 0x05CF Reserved 0x05D0 XDMAC_CIE22 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x05D4 XDMAC_CID22 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x05D8 XDMAC_CIM22 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x05DC XDMAC_CIS22 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x05E0 XDMAC_CSA22 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x05E4 XDMAC_CDA22 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x05E8 XDMAC_CNDA22 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x05EC XDMAC_CNDC22 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x05F0 XDMAC_CUBC22 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x05F4 XDMAC_CBC22 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x05F8 XDMAC_CC22 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 476

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x05FC XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x0600 XDMAC_CSUS22 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x0604 XDMAC_CDUS22 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 0x0608 ... 0x060F Reserved 0x0610 XDMAC_CIE23 7:0 ROIE WBIE RBIE FIE DIE LIE BIE 15:8 23:16 31:24 0x0614 XDMAC_CID23 7:0 ROID WBEID RBEID FID DID LID BID 15:8 23:16 31:24 0x0618 XDMAC_CIM23 7:0 ROIM WBEIM RBEIM FIM DIM LIM BIM 15:8 23:16 31:24 0x061C XDMAC_CIS23 7:0 ROIS WBEIS RBEIS FIS DIS LIS BIS 15:8 23:16 31:24 0x0620 XDMAC_CSA23 7:0 SA[7:0] 15:8 SA[15:8] 23:16 SA[23:16] 31:24 SA[31:24] 0x0624 XDMAC_CDA23 7:0 DA[7:0] 15:8 DA[15:8] 23:16 DA[23:16] 31:24 DA[31:24] 0x0628 XDMAC_CNDA23 7:0 NDA[5:0] NDAIF 15:8 NDA[13:6] 23:16 NDA[21:14] 31:24 NDA[29:22] 0x062C XDMAC_CNDC23 7:0 NDVIEW[1:0] NDDUP NDSUP NDE 15:8 23:16 31:24 0x0630 XDMAC_CUBC23 7:0 UBLEN[7:0] 15:8 UBLEN[15:8] 23:16 UBLEN[23:16] 31:24 0x0634 XDMAC_CBC23 7:0 BLEN[7:0] 15:8 BLEN[11:8] 23:16 31:24 0x0638 XDMAC_CC23 7:0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE 15:8 DIF SIF DWIDTH[1:0] CSIZE[2:0] 23:16 WRIP RDIP INITD DAM[1:0] SAM[1:0] 31:24 PERID[6:0] SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 477

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x063C XDMAC_CDS_MSP 7:0 SDS_MSP[7:0] 15:8 SDS_MSP[15:8] 23:16 DDS_MSP[7:0] 31:24 DDS_MSP[15:8] 0x0640 XDMAC_CSUS23 7:0 SUBS[7:0] 15:8 SUBS[15:8] 23:16 SUBS[23:16] 31:24 0x0644 XDMAC_CDUS23 7:0 DUBS[7:0] 15:8 DUBS[15:8] 23:16 DUBS[23:16] 31:24 SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 478

36.9.1 XDMAC Global Type Register

Name: XDMAC_GTYPE Offset: 0x00 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 NB_REQ[6:0] Access R R R R R R R Reset 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 FIFO_SZ[10:3] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FIFO_SZ[2:0] NB_CH[4:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 22:16 – NB_REQ[6:0] Number of Peripheral Requests Minus One Bits 15:5 – FIFO_SZ[10:0] Number of Bytes Bits 4:0 – NB_CH[4:0] Number of Channels Minus One SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 479

36.9.2 XDMAC Global Configuration Register

Name: XDMAC_GCFG Offset: 0x04 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 BXKBEN Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 CGDISIF CGDISFIFO CGDISPIPE CGDISREG Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 8 – BXKBEN Boundary X Kilobyte Enable Value Description 0 The 1 Kbyte boundary is used. 1 The controller does not meet the AHB specification. Bit 3 – CGDISIF Bus Interface Clock Gating Disable Value Description 0 The automatic clock gating is enabled for the system bus interface. 1 The automatic clock gating is disabled for the system bus interface. Bit 2 – CGDISFIFO FIFO Clock Gating Disable Value Description 0 The automatic clock gating is enabled for the main FIFO. 1 The automatic clock gating is disabled for the main FIFO. Bit 1 – CGDISPIPE Pipeline Clock Gating Disable Value Description 0 The automatic clock gating is enabled for the main pipeline. 1 The automatic clock gating is disabled for the main pipeline. Bit 0 – CGDISREG Configuration Registers Clock Gating Disable Value Description 0 The automatic clock gating is enabled for the configuration registers. 1 The automatic clock gating is disabled for the configuration registers. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 480

36.9.3 XDMAC Global Weighted Arbiter Configuration Register

Name: XDMAC_GWAC Offset: 0x08 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 PW3[3:0] PW2[3:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PW1[3:0] PW0[3:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:12 – PW3[3:0] Pool Weight 3 This field indicates the weight of pool 3 in the arbitration scheme of the DMA scheduler. Bits 11:8 – PW2[3:0] Pool Weight 2 This field indicates the weight of pool 2 in the arbitration scheme of the DMA scheduler. Bits 7:4 – PW1[3:0] Pool Weight 1 This field indicates the weight of pool 1 in the arbitration scheme of the DMA scheduler. Bits 3:0 – PW0[3:0] Pool Weight 0 This field indicates the weight of pool 0 in the arbitration scheme of the DMA scheduler. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 481

36.9.4 XDMAC Global Interrupt Enable Register

Name: XDMAC_GIE Offset: 0x0C Reset: – Property: Write-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 IE23 IE22 IE21 IE20 IE19 IE18 IE17 IE16 Access W W W W W W W W Bit 15 14 13 12 11 10 9 8 IE15 IE14 IE13 IE12 IE11 IE10 IE9 IE8 Access W W W W W W W W Bit 7 6 5 4 3 2 1 0 IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0 Access W W W W W W W W Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – IE XDMAC Channel x Interrupt Enable Value Description 0 This bit has no effect. The Channel x Interrupt Mask bit (XDMAC_GIM.IMx) is not modified. 1 The corresponding mask bit is set. The XDMAC Channel x Interrupt Status register (XDMAC_GIS) can generate an interrupt. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 482

36.9.5 XDMAC Global Interrupt Disable Register

Name: XDMAC_GID Offset: 0x10 Reset: – Property: Write-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 Access W W W W W W W W Bit 15 14 13 12 11 10 9 8 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 Access W W W W W W W W Bit 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Access W W W W W W W W Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – ID XDMAC Channel x Interrupt Disable Value Description 0 This bit has no effect. The Channel x Interrupt Mask bit (XDMAC_GIM.IMx) is not modified. 1 The corresponding mask bit is reset. The Channel x Interrupt Status register interrupt (XDMAC_GIS) is masked. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 483

36.9.6 XDMAC Global Interrupt Mask Register

Name: XDMAC_GIM Offset: 0x14 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 IM23 IM22 IM21 IM20 IM19 IM18 IM17 IM16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 IM15 IM14 IM13 IM12 IM11 IM10 IM9 IM8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – IM XDMAC Channel x Interrupt Mask Value Description 0 This bit indicates that the channel x interrupt source is masked. The interrupt line is not raised. 1 This bit indicates that the channel x interrupt source is unmasked. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 484

36.9.7 XDMAC Global Interrupt Status Register

Name: XDMAC_GIS Offset: 0x18 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 IS23 IS22 IS21 IS20 IS19 IS18 IS17 IS16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 IS15 IS14 IS13 IS12 IS11 IS10 IS9 IS8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – IS XDMAC Channel x Interrupt Status Value Description

0 This bit indicates that either the interrupt source is masked at the channel level or no interrupt is

pending for channel x. 1 This bit indicates that an interrupt is pending for the channel x. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 485

36.9.8 XDMAC Global Channel Enable Register

Name: XDMAC_GE Offset: 0x1C Reset: – Property: Write-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 EN23 EN22 EN21 EN20 EN19 EN18 EN17 EN16 Access W W W W W W W W Bit 15 14 13 12 11 10 9 8 EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 Access W W W W W W W W Bit 7 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 Access W W W W W W W W Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – EN XDMAC Channel x Enable Value Description 0 This bit has no effect. 1 Enables channel n. This operation is permitted if the Channel x Status bit (XDMAC_GS.STx) was read as '0'. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 486

36.9.9 XDMAC Global Channel Disable Register

Name: XDMAC_GD Offset: 0x20 Reset: – Property: Write-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 DI23 DI22 DI21 DI20 DI19 DI18 DI17 DI16 Access W W W W W W W W Bit 15 14 13 12 11 10 9 8 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 Access W W W W W W W W Bit 7 6 5 4 3 2 1 0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 Access W W W W W W W W Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – DI XDMAC Channel x Disable Value Description 0 This bit has no effect. 1 Disables channel x. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 487

36.9.10 XDMAC Global Channel Status Register

Name: XDMAC_GS Offset: 0x24 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 ST23 ST22 ST21 ST20 ST19 ST18 ST17 ST16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ST15 ST14 ST13 ST12 ST11 ST10 ST9 ST8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – ST XDMAC Channel x Status Value Description 0 This bit indicates that the channel x is disabled. 1 This bit indicates that the channel x is enabled. If a channel disable request is issued, this bit remains asserted until pending transaction is completed. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 488

36.9.11 XDMAC Global Channel Read Suspend Register

Name: XDMAC_GRS Offset: 0x28 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 RS23 RS22 RS21 RS20 RS19 RS18 RS17 RS16 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 RS15 RS14 RS13 RS12 RS11 RS10 RS9 RS8 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – RSx XDMAC Channel x Read Suspend Value Description 0 The read channel is not suspended. 1 The source requests for channel n are no longer serviced by the system scheduler. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 489

36.9.12 XDMAC Global Channel Write Suspend Register

Name: XDMAC_GWS Offset: 0x2C Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 WS23 WS22 WS21 WS20 WS19 WS18 WS17 WS16 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 WS15 WS14 WS13 WS12 WS11 WS10 WS9 WS8 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WS7 WS6 WS5 WS4 WS3 WS2 WS1 WS0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – WSx XDMAC Channel x Write Suspend Value Description 0 The write channel is not suspended. 1 Destination requests are no longer routed to the scheduler. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 490

36.9.13 XDMAC Global Channel Read Write Suspend Register

Name: XDMAC_GRWS Offset: 0x30 Reset: – Property: Write-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 RWS23 RWS22 RWS21 RWS20 RWS19 RWS18 RWS17 RWS16 Access W W W W W W W W Bit 15 14 13 12 11 10 9 8 RWS15 RWS14 RWS13 RWS12 RWS11 RWS10 RWS9 RWS8 Access W W W W W W W W Bit 7 6 5 4 3 2 1 0 RWS7 RWS6 RWS5 RWS4 RWS3 RWS2 RWS1 RWS0 Access W W W W W W W W Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – RWSx XDMAC Channel x Read Write Suspend Value Description 0 No effect. 1 Read and write requests are suspended. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 491

36.9.14 XDMAC Global Channel Read Write Resume Register

Name: XDMAC_GRWR Offset: 0x34 Reset: – Property: Write-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 RWR23 RWR22 RWR21 RWR20 RWR19 RWR18 RWR17 RWR16 Access W W W W W W W W Bit 15 14 13 12 11 10 9 8 RWR15 RWR14 RWR13 RWR12 RWR11 RWR10 RWR9 RWR8 Access W W W W W W W W Bit 7 6 5 4 3 2 1 0 RWR7 RWR6 RWR5 RWR4 RWR3 RWR2 RWR1 RWR0 Access W W W W W W W W Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – RWRx XDMAC Channel x Read Write Resume Value Description 0 No effect. 1 Read and write requests are serviced. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 492

36.9.15 XDMAC Global Channel Software Request Register

Name: XDMAC_GSWR Offset: 0x38 Reset: – Property: Write-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 SWREQ23 SWREQ22 SWREQ21 SWREQ20 SWREQ19 SWREQ18 SWREQ17 SWREQ16 Access W W W W W W W W Bit 15 14 13 12 11 10 9 8 SWREQ15 SWREQ14 SWREQ13 SWREQ12 SWREQ11 SWREQ10 SWREQ9 SWREQ8 Access W W W W W W W W Bit 7 6 5 4 3 2 1 0 SWREQ7 SWREQ6 SWREQ5 SWREQ4 SWREQ3 SWREQ2 SWREQ1 SWREQ0 Access W W W W W W W W Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – SWREQ XDMAC Channel x Software Request Value Description 0 No effect. 1 Requests a DMA transfer for channel x. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 493

36.9.16 XDMAC Global Channel Software Request Status Register

Name: XDMAC_GSWS Offset: 0x3C Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 SWRS23 SWRS22 SWRS21 SWRS20 SWRS19 SWRS18 SWRS17 SWRS16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SWRS15 SWRS14 SWRS13 SWRS12 SWRS11 SWRS10 SWRS9 SWRS8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SWRS7 SWRS6 SWRS5 SWRS4 SWRS3 SWRS2 SWRS1 SWRS0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – SWRS XDMAC Channel x Software Request Status Value Description 0 Channel x source request is serviced. 1 Channel x source request is pending. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 494

36.9.17 XDMAC Global Channel Software Flush Request Register

Name: XDMAC_GSWF Offset: 0x40 Reset: – Property: Write-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 SWF23 SWF22 SWF21 SWF20 SWF19 SWF18 SWF17 SWF16 Access W W W W W W W W Bit 15 14 13 12 11 10 9 8 SWF15 SWF14 SWF13 SWF12 SWF11 SWF10 SWF9 SWF8 Access W W W W W W W W Bit 7 6 5 4 3 2 1 0 SWF7 SWF6 SWF5 SWF4 SWF3 SWF2 SWF1 SWF0 Access W W W W W W W W Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – SWFx XDMAC Channel x Software Flush Request Value Description 0 No effect. 1 Requests a DMA transfer flush for channel x. This bit is only relevant when the transfer is source peripheral synchronized. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 495

36.9.18 XDMAC Channel x Interrupt Enable Register [x=0..23] Name: XDMAC_CIE Offset: 0x50 + n*0x40 [n=0..23] Reset: – Property: Write-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ROIE WBIE RBIE FIE DIE LIE BIE Access W W W W W W W Bit 6 – ROIE Request Overflow Error Interrupt Enable Bit Value Description 0 No effect. 1 Enables request overflow error interrupt. Bit 5 – WBIE Write Bus Error Interrupt Enable Bit Value Description 0 No effect. 1 Enables write bus error interrupt. Bit 4 – RBIE Read Bus Error Interrupt Enable Bit Value Description 0 No effect. 1 Enables read bus error interrupt. Bit 3 – FIE End of Flush Interrupt Enable Bit Value Description 0 No effect. 1 Enables end of flush interrupt. Bit 2 – DIE End of Disable Interrupt Enable Bit Value Description 0 No effect. 1 Enables end of disable interrupt. Bit 1 – LIE End of Linked List Interrupt Enable Bit Value Description 0 No effect. 1 Enables end of linked list interrupt. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 496

Bit 0 – BIE End of Block Interrupt Enable Bit Value Description 0 No effect. 1 Enables end of block interrupt. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 497

36.9.19 XDMAC Channel x Interrupt Disable Register [x = 0..23] Name: XDMAC_CID Offset: 0x54 + n*0x40 [n=0..23] Reset: – Property: Write-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ROID WBEID RBEID FID DID LID BID Access W W W W W W W Bit 6 – ROID Request Overflow Error Interrupt Disable Bit Value Description 0 No effect. 1 Disables request overflow error interrupt. Bit 5 – WBEID Write Bus Error Interrupt Disable Bit Value Description 0 No effect. 1 Disables bus error interrupt. Bit 4 – RBEID Read Bus Error Interrupt Disable Bit Value Description 0 No effect. 1 Disables bus error interrupt. Bit 3 – FID End of Flush Interrupt Disable Bit Value Description 0 No effect. 1 Disables end of flush interrupt. Bit 2 – DID End of Disable Interrupt Disable Bit Value Description 0 No effect. 1 Disables end of disable interrupt. Bit 1 – LID End of Linked List Interrupt Disable Bit Value Description 0 No effect. 1 Disables end of linked list interrupt. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 498

Bit 0 – BID End of Block Interrupt Disable Bit Value Description 0 No effect. 1 Disables end of block interrupt. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 499

36.9.20 XDMAC Channel x Interrupt Mask Register [x = 0..23] Name: XDMAC_CIM Offset: 0x58 + n*0x40 [n=0..23] Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ROIM WBEIM RBEIM FIM DIM LIM BIM Access R R R R R R R Reset 0 0 0 0 0 0 0 Bit 6 – ROIM Request Overflow Error Interrupt Mask Bit Value Description 0 Request overflow interrupt is masked. 1 Request overflow interrupt is activated. Bit 5 – WBEIM Write Bus Error Interrupt Mask Bit Value Description 0 Bus error interrupt is masked. 1 Bus error interrupt is activated. Bit 4 – RBEIM Read Bus Error Interrupt Mask Bit Value Description 0 Bus error interrupt is masked. 1 Bus error interrupt is activated. Bit 3 – FIM End of Flush Interrupt Mask Bit Value Description 0 End of flush interrupt is masked. 1 End of flush interrupt is activated. Bit 2 – DIM End of Disable Interrupt Mask Bit Value Description 0 End of disable interrupt is masked. 1 End of disable interrupt is activated. Bit 1 – LIM End of Linked List Interrupt Mask Bit Value Description 0 End of linked list interrupt is masked. 1 End of linked list interrupt is activated. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 500

Bit 0 – BIM End of Block Interrupt Mask Bit Value Description 0 Block interrupt is masked. 1 Block interrupt is activated. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 501

36.9.21 XDMAC Channel x Interrupt Status Register [x = 0..23] Name: XDMAC_CIS Offset: 0x5C + n*0x40 [n=0..23] Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ROIS WBEIS RBEIS FIS DIS LIS BIS Access R R R R R R R Reset 0 0 0 0 0 0 0 Bit 6 – ROIS Request Overflow Error Interrupt Status Bit Value Description 0 Overflow condition has not occurred. 1 Overflow condition has occurred at least once. (This information is only relevant for peripheral synchronized transfers.) Bit 5 – WBEIS Write Bus Error Interrupt Status Bit Value Description 0 Write bus error condition has not occurred. 1 At least one bus error has been detected in a write access since the last read of the Status register. Bit 4 – RBEIS Read Bus Error Interrupt Status Bit Value Description 0 Read bus error condition has not occurred. 1 At least one bus error has been detected in a read access since the last read of the Status register. Bit 3 – FIS End of Flush Interrupt Status Bit Value Description 0 End of flush condition has not occurred. 1 End of flush condition has occurred since the last read of the Status register. Bit 2 – DIS End of Disable Interrupt Status Bit Value Description 0 End of disable condition has not occurred. 1 End of disable condition has occurred since the last read of the Status register. Bit 1 – LIS End of Linked List Interrupt Status Bit Value Description 0 End of linked list condition has not occurred. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 502

1 End of linked list condition has occurred since the last read of the Status register. Bit 0 – BIS End of Block Interrupt Status Bit Value Description 0 End of block interrupt has not occurred. 1 End of block interrupt has occurred since the last read of the Status register. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 503

36.9.22 XDMAC Channel x Source Address Register [x = 0..23] Name: XDMAC_CSA Offset: 0x60 + n*0x40 [n=0..23] Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 SA[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SA[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – SA[31:0] Channel x Source Address Program this register with the source address of the DMA transfer. A configuration error is generated when this address is not aligned with the transfer data size. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 504

36.9.23 XDMAC Channel x Destination Address Register [x = 0..23] Name: XDMAC_CDA Offset: 0x64 + n*0x40 [n=0..23] Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 DA[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DA[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DA[31:0] Channel x Destination Address Program this register with the destination address of the DMA transfer. A configuration error is generated when this address is not aligned with the transfer data size. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 505

36.9.24 XDMAC Channel x Next Descriptor Address Register [x = 0..23] Name: XDMAC_CNDA Offset: 0x68 + n*0x40 [n=0..23] Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 NDA[29:22] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 NDA[21:14] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 NDA[13:6] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NDA[5:0] NDAIF Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bits 31:2 – NDA[29:0] Channel x Next Descriptor Address The 30-bit width of the NDA field represents the next descriptor address range 31:2. The descriptor is word-aligned and the two least significant register bits 1:0 are ignored. Bit 0 – NDAIF Channel x Next Descriptor Interface Value Description 0 The channel descriptor is retrieved through system interface 0. 1 The channel descriptor is retrieved through system interface 1. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 506

36.9.25 XDMAC Channel x Next Descriptor Control Register [x = 0..23] Name: XDMAC_CNDC Offset: 0x6C + n*0x40 [n=0..23] Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 NDVIEW[1:0] NDDUP NDSUP NDE Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bits 4:3 – NDVIEW[1:0] Channel x Next Descriptor View Value Name Description Bit 2 – NDDUP Channel x Next Descriptor Destination Update 0 (DST_PARAMS_UNCHANGED): Destination parameters remain unchanged. 1 (DST_PARAMS_UPDATED): Destination parameters are updated when the descriptor is retrieved. Bit 1 – NDSUP Channel x Next Descriptor Source Update 0 (SRC_PARAMS_UNCHANGED): Source parameters remain unchanged. 1 (SRC_PARAMS_UPDATED): Source parameters are updated when the descriptor is retrieved. Bit 0 – NDE Channel x Next Descriptor Enable 0 (DSCR_FETCH_DIS): Descriptor fetch is disabled. 1 (DSCR_FETCH_EN): Descriptor fetch is enabled. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 507

36.9.26 XDMAC Channel x Microblock Control Register [x = 0..23] Name: XDMAC_CUBC Offset: 0x70 + n*0x40 [n=0..23] Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 UBLEN[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 UBLEN[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 UBLEN[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 23:0 – UBLEN[23:0] Channel x Microblock Length This field indicates the number of data in the microblock. The microblock contains UBLEN data. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 508

36.9.27 XDMAC Channel x Block Control Register [x = 0..23] Name: XDMAC_CBC Offset: 0x74 + n*0x40 [n=0..23] Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 BLEN[11:8] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BLEN[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 11:0 – BLEN[11:0] Channel x Block Length The length of the block is (BLEN+1) microblocks. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 509

36.9.28 XDMAC Channel x Configuration Register [x = 0..23] Name: XDMAC_CC Offset: 0x78 + n*0x40 [n=0..23] Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 PERID[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 WRIP RDIP INITD DAM[1:0] SAM[1:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIF SIF DWIDTH[1:0] CSIZE[2:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MEMSET SWREQ DSYNC MBSIZE[1:0] TYPE Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bits 30:24 – PERID[6:0] Channel x Peripheral Hardware Request Line Identifier This field contains the peripheral hardware request line identifier. PERID refers to identifiers defined in “DMA Controller Peripheral Connections”. Bit 23 – WRIP Write in Progress (this bit is read-only) 0 (DONE): No active write transaction on the bus. 1 (IN_PROGRESS): A write transaction is in progress. Bit 22 – RDIP Read in Progress (this bit is read-only) 0 (DONE): No active read transaction on the bus. 1 (IN_PROGRESS): A read transaction is in progress. Bit 21 – INITD Channel Initialization Done (this bit is read-only) 0 (IN_PROGRESS): Channel initialization is in progress. 1 (TERMINATED): Channel initialization is completed. Note: When set to 0, XDMAC_CUBC.UBLEN and XDMAC_CNDA.NDA field values are unreliable each time a descriptor is being updated. See 36.8 XDMAC Software Requirements. Bits 19:18 – DAM[1:0] Channel x Destination Addressing Mode Value Name Description 0 FIXED_AM The address remains unchanged. 1 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 2 UBS_AM The microblock stride is added at the microblock boundary.

3 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is

added at the data boundary. Bits 17:16 – SAM[1:0] Channel x Source Addressing Mode Value Name Description 0 FIXED_AM The address remains unchanged. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 510

1 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 2 UBS_AM The microblock stride is added at the microblock boundary.

3 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is

added at the data boundary. Bit 14 – DIF Channel x Destination Interface Identifier 0 (AHB_IF0): The data is written through system bus interface 0. 1 (AHB_IF1): The data is written though system bus interface 1. Bit 13 – SIF Channel x Source Interface Identifier 0 (AHB_IF0): The data is read through system bus interface 0. 1 (AHB_IF1): The data is read through system bus interface 1. Bits 12:11 – DWIDTH[1:0] Channel x Data Width Value Name Description

0 BYTE The data size is set to 8 bits

1 HALFWORD The data size is set to 16 bits

2 WORD The data size is set to 32 bits

Bits 10:8 – CSIZE[2:0] Channel x Chunk Size Value Name Description

0 CHK_1 1 data transferred

1 CHK_2 2 data transferred

2 CHK_4 4 data transferred

3 CHK_8 8 data transferred

4 CHK_16 16 data transferred

Bit 7 – MEMSET Channel x Fill Block of Memory 0 (NORMAL_MODE): Memset is not activated. 1 (HW_MODE): Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. Bit 6 – SWREQ Channel x Software Request Trigger 0 (HWR_CONNECTED): Hardware request line is connected to the peripheral request line. 1 (SWR_CONNECTED): Software request is connected to the peripheral request line. Bit 4 – DSYNC Channel x Synchronization 0 (PER2MEM): Peripheral-to-memory transfer. 1 (MEM2PER): Memory-to-peripheral transfer. Bits 2:1 – MBSIZE[1:0] Channel x Memory Burst Size Value Name Description 0 SINGLE The memory burst size is set to one. 1 FOUR The memory burst size is set to four. 2 EIGHT The memory burst size is set to eight. 3 SIXTEEN The memory burst size is set to sixteen. Bit 0 – TYPE Channel x Transfer Type 0 (MEM_TRAN): Self-triggered mode (memory-to-memory transfer). 1 (PER_TRAN): Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 511

36.9.29 XDMAC Channel x Data Stride Memory Set Pattern Register [x = 0..23] Name: XDMAC_CDS_MSP Offset: 0x7C + n*0x40 [n=0..23] Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 DDS_MSP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DDS_MSP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SDS_MSP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SDS_MSP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:16 – DDS_MSP[15:0] Channel x Destination Data Stride or Memory Set Pattern When XDMAC_CCx.MEMSET = 0, this field indicates the destination data stride. When XDMAC_CCx.MEMSET = 1, this field indicates the memory set pattern. Bits 15:0 – SDS_MSP[15:0] Channel x Source Data stride or Memory Set Pattern When XDMAC_CCx.MEMSET = 0, this field indicates the source data stride. When XDMAC_CCx.MEMSET = 1, this field indicates the memory set pattern. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 512

36.9.30 XDMAC Channel x Source Microblock Stride Register [x = 0..23] Name: XDMAC_CSUS Offset: 0x80 + n*0x40 [n=0..23] Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 SUBS[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SUBS[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SUBS[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 23:0 – SUBS[23:0] Channel x Source Microblock Stride Two’s complement microblock stride for channel x. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 513

36.9.31 XDMAC Channel x Destination Microblock Stride Register [x = 0..23] Name: XDMAC_CDUS Offset: 0x84 + n*0x40 [n=0..23] Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 DUBS[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DUBS[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DUBS[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 23:0 – DUBS[23:0] Channel x Destination Microblock Stride Two’s complement microblock stride for channel x. SAMV71Q21RT DMA Controller (XDMAC) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 514

Image Sensor Interface (ISI)

37.1 Description

The Image Sensor Interface (ISI) connects a CMOS-type image sensor to the processor and provides image capture in various formats. The ISI performs data conversion, if necessary, before the storage in memory through DMA. The ISI supports color CMOS image sensor and grayscale image sensors with a reduced set of functionalities. In Grayscale mode, the data stream is stored in memory without any processing and so is not compatible with the LCD controller. Internal FIFOs on the preview and codec paths are used to store the incoming data. The RGB output on the preview path is compatible with the LCD controller. This module outputs the data in RGB format (LCD compatible) and has scaling capabilities to make it compliant to the LCD display resolution (see the table RGB Format in Default Mode, RGB_CFG = 00, No Swap). Several input formats such as preprocessed RGB or YCbCr are supported through the data bus interface. The ISI supports two synchronization modes:

Hardware with ISI_VSYNC and ISI_HSYNC signals
International Telecommunication Union Recommendation ITU-R BT.656-4 Start-of-Active-Video (SAV) and End- of-Active-Video (EAV) synchronization sequence Using EAV/SAV for synchronization reduces the pin count (ISI_VSYNC, ISI_HSYNC not used). The polarity of the synchronization pulse is programmable to comply with the sensor signals. Table 37-1. I/O Description Signal Direction Description ISI_VSYNC In Vertical Synchronization ISI_HSYNC In Horizontal Synchronization ISI_DATA[11..0] In Sensor Pixel Data ISI_MCK Out Master Clock provided to the Image Sensor. Refer to “Clocks”. ISI_PCK In Pixel Clock provided by the Image Sensor Figure 37-1. ISI Connection Example Image Sensor Image Sensor Interface data[11..0] ISI_DATA[11..0] CLK ISI_MCK PCLK ISI_PCK VSYNC HSYNC ISI_VSYNC ISI_HSYNC SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 515

37.2 Embedded Characteristics

ITU-R BT. 601/656 8-bit Mode External Interface Support
Supports up to 12-bit Grayscale CMOS Sensors
Support for ITU-R BT.656-4 SAV and EAV Synchronization
Vertical and Horizontal Resolutions up to 2048 × 2048
Preview Path up to 640 × 480 in RGB Mode
Codec Path up to 2048 × 2048
16-byte FIFO on Codec Path
16-byte FIFO on Preview Path
Support for Packed Data Formatting for YCbCr 4:2:2 Formats
Preview Scaler to Generate Smaller Size image
Programmable Frame Capture Rate
VGA, QVGA, CIF, QCIF Formats Supported for LCD Preview
Custom Formats with Horizontal and Vertical Preview Size as Multiples of 16 Also Supported for LCD Preview

37.3 Block Diagram

Figure 37-2. ISI Block Diagram Timing Signals Interface CCIR-656 Embedded Timing Decoder(SAV/EAV) Pixel Sampling Module Clipping + Color Conversion YCC to RGB 2-D Image Scaler Pixel Formatter Rx Direct Display FIFO Core Video Arbiter Camera AHB Master Interface APB InterfaceCamera Interrupt Controller Configuration Registers Clipping + Color Conversion RGB to YCC Rx Direct Capture FIFO Scatter Mode Support Packed Formatter Frame Rate YCbCr 4:2:2 8:8:8 5:6:5RGB CMOS Sensor Pixel input up to 12 bits Hsync/Line enable Vsync/Frame enable CMOS Sensor Pixel Clock input Pixel Clock Domain AHB Clock Domain APB Clock DomainFrom Rx buffers Camera Interrupt Request Line codec_on AHB bus APB bus Preview path Codec path

37.4 Product Dependencies

37.4.1 I/O Lines

The pins used for interfacing the compliant external devices can be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the ISI pins to their peripheral functions.

37.4.2 Power Management

The ISI can be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the ISI clock.

37.4.3 Interrupt Sources

The ISI interface has an interrupt line connected to the interrupt controller. Handling the ISI interrupt requires programming the interrupt controller before configuring the ISI. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 516

37.5 Functional Description

The Image Sensor Interface (ISI) supports direct connection to the ITU-R BT. 601/656 8-bit mode compliant sensors and up to 12-bit grayscale sensors. It receives the image data stream from the image sensor on the 12-bit data bus. This module receives up to 12 bits for data, the horizontal and vertical synchronizations and the pixel clock. The reduced pin count alternative for synchronization is supported for sensors that embed SAV (start of active video) and EAV (end of active video) delimiters in the data stream. The Image Sensor Interface interrupt line is connected to the Advanced Interrupt Controller and can trigger an interrupt at the beginning of each frame and at the end of a DMA frame transfer. If the SAV/EAV synchronization is used, an interrupt can be triggered on each delimiter event. For 8-bit color sensors, the data stream received can be in several possible formats: YCbCr 4:2:2, RGB 8:8:8, RGB 5:6:5 and may be processed before the storage in memory. When the preview DMA channel is configured and enabled, the preview path is activated and an ‘RGB frame’ is moved to memory. The preview path frame rate is configured with the FRATE field of the ISI_CFG1 register. When the codec DMA channel is configured and enabled, the codec path is activated and a ‘YCbCr 4:2:2 frame’ is captured as soon as the ISI_CDC bit of the ISI Control Register (ISI_CR) is set. When the FULL bit of the ISI_CFG1 register is set, both preview DMA channel and codec DMA channel can operate simultaneously. When a zero is written to the FULL bit of the ISI_CFG1 register, a hardware scheduler checks the FRATE field. If its value is zero, a preview frame is skipped and a codec frame is moved to memory instead. If its value is other than zero, at least one free frame slot is available. The scheduler postpones the codec frame to that free available frame slot. The data stream may be sent on both preview path and codec path if the value of bit ISI_CDC in the ISI_CR is one. To optimize the bandwidth, the codec path should be enabled only when a capture is required. In Grayscale mode, the input data stream is stored in memory without any processing. The 12-bit data, which represent the grayscale level for the pixel, is stored in memory one or two pixels per word, depending on the GS_MODE bit in the ISI_CFG2 register. The codec datapath is not available when grayscale image is selected. A frame rate counter allows users to capture all frames or 1 out of every 2 to 8 frames.

37.5.1 Data Timing

37.5.1.1 VSYNC/HSYNC Data Timing

In the VSYNC/HSYNC synchronization, the valid data is captured with the active edge of the pixel clock (ISI_PCK), after SFD lines of vertical blanking and SLD pixel clock periods delay programmed in the ISI_CR. The data timing using horizontal and vertical synchronization are shown in the following figure. Figure 37-3. HSYNC and VSYNC Synchronization ISI_VSYNC ISI_HSYNC ISI_PCK Frame 1 line Y Cb Y Cr Y Cb Y Cr Y Cb Y CrISI_DATA[7..0]

37.5.1.2 SAV/EAV Data Timing

The ITU-RBT.656-4 standard defines the functional timing for an 8-bit wide interface. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 517

There are two timing reference signals, one at the beginning of each video data block SAV (0xFF000080) and one at the end of each video data block EAV (0xFF00009D). Only data sent between EAV and SAV is captured. Horizontal blanking and vertical blanking are ignored. Use of the SAV and EAV synchronization eliminates the ISI_VSYNC and ISI_HSYNC signals from the interface, thereby reducing the pin count. In order to retrieve both frame and line synchronization properly, at least one line of vertical blanking is mandatory. The data timing using EAV/SAV sequence synchronization are shown in the following figure. Figure 37-4. SAV and EAV Sequence Synchronization ISII_PCK Cr Y Cb Y Cr Y Y Cr Y Cb FF 00ISI_DATA[7..0] FF 00 00 80 Y Cb Y 00 9D SAV EAV Active Video

37.5.2 Data Ordering

The RGB color space format is required for viewing images on a display screen preview, and the YCbCr color space format is required for encoding. All the sensors do not output the YCbCr or RGB components in the same order. The ISI allows the user to program the same component order as the sensor, reducing software treatments to restore the right format. Table 37-2. Data Ordering in YCbCr Mode Mode Byte 0 Byte 1 Byte 2 Byte 3 Default Cb(i) Y(i) Cr(i) Y(i+1) Mode 1 Cr(i) Y(i) Cb(i) Y(i+1) Mode 2 Y(i) Cb(i) Y(i+1) Cr(i) Mode 3 Y(i) Cr(i) Y(i+1) Cb(i) Table 37-3. RGB Format in Default Mode, RGB_CFG = 00, No Swap Mode Byte D7 D6 D5 D4 D3 D2 D1 D0 RGB 8:8:8 Byte 0 R7(i) R6(i) R5(i) R4(i) R3(i) R2(i) R1(i) R0(i) Byte 1 G7(i) G6(i) G5(i) G4(i) G3(i) G2(i) G1(i) G0(i) Byte 2 B7(i) B6(i) B5(i) B4(i) B3(i) B2(i) B1(i) B0(i) Byte 3 R7(i+1) R6(i+1) R5(i+1) R4(i+1) R3(i+1) R2(i+1) R1(i+1) R0(i+1) RGB 5:6:5 Byte 0 R4(i) R3(i) R2(i) R1(i) R0(i) G5(i) G4(i) G3(i) Byte 1 G2(i) G1(i) G0(i) B4(i) B3(i) B2(i) B1(i) B0(i) Byte 2 R4(i+1) R3(i+1) R2(i+1) R1(i+1) R0(i+1) G5(i+1) G4(i+1) G3(i+1) Byte 3 G2(i+1) G1(i+1) G0(i+1) B4(i+1) B3(i+1) B2(i+1) B1(i+1) B0(i+1) Table 37-4. RGB Format, RGB_CFG = 10 (Mode 2), No Swap Mode Byte D7 D6 D5 D4 D3 D2 D1 D0 RGB 5:6:5 Byte 0 G2(i) G1(i) G0(i) R4(i) R3(i) R2(i) R1(i) R0(i) Byte 1 B4(i) B3(i) B2(i) B1(i) B0(i) G5(i) G4(i) G3(i) Byte 2 G2(i+1) G1(i+1) G0(i+1) R4(i+1) R3(i+1) R2(i+1) R1(i+1) R0(i+1) Byte 3 B4(i+1) B3(i+1) B2(i+1) B1(i+1) B0(i+1) G5(i+1) G4(i+1) G3(i+1) SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 518

Table 37-5. RGB Format in Default Mode, RGB_CFG = 00, Swap Activated Mode Byte D7 D6 D5 D4 D3 D2 D1 D0 RGB 8:8:8 Byte 0 R0(i) R1(i) R2(i) R3(i) R4(i) R5(i) R6(i) R7(i) Byte 1 G0(i) G1(i) G2(i) G3(i) G4(i) G5(i) G6(i) G7(i) Byte 2 B0(i) B1(i) B2(i) B3(i) B4(i) B5(i) B6(i) B7(i) Byte 3 R0(i+1) R1(i+1) R2(i+1) R3(i+1) R4(i+1) R5(i+1) R6(i+1) R7(i+1) RGB 5:6:5 Byte 0 G3(i) G4(i) G5(i) R0(i) R1(i) R2(i) R3(i) R4(i) Byte 1 B0(i) B1(i) B2(i) B3(i) B4(i) G0(i) G1(i) G2(i) Byte 2 G3(i+1) G4(i+1) G5(i+1) R0(i+1) R1(i+1) R2(i+1) R3(i+1) R4(i+1) Byte 3 B0(i+1) B1(i+1) B2(i+1) B3(i+1) B4(i+1) G0(i+1) G1(i+1) G2(i+1) The RGB 5:6:5 input format is processed to be displayed as RGB 5:6:5 format, compliant with the 16-bit mode of the LCD controller.

37.5.3 Clocks

The sensor master clock (ISI_MCK) can be generated either by the Advanced Power Management Controller (APMC) through a Programmable Clock output or by an external oscillator connected to the sensor. None of the sensors embed a power management controller, so providing the clock by the APMC is a simple and efficient way to control power consumption of the system. Care must be taken when programming the system clock. The ISI has two clock domains, the sensor master clock and the pixel clock provided by sensor. The two clock domains are not synchronized, but the sensor master clock must be faster than the pixel clock.

37.5.4 Preview Path

37.5.4.1 Scaling, Decimation (Subsampling)

This module resizes captured 8-bit color sensor images to fit the LCD display format. The resize module performs only downscaling. The same ratio is applied for both horizontal and vertical resize, then a fractional decimation algorithm is applied. The decimation factor is a multiple of 1/16; values 0 to 15 are forbidden. Table 37-6. Decimation Factor Decimation Value 0–15 16 17 18 19 ... 124 125 126 127 Table 37-7. Decimation and Scaler Offset Values OUTPUT INPUT 352 × 288 640 × 480 800 × 600 1280 × 1024 1600 × 1200 2048 × 1536 VGA 640 × 480 F — 16 20 32 40 51 QVGA 320 × 240 F 16 32 40 64 80 102 CIF 352 × 288 F 16 26 33 56 66 85 QCIF 176 × 144 F 32 53 66 113 133 170 SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 519

Example: Input 1280 × 1024 Output = 640 × 480 Hratio = 1280/640 = 2 Vratio = 1024/480 = 2.1333 The decimation factor is 2 so 32/16. Figure 37-5. Resize Examples 1280 1024 480 640 32/16 decimation 1280 1024 288 352 56/16 decimation

37.5.4.2 Color Space Conversion

This module converts YCrCb or YUV pixels to RGB color space. Clipping is performed to ensure that the samples value do not exceed the allowable range. The conversion matrix is defined below and is fully programmable: R G B C 0 0 C 1 C 0 − C 2 − C 3 C 0 C 4 0 Y − Y off C b − C boff C r − C roff Example of programmable value to convert YCrCb to RGB: R = 1.164 ⋅ Y − 16 + 1.596 ⋅ C r − 128 G = 1.164 ⋅ Y − 16 − 0.813 ⋅ C r − 128 − 0.392 ⋅ C b − 128 B = 1.164 ⋅ Y − 16 + 2.107 ⋅ C b − 128 An example of programmable value to convert from YUV to RGB: R = Y + 1.596 ⋅ V G = Y − 0.394 ⋅ U − 0.436 ⋅ V B = Y + 2.032 ⋅ U SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 520

37.5.4.3 Memory Interface

37.5.4.3.1 RGB Mode

The preview datapath contains a data formatter that converts 8:8:8 pixel to RGB 5:6:5 format compliant with the 16-bit format of the LCD controller. In general, when converting from a color channel with more bits to one with fewer bits, the formatter module discards the lower-order bits. For example, converting from RGB 8:8:8 to RGB 5:6:5, the formatter module discards the three LSBs from the red and blue channels, and two LSBs from the green channel. 37.5.4.3.2 12-bit Grayscale Mode ISI_DATA[11:0] is the physical interface to the ISI. These bits are sampled and written to memory. When 12-bit Grayscale mode is enabled, two memory formats are supported: ISI_CFG2.GS_MODE = 0: two pixels per word ISI_CFG2.GS_MODE = 1: one pixel per word The following tables illustrate the memory mapping for the two formats. Table 37-8. Grayscale Memory Mapping Configuration for 12-bit Data (ISI_CFG2.GS_MODE = 0: two pixels per word) 31 30 29 28 27 26 25 24 Pixel 0 [11:4] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Pixel 1 [11:4] 7 6 5 4 3 2 1 0 If ISI_CFG1.GRAYLE = 0, the pixels map as follows: If ISI_CFG1.GRAYLE=1, the pixels map as follows: Table 37-9. Grayscale Memory Mapping Configuration for 12-bit Data (ISI_CFG2.GS_MODE = 0: two pixels per word) 31 30 29 28 27 26 25 24 Pixel 1 [11:4] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Pixel 0 [11:4] 7 6 5 4 3 2 1 0 SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 521

Table 37-10. Grayscale Memory Mapping Configuration for 12-bit Data (ISI_CFG2.GS_MODE = 1: one pixel per word) 31 30 29 28 27 26 25 24 Pixel 0 [11:4] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 37.5.4.3.3 8-bit Grayscale Mode For 8-bit Grayscale mode, ISI_DATA[7:0] on the 12-bit data bus is the physical interface to the ISI. These bits are sampled and written to memory. To enable 8-bit Grayscale mode, configure ISI_CFG2 as follows:

Clear ISI_CFG2.GRAYSCALE.
Clear ISI_CFG2.RGB_SWAP.
Clear ISI_CFG2.COL_SPACE.
Configure the field ISI_CFG2.YCC_SWAP to value 0.
Configure the field ISI_CFG2.IM_VSIZE with the vertical resolution of the image minus 1.
Configure the field ISI_CFG2.IM_HSIZE with the horizontal resolution of the image divided by 2. The horizontal resolution must be a multiple of 2. The codec datapath is used to capture the 8-bit grayscale image. Use the following configuration:
Set ISI_DMA_C_CTRL.C_FETCH.
Configure ISI_DMA_C_DSCR.C_DSCR with the descriptor address.
Write a one to the bit ISI_DMA_CHER.C_CH_EN. Table 37-11. Memory Mapping for 8-bit Grayscale Mode 31 30 29 28 27 26 25 24 Pixel 3 23 22 21 20 19 18 17 16 Pixel 2 15 14 13 12 11 10 9 8 Pixel 1 7 6 5 4 3 2 1 0 Pixel 0

37.5.4.4 FIFO and DMA Features

Both preview and codec datapaths contain FIFOs. These asynchronous buffers are used to safely transfer formatted pixels from the pixel clock domain to the AHB clock domain. A video arbiter is used to manage FIFO thresholds and triggers a relevant DMA request through the AHB master interface. Thus, depending on the FIFO state, a specified length burst is asserted. Regarding AHB master interface, it supports Scatter DMA mode through linked SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 522

list operation. This mode of operation improves flexibility of image buffer location and allows the user to allocate two or more frame buffers. The destination frame buffers are defined by a series of Frame Buffer Descriptors (FBD). Each FBD controls the transfer of one entire frame and then optionally loads a further FBD to switch the DMA operation at another frame buffer address. The FBD is defined by a series of three words. The first word defines the current frame buffer address (named DMA_X_ADDR register), the second defines control information (named DMA_X_CTRL register) and the third defines the next descriptor address (named DMA_X_DSCR). DMA Transfer mode with linked list support is available for both codec and preview datapaths. The data to be transferred described by an FBD requires several burst accesses. In the following example, the use of two ping-pong frame buffers is described. Example: The first FBD, stored at address 0x00030000, defines the location of the first frame buffer. This address is programmed in the ISI user interface DMA_P_DSCR. To enable the descriptor fetch operation, the value 0x00000001 must be written to the DMA_P_CTRL register. LLI_0 and LLI_1 are the two descriptors of the linked list. Destination address: frame buffer ID0 0x02A000 (LLI_0.DMA_P_ADDR) Transfer 0 Control Information, fetch and writeback: 0x00000003 (LLI_0.DMA_P_CTRL) Next FBD address: 0x00030010 (LLI_0.DMA_P_DSCR) The second FBD, stored at address 0x00030010, defines the location of the second frame buffer. Destination address: frame buffer ID1 0x0003A000 (LLI_1.DMA_P_ADDR) Transfer 1 Control information fetch and writeback: 0x00000003 (LLI_1.DMA_P_CTRL) The third FBD address: 0x00030000, wrapping to first FBD (LLI_1.DMA_P_DSCR) Using this technique, several frame buffers can be configured through the linked list. The following figure illustrates a typical three-frame buffer application. Frame n is mapped to frame buffer 0, frame n+1 is mapped to frame buffer 1, frame n+2 is mapped to frame buffer 2 and further frames wrap. A codec request occurs, and the full-size 4:2:2 encoded frame is stored in a dedicated memory space. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 523

Figure 37-6. Three Frame Buffers Application and Memory Mapping frame n frame n+1 frame n+2 frame n-1 frame n+3 frame n+4 Frame Buffer 0 Frame Buffer 1 Frame Buffer 3 4:2:2 Image Full ROI ISI config space Codec Request Codec Done LCD Memory Space

37.5.5 Codec Path

37.5.5.1 Color Space Conversion

Depending on user selection, this module can be bypassed so that input YCrCb stream is directly connected to the format converter module. If the RGB input stream is selected, this module converts RGB to YCrCb color space with the formulas given below: Y C r C b C 0 C 1 C 2 C 3 − C 4 − C 5 − C 6 − C 7 C 8 R G B Y off Cr off Cb off An example of coefficients is given below: SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 524

Y = 0.257 ⋅ R + 0.504 ⋅ G + 0.098 ⋅ B + 16 C r = 0.439 ⋅ R − 0.368 ⋅ G − 0.071 ⋅ B + 128 C b = − 0.148 ⋅ R − 0.291 ⋅ G + 0.439 ⋅ B + 128

37.5.5.2 Memory Interface

Dedicated FIFOs are used to support packed memory mapping. YCrCb pixel components are sent in a single 32-bit word in a contiguous space (packed). Data is stored in the order of natural scan lines. Planar mode is not supported.

37.5.5.3 DMA Features

Like preview datapath, codec datapath DMA mode uses linked list operation. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 525

37.6 Register Summary

Note: Several parts of the ISI controller use the pixel clock provided by the image sensor (ISI_PCK). Thus the user must first program the image sensor to provide this clock (ISI_PCK) before programming the Image Sensor Controller. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 ISI_CFG1 7:0 CRC_SYNC EMB_SYNC GRAYLE PIXCLK_POL VSYNC_POL HSYNC_POL 15:8 THMASK[1:0] FULL DISCR FRATE[2:0] 23:16 SLD[7:0] 31:24 SFD[7:0] 0x04 ISI_CFG2 7:0 IM_VSIZE[7:0] 15:8 COL_SPACE RGB_SWAP GRAYSCALE RGB_MODE GS_MODE IM_VSIZE[10:8] 23:16 IM_HSIZE[7:0] 31:24 RGB_CFG[1:0] YCC_SWAP[1:0] IM_HSIZE[10:8] 0x08 ISI_PSIZE 7:0 PREV_VSIZE[7:0] 15:8 PREV_VSIZE[9:8] 23:16 PREV_HSIZE[7:0] 31:24 PREV_HSIZE[9:8] 0x0C ISI_PDECF 7:0 DEC_FACTOR[7:0] 15:8 23:16 31:24 0x10 ISI_Y2R_SET0 7:0 C0[7:0] 15:8 C1[7:0] 23:16 C2[7:0] 31:24 C3[7:0] 0x14 ISI_Y2R_SET1 7:0 C4[7:0] 15:8 Cboff Croff Yoff C4[8] 23:16 31:24 0x18 ISI_R2Y_SET0 7:0 C0[6:0] 15:8 C1[6:0] 23:16 C2[6:0] 31:24 Roff 0x1C ISI_R2Y_SET1 7:0 C3[6:0] 15:8 C4[6:0] 23:16 C5[6:0] 31:24 Goff 0x20 ISI_R2Y_SET2 7:0 C6[6:0] 15:8 C7[6:0] 23:16 C8[6:0] 31:24 Boff 0x24 ISI_CR 7:0 ISI_SRST ISI_DIS ISI_EN 15:8 ISI_CDC 23:16 31:24 0x28 ISI_SR 7:0 SRST DIS_DONE ENABLE 15:8 VSYNC CDC_PND 23:16 SIP CXFR_DONE PXFR_DONE 31:24 FR_OVR CRC_ERR C_OVR P_OVR 0x2C ISI_IER 7:0 SRST DIS_DONE 15:8 VSYNC 23:16 CXFR_DONE PXFR_DONE 31:24 FR_OVR CRC_ERR C_OVR P_OVR 0x30 ISI_IDR 7:0 SRST DIS_DONE 15:8 VSYNC 23:16 CXFR_DONE PXFR_DONE 31:24 FR_OVR CRC_ERR C_OVR P_OVR SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 526

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x34 ISI_IMR 7:0 SRST DIS_DONE 15:8 VSYNC 23:16 CXFR_DONE PXFR_DONE 31:24 FR_OVR CRC_ERR C_OVR P_OVR 0x38 ISI_DMA_CHER 7:0 C_CH_EN P_CH_EN 15:8 23:16 31:24 0x3C ISI_DMA_CHDR 7:0 C_CH_DIS P_CH_DIS 15:8 23:16 31:24 0x40 ISI_DMA_CHSR 7:0 C_CH_S P_CH_S 15:8 23:16 31:24 0x44 ISI_DMA_P_ADDR 7:0 P_ADDR[5:0] 15:8 P_ADDR[13:6] 23:16 P_ADDR[21:14] 31:24 P_ADDR[29:22] 0x48 ISI_DMA_P_CTRL 7:0 P_DONE P_IEN P_WB P_FETCH 15:8 23:16 31:24 0x4C ISI_DMA_P_DSCR 7:0 P_DSCR[5:0] 15:8 P_DSCR[13:6] 23:16 P_DSCR[21:14] 31:24 P_DSCR[29:22] 0x50 ISI_DMA_C_ADDR 7:0 C_ADDR[5:0] 15:8 C_ADDR[13:6] 23:16 C_ADDR[21:14] 31:24 C_ADDR[29:22] 0x54 ISI_DMA_C_CTRL 7:0 C_DONE C_IEN C_WB C_FETCH 15:8 23:16 31:24 0x58 ISI_DMA_C_DSCR 7:0 C_DSCR[5:0] 15:8 C_DSCR[13:6] 23:16 C_DSCR[21:14] 31:24 C_DSCR[29:22] 0x5C ... 0xE3 Reserved 0xE4 ISI_WPMR 7:0 WPEN 15:8 WPKEY[7:0] 23:16 WPKEY[15:8] 31:24 WPKEY[23:16] 0xE8 ISI_WPSR 7:0 WPVS 15:8 WPVSRC[7:0] 23:16 WPVSRC[15:8] 31:24 SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 527

37.6.1 ISI Configuration 1 Register

Name: ISI_CFG1 Offset: 0x00 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 SFD[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SLD[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 THMASK[1:0] FULL DISCR FRATE[2:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRC_SYNC EMB_SYNC GRAYLE PIXCLK_POL VSYNC_POL HSYNC_POL Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bits 31:24 – SFD[7:0] Start of Frame Delay SFD lines are skipped at the beginning of the frame. Bits 23:16 – SLD[7:0] Start of Line Delay SLD pixel clock periods to wait before the beginning of a line. Bits 14:13 – THMASK[1:0] Threshold Mask Value Name Description

0 BEATS_4 Only 4 beats AHB burst allowed

1 BEATS_8 Only 4 and 8 beats AHB burst allowed

2 BEATS_16 4, 8 and 16 beats AHB burst allowed

Bit 12 – FULL Full Mode is Allowed Value Description 0 The codec frame is transferred to memory when an available frame slot is detected. 1 Both preview and codec DMA channels are operating simultaneously. Bit 11 – DISCR Disable Codec Request Value Description 0 Codec datapath DMA interface requires a request to restart. 1 Codec datapath DMA automatically restarts. Bits 10:8 – FRATE[2:0] Frame Rate [0..7] Value Description 0 All the frames are captured, else one frame every FRATE + 1 is captured. Bit 7 – CRC_SYNC Embedded Synchronization Correction SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 528

0 No CRC correction is performed on embedded synchronization. 1 CRC correction is performed. If the correction is not possible, the current frame is discarded and the CRC_ERR bit is set in the ISI_SR. Bit 6 – EMB_SYNC Embedded Synchronization Value Description 0 Synchronization by HSYNC, VSYNC. 1 Synchronization by embedded synchronization sequence SAV/EAV. Bit 5 – GRAYLE Grayscale Little Endian Refer to Table 37-8 and Table 37-9 for details. Value Description 0 The two pixels are represented in big-endian format within a 32-bit register. 1 The two pixels are represented in little-endian format within a 32-bit register. Bit 4 – PIXCLK_POL Pixel Clock Polarity Value Description 0 Data is sampled on rising edge of pixel clock. 1 Data is sampled on falling edge of pixel clock. Bit 3 – VSYNC_POL Vertical Synchronization Polarity Value Description 0 VSYNC active high. 1 VSYNC active low. Bit 2 – HSYNC_POL Horizontal Synchronization Polarity Value Description 0 HSYNC active high. 1 HSYNC active low. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 529

37.6.2 ISI Configuration 2 Register

Name: ISI_CFG2 Offset: 0x04 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 RGB_CFG[1:0] YCC_SWAP[1:0] IM_HSIZE[10:8] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 IM_HSIZE[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COL_SPACE RGB_SWAP GRAYSCALE RGB_MODE GS_MODE IM_VSIZE[10:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 IM_VSIZE[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:30 – RGB_CFG[1:0] RGB Pixel Mapping Configuration Defines RGB pattern when RGB_MODE is set to 1. If RGB_MODE is set to RGB 8:8:8, then RGB_CFG = 0 implies RGB color sequence, else it implies BGR color sequence. Value Name Description

0 DEFAULT Byte 0 R/G(MSB)

Byte 1 G(LSB)/B Byte 2 R/G(MSB) Byte 3 G(LSB)/B

1 MODE1 Byte 0 B/G(MSB)

Byte 1 G(LSB)/R Byte 2 B/G(MSB) Byte 3 G(LSB)/R

2 MODE2 Byte 0 G(LSB)/R

Byte 1 B/G(MSB) Byte 2 G(LSB)/R Byte 3 B/G(MSB)

3 MODE3 Byte 0 G(LSB)/B

Bits 29:28 – YCC_SWAP[1:0] YCrCb Format Swap Mode Defines the YCC image data. Value Name Description

0 DEFAULT Byte 0 Cb(i)

Byte 1 Y(i) Byte 2 Cr(i) Byte 3 Y(i+1)

1 MODE1 Byte 0 Cr(i)

Byte 1 Y(i) Byte 2 Cb(i) Byte 3 Y(i+1)

2 MODE2 Byte 0 Y(i)

Byte 1 Cb(i) Byte 2 Y(i+1) Byte 3 Cr(i)

3 MODE3 Byte 0 Y(i)

Byte 1 Cr(i) Byte 2 Y(i+1) Byte 3 Cb(i) Bits 26:16 – IM_HSIZE[10:0] Horizontal Size of the Image Sensor [0..2047] If 8-bit Grayscale mode is enabled, IM_HSIZE = (Horizontal size/2) - 1. Else IM_HSIZE = Horizontal size - 1. Bit 15 – COL_SPACE Color Space for the Image Data Value Description 0 YCbCr. 1 RGB. Bit 14 – RGB_SWAP RGB Format Swap Mode The RGB_SWAP has no effect when Grayscale mode is enabled. Value Description 0 D7 → R7. 1 D0 → R7. Bit 13 – GRAYSCALE Grayscale Mode Format Enable Value Description 0 Grayscale mode is disabled. 1 Input image is assumed to be grayscale-coded. Bit 12 – RGB_MODE RGB Input Mode Value Description 0 RGB 8:8:8 24 bits. 1 RGB 5:6:5 16 bits. Bit 11 – GS_MODE Grayscale Pixel Format Mode Value Description 0 2 pixels per word. 1 1 pixel per word. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 531

Bits 10:0 – IM_VSIZE[10:0] Vertical Size of the Image Sensor [0..2047] IM_VSIZE = Vertical size - 1 SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 532

37.6.3 ISI Preview Size Register

Name: ISI_PSIZE Offset: 0x08 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 PREV_HSIZE[9:8] Access R/W R/W Reset 0 0 Bit 23 22 21 20 19 18 17 16 PREV_HSIZE[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 PREV_VSIZE[9:8] Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 PREV_VSIZE[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 25:16 – PREV_HSIZE[9:0] Horizontal Size for the Preview Path PREV_HSIZE = Horizontal Preview size - 1 (640 max only in RGB mode). Bits 9:0 – PREV_VSIZE[9:0] Vertical Size for the Preview Path PREV_VSIZE = Vertical Preview size - 1 (480 max only in RGB mode). SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 533

37.6.4 ISI Preview Decimation Factor Register

Name: ISI_PDECF Offset: 0x0C Reset: 0x00000010 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 DEC_FACTOR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 1 0 0 0 0 Bits 7:0 – DEC_FACTOR[7:0] Decimation Factor DEC_FACTOR is 8-bit width, range is from 16 to 255. Values from 0 to 16 do not perform any decimation. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 534

37.6.5 ISI Color Space Conversion YCrCb to RGB Set 0 Register

Name: ISI_Y2R_SET0 Offset: 0x10 Reset: 0x6832CC95 Property: Read/Write Bit 31 30 29 28 27 26 25 24 C3[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 1 0 1 0 0 0 Bit 23 22 21 20 19 18 17 16 C2[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 1 1 0 0 1 0 Bit 15 14 13 12 11 10 9 8 C1[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 0 0 1 1 0 0 Bit 7 6 5 4 3 2 1 0 C0[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 0 0 1 0 1 0 1 Bits 31:24 – C3[7:0] Color Space Conversion Matrix Coefficient C3 C3 element default step is 1/128, ranges from 0 to 1.9921875. Bits 23:16 – C2[7:0] Color Space Conversion Matrix Coefficient C2 C2 element default step is 1/128, ranges from 0 to 1.9921875. Bits 15:8 – C1[7:0] Color Space Conversion Matrix Coefficient C1 C1 element default step is 1/128, ranges from 0 to 1.9921875. Bits 7:0 – C0[7:0] Color Space Conversion Matrix Coefficient C0 C0 element default step is 1/128, ranges from 0 to 1.9921875. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 535

37.6.6 ISI Color Space Conversion YCrCb to RGB Set 1 Register

Name: ISI_Y2R_SET1 Offset: 0x14 Reset: 0x00007102 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Cboff Croff Yoff C4[8] Access R/W R/W R/W R/W Reset 1 1 1 1 Bit 7 6 5 4 3 2 1 0 C4[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 1 0 Bit 14 – Cboff Color Space Conversion Blue Chrominance Default Offset Value Description 0 No offset. 1 Offset = 16. Bit 13 – Croff Color Space Conversion Red Chrominance Default Offset Value Description 0 No offset. 1 Offset = 16. Bit 12 – Yoff Color Space Conversion Luminance Default Offset Value Description 0 No offset. 1 Offset = 128. Bits 8:0 – C4[8:0] Color Space Conversion Matrix Coefficient C4 C4 element default step is 1/128, ranges from 0 to 3.9921875. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 536

37.6.7 ISI Color Space Conversion RGB to YCrCb Set 0 Register

Name: ISI_R2Y_SET0 Offset: 0x18 Reset: 0x01324145 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Roff Access R/W Reset 1 Bit 23 22 21 20 19 18 17 16 C2[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 1 1 0 0 1 0 Bit 15 14 13 12 11 10 9 8 C1[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 1 0 0 0 0 0 1 Bit 7 6 5 4 3 2 1 0 C0[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 1 0 0 0 1 0 1 Bit 24 – Roff Color Space Conversion Red Component Offset Value Description

0 No offset

1 Offset = 16

Bits 22:16 – C2[6:0] Color Space Conversion Matrix Coefficient C2 C2 element default step is 1/512, from 0 to 0.2480468875. Bits 14:8 – C1[6:0] Color Space Conversion Matrix Coefficient C1 C1 element default step is 1/128, from 0 to 0.9921875. Bits 6:0 – C0[6:0] Color Space Conversion Matrix Coefficient C0 C0 element default step is 1/256, from 0 to 0.49609375. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 537

37.6.8 ISI Color Space Conversion RGB to YCrCb Set 1 Register

Name: ISI_R2Y_SET1 Offset: 0x1C Reset: 0x01245E38 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Goff Access R/W Reset 1 Bit 23 22 21 20 19 18 17 16 C5[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 1 0 0 1 0 0 Bit 15 14 13 12 11 10 9 8 C4[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 1 0 1 1 1 1 0 Bit 7 6 5 4 3 2 1 0 C3[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 1 1 1 0 0 0 Bit 24 – Goff Color Space Conversion Green Component Offset Value Description 0 No offset. 1 Offset = 128. Bits 22:16 – C5[6:0] Color Space Conversion Matrix Coefficient C5 C1 element default step is 1/512, ranges from 0 to 0.2480468875. Bits 14:8 – C4[6:0] Color Space Conversion Matrix Coefficient C4 C1 element default step is 1/256, ranges from 0 to 0.49609375. Bits 6:0 – C3[6:0] Color Space Conversion Matrix Coefficient C3 C0 element default step is 1/128, ranges from 0 to 0.9921875. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 538

37.6.9 ISI Color Space Conversion RGB to YCrCb Set 2 Register

Name: ISI_R2Y_SET2 Offset: 0x20 Reset: 0x01384A4B Property: Read/Write Bit 31 30 29 28 27 26 25 24 Boff Access R/W Reset 1 Bit 23 22 21 20 19 18 17 16 C8[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 1 1 1 0 0 0 Bit 15 14 13 12 11 10 9 8 C7[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 1 0 0 1 0 1 0 Bit 7 6 5 4 3 2 1 0 C6[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 1 0 0 1 0 1 1 Bit 24 – Boff Color Space Conversion Blue Component Offset Value Description 0 No offset. 1 Offset = 128. Bits 22:16 – C8[6:0] Color Space Conversion Matrix Coefficient C8 C8 element default step is 1/128, ranges from 0 to 0.9921875. Bits 14:8 – C7[6:0] Color Space Conversion Matrix Coefficient C7 C7 element default step is 1/256, ranges from 0 to 0.49609375. Bits 6:0 – C6[6:0] Color Space Conversion Matrix Coefficient C6 C6 element default step is 1/512, ranges from 0 to 0.2480468875. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 539

37.6.10 ISI Control Register

Name: ISI_CR Offset: 0x24 Reset: – Property: Write-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 ISI_CDC Access W Reset – Bit 7 6 5 4 3 2 1 0 ISI_SRST ISI_DIS ISI_EN Access W W W Reset – – – Bit 8 – ISI_CDC ISI Codec Request Write a one to this bit to enable the codec datapath and capture a full resolution frame. A new request cannot be taken into account while CDC_PND bit is active in the ISI_SR. Bit 2 – ISI_SRST ISI Software Reset Request Write a one to this bit to request a software reset of the module. Software must poll the SRST bit in the ISI_SR to verify that the software request command has terminated. Bit 1 – ISI_DIS ISI Module Disable Request Write a one to this bit to disable the module. If both ISI_EN and ISI_DIS are asserted at the same time, the disable request is not taken into account. Software must poll the DIS_DONE bit in the ISI_SR to verify that the command has successfully completed. Bit 0 – ISI_EN ISI Module Enable Request Write a one to this bit to enable the module. Software must poll the ENABLE bit in the ISI_SR to verify that the command has successfully completed. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 540

37.6.11 ISI Status Register

Name: ISI_SR Offset: 0x28 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 FR_OVR CRC_ERR C_OVR P_OVR Access R R R R Reset 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SIP CXFR_DONE PXFR_DONE Access R R R Reset 0 0 0 Bit 15 14 13 12 11 10 9 8 VSYNC CDC_PND Access R R Reset 0 0 Bit 7 6 5 4 3 2 1 0 SRST DIS_DONE ENABLE Access R R R Reset 0 0 0 Bit 27 – FR_OVR Frame Rate Overrun (cleared on read) Value Description

0 No frame overrun

1 Frame overrun. The current frame is being skipped because a vsync signal has been detected while flushing FIFOs since the last read of ISI_SR. Bit 26 – CRC_ERR CRC Synchronization Error (cleared on read) Value Description

0 No CRC error in the embedded synchronization frame (SAV/EAV)

1 Embedded Synchronization Correction is enabled (CRC_SYNC bit is set) in the ISI_CR and an error

has been detected and not corrected since the last read of ISI_SR. The frame is discarded and the ISI waits for a new one. Bit 25 – C_OVR Codec Datapath Overflow (cleared on read) Value Description

0 No overflow

1 An overrun condition has occurred in input FIFO on the codec path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO since the last read of ISI_SR. Bit 24 – P_OVR Preview Datapath Overflow (cleared on read) Value Description 1 An overrun condition has occurred in input FIFO on the preview path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO since the last read of ISI_SR. Bit 19 – SIP Synchronization in Progress When the status of the preview or codec DMA channel is modified, a minimum amount of time is required to perform the clock domain synchronization. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 541

0 The clock domain synchronization process is terminated. 1 This bit is set when the clock domain synchronization operation occurs. No modification of the channel status is allowed when this bit is set, to guarantee data integrity. Bit 17 – CXFR_DONE Codec DMA Transfer has Terminated (cleared on read) Value Description 0 Codec transfer done not detected. 1 Codec transfer done detected. When set, this bit indicates that the data transfer on the codec channel has completed since the last read of ISI_SR. Bit 16 – PXFR_DONE Preview DMA Transfer has Terminated (cleared on read) Value Description 0 Preview transfer done not detected. 1 Preview transfer done detected. When set, this bit indicates that the data transfer on the preview channel has completed since the last read of ISI_SR. Bit 10 – VSYNC Vertical Synchronization (cleared on read) Value Description 0 Indicates that the vertical synchronization has not been detected since the last read of the ISI_SR. 1 Indicates that a vertical synchronization has been detected since the last read of the ISI_SR. Bit 8 – CDC_PND Pending Codec Request Value Description

0 Indicates that no codec request is pending

1 Indicates that the request has been taken into account but cannot be serviced within the current frame. The operation is postponed to the next frame. Bit 2 – SRST Module Software Reset Request has Terminated (cleared on read) Value Description 0 Indicates that the request is not completed (if a request was issued). 1 Software reset request has completed. This flag is reset after a read operation. Bit 1 – DIS_DONE Module Disable Request has Terminated (cleared on read) Value Description 0 Indicates that the request is not completed (if a request was issued). 1 Disable request has completed. This flag is reset after a read operation. Bit 0 – ENABLE Module Enable Value Description 0 Module is disabled. 1 Module is enabled. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 542

37.6.12 ISI Interrupt Enable Register

Name: ISI_IER Offset: 0x2C Reset: – Property: Write-only Bit 31 30 29 28 27 26 25 24 FR_OVR CRC_ERR C_OVR P_OVR Access W W W W Reset – – – – Bit 23 22 21 20 19 18 17 16 CXFR_DONE PXFR_DONE Access W W Reset – – Bit 15 14 13 12 11 10 9 8 VSYNC Access W Reset – Bit 7 6 5 4 3 2 1 0 SRST DIS_DONE Access W W Reset – – Bit 27 – FR_OVR Frame Rate Overflow Interrupt Enable Value Description 0 No effect. 1 Enables the corresponding interrupt. Bit 26 – CRC_ERR Embedded Synchronization CRC Error Interrupt Enable Value Description 0 No effect. 1 Enables the corresponding interrupt. Bit 25 – C_OVR Codec Datapath Overflow Interrupt Enable Value Description 0 No effect. 1 Enables the corresponding interrupt. Bit 24 – P_OVR Preview Datapath Overflow Interrupt Enable Value Description 0 No effect. 1 Enables the corresponding interrupt. Bit 17 – CXFR_DONE Codec DMA Transfer Done Interrupt Enable Value Description 0 No effect. 1 Enables the corresponding interrupt. Bit 16 – PXFR_DONE Preview DMA Transfer Done Interrupt Enable Value Description 0 No effect. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 543

1 Enables the corresponding interrupt. Bit 10 – VSYNC Vertical Synchronization Interrupt Enable Value Description 0 No effect. 1 Enables the corresponding interrupt. Bit 2 – SRST Software Reset Interrupt Enable Value Description 0 No effect. 1 Enables the corresponding interrupt. Bit 1 – DIS_DONE Disable Done Interrupt Enable Value Description 0 No effect. 1 Enables the corresponding interrupt. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 544

37.6.13 ISI Interrupt Disable Register

Name: ISI_IDR Offset: 0x30 Reset: – Property: Write-only Bit 31 30 29 28 27 26 25 24 FR_OVR CRC_ERR C_OVR P_OVR Access W W W W Reset – – – – Bit 23 22 21 20 19 18 17 16 CXFR_DONE PXFR_DONE Access W W Reset – – Bit 15 14 13 12 11 10 9 8 VSYNC Access W Reset – Bit 7 6 5 4 3 2 1 0 SRST DIS_DONE Access W W Reset – – Bit 27 – FR_OVR Frame Rate Overflow Interrupt Disable Value Description 0 No effect. 1 Disables the corresponding interrupt. Bit 26 – CRC_ERR Embedded Synchronization CRC Error Interrupt Disable Value Description 0 No effect. 1 Disables the corresponding interrupt. Bit 25 – C_OVR Codec Datapath Overflow Interrupt Disable Value Description 0 No effect. 1 Disables the corresponding interrupt. Bit 24 – P_OVR Preview Datapath Overflow Interrupt Disable Value Description 0 No effect. 1 Disables the corresponding interrupt. Bit 17 – CXFR_DONE Codec DMA Transfer Done Interrupt Disable Value Description 0 No effect. 1 Disables the corresponding interrupt. Bit 16 – PXFR_DONE Preview DMA Transfer Done Interrupt Disable Value Description 0 No effect. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 545

1 Disables the corresponding interrupt. Bit 10 – VSYNC Vertical Synchronization Interrupt Disable Value Description 0 No effect. 1 Disables the corresponding interrupt. Bit 2 – SRST Software Reset Interrupt Disable Value Description 0 No effect. 1 Disables the corresponding interrupt. Bit 1 – DIS_DONE Disable Done Interrupt Disable Value Description 0 No effect. 1 Disables the corresponding interrupt. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 546

37.6.14 ISI Interrupt Mask Register

Name: ISI_IMR Offset: 0x34 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 FR_OVR CRC_ERR C_OVR P_OVR Access R R R R Reset 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CXFR_DONE PXFR_DONE Access R R Reset 0 0 Bit 15 14 13 12 11 10 9 8 VSYNC Access R Reset 0 Bit 7 6 5 4 3 2 1 0 SRST DIS_DONE Access R R Reset 0 0 Bit 27 – FR_OVR Frame Rate Overrun Value Description 0 The Frame Rate Overrun interrupt is disabled. 1 The Frame Rate Overrun is enabled. Bit 26 – CRC_ERR CRC Synchronization Error Value Description 0 The CRC Synchronization Error interrupt is disabled. 1 The CRC Synchronization Error interrupt is enabled. Bit 25 – C_OVR Codec FIFO Overflow Value Description 0 The Codec FIFO Overflow interrupt is disabled. 1 The Codec FIFO Overflow interrupt is enabled. Bit 24 – P_OVR Preview FIFO Overflow Value Description 0 The Preview FIFO Overflow interrupt is disabled. 1 The Preview FIFO Overflow interrupt is enabled. Bit 17 – CXFR_DONE Codec DMA Transfer Completed Value Description 0 The Codec DMA Transfer Completed interrupt is disabled. 1 The Codec DMA Transfer Completed interrupt is enabled. Bit 16 – PXFR_DONE Preview DMA Transfer Completed Value Description 0 The Preview DMA Transfer Completed interrupt is disabled. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 547

1 The Preview DMA Transfer Completed interrupt is enabled. Bit 10 – VSYNC Vertical Synchronization Value Description 0 The Vertical Synchronization interrupt is disabled. 1 The Vertical Synchronization interrupt is enabled. Bit 2 – SRST Software Reset Completed Value Description 0 The Software Reset Completed interrupt is disabled. 1 The Software Reset Completed interrupt is enabled. Bit 1 – DIS_DONE Module Disable Operation Completed Value Description 0 The Module Disable Operation Completed interrupt is disabled. 1 The Module Disable Operation Completed interrupt is enabled. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 548

37.6.15 DMA Channel Enable Register

Name: ISI_DMA_CHER Offset: 0x38 Reset: – Property: Write-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 C_CH_EN P_CH_EN Access W W Reset – – Bit 1 – C_CH_EN Codec Channel Enable Write a one to this bit to enable the codec DMA channel. Bit 0 – P_CH_EN Preview Channel Enable Write a one to this bit to enable the preview DMA channel. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 549

37.6.16 DMA Channel Disable Register

Name: ISI_DMA_CHDR Offset: 0x3C Reset: – Property: Write-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 C_CH_DIS P_CH_DIS Access W W Reset – – Bit 1 – C_CH_DIS Codec Channel Disable Request Value Description 0 No effect. 1 Disables the channel. Poll C_CH_S in DMA_CHSR to verify that the codec channel status has been successfully modified. Bit 0 – P_CH_DIS Preview Channel Disable Request Value Description 0 No effect. 1 Disables the channel. Poll P_CH_S in DMA_CHSR to verify that the preview channel status has been successfully modified. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 550

37.6.17 DMA Channel Status Register

Name: ISI_DMA_CHSR Offset: 0x40 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 C_CH_S P_CH_S Access R R Reset 0 0 Bit 1 – C_CH_S Code DMA Channel Status Value Description 0 Indicates that the Codec DMA channel is disabled. 1 Indicates that the Codec DMA channel is enabled. Bit 0 – P_CH_S Preview DMA Channel Status Value Description 0 Indicates that the Preview DMA channel is disabled. 1 Indicates that the Preview DMA channel is enabled. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 551

37.6.18 DMA Preview Base Address Register

Name: ISI_DMA_P_ADDR Offset: 0x44 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 P_ADDR[29:22] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 P_ADDR[21:14] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 P_ADDR[13:6] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 P_ADDR[5:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bits 31:2 – P_ADDR[29:0] Preview Image Base Address This address is word-aligned. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 552

37.6.19 DMA Preview Control Register

Name: ISI_DMA_P_CTRL Offset: 0x48 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 P_DONE P_IEN P_WB P_FETCH Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 3 – P_DONE Preview Transfer Done This bit is only updated in the memory. Value Description 0 The transfer related to this descriptor has not been performed. 1 The transfer related to this descriptor has completed. This bit is updated in memory at the end of the transfer, when writeback operation is enabled. Bit 2 – P_IEN Transfer Done Flag Control Value Description 0 Preview transfer done flag generation is enabled. 1 Preview transfer done flag generation is disabled. Bit 1 – P_WB Descriptor Writeback Control Bit Value Description 0 Preview channel writeback operation is disabled. 1 Preview channel writeback operation is enabled. Bit 0 – P_FETCH Descriptor Fetch Control Bit Value Description 0 Preview channel fetch operation is disabled. 1 Preview channel fetch operation is enabled. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 553

37.6.20 DMA Preview Descriptor Address Register

Name: ISI_DMA_P_DSCR Offset: 0x4C Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 P_DSCR[29:22] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 P_DSCR[21:14] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 P_DSCR[13:6] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 P_DSCR[5:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bits 31:2 – P_DSCR[29:0] Preview Descriptor Base Address This address is word-aligned. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 554

37.6.21 DMA Codec Base Address Register

Name: ISI_DMA_C_ADDR Offset: 0x50 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 C_ADDR[29:22] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 C_ADDR[21:14] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 C_ADDR[13:6] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 C_ADDR[5:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bits 31:2 – C_ADDR[29:0] Codec Image Base Address This address is word-aligned. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 555

37.6.22 DMA Codec Control Register

Name: ISI_DMA_C_CTRL Offset: 0x54 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 C_DONE C_IEN C_WB C_FETCH Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 3 – C_DONE Codec Transfer Done This bit is only updated in the memory. Value Description 0 The transfer related to this descriptor has not been performed. 1 The transfer related to this descriptor has completed. This bit is updated in memory at the end of the transfer when writeback operation is enabled. Bit 2 – C_IEN Transfer Done Flag Control Value Description 0 Codec transfer done flag generation is enabled. 1 Codec transfer done flag generation is disabled. Bit 1 – C_WB Descriptor Writeback Control Bit Value Description 0 Codec channel writeback operation is disabled. 1 Codec channel writeback operation is enabled. Bit 0 – C_FETCH Descriptor Fetch Control Bit Value Description 0 Codec channel fetch operation is disabled. 1 Codec channel fetch operation is enabled. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 556

37.6.23 DMA Codec Descriptor Address Register

Name: ISI_DMA_C_DSCR Offset: 0x58 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 C_DSCR[29:22] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 C_DSCR[21:14] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 C_DSCR[13:6] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 C_DSCR[5:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bits 31:2 – C_DSCR[29:0] Codec Descriptor Base Address This address is word-aligned. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 557

37.6.24 ISI Write Protection Mode Register

Name: ISI_WPMR Offset: 0xE4 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 WPKEY[23:16] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 WPKEY[15:8] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 WPKEY[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WPEN Access R/W Reset 0 Bits 31:8 – WPKEY[23:0] Write Protection Key Password Value Name Description 0x495349 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Bit 0 – WPEN Write Protection Enable Value Description 0 Disables the write protection if WPKEY corresponds to 0x495349 (“ISI” in ASCII). 1 Enables the write protection if WPKEY corresponds to 0x495349 (“ISI” in ASCII). SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 558

37.6.25 ISI Write Protection Status Register

Name: ISI_WPSR Offset: 0xE8 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 WPVSRC[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 WPVSRC[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WPVS Access R Reset 0 Bits 23:8 – WPVSRC[15:0] Write Protection Violation Source Value Name 0 No Write Protection Violation occurred since the last read of this register (ISI_WPSR). 1 Write access in ISI_CFG1 while Write Protection was enabled (since the last read). 2 Write access in ISI_CFG2 while Write Protection was enabled (since the last read). 3 Write access in ISI_PSIZE while Write Protection was enabled (since the last read). 4 Write access in ISI_PDECF while Write Protection was enabled (since the last read). 5 Write access in ISI_Y2R_SET0 while Write Protection was enabled (since the last read). 6 Write access in ISI_Y2R_SET1 while Write Protection was enabled (since the last read). 7 Write access in ISI_R2Y_SET0 while Write Protection was enabled (since the last read). 8 Write access in ISI_R2Y_SET1 while Write Protection was enabled (since the last read). 9 Write access in ISI_R2Y_SET2 while Write Protection was enabled (since the last read). Bit 0 – WPVS Write Protection Violation Status Value Name 0 No write protection violation occurred since the last read of ISI_WPSR. 1 A write protection violation has occurred since the last read of the ISI_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. SAMV71Q21RT Image Sensor Interface (ISI) © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 559

GMAC - Ethernet MAC The description and registers of this peripheral are using the 'GMAC' designation although the device does not support Gigabit Ethernet functionality.

38.1 Description

The Ethernet Media Access Controller (GMAC) module implements a 10/100 Mbps Ethernet MAC, compatible with the IEEE 802.3 standard. The GMAC can operate in either half or full duplex mode at all supported speeds.

38.2 Embedded Characteristics

Compatible with IEEE Standard 802.3
10, 100 Mbps operation
Full and half duplex operation at all supported speeds of operation
Statistics Counter Registers for RMON/MIB
MII/RMII interface to the physical layer
Integrated physical coding
Direct memory access (DMA) interface to external memory
Support for 6 priority queues in DMA
8-KByte transmit RAM and 4-KByte receive RAM (refer to Table 38-4 for queue-specific sizes
Programmable burst length and endianism for DMA
Interrupt generation to signal receive and transmit completion, errors or other events
Automatic pad and cyclic redundancy check (CRC) generation on transmitted frames
Automatic discard of frames received with errors
Receive and transmit IP, TCP and UDP checksum offload. Both IPv4 and IPv6 packet types supported
Address checking logic for four specific 48-bit addresses, four type IDs, promiscuous mode, hash matching of unicast and multicast destination addresses and Wake-on-LAN
Management Data Input/Output (MDIO) interface for physical layer management
Support for jumbo frames up to 10240 Bytes
Full duplex flow control with recognition of incoming pause frames and hardware generation of transmitted pause frames
Half duplex flow control by forcing collisions on incoming frames
Support for 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged frames
Support for 802.1Qbb priority-based flow control
Programmable Inter Packet Gap (IPG) Stretch
Recognition of IEEE 1588 PTP frames
IEEE 1588 time stamp unit (TSU)
Support for 802.1AS timing and synchronization
Supports 802.1Qav traffic shaping on two highest priority queues
Support for 802.3az Energy Efficient Ethernet SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 560

38.3 Block Diagram

Figure 38-1. Block Diagram Register Interface Status & Statistic Registers Control Registers FIFO Interface AHB DMA Interface MAC Transmitter MAC Receiver Frame Filtering MDIO Media Interface APB AHB Packet Buffer Memories

38.4 Signal Interface

The GMAC includes the following signal interfaces:

MII, RMII to an external PHY
MDIO interface for external PHY management
Slave APB interface for accessing GMAC registers
Master AHB interface for memory access
GTSUCOMP signal for TSU timer count value comparison Table 38-1. GMAC Connections in Different Modes Signal Name Function MII RMII GTXCK(1) Transmit Clock or Reference Clock TXCK REFCK GTXEN Transmit Enable TXEN TXEN GTX[3..0] Transmit Data TXD[3:0] TXD[1:0] GTXER Transmit Coding Error TXER Not Used GRXCK Receive Clock RXCK Not Used GRXDV Receive Data Valid RXDV CRSDV GRX[3..0] Receive Data RXD[3:0] RXD[1:0] GRXER Receive Error RXER RXER GCRS Carrier Sense and Data Valid CRS Not Used GCOL Collision Detect COL Not Used GMDC Management Data Clock MDC MDC GMDIO Management Data Input/Output MDIO MDIO SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 561

Note: 1. Input only. GTXCK must be provided with a 25 MHz / 50 MHz external clock signal from the Ethernet PHY for MII / RMII interfaces, respectively.

38.5 Product Dependencies

38.5.1 I/O Lines

The pins used for interfacing the GMAC may be multiplexed with PIO lines. The programmer must first program the PIO Controller to assign the pins to their peripheral function. If I/O lines of the GMAC are not used by the application, they can be used for other purposes by the PIO Controller.

38.5.2 Power Management

The GMAC is not continuously clocked. The user must first enable the GMAC clock in the Power Management Controller before using it.

38.5.3 Interrupt Sources

The GMAC interrupt line is connected to one of the internal sources of the interrupt controller. Using the GMAC interrupt requires prior programming of the interrupt controller. The GMAC features 6 interrupt sources. Refer to the table "Peripheral Identifiers" in the section "Peripherals" for the interrupt numbers for GMAC priority queues. Related Links

38.6 Functional Description

38.6.1 Media Access Controller

The Transmit Block of the Media Access Controller (MAC) takes data from FIFO, adds preamble, checks and adds padding and frame check sequence (FCS). Both half duplex and full duplex Ethernet modes of operation are supported. When operating in half duplex mode, the MAC Transmit Block generates data according to the Carrier Sense Multiple Access with Collision Detect (CSMA/CD) protocol. The start of transmission is deferred if Carrier Sense (CRS) is active. If Collision (COL) is detected during transmission, a jam sequence is asserted and the transmission is retried after a random back off. The CRS and COL signals have no effect in full duplex mode. The Receive Block of the MAC checks for valid preamble, FCS, alignment and length, and presents received frames to the MAC address checking block and FIFO. Software can configure the GMAC to receive jumbo frames of up to 10240 Bytes. It can optionally strip CRC (Cyclic Redundancy Check) from the received frame before transferring it to FIFO. The Address Checker recognizes four specific 48-bit addresses, can recognize four different types of ID values, and contains a 64-bit Hash register for matching multicast and unicast addresses as required. It can recognize the broadcast address all-'1' (0xFFFFFFFFFFFF) and copy all frames. The MAC can also reject all frames that are not VLAN tagged, and recognize Wake on LAN events. The MAC Receive Block supports offloading of IP, TCP and UDP checksum calculations (both IPv4 and IPv6 packet types supported), and can automatically discard bad checksum frames.

38.6.2 IEEE 1588 Time Stamp Unit

The IEEE 1588 time stamp unit (TSU) is implemented as a 94-bit timer.

The 48 upper bits [93:46] of the timer count seconds and are accessible in the GMAC 1588 Timer Seconds High Register” (GMAC_TSH) and GMAC 1588 Timer Seconds Low Register (GMAC_TSL).
The 30 lower bits [45:16] of the timer count nanoseconds and are accessible in the GMAC 1588 Timer Nanoseconds Register (GMAC_TN). SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 562

The lowest 16 bits [15:0] of the timer count sub-nanoseconds. The 46 lower bits roll over when they have counted to 1s. The timer increments by a programmable period (to approximately 15.2fs resolution) with each MCK period and can also be adjusted in 1ns resolution (incremented or decremented) through APB register accesses.

38.6.3 AHB Direct Memory Access Interface

The GMAC DMA controller is connected to the MAC FIFO interface and provides a scatter-gather type capability for packet data storage. The DMA implements packet buffering where dual-port memories are used to buffer multiple frames.

38.6.3.1 Packet Buffer DMA

Easier to guarantee maximum line rate due to the ability to store multiple frames in the packet buffer, where the number of frames is limited by the amount of packet buffer memory and Ethernet frame size
Full store and forward, or partial store and forward programmable options (partial store will cater for shorter latency requirements)
Support for Transmit TCP/IP checksum offload
Support for priority queuing
When a collision on the line occurs during transmission, the packet will be automatically replayed directly from the packet buffer memory rather than having to re-fetch through the AHB (full store and forward ONLY)
Received erroneous packets are automatically dropped before any of the packet is presented to the AHB (full store and forward ONLY), thus reducing AHB activity
Supports manual RX packet flush capabilities
Optional RX packet flush when there is lack of AHB resource

38.6.3.2 Partial Store and Forward Using Packet Buffer DMA

The DMA uses SRAM-based packet buffers, and can be programmed into a low latency mode, known as Partial Store and Forward. This mode allows for a reduced latency as the full packet is not buffered before forwarding. Note: This option is only available when the device is configured for full duplex operation. This feature is enabled via the programmable TX and RX Partial Store and Forward registers (GMAC_TPSF and GMAC_RPSF). When the transmit Partial Store and Forward mode is activated, the transmitter will only begin to forward the packet to the MAC when there is enough packet data stored in the packet buffer. Likewise, when the receive Partial Store and Forward mode is activated, the receiver will only begin to forward the packet to the AHB when enough packet data is stored in the packet buffer. The amount of packet data required to activate the forwarding process is programmable via watermark registers. These registers are located at the same address as the partial store and forward enable bits. Note: The minimum operational value for the TX partial store and forward watermark is 20. There is no operational limit for the RX partial store and forward watermark. Enabling Partial Store and Forward is a useful means to reduce latency, but there are performance implications. The GMAC DMA uses separate transmit and receive lists of buffer descriptors, with each descriptor describing a buffer area in memory. This allows Ethernet packets to be broken up and scattered around the AHB memory space.

38.6.3.3 Receive AHB Buffers

Received frames, optionally including FCS, are written to receive AHB buffers stored in memory. The receive buffer depth is programmable in the range of 64 Bytes to 16 KBytes through the DMA Configuration register (GMAC_DCFGR), with the default being 128 Bytes. The start location for each receive AHB buffer is stored in memory in a list of receive buffer descriptors at an address location pointed to by the receive buffer queue pointer. The base address for the receive buffer queue pointer is configured in software using the Receive Buffer Queue Base Address register (GMAC_RBQB). Each list entry consists of two words. The first is the address of the receive AHB buffer and the second the receive status. If the length of a receive frame exceeds the AHB buffer length, the status word for the used buffer is written with zeroes except for the “Start of Frame” bit, which is always set for the first buffer in a frame. Bit zero of the address field is written to 1 to show that the buffer has been used. The receive buffer manager then reads the location of the next receive AHB buffer and fills that with the next part of the received frame data. AHB SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 563

buffers are filled until the frame is complete and the final buffer descriptor status word contains the complete frame status. See the following table for details of the receive buffer descriptor list. Table 38-2. Receive Buffer Descriptor Entry Bit Function Word 0 31:2 Address of beginning of buffer 1 Wrap—marks last descriptor in receive buffer descriptor list. 0 Ownership—needs to be zero for the GMAC to write data to the receive buffer. The GMAC sets this to one once it has successfully written a frame to memory. Software has to clear this bit before the buffer can be used again. Word 1

31 Global all ones broadcast address detected

30 Multicast hash match

29 Unicast hash match

28 – 27 Specific Address Register match found, bit 25 and bit 26 indicate which Specific Address Register causes the match. 26:25 Specific Address Register match. Encoded as follows: 00: Specific Address Register 1 match 01: Specific Address Register 2 match 10: Specific Address Register 3 match 11: Specific Address Register 4 match If more than one specific address is matched only one is indicated with priority 4 down to 1. 24 This bit has a different meaning depending on whether RX checksum offloading is enabled. With RX checksum offloading disabled: (bit 24 clear in Network Configuration Register) Type ID register match found, bit 22 and bit 23 indicate which type ID register causes the match. With RX checksum offloading enabled: (bit 24 set in Network Configuration Register) 0: The frame was not SNAP encoded and/or had a VLAN tag with the Canonical Format Indicator (CFI) bit set. 1: The frame was SNAP encoded and had either no VLAN tag or a VLAN tag with the CFI bit not set. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 564

23:22 This bit has a different meaning depending on whether RX checksum offloading is enabled. With RX checksum offloading disabled: (bit 24 clear in Network Configuration) Type ID register match. Encoded as follows: 00: Type ID register 1 match 01: Type ID register 2 match 10: Type ID register 3 match 11: Type ID register 4 match If more than one Type ID is matched only one is indicated with priority 4 down to 1. With RX checksum offloading enabled: (bit 24 set in Network Configuration Register) 00: Neither the IP header checksum nor the TCP/UDP checksum was checked. 01: The IP header checksum was checked and was correct. Neither the TCP nor UDP checksum was checked. 10: Both the IP header and TCP checksum were checked and were correct. 11: Both the IP header and UDP checksum were checked and were correct. 21 VLAN tag detected—type ID of 0x8100. For packets incorporating the stacked VLAN processing feature, this bit will be set if the second VLAN tag has a type ID of 0x8100 20 Priority tag detected—type ID of 0x8100 and null VLAN identifier. For packets incorporating the stacked VLAN processing feature, this bit will be set if the second VLAN tag has a type ID of 0x8100 and a null VLAN identifier. 19:17 VLAN priority—only valid if bit 21 is set. 16 Canonical format indicator (CFI) bit (only valid if bit 21 is set). 15 End of frame—when set the buffer contains the end of a frame. If end of frame is not set, then the only valid status bit is start of frame (bit 14). 14 Start of frame—when set the buffer contains the start of a frame. If both bits 15 and 14 are set, the buffer contains a whole frame. 13 This bit has a different meaning depending on whether jumbo frames and ignore FCS modes are enabled. If neither mode is enabled this bit will be zero. With jumbo frame mode enabled: (bit 3 set in Network Configuration Register) Additional bit for length of frame (bit[13]), that is concatenated with bits[12:0] With ignore FCS mode enabled and jumbo frames disabled: (bit 26 set in Network Configuration Register and bit 3 clear in Network Configuration Register) This indicates per frame FCS status as follows: 0: Frame had good FCS 1: Frame had bad FCS, but was copied to memory as ignore FCS enabled. 12:0 These bits represent the length of the received frame which may or may not include FCS depending on whether FCS discard mode is enabled. With FCS discard mode disabled: (bit 17 clear in Network Configuration Register) Least significant 12 bits for length of frame including FCS. If jumbo frames are enabled, these 12 bits are concatenated with bit[13] of the descriptor above. With FCS discard mode enabled: (bit 17 set in Network Configuration Register) Least significant 12 bits for length of frame excluding FCS. If jumbo frames are enabled, these 12 bits are concatenated with bit[13] of the descriptor above. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 565

Each receive AHB buffer start location is a word address. The start of the first AHB buffer in a frame can be offset by up to three Bytes, depending on the value written to bits 14 and 15 of the Network Configuration register (GMAC_NCFGR). If the start location of the AHB buffer is offset, the available length of the first AHB buffer is reduced by the corresponding number of Bytes. To receive frames, the AHB buffer descriptors must be initialized by writing an appropriate address to bits 31:2 in the first word of each list entry. Bit 0 must be written with zero. Bit 1 is the wrap bit and indicates the last entry in the buffer descriptor list. The start location of the receive buffer descriptor list must be written with the receive buffer queue base address before reception is enabled (receive enable in the Network Control register GMAC_NCR). Once reception is enabled, any writes to the Receive Buffer Queue Base Address register (GMAC_RBQB) are ignored. When read, it will return the current pointer position in the descriptor list, though this is only valid and stable when receive is disabled. If the filter block indicates that a frame should be copied to memory, the receive data DMA operation starts writing data into the receive buffer. If an error occurs, the buffer is recovered. An internal counter within the GMAC represents the receive buffer queue pointer and it is not visible through the CPU interface. The receive buffer queue pointer increments by two words after each buffer has been used. It re-initializes to the receive buffer queue base address if any descriptor has its wrap bit set. As receive AHB buffers are used, the receive AHB buffer manager sets bit zero of the first word of the descriptor to logic one indicating the AHB buffer has been used. Software should search through the “used” bits in the AHB buffer descriptors to find out how many frames have been received, checking the start of frame and end of frame bits. When the DMA is configured in the packet buffer Partial Store And Forward mode, received frames are written out to the AHB buffers as soon as enough frame data exists in the packet buffer. For both cases, this may mean several full AHB buffers are used before some error conditions can be detected. If a receive error is detected the receive buffer currently being written will be recovered. Previous buffers will not be recovered. As an example, when receiving frames with cyclic redundancy check (CRC) errors or excessive length, it is possible that a frame fragment might be stored in a sequence of AHB receive buffers. Software can detect this by looking for start of frame bit set in a buffer following a buffer with no end of frame bit set. To function properly, a 10/100 Ethernet system should have no excessive length frames or frames greater than 128 Bytes with CRC errors. Collision fragments will be less than 128 Bytes long, therefore it will be a rare occurrence to find a frame fragment in a receive AHB buffer, when using the default value of 128 Bytes for the receive buffers size. When in packet buffer full store and forward mode, only good received frames are written out of the DMA, so no fragments will exist in the AHB buffers due to MAC receiver errors. There is still the possibility of fragments due to DMA errors, for example used bit read on the second buffer of a multi-buffer frame. If bit zero of the receive buffer descriptor is already set when the receive buffer manager reads the location of the receive AHB buffer, the buffer has been already used and cannot be used again until software has processed the frame and cleared bit zero. In this case, the “buffer not available” bit in the receive status register is set and an interrupt triggered. The receive resource error statistics register is also incremented. When the DMA is configured in the packet buffer full store and forward mode, the user can optionally select whether received frames should be automatically discarded when no AHB buffer resource is available. This feature is selected via the DMA Discard Receive Packets bit in the DMA Configuration register (GMAC_DCFGR.DDRP). By default, the received frames are not automatically discarded. If this feature is off, then received packets will remain to be stored in the SRAM-based packet buffer until AHB buffer resource next becomes available. This may lead to an eventual packet buffer overflow if packets continue to be received when bit zero (used bit) of the receive buffer descriptor remains set. Note: After a used bit has been read, the receive buffer manager will re-read the location of the receive buffer descriptor every time a new packet is received. When the DMA is not configured in the packet buffer full store and forward mode and a used bit is read, the frame currently being received will be automatically discarded. When the DMA is configured in the packet buffer full store and forward mode, a receive overrun condition occurs when the receive SRAM-based packet buffer is full, or because HRESP was not OK. In all other modes, a receive overrun condition occurs when either the AHB bus was not granted quickly enough, or because HRESP was not OK, or because a new frame has been detected by the receive block, but the status update or write back for the previous frame has not yet finished. For a receive overrun condition, the receive overrun interrupt is asserted and the buffer currently being written is recovered. The next frame that is received whose address is recognized reuses the buffer. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 566

In any packet buffer mode, writing a '1' to the Flush Next Package bit in the NCR register (GMAC_NCR.FNP) will force a packet from the external SRAM-based receive packet buffer to be flushed. This feature is only acted upon when the RX DMA is not currently writing packet data out to AHB, i.e., it is in an IDLE state. If the RX DMA is active, GMAC_NCR.FNP=1 is ignored.

38.6.3.4 Transmit AHB Buffers

Frames to transmit are stored in one or more transmit AHB buffers. Transmit frames can be between 1 and 16384 Bytes long, so it is possible to transmit frames longer than the maximum length specified in the IEEE 802.3 standard. It should be noted that zero length AHB buffers are allowed and that the maximum number of buffers permitted for each transmit frame is 128. The start location for each transmit AHB buffer is stored in memory in a list of transmit buffer descriptors at a location pointed to by the transmit buffer queue pointer. The base address for this queue pointer is set in software using the Transmit Buffer Queue Base Address register. Each list entry consists of two words. The first is the Byte address of the transmit buffer and the second containing the transmit control and status. For the packet buffer DMA, the start location for each AHB buffer is a Byte address, the bottom bits of the address being used to offset the start of the data from the data-word boundary (i.e., bits 2,1 and 0 are used to offset the address for 64-bit data paths). Frames can be transmitted with or without automatic Cyclic Redundancy Checksum (CRC) generation. If CRC is automatically generated, pad will also be automatically generated to take frames to a minimum length of 64 Bytes. When CRC is not automatically generated (as defined in word 1 of the transmit buffer descriptor), the frame is assumed to be at least 64 Bytes long and pad is not generated. An entry in the transmit buffer descriptor list is described in this table: Table 38-3. Transmit Buffer Descriptor Entry Bit Function Word 0 31:0 Byte address of buffer Word 1 31 Used—must be zero for the GMAC to read data to the transmit buffer. The GMAC sets this to one for the first buffer of a frame once it has been successfully transmitted. Software must clear this bit before the buffer can be used again. 30 Wrap—marks last descriptor in transmit buffer descriptor list. This can be set for any buffer within the frame.

29 Retry limit exceeded, transmit error detected

28 Reserved. 27 Transmit frame corruption due to AHB error—set if an error occurs while midway through reading transmit frame from the AHB, including HRESP errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and GTXER asserted). Also set if single frame is too large for configured packet buffer memory size. 26 Late collision, transmit error detected. 25:23 Reserved SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 567

22:20 Transmit IP/TCP/UDP checksum generation offload errors: 000: No Error. 001: The Packet was identified as a VLAN type, but the header was not fully complete, or had an error in it. 010: The Packet was identified as a SNAP type, but the header was not fully complete, or had an error in it. 011: The Packet was not of an IP type, or the IP packet was invalidly short, or the IP was not of type IPv4/IPv6. 100: The Packet was not identified as VLAN, SNAP or IP. 101: Non supported packet fragmentation occurred. For IPv4 packets, the IP checksum was generated and inserted. 110: Packet type detected was not TCP or UDP. TCP/UDP checksum was therefore not generated. For IPv4 packets, the IP checksum was generated and inserted. 111: A premature end of packet was detected and the TCP/UDP checksum could not be generated. 19:17 Reserved 16 No CRC to be appended by MAC. When set, this implies that the data in the buffers already contains a valid CRC, hence no CRC or padding is to be appended to the current frame by the MAC. This control bit must be set for the first buffer in a frame and will be ignored for the subsequent buffers of a frame. Note that this bit must be clear when using the transmit IP/TCP/UDP checksum generation offload, otherwise checksum generation and substitution will not occur. 15 Last buffer, when set this bit will indicate the last buffer in the current frame has been reached.

14 Reserved

13:0 Length of buffer To transmit frames, the buffer descriptors must be initialized by writing an appropriate Byte address to bits [31:0] of the first word of each descriptor list entry. The second word of the transmit buffer descriptor is initialized with control information that indicates the length of the frame, whether or not the MAC is to append CRC and whether the buffer is the last buffer in the frame. After transmission the status bits are written back to the second word of the first buffer along with the used bit. Bit 31 is the used bit which must be zero when the control word is read if transmission is to take place. It is written to '1' once the frame has been transmitted. Bits[29:20] indicate various transmit error conditions. Bit 30 is the wrap bit which can be set for any buffer within a frame. If no wrap bit is encountered the queue pointer continues to increment. The Transmit Buffer Queue Base Address register can only be updated while transmission is disabled or halted; otherwise any attempted write will be ignored. When transmission is halted the transmit buffer queue pointer will maintain its value. Therefore when transmission is restarted the next descriptor read from the queue will be from immediately after the last successfully transmitted frame. As long as transmit is disabled by writing a '0' to the Transmit Enable bit in the Network Control register (GMAC_NCR.TXEN), the transmit buffer queue pointer resets to point to the address indicated by the Transmit Buffer Queue Base Address register (GMAC_TBQB). Note: Disabling receive does not have the same effect on the receive buffer queue pointer. Once the transmit queue is initialized, transmit is activated by writing a '1' to the Start Transmission bit of the Network Control register (GMAC_NCR.TSTART). Transmit is halted when a buffer descriptor with its used bit set is read, a transmit error occurs, or by writing to the Transmit Halt bit of the Network Control register (GMAC_NCR.THALT). Transmission is suspended if a pause frame is received while the Transmit Pause Frame bit is '1' in the Network Configuration register (GMAC_NCR.TXPF). Rewriting the Start bit (GMAC_NCR.TSTART) while transmission is active is allowed. This is implemented by the Transmit Go variable which is readable in the Transmit Status register (GMAC_TSR.TXGO). The TXGO variable is reset when:

Transmit is disabled. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 568

A buffer descriptor with its ownership bit set is read.
Bit 10, THALT, of the Network Control register is written.
There is a transmit error such as too many retries or a transmit underrun. To set TXGO, write a '1' to GMAC_NCR.TSTART. Transmit halt does not take effect until any ongoing transmit finishes. If the DMA is configured for packet buffer Partial Store and Forward mode and a collision occurs during transmission of a multi-buffer frame, transmission will automatically restart from the first buffer of the frame. For packet buffer mode, the entire contents of the frame are read into the transmit packet buffer memory, so the retry attempt will be replayed directly from the packet buffer memory rather than having to re-fetch through the AHB. If a used bit is read midway through transmission of a multi-buffer frame, this is treated as a transmit error. Transmission stops, GTXER is asserted and the FCS will be bad. If transmission stops due to a transmit error or a used bit being read, transmission restarts from the first buffer descriptor of the frame being transmitted when the transmit start bit is rewritten.

38.6.3.5 DMA Bursting on the AHB

The DMA will always use SINGLE, or INCR type AHB accesses for buffer management operations. When performing data transfers, the AHB burst length is selected by the Fixed Burst Length for DMA Data Operations bit field in the DMA Configuration register (GMAC_DCFGR.FBLDO) so that either SINGLEor fixed length incrementing bursts (INCR4, INCR8 or INCR16) are used where possible: When there is enough space and enough data to be transferred, the programmed fixed length bursts will be used. If there is not enough data or space available, for example when at the beginning or the end of a buffer, SINGLE type accesses are used. Also SINGLE type accesses are used at 1024 Byte boundaries, so that the 1 KByte boundaries are not burst over as per AHB requirements. The DMA will not terminate a fixed length burst early, unless an error condition occurs on the AHB or if receive or transmit are disabled in the Network Control register (GMAC_NCR).

38.6.3.6 DMA Packet Buffer

The DMA uses packet buffers for both transmit and receive paths. This mode allows multiple packets to be buffered in both transmit and receive directions. This allows the DMA to withstand far greater access latencies on the AHB and make more efficient use of the AHB bandwidth. There are two modes of operation—Full Store and Forward and Partial Store and Forward. As described above, the DMA can be programmed into a low latency mode, known as Partial Store and Forward. For further details of this mode, see the related Links. When the DMA is in full store and forward mode, full packets are buffered which provides the possibility to:

Discard packets with error on the receive path before they are partially written out of the DMA, thus saving AHB bus bandwidth and driver processing overhead,
Retry collided transmit frames from the buffer, thus saving AHB bus bandwidth,
Implement transmit IP/TCP/UDP checksum generation offload. With the packet buffers included, the structure of the GMAC data paths is shown in this image: SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 569

Figure 38-2. Data Paths with Packet Buffers Included MAC Transmitter TX Packet Buffer RX Packet Buffer MAC Receiver RX DMA TX DMA RX Packet Buffer DPSRAM TX Packet Buffer DPSRAM Frame Filtering AHBAHB DMA Status and Statistic Registers Register Interface Control Interface Ethernet MAC RX GMII TX GMII MDIO APB

38.6.3.7 Transmit Packet Buffer

The transmitter packet buffer will continue attempting to fetch frame data from the AHB system memory until the packet buffer itself is full, at which point it will attempt to maintain its full level. To accommodate the status and statistics associated with each frame, three words per packet (or two if the GMAC is configured in 64-bit data path mode) are reserved at the end of the packet data. If the packet is bad and requires to be dropped, the status and statistics are the only information held on that packet. Storing the status in the DPRAM is required in order to decouple the DMA interface of the buffer from the MAC interface, to update the MAC status/ statistics and to generate interrupts in the order in which the packets that they represent were fetched from the AHB memory. If any errors occur on the AHB while reading the transmit frame, the fetching of packet data from AHB memory is halted. The MAC transmitter will continue to fetch packet data, thereby emptying the packet buffer and allowing any good (non-erroneous) frames to be transmitted successfully. Once these have been fully transmitted, the status/ statistics for the erroneous frame will be updated and software will be informed via an interrupt that an AHB error occurred. This way, the error is reported in the correct packet order. The transmit packet buffer will only attempt to read more frame data from the AHB when space is available in the packet buffer memory. If space is not available it must wait until the a packet fetched by the MAC completes transmission and is subsequently removed from the packet buffer memory. Note: If full store and forward mode is active and if a single frame is fetched that is too large for the packet buffer memory, the frame is flushed and the DMA halted with an error status. This is because a complete frame must be written into the packet buffer before transmission can begin, and therefore the minimum packet buffer memory size should be chosen to satisfy the maximum frame to be transmitted in the application. In full store and forward mode, once the complete transmit frame is written into the packet buffer memory, a trigger is sent across to the MAC transmitter, which will then begin reading the frame from the packet buffer memory. Since the whole frame is present and stable in the packet buffer memory an underflow of the transmitter is not possible. The frame is kept in the packet buffer until notification is received from the MAC that the frame data has either been successfully transmitted or can no longer be retransmitted (too many retries in half duplex mode). When this SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 570

notification is received the frame is flushed from memory to make room for a new frame to be fetched from AHB system memory. In Partial Store and Forward mode, a trigger is sent across to the MAC transmitter as soon as sufficient packet data is available, which will then begin fetching the frame from the packet buffer memory. If, after this point, the MAC transmitter is able to fetch data from the packet buffer faster than the AHB DMA can fill it, an underflow of the transmitter is possible. In this case, the transmission is terminated early, and the packet buffer is completely flushed. Transmission can only be restarted by writing a '1' to the Transmit Start bit in the Network Control register (GMAC_NCR.TSTART). In half duplex mode, the frame is kept in the packet buffer until notification is received from the MAC that the frame data has either been successfully transmitted or can no longer be retransmitted (too many retries in half duplex mode). When this notification is received the frame is flushed from memory to make room for a new frame to be fetched from AHB system memory. In full duplex mode, the frame is removed from the packet buffer on the fly. Other than underflow, the only MAC related errors that can occur are due to collisions during half duplex transmissions. When a collision occurs the frame still exists in the packet buffer memory so can be retried directly from there. After sixteen failed transmit attempts, the frame will be flushed from the packet buffer.

38.6.3.8 Receive Packet Buffer

The receive packet buffer stores frames from the MAC receiver along with their status and statistics. Frames with errors are flushed from the packet buffer memory, while good frames are pushed onto the DMA AHB interface. The receiver packet buffer monitors the FIFO write interface from the MAC receiver and translates the FIFO pushes into packet buffer writes. At the end of the received frame the status and statistics are buffered so that the information can be used when the frame is read out. When programmed in full store and forward mode and the frame has an error, the frame data is immediately flushed from the packet buffer memory allowing subsequent frames to utilize the freed up space. The status and statistics for bad frames are still used to update the GMAC registers. To accommodate the status and statistics associated with each frame, three words per packet (or two if configured in 64-bit datapath mode) are reserved at the end of the packet data. If the packet is bad and requires to be dropped, the status and statistics are the only information held on that packet. The receiver packet buffer will also detect a full condition so that an overflow condition can be detected. If this occurs, subsequent packets are dropped and an RX overflow interrupt is raised. For full store and forward, the DMA only begins packet fetches once the status and statistics for a frame are available. If the frame has a bad status due to a frame error, the status and statistics are passed on to the GMAC registers. If the frame has a good status, the information is used to read the frame from the packet buffer memory and burst onto the AHB using the DMA buffer management protocol. Once the last frame data has been transferred to the packet buffer, the status and statistics are updated to the GMAC registers. If Partial Store and Forward mode is active, the DMA will begin fetching the packet data before the status is available. As soon as the status becomes available, the DMA will fetch this information as soon as possible before continuing to fetch the remainder of the frame. Once the last frame data has been transferred to the packet buffer, the status and statistics are updated to the GMAC registers.

38.6.3.9 Priority Queuing in the DMA

The DMA by default uses a single transmit and receive queue. This means the list of transmit/receive buffer descriptors point to data buffers associated with a single transmit/receive data stream. The GMAC can select up to 6 priority queues. Each queue has an independent list of buffer descriptors pointing to separate data streams. The table below gives the DPRAM size associated with each queue. Table 38-4. Queue Size Queue Number Queue Size 5 (highest priority) 1 KB 4 2 KB 3 2 KB SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 571

0 (lowest priority) 2 KB In the transmit direction, higher priority queues are always serviced before lower priority queues, with Q0 as lowest priority and Q5 as highest priority. This strict priority scheme requires the user to ensure that high priority traffic is constrained so that lower priority traffic will have required bandwidth. The GMAC DMA will determine the next queue to service by initiating a sequence of buffer descriptor reads interrogating the ownership bits of each. The buffer descriptor corresponding to the highest priority queue is read first. As an example, if the ownership bit of this descriptor is set, the DMA will progress by reading the 2nd highest priority queue’s descriptor. If that ownership bit read of this lower priority queue is set as well, the DMA will read the 3rd highest priority queue’s descriptor. If all the descriptors return an ownership bit set, a resource error has occurred, so an interrupt is generated and transmission is automatically halted. Transmission can only be restarted by writing a '1' to the Transmission Start bit in the Network Control register (GMAC_NCR.TSTART). The GMAC DMA will need to identify the highest available queue to transmit from when the TSTART bit is written and the TX is in a halted state, or when the last word of any packet has been fetched from external AHB memory. The GMAC transmit DMA maximizes the effectiveness of priority queuing by ensuring that high priority traffic be transmitted as early as possible after being fetched from AHB. High priority traffic fetched from AHB will be pushed to the MAC layer, depending on traffic shaping being enabled and the associated credit value for that queue, before any lower priority traffic that may pre-exist in the transmit SRAM-based packet buffer. This is achieved by separating the transmit SRAM-based packet buffer into regions, one region per queue. The size of each region determines the amount of SRAM space allocated per queue. For each queue, there is an associated Transmit Buffer Queue Base Address register (GMAC_TBQB). For the lowest priority queue (or the only queue when only one queue is selected), the Transmit Buffer Queue Base Address is located at address 0x1C. For all other queues, the Transmit Buffer Queue Base Address registers are located at sequential addresses starting at address 0x440. In the receive direction each packet is written to AHB data buffers in the order that it is received. For each queue, there is an independent set of receive AHB buffers for each queue. There is therefore a separate Receive Buffer Queue Base Address register for each queue (GMAC_RBQBAx). For the lowest priority queue (or the only queue when only one queue is selected), the Receive Buffer Queue Base Address is located at address 0x18. For all other queues, the Receive Buffer Queue Base Address registers are located at sequential addresses starting at address 0x480. Every received packet will pass through a programmable screening algorithm which will allocate a particular queue to that frame. The user interface to the screeners is through two types of programmable registers:

Screening Type 1 registers: The module features 4 Screening Type 1 registers. Screening Type 1 registers hold values to match against specific IP and UDP fields of the received frames. The fields matched against are DS (Differentiated Services field of IPv4 frames), TC (Traffic class field of IPv6 frames) and/or the UDP destination port.
Screening Type 2 registers: The module features 8 Screening Type 2 registers GMAC_ST2RPQ. Screening Type 2 registers operate independently of Screening Type 1 registers and offer additional match capabilities. Screening Type 2 allows a screen to be configured that is the combination of all or any of the following comparisons: – An enable bit VLAN priority, VLANE. A VLAN priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against VLANP in the GMAC_ST2RPQ itself. – An enable bit EtherType, ETHE. The EtherType field I2ETH inside the GMAC_ST2RPQ maps to one of 4 EtherType match registers, GMAC_ST2ER. The extracted EtherType is compared against GMAC_ST2ER designated by this EtherType field. – An enable bit Compare A, COMPAE. This bit is associated with a Screening Type 2 Compare Word 0/1 register x, GMAC_ST2CW0/1. – An enable bit Compare B, COMPBE. This bit is associated with a Screening Type 2 Compare Word 0/1 register x, GMAC_ST2CW0/1. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 572

– An enable bit Compare C, COMPCE. This bit is associated with a Screening Type 2 Compare Word 0/1 register x, GMAC_ST2CW0/1. Each screener type has an enable bit, a match pattern and a queue number. If a received frame matches on an enabled screening register, then the frame will be tagged with the queue value in the associated screening register, and forwarded onto the DMA and subsequently into the external memory associated with that queue. If two screeners are matched then the one which resides at the lowest register address will take priority so care must be taken on the selection of the screener location. When the priority queuing feature is enabled, the number of interrupt outputs from the GMAC core is increased to match the number of supported queues. The number of Interrupt Status registers is increased by the same number. Only DMA related events are reported using the individual interrupt outputs, as the GMAC can relate these events to specific queues. All other events generated within the GMAC are reported in the interrupt associated with the lowest priority queue. For the lowest priority queue (or the only queue when only 1 queue is selected), the Interrupt Status register is located at address 0x24. For all other queues, the Interrupt Status register is located at sequential addresses starting at address 0x400. Note: The address matching is the first level of filtering. If there is a match, the screeners are the next level of filtering for routing the data to the appropriate queue. See MAC Filtering Block for more details. The additional screening done by the functions Compare A, B, and C each have an enable bit and compare register field. COMPA, COMPB and COMPC in GMAC_ST2RPQ are pointers to a configured offset (OFFSVAL), value (COMPVAL), and mask (MASKVAL). If enabled, the compare is true if the data at the offset into the frame, ANDed with MASKVAL, is equal to the value of COMPVAL ANDed with MASKVAL. A 16-bit word comparison is done. The byte at the offset number of bytes from the index start is compared to bits 7:0 of the configured COMPVAL and MASKVAL. The byte at the offset number of bytes + 1 from the index start is compared to bits 15:8 of the configured COMPVAL and MASKVAL. The offset value in bytes, OFFSVAL, ranges from 0 to 127 bytes from either the start of the frame, the byte after the EtherType field, the byte after the IP header (IPv4 or IPv6) or the byte after the TCP/UDP header. Note the logic to decode the IP header or the TCP/UDP header is reused from the TCP/UDP/IP checksum offload logic and therefore has the same restrictions on use (the main limitation is that IP fragmentation is not supported). Refer to the Checksum Offload for IP, TCP and UDP section of this documentation for further details. Compare A, B, and C use a common set of 24 GMAC_ST2CW0/1 registers, thus all COMPA, COMPB and COMPC fields in the registers GMAC_ST2RPQ point to a single pool of 24 GMAC_ST2CW0/1 registers. Note that Compare A, B and C together allow matching against an arbitrary 48 bits of data and so can be used to match against a MAC address. All enabled comparisons are ANDed together to form the overall type 2 screening match. Related Links

38.6.6 Checksum Offload for IP, TCP and UDP

38.6.4 MAC Transmit Block

The MAC transmitter can operate in either half duplex or full duplex mode and transmits frames in accordance with the Ethernet IEEE 802.3 standard. In half duplex mode, the CSMA/CD protocol of the IEEE 802.3 specification is followed. A small input buffer receives data through the FIFO interface which will extract data in 32-bit form. All subsequent processing prior to the final output is performed in bytes. Transmit data can be output using the MII interface. Frame assembly starts by adding preamble and the start frame delimiter. Data is taken from the transmit FIFO interface a word at a time. If necessary, padding is added to take the frame length to 60 bytes. CRC is calculated using an order 32-bit polynomial. This is inverted and appended to the end of the frame taking the frame length to a minimum of 64 bytes. If the no CRC bit is set in the second word of the last buffer descriptor of a transmit frame, neither pad nor CRC are appended. The no CRC bit can also be set through the FIFO interface. In full duplex mode (at all data rates), frames are transmitted immediately. Back to back frames are transmitted at least 96 bit times apart to guarantee the interframe gap. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 573

In half duplex mode, the transmitter checks carrier sense. If asserted, the transmitter waits for the signal to become inactive, and then starts transmission after the interframe gap of 96 bit times. If the collision signal is asserted during transmission, the transmitter will transmit a jam sequence of 32 bits taken from the data register and then retry transmission after the back off time has elapsed. If the collision occurs during either the preamble or Start Frame Delimiter (SFD), then these fields will be completed prior to generation of the jam sequence. The back off time is based on an XOR of the 10 least significant bits of the data coming from the transmit FIFO interface and a 10-bit pseudo random number generator. The number of bits used depends on the number of collisions seen. After the first collision 1 bit is used, then the second 2 bits and so on up to the maximum of 10 bits. All 10 bits are used above ten collisions. An error will be indicated and no further attempts will be made if 16 802.3 standard which refers to the truncated binary exponential back off algorithm. In 10/100 mode, both collisions and late collisions are treated identically, and back off and retry will be performed up to 16 times. This condition is reported in the transmit buffer descriptor word 1 (late collision, bit 26) and also in the Transmit Status register (late collision, bit 7). An interrupt can also be generated (if enabled) when this exception occurs, and bit 5 in the Interrupt Status register will be set. In all modes of operation, if the transmit DMA underruns, a bad CRC is automatically appended using the same mechanism as jam insertion and the GTXER signal is asserted. For a properly configured system this should never happen and also it is impossible if configured to use the DMA with packet buffers, as the complete frame is buffered in local packet buffer memory. By setting when bit 28 is set in the Network Configuration register, the Inter Packet Gap (IPG) may be stretched beyond 96 bits depending on the length of the previously transmitted frame and the value written to the IPG Stretch register (GMAC_IPGS). The least significant 8 bits of the IPG Stretch register multiply the previous frame length (including preamble). The next significant 8 bits (+1 so as not to get a divide by zero) divide the frame length to generate the IPG. IPG stretch only works in full duplex mode and when bit 28 is set in the Network Configuration register. The IPG Stretch register cannot be used to shrink the IPG below 96 bits. If the back pressure bit is set in the Network Control register, or if the HDFC configuration bit is set in the GMAC_UR register (10M or 100M half duplex mode), the transmit block transmits 64 bits of data, which can consist of 16 nibbles of 1011 or in bit rate mode 64 1s, whenever it sees an incoming frame to force a collision. This provides a way of implementing flow control in half duplex mode.

38.6.5 MAC Receive Block

All processing within the MAC receive block is implemented using a 16-bit data path. The MAC receive block checks for valid preamble, FCS, alignment and length, presents received frames to the FIFO interface and stores the frame destination address for use by the address checking block. If, during the frame reception, the frame is found to be too long, a bad frame indication is sent to the FIFO interface. The receiver logic ceases to send data to memory as soon as this condition occurs. At end of frame reception the receive block indicates to the DMA block whether the frame is good or bad. The DMA block will recover the current receive buffer if the frame was bad. Ethernet frames are normally stored in DMA memory complete with the FCS. Setting the FCS remove bit in the network configuration (bit 17) causes frames to be stored without their corresponding FCS. The reported frame length field is reduced by four bytes to reflect this operation. The receive block signals to the register block to increment the alignment, CRC (FCS), short frame, long frame, jabber or receive symbol errors when any of these exception conditions occur. If bit 26 is set in the network configuration, CRC errors will be ignored and CRC errored frames will not be discarded, though the Frame Check Sequence Errors statistic register will still be incremented. Additionally, if not enabled for jumbo frames mode, then bit[13] of the receiver descriptor word 1 will be updated to indicate the FCS validity for the particular frame. This is useful for applications such as EtherCAT whereby individual frames with FCS errors must be identified. Received frames can be checked for length field error by setting the length field error frame discard bit of the Network Configuration register (bit-16). When this bit is set, the receiver compares a frame's measured length with the length field (bytes 13 and 14) extracted from the frame. The frame is discarded if the measured length is shorter. This checking procedure is for received frames between 64 bytes and 1518 bytes in length. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 574

Each discarded frame is counted in the 10-bit length field error statistics register. Frames where the length field is greater than or equal to 0x0600 hex will not be checked. The GMAC can be programmed to perform IP, TCP and UDP checksum offloading in both receive and transmit directions, which is enabled by setting bit 24 in the Network Configuration register for receive and bit 11 in the DMA Configuration register for transmit. IPv4 packets contain a 16-bit checksum field, which is the 16-bit 1’s complement of the 1’s complement sum of all 16-bit words in the header. TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit 1’s complement of the 1’s complement sum of all 16-bit words in the header, the data and a conceptual IP pseudo header. To calculate these checksums in software requires each byte of the packet to be processed. For TCP and UDP this can use a large amount of processing power. Offloading the checksum calculation to hardware can result in significant performance improvements. For IP, TCP or UDP checksum offload to be useful, the operating system containing the protocol stack must be aware that this offload is available so that it can make use of the fact that the hardware can either generate or verify the checksum.

38.6.6.1 Receiver Checksum Offload

When receive checksum offloading is enabled in the GMAC Network Configuration Register (NCFGR.RXCOEN), the IPv4 header checksum is checked as per RFC 791, where the packet meets the following criteria:

If present, the VLAN header must be four octets long and the CFI bit must not be set.
Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP Encoding.
IPv4 packet
IP header is of a valid length The GMAC also checks the TCP checksum as per RFC 793, or the UDP checksum as per RFC 768, if the following criteria are met:
IPv4 or IPv6 packet
Good IP header checksum (if IPv4)
No IP fragmentation
TCP or UDP packet When an IP, TCP or UDP frame is received, the receive buffer descriptor gives an indication if the GMAC was able to verify the checksums. There is also an indication if the frame had SNAP encapsulation. These indication bits will replace the type ID match indication bits when the receive checksum offload is enabled. For details of these indication bits refer to “Receive Buffer Descriptor Entry”. If any of the checksums are verified as incorrect by the GMAC, the packet is discarded and the appropriate statistics counter incremented.

38.6.6.2 Transmitter Checksum Offload

The transmitter checksum offload is only available if the full store and forward mode is enabled. This is because the complete frame to be transmitted must be read into the packet buffer memory before the checksum can be calculated and written back into the headers at the beginning of the frame. Transmitter checksum offload is enabled by setting bit [11] in the DMA Configuration register. When enabled, it will monitor the frame as it is written into the transmitter packet buffer memory to automatically detect the protocol of the frame. Protocol support is identical to the receiver checksum offload. For transmit checksum generation and substitution to occur, the protocol of the frame must be recognized and the frame must be provided without the FCS field, by making sure that bit [16] of the transmit descriptor word 1 is clear. If the frame data already had the FCS field, this would be corrupted by the substitution of the new checksum fields. If these conditions are met, the transmit checksum offload engine will calculate the IP, TCP and UDP checksums as appropriate. Once the full packet is completely written into packet buffer memory, the checksums will be valid and the relevant DPRAM locations will be updated for the new checksum fields as per standard IP/TCP and UDP packet structures. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 575

If the transmitter checksum engine is prevented from generating the relevant checksums, bits [22:20] of the transmitter DMA writeback status will be updated to identify the reason for the error. Note that the frame will still be transmitted but without the checksum substitution, as typically the reason that the substitution did not occur was that the protocol was not recognized.

38.6.7 MAC Filtering Block

The filter block determines which frames should be written to the FIFO interface and on to the DMA. Whether a frame is passed depends on what is enabled in the Network Configuration register, the state of the external matching pins, the contents of the specific address, type and Hash registers and the frame's destination address and type field. If bit 25 of the Network Configuration register is not set, a frame will not be copied to memory if the GMAC is transmitting in half duplex mode at the time a destination address is received. Ethernet frames are transmitted a byte at a time, least significant bit first. The first six bytes (48 bits) of an Ethernet frame make up the destination address. The first bit of the destination address, which is the LSB of the first byte of the frame, is the group or individual bit. This is one for multicast addresses and zero for unicast. The all ones address is the broadcast address and a special case of multicast. The GMAC supports recognition of four specific addresses. Each specific address requires two registers, Specific Address register Bottom and Specific Address register Top. Specific Address register Bottom stores the first four bytes of the destination address and Specific Address register Top contains the last two bytes. The addresses stored can be specific, group, local or universal. The destination address of received frames is compared against the data stored in the Specific Address registers once they have been activated. The addresses are deactivated at reset or when their corresponding Specific Address register Bottom is written. They are activated when Specific Address register Top is written. If a receive frame address matches an active address, the frame is written to the FIFO interface and on to DMA memory. Frames may be filtered using the type ID field for matching. Four type ID registers exist in the register address space and each can be enabled for matching by writing a one to the MSB (bit 31) of the respective register. When a frame is received, the matching is implemented as an OR function of the various types of match. The contents of each type ID register (when enabled) are compared against the length/type ID of the frame being received (e.g., bytes 13 and 14 in non-VLAN and non-SNAP encapsulated frames) and copied to memory if a match is found. The encoded type ID match bits (Word 0, Bit 22 and Bit 23) in the receive buffer descriptor status are set indicating which type ID register generated the match, if the receive checksum offload is disabled. The reset state of the type ID registers is zero, hence each is initially disabled. The following example illustrates the use of the address and type ID match registers for a MAC address of 21:43:65:87:A9:CB: Preamble 55 SFD D5 DA (Octet 0 - LSB) 21 DA (Octet 1) 43 DA (Octet 2) 65 DA (Octet 3) 87 DA (Octet 4) A9 DA (Octet 5 - MSB) CB SA (LSB) 00 (see Note) SA 00(see Note) SA 00(see Note) SA 00(see Note) SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 576

SA 00(see Note) SA (MSB) 00(see Note) Type ID (MSB) 43 Type ID (LSB) 21 Note: Contains the address of the transmitting device. The previous sequence shows the beginning of an Ethernet frame. Byte order of transmission is from top to bottom, as shown. For a successful match to specific address 1, the following address matching registers must be set up: Specific Address 1 Bottom register (GMAC_SAB1) (Address 0x088) 0x87654321 Specific Address 1 Top register (GMAC_SAT1) (Address 0x08C) 0x0000CBA9 For a successful match to the type ID, the following Type ID Match 1 register must be set up: Type ID Match 1 register (GMAC_TIDM1) (Address 0x0A8) 0x80004321

38.6.8 Broadcast Address

Frames with the broadcast address of 0xFFFFFFFFFFFF are stored to memory only if the 'no broadcast' bit in the Network Configuration register is set to zero.

38.6.9 Hash Addressing

The hash address register is 64 bits long and takes up two locations in the memory map. The least significant bits are stored in Hash Register Bottom and the most significant bits in Hash Register Top. The unicast hash enable and the multicast hash enable bits in the Network Configuration register enable the reception of hash matched frames. The destination address is reduced to a 6-bit index into the 64-bit Hash register using the following hash function: The hash function is an XOR of every sixth bit of the destination address. hash_index[05] = da[05] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] hash_index[04] = da[04] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] hash_index[03] = da[03] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] hash_index[02] = da[02] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] hash_index[01] = da[01] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] hash_index[00] = da[00] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] da[0] represents the least significant bit of the first byte received, that is, the multicast/unicast indicator, and da[47] represents the most significant bit of the last byte received. If the hash index points to a bit that is set in the Hash register then the frame will be matched according to whether the frame is multicast or unicast. A multicast match will be signaled if the multicast hash enable bit is set, da[0] is logic 1 and the hash index points to a bit set in the Hash register. A unicast match will be signaled if the unicast hash enable bit is set, da[0] is logic 0 and the hash index points to a bit set in the Hash register. To receive all multicast frames, the Hash register should be set with all ones and the multicast hash enable bit should be set in the Network Configuration register.

38.6.10 Copy all Frames (Promiscuous Mode)

If the Copy All Frames bit is set in the Network Configuration register then all frames (except those that are too long, too short, have FCS errors or have GRXER asserted during reception) will be copied to memory. Frames with FCS errors will be copied if bit 26 is set in the Network Configuration register. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 577

38.6.11 Disable Copy of Pause Frames

Pause frames can be prevented from being written to memory by setting the disable copying of pause frames control bit 23 in the Network Configuration register. When set, pause frames are not copied to memory regardless of the Copy All Frames bit, whether a hash match is found, a type ID match is identified or if a destination address match is found.

38.6.12 VLAN Support

The following table describes an Ethernet encoded 802.1Q VLAN tag. Table 38-5. 802.1Q VLAN Tag TPID (Tag Protocol Identifier) 16 bits TCI (Tag Control Information) 16 bits 0x8100 First 3 bits priority, then CFI bit, last 12 bits VID The VLAN tag is inserted at the 13th byte of the frame adding an extra four bytes to the frame. To support these extra four bytes, the GMAC can accept frame lengths up to 1536 bytes by setting bit 8 in the Network Configuration register. If the VID (VLAN identifier) is null (0x000) this indicates a priority-tagged frame. The following bits in the receive buffer descriptor status word give information about VLAN tagged frames:-

Bit 21 set if receive frame is VLAN tagged (i.e., type ID of 0x8100).
Bit 20 set if receive frame is priority tagged (i.e., type ID of 0x8100 and null VID). (If bit 20 is set, bit 21 will be set also.)
Bit 19, 18 and 17 set to priority if bit 21 is set.
Bit 16 set to CFI if bit 21 is set. The GMAC can be configured to reject all frames except VLAN tagged frames by setting the discard non-VLAN frames bit in the Network Configuration register.

38.6.13 Wake on LAN Support

The receive block supports Wake on LAN by detecting the following events on incoming receive frames:

Magic packet
Address Resolution Protocol (ARP) request to the device IP address
Specific address 1 filter match
Multicast hash filter match These events can be individually enabled through bits [19:16] of the Wake on LAN register. Also, for Wake on LAN detection to occur, receive enable must be set in the Network Control register, however a receive buffer does not have to be available. In case of an ARP request, specific address 1 or multicast filter events will occur even if the frame is errored. For magic packet events, the frame must be correctly formed and error free. A magic packet event is detected if all of the following are true:
Magic packet events are enabled through bit 16 of the Wake on LAN register
The frame's destination address matches specific address 1
The frame is correctly formed with no errors
The frame contains at least 6 bytes of 0xFF for synchronization
There are 16 repetitions of the contents of Specific Address 1 register immediately following the synchronization An ARP request event is detected if all of the following are true:
ARP request events are enabled through bit 17 of the Wake on LAN register
Broadcasts are allowed by bit 5 in the Network Configuration register
The frame has a broadcast destination address (bytes 1 to 6)
The frame has a type ID field of 0x0806 (bytes 13 and 14) SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 578

The frame has an ARP operation field of 0x0001 (bytes 21 and 22)
The least significant 16 bits of the frame's ARP target protocol address (bytes 41 and 42) match the value programmed in bits[15:0] of the Wake on LAN register The decoding of the ARP fields adjusts automatically if a VLAN tag is detected within the frame. The reserved value of 0x0000 for the Wake on LAN target address value will not cause an ARP request event, even if matched by the frame. A specific address 1 filter match event will occur if all of the following are true:
Specific address 1 events are enabled through bit 18 of the Wake on LAN register
The frame's destination address matches the value programmed in the Specific Address 1 registers A multicast filter match event will occur if all of the following are true:
Multicast hash events are enabled through bit 19 of the Wake on LAN register
Multicast hash filtering is enabled through bit 6 of the Network Configuration register
The frame destination address matches against the multicast hash filter
The frame destination address is not a broadcast

38.6.14 IEEE 1588 Support

IEEE 1588 is a standard for precision time synchronization in local area networks. It works with the exchange of special Precision Time Protocol (PTP) frames. The PTP messages can be transported over IEEE 802.3/Ethernet, over Internet Protocol Version 4 or over Internet Protocol Version 6 as described in the annex of IEEE P1588.D2.1. The GMAC indicates the message time-stamp point (asserted on the start packet delimiter and de-asserted at end of frame) for all frames and the passage of PTP event frames (asserted when a PTP event frame is detected and de-asserted at end of frame). IEEE 802.1AS is a subset of IEEE 1588. One difference is that IEEE 802.1AS uses the Ethernet multicast address 0180C200000E for sync frame recognition whereas IEEE 1588 does not. GMAC is designed to recognize sync frames with both IEEE 802.1AS and IEEE 1588 addresses and so can support both 1588 and 802.1AS frame recognition simultaneously. Synchronization between master and slave clocks is a two stage process. First, the offset between the master and slave clocks is corrected by the master sending a sync frame to the slave with a follow up frame containing the exact time the sync frame was sent. Hardware assist modules at the master and slave side detect exactly when the sync frame was sent by the master and received by the slave. The slave then corrects its clock to match the master clock. Second, the transmission delay between the master and slave is corrected. The slave sends a delay request frame to the master which sends a delay response frame in reply. Hardware assist modules at the master and slave side detect exactly when the delay request frame was sent by the slave and received by the master. The slave will now have enough information to adjust its clock to account for delay. For example, if the slave was assuming zero delay, the actual delay will be half the difference between the transmit and receive time of the delay request frame (assuming equal transmit and receive times) because the slave clock will be lagging the master clock by the delay time already. The time-stamp is taken when the message time-stamp point passes the clock time-stamp point. This can generate an interrupt if enabled (GMAC_IER). However, MAC Filtering configuration is needed to actually ‘copy’ the message to memory. For Ethernet, the message time-stamp point is the SFD and the clock time-stamp point is the MII interface. (The IEEE 1588 specification refers to sync and delay_req messages as event messages as these require time-stamping. These events are captured in the registers GMAC_EFTx and GMAC_EFRx, respectively. Follow up, delay response and management messages do not require time-stamping and are referred to as general messages.) 1588 version 2 defines two additional PTP event messages. These are the peer delay request (Pdelay_Req) and peer delay response (Pdelay_Resp) messages. These events are captured in the registers GMAC_PEFTx and GMAC_PEFRx, respectively. These messages are used to calculate the delay on a link. Nodes at both ends of a link send both types of frames (regardless of whether they contain a master or slave clock). The Pdelay_Resp message contains the time at which a Pdelay_Req was received and is itself an event message. The time at which a Pdelay_Resp message is received is returned in a Pdelay_Resp_Follow_Up message. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 579

1588 version 2 introduces transparent clocks of which there are two kinds, peer-to-peer (P2P) and end-to-end (E2E). Transparent clocks measure the transit time of event messages through a bridge and amend a correction field within the message to allow for the transit time. P2P transparent clocks additionally correct for the delay in the receive path of the link using the information gathered from the peer delay frames. With P2P transparent clocks delay_req messages are not used to measure link delay. This simplifies the protocol and makes larger systems more stable. The GMAC recognizes four different encapsulations for PTP event messages: 1. 1588 version 1 (UDP/IPv4 multicast) 2. 1588 version 2 (UDP/IPv4 multicast) 3. 1588 version 2 (UDP/IPv6 multicast) 4. 1588 version 2 (Ethernet multicast) Table 38-6. Example of Sync Frame in 1588 Version 1 Format Frame Segment Value Preamble/SFD 55555555555555D5 DA (Octets 0–5) — SA (Octets 6–11) — Type (Octets 12–13) 0800 IP stuff (Octets 14–22) — UDP (Octet 23) 11 IP stuff (Octets 24–29) — IP DA (Octets 30–32) E00001 IP DA (Octet 33) 81 or 82 or 83 or 84 Source IP port (Octets 34–35) — Dest IP port (Octets 36–37) 013F Other stuff (Octets 38–42) — Version PTP (Octet 43) 01 Other stuff (Octets 44–73) — Control (Octet 74) 00 Other stuff (Octets 75–168) — Table 38-7. Example of Delay Request Frame in 1588 Version 1 Format Frame Segment Value Preamble/SFD 55555555555555D5 DA (Octets 0–5) — SA (Octets 6–11) — Type (Octets 12–13) 0800 IP stuff (Octets 14–22) — UDP (Octet 23) 11 IP stuff (Octets 24–29) — IP DA (Octets 30–32) E00001 IP DA (Octet 33) 81 or 82 or 83 or 84 SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 580

Source IP port (Octets 34–35) — Dest IP port (Octets 36–37) 013F Other stuff (Octets 38–42) — Version PTP (Octet 43) 01 Other stuff (Octets 44–73) — Control (Octet 74) 01 Other stuff (Octets 75–168) — For 1588 version 1 messages, sync and delay request frames are indicated by the GMAC if the frame type field indicates TCP/IP, UDP protocol is indicated, the destination IP address is 224.0.1.129/130/131 or 132, the destination UDP port is 319 and the control field is correct. The control field is 0x00 for sync frames and 0x01 for delay request frames. For 1588 version 2 messages, the type of frame is determined by looking at the message type field in the first byte of the PTP frame. Whether a frame is version 1 or version 2 can be determined by looking at the version PTP field in the second byte of both version 1 and version 2 PTP frames. In version 2 messages sync frames have a message type value of 0x0, delay_req have 0x1, Pdelay_Req have 0x2 and Pdelay_Resp have 0x3. Table 38-8. Example of Sync Frame in 1588 Version 2 (UDP/IPv4) Format Frame Segment Value Preamble/SFD 55555555555555D5 DA (Octets 0–5) — SA (Octets 6–11) — Type (Octets 12–13) 0800 IP stuff (Octets 14–22) — UDP (Octet 23) 11 IP stuff (Octets 24–29) — IP DA (Octets 30–33) E0000181 Source IP port (Octets 34–35) — Dest IP port (Octets 36–37) 013F Other stuff (Octets 38–41) — Message type (Octet 42) 00 Version PTP (Octet 43) 02 Table 38-9. Example of Pdelay_Req Frame in 1588 Version 2 (UDP/IPv4) Format Frame Segment Value Preamble/SFD 55555555555555D5 DA (Octets 0–5) — SA (Octets 6–11) — SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 581

Type (Octets 12–13) 0800 IP stuff (Octets 14–22) — UDP (Octet 23) 11 IP stuff (Octets 24–29) — IP DA (Octets 30–33) E000006B Source IP port (Octets 34–35) — Dest IP port (Octets 36–37) 013F Other stuff (Octets 38–41) — Message type (Octet 42) 02 Version PTP (Octet 43) 02 Table 38-10. Example of Sync Frame in 1588 Version 2 (UDP/IPv6) Format Frame Segment Value Preamble/SFD 55555555555555D5 DA (Octets 0–5) — SA (Octets 6–11) — Type (Octets 12–13) 86dd IP stuff (Octets 14–19) — UDP (Octet 20) 11 IP stuff (Octets 21–37) — IP DA (Octets 38–53) FF0X00000000018 Source IP port (Octets 54–55) — Dest IP port (Octets 56–57) 013F Other stuff (Octets 58–61) — Message type (Octet 62) 00 Other stuff (Octets 63–93) — Version PTP (Octet 94) 02 Table 38-11. Example of Pdelay_Resp Frame in 1588 Version 2 (UDP/IPv6) Format Frame Segment Value Preamble/SFD 55555555555555D5 DA (Octets 0–5) — SA (Octets 6–11) — Type (Octets 12–13) 86dd IP stuff (Octets 14–19) — UDP (Octet 20) 11 SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 582

IP stuff (Octets 21–37) — IP DA (Octets 38–53) FF0200000000006B Source IP port (Octets 54–55) — Dest IP port (Octets 56–57) 013F Other stuff (Octets 58–61) — Message type (Octet 62) 03 Other stuff (Octets 63–93) — Version PTP (Octet 94) 02 For the multicast address 011B19000000 sync and delay request frames are recognized depending on the message type field, 00 for sync and 01 for delay request. Table 38-12. Example of Sync Frame in 1588 Version 2 (Ethernet Multicast) Format Frame Segment Value Preamble/SFD 55555555555555D5 DA (Octets 0–5) 011B19000000 SA (Octets 6–11) — Type (Octets 12–13) 88F7 Message type (Octet 14) 00 Version PTP (Octet 15) 02 Pdelay request frames need a special multicast address so they can pass through ports blocked by the spanning tree protocol. For the multicast address 0180C200000E sync, Pdelay_Req and Pdelay_Resp frames are recognized depending on the message type field, 00 for sync, 02 for pdelay request and 03 for pdelay response. Table 38-13. Example of Pdelay_Req Frame in 1588 Version 2 (Ethernet Multicast) Format Frame Segment Value Preamble/SFD 55555555555555D5 DA (Octets 0–5) 0180C200000E SA (Octets 6–11) — Type (Octets 12–13) 88F7 Message type (Octet 14) 00 Version PTP (Octet 15) 02

38.6.15 Time Stamp Unit

The TSU consists of a timer and registers to capture the time at which PTP event frames cross the message timestamp point. An interrupt is issued when a capture register is updated. The 1588 time stamp unit (TSU) is implemented as a 94-bit timer. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 583

The 48 upper bits [93:46] of the timer count seconds and are accessible in the GMAC 1588 Timer Seconds High Register” (GMAC_TSH) and GMAC 1588 Timer Seconds Low Register (GMAC_TSL).
The 30 lower bits [45:16] of the timer count nanoseconds and are accessible in the GMAC 1588 Timer Nanoseconds Register (GMAC_TN).
The lowest 16 bits [15:0] of the timer count sub-nanoseconds. The 46 lower bits roll over when they have counted to 1s. An interrupt is generated when the seconds increment. The timer increments by a programmable period (to approximately 15.2fs resolution) with each MCK period. The timer value can be read, written and adjusted with 1ns resolution (incremented or decremented) through the APB interface. Timer Adjustment The amount by which the timer increments each clock cycle is controlled by the Timer Increment register (GMAC_TI). Bits [7:0] are the default increment value in nanoseconds. Additional 16 bits of sub-nanosecond resolution are available using the Timer Increment Sub-Nanoseconds register (GMAC_TISUBN). If the rest of the register is written with zero, the timer increments by the value in [7:0], plus the value of the GMAC_TISUBN for each clock cycle. The GMAC_TISUBN allows a resolution of approximately 15fs. Bits [15:8] of the increment register are the alternative increment value in nanoseconds, and bits [23:16] are the number of increments after which the alternative increment value is used. If [23:16] are zero the alternative increment value will never be used. Taking the example of 10.2MHz, there are 102 cycles every 10µs or 51 cycles every 5µs. So a timer with a 10.2MHz clock source is constructed by incrementing by 98ns for fifty cycles and then incrementing by 100ns (98ns × 50 + 100ns = 5000ns). This is programmed by writing the value 0x00326462 to the Timer Increment register (GMAC_TI). In a second example, a 49.8 MHz clock source requires 20ns for 248 cycles, followed by an increment of 40ns (20ns × 248 + 40ns = 5000ns). This is programmed by writing the value 0x00F82814 to the GMAC_TI register. The Number of Increments bit field in the GMAC_TI register is 8 bit in size, so frequencies up to 50MHz are supported with 200kHz resolution. Without the alternative increment field the period of the clock would be limited to an integer number of nanoseconds, resulting in supported clock frequencies of 8, 10, 20, 25, 40, 50, 100, 125, 200 and 250 MHz. There are eight additional 80-bit registers that capture the time at which PTP event frames are transmitted and received. An interrupt is issued when these registers are updated. The TSU timer count value can be compared to a programmable comparison value. For the comparison, the 48 bits of the seconds value and the upper 22 bits of the nanoseconds value are used. A signal (GTSUCOMP) is output from the core to indicate when the TSU timer count value is equal to the comparison value stored in the TSU timer comparison value registers (GMAC_NSC, GMAC_SCL, and GMAC_SCH). The GTSUCOMP signal can be routed to the Timer peripheral to automatically toggle pin TIOA11/PD21. This can be used as the reference clock for an external PLL to regenerate the audio clock in Ethernet AVB.An interrupt can also be generated (if enabled) when the TSU timer count value and comparison value are equal, mapped to bit 29 of the interrupt status register. 38.6.16 MAC 802.3 Pause Frame Support Note: Refer to the Clause 31, and Annex 31A and 31B of the IEEE standard 802.3 for a full description of MAC 802.3 pause operation. The following table shows the start of a MAC 802.3 pause frame. Table 38-14. Start of an 802.3 Pause Frame Address Type (MAC Control Frame) Pause Destination Source Opcode Time 0x0180C2000001 6 bytes 0x8808 0x0001 2 bytes SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 584

The GMAC supports both hardware controlled pause of the transmitter, upon reception of a pause frame, and hardware generated pause frame transmission. 38.6.16.1 802.3 Pause Frame Reception Bit 13 of the Network Configuration register is the pause enable control for reception. If this bit is set, transmission will pause if a non zero pause quantum frame is received. If a valid pause frame is received then the Pause Time register is updated with the new frame's pause time, regardless of whether a previous pause frame is active or not. An interrupt (either bit 12 or bit 13 of the Interrupt Status register) is triggered when a pause frame is received, but only if the interrupt has been enabled (bit 12 and bit 13 of the Interrupt Mask register). Pause frames received with non zero quantum are indicated through the interrupt bit 12 of the Interrupt Status register. Pause frames received with zero quantum are indicated on bit 13 of the Interrupt Status register. Once the Pause Time register is loaded and the frame currently being transmitted has been sent, no new frames are transmitted until the pause time reaches zero. The loading of a new pause time, and hence the pausing of transmission, only occurs when the GMAC is configured for full duplex operation. If the GMAC is configured for half duplex there will be no transmission pause, but the pause frame received interrupt will still be triggered. A valid pause frame is defined as having a destination address that matches either the address stored in Specific Address register 1 or if it matches the reserved address of 0x0180C2000001. It must also have the MAC control frame type ID of 0x8808 and have the pause opcode of 0x0001. Pause frames that have frame check sequence (FCS) or other errors will be treated as invalid and will be discarded. 802.3 Pause frames that are received after Priority-based Flow Control (PFC) has been negotiated will also be discarded. Valid pause frames received will increment the pause frames received statistic register. The pause time register decrements every 512 bit times once transmission has stopped. For test purposes, the retry test bit can be set (bit 12 in the Network Configuration register) which causes the Pause Time register to decrement every GTXCK cycle once transmission has stopped. The interrupt (bit 13 in the Interrupt Status register) is asserted whenever the Pause Time register decrements to zero (assuming it has been enabled by bit 13 in the Interrupt Mask register). This interrupt is also set when a zero quantum pause frame is received. 38.6.16.2 802.3 Pause Frame Transmission Automatic transmission of pause frames is supported through the transmit pause frame bits of the Network Control register. If either bit 11 or bit 12 of the Network Control register is written with logic 1, an 802.3 pause frame will be transmitted, providing full duplex is selected in the Network Configuration register and the transmit block is enabled in the Network Control register. Pause frame transmission will happen immediately if transmit is inactive or if transmit is active between the current frame and the next frame due to be transmitted. Transmitted pause frames comprise the following:

A destination address of 01-80-C2-00-00-01
A source address taken from Specific Address register 1
A type ID of 88-08 (MAC control frame)
A pause opcode of 00-01
A pause quantum register
Fill of 00 to take the frame to minimum frame length
Valid FCS The pause quantum used in the generated frame will depend on the trigger source for the frame as follows:
If bit 11 is written with a '1', the pause quantum will be taken from the Transmit Pause Quantum register. The Transmit Pause Quantum register resets to a value of 0xFFFF giving maximum pause quantum as default.
If bit 12 is written with a '1', the pause quantum will be zero. After transmission, a pause frame transmitted interrupt will be generated (bit 14 of the Interrupt Status register) and the only statistics register that will be incremented will be the Pause Frames Transmitted register. Pause frames can also be transmitted by the MAC using normal frame transmission methods. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 585

38.6.17 MAC PFC Priority-based Pause Frame Support

Note: Refer to the 802.1Qbb standard for a full description of priority-based pause operation. The following table shows the start of a Priority-based Flow Control (PFC) pause frame. Table 38-15. Start of a PFC Pause Frame Address Type (Mac Control Frame) Pause Opcode Priority Enable Vector Pause Time Destination Source 0x0180C2000001 6 bytes 0x8808 0x1001 2 bytes 8 × 2 bytes The GMAC supports PFC priority-based pause transmission and reception. Before PFC pause frames can be received, bit 16 of the Network Control register must be set.

38.6.17.1 PFC Pause Frame Reception

The ability to receive and decode priority-based pause frames is enabled by setting bit 16 of the Network Control register. When this bit is set, the GMAC will match either classic 802.3 pause frames or PFC priority-based pause frames. Once a priority-based pause frame has been received and matched, then from that moment on the GMAC will only match on priority-based pause frames (this is an 802.1Qbb requirement, known as PFC negotiation). Once priority-based pause has been negotiated, any received 802.3x format pause frames will not be acted upon. If a valid priority-based pause frame is received then the GMAC will decode the frame and determine which, if any, of the eight priorities require to be paused. Up to eight Pause Time registers are then updated with the eight pause times extracted from the frame regardless of whether a previous pause operation is active or not. An interrupt (either bit 12 or bit 13 of the Interrupt Status register) is triggered when a pause frame is received, but only if the interrupt has been enabled (bit 12 and bit 13 of the Interrupt Mask register). Pause frames received with non zero quantum are indicated through the interrupt bit 12 of the Interrupt Status register. Pause frames received with zero quantum are indicated on bit 13 of the Interrupt Status register. The loading of a new pause time only occurs when the GMAC is configured for full duplex operation. If the GMAC is configured for half duplex, the pause time counters will not be loaded, but the pause frame received interrupt will still be triggered. A valid pause frame is defined as having a destination address that matches either the address stored in Specific Address register 1 or if it matches the reserved address of 0x0180C2000001. It must also have the MAC control frame type ID of 0x8808 and have the pause opcode of 0x0101. Pause frames that have frame check sequence (FCS) or other errors will be treated as invalid and will be discarded. Valid pause frames received will increment the Pause Frames Received Statistic register. The Pause Time registers decrement every 512 bit times immediately following the PFC frame reception. For test purposes, the retry test bit can be set (bit 12 in the Network Configuration register) which causes the Pause Time register to decrement every GRXCK cycle once transmission has stopped. The interrupt (bit 13 in the Interrupt Status register) is asserted whenever the Pause Time register decrements to zero (assuming it has been enabled by bit 13 in the Interrupt Mask register). This interrupt is also set when a zero quantum pause frame is received.

38.6.17.2 PFC Pause Frame Transmission

Automatic transmission of pause frames is supported through the transmit priority-based pause frame bit of the Network Control register. If bit 17 of the Network Control register is written with logic 1, a PFC pause frame will be transmitted providing full duplex is selected in the Network Configuration register and the transmit block is enabled in the Network Control register. When bit 17 of the Network Control register is set, the fields of the priority-based pause frame will be built using the values stored in the Transmit PFC Pause register. Pause frame transmission will happen immediately if transmit is inactive or if transmit is active between the current frame and the next frame due to be transmitted. Transmitted pause frames comprise the following:

A destination address of 01-80-C2-00-00-01
A source address taken from Specific Address register 1
A type ID of 88-08 (MAC control frame)
A pause opcode of 01-01 SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 586

A priority enable vector taken from Transmit PFC Pause register
8 pause quantum registers
Fill of 00 to take the frame to minimum frame length
Valid FCS The pause quantum registers used in the generated frame will depend on the trigger source for the frame as follows:
If bit 17 of the Network Control register is written with a one, then the priority enable vector of the priority-based pause frame will be set equal to the value stored in the Transmit PFC Pause register [7:0]. For each entry equal to zero in the Transmit PFC Pause register [15:8], the pause quantum field of the pause frame associated with that entry will be taken from the transmit pause quantum register. For each entry equal to one in the Transmit PFC Pause register [15:8], the pause quantum associated with that entry will be zero.
The Transmit Pause Quantum register resets to a value of 0xFFFF giving maximum pause quantum as default. After transmission, a pause frame transmitted interrupt will be generated (bit 14 of the Interrupt Status register) and the only statistics register that will be incremented will be the Pause Frames Transmitted register. PFC Pause frames can also be transmitted by the MAC using normal frame transmission methods.

38.6.18 Energy Efficient Ethernet Support

Energy Efficient Ethernet according to IEEE 802.3az
A system’s transmit path can enter a low power mode if there is nothing to transmit.
A PHY can detect whether its link partner’s transmit path is in low power mode, and configure its own receive path to enter low power mode.
Link remains up during lower power mode and no frames are dropped.
Asymmetric, one direction can be in low power mode while the other is transmitting normally.
LPI (Low Power Idle) signaling is used to control entry and exit to and from low power modes. Note: LPI signaling can only take place if both sides have indicated support for it through auto-negotiation. Operation
Low power control is done at the MII (reconciliation sublayer).
As an architectural convenience in writing the 802.3az it is assumed that transmission is deferred by asserting carrier sense - in practice it will not be done this way. This system will know when it has nothing to transmit and only enter low power mode when it is not transmitting.
LPI should not be requested unless the link has been up for at least one second.
LPI is signaled on the MII transmit path by asserting 0x01 on txd with tx_en low and tx_er high.
A PHY on seeing LPI requested on the MII will send the sleep signal before going quiet. After going quiet it will periodically emit refresh signals.
The sleep, quiet and refresh periods are defined in 802.3az, Table 78-2.
LPI mode ends by transmitting normal idle for the wake time. There is a default time for this but it can be adjusted in software using the Link Layer Discovery Protocol (LLDP) described in 802.3az, Clause 79.
LPI is indicated at the receive side when sleep and refresh signaling has been detected. 38.6.19 802.1Qav Support - Credit-based Shaping A credit-based shaping algorithm is available on the two highest priority queues and is defined in the standard 802.1Qav: Forwarding and Queuing Enhancements for Time-Sensitive Streams. This allows traffic on these queues to be limited and to allow other queues to transmit. Traffic shaping is enabled via the CBS (Credit Based Shaping) Control register. This enables a counter which stores the amount of transmit 'credit', measured in bytes that a particular queue has. A queue may only transmit if it has non-negative credit. If a queue has data to send, but is held off from doing as another queue is transmitting, then credit will accumulate in the credit counter at the rate defined in the IdleSlope register (GMAC_CBSISQx) for that queue. portTransmitRate is the transmission rate, in bits per second, that the underlying MAC service that supports transmission through the Port provides. The value of this parameter is determined by the operation of the MAC. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 587

IdleSlope is the rate of change of increasing credit when waiting to transmit and must be less than the value of the portTransmitRate. IdleSlope is the rate of change of credit when waiting to transmit and must be less than the value of the portTransmitRate. The max value of IdleSlope (or sendSlope) is (portTransmitRate / bits_per_MII_Clock). In case of 100 Mbps, maximum IdleSlope = (100 Mbps / 4) = 0x17D7840. When this queue is transmitting the credit counter is decremented at the rate of sendSlope which is defined as (portTransmitRate - IdleSlope). A queue can accumulate negative credit when transmitting which will hold off any other transfers from that queue until credit returns to a non-negative value. No transfers are halted when a queue's credit becomes negative; it will accumulate negative credit until the transfer completes. The highest priority queue always has priority regardless of which queue has the most credit.

38.6.20 LPI Operation in the EMAC

It is best to use firmware to control LPI. LPI operation happens at the system level. Firmware gives maximum control and flexibility of operation. LPI operation is straightforward and firmware should be capable of responding within the required timeframes. Autonegotiation: 1. Indicate EEE capability using next page autonegotiation. For the transmit path: 1. If the link has been up for 1 second and there is nothing being transmitted, write to the TXLPIEN bit in the Network Control register. 2. Wake up by clearing the TXLPIEN bit in the Network Control register. For the receive path: 1. Enable RXLPISBC bit in GMAC_IER. The bit RXLPIS is set in Network Status Register triggering an interrupt. 2. Wait for an interrupt to indicate that LPI has been received. 3. Disable relevant parts of the receive path if desired. 4. The RXLPIS bit in Network Status Register gets cleared to indicate that regular idle has been received. This triggers an interrupt. 5. Re-enable the receive path.

38.6.21 PHY Interface

Different PHY interfaces are supported by the Ethernet MAC:

MII
RMII The MII interface is provided for 10/100 operation and uses txd[3:0] and rxd[3:0]. The RMII interface is provided for 10/100 operation and uses txd[1:0] and rxd[1:0]. 38.6.22 10/100 Operation The 10/100 Mbps speed bit in the Network Configuration register is used to select between 10 Mbps and 100 Mbps.

38.6.23 Jumbo Frames

The jumbo frames enable bit in the Network Configuration register allows the GMAC, in its default configuration, to receive jumbo frames up to 10240 bytes in size. This operation does not form part of the IEEE 802.3 specification and is normally disabled. When jumbo frames are enabled, frames received with a frame size greater than 10240 bytes are discarded. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 588

38.7 Programming Interface

38.7.1 Initialization

38.7.1.1 Configuration

Initialization of the GMAC configuration (e.g., loop back mode, frequency ratios) must be done while the transmit and receive circuits are disabled. See the description of the Network Control register and Network Configuration register earlier in this document. To change loop back mode, the following sequence of operations must be followed: 1. Write to Network Control register to disable transmit and receive circuits. 2. Write to Network Control register to change loop back mode. 3. Write to Network Control register to re-enable transmit or receive circuits. Note: These writes to the Network Control register cannot be combined in any way.

38.7.1.2 Receive Buffer List

Receive data is written to areas of data (i.e., buffers) in system memory. These buffers are listed in another data structure that also resides in main memory. This data structure (receive buffer queue) is a sequence of descriptor entries as defined in the table Receive Buffer Descriptor Entry. The Receive Buffer Queue Pointer register points to this data structure. Figure 38-3. Receive Buffer List Receive Buffer Queue Pointer (MAC Register) Receive Buffer 0 Receive Buffer 1 Receive Buffer N Receive Buffer Descriptor List (In memory) (In memory) To create the list of buffers: 1. Allocate a number (N) of buffers of X bytes in system memory, where X is the DMA buffer length programmed in the DMA Configuration register. 2. Allocate an area 8N bytes for the receive buffer descriptor list in system memory and create N entries in this list. Mark all entries in this list as owned by GMAC, i.e., bit 0 of word 0 set to 0. 3. Mark the last descriptor in the queue with the wrap bit (bit 1 in word 0 set to 1). 4. Write address of receive buffer descriptor list and control information to GMAC register receive buffer queue pointer 5. The receive circuits can then be enabled by writing to the address recognition registers and the Network Control register. Note: The queue pointers must be initialized and point to USED descriptors for all queues including those not intended for use.

38.7.1.3 Transmit Buffer List

Transmit data is read from areas of data (the buffers) in system memory. These buffers are listed in another data structure that also resides in main memory. This data structure (Transmit Buffer Queue) is a sequence of descriptor entries as defined in the table Transmit Buffer Descriptor Entry. The Transmit Buffer Queue Pointer register points to this data structure. To create this list of buffers: SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 589

Allocate a number (N) of buffers of between 1 and 2047 bytes of data to be transmitted in system memory. Up to 128 buffers per frame are allowed. 2. Allocate an area 8N bytes for the transmit buffer descriptor list in system memory and create N entries in this list. Mark all entries in this list as owned by GMAC, i.e., bit 31 of word 1 set to 0. 3. Mark the last descriptor in the queue with the wrap bit (bit 30 in word 1 set to 1). 4. Write address of transmit buffer descriptor list and control information to GMAC register transmit buffer queue pointer. 5. The transmit circuits can then be enabled by writing to the Network Control register. Note: The queue pointers must be initialized and point to USED descriptors for all queues including those not intended for use.

38.7.1.4 Address Matching

The GMAC Hash register pair and the four Specific Address register pairs must be written with the required values. Each register pair comprises of a bottom register and top register, with the bottom register being written first. The address matching is disabled for a particular register pair after the bottom register has been written and re-enabled when the top register is written. Each register pair may be written at any time, regardless of whether the receive circuits are enabled or disabled. As an example, to set Specific Address register 1 to recognize destination address 21:43:65:87:A9:CB, the following values are written to Specific Address register 1 bottom and Specific Address register 1 top:

Specific Address register 1 bottom bits 31:0 (0x98): 0x8765_4321.
Specific Address register 1 top bits 31:0 (0x9C): 0x0000_CBA9. Note: The address matching is the first level of filtering. If there is a match, the screeners are the next level of filtering for routing the data to the appropriate queue. See Priority Queueing in the DMA for more details.

38.7.1.5 PHY Maintenance

The PHY Maintenance register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit two is set in the Network Status register (about 2000 MCK cycles later when bits 18:16 are set to 010 in the Network Configuration register). An interrupt is generated as this bit is set. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each Management Data Clock (MDC) cycle. This causes the transmission of a PHY management frame on MDIO. Reading during the shift operation will return the current contents of the shift register. At the end of the management operation the bits will have shifted back to their original locations. For a read operation the data bits are updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced. The Management Data Clock (MDC) should not toggle faster than 2.5 MHz (minimum period of 400 ns), as defined by the IEEE 802.3 standard. MDC is generated by dividing down MCK. Three bits in the Network Configuration register determine by how much MCK should be divided to produce MDC.

38.7.1.6 Interrupts

There are 18 interrupt conditions that are detected within the GMAC. The conditions are ORed to make multiple interrupts. Depending on the overall system design this may be passed through a further level of interrupt collection (interrupt controller). On receipt of the interrupt signal, the CPU enters the interrupt handler. Refer to the device interrupt controller documentation to identify that it is the GMAC that is generating the interrupt. To ascertain which interrupt, read the Interrupt Status register. Note that in the default configuration this register will clear itself after being read, though this may be configured to be write-one-to-clear if desired. At reset all interrupts are disabled. To enable an interrupt, write to Interrupt Enable register with the pertinent interrupt bit set to 1. To disable an interrupt, write to Interrupt Disable register with the pertinent interrupt bit set to 1. To check whether an interrupt is enabled or disabled, read Interrupt Mask register. If the bit is set to 1, the interrupt is disabled.

38.7.1.7 Transmitting Frames

The procedure to set up a frame for transmission is the following: 1. Enable transmit in the Network Control register. 2. Allocate an area of system memory for transmit data. This does not have to be contiguous, varying byte lengths can be used if they conclude on byte borders. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 590

Set-up the transmit buffer list by writing buffer addresses to word zero of the transmit buffer descriptor entries and control and length to word one. 4. Write data for transmission into the buffers pointed to by the descriptors. 5. Write the address of the first buffer descriptor to transmit buffer descriptor queue pointer. 6. Enable appropriate interrupts. 7. Write to the transmit start bit (TSTART) in the Network Control register.

38.7.1.8 Receiving Frames

When a frame is received and the receive circuits are enabled, the GMAC checks the address and, in the following cases, the frame is written to system memory:

If it matches one of the four Specific Address registers.
If it matches one of the four type ID registers.
If it matches the hash address function.
If it is a broadcast address (0xFFFFFFFFFFFF) and broadcasts are allowed.
If the GMAC is configured to “copy all frames”. The register receive buffer queue pointer points to the next entry in the receive buffer descriptor list and the GMAC uses this as the address in system memory to write the frame to. Once the frame has been completely and successfully received and written to system memory, the GMAC then updates the receive buffer descriptor entry (see Receive Buffer Descriptor Entry) with the reason for the address match and marks the area as being owned by software. Once this is complete, a receive complete interrupt is set. Software is then responsible for copying the data to the application area and releasing the buffer (by writing the ownership bit back to 0). If the GMAC is unable to write the data at a rate to match the incoming frame, then a receive overrun interrupt is set. If there is no receive buffer available, i.e., the next buffer is still owned by software, a receive buffer not available interrupt is set. If the frame is not successfully received, a statistics register is incremented and the frame is discarded without informing software.

38.7.2 Statistics Registers

Statistics registers are described in the User Interface beginning with GMAC Octets Transmitted Low Register and ending with GMAC UDP Checksum Errors Register. The statistics register block begins at 0x100 and runs to 0x1B0, and comprises the registers listed below. Octets Transmitted Low Register Broadcast Frames Received Register Octets Transmitted High Register Multicast Frames Received Register Frames Transmitted Register Pause Frames Received Register Broadcast Frames Transmitted Register 64 Byte Frames Received Register Multicast Frames Transmitted Register 65 to 127 Byte Frames Received Register Pause Frames Transmitted Register 128 to 255 Byte Frames Received Register

64 Byte Frames Transmitted Register 256 to 511 Byte Frames Received Register

65 to 127 Byte Frames Transmitted Register 512 to 1023 Byte Frames Received Register 128 to 255 Byte Frames Transmitted Register 1024 to 1518 Byte Frames Received Register 256 to 511 Byte Frames Transmitted Register 1519 to Maximum Byte Frames Received Register 512 to 1023 Byte Frames Transmitted Register Undersize Frames Received Register 1024 to 1518 Byte Frames Transmitted Register Oversize Frames Received Register Greater Than 1518 Byte Frames Transmitted Register Jabbers Received Register Transmit Underruns Register Frame Check Sequence Errors Register SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 591

Single Collision Frames Register Length Field Frame Errors Register Multiple Collision Frames Register Receive Symbol Errors Register Excessive Collisions Register Alignment Errors Register Late Collisions Register Receive Resource Errors Register Deferred Transmission Frames Register Receive Overrun Register Carrier Sense Errors Register IP Header Checksum Errors Register Octets Received Low Register TCP Checksum Errors Register Octets Received High Register UDP Checksum Errors Register Frames Received Register These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit (RXEN) is set in the Network Control register. Once a statistics register has been read, it is automatically cleared. When reading the Octets Transmitted and Octets Received registers, bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 592

38.8 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 GMAC_NCR 7:0 WESTAT INCSTAT CLRSTAT MPE TXEN RXEN LBL 15:8 SRTSM TXZQPF TXPF THALT TSTART BP 23:16 FNP TXPBPF ENPBPR 31:24 0x04 GMAC_NCFGR 7:0 UNIHEN MTIHEN NBC CAF JFRAME DNVLAN FD SPD 15:8 RXBUFO[1:0] PEN RTY MAXFS 23:16 DCPF DBW[1:0] CLK[2:0] RFCS LFERD 31:24 IRXER RXBP IPGSEN IRXFCS EFRHD RXCOEN 0x08 GMAC_NSR 7:0 IDLE MDIO 15:8 23:16 31:24 0x0C GMAC_UR 7:0 15:8 23:16 31:24 0x10 GMAC_DCFGR 7:0 ESPA ESMA FBLDO[4:0] 15:8 TXCOEN TXPBMS RXBMS[1:0] 23:16 DRBS[7:0] 31:24 DDRP 0x14 GMAC_TSR 7:0 TXCOMP TFC TXGO RLE COL UBR 15:8 HRESP 23:16 31:24 0x18 GMAC_RBQB 7:0 ADDR[5:0] 15:8 ADDR[13:6] 23:16 ADDR[21:14] 31:24 ADDR[29:22] 0x1C GMAC_TBQB 7:0 ADDR[5:0] 15:8 ADDR[13:6] 23:16 ADDR[21:14] 31:24 ADDR[29:22] 0x20 GMAC_RSR 7:0 HNO RXOVR REC BNA 15:8 23:16 31:24 0x24 GMAC_ISR 7:0 TCOMP TFC RLEX TUR TXUBR RXUBR RCOMP MFS 15:8 PFTR PTZ PFNZ HRESP ROVR 23:16 PDRSFR PDRQFR SFT DRQFT SFR DRQFR 31:24 TSUTIMCMP WOL RXLPISBC SRI PDRSFT PDRQFT 0x28 GMAC_IER 7:0 TCOMP TFC RLEX TUR TXUBR RXUBR RCOMP MFS 15:8 EXINT PFTR PTZ PFNZ HRESP ROVR 23:16 PDRSFR PDRQFR SFT DRQFT SFR DRQFR 31:24 TSUTIMCMP WOL RXLPISBC SRI PDRSFT PDRQFT 0x2C GMAC_IDR 7:0 TCOMP TFC RLEX TUR TXUBR RXUBR RCOMP MFS 15:8 EXINT PFTR PTZ PFNZ HRESP ROVR 23:16 PDRSFR PDRQFR SFT DRQFT SFR DRQFR 31:24 TSUTIMCMP WOL RXLPISBC SRI PDRSFT PDRQFT 0x30 GMAC_IMR 7:0 TCOMP TFC RLEX TUR TXUBR RXUBR RCOMP MFS 15:8 EXINT PFTR PTZ PFNZ HRESP ROVR 23:16 PDRSFR PDRQFR SFT DRQFT SFR DRQFR 31:24 TSUTIMCMP WOL RXLPISBC SRI PDRSFT PDRQFT 0x34 GMAC_MAN 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 PHYA[0] REGA[4:0] WTN[1:0] 31:24 WZO CLTTO OP[1:0] PHYA[4:1] SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 593

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x38 GMAC_RPQ 7:0 RPQ[7:0] 15:8 RPQ[15:8] 23:16 31:24 0x3C GMAC_TPQ 7:0 TPQ[7:0] 15:8 TPQ[15:8] 23:16 31:24 0x40 GMAC_TPSF 7:0 TPB1ADR[7:0] 15:8 TPB1ADR[11:8] 23:16 31:24 ENTXP 0x44 GMAC_RPSF 7:0 RPB1ADR[7:0] 15:8 RPB1ADR[11:8] 23:16 31:24 ENRXP 0x48 GMAC_RJFML 7:0 FML[7:0] 15:8 FML[13:8] 23:16 31:24 0x4C ... 0x7F Reserved 0x80 GMAC_HRB 7:0 ADDR[7:0] 15:8 ADDR[15:8] 23:16 ADDR[23:16] 31:24 ADDR[31:24] 0x84 GMAC_HRT 7:0 ADDR[7:0] 15:8 ADDR[15:8] 23:16 ADDR[23:16] 31:24 ADDR[31:24] 0x88 GMAC_SAB1 7:0 ADDR[7:0] 15:8 ADDR[15:8] 23:16 ADDR[23:16] 31:24 ADDR[31:24] 0x8C GMAC_SAT1 7:0 ADDR[7:0] 15:8 ADDR[15:8] 23:16 31:24 0x90 GMAC_SAB2 7:0 ADDR[7:0] 15:8 ADDR[15:8] 23:16 ADDR[23:16] 31:24 ADDR[31:24] 0x94 GMAC_SAT2 7:0 ADDR[7:0] 15:8 ADDR[15:8] 23:16 31:24 0x98 GMAC_SAB3 7:0 ADDR[7:0] 15:8 ADDR[15:8] 23:16 ADDR[23:16] 31:24 ADDR[31:24] 0x9C GMAC_SAT3 7:0 ADDR[7:0] 15:8 ADDR[15:8] 23:16 31:24 0xA0 GMAC_SAB4 7:0 ADDR[7:0] 15:8 ADDR[15:8] 23:16 ADDR[23:16] 31:24 ADDR[31:24] SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 594

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0xA4 GMAC_SAT4 7:0 ADDR[7:0] 15:8 ADDR[15:8] 23:16 31:24 0xA8 GMAC_TIDM1 7:0 TID[7:0] 15:8 TID[15:8] 23:16 31:24 ENIDn 0xAC GMAC_TIDM2 7:0 TID[7:0] 15:8 TID[15:8] 23:16 31:24 ENIDn 0xB0 GMAC_TIDM3 7:0 TID[7:0] 15:8 TID[15:8] 23:16 31:24 ENIDn 0xB4 GMAC_TIDM4 7:0 TID[7:0] 15:8 TID[15:8] 23:16 31:24 ENIDn 0xB8 GMAC_WOL 7:0 IP[7:0] 15:8 IP[15:8] 23:16 MTI SA1 ARP MAG 31:24 0xBC GMAC_IPGS 7:0 FL[7:0] 15:8 FL[15:8] 23:16 31:24 0xC0 GMAC_SVLAN 7:0 VLAN_TYPE[7:0] 15:8 VLAN_TYPE[15:8] 23:16 31:24 ESVLAN 0xC4 GMAC_TPFCP 7:0 PEV[7:0] 15:8 PQ[7:0] 23:16 31:24 0xC8 GMAC_SAMB1 7:0 ADDR[7:0] 15:8 ADDR[15:8] 23:16 ADDR[23:16] 31:24 ADDR[31:24] 0xCC GMAC_SAMT1 7:0 ADDR[7:0] 15:8 ADDR[15:8] 23:16 31:24 0xD0 ... 0xDB Reserved 0xDC GMAC_NSC 7:0 NANOSEC[7:0] 15:8 NANOSEC[15:8] 23:16 NANOSEC[21:16] 31:24 0xE0 GMAC_SCL 7:0 SEC[7:0] 15:8 SEC[15:8] 23:16 SEC[23:16] 31:24 SEC[31:24] 0xE4 GMAC_SCH 7:0 SEC[7:0] 15:8 SEC[15:8] 23:16 31:24 SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 595

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0xE8 GMAC_EFTSH 7:0 RUD[7:0] 15:8 RUD[15:8] 23:16 31:24 0xEC GMAC_EFRSH 7:0 RUD[7:0] 15:8 RUD[15:8] 23:16 31:24 0xF0 GMAC_PEFTSH 7:0 RUD[7:0] 15:8 RUD[15:8] 23:16 31:24 0xF4 GMAC_PEFRSH 7:0 RUD[7:0] 15:8 RUD[15:8] 23:16 31:24 0xF8 ... 0xFF Reserved 0x0100 GMAC_OTLO 7:0 TXO[7:0] 15:8 TXO[15:8] 23:16 TXO[23:16] 31:24 TXO[31:24] 0x0104 GMAC_OTHI 7:0 TXO[7:0] 15:8 TXO[15:8] 23:16 31:24 0x0108 GMAC_FT 7:0 FTX[7:0] 15:8 FTX[15:8] 23:16 FTX[23:16] 31:24 FTX[31:24] 0x010C GMAC_BCFT 7:0 BFTX[7:0] 15:8 BFTX[15:8] 23:16 BFTX[23:16] 31:24 BFTX[31:24] 0x0110 GMAC_MFT 7:0 MFTX[7:0] 15:8 MFTX[15:8] 23:16 MFTX[23:16] 31:24 MFTX[31:24] 0x0114 GMAC_PFT 7:0 PFTX[7:0] 15:8 PFTX[15:8] 23:16 31:24 0x0118 GMAC_BFT64 7:0 NFTX[7:0] 15:8 NFTX[15:8] 23:16 NFTX[23:16] 31:24 NFTX[31:24] 0x011C GMAC_TBFT127 7:0 NFTX[7:0] 15:8 NFTX[15:8] 23:16 NFTX[23:16] 31:24 NFTX[31:24] 0x0120 GMAC_TBFT255 7:0 NFTX[7:0] 15:8 NFTX[15:8] 23:16 NFTX[23:16] 31:24 NFTX[31:24] 0x0124 GMAC_TBFT511 7:0 NFTX[7:0] 15:8 NFTX[15:8] 23:16 NFTX[23:16] 31:24 NFTX[31:24] SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 596

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x0128 GMAC_TBFT1023 7:0 NFTX[7:0] 15:8 NFTX[15:8] 23:16 NFTX[23:16] 31:24 NFTX[31:24] 0x012C GMAC_TBFT1518 7:0 NFTX[7:0] 15:8 NFTX[15:8] 23:16 NFTX[23:16] 31:24 NFTX[31:24] 0x0130 GMAC_GTBFT1518 7:0 NFTX[7:0] 15:8 NFTX[15:8] 23:16 NFTX[23:16] 31:24 NFTX[31:24] 0x0134 GMAC_TUR 7:0 TXUNR[7:0] 15:8 TXUNR[9:8] 23:16 31:24 0x0138 GMAC_SCF 7:0 SCOL[7:0] 15:8 SCOL[15:8] 23:16 SCOL[17:16] 31:24 0x013C GMAC_MCF 7:0 MCOL[7:0] 15:8 MCOL[15:8] 23:16 MCOL[17:16] 31:24 0x0140 GMAC_EC 7:0 XCOL[7:0] 15:8 XCOL[9:8] 23:16 31:24 0x0144 GMAC_LC 7:0 LCOL[7:0] 15:8 LCOL[9:8] 23:16 31:24 0x0148 GMAC_DTF 7:0 DEFT[7:0] 15:8 DEFT[15:8] 23:16 DEFT[17:16] 31:24 0x014C GMAC_CSE 7:0 CSR[7:0] 15:8 CSR[9:8] 23:16 31:24 0x0150 GMAC_ORLO 7:0 RXO[7:0] 15:8 RXO[15:8] 23:16 RXO[23:16] 31:24 RXO[31:24] 0x0154 GMAC_ORHI 7:0 RXO[7:0] 15:8 RXO[15:8] 23:16 31:24 0x0158 GMAC_FR 7:0 FRX[7:0] 15:8 FRX[15:8] 23:16 FRX[23:16] 31:24 FRX[31:24] 0x015C GMAC_BCFR 7:0 BFRX[7:0] 15:8 BFRX[15:8] 23:16 BFRX[23:16] 31:24 BFRX[31:24] SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 597

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x0160 GMAC_MFR 7:0 MFRX[7:0] 15:8 MFRX[15:8] 23:16 MFRX[23:16] 31:24 MFRX[31:24] 0x0164 GMAC_PFR 7:0 PFRX[7:0] 15:8 PFRX[15:8] 23:16 31:24 0x0168 GMAC_BFR64 7:0 NFRX[7:0] 15:8 NFRX[15:8] 23:16 NFRX[23:16] 31:24 NFRX[31:24] 0x016C GMAC_TBFR127 7:0 NFRX[7:0] 15:8 NFRX[15:8] 23:16 NFRX[23:16] 31:24 NFRX[31:24] 0x0170 GMAC_TBFR255 7:0 NFRX[7:0] 15:8 NFRX[15:8] 23:16 NFRX[23:16] 31:24 NFRX[31:24] 0x0174 GMAC_TBFR511 7:0 NFRX[7:0] 15:8 NFRX[15:8] 23:16 NFRX[23:16] 31:24 NFRX[31:24] 0x0178 GMAC_TBFR1023 7:0 NFRX[7:0] 15:8 NFRX[15:8] 23:16 NFRX[23:16] 31:24 NFRX[31:24] 0x017C GMAC_TBFR1518 7:0 NFRX[7:0] 15:8 NFRX[15:8] 23:16 NFRX[23:16] 31:24 NFRX[31:24] 0x0180 GMAC_TMXBFR 7:0 NFRX[7:0] 15:8 NFRX[15:8] 23:16 NFRX[23:16] 31:24 NFRX[31:24] 0x0184 GMAC_UFR 7:0 UFRX[7:0] 15:8 UFRX[9:8] 23:16 31:24 0x0188 GMAC_OFR 7:0 OFRX[7:0] 15:8 OFRX[9:8] 23:16 31:24 0x018C GMAC_JR 7:0 JRX[7:0] 15:8 JRX[9:8] 23:16 31:24 0x0190 GMAC_FCSE 7:0 FCKR[7:0] 15:8 FCKR[9:8] 23:16 31:24 0x0194 GMAC_LFFE 7:0 LFER[7:0] 15:8 LFER[9:8] 23:16 31:24 SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 598

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x0198 GMAC_RSE 7:0 RXSE[7:0] 15:8 RXSE[9:8] 23:16 31:24 0x019C GMAC_AE 7:0 AER[7:0] 15:8 AER[9:8] 23:16 31:24 0x01A0 GMAC_RRE 7:0 RXRER[7:0] 15:8 RXRER[15:8] 23:16 RXRER[17:16] 31:24 0x01A4 GMAC_ROE 7:0 RXOVR[7:0] 15:8 RXOVR[9:8] 23:16 31:24 0x01A8 GMAC_IHCE 7:0 HCKER[7:0] 15:8 23:16 31:24 0x01AC GMAC_TCE 7:0 TCKER[7:0] 15:8 23:16 31:24 0x01B0 GMAC_UCE 7:0 UCKER[7:0] 15:8 23:16 31:24 0x01B4 ... 0x01BB Reserved 0x01BC GMAC_TISUBN 7:0 LSBTIR[7:0] 15:8 LSBTIR[15:8] 23:16 31:24 0x01C0 GMAC_TSH 7:0 TCS[7:0] 15:8 TCS[15:8] 23:16 31:24 0x01C4 ... 0x01CF Reserved 0x01D0 GMAC_TSL 7:0 TCS[7:0] 15:8 TCS[15:8] 23:16 TCS[23:16] 31:24 TCS[31:24] 0x01D4 GMAC_TN 7:0 TNS[7:0] 15:8 TNS[15:8] 23:16 TNS[23:16] 31:24 TNS[29:24] 0x01D8 GMAC_TA 7:0 ITDT[7:0] 15:8 ITDT[15:8] 23:16 ITDT[23:16] 31:24 ADJ ITDT[29:24] 0x01DC GMAC_TI 7:0 CNS[7:0] 15:8 ACNS[7:0] 23:16 NIT[7:0] 31:24 SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 599

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x01E0 GMAC_EFTSL 7:0 RUD[7:0] 15:8 RUD[15:8] 23:16 RUD[23:16] 31:24 RUD[31:24] 0x01E4 GMAC_EFTN 7:0 RUD[7:0] 15:8 RUD[15:8] 23:16 RUD[23:16] 31:24 RUD[29:24] 0x01E8 GMAC_EFRSL 7:0 RUD[7:0] 15:8 RUD[15:8] 23:16 RUD[23:16] 31:24 RUD[31:24] 0x01EC GMAC_EFRN 7:0 RUD[7:0] 15:8 RUD[15:8] 23:16 RUD[23:16] 31:24 RUD[29:24] 0x01F0 GMAC_PEFTSL 7:0 RUD[7:0] 15:8 RUD[15:8] 23:16 RUD[23:16] 31:24 RUD[31:24] 0x01F4 GMAC_PEFTN 7:0 RUD[7:0] 15:8 RUD[15:8] 23:16 RUD[23:16] 31:24 RUD[29:24] 0x01F8 GMAC_PEFRSL 7:0 RUD[7:0] 15:8 RUD[15:8] 23:16 RUD[23:16] 31:24 RUD[31:24] 0x01FC GMAC_PEFRN 7:0 RUD[7:0] 15:8 RUD[15:8] 23:16 RUD[23:16] 31:24 RUD[29:24] 0x0200 ... 0x026F Reserved 0x0270 GMAC_RXLPI 7:0 COUNT[7:0] 15:8 COUNT[15:8] 23:16 31:24 0x0274 GMAC_RXLPITIME 7:0 LPITIME[7:0] 15:8 LPITIME[15:8] 23:16 LPITIME[23:16] 31:24 0x0278 GMAC_TXLPI 7:0 COUNT[7:0] 15:8 COUNT[15:8] 23:16 COUNT[23:16] 31:24 0x027C GMAC_TXLPITIME 7:0 LPITIME[7:0] 15:8 LPITIME[15:8] 23:16 LPITIME[23:16] 31:24 0x0280 ... 0x03FF Reserved 0x0400 GMAC_ISRPQ1 7:0 TCOMP TFC RLEX RXUBR RCOMP 15:8 HRESP ROVR 23:16 31:24 SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 600

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x0404 GMAC_ISRPQ2 7:0 TCOMP TFC RLEX RXUBR RCOMP 15:8 HRESP ROVR 23:16 31:24 0x0408 GMAC_ISRPQ3 7:0 TCOMP TFC RLEX RXUBR RCOMP 15:8 HRESP ROVR 23:16 31:24 0x040C GMAC_ISRPQ4 7:0 TCOMP TFC RLEX RXUBR RCOMP 15:8 HRESP ROVR 23:16 31:24 0x0410 GMAC_ISRPQ5 7:0 TCOMP TFC RLEX RXUBR RCOMP 15:8 HRESP ROVR 23:16 31:24 0x0414 ... 0x043F Reserved 0x0440 GMAC_TBQBAPQ1 7:0 TXBQBA[5:0] 15:8 TXBQBA[13:6] 23:16 TXBQBA[21:14] 31:24 TXBQBA[29:22] 0x0444 GMAC_TBQBAPQ2 7:0 TXBQBA[5:0] 15:8 TXBQBA[13:6] 23:16 TXBQBA[21:14] 31:24 TXBQBA[29:22] 0x0448 GMAC_TBQBAPQ3 7:0 TXBQBA[5:0] 15:8 TXBQBA[13:6] 23:16 TXBQBA[21:14] 31:24 TXBQBA[29:22] 0x044C GMAC_TBQBAPQ4 7:0 TXBQBA[5:0] 15:8 TXBQBA[13:6] 23:16 TXBQBA[21:14] 31:24 TXBQBA[29:22] 0x0450 GMAC_TBQBAPQ5 7:0 TXBQBA[5:0] 15:8 TXBQBA[13:6] 23:16 TXBQBA[21:14] 31:24 TXBQBA[29:22] 0x0454 ... 0x047F Reserved 0x0480 GMAC_RBQBAPQ1 7:0 RXBQBA[5:0] 15:8 RXBQBA[13:6] 23:16 RXBQBA[21:14] 31:24 RXBQBA[29:22] 0x0484 GMAC_RBQBAPQ2 7:0 RXBQBA[5:0] 15:8 RXBQBA[13:6] 23:16 RXBQBA[21:14] 31:24 RXBQBA[29:22] 0x0488 GMAC_RBQBAPQ3 7:0 RXBQBA[5:0] 15:8 RXBQBA[13:6] 23:16 RXBQBA[21:14] 31:24 RXBQBA[29:22] 0x048C GMAC_RBQBAPQ4 7:0 RXBQBA[5:0] 15:8 RXBQBA[13:6] 23:16 RXBQBA[21:14] 31:24 RXBQBA[29:22] SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 601

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x0490 GMAC_RBQBAPQ5 7:0 RXBQBA[5:0] 15:8 RXBQBA[13:6] 23:16 RXBQBA[21:14] 31:24 RXBQBA[29:22] 0x0494 ... 0x049F Reserved 0x04A0 GMAC_RBSRPQ1 7:0 RBS[7:0] 15:8 RBS[15:8] 23:16 31:24 0x04A4 GMAC_RBSRPQ2 7:0 RBS[7:0] 15:8 RBS[15:8] 23:16 31:24 0x04A8 GMAC_RBSRPQ3 7:0 RBS[7:0] 15:8 RBS[15:8] 23:16 31:24 0x04AC GMAC_RBSRPQ4 7:0 RBS[7:0] 15:8 RBS[15:8] 23:16 31:24 0x04B0 GMAC_RBSRPQ5 7:0 RBS[7:0] 15:8 RBS[15:8] 23:16 31:24 0x04B4 ... 0x04BB Reserved 0x04BC GMAC_CBSCR 7:0 QAE QBE 15:8 23:16 31:24 0x04C0 GMAC_CBSISQA 7:0 IS[7:0] 15:8 IS[15:8] 23:16 IS[23:16] 31:24 IS[31:24] 0x04C4 GMAC_CBSISQB 7:0 IS[7:0] 15:8 IS[15:8] 23:16 IS[23:16] 31:24 IS[31:24] 0x04C8 ... 0x04FF Reserved 0x0500 GMAC_ST1RPQ0 7:0 DSTCM[3:0] QNB[2:0] 15:8 UDPM[3:0] DSTCM[7:4] 23:16 UDPM[11:4] 31:24 UDPE DSTCE UDPM[15:12] 0x0504 GMAC_ST1RPQ1 7:0 DSTCM[3:0] QNB[2:0] 15:8 UDPM[3:0] DSTCM[7:4] 23:16 UDPM[11:4] 31:24 UDPE DSTCE UDPM[15:12] 0x0508 GMAC_ST1RPQ2 7:0 DSTCM[3:0] QNB[2:0] 15:8 UDPM[3:0] DSTCM[7:4] 23:16 UDPM[11:4] 31:24 UDPE DSTCE UDPM[15:12] SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 602

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x050C GMAC_ST1RPQ3 7:0 DSTCM[3:0] QNB[2:0] 15:8 UDPM[3:0] DSTCM[7:4] 23:16 UDPM[11:4] 31:24 UDPE DSTCE UDPM[15:12] 0x0510 ... 0x053F Reserved 0x0540 GMAC_ST2RPQ0 7:0 VLANP[2:0] QNB[2:0] 15:8 COMPA[2:0] ETHE I2ETH[2:0] VLANE 23:16 COMPB[4:0] COMPAE COMPA[4:3] 31:24 COMPCE COMPC[4:0] COMPBE 0x0544 GMAC_ST2RPQ1 7:0 VLANP[2:0] QNB[2:0] 15:8 COMPA[2:0] ETHE I2ETH[2:0] VLANE 23:16 COMPB[4:0] COMPAE COMPA[4:3] 31:24 COMPCE COMPC[4:0] COMPBE 0x0548 GMAC_ST2RPQ2 7:0 VLANP[2:0] QNB[2:0] 15:8 COMPA[2:0] ETHE I2ETH[2:0] VLANE 23:16 COMPB[4:0] COMPAE COMPA[4:3] 31:24 COMPCE COMPC[4:0] COMPBE 0x054C GMAC_ST2RPQ3 7:0 VLANP[2:0] QNB[2:0] 15:8 COMPA[2:0] ETHE I2ETH[2:0] VLANE 23:16 COMPB[4:0] COMPAE COMPA[4:3] 31:24 COMPCE COMPC[4:0] COMPBE 0x0550 GMAC_ST2RPQ4 7:0 VLANP[2:0] QNB[2:0] 15:8 COMPA[2:0] ETHE I2ETH[2:0] VLANE 23:16 COMPB[4:0] COMPAE COMPA[4:3] 31:24 COMPCE COMPC[4:0] COMPBE 0x0554 GMAC_ST2RPQ5 7:0 VLANP[2:0] QNB[2:0] 15:8 COMPA[2:0] ETHE I2ETH[2:0] VLANE 23:16 COMPB[4:0] COMPAE COMPA[4:3] 31:24 COMPCE COMPC[4:0] COMPBE 0x0558 GMAC_ST2RPQ6 7:0 VLANP[2:0] QNB[2:0] 15:8 COMPA[2:0] ETHE I2ETH[2:0] VLANE 23:16 COMPB[4:0] COMPAE COMPA[4:3] 31:24 COMPCE COMPC[4:0] COMPBE 0x055C GMAC_ST2RPQ7 7:0 VLANP[2:0] QNB[2:0] 15:8 COMPA[2:0] ETHE I2ETH[2:0] VLANE 23:16 COMPB[4:0] COMPAE COMPA[4:3] 31:24 COMPCE COMPC[4:0] COMPBE 0x0560 ... 0x05FF Reserved 0x0600 GMAC_IERPQ1 7:0 TCOMP TFC RLEX RXUBR RCOMP 15:8 HRESP ROVR 23:16 31:24 0x0604 GMAC_IERPQ2 7:0 TCOMP TFC RLEX RXUBR RCOMP 15:8 HRESP ROVR 23:16 31:24 0x0608 GMAC_IERPQ3 7:0 TCOMP TFC RLEX RXUBR RCOMP 15:8 HRESP ROVR 23:16 31:24 0x060C GMAC_IERPQ4 7:0 TCOMP TFC RLEX RXUBR RCOMP 15:8 HRESP ROVR 23:16 31:24 SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 603

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x0610 GMAC_IERPQ5 7:0 TCOMP TFC RLEX RXUBR RCOMP 15:8 HRESP ROVR 23:16 31:24 0x0614 ... 0x061F Reserved 0x0620 GMAC_IDRPQ1 7:0 TCOMP TFC RLEX RXUBR RCOMP 15:8 HRESP ROVR 23:16 31:24 0x0624 GMAC_IDRPQ2 7:0 TCOMP TFC RLEX RXUBR RCOMP 15:8 HRESP ROVR 23:16 31:24 0x0628 GMAC_IDRPQ3 7:0 TCOMP TFC RLEX RXUBR RCOMP 15:8 HRESP ROVR 23:16 31:24 0x062C GMAC_IDRPQ4 7:0 TCOMP TFC RLEX RXUBR RCOMP 15:8 HRESP ROVR 23:16 31:24 0x0630 GMAC_IDRPQ5 7:0 TCOMP TFC RLEX RXUBR RCOMP 15:8 HRESP ROVR 23:16 31:24 0x0634 ... 0x063F Reserved 0x0640 GMAC_IMRPQ1 7:0 TCOMP AHB RLEX RXUBR RCOMP 15:8 HRESP ROVR 23:16 31:24 0x0644 GMAC_IMRPQ2 7:0 TCOMP AHB RLEX RXUBR RCOMP 15:8 HRESP ROVR 23:16 31:24 0x0648 GMAC_IMRPQ3 7:0 TCOMP AHB RLEX RXUBR RCOMP 15:8 HRESP ROVR 23:16 31:24 0x064C GMAC_IMRPQ4 7:0 TCOMP AHB RLEX RXUBR RCOMP 15:8 HRESP ROVR 23:16 31:24 0x0650 GMAC_IMRPQ5 7:0 TCOMP AHB RLEX RXUBR RCOMP 15:8 HRESP ROVR 23:16 31:24 0x0654 ... 0x06DF Reserved 0x06E0 GMAC_ST2ER0 7:0 COMPVAL[7:0] 15:8 COMPVAL[15:8] 23:16 31:24 SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 604

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x06E4 GMAC_ST2ER1 7:0 COMPVAL[7:0] 15:8 COMPVAL[15:8] 23:16 31:24 0x06E8 GMAC_ST2ER2 7:0 COMPVAL[7:0] 15:8 COMPVAL[15:8] 23:16 31:24 0x06EC GMAC_ST2ER3 7:0 COMPVAL[7:0] 15:8 COMPVAL[15:8] 23:16 31:24 0x06F0 ... 0x06FF Reserved 0x0700 GMAC_ST2CW00 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x0704 GMAC_ST2CW10 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x0708 GMAC_ST2CW01 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x070C GMAC_ST2CW11 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x0710 GMAC_ST2CW02 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x0714 GMAC_ST2CW12 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x0718 GMAC_ST2CW03 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x071C GMAC_ST2CW13 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x0720 GMAC_ST2CW04 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x0724 GMAC_ST2CW14 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x0728 GMAC_ST2CW05 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 605

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x072C GMAC_ST2CW15 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x0730 GMAC_ST2CW06 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x0734 GMAC_ST2CW16 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x0738 GMAC_ST2CW07 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x073C GMAC_ST2CW17 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x0740 GMAC_ST2CW08 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x0744 GMAC_ST2CW18 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x0748 GMAC_ST2CW09 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x074C GMAC_ST2CW19 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x0750 GMAC_ST2CW010 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x0754 GMAC_ST2CW110 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x0758 GMAC_ST2CW011 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x075C GMAC_ST2CW111 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x0760 GMAC_ST2CW012 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 606

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x0764 GMAC_ST2CW112 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x0768 GMAC_ST2CW013 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x076C GMAC_ST2CW113 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x0770 GMAC_ST2CW014 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x0774 GMAC_ST2CW114 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x0778 GMAC_ST2CW015 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x077C GMAC_ST2CW115 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x0780 GMAC_ST2CW016 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x0784 GMAC_ST2CW116 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x0788 GMAC_ST2CW017 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x078C GMAC_ST2CW117 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x0790 GMAC_ST2CW018 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x0794 GMAC_ST2CW118 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x0798 GMAC_ST2CW019 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 607

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x079C GMAC_ST2CW119 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x07A0 GMAC_ST2CW020 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x07A4 GMAC_ST2CW120 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x07A8 GMAC_ST2CW021 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x07AC GMAC_ST2CW121 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x07B0 GMAC_ST2CW022 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x07B4 GMAC_ST2CW122 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 0x07B8 GMAC_ST2CW023 7:0 MASKVAL[7:0] 15:8 MASKVAL[15:8] 23:16 COMPVAL[7:0] 31:24 COMPVAL[15:8] 0x07BC GMAC_ST2CW123 7:0 OFFSSTRT[0] OFFSVAL[6:0] 15:8 OFFSSTRT[1] 23:16 31:24 SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 608

38.8.1 GMAC Network Control Register

Name: GMAC_NCR Offset: 0x000 Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 FNP TXPBPF ENPBPR Access R/W R/W R/W Reset 0 0 0 Bit 15 14 13 12 11 10 9 8 SRTSM TXZQPF TXPF THALT TSTART BP Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WESTAT INCSTAT CLRSTAT MPE TXEN RXEN LBL Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 18 – FNP Flush Next Packet Writing a '1' to this bit will flush the next packet from the external RX DPRAM. Flushing the next packet will only take effect if the DMA is not currently writing a packet already stored in the DPRAM to memory. Bit 17 – TXPBPF Transmit PFC Priority-based Pause Frame Takes the values stored in the Transmit PFC Pause Register. Bit 16 – ENPBPR Enable PFC Priority-based Pause Reception Writing a '1' to this bit enables PFC Priority Based Pause Reception capabilities, enabling PFC negotiation and recognition of priority-based pause frames. Value Description

0 Normal operation

1 PFC Priority-based Pause frames are recognized. Bit 15 – SRTSM Store Receive Time Stamp to Memory Writing a '1' to this bit causes the CRC of every received frame to be replaced with the value of the nanoseconds field of the 1588 timer that was captured as the receive frame passed the message time stamp point. Note that bit RFCS in register GMAC_NCFGR may not be set to 1 when the timer should be captured. Value Description 1 All received frames' CRC is replaced with a time stamp. Bit 12 – TXZQPF Transmit Zero Quantum Pause Frame Writing a '1' to this bit causes a pause frame with zero quantum to be transmitted. Writing a '0' to this bit has no effect. Bit 11 – TXPF Transmit Pause Frame Writing one to this bit causes a pause frame to be transmitted. Writing a '0' to this bit has no effect. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 609

Bit 10 – THALT Transmit Halt Writing a '1' to this bit halts transmission as soon as any ongoing frame transmission ends. Writing a '0' to this bit has no effect. Bit 9 – TSTART Start Transmission Writing a '1' to this bit starts transmission. Writing a '0' to this bit has no effect. Bit 8 – BP Back Pressure In 10M or 100M half duplex mode, writing a '1' to this bit forces collisions on all received frames. Ignored in gigabit half duplex mode. Value Description 0 Frame collisions are not forced. 1 Frame collisions are forced in 10M and 100M half duplex mode. Bit 7 – WESTAT Write Enable for Statistics Registers Writing a '1' to this bit makes the statistics registers writable for functional test purposes. Value Description 0 Statistics Registers are write-protected. 1 Statistics Registers are write-enabled. Bit 6 – INCSTAT Increment Statistics Registers Writing a '1' to this bit increments all Statistics Registers by one for test purposes. Writing a '0' to this bit has no effect. This bit will always read '0'. Bit 5 – CLRSTAT Clear Statistics Registers Writing a '1' to this bit clears the Statistics Registers. Writing a '0' to this bit has no effect. This bit will always read '0'. Bit 4 – MPE Management Port Enable Writing a '1' to this bit enables the Management Port. Writing a '0' to this bit disables the Management Port, and forces MDIO to high impedance state and MDC to low impedance. Value Description 0 Management Port is disabled. 1 Management Port is enabled. Bit 3 – TXEN Transmit Enable Writing a '1' to this bit enables the GMAC transmitter to send data. Writing a '0' to this bit stops transmission immediately, the transmit pipeline and control registers is cleared, and the Transmit Queue Pointer Register will be set to point to the start of the transmit descriptor list. Value Description 0 Transmit is disabled. 1 Transmit is enabled. Bit 2 – RXEN Receive Enable Writing a '1' to this bit enables the GMAC to receive data. Writing a '0' to this bit stops frame reception immediately, and the receive pipeline is cleared. The Receive Queue Pointer Register is not affected. Value Description 0 Receive is disabled. 1 Receive is enabled. Bit 1 – LBL Loop Back Local Writing '1' to this bit connects GTX to GRX, GTXEN to GRXDV, and forces full duplex mode. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 610

GRXCK and GTXCK may malfunction as the GMAC is switched into and out of internal loop back. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loop back. Value Description 0 Loop back local is disabled. 1 Loop back local is enabled. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 611

38.8.2 GMAC Network Configuration Register

Name: GMAC_NCFGR Offset: 0x004 Reset: 0x00080000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 IRXER RXBP IPGSEN IRXFCS EFRHD RXCOEN Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DCPF DBW[1:0] CLK[2:0] RFCS LFERD Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 1 0 0 0 Bit 15 14 13 12 11 10 9 8 RXBUFO[1:0] PEN RTY MAXFS Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 UNIHEN MTIHEN NBC CAF JFRAME DNVLAN FD SPD Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 30 – IRXER Ignore IPG GRXER When this bit is written to '1', the Receive Error signal (GRXER) has no effect on the GMAC operation when Receive Data Valid signal (GRXDV) is low. Bit 29 – RXBP Receive Bad Preamble When written to '1', frames with non-standard preamble are not rejected. Bit 28 – IPGSEN IP Stretch Enable Writing a '1' to this bit allows the transmit IPG to increase above 96 bit times, depending on the previous frame length using the IPG Stretch Register. Bit 26 – IRXFCS Ignore RX FCS For normal operation this bit must be written to zero. When this bit is written to '1', frames with FCS/CRC errors will not be rejected. FCS error statistics will still be collected for frames with bad FCS, and FCS status will be recorded in the DMA descriptor of the frame. Bit 25 – EFRHD Enable Frames Received in half-duplex Writing a '1' to this bit enables frames to be received in half-duplex mode while transmitting. Bit 24 – RXCOEN Receive Checksum Offload Enable Writing a '1' to this bit enables the receive checksum engine, and frames with bad IP, TCP or UDP checksums are discarded. Bit 23 – DCPF Disable Copy of Pause Frames Writing a '1' to this bit prevents valid pause frames from being copied to memory. Pause frames are not copied regardless of the state of the Copy All Frames (CAF) bit, whether a hash match is found or whether a type ID match is identified. If a destination address match is found, the pause frame will be copied to memory. Note that valid pause frames received will still increment pause statistics and pause the transmission of frames, as required. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 612

Bits 22:21 – DBW[1:0] Data Bus Width Should always be written to '0'. Value Name Description

0 DBW32 32-bit data bus width

1 DBW64 64-bit data bus width

Bits 20:18 – CLK[2:0] MDC Clock Division These bits must be set according to MCK speed, and determine the number MCK will be divided by to generate Management Data Clock (MDC). For conformance with the 802.3 specification, MDC must not exceed 2.5MHz. Note: MDC is only active during MDIO read and write operations. Value Name Description

0 MCK_8 MCK divided by 8 (MCK up to 20MHz)

1 MCK_16 MCK divided by 16 (MCK up to 40MHz)

2 MCK_32 MCK divided by 32 (MCK up to 80MHz)

3 MCK_48 MCK divided by 48 (MCK up to 120MHz)

4 MCK_64 MCK divided by 64 (MCK up to 160MHz)

5 MCK_96 MCK divided by 96 (MCK up to 240MHz)

Bit 17 – RFCS Remove FCS Writing this bit to '1' will cause received frames to be written to memory without their frame check sequence (last 4 bytes). The indicated frame length will be reduced by four bytes in this mode. Bit 16 – LFERD Length Field Error Frame Discard Writing a '1' to this bit discards frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and 14 in a non-VLAN tagged frame). This only applies to frames with a length field less than 0x0600. Bits 15:14 – RXBUFO[1:0] Receive Buffer Offset These bits determine the number of bytes by which the received data is offset from the start of the receive buffer. Bit 13 – PEN Pause Enable When written to '1', transmission will pause if a non-zero 802.3 classic pause frame is received and PFC has not been negotiated. Bit 12 – RTY Retry Test This bit must be written to '0' for normal operation. When writing a '1' to this bit, the back-off between collisions will always be one slot time. This setting helps testing the too many retries condition. This setting is also useful for pause frame tests by reducing the pause counter's decrement time from "512 bit times" to "every GRXCK cycle". Bit 8 – MAXFS 1536 Maximum Frame Size Writing a '1' to this bit increases the maximum accepted frame size to 1536 bytes in length. When written to '0', any frame above 1518 bytes in length is rejected. Bit 7 – UNIHEN Unicast Hash Enable When writing a '1' to this bit, unicast frames will be accepted when the 6-bit hash function of the destination address points to a bit that is set in the Hash Register. Writing a '0' to this bit disables unicast hashing. Bit 6 – MTIHEN Multicast Hash Enable When writing a '1' to this bit, multicast frames will be accepted when the 6-bit hash function of the destination address points to a bit that is set in the Hash Register. Writing a '0' to this bit disables multicast hashing. Bit 5 – NBC No Broadcast Writing a '1' to this bit will reject frames addressed to the broadcast address 0xFFFFFFFFFFFF (all '1'). Writing a '0' to this bit allows broadcasting to 0xFFFFFFFFFFFF. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 613

Bit 4 – CAF Copy All Frames When writing a '1' to this bit, all valid frames will be accepted. Bit 3 – JFRAME Jumbo Frame Size Writing a '1' to this bit enables jumbo frames of up to 10240 bytes to be accepted. The default length is 10240 bytes. Bit 2 – DNVLAN Discard Non-VLAN Frames Writing a '1' to this bit allows only VLAN-tagged frames to pass to the address matching logic. Writing a '0' to this bit allows both VLAN_tagged and untagged frames to pass to the address matching logic. Bit 1 – FD Full Duplex Writing a '1' enables full duplex operation, so the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Writing a '0' disables full duplex operation. Bit 0 – SPD Speed Writing a '1' selects 100Mbps operation. Writing a '0' to this bit selects 10Mbps operation. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 614

38.8.3 GMAC Network Status Register

Name: GMAC_NSR Offset: 0x008 Reset: 0x000001X0 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 IDLE MDIO Access R R Reset 0 0 Bit 2 – IDLE PHY Management Logic Idle The PHY management logic is idle (i.e., has completed). Bit 1 – MDIO MDIO Input Status Returns status of the MDIO pin. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 615

38.8.4 GMAC User Register

Name: GMAC_UR Offset: 0x00C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 Access R/W Reset 0 Bit 0 – Reduced MII Mode Value Description

0 RMII mode is selected

1 MII mode is selected

38.8.5 GMAC DMA Configuration Register

Name: GMAC_DCFGR Offset: 0x010 Reset: 0x00020004 Property: Read/Write Bit 31 30 29 28 27 26 25 24 DDRP Access Reset 0 Bit 23 22 21 20 19 18 17 16 DRBS[7:0] Access Reset 0 0 0 0 0 0 1 0 Bit 15 14 13 12 11 10 9 8 TXCOEN TXPBMS RXBMS[1:0] Access Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ESPA ESMA FBLDO[4:0] Access Reset 0 0 0 0 1 0 0 Bit 24 – DDRP DMA Discard Receive Packets A write to this bit is ignored if the DMA is not configured in the packet buffer full store and forward mode. Value Description

0 Received packets are stored in the SRAM based packet buffer until next AHB buffer resource becomes

available.

1 Receive packets from the receiver packet buffer memory are automatically discarded when no AHB

resource is available. Bits 23:16 – DRBS[7:0] DMA Receive Buffer Size These bits defined by these bits determines the size of buffer to use in main AHB system memory when writing received data. The value is defined in multiples of 64 bytes. For example:

0x02: 128 bytes
0x18: 1536 bytes (1 × max length frame/buffer)
0xA0: 10240 bytes (1 × 10K jumbo frame/buffer) WARNINGDo not write 0x00 to this bit field. Bit 11 – TXCOEN Transmitter Checksum Generation Offload Enable Transmitter IP, TCP and UDP checksum generation offload enable. Value Description 0 Frame data is unaffected.

1 The transmitter checksum generation engine calculates and substitutes checksums for transmit

Bit 10 – TXPBMS Transmitter Packet Buffer Memory Size Select When written to zero, the amount of memory used for the transmit packet buffer is reduced by 50%. This reduces the amount of memory used by the GMAC. It is important to write this bit to '1' if the full configured physical memory is available. The value in parentheses represents the size that would result for the default maximum configured memory size of 4KBytes. Value Description 0 Top address bits not used. (2KByte used.) 1 Full configured addressable space (4KBytes) used. Bits 9:8 – RXBMS[1:0] Receiver Packet Buffer Memory Size Select The default receive packet buffer size is FULL=4 Kbytes. The table below shows how to configure this memory to FULL, HALF, QUARTER or EIGHTH of the default size. Value Name Description

0 EIGHTH 4/8 Kbyte Memory Size

1 QUARTER 4/4 Kbytes Memory Size

2 HALF 4/2 Kbytes Memory Size

3 FULL 4 Kbytes Memory Size

Bit 7 – ESPA Endian Swap Mode Enable for Packet Data Accesses Value Description 0 Little endian mode for AHB transfers selected. 1 Big endian mode for AHB transfers selected. Bit 6 – ESMA Endian Swap Mode Enable for Management Descriptor Accesses Value Description 0 Little endian mode for AHB transfers selected. 1 Big endian mode for AHB transfers selected. Bits 4:0 – FBLDO[4:0] Fixed Burst Length for DMA Data Operations Selects the burst length to attempt to use on the AHB when transferring frame data. Not used for DMA management operations and only used where space and data size allow. Otherwise SINGLE type AHB transfers are used. One-hot priority encoding enforced automatically on register writes as follows. ‘x’ represents don’t care. Value Name Description 0 - Reserved

1 SINGLE 00001: Always use SINGLE AHB bursts

4 INCR4 001xx: Attempt to use INCR4 AHB bursts (Default)

8 INCR8 01xxx: Attempt to use INCR8 AHB bursts

16 INCR16 1xxxx: Attempt to use INCR16 AHB bursts

38.8.6 GMAC Transmit Status Register

Name: GMAC_TSR Offset: 0x014 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 HRESP Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 TXCOMP TFC TXGO RLE COL UBR Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 8 – HRESP HRESP Not OK Set when the DMA block sees HRESP not OK. This bit is cleared by writing a '1' to it. Bit 5 – TXCOMP Transmit Complete Set when a frame has been transmitted. This bit is cleared by writing a '1' to it. Bit 4 – TFC Transmit Frame Corruption Due to AHB Error This bit is set when an error occurs during reading transmit frame from the AHB. Error causes include HRESP errors and buffers exhausted mid frame. (If the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and GTXER asserted). In DMA packet buffer mode, this bit is also set if a single frame is too large for the configured packet buffer memory size. This bit is cleared by writing a '1' to it. Bit 3 – TXGO Transmit Go This bit is '1' when transmit is active. When using the DMA interface this bit represents the TXGO variable as specified in the transmit buffer description. Bit 2 – RLE Retry Limit Exceeded This bit is cleared by writing a '1' to it. Bit 1 – COL Collision Occurred When operating in 10/100Mbps mode, this bit is set by the assertion of either a collision or a late collision. This bit is cleared by writing a '1' to it. Bit 0 – UBR Used Bit Read This bit is set when a transmit buffer descriptor is read with its used bit set. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 619

38.8.7 GMAC Receive Buffer Queue Base Address Register

Name: GMAC_RBQB Offset: 0x018 Reset: 0x00000000 Property: Read/Write This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the Network Control Register. Once reception is enabled, any write to the Receive Buffer Queue Base Address Register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the “used” bits. In terms of AMBA AHB operation, the descriptors are read from memory using a single 32-bit AHB access. The descriptors should be aligned at 32-bit boundaries and the descriptors are written to using two individual non sequential accesses. Bit 31 30 29 28 27 26 25 24 ADDR[29:22] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 ADDR[21:14] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ADDR[13:6] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[5:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bits 31:2 – ADDR[29:0] Receive Buffer Queue Base Address Written with the address of the start of the receive queue. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 621

38.8.8 GMAC Transmit Buffer Queue Base Address Register

Name: GMAC_TBQB Offset: 0x01C Reset: 0x00000000 Property: - This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The Transmit Buffer Queue Base Address Register must be initialized before transmit is started through bit 9 of the Network Control Register. Once transmission has started, any write to the Transmit Buffer Queue Base Address Register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four MCK cycles from the writing of the transmit start bit before the transmitter is active. Writing to the Transmit Buffer Queue Base Address Register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Since the DMA handles two frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB operation, the descriptors are written to memory using a single 32-bit AHB access. The descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual non sequential accesses. Bit 31 30 29 28 27 26 25 24 ADDR[29:22] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 ADDR[21:14] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ADDR[13:6] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[5:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bits 31:2 – ADDR[29:0] Transmit Buffer Queue Base Address Written with the address of the start of the transmit queue. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 622

38.8.9 GMAC Receive Status Register

Name: GMAC_RSR Offset: 0x020 Reset: 0x00000000 Property: - This register, when read, provides receive status details. Once read, individual bits may be cleared by writing a '1' to them. It is not possible to set a bit to '1' by writing to this register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 HNO RXOVR REC BNA Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 3 – HNO HRESP Not OK This bit is set when the DMA block sees HRESP not OK. This bit is cleared by writing a '1' to it. Bit 2 – RXOVR Receive Overrun This bit is set if the receive status was not taken at the end of the frame. The buffer will be recovered if an overrun occurs. This bit is cleared by writing a '1' to it. Bit 1 – REC Frame Received This bit is set to when one or more frames have been received and placed in memory. This bit is cleared by writing a '1' to it. Bit 0 – BNA Buffer Not Available When this bit is set, an attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA will re-read the pointer each time an end of frame is received until a valid pointer is found. This bit is set following each descriptor read attempt that fails, even if consecutive pointers are unsuccessful and software has in the mean time cleared the status flag. This bit is cleared by writing a '1' to it. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 623

38.8.10 GMAC Interrupt Status Register

Name: GMAC_ISR Offset: 0x024 Reset: 0x00000000 Property: Read-only This register indicates the source of the interrupt. An interrupt source must be enabled in the mask register first so the corresponding bits of this register will be set and the GMAC interrupt signal will be asserted in the system. Bit 31 30 29 28 27 26 25 24 TSUTIMCMP WOL RXLPISBC SRI PDRSFT PDRQFT Access R R R R R R Reset 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 PDRSFR PDRQFR SFT DRQFT SFR DRQFR Access R R R R R R Reset 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 PFTR PTZ PFNZ HRESP ROVR Access R R R R R Reset 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TCOMP TFC RLEX TUR TXUBR RXUBR RCOMP MFS Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 29 – TSUTIMCMP TSU Timer Comparison Indicates when TSU timer count value is equal to programmed value. Cleared on read. Bit 28 – WOL Wake On LAN WOL interrupt. Indicates a WOL message has been received. Bit 27 – RXLPISBC Receive LPI indication Status Bit Change Receive LPI indication status bit change. Cleared on read. Bit 26 – SRI TSU Seconds Register Increment Indicates the register has incremented. Cleared on read. Bit 25 – PDRSFT PDelay Response Frame Transmitted Indicates a PTP pdelay_resp frame has been transmitted. Cleared on read. Bit 24 – PDRQFT PDelay Request Frame Transmitted Indicates a PTP pdelay_req frame has been transmitted. Cleared on read. Bit 23 – PDRSFR PDelay Response Frame Received Indicates a PTP pdelay_resp frame has been received. Cleared on read. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 624

Bit 22 – PDRQFR PDelay Request Frame Received Indicates a PTP pdelay_req frame has been received. Cleared on read. Bit 21 – SFT PTP Sync Frame Transmitted Indicates a PTP sync frame has been transmitted. Cleared on read. Bit 20 – DRQFT PTP Delay Request Frame Transmitted Indicates a PTP delay_req frame has been transmitted. Cleared on read. Bit 19 – SFR PTP Sync Frame Received Indicates a PTP sync frame has been received. Cleared on read. Bit 18 – DRQFR PTP Delay Request Frame Received Indicates a PTP delay_req frame has been received. Cleared on read. Bit 14 – PFTR Pause Frame Transmitted Indicates a pause frame has been successfully transmitted after being initiated from the Network Control Register. Cleared on read. Bit 13 – PTZ Pause Time Zero Set when either the Pause Time Register at address 0x38 decrements to zero, or when a valid pause frame is received with a zero pause quantum field. Cleared on read. Bit 12 – PFNZ Pause Frame with Non-zero Pause Quantum Received Indicates a valid pause has been received that has a non-zero pause quantum field. Cleared on read. Bit 11 – HRESP HRESP Not OK Set when the DMA block sees HRESP not OK. Cleared on read. Bit 10 – ROVR Receive Overrun Set when the receive overrun status bit is set. Cleared on read. Bit 7 – TCOMP Transmit Complete Set when a frame has been transmitted. Cleared on read. Bit 6 – TFC Transmit Frame Corruption Due to AHB Error Transmit frame corruption due to AHB error. Set if an error occurs during reading a transmit frame from the AHB, including HRESP errors and buffers exhausted mid frame. Bit 5 – RLEX Retry Limit Exceeded Retry Limit Exceeded Transmit error. Cleared on read. Bit 4 – TUR Transmit Underrun This interrupt is set if the transmitter was forced to terminate an ongoing frame transmission due to further data being unavailable. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 625

This interrupt is also set if a transmitter status write back has not completed when another status write back is attempted. This interrupt is also set when the transmit DMA has written the SOP data into the FIFO and either the AHB bus was not granted in time for further data, or because an AHB not OK response was returned, or because the used bit was read. Bit 3 – TXUBR TX Used Bit Read Set when a transmit buffer descriptor is read with its used bit set. Cleared on read. Bit 2 – RXUBR RX Used Bit Read Set when a receive buffer descriptor is read with its used bit set. Cleared on read. Bit 1 – RCOMP Receive Complete A frame has been stored in memory. Cleared on read. Bit 0 – MFS Management Frame Sent The PHY Maintenance Register has completed its operation. Cleared on read. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 626

38.8.11 GMAC Interrupt Enable Register

Name: GMAC_IER Offset: 0x028 Reset: – Property: Write-only This register is write-only and will always return zero. The following values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt. Bit 31 30 29 28 27 26 25 24 TSUTIMCMP WOL RXLPISBC SRI PDRSFT PDRQFT Access W W R W W W Bit 23 22 21 20 19 18 17 16 PDRSFR PDRQFR SFT DRQFT SFR DRQFR Access W W W W W W Bit 15 14 13 12 11 10 9 8 EXINT PFTR PTZ PFNZ HRESP ROVR Access W W W W W W Bit 7 6 5 4 3 2 1 0 TCOMP TFC RLEX TUR TXUBR RXUBR RCOMP MFS Access W W W W W W W W Bit 29 – TSUTIMCMP TSU Timer Comparison Bit 28 – WOL Wake On LAN Bit 27 – RXLPISBC Receive LPI indication Status Bit Change Receive LPI indication status bit change. Cleared on read. Bit 26 – SRI TSU Seconds Register Increment Bit 25 – PDRSFT PDelay Response Frame Transmitted Bit 24 – PDRQFT PDelay Request Frame Transmitted Bit 23 – PDRSFR PDelay Response Frame Received Bit 22 – PDRQFR PDelay Request Frame Received Bit 21 – SFT PTP Sync Frame Transmitted Bit 20 – DRQFT PTP Delay Request Frame Transmitted Bit 19 – SFR PTP Sync Frame Received SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 627

Bit 18 – DRQFR PTP Delay Request Frame Received Bit 15 – EXINT External Interrupt Bit 14 – PFTR Pause Frame Transmitted Bit 13 – PTZ Pause Time Zero Bit 12 – PFNZ Pause Frame with Non-zero Pause Quantum Received Bit 11 – HRESP HRESP Not OK Bit 10 – ROVR Receive Overrun Bit 7 – TCOMP Transmit Complete Bit 6 – TFC Transmit Frame Corruption Due to AHB Error Bit 5 – RLEX Retry Limit Exceeded or Late Collision Bit 4 – TUR Transmit Underrun Bit 3 – TXUBR TX Used Bit Read Bit 2 – RXUBR RX Used Bit Read Bit 1 – RCOMP Receive Complete Bit 0 – MFS Management Frame Sent SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 628

38.8.12 GMAC Interrupt Disable Register

Name: GMAC_IDR Offset: 0x02C Reset: – Property: Write-only This register is write-only and will always return zero. The following values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt. Bit 31 30 29 28 27 26 25 24 TSUTIMCMP WOL RXLPISBC SRI PDRSFT PDRQFT Access W W R W W W Bit 23 22 21 20 19 18 17 16 PDRSFR PDRQFR SFT DRQFT SFR DRQFR Access W W W W W W Bit 15 14 13 12 11 10 9 8 EXINT PFTR PTZ PFNZ HRESP ROVR Access W W W W W W Bit 7 6 5 4 3 2 1 0 TCOMP TFC RLEX TUR TXUBR RXUBR RCOMP MFS Access W W W W W W W W Bit 29 – TSUTIMCMP TSU Timer Comparison Bit 28 – WOL Wake On LAN Bit 27 – RXLPISBC Receive LPI indication Status Bit Change Receive LPI indication status bit change. Cleared on read. Bit 26 – SRI TSU Seconds Register Increment Bit 25 – PDRSFT PDelay Response Frame Transmitted Bit 24 – PDRQFT PDelay Request Frame Transmitted Bit 23 – PDRSFR PDelay Response Frame Received Bit 22 – PDRQFR PDelay Request Frame Received Bit 21 – SFT PTP Sync Frame Transmitted Bit 20 – DRQFT PTP Delay Request Frame Transmitted Bit 19 – SFR PTP Sync Frame Received SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 629

38.8.13 GMAC Interrupt Mask Register

Name: GMAC_IMR Offset: 0x030 Reset: 0x07FFFFFF Property: Read/Write This register is a read-only register indicating which interrupts are masked. All bits are set at Reset and can be reset individually by writing to the Interrupt Enable Register (GMAC_IER), or set individually by writing to the Interrupt Disable Register (GMAC_IDR). For test purposes there is a write-only function to this register that allows the bits in the Interrupt Status Register to be set or cleared, regardless of the state of the mask register. A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt to be generated if a 1 is written. The following values are valid for all listed bit names of this register when read: 0: The corresponding interrupt is enabled. 1: The corresponding interrupt is not enabled. Bit 31 30 29 28 27 26 25 24 TSUTIMCMP WOL RXLPISBC SRI PDRSFT PDRQFT Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 1 1 1 Bit 23 22 21 20 19 18 17 16 PDRSFR PDRQFR SFT DRQFT SFR DRQFR Access R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 EXINT PFTR PTZ PFNZ HRESP ROVR Access R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 TCOMP TFC RLEX TUR TXUBR RXUBR RCOMP MFS Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 29 – TSUTIMCMP TSU Timer Comparison Bit 28 – WOL Wake On LAN Bit 27 – RXLPISBC Receive LPI indication Status Bit Change Receive LPI indication status bit change. Cleared on read. Bit 26 – SRI TSU Seconds Register Increment Bit 25 – PDRSFT PDelay Response Frame Transmitted Bit 24 – PDRQFT PDelay Request Frame Transmitted Bit 23 – PDRSFR PDelay Response Frame Received Bit 22 – PDRQFR PDelay Request Frame Received SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 631

Bit 21 – SFT PTP Sync Frame Transmitted Bit 20 – DRQFT PTP Delay Request Frame Transmitted Bit 19 – SFR PTP Sync Frame Received Bit 18 – DRQFR PTP Delay Request Frame Received Bit 15 – EXINT External Interrupt Bit 14 – PFTR Pause Frame Transmitted Bit 13 – PTZ Pause Time Zero Bit 12 – PFNZ Pause Frame with Non-zero Pause Quantum Received Bit 11 – HRESP HRESP Not OK Bit 10 – ROVR Receive Overrun Bit 7 – TCOMP Transmit Complete Bit 6 – TFC Transmit Frame Corruption Due to AHB Error Bit 5 – RLEX Retry Limit Exceeded Bit 4 – TUR Transmit Underrun Bit 3 – TXUBR TX Used Bit Read Bit 2 – RXUBR RX Used Bit Read Bit 1 – RCOMP Receive Complete Bit 0 – MFS Management Frame Sent SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 632

38.8.14 GMAC PHY Maintenance Register

Name: GMAC_MAN Offset: 0x034 Reset: 0x00000000 Property: Read/Write This register is a shift register. Writing to it starts a shift operation which is signaled completed when bit 2 is set in the Network Status Register (GMAC_NSR). It takes about 2000 MCK cycles to complete, when MDC is set for MCK divide by 32 in the Network Configuration Register. An interrupt is generated upon completion. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with the IEEE 802.3 standard. Reading during the shift operation returns the current contents of the shift register. At the end of management operation, the bits will have shifted back to their original locations. For a read operation, the data bits are updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced. The MDIO interface can read IEEE 802.3 clause 45 PHYs, as well as clause 22 PHYs. To read clause 45 PHYs, bit 30 should be written with a '0' rather than a '1'. To write clause 45 PHYs, bits 31:28 should be written as 0x1: PHY Access Bit Value WZO CLTTO OP[1] OP[0] Clause 22 Read 0 1 1 0 Write 0 1 0 1 Clause 45 Read 0 0 1 1 Write 0 0 0 1 Read + Address 0 0 1 0 For a description of MDC generation, see also the 'GMAC Network Configuration Register' (GMAC_NCR) description. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 633

Bit 31 30 29 28 27 26 25 24 WZO CLTTO OP[1:0] PHYA[4:1] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 PHYA[0] REGA[4:0] WTN[1:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 31 – WZO Write ZERO Must be written to '0'. Value Description

0 Mandatory

Bit 30 – CLTTO Clause 22 Operation Value Description

0 Clause 45 operation

1 Clause 22 operation

Bits 29:28 – OP[1:0] Operation Value Description

01 Write

10 Read

Bits 27:23 – PHYA[4:0] PHY Address Bits 22:18 – REGA[4:0] Register Address Specifies the register in the PHY to access. Bits 17:16 – WTN[1:0] Write Ten Must be written to '10'. Value Description

10 Mandatory

Bits 15:0 – DATA[15:0] PHY Data For a write operation, this field is written with the data to be written to the PHY. After a read operation, this field contains the data read from the PHY. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 634

38.8.15 GMAC Receive Pause Quantum Register

Name: GMAC_RPQ Offset: 0x038 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 RPQ[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RPQ[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15:0 – RPQ[15:0] Received Pause Quantum Stores the current value of the Receive Pause Quantum Register which is decremented every 512 bit times. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 635

38.8.16 GMAC Transmit Pause Quantum Register

Name: GMAC_TPQ Offset: 0x03C Reset: 0x0000FFFF Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 TPQ[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 TPQ[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bits 15:0 – TPQ[15:0] Transmit Pause Quantum Written with the pause quantum value for pause frame transmission. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 636

38.8.17 GMAC TX Partial Store and Forward Register

Name: GMAC_TPSF Offset: 0x040 Reset: 0x00000FFF Property: - Bit 31 30 29 28 27 26 25 24 ENTXP Access R/W Reset 0 Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 TPB1ADR[11:8] Access R/W R/W R/W R/W Reset 1 1 1 1 Bit 7 6 5 4 3 2 1 0 TPB1ADR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 31 – ENTXP Enable TX Partial Store and Forward Operation Bits 11:0 – TPB1ADR[11:0] Transmit Partial Store and Forward Address Watermark value. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 637

38.8.18 GMAC RX Partial Store and Forward Register

Name: GMAC_RPSF Offset: 0x044 Reset: 0x00000FFF Property: - Bit 31 30 29 28 27 26 25 24 ENRXP Access R Reset 0 Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 RPB1ADR[11:8] Access R/W R/W R/W R/W Reset 1 1 1 1 Bit 7 6 5 4 3 2 1 0 RPB1ADR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 31 – ENRXP Enable RX Partial Store and Forward Operation Bits 11:0 – RPB1ADR[11:0] Receive Partial Store and Forward Address Watermark value. Reset = 1. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 638

38.8.19 GMAC RX Jumbo Frame Max Length Register

Name: GMAC_RJFML Offset: 0x048 Reset: 0x00003FFF Property: Read/Write Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 FML[13:8] Access R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 FML[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bits 13:0 – FML[13:0] Frame Max Length Rx jumbo frame maximum length. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 639

38.8.20 GMAC Hash Register Bottom

Name: GMAC_HRB Offset: 0x080 Reset: 0x00000000 Property: Read/Write The unicast hash enable (UNIHEN) and the multicast hash enable (MITIHEN) bits in the Network Configuration Register (GMAC_NCFGR) enable the reception of hash matched frames. Bit 31 30 29 28 27 26 25 24 ADDR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 ADDR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ADDR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – ADDR[31:0] Hash Address The first 32 bits of the Hash Address Register. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 640

38.8.21 GMAC Hash Register Top

Name: GMAC_HRT Offset: 0x084 Reset: 0x00000000 Property: Read/Write The Unicast Hash Enable (UNIHEN) and the Multicast Hash Enable (MITIHEN) bits in the Network Configuration Register (GMAC_NCFGR) enable the reception of hash matched frames. Bit 31 30 29 28 27 26 25 24 ADDR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 ADDR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ADDR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – ADDR[31:0] Hash Address Bits 63 to 32 of the Hash Address Register. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 641

38.8.22 GMAC Specific Address n Bottom Register

Name: GMAC_SABx Offset: 0x88 + (x-1)*0x08 [x=1..4] Reset: 0x00000000 Property: Read/Write The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written. Bit 31 30 29 28 27 26 25 24 ADDR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 ADDR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ADDR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – ADDR[31:0] Specific Address n Least significant 32 bits of the destination address, that is, bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 642

38.8.23 GMAC Specific Address n Top Register

Name: GMAC_SATx Offset: 0x8C + (x-1)*0x08 [x=1..4] Reset: 0x00000000 Property: Read/Write The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 ADDR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – ADDR[15:0] Specific Address n The most significant bits of the destination address, that is, bits 47:32. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 643

38.8.24 GMAC Type ID Match n Register

Name: GMAC_TIDMx Offset: 0xA8 + (x-1)*0x04 [x=1..4] Reset: 0x00000000 Property: Read/Write Bit 31 30 29 28 27 26 25 24 ENIDn Access R/W Reset 0 Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 TID[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TID[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 31 – ENIDn Enable Copying of TID Matched Frames Value Description 0 TID n is not part of the comparison match. 1 TID n is processed for the comparison match. Bits 15:0 – TID[15:0] Type ID Match n For use in comparisons with received frames type ID/length frames. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 644

38.8.25 GMAC Wake on LAN Register

Name: GMAC_WOL Offset: 0x0B8 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 MTI SA1 ARP MAG Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 IP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 IP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 19 – MTI Multicast Hash Event Enable Value Description

0 Wake on LAN multicast hash Event disabled

1 Wake on LAN multicast hash Event enabled

Bit 18 – SA1 Specific Address Register 1 Event Enable Value Description

0 Wake on Specific Address Register 1 Event disabled

1 Wake on Specific Address Register 1 Event enabled

Bit 17 – ARP ARP Request Event Enable Value Description

0 Wake on LAN ARP request Event disabled

1 Wake on LAN ARP request Event enabled

Bit 16 – MAG Magic Packet Event Enable Value Description

0 Wake on LAN magic packet Event disabled

1 Wake on LAN magic packet Event enabled

Bits 15:0 – IP[15:0] ARP Request IP Address Wake on LAN ARP request IP address. Written to define the 16 least significant bits of the target IP address that is matched to generate a Wake on LAN event. Value Description 0x0000 No Event generated, even if matched by the received frame. 0x0001-0 xFFFF Wake on LAN Event generated for matching LSB of the target IP address. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 645

38.8.26 GMAC IPG Stretch Register

Name: GMAC_IPGS Offset: 0x0BC Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 FL[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FL[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – FL[15:0] Frame Length Bits FL[7:0] are multiplied with the previously transmitted frame length (including preamble), and divided by FL[15:8]+1 (adding 1 to prevent division by zero). RESULT = FL[7:0] F[15+8]+1 If RESULT > 96 and the IP Stretch Enable bit in the Network Configuration Register (GMAC_NCFGR.IPGSEN) is written to '1', RESULT is used for the transmit inter-packet-gap. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 646

38.8.27 GMAC Stacked VLAN Register

Name: GMAC_SVLAN Offset: 0x0C0 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 ESVLAN Access Reset 0 Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 VLAN_TYPE[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 VLAN_TYPE[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 31 – ESVLAN Enable Stacked VLAN Processing Mode 0: Disable the stacked VLAN processing mode 1: Enable the stacked VLAN processing mode Value Description

0 Stacked VLAN Processing disabled

1 Stacked VLAN Processing enabled

Bits 15:0 – VLAN_TYPE[15:0] User Defined VLAN_TYPE Field When Stacked VLAN is enabled (ESVLAN=1), the first VLAN tag in a received frame will only be accepted if the VLAN type field is equal to this user defined VLAN_TYPE, OR equal to the standard VLAN type (0x8100). Note: The second VLAN tag of a Stacked VLAN packet will only be matched correctly if its VLAN_TYPE field equals 0x8100. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 647

38.8.28 GMAC Transmit PFC Pause Register

Name: GMAC_TPFCP Offset: 0x0C4 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 PQ[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PEV[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:8 – PQ[7:0] Pause Quantum When the Remove FCS bit in the GMAC Network Configuration register (GMAC_NCFGR.RFCS) is written to '1', and one or more bits in this bit field are written to '0', the associated PFC pause frame's pause quantum field value is taken from the Transmit Pause Quantum register (GMAC_TPQ). For each entry equal to '1' in this bit field, the pause quantum associated with that entry will be zero. Bits 7:0 – PEV[7:0] Priority Enable Vector When the Remove FCS bit in the GMAC Network Configuration register (GMAC_NCFGR.RFCS) is written to '1', the priority enable vector of the PFC priority-based pause frame is set to the value stored in this bit field. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 648

38.8.29 GMAC Specific Address 1 Mask Bottom

Name: GMAC_SAMB1 Offset: 0x0C8 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 ADDR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 ADDR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ADDR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – ADDR[31:0] Specific Address 1 Mask Setting a bit to '1' masks the corresponding bit in the Specific Address 1 Bottom register (GMAC_SAB1). SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 649

38.8.30 GMAC Specific Address Mask 1 Top

Name: GMAC_SAMT1 Offset: 0x0CC Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 ADDR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – ADDR[15:0] Specific Address 1 Mask Setting a bit to '1' masks the corresponding bit in the Specific Address 1 register GMAC_SAT1. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 650

38.8.31 GMAC 1588 Timer Nanosecond Comparison Register

Name: GMAC_NSC Offset: 0x0DC Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 NANOSEC[21:16] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 NANOSEC[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NANOSEC[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 21:0 – NANOSEC[21:0] 1588 Timer Nanosecond Comparison Value Value is compared to the bits [45:24] of the TSU timer count value (upper 22 bits of nanosecond value). SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 651

38.8.32 GMAC 1588 Timer Second Comparison Low Register

Name: GMAC_SCL Offset: 0x0E0 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 SEC[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SEC[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SEC[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SEC[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – SEC[31:0] 1588 Timer Second Comparison Value Value is compared to seconds value bits [31:0] of the TSU timer count value. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 652

38.8.33 GMAC 1588 Timer Second Comparison High Register

Name: GMAC_SCH Offset: 0x0E4 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 SEC[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SEC[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – SEC[15:0] 1588 Timer Second Comparison Value Value is compared to the top 16 bits (most significant 16 bits [47:32] of seconds value) of the TSU timer count value. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 653

38.8.34 GMAC PTP Event Frame Transmitted Seconds High Register

Name: GMAC_EFTSH Offset: 0x0E8 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 RUD[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RUD[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15:0 – RUD[15:0] Register Update The register is updated with the value that the IEEE 1588 timer seconds register held when the SFD of a PTP transmit primary event crosses the MII interface. An interrupt is issued when the register is updated. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 654

38.8.35 GMAC PTP Event Frame Received Seconds High Register

Name: GMAC_EFRSH Offset: 0x0EC Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 RUD[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RUD[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15:0 – RUD[15:0] Register Update The register is updated with the value that the IEEE 1588 timer seconds register held when the SFD of a PTP transmit primary event crosses the MII interface. An interrupt is issued when the register is updated. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 655

38.8.36 GMAC PTP Peer Event Frame Transmitted Seconds High Register

Name: GMAC_PEFTSH Offset: 0x0F0 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 RUD[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RUD[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15:0 – RUD[15:0] Register Update The register is updated with the value that the IEEE 1588 timer seconds register held when the SFD of a PTP transmit peer event crosses the MII interface. An interrupt is issued when the register is updated. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 656

38.8.37 GMAC PTP Peer Event Frame Received Seconds High Register

Name: GMAC_PEFRSH Offset: 0x0F4 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 RUD[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RUD[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15:0 – RUD[15:0] Register Update The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit peer event crosses the MII interface. An interrupt is issued when the register is updated. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 657

38.8.38 GMAC Octets Transmitted Low Register

Name: GMAC_OTLO Offset: 0x100 Reset: 0x00000000 Property: - When reading the Octets Transmitted and Octets Received Registers, bits [31:0] should be read prior to bits [47:32] to ensure reliable operation. Bit 31 30 29 28 27 26 25 24 TXO[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 TXO[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 TXO[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TXO[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – TXO[31:0] Transmitted Octets Transmitted octets in valid frames of any type without errors, bits [31:0]. This counter is 48-bits, and is read through two registers. This count does not include octets from automatically generated pause frames. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 658

38.8.39 GMAC Octets Transmitted High Register

Name: GMAC_OTHI Offset: 0x104 Reset: 0x00000000 Property: - When reading the Octets Transmitted and Octets Received Registers, bits [31:0] should be read prior to bits [47:32] to ensure reliable operation. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 TXO[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TXO[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15:0 – TXO[15:0] Transmitted Octets Transmitted octets in valid frames of any type without errors, bits [47:32]. This counter is 48-bits, and is read through two registers. This count does not include octets from automatically generated pause frames. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 659

38.8.40 GMAC Frames Transmitted

Name: GMAC_FT Offset: 0x108 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 FTX[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 FTX[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 FTX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FTX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – FTX[31:0] Frames Transmitted without Error Frames transmitted without error. This register counts the number of frames successfully transmitted, i.e., no underrun and not too many retries. Excludes pause frames. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 660

38.8.41 GMAC Broadcast Frames Transmitted Register

Name: GMAC_BCFT Offset: 0x10C Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 BFTX[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 BFTX[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 BFTX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BFTX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – BFTX[31:0] Broadcast Frames Transmitted without Error This register counts the number of broadcast frames successfully transmitted without error, i.e., no underrun and not too many retries. Excludes pause frames. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 661

38.8.42 GMAC Multicast Frames Transmitted Register

Name: GMAC_MFT Offset: 0x110 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 MFTX[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 MFTX[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 MFTX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MFTX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – MFTX[31:0] Multicast Frames Transmitted without Error This register counts the number of multicast frames successfully transmitted without error, i.e., no underrun and not too many retries. Excludes pause frames. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 662

38.8.43 GMAC Pause Frames Transmitted Register

Name: GMAC_PFT Offset: 0x114 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 PFTX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PFTX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15:0 – PFTX[15:0] Pause Frames Transmitted Register This register counts the number of pause frames transmitted. Only pause frames triggered by the register interface or through the external pause pins are counted as pause frames. Pause frames received through the FIFO interface are counted in the frames transmitted counter. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 663

38.8.44 GMAC 64 Byte Frames Transmitted Register

Name: GMAC_BFT64 Offset: 0x118 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 NFTX[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 NFTX[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 NFTX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NFTX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – NFTX[31:0] 64 Byte Frames Transmitted without Error This register counts the number of 64 byte frames successfully transmitted without error, i.e., no underrun and not too many retries. Excludes pause frames. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 664

38.8.45 GMAC 65 to 127 Byte Frames Transmitted Register

Name: GMAC_TBFT127 Offset: 0x11C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 NFTX[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 NFTX[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 NFTX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NFTX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – NFTX[31:0] 65 to 127 Byte Frames Transmitted without Error This register counts the number of 65 to 127 byte frames successfully transmitted without error, i.e., no underrun and not too many retries. Excludes pause frames. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 665

38.8.46 GMAC 128 to 255 Byte Frames Transmitted Register

Name: GMAC_TBFT255 Offset: 0x120 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 NFTX[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 NFTX[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 NFTX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NFTX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – NFTX[31:0] 128 to 255 Byte Frames Transmitted without Error This register counts the number of 128 to 255 byte frames successfully transmitted without error, i.e., no underrun and not too many retries. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 666

38.8.47 GMAC 256 to 511 Byte Frames Transmitted Register

Name: GMAC_TBFT511 Offset: 0x124 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 NFTX[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 NFTX[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 NFTX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NFTX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – NFTX[31:0] 256 to 511 Byte Frames Transmitted without Error This register counts the number of 256 to 511 byte frames successfully transmitted without error, i.e., no underrun and not too many retries. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 667

38.8.48 GMAC 512 to 1023 Byte Frames Transmitted Register

Name: GMAC_TBFT1023 Offset: 0x128 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 NFTX[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 NFTX[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 NFTX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NFTX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – NFTX[31:0] 512 to 1023 Byte Frames Transmitted without Error This register counts the number of 512 to 1023 byte frames successfully transmitted without error, i.e., no underrun and not too many retries. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 668

38.8.49 GMAC 1024 to 1518 Byte Frames Transmitted Register

Name: GMAC_TBFT1518 Offset: 0x12C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 NFTX[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 NFTX[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 NFTX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NFTX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – NFTX[31:0] 1024 to 1518 Byte Frames Transmitted without Error This register counts the number of 1024 to 1518 byte frames successfully transmitted without error, i.e., no underrun and not too many retries. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 669

38.8.50 GMAC Greater Than 1518 Byte Frames Transmitted Register

Name: GMAC_GTBFT1518 Offset: 0x130 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 NFTX[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 NFTX[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 NFTX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NFTX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – NFTX[31:0] Greater than 1518 Byte Frames Transmitted without Error This register counts the number of 1518 or above byte frames successfully transmitted without error i.e., no underrun and not too many retries. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 670

38.8.51 GMAC Transmit Underruns Register

Name: GMAC_TUR Offset: 0x134 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 TXUNR[9:8] Access R R Reset 0 0 Bit 7 6 5 4 3 2 1 0 TXUNR[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 9:0 – TXUNR[9:0] Transmit Underruns This register counts the number of frames not transmitted due to a transmit underrun. If this register is incremented then no other statistics register is incremented. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 671

38.8.52 GMAC Single Collision Frames Register

Name: GMAC_SCF Offset: 0x138 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 SCOL[17:16] Access R R Reset 0 0 Bit 15 14 13 12 11 10 9 8 SCOL[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SCOL[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 17:0 – SCOL[17:0] Single Collision This register counts the number of frames experiencing a single collision before being successfully transmitted i.e., no underrun. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 672

38.8.53 GMAC Multiple Collision Frames Register

Name: GMAC_MCF Offset: 0x13C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 MCOL[17:16] Access R R Reset 0 0 Bit 15 14 13 12 11 10 9 8 MCOL[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MCOL[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 17:0 – MCOL[17:0] Multiple Collision This register counts the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e., no underrun and not too many retries. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 673

38.8.54 GMAC Excessive Collisions Register

Name: GMAC_EC Offset: 0x140 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 XCOL[9:8] Access R R Reset 0 0 Bit 7 6 5 4 3 2 1 0 XCOL[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 9:0 – XCOL[9:0] Excessive Collisions This register counts the number of frames that failed to be transmitted because they experienced 16 collisions. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 674

38.8.55 GMAC Late Collisions Register

Name: GMAC_LC Offset: 0x144 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 LCOL[9:8] Access R R Reset 0 0 Bit 7 6 5 4 3 2 1 0 LCOL[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 9:0 – LCOL[9:0] Late Collisions This register counts the number of late collisions occurring after the slot time (512 bits) has expired. In 10/100 mode, late collisions are counted twice i.e., both as a collision and a late collision. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 675

38.8.56 GMAC Deferred Transmission Frames Register

Name: GMAC_DTF Offset: 0x148 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 DEFT[17:16] Access R R Reset 0 0 Bit 15 14 13 12 11 10 9 8 DEFT[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DEFT[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 17:0 – DEFT[17:0] Deferred Transmission This register counts the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission. Frames involved in any collision are not counted nor are frames that experienced a transmit underrun. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 676

38.8.57 GMAC Carrier Sense Errors Register

Name: GMAC_CSE Offset: 0x14C Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 CSR[9:8] Access R R Reset 0 0 Bit 7 6 5 4 3 2 1 0 CSR[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 9:0 – CSR[9:0] Carrier Sense Error This register counts the number of frames transmitted with carrier sense was not seen during transmission or where carrier sense was de-asserted after being asserted in a transmit frame without collision (no underrun). Only incremented in half duplex mode. The only effect of a carrier sense error is to increment this register. The behavior of the other statistics registers is unaffected by the detection of a carrier sense error. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 677

38.8.58 GMAC Octets Received Low Register

Name: GMAC_ORLO Offset: 0x150 Reset: 0x00000000 Property: - When reading the Octets Transmitted and Octets Received Registers, bits [31:0] should be read prior to bits [47:32] to ensure reliable operation. Bit 31 30 29 28 27 26 25 24 RXO[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 RXO[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 RXO[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RXO[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – RXO[31:0] Received Octets Received octets in frame without errors [31:0]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames, and is only incremented if the frame is successfully filtered and copied to memory. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 678

38.8.59 GMAC Octets Received High Register

Name: GMAC_ORHI Offset: 0x154 Reset: 0x00000000 Property: - When reading the Octets Transmitted and Octets Received Registers, bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 RXO[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RXO[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15:0 – RXO[15:0] Received Octets Received octets in frame without errors [47:32]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames, and is only incremented if the frame is successfully filtered and copied to memory. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 679

38.8.60 GMAC Frames Received Register

Name: GMAC_FR Offset: 0x158 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 FRX[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 FRX[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 FRX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FRX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – FRX[31:0] Frames Received without Error This bit field counts the number of frames successfully received, excluding pause frames. It is only incremented if the frame is successfully filtered and copied to memory. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 680

38.8.61 GMAC Broadcast Frames Received Register

Name: GMAC_BCFR Offset: 0x15C Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 BFRX[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 BFRX[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 BFRX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BFRX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – BFRX[31:0] Broadcast Frames Received without Error Broadcast frames received without error. This bit field counts the number of broadcast frames successfully received. This excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 681

38.8.62 GMAC Multicast Frames Received Register

Name: GMAC_MFR Offset: 0x160 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 MFRX[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 MFRX[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 MFRX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MFRX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – MFRX[31:0] Multicast Frames Received without Error This register counts the number of multicast frames successfully received without error, excluding pause frames, and is only incremented if the frame is successfully filtered and copied to memory. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 682

38.8.63 GMAC Pause Frames Received Register

Name: GMAC_PFR Offset: 0x164 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 PFRX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PFRX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15:0 – PFRX[15:0] Pause Frames Received Register This register counts the number of pause frames received without error. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 683

38.8.64 GMAC 64 Byte Frames Received Register

Name: GMAC_BFR64 Offset: 0x168 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 NFRX[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 NFRX[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 NFRX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NFRX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – NFRX[31:0] 64 Byte Frames Received without Error This bit field counts the number of 64 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 684

38.8.65 GMAC 65 to 127 Byte Frames Received Register

Name: GMAC_TBFR127 Offset: 0x16C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 NFRX[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 NFRX[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 NFRX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NFRX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – NFRX[31:0] 65 to 127 Byte Frames Received without Error This bit field counts the number of 65 to 127 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 685

38.8.66 GMAC 128 to 255 Byte Frames Received Register

Name: GMAC_TBFR255 Offset: 0x170 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 NFRX[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 NFRX[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 NFRX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NFRX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – NFRX[31:0] 128 to 255 Byte Frames Received without Error This bit field counts the number of 128 to 255 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 686

38.8.67 GMAC 256 to 511 Byte Frames Received Register

Name: GMAC_TBFR511 Offset: 0x174 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 NFRX[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 NFRX[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 NFRX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NFRX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – NFRX[31:0] 256 to 511 Byte Frames Received without Error This bit fields counts the number of 256 to 511 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 687

38.8.68 GMAC 512 to 1023 Byte Frames Received Register

Name: GMAC_TBFR1023 Offset: 0x178 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 NFRX[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 NFRX[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 NFRX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NFRX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – NFRX[31:0] 512 to 1023 Byte Frames Received without Error This bit field counts the number of 512 to 1023 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 688

38.8.69 GMAC 1024 to 1518 Byte Frames Received Register

Name: GMAC_TBFR1518 Offset: 0x17C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 NFRX[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 NFRX[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 NFRX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NFRX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – NFRX[31:0] 1024 to 1518 Byte Frames Received without Error This bit field counts the number of 1024 to 1518 byte frames successfully received without error, i.e., no underrun and not too many retries. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 689

38.8.70 GMAC 1519 to Maximum Byte Frames Received Register

Name: GMAC_TMXBFR Offset: 0x180 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 NFRX[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 NFRX[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 NFRX[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NFRX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – NFRX[31:0] 1519 to Maximum Byte Frames Received without Error This bit field counts the number of 1519 Byte or above frames successfully received without error. Maximum frame size is determined by the Maximum Frame Size bit (MAXFS, 1536 Bytes) or Jumbo Frame Size bit (JFRAME, 10240 Bytes) in the Network Configuration Register (GMAC_NCFGR). Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 690

38.8.71 GMAC Undersized Frames Received Register

Name: GMAC_UFR Offset: 0x184 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 UFRX[9:8] Access R R Reset 0 0 Bit 7 6 5 4 3 2 1 0 UFRX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 9:0 – UFRX[9:0] Undersize Frames Received This bit field counts the number of frames received less than 64 bytes in length (10/100 mode, full duplex) that do not have either a CRC error or an alignment error. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 691

38.8.72 GMAC Oversized Frames Received Register

Name: GMAC_OFR Offset: 0x188 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 OFRX[9:8] Access R R Reset 0 0 Bit 7 6 5 4 3 2 1 0 OFRX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 9:0 – OFRX[9:0] Oversized Frames Received This pit field counts the number of frames received exceeding 1518 Bytes in length (1536 Bytes if GMAC_NCFGR.MAXFS is written to '1') but do not have either a CRC error, an alignment error, nor a receive symbol error. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 692

38.8.73 GMAC Jabbers Received Register

Name: GMAC_JR Offset: 0x18C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 JRX[9:8] Access R R Reset 0 0 Bit 7 6 5 4 3 2 1 0 JRX[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 9:0 – JRX[9:0] Jabbers Received This bit field counts the number of frames received exceeding 1518 Bytes in length (1536 Bytes if GMAC_NCFGR.MAXFS is written to '1') and have either a CRC error, an alignment error or a receive symbol error. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 693

38.8.74 GMAC Frame Check Sequence Errors Register

Name: GMAC_FCSE Offset: 0x190 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 FCKR[9:8] Access R R Reset 0 0 Bit 7 6 5 4 3 2 1 0 FCKR[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 9:0 – FCKR[9:0] Frame Check Sequence Errors The register counts frames that are an integral number of bytes, have bad CRC and are between 64 and 1518 bytes in length (1536 Bytes if GMAC_NCFGR.MAXFS is written to '1'). This register is also incremented if a symbol error is detected and the frame is of valid length and has an integral number of bytes. This register is incremented for a frame with bad FCS, regardless of whether it is copied to memory due to ignore FCS mode (enabled by writing GMAC_NCFGR.IRXFCS=1). SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 694

38.8.75 GMAC Length Field Frame Errors Register

Name: GMAC_LFFE Offset: 0x194 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 LFER[9:8] Access R R Reset 0 0 Bit 7 6 5 4 3 2 1 0 LFER[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 9:0 – LFER[9:0] Length Field Frame Errors This bit field counts the number of frames received that have a measured length shorter than that extracted from the length field (Bytes 13 and 14). This condition is only counted if the value of the length field is less than 0x0600, the frame is not of excessive length and checking is enabled by writing a '1' to the Length Field Error Frame Discard bit in the Network Configuration Register (GMAC_NCFGR.LFERD). SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 695

38.8.76 GMAC Receive Symbol Errors Register

Name: GMAC_RSE Offset: 0x198 Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 RXSE[9:8] Access R R Reset 0 0 Bit 7 6 5 4 3 2 1 0 RXSE[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 9:0 – RXSE[9:0] Receive Symbol Errors This bit field counts the number of frames that had GRXER asserted during reception. For 10/100 mode symbol errors are counted regardless of frame length checks. Receive symbol errors will also be counted as an FCS or alignment error if the frame is between 64 and 1518 Bytes (1536 Bytes if GMAC_NCFGR.MAXFS=1). If the frame is larger it will be recorded as a jabber error. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 696

38.8.77 GMAC Alignment Errors Register

Name: GMAC_AE Offset: 0x19C Reset: 0x00000000 Property: Read-only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 AER[9:8] Access R R Reset 0 0 Bit 7 6 5 4 3 2 1 0 AER[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 9:0 – AER[9:0] Alignment Errors This bit field counts the frames that are not an integral number of bytes long and have bad CRC when their length is truncated to an integral number of Bytes and are between 64 and 1518 Bytes in length (1536 if GMAC_NCFGR.MAXFS=1). This register is also incremented if a symbol error is detected and the frame is of valid length and does not have an integral number of bytes. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 697

38.8.78 GMAC Receive Resource Errors Register

Name: GMAC_RRE Offset: 0x1A0 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 RXRER[17:16] Access R R Reset 0 0 Bit 15 14 13 12 11 10 9 8 RXRER[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RXRER[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 17:0 – RXRER[17:0] Receive Resource Errors This bit field counts frames that are not an integral number of bytes long and have bad CRC when their length is truncated to an integral number of Bytes and are between 64 and 1518 Bytes in length (1536 if GMAC_NCFGR.MAXFS=1). This bit field is also incremented if a symbol error is detected and the frame is of valid length and does not have an integral number of Bytes. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 698

38.8.79 GMAC Receive Overruns Register

Name: GMAC_ROE Offset: 0x1A4 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 RXOVR[9:8] Access R R Reset 0 0 Bit 7 6 5 4 3 2 1 0 RXOVR[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 9:0 – RXOVR[9:0] Receive Overruns This bit field counts the number of frames that are address recognized but were not copied to memory due to a receive overrun. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 699

38.8.80 GMAC IP Header Checksum Errors Register

Name: GMAC_IHCE Offset: 0x1A8 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 HCKER[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:0 – HCKER[7:0] IP Header Checksum Errors This register counts the number of frames discarded due to an incorrect IP header checksum, but are between 64 and 1518 Bytes (1536 Bytes if GMAC_NCFGR.MAXFS=1) and do not have a CRC error, an alignment error, nor a symbol error. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 700

38.8.81 GMAC TCP Checksum Errors Register

Name: GMAC_TCE Offset: 0x1AC Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 TCKER[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:0 – TCKER[7:0] TCP Checksum Errors This register counts the number of frames discarded due to an incorrect TCP checksum, but are between 64 and 1518 Bytes (1536 Bytes if GMAC_NCFGR.MAXFS=1) and do not have a CRC error, an alignment error, nor a symbol error. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 701

38.8.82 GMAC UDP Checksum Errors Register

Name: GMAC_UCE Offset: 0x1B0 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 UCKER[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:0 – UCKER[7:0] UDP Checksum Errors This register counts the number of frames discarded due to an incorrect UDP checksum, but are between 64 and 1518 Bytes (1536 Bytes if GMAC_NCFGR.MAXFS=1) and do not have a CRC error, an alignment error, nor a symbol error. SAMV71Q21RT GMAC - Ethernet MAC © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001555D-page 702

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