SAME70J19

Microchip Technology

SAM E70/S70/V70/V71 Family Silicon Errata and Data Sheet Clarification 2018

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Device Data Sheet (DS60001527C), except for the anomalies described in this document. IDs listed in the following tables. The silicon issues are summarized in 1. Silicon Issue Summary. following the discussion of silicon issues. shown in the following tables. Table 1. SAM V71 Silicon Device Identification

Table 2. SAM V70 Silicon Device Identification Table 3. SAM S70 Silicon Device Identification

Table 4. SAM E70 Silicon Device Identification

Refer to the “Chip Identifier (CHIPID)” section in the current Device Data Sheet (DS60001527C) for

detailed information on Chip Identification and Revision IDs for your specific device.

Silicon Issue Summary Table 1-1. Silicon Issue Summary Module Item and Feature Summary Affected Silicon Revisions A B AFEC 2.1 Write Protection The AFEC_CSELR register is not write- protected. X X AFEC 2.2 Performance The AFEC is sensitive to noise. Too much noise may lead to reduced AFEC performance, especially INL, DNL and SNR. X X AFEC 2.3 AOFF bit Changing the AOFF bit in the AFEC_COCR register during conversions is not safe. X X ARM Cortex-

3.1 ARM® Cortex®-M7 All issues related to the ARM r0p1 (for

MRLA) and r1p1 (and MRLB) cores are described on the ARM site. X X Boundary Scan Mode

4.1 Internal Regulator The internal regulator is OFF in

Boundary Scan mode. X Device 5.1 AHB Peripheral (AHBP) Port Frequency Ratio Peripheral accesses done through the AHBP with a Core/Bus ratio of 1/3 and 1/4 may lead to unpredictable results. X X Device 5.2 AHB Slave (AHBS) Port Latency Access DMA accesses done through the AHBS to the TCM with a Core/Bus ratio of 1/2, 1/3, and 1/4 may lead to latency due to one Wait state added to the access from the bus to AHBS. X XDMAC 6.1 TCM Accesses If TCM accesses are generated through the AHBS port of the core, only 32-bit accesses are supported. X X XDMAC 6.2 Byte and Half-Word Accesses If XDMAC is used to transfer 8-bit or 16- bit data in Fixed Source Address mode or Fixed Destination Address mode, source and destination addresses are incremented by 8-bit or 16-bit. X X XDMAC 6.3 Request Overflow Error When a DMA memory-to-memory transfer is performed, if the hardware request line selected by the field PERID bit in the XDMAC_CCx register toggles when the copy is enabled, the ROIS bit in the XDMAC_CISx register is set incorrectly. X X SAM E70/S70/V70/V71 Family Silicon Issue Summary © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 6

Module Item and Feature Summary Affected Silicon Revisions A B FFPI 7.1 Flash Programming The FFPI programs only 1 MB of Flash memory. X GMAC 8.1 Priority Queues On Revision A silicon, only three priority queues are available. X I2SC 9.1 Module Availability The Inter-IC Sound Controller (I2SC) is not available. X I2SC 9.2 Corrupted First Sent Data Immediately after the I2SC module is reset, the first data sent by the controller on the I2SDO line is corrupted. X MCAN 10.1 Non-ISO Operation The default frame format on Revision A silicon does not match the default format specified in the current device data sheet. X MCAN 10.2 MCAN_CCCR Register In Revision A silicon, the MCAN CC Control register content does not match the content of the current device data sheet. X MCAN 10.3 Transmitter Delay Compensation Value (TDCV) Bits In Revision A silicon, the Transmitter Delay Compensation Value (TDCV) bit field does not match the content in the current device data sheet. X MCAN 10.4 MCAN_PSR Register In Revision A silicon, the content of the MCAN Protocol Status register differs from the content in the current device data sheet. X MCAN 10.5 MCAN_IR Register In Revision A silicon, the content of the MCAN Interrupt register differs from the content in the current device data sheet. X MCAN 10.6 MCAN_IE Register On Revision A silicon, the content in the MCAN Interrupt Enable register does not match the content in the current device data sheet. X MCAN 10.7 MCAN_ILS Register On Revision A silicon, the content in the MCAN Interrupt Line Support Register does not match the content in the current device data sheet. X SAM E70/S70/V70/V71 Family Silicon Issue Summary © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 7

Module Item and Feature Summary Affected Silicon Revisions A B MCAN 10.8 MCAN Data Bit Timing and Prescaler Register On Revision A silicon, the MCAN Data Bit Timing and Prescaler register (MCAN_DBTP) is named MCAN Fast Bit Timing and Prescaler register (MCAN_FBTP). X MCAN 10.9 MCAN Nominal Bit Timing and Prescaler Register On Revision A silicon, the MCAN Nominal Bit Timing and Prescaler register (MCAN_NBTP) is named MCAN Bit Timing and Prescaler register (MCAN_BTP). X MCAN 10.10 MCAN Transmitter Delay Compensation Register In Revision A silicon, the MCAN Transmitter Delay Compensation Register (MCAN_TDCR) does not exist. X MCAN 10.11 Timestamping Function On Revision A silicon, TC Counter 0 is not connected to PCK6 and PCK7; therefore, the timestamping functionality does not exist. X PIO 11.1 PIO Line Configuration for AFEC and DACC Analog Inputs To enable the analog inputs, AFE_ADx or DACx, the pull-up resistors on the I/O lines must be disabled in the PIO user interface prior to writing registers AFEC_CHER or DACC_CHER. X X PMC 12.1 Wait Mode Exit Fail from Flash The delay to exit from Wait mode is too short to respect the Flash wake-up time from Stand-by mode and Deep Power- down mode. This delay may lead to bad opcode fetching. X X PMC 12.2 PMC_OCR Register Calibration Reporting When reading the PMC_OCR register with the SEL8 and SEL12 bits cleared, the CAL8 and CAL12 bits are not updated with the manufacturing calibration bits of the Main RC Oscillator. However, the Main RC Oscillator is loaded with this manufacturing calibration data. X X QSPI 13.1 Module Hangs with Long DLYCS The QSPI module hangs if a command is written to any QSPI register during the delay defined in the DLYCS bit. There is no status bit to flag the end of the delay. X X SAM E70/S70/V70/V71 Family Silicon Issue Summary © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 8

Module Item and Feature Summary Affected Silicon Revisions A B QSPI 13.2 WDRBT When the QSPI is in SPI mode, the WDRBT feature is not functional. X X RTC 14.1 RTC_CALR Reset Value On Revision A silicon, the reset value of the RTC_CALR register is 0x01E11220. X SDRAMC 15.1 SDRAM Controller Scrambling Use Limitation The scrambling/unscrambling feature of the SDRAM Controller (SDRAMC) has a use limitation. X X SDRAMC 15.2 USB and SDRAM Concurrent Access Issue USB module functionality is adversely affected with concurrent SDRAM access. X X SMC 16.1 SMC_WPSR Register Write Protection When the write protection feature is enabled and a write attempt into a protected register is performed, the Write Protection Violation Source (WPVSRC) bit field in the SMC_WPSR register does not report the right violation source. X SSC 17.1 Inverted Left/Right Channels When the SSC is in Slave mode, the TF signal is derived from the codec and not controlled by the SSC. X SSC 17.2 Unexpected TD Output Delay An unexpected delay on TD output may occur when the SSC is configured under certain conditions. X X SUPC 18.1 Write-Protection The SUPC_WUIR register is not write- protected. X X SUPC 18.2 Programmable Clock Controller Programmable Clock Outputs, PCK0– PCK2, selected from the clock generator outputs to drive the device PCK pins are not supported and should not be used. X X TWIHS 19.1 I2C Hold Timing Incompatibility The TWIHS module is not compatible with I2C hold timing. X X TWIHS 19.2 Clear Command A bus reset using the CLEAR bit of the TWIHS Control register does not work correctly during a bus busy state. X X USART 20.1 Flow Control with DMA The RTS signal is not connected to the DMA. Therefore, when DMA is used, Flow Control is not supported. X X SAM E70/S70/V70/V71 Family Silicon Issue Summary © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 9

Module Item and Feature Summary Affected Silicon Revisions A B USART 20.2 Bad Frame Detection If a bad frame is received (i.e., incorrect baud rate) with the last data bit being sampled at 1, frame error detection does not occur. X X USBHS 21.1 USBHS Host Does Not Function in Low- Speed Mode The USB Host does not function in Low- Speed mode. X USBHS 21.2 64-pin LQFP Package The USBHS module does not function in 64-pin LQFP package devices. X X USBHS 21.3 NO DMA for Endpoint 7 The DMA feature is not available for Pipe/Endpoint 7. X X DACC 22.1 Interpolation Mode Interpolation Mode is not functional X X SAM E70/S70/V70/V71 Family Silicon Issue Summary © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 10

Analog Front-End Controller (AFEC)

2.1 Write Protection

The AFEC_CSELR register is not write-protected. Workaround None. Affected Silicon Revisions A B X X

2.2 Performance

The AFEC is sensitive to noise. Too much noise may lead to reduced AFEC performance, especially INL, DNL and SNR. The following situations generate noise:

Using a 64-pin QFP package option (it does not have the VREFN pin)
Device activity (that is, clock tree)
External components (that is, missing on-board supply decoupling capacitors) Workaround Adapt the environment to the expected level of performances. Affected Silicon Revisions A B X X

2.3 AOFF bit

Changing the AOFF bit in the AFEC_COCR register during conversions is not safe. The recommended value of the AOFF bit is 512 (the default value is zero). Different values are possible for each channel. The AOFF bit is read and updated during the AFE start-up sequence and at the end of each conversion. If during AFE idle time (no conversion is on-going) the user updates the AOFF bit for the next channel to be converted, the next conversion will be incorrect. Workaround The value of the AOFF bit can be updated only if the AFEC module is restarted, or if two conversions are run; the second one will have the correct AOFF bit setting. SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 11

ARM Cortex-M7

3.1 ARM® Cortex®-M7

All issues related to the ARM r0p1 (for MRLA) and r1p1 (and MRLB) cores are described on the ARM website. Workaround Refer to the following ARM documentation:

For ARM Cortex-M7 r0p1 core (MRLA device): https://silver.arm.com/download/download.tm? pv=2004343
For ARM Cortex-M7 r1p1 core (MRLB device): https://silver.arm.com/download/download.tm? pv=3257391&p=1929427
ARM Embedded Trace Macrocell CoreSight ETM–M7 (TM975) Software Developers Errata Notice: https://silver.arm.com/download/download.tm?pv=1998309 Affected Silicon Revisions A B X X SAM E70/S70/V70/V71 Family ARM Cortex-M7 © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 13

Boundary Scan Mode

4.1 Internal Regulator

The internal regulator is OFF in Boundary Scan mode. Workaround The user must provide external VDDCORE (1.2V) to perform Boundary Scan mode. Affected Silicon Revisions A B X X SAM E70/S70/V70/V71 Family Boundary Scan Mode © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 14

Device

5.1 AHB Peripheral (AHBP) Port Frequency Ratio

Peripheral accesses done through the AHBP with a Core/Bus ratio of 1/3 and 1/4 may lead to unpredictable results. Workaround The user must use a Core/Bus frequency ratio of 1 or 1/2. Affected Silicon Revisions A B X X

5.2 AHB Slave (AHBS) Port Latency Access

DMA accesses done through the AHBS to the TCM with a Core/Bus ratio of 1/2, 1/3, and 1/4 may lead to latency due to one Wait state added to the access from the bus to AHBS. Workaround The user must use only the Core/Bus frequency ratio of 1 to guarantee the length of the access. Affected Silicon Revisions A B X X SAM E70/S70/V70/V71 Family Device © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 15

Extended DMA Controller (XDMAC)

6.1 TCM Accesses

If TCM accesses are generated through the AHBS port of the core, only 32-bit accesses are supported. Accesses that are not 32-bit aligned may overwrite bytes at the beginning and at the end of 32-bit words. Workaround The user application must use 32-bit aligned buffers and buffers with a size of a multiple of 4 bytes when transferring data to or from the TCM through the AHBS port of the core. Affected Silicon Revisions A B X X

6.2 Byte and Half-Word Accesses

If XDMAC is used to transfer 8-bit or 16-bit data in Fixed Source Address mode or Fixed Destination Address mode, source and destination addresses are incremented by 8-bit or 16-bit. Workaround The user can resolve this issue by setting the source and destination addressing mode to use microblock and data striding with microblock stride set to 0 and data stride set to -1. Affected Silicon Revisions A B X X

6.3 Request Overflow Error

When a DMA memory-to-memory transfer is performed, if the hardware request line selected by the field PERID bit in the XDMAC_CCx register toggles when the copy is enabled, the ROIS bit in the XDMAC_CISx register is set incorrectly. The memory transfer proceeds normally and the data area is correctly transferred. Workaround Configure the PERID bit to an unused peripheral ID. Affected Silicon Revisions A B X X SAM E70/S70/V70/V71 Family Extended DMA Controller (XDMAC) © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 16

Fast Flash Programming Interface (FFPI)

7.1 Flash Programming

The FFPI programs only 1 MB of Flash memory. Workaround None. Affected Silicon Revisions A B X X SAM E70/S70/V70/V71 Family Fast Flash Programming Interface (FFPI) © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 17

Ethernet MAC (GMAC)

8.1 Priority Queues

On Revision A silicon, only three priority queues are available with the following sizes: Queue Number Queue Size 2 (highest priority) 4 KB 1 2 KB 0 (lowest priority) 2 KB Workaround None. Affected Silicon Revisions A B X SAM E70/S70/V70/V71 Family Ethernet MAC (GMAC) © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 18

Inter-IC Sound Controller (I2SC)

9.1 Module Availability

The Inter-IC Sound Controller (I2SC) is not available. Workaround None. Affected Silicon Revisions A B X

9.2 Corrupted First Sent Data

Immediately after the I2SC module is reset, the first data sent by the controller on the I2SDO line is corrupted. Any data that follows is not affected. Workaround None. Affected Silicon Revisions A B X SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 19

Controller Area Network (MCAN)

10.1 Non-ISO Operation

The default frame format on Revision A silicon does not match the default format specified in the current device data sheet. Workaround To retain Revision A behavior, set the MCAN_CCCR.NISO bit to '1'. Affected Silicon Revisions A B X

10.2 MCAN_CCCR Register

In Revision A silicon, the MCAN CC Control register content does not match the content of the current device data sheet.

NISO bit is missing
EFBI bit is named FDBS
PXHD bit is named FDO
BRSE bit and FDOE bit are named CME[1:0]
CMR[1:0] bits are present Workaround None. Affected Silicon Revisions A B X

10.3 Transmitter Delay Compensation Value (TDCV) Bits

In Revision A silicon, the Transmitter Delay Compensation Value (TDCV) bit field does not match the content in the current device data sheet. In Revision A silicon, the TDCV bits are located in the MCAN_TEST register. In the current device data sheet, the TDCV bits are located in the MCAN_PSR register. Workaround None. SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 20

Affected Silicon Revisions A B X

10.4 MCAN_PSR Register

In Revision A silicon, the content of the MCAN Protocol Status register differs from the content in the current device data sheet.

PXE bit is not available
RFDF bit is named REDL
DLEC[2:0] bits are named FLEC[2:0] Workaround None. Affected Silicon Revisions A B X

10.5 MCAN_IR Register

In Revision A silicon, the content of the MCAN Interrupt register differs from the content in the current device data sheet.

STE and FOE bits are present
ARA bit is replaced by the ACKE bit
PED bit is replaced by the BE bit
PEA bit is replaced by the CRCE bit Workaround None. Affected Silicon Revisions A B X

10.6 MCAN_IE Register

On Revision A silicon, the content in the MCAN Interrupt Enable register does not match the content in the current device data sheet.

STEE and FOEE bits are present
ARAE bit is replaced by the ACKEE bit SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 21

PEDE bit is replaced by the BEE bit
PEAE bit is replaced by the CRCEE bit Workaround None. Affected Silicon Revisions A B X

10.7 MCAN_ILS Register

On Revision A silicon, the content in the MCAN Interrupt Line Support Register does not match the content in the current device data sheet.

STEL and FOEL bits are present
ARAL bit is replaced by the ACKEL bit
PEDL bit is replaced by the BEL bit
PEAL bit is replaced by the CRCEL bit Workaround None. Affected Silicon Revisions A B X

10.8 MCAN Data Bit Timing and Prescaler Register

On Revision A silicon, the MCAN Data Bit Timing and Prescaler register (MCAN_DBTP) is named MCAN Fast Bit Timing and Prescaler register (MCAN_FBTP). Workaround When using Revision A silicon, ensure that the name MCAN_FBTP is used. Affected Silicon Revisions A B X

10.9 MCAN Nominal Bit Timing and Prescaler Register

On Revision A silicon, the MCAN Nominal Bit Timing and Prescaler register (MCAN_NBTP) is named MCAN Bit Timing and Prescaler register (MCAN_BTP). SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 22

When using Revision A silicon, ensure that the name MCAN_BTP is used. Affected Silicon Revisions A B X

10.10 MCAN Transmitter Delay Compensation Register

In Revision A silicon, the MCAN Transmitter Delay Compensation Register (MCAN_TDCR) does not exist. Workaround The transmit delay compensation offset is configured in the TDCO field of the MCAN_FBTP register. Affected Silicon Revisions A B X

10.11 Timestamping Function

On Revision A silicon, TC Counter 0 is not connected to PCK6 and PCK7; therefore, the timestamping functionality does not exist. Workaround None. Affected Silicon Revisions A B X SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 23

Parallel Input/Output (PIO)

11.1 PIO Line Configuration for AFEC and DACC Analog Inputs

To enable the analog inputs, AFE_ADx or DACx, the pull-up resistors on the I/O lines must be disabled in the PIO user interface prior to writing registers AFEC_CHER or DACC_CHER. Workaround None. Affected Silicon Revisions A B X X SAM E70/S70/V70/V71 Family Parallel Input/Output (PIO) © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 24

Power Management Controller (PMC)

12.1 Wait Mode Exit Fail from Flash

The delay to exit from Wait mode is too short to respect the Flash wake-up time from Stand-by mode and Deep Power-down mode. This delay may lead to bad opcode fetching. Workaround 1 If Flash in Stand-by mode (FLPM = 0) or in Deep Power-down mode (FLPM = 1) is used, run the wake-up routine from SRAM. This option provides a slight improvement in power consumption. Workaround 2 If Flash in Stand-by mode (FLPM = 0) or in Deep Power-down mode (FLPM = 1) is used, run the wake-up routine from SRAM. This option provides a slight improvement in power consumption. Affected Silicon Revisions A B X X

12.2 PMC_OCR Register Calibration Reporting

When reading the PMC_OCR register with the SEL8 and SEL12 bits cleared, the CAL8 and CAL12 bits are not updated with the manufacturing calibration bits of the Main RC Oscillator. However, the Main RC Oscillator is loaded with this manufacturing calibration data. Workaround To recover the manufacturing calibration bits of the Main RC oscillator, use the following steps: 1. Execute the ‘Get CALIB Bit’ command by writing the FCMD bit in the EEFC_FCR register with the GCALB command. 2. Read the EEFC_FRR register. The 8 MHz RC calibration bits are EEFC_FRR bits [17-11] and the the 12 MHz RC calibration bits are EEFC_FRR bits [25-19]. Affected Silicon Revisions A B X X SAM E70/S70/V70/V71 Family Power Management Controller (PMC) © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 25

Quad Serial Peripheral Interface (QSPI)

13.1 Module Hangs with Long DLYCS

The QSPI module hangs if a command is written to any QSPI register during the delay defined in the DLYCS bit. There is no status bit to flag the end of the delay. Workaround The DLYCS bit defines a minimum period over which the Chip Select is deasserted, which is required by some memories. This delay is generally less than 60 ns and comprises internal execution time, arbitration, and latencies. Therefore, the DLYCS bit must be configured to be slightly higher than the value specified for the slave device. The software must wait for at least this same period of time before a command can be written to the QSPI module. Affected Silicon Revisions A B X X

13.2 WDRBT

When the QSPI is configured in SPI mode, the Wait Data Read Before Transfer (WDRBT) feature does not work. Workaround None. Affected Silicon Revisions A B X X SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 26

Real-Time Clock (RTC)

14.1 RTC_CALR Reset Value

On Revision A silicon, the reset value of the RTC_CALR register is 0x01E11220. Workaround None. Affected Silicon Revisions A B X SAM E70/S70/V70/V71 Family Real-Time Clock (RTC) © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 27

SDRAM Controller (SDRAMC)

15.1 SDRAM Controller Scrambling Use Limitation

The scrambling/unscrambling feature of the SDRAM Controller (SDRAMC) has a use limitation. Workaround The read of a scrambled area must be performed with the same type of access done during the write of this area. As an example, it is recommended to write using 32-bit words and read 32-bit words. Affected Silicon Revisions A B X X

15.2 USB and SDRAM Concurrent Access Issue

USB module functionality is adversely affected with concurrent SDRAM access. Workaround Ensure that no concurrent module operations when using both SDRAM and USB. Affected Silicon Revisions A B X X SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 28

Static Memory Controller (SMC)

16.1 SMC_WPSR Register Write Protection

When the write protection feature is enabled and a write attempt into a protected register is performed, the Write Protection Violation Source (WPVSRC) bit field in the SMC_WPSR register does not report the right violation source. As a consequence, the value in the WPVSRC bit field is incorrect. This issue does not affect the write protection feature itself, which is fully functional. Workaround None. Affected Silicon Revisions A B X SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 29

Serial Synchronous Controller (SSC)

17.1 Inverted Left/Right Channels

When the SSC is in Slave mode, the TF signal is derived from the codec and not controlled by the SSC. The SSC transmits the data when detecting the falling edge on the TF signal after the SSC transmission is enabled. In some cases of overflow, a left/right channel inversion may occur. When this occurs, the SSC must be reinitialized. Workaround Using the SSC in Master mode will ensure that TF is controlled by the SSC and no error occurs. If the SSC must be used in TF Slave mode, the SSC must be started by writing TXEN and RXEN synchronously with the TXSYN flag rising in the SSC_SR. Affected Silicon Revisions A B X

17.2 Unexpected TD Output Delay

An unexpected delay on TD output may occur when the SSC is configured with the following conditions:

The START bit in the RCMR register = Start on falling edge/Start on Rising edge/Start on any edge
The FSOS bit in the RFMR register = None (input)
The START bit in the TCMR register = Receive Start Under these conditions, an unexpected delay of two or three system clock cycles is added to the TD output. Workaround None. Affected Silicon Revisions A B X X SAM E70/S70/V70/V71 Family Serial Synchronous Controller (SSC) © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 30

Supply Controller (SUPC)

18.1 Write-Protection

The SUPC_WUIR register is not write-protected. Workaround None. Affected Silicon Revisions A B X X

18.2 Programmable Clock Controller

Programmable Clock Outputs, PCK0 and PCK2, selected from the clock generator outputs to drive the device PCK pins are not supported and should not be used. Workaround Use PCK1. Table 18-1. Affected Silicon Revisions A B X X SAM E70/S70/V70/V71 Family Supply Controller (SUPC) © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 31

TWI High-Speed (TWIHS)

19.1 I2C Hold Timing Incompatibility

The TWIHS module is not compatible with I2C hold timing. The divider to program the hold time is too short to achieve the expected hold time at high frequency. The achieved time is 227 ns maximum at 150 MHz, instead of the required 300 ns. Workaround None. Affected Silicon Revisions A B X X

19.2 Clear Command

A bus reset using the CLEAR bit of the TWIHS Control register does not work correctly during a bus busy state. Workaround Reconfigure the TWCK line in GPIO output and generate nine clock pulses through software to unlock the I2C device. Once this is done, the TWCK line can be reconfigured as a peripheral line. Affected Silicon Revisions A B X X SAM E70/S70/V70/V71 Family TWI High-Speed (TWIHS) © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 32

Universal Synchronous Asynchronous Receiver Transmitter (USART)

20.1 Flow Control with DMA

The RTS signal is not connected to the DMA. Therefore, when DMA is used, Flow Control is not supported. Workaround None. Affected Silicon Revisions A B X X

20.2 Bad Frame Detection

If a bad frame is received (i.e., incorrect baud rate) with the last data bit being sampled at 1, frame error detection does not occur. Workaround There is no general workaround. When performing baud rate detection with receive part, the transmit frame must be sent with a parity bit set to '0'. Affected Silicon Revisions A B X X SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transm... © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 33

USB High-Speed (USBHS)

21.1 USBHS Host Does Not Function in Low-Speed Mode

The USB Host does not function in Low-Speed mode. Workaround None. Affected Silicon Revisions A B X 21.2 64-pin LQFP Package The USBHS module does not function in 64-pin LQFP package devices. Workaround None. Affected Silicon Revisions A B X X

21.3 NO DMA for Endpoint 7

The DMA feature is not available for Pipe/Endpoint 7. Workaround None. Affected Silicon Revisions A B X X SAM E70/S70/V70/V71 Family USB High-Speed (USBHS) © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 34

Digital to Analog Converter Controller (DACC)

22.1 Interpolation Mode

The Interpolation mode that allows Oversampling Ratio (OSR) of 2x, 4x, 8x, 16x, or 32x is not functional. Workaround None. Affected Silicon Revisions A B X X SAM E70/S70/V70/V71 Family Digital to Analog Converter Controller (DACC) © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 35

Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS60001527C): Note: Corrections in tables, registers, and text are shown in bold. Where possible, the original bold text formatting has been removed for clarity.

23.1 Controller Area Network (MCAN)

The MCAN_CREL register reset value documented in the data sheet is applicable to devices with silicon revision B. The MCAN_CREL register reset value for devices with silicon revision A is 0x30130506.

23.2 Quad Serial Peripheral Interface (QSPI)

The QSPI in SPI mode does not support the Wait Data Read Before Transfer feature, the WDRBT bit in the SPI Mode Register (SPI_MR) must be ignored. SAM E70/S70/V70/V71 Family Data Sheet Clarifications © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 36

Appendix A: Revision History Revision C (11/2018) The following silicon issues were added:

18.2 Programmable Clock Controller
22.1 Interpolation Mode The following Data Sheet Clarifications were added:
Controller Area Network (MCAN)
Quad Serial Peripheral Interface (QSPI) Revision B (8/2018) This revision was updated for Revision B silicon. The following silicon issue was added:
13.2 WDRBT Revision A (11/2017) Initial release of this document. SAM E70/S70/V70/V71 Family Appendix A: Revision History © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 37

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Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives Customer Change Notification Service Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at http://www.microchip.com/. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. Customer Support Users of Microchip products can receive assistance through several channels:
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support Microchip Devices Code Protection Feature Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code. SAM E70/S70/V70/V71 Family © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 38

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Legal Notice Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. SAM E70/S70/V70/V71 Family © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 39

© 2017, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-3831-1 Quality Management System Certified by DNV ISO/TS 16949 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. SAM E70/S70/V70/V71 Family © 2018 Microchip Technology Inc. Datasheet Errata DS80000767C-page 40

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Product Information

SAME70J19 specifications and overview.

Summary

SAM E70/S70/V70/V71 Family Silicon Errata and Data Sheet Clarification 2018

Description

SAM E70/S70/V70/V71 Family Silicon Errata and Data Sheet Clarification 2018

Source title SAME70J19 Datasheet(PDF) - Microchip Technology

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