Microcontroller

SAMC21

Microchip Technology

32-bit ARM Cortex-M0+ 5V Support, CAN-FD, PTC and Advanced Analog 2019

Manufacturer: Microchip Technology

Document: 1293 Pages / 10Mb

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Technical content

Features

2.7V – 5.5V, -40°C to +125°C, DC to 48 MHz Core
ARM ® Cortex®-M0+ CPU running at up to 48 MHz – Single-cycle hardware multiplier – Micro Trace Buffer – Memory Protection Unit (MPU) Memories
32/64/128/256 KB in-system self-programmable Flash
1/2/4/8 KB independent self-programmable Flash for EEPROM emulation
4/8/16/32 KB SRAM Main Memory System
Power-on Reset (POR) and Brown-out Detection (BOD)
Internal and external clock options with 48 MHz to 96 MHz Fractional Digital Phase Locked Loop (FDPLL96M)
External Interrupt Controller (EIC) (Interrupt pin debouncing is only available in SAM C21N)
16 external interrupts – Hardware debouncing (only on the 100Pin TQFP)
One non-maskable interrupt
Two-pin Serial Wire Debug (SWD) programming, test, and debugging interface Low-Power
Idle and Standby Sleep modes
SleepWalking peripherals Peripherals
Hardware Divide and Square Root Accelerator (DIVAS)
12-channel Direct Memory Access Controller (DMAC)
12-channel Event System
Up to eight 16-bit Timer/Counters (TC), configurable as either (see Note): Note: Maximum and minimum capture is only available in SAM C21N devices. – One 16-bit TC with compare/capture channels – One 8-bit TC with compare/capture channels © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 1

– One 32-bit TC with compare/capture channels, by using two TCs

Two 24-bit Timer/Counters and one 16-bit Timer/Counter for Control (TCC), with extended functions: – Up to four compare channels with optional complementary output – Generation of synchronized pulse width modulation (PWM) pattern across port pins – Deterministic fault protection, fast decay and configurable dead-time between complementary output – Dithering that increase resolution with up to 5 bit and reduce quantization error
Frequency Meter (The division reference clock is only available in the SAM C21N)
32-bit Real Time Counter (RTC) with clock/calendar function
Watchdog Timer (WDT)
CRC-32 generator
Up to two Controller Area Network (CAN) interfaces: – CAN 2.0A/B and CAN-FD (ISO 11898-1:2015)
Each CAN interface have two selectable pin locations to switch between two external CAN transceivers (without the need for an external switch)
Up to eight Serial Communication Interfaces (SERCOM), each configurable to operate as either: – USART with full-duplex and single-wire half-duplex configuration – I2C up to 3.4 MHz (Except SERCOM6 and SERCOM7) – SPI – LIN master/slave – RS-485 – PMBus
One Configurable Custom Logic (CCL)
Up to Two 12-bit, 1 Msps Analog-to-Digital Converter (ADC) with up to 12 channels each (20 unique channels) – Differential and single-ended input – Automatic offset and gain error compensation – Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution
One 16-bit Sigma-Delta Analog-to-Digital Converter (SDADC) with up to 3 differential channels
10-bit, 350 ksps Digital-to-Analog Converter (DAC)
Up to four Analog Comparators (AC) with Window Compare function
Integrated Temperature Sensor
Peripheral Touch Controller (PTC) – 256-Channel capacitive touch and proximity sensing I/O
Up to 84 programmable I/O pins Qualification
AEC-Q100 Grade 1 (-40°C to 125°C) Packages
100-pin TQFP
64-pin TQFP, VQFN
56-pin WLCSP SAM C20/C21 Family Data Sheet © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 2

48-pin TQFP, VQFN
32-pin TQFP, VQFN General
Drop in compatible with SAM D20 and SAM D21 (see Note) Note: Only applicable for 32-pin, 48-pin, and 64-pin TQFP and VQFN packages. SAM C20/C21 Family Data Sheet © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 3

SERCOM USART - SERCOM Synchronous and Asynchronous Receiver and SAM C20/C21 Family Data Sheet © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 9

AEC Q-100 Grade 1, 125°C Electrical Characteristics (SAM C20/C21 E/G/J)... 1217 SAM C20/C21 Family Data Sheet © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 12

Configuration Summary Table 1-1. SAM C20 Device-specific Features Device Flash (KB) SRAM (KB) ATSAMC20E15 32 4 ATSAMC20E16 64 8 ATSAMC20E17 128 16 ATSAMC20E18 256 32 ATSAMC20G15 32 4 ATSAMC20G16 64 8 ATSAMC20G17 128 16 ATSAMC20G18 256 32 ATSAMC20J15 32 4 ATSAMC20J16 64 8 ATSAMC20J17 128 16 ATSAMC20J18 256 32 ATSAMC20N17 128 16 ATSAMC20N18 256 32 Table 1-2. SAM C21 Device-specific Features Device Flash (KB) SRAM (KB) ATSAMC21E15 32 4 ATSAMC21E16 64 8 ATSAMC21E17 128 16 ATSAMC21E18 256 32 ATSAMC21G15 32 4 ATSAMC21G16 64 8 ATSAMC21G17 128 16 ATSAMC21G18 256 32 ATSAMC21J15 32 4 ATSAMC21J16 64 8 ATSAMC21J17 128 16 ATSAMC21J18 256 32 ATSAMC21N17 128 16 SAM C20/C21 Family Data Sheet Configuration Summary © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 14

Device Flash (KB) SRAM (KB) ATSAMC21N18 256 32 Table 1-3. SAM C21 Family Features SAM C21N SAM C21J SAM C21G SAM C21E Pins 100 64 (56 for WLCSP) 48 32 General Purpose I/O-pins (GPIOs) 84 52 (44 for WLCSP) 38 26 Flash 256/128 KB 256/128/64/32 KB 256/128/64/32 KB 256/128/64/32 KB Flash RWW section 8/4 KB 8/4/2/1 KB 8/4/2/1 KB 8/4/2/1 KB System SRAM 32/16 KB 32/16/8/4 KB 32/16/8/4 KB 32/16/8/4 KB Timer Counter (TC) instances 8 5 5 5 Waveform output channels per TC instance 2 2 2 2 TC Maximum and Minimum Capture Yes No No No Timer Counter for Control (TCC) instances 3 3 3 3 Waveform output channels per TCC DMA channels 12 12 12 12 CAN interface 2 2 2 1 Configurable Custom Logic (CCL) (LUTs) 4 4 4 4 Serial Communication Interface (SERCOM) instances 8 6 6 4 Divide and Square Root Accelerator (DIVAS) Yes Yes Yes Yes Analog-to-Digital Converter (ADC) channels 20 20 14 10 Analog-to-Digital Converter (ADC) instances 2 2 2 2 Sigma-Delta Analog-to-Digital Converter (SDADC) channels 3 3 2 1 Analog Comparators (AC) 4 4 4 4 Digital-to-Analog Converter (DAC) channels 1 1 1 1 SAM C20/C21 Family Data Sheet Configuration Summary © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 15

SAM C21N SAM C21J SAM C21G SAM C21E Temperature Sensor (TSENS)(1) 1 1 1 1 Real-Time Counter (RTC) Yes Yes Yes Yes RTC alarms 1 1 1 1 RTC compare values One 32-bit value or two 16-bit values One 32-bit value or two 16-bit values One 32-bit value or two 16-bit values One 32-bit value or two 16-bit values External Interrupt lines 16 with HW debouncing 16 16 16 Peripheral Touch Controller (PTC) Number of self-capacitance channels (Y-lines) 32 32 22 16 Peripheral Touch Controller (PTC) Number of mutual-capacitance channels (X x Y lines) 256 (16x16) 256 (16x16) 121 (11x11) 64 (8x8) Frequency Meter (FREQM) reference clock divider Yes Yes Yes Yes Maximum CPU frequency 48 MHz Packages TQFP VQFN TQFP WLCSP VQFN TQFP VQFN TQFP Oscillators 32.768 kHz crystal oscillator (XOSC32K) 0.4-32 MHz crystal oscillator (XOSC) 32.768 kHz internal oscillator (OSC32K) 32 kHz ultra low-power internal oscillator (OSCULP32K)

48 MHz high-accuracy internal oscillator (OSC48M)

96 MHz Fractional Digital Phased Locked Loop (FDPLL96M)

Event System channels 12 12 12 12 SW Debug Interface Yes Yes Yes Yes Watchdog Timer (WDT) Yes Yes Yes Yes Note: 1. TSENS is not available in AEC Q-100 qualified device part numbers. SAM C20/C21 Family Data Sheet Configuration Summary © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 16

Table 1-4. SAM C20 Family Features SAM C20N SAM C20J SAM C20G SAM C20E Pins 100 64 (56 for WLCSP) 48 (44 for WLCSP) 32 General Purpose I/O-pins (GPIOs) 84 52 38 26 Flash 256/128 KB 256/128/64/32 KB 256/128/64/32 KB 256/128/64/32 KB Flash RWW section 8/4 KB 8/4/2/1 KB 8/4/2/1 KB 8/4/2/1 KB System SRAM 32/16 KB 32/16/8/4 KB 32/16/8/4 KB 32/16/8/4 KB Timer Counter (TC) instances 8 5 5 5 Waveform output channels per TC instance 2 2 2 2 TC Maximum and Minimum Capture Yes No No No Timer Counter for Control (TCC) instances 3 3 3 3 Waveform output channels per TCC DMA channels 12 6 6 6 Configurable Custom Logic (CCL) (LUTs) 4 4 4 4 Serial Communication Interface (SERCOM) instances 8 4 4 4 Divide and Square Root Accelerator (DIVAS) Yes Yes Yes Yes Analog-to-Digital Converter (ADC) channels 12 12 12 10 Analog-to-Digital Converter (ADC) instances 1 1 1 1 Analog Comparators (AC) 4 2 2 2 Real-Time Counter (RTC) Yes Yes Yes Yes RTC alarms 1 1 1 1 RTC compare values One 32-bit value or two 16-bit values One 32-bit value or two 16-bit values One 32-bit value or two 16-bit values One 32-bit value or two 16-bit values External Interrupt lines 16 with HW debouncing 16 16 16 SAM C20/C21 Family Data Sheet Configuration Summary © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 17

SAM C20N SAM C20J SAM C20G SAM C20E Peripheral Touch Controller (PTC) Number of self-capacitance channels (Y-lines) 32 32 22 16 Peripheral Touch Controller (PTC) Number of mutual-capacitance channels (X x Y lines) 256 (16x16) 256 (16x16) 120 (12x10) 60 (10x6) Frequency Meter (FREQM) reference clock divider Yes Yes Yes Yes Maximum CPU frequency 48 MHz Packages TQFP VQFN TQFP WLCSP VQFN TQFP VQFN TQFP Oscillators 32.768 kHz crystal oscillator (XOSC32K) 0.4-32 MHz crystal oscillator (XOSC) 32.768 kHz internal oscillator (OSC32K) 32 kHz ultra low-power internal oscillator (OSCULP32K) Event System channels 6 6 6 6 SW Debug Interface Yes Yes Yes Yes Watchdog Timer (WDT) Yes Yes Yes Yes Related Links 6. I/O Multiplexing and Considerations SAM C20/C21 Family Data Sheet Configuration Summary © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 18

Ordering Information ATSAMC 21 N 18 A - M U T Product Family E = 32 Pins G = 48 Pins J = 64 Pins N = 100 Pins No character = Tray (Default) T = Tape and Reel U = -40 - 85°C Matte Sn Plating N = -40 - 105°C Matte Sn Plating Z = -40°C - 125°C Matte Sn Plating (AEC-Q100 Qualified) A = TQFP M = VQFN U = WLCSP 21 = Cortex M0+ CPU, DMA, CAN, 16-bit SDADC SAMC = 5V Microcontroller Product Series Flash Memory Density Device Variant A = Default Variant Pin Count Package Carrier Package Grade Package Type 18 = 256KB 17 = 128KB 16 = 64KB 15 = 32KB 20 = Cortex M0+ CPU, DMA ;3Ϳ (4)(5) Note: 1. Not all combinations are valid. The available ordering numbers are listed in the Configuration Summary. 2. SAM C2xN product is available only for the 105°C temperature grade. 3. The AEC-Q100 Grade 1 qualified version is only offered for SAM C20/C21 E/G/J in the TQFP and VQFN packages. The VQFN package will have wettable flanks, and both TQFP and VQFN packages are assembled with gold bond wires. 4. Devices in the WLCSP package include a factory programmed Bootloader. Please contact your local Microchip sales office for more information. 5. The WLCSP package type is available only with the package Grade U. SAM C20/C21 Family Data Sheet

Ordering Information

Block Diagram Figure 3-1. System Block Diagram for SAM C20/C21 6 x SERCOM 8 x Timer Counter AHB-APB BRIDGE C M MHIGH SPEED BUS MATRIX PORT PORT SERIAL WIRESWDIO S CORTEX-M0+ PROCESSOR Fmax 48 MHz SWCLK DEVICE SERVICE UNIT AHB-APB BRIDGE A 2x 12-CHANNEL 12-bit ADC 1MSPS AIN[11..0] VREFA AIN[7..0] S SRAM CONTROLLER 32/16KB RAM M 5x TIMER / COUNTER EVENT SYSTEM S 6x SERCOM

4 ANALOG

X[15..0] Y[15..0] PERIPHERAL TOUCH CONTROLLER AHB-APB BRIDGE B VREFA VOUT 10-bit DAC PERIPHERAL ACCESS CONTROLLER S PAD0 WO1 PAD1 PAD2 PAD3 WO0 256/128KB RWW NVM NVM CONTROLLER Cache M DMA 2x CAN 3x TIMER / COUNTER FOR CONTROL WOn IOBUS DMA DMA DMA DMA DMA MICRO TRACE BUFFER S WO0 WO1 TxD RxD 3-CHANNEL 16-bit SDADC 3KSPS AIN[5..0] VREFB DMA REAL TIME COUNTER WATCHDOG TIMER RESETN OSCILLATORS CONTROLLER XOUT XIN XOUT32 XIN32 OSCULP32K OSC32K OSC48M XOSC32K XOSC EXTERNAL INTERRUPT CONTROLLER MAIN CLOCKS CONTROLLER EXTINT[15..0] NMI GCLK_IO[7..0] FDPLL96M GENERIC CLOCK CONTROLLER POWER MANAGER RESET CONTROLLER OSC32K CONTROLLER SUPPLY CONTROLLER VREFBOD55 VREG DivideAccellerator S DMA TEMPERATURE SENSOR FREQUENCY METER 6 x SERCOM 3x TIMER / COUNTER 2x SERCOM PAD0 WO1 PAD1 PAD2 PAD3 WO0 DMA DMA AHB-APB BRIDGE D S 3.3V VREG SAM C20/C21 Family Data Sheet Block Diagram © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 20

Note: Not all features are available for all devices. Please refer to Table 1-3 and Table 1-4 to determine feature availability for the particular device. Related Links

6.2.5 TCC Configurations

6.1 Multiplexed Signals

Pinout

4.1 SAM C21E / SAM C20E

4.1.1 VQFN32/TQFP32

4.2 SAM C21G / SAM C20G

4.2.1 VQFN48 / TQFP48

4.3 SAM C21J / SAM C20J

4.3.1 VQFN64/TQFP64

4.3.2 WLCSP56

4.4 SAM C21N / SAM C20N

4.4.1 TQFP100

Signal Descriptions List The following tables provide the details on signal names classified by peripheral. Table 5-1. Signal Descriptions List - SAM C20/C21 Signal Name Function Type Active Level Analog Comparators - AC AIN[7:0] AC Analog Inputs Analog CMP[2:0] AC Comparator Outputs Digital Analog Digital Converter - ADCx AIN[19:0] ADC Analog Inputs Analog VREFA ADC Voltage External Reference A Analog Digital Analog Converter - DAC VOUT[1:0] DAC Voltage output Analog VREFA DAC Voltage External Reference Analog Sigma-Delta Analog Digital Converter - SDADC INN[2:0] SDADC Analog Negative Inputs Analog INP[2:0] SDADC Analog Positive Inputs Analog VREFB SDADC Voltage External Reference B Analog External Interrupt Controller - EIC EXTINT[15:0] External Interrupts inputs Digital NMI External Non-Maskable Interrupt input Digital Generic Clock Generator - GCLK GCLK_IO[7:0] Generic Clock (source clock inputs or generic clock generator output) Digital Custom Control Logic - CCL IN[11:0] Logic Inputs Digital OUT[3:0] Logic Outputs Digital Power Manager - PM RESETN Reset input Digital Low Serial Communication Interface - SERCOMx PAD[3:0] SERCOM Inputs/Outputs Pads Digital Oscillators Control - OSCCTRL XIN Crystal or external clock Input Analog/Digital XOUT Crystal Output Analog 32 kHz Oscillators Control - OSC32KCTRL XIN32 32 kHz Crystal or external clock Input Analog/Digital XOUT32 32 kHz Crystal Output Analog Timer Counter - TCx SAM C20/C21 Family Data Sheet Signal Descriptions List © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 27

Signal Name Function Type Active Level WO[1:0] Waveform Outputs Digital Timer Counter - TCCx WO[1:0] Waveform Outputs Digital Peripheral Touch Controller - PTC X[15:0] PTC Input Analog Y[15:0] PTC Input Analog General Purpose I/O - PORT PA25 - PA00 Parallel I/O Controller I/O Port A Digital PA28 - PA27 Parallel I/O Controller I/O Port A Digital PA31 - PA30 Parallel I/O Controller I/O Port A Digital PB17 - PB00 Parallel I/O Controller I/O Port B Digital PB21 - PB19 Parallel I/O Controller I/O Port B Digital PB25 - PB22 Parallel I/O Controller I/O Port B Digital PB31 - PB30 Parallel I/O Controller I/O Port B Digital PC03 - PC-00 Parallel I/O Controller I/O Port C Digital PC21 - PC05 Parallel I/O Controller I/O Port C Digital PC28 - PC24 Parallel I/O Controller I/O Port C Digital Controller Area Network - CAN TX CAN Transmit Line Digital RX CAN Receive Line Digital SAM C20/C21 Family Data Sheet Signal Descriptions List © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 28

I/O Multiplexing and Considerations

Each pin is by default controlled by the PORT as a general purpose I/O, and alternatively it can be assigned to one of the peripheral functions, such as A, B, C, D, E, F, G, H, or I. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one. The selection of peripheral function A to H is done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT. Table 6-1. PORT Function Multiplexing for SAM C21 N Pin I/O Pin Supply A B B (1,2) C D E F G H I EIC REF ADC0 ADC1 SDADC AC PTC DAC SERCOM SERCOM-ALT TC TCC COM AC/GCLK CCL

1 PA00 VDDANA EXTINT[0] SERCOM1/PAD[0] TC2/WO[0] CMP[2]

2 PA01 VDDANA EXTINT[1] SERCOM1/PAD[1] TC2/WO[1] CMP[3]

3 PC00 VDDANA EXTINT[8] AIN[8]

4 PC01 VDDANA EXTINT[9] AIN[9]

5 PC02 VDDANA EXTINT[10] AIN[10]

6 PC03 VDDIO EXTINT[11] AIN[11] SERCOM7/PAD[0] TCC2/WO[0]

7 PA02 VDDANA EXTINT[2] AIN[0] AIN[4] Y[0] VOUT

8 PA03 VDDANA EXTINT[3] ADC/VREFA

AIN[1] Y[1]

9 PB04 VDDANA EXTINT[4] AIN[6] AIN[5] Y[10]

10 PB05 VDDANA EXTINT[5] AIN[7] AIN[6] Y[11]

13 PB06 VDDIO EXTINT[6] AIN[8] INN[2] AIN[7] Y[12] SERCOM7/PAD[1] CCL2/IN[6]

14 PB07 VDDIO EXTINT[7] AIN[9] INP[2] Y[13] SERCOM7/PAD[3] SERCOM7/PAD[2] CCL2/IN[7]

15 PB08 VDDIO EXTINT[8] AIN[2] AIN[4] INN[1] Y[14] SERCOM7/PAD[2] SERCOM7/PAD[3] TC4/WO[0] CCL2/IN[8]

16 PB09 VDDANA EXTINT[9] AIN[3] AIN[5] INP[1] Y[15] SERCOM4/PAD[1] TC4/WO[1] CCL2/OUT[2]

17 PA04 VDDANA EXTINT[4] SDADC/VREFB AIN[4] AIN[0] Y[2] SERCOM0/PAD[0] TC0/WO[0] CCL0/IN[0]

18 PA05 VDDANA EXTINT[5] AIN[5] AIN[1] Y[3] SERCOM0/PAD[1] TC0/WO[1] CCL0/IN[1]

19 PA06 VDDANA EXTINT[6] AIN[6] INN[0] AIN[2] Y[4] SERCOM0/PAD[2] TC1/WO[0] CCL0/IN[2]

20 PA07 VDDANA EXTINT[7] AIN[7] INP[0] AIN[3] Y[5] SERCOM0/PAD[3] TC1/WO[1] CCL0/OUT[0]

21 PC05 VDDANA EXTINT[13] SERCOM6/PAD[3] TCC2/WO[1]

22 PC06 VDDANA EXTINT[14] SERCOM6/PAD[0]

23 PC07 VDDANA EXTINT[15] SERCOM6/PAD[1]

26 PA08 VDDIO NMI AIN[10] X[0]/Y[16] SERCOM0/PAD[0] SERCOM2/PAD[0] TC0/WO[0] TCC0/WO[0] CCL1/IN[3]

27 PA09 VDDIO EXTINT[9] AIN[11] X[1]/Y[17] SERCOM0/PAD[1] SERCOM2/PAD[1] TC0/WO[1] TCC0/WO[1] CCL1/IN[4]

28 PA10 VDDIO EXTINT[10] X[2]/Y[18] SERCOM0/PAD[2] SERCOM2/PAD[2] TC1/WO[0] TCC0/WO[2] GCLK_IO[4] CCL1/IN[5] 29 PA11 VDDIO EXTINT[11] X[3]/Y[19] SERCOM0/PAD[3] SERCOM2/PAD[3] TC1/WO[1] TCC0/WO[3] GCLK_IO[5] CCL1/OUT[1]

30 PB10 VDDIO EXTINT[10] SERCOM4/PAD[2] TC5/WO[0] TCC0_WO4 GCLK_IO[4] CCL1/IN[5]

31 PB11 VDDIO EXTINT[11] SERCOM4/PAD[3] TC5/WO[1] TCC0_WO5 GCLK_IO[5] CCL1/OUT[1]

32 PB12 VDDIO EXTINT[12] X[12]/Y[28] SERCOM4/PAD[0] TC4/WO[0] TCC0_WO6 CAN1/TX GCLK_IO[6]

33 PB13 VDDIO EXTINT[13] X[13]/Y[29] SERCOM4/PAD[1] TC4/WO[1] TCC0_WO7 CAN1/RX GCLK_IO[7]

34 PB14 VDDIO EXTINT[14] X[14]/Y[30] SERCOM4/PAD[2] TC5/WO[0] CAN1/TX GCLK_IO[0] CCL3/IN[9]

35 PB15 VDDIO EXTINT[15] X[15]/Y[31] SERCOM4/PAD[3] TC5/WO[1] CAN1/RX GCLK_IO[1] CCL3/IN[10]

38 PC08 VDDIO EXTINT[0] SERCOM6/PAD[0] SERCOM7/PAD[0]

39 PC09 VDDIO EXTINT[1] SERCOM6/PAD[1] SERCOM7/PAD[1]

40 PC10 VDDIO EXTINT[2] SERCOM6/PAD[2] SERCOM7/PAD[2]

41 PC11 VDDIO EXTINT[3] SERCOM6/PAD[3] SERCOM7/PAD[3]

42 PC12 VDDIO EXTINT[4] SERCOM7/PAD[0]

43 PC13 VDDIO EXTINT[5] SERCOM7/PAD[1]

44 PC14 VDDIO EXTINT[6] SERCOM7/PAD[2]

45 PC15 VDDIO EXTINT[7] SERCOM7/PAD[3]

46 PA12 VDDIO EXTINT[12] SERCOM2/PAD[0] SERCOM4/PAD[0] TC2/WO[0] TCC0_WO6 CMP[0]

47 PA13 VDDIO EXTINT[13] SERCOM2/PAD[1] SERCOM4/PAD[1] TC2/WO[1] TCC0_WO7 CMP[1]

48 PA14 VDDIO EXTINT[14] SERCOM2/PAD[2] SERCOM4/PAD[2] TC3/WO[0] GCLK_IO[0]

49 PA15 VDDIO EXTINT[15] SERCOM2/PAD[3] SERCOM4/PAD[3] TC3/WO[1] GCLK_IO[1]

52 PA16 VDDIO EXTINT[0] X[4]/Y[20] SERCOM1/PAD[0] SERCOM3/PAD[0] TC2/WO[0] TCC1/WO[0] GCLK_IO[2] CCL0/IN[0] 53 PA17 VDDIO EXTINT[1] X[5]/Y[21] SERCOM1/PAD[1] SERCOM3/PAD[1] TC2/WO[1] TCC1/WO[1] GCLK_IO[3] CCL0/IN[1]

54 PA18 VDDIO EXTINT[2] X[6]/Y[22] SERCOM1/PAD[2] SERCOM3/PAD[2] TC3/WO[0] TCC1/WO[2] CMP[0] CCL0/IN[2]

55 PA19 VDDIO EXTINT[3] X[7]/Y[23] SERCOM1/PAD[3] SERCOM3/PAD[3] TC3/WO[1] TCC1/WO[3] CMP[1] CCL0/OUT[0]

56 PC16 VDDIO EXTINT[8] SERCOM6/PAD[0]

57 PC17 VDDIO EXTINT[9] SERCOM6/PAD[1]

Pin I/O Pin Supply A B B (1,2) C D E F G H I EIC REF ADC0 ADC1 SDADC AC PTC DAC SERCOM SERCOM-ALT TC TCC COM AC/GCLK CCL

58 PC18 VDDIO EXTINT[10] SERCOM6/PAD[2]

59 PC19 VDDIO EXTINT[11] SERCOM6/PAD[3]

60 PC20 VDDIO EXTINT[12] CCL3/IN[9]

61 PC21 VDDIO EXTINT[13] CCL3/IN[10]

64 PB16 VDDIO EXTINT[0] SERCOM5/PAD[0] TC6/WO[0] GCLK_IO[2] CCL3/IN[11]

65 PB17 VDDIO EXTINT[1] SERCOM5/PAD[1] TC6/WO[1] GCLK_IO[3] CCL3/OUT[3]

66 PB18 VDDIO EXTINT[2] SERCOM5/PAD[2] SERCOM3/PAD[2] GCLK_IO[4]

67 PB19 VDDIO EXTINT[3] SERCOM5/PAD[3] SERCOM3/PAD[3] GCLK_IO[5]

68 PB20 VDDIO EXTINT[4] SERCOM3/PAD[0] SERCOM2/PAD[0] GCLK_IO[6]

69 PB21 VDDIO EXTINT[5] SERCOM3/PAD[1] SERCOM2/PAD[1] GCLK_IO[7]

70 PA20 VDDIO EXTINT[4] X[8]/Y[24] SERCOM5/PAD[2] SERCOM3/PAD[2] TC7/WO[0] TCC2/WO[0] GCLK_IO[4]

71 PA21 VDDIO EXTINT[5] X[9]/Y[25] SERCOM5/PAD[3] SERCOM3/PAD[3] TC7/WO[1] TCC2/WO[1] GCLK_IO[5]

72 PA22 VDDIO EXTINT[6] X[10]/Y[26] SERCOM3/PAD[0] SERCOM5/PAD[0] TC4/WO[0] TCC1/WO[0] CAN0/TX GCLK_IO[6] CCL2/IN[6] 73 PA23 VDDIO EXTINT[7] X[11]/Y[27] SERCOM3/PAD[1] SERCOM5/PAD[1] TC4/WO[1] TCC1/WO[1] CAN0/RX GCLK_IO[7] CCL2/IN[7]

74 PA24 VDDIO EXTINT[12] SERCOM3/PAD[2] SERCOM5/PAD[2] TC5/WO[0] TCC2/WO[0] CAN0/TX CMP[2] CCL2/IN[8]

75 PA25 VDDIO EXTINT[13] SERCOM3/PAD[3] SERCOM5/PAD[3] TC5/WO[1] TCC2/WO[1] CAN0/RX CMP[3] CCL2/OUT[2]

78 PB22 VDDIO EXTINT[6] SERCOM0/PAD[2] SERCOM5/PAD[2] TC7/WO[0] TCC1/WO[2] GCLK_IO[0] CCL0/IN[0]

79 PB23 VDDIO EXTINT[7] SERCOM0/PAD[3] SERCOM5/PAD[3] TC7/WO[1] TCC1/WO[3] GCLK_IO[1] CCL0/OUT[0]

80 PB24 VDDIO EXTINT[8] SERCOM0/PAD[0] SERCOM4/PAD[0] CMP[0]

81 PB25 VDDIO EXTINT[9] SERCOM0/PAD[1] SERCOM4/PAD[1] CMP[1]

82 PC24 VDDIO EXTINT[0] SERCOM0/PAD[2] SERCOM4/PAD[2]

83 PC25 VDDIO EXTINT[1] SERCOM0/PAD[3] SERCOM4/PAD[3]

84 PC26 VDDIO EXTINT[2]

85 PC27 VDDIO EXTINT[3] SERCOM1/PAD[0] CCL1/IN[4]

86 PC28 VDDIO EXTINT[4] SERCOM1/PAD[1] CCL1/IN[5]

87 PA27 VDDIN EXTINT[15] GCLK_IO[0]

89 PA28 VDDIN EXTINT[8] GCLK_IO[0]

93 PA30 VDDIN EXTINT[10] SERCOM1/PAD[2] TC1/WO[0] CORTEX_M0P/SWCLK GCLK_IO[0] CCL1/IN[3]

94 PA31 VDDIN EXTINT[11] SERCOM1/PAD[3] TC1/WO[1] CORTEX_M0P/SWDIO CCL1/OUT[1]

95 PB30 VDDIN EXTINT[14] SERCOM1/PAD[0] SERCOM5/PAD[0] TC0/WO[0] CMP[2]

96 PB31 VDDIN EXTINT[15] SERCOM1/PAD[1] SERCOM5/PAD[1] TC0/WO[1] CMP[3]

97 PB00 VDDANA EXTINT[0] AIN[0] Y[6] SERCOM5/PAD[2] TC7/WO[0] CCL0/IN[1]

98 PB01 VDDANA EXTINT[1] AIN[1] Y[7] SERCOM5/PAD[3] TC7/WO[1] CCL0/IN[2]

99 PB02 VDDANA EXTINT[2] AIN[2] Y[8] SERCOM5/PAD[0] TC6/WO[0] CCL0/OUT[0]

100 PB03 VDDANA EXTINT[3] AIN[3] Y[9] SERCOM5/PAD[1] TC6/WO[1]

Note: 1. All analog pin functions are on peripheral function B. Peripheral function B must be selected to disable the digital control of the pin. 2. Only some pins can be used in SERCOM I 2C mode. For additional information, refer to 6.2.3 SERCOM I2C Pins. Table 6-2. PORT Function Multiplexing for SAM C21 E/G/J Pin(1) I/O Pin Supply A B(2,3) C D E F G H I SAM C21E SAM C21G SAM C21J EIC REF ADC0 ADC1 AC PTC DAC SDADC SERCOM (2,3,4) SERCOM-ALT(4) TC TCC TCC COM AC/GCLK CCL 1 1 1 PA00 VDDANA EXTINT[0] SERCOM1/ PAD[0] TCC2/WO[0] CMP[2] 2 2 2 PA01 VDDANA EXTINT[1] SERCOM1/ PAD[1] TCC2/WO[1] CMP[3] 3 3 3 PA02 VDDANA EXTINT[2] AIN[0] AIN[4] Y[0] VOUT 4 4 4 PA03 VDDANA EXTINT[3] ADC/VREFA AIN[1] AIN[5] Y[1]

5 PB04 VDDANA EXTINT[4] AIN[6] Y[10]

6 PB05 VDDANA EXTINT[5] AIN[7] AIN[6] Y[11]

9 PB06 VDDANA EXTINT[6] AIN[8] AIN[7] Y[12] INN[2] CCL2/

IN[6]

10 PB07 VDDANA EXTINT[7] AIN[9] Y[13] INP[2] CCL2/

IN[7] 7 11 PB08 VDDANA EXTINT[8] AIN[2] AIN[4] Y[14] INN[1] SERCOM4/ PAD[0] TC0/WO[0] CCL2/ IN[8] 8 12 PB09 VDDANA EXTINT[9] AIN[3] AIN[5] Y[15] INP[1] SERCOM4/ PAD[1] TC0WO[1] CCL2/ OUT[2] 5 9 13 PA04 VDDANA EXTINT[4] SDADC / VREFB AIN[4] AIN[0] Y[2] SERCOM0/ PAD[0] TCC0/WO[0] CCL0/ IN[0] SAM C20/C21 Family Data Sheet I/O Multiplexing and Considerations © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 30

Pin(1) I/O Pin Supply A B(2,3) C D E F G H I SAM C21E SAM C21G SAM C21J EIC REF ADC0 ADC1 AC PTC DAC SDADC SERCOM (2,3,4) SERCOM-ALT(4) TC TCC TCC COM AC/GCLK CCL 6 10 14 PA05 VDDANA EXTINT[5] AIN[5] AIN[1] Y[3] SERCOM0/ PAD[1] TCC0/WO[1] CCL0/ IN[1] 7 11 15 PA06 VDDANA EXTINT[6] AIN[6] AIN[2] Y[4] INN[0] SERCOM0/ PAD[2] TCC1/WO[0] CCL0/ IN[2] 8 12 16 PA07 VDDANA EXTINT[7] AIN[7] AIN[3] Y[5] INP[0] SERCOM0/ PAD[3] TCC1/WO[1] CCL0/ OUT[0] 11 13 17 PA08 VDDIO NMI AIN[8] AIN[10] X[0]/Y[16] SERCOM0/ PAD[0] SERCOM2/ PAD[0] TCC0/WO[0] TCC1/ WO[2] CCL1/ IN[3] 12 14 18 PA09 VDDIO EXTINT[9] AIN[9] AIN[11] X[1]/Y[17] SERCOM0/ PAD[1] SERCOM2/ PAD[1] TCC0/WO[1] TCC1/ WO[3] CCL1/ IN[4] 13 15 19 PA10 VDDIO EXTINT[10] AIN[10] X[2]/Y[18] SERCOM0/ PAD[2] SERCOM2/ PAD[2] TCC1/WO[0] TCC0/ WO[2] GCLK_IO[4] CCL1/ IN[5] 14 16 20 PA11 VDDIO EXTINT[11] AIN[11] X[3]/Y[19] SERCOM0/ PAD[3] SERCOM2/ PAD[3] TCC1/WO[1] TCC0/ WO[3] GCLK_IO[5] CCL1/ OUT[1] 19 23 PB10 VDDIO EXTINT[10] SERCOM4/ PAD[2] TC1/WO[0] TCC0/ WO[4] CAN1/TX GCLK_IO[4] CCL1/ IN[5] 20 24 PB11 VDDIO EXTINT[11] SERCOM4/ PAD[3] TC1/WO[1] TCC0/ WO[5] CAN1/RX GCLK_IO[5] CCL1/ OUT[1]

25 PB12 VDDIO EXTINT[12] X[12]/Y[28] SERCOM4/

PAD[0] TC0/WO[0] TCC0/ WO[6] GCLK_IO[6]

26 PB13 VDDIO EXTINT[13] X[13]/Y[29] SERCOM4/

PAD[1] TC0/WO[1] TCC0/ WO[7] GCLK_IO[7]

27 PB14 VDDIO EXTINT[14] X[14]/Y[30] SERCOM4/

PAD[2] TC1/WO[0] CAN1/TX GCLK_IO[0] CCL3/ IN[9]

28 PB15 VDDIO EXTINT[15] X[15]/Y[31] SERCOM4/

PAD[3] TC1/WO[1] CAN1/RX GCLK_IO[1] CCL3/ IN[10] 21 29 PA12 VDDIO EXTINT[12] SERCOM2/ PAD[0] SERCOM4/ PAD[0] TCC2/WO[0] TCC0/ WO[6] AC/CMP[0] 22 30 PA13 VDDIO EXTINT[13] SERCOM2/ PAD[1] SERCOM4/ PAD[1] TCC2/WO[1] TCC0/ WO[7] AC/CMP[1] 15 23 31 PA14 VDDIO EXTINT[14] SERCOM2/ PAD[2] SERCOM4/ PAD[2] TC4/WO[0] TCC0/ WO[4] GCLK_IO[0] 16 24 32 PA15 VDDIO EXTINT[15] SERCOM2/ PAD[3] SERCOM4/ PAD[3] TC4/WO[1] TCC0/ WO[5] GCLK_IO[1] 17 25 35 PA16 VDDIO EXTINT[0] X[4]/Y[20] SERCOM1/ PAD[0] SERCOM3/ PAD[0] TCC2/WO[0] TCC0/ WO[6] GCLK_IO[2] CCL0/ IN[0] 18 26 36 PA17 VDDIO EXTINT[1] X[5]/Y[21] SERCOM1/ PAD[1] SERCOM3/ PAD[1] TCC2/WO[1] TCC0/ WO[7] GCLK_IO[3] CCL0/ IN[1] 19 27 37 PA18 VDDIO EXTINT[2] X[6]/Y[22] SERCOM1/ PAD[2] SERCOM3/ PAD[2] TC4/WO[0] TCC0/ WO[2] AC/CMP[0] CCL0/ IN[2] 20 28 38 PA19 VDDIO EXTINT[3] X[7]/Y[23] SERCOM1/ PAD[3] SERCOM3/ PAD[3] TC4/WO[1] TCC0/ WO[3] AC/CMP[1] CCL0/ OUT[0]

39 PB16 VDDIO EXTINT[0] SERCOM5/

PAD[0] TC2/WO[0] TCC0/ WO[4] GCLK_IO[2] CCL3/ IN[11]

40 PB17 VDDIO EXTINT[1] SERCOM5/

PAD[1] TC2/WO[1] TCC0/ WO[5] GCLK_IO[3] CCL3/ OUT[3] 29 41 PA20 VDDIO EXTINT[4] X[8]/Y[24] SERCOM5/ PAD[2] SERCOM3/ PAD[2] TC3/WO[0] TCC0/ WO[6] GCLK_IO[4] 30 42 PA21 VDDIO EXTINT[5] X[9]/Y[25] SERCOM5/ PAD[3] SERCOM3/ PAD[3] TC3/WO[1] TCC0/ WO[7] GCLK_IO[5] 21 31 43 PA22 VDDIO EXTINT[6] X[10]/Y[26] SERCOM3/ PAD[0] SERCOM5/ PAD[0] TC0/WO[0] TCC0/ WO[4] GCLK_IO[6] CCL2/ IN[6] 22 32 44 PA23 VDDIO EXTINT[7] X[11]/Y[27] SERCOM3/ PAD[1] SERCOM5/ PAD[1] TC0/WO[1] TCC0/ WO[5] GCLK_IO[7] CCL2/ IN[7] 23 33 45 PA24 VDDIO EXTINT[12] SERCOM3/ PAD[2] SERCOM5/ PAD[2] TC1/WO[0] TCC1/ WO[2] CAN0/TX AC/CMP[2] CCL2/ IN[8] 24 34 46 PA25 VDDIO EXTINT[13] SERCOM3/ PAD[3] SERCOM5/ PAD[3] TC1/WO[1] TCC1/ WO[3] CAN0/RX AC/CMP[3] CCL2/ OUT[2] 37 49 PB22 VDDIO EXTINT[6] SERCOM5/ PAD[2] TC3/WO[0] CAN0/TX GCLK_IO[0] CCL0/ IN[0] 38 50 PB23 VDDIO EXTINT[7] SERCOM5/ PAD[3] TC3/WO[1] CAN0/RX GCLK_IO[1] CCL0/ OUT[0] 25 39 51 PA27 VDDIN EXTINT[15] GCLK_IO[0] 27 41 53 PA28 VDDIN EXTINT[8] GCLK_IO[0] 31 45 57 PA30 VDDIN EXTINT[10] SERCOM1/ PAD[2] TCC1/WO[0] CORTEX_M0P/ SWCLK GCLK_IO[0] CCL1/ IN[3] 32 46 58 PA31 VDDIN EXTINT[11] SERCOM1/ PAD[3] TCC1/WO[1] CORTEX_M0P/ SWDIO CCL1/ OUT[1]

59 PB30 VDDIN EXTINT[14] SERCOM5/

PAD[0] TCC0/WO[0] TCC1/ WO[2] AC/CMP[2]

60 PB31 VDDIN EXTINT[15] SERCOM5/

Pin(1) I/O Pin Supply A B(2,3) C D E F G H I SAM C21E SAM C21G SAM C21J EIC REF ADC0 ADC1 AC PTC DAC SDADC SERCOM (2,3,4) SERCOM-ALT(4) TC TCC TCC COM AC/GCLK CCL

61 PB00 VDDANA EXTINT[0] AIN[0] Y[6] SERCOM5/

PAD[2] TC3/WO[0] CCL0/ IN[1]

62 PB01 VDDANA EXTINT[1] AIN[1] Y[7] SERCOM5/

PAD[3] TC3/WO[1] CCL0/ IN[2] 47 63 PB02 VDDANA EXTINT[2] AIN[2] Y[8] SERCOM5/ PAD[0] TC2/WO[0] CCL0/ OUT[0] 48 64 PB03 VDDANA EXTINT[3] AIN[3] Y[9] SERCOM5/ PAD[1] TC2/WO[1] Note: 1. Use the SAM C21J pinout muxing for the WLCSP56 package. 2. All analog pin functions are on peripheral function B. Peripheral function B must be selected to disable the digital control of the pin. 3. Only some pins can be used in SERCOM I 2C mode. For additional information, refer to 6.2.3 SERCOM I2C Pins. 4. SERCOM4 and SERCOM5 are not supported on SAM C21E. Table 6-3. PORT Function Multiplexing for SAM C20 N Pin I/O Pin Supply A B B (1,2) C D E F G H I EIC REF ADC0 AC PTC SERCOM SERCOM-ALT TC TCC COM AC/GCLK CCL

7 PA02 VDDANA EXTINT[2] AIN[0] AIN[4] Y[0]

8 PA03 VDDANA EXTINT[3] ADC/VREFA AIN[1] Y[1]

9 PB04 VDDANA EXTINT[4] AIN[5] Y[10]

10 PB05 VDDANA EXTINT[5] AIN[6] Y[11]

13 PB06 VDDIO EXTINT[6] AIN[7] Y[12] SERCOM7/PAD[1] CCL2/IN[6]

14 PB07 VDDIO EXTINT[7] Y[13] SERCOM7/PAD[3] SERCOM7/PAD[2] CCL2/IN[7]

15 PB08 VDDIO EXTINT[8] AIN[2] Y[14] SERCOM7/PAD[2] SERCOM7/PAD[3] TC4/WO[0] CCL2/IN[8]

16 PB09 VDDANA EXTINT[9] AIN[3] Y[15] SERCOM4/PAD[1] TC4/WO[1] CCL2/OUT[2]

17 PA04 VDDANA EXTINT[4] AIN[4] AIN[0] Y[2] SERCOM0/PAD[0] TC0/WO[0] CCL0/IN[0]

19 PA06 VDDANA EXTINT[6] AIN[6] AIN[2] Y[4] SERCOM0/PAD[2] TC1/WO[0] CCL0/IN[2]

20 PA07 VDDANA EXTINT[7] AIN[7] AIN[3] Y[5] SERCOM0/PAD[3] TC1/WO[1] CCL0/OUT[0]

26 PA08 VDDIO NMI X[0]/Y[16] SERCOM0/PAD[0] SERCOM2/PAD[0] TC0/WO[0] TCC0/WO[0] CCL1/IN[3]

27 PA09 VDDIO EXTINT[9] X[1]/Y[17] SERCOM0/PAD[1] SERCOM2/PAD[1] TC0/WO[1] TCC0/WO[1] CCL1/IN[4]

32 PB12 VDDIO EXTINT[12] X[12]/Y[28] SERCOM4/PAD[0] TC4/WO[0] TCC0_WO6 GCLK_IO[6]

33 PB13 VDDIO EXTINT[13] X[13]/Y[29] SERCOM4/PAD[1] TC4/WO[1] TCC0_WO7 GCLK_IO[7]

34 PB14 VDDIO EXTINT[14] X[14]/Y[30] SERCOM4/PAD[2] TC5/WO[0] GCLK_IO[0] CCL3/IN[9]

35 PB15 VDDIO EXTINT[15] X[15]/Y[31] SERCOM4/PAD[3] TC5/WO[1] GCLK_IO[1] CCL3/IN[10]

Pin I/O Pin Supply A B B (1,2) C D E F G H I EIC REF ADC0 AC PTC SERCOM SERCOM-ALT TC TCC COM AC/GCLK CCL 52 PA16 VDDIO EXTINT[0] X[4]/Y[20] SERCOM1/PAD[0] SERCOM3/PAD[0] TC2/WO[0] TCC1/WO[0] GCLK_IO[2] CCL0/IN[0] 53 PA17 VDDIO EXTINT[1] X[5]/Y[21] SERCOM1/PAD[1] SERCOM3/PAD[1] TC2/WO[1] TCC1/WO[1] GCLK_IO[3] CCL0/IN[1] 72 PA22 VDDIO EXTINT[6] X[10]/Y[26] SERCOM3/PAD[0] SERCOM5/PAD[0] TC4/WO[0] TCC1/WO[0] GCLK_IO[6] CCL2/IN[6] 73 PA23 VDDIO EXTINT[7] X[11]/Y[27] SERCOM3/PAD[1] SERCOM5/PAD[1] TC4/WO[1] TCC1/WO[1] GCLK_IO[7] CCL2/IN[7]

74 PA24 VDDIO EXTINT[12] SERCOM3/PAD[2] SERCOM5/PAD[2] TC5/WO[0] TCC2/WO[0] CMP[2] CCL2/IN[8]

75 PA25 VDDIO EXTINT[13] SERCOM3/PAD[3] SERCOM5/PAD[3] TC5/WO[1] TCC2/WO[1] CMP[3] CCL2/OUT[2]

97 PB00 VDDANA EXTINT[0] Y[6] SERCOM5/PAD[2] TC7/WO[0] CCL0/IN[1]

98 PB01 VDDANA EXTINT[1] Y[7] SERCOM5/PAD[3] TC7/WO[1] CCL0/IN[2]

99 PB02 VDDANA EXTINT[2] Y[8] SERCOM5/PAD[0] TC6/WO[0] CCL0/OUT[0]

100 PB03 VDDANA EXTINT[3] Y[9] SERCOM5/PAD[1] TC6/WO[1]

Note: 1. All analog pin functions are on peripheral function B. Peripheral function B must be selected to disable the digital control of the pin. 2. Only some pins can be used in SERCOM I 2C mode. For additional information, refer to 6.2.3 SERCOM I2C Pins. Table 6-4. PORT Function Multiplexing for SAM C20 E/G/J Pin(1) I/O Pin Supply A B (2,3) C D E F G H I SAM C20E SAM C20G SAM C20J EIC REF ADC0 AC PTC SERCOM (2,3) SERCOM-ALT TC TCC TCC COM AC/GCLK CCL 1 1 1 PA00 VDDANA EXTINT[0] SERCOM1/ PAD[0] TCC2/WO[0] CMP[2] 2 2 2 PA01 VDDANA EXTINT[1] SERCOM1/ PAD[1] TCC2/WO[1] CMP[3] 3 3 3 PA02 VDDANA EXTINT[2] AIN[0] AIN[4] Y[0] 4 4 4 PA03 VDDANA EXTINT[3] ADC/VREFA AIN[1] AIN[5] Y[1]

5 PB04 VDDANA EXTINT[4] Y[10]

6 PB05 VDDANA EXTINT[5] AIN[6] Y[11]

9 PB06 VDDANA EXTINT[6] AIN[7] Y[12] CCL2/

IN[6]

10 PB07 VDDANA EXTINT[7] Y[13] CCL2/

Pin(1) I/O Pin Supply A B (2,3) C D E F G H I SAM C20E SAM C20G SAM C20J EIC REF ADC0 AC PTC SERCOM (2,3) SERCOM-ALT TC TCC TCC COM AC/GCLK CCL 7 11 PB08 VDDANA EXTINT[8] AIN[2] Y[14] - TC0/WO[0] CCL2/ IN[8] 8 12 PB09 VDDANA EXTINT[9] AIN[3] Y[15] - TC0WO[1] CCL2/ OUT[2] 5 9 13 PA04 VDDANA EXTINT[4] AIN[4] AIN[0] Y[2] SERCOM0/ PAD[0] TCC0/WO[0] CCL0/ IN[0] 6 10 14 PA05 VDDANA EXTINT[5] AIN[5] AIN[1] Y[3] SERCOM0/ PAD[1] TCC0/WO[1] CCL0/ IN[1] 7 11 15 PA06 VDDANA EXTINT[6] AIN[6] AIN[2] Y[4] SERCOM0/ PAD[2] TCC1/WO[0] CCL0/ IN[2] 8 12 16 PA07 VDDANA EXTINT[7] AIN[7] AIN[3] Y[5] SERCOM0/ PAD[3] TCC1/WO[1] CCL0/ OUT[0] 11 13 17 PA08 VDDIO NMI AIN[8] X[0]/Y[16] SERCOM0/ PAD[0] SERCOM2/ PAD[0] TCC0/WO[0] TCC1/ WO[2] CCL1/ IN[3] 12 14 18 PA09 VDDIO EXTINT[9] AIN[9] X[1]/Y[17] SERCOM0/ PAD[1] SERCOM2/ PAD[1] TCC0/WO[1] TCC1/ WO[3] CCL1/ IN[4] 13 15 19 PA10 VDDIO EXTINT[10] AIN[10] X[2]/Y[18] SERCOM0/ PAD[2] SERCOM2/ PAD[2] TCC1/WO[0] TCC0/ WO[2] GCLK_IO[4] CCL1/ IN[5] 14 16 20 PA11 VDDIO EXTINT[11] AIN[11] X[3]/Y[19] SERCOM0/ PAD[3] SERCOM2/ PAD[3] TCC1/WO[1] TCC0/ WO[3] GCLK_IO[5] CCL1/ OUT[1] 19 23 PB10 VDDIO EXTINT[10] - TC1/WO[0] TCC0/ WO[4] GCLK_IO[4] CCL1/ IN[5] 20 24 PB11 VDDIO EXTINT[11] - TC1/WO[1] TCC0/ WO[5] GCLK_IO[5] CCL1/ OUT[1]

25 PB12 VDDIO EXTINT[12] X[12]/Y[28] - TC0/WO[0] TCC0/

WO[6] GCLK_IO[6]

26 PB13 VDDIO EXTINT[13] X[13]/Y[29] - TC0/WO[1] TCC0/

WO[7] GCLK_IO[7]

27 PB14 VDDIO EXTINT[14] X[14]/Y[30] - TC1/WO[0] GCLK_IO[0] CCL3/

IN[9]

28 PB15 VDDIO EXTINT[15] X[15]/Y[31] - TC1/WO[1] GCLK_IO[1] CCL3/

IN[10] 21 29 PA12 VDDIO EXTINT[12] SERCOM2/ PAD[0] - TCC2/WO[0] TCC0/ WO[6] AC/CMP[0] 22 30 PA13 VDDIO EXTINT[13] SERCOM2/ PAD[1] - TCC2/WO[1] TCC0/ WO[7] AC/CMP[1] 15 23 31 PA14 VDDIO EXTINT[14] SERCOM2/ PAD[2] - TC4/WO[0] TCC0/ WO[4] GCLK_IO[0] 16 24 32 PA15 VDDIO EXTINT[15] SERCOM2/ PAD[3] - TC4/WO[1] TCC0/ WO[5] GCLK_IO[1] 17 25 35 PA16 VDDIO EXTINT[0] X[4]/Y[20] SERCOM1/ PAD[0] SERCOM3/ PAD[0] TCC2/WO[0] TCC0/ WO[6] GCLK_IO[2] CCL0/ IN[0] 18 26 36 PA17 VDDIO EXTINT[1] X[5]/Y[21] SERCOM1/ PAD[1] SERCOM3/ PAD[1] TCC2/WO[1] TCC0/ WO[7] GCLK_IO[3] CCL0/ IN[1] 19 27 37 PA18 VDDIO EXTINT[2] X[6]/Y[22] SERCOM1/ PAD[2] SERCOM3/ PAD[2] TC4/WO[0] TCC0/ WO[2] AC/CMP[0] CCL0/ IN[2] 20 28 38 PA19 VDDIO EXTINT[3] X[7]/Y[23] SERCOM1/ PAD[3] SERCOM3/ PAD[3] TC4/WO[1] TCC0/ WO[3] AC/CMP[1] CCL0/ OUT[0]

39 PB16 VDDIO EXTINT[0] - TC2/WO[0] TCC0/

WO[4] GCLK_IO[2] CCL3/ IN[11]

40 PB17 VDDIO EXTINT[1] - TC2/WO[1] TCC0/

WO[5] GCLK_IO[3] CCL3/ OUT[3] 29 41 PA20 VDDIO EXTINT[4] X[8]/Y[24] - SERCOM3/ PAD[2] TC3/WO[0] TCC0/ WO[6] GCLK_IO[4] 30 42 PA21 VDDIO EXTINT[5] X[9]/Y[25] - SERCOM3/ PAD[3] TC3/WO[1] TCC0/ WO[7] GCLK_IO[5] 21 31 43 PA22 VDDIO EXTINT[6] X[10]/Y[26] SERCOM3/ PAD[0] - TC0/WO[0] TCC0/ WO[4] GCLK_IO[6] CCL2/ IN[6] 22 32 44 PA23 VDDIO EXTINT[7] X[11]/Y[27] SERCOM3/ PAD[1] - TC0/WO[1] TCC0/ WO[5] GCLK_IO[7] CCL2/ IN[7] 23 33 45 PA24 VDDIO EXTINT[12] SERCOM3/ PAD[2] - TC1/WO[0] TCC1/ WO[2] AC/CMP[2] CCL2/ IN[8] 24 34 46 PA25 VDDIO EXTINT[13] SERCOM3/ PAD[3] - TC1/WO[1] TCC1/ WO[3] AC/CMP[3] CCL2/ OUT[2] 37 49 PB22 VDDIN EXTINT[6] - TC3/WO[0] GCLK_IO[0] CCL0/ IN[0] 38 50 PB23 VDDIN EXTINT[7] - TC3/WO[1] GCLK_IO[1] CCL0/ OUT[0] 25 39 51 PA27 VDDIN EXTINT[15] GCLK_IO[0] 27 41 53 PA28 VDDIN EXTINT[8] GCLK_IO[0] SAM C20/C21 Family Data Sheet I/O Multiplexing and Considerations © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 34

Pin(1) I/O Pin Supply A B (2,3) C D E F G H I SAM C20E SAM C20G SAM C20J EIC REF ADC0 AC PTC SERCOM (2,3) SERCOM-ALT TC TCC TCC COM AC/GCLK CCL 31 45 57 PA30 VDDIN EXTINT[10] SERCOM1/ PAD[2] TCC1/WO[0] CORTEX_M0P/ SWCLK GCLK_IO[0] CCL1/ IN[3] 32 46 58 PA31 VDDIN EXTINT[11] SERCOM1/ PAD[3] TCC1/WO[1] CORTEX_M0P/ SWDIO CCL1/ OUT[1]

59 PB30 VDDIN EXTINT[14] - TCC0/WO[0] TCC1/

WO[2] AC/CMP[2]

60 PB31 VDDIN EXTINT[15] - TCC0/WO[1] TCC1/

WO[3] AC/CMP[3]

61 PB00 VDDANA EXTINT[0] Y[6] - TC3/WO[0] CCL0/

IN[1]

62 PB01 VDDANA EXTINT[1] Y[7] - TC3/WO[1] CCL0/

IN[2] 47 63 PB02 VDDANA EXTINT[2] Y[8] - TC2/WO[0] CCL0/ OUT[0] 48 64 PB03 VDDANA EXTINT[3] Y[9] - TC2/WO[1] Note: 1. Use the SAM C21J pinout muxing for the WLCSP56 package. 2. All analog pin functions are on peripheral function B. Peripheral function B must be selected to disable the digital control of the pin. 3. Only some pins can be used in SERCOM I 2C mode. For additional information, refer to 6.2.3 SERCOM I2C Pins. Related Links

6.2.3 SERCOM I2C Pins

6.2 Other Functions

6.2.1 Oscillator Pinout

The oscillators are not mapped to the normal PORT functions and their multiplexing are controlled by registers in the Oscillators Controller (OSCCTRL) and in the 32K Oscillators Controller (OSC32KCTRL). Table 6-5. Oscillator Pinout Oscillator Supply Signal I/O pin XOSC VDDIO XIN PA14 XOUT PA15 XOSC32K VDDANA XIN32 PA00 XOUT32 PA01

6.2.2 Serial Wire Debug Interface Pinout

Only the SWCLK pin is mapped to the normal PORT functions. A debugger cold-plugging or hot-plugging detection will automatically switch the SWDIO port to the SWDIO function. Table 6-6. Serial Wire Debug Interface Pinout Signal Supply I/O pin SWCLK VDDIN PA30 SWDIO VDDIN PA31 SAM C20/C21 Family Data Sheet I/O Multiplexing and Considerations © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 35

6.2.3 SERCOM I 2C Pins

Table 6-7. SERCOM Pins Supporting I2C Package Pins Supporting I 2C 32-pin PA08, PA09, PA16, PA17, PA22, PA23 48-pin PA08, PA09, PA12, PA13, PA16, PA17, PA22, PA23 64-pin PA08, PA09, PA12, PA13, PA16, PA17, PA22, PA23, PB12, PB13, PB16, PB17, PB30, PB31 100-pin PA08, PA09, PA16, PA17, PB12, PB13, PB16, PB17

6.2.4 GPIO Clusters

Table 6-8. GPIO Clusters Package Cluster GPIO Supplies Pin connected to the cluster 100 pins 1 PB31 PB30 PA31 PA30 PA28 PA27 VDDIN (92) GND (90)

2 PC28 PC27 PC26 PC25 PC24 PB25

VDDIO (77) GND( 76 )

3 PA25 PA24 PA23 PA22 PA21 PA20 PB21

VDDIO(63+77) GND(62+76)

4 PC21 PC20 PC19 PC18 PC17 PC16

VDDIO(51+63) GND(50+62)

5 PA15 PA14 PA13 PA12 PC14 PC13 PC12

VDDIO(36+51) GND(37+50)

6 PB15 PB13 PB12 PB11 PB10 PA11 PA10

VDDIO(25+36) GND(24+37)

7 PC07 PC06 PC05 PA07 PA06 PA05 PA04

PB09 PB05 PB04 PA03 PA02 PC02 PC01 PC00 PA01 PA00 PB03 PB02 PB01 PB00 VDDANA (12) GNDANA (11)

8 PC15 VDDIO(25) GND(37+50)

9 PB14 VDDIO(25) GND(24+37)

10 PB08 PB07 PB06 PC03 VDDIO(25) GNDANA (11)

Package Cluster GPIO Supplies Pin connected to the cluster 64 pins 1 PB31 PB30 PA31 PA30 PA28 PA27 VDDIN (56) GND (54)

2 PB23 PB22 VDDIO (48) GND (54+47)

3 PA25 PA24 PA23 PA22 PA21 PA20 PB17

VDDIO (48+34) GND (47+33)

4 PA15 PA14 PA13 PA12 PB15 PB14 PB13

VDDIO (34+21) GND (33+22)

5 PA11 PA10 PA08 PA09 VDDIO (21) GND (22)

6 PA07 PA06 PA05 PA04 PB09 PB08 PB07

PB06 PB05 PB04 PA03 PA02 PA01 PA00 PB03 PB02 PB01 PB00 VDDANA (8) GNDANA (7) 48 pins 1 PA31 PA30 PA28 PA27 VDDIN (44) GND (42)

2 PB23 PB22 VDDIO (36) GND (42+35)

3 PA25 PA24 PA23 PA22 PA21 PA20 PA19

PA18 PA17 PA16 PA15 PA14 PA13 PA12 PB11 PB10 VDDIO (36+17) GND (35+18)

4 PA11 PA10 PA08 PA09 VDDIO (17) GND (18)

5 PA07 PA06 PA05 PA04 PB09 PB08 PA03

VDDANA (6) GNDANA (5) 32 pins 1 PA31 PA30 PA28 PA27 VDDIN (30) GND (28)

2 PA25 PA24 PA23 PA22 PA19 PA18 PA17

PA16 PA15 PA14 PA11 PA10 PA08 PA09 VDDANA (9) GND (28+10)

3 PA07 PA06 PA05 PA04 PA03 PA02 PA01

VDDANA (9) GND (28+10) The SAM C20/C21 devices have three instances of the Timer/Counter for Control applications (TCC) peripheral, , TCC[2:0]. The following table lists the features for each TCC instance. Table 6-9. TCC Configuration Summary TCC# Channels (CC_NUM) Waveform Output (WO_NUM) Counter size Fault Dithering Output matrix Dead Time Insertion (DTI) SWAP Pattern generation 0 4 8 24-bit Yes Yes Yes Yes Yes Yes 1 2 4 24-bit Yes Yes Yes 2 2 2 16-bit Yes Note: The number of CC registers (CC_NUM) for each TCC corresponds to the number of compare/ capture channels, therefore a TCC can have more Waveform Outputs (WO_NUM) than CC registers. SAM C20/C21 Family Data Sheet I/O Multiplexing and Considerations © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 37

Power Supply and Start-Up Considerations

7.1 Power Domain Overview

Figure 7-1. Power Domain Overview, SAM C20/C21 E/G/J PD1 Digital Logic SERCOM[4:0], TCC[2:0] TC[3:0], DAC, I2S, AES, TRNG PAC, DMAC LOW POWER RAM LOW POWER RAM PA[7:2] PB[9:0] PA[1:0] PB[17:10] PA[25:8] PA[31:30] PB[31:30] VDDIO VDDIN GND VDDCORE GNDANA VDDANA ADC0 AC DAC PTC SDADC POR BOD50 OSCULP32K OSC32K XOSC32K Voltage Regulator OSC48M TOSC BODCORE POR XOSC Digital Logic (CPU, Peripherals) DPLL NVM HIGH SPEED RAM ADC1 PA[28:27] PB[23:22] SAM C20/C21 Family Data Sheet Power Supply and Start-Up Considerations © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 38

Figure 7-2. Power Domain Overview, SAM C20/C21 N PD1 Digital Logic SERCOM[4:0], TCC[2:0] TC[3:0], DAC, I2S, AES, TRNG PAC, DMAC LOW POWER RAM LOW POWER RAM PA[7:2] PB[5:0] PA[1:0] PB[25:10] PA[25:8] PA[31:30] PB[31:30] VDDIO VDDIN GND VDDCORE GNDANA VDDANA ADC0 AC DAC PTC SDADC POR BOD50 OSCULP32K OSC32K XOSC32K Voltage Regulator OSC48M TOSC BODCORE POR XOSC Digital Logic (CPU, Peripherals) DPLL NVM HIGH SPEED RAM ADC1 PC[2:0] PC3,PB14 PC[15:8] PB[8:6] PC[21:16] PC[28:24] PA[28:27] PC[7:5] PB[9]

7.2 Power Supply Considerations

7.2.1 Power Supplies, SAM C21/SAM C20

The SAM C21 has the following power supply pins:

VDDIO: Powers I/O lines and XOSC. Voltage is 2.70V to 5.50V.
VDDIN: Powers I/O lines and the OSC48M, TOSC and internal regulator. Voltage is 2.70V to 5.50V.
VDDANA: Powers I/O lines and the ADC, AC, DAC, PTC, SDADC, OSCULP32K, OSC32K, and XOSC32K. Voltage is 2.70V to 5.50V.
VDDCORE: Internal regulated voltage output. Powers the core, memories, peripherals, and FDPLL96M. Voltage is 1.2V typical. The same voltage must be applied to both the VDDIN and VDDANA pins. This common voltage is referred to as VDD in the datasheet. VDDIO must always be less than or equal to VDDIN. The ground pins, GND, are common to VDDCORE, VDDIO and VDDIN. The ground pin for VDDANA is GNDANA. For decoupling recommendations for the different power supplies, refer to the schematic checklist. The SAM C20 has the following power supply pins:
VDDIO: Powers I/O lines and XOSC. Voltage is 2.70V to 5.50V.
VDDIN: Powers I/O lines and the OSC48M, TOSC and internal regulator. Voltage is 2.70V to 5.50V. SAM C20/C21 Family Data Sheet Power Supply and Start-Up Considerations © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 39

VDDANA: Powers I/O lines and the ADC, AC, PTC, OSCULP32K, OSC32K, and XOSC32K. Voltage is 2.70V to 5.50V.
VDDCORE: Internal regulated voltage output. Powers the core, memories, peripherals, and FDPLL96M. Voltage is 1.2V typical. The same voltage must be applied to both VDDIN and VDDANA. This common voltage is referred to as VDD in the datasheet. VDDIO must always be less than or equal to VDDIN. The ground pins, GND, are common to VDDCORE, VDDIO and VDDIN. The ground pin for VDDANA is GNDANA. For decoupling recommendations for the different power supplies, refer to the schematic checklist.

7.2.2 Voltage Regulator

The SAM C20/C21 voltage regulators have these two modes:

Normal mode: This is the default mode when CPU and peripherals are running.
Low Power (LP) mode: This default mode is used when the chip is in standby mode.

7.2.3 Typical Powering Schematics

The SAM C20/C21 use a single supply from 2.70V to 5.50V or dual supply mode where VDDIO is supplied separately from VDDIN. The following figures show the recommended power supply connections. Figure 7-3. Power Supply Connection for single supply mode only VDDIO VDDANA VDDIN VDDCORE GND Main Supply (2.70V - 5.50V) SAM C20/C21 Family Data Sheet Power Supply and Start-Up Considerations © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 40

Power Supply Connection for dual supply mode Main Supply (2.70V - 5.50V) IO Supply (2.70V - 5.50V)

7.2.4 Power-Up Sequence

7.2.4.1 Minimum Rise Rate

The integrated Power-on Reset (POR) circuitry monitoring the VDDIN power supply requires a minimum rise rate.

7.2.4.2 Maximum Rise Rate

The rise rate of the power supply must not exceed the values described in Electrical Characteristics.

7.3 Power-Up

This section summarizes the power-up sequence of the SAM C20/C21. The behavior after power-up is controlled by the Power Manager.

7.3.1 Starting of Clocks

After power-up, the device is set to its initial state and kept in reset, until the power has stabilized throughout the device. Once the power has stabilized, the device will use a 4MHz clock. This clock is derived from the 48MHz Internal Oscillator (OSC48M), which is configured to provide a 4MHz clock and used as a clock source for generic clock generator 0. Generic clock generator 0 is the main clock for the Power Manager (PM). Some synchronous system clocks are active, allowing software execution. Refer to the “Clock Mask Register” in the Power Manager for the list of default peripheral clocks running. Synchronous system clocks that are running are by default not divided and receive a 4MHz clock through generic clock generator 0. Other generic clocks are disabled.

7.3.2 I/O Pins

7.3.3 Fetching of Initial Instructions

After reset has been released, the CPU starts fetching PC and SP values from the reset address, which is 0x00000000. This address points to the first executable address in the internal flash. The code read from the internal flash is free to configure the clock system and clock sources. Refer to the ARM Architecture Reference Manual for more information on CPU startup ( http://www.arm.com).

7.4 Power-On Reset and Brown-Out Detector

The SAM C20/C21 embed three features to monitor, warn, and/or reset the device:

POR: Power-on reset on VDDIN and VDDIO
BODVDD: Brown-out detector on VDDIN
BODCORE: Voltage Regulator Internal Brown-out detector on VDDCORE. The Voltage Regulator Internal BOD is calibrated in production and its calibration configuration is stored in the NVM User Row. This configuration should not be changed if the user row is written to assure the correct behavior of the BODCORE.

7.4.1 Power-On Reset on VDDIN

POR monitors VDDIN. It is always activated and monitors voltage at startup and also during all the sleep modes. If VDDIN goes below the threshold voltage, the entire chip is reset.

7.4.2 Power-On Reset on VDDIO

POR monitors VDDIO. It is always activated and monitors voltage at startup and also during all the sleep modes. If VDDIO goes below the threshold voltage, all IOs supplied by VDDIO are reset.

7.4.3 Brown-Out Detector on VDDIN

BODVDD monitors VDDIN.

7.4.4 Brown-Out Detector on VDDCORE

Once the device has started up, BODCORE monitors the internal VDDCORE. SAM C20/C21 Family Data Sheet Power Supply and Start-Up Considerations © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 42

Product Mapping Figure 8-1. SAM C21 N Product Mapping Code SRAM Undefined Peripherals Reserved IOBUS Reserved CAN0 EVSYS SERCOM0 SERCOM1 SERCOM2 SERCOM3 SERCOM4 SERCOM5 CAN1 TCC0 TCC1 TCC2 TC0 TC1 ADC0 0x42000400 0x42000800 0x42000C00 0x42001000 0x42001400 0x42001800 0x42002000 0x42001C00 0x42003000 0x42003400 0x42003800 0x42003C00 0x42004000 0x42004400 0x42004800 ADC1 0x42004C00 0x42002400 0x42002800 0x42002C00 SDADC 0x42005400 0x42005000 AC Reserved PORT DSU NVMCTRL DMAC MTB PAC PM MCLK RSTC OSCCTRL OSC32KCTRL SUPC Reserved GCLK WDT RTC EIC FREQM TSENS Reserved 0x42FFFFFF DAC 0x42005800 PTC 0x42006000 0x42005C00 CCL AHB-APB Bridge A AHB-APB Bridge B AHB-APB Bridge C AHB-APB Bridge D AHB DIVAS Reserved SERCOM6 SERCOM7 TC5 TC6 TC7 Internal SRAM Reserved Internal Flash AHB-APB Bridge D AHB-APB Bridge B AHB-APB Bridge CCodeGlobal Memory Space AHB-APB Bridge A SRAM AHB-APB 0x00000000 0x20000000 0x22008000 0x40000000 0x48000200 0x60000000 0x60000400 0xFFFFFFFF 0x00000000 0x00400000 0x1FFFFFFF 0x40000000 0x40000400 0x40000800 0x40000C00 0x40001000 0x40001400 0x40001800 0x40001C00 0x40002000 0x40002400 0x40002800 0x40002C00 0x40003000 0x40003400 0x40FFFFFF 0x20000000 0x20008000 0x40000000 0x41000000 0x42000000 0x43000000 0x48000000 0x480001FF 0x41000000 0x41002000 0x41004000 0x41006000 0x41008000 0x41009000 0x41FFFFFF TC2 TC3 TC4 0x42000000 0x43000000 0x43000400 0x43000800 0x43000C00 0x43001000 0x43001400 0x43001800 SAM C20/C21 Family Data Sheet Product Mapping © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 43

Figure 8-2. SAM C20 N Product Mapping Code SRAM Undefined Peripherals Reserved IOBUS Reserved EVSYS SERCOM0 SERCOM1 SERCOM2 SERCOM3 SERCOM4 SERCOM5 TCC0 TCC1 TCC2 TC0 TC1 ADC0 0x42000400 0x42000800 0x42000C00 0x42001000 0x42001400 0x42001800 0x42002000 0x42001C00 0x42003000 0x42003400 0x42003800 0x42003C00 0x42004000 0x42004400 0x42004800 0x42004C00 0x42002400 0x42002800 0x42002C00 0x42005400 0x42005000 AC Reserved PORT DSU NVMCTRL DMAC MTB PAC PM MCLK RSTC OSCCTRL OSC32KCTRL SUPC Reserved GCLK WDT RTC EIC FREQM TSENS Reserved 0x42FFFFFF 0x42005800 PTC 0x42006000 0x42005C00 CCL AHB-APB Bridge A AHB-APB Bridge B AHB-APB Bridge C AHB-APB Bridge D AHB DIVAS Reserved SERCOM6 SERCOM7 TC5 TC6 TC7 Internal SRAM Reserved Internal Flash AHB-APB Bridge D AHB-APB Bridge B AHB-APB Bridge CCodeGlobal Memory Space AHB-APB Bridge A SRAM AHB-APB 0x00000000 0x20000000 0x22008000 0x40000000 0x48000200 0x60000000 0x60000400 0xFFFFFFFF 0x00000000 0x00400000 0x1FFFFFFF 0x40000000 0x40000400 0x40000800 0x40000C00 0x40001000 0x40001400 0x40001800 0x40001C00 0x40002000 0x40002400 0x40002800 0x40002C00 0x40003000 0x40003400 0x40FFFFFF 0x20000000 0x20008000 0x40000000 0x41000000 0x42000000 0x43000000 0x48000000 0x480001FF 0x41000000 0x41002000 0x41004000 0x41006000 0x41008000 0x41009000 0x41FFFFFF TC2 TC3 TC4 0x42000000 0x43000000 0x43000400 0x43000800 0x43000C00 0x43001000 0x43001400 0x43001800 Reserved Reserved Reserved Reserved Reserved SAM C20/C21 Family Data Sheet Product Mapping © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 44

Figure 8-3. SAM C21 E/G/J Product Mapping Code SRAM Undefined Peripherals Reserved IOBUS Reserved Internal SRAM Internal Flash Reserved CAN0 EVSYS SERCOM0 SERCOM1 SERCOM2 SERCOM3 SERCOM4 SERCOM5 TC3 CAN1 TCC0 TCC1 TCC2 TC0 TC1 TC2 TC4 ADC0 0x42000400 0x42000800 0x42000C00 0x42001000 0x42001400 0x42001800 0x42002000 0x42001C00 0x42003000 0x42003400 0x42003800 0x42003C00 0x42004000 0x42004400 0x42004800 ADC1 0x42004C00 0x42002400 0x42002800 0x42002C00 SDADC 0x42005400 0x42005000 AC Reserved PORT DSU NVMCTRL DMAC MTB PAC PM MCLK RSTC OSCCTRL OSC32KCTRL SUPC Reserved GCLK WDT RTC EIC FREQM TSENS Reserved 0x42FFFFFF DAC 0x42005800 PTC 0x42006000 0x42005C00 CCL AHB-APB Bridge A AHB-APB Bridge B AHB-APB Bridge C Reserved AHB DIVAS 0x42000000 0x00000000 0x20000000 0x22008000 0x40000000 0x48000200 0x60000000 0x60000400 0xFFFFFFFF 0x00000000 0x00400000 0x1FFFFFFF 0x20000000 0x20008000 AHB-APB Bridge C CodeGlobal Memory Space AHB-APB Bridge A SRAM AHB-APB AHB-APB Bridge B 0x40000000 0x41000000 0x42000000 0x43000000 0x48000000 0x480001FF 0x41000000 0x41002000 0x41004000 0x41006000 0x41008000 0x41009000 0x41FFFFFF 0x40000000 0x40000400 0x40000800 0x40000C00 0x40001000 0x40001400 0x40001800 0x40001C00 0x40FFFFFF 0x40002000 0x40002800 0x40002C00 0x40003000 0x40003400 0x40002400 SAM C20/C21 Family Data Sheet Product Mapping © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 45

Figure 8-4. SAM C20 E/G/J Product Mapping Code SRAM Undefined Peripherals Reserved IOBUS Reserved Global Memory Space 0x00000000 0x20000000 0x22008000 0x40000000 0x48000200 0x60000000 0x60000400 0xFFFFFFFF Internal SRAM SRAM AHB-APB Internal Flash Reserved Code 0x00000000 0x00400000 0x1FFFFFFF 0x20000000 0x20008000 0x40000000 0x41000000 0x42000000 0x43000000 Reserved EVSYS SERCOM0 SERCOM1 SERCOM2 SERCOM3 Reserved Reserved AHB-APB Bridge C TC3 Reserved TCC0 TC0 TC1 TC2 TC4 ADC0 0x42000000 0x42000400 0x42000800 0x42000C00 0x42001000 0x42001400 0x42001800 0x42002000 0x42001C00 0x42003000 0x42003400 0x42003800 0x42003C00 0x42004000 0x42004400 0x42004800 Reserved 0x42004C00 0x42002400 0x42002800 0x42002C00 Reserved 0x42005400 0x42005000 AC AHB-APB Bridge B Reserved PORT DSU NVMCTRL DMAC 0x41000000 0x41002000 0x41004000 0x41006000 MTB 0x41008000 0x41009000 0x41FFFFFF PAC PM MCLK RSTC OSCCTRL OSC32KCTRL SUPC AHB-APB Bridge A 0x40000000 0x40000400 0x40000800 0x40000C00 0x40001000 0x40001400 0x40001800 0x40001C00 Reserved 0x40FFFFFF GCLK WDT RTC EIC FREQM Reserved 0x40002000 0x40002800 0x40002C00 0x40003000 0x40003400 Reserved 0x42FFFFFF Reserved 0x42005800 PTC 0x42006000 0x42005C00 CCL 0x48000000 0x480001FF AHB-APB Bridge A AHB-APB Bridge B AHB-APB Bridge C Reserved AHB DIVAS 0x40002400 TCC1 TCC2 SAM C20/C21 Family Data Sheet Product Mapping © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 46

Memories

9.1 Embedded Memories

Internal high-speed Flash with read-while-write capability on section of the array
Internal high-speed RAM, single-cycle access at full speed

9.2 Physical Memory Map

The High-Speed bus is implemented as a bus matrix. All High-Speed bus addresses are fixed, and they are never remapped in any way, even during boot. The 32-bit physical address space is mapped as follows: Table 9-1. SAM C20/C21 Physical Memory Map(1) Memory Start address Size Size Size Size x18 x17 x16 x15 Embedded Flash 0x00000000 256 Kbytes 128 Kbytes 64 Kbytes 32 Kbytes Embedded RWW section 0x00400000 8 Kbytes 4 Kbytes 2 Kbytes 1 Kbytes Embedded high-speed SRAM 0x20000000 32 Kbytes 16 Kbytes 8 Kbytes 4 Kbytes AHB-APB Bridge A 0x40000000 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes AHB-APB Bridge B 0x41000000 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes AHB-APB Bridge C 0x42000000 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes AHB-APB Bridge D 0x43000000 64 Kbytes - - - AHB DIVAS 0x48000000 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes IOBUS 0x60000000 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes Note: 1. x = SAM C20/C21 G/J/E/N. The N-series (100-pin devices) does not include x16 and x15 option. Table 9-2. SAM C20/C21 Flash Memory Parameters(1) Device Flash size (FLASH_PM) Number of pages (FLASH_P) Page size (FLASH_W) x18 256Kbytes 4096 64 bytes x17 128Kbytes 2048 64 bytes x16 64Kbytes 1024 64 bytes x15 32Kbytes 512 64 bytes Note: 1. x = SAM C20/C21 G/J/E/N. The N-series (100-pin devices) does not include x16 and x15 option. SAM C20/C21 Family Data Sheet Memories © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 47

Table 9-3. SAM C20/C21 RWW Section Parameters(1) Device Flash size (FLASH_PM) Number of pages (FLASH_P) Page size (FLASH_W) x18 8Kbytes 128 64 bytes x17 4Kbytes 64 64 bytes x16 2Kbytes 32 64 bytes x15 1Kbytes 16 64 bytes Note: 1. x = SAM C20/C21 G/J/E/N. The N-series (100-pin devices) does not include x16 and x15 option.

9.3 NVM User Row Mapping

The first two 32-bit words of the NVM User Row contains calibration data that are automatically read at device power on. The NVM User Row can be read at address 0x804000. To write the NVM User Row, refer to the NVMCTRL - Non-Volatile Memory Controller. Note that when writing to the user row the values do not get loaded by the other modules on the device until a device reset occurs. Table 9-4. NVM User Row Mapping Bit Position Name Usage Production setting Related Peripheral Register 2:0 BOOTPROT Used to select one of eight different bootloader sizes.

7 NVMCTRL

3 Reserved - 1 -

6:4 EEPROM Used to select one of eight different EEPROM sizes.

7 Reserved - 1 -

13:8 BODVDD Level BODVDD Threshold Level at power on. 8 SUPC.BODVDD 14 BODVDD Disable BODVDD Disable at power on. 0 SUPC.BODVDD 16:15 BODVDD Action BODVDD Action at power on. 1 SUPC.BODVDD 25:17 Reserved Voltage Regulator Internal BOD (BODCORE) configuration. These bits are written in production and must not be changed. 0xA8 - 26 WDT Enable WDT Enable at power on. 0 WDT.CTRLA 27 WDT Always-On WDT Always-On at power on. 0 WDT.CTRLA 31:28 WDT Period WDT Period at power on. 0xB WDT.CONFIG SAM C20/C21 Family Data Sheet Memories © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 48

Bit Position Name Usage Production setting Related Peripheral Register 35:32 WDT Window WDT Window mode time-out at power on. 0xB WDT.CONFIG 39:36 WDT EWOFFSET WDT Early Warning Interrupt Time Offset at power on. 0xB WDT.EWCTRL

40 WDT WEN WDT Timer Window Mode

Enable at power on. 0 WDT.CTRLA

41 BODVDD

configuration at power on. 0 SUPC.BODVDD

42 Reserved Voltage Regulator Internal

BOD (BODCORE) configuration. These bits are written in production and must not be changed. 0 - 47:43 Reserved - 0x1F - 63:48 LOCK NVM Region Lock Bits. 0xFFFF NVMCTRL Related Links 27. NVMCTRL – Nonvolatile Memory Controller

23.8.1 CTRLA

23.8.2 CONFIG

23.8.3 EWCTRL

22.8.5 BODVDD

9.4 NVM Software Calibration Area Mapping

The NVM Software Calibration Area contains calibration data that are measured and written during production test. These calibration values should be read by the application software and written back to the corresponding register. The NVM Software Calibration Area can be read at address 0x806020. The NVM Software Calibration Area can not be written. Table 9-5. SAM CA1 NVM Software Calibration Area Mapping Bit Position Name Description 2:0 ADC0 LINEARITY ADC0 Linearity Calibration. Should be written to the CALIB register. 5:3 ADC0 BIASCAL ADC0 Bias Calibration. Should be written to the CALIB register. 8:6 ADC1 LINEARITY ADC1 Linearity Calibration. Should be written to the CALIB register. 11:9 ADC1 BIASCAL ADC1 Bias Calibration. Should be written to the CALIB register. 18:12 OSC32K CAL OSC32K Calibration. Should be written to OSC32K register. SAM C20/C21 Family Data Sheet Memories © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 49

Bit Position Name Description 40:19 CAL48M 5V OSC48M Calibration: VDD range 3.6V to 5.5V. Should be written to the CAL48M register. 62:41 CAL48M 3V3 OSC48M Calibration: VDD range 2.7V to 3.6V. Should be written to the CAL48M register.

63 Reserved

20.8.18 CAL48M

9.5 NVM Temperature Calibration Area Mapping, SAM C21

The NVM Temperature Calibration Area contains calibration data that are measured and written during production test. These calibration values should be read by the application software and written back to the corresponding register. The NVM Temperature Calibration Area can be read at address 0x806030. The NVM Temperature Calibration Area can not be written. Table 9-6. NVM Temperature Calibration Area Mapping, SAM C21 Bit Position Name Description 5:0 TSENS TCAL TSENS Temperature Calibration. Should be written to the TSENS CAL register. 11:6 TSENS FCAL TSENS Frequency Calibration. Should be written to the TSENS CAL register. 35:12 TSENS GAIN TSENS Gain Calibration. Should be written to the TSENS GAIN register. 59:36 TSENS OFFSET TSENS Offset Calibration. Should be written to TSENS OFFSET register. 63:60 Reserved Related Links

43.8.15 CAL

43.8.13 GAIN

43.8.14 OFFSET

9.6 Serial Number

Each device has a unique 128-bit serial number which is a concatenation of four 32-bit words contained at the following addresses: Word 0: 0x0080A00C Word 1: 0x0080A040 SAM C20/C21 Family Data Sheet Memories © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 50

Word 2: 0x0080A044 Word 3: 0x0080A048 The uniqueness of the serial number is guaranteed only when using all 128 bits. SAM C20/C21 Family Data Sheet Memories © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 51

Processor and Architecture

10.1 Cortex M0+ Processor

The SAM C20/C21 implement the ARM Cortex -M0+ processor, based on the ARMv6 Architecture and Thumb -2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0 core, and upward compatible to Cortex-M3 and M4 cores. The implemented ARM Cortex-M0+ is revision r0p1. For more information refer to http://www.arm.com.

10.1.1 Cortex M0+ Configuration

Table 10-1. Cortex M0+ Configuration Features Cortex-M0+ options SAM C20/C21 configurations Interrupts External interrupts 0-32 32 Data endianness Little-endian or big-endian Little-endian SysTick timer Present or absent Present Number of watchpoint comparators 0, 1, 2 2 Number of breakpoint comparators 0, 1, 2, 3, 4 4 Halting debug support Present or absent Present Multiplier Fast or small Fast (single cycle) Single-cycle I/O port Present or absent Present Wake-up interrupt controller Supported or not supported Not supported Vector Table Offset Register Present or absent Present Unprivileged/Privileged support Present or absent Present Memory Protection Unit Not present or 8-region 8-region Reset all registers Present or absent Absent Instruction fetch width 16-bit only or mostly 32-bit 32-bit The ARM Cortex-M0+ core has two bus interfaces:

Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all system memory, which includes flash and RAM.
Single 32-bit I/O port bus interfacing to the PORT and DIVAS with 1-cycle loads and stores.

10.1.2 Cortex-M0+ Peripherals

System Control Space (SCS) – The processor provides debug through registers in the SCS. Refer to the Cortex-M0+ Technical Reference Manual for details (http://www.arm.com).
Nested Vectored Interrupt Controller (NVIC) – External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software can set the priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely SAM C20/C21 Family Data Sheet Processor and Architecture © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 52

coupled, providing low latency interrupt processing and efficient processing of late arriving interrupts. Refer to

10.2 Nested Vector Interrupt Controller and the Cortex-M0+ Technical

Reference Manual for details (http://www.arm.com).

System Timer (SysTick) – The System Timer is a 24-bit timer clocked by CLK_CPU that extends the functionality of both the processor and the NVIC. Refer to the Cortex-M0+ Technical Reference Manual for details http://www.arm.com).
System Control Block (SCB) – The System Control Block provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions. Refer to the Cortex-M0+ Devices Generic User Guide for details ( http://www.arm.com).
Micro Trace Buffer (MTB) – The CoreSight MTB-M0+ (MTB) provides a simple execution trace capability to the Cortex-M0+ processor. Refer to section 10.3 Micro Trace Buffer and the CoreSight MTB-M0+ Technical Reference Manual for details (http://www.arm.com).
Memory Protection Unit (MPU) – The Memory Protection Unit divides the memory map into a number of regions, and defines the location, size, access permissions and memory attributes of each region. Refer to the Cortex- M0+ Devices Generic User Guide for details ( http://www.arm.com)

10.1.3 Cortex-M0+ Address Map

Table 10-2. Cortex-M0+ Address Map Address Peripheral 0xE000E000 System Control Space (SCS) 0xE000E010 System Timer (SysTick) 0xE000E100 Nested Vectored Interrupt Controller (NVIC) 0xE000ED00 System Control Block (SCB) 0x41008000 Micro Trace Buffer (MTB) Related Links 8. Product Mapping

10.1.4 I/O Interface

10.1.4.1 Overview

Because accesses to the AMBA® AHB-Lite™ and the single cycle I/O interface can be made concurrently, the Cortex-M0+ processor can fetch the next instructions while accessing the I/Os. This enables single cycle I/O accesses to be sustained for as long as needed.

10.1.4.2 Description

10.2 Nested Vector Interrupt Controller

10.2.1 Overview

The Nested Vectored Interrupt Controller (NVIC) in the SAM C20/C21 supports 32 interrupt lines with four different priority levels. For more details, refer to the Cortex-M0+ Technical Reference Manual ( http:// www.arm.com).

10.2.2 Interrupt Line Mapping

Each of the interrupt lines is connected to one peripheral instance, as shown in the table below. Each peripheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register. The interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by writing a one to the corresponding bit in the peripheral’s Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the corresponding bit in the peripheral’s Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt requests for one peripheral are ORed together on system level, generating one interrupt request for each peripheral. An interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending registers (SETPEND/CLRPEND bits in ISPR/ICPR). For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/ CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for each interrupt. Table 10-3. Interrupt Line Mapping, SAM C21 Peripheral Source NVIC Line EIC NMI – External Interrupt Controller NMI PM – Power Manager MCLK - Main Clock OSCCTRL - Oscillators Controller OSC32KCTRL - 32kHz Oscillators Controller SUPC - Supply Controller PAC - Protection Access Controller WDT – Watchdog Timer 1 RTC – Real Time Clock 2 EIC – External Interrupt Controller 3 FREQM – Frequency Meter 4 TSENS – Temperature Sensor 5 NVMCTRL – Non-Volatile Memory Controller 6 DMAC - Direct Memory Access Controller 7 SAM C20/C21 Family Data Sheet Processor and Architecture © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 54

Peripheral Source NVIC Line EVSYS – Event System 8 SERCOM0 – Serial Communication Controller 0 SERCOM6 – Serial Communication Controller 6 SERCOM1 – Serial Communication Controller 1 SERCOM7 – Serial Communication Controller 7 SERCOM2 – Serial Communication Controller 2 11 SERCOM3 – Serial Communication Controller 3 12 SERCOM4 – Serial Communication Controller 4 13 SERCOM5 – Serial Communication Controller 5 14 CAN0 – Controller Area Network 0 15 CAN1 – Controller Area Network 1 16 TCC0 – Timer Counter for Control 0 17 TCC1 – Timer Counter for Control 1 18 TCC2 – Timer Counter for Control 2 19 TC0 – Timer Counter 0 TC5 – Timer Counter 5 TC1 – Timer Counter 1 TC6 – Timer Counter 6 TC2 – Timer Counter 2 TC7 – Timer Counter 7 TC3 – Timer Counter 3Reserved 23 TC4 – Timer Counter 4Reserved 24 ADC0 – Analog-to-Digital Converter 0 25 ADC1 – Analog-to-Digital Converter 1Reserved 26 AC – Analog Comparator 27 DAC – Digital-to-Analog Converter 28 SDADC – Sigma-Delta Analog-to-Digital Converter 1 29 PTC – Peripheral Touch Controller 30 Reserved 31 SAM C20/C21 Family Data Sheet Processor and Architecture © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 55

Table 10-4. Interrupt Line Mapping, SAM C20 Peripheral Source NVIC Line EIC NMI – External Interrupt Controller NMI PM – Power Manager MCLK - Main Clock OSCCTRL - Oscillators Controller OSC32KCTRL - 32kHz Oscillators Controller SUPC - Supply Controller PAC - Protection Access Controller WDT – Watchdog Timer 1 RTC – Real Time Clock 2 EIC – External Interrupt Controller 3 FREQM – Frequency Meter 4 Reserved 5 NVMCTRL – Non-Volatile Memory Controller 6 DMAC - Direct Memory Access Controller 7 EVSYS – Event System 8 SERCOM0 – Serial Communication Controller 0 SERCOM6 – Serial Communication Controller 6 SERCOM1 – Serial Communication Controller 1 SERCOM7 – Serial Communication Controller 7 SERCOM2 – Serial Communication Controller 2 11 SERCOM3 – Serial Communication Controller 3 12 SERCOM4 – Serial Communication Controller 4 13 SERCOM5 – Serial Communication Controller 5 14 Reserved 15 Reserved 16 TCC0 – Timer Counter for Control 0 17 TCC1 – Timer Counter for Control 1 18 TCC2 – Timer Counter for Control 2 19 TC0 – Timer Counter 0 TC5 – Timer Counter 5 SAM C20/C21 Family Data Sheet Processor and Architecture © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 56

Peripheral Source NVIC Line TC1 – Timer Counter 1 TC6 – Timer Counter 6 TC2 – Timer Counter 2 TC7 – Timer Counter 7 TC3 – Timer Counter 3Reserved 23 TC4 – Timer Counter 4Reserved 24 ADC0 – Analog-to-Digital Converter 0 25 Reserved 26 AC – Analog Comparator 27 Reserved 28 Reserved 29 PTC – Peripheral Touch Controller 30 Reserved 31

10.3 Micro Trace Buffer

10.3.1 Features

Program flow tracing for the Cortex-M0+ processor
MTB SRAM can be used for both trace and general purpose storage by the processor
The position and size of the trace buffer in SRAM is configurable by software
CoreSight compliant

10.3.2 Overview

When enabled, the MTB records changes in program flow, reported by the Cortex-M0+ processor over the execution trace interface shared between the Cortex-M0+ processor and the CoreSight MTB-M0+. This information is stored as trace packets in the SRAM by the MTB. An off-chip debugger can extract the trace information using the Debug Access Port to read the trace information from the SRAM. The debugger can then reconstruct the program flow from this information. The MTB simultaneously stores trace information into the SRAM, and gives the processor access to the SRAM. The MTB ensures that trace write accesses have priority over processor accesses. The execution trace packet consists of a pair of 32-bit words that the MTB generates when it detects the processor PC value changes non-sequentially. A non-sequential PC change can occur during branch instructions or during exception entry. See the CoreSight MTB-M0+ Technical Reference Manual for more details on the MTB execution trace packet format. Tracing is enabled when the MASTER.EN bit in the Master Trace Control Register is 1. There are various ways to set the bit to 1 to start tracing, or to 0 to stop tracing. See the CoreSight Cortex-M0+ Technical SAM C20/C21 Family Data Sheet Processor and Architecture © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 57

Reference Manual for more details on the Trace start and stop and for a detailed description of the MTB’s MASTER register. The MTB can be programmed to stop tracing automatically when the memory fills to a specified watermark level or to start or stop tracing by writing directly to the MASTER.EN bit. If the watermark mechanism is not being used and the trace buffer overflows, then the buffer wraps around overwriting previous trace packets. The base address of the MTB registers is 0x41008000; this address is also written in the CoreSight ROM Table. The offset of each register from the base address is fixed and as defined by the CoreSight MTB- M0+ Technical Reference Manual. The MTB has 4 programmable registers to control the behavior of the trace features:

POSITION: Contains the trace write pointer and the wrap bit,
MASTER: Contains the main trace enable bit and other trace control fields,
FLOW: Contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits,
BASE: Indicates where the SRAM is located in the processor memory map. This register is provided to enable auto discovery of the MTB SRAM location, by a debug agent. See the CoreSight MTB-M0+ Technical Reference Manual for a detailed description of these registers.

10.4 High-Speed Bus System

10.4.1 Features

High-Speed Bus Matrix has the following features:

Symmetric crossbar bus switch implementation
Allows concurrent accesses from different masters to different slaves
32-bit data bus
Operation at a 1-to-1 clock frequency with the bus masters

10.4.2 Configuration

Figure 10-1. Master-Slave Relation High-Speed Bus Matrix, SAM C20/C21 DSU DSU High-Speed Bus SLAVES FlexRAM MASTER ID SLAVE ID FlexRAM PORT ID Internal Flash AHB-APB Bridge A AHB-APB Bridge B AHB-APB Bridge C DIVAS 0 3 4 5 7 9 8 7 5-6 3-4 2 1 0 126 Multi-Slave MASTERS Priviledged FlexRAM-access MASTERS CM0+ DSU DMAC Data MTB CAN 1 CAN 0 DMAC WB DMAC Fetch MTB CAN 1 CAN 0 DMAC WB DMAC Fetch DSU CM0+ DMAC Data AHB-APB Bridge D (2) (2) 1. The AHB-APB bridge D is available only on C21N and C20N. SAM C20/C21 Family Data Sheet Processor and Architecture © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 58

The CAN peripheral is available only on C21. Table 10-5. Bus Matrix Masters Bus Matrix Masters Master ID CM0+ - Cortex M0+ Processor 0 DSU - Device Service Unit 1 DMAC - Direct Memory Access Controller / Data Access 2 Table 10-6. Bus Matrix Slaves Bus Matrix Slaves Slave ID Internal Flash Memory 0 SRAM Port 4 - CM0+ Access 1 SRAM Port 6 - DSU Access 2 AHB-APB Bridge A 3 AHB-APB Bridge B 4 AHB-APB Bridge C 5 SRAM Port 5 - DMAC Data Access 6 DIVAS - Divide Accelerator 7 Table 10-7. SRAM Port Connections SRAM Port Connection Port ID Connection Type CM0+ - Cortex M0+ Processor 0 Bus Matrix DSU - Device Service Unit 1 Bus Matrix DMAC - Direct Memory Access Controller - Data Access 2 Bus Matrix DMAC - Direct Memory Access Controller - Fetch Access 0 3 Direct DMAC - Direct Memory Access Controller - Fetch Access 1 4 Direct DMAC - Direct Memory Access Controller - Write-Back Access 0 5 Direct DMAC - Direct Memory Access Controller - Write-Back Access 1 6 Direct CAN0 - Controller Area Network 0 7 Direct Reserved 8 Reserved MTB - Micro Trace Buffer 9 Direct

10.4.3 SRAM Quality of Service

To ensure that masters with latency requirements get sufficient priority when accessing RAM, the different masters can be configured to have a given priority for different type of access. SAM C20/C21 Family Data Sheet Processor and Architecture © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 59

The Quality of Service (QoS) level is independently selected for each master accessing the RAM. For any access to the RAM the RAM also receives the QoS level. The QoS levels and their corresponding bit values for the QoS level configuration is shown in below. Table 10-8. Quality of Service Level Configuration Value Name Description 0x0 DISABLE Background (no sensitive operation) 0x1 LOW Sensitive Bandwidth 0x2 MEDIUM Sensitive Latency 0x3 HIGH Critical Latency If a master is configured with QoS level DISABLE (0x0) or LOW (0x1) there will be minimum latency of one cycle for the RAM access. The priority order for concurrent accesses are decided by two factors. First, the QoS level for the master and second, a static priority given by Table 10-7. The lowest port ID has the highest static priority. The MTB has fixed QoS level HIGH (0x3) and the DSU has fixed QoS level LOW (0x1). The CPU QoS level can be written/read at address 0x41007110, bits [1:0]. Its reset value is 0x0. Refer to different master QOSCTRL registers for configuring QoS for the other masters (for SAM C21: CAN, DMAC; for SAM C20: DMAC). SAM C20/C21 Family Data Sheet Processor and Architecture © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 60

PAC - Peripheral Access Controller

11.1 Overview

The Peripheral Access Controller provides an interface for the locking and unlocking of peripheral registers within the device. It reports all violations that could happen when accessing a peripheral: write protected access, illegal access, enable protected access, access when clock synchronization or software reset is on-going. These errors are reported in a unique interrupt flag for a peripheral. The PAC module also reports errors occurring at the slave bus level, when an access to a non-existing address is detected.

11.2 Features

Manages write protection access and reports access errors for the peripheral modules or bridges.

11.3 Block Diagram

Figure 11-1. PAC Block Diagram INTFLAG PERIPHERAL m PERIPHERAL 0 BUSn BUS0 Peripheral ERROR Peripheral ERROR WRITE CONTROL WRITE CONTROL PAC CONTROL PERIPHERAL m PERIPHERAL 0 SLAVEs PAC IRQ APB Slave ERROR

11.4 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

11.4.1 IO Lines

Not applicable.

11.4.2 Power Management

The PAC can continue to operate in any Sleep mode where the selected source clock is running. The PAC interrupts can be used to wake up the device from Sleep modes. The events can trigger other operations in the system without exiting sleep modes. SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 61

PM – Power Manager

11.4.3 Clocks

The PAC bus clock (CLK_PAC_APB) can be enabled and disabled in the Main Clock module. The default state of CLK_PAC_APB can be found in the related links. Related Links 17. MCLK – Main Clock

17.6.2.6 Peripheral Clock Masking

11.4.4 DMA

Not applicable.

11.4.5 Interrupts

The interrupt request line is connected to the Interrupt Controller. Using the PAC interrupt requires the Interrupt Controller to be configured first. Table 11-1. Interrupt Lines Instances NVIC Line PAC PACERR Related Links

11.4.6 Events

The events are connected to the Event System, which may need configuration. Related Links 29. EVSYS – Event System

11.4.7 Debug Operation

When the CPU is halted in debug mode, write protection of all peripherals is disabled and the PAC continues normal operation.

11.4.8 Register Access Protection

All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Write Control (WRCTRL) register
AHB Slave Bus Interrupt Flag Status and Clear (INTFLAGAHB) register
Peripheral Interrupt Flag Status and Clear n (INTFLAG A/B/C...) registers Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write- Protection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger. SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 62

11.5 Functional Description

11.5.1 Principle of Operation

The Peripheral Access Control module allows the user to set a write protection on peripheral modules and generate an interrupt in case of a peripheral access violation. The peripheral’s protection can be set, cleared or locked at the user discretion. A set of Interrupt Flag and Status registers informs the user on the status of the violation in the peripherals. In addition, slaves bus errors can be also reported in the cases where reserved area is accessed by the application.

11.5.2 Basic Operation

11.5.2.1 Initialization

After reset, the PAC is enabled.

11.5.2.2 Initialization, Enabling and Resetting

The PAC is always enabled after reset. Only a hardware reset will reset the PAC module.

11.5.2.3 Operations

The PAC module allows the user to set, clear or lock the write protection status of all peripherals on all Peripheral Bridges. If a peripheral register violation occurs, the Peripheral Interrupt Flag n registers (INTFLAGn) are updated to inform the user on the status of the violation in the peripherals connected to the Peripheral Bridge n (n = A,B,C ...). The corresponding Peripheral Write Control Status n register (STATUSn) gives the state of the write protection for all peripherals connected to the corresponding Peripheral Bridge n. Refer to 11.5.2.4 Peripheral Access Errors for details. The PAC module also report the errors occurring at slave bus level when an access to reserved area is detected. AHB Slave Bus Interrupt Flag register (INTFLAGAHB) informs the user on the status of the violation in the corresponding slave. Refer to the 11.5.2.7 AHB Slave Bus Errors for details.

11.5.2.4 Peripheral Access Errors

The following events will generate a Peripheral Access Error:

Protected write: To avoid unexpected writes to a peripheral's registers, each peripheral can be write protected. Only the registers denoted as “PAC Write-Protection” in the module’s datasheet can be protected. If a peripheral is not write protected, write data accesses are performed normally. If a peripheral is write protected and if a write access is attempted, data will not be written and peripheral returns an access error. The corresponding interrupt flag bit in the INTFLAGn register will be set.
Illegal access: Access to an unimplemented register within the module.
Synchronized write error: For write-synchronized registers an error will be reported if the register is written while a synchronization is ongoing. When any of the INTFLAGn registers bit are set, an interrupt will be requested if the PAC interrupt enable bit is set.

11.5.2.5 Write Access Protection Management

Peripheral access control can be enabled or disabled by writing to the WRCTRL register. The data written to the WRCTRL register is composed of two fields; WRCTRL.PERID and WRCTRL.KEY. The WRCTRL.PERID is an unique identifier corresponding to a peripheral. The WRCTRL.KEY is a key SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 63

value that defines the operation to be done on the control access bit. These operations can be “clear protection”, “set protection” and “set and lock protection bit”. The “clear protection” operation will remove the write access protection for the peripheral selected by WRCTRL.PERID. Write accesses are allowed for the registers in this peripheral. The “set protection” operation will set the write access protection for the peripheral selected by WRCTRL.PERID. Write accesses are not allowed for the registers with write protection property in this peripheral. The “set and lock protection” operation will set the write access protection for the peripheral selected by WRCTRL.PERID and locks the access rights of the selected peripheral registers. The write access protection will only be cleared by a hardware reset. The peripheral access control status can be read from the corresponding STATUSn register.

11.5.2.6 Write Access Protection Management Errors

Only word-wise writes to the WRCTRL register will effectively change the access protection. Other type of accesses will have no effect and will cause a PAC write access error. This error is reported in the INTFLAGn.PAC bit corresponding to the PAC module. PAC also offers an additional safety feature for correct program execution with an interrupt generated on double write clear protection or double write set protection. If a peripheral is write protected and a subsequent set protection operation is detected then the PAC returns an error, and similarly for a double clear protection operation. In addition, an error is generated when writing a “set and lock” protection to a write-protected peripheral or when a write access is done to a locked set protection. This can be used to ensure that the application follows the intended program flow by always following a write protect with an unprotect and conversely. However in applications where a write protected peripheral is used in several contexts, e.g. interrupt, care should be taken so that either the interrupt can not happen while the main application or other interrupt levels manipulates the write protection status or when the interrupt handler needs to unprotect the peripheral based on the current protection status by reading the STATUS register. The errors generated while accessing the PAC module registers (eg. key error, double protect error...) will set the INTFLAGn.PAC flag.

11.5.2.7 AHB Slave Bus Errors

The PAC module reports errors occurring at the AHB Slave bus level. These errors are generated when an access is performed at an address where no slave (bridge or peripheral) is mapped . These errors are reported in the corresponding bits of the INTFLAGAHB register.

11.5.2.8 Generating Events

The PAC module can also generate an event when any of the Interrupt Flag registers bit are set. To enable the PAC event generation, the control bit EVCTRL.ERREO must be set a '1'.

11.5.3 DMA Operation

Not applicable.

11.5.4 Interrupts

The PAC has the following interrupt source:

Error (ERR): Indicates that a peripheral access violation occurred in one of the peripherals controlled by the PAC module, or a bridge error occurred in one of the bridges reported by the PAC – This interrupt is a synchronous wake-up source. SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 64

Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAGAHB and INTFLAGn) registers is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the PAC is reset. All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. The user must read the INTFLAGAHB and INTFLAGn registers to determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be generated. Related Links

19.6.3.3 Sleep Mode Controller

11.5.5 Events

The PAC can generate the following output event:

Error (ERR): Generated when one of the interrupt flag registers bits is set Writing a '1' to an Event Output bit in the Event Control Register (EVCTRL.ERREO) enables the corresponding output event. Writing a '0' to this bit disables the corresponding output event.

11.5.6 Sleep Mode Operation

In Sleep mode, the PAC is kept enabled if an available bus master (CPU, DMA) is running. The PAC will continue to catch access errors from the module and generate interrupts or events.

11.5.7 Synchronization

11.6 Register Summary

Offset Name Bit Pos. 0x00 WRCTRL 7:0 PERID[7:0] 15:8 PERID[15:8] 23:16 KEY[7:0] 31:24 0x04 EVCTRL 7:0 ERREO 0x05 ... 0x07 Reserved 0x08 INTENCLR 7:0 ERR 0x09 INTENSET 7:0 ERR 0x0A ... 0x0F Reserved 0x10 INTFLAGAHB 7:0 DIVAS LPRAMDMAC HPB2 HPB0 HPB1 HSRAMDSU HSRAMCM0P FLASH 15:8 HPB3 23:16 31:24 0x14 INTFLAGA 7:0 GCLK SUPC OSC32KCTR L OSCCTRL RSTC MCLK PM PAC 15:8 TSENS FREQM EIC RTC WDT 23:16 31:24 0x18 INTFLAGB 7:0 MTB DMAC NVMCTRL DSU PORT 15:8 23:16 31:24 0x1C INTFLAGC 7:0 CAN0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS 15:8 TC3 TC2 TC1 TC0 TCC2 TCC1 TCC0 CAN1 23:16 CCL DAC AC SDADC ADC1 ADC0 TC4 31:24 0x20 INTFLAGD 7:0 TC7 TC6 TC5 SERCOM7 SERCOM6 15:8 23:16 31:24 0x24 ... 0x33 Reserved 0x34 STATUSA 7:0 GCLK SUPC OSC32KCTR L OSCCTRL MCLK PM 15:8 TSENS FREQM EIC RTC WDT 23:16 31:24 SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 66

Offset Name Bit Pos. 0x38 STATUSB 7:0 MTB DMAC NVMCTRL DSU PORT 15:8 23:16 31:24 0x3C STATUSC 7:0 CAN0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS 15:8 TC3 TC2 TC1 TC0 TCC2 TCC1 TCC0 CAN1 23:16 CCL DAC AC SDADC ADC1 ADC0 TC4 31:24 0x40 STATUSD 7:0 TC7 TC6 TC5 SERCOM7 SERCOM6 15:8 23:16 31:24

11.7 Register Description

11.7.1 Write Control

Name: WRCTRL Offset: 0x00 Reset: 0x00000000 Property: – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 KEY[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 PERID[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PERID[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 23:16 – KEY[7:0] Peripheral Access Control Key These bits define the peripheral access control key: Value Name Description 0x0 OFF No action 0x1 CLEAR Clear the peripheral write control 0x2 SET Set the peripheral write control 0x3 LOCK Set and lock the peripheral write control until the next hardware reset Bits 15:0 – PERID[15:0] Peripheral Identifier The PERID represents the peripheral whose control is changed using the WRCTRL.KEY. The Peripheral Identifier is calculated following formula: Where BridgeNumber represents the Peripheral Bridge Number (0 for Peripheral Bridge A, 1 for Peripheral Bridge B, etc). N represents the peripheral index from the respective Bridge Number: Table 11-2. PERID Values Periph. Bridge Name BridgeNumber PERID Values A 0 0+N B 1 32+N C 2 64+N SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 68

11.7.2 Event Control

Name: EVCTRL Offset: 0x04 Reset: 0x00 Bit 7 6 5 4 3 2 1 0 ERREO Access RW Reset 0 Bit 0 – ERREO Peripheral Access Error Event Output This bit indicates if the Peripheral Access Error Event Output is enabled or disabled. When enabled, an event will be generated when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set: Value Description 0 Peripheral Access Error Event Output is disabled. 1 Peripheral Access Error Event Output is enabled. SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 70

11.7.3 Interrupt Enable Clear

Name: INTENCLR Offset: 0x08 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 5 4 3 2 1 0 ERR Access RW Reset 0 Bit 0 – ERR Peripheral Access Error Interrupt Disable This bit indicates that the Peripheral Access Error Interrupt is disabled and an interrupt request will be generated when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set: Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Peripheral Access Error interrupt Enable bit and disables the corresponding interrupt request. Value Description 0 Peripheral Access Error interrupt is disabled. 1 Peripheral Access Error interrupt is enabled. SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 71

11.7.4 Interrupt Enable Set

Name: INTENSET Offset: 0x09 Reset: 0x00 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENCLR). Bit 7 6 5 4 3 2 1 0 ERR Access RW Reset 0 Bit 0 – ERR Peripheral Access Error Interrupt Enable This bit indicates that the Peripheral Access Error Interrupt is enabled and an interrupt request will be generated when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set: Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Peripheral Access Error interrupt Enable bit and enables the corresponding interrupt request. Value Description 0 Peripheral Access Error interrupt is disabled. 1 Peripheral Access Error interrupt is enabled. SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 72

11.7.5 AHB Slave Bus Interrupt Flag Status and Clear

Name: INTFLAGAHB Offset: 0x10 Reset: 0x000000 Property: – This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 HPB3 Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 DIVAS LPRAMDMAC HPB2 HPB0 HPB1 HSRAMDSU HSRAMCM0P FLASH Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 8 – HPB3 Interrupt Flag for SLAVE HPB3 Bit 7 – DIVAS Interrupt Flag for SLAVE DIVAS Bit 6 – LPRAMDMAC Interrupt Flag for SLAVE LPRAMDMAC Bit 5 – HPB2 Interrupt Flag for SLAVE HPB2 Bit 4 – HPB0 Interrupt Flag for SLAVE HPB0 Bit 3 – HPB1 Interrupt Flag for SLAVE HPB1 Bit 2 – HSRAMDSU Interrupt Flag for SLAVE HSRAMDSU Bit 1 – HSRAMCM0P Interrupt Flag for SLAVE HSRAMCM0P SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 73

11.7.6 Peripheral Interrupt Flag Status and Clear A

Name: INTFLAGA Offset: 0x14 Reset: 0x000000 Property: – This flag is cleared by writing a one to the flag. This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGA bit, and will generate an interrupt request if INTENCLR/SET.ERR is one. Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding INTFLAGA interrupt flag. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 TSENS FREQM EIC RTC WDT Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GCLK SUPC OSC32KCTRL OSCCTRL RSTC MCLK PM PAC Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 12 – TSENS Interrupt Flag for TSENS Bit 11 – FREQM Interrupt Flag for FREQM Bit 10 – EIC Interrupt Flag for EIC Bit 9 – RTC Interrupt Flag for RTC Bit 8 – WDT Interrupt Flag for WDT Bit 7 – GCLK Interrupt Flag for GCLK Bit 6 – SUPC Interrupt Flag for SUPC Bit 5 – OSC32KCTRL Interrupt Flag for OSC32KCTRL SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 75

Bit 4 – OSCCTRL Interrupt Flag for OSCCTRL Bit 3 – RSTC Interrupt Flag for RSTC Bit 2 – MCLK Interrupt Flag for MCLK Bit 1 – PM Interrupt Flag for PM Bit 0 – PAC Interrupt Flag for PAC SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 76

11.7.7 Peripheral Interrupt Flag Status and Clear B

Name: INTFLAGB Offset: 0x18 Reset: 0x000000 Property: – This flag is cleared by writing a '1' to the flag. This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGB bit, and will generate an interrupt request if INTENCLR/SET.ERR is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGB interrupt flag. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 MTB DMAC NVMCTRL DSU PORT Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 4 – MTB Interrupt Flag for MTB Bit 3 – DMAC Interrupt Flag for DMAC Bit 2 – NVMCTRL Interrupt Flag for NVMCTRL Bit 1 – DSU Interrupt Flag for DSU Bit 0 – PORT Interrupt Flag for PORT SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 77

11.7.8 Peripheral Interrupt Flag Status and Clear C

Name: INTFLAGC Offset: 0x1C Reset: 0x000000 Property: – This flag is cleared by writing a one to the flag. This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGC bit, and will generate an interrupt request if INTENCLR/SET.ERR is one. Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding INTFLAGC interrupt flag. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 CCL DAC AC SDADC ADC1 ADC0 TC4 Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 TC3 TC2 TC1 TC0 TCC2 TCC1 TCC0 CAN1 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CAN0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 – CCL Interrupt Flag for CCL Bit 21 – DAC Interrupt Flag for DAC Bit 20 – AC Interrupt Flag for AC Bit 19 – SDADC Interrupt Flag for SDADC Bits 17, 18 – ADC Interrupt Flag for ADCn [n=1..0] Bits 12, 13, 14, 15, 16 – TC Interrupt Flag for TCn [n = 4..0] Bits 9, 10, 11 – TCC Interrupt Flag for TCCn [n = 2..0] Bits 7, 8 – CAN Interrupt Flag for CAN SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 78

Bits 1, 2, 3, 4, 5, 6 – SERCOM Interrupt Flag for SERCOMn [n = 5..0] Bit 0 – EVSYS Interrupt Flag for EVSYS SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 79

11.7.9 Peripheral Interrupt Flag Status and Clear D

Name: INTFLAGD Offset: 0x20 Reset: 0x000000 Property: – This flag is cleared by writing a one to the flag. This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGD bit, and will generate an interrupt request if INTENCLR/SET.ERR is one. Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding INTFLAGD interrupt flag. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 TC7 TC6 TC5 SERCOM7 SERCOM6 Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bits 2, 3, 4 – TC Interrupt Flag for TCn [n = 7..5] Bits 0, 1 – SERCOM Interrupt Flag for SERCOMn [n = 7..6] SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 80

11.7.10 Peripheral Write Protection Status A

Name: STATUSA Offset: 0x34 Reset: 0x000000 Property: – Writing to this register has no effect. Reading STATUS register returns peripheral write protection status: Value Description 0 Peripheral is not write protected. 1 Peripheral is write protected. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 TSENS FREQM EIC RTC WDT Access R R R R R Reset 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GCLK SUPC OSC32KCTRL OSCCTRL MCLK PM Access R R R R R R Reset 0 0 0 0 0 0 Bit 12 – TSENS Peripheral TSENS Write Protection Status Bit 11 – FREQM Peripheral FREQM Write Protection Status Bit 10 – EIC Peripheral EIC Write Protection Status Bit 9 – RTC Peripheral RTC Write Protection Status Bit 8 – WDT Peripheral WDT Write Protection Status Bit 7 – GCLK Peripheral GCLK Write Protection Status Bit 6 – SUPC Peripheral SUPC Write Protection Status Bit 5 – OSC32KCTRL Peripheral OSC32KCTRL Write Protection Status SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 81

Bit 4 – OSCCTRL Peripheral OSCCTRL Write Protection Status Bit 2 – MCLK Peripheral MCLK Write Protection Status Bit 1 – PM Peripheral PM Write Protection Status SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 82

11.7.11 Peripheral Write Protection Status B

Name: STATUSB Offset: 0x38 Reset: 0x000000 Property: – Writing to this register has no effect. Reading STATUS register returns peripheral write protection status: Value Description 0 Peripheral is not write protected. 1 Peripheral is write protected. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 MTB DMAC NVMCTRL DSU PORT Access R R R R R Reset 0 0 0 0 0 Bit 4 – MTB Peripheral MTB Write Protection Status Bit 3 – DMAC Peripheral DMAC Write Protection Status Bit 2 – NVMCTRL Peripheral NVMCTRL Write Protection Status Bit 1 – DSU Peripheral DSU Write Protection Status Bit 0 – PORT Peripheral PORt Write Protection Status SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 83

11.7.12 Peripheral Write Protection Status C

Name: STATUSC Offset: 0x3C Reset: 0x000000 Property: – Writing to this register has no effect. Reading STATUS register returns peripheral write protection status: Value Description 0 Peripheral is not write protected. 1 Peripheral is write protected. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 CCL DAC AC SDADC ADC1 ADC0 TC4 Access R R R R R R R Reset 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 TC3 TC2 TC1 TC0 TCC2 TCC1 TCC0 CAN1 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CAN0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 – CCL Peripheral CCL Write Protection Status Bit 21 – DAC Peripheral DAC Write Protection Status Bit 20 – AC Peripheral AC Write Protection Status Bit 19 – SDADC Peripheral SDADC Write Protection Status Bits 17, 18 – ADC Peripheral ADCn [n=1..0] Write Protection Status Bits 12, 13, 14, 15, 16 – TC Peripheral TCn Write Protection Status [n = 4..0] Bits 9, 10, 11 – TCC Peripheral TCCn [n = 2..0] Write Protection Status TCCn [n = 2..0] Bits 7, 8 – CAN Peripheral CAN Write Protection Status SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 84

Bits 1, 2, 3, 4, 5, 6 – SERCOM Peripheral SERCOMn Write Protection Status [n = 5..0] Bit 0 – EVSYS Peripheral EVSYS Write Protection Status SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 85

11.7.13 Peripheral Write Protection Status D

Name: STATUSD Offset: 0x40 Reset: 0x000000 Property: – Writing to this register has no effect. Reading STATUS register returns peripheral write protection status: Value Description 0 Peripheral is not write protected. 1 Peripheral is write protected. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 TC7 TC6 TC5 SERCOM7 SERCOM6 Access R R R R R Reset 0 0 0 0 0 Bits 2, 3, 4 – TC Peripheral TCn Write Protection Status [n = 7..5] Bits 0, 1 – SERCOM Peripheral SERCOMn Write Protection Status [n = 7..6] SAM C20/C21 Family Data Sheet PAC - Peripheral Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 86

Peripherals Configuration Summary Table 12-1. Peripherals Configuration Summary SAM C20/C21 E Peripheral Name Base Address IRQ Line AHB Clock APB Clock Generic Clock PAC Events DMA Index Enabled at Reset Index Enabled at Reset Index Index Prot at Reset User Generator Index Sleep Walking AHB-APB Bridge A 0x40000000 0 Y N/A PAC 0x44000000 0 10 Y 0 Y 0 N 85 : ACCERR N/A PM 0x40000400 0 1 Y 1 N N/A MCLK 0x40000800 0 2 Y 2 N Y RSTC 0x40000C00 3 Y 3 N N/A OSCCTRL 0x40001000 0 4 Y 0: FDPLL96M clk source 1: FDPLL96M 32kHz

4 N 0: XOSC_FAIL Y

OSC32KCTRL 0x40001400 0 5 Y 5 N 1: XOSC32K_FAIL Y SUPC 0x40001800 0 6 Y 6 N N/A GCLK 0x40001C00 7 Y 7 N N/A WDT 0x40002000 1 8 Y 8 N Y RTC 0x40002400 2 9 Y 9 N 2: CMP0/ALARM0 3: CMP1 4: OVF 5-12: PER0-7 Y EIC 0x40002800 3, NMI

10 Y 2 10 N 13-28: EXTINT0-15 Y

FREQM 0x40002C00 4 11 Y 3: Measure 4: Reference

11 N N/A

TSENS 0x40003000 5 12 N 5 12 N 0: START 29: WINMON 1: RESRDY A AHB-APB Bridge B 0x41000000 1 Y N/A PORT 0x41000000 0 Y 0 N 1-4 : EV0-3 Y DSU 0x41002000 3 Y 1 Y 1 Y N/A NVMCTRL 0x41004000 6 5 Y 2 Y 39 2 N Y DMAC 0x41006000 7 7 Y 3 N 5-8: CH0-3 30-33: CH0-3 Y MTB 0x41008000 N 44: START 45: STOP N/A AHB-APB Bridge C 0x42000000 2 Y N/A EVSYS 0x42000000 8 0 N 6-17: one per CHANNEL

0 N Y

SERCOM0 0x42000400 9 1 N 19: CORE 18: SLOW

1 N 2: RX

3: TX Y SERCOM1 0x42000800 10 2 N 20: CORE 18: SLOW

2 N 4: RX

5: TX Y SERCOM2 0x42000C00 11 3 N 21: CORE 18: SLOW

3 N 6: RX

7: TX Y SERCOM3 0x42001000 12 4 N 22: CORE 18: SLOW

4 N 8: RX

9: TX Y CAN0 0x42001C00 15 8 N 26 14: DEBUG N/A CAN1 0x42002000 16 9 N 27 15: DEBUG N/A TCC0 0x42002400 17 9 N 28 9 N 9-10: EV0-1 11-14: MC0-3 34: OVF 35: TRG 36: CNT 37-40: MC0-3 16: OVF 17-20: MC0-3 Y SAM C20/C21 Family Data Sheet Peripherals Configuration Summary © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 87

12.1 SAM C20/C21 N

Table 12-2. Peripherals Configuration Summary SAM C21 N Peripheral Name Base Address IRQ Line AHB Clock APB Clock Generic Clock PAC Events DMA Index Enabled at Reset Index Enabled at Reset Index Index Prot at Reset User Generator Index Sleep Walking AHB-APB Bridge A 0x40000000 0 Y N/A PAC 0x40000000 0 10 Y 0 Y 0 N 85 : ACCERR N/A PM 0x40000400 0 1 Y 1 N N/A MCLK 0x40000800 0 2 Y 2 N Y RSTC 0x40000C00 3 Y 3 N N/A OSCCTRL 0x40001000 0 4 Y 0: FDPLL96M clk source 1: FDPLL96M 32kHz OSC32KCTRL 0x40001400 0 5 Y 5 N 1: XOSC32K_FAIL Y SAM C20/C21 Family Data Sheet Peripherals Configuration Summary © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 88

Peripheral Name Base Address IRQ Line AHB Clock APB Clock Generic Clock PAC Events DMA Index Enabled at Reset Index Enabled at Reset Index Index Prot at Reset User Generator Index Sleep Walking SUPC 0x40001800 0 6 Y 6 N N/A GCLK 0x40001C00 7 Y 7 N N/A WDT 0x40002000 1 8 Y 8 N Y RTC 0x40002400 2 9 Y 9 N 2: CMP0/ALARM0 3: CMP1 4: OVF5-1 5:12: PER0-7 Y EIC 0x40002800 3, NMI FREQM 0x40002C00 4 11 Y 3: Measure 4: Reference TSENS 0x40003000 5 12 N 5 12 N 0: START 29: WINMON 1: RESRDY A AHB-APB Bridge B 0x41000000 1 Y N/A PORT 0x41000000 0 Y 0 N 1-4 : EV0-3 Y DSU 0x41002000 3 Y 1 Y 1 Y N/A NVMCTRL 0x41004000 6 5 Y 2 Y 39 2 N Y DMAC 0x41006000 7 7 Y 3 N 5-8: CH0-3 30-33: CH0-3 Y MTB 0x41008000 N 45: START 46: STOP N/A AHB-APB Bridge C 0x42000000 2 Y N/A EVSYS 0x42000000 8 0 N 6-17: one per CHANNEL SERCOM0 0x42000400 9 1 N 19: CORE 18: SLOW 3: TX Y SERCOM1 0x42000800 10 2 N 20: CORE 18: SLOW 5: TX Y SERCOM2 0x42000C00 11 3 N 21: CORE 18: SLOW 7: TX Y SERCOM3 0x42001000 12 4 N 22: CORE 18: SLOW 9: TX Y SERCOM4 0x42001400 13 5 N 23: CORE 18: SLOW

5 N 10: RX

11: TX Y SERCOM5 0x42001800 14 6 N 25: CORE 24: SLOW

6 N 12: RX

13: TX Y CAN0 0x42001C00 15 8 N 26 7 14: DEBUG N/A CAN1 0x42002000 16 9 N 27 8 15: DEBUG N/A TCC0 0x42002400 17 9 N 28 9 N 9-10: EV0-1 11-14: MC0-3 34: OVF 35: TRG 36: CNT 37-40: MC0-3 16: OVF 17-20: MC0-3 Y TCC1 0x42002800 18 10 N 28 10 N 15-16: EV0-1 17-18: MC0-1 41: OVF 42: TRG 43: CNT 44-45: MC0-1 21: OVF 22-23: MC0-1 Y SAM C20/C21 Family Data Sheet Peripherals Configuration Summary © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 89

0 N 49: RX

50: TX Y SERCOM7 0x43000400 10 1 N 42: CORE 18: SLOW

1 N 51: RX

52: TX Y TC5 0x43000800 20 2 N 43 2 N 47: EVU 87: OVF 88-89: MC0-1 53: OVF 54-55: MC0-1 Y TC6 0x43000C00 21 3 N 44 3 N 48:EVU 90: OVF 91-92: MC0-1 56: OVF 57-58: MC0-1 Y TC7 0x43001000 22 4 N 45 4 N 49:EVU 93: OVF 94-95: MC0-1 59: OVF 60-61: MC0-1 Y DIVAS 0x48000000 12 Y N/A SAM C20/C21 Family Data Sheet Peripherals Configuration Summary © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 90

Table 12-3. Peripherals Configuration Summary SAM C20 N Peripheral Name Base Address IRQ Line AHB Clock APB Clock Generic Clock PAC Events DMA Index Enabled at Reset Index Enabled at Reset Index Index Prot at Reset User Generator Index Sleep Walking AHB-APB Bridge A 0x40000000 0 Y N/A PAC 0x40000000 0 10 Y 0 Y 0 N 85 : ACCERR N/A PM 0x40000400 0 1 Y 1 N N/A MCLK 0x40000800 0 2 Y 2 N Y RSTC 0x40000C00 3 Y 3 N N/A OSCCTRL 0x40001000 0 4 Y 0: FDPLL96M clk source 1: FDPLL96M 32kHz OSC32KCTRL 0x40001400 0 5 Y 5 N 1: XOSC32K_FAIL Y SUPC 0x40001800 0 6 Y 6 N N/A GCLK 0x40001C00 7 Y 7 N N/A WDT 0x40002000 1 8 Y 8 N Y RTC 0x40002400 2 9 Y 9 N 2: CMP0/ALARM0 3: CMP1 4: OVF5-1 5:12: PER0-7 Y EIC 0x40002800 3, NMI FREQM 0x40002C00 4 11 Y 3: Measure 4: Reference PORT 0x41000000 0 Y 0 N 1-4 : EV0-3 Y DSU 0x41002000 3 Y 1 Y 1 Y N/A NVMCTRL 0x41004000 6 5 Y 2 Y 39 2 N Y DMAC 0x41006000 7 7 Y 3 N 5-8: CH0-3 30-33: CH0-3 Y MTB 0x41008000 N 45: START 46: STOP N/A AHB-APB Bridge C 0x42000000 2 Y N/A EVSYS 0x42000000 8 0 N 6-17: one per CHANNEL SERCOM0 0x42000400 9 1 N 19: CORE 18: SLOW 3: TX Y SERCOM1 0x42000800 10 2 N 20: CORE 18: SLOW 5: TX Y SERCOM2 0x42000C00 11 3 N 21: CORE 18: SLOW 7: TX Y SERCOM3 0x42001000 12 4 N 22: CORE 18: SLOW 9: TX Y SERCOM4 0x42001400 13 5 N 23: CORE 18: SLOW 11: TX Y SERCOM5 0x42001800 14 6 N 25: CORE 24: SLOW 13: TX Y SAM C20/C21 Family Data Sheet Peripherals Configuration Summary © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 91

Peripheral Name Base Address IRQ Line AHB Clock APB Clock Generic Clock PAC Events DMA Index Enabled at Reset Index Enabled at Reset Index Index Prot at Reset User Generator Index Sleep Walking TCC0 0x42002400 17 9 N 28 9 N 9-10: EV0-1 11-14: MC0-3 34: OVF 35: TRG 36: CNT 37-40: MC0-3 16: OVF 17-20: MC0-3 Y TCC1 0x42002800 18 10 N 28 10 N 15-16: EV0-1 17-18: MC0-1 41: OVF 42: TRG 43: CNT 44-45: MC0-1 21: OVF 22-23: MC0-1 Y TCC2 0x42002C00 19 11 N 29 11 N 19-20: EV0-1 21-22: MC0-1 46: OVF 47: TRG 48: CNT 49-50: MC0-1 24: OVF 25-26: MC0-1 Y TC0 0x42003000 20 12 N 30 12 N 23: EVU 51: OVF 52-53: MC0-1 27: OVF 28-29: MC0-1 Y TC1 0x42003400 21 13 N 30 13 N 24: EVU 54: OVF 55-56: MC0-1 30: OVF 31-32: MC0-1 Y TC2 0x42003800 22 14 N 31 14 N 25: EVU 57: OVF 58-59: MC0-1 33: OVF 34-35: MC0-1 Y TC3 0x42003C00 23 15 N 31 15 N 26: EVU 60: OVF 61-62: MC0-1 36: OVF 37-38: MC0-1 Y TC4 0x42004000 24 16 N 32 16 N 27: EVU 63: OVF 64-65: MC0-1 39: OVF 40-41: MC0-1 Y ADC0 0x42004400 25 17 N 33 17 N 28: START 29: SYNC 66: RESRDY 67: WINMON 42: RESRDY Y AC 0x42005000 27 20 N 40 20 N 34-37: SOC0-3 72-75: COMP0-3 76-77: WIN0-1 Y PTC 0x42005800 30 22 N 37 22 N 39: STCONV 79: EOC 80: WCOMP EOC: 46 WCOMP: 47 SEQ: 48 CCL 0x42005C00 23 N 38 23 N 40-43 : LUTIN0-3 81-84: LUTOUT0-3 Y AHB-APB Bridge D 0x43000000 13 Y 0 N/A SERCOM6 0x43000000 9 0 N 41: CORE 18: SLOW 50: TX Y SERCOM7 0x43000400 10 1 N 42: CORE 18: SLOW 52: TX Y TC5 0x43000800 20 2 N 43 2 N 47: EVU 87: OVF 88-89: MC0-1 53: OVF 54-55: MC0-1 Y TC6 0x43000C00 21 3 N 44 3 N 48:EVU 90: OVF 91-92: MC0-1 56: OVF 57-58: MC0-1 Y TC7 0x43001000 22 4 N 45 4 N 49:EVU 93: OVF 94-95: MC0-1 59: OVF 60-61: MC0-1 Y DIVAS 0x48000000 12 Y N/A SAM C20/C21 Family Data Sheet Peripherals Configuration Summary © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 92

12.2 SAM C20/C21 E/G/J

Table 12-4. Peripherals Configuration Summary SAM C21 E/G/J Peripheral Name Base Address IRQ Line AHB Clock APB Clock Generic Clock PAC Events DMA Index Enabled at Reset Index Enabled at Reset Index Index Prot at Reset User Generator Index Sleep Walking AHB-APB Bridge A 0x40000000 0 Y N/A PAC 0x44000000 0 10 Y 0 Y 0 N 85 : ACCERR N/A PM 0x40000400 0 1 Y 1 N N/A MCLK 0x40000800 0 2 Y 2 N Y RSTC 0x40000C00 3 Y 3 N N/A OSCCTRL 0x40001000 0 4 Y 0: FDPLL96M clk source 1: FDPLL96M 32kHz OSC32KCTRL 0x40001400 0 5 Y 5 N 1: XOSC32K_FAIL Y SUPC 0x40001800 0 6 Y 6 N N/A GCLK 0x40001C00 7 Y 7 N N/A WDT 0x40002000 1 8 Y 8 N Y RTC 0x40002400 2 9 Y 9 N 2: CMP0/ALARM0 3: CMP1 4: OVF 5-12: PER0-7 Y EIC 0x40002800 3, NMI FREQM 0x40002C00 4 11 Y 3: Measure 4: Reference TSENS 0x40003000 5 12 N 5 12 N 0: START 29: WINMON 1: RESRDY A AHB-APB Bridge B 0x41000000 1 Y N/A PORT 0x41000000 0 Y 0 N 1-4 : EV0-3 Y DSU 0x41002000 3 Y 1 Y 1 Y N/A NVMCTRL 0x41004000 6 5 Y 2 Y 39 2 N Y DMAC 0x41006000 7 7 Y 3 N 5-8: CH0-3 30-33: CH0-3 Y MTB 0x41008000 N 44: START 45: STOP N/A AHB-APB Bridge C 0x42000000 2 Y N/A EVSYS 0x42000000 8 0 N 6-17: one per CHANNEL SERCOM0 0x42000400 9 1 N 19: CORE 18: SLOW 3: TX Y SERCOM1 0x42000800 10 2 N 20: CORE 18: SLOW 5: TX Y SERCOM2 0x42000C00 11 3 N 21: CORE 18: SLOW 7: TX Y SERCOM3 0x42001000 12 4 N 22: CORE 18: SLOW 9: TX Y SERCOM4 0x42001400 13 5 N 23: CORE 18: SLOW 11: TX Y SERCOM5 0x42001800 14 6 N 25: CORE 24: SLOW 13: TX Y CAN0 0x42001C00 15 8 N 26 14: DEBUG N/A CAN1 0x42002000 16 9 N 27 15: DEBUG N/A SAM C20/C21 Family Data Sheet Peripherals Configuration Summary © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 93

Peripheral Name Base Address IRQ Line AHB Clock APB Clock Generic Clock PAC Events DMA Index Enabled at Reset Index Enabled at Reset Index Index Prot at Reset User Generator Index Sleep Walking TCC0 0x42002400 17 9 N 28 9 N 9-10: EV0-1 11-14: MC0-3 34: OVF 35: TRG 36: CNT 37-40: MC0-3 16: OVF 17-20: MC0-3 Y TCC1 0x42002800 18 10 N 28 10 N 15-16: EV0-1 17-18: MC0-1 41: OVF 42: TRG 43: CNT 44-45: MC0-1 21: OVF 22-23: MC0-1 Y TCC2 0x42002C00 19 11 N 29 11 N 19-20: EV0-1 21-22: MC0-1 46: OVF 47: TRG 48: CNT 49-50: MC0-1 24: OVF 25-26: MC0-1 Y TC0 0x42003000 20 12 N 30 12 N 23: EVU 51: OVF 52-53: MC0-1 27: OVF 28-29: MC0-1 Y TC1 0x42003400 21 13 N 30 13 N 24: EVU 54: OVF 55-56: MC0-1 30: OVF 21-32: MC0-1 Y TC2 0x42003800 22 14 N 31 14 N 25: EVU 57: OVF 58-59: MC0-1 33: OVF 23-35: MC0-1 Y TC3 0x42003C00 23 15 N 31 15 N 26: EVU 60: OVF 61-62: MC0-1 36: OVF 37-38: MC0-1 Y TC4 0x42004000 24 16 N 32 16 N 27: EVU 63: OVF 64-65: MC0-1 39: OVF 40-41: MC0-1 Y ADC0 0x42004400 25 17 N 33 17 N 28: START 29: SYNC 66: RESRDY 67: WINMON 42: RESRDY Y ADC1 0x42004800 26 18 N 34 18 N 30: START 31: SYNC 68: RESRDY 69: WINMON 43: RESRDY Y SDADC 0x42004C00 29 19 N 35 19 N 32: START 33: FLUSH 70: RESRDY 71: WINMON 44: RESRDY Y AC 0x42005000 27 20 N 34 20 N 34-37: SOC0-3 72-75: COMP0-3 76-77: WIN0-1 Y DAC 0x42005400 28 21 N 36 21 N 38: START 78: EMPTY 45: EMPTY Y PTC 0x42005800 30 22 N 37 22 N 39: STCONV 79: EOC 80: WCOMP EOC: 46 WCOMP: 47 SEQ: 48 CCL 0x42005C00 23 N 38 23 N 40-43 : LUTIN0-3 781-84: LUTOUT0-3 Y DIVAS 0x48000000 12 Y N/A Table 12-5. Peripherals Configuration Summary SAM C20 E/G/J Peripheral Name Base Address IRQ Line AHB Clock APB Clock Generic Clock PAC Events DMA Index Enabled at Reset Index Enabled at Reset Index Index Prot at Reset User Generator Index Sleep Walking AHB-APB Bridge A 0x40000000 0 Y N/A PAC 0x44000000 0 10 Y 0 Y 0 N 85 : ACCERR N/A PM 0x40000400 0 1 Y 1 N N/A MCLK 0x40000800 0 2 Y 2 N Y RSTC 0x40000C00 3 Y 3 N N/A OSCCTRL 0x40001000 0 4 Y 0: FDPLL96M clk source 1: FDPLL96M 32kHz SAM C20/C21 Family Data Sheet Peripherals Configuration Summary © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 94

Peripheral Name Base Address IRQ Line AHB Clock APB Clock Generic Clock PAC Events DMA Index Enabled at Reset Index Enabled at Reset Index Index Prot at Reset User Generator Index Sleep Walking OSC32KCTRL 0x40001400 0 5 Y 5 N 1: XOSC32K_FAIL Y SUPC 0x40001800 0 6 Y 6 N N/A GCLK 0x40001C00 7 Y 7 N N/A WDT 0x40002000 1 8 Y 8 N Y RTC 0x40002400 2 9 Y 9 N 2: CMP0/ALARM0 3: CMP1 4: OVF 5-12: PER0-7 Y EIC 0x40002800 3, NMI FREQM 0x40002C00 4 11 Y 3: Measure 4: Reference PORT 0x41000000 0 Y 0 N 1-4 : EV0-3 Y DSU 0x41002000 3 Y 1 Y 1 Y N/A NVMCTRL 0x41004000 6 5 Y 2 Y 39 2 N Y DMAC 0x41006000 7 7 Y 3 N 5-8: CH0-3 30-33: CH0-3 Y MTB 0x41008000 N 44: START 45: STOP N/A AHB-APB Bridge C 0x42000000 2 Y N/A EVSYS 0x42000000 8 0 N 6-17: one per CHANNEL SERCOM0 0x42000400 9 1 N 19: CORE 18: SLOW 3: TX Y SERCOM1 0x42000800 10 2 N 20: CORE 18: SLOW 5: TX Y SERCOM2 0x42000C00 11 3 N 21: CORE 18: SLOW 7: TX Y SERCOM3 0x42001000 12 4 N 22: CORE 18: SLOW 9: TX Y SERCOM4 0x42001400 13 5 N 23: CORE 18: SLOW 11: TX Y SERCOM5 0x42001800 14 6 N 25: CORE 24: SLOW 13: TX Y TCC0 0x42002400 17 9 N 28 9 N 9-10: EV0-1 11-14: MC0-3 34: OVF 35: TRG 36: CNT 37-40: MC0-3 16: OVF 17-20: MC0-3 Y TCC1 0x42002800 18 10 N 28 10 N 15-16: EV0-1 17-18: MC0-1 41: OVF 42: TRG 43: CNT 44-45: MC0-1 21: OVF 22-23: MC0-1 Y TCC2 0x42002C00 19 11 N 29 11 N 19-20: EV0-1 21-22: MC0-1 46: OVF 47: TRG 48: CNT 49-50: MC0-1 24: OVF 25-26: MC0-1 Y TC0 0x42003000 20 12 N 30 12 N 23: EVU 51: OVF 52-53: MC0-1 27: OVF 28-29: MC0-1 Y TC1 0x42003400 21 13 N 30 13 N 24: EVU 54: OVF 55-56: MC0-1 30: OVF 21-32: MC0-1 Y SAM C20/C21 Family Data Sheet Peripherals Configuration Summary © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 95

Peripheral Name Base Address IRQ Line AHB Clock APB Clock Generic Clock PAC Events DMA Index Enabled at Reset Index Enabled at Reset Index Index Prot at Reset User Generator Index Sleep Walking TC2 0x42003800 22 14 N 31 14 N 25: EVU 57: OVF 58-59: MC0-1 33: OVF 23-35: MC0-1 Y TC3 0x42003C00 23 15 N 31 15 N 26: EVU 60: OVF 61-62: MC0-1 36: OVF 37-38: MC0-1 Y TC4 0x42004000 24 16 N 32 16 N 27: EVU 63: OVF 64-65: MC0-1 39: OVF 40-41: MC0-1 Y ADC0 0x42004400 25 17 N 33 17 N 28: START 29: SYNC 66: RESRDY 67: WINMON 42: RESRDY Y AC 0x42005000 27 20 N 34 20 N 34-37: SOC0-3 72-75: COMP0-3 76-77: WIN0-1 Y PTC 0x42005800 30 22 N 37 22 N 39: STCONV 79: EOC 80: WCOMP EOC: 46 WCOMP: 47 SEQ: 48 CCL 0x42005C00 23 N 38 23 N 40-43 : LUTIN0-3 781-84: LUTOUT0-3 Y DIVAS 0x48000000 12 Y N/A SAM C20/C21 Family Data Sheet Peripherals Configuration Summary © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 96

DSU - Device Service Unit

13.1 Overview

The Device Service Unit (DSU) provides a means of detecting debugger probes. It enables the ARM Debug Access Port (DAP) to have control over multiplexed debug pads and CPU reset. The DSU also provides system-level services to debug adapters in an ARM debug system. It implements a CoreSight Debug ROM that provides device identification as well as identification of other debug components within the system. Hence, it complies with the ARM Peripheral Identification specification. The DSU also provides system services to applications that need memory testing, as required for IEC60730 Class B compliance, for example. The DSU can be accessed simultaneously by a debugger and the CPU, as it is connected on the High-Speed Bus Matrix. For security reasons, some of the DSU features will be limited or unavailable when the device is protected by the NVMCTRL security bit. Related Links

13.11.6 System Services Availability when Accessed Externally and Device is Protected

NVMCTRL – Nonvolatile Memory Controller

27.6.6 Security Bit

13.2 Features

CPU reset extension
Debugger probe detection (Cold- and Hot-Plugging)
Chip-Erase command and status
32-bit cyclic redundancy check (CRC32) of any memory accessible through the bus matrix
ARM CoreSight compliant device identification
Two debug communications channels with DMA connection
Debug access port security filter
Onboard memory built-in self-test (MBIST) SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 97

13.3 Block Diagram

Figure 13-1. DSU Block Diagram DSU SWCLK CORESIGHT ROM DAP SECURITY FILTER CRC-32 MBIST CHIP ERASE RESET cpu_reset_extension CPUDAP SWDIO NVMCTRL DBG M HIGH-SPEED BUS MATRIXM S debugger_present DEBUGGER PROBE INTERFACE AHB-AP DMA S DMA request PORT

13.4 Signal Description

The DSU uses three signals to function. Signal Name Type Description RESET Digital Input External reset SWCLK Digital Input SW clock SWDIO Digital I/O SW bidirectional data pin Related Links 6. I/O Multiplexing and Considerations

13.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

13.5.1 I/O Lines

The SWCLK pin is by default assigned to the DSU module to allow debugger probe detection and to stretch the CPU reset phase. For more information, refer to 13.6.3 Debugger Probe Detection. The Hot- Plugging feature depends on the PORT configuration. If the SWCLK pin function is changed in the PORT or if the PORT_MUX is disabled, the Hot-Plugging feature is disabled until a power-reset or an external reset is performed.

13.5.2 Power Management

PM – Power Manager

13.5.3 Clocks

The DSU bus clocks (CLK_DSU_APB and CLK_DSU_AHB) can be enabled and disabled by the Main Clock Controller. Related Links 19. PM – Power Manager 17. MCLK – Main Clock

13.5.4 DMA

The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with this peripheral the DMAC must be configured first. Refer to DMAC – Direct Memory Access Controller for details.

13.5.5 Interrupts

Not applicable.

13.5.6 Events

Not applicable.

13.5.7 Register Access Protection

Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following:

Debug Communication Channel 0 register (DCC0)
Debug Communication Channel 1 register (DCC1) Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. Write-protection does not apply for accesses through an external debugger. Related Links 11. PAC - Peripheral Access Controller

13.5.8 Analog Connections

Not applicable.

13.6 Debug Operation

13.6.1 Principle of Operation

The DSU provides basic services to allow on-chip debug using the ARM Debug Access Port and the ARM processor debug resources:

CPU reset extension
Debugger probe detection For more details on the ARM debug components, refer to the ARM Debug Interface v5 Architecture Specification. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 99

13.6.2 CPU Reset Extension

“CPU reset extension” refers to the extension of the reset phase of the CPU core after the external reset is released. This ensures that the CPU is not executing code at startup while a debugger is connects to the system. The debugger is detected on a RESET release event when SWCLK is low. At startup, SWCLK is internally pulled up to avoid false detection of a debugger if the SWCLK pin is left unconnected. When the CPU is held in the reset extension phase, the CPU Reset Extension bit of the Status A register (STATUSA.CRSTEXT) is set. To release the CPU, write a '1' to STATUSA.CRSTEXT. STATUSA.CRSTEXT will then be set to '0'. Writing a '0' to STATUSA.CRSTEXT has no effect. For security reasons, it is not possible to release the CPU reset extension when the device is protected by the NVMCTRL security bit. Trying to do so sets the Protection Error bit (PERR) of the Status A register (STATUSA.PERR). Figure 13-2. Typical CPU Reset Extension Set and Clear Timing Diagram DSU CRSTEXT Clear SWCLK CPU reset extension CPU_STATE reset running RESET Related Links 27. NVMCTRL – Nonvolatile Memory Controller

13.6.3 Debugger Probe Detection

13.6.3.1 Cold Plugging

Cold-Plugging is the detection of a debugger when the system is in reset. Cold-Plugging is detected when the CPU reset extension is requested, as described above.

13.6.3.2 Hot Plugging

Hot-Plugging is the detection of a debugger probe when the system is not in reset. Hot-Plugging is not possible under reset because the detector is reset when POR or RESET are asserted. Hot-Plugging is active when a SWCLK falling edge is detected. The SWCLK pad is multiplexed with other functions and the user must ensure that its default function is assigned to the debug system. If the SWCLK function is changed, the Hot-Plugging feature is disabled until a power-reset or external reset occurs. Availability of the Hot-Plugging feature can be read from the Hot-Plugging Enable bit of the Status B register (STATUSB.HPE). SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 100

Figure 13-3. Hot-Plugging Detection Timing Diagram SWCLK Hot-Plugging CPU_STATE reset running RESET The presence of a debugger probe is detected when either Hot-Plugging or Cold-Plugging is detected. Once detected, the Debugger Present bit of the Status B register (STATUSB.DBGPRES) is set. For security reasons, Hot-Plugging is not available when the device is protected by the NVMCTRL security bit. This detection requires that pads are correctly powered. Thus, at cold startup, this detection cannot be done until POR is released. If the device is protected, Cold-Plugging is the only way to detect a debugger probe, and so the external reset timing must be longer than the POR timing. If external reset is deasserted before POR release, the user must retry the procedure above until it gets connected to the device. Related Links 27. NVMCTRL – Nonvolatile Memory Controller

13.7 Chip Erase

Chip-Erase consists of removing all sensitive information stored in the chip and clearing the NVMCTRL security bit. Therefore, all volatile memories and the Flash memory (including the EEPROM emulation area) will be erased. The Flash auxiliary rows, including the user row, will not be erased. When the device is protected, the debugger must first reset the device in order to be detected. This ensures that internal registers are reset after the protected state is removed. The Chip-Erase operation is triggered by writing a '1' to the Chip-Erase bit in the Control register (CTRL.CE). This command will be discarded if the DSU is protected by the Peripheral Access Controller (PAC). Once issued, the module clears volatile memories prior to erasing the Flash array. To ensure that the Chip-Erase operation is completed, check the Done bit of the Status A register (STATUSA.DONE). The Chip-Erase operation depends on clocks and power management features that can be altered by the CPU. For that reason, it is recommended to issue a Chip- Erase after a Cold-Plugging procedure to ensure that the device is in a known and safe state. The recommended sequence is as follows: 1. Issue the Cold-Plugging procedure (refer to 13.6.3.1 Cold Plugging). The device then: 1.1. Detects the debugger probe. 1.2. Holds the CPU in reset. 2. Issue the Chip-Erase command by writing a '1' to CTRL.CE. The device then: 2.1. Clears the system volatile memories. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 101

2.2. Erases the whole Flash array (including the EEPROM emulation area, not including auxiliary rows). 2.3. Erases the lock row, removing the NVMCTRL security bit protection. 3. Check for completion by polling STATUSA.DONE (read as '1' when completed). 4. Reset the device to let the NVMCTRL update the fuses.

13.8 Programming

Programming the Flash or RAM memories is only possible when the device is not protected by the NVMCTRL security bit. The programming procedure is as follows: 1. At power up, RESET is driven low by a debugger. The on-chip regulator holds the system in a POR state until the input supply is above the POR threshold (refer to Powe-On Reset (POR) characteristics). The system continues to be held in this static state until the internally regulated supplies have reached a safe operating state. 2. The PM starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash Clock and any Bus Clocks that do not have clock gate control). Internal resets are maintained due to the external reset. 3. The debugger maintains a low level on SWCLK. RESET is released, resulting in a debugger Cold- Plugging procedure. 4. The debugger generates a clock signal on the SWCLK pin, the Debug Access Port (DAP) receives a clock. 5. The CPU remains in Reset due to the Cold-Plugging procedure; meanwhile, the rest of the system is released. 6. A Chip-Erase is issued to ensure that the Flash is fully erased prior to programming. 7. Programming is available through the AHB-AP. 8. After the operation is completed, the chip can be restarted either by asserting RESET or toggling power. Make sure that the SWCLK pin is high when releasing RESET to prevent extending the CPU reset. Related Links 45. Electrical Characteristics 85°C (SAM C20/C21 E/G/J) 27. NVMCTRL – Nonvolatile Memory Controller

13.9 Intellectual Property Protection

Intellectual property protection consists of restricting access to internal memories from external tools when the device is protected, and this is accomplished by setting the NVMCTRL security bit. This protected state can be removed by issuing a Chip-Erase (refer to 13.7 Chip Erase). When the device is protected, read/write accesses using the AHB-AP are limited to the DSU address range and DSU commands are restricted. When issuing a Chip-Erase, sensitive information is erased from volatile memory and Flash. The DSU implements a security filter that monitors the AHB transactions inside the DAP. If the device is protected, then AHB-AP read/write accesses outside the DSU external address range are discarded, causing an error response that sets the ARM AHB-AP sticky error bits (refer to the ARM Debug Interface v5 Architecture Specification on http://www.arm.com). The DSU is intended to be accessed either: SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 102

Internally from the CPU, without any limitation, even when the device is protected
Externally from a debug adapter, with some restrictions when the device is protected For security reasons, DSU features have limitations when used from a debug adapter. To differentiate external accesses from internal ones, the first 0x100 bytes of the DSU register map has been mirrored at offset 0x100:
The first 0x100 bytes form the internal address range
The next 0x100 bytes form the external address range When the device is protected, the DAP can only issue MEM-AP accesses in the DSU range 0x0100-0x2000. The DSU operating registers are located in the 0x0000-0x00FF area and remapped in 0x0100-0x01FF to differentiate accesses coming from a debugger and the CPU. If the device is protected and an access is issued in the region 0x0100-0x01FF, it is subject to security restrictions. For more information, refer to the Table 13-1. Figure 13-4. APB Memory Mapping 0x0000 0x00FF 0x0100 0x01FF 0x1000 0x1FFF DSU operating registers Mirrored DSU operating registers DSU CoreSight ROM Empty Internal address range (cannot be accessed from debug tools when the device is protected by the NVMCTRL security bit) External address range (can be accessed from debug tools with some restrictions) Some features not activated by APB transactions are not available when the device is protected: Table 13-1. Feature Availability Under Protection Features Availability when the device is protected CPU Reset Extension Yes Clear CPU Reset Extension No Debugger Cold-Plugging Yes Debugger Hot-Plugging No Related Links SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 103

NVMCTRL – Nonvolatile Memory Controller

13.10 Device Identification

Device identification relies on the ARM CoreSight component identification scheme, which allows the chip to be identified as a SAM device implementing a DSU. The DSU contains identification registers to differentiate the device.

13.10.1 CoreSight Identification

A system-level ARM® CoreSight™ ROM table is present in the device to identify the vendor and the chip identification method. Its address is provided in the MEM-AP BASE register inside the ARM Debug Access Port. The CoreSight ROM implements a 64-bit conceptual ID composed as follows from the PID0 to PID7 CoreSight ROM Table registers: Figure 13-5. Conceptual 64-bit Peripheral ID Table 13-2. Conceptual 64-Bit Peripheral ID Bit Descriptions Field Size Description Location JEP-106 CC code 4 Continuation code: 0x0 PID4 JEP-106 ID code 7 Device ID: 0x1F PID1+PID2 4KB count 4 Indicates that the CoreSight component is a ROM: 0x0 PID4 RevAnd 4 Not used; read as 0 PID3 CUSMOD 4 Not used; read as 0 PID3 PARTNUM 12 Contains 0xCD0 to indicate that DSU is present PID0+PID1 REVISION 4 DSU revision (starts at 0x0 and increments by 1 at both major and minor revisions). Identifies DSU identification method variants. If 0x0, this indicates that device identification can be completed by reading the Device Identification register (DID) PID2 For more information, refer to the ARM Debug Interface Version 5 Architecture Specification.

13.10.2 Chip Identification Method

The DSU DID register identifies the device by implementing the following information:

Processor identification
Product family identification SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 104

Product series identification
Device select

13.11 Functional Description

13.11.1 Principle of Operation

The DSU provides memory services, such as CRC32 or MBIST that require almost the same interface. Hence, the Address, Length and Data registers (ADDR, LENGTH, DATA) are shared. These shared registers must be configured first; then a command can be issued by writing the Control register. When a command is ongoing, other commands are discarded until the current operation is completed. Hence, the user must wait for the STATUSA.DONE bit to be set prior to issuing another one.

13.11.2 Basic Operation

13.11.2.1 Initialization

The module is enabled by enabling its clocks. For more details, refer to 13.5.3 Clocks. The DSU registers can be PAC write-protected. Related Links 11. PAC - Peripheral Access Controller

13.11.2.2 Operation From a Debug Adapter

Debug adapters should access the DSU registers in the external address range 0x100 – 0x2000. If the device is protected by the NVMCTRL security bit, accessing the first 0x100 bytes causes the system to return an error. Refer to 13.9 Intellectual Property Protection. Related Links 27. NVMCTRL – Nonvolatile Memory Controller

13.11.2.3 Operation From the CPU

There are no restrictions when accessing DSU registers from the CPU. However, the user should access DSU registers in the internal address range (0x0 – 0x100) to avoid external security restrictions. Refer to 13.9 Intellectual Property Protection. 13.11.3 32-bit Cyclic Redundancy Check CRC32 The DSU unit provides support for calculating a cyclic redundancy check (CRC32) value for a memory area (including Flash and AHB RAM). When the CRC32 command is issued from:

The internal range, the CRC32 can be operated at any memory location
The external range, the CRC32 operation is restricted; DATA, ADDR, and LENGTH values are forced (see below) Table 13-3. AMOD Bit Descriptions when Operating CRC32 AMOD[1:0] Short name External range restrictions

0 ARRAY CRC32 is restricted to the full Flash array area (EEPROM emulation area not

AMOD[1:0] Short name External range restrictions

1 EEPROM CRC32 of the whole EEPROM emulation area DATA forced to 0xFFFFFFFF

before calculation (no seed) 2-3 Reserved The algorithm employed is the industry standard CRC32 algorithm using the generator polynomial 0xEDB88320 (reversed representation).

13.11.3.1 Starting CRC32 Calculation

CRC32 calculation for a memory range is started after writing the start address into the Address register (ADDR) and the size of the memory range into the Length register (LENGTH). Both must be word- aligned. The initial value used for the CRC32 calculation must be written to the Data register (DATA). This value will usually be 0xFFFFFFFF, but can be, for example, the result of a previous CRC32 calculation if generating a common CRC32 of separate memory blocks. Once completed, the calculated CRC32 value can be read out of the Data register. The read value must be complemented to match standard CRC32 implementations or kept non-inverted if used as starting point for subsequent CRC32 calculations. The actual test is started by writing a '1' in the 32-bit Cyclic Redundancy Check bit of the Control register (CTRL.CRC). A running CRC32 operation can be canceled by resetting the module (writing '1' to CTRL.SWRST). Related Links 27. NVMCTRL – Nonvolatile Memory Controller

13.11.3.2 Interpreting the Results

The user should monitor the Status A register. When the operation is completed, STATUSA.DONE is set. Then the Bus Error bit of the Status A register (STATUSA.BERR) must be read to ensure that no bus error occurred.

13.11.4 Debug Communication Channels

The Debug Communication Channels (DCCO and DCC1) consist of a pair of registers with associated handshake logic, accessible by both CPU and debugger even if the device is protected by the NVMCTRL security bit. The registers can be used to exchange data between the CPU and the debugger, during run time as well as in debug mode. This enables the user to build a custom debug protocol using only these registers. The DCC0 and DCC1 registers are accessible when the protected state is active. When the device is protected, however, it is not possible to connect a debugger while the CPU is running (STATUSA.CRSTEXT is not writable and the CPU is held under Reset). Two Debug Communication Channel status bits in the Status B registers (STATUS.DCCDx) indicate whether a new value has been written in DCC0 or DCC1. These bits, DCC0D and DCC1D, are located in the STATUSB registers. They are automatically set on write and cleared on read. Note: The DCC0 and DCC1 registers are shared with the on-board memory testing logic (MBIST). Accordingly, DCC0 and DCC1 must not be used while performing MBIST operations. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 106

NVMCTRL – Nonvolatile Memory Controller

13.11.5 Testing of On-Board Memories MBIST

The DSU implements a feature for automatic testing of memory, also known as MBIST (memory built-in self test). This is primarily intended for production test of on-board memories. MBIST cannot be operated from the external address range when the device is protected by the NVMCTRL security bit. If an MBIST command is issued when the device is protected, a protection error is reported in the Protection Error bit in the Status A register (STATUSA.PERR). 1. Algorithm The algorithm used for testing is a type of March algorithm called "March LR". This algorithm is able to detect a wide range of memory defects, while still keeping a linear run time. The algorithm is: 1.1. Write entire memory to '0', in any order. 1.2. Bit by bit read '0', write '1', in descending order. 1.3. Bit by bit read '1', write '0', read '0', write '1', in ascending order. 1.4. Bit by bit read '1', write '0', in ascending order. 1.5. Bit by bit read '0', write '1', read '1', write '0', in ascending order. 1.6. Read '0' from entire memory, in ascending order. The specific implementation used as a run time which depends on the CPU clock frequency and the number of bytes tested in the RAM. The detected faults are: – Address decoder faults – Stuck-at faults – Transition faults – Coupling faults – Linked Coupling faults 2. Starting MBIST To test a memory, you need to write the start address of the memory to the ADDR.ADDR bit field, and the size of the memory into the Length register. For best test coverage, an entire physical memory block should be tested at once. It is possible to test only a subset of a memory, but the test coverage will then be somewhat lower. The actual test is started by writing a '1' to CTRL.MBIST. A running MBIST operation can be canceled by writing a '1' to CTRL.SWRST. 3. Interpreting the Results The tester should monitor the STATUSA register. When the operation is completed, STATUSA.DONE is set. There are two different modes: – ADDR.AMOD=0: exit-on-error (default) In this mode, the algorithm terminates either when a fault is detected or on successful completion. In both cases, STATUSA.DONE is set. If an error was detected, STATUSA.FAIL will be set. User then can read the DATA and ADDR registers to locate the fault. – ADDR.AMOD=1: pause-on-error In this mode, the MBIST algorithm is paused when an error is detected. In such a situation, only STATUSA.FAIL is asserted. The state machine waits for user to clear STATUSA.FAIL by SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 107

writing a '1' in STATUSA.FAIL to resume. Prior to resuming, user can read the DATA and ADDR registers to locate the fault. 4. Locating Faults If the test stops with STATUSA.FAIL set, one or more bits failed the test. The test stops at the first detected error. The position of the failing bit can be found by reading the following registers: – ADDR: Address of the word containing the failing bit – DATA: contains data to identify which bit failed, and during which phase of the test it failed. The DATA register will in this case contains the following bit groups: Figure 13-6. DATA bits Description When MBIST Operation Returns an Error Bit Bit Bit Bit phase bit_index 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

bit_index: contains the bit number of the failing bit
phase: indicates which phase of the test failed and the cause of the error, as listed in the following table. Table 13-4. MBIST Operation Phases Phase Test actions 0 Write all bits to zero. This phase cannot fail.

1 Read '0', write '1', increment address

2 Read '1', write '0'

3 Read '0', write '1', decrement address

4 Read '1', write '0', decrement address

5 Read '0', write '1'

6 Read '1', write '0', decrement address

7 Read all zeros. bit_index is not used Table 13-5. AMOD Bit Descriptions for MBIST AMOD[1:0] Description 0x0 Exit on Error 0x1 Pause on Error SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 108

AMOD[1:0] Description 0x2, 0x3 Reserved Related Links 27. NVMCTRL – Nonvolatile Memory Controller

Product Mapping

External access: Access performed in the DSU address offset 0x200-0x1FFF range. Internal access: Access performed in the DSU address offset 0x000-0x100 range. Table 13-6. Available Features when Operated From The External Address Range and Device is Protected Features Availability From The External Address Range and Device is Protected Chip-Erase command and status Yes CRC32 Yes, only full array or full EEPROM CoreSight Compliant Device identification Yes Debug communication channels Yes Testing of onboard memories (MBIST) No STATUSA.CRSTEXT clearing No (STATUSA.PERR is set when attempting to do so) SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 109

13.12 Register Summary

Offset Name Bit Pos. 0x00 CTRL 7:0 CE MBIST CRC SWRST 0x01 STATUSA 7:0 PERR FAIL BERR CRSTEXT DONE 0x02 STATUSB 7:0 HPE DCCD1 DCCD0 DBGPRES PROT 0x03 Reserved 0x04 ADDR 7:0 ADDR[5:0] AMOD[1:0] 15:8 ADDR[13:6] 23:16 ADDR[21:14] 31:24 ADDR[29:22] 0x08 LENGTH 7:0 LENGTH[5:0] 15:8 LENGTH[13:6] 23:16 LENGTH[21:14] 31:24 LENGTH[29:22] 0x0C DATA 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] 0x10 DCC0 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] 0x14 DCC1 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] 0x18 DID 7:0 DEVSEL[7:0] 15:8 DIE[3:0] REVISION[3:0] 23:16 FAMILY[0:0] SERIES[5:0] 31:24 PROCESSOR[3:0] FAMILY[4:1] 0x1C ... 0x0FFF Reserved 0x1000 ENTRY0 7:0 FMT EPRES 15:8 ADDOFF[3:0] 23:16 ADDOFF[11:4] 31:24 ADDOFF[19:12] 0x1004 ENTRY1 7:0 FMT EPRES 15:8 ADDOFF[3:0] 23:16 ADDOFF[11:4] 31:24 ADDOFF[19:12] 0x1008 END 7:0 END[7:0] 15:8 END[15:8] 23:16 END[23:16] 31:24 END[31:24] SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 110

Offset Name Bit Pos. 0x100C ... 0x1FCB Reserved 0x1FCC MEMTYPE 7:0 SMEMP 15:8 23:16 31:24 0x1FD0 PID4 7:0 FKBC[3:0] JEPCC[3:0] 15:8 23:16 31:24 0x1FD4 ... 0x1FDF Reserved 0x1FE0 PID0 7:0 PARTNBL[7:0] 15:8 23:16 31:24 0x1FE4 PID1 7:0 JEPIDCL[3:0] PARTNBH[3:0] 15:8 23:16 31:24 0x1FE8 PID2 7:0 REVISION[3:0] JEPU JEPIDCH[2:0] 15:8 23:16 31:24 0x1FEC PID3 7:0 REVAND[3:0] CUSMOD[3:0] 15:8 23:16 31:24 0x1FF0 CID0 7:0 PREAMBLEB0[7:0] 15:8 23:16 31:24 0x1FF4 CID1 7:0 CCLASS[3:0] PREAMBLE[3:0] 15:8 23:16 31:24 0x1FF8 CID2 7:0 PREAMBLEB2[7:0] 15:8 23:16 31:24 SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 111

Offset Name Bit Pos. 0x1FFC CID3 7:0 PREAMBLEB3[7:0] 15:8 23:16 31:24

13.13 Register Description

13.13.1 Control

Name: CTRL Offset: 0x0000 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CE MBIST CRC SWRST Access W W W W Reset 0 0 0 0 Bit 4 – CE Chip-Erase Writing a '0' to this bit has no effect. Writing a '1' to this bit starts the Chip-Erase operation. Bit 3 – MBIST Memory Built-In Self-Test Writing a '0' to this bit has no effect. Writing a '1' to this bit starts the memory BIST algorithm. Bit 1 – CRC 32-bit Cyclic Redundancy Check Writing a '0' to this bit has no effect. Writing a '1' to this bit starts the cyclic redundancy check algorithm. Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets the module. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 113

13.13.2 Status A

Name: STATUSA Offset: 0x0001 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 PERR FAIL BERR CRSTEXT DONE Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 4 – PERR Protection Error Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Protection Error bit. This bit is set when a command that is not allowed in protected state is issued. Bit 3 – FAIL Failure Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Failure bit. This bit is set when a DSU operation failure is detected. Bit 2 – BERR Bus Error Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Bus Error bit. This bit is set when a bus error is detected. Bit 1 – CRSTEXT CPU Reset Phase Extension Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the CPU Reset Phase Extension bit. This bit is set when a debug adapter Cold-Plugging is detected, which extends the CPU reset phase. Bit 0 – DONE Done Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Done bit. This bit is set when a DSU operation is completed. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 114

13.13.3 Status B

Name: STATUSB Offset: 0x0002 Reset: 0x1X Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 HPE DCCD1 DCCD0 DBGPRES PROT Access R R R R R Reset 1 0 0 0 0 Bit 4 – HPE Hot-Plugging Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit has no effect. This bit is set when Hot-Plugging is enabled. This bit is cleared when Hot-Plugging is disabled. This is the case when the SWCLK function is changed. Only a power-reset or a external reset can set it again. Bits 2, 3 – DCCDx Debug Communication Channel x Dirty [x=1..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit has no effect. This bit is set when DCCx is written. This bit is cleared when DCCx is read. Bit 1 – DBGPRES Debugger Present Writing a '0' to this bit has no effect. Writing a '1' to this bit has no effect. This bit is set when a debugger probe is detected. This bit is never cleared. Bit 0 – PROT Protected Writing a '0' to this bit has no effect. Writing a '1' to this bit has no effect. This bit is set at power-up when the device is protected. This bit is never cleared. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 115

13.13.4 Address

Name: ADDR Offset: 0x0004 Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 ADDR[29:22] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 ADDR[21:14] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ADDR[13:6] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[5:0] AMOD[1:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:2 – ADDR[29:0] Address Initial word start address needed for memory operations. Bits 1:0 – AMOD[1:0] Access Mode The functionality of these bits is dependent on the operation mode. Bit description when operating CRC32: refer to 13.11.3 32-bit Cyclic Redundancy Check CRC32 Bit description when testing onboard memories (MBIST): refer to 13.11.5 Testing of On-Board Memories MBIST SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 116

13.13.5 Length

Name: LENGTH Offset: 0x0008 Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 LENGTH[29:22] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 LENGTH[21:14] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 LENGTH[13:6] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LENGTH[5:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bits 31:2 – LENGTH[29:0] Length Length in words needed for memory operations. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 117

13.13.6 Data

Name: DATA Offset: 0x000C Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 DATA[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DATA[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DATA[31:0] Data Memory operation initial value or result value. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 118

13.13.7 Debug Communication Channel 0

Name: DCC0 Offset: 0x0010 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 DATA[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DATA[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DATA[31:0] Data Data register. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 119

13.13.8 Debug Communication Channel 1

Name: DCC1 Offset: 0x0014 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 DATA[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DATA[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DATA[31:0] Data Data register. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 120

13.13.9 Device Identification

Name: DID Offset: 0x0018 Property: PAC Write-Protection The information in this register is related to the Ordering Information. Bit 31 30 29 28 27 26 25 24 PROCESSOR[3:0] FAMILY[4:1] Access R R R R R R R R Reset p p p p f f f f Bit 23 22 21 20 19 18 17 16 FAMILY[0:0] SERIES[5:0] Access R R R R R R R Reset f s s s s s s Bit 15 14 13 12 11 10 9 8 DIE[3:0] REVISION[3:0] Access R R R R R R R R Reset d d d d r r r r Bit 7 6 5 4 3 2 1 0 DEVSEL[7:0] Access R R R R R R R R Reset x x x x x x x x Bits 31:28 – PROCESSOR[3:0] Processor The value of this field defines the processor used on the device. Bits 27:23 – FAMILY[4:0] Product Family The value of this field corresponds to the product family part of the ordering code. Bits 21:16 – SERIES[5:0] Product Series The value of this field corresponds to the product series part of the ordering code. Bits 15:12 – DIE[3:0] Die Number Identifies the die family. Bits 11:8 – REVISION[3:0] Revision Number Identifies the die revision number. 0x0=rev.A, 0x1=rev.B etc. Note: The device variant (last letter of the ordering number) is independent of the die revision (DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks evolution of the die. Bits 7:0 – DEVSEL[7:0] Device Selection This bit field identifies a device within a product family and product series. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 121

13.13.10 CoreSight ROM Table Entry 0

Name: ENTRY0 Offset: 0x1000 Reset: 0xXXXXX00X Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 ADDOFF[19:12] Access R R R R R R R R Reset x x x x x x x x Bit 23 22 21 20 19 18 17 16 ADDOFF[11:4] Access R R R R R R R R Reset x x x x x x x x Bit 15 14 13 12 11 10 9 8 ADDOFF[3:0] Access R R R R Reset x x x x Bit 7 6 5 4 3 2 1 0 FMT EPRES Access R R Reset 1 x Bits 31:12 – ADDOFF[19:0] Address Offset The base address of the component, relative to the base address of this ROM table. Bit 1 – FMT Format Always reads as '1', indicating a 32-bit ROM table. Bit 0 – EPRES Entry Present This bit indicates whether an entry is present at this location in the ROM table. This bit is set at power-up if the device is not protected indicating that the entry is not present. This bit is cleared at power-up if the device is not protected indicating that the entry is present. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 122

13.13.11 CoreSight ROM Table Entry 1

Name: ENTRY1 Offset: 0x1004 Reset: 0xXXXXX00X Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 ADDOFF[19:12] Access R R R R R R R R Reset x x x x x x x x Bit 23 22 21 20 19 18 17 16 ADDOFF[11:4] Access R R R R R R R R Reset x x x x x x x x Bit 15 14 13 12 11 10 9 8 ADDOFF[3:0] Access R R R R Reset x x x x Bit 7 6 5 4 3 2 1 0 FMT EPRES Access R R Reset 1 x Bits 31:12 – ADDOFF[19:0] Address Offset The base address of the component, relative to the base address of this ROM table. Bit 1 – FMT Format Always read as '1', indicating a 32-bit ROM table. Bit 0 – EPRES Entry Present This bit indicates whether an entry is present at this location in the ROM table. This bit is set at power-up if the device is not protected indicating that the entry is not present. This bit is cleared at power-up if the device is not protected indicating that the entry is present. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 123

13.13.12 CoreSight ROM Table End

Name: END Offset: 0x1008 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 END[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 END[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 END[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 END[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – END[31:0] End Marker Indicates the end of the CoreSight ROM table entries. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 124

13.13.13 CoreSight ROM Table Memory Type

Name: MEMTYPE Offset: 0x1FCC Reset: 0x0000000x Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 SMEMP Access R Reset x Bit 0 – SMEMP System Memory Present This bit indicates whether system memory is present on the bus that connects to the ROM table. This bit is set at power-up if the device is not protected, indicating that the system memory is accessible from a debug adapter. This bit is cleared at power-up if the device is protected, indicating that the system memory is not accessible from a debug adapter. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 125

13.13.14 Peripheral Identification 4

Name: PID4 Offset: 0x1FD0 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 FKBC[3:0] JEPCC[3:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:4 – FKBC[3:0] 4KB Count These bits will always return zero when read, indicating that this debug component occupies one 4KB block. Bits 3:0 – JEPCC[3:0] JEP-106 Continuation Code These bits will always return zero when read. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 126

13.13.15 Peripheral Identification 0

Name: PID0 Offset: 0x1FE0 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PARTNBL[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:0 – PARTNBL[7:0] Part Number Low These bits will always return 0xD0 when read, indicating that this device implements a DSU module instance. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 127

13.13.16 Peripheral Identification 1

Name: PID1 Offset: 0x1FE4 Reset: 0x000000FC Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 JEPIDCL[3:0] PARTNBH[3:0] Access R R R R R R R R Reset 1 1 1 1 1 1 0 0 Bits 7:4 – JEPIDCL[3:0] Low part of the JEP-106 Identity Code These bits will always return 0xF when read (JEP-106 identity code is 0x1F). Bits 3:0 – PARTNBH[3:0] Part Number High These bits will always return 0xC when read, indicating that this device implements a DSU module instance. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 128

13.13.17 Peripheral Identification 2

Name: PID2 Offset: 0x1FE8 Reset: 0x00000009 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 REVISION[3:0] JEPU JEPIDCH[2:0] Access R R R R R R R R Reset 0 0 0 0 1 0 0 1 Bits 7:4 – REVISION[3:0] Revision Number Revision of the peripheral. Starts at 0x0 and increments by one at both major and minor revisions. Bit 3 – JEPU JEP-106 Identity Code is used This bit will always return one when read, indicating that JEP-106 code is used. Bits 2:0 – JEPIDCH[2:0] JEP-106 Identity Code High These bits will always return 0x1 when read, (JEP-106 identity code is 0x1F). SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 129

13.13.18 Peripheral Identification 3

Name: PID3 Offset: 0x1FEC Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 REVAND[3:0] CUSMOD[3:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:4 – REVAND[3:0] Revision Number These bits will always return 0x0 when read. Bits 3:0 – CUSMOD[3:0] ARM CUSMOD These bits will always return 0x0 when read. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 130

13.13.19 Component Identification 0

Name: CID0 Offset: 0x1FF0 Reset: 0x0000000D Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PREAMBLEB0[7:0] Access R R R R R R R R Reset 0 0 0 0 1 1 0 1 Bits 7:0 – PREAMBLEB0[7:0] Preamble Byte 0 These bits will always return 0x0000000D when read. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 131

13.13.20 Component Identification 1

Name: CID1 Offset: 0x1FF4 Reset: 0x00000010 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CCLASS[3:0] PREAMBLE[3:0] Access R R R R R R R R Reset 0 0 0 1 0 0 0 0 Bits 7:4 – CCLASS[3:0] Component Class These bits will always return 0x1 when read indicating that this ARM CoreSight component is ROM table (refer to the ARM Debug Interface v5 Architecture Specification at http://www.arm.com). Bits 3:0 – PREAMBLE[3:0] Preamble These bits will always return 0x00 when read. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 132

13.13.21 Component Identification 2

Name: CID2 Offset: 0x1FF8 Reset: 0x00000005 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PREAMBLEB2[7:0] Access R R R R R R R R Reset 0 0 0 0 0 1 0 1 Bits 7:0 – PREAMBLEB2[7:0] Preamble Byte 2 These bits will always return 0x00000005 when read. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 133

13.13.22 Component Identification 3

Name: CID3 Offset: 0x1FFC Reset: 0x000000B1 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PREAMBLEB3[7:0] Access R R R R R R R R Reset 1 0 1 1 0 0 0 1 Bits 7:0 – PREAMBLEB3[7:0] Preamble Byte 3 These bits will always return 0x000000B1 when read. SAM C20/C21 Family Data Sheet DSU - Device Service Unit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 134

DIVAS – Divide and Square Root Accelerator

14.1 Overview

The Divide and Square Root Accelerator (DIVAS) is a programmable 32-bit signed or unsigned hardware divider and a 32-bit unsigned square root hardware engine. The DIVAS is connected to the high-speed bus matrix and may also be accessed using the low-latency CPU local bus (IOBUS; ARM® single-cycle I/O port). The DIVAS takes dividend and divisor values and returns the quotient and remainder when it is used as divider. The DIVAS takes unsigned input value and returns its square root and remainder when it is used as square root function.

14.2 Features

Division accelerator for Cortex-M0+ systems
32-bit signed or unsigned integer division
32-bit unsigned square root
32-bit division in 2-16 cycles
Programmable leading zero optimization
Result includes quotient and remainder
Result includes square root and remainder
Busy and Divide-by-zero status
Automatic start of operation when divisor or square root input is loaded

14.3 Block Diagram

Figure 14-1. DIVAS Block Diagram DIVAS DEVIDE ENGINE INTERFACE AHB IOBUSQUOTIENT REMAINDER DIVIDEND DIVISOR CTRLA

14.4 Signal Description

14.5 Product Dependencies

In order to use this peripherial, other parts of the system must be configured correctly, as described below. SAM C20/C21 Family Data Sheet DIVAS – Divide and Square Root Accelerator © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 135

14.5.1 I/O Lines

14.5.2 Power Management

The DIVAS will not operate in any sleep mode .

14.5.3 Clocks

The DIVAS bus clock (CLK_DIVAS_AHB) can be enabled and disabled in the power manager, and the default state of CLK_DIVAS_AHB can be found in the Peripheral Clock Masking section in the Power Manager chapter.

14.5.4 DMA

14.5.5 Interrupts

14.5.6 Events

14.5.7 Debug Operation

14.5.8 Register Access Protection

Certain registers cannot be modified while DIVAS is busy. The following registers are write-protected while busy:

Control A (

14.8.1 CTRLA)

Dividend ( 14.8.3 DIVIDEND)
Divisor ( 14.8.4 DIVISOR)
Square Root Input ( 14.8.7 SQRNUM) Accessing these registers while protected will result in an error.

14.5.9 Analog Connections

14.5.10 CPU Local Bus

The CPU local bus (IOBUS) is an interface that connects the CPU directly to the DIVAS. It is a single- cycle bus interface, and does not support wait states. It supports byte, half word and word sizes. This bus is generally used for low latency. All registers can be read and written using this bus. Since the IOBUS cannot wait for DIVAS to complete operation, the Quotient and Remainder registers must be only be read via the IOBUS while the Busy bit in the Status register (STATUS.BUSY) is zero to prevent incorrect data from being read.

14.6 Functional Description

14.6.1 Principle of Operation

The Divide and Square Root Accelerator (DIVAS) supports signed or unsigned hardware division of 32-bit values and unsigned square root of 32-bit value. It is accessible from the CPU via both the AHB bus and SAM C20/C21 Family Data Sheet DIVAS – Divide and Square Root Accelerator © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 136

IOBUS. When the dividend and divide registers are programmed, the division starts and the result will be stored in the Result and Remainder registers. The Busy and Divide-by-zero status can be read from STATUS register. When the square root input register (

14.8.7 SQRNUM) is programmed, the square root function starts

and the result will be stored in the Result and Remainder registers. The Busy status can be read from STATUS register.

14.6.2 Basic Operation

14.6.2.1 Initialization

The DIVAS configuration cannot be modified while a divide operation is ongoing. The following bits must be written prior to starting a division:

Sign selection bit in Control A register ( 14.8.1 CTRLA.SIGNED)
Leading zero mode bit in Control A register ( 14.8.1 CTRLA.DLZ)

14.6.2.2 Performing Division

First write the dividend to DIVIDEND register. Writing the divisor to DIVISOR register starts the division and sets the busy bit in the Status register (STATUS.BUSY). When the division has completed, the STATUS.BUSY bit is cleared and the result will be stored in RESULT and REMAINDER registers. The RESULT and REMAINDER registers can be read directly via the high-speed bus without checking first STATUS.BUSY. Wait states will be inserted on the high-speed bus until the operation is complete. The IOBUS does not support wait states. For accesses via the IOBUS, the STATUS.BUSY bit must be polled before reading the result from the RESULTand REMAINDER registers.

14.6.2.3 Operand Size

The DIVAS can perform 32-bit signed and unsigned division and the operation follows the equation as below. DIVAS completes 32-bit division in 2-16 cycles. Square Root The DIVAS can perform 32-bit unsigned division and the operation follows the equation as below.

14.6.2.4 Signed Division

When CTRLA.SIGNED is one, both the input and the result will be in 2’s complement format. The results of signed division are such that the remainder and dividend have the same sign and the quotient is negative if the dividend and divisor have opposite signs. 16-bit results are sign extended to 32-bits. Note that when the maximum negative number is divided by the minimum negative number, the resulting quotient overflows the signed integer range and will return the maximum negative number with no indication of the overflow. This occurs for 0x80000000 / 0xFFFFFFFF in 32-bit operation and 0x8000 / 0xFFFF in 16-bit operation. SAM C20/C21 Family Data Sheet DIVAS – Divide and Square Root Accelerator © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 137

14.6.2.5 Divide By Zero

A divide by zero fault occurs if the DIVISOR is programmed to zero. QUOTIENT will be zero and the REMAINDER is equal to DIVIDEND. Divide by zero sets the Divide-by-zero bit in the Status register (STATUS.DBZ) to one. STATUS.DBZ must be cleared by writing a one to it.

14.6.2.6 Leading Zero Optimization

Leading zero optimization can reduce the time it takes to complete a division by skipping leading zeros in the DIVIDEND (or leading ones in signed mode). Leading zero optimization is enabled by default and can be disabled by the Disable Leading Zero bit in the Control A register (CTRLA.DLZ). When CTRLA.DLZ is zero, 16-bit division completes in 2-8 cycles and 32-bit division completes in 2-16 cycles, depending on the dividend value. If deterministic timing is required, setting CTRLA.DLZ to one forces 16-bit division to always take 8 cycles and 32-bit division to always take 16 cycles.

14.6.2.7 Unsigned Square Root

When the square root input register ( and the result will be stored in the Result and Remainder registers. The Busy status can be read from STATUS register. SAM C20/C21 Family Data Sheet DIVAS – Divide and Square Root Accelerator © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 138

14.7 Register Summary

Offset Name Bit Pos. 0x00 CTRLA 7:0 DLZ SIGNED 0x01 ... 0x03 Reserved 0x04 STATUS 7:0 DBZ BUSY 0x05 ... 0x07 Reserved 0x08 DIVIDEND 7:0 DIVIDEND[7:0] 15:8 DIVIDEND[15:8] 23:16 DIVIDEND[23:16] 31:24 DIVIDEND[31:24] 0x0C DIVISOR 7:0 DIVISOR[7:0] 15:8 DIVISOR[15:8] 23:16 DIVISOR[23:16] 31:24 DIVISOR[31:24] 0x10 RESULT 7:0 RESULT[7:0] 15:8 RESULT[15:8] 23:16 RESULT[23:16] 31:24 RESULT[31:24] 0x14 REMAINDER 7:0 REMAINDER[7:0] 15:8 REMAINDER[15:8] 23:16 REMAINDER[23:16] 31:24 REMAINDER[31:24] 0x18 SQRNUM 7:0 SQRNUM[7:0] 15:8 SQRNUM[15:8] 23:16 SQRNUM[23:16] 31:24 SQRNUM[31:24]

14.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. SAM C20/C21 Family Data Sheet DIVAS – Divide and Square Root Accelerator © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 139

14.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 DLZ SIGNED Access R/W R/W Reset 0 0 Bit 1 – DLZ Disable Leading Zero Optimization Value Description 0 Enable leading zero optimization; 32-bit division takes 2-16 cycles. 1 Disable leading zero optimization; 32-bit division takes 16 cycles. Bit 0 – SIGNED Signed Division Enable Value Description 0 Unsigned division. 1 Signed division. SAM C20/C21 Family Data Sheet DIVAS – Divide and Square Root Accelerator © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 140

14.8.2 Status

Name: STATUS Offset: 0x04 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 DBZ BUSY Access R/W R/W Reset 0 0 Bit 1 – DBZ Disable-By-Zero Writing a zero to this bit has no effect. Writing a one to this bit clears DBZ to zero. Value Description

0 A divide-by-zero fault has not occurred

1 A divide-by-zero fault has occurred

Bit 0 – BUSY DIVAS Accelerator Busy This bit is cleared when either division or square root function completes and results are ready in the Value Description

0 DIVAS is idle

1 DIVAS is busy with an ongoing division

14.8.3 Dividend

Name: DIVIDEND Offset: 0x08 Reset: 0x0000 Property: - Bit 31 30 29 28 27 26 25 24 DIVIDEND[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIVIDEND[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIVIDEND[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIVIDEND[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DIVIDEND[31:0] Dividend Value Holds the 32-bit dividend for the divide operation. If the Signed bit in Control A register (CTRLA.SIGNED) is zero, DIVIDEND is unsigned. If CTRLA.SIGNED = 1, DIVIDEND is signed two’s complement. Refer to SAM C20/C21 Family Data Sheet DIVAS – Divide and Square Root Accelerator © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 142

14.8.4 Divisor

Name: DIVISOR Offset: 0x0C Reset: 0x0000 Property: - Bit 31 30 29 28 27 26 25 24 DIVISOR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIVISOR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIVISOR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIVISOR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DIVISOR[31:0] Divisor Value Holds the 32-bit divisor for the divide operation. If the Signed bit in Control A register (CTRLA.SIGNED) is zero, DIVISOR is unsigned. If CTRLA.SIGNED = 1, DIVISOR is signed two’s complement. Writing the DIVISOR register will start the divide function. Refer to Size and 14.6.2.4 Signed Division. SAM C20/C21 Family Data Sheet DIVAS – Divide and Square Root Accelerator © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 143

14.8.5 Result

Name: RESULT Offset: 0x10 Reset: 0x0000 Property: - Bit 31 30 29 28 27 26 25 24 RESULT[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 RESULT[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 RESULT[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RESULT[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – RESULT[31:0] Result of Operation Holds the 32-bit result of the last performed operation. For a divide operation this is the quotient. If the Signed bit in Control A register (CTRLA.SIGNED) is zero, the quotient is unsigned. If CTRLA.SIGNED = 1, the quotient is signed two’s complement. For a square root operation this is the square root. Refer to SAM C20/C21 Family Data Sheet DIVAS – Divide and Square Root Accelerator © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 144

14.8.6 Remainder

Name: REMAINDER Offset: 0x14 Reset: 0x0000 Property: - Bit 31 30 29 28 27 26 25 24 REMAINDER[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 REMAINDER[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 REMAINDER[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 REMAINDER[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – REMAINDER[31:0] Remainder of Operation Holds the 32-bit remainder of the last performed operation. For a divide operation this is the division remainder. If the Signed bit in Control A register (CTRLA.SIGNED) is zero, the quotient is unsigned. If CTRLA.SIGNED = 1, the quotient is signed two’s complement. For a square root operation this is the square root remainder. Refer to Signed Division. SAM C20/C21 Family Data Sheet DIVAS – Divide and Square Root Accelerator © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 145

14.8.7 Square Root Input

Name: SQRNUM Offset: 0x18 Reset: 0x0000 Property: - Bit 31 30 29 28 27 26 25 24 SQRNUM[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SQRNUM[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SQRNUM[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SQRNUM[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – SQRNUM[31:0] Square Root Input Holds the 32-bit unsigned input for the square root operation. Writing the SQRNUM register will start the square root function. Refer to 14.6.2.7 Unsigned Square Root. SAM C20/C21 Family Data Sheet DIVAS – Divide and Square Root Accelerator © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 146

Clock System This chapter only aims to summarize the clock distribution and terminology in the SAM C20/C21 device. It will not explain every detail of its configuration. For in-depth documentation, see the referenced module chapters.

15.1 Clock Distribution

Figure 15-1. Clock distribution OSCCTRL GCLK GCLK Generator 1 GCLK Generator x Peripheral Channel 0 Peripheral Channel 1 (FDPLL96M Reference) Peripheral z Peripheral 0 Syncronous Clock Controller MCLK AHB/APB System Clocks GCLK_MAIN OSC48M XOSC Generic Clocks OSCK32CTRL OSC32K OSCULP32K XOSC32K FDPLL96M Peripheral Channel 3 GCLK_DPLL Peripheral Channel y GCLK_DPLL_32K GCLK_DPLL GCLK_DPLL_32K RTC CLK_RTC_OSC CLK_WDT_OSC Peripheral Channel 2 (FDPLL96M Reference) WDT 32kHz 1kHz 32kHz 1kHz 32kHz 1kHz CLK_ULP32K EIC GCLK Generator 0 The clock system on the SAM C20/C21 consists of:

Clock sources, controlled by OSCCTRL and OSC32KCTRL – A Clock source is the base clock signal used in the system. Example clock sources are the internal 48MHz oscillator (OSC48M), External crystal oscillator (XOSC) and the Digital phase locked loop (FDPLL96M).
Generic Clock Controller (GCLK) which controls the clock distribution system, made up of: – Generic Clock generators: A programmable prescaler, that can use any of the system clock sources as its source clock. The Generic Clock Generator 0, also called GCLK_MAIN, is the clock feeding the Power Manager used to generate synchronous clocks. – Generic Clocks: Typically the clock input of a peripheral on the system. The generic clocks, through the Generic Clock Multiplexer, can use any of the Generic Clock generators as its clock source. Multiple instances of a peripheral will typically have a separate generic clock for each instance.
Main Clock controller (MCLK) – The MCLK controls synchronous clocks on the system. This includes the CPU, bus clocks (APB, AHB) as well as the synchronous (to the CPU) user interfaces of the peripherals. It contains clock masks that can turn on/off the user interface of a peripheral as well as prescalers for the CPU and bus clocks. SAM C20/C21 Family Data Sheet Clock System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 147

The figure below shows an example where SERCOM0 is clocked by the OSC48M. The OSC48M is enabled, the Generic Clock Generator 1 uses the OSCLL48M as its clock source, and the generic clock 19, also called GCLK_SERCOM0_CORE, that is connected to SERCOM0 uses generator 1 as its source. The SERCOM0 interface, clocked by CLK_SERCOM0_APB, has been unmasked in the APBC Mask register in the MCLK. Figure 15-2. Example of SERCOM clock OSCCTRL OSC48 Generic Clock Generator 1 Peripheral Channel 19 SERCOM 0 Syncronous Clock Controller MCLK CLK_SERCOM0_APB GCLK_SERCOM0_CORE GCLK

15.2 Synchronous and Asynchronous Clocks

As the CPU and the peripherals can be clocked from different clock sources, possibly with widely different clock speeds, some peripheral accesses by the CPU needs to be synchronized between the different clock domains. In these cases the peripheral includes a SYNCBUSY status register that can be used to check if a sync operation is in progress. As the nature of the synchronization might vary between different peripherals, detailed description for each peripheral can be found in the sub-chapter “synchronization” for each peripheral where this is necessary. In the datasheet references to synchronous clocks are referring to the CPU and bus clocks, while asynchronous clocks are clock generated by generic clocks.

15.3 Register Synchronization

15.3.1 Overview

All peripherals are composed of one digital bus interface, which is connected to the APB or AHB bus and clocked using a corresponding synchronous clock, and one core clock, which is clocked using a generic clock. Access between these clock domains must be synchronized. As this mechanism is implemented in hardware the synchronization process takes place even if the different clocks domains are clocked from the same source and on the same frequency. All registers in the bus interface are accessible without synchronization. All core registers in the generic clock domain must be synchronized when written. Some core registers must be synchronized when read. Registers that need synchronization has this denoted in each individual register description.

15.3.2 General Write-Synchronization

Inside the same module, each core register, denoted by the Write-Synchronized property, use its own synchronization mechanism so that writing to different core registers can be done without waiting for the end of synchronization of previous core register access. However a second write access to the same core register, while synchronization is on going, is discarded and an error is reported through the PAC. To write again to the same core register in the same module, user must wait for the end of synchronization. For each core register, that can be written, a synchronization status bit is associated SAM C20/C21 Family Data Sheet Clock System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 148

Example: REGA, REGB are 8-bit core registers. REGC is 16-bit core register. Offset Register 0x00 REGA 0x01 REGB 0x02 REGC 0x03 Since synchronization is per register, user can write REGA (8-bit access) then immediately write REGB (8-bit access) without error. User can write REGC (16-bit access) without affecting REGA or REGB. But if user writes REGC in two consecutive 8-bit accesses, second write will be discarded and generate an error. When user makes a 32-bit access to offset 0x00, all registers are written but REGA, REGB, REGC can be updated at a different time because of independent write synchronization

15.3.3 General Read-Synchronization

Before any read of a core register, the user must check that the related bit in SYNCBUSY register is cleared. Read access to core register is always immediate but the return value is reliable only if a synchronization of this core register is not going.

15.3.4 Completion of Synchronization

The user can either poll SYNCBUSY register or use the Synchronization Ready interrupt (if available) to check when the synchronization is complete.

15.3.5 Enable Write-Synchronization

Writing to the Enable bit in the Control register (CTRL.ENABLE) will also trigger write-synchronization and set SYNCBUSY.ENABLE. CTRL.ENABLE will read its new value immediately after being written. The Synchronisation Ready interrupt (if available) cannot be used for Enable write-synchronization.

15.3.6 Software Reset Write-Synchronization

Writing a one to the Software Reset bit in CTRL (CTRL.SWRST) will also trigger write-synchronization and set SYNCBUSY.SWRST. When writing a one to the CTRL.SWRST bit it will immediately read as one. CTRL.SWRST and SYNCBUSY.SWRST will be cleared by hardware when the peripheral has been reset. Writing a zero to the CTRL.SWRST bit has no effect. The Synchronisation Ready interrupt (if available) cannot be used for Software Reset write-synchronization.

15.3.7 Synchronization Delay

The synchronization will delay the write or read access duration by a delay D, given by the equation: Where ?GCLK is the period of the generic clock and ?APB is the period of the peripheral bus clock. A normal peripheral bus register access duration is ʹ ⋅ ?APB. SAM C20/C21 Family Data Sheet Clock System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 149

15.4 Enabling a Peripheral

To enable a peripheral clocked by a generic clock, the following parts of the system needs to be configured:

A running clock source.
A clock from the Generic Clock Generator must be configured to use one of the running clock sources, and the generator must be enabled.
The generic clock, through the Generic Clock Multiplexer, that connects to the peripheral needs to be configured with a running clock from the Generic Clock Generator, and the generic clock must be enabled.
The user interface of the peripheral needs to be unmasked in the PM. If this is not done the peripheral registers will read as all 0’s and any writes to the peripheral will be discarded.

15.5 On-demand, Clock Requests

Figure 15-3. Clock request routing OSC48 Generic Clock Generator Clock request Generic Clock Periph. Channel Clock request Peripheral Clock request ENABLE RUNSTDBY ONDEMAND CLKEN RUNSTDBY ENABLE RUNSTDBY GENEN All the clock sources in the system can be run in an on-demand mode, where the clock source is in a stopped state when no peripherals are requesting the clock source. Clock requests propagate from the peripheral, via the GCLK, to the clock source. If one or more peripheral is using a clock source, the clock source will be started/kept running. As soon as the clock source is no longer needed and no peripheral have an active request the clock source will be stopped until requested again. For the clock request to reach the clock source, the peripheral, the generic clock and the clock from the Generic Clock Generator in-between must be enabled. The time taken from a clock request being asserted to the clock source being ready is dependent on the clock source startup time, clock source frequency as well as the divider used in the Generic Clock Generator. The total startup time from a clock request to the clock is available for the peripheral is: Delay_start_max = Clock source startup time + 2 * clock source periods + 2 * divided clock source periods Delay_start_min = Clock source startup time + 1 * clock source period + 1 * divided clock source periodDelay_start_min = Clock source startup time + 1 * clock source period + 1 * divided clock source period The delay for shutting down the clock source when there is no longer an active request is: Delay_stop_min = 1 * divided clock source period + 1 * clock source period Delay_stop_max = 2 * divided clock source periods + 2 * clock source periods The On-Demand principle can be disabled individually for each clock source by clearing the ONDEMAND bit located in each clock source controller. The clock is always running whatever is the clock request. This has the effect to remove the clock source startup time at the cost of the power consumption. In standby mode, the clock request mechanism is still working if the modules are configured to run in standby mode (RUNSTDBY bit). SAM C20/C21 Family Data Sheet Clock System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 150

15.6 Power Consumption vs. Speed Due to the nature of the asynchronous clocking of the peripherals there are some considerations that needs to be taken if either targeting a low-power or a fast-acting system. If clocking a peripheral with a very low clock, the active power consumption of the peripheral will be lower. At the same time the synchronization to the synchronous (CPU) clock domain is dependent on the peripheral clock speed, and will be longer with a slower peripheral clock; giving lower response time and more time waiting for the synchronization to complete.

15.7 Clocks after Reset

On any reset the synchronous clocks start to their initial state:

OSC48M is enabled and divided by 12
GCLK_MAIN uses OSC48M as source
CPU and BUS clocks are undivided On a power reset the GCLK starts to their initial state:
All generic clock generators disabled except: – The generator 0 (GCLK_MAIN) using OSC48M as source, with no division
All generic clocks disabled On a user reset the GCLK starts to their initial state, except for:
Generic clocks that are write-locked (WRTLOCK is written to one prior to reset) On any reset the clock sources are reset to their initial state except the 32KHz clock sources which are reset only by a power reset. SAM C20/C21 Family Data Sheet Clock System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 151

GCLK - Generic Clock Controller

16.1 Overview

Depending on the application, peripherals may require specific clock frequencies to operate correctly. The Generic Clock controller (GCLK) features 9 Generic Clock Generators 0..8 that can provide a wide range of clock frequencies. Generators can be set to use different external and internal oscillators as source. The clock of each Generator can be divided. The outputs from the Generators are used as sources for the Peripheral Channels, which provide the Generic Clock (GCLK_PERIPH) to the peripheral modules, as shown in Figure 16-2. The number of Peripheral Clocks depends on how many peripherals the device has. Note: The Generator 0 is always the direct source of the GCLK_MAIN signal.

16.2 Features

Provides a device-defined, configurable number of Peripheral Channel clocks
Wide frequency range: – Various clock sources – Embedded dividers

16.3 Block Diagram

The generation of Peripheral Clock signals (GCLK_PERIPH) and the Main Clock (GCLK_MAIN) can be seen in Device Clocking Diagram. Figure 16-1. Device Clocking Diagram GCLK_IO Generic Clock Generator OSC48M OSCCTRL Clock Divider & Masker Clock Gate Peripheral Channel GCLK_PERIPH PERIPHERAL GENERIC CLOCK CONTROLLER MCLKGCLK_MAIN XOSC OSC32CTRL OSC32K OSCULP32K XOSC32K FDPLL96M The GCLK block diagram is shown below: SAM C20/C21 Family Data Sheet GCLK - Generic Clock Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 152

Figure 16-2. Generic Clock Controller Block Diagram Generic Clock Generator 0 GCLK_IO[0] (I/O input) Clock Divider & Masker Clock Sources GCLKGEN[0] GCLK_IO[1] (I/O input) GCLKGEN[1] GCLK_IO[n] (I/O input) GCLKGEN[n] Clock Gate Peripheral Channel 0 GCLK_PERIPH[0] Clock Gate Peripheral Channel 1 Clock Gate Peripheral Channel n GCLKGEN[n:0] GCLK_MAIN GCLK_IO[1] (I/O output) GCLK_IO[0] (I/O output) GCLK_IO[n] (I/O output) Generic Clock Generator 1 Clock Divider & Masker Generic Clock Generator n Clock Divider & Masker GCLK_PERIPH[1] GCLK_PERIPH[n]

16.4 Signal Description

Table 16-1. GCLK Signal Description Signal Name Type Description GCLK_IO[7:0] Digital I/O Clock source for Generators when input Generic Clock signal when output Note: One signal can be mapped on several pins. Related Links 6. I/O Multiplexing and Considerations

16.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

16.5.1 I/O Lines

Using the GCLK I/O lines requires the I/O pins to be configured. Related Links 28. PORT - I/O Pin Controller

16.5.2 Power Management

The GCLK can operate in sleep modes, if required. Refer to the sleep mode description in the Power Manager (PM) section. Related Links 19. PM – Power Manager SAM C20/C21 Family Data Sheet GCLK - Generic Clock Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 153

16.5.3 Clocks

The GCLK bus clock (CLK_GCLK_APB) can be enabled and disabled in the Main Clock Controller. Related Links

OSC32KCTRL – 32KHz Oscillators Controller

16.5.4 DMA

Not applicable.

16.5.5 Interrupts

Not applicable.

16.5.6 Events

Not applicable.

16.5.7 Debug Operation

When the CPU is halted in debug mode the GCLK continues normal operation. If the GCLK is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging.

16.5.8 Register Access Protection

All registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC). Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. Write-protection does not apply for accesses through an external debugger. Related Links 11. PAC - Peripheral Access Controller

16.5.9 Analog Connections

Not applicable.

16.6 Functional Description

16.6.1 Principle of Operation

The GCLK module is comprised of nine Generic Clock Generators (Generators) sourcing up to 64 Peripheral Channels and the Main Clock signal GCLK_MAIN. A clock source selected as input to a Generator can either be used directly, or it can be prescaled in the Generator. A generator output is used by one or more Peripheral Channels to provide a peripheral generic clock signal (GCLK_PERIPH) to the peripherals.

16.6.2 Basic Operation

16.6.2.1 Initialization

Before a Generator is enabled, the corresponding clock source should be enabled. The Peripheral clock must be configured as outlined by the following steps: SAM C20/C21 Family Data Sheet GCLK - Generic Clock Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 154

The Generator must be enabled (GENCTRLn.GENEN=1) and the division factor must be set (GENTRLn.DIVSEL and GENCTRLn.DIV) by performing a single 32-bit write to the Generator Control register (GENCTRLn). 2. The Generic Clock for a peripheral must be configured by writing to the respective Peripheral Channel Control register (PCHCTRLm). The Generator used as the source for the Peripheral Clock must be written to the GEN bit field in the Peripheral Channel Control register (PCHCTRLm.GEN). Note: Each Generator n is configured by one dedicated register GENCTRLn. Note: Each Peripheral Channel m is configured by one dedicated register PCHCTRLm.

16.6.2.2 Enabling, Disabling, and Resetting

The GCLK module has no enable/disable bit to enable or disable the whole module. The GCLK is reset by setting the Software Reset bit in the Control A register (CTRLA.SWRST) to 1. All registers in the GCLK will be reset to their initial state, except for Peripheral Channels and associated Generators that have their Write Lock bit set to 1 (PCHCTRLm.WRTLOCK). For further details, refer to 16.6.3.4 Configuration Lock.

16.6.2.3 Generic Clock Generator

Each Generator (GCLK_GEN) can be set to run from one of nine different clock sources except GCLK_GEN[1], which can be set to run from one of eight sources. GCLK_GEN[1] is the only Generator that can be selected as source to others Generators. Each generator GCLK_GEN[x] can be connected to one specific pin GCLK_IO[x]. A pin GCLK_IO[x] can be set either to act as source to GCLK_GEN[x] or to output the clock signal generated by GCLK_GEN[x]. The selected source can be divided. Each Generator can be enabled or disabled independently. Each GCLK_GEN clock signal can then be used as clock source for Peripheral Channels. Each Generator output is allocated to one or several Peripherals. GCLK_GEN[0] is used as GCLK_MAIN for the synchronous clock controller inside the Main Clock Controller. Refer to the Main Clock Controller description for details on the synchronous clock generation. Figure 16-3. Generic Clock Generator Related Links 17. MCLK – Main Clock

16.6.2.4 Enabling a Generator

A Generator is enabled by writing a '1' to the Generator Enable bit in the Generator Control register (GENCTRLn.GENEN=1). SAM C20/C21 Family Data Sheet GCLK - Generic Clock Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 155

16.6.2.5 Disabling a Generator

A Generator is disabled by writing a '0' to GENCTRLn.GENEN. When GENCTRLn.GENEN=0, the GCLK_GEN[n] clock is disabled and gated.

16.6.2.6 Selecting a Clock Source for the Generator

Each Generator can individually select a clock source by setting the Source Select bit group in the Generator Control register (GENCTRLn.SRC). Changing from one clock source, for example A, to another clock source, B, can be done on the fly: If clock source B is not ready, the Generator will continue using clock source A. As soon as source B is ready, the Generator will switch to it. During the switching operation, the Generator maintains clock requests to both clock sources A and B, and will release source A as soon as the switch is done. The according bit in SYNCBUSY register (SYNCBUSY.GENCTRLn) will remain '1' until the switch operation is completed. Before switching the Generic Clock Generator 0 (GCLKGEN0) from a clock source A to another clock source B, enable the ONDEMAND feature of the clock source A to ensure a proper transition from clock source A to clock source B. The available clock sources are device dependent (usually the oscillators, RC oscillators, and DPLL). Only Generator 1 can be used as a common source for all other generators.

16.6.2.7 Changing the Clock Frequency

The selected source for a Generator can be divided by writing a division value in the Division Factor bit field of the Generator Control register (GENCTRLn.DIV). How the actual division factor is calculated is depending on the Divide Selection bit (GENCTRLn.DIVSEL). If GENCTRLn.DIVSEL=0 and GENCTRLn.DIV is either 0 or 1, the output clock will be undivided. Note: The number of available DIV bits may vary from Generator to Generator.

16.6.2.8 Duty Cycle

When dividing a clock with an odd division factor, the duty-cycle will not be 50/50. Setting the Improve Duty Cycle bit of the Generator Control register (GENCTRLn.IDC) will result in a 50/50 duty cycle.

16.6.2.9 External Clock

The output clock (GCLK_GEN) of each Generator can be sent to I/O pins (GCLK_IO). If the Output Enable bit in the Generator Control register is set (GENCTRLn.OE = 1) and the generator is enabled (GENCTRLn.GENEN=1), the Generator requests its clock source and the GCLK_GEN clock is output to an I/O pin. Note: The I/O pin (GCLK/IO[n]) must first be configured as output by writing the corresponding PORT registers. If GENCTRLn.OE is 0, the according I/O pin is set to an Output Off Value, which is selected by GENCTRLn.OOV: If GENCTRLn.OOV is '0', the output clock will be low. If this bit is '1', the output clock will be high. In Standby mode, if the clock is output (GENCTRLn.OE=1), the clock on the I/O pin is frozen to the OOV value if the Run In Standby bit of the Generic Control register (GENCTRLn.RUNSTDBY) is zero. If GENCTRLn.RUNSTDBY is '1', the GCLKGEN clock is kept running and output to the I/O pin. SAM C20/C21 Family Data Sheet GCLK - Generic Clock Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 156

16.6.3 Peripheral Clock

Figure 16-4. Peripheral Clock

16.6.3.1 Enabling a Peripheral Clock

Before a Peripheral Clock is enabled, one of the Generators must be enabled (GENCTRLn.GENEN) and selected as source for the Peripheral Channel by setting the Generator Selection bits in the Peripheral Channel Control register (PCHCTRL.GEN). Any available Generator can be selected as clock source for each Peripheral Channel. When a Generator has been selected, the peripheral clock is enabled by setting the Channel Enable bit in the Peripheral Channel Control register, PCHCTRLm.CHEN = 1. The PCHCTRLm.CHEN bit must be synchronized to the generic clock domain. PCHCTRLm.CHEN will continue to read as its previous state until the synchronization is complete.

16.6.3.2 Disabling a Peripheral Clock

A Peripheral Clock is disabled by writing PCHCTRLm.CHEN=0. The PCHCTRLm.CHEN bit must be synchronized to the Generic Clock domain. PCHCTRLm.CHEN will stay in its previous state until the synchronization is complete. The Peripheral Clock is gated when disabled. Related Links

16.8.4 PCHCTRLm

16.6.3.3 Selecting the Clock Source for a Peripheral

When changing a peripheral clock source by writing to PCHCTRLm.GEN, the peripheral clock must be disabled before re-enabling it with the new clock source setting. This prevents glitches during the transition: 1. Disable the Peripheral Channel by writing PCHCTRLm.CHEN=0 2. Assert that PCHCTRLm.CHEN reads '0' 3. Change the source of the Peripheral Channel by writing PCHCTRLm.GEN 4. Re-enable the Peripheral Channel by writing PCHCTRLm.CHEN=1 Related Links

16.6.3.4 Configuration Lock

The peripheral clock configuration can be locked for further write accesses by setting the Write Lock bit in the Peripheral Channel Control register PCHCTRLm.WRTLOCK=1). All writing to the PCHCTRLm register will be ignored. It can only be unlocked by a Power Reset. The Generator source of a locked Peripheral Channel will be locked, too: The corresponding GENCTRLn register is locked, and can be unlocked only by a Power Reset. SAM C20/C21 Family Data Sheet GCLK - Generic Clock Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 157

There is one exception concerning the Generator 0. As it is used as GCLK_MAIN, it cannot be locked. It is reset by any Reset and will start up in a known configuration. The software reset (CTRLA.SWRST) can not unlock the registers. In case of an external Reset, the Generator source will be disabled. Even if the WRTLOCK bit is written to '1' the peripheral channels are disabled (PCHCTRLm.CHEN set to '0') until the Generator source is enabled again. Then, the PCHCTRLm.CHEN are set to '1' again. Related Links

16.8.1 CTRLA

16.6.4 Additional Features

16.6.4.1 Peripheral Clock Enable after Reset

The Generic Clock Controller must be able to provide a generic clock to some specific peripherals after a Reset. That means that the configuration of the Generators and Peripheral Channels after Reset is device-dependent. Refer to GENCTRLn.SRC for details on GENCTRLn reset. Refer to PCHCTRLm.SRC for details on PCHCTRLm reset.

16.6.5 Sleep Mode Operation

16.6.5.1 SleepWalking

The GCLK module supports the SleepWalking feature. If the system is in a sleep mode where the Generic Clocks are stopped, a peripheral that needs its clock in order to execute a process must request it from the Generic Clock Controller. The Generic Clock Controller receives this request, determines which Generic Clock Generator is involved and which clock source needs to be awakened. It then wakes up the respective clock source, enables the Generator and Peripheral Channel stages successively, and delivers the clock to the peripheral. The RUNSTDBY bit in the Generator Control register controls clock output to pin during standby sleep mode. If the bit is cleared, the Generator output is not available on pin. When set, the GCLK can continuously output the generator output to GCLK_IO. Refer to 16.6.2.9 External Clock for details. Related Links 19. PM – Power Manager

16.6.5.2 Minimize Power Consumption in Standby

The following table identifies when a Clock Generator is off in Standby Mode, minimizing the power consumption: Table 16-2. Clock Generator n Activity in Standby Mode Request for Clock n present GENCTRLn.RUNSTDBY GENCTRLn.OE Clock Generator n yes - - active no 1 1 active no 1 0 OFF no 0 1 OFF no 0 0 OFF SAM C20/C21 Family Data Sheet GCLK - Generic Clock Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 158

16.6.5.3 Entering Standby Mode

There may occur a delay when the device is put into Standby, until the power is turned off. This delay is caused by running Clock Generators: if the Run in Standby bit in the Generator Control register (GENCTRLn.RUNSTDBY) is '0', GCLK must verify that the clock is turned of properly. The duration of this verification is frequency-dependent. Related Links 19. PM – Power Manager

16.6.6 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. An exception is the Channel Enable bit in the Peripheral Channel Control registers (PCHCTRLm.CHEN). When changing this bit, the bit value must be read-back to ensure the synchronization is complete and to assert glitch free internal operation. Note that changing the bit value under ongoing synchronization will not generate an error. The following registers are synchronized when written:

Generic Clock Generator Control register (GENCTRLn)
Control A register (CTRLA) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Related Links

16.7 Register Summary

Offset Name Bit Pos. 0x00 CTRLA 7:0 SWRST 0x01 ... 0x03 Reserved 0x04 SYNCBUSY 7:0 GENCTRL5 GENCTRL4 GENCTRL3 GENCTRL2 GENCTRL1 GENCTRL0 SWRST 15:8 GENCTRL7 GENCTRL6 23:16 31:24 0x08 ... 0x1F Reserved 0x20 GENCTRL0 7:0 SRC[4:0] 15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN 23:16 DIV[7:0] 31:24 DIV[15:8] 0x24 GENCTRL1 7:0 SRC[4:0] 15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN 23:16 DIV[7:0] 31:24 DIV[15:8] 0x28 GENCTRL2 7:0 SRC[4:0] 15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN 23:16 DIV[7:0] 31:24 DIV[15:8] 0x2C GENCTRL3 7:0 SRC[4:0] 15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN 23:16 DIV[7:0] 31:24 DIV[15:8] 0x30 GENCTRL4 7:0 SRC[4:0] 15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN 23:16 DIV[7:0] 31:24 DIV[15:8] 0x34 GENCTRL5 7:0 SRC[4:0] 15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN 23:16 DIV[7:0] 31:24 DIV[15:8] 0x38 GENCTRL6 7:0 SRC[4:0] 15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN 23:16 DIV[7:0] 31:24 DIV[15:8] 0x3C GENCTRL7 7:0 SRC[4:0] 15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN 23:16 DIV[7:0] 31:24 DIV[15:8] SAM C20/C21 Family Data Sheet GCLK - Generic Clock Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 160

Offset Name Bit Pos. 0x40 GENCTRL8 7:0 SRC[4:0] 15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN 23:16 DIV[7:0] 31:24 DIV[15:8] 0x44 ... 0x7F Reserved 0x80 PCHCTRL0 7:0 WRTLOCK CHEN GEN[3:0] 15:8 23:16 31:24 ... 0x0134 PCHCTRL45 7:0 WRTLOCK CHEN GEN[3:0] 15:8 23:16 31:24

16.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 16.5.8 Register Access Protection. Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write- Synchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to 16.6.6 Synchronization. SAM C20/C21 Family Data Sheet GCLK - Generic Clock Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 161

16.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00 Property: PAC Write-Protection, Write-Synchronized Bit 7 6 5 4 3 2 1 0 SWRST Access R/W Reset 0 Bit 0 – SWRST Software Reset Writing a zero to this bit has no effect. Setting this bit to 1 will reset all registers in the GCLK to their initial state after a Power Reset, except for generic clocks and associated Generators that have their WRTLOCK bit in PCHCTRLm set to 1. Refer to GENCTRL Reset Value for details on GENCTRL register reset. Refer to PCHCTRL Reset Value for details on PCHCTRL register reset. Due to synchronization, there is a waiting period between setting CTRLA.SWRST and a completed Reset. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. Value Description 0 There is no Reset operation ongoing. 1 A Reset operation is ongoing. SAM C20/C21 Family Data Sheet GCLK - Generic Clock Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 162

16.8.2 Synchronization Busy

Name: SYNCBUSY Offset: 0x04 Reset: 0x00000000 Property: – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 GENCTRL7 GENCTRL6 Access R R Reset 0 0 Bit 7 6 5 4 3 2 1 0 GENCTRL5 GENCTRL4 GENCTRL3 GENCTRL2 GENCTRL1 GENCTRL0 SWRST Access R R R R R R R Reset 0 0 0 0 0 0 0 Bits 2, 3, 4, 5, 6, 7, 8, 9 – GENCTRL Generator Control n Synchronization Busy This bit is cleared when the synchronization of the Generator Control n register (GENCTRLn) between clock domains is complete, or when clock switching operation is complete. This bit is set when the synchronization of the Generator Control n register (GENCTRLn) between clock domains is started. Bit 0 – SWRST Software Reset Synchronization Busy This bit is cleared when the synchronization of the CTRLA.SWRST register bit between clock domains is complete. This bit is set when the synchronization of the CTRLA.SWRST register bit between clock domains is started. SAM C20/C21 Family Data Sheet GCLK - Generic Clock Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 163

16.8.3 Generator Control

Name: GENCTRLn Offset: 0x20 + n*0x04 [n=0..8] Reset: 0x00000106 Property: PAC Write-Protection, Write-Synchronized GENCTRLn controls the settings of Generic Generator n (n=0..8). The reset value is 0x00000106 for Generator n=0, else 0x00000000 Bit 31 30 29 28 27 26 25 24 DIV[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIV[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 RUNSTDBY DIVSEL OE OOV IDC GENEN Access Reset 0 0 0 0 0 1 Bit 7 6 5 4 3 2 1 0 SRC[4:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bits 31:16 – DIV[15:0] Division Factor These bits represent a division value for the corresponding Generator. The actual division factor is dependent on the state of DIVSEL. The number of relevant DIV bits for each Generator can be seen in this table. Written bits outside of the specified range will be ignored. Table 16-3. Division Factor Bits Generic Clock Generator Division Factor Bits Generator 0 8 division factor bits - DIV[7:0] Generator 1 16 division factor bits - DIV[15:0] Generator 2-9 8 division factor bits - DIV[4:0] Bit 13 – RUNSTDBY Run in Standby This bit is used to keep the Generator running in Standby as long as it is configured to output to a dedicated GCLK_IO pin. If GENCTRLn.OE is zero, this bit has no effect and the generator will only be running if a peripheral requires the clock. Value Description

0 The Generator is stopped in Standby and the GCLK_IO pin state (one or zero) will be

1 The Generator is kept running and output to its dedicated GCLK_IO pin during Standby

mode. Bit 12 – DIVSEL Divide Selection This bit determines how the division factor of the clock source of the Generator will be calculated from DIV. If the clock source should not be divided, DIVSEL must be 0 and the GENCTRLn.DIV value must be either 0 or 1. Value Description

0 The Generator clock frequency equals the clock source frequency divided by

GENCTRLn.DIV.

1 The Generator clock frequency equals the clock source frequency divided by 2^(N+1), where

N is the Division Factor Bits for the selected generator (refer to GENCTRLn.DIV). Bit 11 – OE Output Enable This bit is used to output the Generator clock output to the corresponding pin (GCLK_IO), as long as GCLK_IO is not defined as the Generator source in the GENCTRLn.SRC bit field. Value Description 0 No Generator clock signal on pin GCLK_IO.

1 The Generator clock signal is output on the corresponding GCLK_IO, unless GCLK_IO is

selected as a generator source in the GENCTRLn.SRC bit field. Bit 10 – OOV Output Off Value This bit is used to control the clock output value on pin (GCLK_IO) when the Generator is turned off or the OE bit is zero, as long as GCLK_IO is not defined as the Generator source in the GENCTRLn.SRC bit field. Value Description 0 The GCLK_IO will be LOW when generator is turned off or when the OE bit is zero. 1 The GCLK_IO will be HIGH when generator is turned off or when the OE bit is zero. Bit 9 – IDC Improve Duty Cycle This bit is used to improve the duty cycle of the Generator output to 50/50 for odd division factors. Value Description 0 Generator output clock duty cycle is not balanced to 50/50 for odd division factors. 1 Generator output clock duty cycle is 50/50. Bit 8 – GENEN Generator Enable This bit is used to enable and disable the Generator. Value Description 0 Generator is disabled. 1 Generator is enabled. Bits 4:0 – SRC[4:0] Generator Clock Source Selection These bits select the Generator clock source, as shown in this table. Table 16-4. Generator Clock Source Selection Value Name Description 0x00 XOSC XOSC oscillator output SAM C20/C21 Family Data Sheet GCLK - Generic Clock Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 165

0x01 GCLK_IN Generator input pad (GCLK_IO) 0x02 GCLK_GEN1 Generic clock generator 1 output 0x03 OSCULP32K OSCULP32K oscillator output 0x04 OSC32K OSC32K oscillator output 0x05 XOSC32K XOSC32K oscillator output 0x06 OSC48M OSC48M oscillator output 0x07 DPLL96M DPLL96M output 0x08-0x1F Reserved Reserved for future use A Power Reset will reset all GENCTRLn registers. the Reset values of the GENCTRLn registers are shown in table below. Table 16-5. GENCTRLn Reset Value after a Power Reset GCLK Generator Reset Value after a Power Reset 0 0x00000106 others 0x00000000 A User Reset will reset the associated GENCTRL register unless the Generator is the source of a locked Peripheral Channel (PCHCTRLm.WRTLOCK=1). The reset values of the GENCTRL register are as shown in the table below. Table 16-6. GENCTRLn Reset Value after a User Reset GCLK Generator Reset Value after a User Reset 0 0x00000106 others No change if the generator is used by a Peripheral Channel m with PCHCTRLm.WRTLOCK=1 else 0x00000000 Related Links SAM C20/C21 Family Data Sheet GCLK - Generic Clock Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 166

16.8.4 Peripheral Channel Control

Name: PCHCTRLm Offset: 0x80 + m*0x04 [m=0..45] Reset: 0x00000000 Property: PAC Write-Protection PCHTRLm controls the settings of Peripheral Channel number m (m=0..45). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 WRTLOCK CHEN GEN[3:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 – WRTLOCK Write Lock After this bit is set to '1', further writes to the PCHCTRLm register will be discarded. The control register of the corresponding Generator n (GENCTRLn), as assigned in PCHCTRLm.GEN, will also be locked. It can only be unlocked by a Power Reset. Note that Generator 0 cannot be locked. Value Description

0 The Peripheral Channel register and the associated Generator register are not locked

1 The Peripheral Channel register and the associated Generator register are locked

Bit 6 – CHEN Channel Enable This bit is used to enable and disable a Peripheral Channel. Value Description

0 The Peripheral Channel is disabled

1 The Peripheral Channel is enabled

Bits 3:0 – GEN[3:0] Generator Selection This bit field selects the Generator to be used as the source of a peripheral clock, as shown in the table below: SAM C20/C21 Family Data Sheet GCLK - Generic Clock Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 167

Table 16-7. Generator Selection Value Description 0x0 Generic Clock Generator 0 0x1 Generic Clock Generator 1 0x2 Generic Clock Generator 2 0x3 Generic Clock Generator 3 0x4 Generic Clock Generator 4 0x5 Generic Clock Generator 5 0x6 Generic Clock Generator 6 0x7 Generic Clock Generator 7 0x8 Generic Clock Generator 8 0x9 - 0xF Reserved Table 16-8. Reset Value after a User Reset or a Power Reset Reset PCHCTRLm.GEN PCHCTRLm.CHEN PCHCTRLm.WRTLOCK Power Reset 0x0 0x0 0x0 User Reset If WRTLOCK = 0 : 0x0 If WRTLOCK = 1: no change If WRTLOCK = 0 : 0x0 If WRTLOCK = 1: no change No change A Power Reset will reset all the PCHCTRLm registers. A User Reset will reset a PCHCTRL if WRTLOCK=0, or else, the content of that PCHCTRL remains unchanged. PCHCTRL register Reset values are shown in the table PCHCTRLm Mapping. Table 16-9. PCHCTRLm Mapping index(m) Name Description

0 GCLK_DPLL FDPLL96M input clock source for reference

1 GCLK_DPLL_32K FDPLL96M 32kHz clock for FDPLL96M internal clock

2 GCLK_EIC EIC

3 GCLK_FREQM_MSR FREQM Measure

4 GCLK_FREQM_REF FREQM Reference

5 GCLK_TSENS TSENS

6 GCLK_EVSYS_CHANNEL_0 EVSYS_CHANNEL_0

7 GCLK_EVSYS_CHANNEL_1 EVSYS_CHANNEL_1

8 GCLK_EVSYS_CHANNEL_2 EVSYS_CHANNEL_2

index(m) Name Description

9 GCLK_EVSYS_CHANNEL_3 EVSYS_CHANNEL_3

10 GCLK_EVSYS_CHANNEL_4 EVSYS_CHANNEL_4

11 GCLK_EVSYS_CHANNEL_5 EVSYS_CHANNEL_5

12 GCLK_EVSYS_CHANNEL_6 EVSYS_CHANNEL_6

13 GCLK_EVSYS_CHANNEL_7 EVSYS_CHANNEL_7

14 GCLK_EVSYS_CHANNEL_8 EVSYS_CHANNEL_8

15 GCLK_EVSYS_CHANNEL_9 EVSYS_CHANNEL_9

16 GCLK_EVSYS_CHANNEL_10 EVSYS_CHANNEL_10

17 GCLK_EVSYS_CHANNEL_11 EVSYS_CHANNEL_11

18 GCLK_SERCOM[0,1,2,3]_SLOW SERCOM[0,1,2,3]_SLOW

19 GCLK_SERCOM0_CORE SERCOM0_CORE

20 GCLK_SERCOM1_CORE SERCOM1_CORE

21 GCLK_SERCOM2_CORE SERCOM2_CORE

22 GCLK_SERCOM3_CORE SERCOM3_CORE

24 GCLK_SERCOM5_SLOW

25 GCLK_SERCOM5_CORE SERCOM5_CORE

26 GCLK_CAN0 CAN0

27 GCLK_CAN1 CAN1

28 GCLK_TCC0, GCLK_TCC1 TCC0,TCC1

29 GCLK_TCC2 TCC2

30 GCLK_TC0, GCLK_TC1 TC0,TC1

31 GCLK_TC2, GCLK_TC3 TC2,TC3

32 GCLK_TC4 TC4

33 GCLK_ADC0 ADC0

34 GCLK_ADC1 ADC1

35 GCLK_SDADC SDADC

36 GCLK_DAC DAC

37 GCLK_PTC PTC

38 GCLK_CCL CCL

index(m) Name Description

40 GCLK_AC AC

41 GCLK_SERCOM6_CORE SERCOM6_CORE

42 GCLK_SERCOM7_CORE SERCOM7_CORE

43 GCLK_TC5 TC5

44 GCLK_TC6 TC6

45 GCLK_TC7 TC7

MCLK – Main Clock

17.1 Overview

The Main Clock (MCLK) controls the synchronous clock generation of the device. Using a clock provided by the Generic Clock Module (GCLK_MAIN), the Main Clock Controller provides synchronous system clocks to the CPU and the modules connected to the AHBx and the APBx bus. The synchronous system clocks are divided into a number of clock domains. Each clock domain can run at different frequencies, enabling the user to save power by running peripherals at a relatively low clock frequency, while maintaining high CPU performance or vice versa. In addition, the clock can be masked for individual modules, enabling the user to minimize power consumption.

17.2 Features

Generates CPU, AHB, and APB system clocks – Clock source and division factor from GCLK – Clock prescaler with 1x to 128x division
Safe run-time clock switching from GCLK
Module-level clock gating through maskable peripheral clocks

17.3 Block Diagram

Figure 17-1. MCLK Block Diagram MAIN CLOCK CONTROLLER CPU GCLK GCLK_MAIN PERIPHERALS CLK_APBx CLK_AHBx CLK_CPU

17.4 Signal Description

Not applicable.

17.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

17.5.1 I/O Lines

17.5.2 Power Management

The MCLK will operate in all sleep modes if a synchronous clock is required in these modes. Related Links 19. PM – Power Manager

17.5.3 Clocks

The MCLK bus clock (CLK_MCLK_APB) can be enabled and disabled in the Main Clock module, and the default state of CLK_MCLK_APB can be found in the Peripheral Clock Masking section. If this clock is disabled, it can only be re-enabled by a reset. The Generic Clock GCLK_MAIN is required to generate the Main Clocks. GCLK_MAIN is configured in the Generic Clock Controller, and can be re-configured by the user if needed. Related Links 16. GCLK - Generic Clock Controller

17.5.3.1 Main Clock

The main clock GCLK_MAIN is the common source for the synchronous clocks. This is fed into the common 8-bit prescaler that is used to generate synchronous clocks to the CPU, AHBx, and APBx modules.

17.5.3.2 CPU Clock

The CPU clock (CLK_CPU) is routed to the CPU. Halting the CPU clock inhibits the CPU from executing instructions.

17.5.3.3 APBx and AHBx Clock

The APBx clocks (CLK_APBx) and the AHBx clocks (CLK_AHBx) are the root clock source used by modules requiring a clock on the APBx and the AHBx bus. These clocks are always synchronous to the CPU clock, and can run even when the CPU clock is turned off in sleep mode. A clock gater is inserted after the common APB clock to gate any APBx clock of a module on APBx bus, as well as the AHBx clock.

17.5.3.4 Clock Domains

The device has these synchronous clock domains:

CPU synchronous clock domain (CPU Clock Domain). Frequency is f CPU. See also the related links for the clock domain partitioning. Related Links

17.5.4 DMA

Not applicable.

17.5.5 Interrupts

The interrupt request line is connected to the Interrupt Controller. Using the MCLK interrupt requires the Interrupt Controller to be configured first.

17.5.6 Events

17.5.7 Debug Operation

When the CPU is halted in debug mode, the MCLK continues normal operation. In sleep mode, the clocks generated from the MCLK are kept running to allow the debugger accessing any module. As a consequence, power measurements are incorrect in debug mode.

17.5.8 Register Access Protection

All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Interrupt Flag register (INTFLAG) Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write- Protection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger. Related Links 11. PAC - Peripheral Access Controller

17.5.9 Analog Connections

Not applicable.

17.6 Functional Description

17.6.1 Principle of Operation

The GCLK_MAIN clock signal from the GCLK module is the source for the main clock, which in turn is the common root for the synchronous clocks for the CPU, APBx, and AHBx modules. The GCLK_MAIN is divided by an 8-bit prescaler. Each of the derived clocks can run from any divided or undivided main clock, ensuring synchronous clock sources for each clock domain. The clock domain (CPU) can be changed on the fly to respond to variable load in the application. The clocks for each module in a clock domain can be masked individually to avoid power consumption in inactive modules. Depending on the sleep mode, some clock domains can be turned off.

17.6.2 Basic Operation

17.6.2.1 Initialization

After a Reset, the default clock source of the GCLK_MAIN clock is started and calibrated before the CPU starts running. The GCLK_MAIN clock is selected as the main clock without any prescaler division. By default, only the necessary clocks are enabled. Related Links

17.6.2.2 Enabling, Disabling, and Resetting

The MCLK module is always enabled and cannot be reset.

17.6.2.3 Selecting the Main Clock Source

Refer to the Generic Clock Controller description for details on how to configure the clock source of the GCLK_MAIN clock. Related Links 16. GCLK - Generic Clock Controller SAM C20/C21 Family Data Sheet MCLK – Main Clock © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 173

17.6.2.4 Selecting the Synchronous Clock Division Ratio

The main clock GCLK_MAIN feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By default, the synchronous clocks run on the undivided main clock. The user can select a prescaler division for the CPU clock domain by writing the Division (DIV) bits in the CPU Clock Division register CPUDIV, resulting in a CPU clock domain frequency determined by this equation: ???? = If the application attempts to write forbidden values in CPUDIV register, registers are written but these bad values are not used and a violation is reported to the PAC module. Division bits (DIV) can be written without halting or disabling peripheral modules. Writing DIV bits allows a new clock setting to be written to all synchronous clocks belonging to the corresponding clock domain at the same time. Figure 17-2. Synchronous Clock Selection and Prescaler Sleep Controller Sleep mode CPUDIV CLK_CPU GCLK GCLKMAIN Clock gate Clock gate Clock gateCLK_AHB_HS clk_ahb_ip0 clk_ahb_ip1 clk_ahb_ipn Clock gate Clock gate CLK_APB_HS clk_apb_ip0 clk_apb_ip1 clk_apb_ipn Clock gate Clock gate PERIPHERALS CPU CPU Clock Domain: fCPU MASK MASK Prescaler

17.6.2.5 Clock Ready Flag

There is a slight delay between writing to CPUDIV until the new clock settings become effective. During this interval, the Clock Ready flag in the Interrupt Flag Status and Clear register INTFLAG.CKRDY) will return zero when read. If CKRDY in the INTENSET register is set to '1', the Clock Ready interrupt will be triggered when the new clock setting is effective. The clock settings (CLKCFG) must not be re-written while INTFLAG. CKRDY reads '0'. The system may become unstable or hang, and a violation is reported to the PAC module. Related Links 11. PAC - Peripheral Access Controller It is possible to disable/enable the AHB or APB clock for a peripheral by writing the corresponding bit in the Clock Mask registers (APBxMASK) to '0'/'1'. The default state of the peripheral clocks is shown here. Table 17-1. Peripheral Clock Default State CPU Clock Domain Peripheral Clock Default State CLK_AC_APB Disabled CLK_ADC0_APB Disabled SAM C20/C21 Family Data Sheet MCLK – Main Clock © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 174

Peripheral Clock Default State CLK_ADC1_APB Disabled CLK_BRIDGE_A_AHB Enabled CLK_BRIDGE_B_AHB Enabled CLK_BRIDGE_C_AHB Enabled CLK_BRIDGE_D_AHB Enabled CLK_CAN0_AHB Disabled CLK_CAN1_AHB Disabled CLK_CCL_APB Disabled CLK_DAC_APB Disabled CLK_DIVAS_AHB Enabled CLK_DMAC_AHB Enabled CLK_DMAC_APB Enabled CLK_DSU_AHB Enabled CLK_DSU_APB Enabled CLK_EIC_APB Enabled CLK_EVSYS_APB Disabled CLK_FREQM_APB Enabled CLK_GCLK_AHB Enabled CLK_HAMATRIX_APB Disabled CLK_MCLK_APB Enabled CLK_MTB_APB Enabled CLK_NVMCTRL_AHB Enabled CLK_NVMCTRL_APB Enabled CLK_OSCCTRL_APB Enabled CLK_OSC32CTRL_APB Enabled CLK_PAC_AHB Enabled CLK_PAC_APB Enabled CLK_PORT_APB Enabled CLK_PTC_APB Disabled CLK_SDADC_APB Disabled SAM C20/C21 Family Data Sheet MCLK – Main Clock © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 175

Peripheral Clock Default State CLK_SERCOM0_APB Disabled CLK_SERCOM1_AHB Disabled CLK_SERCOM2_APB Disabled CLK_SERCOM3_APB Disabled CLK_SERCOM4_APB Disabled CLK_SERCOM5_APB Disabled CLK_SERCOM6_APB Disabled CLK_SERCOM7_APB Disabled CLK_TCC0_APB Disabled CLK_TCC1_APB Disabled CLK_TCC2_APB Disabled CLK_TC0_APB Disabled CLK_TC1_APB Disabled CLK_TC2_APB Disabled CLK_TC3_APB Disabled CLK_TC4_APB Disabled CLK_TC5_APB Disabled CLK_TC6_APB Disabled CLK_TC7_APB Disabled CLK_TSENS_APB Disabled CLK_WDT_APB Enabled Backup Clock Domain Peripheral Clock Default State CLK_OSC32KCTRL_APB Enabled CLK_PM_APB Enabled CLK_SUPC_APB Enabled CLK_RSTC_APB Enabled CLK_RTC_APB Enabled When the APB clock is not provided to a module, its registers cannot be read or written. The module can be re-enabled later by writing the corresponding mask bit to '1'. SAM C20/C21 Family Data Sheet MCLK – Main Clock © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 176

A module may be connected to several clock domains (for instance, AHB and APB), in which case it will have several mask bits. Note that clocks should only be switched off if it is certain that the module will not be used: Switching off the clock for the NVM Controller (NVMCTRL) will cause a problem if the CPU needs to read from the Flash Memory. Switching off the clock to the MCLK module (which contains the mask registers) or the corresponding APBx bridge, will make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset.

17.6.3 DMA Operation

Not applicable.

17.6.4 Interrupts

The peripheral has the following interrupt sources:

Clock Ready (CKRDY): indicates that CPU clocks are ready. This interrupt is a synchronous wake-up source. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear ( INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be enabled individually by writing a '1' to the corresponding enabling bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the corresponding clearing bit in the Interrupt Enable Clear INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the peripheral is reset. An interrupt flag is cleared by writing a '1' to the corresponding bit in the INTFLAG register. Each peripheral can have one interrupt request line per interrupt source or one common interrupt request line for all the interrupt sources.If the peripheral has one common interrupt request line for all the interrupt sources, the user must read the INTFLAG register to determine which interrupt condition is present. Related Links

PM – Power Manager

17.6.5 Events

Not applicable.

17.6.6 Sleep Mode Operation

In IDLE sleep mode, the MCLK is still running on the selected main clock. In STANDBY sleep mode, the MCLK is frozen if no synchronous clock is required. SAM C20/C21 Family Data Sheet MCLK – Main Clock © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 177

17.7 Register Summary

Offset Name Bit Pos. 0x00 CTRLA 7:0 0x01 INTENCLR 7:0 CKRDY 0x02 INTENSET 7:0 CKRDY 0x03 INTFLAG 7:0 CKRDY 0x04 Reserved 0x05 CPUDIV 7:0 CPUDIV[7:0] 0x06 ... 0x0F Reserved 0x10 AHBMASK 7:0 DMAC HSRAM NVMCTRL HMATRIXHS DSU APBC APBB APBA 15:8 PAC CAN1 CAN0 23:16 31:24 0x14 APBAMASK 7:0 GCLK SUPC OSC32KCTR L OSCCTRL RSTC MCLK PM PAC 15:8 TSENS FREQM EIC RTC WDT 23:16 31:24 0x18 APBBMASK 7:0 HMATRIXHS NVMCTRL DSU PORT 15:8 23:16 31:24 0x1C APBCMASK 7:0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS 15:8 TC3 TC2 TC1 TC0 TCC2 TCC1 TCC0 23:16 CCL TC DAC AC SDADC ADC1 ADC0 TC4 31:24 0x20 APBDMASK 7:0 TC7 TC6 TC5 SERCOM7 SERCOM6 15:8 23:16 31:24

17.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers can be write-protected optionally by the Peripheral Access Controller (PAC). This is denoted by the property "PAC Write-Protection" in each individual register description. Refer to the 17.5.8 Register Access Protection for details. SAM C20/C21 Family Data Sheet MCLK – Main Clock © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 178

17.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00 Property: PAC Write-Protection All bits in this register are reserved. Bit 7 6 5 4 3 2 1 0 Access Reset SAM C20/C21 Family Data Sheet MCLK – Main Clock © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 179

17.8.2 Interrupt Enable Clear

Name: INTENCLR Offset: 0x01 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 7 6 5 4 3 2 1 0 CKRDY Access R/W Reset 0 Bit 0 – CKRDY Clock Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Clock Ready Interrupt Enable bit and the corresponding interrupt request. Value Description

0 The Clock Ready interrupt is enabled and will generate an interrupt request when the Clock

17.8.3 Interrupt Enable Set

Name: INTENSET Offset: 0x02 Reset: 0x00 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 7 6 5 4 3 2 1 0 CKRDY Access R/W Reset 0 Bit 0 – CKRDY Clock Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Clock Ready Interrupt Enable bit and enable the Clock Ready interrupt. Value Description 0 The Clock Ready interrupt is disabled. 1 The Clock Ready interrupt is enabled. SAM C20/C21 Family Data Sheet MCLK – Main Clock © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 181

17.8.4 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x03 Reset: 0x01 Property: – Bit 7 6 5 4 3 2 1 0 CKRDY Access R/W Reset 1 Bit 0 – CKRDY Clock Ready This flag is cleared by writing a '1' to the flag. This flag is set when the synchronous CPU, APBx, and AHBx clocks have frequencies as indicated in the CLKCFG registers and will generate an interrupt if INTENCLR/SET.CKRDY is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Clock Ready interrupt flag. SAM C20/C21 Family Data Sheet MCLK – Main Clock © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 182

17.8.5 CPU Clock Division

Name: CPUDIV Offset: 0x05 Reset: 0x01 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CPUDIV[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 1 Bits 7:0 – CPUDIV[7:0] CPU Clock Division Factor These bits define the division ratio of the main clock prescaler related to the CPU clock domain. Frequencies must never exceed the specified maximum frequency for each clock domain. Value Name Description 0x01 DIV1 Divide by 1 0x02 DIV2 Divide by 2 0x04 DIV4 Divide by 4 0x08 DIV8 Divide by 8 0x10 DIV16 Divide by 16 0x20 DIV32 Divide by 32 0x40 DIV64 Divide by 64 0x80 DIV128 Divide by 128 others - Reserved SAM C20/C21 Family Data Sheet MCLK – Main Clock © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 183

17.8.6 AHB Mask

Name: AHBMASK Offset: 0x10 Reset: 0x000003CFF Property: PAC Write-Protection Note: This register is only available for SAMC2x "N" series devices. Bit 31 30 29 28 27 26 25 24 Access R R R R R R Reset 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 PAC CAN1 CAN0 Access R R R R R R/W R/W R/W Reset 0 0 0 0 1 1 0 0 Bit 7 6 5 4 3 2 1 0 DMAC HSRAM NVMCTRL HMATRIXHS DSU APBC APBB APBA Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 13 – APBD APBD AHB Clock Enable Value Description 0 The AHB clock for the APBD is stopped. 1 The AHB clock for the APBD is enabled. Bit 12 – DIVAS DIVAS AHB Clock Enable Value Description 0 The AHB clock for the DIVAS is stopped. 1 The AHB clock for the DIVAS is enabled. Bit 10 – PAC PAC AHB Clock Enable Value Description 0 The AHB clock for the PAC is stopped. 1 The AHB clock for the PAC is enabled. Bit 9 – CAN1 CAN1 AHB Clock Enable Value Description 0 The AHB clock for the CAN1 is stopped. 1 The AHB clock for the CAN1 is enabled. Bit 8 – CAN0 CAN0 AHB Clock Enable SAM C20/C21 Family Data Sheet MCLK – Main Clock © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 184

0 The AHB clock for the CAN0 is stopped. 1 The AHB clock for the CAN0 is enabled. Bit 7 – DMAC DMAC AHB Clock Enable Value Description 0 The AHB clock for the DMAC is stopped. 1 The AHB clock for the DMAC is enabled. Bit 6 – HSRAM HSRAM AHB Clock Enable Value Description 0 The AHB clock for the HSRAM is stopped. 1 The AHB clock for the HSRAM is enabled. Bit 5 – NVMCTRL NVMCTRL AHB Clock Enable Value Description 0 The AHB clock for the NVMCTRL is stopped. 1 The AHB clock for the NVMCTRL is enabled. Bit 4 – HMATRIXHS HMATRIXHS AHB Clock Enable Value Description 0 The AHB clock for the HMATRIXHS is stopped. 1 The AHB clock for the HMATRIXHS is enabled. Bit 3 – DSU DSU AHB Clock Enable Value Description 0 The AHB clock for the DSU is stopped. 1 The AHB clock for the DSU is enabled. Bit 2 – APBC APBC AHB Clock Enable Value Description 0 The AHB clock for the APBC is stopped.

1 The AHB clock for the APBC is enabled

Bit 1 – APBB APBB AHB Clock Enable Value Description 0 The AHB clock for the APBB is stopped. 1 The AHB clock for the APBB is enabled. Bit 0 – APBA APBA AHB Clock Enable Value Description 0 The AHB clock for the APBA is stopped. 1 The AHB clock for the APBA is enabled. SAM C20/C21 Family Data Sheet MCLK – Main Clock © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 185

17.8.7 APBA Mask

Name: APBAMASK Offset: 0x14 Reset: 0x00000FFF Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 TSENS FREQM EIC RTC WDT Access R/W R/W R/W R/W R/W Reset 0 1 1 1 1 Bit 7 6 5 4 3 2 1 0 GCLK SUPC OSC32KCTRL OSCCTRL RSTC MCLK PM PAC Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 12 – TSENS TSENS APBA Clock Enable Value Description 0 The APBA clock for the TSENS is stopped. 1 The APBA clock for the TSENS is enabled. Bit 11 – FREQM FREQM APBA Clock Enable Value Description 0 The APBA clock for the FREQM is stopped. 1 The APBA clock for the FREQM is enabled. Bit 10 – EIC EIC APBA Clock Enable Value Description 0 The APBA clock for the EIC is stopped. 1 The APBA clock for the EIC is enabled. Bit 9 – RTC RTC APBA Clock Enable Value Description 0 The APBA clock for the RTC is stopped. 1 The APBA clock for the RTC is enabled. Bit 8 – WDT WDT APBA Clock Enable SAM C20/C21 Family Data Sheet MCLK – Main Clock © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 186

0 The APBA clock for the WDT is stopped. 1 The APBA clock for the WDT is enabled. Bit 7 – GCLK GCLK APBA Clock Enable Value Description 0 The APBA clock for the GCLK is stopped. 1 The APBA clock for the GCLK is enabled. Bit 6 – SUPC SUPC APBA Clock Enable Value Description 0 The APBA clock for the SUPC is stopped. 1 The APBA clock for the SUPC is enabled. Bit 5 – OSC32KCTRL OSC32KCTRL APBA Clock Enable Value Description 0 The APBA clock for the OSC32KCTRL is stopped. 1 The APBA clock for the OSC32KCTRL is enabled. Bit 4 – OSCCTRL OSCCTRL APBA Clock Enable Value Description 0 The APBA clock for the OSCCTRL is stopped. 1 The APBA clock for the OSCCTRL is enabled. Bit 3 – RSTC RSTC APBA Clock Enable Value Description 0 The APBA clock for the RSTC is stopped. 1 The APBA clock for the RSTC is enabled. Bit 2 – MCLK MCLK APBA Clock Enable Value Description 0 The APBA clock for the MCLK is stopped. 1 The APBA clock for the MCLK is enabled. Bit 1 – PM PM APBA Clock Enable Value Description 0 The APBA clock for the PM is stopped. 1 The APBA clock for the PM is enabled. Bit 0 – PAC PAC APBA Clock Enable Value Description 0 The APBA clock for the PAC is stopped. 1 The APBA clock for the PAC is enabled. SAM C20/C21 Family Data Sheet MCLK – Main Clock © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 187

17.8.8 APBB Mask

Name: APBBMASK Offset: 0x18 Reset: 0x00000007 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 HMATRIXHS NVMCTRL DSU PORT Access R/W R/W R/W R/W Reset 0 1 1 1 Bit 5 – HMATRIXHS HMATRIXHS APBB Clock Enable Value Description

0 The APBB clock for the HMATRIXHS is stopped

1 The APBB clock for the HMATRIXHS is enabled

Bit 2 – NVMCTRL NVMCTRL APBB Clock Enable Value Description

0 The APBB clock for the NVMCTRL is stopped

1 The APBB clock for the NVMCTRL is enabled

Bit 1 – DSU DSU APBB Clock Enable Value Description

0 The APBB clock for the DSU is stopped

1 The APBB clock for the DSU is enabled

Bit 0 – PORT PORT APBB Clock Enable Value Description 0 The APBB clock for the PORT is stopped. 1 The APBB clock for the PORT is enabled. SAM C20/C21 Family Data Sheet MCLK – Main Clock © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 188

17.8.9 APBC Mask

Name: APBCMASK Offset: 0x1C Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 CCL PTC DAC AC SDADC ADC1 ADC0 TC4 Access R/W R/W R R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 TC3 TC2 TC1 TC0 TCC2 TCC1 TCC0 Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 23 – CCL CCL APBC Clock Enable Value Description 0 The APBC clock for the CCL is stopped. 1 The APBC clock for the CCL is enabled. Bit 22 – PTC PTC APBC Mask Clock Enable Value Description 0 The APBC clock for the PTC is stopped. 1 The APBC clock for the PTC is enabled. Bit 21 – DAC DAC APBC Mask Clock Enable Value Description 0 The APBC clock for the DAC is stopped. 1 The APBC clock for the DAC is enabled. Bit 20 – AC AC APBC Clock Enable Value Description 0 The APBC clock for the AC is stopped. 1 The APBC clock for the AC is enabled. Bit 19 – SDADC SDADC APBC Clock Enable SAM C20/C21 Family Data Sheet MCLK – Main Clock © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 189

0 The APBC clock for the SDADC is stopped. 1 The APBC clock for the SDADC is enabled. Bit 18 – ADC1 ADC1 APBC Clock Enable Value Description 0 The APBC clock for the ADC1 is stopped. 1 The APBC clock for the ADC1 is enabled. Bit 17 – ADC0 ADC0 APBC Clock Enable Value Description 0 The APBC clock for the ADC0 is stopped. 1 The APBC clock for the ADC0 is enabled. Bit 16 – TC4 TC4 APBC Mask Clock Enable Bit 15 – TC3 TC3 APBC Mask Clock Enable Value Description 0 The APBC clock for the TC3 is stopped. 1 The APBC clock for the TC3 is enabled. Bit 14 – TC2 TC2 APBC Mask Clock Enable Value Description 0 The APBC clock for the TC2 is stopped. 1 The APBC clock for the TC2 is enabled. Bit 13 – TC1 TC1 APBC Mask Clock Enable Value Description 0 The APBC clock for the TC1 is stopped. 1 The APBC clock for the TC1 is enabled. Bit 12 – TC0 TC0 APBC Mask Clock Enable Value Description 0 The APBC clock for the TC0 is stopped. 1 The APBC clock for the TC0 is enabled. Bit 11 – TCC2 TCC2 APBC Mask Clock Enable Value Description 0 The APBC clock for the TCC2 is stopped. 1 The APBC clock for the TCC2 is enabled. Bit 10 – TCC1 TCC1 APBC Mask Clock Enable Value Description 0 The APBC clock for the TCC1 is stopped. 1 The APBC clock for the TCC1 is enabled. Bit 9 – TCC0 TCC0 APBC Mask Clock Enable Value Description 0 The APBC clock for the TCC0 is stopped. SAM C20/C21 Family Data Sheet MCLK – Main Clock © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 190

1 The APBC clock for the TCC0 is enabled. Bit 6 – SERCOM5 SERCOM5 APBC Mask Clock Enable Value Description 0 The APBC clock for the SERCOM5 is stopped. 1 The APBC clock for the SERCOM5 is enabled. Bit 5 – SERCOM4 SERCOM4 APBC Mask Clock Enable Value Description 0 The APBC clock for the SERCOM4 is stopped. 1 The APBC clock for the SERCOM4 is enabled. Bit 4 – SERCOM3 SERCOM3 APBC Mask Clock Enable Value Description 0 The APBC clock for the SERCOM3 is stopped. 1 The APBC clock for the SERCOM3 is enabled. Bit 3 – SERCOM2 SERCOM2 APBC Mask Clock Enable Value Description 0 The APBC clock for the SERCOM2 is stopped. 1 The APBC clock for the SERCOM2 is enabled. Bit 2 – SERCOM1 SERCOM1 APBC Mask Clock Enable Value Description 0 The APBC clock for the SERCOM1 is stopped. 1 The APBC clock for the SERCOM1 is enabled. Bit 1 – SERCOM0 SERCOM0 APBC Mask Clock Enable Value Description 0 The APBC clock for the SERCOM0 is stopped. 1 The APBC clock for the SERCOM0 is enabled. Bit 0 – EVSYS EVSYS APBC Clock Enable Value Description 0 The APBC clock for the EVSYS is stopped. 1 The APBC clock for the EVSYS is enabled. SAM C20/C21 Family Data Sheet MCLK – Main Clock © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 191

17.8.10 APBD Mask

Name: APBDMASK Offset: 0x20 Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 TC7 TC6 TC5 SERCOM7 SERCOM6 Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 4 – TC7 TC7 APBD Mask Clock Enable Value Description 0 The APBD clock for the TC7 is stopped. 1 The APBD clock for the TC7 is enabled. Bit 3 – TC6 TC6 APBD Mask Clock Enable Value Description 0 The APBD clock for the TC6 is stopped. 1 The APBD clock for the TC6 is enabled. Bit 2 – TC5 TC5 APBd Mask Clock Enable Value Description 0 The APBD clock for the TC5 is stopped. 1 The APBD clock for the TC5 is enabled. Bit 1 – SERCOM7 SERCOM7 APBD Mask Clock Enable Value Description 0 The APBD clock for the SERCOM7 is stopped. 1 The APBD clock for the SERCOM7 is enabled. Bit 0 – SERCOM6 SERCOM6 APBD Mask Clock Enable SAM C20/C21 Family Data Sheet MCLK – Main Clock © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 192

0 The APBD clock for the SERCOM6 is stopped. 1 The APBD clock for the SERCOM6 is enabled. SAM C20/C21 Family Data Sheet MCLK – Main Clock © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 193

RSTC – Reset Controller

18.1 Overview

The Reset Controller (RSTC) manages the reset of the microcontroller. It issues a microcontroller reset, sets the device to its initial state and allows the reset source to be identified by software.

18.2 Features

Reset the microcontroller and set it to an initial state according to the reset source
Reset cause register for reading the reset source from the application code
Multiple reset sources – Power supply reset sources: POR, BODCORE, BODVDD – User reset sources: External reset ( RESET), Watchdog reset, and System Reset Request

18.3 Block Diagram

Figure 18-1. Reset System RESET CONTROLLER BODCORE BODVDD POR WDT RESET RESET SOURCES RTC 32kHz clock sources WDT with ALWAYSON GCLK with WRTLOCK Debug Logic Other ModulesCPU RCAUSE

18.4 Signal Description

Signal Name Type Description RESET Digital input External reset One signal can be mapped on several pins. Related Links 6. I/O Multiplexing and Considerations

18.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below. SAM C20/C21 Family Data Sheet RSTC – Reset Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 194

18.5.1 I/O Lines

Not applicable.

18.5.2 Power Management

The Reset Controller module is always on.

18.5.3 Clocks

The RSTC bus clock (CLK_RSTC_APB) can be enabled and disabled in the Main Clock Controller. Related Links 17. MCLK – Main Clock

18.5.4 DMA

Not applicable.

18.5.5 Interrupts

Not applicable.

18.5.6 Events

Not applicable.

18.5.7 Debug Operation

When the CPU is halted in debug mode, the RSTC continues normal operation.

18.5.8 Register Access Protection

18.5.9 Analog Connections

Not applicable.

18.6 Functional Description

18.6.1 Principle of Operation

The Reset Controller collects the various Reset sources and generates Reset for the device.

18.6.2 Basic Operation

18.6.2.1 Initialization

After a power-on Reset, the RSTC is enabled and the Reset Cause (RCAUSE) register indicates the POR source.

18.6.2.2 Enabling, Disabling, and Resetting

18.6.2.3 Reset Causes and Effects

The latest Reset cause is available in RCAUSE register, and can be read during the application boot sequence in order to determine proper action. These are the groups of Reset sources:

Power supply Reset: Resets caused by an electrical issue. It covers POR and BODs Resets
User Reset: Resets caused by the application. It covers external Resets, system Reset requests and watchdog Resets The following table lists the parts of the device that are reset, depending on the Reset type. Table 18-1. Effects of the Different Reset Causes Power Supply Reset User Reset POR, BODVDD, BODCORE External Reset WDT Reset, System Reset Request RTC, OSC32KCTRL, RSTC Y N N GCLK with WRTLOCK Y N N Debug logic Y Y N Others Y Y Y The external Reset is generated when pulling the RESET pin low. The POR, BODCORE, and BODVDD Reset sources are generated by their corresponding module in the Supply Controller Interface (SUPC). The WDT Reset is generated by the Watchdog Timer. The System Reset Request is a Reset generated by the CPU when asserting the SYSRESETREQ bit located in the Reset Control register of the CPU (for details refer to the ARM Cortex Technical Reference Manual on http://www.arm.com). Note: Refer to the External Reset Characteristics table in the Timing Characteristics section of the Electrical Characteristics chapter. Related Links 23. WDT – Watchdog Timer 22. SUPC – Supply Controller

18.6.3 Additional Features

Not applicable.

18.6.4 DMA Operation

Not applicable.

18.6.5 Interrupts

Not applicable.

18.6.6 Events

18.6.7 Sleep Mode Operation

18.7 Register Summary

Offset Name Bit Pos. 0x00 RCAUSE 7:0 SYST WDT EXT BODVDD BODCORE POR

18.8 Register Description

18.8.1 Reset Cause

Name: RCAUSE Offset: 0x00 Property: – When a Reset occurs, the bit corresponding to the Reset source is set to '1' and all other bits are written to '0'. Bit 7 6 5 4 3 2 1 0 SYST WDT EXT BODVDD BODCORE POR Access R R R R R R Reset x x x x x x Bit 6 – SYST System Reset Request This bit is set if a System Reset Request has occurred. Refer to the Cortex processor documentation for more details. Bit 5 – WDT Watchdog Reset This bit is set if a Watchdog Timer Reset has occurred. Bit 4 – EXT External Reset This bit is set if an external Reset has occurred. Bit 2 – BODVDD Brown Out VDD Detector Reset This bit is set if a BODVDD Reset has occurred. Bit 1 – BODCORE Brown Out CORE Detector Reset This bit is set if a BODCORE Reset has occurred. Bit 0 – POR Power On Reset This bit is set if a POR has occurred. SAM C20/C21 Family Data Sheet RSTC – Reset Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 199

PM – Power Manager Related Links

34.6.9 Sleep Mode Operation

19.1 Overview

The Power Manager (PM) controls the sleep modes of the device. Various sleep modes are provided in order to fit power consumption requirements. This enables the PM to stop unused modules in order to save power. In active mode, the CPU is executing application code. When the device enters a sleep mode, program execution is stopped and some modules and clock domains are automatically switched off by the PM according to the sleep mode. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals and all enabled reset sources can restore the device from a sleep mode to active mode.

19.2 Features

Power management control – Sleep modes: Idle, Standby

19.3 Block Diagram

Figure 19-1. PM Block Diagram SLEEP MODE CONTROLLER POWER MANAGER SUPPLY CONTROLLER MAIN CLOCK CONTROLLER SLEEPCFG POWER DOMAIN CONTROLLER STDBYCFG

19.4 Signal Description

Not applicable.

19.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

19.5.1 I/O Lines

Not applicable.

19.5.2 Clocks

The PM bus clock (CLK_PM_APB) can be enabled and disabled in the Main Clock module. If this clock is disabled, it can only be re-enabled by a system reset. SAM C20/C21 Family Data Sheet PM – Power Manager © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 200

19.5.3 DMA

Not applicable.

19.5.4 Interrupts

The interrupt request line is connected to the interrupt controller. Using the PM interrupt requires the interrupt controller to be configured first.

19.5.5 Events

Not applicable.

19.5.6 Debug Operation

When the CPU is halted in debug mode, the PM continues normal operation. If standby sleep mode is requested by the system while in debug mode, the power domains are not turned off. As a consequence, power measurements while in debug mode are not relevant. Hot plugging in standby mode is supported.

19.5.7 Register Access Protection

Registers with write-access can be write-protected optionally by the peripheral access controller (PAC). Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger.

19.5.8 Analog Connections

Not applicable.

19.6 Functional Description

19.6.1 Terminology

The following is a list of terms used to describe the Power Managemement features of this microcontroller.

19.6.1.1 Sleep Modes

The device can be set in a sleep mode. In sleep mode, the CPU is stopped and the peripherals are either active or idle, according to the sleep mode depth:

Idle sleep mode: The CPU is stopped. Synchronous clocks are stopped except when requested. The logic is retained.
Standby sleep mode: The CPU is stopped as well as the peripherals.

19.6.2 Principle of Operation

In active mode, all clock domains and power domains are active, allowing software execution and peripheral operation. The PM Sleep Mode Controller allows to save power by choosing between different sleep modes depending on application requirements, see 19.6.3.3 Sleep Mode Controller. The PM Power Domain Controller allows to reduce the power consumption in standby mode even further.

19.6.3 Basic Operation

19.6.3.1 Initialization

19.6.3.2 Enabling, Disabling and Resetting

The PM is always enabled and can not be reset. A Sleep mode is entered by executing the Wait For Interrupt instruction (WFI). The Sleep Mode bits in the Sleep Configuration register (SLEEPCFG.SLEEPMODE) select the level of the sleep mode. Note: A small latency happens between the store instruction and actual writing of the SLEEPCFG register due to bridges. Software must ensure that the SLEEPCFG register reads the desired value before issuing a WFI instruction. Table 19-1. Sleep Mode Entry and Exit Table Mode Mode Entry Wake-Up Sources IDLE SLEEPCFG.SLEEPMODE = IDLE Synchronous (2) (APB, AHB), asynchronous (1) STANDBY SLEEPCFG.SLEEPMODE = STANDBY Synchronous (3), Asynchronous Note: 1. Asynchronous: interrupt generated on generic clock, external clock, or external event. 2. Synchronous: interrupt generated on the APB clock. 3. Synchronous interrupt only for peripherals configured to run in standby. Note: The type of wake-up sources (synchronous or asynchronous) is given in each module interrupt section. The sleep modes (idle, standby) and their effect on the clocks activity, the regulator and the NVM state are described in the table and the sections below. Table 19-2. Sleep Mode Overview Mode CPU clock AHB clock APB clock Main clock GCLK clocks Oscillators Regulator RAM ONDEMAND = 0 ONDEMAND = 1 IDLE Stop Stop (2) Stop(2) Run Run (1) Run Run if requested Main Normal STANDBY Stop Stop (2) Stop(2) Stop Stop (2) Run if requested or RUNSTDBY=1 Run if requested LPVREG (3) Low power(4) Note: 1. Running if requested by peripheral. 2. Running during SleepWalking. 3. Regulator state is programmable by using STDBYCFG.VREGSMOD bits. 4. RAM state is programmable by using STDBYCFG.BBIASHS bit.

19.6.3.3.1 IDLE Mode

The IDLE mode allows power optimization with the fastest wake-up time. The CPU is stopped. To further reduce power consumption, the user can disable the clocking of modules and clock sources by configuring the SLEEPCFG bit group to IDLE. The peripheral will be halted regardless of the bit settings of the mask registers in the MCLK (MCLK.AHBMASK, MCLK.APBxMASK).

Entering IDLE mode: The IDLE mode is entered by executing the WFI instruction. Additionally, if the SLEEPONEXIT bit in the ARM Cortex System Control register (SCR) is set, the IDLE mode will also be entered when the CPU exits the lowest priority ISR. This mechanism can be useful for SAM C20/C21 Family Data Sheet PM – Power Manager © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 202

applications that only require the processor to run when an interrupt occurs. Before entering the IDLE mode, the user must configure the Sleep Configuration register.

Exiting IDLE mode: The processor wakes the system up when it detects any non-masked interrupt with sufficient priority to cause exception entry. The system goes back to the ACTIVE mode. The CPU and affected modules are restarted. Regulator operates in normal mode.

19.6.3.3.2 STANDBY Mode

The STANDBY mode is the lowest power configuration while keeping the state of the logic and the content of the RAM. In this mode, all clocks are stopped except those which are kept running if requested by a running peripheral or have the ONDEMAND bit written to "0". For example, the RTC can operate in STANDBY mode. In this case, its GCLK clock source will also be enabled. All features that don’t require CPU intervention are supported in STANDBY mode. Here are examples:

Autonomous peripherals features.
Features relying on Event System allowing autonomous communication between peripherals.
Features relying on on-demand clock.
DMA transfers.
Entering STANDBY mode: This mode is entered by executing the WFI instruction with the SLEEPCFG register written to STANDBY. The SLEEPONEXIT feature is also available as in IDLE mode.
Exiting STANDBY mode: Any peripheral able to generate an asynchronous interrupt can wake up the system. For example, a peripheral running on a GCLK clock can trigger an interrupt. When the enabled asynchronous wake-up event occurs and the system is woken up, the device will either execute the interrupt service routine or continue the normal program execution according to the Priority Mask Register (PRIMASK) configuration of the CPU. Depending on the configuration of these modules, the current consumption of the device in STANDBY mode can be slightly different. The regulator operates in low-power mode (LP VREG) by default and can switch automatically to the main regulator if a task required by a peripheral requires more power. It returns automatically in the low power mode as soon as the task is completed.

19.6.4 Advanced Features

19.6.4.1 RAM Automatic Low Power Mode

The RAM is by default put in low power mode (back-biased) if the device is in standby sleep mode. This behavior can be changed by configuring the Back Bias bit in the Standby Configuration register (STDBYCFG.BBIASHS), refer to the table below for details. Note: In standby sleep mode, the RAM is put in low-power mode by default. This means that the RAM is back-biased, and the DMAC cannot access it. The DMAC can only access the RAM when it is not back biased (PM.STDBYCFG.BBIASxx=0x0). Table 19-3. RAM Back-Biasing Mode STBYCDFG.BBIASHS RAM 0x0 No Back Biasing RAM is not back-biased if the device is in standby sleep mode. SAM C20/C21 Family Data Sheet PM – Power Manager © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 203

STBYCDFG.BBIASHS RAM 0x1 Standby Back Biasing mode RAM is back-biased if the device is in standby sleep mode.

19.6.4.2 Regulator Automatic Low Power Mode

In standby mode, the PM selects either the main or the low power voltage regulator to supply the VDDCORE. By default the low power voltage regulator is used. If a sleepwalking task is working on either asynchronous clocks (generic clocks) or synchronous clock (APB/AHB clocks), the main voltage regulator is used. This behavior can be changed by writing the Voltage Regulator Standby Mode bits in the Standby Configuration register (STDBYCFG.VREGSMOD). Refer to the following table for details. Table 19-4. Regulator State in Sleep Mode Sleep Mode STDBYCFG. VREGSMOD SleepWalking Regulator state for VDDCORE Active - - main voltage regulator Idle - - main voltage regulator Standby 0x0: AUTO NO low power regulator YES main voltage regulator 0x1: PERFORMANCE - main voltage regulator 0x2: LP - low power regulator

19.6.5 DMA Operation

Not applicable.

19.6.6 Interrupts

Not applicable.

19.6.7 Events

Not applicable.

19.6.8 Sleep Mode Operation

19.7 Register Summary

Offset Name Bit Pos. 0x01 SLEEPCFG 7:0 SLEEPMODE[2:0] 0x02 ... 0x07 Reserved 0x08 STDBYCFG 7:0 VREGSMOD[1:0] 15:8 BBIASHS

19.8 Register Description

19.8.1 Sleep Configuration

Name: SLEEPCFG Offset: 0x01 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 SLEEPMODE[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 2:0 – SLEEPMODE[2:0] Sleep Mode Note: A small latency happens between the store instruction and actual writing of the SLEEPCFG register due to bridges. Software has to make sure the SLEEPCFG register reads the wanted value before issuing Wait For Interrupt (WFI) instruction. Value Name Definition 0x0 0x1 0x2 IDLE 0x3 Reserved Reserved 0x4 STANDBY 0x5 - 0x7 Reserved Reserved SAM C20/C21 Family Data Sheet PM – Power Manager © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 206

19.8.2 Standby Configuration

Name: STDBYCFG Offset: 0x08 Reset: 0x0400 Property: PAC Write-Protection Bit 15 14 13 12 11 10 9 8 BBIASHS Access R/W Reset 1 Bit 7 6 5 4 3 2 1 0 VREGSMOD[1:0] Access R/W R/W Reset 0 0 Bit 10 – BBIASHS Back Bias for HMCRAMCHS Refer to 19.6.4.1 RAM Automatic Low Power Mode for details. Value Description

0 No Back Biasing Mode

1 Standby Back Biasing Mode

Bits 7:6 – VREGSMOD[1:0] VREG Switching Mode Refer to for 19.6.4.2 Regulator Automatic Low Power Mode details. Value Name Description 0x0 AUTO Automatic Mode 0x1 PERFORMANCE Performance oriented 0x2 LP Low Power consumption oriented 0x9 Reserved Reserved SAM C20/C21 Family Data Sheet PM – Power Manager © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 207

OSCCTRL – Oscillators Controller

20.1 Overview

The Oscillators Controller (OSCCTRL) provides a user interface to the XOSC, OSC48M and FDPLL96M. Through the interface registers, it is possible to enable, disable, calibrate, and monitor the OSCCTRL oscillators. All oscillators statuses are collected in the Status register (STATUS). They can additionally trigger interrupts upon status changes via the INTENSET, INTENCLR, and INTFLAG registers. Related Links

20.8.1 INTENCLR

20.8.2 INTENSET

20.8.3 INTFLAG

20.8.4 STATUS

20.2 Features

0.4-32MHz Crystal Oscillator (XOSC) – Tunable gain control – Programmable start-up time – Crystal or external input clock on XIN I/O – Clock failure detection with safe clock switch – Clock failure event output
48MHz Internal Oscillator (OSC48M) – Fast start-up – Programmable start-up time – 4-bit linear divider available
Fractional Digital Phase Locked Loop (FDPLL96M) – 48MHz to 96MHz output frequency – 32kHz to 2MHz reference clock – A selection of sources for the reference clock – Adjustable proportional integral controller – Fractional part used to achieve 1/16th of reference clock step SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 208

20.3 Block Diagram

Figure 20-1. OSCCTRL Block Diagram OSCILLATORS CONTROL STATUS INTERRUPTS GENERATOR Interrupts OSCCTRL XINXOUT XOSC DPLL96M OSC48M CLK_XOSC CLK_DPLL CLK_OSC48M CFD CFD Event register

20.4 Signal Description

XIN Multipurpose Crystal Oscillator or external clock generator input Analog input XOUT Multipurpose Crystal Oscillator output Analog output The I/O lines are automatically selected when XOSC is enabled.

20.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

20.5.1 I/O Lines

I/O lines are configured by OSCCTRL when XOSC is enabled, and need no user configuration.

20.5.2 Power Management

The OSCCTRL can continue to operate in any sleep mode where the selected source clock is running. The OSCCTRL interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes. Related Links 19. PM – Power Manager

20.5.3 Clocks

The OSCCTRL gathers controls for all device oscillators and provides clock sources to the Generic Clock Controller (GCLK). The available clock sources are: XOSC, OSC48M and FDPLL96M. The OSCCTRL bus clock (CLK_OSCCTRL_APB) can be enabled and disabled in the Main Clock module (MCLK). SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 209

The OSC48M control logic uses the oscillator output, which is also asynchronous to the user interface clock (CLK_OSCCTRL_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to 20.6.9 Synchronization for further details. Related Links 17. MCLK – Main Clock

20.5.4 DMA

Not applicable.

20.5.5 Interrupts

The interrupt request line is connected to the Interrupt Controller. Using the OSCCTRL interrupts requires the interrupt controller to be configured first. Related Links

20.5.6 Events

The events of this peripheral are connected to the Event System. Related Links 29. EVSYS – Event System

20.5.7 Debug Operation

When the CPU is halted in debug mode the OSCCTRL continues normal operation. If the OSCCTRL is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging.

20.5.8 Register Access Protection

All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Interrupt Flag Status and Clear register (INTFLAG) Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. Write-protection does not apply for accesses through an external debugger.

20.5.9 Analog Connections

The 0.4-32MHz crystal must be connected between the XIN and XOUT pins, along with any required load capacitors.

20.6 Functional Description

20.6.1 Principle of Operation

XOSC, OSC48M, and FDPLL96M. are configured via OSCCTRL control registers. Through this interface, the oscillators are enabled, disabled, or have their calibration values updated. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 210

The Status register gathers different status signals coming from the oscillators controlled by the OSCCTRL. The status signals can be used to generate system interrupts, and in some cases wake the system from Sleep mode, provided the corresponding interrupt is enabled.

20.6.2 External Multipurpose Crystal Oscillator (XOSC) Operation

The XOSC can operate in two different modes:

External clock, with an external clock signal connected to the XIN pin
Crystal oscillator, with an external 0.4-32MHz crystal The XOSC can be used as a clock source for generic clock generators. This is configured by the Generic Clock Controller. At reset, the XOSC is disabled, and the XIN/XOUT pins can be used as General Purpose I/O (GPIO) pins or by other peripherals in the system. When XOSC is enabled, the operating mode determines the GPIO usage. When in crystal oscillator mode, the XIN and XOUT pins are controlled by the OSCCTRL, and GPIO functions are overridden on both pins. When in external clock mode, only the XIN pin will be overridden and controlled by the OSCCTRL, while the XOUT pin can still be used as a GPIO pin. The XOSC is enabled by writing a '1' to the Enable bit in the External Multipurpose Crystal Oscillator Control register (XOSCCTRL.ENABLE). To enable XOSC as an external crystal oscillator, the XTAL Enable bit (XOSCCTRL.XTALEN) must be written to '1'. If XOSCCTRL.XTALEN is zero, the external clock input on XIN will be enabled. When in crystal oscillator mode (XOSCCTRL.XTALEN=1), the External Multipurpose Crystal Oscillator Gain (XOSCCTRL.GAIN) must be set to match the external crystal oscillator frequency. If the External Multipurpose Crystal Oscillator Automatic Amplitude Gain Control (XOSCCTRL.AMPGC) is '1', the oscillator amplitude will be automatically adjusted, and in most cases result in a lower power consumption. The XOSC will behave differently in different sleep modes, based on the settings of XOSCCTRL.RUNSTDBY, XOSCCTRL.ONDEMAND, and XOSCCTRL.ENABLE. If XOSCCTRL.ENABLE=0, the XOSC will be always stopped. For XOSCCTRL.ENABLE=1, this table is valid: Table 20-1. XOSC Sleep Behavior CPU Mode XOSCCTRL.RUNST DBY XOSCCTRL.ONDEM AND Sleep Behavior Active or Idle - 0 Always run Active or Idle - 1 Run if requested by peripheral Standby 1 0 Always run Standby 1 1 Run if requested by peripheral Standby 0 - Run if requested by peripheral After a hard reset, or when waking up from a sleep mode where the XOSC was disabled, the XOSC will need a certain amount of time to stabilize on the correct frequency. This start-up time can be configured by changing the Oscillator Start-Up Time bit group (XOSCCTRL.STARTUP) in the External Multipurpose Crystal Oscillator Control register. During the start-up time, the oscillator output is masked to ensure that no unstable clock propagates to the digital logic. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 211

The External Multipurpose Crystal Oscillator Ready bit in the Status register (STATUS.XOSCRDY) is set once the external clock or crystal oscillator is stable and ready to be used as a clock source. An interrupt is generated on a zero-to-one transition on STATUS.XOSCRDY if the External Multipurpose Crystal Oscillator Ready bit in the Interrupt Enable Set register (INTENSET.XOSCRDY) is set. Related Links 16. GCLK - Generic Clock Controller

20.6.3 Clock Failure Detection Operation

The Clock Failure Detector (CFD) allows the user to monitor the external clock or crystal oscillator signal provided by the external oscillator (XOSC). The CFD detects failing operation of the XOSC clock with reduced latency, and allows to switch to a safe clock source in case of clock failure. The user can also switch from the safe clock back to XOSC in case of recovery. The safe clock is derived from the OSC48M oscillator with a configurable prescaler. This allows to configure the safe clock in order to fulfill the operative conditions of the microcontroller. In sleep modes, CFD operation is automatically disabled when the external oscillator is not requested to run by a peripheral. See the Sleep Behavior table above when this is the case. The user interface registers allow to enable, disable, and configure the CFD. The Status register provides status flags on failure and clock switch conditions. The CFD can optionally trigger an interrupt or an event when a failure is detected. Clock Failure Detection The CFD is disabled at reset. The CFD does not monitor the XOSC clock when the oscillator is disabled (XOSCCTRL.ENABLE=0). Before starting CFD operation, the user must start and enable the safe clock source (OSC48M oscillator). CFD operation is started by writing a '1' to the CFD Enable bit in the External Oscillator Control register (XOCCTRL.CFDEN). After starting or restarting the XOSC, the CFD does not detect failure until the start- up time has elapsed. The start-up time is configured by the Oscillator Start-Up Time in the External Multipurpose Crystal Oscillator Control register (XOSCCTRL.STARTUP). Once the XOSC Start-Up Time is elapsed, the XOSC clock is constantly monitored. During a period of 4 safe clocks (monitor period), the CFD watches for a clock activity from the XOSC. There must be at least one rising and one falling XOSC clock edge during 4 safe clock periods to meet non-failure conditions. If no or insufficient activity is detected, the failure status is asserted: The Clock Failure Detector status bit in the Status register (STATUS.CLKFAIL) and the Clock Failure Detector interrupt flag bit in the Interrupt Flag register (INTFLAG.CLKFAIL) are set. If the CLKFAIL bit in the Interrupt Enable Set register (INTENSET.CLKFAIL) is set, an interrupt is generated as well. If the Event Output enable bit in the Event Control register (EVCTRL.CFDEO) is set, an output event is generated, too. After a clock failure was issued the monitoring of the XOSC clock is continued, and the Clock Failure Detector status bit in the Status register (STATUS.CLKFAIL) reflects the current XOSC activity. Clock Switch When a clock failure is detected, the XOSC clock is replaced by the safe clock in order to maintain an active clock during the XOSC clock failure. The safe clock source is the OSC48M oscillator clock. The safe clock source can be scaled down by a configurable prescaler to ensure that the safe clock frequency does not exceed the operating conditions selected by the application. When the XOSC clock is switched to the safe clock, the Clock Switch bit in the Status register (STATUS.CLKSW) is set. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 212

When the CFD has switched to the safe clock, the XOSC is not disabled. If desired, the application must take the necessary actions to disable the oscillator. The application must also take the necessary actions to configure the system clocks to continue normal operations. In the case the application can recover the XOSC, the application can switch back to the XOSC clock by writing a '1' to Switch Back Enable bit in the Clock Failure Control register (XOSCCTRL.SWBACK). Once the XOSC clock is switched back, the Switch Back bit (XOSCCTRL.SWBACK) is cleared by hardware. Prescaler The CFD has an internal configurable prescaler to generate the safe clock from the OSC48M oscillator. The prescaler size allows to scale down the OSC48M oscillator so the safe clock frequency is not higher than the XOSC clock frequency monitored by the CFD. The division factor is 2^P, with P being the value of the CFD Prescaler bits in the CFD Prescaler Register (CFDPRESC.CFDPRESC). Example 20-1. Example For an external crystal oscillator at 0.4MHz and the OSC48M frequency at 16MHz, the CFDPRESC.CFDPRESC value should be set scale down by more than factor 16/0.4=80, e.g. to 128, for a safe clock of adequate frequency. Event If the Event Output Enable bit in the Event Control register (EVCTRL.CFDEO) is set, the CFD clock failure will be output on the Event Output. When the CFD is switched to the safe clock, the CFD clock failure will not be output on the Event Output. Sleep Mode The CFD is halted depending on configuration of the XOSC and the peripheral clock request. For further details, refer to the Sleep Behavior table above. The CFD interrupt can be used to wake up the device from sleep modes. 20.6.4 48MHz Internal Oscillator (OSC48M) Operation The OSC48M is an internal oscillator operating in open-loop mode and generating 48MHz frequency. The OSC48M frequency is selected by writing to the Division Factor field in the OSC48MDIV register (OSC48MDIV.DIV). OSC48M is enabled by writing '1' to the Oscillator Enable bit in the OSC48M Control register (OSC48MCTRL.ENABLE), and disabled by writing a '0' to this bit. After enabling OSC48M, the OSC48M clock is output as soon as the oscillator is ready (STATUS.OSC48MRDY=1). User must ensure that the OSC48M is fully disabled before enabling it by reading STATUS.OSC48MRDY=0. After reset, OSC48M is enabled and serves as the default clock source at 4MHz. OSC48M will behave differently in different sleep modes based on the settings of OSC48MCTRL.RUNSTDBY, OSC48MCTRL.ONDEMAND, and OSC48MCTRL.ENABLE. If OSC48MCTRL.ENABLE=0, the OSC48M will be always stopped. For OSC48MCTRL.ENABLE=1, this table is valid: Table 20-2. OSC48M Sleep Behavior CPU Mode OSC48MCTRL.RUN STDBY OSC48MCTRL.OND EMAND Sleep Behavior Active or Idle - 0 Always run SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 213

CPU Mode OSC48MCTRL.RUN STDBY OSC48MCTRL.OND EMAND Sleep Behavior Active or Idle - 1 Run if requested by peripheral Standby 1 0 Always run Standby 1 1 Run if requested by peripheral Standby 0 - Run if requested by peripheral After a hard reset, or when waking up from a sleep mode where the OSC48M was disabled, the OSC48M will need a certain amount of time to stabilize on the correct frequency. This start-up time can be configured by changing the Oscillator Start-Up Delay bit group (OSC48MSTUP.STARTUP) in the OSC48M Startup register. During the start-up time, the oscillator output is masked to ensure that no unstable clock propagates to the digital logic. The OSC48M Ready bit in the Status register (STATUS.OSC48MRDY) is set when the oscillator is stable and ready to be used as a clock source. An interrupt is generated on a zero-to-one transition on STATUS.OSC48MRDY if the OSC48M Ready bit in the Interrupt Enable Set register (INTENSET.OSC48MRDY) is set. Faster start-up times are achievable by selecting shorter delays. However, the oscillator frequency may not stabilize within tolerances when short delays are used. If a fast start-up time is desired at the expense of initial accuracy, the division factor should be set to two or higher (OSC48MDIV.DIV > 0). The OSC48M is used as a clock source for the generic clock generators. Related Links 16. GCLK - Generic Clock Controller

20.6.5 Digital Phase Locked Loop (DPLL) Operation

The task of the DPLL is to maintain coherence between the input (reference) signal and the respective output frequency, CLK_DPLL, via phase comparison. The DPLL controller supports three independent sources of reference clocks:

XOSC32K: this clock is provided by the 32K External Crystal Oscillator (XOSC32K).
XOSC: this clock is provided by the External Multipurpose Crystal Oscillator (XOSC).
GCLK: this clock is provided by the Generic Clock Controller. When the controller is enabled, the relationship between the reference clock frequency and the output clock frequency is: ?CK = ?CKR × LDR + ͳ +LDRFRAC ͳ͸ × ͳ ʹPRESC Where fCK is the frequency of the DPLL output clock, LDR is the loop divider ratio integer part, LDRFRAC is the loop divider ratio fractional part, fCKR is the frequency of the selected reference clock, and PRESC is the output prescaler value. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 214

Figure 20-2. DPLL Block Diagram XIN XOUT XOSC XIN32 XOUT32 XOSC32K GCLK DIVIDER DPLLCTRLB.DIV DPLLCTRLB.REFCLK DIGITAL FILTERTDC DPLLCTRLB.FILTER DCO CKDIV4 CKDIV2 CKDIV1 DPLLPRESC CLK_DPLL RATIO DPLLRATIO CK CKR CG When the controller is disabled, the output clock is low. If the Loop Divider Ratio Fractional part bit field in the DPLL Ratio register (DPLLRATIO.LDRFRAC) is zero, the DPLL works in integer mode. Otherwise, the fractional mode is activated. Note that the fractional part has a negative impact on the jitter of the DPLL. Example (integer mode only): assuming FCKR = 32kHz and FCK = 48MHz, the multiplication ratio is 1500. It means that LDR shall be set to 1499. Example (fractional mode): assuming FCKR = 32kHz and FCK = 48.006MHz, the multiplication ratio is 1500.1875 (1500 + 3/16). Thus LDR is set to 1499 and LDRFRAC to 3. Related Links 16. GCLK - Generic Clock Controller 21. OSC32KCTRL – 32KHz Oscillators Controller

20.6.5.1 Basic Operation

20.6.5.1.1 Initialization, Enabling, Disabling, and Resetting

The DPLLC is enabled by writing a '1' to the Enable bit in the DPLL Control A register (DPLLCTRLA.ENABLE). The DPLLC is disabled by writing a zero to this bit. The DPLLSYNCBUSY.ENABLE is set when the DPLLCTRLA.ENABLE bit is modified. It is cleared when the DPLL output clock CK has sampled the bit at the high level after enabling the DPLL. When disabling the DPLL, DPLLSYNCBUSY.ENABLE is cleared when the output clock is no longer running. Figure 20-3. Enable Synchronization Busy Operation ENABLE CK SYNCBUSY.ENABLE CLK_APB_OSCCTRL The frequency of the DPLL output clock CK is stable when the module is enabled and when the Lock bit in the DPLL Status register is set (DPLLSTATUS.LOCK). When the Lock Time bit field in the DPLL Control B register (DPLLCTRLB.LTIME) is non-zero, a user defined lock time is used to validate the lock operation. In this case the lock time is constant. If DPLLCTRLB.LTIME=0, the lock signal is linked with the status bit of the DPLL, and the lock time varies depending on the filter selection and the final target frequency. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 215

When the Wake Up Fast bit (DPLLCTRLB.WUF) is set, the wake up fast mode is activated. In this mode the clock gating cell is enabled at the end of the startup time. At this time the final frequency is not stable, as it is still during the acquisition period, but it allows to save several milliseconds. After first acquisition, the Lock Bypass bit (DPLLCTRLB.LBYPASS) indicates if the lock signal is discarded from the control of the clock gater (CG) generating the output clock CLK_DPLL. Table 20-3. CLK_DPLL Behavior from Startup to First Edge Detection WUF LTIME CLK_DPLL Behavior 0 0 Normal Mode: First Edge when lock is asserted 0 Not Equal To Zero Lock Timer Timeout mode: First Edge when the timer down-counts to 0.

1 X Wake Up Fast Mode: First Edge when CK is active (startup time)

Table 20-4. CLK_DPLL Behavior after First Edge Detection LBYPASS CLK_DPLL Behavior 0 Normal Mode: the CLK_DPLL is turned off when lock signal is low. 1 Lock Bypass Mode: the CLK_DPLL is always running, lock is irrelevant. Figure 20-4. CK and CLK_DPLL Output from DPLL Off Mode to Running Mode CKR ENABLE CK LOCK CK STABLEtstartup_time tlock_time CLK_DPLL

20.6.5.1.2 Reference Clock Switching

When a software operation requires reference clock switching, the recommended procedure is to turn the DPLL into the standby mode, modify the DPLLCTRLB.REFCLK to select the desired reference source, and activate the DPLL again.

20.6.5.1.3 Output Clock Prescaler

The DPLL controller includes an output prescaler. This prescaler provides three selectable output clocks CK, CKDIV2 and CKDIV4. The Prescaler bit field in the DPLL Prescaler register (DPLLPRESC.PRESC) is used to select a new output clock prescaler. When the prescaler field is modified, the DPLLSYNCBUSY.DPLLPRESC bit is set. It will be cleared by hardware when the synchronization is over. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 216

Figure 20-5. Output Clock Switching Operation CKR PRESC CLK_DPLL DPLL_LOCK 0 1 CK STABLECK STABLE CK SWITCHING SYNCBUSY .PRESC CK CKDIV2

20.6.5.1.4 Loop Divider Ratio Updates

The DPLL Controller supports on-the-fly update of the DPLL Ratio Control (DPLLRATIO) register, allowing to modify the loop divider ratio and the loop divider ratio fractional part when the DPLL is enabled. STATUS.DPLLLDRTO is set when the DPLLRATIO register has been modified and the DPLL analog cell has successfully sampled the updated value. At that time the DPLLSTATUS.LOCK bit is cleared and set again by hardware when the output frequency reached a stable state. Figure 20-6. RATIOCTRL register update operation CKR LDR LDRFRAC CK CLK_DPLL mult0 mult1 LOCK LOCKL

20.6.5.1.5 Digital Filter Selection

The PLL digital filter (PI controller) is automatically adjusted in order to provide a good compromise between stability and jitter. Nevertheless a software operation can override the filter setting using the Filter bit field in the DPLL Control B register (DPLLCTRLB.FILTER). The Low Power Enable bit (DPLLCTRLB.LPEN) can be use to bypass the Time to Digital Converter (TDC) module.

20.6.6 DMA Operation

Not applicable.

20.6.7 Interrupts

XOSCRDY - Multipurpose Crystal Oscillator Ready: A 0-to-1 transition on the STATUS.XOSCRDY bit is detected
CLKFAIL - Clock Failure. A 0-to-1 transition on the STATUS.CLKFAIL bit is detected
OSC48MRDY - 48MHz Internal Oscillator Ready: A 0-to-1 transition on the STATUS.OSC48MRDY bit is detected
DPLL-related: – DPLLLOCKR - DPLL Lock Rise: A 0-to-1 transition of the STATUS.DPLLLOCKR bit is detected – DPLLLOCKF - DPLL Lock Fall: A 0-to-1 transition of the STATUS.DPLLLOCKF bit is detected – DPLLLTTO - DPLL Lock Timer Time-out: A 0-to-1 transition of the STATUS.DPLLLTTO bit is detected – DPLLLDRTO - DPLL Loop Divider Ratio Update Complete. A 0-to-1 transition of the STATUS.DPLLLDRTO bit is detected All these interrupts are synchronous wake-up source. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the OSCCTRL is reset. See the INTFLAG register for details on how to clear interrupt flags. The OSCCTRL has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register to determine which interrupt condition is present. Refer to the INTFLAG register for details. Note: The interrupts must be globally enabled for interrupt requests to be generated.

20.6.8 Events

The CFD can generate the following output event:

Clock Failure (CLKFAIL): Generated when the Clock Failure status bit is set in the Status register (STATUS.CLKFAIL). The CFD event is not generated when the Clock Switch bit (STATUS.CLKSW) in the Status register is set. Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.CFDEO) enables the CFD output event. Writing a '0' to this bit disables the CFD output event. Refer to the Event System chapter for details on configuring the event system.

20.6.9 Synchronization

Due to the multiple clock domains, values in the OSC48M control registers need to be synchronized to other clock domains. When executing an operation that requires synchronization, the relevant synchronization bit in the Synchronization Busy register (OSC48MSYNCBUSY) will be set immediately, and cleared when synchronization is complete. The following registers need synchronization when written: SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 218

OSC48M Divider register (OSC48MDIV) DPLL96M Due to the multiple clock domains, some registers in the DPLL96M must be synchronized when accessed. When executing an operation that requires synchronization, the relevant synchronization bit in the Synchronization Busy register (DPLLSYNCBUSY) will be set immediately, and cleared when synchronization is complete. The following bits need synchronization when written:
Enable bit in control register A (DPLLCTRLA.ENABLE)
DPLL Ratio register (DPLLRATIO)
DPLL Prescaler register (DPLLPRESC) Related Links

20.7 Register Summary

Offset Name Bit Pos. 0x00 INTENCLR 7:0 OSC48MRDY CLKFAIL XOSCRDY 15:8 DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR 23:16 31:24 0x04 INTENSET 7:0 OSC48MRDY CLKFAIL XOSCRDY 15:8 DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR 23:16 31:24 0x08 INTFLAG 7:0 OSC48MRDY CLKFAIL XOSCRDY 15:8 DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR 23:16 31:24 0x0C STATUS 7:0 OSC48MRDY CLKSW CLKFAIL XOSCRDY 15:8 DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR 23:16 31:24 0x10 XOSCCTRL 7:0 ONDEMAND RUNSTDBY SWBACK CFDEN XTALEN ENABLE 15:8 STARTUP[3:0] AMPGC GAIN[2:0] 0x12 CFDPRESC 7:0 CFDPRESC[2:0] 0x13 EVCTRL 7:0 CFDEO 0x14 OSC48MCTRL 7:0 ONDEMAND RUNSTDBY ENABLE 0x15 OSC48MDIV 7:0 DIV[3:0] 0x16 OSC48MSTUP 7:0 STARTUP[2:0] 0x17 Reserved 0x18 OSC48MSYNCBUS Y 7:0 OSC48MDIV 15:8 23:16 31:24 0x1C DPLLCTRLA 7:0 ONDEMAND RUNSTDBY ENABLE 0x1D ... 0x1F Reserved 0x20 DPLLRATIO 7:0 LDR[7:0] 15:8 LDR[11:8] 23:16 LDRFRAC[3:0] 31:24 0x24 DPLLCTRLB 7:0 REFCLK[1:0] WUF LPEN FILTER[1:0] 15:8 LBYPASS LTIME[2:0] 23:16 DIV[7:0] 31:24 DIV[10:8] 0x28 DPLLPRESC 7:0 PRESC[1:0] SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 220

Offset Name Bit Pos. 0x29 ... 0x2B Reserved 0x2C DPLLSYNCBUSY 7:0 DPLLPRESC DPLLRATIO ENABLE 0x2D ... 0x2F Reserved 0x30 DPLLSTATUS 7:0 CLKRDY LOCK 0x31 ... 0x37 Reserved 0x38 CAL48M 7:0 FCAL[5:0] 15:8 FRANGE[1:0] 23:16 TCAL[5:0] 31:24

20.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the "PAC Write-Protection" property in each individual register description. Refer to the 20.5.8 Register Access Protection section and the PAC - Peripheral Access Controller chapter for details. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-Synchronized" or "Write-Synchronized" property in each individual register description. Refer to the section on Synchronization for details. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 221

20.8.1 Interrupt Enable Clear

1 The DPLL Loop Divider Ratio Update Complete interrupt is enabled, and an interrupt request

will be generated when the DPLL Loop Divider Ratio Update Complete Interrupt flag is set. Bit 10 – DPLLLTO DPLL Lock Timeout Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the DPLL Lock Timeout Interrupt Enable bit, which disables the DPLL Lock Timeout interrupt. Value Description 0 The DPLL Lock Timeout interrupt is disabled.

1 The DPLL Lock Timeout interrupt is enabled, and an interrupt request will be generated

when the DPLL Lock Timeout Interrupt flag is set. Bit 9 – DPLLLCKF DPLL Lock Fall Interrupt Enable Writing '0' to this bit has no effect. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 222

Writing '1' to this bit will clear the DPLL Lock Fall Interrupt Enable bit, which disables the DPLL Lock Fall interrupt. Value Description 0 The DPLL Lock Fall interrupt is disabled.

1 The DPLL Lock Fall interrupt is enabled, and an interrupt request will be generated when the

DPLL Lock Fall Interrupt flag is set. Bit 8 – DPLLLCKR DPLL Lock Rise Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the DPLL Lock Rise Interrupt Enable bit, which disables the DPLL Lock Rise interrupt. Value Description 0 The DPLL Lock Rise interrupt is disabled.

1 The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when

the DPLL Lock Rise Interrupt flag is set. Bit 4 – OSC48MRDY OSC48M Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the OSC48M Ready Interrupt Enable bit, which disables the OSC48M Ready interrupt. Value Description 0 The OSC48M Ready interrupt is disabled.

1 The OSC48M Ready interrupt is enabled, and an interrupt request will be generated when

the OSC48M Ready Interrupt flag is set. Bit 1 – CLKFAIL Clock Failure Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the XOSC Clock Failure Interrupt Enable bit, which disables the XOSC Clock Failure interrupt. Value Description 0 The XOSC Clock Failure interrupt is disabled.

1 The XOSC Clock Failure interrupt is enabled, and an interrupt request will be generated

when the XOSC Clock Failure Interrupt flag is set. Bit 0 – XOSCRDY XOSC Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the XOSC Ready Interrupt Enable bit, which disables the XOSC Ready interrupt. Value Description 0 The XOSC Ready interrupt is disabled.

1 The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the

20.8.2 Interrupt Enable Set

1 The DPLL Loop Ratio Update Complete interrupt is enabled, and an interrupt request will be

generated when the DPLL Loop Ratio Update Complete Interrupt flag is set. Bit 10 – DPLLLTO DPLL Lock Timeout Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the DPLL Lock Timeout Interrupt Enable bit, which enables the DPLL Lock Timeout interrupt. Value Description 0 The DPLL Lock Timeout interrupt is disabled. when the DPLL Lock Timeout Interrupt flag is set. Bit 9 – DPLLLCKF DPLL Lock Fall Interrupt Enable Writing '0' to this bit has no effect. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 224

Writing '1' to this bit will set the DPLL Lock Fall Interrupt Enable bit, which enables the DPLL Lock Fall interrupt. Value Description 0 The DPLL Lock Fall interrupt is disabled. DPLL Lock Fall Interrupt flag is set. Bit 8 – DPLLLCKR DPLL Lock Rise Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the DPLL Lock Rise Interrupt Enable bit, which enables the DPLL Lock Rise interrupt. Value Description 0 The DPLL Lock Rise interrupt is disabled. the DPLL Lock Rise Interrupt flag is set. Bit 4 – OSC48MRDY OSC48M Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the OSC48M Ready Interrupt Enable bit, which enables the OSC48M Ready interrupt. Value Description 0 The OSC48M Ready interrupt is disabled. the OSC48M Ready Interrupt flag is set. Bit 1 – CLKFAIL XOSC Clock Failure Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the XOSC Clock Failure Interrupt Enable bit, which enables the XOSC Clock Failure Interrupt. Value Description 0 The XOSC Clock Failure Interrupt is disabled. when the XOSC Clock Failure Interrupt flag is set. Bit 0 – XOSCRDY XOSC Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the XOSC Ready Interrupt Enable bit, which enables the XOSC Ready interrupt. Value Description 0 The XOSC Ready interrupt is disabled. XOSC Ready Interrupt flag is set. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 225

20.8.3 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x08 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OSC48MRDY CLKFAIL XOSCRDY Access R/W R/W R/W Reset 0 0 0 Bit 11 – DPLLLDRTO DPLL Loop Divider Ratio Update Complete This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the DPLL Loop Divider Ratio Update Complete bit in the Status register (STATUS.DPLLLDRTO) and will generate an interrupt request if INTENSET.DPLLLDRTO is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DPLL Loop Divider Ratio Update Complete interrupt flag. Bit 10 – DPLLLTO DPLL Lock Timeout This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the DPLL Lock Timeout bit in the Status register (STATUS.DPLLLTO) and will generate an interrupt request if INTENSET.DPLLLTO is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DPLL Lock Timeout interrupt flag. Bit 9 – DPLLLCKF DPLL Lock Fall This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the DPLL Lock Fall bit in the Status register (STATUS.DPLLLCKF) and will generate an interrupt request if INTENSET.DPLLLCKF is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DPLL Lock Fall interrupt flag. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 226

Bit 8 – DPLLLCKR DPLL Lock Rise This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the DPLL Lock Rise bit in the Status register (STATUS.DPLLLCKR) and will generate an interrupt request if INTENSET.DPLLLCKR is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DPLL Lock Rise interrupt flag. Bit 4 – OSC48MRDY OSC48M Ready This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the OSC48M Ready bit in the Status register (STATUS.OSC48MRDY) and will generate an interrupt request if INTENSET.OSC48MRDY is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the OSC48M Ready interrupt flag. Bit 1 – CLKFAIL XOSC Failure Detection This flag is cleared by writing '1' to it. This flag is set on a 0-to-1 transition of the XOSC Clock Failure bit in the Status register (STATUS.CLKFAIL) and will generate an interrupt request if INTENSET.CLKFAIL is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the XOSC Clock Fail interrupt flag. Bit 0 – XOSCRDY XOSC Ready This flag is cleared by writing '1' to it. This flag is set on a 0-to-1 transition of the XOSC Ready bit in the Status register (STATUS.XOSCRDY) and will generate an interrupt request if INTENSET.XOSCRDY is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the XOSC Ready interrupt flag. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 227

Name: STATUS Offset: 0x0C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR Access R R R R Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OSC48MRDY CLKSW CLKFAIL XOSCRDY Access R R R R Reset 0 0 0 0 Bit 11 – DPLLLDRTO DPLL Loop Divider Ratio Update Complete Value Description 0 DPLL Loop Divider Ratio Update Complete not detected. 1 DPLL Loop Divider Ratio Update Complete detected. Bit 10 – DPLLLTO DPLL Lock Timeout Value Description 0 DPLL Lock time-out not detected. 1 DPLL Lock time-out detected. Bit 9 – DPLLLCKF DPLL Lock Fall Value Description 0 DPLL Lock fall edge not detected. 1 DPLL Lock fall edge detected. Bit 8 – DPLLLCKR DPLL Lock Rise Value Description 0 DPLL Lock rise edge not detected. 1 DPLL Lock fall edge detected. Bit 4 – OSC48MRDY OSC48M Ready SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 228

0 OSC48M is not ready. 1 OSC48M is stable and ready to be used as a clock source. Bit 2 – CLKSW XOSC Clock Switch Value Description 0 XOSC is not switched and provides the external clock or crystal oscillator clock. 1 XOSC is switched and provides the safe clock. Bit 1 – CLKFAIL XOSC Clock Failure Value Description 0 No XOSC failure detected. 1 A XOSC failure was detected. Bit 0 – XOSCRDY XOSC Ready Value Description 0 XOSC is not ready. 1 XOSC is stable and ready to be used as a clock source. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 229

20.8.5 External Multipurpose Crystal Oscillator (XOSC) Control

Name: XOSCCTRL Offset: 0x10 Reset: 0x0080 Property: PAC Write-Protection Bit 15 14 13 12 11 10 9 8 STARTUP[3:0] AMPGC GAIN[2:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY SWBACK CFDEN XTALEN ENABLE Access R/W R/W R/W R/W R/W R/W Reset 1 0 0 0 0 0 Bits 15:12 – STARTUP[3:0] Start-Up Time These bits select start-up time for the oscillator. The OSCULP32K oscillator is used to clock the start-up counter. Table 20-5. Start-Up Time for External Multipurpose Crystal Oscillator STARTUP[3:0] Number of OSCULP32K Clock Cycles Number of XOSC Clock Cycles Approximate Equivalent Time [µs] 0x0 1 3 31 0x1 2 3 61 0x2 4 3 122 0x3 8 3 244 0x4 16 3 488 0x5 32 3 977 0x6 64 3 1953 0x7 128 3 3906 0x8 256 3 7813 0x9 512 3 15625 0xA 1024 3 31250 0xB 2048 3 62500µs 0xC 4096 3 125000 0xD 8192 3 250000 0xE 16384 3 500000 0xF 32768 3 1000000 SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 230

Note: 1. Actual startup time is 1 OSCULP32K cycle + 3 XOSC cycles. 2. The given time neglects the three XOSC cycles before OSCULP32K cycle. Bit 11 – AMPGC Automatic Amplitude Gain Control Note: This bit must be set only after the XOSC has settled, indicated by the XOSC Ready flag in the Status register (STATUS.XOSCRDY). Value Description 0 The automatic amplitude gain control is disabled. 1 The automatic amplitude gain control is enabled. Amplitude gain will be automatically adjusted during Crystal Oscillator operation. Bits 10:8 – GAIN[2:0] Oscillator Gain These bits select the gain for the oscillator. The listed maximum frequencies are recommendations, and might vary based on capacitive load and crystal characteristics. Those bits must be properly configured even when the Automatic Amplitude Gain Control is active. Value Recommended Max Frequency [MHz] 0x0 2 0x1 4 0x2 8 0x3 16 0x4 30 0x5-0x7 Reserved Bit 7 – ONDEMAND On Demand Control The On Demand operation mode allows the oscillator to be enabled or disabled, depending on peripheral clock requests. If the ONDEMAND bit has been previously written to '1', the oscillator will be running only when requested by a peripheral. If there is no peripheral requesting the oscillator’s clock source, the oscillator will be in a disabled state. If On Demand is disabled, the oscillator will always be running when enabled. In standby sleep mode, the On Demand operation is still active. Value Description 0 The oscillator is always on, if enabled.

1 The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock

source. The oscillator is disabled if no peripheral is requesting the clock source. Bit 6 – RUNSTDBY Run in Standby This bit controls how the XOSC behaves during standby sleep mode, together with the ONDEMAND bit: Value Description 0 The XOSC is not running in Standby sleep mode if no peripheral requests the clock. 1 The XOSC is running in Standby sleep mode. If ONDEMAND=1, the XOSC will be running when a peripheral is requesting the clock. If ONDEMAND=0, the clock source will always be running in Standby sleep mode. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 231

Bit 4 – SWBACK Clock Switch Back This bit controls the XOSC output switch back to the external clock or crystal oscillator in case of clock recovery: Value Description 0 The clock switch back is disabled. 1 The clock switch back is enabled. This bit is reset once the XOSC putput clock is switched back to the external clock or crystal oscillator. Bit 3 – CFDEN Clock Failure Detector Enable This bit controls the clock failure detector: Value Description 0 The Clock Failure Detector is disabled. 1 the Clock Failure Detector is enabled. Bit 2 – XTALEN Crystal Oscillator Enable This bit controls the connections between the I/O pads and the external clock or crystal oscillator: Value Description 0 External clock connected on XIN. XOUT can be used as general-purpose I/O. 1 Crystal connected to XIN/XOUT. Bit 1 – ENABLE Oscillator Enable Value Description 0 The oscillator is disabled. 1 The oscillator is enabled. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 232

20.8.6 Clock Failure Detector Prescaler

Name: CFDPRESC Offset: 0x12 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CFDPRESC[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 2:0 – CFDPRESC[2:0] Clock Failure Detector Prescaler These bits select the prescaler for the clock failure detector. The OSC48M oscillator is used to clock the CFD prescaler. The CFD safe clock frequency is the OSC48M frequency divided by 2^CFDPRESC. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 233

20.8.7 Event Control

Name: EVCTRL Offset: 0x13 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CFDEO Access R/W Reset 0 Bit 0 – CFDEO Clock Failure Detector Event Output Enable This bit indicates whether the Clock Failure detector event output is enabled or not and an output event will be generated when the Clock Failure detector detects a clock failure Value Description 0 Clock Failure detector event output is disabled and no event will be generated. 1 Clock Failure detector event output is enabled and an event will be generated. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 234

20.8.8 48MHz Internal Oscillator (OSC48M) Control Name: OSC48MCTRL Offset: 0x14 Reset: 0x82 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY ENABLE Access R/W R/W R/W Reset 1 0 1 Bit 7 – ONDEMAND On Demand Control The On Demand operation mode allows the oscillator to be enabled or disabled depending on peripheral clock requests. If the ONDEMAND bit has been previously written to '1', the oscillator will only be running when requested by a peripheral. If there is no peripheral requesting the oscillator’s clock source, the oscillator will be in a disabled state. If On Demand is disabled the oscillator will always be running when enabled. In standby sleep mode, the On Demand operation is still active. Value Description 0 The oscillator is always on, if enabled. source. The oscillator is disabled if no peripheral is requesting the clock source. Bit 6 – RUNSTDBY Run in Standby This bit controls how the OSC48M behaves during standby sleep mode. Value Description 0 The OSC48M is disabled in standby sleep mode if no peripheral requests the clock. 1 The OSC48M is not stopped in standby sleep mode. If ONDEMAND=1, the OSC48M will be running when a peripheral is requesting the clock. If ONDEMAND=0, the clock source will always be running in standby sleep mode. Bit 1 – ENABLE Oscillator Enable Value Description 0 The oscillator is disabled. 1 The oscillator is enabled. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 235

20.8.9 OSC48M Divider

Name: OSC48MDIV Offset: 0x15 Reset: 0x0B Property: - Bit 7 6 5 4 3 2 1 0 DIV[3:0] Access R/W R/W R/W R/W Reset 1 0 1 1 Bits 3:0 – DIV[3:0] Oscillator Divider Selection These bits control the oscillator frequency range by adjusting the division ratio. The oscillator frequency is 48MHz divided by DIV+1. Value Description 0000 48MHz 0001 24MHz 0010 16MHz 0011 12MHz 0100 9.6MHz 0101 8MHz 0110 6.86MHz 0111 6MHz 1000 5.33MHz 1001 4.8MHz 1010 4.36MHz 1011 4MHz 1100 3.69MHz 1101 3.43MHz 1110 3.2MHz 1111 3MHz SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 236

20.8.10 OSC48M Startup

Name: OSC48MSTUP Offset: 0x16 Reset: 0x07 Property: - Bit 7 6 5 4 3 2 1 0 STARTUP[2:0] Access R/W R/W R/W Reset 1 1 1 Bits 2:0 – STARTUP[2:0] Oscillator Startup Delay These bits select the oscillator start-up delay in oscillator cycles. Table 20-6. Oscillator Divider Selection STARTUP[2:0] Number of OSCM48M Clock Cycles Approximate Equivalent Time 0x0 8 166ns 0x1 16 333ns 0x2 32 667ns 0x3 64 1.333μs 0x4 128 2.667μs 0x5 256 5.333μs 0x6 512 10.667μs 0x7 1024 21.333μs SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 237

20.8.11 OSC48M Synchronization Busy

Name: OSC48MSYNCBUSY Offset: 0x18 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 OSC48MDIV Access R/W Reset 1 Bit 2 – OSC48MDIV Oscillator Divider Synchronization Status This bit is set when OSC48MDIV register is written. This bit is cleared when OSC48MDIV synchronization is completed. Value Description 0 No synchronized access. 1 Synchronized access is ongoing. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 238

20.8.12 DPLL Control A

Name: DPLLCTRLA Offset: 0x1C Reset: 0x80 Property: PAC Write-Protection, Write-Synchronized (ENABLE) Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY ENABLE Access R/W R/W R/W Reset 1 0 0 Bit 7 – ONDEMAND On Demand Clock Activation The On Demand operation mode allows the DPLL to be enabled or disabled depending on peripheral clock requests. If the ONDEMAND bit has been previously written to '1', the DPLL will only be running when requested by a peripheral. If there is no peripheral requesting the DPLL’s clock source, the DPLL will be in a disabled state. If On Demand is disabled the DPLL will always be running when enabled. In standby sleep mode, the On Demand operation is still active. Value Description 0 The DPLL is always on, if enabled.

1 The DPLL is enabled when a peripheral is requesting the DPLL to be used as a clock

source. The DPLL is disabled if no peripheral is requesting the clock source. Bit 6 – RUNSTDBY Run in Standby This bit controls how the DPLL behaves during standby sleep mode: Value Description 0 The DPLL is disabled in standby sleep mode if no peripheral requests the clock. 1 The DPLL is not stopped in standby sleep mode. If ONDEMAND=1, the DPLL will be running when a peripheral is requesting the clock. If ONDEMAND=0, the clock source will always be running in standby sleep mode. Bit 1 – ENABLE DPLL Enable The software operation of enabling or disabling the DPLL takes a few clock cycles, so the DPLLSYNCBUSY.ENABLE status bit indicates when the DPLL is successfully enabled or disabled. Value Description 0 The DPLL is disabled. 1 The DPLL is enabled. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 239

20.8.13 DPLL Ratio Control

Name: DPLLRATIO Offset: 0x20 Reset: 0x00 Property: PAC Write-Protection, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 LDRFRAC[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 LDR[11:8] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 19:16 – LDRFRAC[3:0] Loop Divider Ratio Fractional Part Writing these bits selects the fractional part of the frequency multiplier. Due to synchronization there is a delay between writing these bits and the effect on the DPLL output clock. The value written will read back immediately and the DPLLRATIO bit in the DPLL Synchronization Busy register (DPLLSYNCBUSY.DPLLRATIO) will be set. DPLLSYNCBUSY.DPLLRATIO will be cleared when the operation is completed. Bits 11:0 – LDR[11:0] Loop Divider Ratio Writing these bits selects the integer part of the frequency multiplier. The value written to these bits will read back immediately, and the DPLLRATIO bit in the DPLL Synchronization busy register (DPLLSYNCBUSY.DPLLRATIO), will be set. DPLLSYNCBUSY.DPLLRATIO will be cleared when the operation is completed. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 240

20.8.14 DPLL Control B

Name: DPLLCTRLB Offset: 0x24 Reset: 0x00 Property: Enable-Protected, PAC Write-Protection Bit 31 30 29 28 27 26 25 24 DIV[10:8] Access R/W R/W R/W Reset 0 0 0 Bit 23 22 21 20 19 18 17 16 DIV[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 LBYPASS LTIME[2:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 REFCLK[1:0] WUF LPEN FILTER[1:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bits 26:16 – DIV[10:0] Clock Divider These bits set the XOSC clock division factor and can be calculated with following formula: f??? = ʹ? ??? + ͳ Bit 12 – LBYPASS Lock Bypass Value Description 0 DPLL Lock signal drives the DPLL controller internal logic. 1 DPLL Lock signal is always asserted. Bits 10:8 – LTIME[2:0] Lock Time These bits select the lock time-out value: Value Name Description 0x0 Default No time-out. Automatic lock. 0x1 Reserved 0x2 Reserved 0x3 Reserved 0x4 8MS Time-out if no lock within 8ms 0x5 9MS Time-out if no lock within 9ms 0x6 10MS Time-out if no lock within 10ms 0x7 11MS Time-out if no lock within 11ms SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 241

Bits 5:4 – REFCLK[1:0] Reference Clock Selection Write these bits to select the DPLL clock reference: Value Name Description 0x0 XOSC32K XOSC32K clock reference 0x1 XOSC XOSC clock reference 0x2 GCLK GCLK clock reference 0x3 Reserved Bit 3 – WUF Wake Up Fast Value Description 0 DPLL clock is output after startup and lock time. 1 DPLL clock is output after startup time. Bit 2 – LPEN Low-Power Enable Value Description 0 The low-power mode is disabled. Time to Digital Converter is enabled. 1 The low-power mode is enabled. Time to Digital Converter is disabled. This will improve power consumption but increase the output jitter. Bits 1:0 – FILTER[1:0] Proportional Integral Filter Selection These bits select the DPLL filter type: Value Name Description 0x0 DEFAULT Default filter mode 0x1 LBFILT Low bandwidth filter 0x2 HBFILT High bandwidth filter 0x3 HDFILT High damping filter SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 242

20.8.15 DPLL Prescaler

Name: DPLLPRESC Offset: 0x28 Reset: 0x00 Property: PAC Write-Protection, Write-Synchronized Bit 7 6 5 4 3 2 1 0 PRESC[1:0] Access R/W R/W Reset 0 0 Bits 1:0 – PRESC[1:0] Output Clock Prescaler These bits define the output clock prescaler setting. Value Name Description 0x0 DIV1 DPLL output is divided by 1 0x1 DIV2 DPLL output is divided by 2 0x2 DIV4 DPLL output is divided by 4 0x3 Reserved SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 243

20.8.16 DPLL Synchronization Busy

Name: DPLLSYNCBUSY Offset: 0x2C Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 DPLLPRESC DPLLRATIO ENABLE Access R R R Reset 0 0 0 Bit 3 – DPLLPRESC DPLL Prescaler Synchronization Status Value Description 0 The DPLLRESC register has been synchronized. 1 The DPLLRESC register value has changed and its synchronization is in progress. Bit 2 – DPLLRATIO DPLL Loop Divider Ratio Synchronization Status Value Description 0 The DPLLRATIO register has been synchronized. 1 The DPLLRATIO register value has changed and its synchronization is in progress. Bit 1 – ENABLE DPLL Enable Synchronization Status Value Description 0 The DPLLCTRLA.ENABLE bit has been synchronized. 1 The DPLLCTRLA.ENABLE bit value has changed and its synchronization is in progress. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 244

20.8.17 DPLL Status

Name: DPLLSTATUS Offset: 0x30 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 CLKRDY LOCK Access R R Reset 0 0 Bit 1 – CLKRDY Output Clock Ready Value Description 0 The DPLL output clock is off. 1 The DPLL output clock in on. Bit 0 – LOCK DPLL Lock status bit Value Description

0 The DPLL Lock signal is cleared, when the DPLL is disabled or when the DPLL is trying to

reach the target frequency. 1 The DPLL Lock signal is asserted when the desired frequency is reached. SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 245

20.8.18 OSC48M Calibration

Name: CAL48M Offset: 0x38 Reset: Calibrated value for VDD range 3.6 V to 5.5 V Property: PAC Write-Protection This register (bits 0 to 21) must be updated with the corresponding data in the NVM Software Calibration Area: CAL48M 5V or CAL48M 3V3, depending on the VDD range. Refer to

9.4 NVM Software

Calibration Area Mapping. Note: This register is only available for Rev D silicon. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 TCAL[5:0] Access R/W R/W R/W R/W R/W R/W Reset x x x x x x Bit 15 14 13 12 11 10 9 8 FRANGE[1:0] Access R/W R/W Reset x x Bit 7 6 5 4 3 2 1 0 FCAL[5:0] Access R/W R/W R/W R/W R/W R/W Reset x x x x x x Bits 21:16 – TCAL[5:0] Temperature Calibration Bits 9:8 – FRANGE[1:0] Frequency Range Bits 5:0 – FCAL[5:0] Frequency Calibration Related Links SAM C20/C21 Family Data Sheet OSCCTRL – Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 246

OSC32KCTRL – 32KHz Oscillators Controller

21.1 Overview

The 32KHz Oscillators Controller (OSC32KCTRL) provides a user interface to the 32.768kHz oscillators: XOSC32K, OSC32K, and OSCULP32K. The OSC32KCTRL sub-peripherals can be enabled, disabled, calibrated, and monitored through interface registers. All sub-peripheral statuses are collected in the Status register (STATUS). They can additionally trigger interrupts upon status changes via the INTENSET, INTENCLR, and INTFLAG registers.

21.2 Features

32.768kHz Crystal Oscillator (XOSC32K) – Programmable start-up time – Crystal or external input clock on XIN32 I/O – Clock failure detection with safe clock switch – Clock failure event output
32.768kHz High Accuracy Internal Oscillator (OSC32K) – Frequency fine tuning – Programmable start-up time
32.768kHz Ultra Low Power Internal Oscillator (OSCULP32K) – Ultra low power, always-on oscillator – Frequency fine tuning
Calibration value loaded from Flash factory calibration at reset
1.024kHz clock outputs available SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 247

21.3 Block Diagram

Figure 21-1. OSC32KCTRL Block Diagram STATUS register INTERRUPTS GENERATOR Interrupts OSC32KCTRL 32K OSCILLATORS CONTROL XOUT32 XIN32 CLK_XOSC32K CLK_OSC32K CLK_OSCULP32K CFD Event XOSC32K OSCULP32K OSC32K CFD

21.4 Signal Description

XIN32 Analog Input 32.768 kHz Crystal Oscillator or external clock input XOUT32 Analog Output 32.768 kHz Crystal Oscillator output The I/O lines are automatically selected when XOSC32K is enabled. Note: The signal of the external crystal oscillator may affect the jitter of neighboring pads.

21.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

21.5.1 I/O Lines

I/O lines are configured by OSC32KCTRL when XOSC32K is enabled, and need no user configuration.

21.5.2 Power Management

The OSC32KCTRL will continue to operate in any sleep mode where a 32KHz oscillator is running as source clock. The OSC32KCTRL interrupts can be used to wake up the device from sleep modes. Related Links SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 248

PM – Power Manager

21.5.3 Clocks

The OSC32KCTRL gathers controls for all 32KHz oscillators and provides clock sources to the Generic Clock Controller (GCLK), Real-Time Counter (RTC), and Watchdog Timer (WDT). The available clock sources are: XOSC32K, OSC32K, and OSCULP32K. The OSC32KCTRL bus clock (CLK_OSC32KCTRL_APB) can be enabled and disabled in the Main Clock module (MCLK). Related Links

21.5.4 Interrupts

The interrupt request lines are connected to the interrupt controller. Using the OSC32KCTRL interrupts requires the interrupt controller to be configured first. Related Links

21.5.5 Events

The events of this peripheral are connected to the Event System. Related Links 29. EVSYS – Event System

21.5.6 Debug Operation

When the CPU is halted in debug mode, OSC32KCTRL will continue normal operation. If OSC32KCTRL is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging.

21.5.7 Register Access Protection

All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Interrupt Flag Status and Clear (INTFLAG) register Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write- Protection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger. Related Links 11. PAC - Peripheral Access Controller

21.5.8 Analog Connections

The external 32.768kHz crystal must be connected between the XIN32 and XOUT32 pins, along with any required load capacitors. For details on recommended oscillator characteristics and capacitor load, refer to the related links. Related Links 45. Electrical Characteristics 85°C (SAM C20/C21 E/G/J) SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 249

21.5.9 Calibration

The OSC32K calibration value from the production test must be loaded from the NVM Software Calibration Area into the OSC32K register (OSC32K.CALIB) by software to achieve specified accuracy. Related Links

21.6 Functional Description

21.6.1 Principle of Operation

XOSC32K, OSC32K, and OSCULP32K are configured via OSC32KCTRL control registers. Through this interface, the sub-peripherals are enabled, disabled, or have their calibration values updated. The STATUS register gathers different status signals coming from the sub-peripherals of OSC32KCTRL. The status signals can be used to generate system interrupts, and in some cases wake up the system from standby mode, provided the corresponding interrupt is enabled. 21.6.2 32KHz External Crystal Oscillator (XOSC32K) Operation The XOSC32K can operate in two different modes:

External clock, with an external clock signal connected to XIN32
Crystal oscillator, with an external 32.768kHz crystal connected between XIN32 and XOUT32 At reset, the XOSC32K is disabled, and the XIN32/XOUT32 pins can either be used as General Purpose I/O (GPIO) pins or by other peripherals in the system. When XOSC32K is enabled, the operating mode determines the GPIO usage. When in crystal oscillator mode, the XIN32 and XOUT32 pins are controlled by the OSC32KCTRL, and GPIO functions are overridden on both pins. When in external clock mode, the only XIN32 pin will be overridden and controlled by the OSC32KCTRL, while the XOUT32 pin can still be used as a GPIO pin. The XOSC32K is enabled by writing a '1' to the Enable bit in the 32KHz External Crystal Oscillator Control register (XOSC32K.ENABLE=1). The XOSC32K is disabled by writing a '0' to the Enable bit in the 32KHz External Crystal Oscillator Control register (XOSC32K.ENABLE=0). To enable the XOSC32K as a crystal oscillator, the XTALEN bit in the 32KHz External Crystal Oscillator Control register must be set (XOSC32K.XTALEN=1). If XOSC32K.XTALEN is '0', the external clock input will be enabled. The XOSC32K 32.768kHz output is enabled by setting the 32KHz Output Enable bit in the 32KHz External Crystal Oscillator Control register (XOSC32K.EN32K=1). The XOSC32K also has a 1.024kHz clock output. This is enabled by setting the 1KHz Output Enable bit in the 32KHz External Crystal Oscillator Control register (XOSC32K.EN1K=1). It is also possible to lock the XOSC32K configuration by setting the Write Lock bit in the 32KHz External Crystal Oscillator Control register (XOSC32K.WRTLOCK=1). If set, the XOSC32K configuration is locked until a Power-On Reset (POR) is detected. The XOSC32K will behave differently in different sleep modes based on the settings of XOSC32K.RUNSTDBY, XOSC32K.ONDEMAND, and XOSC32K.ENABLE. If XOSC32KCTRL.ENABLE=0, the XOSC32K will be always stopped. For XOS32KCTRL.ENABLE=1, this table is valid: SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 250

Table 21-1. XOSC32K Sleep Behavior CPU Mode XOSC32K. RUNSTDBY XOSC32K. ONDEMAND Sleep Behavior of XOSC32K and CFD Active or Idle - 0 Always run Active or Idle - 1 Run if requested by peripheral Standby 1 0 Always run Standby 1 1 Run if requested by peripheral Standby 0 - Run if requested by peripheral As a crystal oscillator usually requires a very long start-up time, the 32KHz External Crystal Oscillator will keep running across resets when XOSC32K.ONDEMAND=0, except for power-on reset (POR). After a reset or when waking up from a sleep mode where the XOSC32K was disabled, the XOSC32K will need a certain amount of time to stabilize on the correct frequency. This start-up time can be configured by changing the Oscillator Start-Up Time bit group (XOSC32K.STARTUP) in the 32KHz External Crystal Oscillator Control register. During the start-up time, the oscillator output is masked to ensure that no unstable clock propagates to the digital logic. Once the external clock or crystal oscillator is stable and ready to be used as a clock source, the XOSC32K Ready bit in the Status register is set (STATUS.XOSC32KRDY=1). The transition of STATUS.XOSC32KRDY from '0' to '1' generates an interrupt if the XOSC32K Ready bit in the Interrupt Enable Set register is set (INTENSET.XOSC32KRDY=1). The XOSC32K can be used as a source for Generic Clock Generators (GCLK) or for the Real-Time Counter (RTC). Before enabling the GCLK or the RTC module, the corresponding oscillator output must be enabled (XOSC32K.EN32K or XOSC32K.EN1K) in order to ensure proper operation. In the same way, the GCLK or RTC modules must be disabled before the clock selection is changed. For details on RTC clock configuration, refer also to 21.6.7 Real-Time Counter Clock Selection. Related Links 16. GCLK - Generic Clock Controller 24. RTC – Real-Time Counter

21.6.3 Clock Failure Detection Operation

The Clock Failure Detector (CFD) allows the user to monitor the external clock or crystal oscillator signal provided by the external oscillator (XOSC32K). The CFD detects failing operation of the XOSC32K clock with reduced latency, and allows to switch to a safe clock source in case of clock failure. The user can also switch from the safe clock back to XOSC32K in case of recovery. The safe clock is derived from the OSCULP32K oscillator with a configurable prescaler. This allows to configure the safe clock in order to fulfill the operative conditions of the microcontroller. In sleep modes, CFD operation is automatically disabled when the external oscillator is not requested to run by a peripheral. See the Sleep Behavior table above when this is the case. The user interface registers allow to enable, disable, and configure the CFD. The Status register provides status flags on failure and clock switch conditions. The CFD can optionally trigger an interrupt or an event when a failure is detected. SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 251

The CFD is reset only at power-on (POR). The CFD does not monitor the XOSC32K clock when the oscillator is disabled (XOSC32K.ENABLE=0). Before starting CFD operation, the user must start and enable the safe clock source (OSCULP32K oscillator). CFD operation is started by writing a '1' to the CFD Enable bit in the External Oscillator Control register (CFDCTRL.CFDEN). After starting or restarting the XOSC32K, the CFD does not detect failure until the start-up time has elapsed. The start-up time is configured by the Oscillator Start-Up Time in the External Multipurpose Crystal Oscillator Control register (XOSC32K.STARTUP). Once the XOSC32K Start-Up Time is elapsed, the XOSC32K clock is constantly monitored. During a period of 4 safe clocks (monitor period), the CFD watches for a clock activity from the XOSC32K. There must be at least one rising and one falling XOSC32K clock edge during 4 safe clock periods to meet non-failure conditions. If no or insufficient activity is detected, the failure status is asserted: The Clock Failure Detector status bit in the Status register (STATUS.CLKFAIL) and the Clock Failure Detector interrupt flag bit in the Interrupt Flag register (INTFLAG.CLKFAIL) are set. If the CLKFAIL bit in the Interrupt Enable Set register (INTENSET.CLKFAIL) is set, an interrupt is generated as well. If the Event Output enable bit in the Event Control register (EVCTRL.CFDEO) is set, an output event is generated, too. After a clock failure was issued the monitoring of the XOSC32K clock is continued, and the Clock Failure Detector status bit in the Status register (STATUS.CLKFAIL) reflects the current XOSC32K activity. Clock Switch When a clock failure is detected, the XOSC32K clock is replaced by the safe clock in order to maintain an active clock during the XOSC32K clock failure. The safe clock source is the OSCULP32K oscillator clock. Both 32KHz and 1KHz outputs of the XOSC32K are replaced by the respective OSCULP32K 32KHz and 1KHz outputs. The safe clock source can be scaled down by a configurable prescaler to ensure that the safe clock frequency does not exceed the operating conditions selected by the application. When the XOSC32K clock is switched to the safe clock, the Clock Switch bit in the Status register (STATUS.CLKSW) is set. When the CFD has switched to the safe clock, the XOSC32K is not disabled. If desired, the application must take the necessary actions to disable the oscillator. The application must also take the necessary actions to configure the system clocks to continue normal operations. In the case the application can recover the XOSC32K, the application can switch back to the XOSC32K clock by writing a '1' to Switch Back Enable bit in the Clock Failure Control register (CFDCTRL.SWBACK). Once the XOSC32K clock is switched back, the Switch Back bit (CFDCTRL.SWBACK) is cleared by hardware. Prescaler The CFD has an internal configurable prescaler to generate the safe clock from the OSCULP32K oscillator. The prescaler size allows to scale down the OSCULP32K oscillator so the safe clock frequency is not higher than the XOSC32K clock frequency monitored by the CFD. The maximum division factor is The prescaler is applied on both outputs (32KHz and 1KHz) of the safe clock. Example 21-1. Example For an external crystal oscillator at 32KHz and the OSCULP32K frequency is 32KHz, the XOSC32K.CFDPRESC should be set to 0 for a safe clock of equal frequency. SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 252

If the Event Output Enable bit in the Event Control register (EVCTRL.CFDEO) is set, the CFD clock failure will be output on the Event Output. When the CFD is switched to the safe clock, the CFD clock failure will not be output on the Event Output. Sleep Mode The CFD is halted depending on configuration of the XOSC32K and the peripheral clock request. For further details, refer to the Sleep Behavior table above. The CFD interrupt can be used to wake up the device from sleep modes. 21.6.4 32KHz Internal Oscillator (OSC32K) Operation The OSC32K provides a tunable, low-speed, and low-power clock source. At reset, the OSC32K is disabled. It can be enabled by setting the Enable bit in the 32KHz Internal Oscillator Control register (OSC32K.ENABLE=1). The OSC32K is disabled by clearing the Enable bit in the 32KHz Internal Oscillator Control register (OSC32K.ENABLE=0). The frequency of the OSC32K oscillator is controlled by OSC32K.CALIB, which is a calibration value in the 32KHz Internal Oscillator Calibration bits in the 32KHz Internal Oscillator Control register. The CALIB value must be must be loaded with production calibration values from the NVM Software Calibration Area. When writing the Calibration bits, the user must wait for the STATUS.OSC32KRDY bit to go high before the new value is committed to the oscillator. The OSC32K has a 32.768kHz output which is enabled by setting the 32KHz Output Enable bit in the 32KHz Internal Oscillator Control register (OSC32K.EN32K=1). The OSC32K also has a 1.024kHz clock output. This is enabled by setting the 1KHz Output Enable bit in the 32KHz Internal Oscillator Control register (OSC32K.EN1K). Before using the OSC32K, the Calibration field in the OSC32K register (OSC32K.CALIB) must be loaded with production calibration values from the NVM Software Calibration Area. The OSC32K will behave differently in different sleep modes based on the settings of OSC32K will be always stopped. For OS32KCTRL.ENABLE=1, this table is valid: Table 21-2. OSC32K Sleep Behavior CPU Mode OSC32KCTRL.RUN STDBY OSC32KCTRL.OND EMAND Sleep Behavior Active or Idle - 0 Always run Active or Idle - 1 Run if requested by peripheral Standby 1 0 Always run Standby 1 1 Run if requested by peripheral Standby 0 - Run if requested by peripheral The OSC32K requires a start-up time. For this reason, OSC32K will keep running across resets when OSC32K.ONDEMAND=0, except for power-on reset (POR). After such a reset, or when waking up from a sleep mode where the OSC32K was disabled, the OSC32K will need a certain amount of time to stabilize on the correct frequency. SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 253

This startup time can be configured by changing the Oscillator Start-Up Time bit group (OSC32K.STARTUP) in the OSC32K Control register. During the start-up time, the oscillator output is masked to ensure that no unstable clock propagates to the digital logic. Once the external clock or crystal oscillator is stable and ready to be used as a clock source, the OSC32K Ready bit in the Status register is set (STATUS.OSC32KRDY=1). The transition of STATUS.OSC32KRDY from '0' to '1' generates an interrupt if the OSC32K Ready bit in the Interrupt Enable Set register is set (INTENSET.OSC32KRDY=1). The OSC32K can be used as a source for Generic Clock Generators (GCLK) or for the Real-Time Counter (RTC). Before enabling the GCLK or the RTC module, the corresponding oscillator output must be enabled (OSC32K.EN32K or OSC32K.EN1K) in order to ensure proper operation. In the same way, the GCLK or RTC modules must be disabled before the clock selection is changed. Related Links

RTC – Real-Time Counter

21.6.7 Real-Time Counter Clock Selection

21.6.5 32 kHz Ultra-Low-Power Internal Oscillator (OSCULP32K) Operation The OSCULP32K provides a tunable, low-speed, and ultra-low-power clock source. The OSCULP32K is factory-calibrated under typical voltage and temperature conditions. The OSCULP32K should be preferred to the OSC32K whenever the power requirements are prevalent over frequency stability and accuracy. The OSCULP32K is enabled by default after a power-on reset (POR) and will always run except during POR. The frequency of the OSCULP32K Oscillator is controlled by the value in the Calibration bits in the 32 kHz Ultra-Low-Power Internal Oscillator Control register (OSCULP32K.CALIB). This data is used to compensate for process variations. OSCULP32K.CALIB is automatically loaded from Flash Factory Calibration during start-up. The calibration value can be overridden by the user by writing to OSCULP32K.CALIB. It is also possible to lock the OSCULP32K configuration by setting the Write Lock bit in the 32 kHz Ultra- Low-Power Internal Oscillator Control register (OSCULP32K.WRTLOCK = 1). If set, the OSCULP32K configuration is locked until a Power-on Reset (POR) is detected. The OSCULP32K can be used as a source for Generic Clock Generators (GCLK) or for the Real-Time Counter (RTC). To ensure proper operation, the GCLK or RTC modules must be disabled before the clock selection is changed. Related Links 24. RTC – Real-Time Counter

GCLK - Generic Clock Controller

21.6.6 Watchdog Timer Clock Selection

The Watchdog Timer (WDT) uses the internal 1.024kHz OSCULP32K output clock. This clock is running all the time and internally enabled when requested by the WDT module. Related Links 23. WDT – Watchdog Timer SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 254

Before enabling the RTC module, the RTC clock must be selected first. All oscillator outputs are valid as RTC clock. The selection is done in the RTC Control register (RTCCTRL). To ensure a proper operation, it is highly recommended to disable the RTC module first, before the RTC clock source selection is changed. Related Links 24. RTC – Real-Time Counter

21.6.8 Interrupts

The OSC32KCTRL has the following interrupt sources:

XOSC32KRDY - 32KHz Crystal Oscillator Ready: A 0-to-1 transition on the STATUS.XOSC32KRDY bit is detected
CLKFAIL - Clock Failure Detector: A 0-to-1 transition on the STATUS.CLKFAIL bit is detected
OSC32KRDY - 32KHz Internal Oscillator Ready: A 0-to-1 transition on the STATUS.OSC32KRDY bit is detected All these interrupts are synchronous wake-up source. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be enabled individually by setting the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by setting the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the OSC32KCTRL is reset. See the INTFLAG register for details on how to clear interrupt flags. The OSC32KCTRL has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register to determine which interrupt condition is present. Refer to the INTFLAG register for details. Note: Interrupts must be globally enabled for interrupt requests to be generated. Related Links 19. PM – Power Manager

21.6.9 Events

The CFD can generate the following output event:

Clock Failure Detector (CLKFAIL): Generated when the Clock Failure Detector status bit is set in the Status register (STATUS.CLKFAIL). The CFD event is not generated when the Clock Switch bit (STATUS.SWBACK) in the Status register is set. Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.CFDEO) enables the CFD output event. Writing a '0' to this bit disables the CFD output event. Refer to the Event System chapter for details on configuring the event system. SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 255

21.7 Register Summary

Offset Name Bit Pos. 0x00 INTENCLR 7:0 CLKFAIL OSC32KRDY XOSC32KRD Y 15:8 23:16 31:24 0x04 INTENSET 7:0 CLKFAIL OSC32KRDY XOSC32KRD Y 15:8 23:16 31:24 0x08 INTFLAG 7:0 CLKFAIL OSC32KRDY XOSC32KRD Y 15:8 23:16 31:24 0x0C STATUS 7:0 CLKSW CLKFAIL OSC32KRDY XOSC32KRD Y 15:8 23:16 31:24 0x10 RTCCTRL 7:0 RTCSEL[2:0] 15:8 23:16 31:24 0x14 XOSC32K 7:0 ONDEMAND RUNSTDBY EN1K EN32K XTALEN ENABLE 15:8 WRTLOCK STARTUP[2:0] 0x16 CFDCTRL 7:0 CFDPRESC SWBACK CFDEN 0x17 EVCTRL 7:0 CFDEO 0x18 OSC32K 7:0 ONDEMAND RUNSTDBY EN1K EN32K ENABLE 15:8 WRTLOCK STARTUP[2:0] 23:16 CALIB[6:0] 31:24 0x1C OSCULP32K 7:0 15:8 WRTLOCK CALIB[4:0] 23:16 31:24

21.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 256

All registers with write-access can be write-protected optionally by the peripheral access controller (PAC). Optional Write-Protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write- Protection" property in the register description. Write-protection does not apply to accesses through an external debugger. Related Links 11. PAC - Peripheral Access Controller SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 257

21.8.1 Interrupt Enable Clear

Name: INTENCLR Offset: 0x00 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CLKFAIL OSC32KRDY XOSC32KRDY Access R/W R/W R/W Reset 0 0 0 Bit 2 – CLKFAIL XOSC32K Clock Failure Detection Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the XOSC32K Clock Failure Interrupt Enable bit, which disables the XOSC32K Clock Failure interrupt. Value Description 0 The XOSC32K Clock Failure Detection is disabled. 1 The XOSC32K Clock Failure Detection is enabled. An interrupt request will be generated when the XOSC32K Clock Failure Detection interrupt flag is set. Bit 1 – OSC32KRDY OSC32K Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the OSC32K Ready Interrupt Enable bit, which disables the OSC32K Ready interrupt. Value Description 0 The OSC32K Ready interrupt is disabled. 1 The OSC32K Ready interrupt is enabled. Bit 0 – XOSC32KRDY XOSC32K Ready Interrupt Enable Writing a '0' to this bit has no effect. SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 258

Writing a '1' to this bit will clear the XOSC32K Ready Interrupt Enable bit, which disables the XOSC32K Ready interrupt. Value Description 0 The XOSC32K Ready interrupt is disabled. 1 The XOSC32K Ready interrupt is enabled. SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 259

21.8.2 Interrupt Enable Set

Name: INTENSET Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CLKFAIL OSC32KRDY XOSC32KRDY Access R/W R/W R/W Reset 0 0 0 Bit 2 – CLKFAIL XOSC32K Clock Failure Detection Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the XOSC32K Clock Failure Interrupt Enable bit, which enables the XOSC32K Clock Failure interrupt. Value Description 0 The XOSC32K Clock Failure Detection is disabled. 1 The XOSC32K Clock Failure Detection is enabled. An interrupt request will be generated when the XOSC32K Clock Failure Detection interrupt flag is set. Bit 1 – OSC32KRDY OSC32K Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the OSC32K Ready Interrupt Enable bit, which enables the OSC32K Ready interrupt. Value Description 0 The OSC32K Ready interrupt is disabled. 1 The OSC32K Ready interrupt is enabled. Bit 0 – XOSC32KRDY XOSC32K Ready Interrupt Enable Writing a '0' to this bit has no effect. SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 260

Writing a '1' to this bit will set the XOSC32K Ready Interrupt Enable bit, which enables the XOSC32K Ready interrupt. Value Description 0 The XOSC32K Ready interrupt is disabled. 1 The XOSC32K Ready interrupt is enabled. SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 261

21.8.3 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x08 Reset: 0x00000000 Property: – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CLKFAIL OSC32KRDY XOSC32KRDY Access R/W R/W R/W Reset 0 0 0 Bit 2 – CLKFAIL XOSC32K Clock Failure Detection This flag is cleared by writing a '1' to it. This flag is set on a zero-to-one transition of the XOSC32K Clock Failure Detection bit in the Status register (STATUS.CLKFAIL) and will generate an interrupt request if INTENSET.CLKFAIL is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the XOSC32K Clock Failure Detection flag. Bit 1 – OSC32KRDY OSC32K Ready This flag is cleared by writing a '1' to it. This flag is set by a zero-to-one transition of the OSC32K Ready bit in the Status register (STATUS.OSC32KRDY), and will generate an interrupt request if INTENSET.OSC32KRDY=1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the OSC32K Ready interrupt flag. Bit 0 – XOSC32KRDY XOSC32K Ready This flag is cleared by writing a '1' to it. This flag is set by a zero-to-one transition of the XOSC32K Ready bit in the Status register (STATUS.XOSC32KRDY), and will generate an interrupt request if INTENSET.XOSC32KRDY=1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the XOSC32K Ready interrupt flag. SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 262

21.8.4 Status

Name: STATUS Offset: 0x0C Reset: 0x00000000 Property: – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CLKSW CLKFAIL OSC32KRDY XOSC32KRDY Access R R R R Reset 0 0 0 0 Bit 3 – CLKSW XOSC32K Clock Switch Value Description 0 XOSC32K is not switched and provided the crystal oscillator. 1 XOSC32K is switched to be provided by the safe clock. Bit 2 – CLKFAIL XOSC32K Clock Failure Detector Value Description 0 XOSC32K is passing failure detection. 1 XOSC32K is not passing failure detection. Bit 1 – OSC32KRDY OSC32K Ready Value Description 0 OSC32K is not ready. 1 OSC32K is stable and ready to be used as a clock source. Bit 0 – XOSC32KRDY XOSC32K Ready Value Description 0 XOSC32K is not ready. 1 XOSC32K is stable and ready to be used as a clock source. SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 263

21.8.5 RTC Clock Selection Control

Name: RTCCTRL Offset: 0x10 Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 RTCSEL[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 2:0 – RTCSEL[2:0] RTC Clock Source Selection These bits select the source for the RTC. Value Name Description 0x0 ULP1K 1.024 kHz from 32 kHz internal ULP oscillator 0x1 ULP32K 32.768 kHz from 32 kHz internal ULP oscillator 0x2 OSC1K 1.024 kHz from 32 kHz internal oscillator 0x3 OSC32K 32.768 kHz from 32 kHz internal oscillator 0x4 XOSC1K 1.024 kHz from 32 kHz external oscillator 0x5 XOSC32K 32.768 kHz from 32 kHz external crystal oscillator 0x6 Reserved 0x7 Reserved SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 264

21.8.6 32KHz External Crystal Oscillator (XOSC32K) Control Name: XOSC32K Offset: 0x14 Reset: 0x00000080 Property: PAC Write-Protection Bit 15 14 13 12 11 10 9 8 WRTLOCK STARTUP[2:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY EN1K EN32K XTALEN ENABLE Access R/W R/W R/W R/W R/W R/W Reset 1 0 0 0 0 0 Bit 12 – WRTLOCK Write Lock This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration. Value Description 0 The XOSC32K configuration is not locked. 1 The XOSC32K configuration is locked. Bits 10:8 – STARTUP[2:0] Oscillator Start-Up Time These bits select the start-up time for the oscillator. The OSCULP32K oscillator is used to clock the start-up counter. Table 21-3. Start-Up Time for 32KHz External Crystal Oscillator STARTUP[2:0] Number of OSCULP32K Clock Cycles Number of XOSC32K Clock Cycles Approximate Equivalent Time [s] 0x0 2048 3 0.06 0x1 4096 3 0.13 0x2 16384 3 0.5 0x3 32768 3 1 0x4 65536 3 2 0x5 131072 3 4 0x6 262144 3 8 0x7 - - Reserved Note: 1. Actual Start-Up time is 1 OSCULP32K cycle + 3 XOSC32K cycles. 2. The given time assumes an XTAL frequency of 32.768kHz. SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 265

Bit 7 – ONDEMAND On Demand Control This bit controls how the XOSC32K behaves when a peripheral clock request is detected. For details, refer to XOSC32K Sleep Behavior. Bit 6 – RUNSTDBY Run in Standby This bit controls how the XOSC32K behaves during standby sleep mode. For details, refer to XOSC32K Sleep Behavior. Bit 4 – EN1K 1KHz Output Enable Value Description 0 The 1KHz output is disabled. 1 The 1KHz output is enabled, and available internally only for RTC. Bit 3 – EN32K 32KHz Output Enable Value Description 0 The 32KHz output is disabled. 1 The 32KHz output is enabled, and can be routed to GCLK/GCLK_IO. Bit 2 – XTALEN Crystal Oscillator Enable This bit controls the connections between the I/O pads and the external clock or crystal oscillator. Value Description 0 External clock connected on XIN32. XOUT32 can be used as general-purpose I/O. 1 Crystal connected to XIN32/XOUT32. Bit 1 – ENABLE Oscillator Enable Value Description 0 The oscillator is disabled. 1 The oscillator is enabled. SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 266

21.8.7 Clock Failure Detector Control

Name: CFDCTRL Offset: 0x16 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CFDPRESC SWBACK CFDEN Access R/W R/W R/W Reset 0 0 0 Bit 2 – CFDPRESC Clock Failure Detector Prescaler This bit selects the prescaler for the Clock Failure Detector. Value Description

0 The CFD safe clock frequency is the OSCULP32K frequency

1 The CFD safe clock frequency is the OSCULP32K frequency divided by 2

Bit 1 – SWBACK Clock Switch Back This bit clontrols the XOSC32K output switch back to the external clock or crystal scillator in case of clock recovery. Value Description 0 The clock switch is disabled. 1 The clock switch is enabled. This bit is reset when the XOSC32K output is switched back to the external clock or crystal oscillator. Bit 0 – CFDEN Clock Failure Detector Enable This bit selects the Clock Failure Detector state. Value Description 0 The CFD is disabled. 1 The CFD is enabled. SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 267

21.8.8 Event Control

Name: EVCTRL Offset: 0x17 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CFDEO Access R/W Reset 0 Bit 0 – CFDEO Clock Failure Detector Event Out Enable This bit controls whether the Clock Failure Detector event output is enabled and an event will be generated when the CFD detects a clock failure. Value Description 0 Clock Failure Detector Event output is disabled, no event will be generated. 1 Clock Failure Detector Event output is enabled, an event will be generated. SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 268

21.8.9 32KHz Internal Oscillator (OSC32K) Control Name: OSC32K Offset: 0x18 Reset: 0x0000 0080 (Writing action by User required) Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 CALIB[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 WRTLOCK STARTUP[2:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY EN1K EN32K ENABLE Access R/W R/W R/W R/W R/W Reset 1 0 0 0 0 Bits 22:16 – CALIB[6:0] Oscillator Calibration These bits control the oscillator calibration. The calibration values must be loaded by the user from the NVM Software Calibration Area. Bit 12 – WRTLOCK Write Lock This bit locks the OSC32K register for future writes, effectively freezing the OSC32K configuration. Value Description 0 The OSC32K configuration is not locked. 1 The OSC32K configuration is locked. Bits 10:8 – STARTUP[2:0] Oscillator Start-Up Time These bits select start-up time for the oscillator. The OSCULP32K oscillator is used as input clock to the start-up counter. Table 21-4. Start-Up Time for 32KHz Internal Oscillator STARTUP[2:0] Number of OSC32K clock cycles Approximate Equivalent Time [ms] 0x0 3 0.092 0x1 4 0.122 0x2 6 0.183 0x3 10 0.305 SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 269

STARTUP[2:0] Number of OSC32K clock cycles Approximate Equivalent Time [ms] 0x4 18 0.549 0x5 34 1.038 0x6 66 2.014 0x7 130 3.967 Note: 1. Start-up time is given by STARTUP + three OSC32K cycles. 2. The given time assumes an XTAL frequency of 32.768kHz. Bit 7 – ONDEMAND On Demand Control This bit controls how the OSC32K behaves when a peripheral clock request is detected. For details, refer to OSC32K Sleep Behavior. Bit 6 – RUNSTDBY Run in Standby This bit controls how the OSC32K behaves during standby sleep mode. For details, refer to OSC32K Sleep Behavior. Bit 3 – EN1K 1KHz Output Enable Value Description 0 The 1KHz output is disabled. 1 The 1KHz output is enabled, and available internally only for RTC. Bit 2 – EN32K 32KHz Output Enable Value Description 0 The 32KHz output is disabled. 1 The 32KHz output is enabled, and can be routed to GCLK/GCLK_IO. Bit 1 – ENABLE Oscillator Enable Value Description 0 The oscillator is disabled. 1 The oscillator is enabled. SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 270

21.8.10 32KHz Ultra Low Power Internal Oscillator (OSCULP32K) Control Name: OSCULP32K Offset: 0x1C Reset: 0x0000XX06 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 WRTLOCK CALIB[4:0] Access R/W R/W R/W R/W R/W R/W Reset 0 x x x x x Bit 7 6 5 4 3 2 1 0 Access Reset Bit 15 – WRTLOCK Write Lock This bit locks the OSCULP32K register for future writes to fix the OSCULP32K configuration. Value Description 0 The OSCULP32K configuration is not locked. 1 The OSCULP32K configuration is locked. Bits 12:8 – CALIB[4:0] Oscillator Calibration These bits control the oscillator calibration. These bits are loaded from Flash Calibration at startup. SAM C20/C21 Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 271

SUPC – Supply Controller

22.1 Overview

The Supply Controller (SUPC) manages the voltage reference and power supply of the device. The SUPC controls the voltage regulators for the core (VDDCORE) domain. It sets the voltage regulators according to the sleep modes, or the user configuration. The SUPC embeds two Brown-Out Detectors. BODVDD monitors the voltage applied to the device (VDD) and BODCORE monitors the internal voltage to the core (VDDCORE). The BOD can monitor the supply voltage continuously (continuous mode) or periodically (sampling mode). The SUPC generates also a selectable reference voltage and a voltage dependent on the temperature which can be used by analog modules like the ADC, SDADC or DAC.

22.2 Features

Voltage Regulator System – Main voltage regulator: LDO in active mode (MAINVREG) – Low Power voltage regulator in standby mode (LPVREG)
Voltage Reference System – Reference voltage for ADC, SDADC and DAC – Temperature sensor
VDD Brown-Out Detector (BODVDD) – Programmable threshold – Threshold value loaded from NVM User Row at startup – Triggers resets or interrupts. Action loaded from NVM User Row – Operating modes:
Continuous mode
Sampled mode for low power applications with programmable sample frequency – Hysteresis value from Flash User Calibration
VDDCORE Brown-Out Detector (BODCORE) – Internal non-configurable Brown-Out Detector SAM C20/C21 Family Data Sheet SUPC – Supply Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 272

22.3 Block Diagram

Figure 22-1. SUPC Block Diagram LDO LP VREG VDDCORE BODCORE VDD BODVDD BODVDD BODCORE VREG Core domain PM sleep mode VREFVREF temperature sensor reference voltage Main VREG

22.4 Signal Description

Not appclicable. Related Links 6. I/O Multiplexing and Considerations

22.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

22.5.1 I/O Lines

Not applicable.

22.5.2 Power Management

The SUPC can operate in all sleep modes. Related Links 19. PM – Power Manager

22.5.3 Clocks

The SUPC bus clock (CLK_SUPC_APB) can be enabled and disabled in the Main Clock module. A 32KHz clock, asynchronous to the user interface clock (CLK_SUPC_APB), is required to run BODVDD and BODCORE in sampled mode. Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains. Refer to 22.6.5 Synchronization for further details. Related Links 21. OSC32KCTRL – 32KHz Oscillators Controller SAM C20/C21 Family Data Sheet SUPC – Supply Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 273

22.5.4 DMA

Not applicable.

22.5.5 Interrupts

The interrupt request lines are connected to the interrupt controller. Using the SUPC interrupts requires the interrupt controller to be configured first. Related Links

22.5.6 Events

Not applicable.

22.5.7 Debug Operation

When the CPU is halted in debug mode, the SUPC continues normal operation. If the SUPC is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. If debugger cold-plugging is detected by the system, BODVDD and BODCORE resets will be masked. The BOD resets keep running under hot-plugging. This allows to correct a BODVDD user level too high for the available supply.

22.5.8 Register Access Protection

Registers with write-access can be write-protected optionally by the peripheral access controller (PAC). Note: Not all registers with write-access can be write-protected. PAC Write-Protection is not available for the following registers:

Interrupt Flag Status and Clear register (INTFLAG) Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register description. Related Links 11. PAC - Peripheral Access Controller

22.5.9 Analog Connections

Not applicable.

22.6 Functional Description

22.6.1 Voltage Regulator System Operation

22.6.1.1 Enabling, Disabling, and Resetting

The LDO main voltage regulator is enabled after any Reset. The main voltage regulator (MAINVREG) can be disabled by writing the Enable bit in the VREG register (VREG.ENABLE) to zero. The main voltage regulator output supply level is automatically defined by the sleep mode selected in the Power Manager module. Related Links 19. PM – Power Manager SAM C20/C21 Family Data Sheet SUPC – Supply Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 274

22.6.1.2 Initialization

After a Reset, the LDO voltage regulator supplying VDDCORE is enabled.

22.6.1.3 Sleep Mode Operation

In standby mode, the low power voltage regulator (LPVREG) is used to supply VDDCORE. When the Run in Standby bit in the VREG register (VREG.RUNSTDBY) is written to '1', VDDCORE is supplied by the main voltage regulator. The VDDCORE level is set to the active mode voltage level. Related Links

22.6.2 Voltage Reference System Operation

The reference voltages are generated by a functional block DETREF inside of the SUPC. DETREF is providing a fixed-voltage source, BANDGAP=1.1V, and a variable voltage, INTREF.

22.6.2.1 Initialization

The voltage reference output and the temperature sensor are disabled after any Reset.

22.6.2.2 Enabling, Disabling, and Resetting

The voltage reference output is enabled/disabled by setting/clearing the Voltage Reference Output Enable bit in the Voltage Reference register (VREF.VREFOE). The temperature sensor is enabled/disabled by setting/clearing the Temperature Sensor Enable bit in the Voltage Reference register (VREF.TSEN). Note: When VREF.ONDEMAND=0, it is not recommended to enable both voltage reference output and temperature sensor at the same time - only the voltage reference output will be present at both ADC inputs.

22.6.2.3 Selecting a Voltage Reference

The Voltage Reference Selection bit field in the VREF register (VREF.SEL) selects the voltage of INTREF to be applied to analog modules, e.g. the ADC.

22.6.2.4 Sleep Mode Operation

The Voltage Reference output and the Temperature Sensor output behavior during sleep mode can be configured using the Run in Standby bit and the On Demand bit in the Voltage Reference register (VREF.RUNSTDBY, VREF.ONDEMAND), see the following table: Table 22-1. VREF Sleep Mode Operation VREF.ONDEMAND VREF.RUNSTDBY Voltage Reference Sleep behavior - - Disable 0 0 Always run in all sleep modes except standby sleep mode 0 1 Always run in all sleep modes including standby sleep mode 1 0 Only run if requested by the ADC, in all sleep modes except standby sleep mode 1 1 Only run if requested by the ADC, in all sleep modes including standby sleep mode SAM C20/C21 Family Data Sheet SUPC – Supply Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 275

22.6.3 Brown-Out Detectors

22.6.3.1 Initialization

Before a Brown-Out Detector (BODVDD) is enabled, it must be configured, as outlined by the following:

Set the BOD threshold level (BODVDD.LEVEL)
Set the configuration in Active, Standby (BODVDD.ACTION, BODVDD.STDBYCFG)
Set the prescaling value if the BOD will run in sampling mode (BODVDD.PSEL)
Set the action and hysteresis (BODVDD.ACTION and BODVDD.HYST) The BODVDD register is Enable-Protected, meaning that they can only be written when the BOD is disabled (BODVDD.ENABLE=0 and STATUS.BVDDSRDY=0). As long as the Enable bit is '1', any writes to Enable-Protected registers will be discarded, and an APB error will be generated. The Enable bits are not Enable-Protected.

22.6.3.2 Enabling, Disabling, and Resetting

After power or user reset, the BODVDD and BODCORE register values are loaded from the NVM User Page. The BODVDD is enabled by writing a '1' to the Enable bit in the BOD control register (BODVDD.ENABLE). The BOD is disabled by writing a '0' to the BODVDD.ENABLE. Related Links

22.6.3.3 VDD Brown-Out Detector (BODVDD)

The VDD Brown-Out Detector (BODVDD) is able to monitor the VDD supply and compares the voltage with the brown-out threshold level set in the BODVDD Level field (BODVDD.LEVEL) in the BODVDD register. When VDD crosses below the brown-out threshold level, the BODVDD can generate either an interrupt or a Reset, depending on the BODVDD Action bit field (BODVDD.ACTION). The BODVDD detection status can be read from the BODVDD Detection bit in the Status register (STATUS.BODVDDDET). At start-up or at Power-On Reset (POR), the BODVDD register values are loaded from the NVM User Row. Related Links

45.10.2 Brown Out Detectors Characteristics

22.6.3.4 VDDCORE Brown-Out Detector (BODCORE)

The BODCORE is calibrated in production and its calibration configuration is stored in the NVM User Row. This configuration must not be changed to assure the correct behavior of the BODCORE. The BODCORE generates a reset when VDDCORE crosses below the preset brown-out level. The BODCORE is always disabled in Standby Sleep mode. Related Links

22.6.3.5 Continuous Mode

The BODVDD is continuously monitoring the VDD supply voltage if it is enabled (BODVDD.ENABLE=1) and if the BODVDD Configuration bit in the BODVDD register is cleared (BODVDD.ACTCFG=0 for active mode, BODVDD.STDBYCFG=0 for standby mode).

22.6.3.6 Sampling Mode

The Sampling Mode is a low-power mode where the BODVDD is being repeatedly enabled on a sampling clock’s ticks. The BODVDD will monitor the supply voltage for a short period of time and then go to a low- power disabled state until the next sampling clock tick. Sampling mode is enabled in Active mode for BODVDD by writing the ACTCFG bit (BODVDD.ACTCFG=1). Sampling mode is enabled in Standby mode by writing to the STDBYCFG bit (BODVDD.STBYCFG=1). The frequency of the clock ticks (Fclksampling) is controlled by the Prescaler Select bit groups in the BODVDD register (BODVDD.PSEL). ʹ PSEL + ͳ The prescaler signal (Fclkprescaler) is a 1KHz clock, output by the 32KHz Ultra Low Power Oscillator OSCULP32K. As the sampling clock is different from the APB clock domain, synchronization among the clocks is necessary. See also 22.6.5 Synchronization.

22.6.3.7 Hysteresis

A hysteresis on the trigger threshold of a BOD will reduce the sensitivity to ripples on the monitored voltage: instead of switching RESET at each crossing of VBOD, the thresholds for switching RESET on and off are separated (VBOD- and VBOD+, respectively). Figure 22-2. BOD Hysteresis Principle Hysteresis OFF: VCC RESET VBOD Hysteresis ON: VCC RESET VBOD- VBOD+ Enabling the BODVDD hysteresis by writing the Hysteresis bit in the BODVDD register (BODVDD.HYST) to '1' will add hysteresis to the BODVDD threshold level. The hysteresis functionality can be used in both Continuous and Sampling Mode.

22.6.3.8 Sleep Mode Operation

22.6.3.8.1 Standby Mode

The BODVDD can be used in standby mode if the BOD is enabled and the corresponding Run in Standby bit is written to '1' (BODVDD.RUNSTDBY). The BODVDD can be configured to work in either Continuous or Sampling Mode by writing a '1' to the Configuration in Standby Sleep Mode bit (BODVDD.STDBYCFG). SAM C20/C21 Family Data Sheet SUPC – Supply Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 277

22.6.4 Interrupts

The SUPC has the following interrupt sources, which are either synchronous or asynchronous wake-up sources:

BODVDD Ready (BODVDDRDY), synchronous
BODVDD Detection (BODVDDDET), asynchronous
BODVDD Synchronization Ready (BVDDSRDY), synchronous Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the SUPC is reset. See the INTFLAG register for details on how to clear interrupt flags. The SUPC has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register to determine which interrupt condition is present. Note: Interrupts must be globally enabled for interrupt requests to be generated. Related Links

22.6.5 Synchronization

The prescaler counters that are used to trigger brown-out detections operate asynchronously from the peripheral bus. As a consequence, the BODVDD Enable bit (BODVDD.ENABLE) need synchronization when written. The Write-Synchronization of the Enable bit is triggered by writing a '1' to the Enable bit of the BODVDD Control register. The Synchronization Ready bit (STATUS.BVDDSRDY) in the STATUS register will be cleared when the Write-Synchronization starts, and set again when the Write-Synchronization is complete. Writing to the same register while the Write-Synchronization is ongoing (STATUS.BVDDSRDY is '0') will generate a PAC error without stalling the APB bus. SAM C20/C21 Family Data Sheet SUPC – Supply Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 278

22.7 Register Summary

Offset Name Bit Pos. 0x00 INTENCLR 7:0 BVDDSRDY BODVDDDET BODVDDRDY 15:8 23:16 31:24 0x04 INTENSET 7:0 BVDDSRDY BODVDDDET BODVDDRDY 15:8 23:16 31:24 0x08 INTFLAG 7:0 BVDDSRDY BODVDDDET BODVDDRDY 15:8 23:16 31:24 0x0C STATUS 7:0 BVDDSRDY BODVDDDET BODVDDRDY 15:8 23:16 31:24 0x10 BODVDD 7:0 RUNSTDBY STDBYCFG ACTION[1:0] HYST ENABLE 15:8 PSEL[3:0] ACTCFG 23:16 LEVEL[5:0] 31:24 0x14 ... 0x17 Reserved 0x18 VREG 7:0 RUNSTDBY ENABLE 15:8 23:16 31:24 0x1C VREF 7:0 ONDEMAND RUNSTDBY VREFOE 15:8 23:16 SEL[3:0] 31:24

22.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). PAC Write- protection is denoted by the "PAC Write-Protection" property in each individual register description. Refer to 22.5.8 Register Access Protection for details. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Write-Synchronized" or the "Read-Synchronized" property in each individual register description. Refer to 22.6.5 Synchronization for details. SAM C20/C21 Family Data Sheet SUPC – Supply Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 279

22.8.1 Interrupt Enable Clear

1 The BODVDD Synchronization Ready interrupt is enabled, and an interrupt request will be

generated when the BODVDD Synchronization Ready Interrupt flag is set. Bit 1 – BODVDDDET BODVDD Detection Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the BODVDD Detection Interrupt Enable bit, which disables the BODVDD Detection interrupt. Value Description 0 The BODVDD Detection interrupt is disabled.

1 The BODVDD Detection interrupt is enabled, and an interrupt request will be generated

when the BODVDD Detection Interrupt flag is set. Bit 0 – BODVDDRDY BODVDD Ready Interrupt Enable Writing a '0' to this bit has no effect. SAM C20/C21 Family Data Sheet SUPC – Supply Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 280

Writing a '1' to this bit will clear the BODVDD Ready Interrupt Enable bit, which disables the BODVDD Ready interrupt. Value Description 0 The BODVDD Ready interrupt is disabled.

1 The BODVDD Ready interrupt is enabled, and an interrupt request will be generated when

22.8.2 Interrupt Enable Set

Name: INTENSET Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 BVDDSRDY BODVDDDET BODVDDRDY Access R/W R/W R/W Reset 0 0 0 Bit 2 – BVDDSRDY BODVDD Synchronization Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the BODVDD Synchronization Ready Interrupt Enable bit, which enables the BODVDD Synchronization Ready interrupt. Value Description 0 The BODVDD Synchronization Ready interrupt is disabled. generated when the BODVDD Synchronization Ready Interrupt flag is set. Bit 1 – BODVDDDET BODVDD Detection Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the BODVDD Detection Interrupt Enable bit, which enables the BODVDD Detection interrupt. Value Description 0 The BODVDD Detection interrupt is disabled. when the BODVDD Detection Interrupt flag is set. Bit 0 – BODVDDRDY BODVDD Ready Interrupt Enable Writing a '0' to this bit has no effect. SAM C20/C21 Family Data Sheet SUPC – Supply Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 282

Writing a '1' to this bit will set the BODVDD Ready Interrupt Enable bit, which enables the BODVDD Ready interrupt. Value Description 0 The BODVDD Ready interrupt is disabled. the BODVDD Ready Interrupt flag is set. SAM C20/C21 Family Data Sheet SUPC – Supply Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 283

22.8.3 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x08 Reset: X determined from NVM User Row Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 BVDDSRDY BODVDDDET BODVDDRDY Access R/W R/W R/W Reset 0 0 x Bit 2 – BVDDSRDY BODVDD Synchronization Ready This flag is cleared by writing a '1' to it. This flag is set on a zero-to-one transition of the BODVDD Synchronization Ready bit in the Status register (STATUS.BVDDSRDY) and will generate an interrupt request if INTENSET.BVDDSRDY=1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the BODVDD Synchronization Ready interrupt flag. Bit 1 – BODVDDDET BODVDD Detection This flag is cleared by writing a '1' to it. This flag is set on a zero-to-one transition of the BODVDD Detection bit in the Status register (STATUS.BODVDDDET) and will generate an interrupt request if INTENSET.BODVDDDET=1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the BODVDD Detection interrupt flag. Bit 0 – BODVDDRDY BODVDD Ready This flag is cleared by writing a '1' to it. This flag is set on a zero-to-one transition of the BODVDD Ready bit in the Status register (STATUS.BODVDDRDY) and will generate an interrupt request if INTENSET.BODVDDRDY=1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the BODVDD Ready interrupt flag. The BODVDD can be enabled. Related Links SAM C20/C21 Family Data Sheet SUPC – Supply Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 284

22.8.4 Status

Name: STATUS Offset: 0x0C Reset: Determined from NVM User Row Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 BVDDSRDY BODVDDDET BODVDDRDY Access R R R Reset 0 0 y Bit 2 – BVDDSRDY BODVDD Synchronization Ready Value Description 0 BODVDD synchronization is ongoing. 1 BODVDD synchronization is complete. Bit 1 – BODVDDDET BODVDD Detection Value Description 0 No BODVDD detection.

1 BODVDD has detected that the I/O power supply is going below the BODVDD reference

value. Bit 0 – BODVDDRDY BODVDD Ready The BODVDD can be enabled at start-up from NVM User Row. Value Description 0 BODVDD is not ready. 1 BODVDD is ready. Related Links SAM C20/C21 Family Data Sheet SUPC – Supply Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 286

22.8.5 VDD Brown-Out Detector (BODVDD) Control

Name: BODVDD Offset: 0x10 Reset: X determined from NVM User Row Property: Write-Synchronized, Enable-Protected, PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 LEVEL[5:0] Access R/W R/W R/W R/W R/W R/W Reset x x x x x x Bit 15 14 13 12 11 10 9 8 PSEL[3:0] ACTCFG Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RUNSTDBY STDBYCFG ACTION[1:0] HYST ENABLE Access R/W R/W R/W R/W R/W R/W Reset 0 0 x x x x Bits 21:16 – LEVEL[5:0] BODVDD Threshold Level on VDD These bits set the triggering voltage threshold for the BODVDD when the BODVDD monitors the VDD. These bits are loaded from NVM User Row at start-up. This bit field is not synchronized. Bits 15:12 – PSEL[3:0] Prescaler Select Selects the prescaler divide-by output for the BODVDD sampling mode. The input clock comes from the OSCULP32K 1KHz output. Value Name Description 0x0 DIV2 Divide clock by 2 0x1 DIV4 Divide clock by 4 0x2 DIV8 Divide clock by 8 0x3 DIV16 Divide clock by 16 0x4 DIV32 Divide clock by 32 0x5 DIV64 Divide clock by 64 0x6 DIV128 Divide clock by 128 0x7 DIV256 Divide clock by 256 0x8 DIV512 Divide clock by 512 0x9 DIV1024 Divide clock by 1024 0xA DIV2048 Divide clock by 2048 0xB DIV4096 Divide clock by 4096 SAM C20/C21 Family Data Sheet SUPC – Supply Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 287

0xC DIV8192 Divide clock by 8192 0xD DIV16384 Divide clock by 16384 0xE DIV32768 Divide clock by 32768 0xF DIV65536 Divide clock by 65536 Bit 8 – ACTCFG BODVDD Configuration in Active Sleep Mode This bit is not synchronized. Value Description 0 In active mode, the BODVDD operates in continuous mode. 1 In active mode, the BODVDD operates in sampling mode. Bit 6 – RUNSTDBY Run in Standby This bit is not synchronized. Value Description 0 In standby sleep mode, the BODVDD is disabled. 1 In standby sleep mode, the BODVDD is enabled. Bit 5 – STDBYCFG BODVDD Configuration in Standby Sleep Mode If the RUNSTDBY bit is set to '1', the STDBYCFG bit sets the BODVDD configuration in standby sleep mode. This bit is not synchronized. Value Description 0 In standby sleep mode, the BODVDD is enabled and configured in continuous mode. 1 In standby sleep mode, the BODVDD is enabled and configured in sampling mode. Bits 4:3 – ACTION[1:0] BODVDD Action These bits are used to select the BODVDD action when the supply voltage crosses below the BODVDD threshold. These bits are loaded from NVM User Row at start-up. This bit field is not synchronized. Value Name Description 0x0 NONE No action 0x1 RESET The BODVDD generates a reset 0x2 INT The BODVDD generates an interrupt 0x3 - Reserved Bit 2 – HYST Hysteresis This bit indicates whether hysteresis is enabled for the BODVDD threshold voltage. This bit is loaded from NVM User Row at start-up. This bit is not synchronized. Value Description 0 No hysteresis. 1 Hysteresis enabled. SAM C20/C21 Family Data Sheet SUPC – Supply Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 288

Bit 1 – ENABLE Enable This bit is loaded from NVM User Row at start-up. This bit is not enable-protected. Value Description 0 BODVDD is disabled. 1 BODVDD is enabled. Related Links 45. Electrical Characteristics 85°C (SAM C20/C21 E/G/J) SAM C20/C21 Family Data Sheet SUPC – Supply Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 289

22.8.6 Voltage Regulator System (VREG) Control

Name: VREG Offset: 0x18 Reset: 0x00000002 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RUNSTDBY ENABLE Access R R/W R R R R R/W R Reset 0 0 0 0 0 0 1 0 Bit 6 – RUNSTDBY Run in Standby Value Description 0 The voltage regulator is in Low-Power mode in Standby-Sleep mode. 1 The voltage regulator is in normal mode in Standby-Sleep mode. Bit 1 – ENABLE Must be set to 1. SAM C20/C21 Family Data Sheet SUPC – Supply Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 290

22.8.7 Voltage References System (VREF) Control

Name: VREF Offset: 0x1C Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 SEL[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY VREFOE Access R/W R/W R/W Reset 0 0 0 Bits 19:16 – SEL[3:0] Voltage Reference Selection These bits select the Voltage Reference for the ADC/ SDADC/DAC. Value Description 0x0 1.024V voltage reference typical value 0x2 2.048V voltage reference typical value 0x3 4.096V voltage reference typical value Others Reserved Bit 7 – ONDEMAND On Demand Control The On Demand operation mode allows to enable or disable the voltage reference depending on peripheral requests. Value Description 0 The voltage reference is always on, if enabled. 1 The voltage reference is enabled when a peripheral is requesting it. The voltage reference is disabled if no peripheral is requesting it. Bit 6 – RUNSTDBY Run In Standby The bit controls how the voltage reference behaves during Standby Sleep mode. Value Description 0 The voltage reference is halted during Standby Sleep mode. SAM C20/C21 Family Data Sheet SUPC – Supply Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 291

1 The voltage reference is not stopped in Standby Sleep mode. If VREF.ONDEMAND=1, the voltage reference will be running when a peripheral is requesting it. If VREF.ONDEMAND=0, the voltage reference will always be running in Standby Sleep mode. Bit 2 – VREFOE Voltage Reference Output Enable Value Description 0 The Voltage Reference output is not available as an ADC input channel. 1 The Voltage Reference output is routed to an ADC input channel. SAM C20/C21 Family Data Sheet SUPC – Supply Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 292

WDT – Watchdog Timer

23.1 Overview

The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover from error situations such as runaway or deadlocked code. The WDT is configured to a predefined time-out period, and is constantly running when enabled. If the WDT is not cleared within the time-out period, it will issue a system reset. An early-warning interrupt is available to indicate an upcoming watchdog time-out condition. The window mode makes it possible to define a time slot (or window) inside the total time-out period during which the WDT must be cleared. If the WDT is cleared outside this window, either too early or too late, a system reset will be issued. Compared to the normal mode, this can also catch situations where a code error causes the WDT to be cleared frequently. When enabled, the WDT will run in active mode and all sleep modes. It is asynchronous and runs from a CPU-independent clock source. The WDT will continue operation and issue a system reset or interrupt even if the main clocks fail.

23.2 Features

Issues a system reset if the Watchdog Timer is not cleared before its time-out period
Early Warning interrupt generation
Asynchronous operation from dedicated oscillator
Two types of operation – Normal – Window mode
Selectable time-out periods – From 8 cycles to 16,384 cycles in Normal mode – From 16 cycles to 32,768 cycles in Window mode
Always-On capability SAM C20/C21 Family Data Sheet WDT – Watchdog Timer © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 293

23.3 Block Diagram

Figure 23-1. WDT Block Diagram 0xA5 CLEAR COUNT CLK_WDT_OSC OSC32KCTRL PER/WINDOWS/EWOFFSET Early Warning Interrupt Reset

23.4 Signal Description

Not applicable.

23.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

23.5.1 I/O Lines

Not applicable.

23.5.2 Power Management

The WDT can continue to operate in any sleep mode where the selected source clock is running. The WDT interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes. Related Links 19. PM – Power Manager

23.5.3 Clocks

The WDT bus clock (CLK_WDT_APB) can be enabled and disabled (masked) in the Main Clock module (MCLK). A 1 kHz oscillator clock (CLK_WDT_OSC) is required to clock the WDT internal counter. CLK_WDT_OSC is sourced from the clock of the internal ultra-low-power oscillator, OSCULP32K. Due to the ultra-low-power design, the oscillator is not very accurate, and so the exact time-out period may vary from device to device. This variation must be kept in mind when designing software that uses the WDT to ensure that the time-out periods used are valid for all devices. SAM C20/C21 Family Data Sheet WDT – Watchdog Timer © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 294

The counter clock CLK_WDT_OSC is asynchronous to the bus clock (CLK_WDT_APB). Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains. Refer to 23.6.7 Synchronization for further details. Related Links

OSC32KCTRL – 32KHz Oscillators Controller

23.5.4 DMA

Not applicable.

23.5.5 Interrupts

The interrupt request line is connected to the interrupt controller. Using the WDT interrupt(s) requires the interrupt controller to be configured first. Related Links

23.5.6 Events

Not applicable.

23.5.7 Debug Operation

When the CPU is halted in debug mode the WDT will halt normal operation.

23.5.8 Register Access Protection

All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Interrupt Flag Status and Clear (INTFLAG) register Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write- Protection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger.

23.5.9 Analog Connections

Not applicable.

23.6 Functional Description

23.6.1 Principle of Operation

The Watchdog Timer (WDT) is a system for monitoring correct program operation, making it possible to recover from error situations such as runaway code, by issuing a Reset. When enabled, the WDT is a constantly running timer that is configured to a predefined time-out period. Before the end of the time-out period, the WDT should be set back, or else, a system Reset is issued. The WDT has two modes of operation, Normal mode and Window mode. Both modes offer the option of Early Warning interrupt generation. The description for each of the basic modes is given below. The settings in the Control A register (CTRLA) and the Interrupt Enable register (handled by INTENCLR/ INTENSET) determine the mode of operation: SAM C20/C21 Family Data Sheet WDT – Watchdog Timer © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 295

Table 23-1. WDT Operating Modes CTRLA.ENABLE CTRLA.WEN Interrupt Enable Mode 0 x x Stopped 1 0 0 Normal mode 1 0 1 Normal mode with Early Warning interrupt 1 1 0 Window mode 1 1 1 Window mode with Early Warning interrupt

23.6.2 Basic Operation

23.6.2.1 Initialization

The following bits are enable-protected, meaning that they can only be written when the WDT is disabled (CTRLA.ENABLE=0):

Control A register (CTRLA), except the Enable bit (CTRLA.ENABLE)
Configuration register (CONFIG)
Early Warning Interrupt Control register (EWCTRL) Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1', but not at the same time as CTRLA.ENABLE is written to '0'. The WDT can be configured only while the WDT is disabled. The WDT is configured by defining the required Time-Out Period bits in the Configuration register (CONFIG.PER). If Window mode operation is desired, the Window Enable bit in the Control A register must be set (CTRLA.WEN=1) and the Window Period bits in the Configuration register (CONFIG.WINDOW) must be defined. Enable-protection is denoted by the "Enable-Protected" property in the register description.

23.6.2.2 Configurable Reset Values

After a Power-on Reset, some registers will be loaded with initial values from the NVM User Row. This includes the following bits and bit groups:

Enable bit in the Control A register, CTRLA.ENABLE
Always-On bit in the Control A register, CTRLA.ALWAYSON
Watchdog Timer Windows Mode Enable bit in the Control A register, CTRLA.WEN
Watchdog Timer Windows Mode Time-Out Period bits in the Configuration register, CONFIG.WINDOW
Time-Out Period bits in the Configuration register, CONFIG.PER
Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register, EWCTRL.EWOFFSET Related Links

23.6.2.3 Enabling, Disabling, and Resetting

The WDT is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The WDT is disabled by writing a '0' to CTRLA.ENABLE. The WDT can be disabled only if the Always-On bit in the Control A register (CTRLA.ALWAYSON) is '0'. SAM C20/C21 Family Data Sheet WDT – Watchdog Timer © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 296

23.6.2.4 Normal Mode

In Normal mode operation, the length of a time-out period is configured in CONFIG.PER. The WDT is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). Once enabled, the WDT will issue a system reset if a time-out occurs. This can be prevented by clearing the WDT at any time during the time-out period. The WDT is cleared and a new WDT time-out period is started by writing 0xA5 to the Clear register (CLEAR). Writing any other value than 0xA5 to CLEAR will issue an immediate system reset. There are 12 possible WDT time-out (TOWDT) periods, selectable from 8ms to 16s. By default, the early warning interrupt is disabled. If it is desired, the Early Warning Interrupt Enable bit in the Interrupt Enable register (INTENSET.EW) must be written to '1'. The Early Warning Interrupt is disabled again by writing a '1' to the Early Warning Interrupt bit in the Interrupt Enable Clear register (INTENCLR.EW). If the Early Warning Interrupt is enabled, an interrupt is generated prior to a WDT time-out condition. In Normal mode, the Early Warning Offset bits in the Early Warning Interrupt Control register, EWCTRL.EWOFFSET, define the time when the early warning interrupt occurs. The Normal mode operation is illustrated in the figure Normal-Mode Operation. Figure 23-2. Normal-Mode Operation 5 10 15 20 25 30 35 WDT Timeout Early Warning Interrupt Timely WDT Clear t[ms] TOWDT System Reset WDT Count PER[3:0] = 1 EWOFFSET[3:0] = 0

23.6.2.5 Window Mode

In Window mode operation, the WDT uses two different time specifications: the WDT can only be cleared by writing 0xA5 to the CLEAR register after the closed window time-out period (TOWDTW), during the subsequent Normal time-out period (TOWDT). If the WDT is cleared before the time window opens (before TOWDTW is over), the WDT will issue a system reset. Both parameters TOWDTW and TOWDT are periods in a range from 8ms to 16s, so the total duration of the WDT time-out period is the sum of the two parameters. The closed window period is defined by the Window Period bits in the Configuration register (CONFIG.WINDOW), and the open window period is defined by the Period bits in the Configuration register (CONFIG.PER). By default, the Early Warning interrupt is disabled. If it is desired, the Early Warning Interrupt Enable bit in the Interrupt Enable register (INTENSET.EW) must be written to '1'. The Early Warning Interrupt is disabled again by writing a '1' to the Early Warning Interrupt bit in the Interrupt Enable Clear (INTENCLR.EW) register. If the Early Warning interrupt is enabled in Window mode, the interrupt is generated at the start of the open window period, i.e. after TOWDTW. The Window mode operation is illustrated in figure Window-Mode Operation. SAM C20/C21 Family Data Sheet WDT – Watchdog Timer © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 297

Figure 23-3. Window-Mode Operation 5 10 15 20 25 30 35 WDT Timeout Early Warning Interrupt Timely WDT Clear t[ms] TOWDT System Reset WDT Count PER[3:0] = 0 WINDOW[3:0] = 0 TOWDTW Early WDT Clear Closed Open

23.6.3 DMA Operation

Not applicable.

23.6.4 Interrupts

The WDT has the following interrupt source:

Early Warning (EW): Indicates that the counter is approaching the time-out condition. – This interrupt is an asynchronous wake-up source. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the WDT is reset. See the 23.8.6 INTFLAG register description for details on how to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. The user must read the INTFLAG register to determine which interrupt condition is present. Note: Interrupts must be globally enabled for interrupt requests to be generated. Related Links

PM – Power Manager

23.6.5 Events

Not applicable.

23.6.6 Sleep Mode Operation

23.6.7 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following registers are synchronized when written:

Enable bit in Control A register (CTRLA.ENABLE)
Window Enable bit in Control A register (CTRLA.WEN)
Always-On bit in control Control A (CTRLA.ALWAYSON)
Watchdog Clear register (CLEAR) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Required read-synchronization is denoted by the "Read-Synchronized" property in the register description.

23.6.8 Additional Features

23.6.8.1 Always-On Mode

The Always-On mode is enabled by setting the Always-On bit in the Control A register (CTRLA.ALWAYSON=1). When the Always-On mode is enabled, the WDT runs continuously, regardless of the state of CTRLA.ENABLE. Once written, the Always-On bit can only be cleared by a power-on reset. The Configuration (CONFIG) and Early Warning Control (EWCTRL) registers are read-only registers while the CTRLA.ALWAYSON bit is set. Thus, the time period configuration bits (CONFIG.PER, CONFIG.WINDOW, EWCTRL.EWOFFSET) of the WDT cannot be changed. Enabling or disabling Window mode operation by writing the Window Enable bit (CTRLA.WEN) is allowed while in Always-On mode, but note that CONFIG.PER cannot be changed. The Interrupt Clear and Interrupt Set registers are accessible in the Always-On mode. The Early Warning interrupt can still be enabled or disabled while in the Always-On mode, but note that EWCTRL.EWOFFSET cannot be changed. Table WDT Operating Modes With Always-On shows the operation of the WDT for CTRLA.ALWAYSON=1. Table 23-2. WDT Operating Modes With Always-On WEN Interrupt Enable Mode 0 0 Always-on and normal mode 0 1 Always-on and normal mode with Early Warning interrupt 1 0 Always-on and window mode 1 1 Always-on and window mode with Early Warning interrupt

23.6.8.2 Early Warning

The Early Warning interrupt notifies that the WDT is approaching its time-out condition. The Early Warning interrupt behaves differently in Normal mode and in Window mode. In Normal mode, the Early Warning interrupt generation is defined by the Early Warning Offset in the Early Warning Control register (EWCTRL.EWOFFSET). The Early Warning Offset bits define the number of CLK_WDT_OSC clocks before the interrupt is generated, relative to the start of the watchdog time-out period. SAM C20/C21 Family Data Sheet WDT – Watchdog Timer © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 299

The user must take caution when programming the Early Warning Offset bits. If these bits define an Early Warning interrupt generation time greater than the watchdog time-out period, the watchdog time-out system reset is generated prior to the Early Warning interrupt. Consequently, the Early Warning interrupt will never be generated. In window mode, the Early Warning interrupt is generated at the start of the open window period. In a typical application where the system is in sleep mode, the Early Warning interrupt can be used to wake up and clear the Watchdog Timer, after which the system can perform other tasks or return to sleep mode. If the WDT is operating in Normal mode with CONFIG.PER = 0x2 and EWCTRL.EWOFFSET = 0x1, the Early Warning interrupt is generated 16 CLK_WDT_OSC clock cycles after the start of the time-out period. The time-out system reset is generated 32 CLK_WDT_OSC clock cycles after the start of the watchdog time- out period. SAM C20/C21 Family Data Sheet WDT – Watchdog Timer © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 300

23.7 Register Summary

Offset Name Bit Pos. 0x00 CTRLA 7:0 ALWAYSON WEN ENABLE 0x01 CONFIG 7:0 WINDOW[3:0] PER[3:0] 0x02 EWCTRL 7:0 EWOFFSET[3:0] 0x03 Reserved 0x04 INTENCLR 7:0 EW 0x05 INTENSET 7:0 EW 0x06 INTFLAG 7:0 EW 0x07 Reserved 0x08 SYNCBUSY 7:0 WEN ENABLE 15:8 23:16 31:24 0x0C CLEAR 7:0 CLEAR[7:0]

23.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 23.5.8 Register Access Protection. Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write- Synchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to 23.6.7 Synchronization. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. SAM C20/C21 Family Data Sheet WDT – Watchdog Timer © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 301

23.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: X determined from NVM User Row Property: PAC Write-Protection, Write-Synchronized Bit 7 6 5 4 3 2 1 0 ALWAYSON WEN ENABLE Access R/W R/W R/W Reset x x x Bit 7 – ALWAYSON Always-On This bit allows the WDT to run continuously. After being set, this bit cannot be written to '0', and the WDT will remain enabled until a power-on Reset is received. When this bit is '1', the Control A register (CTRLA), the Configuration register (CONFIG) and the Early Warning Control register (EWCTRL) will be read-only, and any writes to these registers are not allowed. Writing a '0' to this bit has no effect. This bit is not Enable-Protected. This bit is loaded from NVM User Row at start-up. Value Description 0 The WDT is enabled and disabled through the ENABLE bit. 1 The WDT is enabled and can only be disabled by a power-on reset (POR). Bit 2 – WEN Watchdog Timer Window Mode Enable This bit enables Window mode. It can only be written if the peripheral is disabled unless CTRLA.ALWAYSON=1. The initial value of this bit is loaded from Flash Calibration. This bit is loaded from NVM User Row at startup. Value Description 0 Window mode is disabled (normal operation). 1 Window mode is enabled. Bit 1 – ENABLE Enable This bit enables or disables the WDT. It can only be written if CTRLA.ALWAYSON=0. Due to synchronization, there is delay between writing CTRLA.ENABLE until the peripheral is enabled/ disabled. The value written to CTRLA.ENABLE will read back immediately, and the Enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not Enable-Protected. This bit is loaded from NVM User Row at startup. Value Description 0 The WDT is disabled. 1 The WDT is enabled. Related Links SAM C20/C21 Family Data Sheet WDT – Watchdog Timer © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 302

23.8.2 Configuration

Name: CONFIG Offset: 0x01 Reset: X determined from NVM User Row Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 WINDOW[3:0] PER[3:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Bits 7:4 – WINDOW[3:0] Window Mode Time-Out Period In Window mode, these bits determine the watchdog closed window period as a number of cycles of the 1.024kHz CLK_WDT_OSC clock. These bits are loaded from NVM User Row at start-up. Value Name Description 0x0 CYC8 8 clock cycles 0x1 CYC16 16 clock cycles 0x2 CYC32 32 clock cycles 0x3 CYC64 64 clock cycles 0x4 CYC128 128 clock cycles 0x5 CYC256 256 clock cycles 0x6 CYC512 512 clock cycles 0x7 CYC1024 1024 clock cycles 0x8 CYC2048 2048 clock cycles 0x9 CYC4096 4096 clock cycles 0xA CYC8192 8192 clock cycles 0xB - 0xF - Reserved Bits 3:0 – PER[3:0] Time-Out Period These bits determine the watchdog time-out period as a number of 1.024kHz CLK_WDTOSC clock cycles. In Window mode operation, these bits define the open window period. These bits are loaded from NVM User Row at startup. Value Name Description 0x0 CYC8 8 clock cycles 0x1 CYC16 16 clock cycles 0x2 CYC32 32 clock cycles 0x3 CYC64 64 clock cycles 0x4 CYC128 128 clock cycles 0x5 CYC256 256 clock cycles 0x6 CYC512 512 clock cycles 0x7 CYC1024 1024 clock cycles 0x8 CYC2048 2048 clock cycles 0x9 CYC4096 4096 clock cycles 0xA CYC8192 8192 clock cycles 0xB CYC16384 16384 clock cycles SAM C20/C21 Family Data Sheet WDT – Watchdog Timer © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 303

Reserved Related Links

23.8.3 Early Warning Control

Name: EWCTRL Offset: 0x02 Reset: X determined from NVM User Row Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 EWOFFSET[3:0] Access R/W R/W R/W R/W Reset x x x x Bits 3:0 – EWOFFSET[3:0] Early Warning Interrupt Time Offset These bits determine the number of GCLK_WDT clock cycles between the start of the watchdog time-out period and the generation of the Early Warning interrupt. These bits are loaded from NVM User Row at start-up. Value Name Description 0x0 CYC8 8 clock cycles 0x1 CYC16 16 clock cycles 0x2 CYC32 32 clock cycles 0x3 CYC64 64 clock cycles 0x4 CYC128 128 clock cycles 0x5 CYC256 256 clock cycles 0x6 CYC512 512 clock cycles 0x7 CYC1024 1024 clock cycles 0x8 CYC2048 2048 clock cycles 0x9 CYC4096 4096 clock cycles 0xA CYC8192 8192 clock cycles 0xB CYC16384 16384 clock cycles 0xC - 0xF - Reserved SAM C20/C21 Family Data Sheet WDT – Watchdog Timer © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 305

23.8.4 Interrupt Enable Clear

Name: INTENCLR Offset: 0x04 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 7 6 5 4 3 2 1 0 EW Access R/W Reset 0 Bit 0 – EW Early Warning Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Early Warning Interrupt Enable bit, which disables the Early Warning interrupt. Value Description 0 The Early Warning interrupt is disabled. 1 The Early Warning interrupt is enabled. SAM C20/C21 Family Data Sheet WDT – Watchdog Timer © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 306

23.8.5 Interrupt Enable Set

Name: INTENSET Offset: 0x05 Reset: 0x00 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 7 6 5 4 3 2 1 0 EW Access R/W Reset 0 Bit 0 – EW Early Warning Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit sets the Early Warning Interrupt Enable bit, which enables the Early Warning interrupt. Value Description 0 The Early Warning interrupt is disabled. 1 The Early Warning interrupt is enabled. SAM C20/C21 Family Data Sheet WDT – Watchdog Timer © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 307

23.8.6 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x06 Reset: 0x00 Property: N/A Bit 7 6 5 4 3 2 1 0 EW Access R/W Reset 0 Bit 0 – EW Early Warning This flag is cleared by writing a '1' to it. This flag is set when an Early Warning interrupt occurs, as defined by the EWOFFSET bit group in EWCTRL. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Early Warning interrupt flag. SAM C20/C21 Family Data Sheet WDT – Watchdog Timer © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 308

23.8.7 Synchronization Busy

Name: SYNCBUSY Offset: 0x08 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 WEN ENABLE Access R R Reset 0 0 Bit 2 – WEN Window Enable Synchronization Busy Value Description 0 Write synchronization of the CTRLA.WEN bit is complete. 1 Write synchronization of the CTRLA.WEN bit is ongoing. Bit 1 – ENABLE Enable Synchronization Busy Value Description 0 Write synchronization of the CTRLA.ENABLE bit is complete. 1 Write synchronization of the CTRLA.ENABLE bit is ongoing. SAM C20/C21 Family Data Sheet WDT – Watchdog Timer © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 309

23.8.8 Clear

Name: CLEAR Offset: 0x0C Reset: 0x00 Property: Write-Synchronized Bit 7 6 5 4 3 2 1 0 CLEAR[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – CLEAR[7:0] Watchdog Clear In Normal mode, writing 0xA5 to this register during the watchdog time-out period will clear the Watchdog Timer and the watchdog time-out period is restarted. In Window mode, any writing attempt to this register before the time-out period started (i.e., during TOWDTW) will issue an immediate system Reset. Writing 0xA5 during the time-out period TOWDT will clear the Watchdog Timer and the complete time-out sequence (first TOWDTW then TOWDT) is restarted. In both modes, writing any other value than 0xA5 will issue an immediate system Reset. SAM C20/C21 Family Data Sheet WDT – Watchdog Timer © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 310

RTC – Real-Time Counter

24.1 Overview

The Real-Time Counter (RTC) is a 32-bit counter with a 10-bit programmable prescaler that typically runs continuously to keep track of time. The RTC can wake up the device from sleep modes using the alarm/ compare wake up, periodic wake up, or overflow wake up mechanisms. The RTC can generate periodic peripheral events from outputs of the prescaler, as well as alarm/compare interrupts and peripheral events, which can trigger at any counter value. Additionally, the timer can trigger an overflow interrupt and peripheral event, and can be reset on the occurrence of an alarm/compare match. This allows periodic interrupts and peripheral events at very long and accurate intervals. The 10-bit programmable prescaler can scale down the clock source. By this, a wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the minimum counter tick interval is 30.5µs, and time-out periods can range up to 36 hours. For a counter tick interval of 1s, the maximum time-out period is more than 136 years.

24.2 Features

32-bit counter with 10-bit prescaler
Multiple clock sources
32-bit or 16-bit counter mode
One 32-bit or two 16-bit compare values
Clock/Calendar mode – Time in seconds, minutes, and hours (12/24) – Date in day of month, month, and year – Leap year correction
Digital prescaler correction/tuning for increased accuracy
Overflow, alarm/compare match and prescaler interrupts and events – Optional clear on alarm/compare match

24.3 Block Diagram

Figure 24-1. RTC Block Diagram (Mode 0 — 32-Bit Counter) OVF MATCHCLR CMPn OSC32KCTRL CLK_RTC_OSC PRESCALER CLK_RTC_CNT Periodic Events COUNT COMPn 0x00000000 SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 311

Figure 24-2. RTC Block Diagram (Mode 1 — 16-Bit Counter) CLK_RTC_OSC CLK_RTC_CNT OSC32KCTRL PRESCALER COMPn PER COUNT 0x0000 Periodic Events CMPn OVF Figure 24-3. RTC Block Diagram (Mode 2 — Clock/Calendar) CLK_RTC_CNTCLK_RTC_OSC OSC32KCTRL PRESCALER Periodic Events MASKn CLOCK ALARMn 0x00000000 OVF MATCHCLR ALARMn Related Links 24.6.2.3 32-Bit Counter (Mode 0) 24.6.2.4 16-Bit Counter (Mode 1)

24.6.2.5 Clock/Calendar (Mode 2)

24.4 Signal Description

Not applicable.

24.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

24.5.1 I/O Lines

For more information on I/O configurations, refer to the "RTC Pinout" section. Related Links: 6. I/O Multiplexing and Considerations

24.5.2 Power Management

The RTC will continue to operate in any sleep modes where the selected source clock is running. The RTC interrupts can be used to wake up the device from sleep modes. Events connected to the event system can trigger other operations in the system without exiting sleep modes. Refer to the Power Manager for details on the different sleep modes. The RTC will be reset only at power-on (POR) or by setting the Software Reset bit in the Control A register (CTRLA.SWRST=1). SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 312

PM – Power Manager

24.5.3 Clocks

The RTC bus clock (CLK_RTC_APB) can be enabled and disabled in the Main Clock module MCLK, and the default state of CLK_RTC_APB can be found in Peripheral Clock Masking section. A 32KHz or 1KHz oscillator clock (CLK_RTC_OSC) is required to clock the RTC. This clock must be configured and enabled in the 32KHz oscillator controller (OSC32KCTRL) before using the RTC. This oscillator clock is asynchronous to the bus clock (CLK_RTC_APB). Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains. Refer to 24.6.7 Synchronization for further details. Related Links 21. OSC32KCTRL – 32KHz Oscillators Controller

24.5.4 DMA

Not applicable. Related Links 25. DMAC – Direct Memory Access Controller

24.5.5 Interrupts

The interrupt request line is connected to the Interrupt Controller. Using the RTC interrupt requires the Interrupt Controller to be configured first. Related Links

24.5.6 Events

The events are connected to the Event System. Related Links 29. EVSYS – Event System

24.5.7 Debug Operation

When the CPU is halted in debug mode the RTC will halt normal operation. The RTC can be forced to continue operation during debugging. Refer to 24.8.6 DBGCTRL for details.

24.5.8 Register Access Protection

All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the following registers:

Interrupt Flag Status and Clear (INTFLAG) register Write-protection is denoted by the "PAC Write-Protection" property in the register description. Write-protection does not apply to accesses through an external debugger. Refer to the PAC - Peripheral Access Controller for details. Related Links 11. PAC - Peripheral Access Controller SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 313

24.5.9 Analog Connections

A 32.768kHz crystal can be connected to the XIN32 and XOUT32 pins, along with any required load capacitors. See Electrical Characteristics for details on recommended crystal characteristics and load capacitors.

24.6 Functional Description

24.6.1 Principle of Operation

The RTC keeps track of time in the system and enables periodic events, as well as interrupts and events at a specified time. The RTC consists of a 10-bit prescaler that feeds a 32-bit counter. The actual format of the 32-bit counter depends on the RTC operating mode. The RTC can function in one of these modes:

Mode 0 - COUNT32: RTC serves as 32-bit counter
Mode 1 - COUNT16: RTC serves as 16-bit counter
Mode 2 - CLOCK: RTC serves as clock/calendar with alarm functionality

24.6.2 Basic Operation

24.6.2.1 Initialization

The following bits are enable-protected, meaning that they can only be written when the RTC is disabled (CTRLA.ENABLE=0):

Operating Mode bits in the Control A register (CTRLA.MODE)
Prescaler bits in the Control A register (CTRLA.PRESCALER)
Clear on Match bit in the Control A register (CTRLA.MATCHCLR)
Clock Representation bit in the Control A register (CTRLA.CLKREP) The following registers are enable-protected:
Event Control register (EVCTRL) Enable-protected bits and registers can be changed only when the RTC is disabled (CTRLA.ENABLE=0). If the RTC is enabled (CTRLA.ENABLE=1), these operations are necessary: first write CTRLA.ENABLE=0 and check whether the write synchronization has finished, then change the desired bit field value. Enable-protected bits in CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1', but not at the same time as CTRLA.ENABLE is written to '0'. Enable-protection is denoted by the "Enable-Protected" property in the register description. The RTC prescaler divides the source clock for the RTC counter. Note: In Clock/Calendar mode, the prescaler must be configured to provide a 1Hz clock to the counter for correct operation. The frequency of the RTC clock (CLK_RTC_CNT) is given by the following formula: ?CLK_RTC_CNT = ?CLK_RTC_OSC ʹPRESCALER The frequency of the oscillator clock, CLK_RTC_OSC, is given by fCLK_RTC_OSC, and fCLK_RTC_CNT is the frequency of the internal prescaled RTC clock, CLK_RTC_CNT. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 314

24.6.2.2 Enabling, Disabling, and Resetting

The RTC is enabled by setting the Enable bit in the Control A register (CTRLA.ENABLE=1). The RTC is disabled by writing CTRLA.ENABLE=0. The RTC is reset by setting the Software Reset bit in the Control A register (CTRLA.SWRST=1). All registers in the RTC, except DEBUG, will be reset to their initial state, and the RTC will be disabled. The RTC must be disabled before resetting it. 24.6.2.3 32-Bit Counter (Mode 0) When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x0, the counter operates in 32-bit Counter mode. The block diagram of this mode is shown in Figure 24-1. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The counter will increment until it reaches the top value of 0xFFFFFFFF, and then wrap to 0x00000000. This sets the Overflow Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF). The RTC counter value can be read from or written to the Counter Value register (COUNT) in 32-bit format. The counter value is continuously compared with the 32-bit Compare register (COMP0). When a compare match occurs, the Compare 0 Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMP0) is set on the next 0-to-1 transition of CLK_RTC_CNT. If the Clear on Match bit in the Control A register (CTRLA.MATCHCLR) is '1', the counter is cleared on the next counter cycle when a compare match with COMP0 occurs. This allows the RTC to generate periodic interrupts or events with longer periods than the prescaler events. Note that when CTRLA.MATCHCLR is '1', INTFLAG.CMP0 and INTFLAG.OVF will both be set simultaneously on a compare match with COMP0. 24.6.2.4 16-Bit Counter (Mode 1) When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x1, the counter operates in 16-bit Counter mode as shown in Figure 24-2. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. In 16-bit Counter mode, the 16-bit Period register (PER) holds the maximum value of the counter. The counter will increment until it reaches the PER value, and then wrap to 0x0000. This sets the Overflow Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF). The RTC counter value can be read from or written to the Counter Value register (COUNT) in 16-bit format. The counter value is continuously compared with the 16-bit Compare registers (COMPn, n=0..1). When a compare match occurs, the Compare n Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn, n=0..1) is set on the next 0-to-1 transition of CLK_RTC_CNT. When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x2, the counter operates in Clock/Calendar mode, as shown in Figure 24-3. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The selected clock source and RTC prescaler must be configured to provide a 1Hz clock to the counter for correct operation in this mode. The time and date can be read from or written to the Clock Value register (CLOCK) in a 32-bit time/date format. Time is represented as:

Seconds
Minutes
Hours SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 315

Hours can be represented in either 12- or 24-hour format, selected by the Clock Representation bit in the Control A register (CTRLA.CLKREP). This bit can be changed only while the RTC is disabled. The date is represented in this form:

Day as the numeric day of the month (starting at 1)
Month as the numeric month of the year (1 = January, 2 = February, etc.)
Year as a value from 0x00 to 0x3F. This value must be added to a user-defined reference year. The reference year must be a leap year (2016, 2020 etc). Example: the year value 0x2D, added to a reference year 2016, represents the year 2061. The RTC will increment until it reaches the top value of 23:59:59 December 31 of year value 0x3F, and then wrap to 00:00:00 January 1 of year value 0x00. This will set the Overflow Interrupt flag in the Interrupt Flag Status and Clear registers (INTFLAG.OVF). The clock value is continuously compared with the 32-bit Alarm register (ALARM0). When an alarm match occurs, the Alarm 0 Interrupt flag in the Interrupt Flag Status and Clear registers (INTFLAG.ALARM0) is set on the next 0-to-1 transition of CLK_RTC_CNT. E.g. For a 1Hz clock counter, it means the Alarm 0 Interrupt flag is set with a delay of 1s after the occurrence of alarm match. A valid alarm match depends on the setting of the Alarm Mask Selection bits in the Alarm 0 Mask register (MASK0.SEL). These bits determine which time/date fields of the clock and alarm values are valid for comparison and which are ignored. If the Clear on Match bit in the Control A register (CTRLA.MATCHCLR) is set, the counter is cleared on the next counter cycle when an alarm match with ALARM0 occurs. This allows the RTC to generate periodic interrupts or events with longer periods than it would be possible with the prescaler events only (see 24.6.8.1 Periodic Intervals). Note: When CTRLA.MATCHCLR is 1, INTFLAG.ALARM0 and INTFLAG.OVF will both be set simultaneously on an alarm match with ALARM0.

24.6.3 DMA Operation

Not applicable.

24.6.4 Interrupts

The RTC has the following interrupt sources:

Overflow (OVF): Indicates that the counter has reached its top value and wrapped to zero.
Compare (CMPn): Indicates a match between the counter value and the compare register.
Alarm (ALARM): Indicates a match between the clock value and the alarm register.
Period n (PERn): The corresponding bit in the prescaler has toggled. Refer to

24.6.8.1 Periodic

Intervals for details. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by setting the corresponding bit in the Interrupt Enable Set register (INTENSET=1), and disabled by setting the corresponding bit in the Interrupt Enable Clear register (INTENCLR=1). An interrupt request is generated when the interrupt flag is raised and the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled or the RTC is reset. See the description of the INTFLAG registers for details on how to clear interrupt flags. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 316

All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. Refer to the Nested Vector Interrupt Controller for details. The user must read the INTFLAG register to determine which interrupt condition is present. Note: Interrupts must be globally enabled for interrupt requests to be generated. Refer to the Nested Vector Interrupt Controller for details. Related Links

24.6.5 Events

The RTC can generate the following output events:

Overflow (OVF): Generated when the counter has reached its top value and wrapped to zero.
Compare (CMPn): Indicates a match between the counter value and the compare register.
Alarm (ALARM): Indicates a match between the clock value and the alarm register.
Period n (PERn): The corresponding bit in the prescaler has toggled. Refer to

Intervals for details.

Periodic Daily (PERD): Generated when the COUNT/CLOCK has incremented at a fixed period of time. Setting the Event Output bit in the Event Control Register (EVCTRL.xxxEO=1) enables the corresponding output event. Writing a zero to this bit disables the corresponding output event. Refer to the EVSYS - Event System for details on configuring the event system. Related Links 29. EVSYS – Event System

24.6.6 Sleep Mode Operation

The RTC will continue to operate in any sleep mode where the source clock is active. The RTC interrupts can be used to wake up the device from a sleep mode. RTC events can trigger other operations in the system without exiting the sleep mode. An interrupt request will be generated after the wake-up if the Interrupt Controller is configured accordingly. Otherwise the CPU will wake up directly, without triggering any interrupt. In this case, the CPU will continue executing right from the first instruction that followed the entry into sleep.

24.6.7 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written:

Software Reset bit in Control A register, CTRLA.SWRST
Enable bit in Control A register, CTRLA.ENABLE The following registers are synchronized when written:
Counter Value register, COUNT
Clock Value register, CLOCK
Counter Period register, PER
Compare n Value registers, COMPn
Alarm n Value registers, ALARMn SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 317

Frequency Correction register, FREQCORR
Alarm n Mask register, MASKn The following registers are synchronized when read:
The Counter Value register, COUNT, if the Counter Read Sync Enable bit in CTRLA (CTRLA.COUNTSYNC) is '1'
The Clock Value register, CLOCK, if the Clock Read Sync Enable bit in CTRLA (CTRLA.CLOCKSYNC) is '1' Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Required read-synchronization is denoted by the "Read-Synchronized" property in the register description. Related Links

24.6.8 Additional Features

24.6.8.1 Periodic Intervals

The RTC prescaler can generate interrupts and events at periodic intervals, allowing flexible system tick creation. Any of the upper eight bits of the prescaler (bits 2 to 9) can be the source of an interrupt/event. When one of the eight Periodic Event Output bits in the Event Control register (EVCTRL.PEREO[n=0..7]) is '1', an event is generated on the 0-to-1 transition of the related bit in the prescaler, resulting in a periodic event frequency of: ?PERIODICሺnሻ = ?CLK_RTC_OSC ʹn+͵ fCLK_RTC_OSC is the frequency of the internal prescaler clock CLK_RTC_OSC, and n is the position of the EVCTRL.PEREOn bit. For example, PER0 will generate an event every eight CLK_RTC_OSC cycles, PER1 every 16 cycles, etc. This is shown in the figure below. Periodic events are independent of the prescaler setting used by the RTC counter, except if CTRLA.PRESCALER is zero. Then, no periodic events will be generated. Figure 24-4. Example Periodic Events CLK_RTC_OSC PER0 PER1 PER2 PER3

24.6.8.2 Frequency Correction

The RTC Frequency Correction module employs periodic counter corrections to compensate for a too- slow or too-fast oscillator. Frequency correction requires that CTRLA.PRESCALER is greater than 1. The digital correction circuit adds or subtracts cycles from the RTC prescaler to adjust the frequency in approximately 1ppm steps. Digital correction is achieved by adding or skipping a single count in the prescaler once every 4096 CLK_RTC_OSC cycles. The Value bit group in the Frequency Correction register (FREQCORR.VALUE) determines the number of times the adjustment is applied over 240 of these periods. The resulting correction is as follows: SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 318

Correction in ppm =FREQCORR.VALUE ͶͲͻ͸ ⋅ ʹͶͲ ⋅ ͳͲ͸ppm This results in a resolution of 1.017ppm. The Sign bit in the Frequency Correction register (FREQCORR.SIGN) determines the direction of the correction. A positive value will add counts and increase the period (reducing the frequency), and a negative value will reduce counts per period (speeding up the frequency). Digital correction also affects the generation of the periodic events from the prescaler. When the correction is applied at the end of the correction cycle period, the interval between the previous periodic event and the next occurrence may also be shortened or lengthened depending on the correction value. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 319

24.7 Register Summary - Mode 0 - 32-Bit Counter

Offset Name Bit Pos. 0x00 CTRLA 7:0 MATCHCLR MODE[1:0] ENABLE SWRST 15:8 COUNTSYNC PRESCALER[3:0] 0x02 ... 0x03 Reserved 0x04 EVCTRL 7:0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 15:8 OVFEO CMPEO0 23:16 31:24 0x08 INTENCLR 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF CMP0 0x0A INTENSET 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF CMP0 0x0C INTFLAG 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF CMP0 0x0E DBGCTRL 7:0 DBGRUN 0x0F Reserved 0x10 SYNCBUSY 7:0 COMP0 COUNT FREQCORR ENABLE SWRST 15:8 COUNTSYNC 23:16 31:24 0x14 FREQCORR 7:0 SIGN VALUE[6:0] 0x15 ... 0x17 Reserved 0x18 COUNT 7:0 COUNT[7:0] 15:8 COUNT[15:8] 23:16 COUNT[23:16] 31:24 COUNT[31:24] 0x1C ... 0x1F Reserved 0x20 COMP 7:0 COMP[7:0] 15:8 COMP[15:8] 23:16 COMP[23:16] 31:24 COMP[31:24]

24.8 Register Description - Mode 0 - 32-Bit Counter

This Register Description section is valid if the RTC is in COUNT32 mode (CTRLA.MODE=0). Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 320

Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-Synchronized" and/or "Write-Synchronized" property in each individual register description. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write- Protection" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 321

24.8.1 Control A in COUNT32 mode (CTRLA.MODE=0) Name: CTRLA Offset: 0x00 Reset: 0x0000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 COUNTSYNC PRESCALER[3:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MATCHCLR MODE[1:0] ENABLE SWRST Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 15 – COUNTSYNC COUNT Read Synchronization Enable The COUNT register requires synchronization when reading. Disabling the synchronization will prevent reading valid values from the COUNT register. This bit is not enable-protected. Value Description

0 COUNT read synchronization is disabled

1 COUNT read synchronization is enabled

Bits 11:8 – PRESCALER[3:0] Prescaler These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not synchronized. Value Name Description 0x0 OFF CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x2 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x3 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x4 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x5 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x6 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x7 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x8 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x9 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0xA DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xB DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xC-0xF - Reserved Bit 7 – MATCHCLR Clear on Match This bit defines if the counter is cleared or not on a match. This bit is not synchronized. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 322

0 The counter is not cleared on a Compare/Alarm 0 match

1 The counter is cleared on a Compare/Alarm 0 match

Bits 3:2 – MODE[1:0] Operating Mode This bit group defines the operating mode of the RTC. This bit is not synchronized. Value Name Description 0x0 COUNT32 Mode 0: 32-bit counter 0x1 COUNT16 Mode 1: 16-bit counter 0x2 CLOCK Mode 2: Clock/calendar 0x3 - Reserved Bit 1 – ENABLE Enable Due to synchronization there is a delay between writing CTRLA.ENABLE and until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. Value Description

0 The peripheral is disabled

1 The peripheral is enabled

Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the RTC (except DBGCTRL) to their initial state, and the RTC will be disabled. Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization there is a delay between writing CTRLA.SWRST and until the reset is complete. CTRLA.SWRST will be cleared when the reset is complete. Value Description

0 There is not reset operation ongoing

1 The reset operation is ongoing

24.8.2 Event Control in COUNT32 mode (CTRLA.MODE=0) Name: EVCTRL Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 OVFEO CMPEO0 Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVFEO Overflow Event Output Enable Value Description 0 Overflow event is disabled and will not be generated. 1 Overflow event is enabled and will be generated for every overflow. Bit 8 – CMPEO0 Compare 0 Event Output Enable Value Description 0 Compare 0 event is disabled and will not be generated. 1 Compare 0 event is enabled and will be generated for every compare match. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PEREOn Periodic Interval n Event Output Enable [n = 7..0] Value Description 0 Periodic Interval n event is disabled and will not be generated. 1 Periodic Interval n event is enabled and will be generated. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 324

24.8.3 Interrupt Enable Clear in COUNT32 mode (CTRLA.MODE=0) Name: INTENCLR Offset: 0x08 Reset: 0x0000 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 15 14 13 12 11 10 9 8 OVF CMP0 Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. Bit 8 – CMP0 Compare 0 Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Compare 0 Interrupt Enable bit, which disables the Compare 0 interrupt. Value Description 0 The Compare 0 interrupt is disabled. 1 The Compare 0 interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 7..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Periodic Interval n Interrupt Enable bit, which disables the Periodic Interval n interrupt. Value Description 0 Periodic Interval n interrupt is disabled. 1 Periodic Interval n interrupt is enabled. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 325

24.8.4 Interrupt Enable Set in COUNT32 mode (CTRLA.MODE=0) Name: INTENSET Offset: 0x0A Reset: 0x0000 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 15 14 13 12 11 10 9 8 OVF CMP0 Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. Bit 8 – CMP0 Compare 0 Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Compare 0 Interrupt Enable bit, which enables the Compare 0 interrupt. Value Description 0 The Compare 0 interrupt is disabled. 1 The Compare 0 interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 7..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Periodic Interval n Interrupt Enable bit, which enables the Periodic Interval n interrupt. Value Description 0 Periodic Interval n interrupt is disabled. 1 Periodic Interval n interrupt is enabled. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 326

24.8.5 Interrupt Flag Status and Clear in COUNT32 mode (CTRLA.MODE=0) Name: INTFLAG Offset: 0x0C Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 OVF CMP0 Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Overflow interrupt flag. Bit 8 – CMP0 Compare 0 This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request will be generated if INTENCLR/SET.COMP0 is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Compare 0 interrupt flag. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n [n = 7..0] This flag is cleared by writing a '1' to the flag. This flag is set on the 0-to-1 transition of prescaler bit [n+2], and an interrupt request will be generated if INTENCLR/SET.PERn is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Periodic Interval n interrupt flag. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 327

24.8.6 Debug Control

Name: DBGCTRL Offset: 0x0E Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Debug Run This bit is not reset by a software reset. This bit controls the functionality when the CPU is halted by an external debugger. Value Description 0 The RTC is halted when the CPU is halted by an external debugger. 1 The RTC continues normal operation when the CPU is halted by an external debugger. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 328

24.8.7 Synchronization Busy in COUNT32 mode (CTRLA.MODE=0) Name: SYNCBUSY Offset: 0x10 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 COUNTSYNC Access R Reset 0 Bit 7 6 5 4 3 2 1 0 COMP0 COUNT FREQCORR ENABLE SWRST Access R R R R R Reset 0 0 0 0 0 Bit 15 – COUNTSYNC Count Read Sync Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.COUNTSYNC bit is complete. 1 Write synchronization for CTRLA.COUNTSYNC bit is ongoing. Bit 5 – COMP0 Compare 0 Synchronization Busy Status Value Description 0 Write synchronization for COMP0 register is complete. 1 Write synchronization for COMP0 register is ongoing. Bit 3 – COUNT Count Value Synchronization Busy Status Value Description 0 Read/write synchronization for COUNT register is complete. 1 Read/write synchronization for COUNT register is ongoing. Bit 2 – FREQCORR Frequency Correction Synchronization Busy Status Value Description 0 Write synchronization for FREQCORR register is complete. 1 Write synchronization for FREQCORR register is ongoing. Bit 1 – ENABLE Enable Synchronization Busy Status SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 329

0 Write synchronization for CTRLA.ENABLE bit is complete. 1 Write synchronization for CTRLA.ENABLE bit is ongoing. Bit 0 – SWRST Software Reset Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.SWRST bit is complete. 1 Write synchronization for CTRLA.SWRST bit is ongoing. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 330

24.8.8 Frequency Correction

Name: FREQCORR Offset: 0x14 Reset: 0x00 Property: PAC Write-Protection, Write-Synchronized Bit 7 6 5 4 3 2 1 0 SIGN VALUE[6:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 – SIGN Correction Sign Value Description 0 The correction value is positive, i.e., frequency will be decreased. 1 The correction value is negative, i.e., frequency will be increased. Bits 6:0 – VALUE[6:0] Correction Value These bits define the amount of correction applied to the RTC prescaler. Value Description 0 Correction is disabled and the RTC frequency is unchanged. 1 - 127 The RTC frequency is adjusted according to the value. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 331

24.8.9 Counter Value in COUNT32 mode (CTRLA.MODE=0) Name: COUNT Offset: 0x18 Reset: 0x00000000 Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized Bit 31 30 29 28 27 26 25 24 COUNT[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 COUNT[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COUNT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – COUNT[31:0] Counter Value These bits define the value of the 32-bit RTC counter in mode 0. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 332

24.8.10 Compare 0 Value in COUNT32 mode (CTRLA.MODE=0) Name: COMP Offset: 0x20 Reset: 0x00000000 Property: PAC Write-Protection, Write-Synchronized Bit 31 30 29 28 27 26 25 24 COMP[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 COMP[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COMP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COMP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – COMP[31:0] Compare Value The 32-bit value of COMP0 is continuously compared with the 32-bit COUNT value. When a match occurs, the Compare 0 interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMP0) is set on the next counter cycle, and the counter value is cleared if CTRLA.MATCHCLR is '1'. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 333

24.9 Register Summary - Mode 1 - 16-Bit Counter

Offset Name Bit Pos. 0x00 CTRLA 7:0 MODE[1:0] ENABLE SWRST 15:8 COUNTSYNC PRESCALER[3:0] 0x02 ... 0x03 Reserved 0x04 EVCTRL 7:0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 15:8 OVFEO CMPEO1 CMPEO0 23:16 31:24 0x08 INTENCLR 7:0 PER7 PER6 PER5 PER4 PER3 PER2 CMP1 CMP0 15:8 OVF 0x0A INTENSET 7:0 PER7 PER6 PER5 PER4 PER3 PER2 CMP1 CMP0 15:8 OVF 0x0C INTFLAG 7:0 PER7 PER6 PER5 PER4 PER3 PER2 CMP1 CMP0 15:8 OVF 0x0E DBGCTRL 7:0 DBGRUN 0x0F Reserved 0x10 SYNCBUSY 7:0 COMP1 COMP0 PER COUNT FREQCORR ENABLE SWRST 15:8 COUNTSYNC 23:16 31:24 0x14 FREQCORR 7:0 SIGN VALUE[6:0] 0x15 ... 0x17 Reserved 0x18 COUNT 7:0 COUNT[7:0] 15:8 COUNT[15:8] 0x1A ... 0x1B Reserved 0x1C PER 7:0 PER[7:0] 15:8 PER[15:8] 0x1E ... 0x1F Reserved 0x20 COMP0 7:0 COMP[7:0] 15:8 COMP[15:8] 0x22 COMP1 7:0 COMP[7:0] 15:8 COMP[15:8]

24.10 Register Description - Mode 1 - 16-Bit Counter

This Register Description section is valid if the RTC is in COUNT16 mode (CTRLA.MODE=1). SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 334

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-Synchronized" and/or "Write-Synchronized" property in each individual register description. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write- Protection" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 335

24.10.1 Control A in COUNT16 mode (CTRLA.MODE=1) Name: CTRLA Offset: 0x00 Reset: 0x0000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 COUNTSYNC PRESCALER[3:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MODE[1:0] ENABLE SWRST Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 – COUNTSYNC COUNT Read Synchronization Enable The COUNT register requires synchronization when reading. Disabling the synchronization will prevent reading valid values from the COUNT register. This bit is not enable-protected. Value Description Bits 11:8 – PRESCALER[3:0] Prescaler These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not synchronized. Value Name Description 0x0 OFF CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x2 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x3 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x4 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x5 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x6 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x7 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x8 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x9 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0xA DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xB DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xC-0xF - Reserved Bits 3:2 – MODE[1:0] Operating Mode This field defines the operating mode of the RTC. This bit is not synchronized. Value Name Description 0x0 COUNT32 Mode 0: 32-bit counter SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 336

0x1 COUNT16 Mode 1: 16-bit counter 0x2 CLOCK Mode 2: Clock/calendar 0x3 - Reserved Bit 1 – ENABLE Enable Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/ disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. Value Description Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the RTC (except DBGCTRL) to their initial state, and the RTC will be disabled. Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST will be cleared when the reset is complete. Value Description SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 337

24.10.2 Event Control in COUNT16 mode (CTRLA.MODE=1) Name: EVCTRL Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 OVFEO CMPEO1 CMPEO0 Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVFEO Overflow Event Output Enable Value Description 0 Overflow event is disabled and will not be generated. 1 Overflow event is enabled and will be generated for every overflow. Bits 8, 9 – CMPEOn Compare n Event Output Enable [n = 1..0] Value Description 0 Compare n event is disabled and will not be generated. 1 Compare n event is enabled and will be generated for every compare match. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PEREOn Periodic Interval n Event Output Enable [n = 7..0] Value Description 0 Periodic Interval n event is disabled and will not be generated. 1 Periodic Interval n event is enabled and will be generated. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 338

24.10.3 Interrupt Enable Clear in COUNT16 mode (CTRLA.MODE=1) Name: INTENCLR Offset: 0x08 Reset: 0x0000 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 15 14 13 12 11 10 9 8 OVF Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 CMP1 CMP0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. Bits 0, 1 – CMPn Compare n Interrupt Enable [n = 1..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Compare n Interrupt Enable bit, which disables the Compare n interrupt. Value Description 0 The Compare n interrupt is disabled. 1 The Compare n interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 7..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Periodic Interval n Interrupt Enable bit, which disables the Periodic Interval n interrupt. Value Description 0 Periodic Interval n interrupt is disabled. 1 Periodic Interval n interrupt is enabled. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 339

24.10.4 Interrupt Enable Set in COUNT16 mode (CTRLA.MODE=1) Name: INTENSET Offset: 0x0A Reset: 0x0000 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 15 14 13 12 11 10 9 8 OVF Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 CMP1 CMP0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. Bits 0, 1 – CMPn Compare n Interrupt Enable [n = 1..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Compare n Interrupt Enable bit, which and enables the Compare n interrupt. Value Description 0 The Compare n interrupt is disabled. 1 The Compare n interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 7..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Periodic Interval n Interrupt Enable bit, which enables the Periodic Interval n interrupt. Value Description 0 Periodic Interval n interrupt is disabled. 1 Periodic Interval n interrupt is enabled. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 340

24.10.5 Interrupt Flag Status and Clear in COUNT16 mode (CTRLA.MODE=1) Name: INTFLAG Offset: 0x0C Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 OVF Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 CMP1 CMP0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Overflow interrupt flag. Bits 0, 1 – CMPn Compare n [n = 1..0] This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request will be generated if INTENCLR/SET.COMPn is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Compare n interrupt flag. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n [n = 7..0] This flag is cleared by writing a '1' to the flag. This flag is set on the 0-to-1 transition of prescaler bit [n+2], and an interrupt request will be generated if INTENCLR/SET.PERx is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Periodic Interval n interrupt flag. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 341

24.10.6 Debug Control

24.10.7 Synchronization Busy in COUNT16 mode (CTRLA.MODE=1) Name: SYNCBUSY Offset: 0x10 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 COUNTSYNC Access R Reset 0 Bit 7 6 5 4 3 2 1 0 COMP1 COMP0 PER COUNT FREQCORR ENABLE SWRST Access R/W R/W R R R R R Reset 0 0 0 0 0 0 0 Bit 15 – COUNTSYNC Count Read Sync Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.COUNTSYNC bit is complete. 1 Write synchronization for CTRLA.COUNTSYNC bit is ongoing. Bits 5, 6 – COMPn Compare n Synchronization Busy Status [n = 1..0] Value Description 0 Write synchronization for COMPn register is complete. 1 Write synchronization for COMPn register is ongoing. Bit 4 – PER Period Synchronization Busy Status Value Description 0 Write synchronization for PER register is complete. 1 Write synchronization for PER register is ongoing. Bit 3 – COUNT Count Value Synchronization Busy Status Value Description 0 Read/write synchronization for COUNT register is complete. 1 Read/write synchronization for COUNT register is ongoing. Bit 2 – FREQCORR Frequency Correction Synchronization Busy Status SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 343

0 Write synchronization for FREQCORR register is complete. 1 Write synchronization for FREQCORR register is ongoing. Bit 1 – ENABLE Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.ENABLE bit is complete. 1 Write synchronization for CTRLA.ENABLE bit is ongoing. Bit 0 – SWRST Software Reset Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.SWRST bit is complete. 1 Write synchronization for CTRLA.SWRST bit is ongoing. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 344

24.10.8 Frequency Correction

24.10.9 Counter Value in COUNT16 mode (CTRLA.MODE=1) Name: COUNT Offset: 0x18 Reset: 0x0000 Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized Bit 15 14 13 12 11 10 9 8 COUNT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – COUNT[15:0] Counter Value These bits define the value of the 16-bit RTC counter in COUNT16 mode (CTRLA.MODE=1). SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 346

24.10.10 Counter Period in COUNT16 mode (CTRLA.MODE=1) Name: PER Offset: 0x1C Reset: 0x0000 Property: PAC Write-Protection, Write-Synchronized Bit 15 14 13 12 11 10 9 8 PER[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PER[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – PER[15:0] Counter Period These bits define the value of the 16-bit RTC period in COUNT16 mode (CTRLA.MODE=1). SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 347

24.10.11 Compare n Value in COUNT16 mode (CTRLA.MODE=1) Name: COMP Offset: 0x20 + n*0x02 [n=0..1] Reset: 0x0000 Property: PAC Write-Protection, Write-Synchronized Bit 15 14 13 12 11 10 9 8 COMP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COMP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – COMP[15:0] Compare Value The 16-bit value of COMPn is continuously compared with the 16-bit COUNT value. When a match occurs, the Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next counter cycle. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 348

24.11 Register Summary - Mode 2 - Clock/Calendar

Offset Name Bit Pos. 0x00 CTRLA 7:0 MATCHCLR CLKREP MODE[1:0] ENABLE SWRST 15:8 CLOCKSYNC PRESCALER[3:0] 0x02 ... 0x03 Reserved 0x04 EVCTRL 7:0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 15:8 OVFEO ALARMEO 23:16 31:24 0x08 INTENCLR 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF ALARM0 0x0A INTENSET 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF ALARM0 0x0C INTFLAG 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF ALARM0 0x0E DBGCTRL 7:0 DBGRUN 0x0F Reserved 0x10 SYNCBUSY 7:0 ALARM0 CLOCK FREQCORR ENABLE SWRST 15:8 CLOCKSYNC MASK0 23:16 31:24 0x14 FREQCORR 7:0 SIGN VALUE[6:0] 0x15 ... 0x17 Reserved 0x18 CLOCK 7:0 MINUTE[1:0] SECOND[5:0] 15:8 HOUR[3:0] MINUTE[5:2] 23:16 MONTH[1:0] DAY[4:0] HOUR[4:4] 31:24 YEAR[5:0] MONTH[3:2] 0x1C ... 0x1F Reserved 0x20 ALARM 7:0 MINUTE[1:0] SECOND[5:0] 15:8 HOUR[3:0] MINUTE[5:2] 23:16 MONTH[1:0] DAY[4:0] HOUR[4:4] 31:24 YEAR[5:0] MONTH[3:2] 0x24 MASK 7:0 SEL[2:0]

24.12 Register Description - Mode 2 - Clock/Calendar

This Register Description section is valid if the RTC is in Clock/Calendar mode (CTRLA.MODE=2). SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 349

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-Synchronized" and/or "Write-Synchronized" property in each individual register description. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write- Protection" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 350

24.12.1 Control A in Clock/Calendar mode (CTRLA.MODE=2) Name: CTRLA Offset: 0x00 Reset: 0x0000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 CLOCKSYNC PRESCALER[3:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MATCHCLR CLKREP MODE[1:0] ENABLE SWRST Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 15 – CLOCKSYNC CLOCK Read Synchronization Enable The CLOCK register requires synchronization when reading. Disabling the synchronization will prevent reading valid values from the CLOCK register. This bit is not enable-protected. Value Description

0 CLOCK read synchronization is disabled

1 CLOCK read synchronization is enabled

Bits 11:8 – PRESCALER[3:0] Prescaler These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not synchronized. Value Name Description 0x0 OFF CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x2 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x3 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x4 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x5 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x6 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x7 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x8 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x9 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0xA DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xB DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xC-0xF - Reserved Bit 7 – MATCHCLR Clear on Match This bit is valid only in Mode 0 (COUNT32) and Mode 2 (CLOCK). This bit can be written only when the peripheral is disabled. This bit is not synchronized. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 351

Bit 6 – CLKREP Clock Representation This bit is valid only in Mode 2 and determines how the hours are represented in the Clock Value (CLOCK) register. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Value Description 0 24 Hour 1 12 Hour (AM/PM) Bits 3:2 – MODE[1:0] Operating Mode This field defines the operating mode of the RTC. This bit is not synchronized. Value Name Description 0x0 COUNT32 Mode 0: 32-bit counter 0x1 COUNT16 Mode 1: 16-bit counter 0x2 CLOCK Mode 2: Clock/calendar 0x3 - Reserved Bit 1 – ENABLE Enable Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/ disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. Value Description Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be disabled. Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST will be cleared when the reset is complete. Value Description SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 352

24.12.2 Event Control in Clock/Calendar mode (CTRLA.MODE=2) Name: EVCTRL Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 OVFEO ALARMEO Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVFEO Overflow Event Output Enable Value Description 0 Overflow event is disabled and will not be generated. 1 Overflow event is enabled and will be generated for every overflow. Bit 8 – ALARMEO Alarm 0 Event Output Enable Value Description 0 Alarm 0 event is disabled and will not be generated. 1 Alarm 0 event is enabled and will be generated for every compare match. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PEREOn Periodic Interval n Event Output Enable [n = 7..0] Value Description 0 Periodic Interval n event is disabled and will not be generated. 1 Periodic Interval n event is enabled and will be generated. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 353

24.12.3 Interrupt Enable Clear in Clock/Calendar mode (CTRLA.MODE=2) Name: INTENCLR Offset: 0x08 Reset: 0x0000 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 15 14 13 12 11 10 9 8 OVF ALARM0 Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. Bit 8 – ALARM0 Alarm 0 Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Alarm 0 Interrupt Enable bit, which disables the Alarm interrupt. Value Description 0 The Alarm 0 interrupt is disabled. 1 The Alarm 0 interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 7..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Periodic Interval n Interrupt Enable bit, which disables the Periodic Interval n interrupt. Value Description 0 Periodic Interval n interrupt is disabled. 1 Periodic Interval n interrupt is enabled. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 354

24.12.4 Interrupt Enable Set in Clock/Calendar mode (CTRLA.MODE=2) Name: INTENSET Offset: 0x0A Reset: 0x0000 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 15 14 13 12 11 10 9 8 OVF ALARM0 Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. Bit 8 – ALARM0 Alarm 0 Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Alarm 0 Interrupt Enable bit, which enables the Alarm 0 interrupt. Value Description 0 The Alarm 0 interrupt is disabled. 1 The Alarm 0 interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 7..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Periodic Interval n Interrupt Enable bit, which enables the Periodic Interval n interrupt. Value Description 0 Periodic Interval n interrupt is disabled. 1 Periodic Interval n interrupt is enabled. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 355

24.12.5 Interrupt Flag Status and Clear in Clock/Calendar mode (CTRLA.MODE=2) Name: INTFLAG Offset: 0x0C Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 OVF ALARM0 Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Overflow interrupt flag. Bit 8 – ALARM0 Alarm 0 This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request will be generated if INTENCLR/SET.ALARM0 is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Alarm 0 interrupt flag. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n [n = 7..0] This flag is cleared by writing a '1' to the flag. This flag is set on the 0-to-1 transition of prescaler bit [n+2], and an interrupt request will be generated if INTENCLR/SET.PERx is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Periodic Interval n interrupt flag. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 356

24.12.6 Debug Control

24.12.7 Synchronization Busy in Clock/Calendar mode (CTRLA.MODE=2) Name: SYNCBUSY Offset: 0x10 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 CLOCKSYNC MASK0 Access R R Reset 0 0 Bit 7 6 5 4 3 2 1 0 ALARM0 CLOCK FREQCORR ENABLE SWRST Access R R R R R Reset 0 0 0 0 0 Bit 15 – CLOCKSYNC Clock Read Sync Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.CLOCKSYNC bit is complete. 1 Write synchronization for CTRLA.CLOCKSYNC bit is ongoing. Bit 11 – MASK0 Mask 0 Synchronization Busy Status Value Description 0 Write synchronization for MASK0 register is complete. 1 Write synchronization for MASK0 register is ongoing. Bit 5 – ALARM0 Alarm 0 Synchronization Busy Status Value Description 0 Write synchronization for ALARM0 register is complete. 1 Write synchronization for ALARM0 register is ongoing. Bit 3 – CLOCK Clock Register Synchronization Busy Status Value Description 0 Read/write synchronization for CLOCK register is complete. 1 Read/write synchronization for CLOCK register is ongoing. Bit 2 – FREQCORR Frequency Correction Synchronization Busy Status SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 358

24.12.8 Frequency Correction

24.12.9 Clock Value in Clock/Calendar mode (CTRLA.MODE=2) Name: CLOCK Offset: 0x18 Reset: 0x00000000 Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized Bit 31 30 29 28 27 26 25 24 YEAR[5:0] MONTH[3:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 MONTH[1:0] DAY[4:0] HOUR[4:4] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 HOUR[3:0] MINUTE[5:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MINUTE[1:0] SECOND[5:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:26 – YEAR[5:0] Year The year offset with respect to the reference year (defined in software). The year is considered a leap year if YEAR[1:0] is zero. Bits 25:22 – MONTH[3:0] Month 1 – January 2 – February ... 12 – December Bits 21:17 – DAY[4:0] Day Day starts at 1 and ends at 28, 29, 30, or 31, depending on the month and year. Bits 16:12 – HOUR[4:0] Hour When CTRLA.CLKREP=0, the Hour bit group is in 24-hour format, with values 0-23. When CTRLA.CLKREP=1, HOUR[3:0] has values 1-12, and HOUR[4] represents AM (0) or PM (1). Bits 11:6 – MINUTE[5:0] Minute 0 – 59 Bits 5:0 – SECOND[5:0] Second 0 – 59 SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 361

24.12.10 Alarm Value in Clock/Calendar mode (CTRLA.MODE=2) Name: ALARM Offset: 0x20 Reset: 0x00000000 Property: PAC Write-Protection, Write-Synchronized The 32-bit value of ALARM is continuously compared with the 32-bit CLOCK value, based on the masking set by MASK.SEL. When a match occurs, the Alarm n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.ALARM) is set on the next counter cycle, and the counter is cleared if CTRLA.MATCHCLR is '1'. Bit 31 30 29 28 27 26 25 24 YEAR[5:0] MONTH[3:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 MONTH[1:0] DAY[4:0] HOUR[4:4] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 HOUR[3:0] MINUTE[5:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MINUTE[1:0] SECOND[5:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:26 – YEAR[5:0] Year The alarm year. Years are only matched if MASK.SEL is 6 Bits 25:22 – MONTH[3:0] Month The alarm month. Months are matched only if MASK.SEL is greater than 4. Bits 21:17 – DAY[4:0] Day The alarm day. Days are matched only if MASK.SEL is greater than 3. Bits 16:12 – HOUR[4:0] Hour The alarm hour. Hours are matched only if MASK.SEL is greater than 2. Bits 11:6 – MINUTE[5:0] Minute The alarm minute. Minutes are matched only if MASK.SEL is greater than 1. Bits 5:0 – SECOND[5:0] Second The alarm second. Seconds are matched only if MASK.SEL is greater than 0. SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 362

24.12.11 Alarm Mask in Clock/Calendar mode (CTRLA.MODE=2) Name: MASK Offset: 0x24 Reset: 0x00 Property: PAC Write-Protection, Write-Synchronized Bit 7 6 5 4 3 2 1 0 SEL[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 2:0 – SEL[2:0] Alarm Mask Selection These bits define which bit groups of ALARM are valid. Value Name Description 0x0 OFF Alarm Disabled 0x1 SS Match seconds only 0x2 MMSS Match seconds and minutes only 0x3 HHMMSS Match seconds, minutes, and hours only 0x4 DDHHMMSS Match seconds, minutes, hours, and days only 0x5 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x6 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x7 - Reserved SAM C20/C21 Family Data Sheet RTC – Real-Time Counter © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 363

DMAC – Direct Memory Access Controller

25.1 Overview

The Direct Memory Access Controller (DMAC) contains both a Direct Memory Access engine and a Cyclic Redundancy Check (CRC) engine. The DMAC can transfer data between memories and peripherals, and thus off-load these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time. With access to all peripherals, the DMAC can handle automatic transfer of data between communication modules. The DMA part of the DMAC has several DMA channels which all can receive different types of transfer triggers to generate transfer requests from the DMA channels to the arbiter, see also the Block Diagram. The arbiter will grant one DMA channel at a time to act as the active channel. When an active channel has been granted, the fetch engine of the DMAC will fetch a transfer descriptor from the SRAM and store it in the internal memory of the active channel, which will execute the data transmission. An ongoing data transfer of an active channel can be interrupted by a higher prioritized DMA channel. The DMAC will write back the updated transfer descriptor from the internal memory of the active channel to SRAM, and grant the higher prioritized channel to start transfer as the new active channel. Once a DMA channel is done with its transfer, interrupts and events can be generated optionally. The DMAC has four bus interfaces:

The data transfer bus is used for performing the actual DMA transfer.
The AHB/APB Bridge bus is used when writing and reading the I/O registers of the DMAC.
The descriptor fetch bus is used by the fetch engine to fetch transfer descriptors before data transfer can be started or continued.
The write-back bus is used to write the transfer descriptor back to SRAM. All buses are AHB master interfaces but the AHB/APB Bridge bus, which is an APB slave interface. The CRC engine can be used by software to detect an accidental error in the transferred data and to take corrective action, such as requesting the data to be sent again or simply not using the incorrect data.

25.2 Features

Data transfer from: – Peripheral to peripheral – Peripheral to memory – Memory to peripheral – Memory to memory
Transfer trigger sources – Software – Events from Event System – Dedicated requests from peripherals
SRAM based transfer descriptors – Single transfer using one descriptor – Multi-buffer or circular buffer modes by linking multiple descriptors SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 364

Up to 12 channels – Enable 12 independent transfers – Automatic descriptor fetch for each channel – Suspend/resume operation support for each channel
Flexible arbitration scheme – 4 configurable priority levels for each channel – Fixed or round-robin priority scheme within each priority level
From 1 to 256KB data transfer in a single block transfer
Multiple addressing modes – Static – Configurable increment scheme
Optional interrupt generation – On block transfer complete – On error detection – On channel suspend
4 event inputs – One event input for each of the 4 least significant DMA channels – Can be selected to trigger normal transfers, periodic transfers or conditional transfers – Can be selected to suspend or resume channel operation
4 event outputs – One output event for each of the 4 least significant DMA channels – Selectable generation on AHB, block, or transaction transfer complete
Error management supported by write-back function – Dedicated Write-Back memory section for each channel to store ongoing descriptor transfer
CRC polynomial software selectable to – CRC-16 (CRC-CCITT) – CRC-32 (IEEE 802.3) SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 365

25.3 Block Diagram

Figure 25-1. DMAC Block Diagram HIGH SPEED BUS MATRIX AHB/APB Bridge CPU SRAM S S M M Events Channel 0 Channel 1 Channel n Arbiter DMA Channels MASTER Active Channel CRC Engine n Fetch Engine Interrupt / Events DMAC Interrupts Transfer Triggers n Data Transfer Write-back Descriptor Fetch

25.4 Signal Description

Not applicable.

25.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

25.5.1 I/O Lines

Not applicable.

25.5.2 Power Management

The DMAC will continue to operate in any sleep mode where the selected source clock is running. The DMAC’s interrupts can be used to wake up the device from sleep modes. Events connected to the event system can trigger other operations in the system without exiting sleep modes. On hardware or software reset, all registers are set to their reset value. Related Links 19. PM – Power Manager

25.5.3 Clocks

The DMAC bus clock (CLK_DMAC_APB) must be configured and enabled in the Main Clock module before using the DMAC. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 366

This bus clock (CLK_DMAC_APB) is always synchronous to the module clock (CLK_DMAC_AHB), but can be divided by a prescaler and may run even when the module clock is turned off. Related Links

25.5.4 DMA

Not applicable.

25.5.5 Interrupts

The interrupt request line is connected to the interrupt controller. Using the DMAC interrupt requires the interrupt controller to be configured first. Related Links

25.5.6 Events

The events are connected to the event system. Related Links 29. EVSYS – Event System

25.5.7 Debug Operation

When the CPU is halted in debug mode the DMAC will halt normal operation. The DMAC can be forced to continue operation during debugging. Refer to 25.8.6 DBGCTRL for details.

25.5.8 Register Access Protection

All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Interrupt Pending register (INTPEND)
Channel ID register (CHID)
Channel Interrupt Flag Status and Clear register (CHINTFLAG) Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write- Protection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger. Related Links 11. PAC - Peripheral Access Controller

25.5.9 Analog Connections

Not applicable.

25.6 Functional Description

25.6.1 Principle of Operation

25.6.1.1 DMA

The DMAC can transfer data between memories and peripherals without interaction from the CPU. The data transferred by the DMAC are called transactions, and these transactions can be split into smaller data transfers. The following figure shows the relationship between the different transfer sizes: Figure 25-2. DMA Transfer Sizes DMA transaction Block transfer Link Enabled Burst transfer Link EnabledLink Enabled Beat transfer

Beat transfer: The size of one data transfer bus access, and the size is selected by writing the Beat Size bit group in the Block Transfer Control register (BTCTRL.BEATSIZE)
Block transfer: The amount of data one transfer descriptor can transfer, and the amount can range from 1 to 64k beats. A block transfer can be interrupted.
Transaction: The DMAC can link several transfer descriptors by having the first descriptor pointing to the second and so forth, as shown in the figure above. A DMA transaction is the complete transfer of all blocks within a linked list. A transfer descriptor describes how a block transfer should be carried out by the DMAC, and it must remain in SRAM. For further details on the transfer descriptor refer to 25.6.2.3 Transfer Descriptors. The figure above shows several block transfers linked together, which are called linked descriptors. For further information about linked descriptors, refer to 25.6.3.1 Linked Descriptors. A DMA transfer is initiated by an incoming transfer trigger on one of the DMA channels. This trigger can be configured to be either a software trigger, an event trigger, or one of the dedicated peripheral triggers. The transfer trigger will result in a DMA transfer request from the specific channel to the arbiter. If there are several DMA channels with pending transfer requests, the arbiter chooses which channel is granted access to become the active channel. The DMA channel granted access as the active channel will carry out the transaction as configured in the transfer descriptor. A current transaction can be interrupted by a higher prioritized channel, but will resume the block transfer when the according DMA channel is granted access as the active channel again. For each beat transfer, an optional output event can be generated. For each block transfer, optional interrupts and an optional output event can be generated. When a transaction is completed, dependent of the configuration, the DMA channel will either be suspended or disabled.

25.6.1.2 CRC

The internal CRC engine supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3). It can be used on a selectable DMA channel, or on the I/O interface. Refer to 25.6.3.7 CRC Operation for details.

25.6.2 Basic Operation

25.6.2.1 Initialization

The following DMAC registers are enable-protected, meaning that they can only be written when the DMAC is disabled (CTRL.DMAENABLE=0): SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 368

Descriptor Base Memory Address register (BASEADDR)
Write-Back Memory Base Address register (WRBADDR) The following DMAC bit is enable-protected, meaning that it can only be written when both the DMAC and CRC are disabled (CTRL.DMAENABLE=0 and CTRL.CRCENABLE=0):
Software Reset bit in Control register (CTRL.SWRST) The following DMA channel register is enable-protected, meaning that it can only be written when the corresponding DMA channel is disabled (CHCTRLA.ENABLE=0):
Channel Control B (CHCTRLB) register, except the Command bit (CHCTRLB.CMD) and the Channel Arbitration Level bit (CHCTRLB.LVL) The following DMA channel bit is enable-protected, meaning that it can only be written when the corresponding DMA channel is disabled:
Channel Software Reset bit in Channel Control A register (CHCTRLA.SWRST) The following CRC registers are enable-protected, meaning that they can only be written when the CRC is disabled (CTRL.CRCENABLE=0):
CRC Control register (CRCCTRL)
CRC Checksum register (CRCCHKSUM) Enable-protection is denoted by the "Enable-Protected" property in the register description. Before the DMAC is enabled it must be configured, as outlined by the following steps:
The SRAM address of where the descriptor memory section is located must be written to the Description Base Address (BASEADDR) register
The SRAM address of where the write-back section should be located must be written to the Write- Back Memory Base Address (WRBADDR) register
Priority level x of the arbiter can be enabled by setting the Priority Level x Enable bit in the Control register (CTRL.LVLENx=1) Before a DMA channel is enabled, the DMA channel and the corresponding first transfer descriptor must be configured, as outlined by the following steps:
DMA channel configurations – The channel number of the DMA channel to configure must be written to the Channel ID (CHID) register – Trigger action must be selected by writing the Trigger Action bit group in the Channel Control B register (CHCTRLB.TRIGACT) – Trigger source must be selected by writing the Trigger Source bit group in the Channel Control B register (CHCTRLB.TRIGSRC)
Transfer Descriptor – The size of each access of the data transfer bus must be selected by writing the Beat Size bit group in the Block Transfer Control register (BTCTRL.BEATSIZE) – The transfer descriptor must be made valid by writing a one to the Valid bit in the Block Transfer Control register (BTCTRL.VALID) – Number of beats in the block transfer must be selected by writing the Block Transfer Count (BTCNT) register – Source address for the block transfer must be selected by writing the Block Transfer Source Address (SRCADDR) register SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 369

– Destination address for the block transfer must be selected by writing the Block Transfer Destination Address (DSTADDR) register If CRC calculation is needed, the CRC engine must be configured before it is enabled, as outlined by the following steps:

The CRC input source must selected by writing the CRC Input Source bit group in the CRC Control register (CRCCTRL.CRCSRC)
The type of CRC calculation must be selected by writing the CRC Polynomial Type bit group in the CRC Control register (CRCCTRL.CRCPOLY)
If I/O is selected as input source, the beat size must be selected by writing the CRC Beat Size bit group in the CRC Control register (CRCCTRL.CRCBEATSIZE) Related Links

25.8.15 BASEADDR

25.8.18 CHCTRLA

25.8.19 CHCTRLB

25.8.4 CRCCHKSUM

25.8.2 CRCCTRL

25.8.1 CTRL

25.8.16 WRBADDR

25.10.1 BTCTRL

25.10.2 BTCNT

25.10.4 DSTADDR

25.10.3 SRCADDR

25.6.2.2 Enabling, Disabling, and Resetting

The DMAC is enabled by writing the DMA Enable bit in the Control register (CTRL.DMAENABLE) to '1'. The DMAC is disabled by writing a '0' to CTRL.DMAENABLE. A DMA channel is enabled by writing the Enable bit in the Channel Control A register (CHCTRLA.ENABLE) to '1', after writing the corresponding channel id to the Channel ID bit group in the Channel ID register (CHID.ID). A DMA channel is disabled by writing a '0' to CHCTRLA.ENABLE. The CRC is enabled by writing a '1' to the CRC Enable bit in the Control register (CTRL.CRCENABLE). The CRC is disabled by writing a '0' to CTRL.CRCENABLE. The DMAC is reset by writing a '1' to the Software Reset bit in the Control register (CTRL.SWRST) while the DMAC and CRC are disabled. All registers in the DMAC except DBGCTRL will be reset to their initial state. A DMA channel is reset by writing a '1' to the Software Reset bit in the Channel Control A register (CHCTRLA.SWRST), after writing the corresponding channel id to the Channel ID bit group in the Channel ID register (CHID.ID). The channel registers will be reset to their initial state. The corresponding DMA channel must be disabled in order for the reset to take effect.

25.6.2.3 Transfer Descriptors

Together with the channel configurations the transfer descriptors decides how a block transfer should be executed. Before a DMA channel is enabled (CHCTRLA.ENABLE is written to one), and receives a transfer trigger, its first transfer descriptor has to be initialized and valid (BTCTRL.VALID). The first transfer descriptor describes the first block transfer of a transaction. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 370

All transfer descriptors must reside in SRAM. The addresses stored in the Descriptor Memory Section Base Address (BASEADDR) and Write-Back Memory Section Base Address (WRBADDR) registers tell the DMAC where to find the descriptor memory section and the write-back memory section. The descriptor memory section is where the DMAC expects to find the first transfer descriptors for all DMA channels. As BASEADDR points only to the first transfer descriptor of channel 0 (see figure below), all first transfer descriptors must be stored in a contiguous memory section, where the transfer descriptors must be ordered according to their channel number. For further details on linked descriptors, refer to 25.6.3.1 Linked Descriptors. The write-back memory section is the section where the DMAC stores the transfer descriptors for the ongoing block transfers. WRBADDR points to the ongoing transfer descriptor of channel 0. All ongoing transfer descriptors will be stored in a contiguous memory section where the transfer descriptors are ordered according to their channel number. The figure below shows an example of linked descriptors on DMA channel 0. For further details on linked descriptors, refer to 25.6.3.1 Linked Descriptors. Figure 25-3. Memory Sections Channel 0 – Descriptor n-1 Channel 0 – Last Descriptor DESCADDR DESCADDR Device Memory Space BASEADDR Channel 0 – First Descriptor Channel 1 – First Descriptor Channel 2 – First Descriptor Channel n – First Descriptor Descriptor Section WRBADDR Channel 0 Ongoing Descriptor Channel 1 Ongoing Descriptor Channel 2 Ongoing Descriptor Channel n Ongoing Descriptor Write-Back Section Undefined Undefined Undefined Undefined Undefined SRCADDR DSTADDR BTCTRL DESCADDR BTCNT SRCADDR DSTADDR BTCTRL DESCADDR BTCNT SRCADDR DSTADDR BTCTRL 0x00000000 BTCNT The size of the descriptor and write-back memory sections is dependent on the number of the most significant enabled DMA channel m, as shown below: ? + ͳ SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 371

For memory optimization, it is recommended to always use the less significant DMA channels if not all channels are required. The descriptor and write-back memory sections can either be two separate memory sections, or they can share memory section (BASEADDR=WRBADDR). The benefit of having them in two separate sections, is that the same transaction for a channel can be repeated without having to modify the first transfer descriptor. The benefit of having descriptor memory and write-back memory in the same section is that it requires less SRAM. In addition, the latency from fetching the first descriptor of a transaction to the first burst transfer is executed, is reduced.

25.6.2.4 Arbitration

If a DMA channel is enabled and not suspended when it receives a transfer trigger, it will send a transfer request to the arbiter. When the arbiter receives the transfer request it will include the DMA channel in the queue of channels having pending transfers, and the corresponding Pending Channel x bit in the Pending Channels registers ( PENDCH.PENDCHx) will be set. Depending on the arbitration scheme, the arbiter will choose which DMA channel will be the next active channel. The active channel is the DMA channel being granted access to perform its next burst transfer. When the arbiter has granted a DMA channel access to the DMAC, the corresponding bit PENDCH.PENDCHx will be cleared. See also the following figure. If the upcoming burst transfer is the first for the transfer request, the corresponding Busy Channel x bit in the Busy Channels register will be set ( BUSYCH.BUSYCHx=1), and it will remain '1' for the subsequent granted burst transfers. When the channel has performed its granted burst transfer(s) it will be either fed into the queue of channels with pending transfers, set to be waiting for a new transfer trigger, suspended, or disabled. This depends on the channel and block transfer configuration. If the DMA channel is fed into the queue of channels with pending transfers, the corresponding BUSYCH.BUSYCHx will remain '1'. If the DMA channel is set to wait for a new transfer trigger, suspended, or disabled, the corresponding BUSYCH.BUSYCHx will be cleared. If a DMA channel is suspended while it has a pending transfer, it will be removed from the queue of pending channels, but the corresponding PENDCH.PENDCHx will remain set. When the same DMA channel is resumed, it will be added to the queue of pending channels again. If a DMA channel gets disabled ( CHCTRLA.ENABLE=0) while it has a pending transfer, it will be removed from the queue of pending channels, and the corresponding PENDCH.PENDCHx will be cleared. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 372

Figure 25-4. Arbiter Overview Channel 0 Channel N Active Channel Priority decoder Active.LVLEXx PRICTRLx.LVLPRI Arbiter CTRL.LVLENx Burst Done Transfer Request Channel Number Level Enable Channel Burst Done Channel Priority Level Channel Pending Channel Suspend Channel Burst Done Channel Priority Level Channel Pending Channel Suspend Priority Levels When a channel level is pending or the channel is transferring data, the corresponding Level Executing bit is set in the Active Channel and Levels register ( ACTIVE.LVLEXx). Each DMA channel supports a 4-level priority scheme. The priority level for a channel is configured by writing to the Channel Arbitration Level bit group in the Channel Control B register (CHCTRLB.LVL). As long as all priority levels are enabled, a channel with a higher priority level number will have priority over a channel with a lower priority level number. Each priority level x is enabled by setting the corresponding Priority Level x Enable bit in the Control register ( CTRL.LVLENx=1). Within each priority level the DMAC's arbiter can be configured to prioritize statically or dynamically: Static Arbitration within a priority level is selected by writing a '0' to the Level x Round-Robin Scheduling Enable bit in the Priority Control 0 register ( PRICTRL0.RRLVLENx). When static arbitration is selected, the arbiter will prioritize a low channel number over a high channel number as shown in the figure below. When using the static arbitration there is a risk of high channel numbers never being granted access as the active channel. This can be avoided using a dynamic arbitration scheme. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 373

Figure 25-5. Static Priority Scheduling Highest Channel Lowest Channel Highest Priority Lowest PriorityChannel N Channel 0 Channel x+1 Channel x Dynamic Arbitration within a priority level is selected by writing a '1' to PRICTRL0.RRLVLENx. The dynamic arbitration scheme in the DMAC is round-robin. With the round-robin scheme, the channel number of the last channel being granted access will have the lowest priority the next time the arbiter has to grant access to a channel within the same priority level, as shown in Figure 25-6. The channel number of the last channel being granted access as the active channel is stored in the Level x Channel Priority Number bit group in the Priority Control 0 register ( PRICTRL0.LVLPRIx) for the corresponding priority level. Figure 25-6. Dynamic (Round-Robin) Priority Scheduling Channel N Channel N Channel 0 Channel x Channel x+1 Channel x last acknowledge request Channel (x+1) last acknowledge request Channel 0 Channel x Channel x+1 Channel x+2 Lowest Priority Highest Priority Highest Priority Lowest Priority

25.6.2.5 Data Transmission

Before the DMAC can perform a data transmission, a DMA channel has to be configured and enabled, its corresponding transfer descriptor has to be initialized, and the arbiter has to grant the DMA channel access as the active channel. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 374

Once the arbiter has granted a DMA channel access as the active channel (refer to DMA Block Diagram section) the transfer descriptor for the DMA channel will be fetched from SRAM using the fetch bus, and stored in the internal memory for the active channel. For a new block transfer, the transfer descriptor will be fetched from the descriptor memory section ( BASEADDR); For an ongoing block transfer, the descriptor will be fetched from the write-back memory section (WRBADDR). By using the data transfer bus, the DMAC will read the data from the current source address and write it to the current destination address. For further details on how the current source and destination addresses are calculated, refer to the section on Addressing. The arbitration procedure is performed after each burst transfer. If the current DMA channel is granted access again, the block transfer counter ( BTCNT) of the internal transfer descriptor will be decremented by the number of beats in a burst transfer, the optional output event Beat will be generated if configured and enabled, and the active channel will perform a new burst transfer. If a different DMA channel than the current active channel is granted access, the block transfer counter value will be written to the write-back section before the transfer descriptor of the newly granted DMA channel is fetched into the internal memory of the active channel. When a block transfer has come to its end ( BTCNT is zero), the Valid bit in the Block Transfer Control register will be cleared (BTCTRL.VALID=0) before the entire transfer descriptor is written to the write- back memory. The optional interrupts, Channel Transfer Complete and Channel Suspend, and the optional output event Block, will be generated if configured and enabled. After the last block transfer in a transaction, the Next Descriptor Address register ( DESCADDR) will hold the value 0x00000000, and the DMA channel will either be suspended or disabled, depending on the configuration in the Block Action bit group in the Block Transfer Control register ( BTCTRL.BLOCKACT). If the transaction has further block transfers pending, DESCADDR will hold the SRAM address to the next transfer descriptor to be fetched. The DMAC will fetch the next descriptor into the internal memory of the active channel and write its content to the write-back section for the channel, before the arbiter gets to choose the next active channel.

25.6.2.6 Transfer Triggers and Actions

A DMA transfer through a DMA channel can be started only when a DMA transfer request is detected, and the DMA channel has been granted access to the DMA. A transfer request can be triggered from software, from a peripheral, or from an event. There are dedicated Trigger Source selections for each DMA Channel Control B (CHCTRLB.TRIGSRC). The trigger actions are available in the Trigger Action bit group in the Channel Control B register (CHCTRLB.TRIGACT). By default, a trigger generates a request for a block transfer operation. If a single descriptor is defined for a channel, the channel is automatically disabled when a block transfer has been completed. If a list of linked descriptors is defined for a channel, the channel is automatically disabled when the last descriptor in the list is executed. If the list still has descriptors to execute, the channel will be waiting for the next block transfer trigger. When enabled again, the channel will wait for the next block transfer trigger. The trigger actions can also be configured to generate a request for a beat transfer (CHCTRLB.TRIGACT=0x2) or transaction transfer (CHCTRLB.TRIGACT=0x3) instead of a block transfer (CHCTRLB.TRIGACT=0x0). Figure 25-7 shows an example where triggers are used with two linked block descriptors. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 375

Figure 25-7. Trigger Action and Transfers CHENn Trigger PENDCHn BUSYCHn Data Transfer CHENn Trigger PENDCHn BUSYCHn Data Transfer CHENn Trigger PENDCHn BUSYCHn Data Transfer Block Transfer Block TransferBlock Transfer Block TransferBlock Transfer Block Transfer Trigger Lost Trigger Lost Trigger Lost Transaction Trigger Action Block Trigger Action Beat Trigger Action BEATBEAT BEAT BEAT BEATBEAT BEATBEAT BEAT BEAT BEATBEAT BEATBEAT BEAT BEAT BEATBEAT If the trigger source generates a transfer request for a channel during an ongoing transfer, the new transfer request will be kept pending (CHSTATUS.PEND=1), and the new transfer can start after the ongoing one is done. Only one pending transfer can be kept per channel. If the trigger source generates more transfer requests while one is already pending, the additional ones will be lost. All channels pending status flags are also available in the Pending Channels register (PENDCH). When the transfer starts, the corresponding Channel Busy status flag is set in Channel Status register (CHSTATUS.BUSY). When the trigger action is complete, the Channel Busy status flag is cleared. All channel busy status flags are also available in the Busy Channels register (BUSYCH) in DMAC.

25.6.2.7 Addressing

Each block transfer needs to have both a source address and a destination address defined. The source address is set by writing the Transfer Source Address ( SRCADDR) register, the destination address is set by writing the Transfer Destination Address (SRCADDR) register. The addressing of this DMAC module can be static or incremental, for either source or destination of a block transfer, or both. Incrementation for the source address of a block transfer is enabled by writing the Source Address Incrementation Enable bit in the Block Transfer Control register ( BTCTRL.SRCINC=1). The step size of the incrementation is configurable and can be chosen by writing the Step Selection bit in the Block SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 376

Transfer Control register (BTCTRL.STEPSEL=1) and writing the desired step size in the Address Increment Step Size bit group in the Block Transfer Control register (BTCTRL.STEPSIZE). If BTCTRL.STEPSEL=0, the step size for the source incrementation will be the size of one beat. When source address incrementation is configured (BTCTRL.SRCINC=1), SRCADDR is calculated as follows: If BTCTRL.STEPSEL=1: If BTCTRL.STEPSEL=0:

SRCADDR START is the source address of the first beat transfer in the block transfer
BTCNT is the initial number of beats remaining in the block transfer
BEATSIZE is the configured number of bytes in a beat
STEPSIZE is the configured number of beats for each incrementation The following figure shows an example where DMA channel 0 is configured to increment the source address by one beat after each beat transfer ( BTCTRL.SRCINC=1), and DMA channel 1 is configured to increment the source address by two beats (BTCTRL.SRCINC=1, BTCTRL.STEPSEL=1, and BTCTRL.STEPSIZE=0x1). As the destination address for both channels are peripherals, destination incrementation is disabled (BTCTRL.DSTINC=0). Figure 25-8. Source Address Increment SRC Data Buffer a b c d e f Incrementation for the destination address of a block transfer is enabled by setting the Destination Address Incrementation Enable bit in the Block Transfer Control register ( BTCTRL.DSTINC=1). The step size of the incrementation is configurable by clearing BTCTRL.STEPSEL=0 and writing BTCTRL.STEPSIZE to the desired step size. If BTCTRL.STEPSEL=1, the step size for the destination incrementation will be the size of one beat. When the destination address incrementation is configured ( BTCTRL.DSTINC=1), DSTADDR must be set and calculated as follows: SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 377

DSTADDR START is the destination address of the first beat transfer in the block transfer
BTCNT is the initial number of beats remaining in the block transfer
BEATSIZE is the configured number of bytes in a beat
STEPSIZE is the configured number of beats for each incrementation The followiong figure shows an example where DMA channel 0 is configured to increment destination address by one beat ( BTCTRL.DSTINC=1) and DMA channel 1 is configured to increment destination address by two beats (BTCTRL.DSTINC=1, BTCTRL.STEPSEL=0, and BTCTRL.STEPSIZE=0x1). As the source address for both channels are peripherals, source incrementation is disabled BTCTRL.SRCINC=0). Figure 25-9. Destination Address Increment DST Data Buffer a b c d

25.6.2.8 Error Handling

If a bus error is received from an AHB slave during a DMA data transfer, the corresponding active channel is disabled and the corresponding Channel Transfer Error Interrupt flag in the Channel Interrupt Status and Clear register (CHINTFLAG.TERR) is set. If enabled, the optional transfer error interrupt is generated. The transfer counter will not be decremented and its current value is written-back in the write- back memory section before the channel is disabled. When the DMAC fetches an invalid descriptor (BTCTRL.VALID=0) or when the channel is resumed and the DMA fetches the next descriptor with null address (DESCADDR=0x00000000), the corresponding channel operation is suspended, the Channel Suspend Interrupt Flag in the Channel Interrupt Flag Status and Clear register (CHINTFLAG.SUSP) is set, and the Channel Fetch Error bit in the Channel Status register (CHSTATUS.FERR) is set. If enabled, the optional suspend interrupt is generated.

25.6.3 Additional Features

25.6.3.1 Linked Descriptors

A transaction can consist of either a single block transfer or of several block transfers. When a transaction consists of several block transfers it is done with the help of linked descriptors. Figure 25-3 illustrates how linked descriptors work. When the first block transfer is completed on DMA channel 0, the DMAC fetches the next transfer descriptor, which is pointed to by the value stored in the Next Descriptor Address ( DESCADDR) register of the first transfer descriptor. Fetching the next transfer descriptor (DESCADDR) is continued until the last transfer descriptor. When the block transfer for the last transfer descriptor is executed and DESCADDR=0x00000000, the transaction is terminated. For further details on how the next descriptor is fetched from SRAM, refer to section 25.6.2.5 Data Transmission. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 378

25.6.3.1.1 Adding Descriptor to the End of a List

To add a new descriptor at the end of the descriptor list, create the descriptor in SRAM, with DESCADDR=0x00000000 indicating that it is the new last descriptor in the list, and modify the DESCADDR value of the current last descriptor to the address of the newly created descriptor.

25.6.3.1.2 Modifying a Descriptor in a List

In order to add descriptors to a linked list, the following actions must be performed: 1. Enable the Suspend interrupt for the DMA channel. 2. Enable the DMA channel. 3. Reserve memory space in SRAM to configure a new descriptor. 4. Configure the new descriptor: – Set the next descriptor address ( DESCADDR) – Set the destination address (DSTADDR) – Set the source address (SRCADDR) – Configure the block transfer control (BTCTRL) including

Optionally enable the Suspend block action
Set the descriptor VALID bit 5. Clear the VALID bit for the existing list and for the descriptor which has to be updated. 6. Read DESCADDR from the Write-Back memory. – If the DMA has not already fetched the descriptor which requires changes (i.e., DESCADDR is wrong):
Update the DESCADDR location of the descriptor from the List
Optionally clear the Suspend block action
Set the descriptor VALID bit to '1'
Optionally enable the Resume software command – If the DMA is executing the same descriptor as the one which requires changes:
Set the Channel Suspend software command and wait for the Suspend interrupt
Update the next descriptor address ( DESCRADDR) in the write-back memory
Clear the interrupt sources and set the Resume software command
Update the DESCADDR location of the descriptor from the List
Optionally clear the Suspend block action
Set the descriptor VALID bit to '1' 7. Go to step 4 if needed.

25.6.3.1.3 Adding a Descriptor Between Existing Descriptors

To insert a new descriptor 'C' between two existing descriptors ('A' and 'B'), the descriptor currently executed by the DMA must be identified. 1. If DMA is executing descriptor B, descriptor C cannot be inserted. 2. If DMA has not started to execute descriptor A, follow the steps: 2.1. Set the descriptor A VALID bit to '0'. 2.2. Set the DESCADDR value of descriptor A to point to descriptor C instead of descriptor B. 2.3. Set the DESCADDR value of descriptor C to point to descriptor B. 2.4. Set the descriptor A VALID bit to '1'. 3. If DMA is executing descriptor A: 3.1. Apply the software suspend command to the channel and SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 379

3.3. Apply the software resume command to the channel.

25.6.3.2 Channel Suspend

The channel operation can be suspended at any time by software by writing a '1' to the Suspend command in the Command bit field of Channel Control B register (CHCTRLB.CMD). After the ongoing burst transfer is completed, the channel operation is suspended and the suspend command is automatically cleared. When suspended, the Channel Suspend Interrupt flag in the Channel Interrupt Status and Clear register is set (CHINTFLAG.SUSP=1) and the optional suspend interrupt is generated. By configuring the block action to suspend by writing Block Action bit group in the Block Transfer Control register (BTCTRL.BLOCKACT is 0x2 or 0x3), the DMA channel will be suspended after it has completed a block transfer. The DMA channel will be kept enabled and will be able to receive transfer triggers, but it will be removed from the arbitration scheme. If an invalid transfer descriptor (BTCTRL.VALID=0) is fetched from SRAM, the DMA channel will be suspended, and the Channel Fetch Error bit in the Channel Status register(CHASTATUS.FERR) will be set. Note: Only enabled DMA channels can be suspended. If a channel is disabled when it is attempted to be suspended, the internal suspend command will be ignored. For more details on transfer descriptors, refer to section 25.6.2.3 Transfer Descriptors. Related Links

25.8.22 CHINTFLAG

25.6.3.3 Channel Resume and Next Suspend Skip

A channel operation can be resumed by software by setting the Resume command in the Command bit field of the Channel Control B register (CHCTRLB.CMD). If the channel is already suspended, the channel operation resumes from where it previously stopped when the Resume command is detected. When the Resume command is issued before the channel is suspended, the next suspend action is skipped and the channel continues the normal operation. Figure 25-10. Channel Suspend/Resume Operation CHENn Memory Descriptor Transfer Resume Command Descriptor 0 (suspend disabled) Fetch Block Transfer 0 Descriptor 1 (suspend enabled) Block Transfer 1 Suspend skipped Descriptor 2 (suspend enabled) Block Transfer 2 Channel suspended Descriptor 3 (last) Block Transfer 3 Related Links

25.6.3.4 Event Input Actions

The event input actions are available only on the least significant DMA channels. For details on channels with event input support, refer to the in the Event system documentation. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 380

Before using event input actions, the event controller must be configured first according to the following table, and the Channel Event Input Enable bit in the Channel Control B register (CHCTRLB.EVIE) must be written to '1'. Refer also to 25.6.6 Events. Table 25-1. Event Input Action Action CHCTRLB.EVACT CHCTRLB.TRGSRC None NOACT - Normal Transfer TRIG DISABLE Conditional Transfer on Strobe TRIG any peripheral Conditional Transfer CTRIG Conditional Block Transfer CBLOCK Channel Suspend SUSPEND Channel Resume RESUME Skip Next Block Suspend SSKIP Normal Transfer The event input is used to trigger a beat or burst transfer on peripherals. The event is acknowledged as soon as the event is received. When received, both the Channel Pending status bit in the Channel Status register ( CHSTATUS.PEND) and the corresponding Channel n bit in the Pending Channels register (25.8.13 PENDCH.PENDCHn) are set. If the event is received while the channel is pending, the event trigger is lost. The figure below shows an example where beat transfers are enabled by internal events. Figure 25-11. Beat Event Trigger Action CHENn Peripheral Trigger Event PENDCHn BUSYCHn Data Transfer Trigger Lost Block Transfer BEAT BEAT BEAT BEAT BEAT BEAT Block Transfer Conditional Transfer on Strobe The event input is used to trigger a transfer on peripherals with pending transfer requests. This event action is intended to be used with peripheral triggers, e.g. for timed communication protocols or periodic transfers between peripherals: only when the peripheral trigger coincides with the occurrence of a (possibly cyclic) event the transfer is issued. The event is acknowledged as soon as the event is received. The peripheral trigger request is stored internally when the previous trigger action is completed (i.e. the channel is not pending) and when an SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 381

Conditional Block Transfer The event input is used to trigger a conditional block transfer on peripherals. Before starting transfers within a block, an event must be received. When received, the event is acknowledged when the block transfer is completed. A software trigger will trigger a transfer. The figure below shows an example where conditional event block transfer is started with peripheral beat trigger requests. Figure 25-14. Conditional Block Transfer with Beat Peripheral Triggers BEAT BEAT Block Transfer BEAT BEAT Block Transfer Data Transfer Peripheral Trigger Event PENDCHn Channel Suspend The event input is used to suspend an ongoing channel operation. The event is acknowledged when the current AHB access is completed. For further details on Channel Suspend, refer to

25.6.3.2 Channel

Suspend. Channel Resume The event input is used to resume a suspended channel operation. The event is acknowledged as soon as the event is received and the Channel Suspend Interrupt Flag ( CHINTFLAG.SUSP) is cleared. For further details refer to 25.6.3.2 Channel Suspend. Skip Next Block Suspend This event can be used to skip the next block suspend action. If the channel is suspended before the event rises, the channel operation is resumed and the event is acknowledged. If the event rises before a suspend block action is detected, the event is kept until the next block suspend detection. When the block transfer is completed, the channel continues the operation (not suspended) and the event is acknowledged.

25.6.3.5 Event Output Selection

Event output selection is available only for the least significant DMA channels. The pulse width of an event output from a channel is one AHB clock cycle. The output of channel events is enabled by writing a '1' to the Channel Event Output Enable bit in the Control B register (CHCTRLB.EVOE). The event output cause is selected by writing to the Event Output Selection bits in the Block Transfer Control register (BTCTRL.EVOSEL). It is possible to generate events after each block transfer (BTCTRL.EVOSEL=0x1) or beat transfer (BTCTRL.EVOSEL=0x3). To enable an event being generated when a transaction is complete, the block event selection must be set in the last transfer descriptor only. Figure 25-15 shows an example where the event output generation is enabled in the first block transfer, and disabled in the second block. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 383

Figure 25-15. Event Output Generation Beat Event Output Data Transfer Event Output Data Transfer Event Output Block Transfer BEAT Block Event Output Block Transfer Block TransferBlock Transfer BEAT BEATBEAT BEAT BEAT BEAT BEAT Related Links

25.6.3.6 Aborting Transfers

Transfers on any channel can be aborted gracefully by software by disabling the corresponding DMA channel. It is also possible to abort all ongoing or pending transfers by disabling the DMAC. When a DMA channel disable request or DMAC disable request is detected:

Ongoing transfers of the active channel will be disabled when the ongoing beat transfer is completed and the write-back memory section is updated. This prevents transfer corruption before the channel is disabled.
All other enabled channels will be disabled in the next clock cycle. The corresponding Channel Enable bit in the Channel Control A register is cleared (CHCTRLA.ENABLE=0) when the channel is disabled. The corresponding DMAC Enable bit in the Control register is cleared (CTRL.DMAENABLE=0) when the entire DMAC module is disabled.

25.6.3.7 CRC Operation

A cyclic redundancy check (CRC) is an error detection technique used to find errors in data. It is commonly used to determine whether the data during a transmission, or data present in data and program memories has been corrupted or not. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be appended to the data and used as a checksum. When the data is received, the device or application repeats the calculation: If the new CRC result does not match the one calculated earlier, the block contains a data error. The application will then detect this and may take a corrective action, such as requesting the data to be sent again or simply not using the incorrect data. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 384

The CRC engine in DMAC supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3). Typically, applying CRC-n (CRC-16 or CRC-32) to a data block of arbitrary length will detect any single alteration that is ≤n bits in length, and will detect the fraction 1-2-n of all longer error bursts.

CRC-16: – Polynomial: x16+ x12+ x5+ 1 – Hex value: 0x1021
CRC-32: – Polynomial: x32+x26+ x23+ x22+x16+ x12+ x11+ x10+ x8+ x7+ x5+ x4+ x2+ x + 1 – Hex value: 0x04C11DB7 The data source for the CRC engine can either be one of the DMA channels or the APB bus interface, and must be selected by writing to the CRC Input Source bits in the CRC Control register (CRCCTRL.CRCSRC). The CRC engine then takes data input from the selected source and generates a checksum based on these data. The checksum is available in the CRC Checksum register CRCCHKSUM). When CRC-32 polynomial is used, the final checksum read is bit reversed and complemented, as shown in Figure 25-16. The CRC polynomial is selected by writing to the CRC Polynomial Type bit in the CRC Control register (CRCCTRL.CRCPOLY), the default is CRC-16. The CRC engine operates on byte only. When the DMA is used as data source for the CRC engine, the DMA channel beat size setting will be used. When used with APB bus interface, the application must select the CRC Beat Size bit field of CRC Control register (CRCCTRL.CRCBEATSIZE). 8-, 16-, or 32-bit bus transfer access type is supported. The corresponding number of bytes will be written in the CRCDATAIN register and the CRC engine will operate on the input data in a byte by byte manner. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 385

Figure 25-16. CRC Generator Block Diagram 168 8 32 Checksum read crc32 CRCCTRL CHECKSUM bit-reverse + complement CRC-16 CRC-32 DMAC Channels CRCDATAIN CRC on DMA data CRC-16 or CRC-32 calculations can be performed on data passing through any DMA channel. Once a DMA channel is selected as the source, the CRC engine will continuously generate the CRC on the data passing through the DMA channel. The checksum is available for readout once the DMA transaction is completed or aborted. A CRC can also be generated on SRAM, Flash, or I/O memory by passing these data through a DMA channel. If the latter is done, the destination register for the DMA data can be the data input ( CRCDATAIN) register in the CRC engine. CRC using the I/O interface Before using the CRC engine with the I/O interface, the application must set the CRC Beat Size bits in the CRC Control register (CRCCTRL.CRCBEATSIZE). 8/16/32-bit bus transfer type can be selected. CRC can be performed on any data by loading them into the CRC engine using the CPU and writing the data to the CRCDATAIN register. Using this method, an arbitrary number of bytes can be written to the register by the CPU, and CRC is done continuously for each byte. This means if a 32-bit data is written to the CRCDATAIN register the CRC engine takes four cycles to calculate the CRC. The CRC complete is signaled by a set CRCBUSY bit in the CRCSTATUS register. New data can be written only when CRCBUSY flag is not set.

25.6.4 DMA Operation

25.6.5 Interrupts

The DMAC channels have the following interrupt sources:

Transfer Complete (TCMPL): Indicates that a block transfer is completed on the corresponding
Transfer Error (TERR): Indicates that a bus error has occurred during a burst transfer, or that an
Channel Suspend (SUSP): Indicates that the corresponding channel has been suspended. Refer to Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Channel Interrupt Flag Status and Clear (CHINTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by setting the corresponding bit in the Channel Interrupt Enable Set register (CHINTENSET=1), and disabled by setting the corresponding bit in the Channel Interrupt Enable Clear register (CHINTENCLR=1). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, the DMAC is reset or the corresponding DMA channel is reset. See CHINTFLAG for details on how to clear interrupt flags. All interrupt requests are ORed together on system level to generate one combined interrupt request to the NVIC. The user must read the Channel Interrupt Status (INTSTATUS) register to identify the channels with pending interrupts and must read the Channel Interrupt Flag Status and Clear (CHINTFLAG) register to determine which interrupt condition is present for the corresponding channel. It is also possible to read the Interrupt Pending register (INTPEND), which provides the lowest channel number with pending interrupt and the respective interrupt flags. Note: Interrupts must be globally enabled for interrupt requests to be generated. Related Links

25.6.6 Events

The DMAC can generate the following output events:

Channel (CH): Generated when a block transfer for a given channel has been completed, or when a beat transfer within a block transfer for a given channel has been completed. Refer to Event Output Selection for details. Setting the Channel Event Output Enable bit (CHEVCTRLx.EVOE = 1) enables the corresponding output event configured in the Event Output Selection bit group in the Block Transfer Control register (BTCTRL.EVOSEL). Clearing CHEVCTRLx.EVOE = 0 disables the corresponding output event. The DMAC can take the following actions on an input event:
Transfer and Periodic Transfer Trigger (TRIG): normal transfer or periodic transfers on peripherals are enabled
Conditional Transfer Trigger (CTRIG): conditional transfers on peripherals are enabled
Conditional Block Transfer Trigger (CBLOCK): conditional block transfers on peripherals are enabled
Channel Suspend Operation (SUSPEND): suspend a channel operation
Channel Resume Operation (RESUME): resume a suspended channel operation
Skip Next Block Suspend Action (SSKIP): skip the next block suspend transfer condition SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 387

Increase Priority (INCPRI): increase channel priority Setting the Channel Event Input Enable bit (CHEVCTRLx.EVIE = 1) enables the corresponding action on input event. Clearing this bit disables the corresponding action on input event. Note that several actions can be enabled for incoming events. If several events are connected to the peripheral, any enabled action will be taken for any of the incoming events. For further details on event input actions, refer to Event Input Actions. Note: Event input and outputs are not available for every channel. Refer to the Features section for more information. Related Links 29. EVSYS – Event System

25.6.7 Sleep Mode Operation

Each DMA channel can be configured to operate in any sleep mode. To be able to run in standby, the RUNSTDBY bit in Channel Control A register (CHCTRLA.RUNSTDBY) must be written to '1'. The DMAC can wake up the device using interrupts from any sleep mode or perform actions through the Event System. For channels with CHCTRLA.RUNSTDBY = 0, it is up to software to stop DMA transfers on these channels and wait for completion before going to standby mode using the following sequence: 1. Suspend the DMAC channels for which CHCTRLA.RUNSTDBY = 0. 2. Check the SYNCBUSY bits of registers accessed by the DMAC channels being suspended. 3. Go to sleep. 4. When the device wakes up, resume the suspended channels. Note: In Stand-by Sleep mode, the DMAC can only access RAM when it is not back biased (PM.STDBYCFG.BBIASxx = 0x0)

25.6.8 Synchronization

25.7 Register Summary

Offset Name Bit Pos. 0x00 CTRL 7:0 CRCENABLE DMAENABLE SWRST 15:8 LVLENx3 LVLENx2 LVLENx1 LVLENx0 0x02 CRCCTRL 7:0 CRCPOLY[1:0] CRCBEATSIZE[1:0] 15:8 CRCSRC[5:0] 0x04 CRCDATAIN 7:0 CRCDATAIN[7:0] 15:8 CRCDATAIN[15:8] 23:16 CRCDATAIN[23:16] 31:24 CRCDATAIN[31:24] 0x08 CRCCHKSUM 7:0 CRCCHKSUM[7:0] 15:8 CRCCHKSUM[15:8] 23:16 CRCCHKSUM[23:16] 31:24 CRCCHKSUM[31:24] 0x0C CRCSTATUS 7:0 CRCZERO CRCBUSY 0x0D DBGCTRL 7:0 DBGRUN 0x0E QOSCTRL 7:0 DQOS[1:0] FQOS[1:0] WRBQOS[1:0] 0x0F Reserved 0x10 SWTRIGCTRL 7:0 SWTRIGn[7:0] 15:8 SWTRIGn[11:8] 23:16 31:24 0x14 PRICTRL0 7:0 RRLVLEN0 LVLPRI0[3:0] 15:8 RRLVLEN1 LVLPRI1[3:0] 23:16 RRLVLEN2 LVLPRI2[3:0] 31:24 RRLVLEN3 LVLPRI3[3:0] 0x18 ... 0x1F Reserved 0x20 INTPEND 7:0 ID[3:0] 15:8 PEND BUSY FERR SUSP TCMPL TERR 0x22 ... 0x23 Reserved 0x24 INTSTATUS 7:0 CHINTn[7:0] 15:8 CHINTn[11:8] 23:16 31:24 0x28 BUSYCH 7:0 BUSYCHn[7:0] 15:8 BUSYCHn[11:8] 23:16 31:24 SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 389

Offset Name Bit Pos. 0x2C PENDCH 7:0 PENDCH7 PENDCH6 PENDCH5 PENDCH4 PENDCH3 PENDCH2 PENDCH1 PENDCH0 15:8 PENDCH11 PENDCH10 PENDCH9 PENDCH8 23:16 31:24 0x30 ACTIVE 7:0 LVLEXx LVLEXx LVLEXx LVLEXx 15:8 ABUSY ID[4:0] 23:16 BTCNT[7:0] 31:24 BTCNT[15:8] 0x34 BASEADDR 7:0 15:8 23:16 31:24 0x38 WRBADDR 7:0 15:8 23:16 31:24 0x3C ... 0x3E Reserved 0x3F CHID 7:0 ID[3:0] 0x40 CHCTRLA 7:0 RUNSTDBY ENABLE SWRST 0x41 ... 0x43 Reserved 0x44 CHCTRLB 7:0 LVL[1:0] EVOE EVIE EVACT[2:0] 15:8 TRIGSRC[5:0] 23:16 TRIGACT[1:0] 31:24 CMD[1:0] 0x48 ... 0x4B Reserved 0x4C CHINTENCLR 7:0 SUSP TCMPL TERR 0x4D CHINTENSET 7:0 SUSP TCMPL TERR 0x4E CHINTFLAG 7:0 SUSP TCMPL TERR 0x4F CHSTATUS 7:0 FERR BUSY PEND

25.8 Register Description

Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 391

25.8.1 Control

Name: CTRL Offset: 0x00 Reset: 0x00X0 Property: PAC Write-Protection, Enable-Protected Bit 15 14 13 12 11 10 9 8 LVLENx3 LVLENx2 LVLENx1 LVLENx0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCENABLE DMAENABLE SWRST Access R/W R/W R/W Reset 0 0 0 Bits 8, 9, 10, 11 – LVLENx Priority Level x Enable When this bit is set, all requests with the corresponding level will be fed into the arbiter block. When cleared, all requests with the corresponding level will be ignored. For details on arbitration schemes, refer to the Arbitration section. These bits are not enable-protected. Value Description 0 Transfer requests for Priority level x will not be handled. 1 Transfer requests for Priority level x will be handled. Bit 2 – CRCENABLE CRC Enable Writing a '0' to this bit will disable the CRC calculation when the CRC Status Busy flag is cleared (CRCSTATUS. CRCBUSY). The bit is zero when the CRC is disabled. Writing a '1' to this bit will enable the CRC calculation. Value Description 0 The CRC calculation is disabled. 1 The CRC calculation is enabled. Bit 1 – DMAENABLE DMA Enable Setting this bit will enable the DMA module. Writing a '0' to this bit will disable the DMA module. When writing a '0' during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst transfer is completed. This bit is not enable-protected. Value Description 0 The peripheral is disabled. 1 The peripheral is enabled. Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit when both the DMAC and the CRC module are disabled (DMAENABLE and CRCENABLE are '0') resets all registers in the DMAC (except DBGCTRL) to their initial state. If either the SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 392

DMAC or CRC module is enabled, the Reset request will be ignored and the DMAC will return an access error. Value Description 0 There is no Reset operation ongoing. 1 A Reset operation is ongoing. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 393

25.8.2 CRC Control

Name: CRCCTRL Offset: 0x02 Reset: 0x0000 Property: PAC Write-Protection, Enable-Protected Bit 15 14 13 12 11 10 9 8 CRCSRC[5:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCPOLY[1:0] CRCBEATSIZE[1:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 13:8 – CRCSRC[5:0] CRC Input Source These bits select the input source for generating the CRC, as shown in the table below. The selected source is locked until either the CRC generation is completed or the CRC module is disabled. This means the CRCSRC cannot be modified when the CRC operation is ongoing. The lock is signaled by the CRCBUSY status bit. CRC generation complete is generated and signaled from the selected source when used with the DMA channel. Value Name Description 0x00 NOACT No action 0x01 IO I/O interface 0x02-0x - Reserved 0x20 CHN DMA channel 0 0x21 CHN DMA channel 1 0x22 CHN DMA channel 2 0x23 CHN DMA channel 3 0x24 CHN DMA channel 4 0x25 CHN DMA channel 5 0x26 CHN DMA channel 6 0x27 CHN DMA channel 7 0x28 CHN DMA channel 8 0x29 CHN DMA channel 9 0x2A CHN DMA channel 10 0x2B CHN DMA channel 11 0x2C CHN DMA channel 12 0x2D CHN DMA channel 13 0x2E CHN DMA channel 14 0x2F CHN DMA channel 15 0x30 CHN DMA channel 16 0x31 CHN DMA channel 17 0x32 CHN DMA channel 18 0x33 CHN DMA channel 19 SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 394

Bits 3:2 – CRCPOLY[1:0] CRC Polynomial Type These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface, as shown in the table below. Value Name Description 0x0 CRC16 CRC-16 (CRC-CCITT) 0x1 CRC32 CRC32 (IEEE 802.3) 0x2-0x3 Reserved Bits 1:0 – CRCBEATSIZE[1:0] CRC Beat Size These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface. Value Name Description 0x0 BYTE 8-bit bus transfer 0x1 HWORD 16-bit bus transfer 0x2 WORD 32-bit bus transfer 0x3 Reserved SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 395

25.8.3 CRC Data Input

Name: CRCDATAIN Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 CRCDATAIN[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CRCDATAIN[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CRCDATAIN[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCDATAIN[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – CRCDATAIN[31:0] CRC Data Input These bits store the data for which the CRC checksum is computed. A new CRC Checksum is ready (CRCBEAT+ 1) clock cycles after the CRCDATAIN register is written. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 396

25.8.4 CRC Checksum

Name: CRCCHKSUM Offset: 0x08 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected The CRCCHKSUM represents the 16- or 32-bit checksum value and the generated CRC. The register is reset to zero by default, but it is possible to reset all bits to one by writing the CRCCHKSUM register directly. It is possible to write this register only when the CRC module is disabled. If CRC-32 is selected and the CRC Status Busy flag is cleared (i.e., CRC generation is completed or aborted), the bit reversed (bit 31 is swapped with bit 0, bit 30 with bit 1, etc.) and complemented result will be read from CRCCHKSUM. If CRC-16 is selected or the CRC Status Busy flag is set (i.e., CRC generation is ongoing), CRCCHKSUM will contain the actual content. Bit 31 30 29 28 27 26 25 24 CRCCHKSUM[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CRCCHKSUM[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CRCCHKSUM[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCCHKSUM[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – CRCCHKSUM[31:0] CRC Checksum These bits store the generated CRC result. The 16 MSB bits are always read zero when CRC-16 is enabled. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 397

25.8.5 CRC Status

Name: CRCSTATUS Offset: 0x0C Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CRCZERO CRCBUSY Access R R/W Reset 0 0 Bit 1 – CRCZERO CRC Zero This bit is cleared when a new CRC source is selected. This bit is set when the CRC generation is complete and the CRC Checksum is zero. When running CRC-32 and appending the checksum at the end of the packet (as little endian), the final checksum should be 0x2144df1c, and not zero. However, if the checksum is complemented before it is appended (as little endian) to the data, the final result in the checksum register will be zero. See the description of CRCCHKSUM to read out different versions of the checksum. Bit 0 – CRCBUSY CRC Module Busy This flag is cleared by writing a one to it when used with I/O interface. When used with a DMA channel, the bit is set when the corresponding DMA channel is enabled, and cleared when the corresponding DMA channel is disabled. This register bit cannot be cleared by the application when the CRC is used with a DMA channel. This bit is set when a source configuration is selected and as long as the source is using the CRC module. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 398

25.8.6 Debug Control

Name: DBGCTRL Offset: 0x0D Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Debug Run This bit is not reset by a software reset. This bit controls the functionality when the CPU is halted by an external debugger. Value Description 0 The DMAC is halted when the CPU is halted by an external debugger. 1 The DMAC continues normal operation when the CPU is halted by an external debugger. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 399

25.8.7 Quality of Service Control

Name: QOSCTRL Offset: 0x0E Reset: 0x2A Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DQOS[1:0] FQOS[1:0] WRBQOS[1:0] Access R/W R/W R/W R/W R/W R/W Reset 1 0 1 0 1 0 Bits 5:4 – DQOS[1:0] Data Transfer Quality of Service These bits define the memory priority access during the data transfer operation. DQOS[1:0] Name Description 0x0 DISABLE Background (no sensitive operation) 0x1 LOW Sensitive Bandwidth 0x2 MEDIUM Sensitive Latency 0x3 HIGH Critical Latency Bits 3:2 – FQOS[1:0] Fetch Quality of Service These bits define the memory priority access during the fetch operation. FQOS[1:0] Name Description 0x0 DISABLE Background (no sensitive operation) 0x1 LOW Sensitive Bandwidth 0x2 MEDIUM Sensitive Latency 0x3 HIGH Critical Latency Bits 1:0 – WRBQOS[1:0] Write-Back Quality of Service These bits define the memory priority access during the write-back operation. WRBQOS[1:0] Name Description 0x0 DISABLE Background (no sensitive operation) 0x1 LOW Sensitive Bandwidth 0x2 MEDIUM Sensitive Latency 0x3 HIGH Critical Latency Related Links SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 400

25.8.8 Software Trigger Control

Name: SWTRIGCTRL Offset: 0x10 Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 SWTRIGn[11:8] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SWTRIGn[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 11:0 – SWTRIGn[11:0] Channel n Software Trigger [n = 11..0] This bit is cleared when the Channel Pending bit in the Channel Status register (CHSTATUS.PEND) for the corresponding channel is either set, or by writing a '1' to it. This bit is set if CHSTATUS.PEND is already '1' when writing a '1' to that bit. Writing a '0' to this bit will clear the bit. Writing a '1' to this bit will generate a DMA software trigger on channel x, if CHSTATUS.PEND=0 for channel x. CHSTATUS.PEND will be set and SWTRIGn will remain cleared. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 401

25.8.9 Priority Control 0

Name: PRICTRL0 Offset: 0x14 Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 RRLVLEN3 LVLPRI3[3:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 RRLVLEN2 LVLPRI2[3:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 RRLVLEN1 LVLPRI1[3:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RRLVLEN0 LVLPRI0[3:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 31 – RRLVLEN3 Level 3 Round-Robin Arbitration Enable This bit controls which arbitration scheme is selected for DMA channels with priority level 3. For details on arbitration schemes, refer to 25.6.2.4 Arbitration. Value Description 0 Static arbitration scheme for channels with level 3 priority. 1 Round-robin arbitration scheme for channels with level 3 priority. Bits 27:24 – LVLPRI3[3:0] Level 3 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN3=1) for priority level 3, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 3. When static arbitration is enabled (PRICTRL0.RRLVLEN3=0) for priority level 3, and the value of this bit group is non-zero, it will not affect the static priority scheme. This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN3 written to '0'). Bit 23 – RRLVLEN2 Level 2 Round-Robin Arbitration Enable This bit controls which arbitration scheme is selected for DMA channels with priority level 2. For details on arbitration schemes, refer to 25.6.2.4 Arbitration. Value Description 0 Static arbitration scheme for channels with level 2 priority. 1 Round-robin arbitration scheme for channels with level 2 priority. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 402

Bits 19:16 – LVLPRI2[3:0] Level 2 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN2=1) for priority level 2, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 2. When static arbitration is enabled (PRICTRL0.RRLVLEN2=0) for priority level 2, and the value of this bit group is non-zero, it will not affect the static priority scheme. This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN2 written to '0'). Bit 15 – RRLVLEN1 Level 1 Round-Robin Scheduling Enable For details on arbitration schemes, refer to 25.6.2.4 Arbitration. Value Description 0 Static arbitration scheme for channels with level 1 priority. 1 Round-robin arbitration scheme for channels with level 1 priority. Bits 11:8 – LVLPRI1[3:0] Level 1 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN1=1) for priority level 1, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 1. When static arbitration is enabled (PRICTRL0.RRLVLEN1=0) for priority level 1, and the value of this bit group is non-zero, it will not affect the static priority scheme. This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN1 written to '0'). Bit 7 – RRLVLEN0 Level 0 Round-Robin Scheduling Enable For details on arbitration schemes, refer to 25.6.2.4 Arbitration. Value Description 0 Static arbitration scheme for channels with level 0 priority. 1 Round-robin arbitration scheme for channels with level 0 priority. Bits 3:0 – LVLPRI0[3:0] Level 0 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN0=1) for priority level 0, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 0. When static arbitration is enabled (PRICTRL0.RRLVLEN0=0) for priority level 0, and the value of this bit group is non-zero, it will not affect the static priority scheme. This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN0 written to '0'). SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 403

25.8.10 Interrupt Pending

Name: INTPEND Offset: 0x20 Reset: 0x0000 Property: - This register allows the user to identify the lowest DMA channel with pending interrupt. Bit 15 14 13 12 11 10 9 8 PEND BUSY FERR SUSP TCMPL TERR Access R R R R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ID[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 – PEND Pending This bit will read '1' when the channel selected by Channel ID field (ID) is pending. Bit 14 – BUSY Busy This bit will read '1' when the channel selected by Channel ID field (ID) is busy. Bit 13 – FERR Fetch Error This bit will read '1' when the channel selected by Channel ID field (ID) fetched an invalid descriptor. Bit 10 – SUSP Channel Suspend This bit will read '1' when the channel selected by Channel ID field (ID) has pending Suspend interrupt. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel ID (ID) Suspend interrupt flag. Bit 9 – TCMPL Transfer Complete This bit will read '1' when the channel selected by Channel ID field (ID) has pending Transfer Complete interrupt. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel ID (ID) Transfer Complete interrupt flag. Bit 8 – TERR Transfer Error This bit is read one when the channel selected by Channel ID field (ID) has pending Transfer Error interrupt. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel ID (ID) Transfer Error interrupt flag. Bits 3:0 – ID[3:0] Channel ID These bits store the lowest channel number with pending interrupts. The number is valid if Suspend (SUSP), Transfer Complete (TCMPL) or Transfer Error (TERR) bits are set. The Channel ID field is refreshed when a new channel (with channel number less than the current one) with pending interrupts is SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 404

detected, or when the application clears the corresponding channel interrupt sources. When no pending channels interrupts are available, these bits will always return zero value when read. When the bits are written, indirect access to the corresponding Channel Interrupt Flag register is enabled. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 405

25.8.11 Interrupt Status

Name: INTSTATUS Offset: 0x24 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 CHINTn[11:8] Access R R R R Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CHINTn[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 11:0 – CHINTn[11:0] Channel n Pending Interrupt [n=11..0] This bit is set when Channel n has a pending interrupt/the interrupt request is received. This bit is cleared when the corresponding Channel n interrupts are disabled or the interrupts sources are cleared. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 406

25.8.12 Busy Channels

Name: BUSYCH Offset: 0x28 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 BUSYCHn[11:8] Access R R R R Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BUSYCHn[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 11:0 – BUSYCHn[11:0] Busy Channel n [x=11..0] This bit is cleared when the channel trigger action for DMA channel n is complete, when a bus error for DMA channel n is detected, or when DMA channel n is disabled. This bit is set when DMA channel n starts a DMA transfer. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 407

25.8.13 Pending Channels

Name: PENDCH Offset: 0x2C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 PENDCH11 PENDCH10 PENDCH9 PENDCH8 Access R R R R Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PENDCH7 PENDCH6 PENDCH5 PENDCH4 PENDCH3 PENDCH2 PENDCH1 PENDCH0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – PENDCH Pending Channel n [n=11..0] This bit is cleared when trigger execution defined by channel trigger action settings for DMA channel n is started, when a bus error for DMA channel n is detected or when DMA channel n is disabled. For details on trigger action settings, refer to CHCTRLB.TRIGACT. This bit is set when a transfer is pending on DMA channel n. Related Links SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 408

25.8.14 Active Channel and Levels

Name: ACTIVE Offset: 0x30 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 BTCNT[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 BTCNT[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ABUSY ID[4:0] Access R R R R R R Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LVLEXx LVLEXx LVLEXx LVLEXx Access R R R R Reset 0 0 0 0 Bits 31:16 – BTCNT[15:0] Active Channel Block Transfer Count These bits hold the 16-bit block transfer count of the ongoing transfer. This value is stored in the active channel and written back in the corresponding Write-Back channel memory location when the arbiter grants a new channel access. The value is valid only when the active channel active busy flag (ABUSY) is set. Bit 15 – ABUSY Active Channel Busy This bit is cleared when the active transfer count is written back in the write-back memory section. This bit is set when the next descriptor transfer count is read from the write-back memory section. Bits 12:8 – ID[4:0] Active Channel ID These bits hold the channel index currently stored in the active channel registers. The value is updated each time the arbiter grants a new channel transfer access request. Bits 3,2,1,0 – LVLEXx Level x Channel Trigger Request Executing [x=3..0] This bit is set when a level-x channel trigger request is executing or pending. This bit is cleared when no request is pending or being executed. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 409

25.8.15 Descriptor Memory Section Base Address

Name: BASEADDR Offset: 0x34 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 Access Reset SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 410

25.8.16 Write-Back Memory Section Base Address

Name: WRBADDR Offset: 0x38 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 Access Reset SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 411

25.8.17 Channel ID

Name: CHID Offset: 0x3F Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 ID[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 3:0 – ID[3:0] Channel ID These bits define the channel number that will be affected by the channel registers (CH*). Before reading or writing a channel register, the channel ID bit group must be written first. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 412

25.8.18 Channel Control A

Name: CHCTRLA Offset: 0x40 Reset: 0x00 Property: PAC Write-Protection, Enable-Protected This register affects the DMA channel that is selected in the Channel ID register (CHID.ID). Bit 7 6 5 4 3 2 1 0 RUNSTDBY ENABLE SWRST Access R R/W R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 6 – RUNSTDBY Channel run in standby This bit is used to keep the DMAC channel running in standby mode. This bit is not enable-protected. Value Description 0 The DMAC channel is halted in standby. 1 The DMAC channel continues to run in standby. Bit 1 – ENABLE Channel Enable Writing a '0' to this bit during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst transfer is completed. Writing a '1' to this bit will enable the DMA channel. This bit is not enable-protected. Value Description 0 DMA channel is disabled. 1 DMA channel is enabled. Bit 0 – SWRST Channel Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets the channel registers to their initial state. The bit can be set when the channel is disabled (ENABLE=0). Writing a '1' to this bit will be ignored as long as ENABLE=1. This bit is automatically cleared when the reset is completed. Value Description 0 There is no reset operation ongoing. 1 The reset operation is ongoing. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 413

25.8.19 Channel Control B

Name: CHCTRLB Offset: 0x44 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected This register affects the DMA channel that is selected in the Channel ID register (CHID.ID). Bit 31 30 29 28 27 26 25 24 CMD[1:0] Access R/W R/W Reset 0 0 Bit 23 22 21 20 19 18 17 16 TRIGACT[1:0] Access R/W R/W Reset 0 0 Bit 15 14 13 12 11 10 9 8 TRIGSRC[5:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LVL[1:0] EVOE EVIE EVACT[2:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bits 25:24 – CMD[1:0] Software Command Resume and Next Suspend Skip. These bits are not enable-protected. CMD[1:0] Name Description 0x0 NOACT No action 0x1 SUSPEND Channel suspend operation 0x2 RESUME Channel resume operation 0x3 - Reserved Bits 23:22 – TRIGACT[1:0] Trigger Action These bits define the trigger action used for a transfer. TRIGACT[1:0] Name Description 0x0 BLOCK One trigger required for each block transfer 0x1 - Reserved SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 414

TRIGACT[1:0] Name Description 0x2 BEAT One trigger required for each beat transfer 0x3 TRANSACTION One trigger required for each transaction Bits 13:8 – TRIGSRC[5:0] Trigger Source These bits define the peripheral trigger which is source of the transfer. For details on trigger selection and trigger modes, refer to Transfer Triggers and Actions and CHCTRLB.TRIGACT. Table 25-2. Peripheral Trigger Source Value Name Description 0x00 DISABLE Only software/event triggers 0x01 TSENS TSENS Result Ready Trigger 0x02 SERCOM0 RX SERCOM0 RX Trigger 0x03 SERCOM0 TX SERCOM0TX Trigger 0x04 SERCOM1 RX SERCOM1 RX Trigger 0x05 SERCOM1 TX SERCOM1 TX Trigger 0x06 SERCOM2 RX SERCOM2 RX Trigger 0x07 SERCOM2 TX SERCOM2 TX Trigger 0x08 SERCOM3 RX SERCOM3 RX Trigger 0x09 SERCOM3 TX SERCOM3 TX Trigger 0x0A SERCOM4 RX- SERCOM4 RX TriggerReserved 0x0B SERCOM4 TX- SERCOM4 TX TriggerReserved 0x0C SERCOM5 RX- SERCOM5 RX TriggerReserved 0x0D SERCOM5 TX- SERCOM5 TX TriggerReserved 0x0E CAN0 DEBUG- CAN0 Debug TriggerReserved 0x0F CAN1 DEBUG- CAN1 Debug TriggerReserved 0x10 TCC0 OVF TCC0 Overflow Trigger 0x11 TCC0 MC0 TCC0 Match/Compare 0 Trigger 0x12 TCC0 MC1 TCC0 Match/Compare 1 Trigger 0x13 TCC0 MC2 TCC0 Match/Compare 2 Trigger 0x14 TCC0 MC3 TCC0 Match/Compare 3 Trigger 0x15 TCC1 OVF TCC1 Overflow Trigger 0x16 TCC1 MC0 TCC1 Match/Compare 0 Trigger 0x17 TCC1 MC1 TCC1 Match/Compare 1 Trigger SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 415

0x18 TCC2 OVF TCC2 Overflow Trigger 0x19 TCC2 MC0 TCC2 Match/Compare 0 Trigger 0x1A TCC2 MC1 TCC2 Match/Compare 1 Trigger 0x1B TC0 OVF TC0 Overflow Trigger 0x1C TC0 MC0 TC0 Match/Compare 0 Trigger 0x1D TC0 MC1 TC0 Match/Compare 1 Trigger 0x1E TC1 OVF TC1 Overflow Trigger 0x1F TC1 MC0 TC1 Match/Compare 0 Trigger 0x20 TC1 MC1 TC1 Match/Compare 1 Trigger 0x21 TC2 OVF TC2 Overflow Trigger 0x22 TC2 MC0 TC2 Match/Compare 0 Trigger 0x23 TC2 MC1 TC2 Match/Compare 1 Trigger 0x24 TC3 OVF TC3 Overflow Trigger 0x25 TC3 MC0 TC3 Match/Compare 0 Trigger 0x26 TC3 MC1 TC3 Match/Compare 1 Trigger 0x27 TC4 OVF TC4 Overflow Trigger 0x28 TC4 MC0 TC4 Match/Compare 0 Trigger 0x29 TC4 MC1 TC4 Match/Compare 1 Trigger 0x2A ADC0 RESRDY ADC0 Result Ready Trigger 0x2B ADC1 RESRDY ADC1 Result Ready Trigger 0x2C SDADC RESRDY SDADC Result Ready Trigger 0x2D DAC EMPTY DAC Empty Trigger 0x2E PTC EOC PTC End of Conversion Trigger 0x2F PTC WCOMP PTC Window Compare Trigger 0x30 PTC SEQ PTC Sequence Trigger 0x31 SERCOM6 RX SERCOM6 RX Trigger 0x32 SERCOM6 TX SERCOM6 TX Trigger 0x33 SERCOM7 RX SERCOM6 RX Trigger 0x34 SERCOM7 TX SERCOM6 TX Trigger 0x35 TC5 OVF TC5 Overflow Trigger 0x36 TC5 MC0 TC5 Match/Compare 0 Trigger SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 416

0x37 TC5 MC1 TC5 Match/Compare 1 Trigger 0x38 TC6 OVF TC6 Overflow Trigger 0x39 TC6 MC0 TC6 Match/Compare 0 Trigger 0x3A TC6 MC1 TC6 Match/Compare 1 Trigger 0x3B TC7 OVF TC7 Overflow Trigger 0x3C TC7 MC0 TC7 Match/Compare 0 Trigger 0x3D TC7MC1 TC7 Match/Compare 1 Trigger Bits 6:5 – LVL[1:0] Channel Arbitration Level These bits define the arbitration level used for the DMA channel, where a high level has priority over a low level. For further details on arbitration schemes, refer to 25.6.2.4 Arbitration. These bits are not enable-protected. TRIGACT[1:0] Name Description 0x0 LVL0 Channel Priority Level 0 0x1 LVL1 Channel Priority Level 1 0x2 LVL2 Channel Priority Level 2 0x3 LVL3 Channel Priority Level 3 Bit 4 – EVOE Channel Event Output Enable This bit indicates if the Channel event generation is enabled. The event will be generated for every condition defined in the descriptor Event Output Selection ( BTCTRL.EVOSEL). This bit is available only for the least significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details. Value Description 0 Channel event generation is disabled. 1 Channel event generation is enabled. Bit 3 – EVIE Channel Event Input Enable This bit is available only for the least significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details. Value Description 0 Channel event action will not be executed on any incoming event. 1 Channel event action will be executed on any incoming event. Bits 2:0 – EVACT[2:0] Event Input Action These bits define the event input action, as shown below. The action is executed only if the corresponding EVIE bit in CHCTRLB register of the channel is set. These bits are available only for the least significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 417

EVACT[2:0] Name Description 0x0 NOACT No action 0x1 TRIG Normal Transfer and Conditional Transfer on Strobe trigger 0x2 CTRIG Conditional transfer trigger 0x3 CBLOCK Conditional block transfer 0x4 SUSPEND Channel suspend operation 0x5 RESUME Channel resume operation 0x6 SSKIP Skip next block suspend action 0x7 - Reserved Related Links

29.8.7 CHANNELn

29.7.3 USERm

25.8.20 Channel Interrupt Enable Clear

Name: CHINTENCLR Offset: 0x4C Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Channel Interrupt Enable Set (CHINTENSET) register. This register affects the DMA channel that is selected in the Channel ID register (CHID.ID). Bit 7 6 5 4 3 2 1 0 SUSP TCMPL TERR Access R/W R/W R/W Reset 0 0 0 Bit 2 – SUSP Channel Suspend Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel Suspend Interrupt Enable bit, which disables the Channel Suspend interrupt. Value Description 0 The Channel Suspend interrupt is disabled. 1 The Channel Suspend interrupt is enabled. Bit 1 – TCMPL Channel Transfer Complete Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel Transfer Complete Interrupt Enable bit, which disables the Channel Transfer Complete interrupt. Value Description 0 The Channel Transfer Complete interrupt is disabled. When block action is set to none, the TCMPL flag will not be set when a block transfer is completed. 1 The Channel Transfer Complete interrupt is enabled. Bit 0 – TERR Channel Transfer Error Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel Transfer Error Interrupt Enable bit, which disables the Channel Transfer Error interrupt. Value Description 0 The Channel Transfer Error interrupt is disabled. 1 The Channel Transfer Error interrupt is enabled. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 419

25.8.21 Channel Interrupt Enable Set

Name: CHINTENSET Offset: 0x4D Reset: 0x00 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Channel Interrupt Enable Clear (CHINTENCLR) register. This register affects the DMA channel that is selected in the Channel ID register (CHID.ID). Bit 7 6 5 4 3 2 1 0 SUSP TCMPL TERR Access R/W R/W R/W Reset 0 0 0 Bit 2 – SUSP Channel Suspend Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Channel Suspend Interrupt Enable bit, which enables the Channel Suspend interrupt. Value Description 0 The Channel Suspend interrupt is disabled. 1 The Channel Suspend interrupt is enabled. Bit 1 – TCMPL Channel Transfer Complete Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Channel Transfer Complete Interrupt Enable bit, which enables the Channel Transfer Complete interrupt. Value Description 0 The Channel Transfer Complete interrupt is disabled. 1 The Channel Transfer Complete interrupt is enabled. Bit 0 – TERR Channel Transfer Error Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Channel Transfer Error Interrupt Enable bit, which enables the Channel Transfer Error interrupt. Value Description 0 The Channel Transfer Error interrupt is disabled. 1 The Channel Transfer Error interrupt is enabled. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 420

25.8.22 Channel Interrupt Flag Status and Clear

Name: CHINTFLAG Offset: 0x4E Reset: 0x00 Property: - This register affects the DMA channel that is selected in the Channel ID register (CHID.ID). Bit 7 6 5 4 3 2 1 0 SUSP TCMPL TERR Access R/W R/W R/W Reset 0 0 0 Bit 2 – SUSP Channel Suspend This flag is cleared by writing a '1' to it. This flag is set when a block transfer with suspend block action is completed, when a software suspend command is executed, when a suspend event is received or when an invalid descriptor is fetched by the DMA. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel Suspend interrupt flag for the corresponding channel. For details on available software commands, refer to CHCTRLB.CMD. For details on available event input actions, refer to CHCTRLB.EVACT. For details on available block actions, refer to BTCTRL.BLOCKACT. Bit 1 – TCMPL Channel Transfer Complete This flag is cleared by writing a '1' to it. This flag is set when a block transfer is completed and the corresponding interrupt block action is enabled. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Transfer Complete interrupt flag for the corresponding channel. Bit 0 – TERR Channel Transfer Error This flag is cleared by writing a '1' to it. This flag is set when a bus error is detected during a beat transfer or when the DMAC fetches an invalid descriptor. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Transfer Error interrupt flag for the corresponding channel. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 421

25.8.23 Channel Status

Name: CHSTATUS Offset: 0x4F Reset: 0x00 Property: - This register affects the DMA channel that is selected in the Channel ID register (CHID.ID). Bit 7 6 5 4 3 2 1 0 FERR BUSY PEND Access R R R Reset 0 0 0 Bit 2 – FERR Channel Fetch Error This bit is cleared when a software resume command is executed. This bit is set when an invalid descriptor is fetched. Bit 1 – BUSY Channel Busy This bit is cleared when the channel trigger action is completed, when a bus error is detected or when the channel is disabled. This bit is set when the DMA channel starts a DMA transfer. Bit 0 – PEND Channel Pending This bit is cleared when the channel trigger action is started, when a bus error is detected or when the channel is disabled. For details on trigger action settings, refer to CHCTRLB.TRIGACT. This bit is set when a transfer is pending on the DMA channel, as soon as the transfer request is received. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 422

25.9 Register Summary - SRAM

Offset Name Bit Pos. 0x00 BTCTRL 7:0 BLOCKACT[1:0] EVOSEL[1:0] VALID 15:8 STEPSIZE[2:0] STEPSEL DSTINC SRCINC BEATSIZE[1:0] 0x02 BTCNT 7:0 BTCNT[7:0] 15:8 BTCNT[15:8] 0x04 SRCADDR 7:0 SRCADDR[7:0] 15:8 SRCADDR[15:8] 23:16 SRCADDR[23:16] 31:24 SRCADDR[31:24] 0x08 DSTADDR 7:0 DSTADDR[7:0] 15:8 DSTADDR[15:8] 23:16 DSTADDR[23:16] 31:24 DSTADDR[31:24] 0x0C DESCADDR 7:0 DESCADDR[7:0] 15:8 DESCADDR[15:8] 23:16 DESCADDR[23:16] 31:24 DESCADDR[31:24]

25.10 Register Description - SRAM

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 25.5.8 Register Access Protection. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 423

25.10.1 Block Transfer Control

Name: BTCTRL Offset: 0x00 Property: - The BTCTRL register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 15 14 13 12 11 10 9 8 STEPSIZE[2:0] STEPSEL DSTINC SRCINC BEATSIZE[1:0] Access Reset Bit 7 6 5 4 3 2 1 0 BLOCKACT[1:0] EVOSEL[1:0] VALID Access Reset Bits 15:13 – STEPSIZE[2:0] Address Increment Step Size These bits select the address increment step size. The setting apply to source or destination address, depending on STEPSEL setting. Value Name Description 0x0 X1 Next ADDR = ADDR + (Beat size in byte) * 1 0x1 X2 Next ADDR = ADDR + (Beat size in byte) * 2 0x2 X4 Next ADDR = ADDR + (Beat size in byte) * 4 0x3 X8 Next ADDR = ADDR + (Beat size in byte) * 8 0x4 X16 Next ADDR = ADDR + (Beat size in byte) * 16 0x5 X32 Next ADDR = ADDR + (Beat size in byte) * 32 0x6 X64 Next ADDR = ADDR + (Beat size in byte) * 64 0x7 X128 Next ADDR = ADDR + (Beat size in byte) * 128 Bit 12 – STEPSEL Step Selection This bit selects if source or destination addresses are using the step size settings. Value Name Description 0x0 DST Step size settings apply to the destination address 0x1 SRC Step size settings apply to the source address Bit 11 – DSTINC Destination Address Increment Enable Writing a '0' to this bit will disable the destination address incrementation. The address will be kept fixed during the data transfer. Writing a '1' to this bit will enable the destination address incrementation. By default, the destination address is incremented by 1. If the STEPSEL bit is cleared, flexible step-size settings are available in the STEPSIZE register. Value Description 0 The Destination Address Increment is disabled. 1 The Destination Address Increment is enabled. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 424

Bit 10 – SRCINC Source Address Increment Enable Writing a '0' to this bit will disable the source address incrementation. The address will be kept fixed during the data transfer. Writing a '1' to this bit will enable the source address incrementation. By default, the source address is incremented by 1. If the STEPSEL bit is set, flexible step-size settings are available in the STEPSIZE register. Value Description 0 The Source Address Increment is disabled. 1 The Source Address Increment is enabled. Bits 9:8 – BEATSIZE[1:0] Beat Size These bits define the size of one beat. A beat is the size of one data transfer bus access, and the setting apply to both read and write accesses. Value Name Description 0x0 BYTE 8-bit bus transfer 0x1 HWORD 16-bit bus transfer 0x2 WORD 32-bit bus transfer other Reserved Bits 4:3 – BLOCKACT[1:0] Block Action These bits define what actions the DMAC should take after a block transfer has completed. BLOCKACT[1:0] Name Description 0x0 NOACT Channel will be disabled if it is the last block transfer in the transaction 0x1 INT Channel will be disabled if it is the last block transfer in the transaction and block interrupt 0x2 SUSPEND Channel suspend operation is completed 0x3 BOTH Both channel suspend operation and block interrupt Bits 2:1 – EVOSEL[1:0] Event Output Selection These bits define the event output selection. EVOSEL[1:0] Name Description 0x0 DISABLE Event generation disabled 0x1 BLOCK Event strobe when block transfer complete 0x2 Reserved 0x3 BEAT Event strobe when beat transfer complete Bit 0 – VALID Descriptor Valid Writing a '0' to this bit in the Descriptor or Write-Back memory will suspend the DMA channel operation when fetching the corresponding descriptor. The bit is automatically cleared in the Write-Back memory section when channel is aborted, when an error is detected during the block transfer, or when the block transfer is completed. Value Description 0 The descriptor is not valid. 1 The descriptor is valid. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 425

25.10.2 Block Transfer Count

Name: BTCNT Offset: 0x02 Property: - The BTCNT register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 15 14 13 12 11 10 9 8 BTCNT[15:8] Access Reset Bit 7 6 5 4 3 2 1 0 BTCNT[7:0] Access Reset Bits 15:0 – BTCNT[15:0] Block Transfer Count This bit group holds the 16-bit block transfer count. During a transfer, the internal counter value is decremented by one after each beat transfer. The internal counter is written to the corresponding write-back memory section for the DMA channel when the DMA channel loses priority, is suspended or gets disabled. The DMA channel can be disabled by a complete transfer, a transfer error or by software. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 426

25.10.3 Block Transfer Source Address

Name: SRCADDR Offset: 0x04 Property: - The SRCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 31 30 29 28 27 26 25 24 SRCADDR[31:24] Access Reset Bit 23 22 21 20 19 18 17 16 SRCADDR[23:16] Access Reset Bit 15 14 13 12 11 10 9 8 SRCADDR[15:8] Access Reset Bit 7 6 5 4 3 2 1 0 SRCADDR[7:0] Access Reset Bits 31:0 – SRCADDR[31:0] Transfer Source Address This bit group holds the source address corresponding to the last beat transfer address in the block transfer. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 427

25.10.4 Block Transfer Destination Address

Name: DSTADDR Offset: 0x08 Property: - The DSTADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 31 30 29 28 27 26 25 24 DSTADDR[31:24] Access Reset Bit 23 22 21 20 19 18 17 16 DSTADDR[23:16] Access Reset Bit 15 14 13 12 11 10 9 8 DSTADDR[15:8] Access Reset Bit 7 6 5 4 3 2 1 0 DSTADDR[7:0] Access Reset Bits 31:0 – DSTADDR[31:0] Transfer Destination Address This bit group holds the destination address corresponding to the last beat transfer address in the block transfer. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 428

25.10.5 Next Descriptor Address

Name: DESCADDR Offset: 0x0C Property: - The DESCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 31 30 29 28 27 26 25 24 DESCADDR[31:24] Access Reset Bit 23 22 21 20 19 18 17 16 DESCADDR[23:16] Access Reset Bit 15 14 13 12 11 10 9 8 DESCADDR[15:8] Access Reset Bit 7 6 5 4 3 2 1 0 DESCADDR[7:0] Access Reset Bits 31:0 – DESCADDR[31:0] Next Descriptor Address This bit group holds the SRAM address of the next descriptor. The value must be 128-bit aligned. If the value of this SRAM register is 0x00000000, the transaction will be terminated when the DMAC tries to load the next transfer descriptor. SAM C20/C21 Family Data Sheet DMAC – Direct Memory Access Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 429

EIC – External Interrupt Controller

26.1 Overview

The External Interrupt Controller (EIC) allows external pins to be configured as interrupt lines. Each interrupt line can be individually masked and can generate an interrupt on rising, falling, or both edges, or on high or low levels. Each external pin has a configurable filter to remove spikes. Each external pin can also be configured to be asynchronous in order to wake up the device from sleep modes where all clocks have been disabled. External pins can also generate an event. A separate non-maskable interrupt (NMI) is also supported. It has properties similar to the other external interrupts, but is connected to the NMI request of the CPU, enabling it to interrupt any other interrupt mode.

26.2 Features

Up to 16 external pins (EXTINTx), plus one non-maskable pin (NMI)
Dedicated, individually maskable interrupt for each pin
Interrupt on rising, falling, or both edges
Synchronous or asynchronous edge detection mode
Interrupt pin debouncing
Interrupt on high or low levels
Asynchronous interrupts for sleep modes without clock
Filtering of external pins
Event generation from EXTINTx

26.3 Block Diagram

Figure 26-1. EIC Block Diagram Filter Edge/Level Detection Interrupt Wake Event FILTENx EXTINTx intreq_extint inwake_extint evt_extint Filter Edge/Level Detection Interrupt Wake NMIFILTEN NMISENSE[2:0] NMI intreq_nmi inwake_nmi SENSEx[2:0] SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 430

26.4 Signal Description

Signal Name Type Description EXTINT[15..0] Digital Input External interrupt pin NMI Digital Input Non-maskable interrupt pin One signal may be available on several pins. Related Links 6. I/O Multiplexing and Considerations

26.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

26.5.1 I/O Lines

Using the EIC’s I/O lines requires the I/O pins to be configured. Related Links 28. PORT - I/O Pin Controller

26.5.2 Power Management

All interrupts are available down to STANDBY sleep mode, but the EIC can be configured to automatically mask some interrupts in order to prevent device wake-up. The EIC will continue to operate in any sleep mode where the selected source clock is running. The EIC’s interrupts can be used to wake up the device from sleep modes. Events connected to the Event System can trigger other operations in the system without exiting sleep modes. Related Links 19. PM – Power Manager

26.5.3 Clocks

The EIC bus clock (CLK_EIC_APB) can be enabled and disabled by the Main Clock Controller, the default state of CLK_EIC_APB can be found in the Peripheral Clock Masking section. Some optional functions need a peripheral clock, which can either be a generic clock (GCLK_EIC, for wider frequency selection) or a Ultra Low Power 32KHz clock (CLK_ULP32K, for highest power efficiency). One of the clock sources must be configured and enabled before using the peripheral: GCLK_EIC is configured and enabled in the Generic Clock Controller. CLK_ULP32K is provided by the internal ultra-low-power (OSCULP32K) oscillator in the OSC32KCTRL module. Both GCLK_EIC and CLK_ULP32K are asynchronous to the user interface clock (CLK_EIC_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to Synchronization for further details. Related Links 17. MCLK – Main Clock SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 431

GCLK - Generic Clock Controller 21. OSC32KCTRL – 32KHz Oscillators Controller

26.5.4 DMA

Not applicable.

26.5.5 Interrupts

There are several interrupt request lines, at least one for the external interrupts (EXTINT) and one for non-maskable interrupt (NMI). The EXTINT interrupt request line is connected to the interrupt controller. Using the EIC interrupt requires the interrupt controller to be configured first. The NMI interrupt request line is also connected to the interrupt controller, but does not require the interrupt to be configured. Related Links

26.5.6 Events

The events are connected to the Event System. Using the events requires the Event System to be configured first. Related Links 29. EVSYS – Event System

26.5.7 Debug Operation

When the CPU is halted in debug mode, the EIC continues normal operation. If the EIC is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging.

26.5.8 Register Access Protection

All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Interrupt Flag Status and Clear register (INTFLAG)
Non-Maskable Interrupt Flag Status and Clear register (NMIFLAG) Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write- Protection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger. Related Links 11. PAC - Peripheral Access Controller

26.5.9 Analog Connections

26.6 Functional Description

26.6.1 Principle of Operation

The EIC detects edge or level condition to generate interrupts to the CPU interrupt controller or events to the Event System. Each external interrupt pin (EXTINT) can be filtered using majority vote filtering, clocked by GCLK_EIC or by CLK_ULP32K. Related Links

26.6.3 External Pin Processing

26.6.2 Basic Operation

26.6.2.1 Initialization

The EIC must be initialized in the following order: 1. Enable CLK_EIC_APB 2. If required, configure the NMI by writing the Non-Maskable Interrupt Control register (NMICTRL) 3. Enable GCLK_EIC or CLK_ULP32K when one of the following configuration is selected: – the NMI uses edge detection or filtering. – one EXTINT uses filtering. – one EXTINT uses synchronous edge detection. – one EXTINT uses debouncing. GCLK_EIC is used when a frequency higher than 32KHz is required for filtering. CLK_ULP32K is recommended when power consumption is the priority. For CLK_ULP32K write a '1' to the Clock Selection bit in the Control A register (CTRLA.CKSEL). 4. Configure the EIC input sense and filtering by writing the Configuration n register (CONFIG). 5. Optionally, enable the asynchronous mode. 6. Optionally, enable the debouncer mode. 7. Enable the EIC by writing a ‘1’ to CTRLA.ENABLE. The following bits are enable-protected, meaning that it can only be written when the EIC is disabled CTRLA.ENABLE=0):

Clock Selection bit in Control A register ( CTRLA.CKSEL) The following registers are enable-protected:
Event Control register (EVCTRL)
Configuration n register (CONFIG).
External Interrupt Asynchronous Mode register (

26.8.9 ASYNCH)

Debouncer Enable register ( 26.8.11 DEBOUNCEN)
Debounce Prescaler register ( 26.8.12 DPRESCALER) Enable-protected bits in the CTRLA register can be written at the same time when setting CTRLA.ENABLE to '1', but not at the same time as CTRLA.ENABLE is being cleared. Enable-protection is denoted by the "Enable-Protected" property in the register description. Related Links

26.8.10 CONFIG

26.6.2.2 Enabling, Disabling, and Resetting

The EIC is enabled by writing a '1' the Enable bit in the Control A register (CTRLA.ENABLE). The EIC is disabled by writing CTRLA.ENABLE to '0'. The EIC is reset by setting the Software Reset bit in the Control register (CTRLA.SWRST). All registers in the EIC will be reset to their initial state, and the EIC will be disabled. Refer to the CTRLA register description for details. Each external pin can be configured to generate an interrupt/event on edge detection (rising, falling or both edges) or level detection (high or low). The sense of external interrupt pins is configured by writing the Input Sense x bits in the Config n register (CONFIG.SENSEx). The corresponding interrupt flag (INTFLAG.EXTINT[x]) in the Interrupt Flag Status and Clear register (

26.8.8 INTFLAG) is set when the

interrupt condition is met. When the interrupt flag has been cleared in edge-sensitive mode, INTFLAG.EXTINT[x] will only be set if a new interrupt condition is met. In level-sensitive mode, when interrupt has been cleared, INTFLAG.EXTINT[x] will be set immediately if the EXTINTx pin still matches the interrupt condition. Each external pin can be filtered by a majority vote filtering, clocked by GCLK_EIC or CLK_ULP32K. Filtering is enabled if bit Filter Enable x in the Configuration n register (CONFIG.FILTENx) is written to '1'. The majority vote filter samples the external pin three times with GCLK_EIC or CLK_ULP32K and outputs the value when two or more samples are equal. Table 26-1. Majority Vote Filter Samples [0, 1, 2] Filter Output [0,0,0] 0 [0,0,1] 0 [0,1,0] 0 [0,1,1] 1 [1,0,0] 0 [1,0,1] 1 [1,1,0] 1 [1,1,1] 1 When an external interrupt is configured for level detection and when filtering is disabled, detection is done asynchronously. Level detection and asynchronous edge detection does not require GCLK_EIC or CLK_ULP32K, but interrupt and events can still be generated. If filtering or synchronous edge detection or debouncing is enabled, the EIC automatically requests GCLK_EIC or CLK_ULP32K to operate. The selection between these two clocks is done by writing the Clock Selection bits in the Control A register ( CTRLA.CKSEL). GCLK_EIC must be enabled in the GCLK module. In these modes the external pin is sampled at the EIC clock rate, thus pulses with duration lower than two EIC clock periods may not be properly detected. SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 434

Figure 26-2. Interrupt Detection Latency by modes (Rising Edge) intreq_extint[x] (edge detection / filter) intreq_extint[x] (edge detection / no filter) intreq_extint[x] (level detection / filter) intreq_extint[x] (level detection / no filter) EXTINTx CLK_EIC_APB GCLK_EIC clear INTFLAG.EXTINT[x] No interrupt No interrupt The detection latency depends on the detection mode. Table 26-2. Detection Latency Detection mode Latency (worst case) Level without filter Five CLK_EIC_APB periods Level with filter Four GCLK_EIC/CLK_ULP32K periods + five CLK_EIC_APB periods Edge without filter Four GCLK_EIC/CLK_ULP32K periods + five CLK_EIC_APB periods Edge with filter Six GCLK_EIC/CLK_ULP32K periods + five CLK_EIC_APB periods Related Links 16. GCLK - Generic Clock Controller

26.6.4 Additional Features

26.6.4.1 Non-Maskable Interrupt (NMI)

The non-maskable interrupt pin can also generate an interrupt on edge or level detection, but it is configured with the dedicated NMI Control register (NMICTRL). To select the sense for NMI, write to the NMISENSE bit group in the NMI Control register (NMICTRL.NMISENSE). NMI filtering is enabled by writing a '1' to the NMI Filter Enable bit (NMICTRL.NMIFILTEN). If edge detection or filtering is required, enable GCLK_EIC or CLK_ULP32K. NMI detection is enabled only by the NMICTRL.NMISENSE value, and the EIC is not required to be enabled. When an NMI is detected, the non-maskable interrupt flag in the NMI Flag Status and Clear register is set (NMIFLAG.NMI). NMI interrupt generation is always enabled, and NMIFLAG.NMI generates an interrupt request when set.

26.6.4.2 Asynchronous Edge Detection Mode (No Debouncing)

The EXTINT edge detection can be operated synchronously or asynchronously, selected by the Asynchronous Control Mode bit for external pin x in the External Interrupt Asynchronous Mode register ASYNCH.ASYNCH[x]). The EIC edge detection is operated synchronously when the Asynchronous Control Mode bit (ASYNCH.ASYNCH[x]) is '0' (default value). It is operated asynchronously when ASYNCH.ASYNCH[x] is written to '1'. SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 435

In Synchronous Edge Detection Mode, the external interrupt (EXTINT) or the non-maskable interrupt (NMI) pins are sampled using the EIC clock as defined by the Clock Selection bit in the Control A register CTRLA.CKSEL). The External Interrupt flag (INTFLAG.EXTINT[x]) or Non-Maskable Interrupt flag (NMIFLAG.NMI) is set when the last sampled state of the pin differs from the previously sampled state. In this mode, the EIC clock is required. The Synchronous Edge Detection Mode can be used in Idle and Standby sleep modes. In Asynchronous Edge Detection Mode, the external interrupt (EXTINT) pins or the non-maskable interrupt (NMI) pins set the External Interrupt flag or Non-Maskable Interrupt flag (INTFLAG.EXTINT[x] or NMIFLAG) directly. In this mode, the EIC clock is not requested. The asynchronous edge detection mode can be used in Idle and Standby sleep modes.

26.6.4.3 Interrupt Pin Debouncing

The external interrupt pin (EXTINT) edge detection can use a debouncer to improve input noise immunity. When selected, the debouncer can work in the synchronous mode or the asynchronous mode, depending on the configuration of the ASYNCH.ASYNCH[x] bit for the pin. The debouncer uses the EIC clock as defined by the bit CTRLA.CKSEL to clock the debouncing circuitry. The debouncing time frame is set with the debouncer prescaler DPRESCALER.DPRESCALERn, which provides the low frequency clock tick that is used to reject higher frequency signals. The debouncing mode for pin EXTINT x can be selected only if the Sense bits in the Configuration y register (CONFIGy.SENSEx) are set to RISE, FALL or BOTH. If the debouncing mode for pin EXTINT x is selected, the filter mode for that pin (CONFIGy.FILTENx) can not be selected. The debouncer manages an internal “valid pin state” that depends on the external interrupt (EXTINT) pin transitions, the debouncing mode and the debouncer prescaler frequency. The valid pin state reflects the pin value after debouncing. The external interrupt pin (EXTINT) is sampled continously on EIC clock. The sampled value is evaluated on each low frequency clock tick to detect a transitional edge when the sampled value is different of the current valid pin state. The sampled value is evaluated on each EIC clock when DPRESCALER.TICKON=0 or on each low frequency clock tick when DPRESCALER.TICKON=1, to detect a bounce when the sampled value is equal to the current valid pin state. Transitional edge detection increments the transition counter of the EXTINT pin, while bounce detection resets the transition counter. The transition counter must exceed the transition count threshold as defined by the DPRESCALER.STATESn bitfield. In the synchronous mode the threshold is 4 when DPRESCALER.STATESn=0 or 8 when DPRESCALER.STATESn=1. In the asynchronous mode the threshold is 4. The valid pin state for the pins can be accessed by reading the register PINSTATE for both synchronous or asynchronous debouncing mode. Synchronous edge detection In this mode the external interrupt (EXTINT) pin is sampled continously on EIC clock. 1. A pin edge transition will be validated when the sampled value is consistently different of the current valid pin state for 4 (or 8 depending on bit DPRESCALER.STATESn) consecutive ticks of the low frequency clock. 2. Any pin sample, at the low frequency clock tick rate, with a value opposite to the current valid pin state will increment the transition counter. 3. Any pin sample, at EIC clock rate (when DPRESCALER.TICKON=0) or the low frequency clock tick (when DPRESCALER.TICKON=1), with a value identical to the current valid pin state will return the transition counter to zero. SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 436

When the transition counter meets the count threshold, the pin edge transition is validated and the pin state PINSTATE.PINSTATE[x] is changed to the detected level. 5. The external interrupt flag (INTFLAG.EXTINT[x]) is set when the pin state PINSTATE.PINSTATE[x] is changed. Figure 26-3. EXTINT Pin Synchronous Debouncing (Rising Edge) CLK_EIC CLK_PRESCALER EXTINTx PIN_STATE INTGLAG TRANSITIONLOW HIGH Set INTFLAG In the synchronous edge detection mode, the EIC clock is required. The synchronous edge detection mode can be used in Idle and Standby sleep modes. Asynchronous edge detection In this mode, the external interrupt (EXTINT) pin directly drives an asynchronous edges detector which triggers any rising or falling edge on the pin: 1. Any edge detected that indicates a transition from the current valid pin state will immediately set the valid pin state PINSTATE.PINSTATE[x] to the detected level. 2. The external interrupt flag (INTFLAG.EXTINT[x] is immediately changed. 3. The edge detector will then be idle until no other rising or falling edge transition is detected during 4 consecutive ticks of the low frequency clock. 4. Any rising or falling edge transition detected during the idle state will return the transition counter to 5. After 4 consecutive ticks of the low frequency clock without bounce detected, the edge detector is ready for a new detection. Figure 26-4. EXTINT Pin Asynchronous Debouncing (Rising Edge) CLK_EIC CLK_PRESCALER EXTINTx PIN_STATE INTGLAG TRANSITIONLOW HIGH Set INTFLAG In this mode, the EIC clock is requested. The asynchronous edge detection mode can be used in Idle and Standby sleep modes.

26.6.5 DMA Operation

Not applicable.

26.6.6 Interrupts

The EIC has the following interrupt sources:

External interrupt pins (EXTINTx). See 26.6.2 Basic Operation.
Non-maskable interrupt pin (NMI). See 26.6.4 Additional Features. SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 437

Each interrupt source has an associated interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when an interrupt condition occurs (NMIFLAG for NMI). Each interrupt, except NMI, can be individually enabled by setting the corresponding bit in the Interrupt Enable Set register (INTENSET=1), and disabled by setting the corresponding bit in the Interrupt Enable Clear register (INTENCLR=1). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the EIC is reset. See the INTFLAG register for details on how to clear interrupt flags. The EIC has one interrupt request line for each external interrupt (EXTINTx) and one line for NMI. The user must read the INTFLAG (or NMIFLAG) register to determine which interrupt condition is present. Note: 1. Interrupts must be globally enabled for interrupt requests to be generated. 2. If an external interrupts (EXTINT) is common on two or more I/O pins, only one will be active (the first one programmed). Related Links 10. Processor and Architecture

26.6.7 Events

The EIC can generate the following output events:

External event from pin (EXTINTx). Setting an Event Output Control register (EVCTRL.EXTINTEO) enables the corresponding output event. Clearing this bit disables the corresponding output event. Refer to Event System for details on configuring the Event System. When the condition on pin EXTINTx matches the configuration in the CONFIGn register, the corresponding event is generated, if enabled. Related Links 29. EVSYS – Event System

26.6.8 Sleep Mode Operation

In sleep modes, an EXTINTx pin can wake up the device if the corresponding condition matches the configuration in the CONFIG register, and the corresponding bit in the Interrupt Enable Set register 26.8.7 INTENSET) is written to '1'. Figure 26-5. Wake-up Operation Example (High-Level Detection, No Filter, Interrupt Enable Set) CLK_EIC_APB EXTINTx intwake_extint[x] intreq_extint[x] clear INTFLAG.EXTINT[x]wake from sleep mode Related Links SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 438

26.6.9 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written:

Software Reset bit in control register ( CTRLA.SWRST)
Enable bit in control register ( CTRLA.ENABLE) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 439

26.7 Register Summary

Offset Name Bit Pos. 0x00 CTRLA 7:0 CKSEL ENABLE SWRST 0x01 NMICTRL 7:0 NMIASYNCH NMIFILTEN NMISENSE[2:0] 0x02 NMIFLAG 7:0 NMI 15:8 0x04 SYNCBUSY 7:0 ENABLE SWRST 15:8 23:16 31:24 0x08 EVCTRL 7:0 EXTINTEO[7:0] 15:8 EXTINTEO[15:8] 23:16 31:24 0x0C INTENCLR 7:0 EXTINT[7:0] 15:8 EXTINT[15:8] 23:16 31:24 0x10 INTENSET 7:0 EXTINT[7:0] 15:8 EXTINT[15:8] 23:16 31:24 0x14 INTFLAG 7:0 EXTINT[7:0] 15:8 EXTINT[15:8] 23:16 31:24 0x18 ASYNCH 7:0 ASYNCH[7:0] 15:8 ASYNCH[15:8] 23:16 31:24 0x1C CONFIG0 7:0 FILTENx SENSEx[2:0] FILTENx SENSEx[2:0] 15:8 FILTENx SENSEx[2:0] FILTENx SENSEx[2:0] 23:16 FILTENx SENSEx[2:0] FILTENx SENSEx[2:0] 31:24 FILTENx SENSEx[2:0] FILTENx SENSEx[2:0] 0x20 CONFIG1 7:0 FILTENx SENSEx[2:0] FILTENx SENSEx[2:0] 15:8 FILTENx SENSEx[2:0] FILTENx SENSEx[2:0] 23:16 FILTENx SENSEx[2:0] FILTENx SENSEx[2:0] 31:24 FILTENx SENSEx[2:0] FILTENx SENSEx[2:0] 0x24 ... 0x2F Reserved 0x30 DEBOUNCEN 7:0 DEBOUNCEN[7:0] 15:8 DEBOUNCEN[15:8] 23:16 31:24 SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 440

Offset Name Bit Pos. 0x34 DPRESCALER 7:0 STATESx PRESCALERx[2:0] STATESx PRESCALERx[2:0] 15:8 23:16 TICKON 31:24 0x38 PINSTATE 7:0 PINSTATE[7:0] 15:8 PINSTATE[15:8] 23:16 31:24

26.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-Synchronized" and/or "Write-Synchronized" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 441

26.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00 Property: PAC Write-Protection, Write-Synchronized Bit 7 6 5 4 3 2 1 0 CKSEL ENABLE SWRST Access RW RW W Reset 0 0 0 Bit 4 – CKSEL Clock Selection The EIC can be clocked either by GCLK_EIC (when a frequency higher than 32KHz is required for filtering) or by CLK_ULP32K (when power consumption is the priority). This bit is not Write-Synchronized. Value Description 0 The EIC is clocked by GCLK_EIC. 1 The EIC is clocked by CLK_ULP32K. Bit 1 – ENABLE Enable Due to synchronization there is a delay between writing to CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register will be set (SYNCBUSY.ENABLE=1). SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not Enable-Protected. This bit is Write-Synchronized. Value Description 0 The EIC is disabled. 1 The EIC is enabled. Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the EIC to their initial state, and the EIC will be disabled. Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the Reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the Reset is complete. This bit is not Enable-Protected. This bit is Write-Synchronized. Value Description 0 There is no ongoing reset operation. 1 The reset operation is ongoing. SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 442

26.8.2 Non-Maskable Interrupt Control

Name: NMICTRL Offset: 0x01 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 NMIASYNCH NMIFILTEN NMISENSE[2:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 4 – NMIASYNCH Asynchronous Edge Detection Mode The NMI edge detection can be operated synchronously or asynchronously to the EIC clock. Value Description 0 The NMI edge detection is synchronously operated. 1 The NMI edge detection is asynchronously operated. Bit 3 – NMIFILTEN Non-Maskable Interrupt Filter Enable Value Description 0 NMI filter is disabled. 1 NMI filter is enabled. Bits 2:0 – NMISENSE[2:0] Non-Maskable Interrupt Sense Configuration These bits define on which edge or level the NMI triggers. Value Name Description 0x0 NONE No detection 0x1 RISE Rising-edge detection 0x2 FALL Falling-edge detection 0x3 BOTH Both-edge detection 0x4 HIGH High-level detection 0x5 LOW Low-level detection 0x6 - 0x7 - Reserved SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 443

26.8.3 Non-Maskable Interrupt Flag Status and Clear

Name: NMIFLAG Offset: 0x02 Reset: 0x0000 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 NMI Access RW Reset 0 Bit 0 – NMI Non-Maskable Interrupt This flag is cleared by writing a '1' to it. This flag is set when the NMI pin matches the NMI sense configuration, and will generate an interrupt request. Writing a '0' to this bit has no effect. SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 444

26.8.4 Synchronization Busy

Name: SYNCBUSY Offset: 0x04 Reset: 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ENABLE SWRST Access R R Reset 0 0 Bit 1 – ENABLE Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.ENABLE bit is complete. 1 Write synchronization for CTRLA.ENABLE bit is ongoing. Bit 0 – SWRST Software Reset Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.SWRST bit is complete. 1 Write synchronization for CTRLA.SWRST bit is ongoing. SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 445

26.8.5 Event Control

Name: EVCTRL Offset: 0x08 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 EXTINTEO[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EXTINTEO[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – EXTINTEO[15:0] External Interrupt Event Output Enable The bit x of EXTINTEO enables the event associated with the EXTINTx pin. Value Description 0 Event from pin EXTINTx is disabled.

1 Event from pin EXTINTx is enabled and will be generated when EXTINTx pin matches the

26.8.6 Interrupt Enable Clear

Name: INTENCLR Offset: 0x0C Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 EXTINT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EXTINT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – EXTINT[15:0] External Interrupt Enable The bit x of EXTINT disables the interrupt associated with the EXTINTx pin. Writing a '0' to bit x has no effect. Writing a '1' to bit x will clear the External Interrupt Enable bit x, which disables the external interrupt EXTINTx. Value Description 0 The external interrupt x is disabled. 1 The external interrupt x is enabled. SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 447

26.8.7 Interrupt Enable Set

Name: INTENSET Offset: 0x10 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 EXTINT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EXTINT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – EXTINT[15:0] External Interrupt Enable The bit x of EXTINT enables the interrupt associated with the EXTINTx pin. Writing a '0' to bit x has no effect. Writing a '1' to bit x will set the External Interrupt Enable bit x, which enables the external interrupt EXTINTx. Value Description 0 The external interrupt x is disabled. 1 The external interrupt x is enabled. SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 448

26.8.8 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x14 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 EXTINT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EXTINT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – EXTINT[15:0] External Interrupt The flag bit x is cleared by writing a '1' to it. This flag is set when EXTINTx pin matches the external interrupt sense configuration and will generate an interrupt request if INTENCLR/SET.EXTINT[x] is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the External Interrupt x flag. SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 449

26.8.9 External Interrupt Asynchronous Mode

Name: ASYNCH Offset: 0x18 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 ASYNCH[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ASYNCH[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 15:0 – ASYNCH[15:0] Asynchronous Edge Detection Mode The bit x of ASYNCH set the Asynchronous Edge Detection Mode for the interrupt associated with the EXTINTx pin. Value Description 0 The EXTINT x edge detection is synchronously operated. 1 The EXTINT x edge detection is asynchronously operated. SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 450

26.8.10 External Interrupt Sense Configuration n

Name: CONFIG Offset: 0x1C + n*0x04 [n=0..1] Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 FILTENx SENSEx[2:0] FILTENx SENSEx[2:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 FILTENx SENSEx[2:0] FILTENx SENSEx[2:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 FILTENx SENSEx[2:0] FILTENx SENSEx[2:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FILTENx SENSEx[2:0] FILTENx SENSEx[2:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 3,7,11,15,19,23,27,31 – FILTENx Filter Enable x [x=7..0] Note: The filter must be disabled if the asynchronous detection is enabled. Value Description 0 Filter is disabled for EXTINT[n*8+x] input. 1 Filter is enabled for EXTINT[n*8+x] input. Bits 0:2,4:6,8:10,12:14,16:18,20:22,24:26,28:30 – SENSEx Input Sense Configuration x [x=7..0] These bits define on which edge or level the interrupt or event for EXTINT[n*8+x] will be generated. Value Name Description 0x0 NONE No detection 0x1 RISE Rising-edge detection 0x2 FALL Falling-edge detection 0x3 BOTH Both-edge detection 0x4 HIGH High-level detection 0x5 LOW Low-level detection 0x6 - 0x7 - Reserved SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 451

26.8.11 Debouncer Enable

Name: DEBOUNCEN Offset: 0x30 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 DEBOUNCEN[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DEBOUNCEN[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 15:0 – DEBOUNCEN[15:0] Debouncer Enable The bit x of DEBOUNCEN set the Debounce mode for the interrupt associated with the EXTINTx pin. Value Description 0 The EXTINT x edge input is not debounced. 1 The EXTINT x edge input is debounced. SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 452

26.8.12 Debouncer Prescaler

Name: DPRESCALER Offset: 0x34 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 TICKON Access RW Reset 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 STATESx PRESCALERx[2:0] STATESx PRESCALERx[2:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 16 – TICKON Pin Sampler frequency selection This bit selects the clock used for the sampling of bounce during transition detection. Value Description 0 The bounce sampler is using GCLK_EIC. 1 The bounce sampler is using the low frequency clock. Bits 3,7 – STATESx Debouncer number of states x This bit selects the number of samples by the debouncer low frequency clock needed to validate a transition from current pin state to next pin state in synchronous debouncing mode for pins EXTINT[7+(8x):8x]. Value Description 0 The number of low frequency samples is 3. 1 The number of low frequency samples is 7. Bits 2:0, 6:4 – PRESCALERx Debouncer Prescaler x These bits select the debouncer low frequency clock for pins EXTINT[7+(8x):8x]. Value Name Description 0x0 F/2 EIC clock divided by 2 0x1 F/4 EIC clock divided by 4 0x2 F/8 EIC clock divided by 8 0x3 F/16 EIC clock divided by 16 SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 453

0x4 F/32 EIC clock divided by 32 0x5 F/64 EIC clock divided by 64 0x6 F/128 EIC clock divided by 128 0x7 F/256 EIC clock divided by 256 SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 454

26.8.13 Pin State

Name: PINSTATE Offset: 0x38 Reset: 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 PINSTATE[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PINSTATE[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15:0 – PINSTATE[15:0] Pin State These bits return the valid pin state of the debounced external interrupt pin EXTINTx. SAM C20/C21 Family Data Sheet EIC – External Interrupt Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 455

NVMCTRL – Nonvolatile Memory Controller

27.1 Overview

Nonvolatile Memory (NVM) is a reprogrammable Flash memory that retains program and data storage even with power off. It embeds a main array and a separate smaller array intended for EEPROM emulation (RWWEE) that can be programmed while reading the main array. The NVM Controller (NVMCTRL) connects to the AHB and APB bus interfaces for system access to the NVM block. The AHB interface is used for reads and writes to the NVM block, while the APB interface is used for commands and configuration.

27.2 Features

32-bit AHB interface for reads and writes
Read-While-Write DATA Flash
All NVM sections are memory mapped to the AHB, including calibration and system configuration
32-bit APB interface for commands and control
Programmable wait states for read optimization
16 regions can be individually protected or unprotected
Additional protection for bootloader
Supports device protection through a security bit
Interface to Power Manager for power-down of Flash blocks in sleep modes
Can optionally wake up on exit from sleep or on first access
Direct-mapped cache Note: A register with property "Enable-Protected" may contain bits that are not enable-protected.

27.3 Block Diagram

Figure 27-1. Block Diagram Command and Control NVM Interface Cache NVM BlockNVMCTRL AHB APB main array RWWEE array SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 456

27.4 Signal Description

Not applicable.

27.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described in the following sections.

27.5.1 Power Management

The NVMCTRL will continue to operate in any sleep mode where the selected source clock is running. The NVMCTRL interrupts can be used to wake up the device from sleep modes. The Power Manager will automatically put the NVM block into a low-power state when entering sleep mode. This is based on the Control B register (CTRLB) SLEEPPRM bit setting. Refer to the 27.8.2 CTRLB. SLEEPPRM register description for more details. The NVM block goes into low-power mode automatically when the device enters STANDBY mode regardless of SLEEPPRM. The NVM Page Buffer is lost when the NVM goes into low power mode therefore a write command must be issued prior entering the NVM low power mode. NVMCTRL SLEEPPRM can be disabled to avoid such loss when the CPU goes into sleep except if the device goes into STANDBY mode for which there is no way to retain the Page Buffer. Related Links 19. PM – Power Manager

27.5.2 Clocks

Two synchronous clocks are used by the NVMCTRL. One is provided by the AHB bus (CLK_NVMCTRL_AHB) and the other is provided by the APB bus (CLK_NVMCTRL_APB). For higher system frequencies, a programmable number of wait states can be used to optimize performance. When changing the AHB bus frequency, the user must ensure that the NVM Controller is configured with the proper number of wait states. Refer to the Electrical Characteristics for the exact number of wait states to be used for a particular frequency range. Related Links 45. Electrical Characteristics 85°C (SAM C20/C21 E/G/J)

27.5.3 Interrupts

The NVM Controller interrupt request line is connected to the interrupt controller. Using the NVMCTRL interrupt requires the interrupt controller to be programmed first.

27.5.4 Debug Operation

When an external debugger forces the CPU into debug mode, the peripheral continues normal operation. Access to the NVM block can be protected by the security bit. In this case, the NVM block will not be accessible. See the section on the NVMCTRL 27.6.6 Security Bit for details.

27.5.5 Register Access Protection

All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the following registers:

Interrupt Flag Status and Clear register (INTFLAG) SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 457

Status register (STATUS) Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write- Protection" property in each individual register description. Related Links 11. PAC - Peripheral Access Controller

27.5.6 Analog Connections

Not applicable.

27.6 Functional Description

27.6.1 Principle of Operation

The NVM Controller is a slave on the AHB and APB buses. It responds to commands, read requests and write requests, based on user configuration.

27.6.1.1 Initialization

After power up, the NVM Controller goes through a power-up sequence. During this time, access to the NVM Controller from the AHB bus is halted. Upon power-up completion, the NVM Controller is operational without any need for user configuration.

27.6.2 Memory Organization

Refer to the Physical Memory Map for memory sizes and addresses for each device. The NVM is organized into rows, where each row contains four pages, as shown in the NVM Row Organization figure. The NVM has a row-erase granularity, while the write granularity is by page. In other words, a single row erase will erase all four pages in the row, while four write operations are used to write the complete row. Figure 27-2. NVM Row Organization Page (n*4) + 3 Page (n*4) + 2 Page (n*4) + 1 Page (n*4) + 0 Row n The NVM block contains a calibration and auxiliary space plus a dedicated EEPROM emulation space that are memory mapped. Refer to the NVM Organization figure below for details. The calibration and auxiliary space contains factory calibration and system configuration information. These spaces can be read from the AHB bus in the same way as the main NVM main address space. In addition, a boot loader section can be allocated at the beginning of the main array, and an EEPROM section can be allocated at the end of the NVM main address space. SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 458

Figure 27-3. NVM Memory Organization Calibration and Auxillary Space RWWEE Address Space NVM Main Address Space NVM Base Address + 0x00800000 NVM Base Address + 0x00400000 NVM Base Address + NVM Size NVM Base Address The lower rows in the NVM main address space can be allocated as a boot loader section by using the BOOTPROT fuses, and the upper rows can be allocated to EEPROM, as shown in the figure below. The boot loader section is protected by the lock bit(s) corresponding to this address space and by the BOOTPROT[2:0] fuse. The EEPROM rows can be written regardless of the region lock status. The number of rows protected by BOOTPROT is given in Boot Loader Size, the number of rows allocated to the EEPROM are given in EEPROM Size. SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 459

Figure 27-4. EEPROM and Boot Loader Allocation Related Links

27.6.3 Region Lock Bits

The NVM block is grouped into 16 equally sized regions. The region size is dependent on the Flash memory size, and is given in the table below. Each region has a dedicated lock bit preventing writing and erasing pages in the region. After production, all regions will be unlocked. Table 27-1. Region Size Memory Size [KB] Region Size [KB] 256 16 128 8 64 4 32 2 To lock or unlock a region, the Lock Region and Unlock Region commands are provided. Writing one of these commands will temporarily lock/unlock the region containing the address loaded in the ADDR register. ADDR can be written by software, or the automatically loaded value from a write operation can be used. The new setting will stay in effect until the next Reset, or until the setting is changed again using SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 460

the Lock and Unlock commands. The current status of the lock can be determined by reading the LOCK register. To change the default lock/unlock setting for a region, the user configuration section of the auxiliary space must be written using the Write Auxiliary Page command. Writing to the auxiliary space will take effect after the next Reset. Therefore, a boot of the device is needed for changes in the lock/unlock setting to take effect. Refer to the Physical Memory Map for calibration and auxiliary space address mapping. Related Links

27.6.4 Command and Data Interface

The NVM Controller is addressable from the APB bus, while the NVM main address space is addressable from the AHB bus. Read and automatic page write operations are performed by addressing the NVM main address space or the RWWEE address space directly, while other operations such as manual page writes and row erases must be performed by issuing commands through the NVM Controller. To issue a command, the CTRLA.CMD bits must be written along with the CTRLA.CMDEX value. When a command is issued, INTFLAG.READY will be cleared until the command has completed. Any commands written while INTFLAG.READY is low will be ignored. The CTRLB register must be used to control the power reduction mode, read wait states, and the write mode.

27.6.4.1 NVM Read

Reading from the NVM main address space is performed via the AHB bus by addressing the NVM main address space or auxiliary address space directly. Read data is available after the configured number of read wait states (CTRLB.RWS) set in the NVM Controller. The number of cycles data are delayed to the AHB bus is determined by the read wait states. Examples of using zero and one wait states are shown in the following figure. Reading the NVM main address space while a programming or erase operation is ongoing on the NVM main array results in an AHB bus stall until the end of the operation. Reading the NVM main array does not stall the bus when the RWWEE array is being programmed or erased. Figure 27-5. Read Wait State Examples

0 Wait States

1 Wait States

27.6.4.2 RWWEE Read

Reading from the RWW EEPROM address space is performed via the AHB bus by addressing the RWWEE address space directly. Read timings are similar to regular NVM read timings when access size is Byte or half-Word. The AHB data phase is twice as long in case of full-Word-size access. It is not possible to read the RWWEE area while the NVM main array is being written or erased, whereas the RWWEE area can be written or erased while the main array is being read. The RWWEE address space is not cached, therefore it is recommended to limit access to this area for performance and power consumption considerations.

27.6.4.3 NVM Write

The NVM Controller requires that an erase must be done before programming. The entire NVM main address space and the RWWEE address space can be erased by a debugger Chip Erase command. Alternatively, rows can be individually erased by the Erase Row command or the RWWEE Erase Row command to erase the NVM main address space or the RWWEE address space, respectively. After programming the NVM main array, the region that the page resides in can be locked to prevent spurious write or erase sequences. Locking is performed on a per-region basis, and so, locking a region will lock all pages inside the region. Data to be written to the NVM block are first written to and stored in an internal buffer called the page buffer. The page buffer contains the same number of bytes as an NVM page. Writes to the page buffer must be 16 or 32 bits. 8-bit writes to the page buffer are not allowed and will cause a system exception. Internally, writes to the page buffer are on a 64-bit basis through the page buffer load data register (PBLDATA1 and PBLDATA0). The PBLDATA register is a holding register for writes to the same 64-bit page buffer section. Data within a 64-bit section can be written in any order. Crossing a 64-bit boundary will reset the PBLDATA register to all ones. The following example assumes startup from reset where the current address is 0 and PBLDATA is all ones. Only 64 bits of the page buffer are written at a time, but 128 bits are shown for reference. Sequential 32-bit Write Example:

32-bit 0x1 written to address 0 – Page buffer[127:0] = {0xFFFFFFFF_FFFFFFFF, PBLDATA[63:32], 0x00000001} – PBLDATA[63:0] = {PBLDATA[63:32], 0x00000001}
32-bit 0x2 written to address 1 – Page buffer[127:0] = {0xFFFFFFFF_FFFFFFFF, 0x00000002, PBLDATA[31:0] – PBLDATA[63:0] = 0x00000002, PBLDATA[31:0]}
32-bit 0x3 written to address 2 (crosses 64-bit boundary) – Page buffer[127:0] = 0xFFFFFFFF_00000003_00000002_00000001 – PBLDATA[63:0] = 0xFFFFFFFF_00000003 Random access writes to 32-bit words within the page buffer will overwrite the opposite word within the same 64-bit section with ones. In the following example, notice that 0x00000001 is overwritten with 0xFFFFFFFF from the third write due to the 64-bit boundary crossing. Only 64 bits of the page buffer are written at a time, but 128 bits are shown for reference. Random Access 32-bit Write Example:
32-bit 0x1 written to address 2 – Page buffer[127:0] = 0xFFFFFFFF_00000001_FFFFFFFF_FFFFFFFF SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 462

– PBLDATA[63:0] = 0xFFFFFFFF_00000001

32-bit 0x2 written to address 1 – Page buffer[127:0] = 0xFFFFFFFF_00000001_00000002_FFFFFFFF – PBLDATA[63:0] = 0x00000002_FFFFFFFF
32-bit 0x3 written to address 3 – Page buffer[127:0] = 0x00000003_FFFFFFFF_00000002_FFFFFFFF – PBLDATA[63:0] = 0x00000003_0xFFFFFFFF Both the NVM main array and the RWWEE array share the same page buffer. Writing to the NVM block via the AHB bus is performed by a load operation to the page buffer. For each AHB bus write, the address is stored in the ADDR register. After the page buffer has been loaded with the required number of bytes, the page can be written to the NVM main array or the RWWEE array by setting CTRLA.CMD to 'Write Page' or 'RWWEE Write Page', respectively, and setting the key value to CMDEX. The LOAD bit in the STATUS register indicates whether the page buffer has been loaded or not. Before writing the page to memory, the accessed row must be erased. Automatic page writes are enabled by writing the manual write bit to zero (CTRLB.MANW=0). This will trigger a write operation to the page addressed by ADDR when the last location of the page is written. Because the address is automatically stored in ADDR during the I/O bus write operation, the last given address will be present in the ADDR register. There is no need to load the ADDR register manually, unless a different page in memory is to be written. The row to be written to must be erased before the write command is given.
Write to the page buffer by addressing the NVM main address space directly
Write the page buffer to memory: CTRL.CMD='Write Page' and CMDEX
The READY bit in the INTFLAG register will be low while programming is in progress, and access through the AHB will be stalled The row to be written to must be erased before the last write to the page buffer is performed. Note that partially written pages must be written with a manual write.
Write to the page buffer by addressing the NVM main address space directly. When the last location in the page buffer is written, the page is automatically written to NVM main address space.
INTFLAG.READY will be zero while programming is in progress and access through the AHB will be stalled.

27.6.4.4 Page Buffer Clear

The page buffer is automatically set to all '1' after a page write is performed. If a partial page has been written and it is desired to clear the contents of the page buffer, the Page Buffer Clear command can be used.

27.6.4.5 Erase Row

Before a page can be written, the row containing that page must be erased. The Erase Row command can be used to erase the desired row in the NVM main address space. The RWWEE Erase Row can be used to erase the desired row in the RWWEE array. Erasing the row sets all bits to '1'. If the row resides in a region that is locked, the erase will not be performed and the Lock Error bit in the Status register (STATUS.LOCKE) will be set. SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 463

27.6.4.5.1 Procedure for Erase Row

Write the address of the row to erase to ADDR. Any address within the row can be used.
Issue an Erase Row command. Note: The NVM Address bit field in the Address register (ADDR.ADDR) uses 16-bit addressing.

27.6.4.6 Lock and Unlock Region

These commands are used to lock and unlock regions as detailed in section 27.6.3 Region Lock Bits.

27.6.4.7 Set and Clear Power Reduction Mode

The NVM Controller and block can be taken in and out of power reduction mode through the Set and Clear Power Reduction Mode commands. When the NVM Controller and block are in power reduction mode, the Power Reduction Mode bit in the Status register (STATUS.PRM) is set.

27.6.5 NVM User Configuration

The NVM user configuration resides in the auxiliary space. Refer to the Physical Memory Map of the device for calibration and auxiliary space address mapping. The bootloader resides in the main array starting at offset zero. The allocated boot loader section is write- protected. Table 27-2. Boot Loader Size BOOTPROT [2:0] Rows Protected by BOOTPROT Boot Loader Size in Bytes 0x7(1) None 0 0x6 2 512 0x5 4 1024 0x4 8 2048 0x3 16 4096 0x2 32 8192 0x1 64 16384 0x0 128 32768 Note: 1) Default value is 0x7. The EEPROM[2:0] bits indicate the EEPROM size, see the table below. The EEPROM resides in the upper rows of the NVM main address space and is writable, regardless of the region lock status. Table 27-3. EEPROM Size EEPROM[2:0] Rows Allocated to EEPROM EEPROM Size in Bytes

7 None 0

EEPROM[2:0] Rows Allocated to EEPROM EEPROM Size in Bytes 2 16 4096 1 32 8192 0 64 16384 Related Links The security bit allows the entire chip to be locked from external access for code security. The security bit can be written by a dedicated command, Set Security Bit (SSB). Once set, the only way to clear the security bit is through a debugger Chip Erase command. After issuing the SSB command, the PROGE error bit can be checked. In order to increase the security level it is recommended to enable the internal BODVDD when the security bit is set. Related Links 13. DSU - Device Service Unit

27.6.7 Cache

The NVM Controller cache reduces the device power consumption and improves system performance when wait states are required. Only the NVM main array address space is cached. It is a direct-mapped cache that implements 8 lines of 64 bits (i.e., 64 Bytes). NVM Controller cache can be enabled by writing a '0' to the Cache Disable bit in the Control B register ( CTRLB.CACHEDIS). The cache can be configured to three different modes using the Read Mode bit group in the Control B register ( CTRLB.READMODE). The INVALL command can be issued using the Command bits in the Control A register to invalidate all cache lines ( CTRLA.CMD=INVALL). Commands affecting NVM content automatically invalidate cache lines. SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 465

27.7 Register Summary

Offset Name Bit Pos. 0x00 CTRLA 7:0 CMD[6:0] 15:8 CMDEX[7:0] 0x02 ... 0x03 Reserved 0x04 CTRLB 7:0 MANW RWS[3:0] 15:8 SLEEPPRM[1:0] 23:16 CACHEDIS READMODE[1:0] 31:24 0x08 PARAM 7:0 NVMP[7:0] 15:8 NVMP[15:8] 23:16 RWWEEP[3:0] PSZ[2:0] 31:24 RWWEEP[11:4] 0x0C INTENCLR 7:0 ERROR READY 0x0D ... 0x0F Reserved 0x10 INTENSET 7:0 ERROR READY 0x11 ... 0x13 Reserved 0x14 INTFLAG 7:0 ERROR READY 0x15 ... 0x17 Reserved 0x18 STATUS 7:0 NVME LOCKE PROGE LOAD PRM 15:8 SB 0x1A ... 0x1B Reserved 0x1C ADDR 7:0 ADDR[7:0] 15:8 ADDR[15:8] 23:16 ADDR[20:16] 31:24 0x20 LOCK 7:0 LOCK[7:0] 15:8 LOCK[15:8] 0x22 ... 0x27 Reserved 0x28 PBLDATA0 7:0 PBLDATA[7:0] 15:8 PBLDATA[15:8] 23:16 PBLDATA[23:16] 31:24 PBLDATA[31:24] SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 466

Offset Name Bit Pos. 0x2C PBLDATA1 7:0 PBLDATA[7:0] 15:8 PBLDATA[15:8] 23:16 PBLDATA[23:16] 31:24 PBLDATA[31:24]

27.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-Synchronized" and/or "Write-Synchronized" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 467

27.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x0000 Property: PAC Write-Protection Bit 15 14 13 12 11 10 9 8 CMDEX[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CMD[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bits 15:8 – CMDEX[7:0] Command Execution When this bit group is written to the key value 0xA5, the command written to CMD will be executed. If a value different from the key value is tried, the write will not be performed and the Programming Error bit in the Status register (STATUS.PROGE) will be set. PROGE is also set if a previously written command is not completed yet. The key value must be written at the same time as CMD. If a command is issued through the APB bus on the same cycle as an AHB bus access, the AHB bus access will be given priority. The command will then be executed when the NVM block and the AHB bus are idle. INTFLAG.READY must be '1' when the command is issued. Bit 0 of the CMDEX bit group will read back as '1' until the command is issued. Note: The NVM Address bit field in the Address register (ADDR.ADDR) uses 16-bit addressing. Bits 6:0 – CMD[6:0] Command These bits define the command to be executed when the CMDEX key is written. CMD[6:0] Group Configuration

Description

0x02 ER Erase Row - Erases the row addressed by the ADDR register in the NVM main array. 0x03 - Reserved 0x04 WP Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. 0x05 EAR Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the Security bit is not set and only to the User Configuration Row. SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 468

CMD[6:0] Group Configuration 0x06 WAP Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the Security bit is not set and only to the User Configuration Row. 0x07-0x0E - Reserved 0x0F - Reserved 0x1A-0x19 - Reserved 0x1A RWWEEER RWWEE Erase Row - Erases the row addressed by the ADDR register in the RWWEE array. 0x1B - Reserved 0x1C RWWEEWP RWWEE Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register in the RWWEE array. 0x1D-0x3F - Reserved 0x40 LR Lock Region - Locks the region containing the address location in the ADDR register. 0x41 UR Unlock Region - Unlocks the region containing the address location in the ADDR register. 0x42 SPRM Sets the Power Reduction mode. 0x43 CPRM Clears the Power Reduction mode. 0x44 PBC Page Buffer Clear - Clears the page buffer. 0x45 SSB Set Security Bit - Sets the Security bit by writing 0x00 to the first byte in the lockbit row. 0x46 INVALL Invalidates all cache lines. 0x47 LDR Lock Data Region - Locks the data region containing the address location in the ADDR register. When the security extension is enabled, only secure access can lock secure regions. 0x48 UDR Unlock Data Region - Unlocks the data region containing the address location in the ADDR register. When the security extension is enabled, only secure access can unlock secure regions. 0x47-0x7F - Reserved SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 469

27.8.2 Control B

Name: CTRLB Offset: 0x04 Reset: 0x00000080 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 CACHEDIS READMODE[1:0] Access R/W R/W R/W Reset 0 0 0 Bit 15 14 13 12 11 10 9 8 SLEEPPRM[1:0] Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 MANW RWS[3:0] Access R/W R/W R/W R/W R/W Reset 1 0 0 0 0 Bit 18 – CACHEDIS Cache Disable This bit is used to disable the cache. Value Description

0 The cache is enabled

1 The cache is disabled

Bits 17:16 – READMODE[1:0] NVMCTRL Read Mode Value Name Description 0x0 NO_MISS_PENALTY The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. 0x1 LOW_POWER Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increased run time. 0x2 DETERMINISTIC The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed Flash wait states. This mode can be used for real-time applications that require deterministic execution timings. 0x3 Reserved Bits 9:8 – SLEEPPRM[1:0] Power Reduction Mode during Sleep Indicates the Power Reduction Mode during sleep. SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 470

0x0 WAKEUPACCESS NVM block enters low-power mode when entering sleep. NVM block exits low-power mode upon first access. 0x1 WAKEUPINSTANT NVM block enters low-power mode when entering sleep. NVM block exits low-power mode when exiting sleep. 0x2 Reserved 0x3 DISABLED Auto power reduction disabled. Bit 7 – MANW Manual Write Note that reset value of this bit is '1'. Value Description

0 Writing to the last word in the page buffer will initiate a write operation to the page addressed

by the last write operation. This includes writes to memory and auxiliary rows. 1 Write commands must be issued through the CTRLA.CMD register. Bits 4:1 – RWS[3:0] NVM Read Wait States These bits control the number of wait states for a read operation. '0' indicates zero wait states, '1' indicates one wait state, etc., up to 15 wait states. This register is initialized to 0 wait states. Software can change this value based on the NVM access time and system frequency. SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 471

27.8.3 NVM Parameter

Name: PARAM Offset: 0x08 Reset: 0x000XXXXX Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 RWWEEP[11:4] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 RWWEEP[3:0] PSZ[2:0] Access R R R R R R R Reset 0 0 0 0 x x x Bit 15 14 13 12 11 10 9 8 NVMP[15:8] Access R R R R R R R R Reset x x x x x x x x Bit 7 6 5 4 3 2 1 0 NVMP[7:0] Access R R R R R R R R Reset x x x x x x x x Bits 31:20 – RWWEEP[11:0] Read While Write EEPROM emulation area Pages Indicates the number of pages in the RWW EEPROM emulation address space. Bits 18:16 – PSZ[2:0] Page Size Indicates the page size. Not all devices of the device families will provide all the page sizes indicated in the table. Value Name Description 0x0 8 8 bytes 0x1 16 16 bytes 0x2 32 32 bytes 0x3 64 64 bytes 0x4 128 128 bytes 0x5 256 256 bytes 0x6 512 512 bytes 0x7 1024 1024 bytes Bits 15:0 – NVMP[15:0] NVM Pages Indicates the number of pages in the NVM main address space. SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 472

27.8.4 Interrupt Enable Clear

Name: INTENCLR Offset: 0x0C Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 5 4 3 2 1 0 ERROR READY Access R/W R/W Reset 0 0 Bit 1 – ERROR Error Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the ERROR interrupt enable. This bit will read as the current value of the ERROR interrupt enable. Bit 0 – READY NVM Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the READY interrupt enable. This bit will read as the current value of the READY interrupt enable. SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 473

27.8.5 Interrupt Enable Set

Name: INTENSET Offset: 0x10 Reset: 0x00 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 5 4 3 2 1 0 ERROR READY Access R/W R/W Reset 0 0 Bit 1 – ERROR Error Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit sets the ERROR interrupt enable. This bit will read as the current value of the ERROR interrupt enable. Bit 0 – READY NVM Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit sets the READY interrupt enable. This bit will read as the current value of the READY interrupt enable. SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 474

27.8.6 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x14 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 ERROR READY Access R/W R Reset 0 0 Bit 1 – ERROR Error This flag is set on the occurrence of an NVME, LOCKE or PROGE error. This bit can be cleared by writing a '1' to its bit location. Value Description 0 No errors have been received since the last clear. 1 At least one error has occurred since the last clear. Bit 0 – READY NVM Ready Value Description 0 The NVM controller is busy programming or erasing. 1 The NVM controller is ready to accept a new command. SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 475

27.8.7 Status

Name: STATUS Offset: 0x18 Reset: 0x0X00 Property: – Bit 15 14 13 12 11 10 9 8 SB Access R Reset x Bit 7 6 5 4 3 2 1 0 NVME LOCKE PROGE LOAD PRM Access R/W R/W R/W R/W R Reset 0 0 0 0 0 Bit 8 – SB Security Bit Status Value Description 0 The Security bit is inactive. 1 The Security bit is active. Bit 4 – NVME NVM Error This bit can be cleared by writing a '1' to its bit location. Value Description

0 No programming or erase errors have been received from the NVM controller since this bit

was last cleared.

1 At least one error has been registered from the NVM Controller since this bit was last

cleared. Bit 3 – LOCKE Lock Error Status This bit can be cleared by writing a '1' to its bit location. Value Description 0 No programming of any locked lock region has happened since this bit was last cleared. 1 Programming of at least one locked lock region has happened since this bit was last cleared. Bit 2 – PROGE Programming Error Status This bit can be cleared by writing a '1' to its bit location. Value Description

0 No invalid commands or bad keywords were written in the NVM Command register since this

bit was last cleared.

1 An invalid command and/or a bad keyword was/were written in the NVM Command register

since this bit was last cleared. Bit 1 – LOAD NVM Page Buffer Active Loading This bit indicates that the NVM page buffer has been loaded with one or more words. Immediately after an NVM load has been performed, this flag is set. It remains set until a page write or a page buffer clear (PBCLR) command is given. This bit can be cleared by writing a '1' to its bit location. SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 476

Bit 0 – PRM Power Reduction Mode This bit indicates the current NVM power reduction state. The NVM block can be set in power reduction mode in two ways: through the command interface or automatically when entering sleep with SLEEPPRM set accordingly. PRM can be cleared in three ways: through AHB access to the NVM block, through the command interface (SPRM and CPRM) or when exiting sleep with SLEEPPRM set accordingly. Value Description 0 NVM is not in power reduction mode. 1 NVM is in power reduction mode. SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 477

27.8.8 Address

Name: ADDR Offset: 0x1C Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 ADDR[20:16] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ADDR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 20:0 – ADDR[20:0] NVM Address ADDR drives the hardware (16-bit) address to the NVM when a command is executed using CMDEX. This register is also automatically updated when writing to the page buffer. SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 478

27.8.9 Lock Section

Name: LOCK Offset: 0x20 Reset: 0xXXXX Property: – Bit 15 14 13 12 11 10 9 8 LOCK[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LOCK[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 x Bits 15:0 – LOCK[15:0] Region Lock Bits To set or clear these bits, the CMD register must be used. Default state after erase will be unlocked (0x0000). Value Description 0 The corresponding lock region is locked. 1 The corresponding lock region is not locked. SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 479

27.8.10 Page Buffer Load Data 0

Name: PBLDATA0 Offset: 0x28 Reset: 0xFFFFFFFF Property: - Bit 31 30 29 28 27 26 25 24 PBLDATA[31:24] Access R R R R R R R R Reset 1 1 1 1 1 1 1 1 Bit 23 22 21 20 19 18 17 16 PBLDATA[23:16] Access R R R R R R R R Reset 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 PBLDATA[15:8] Access R R R R R R R R Reset 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 PBLDATA[7:0] Access R R R R R R R R Reset 1 1 1 1 1 1 1 1 Bits 31:0 – PBLDATA[31:0] Page Buffer Load Data The PBLDATA register is a holding register for partial AHB writes to the same 64-bit page buffer section. Page buffer loads are performed on a 64-bit basis. This is a read only register. SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 480

27.8.11 Page Buffer Load Data 1

Name: PBLDATA1 Offset: 0x2C Reset: 0xFFFFFFFF Property: - Bit 31 30 29 28 27 26 25 24 PBLDATA[31:24] Access R R R R R R R R Reset 1 1 1 1 1 1 1 1 Bit 23 22 21 20 19 18 17 16 PBLDATA[23:16] Access R R R R R R R R Reset 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 PBLDATA[15:8] Access R R R R R R R R Reset 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 PBLDATA[7:0] Access R R R R R R R R Reset 1 1 1 1 1 1 1 1 Bits 31:0 – PBLDATA[31:0] Page Buffer Load Data (Bits 63:32]) The PBLDATA register is a holding register for partial AHB writes to the same 64-bit page buffer section. Page buffer loads are performed on a 64-bit basis. This is a read only register. SAM C20/C21 Family Data Sheet NVMCTRL – Nonvolatile Memory Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 481

PORT - I/O Pin Controller

28.1 Overview

The IO Pin Controller (PORT) controls the I/O pins of the device. The I/O pins are organized in a series of groups, collectively referred to as a PORT group. Each PORT group can have up to 32 pins that can be configured and controlled individually or as a group. The number of PORT groups on a device may depend on the package/number of pins. Each pin may either be used for general-purpose I/O under direct application control or be assigned to an embedded device peripheral. When used for general- purpose I/O, each pin can be configured as input or output, with highly configurable driver and pull settings. All I/O pins have true read-modify-write functionality when used for general-purpose I/O; the direction or the output value of one or more pins may be changed (set, reset or toggled) explicitly without unintentionally changing the state of any other pins in the same port group by a single, atomic 8-, 16- or 32-bit write. The PORT is connected to the high-speed bus matrix through an AHB/APB bridge.

28.2 Features

Selectable input and output configuration for each individual pin
Software-controlled multiplexing of peripheral functions on I/O pins
Flexible pin configuration through a dedicated Pin Configuration register
Configurable output driver and pull settings: – Totem-pole (push-pull) – Pull configuration – Driver strength
Configurable input buffer and pull settings: – Internal pull-up or pull-down – Input sampling criteria – Input buffer can be disabled if not needed for lower power consumption – Read-Modify-Write support for output value (OUTCLR/OUTSET/OUTGL) and pin direction (DIRCLR/DIRSET/DIRTGL)
Input event: – Up to four input event pins for each PORT group – SET/CLEAR/TOGGLE event actions for each event input on output value of a pin – Can be output to pin SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 482

28.3 Block Diagram

Figure 28-1. PORT Block Diagram ANALOG BLOCKS PERIPHERALS Digital Controls of Analog Blocks Analog Pad Connections I/O PADS Port Line Bundles IP Line Bundles Peripheral Mux Select PORT Control and Status Pad Line Bundles PORTMUX

28.4 Signal Description

Table 28-1. Signal description for PORT Signal name Type Description Pxy Digital I/O General-purpose I/O pin y in group x Refer to the I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be mapped on several pins. Related Links 6. I/O Multiplexing and Considerations

28.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly as follows.

28.5.1 I/O Lines

The I/O lines of the PORT are mapped to pins of the physical device. The following naming scheme is used: Each line bundle with up to 32 lines is assigned an identifier 'xy', with letter x=A, B, C… and two-digit number y=00, 01, …31. Examples: A24, C03. PORT pins are labeled 'Pxy' accordingly, for example PA24, PC03. This identifies each pin in the device uniquely. Each pin may be controlled by one or more peripheral multiplexer settings, which allow the pad to be routed internally to a dedicated peripheral function. When the setting is enabled, the selected peripheral SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 483

has control over the output state of the pad, as well as the ability to read the current physical pad state. Refer to I/O Multiplexing and Considerations for details. Device-specific configurations may cause some lines (and the corresponding Pxy pin) not to be implemented. Related Links 6. I/O Multiplexing and Considerations

28.5.2 Power Management

During Reset, all PORT lines are configured as inputs with input buffers, output buffers and pull disabled. The PORT peripheral will continue operating in any sleep mode where its source clock is running.

28.5.3 Clocks

The PORT bus clock (CLK_PORT_APB) can be enabled and disabled in the Main Clock module, and the default state of CLK_PORT_APB can be found in the Peripheral Clock Masking section in MCLK – Main Clock. The PORT requires an APB clock, which may be divided from the CPU main clock and allows the CPU to access the registers of PORT through the high-speed matrix and the AHB/APB bridge. One clock cycle latency can be observed on the APB access in case of concurrent PORT accesses. Related Links 17. MCLK – Main Clock

28.5.4 DMA

Not applicable.

28.5.5 Interrupts

Not applicable.

28.5.6 Events

The events of this peripheral are connected to the Event System. Related Links 29. EVSYS – Event System

28.5.7 Debug Operation

When the CPU is halted in debug mode, this peripheral will continue normal operation.

28.5.8 Register Access Protection

28.5.9 Analog Connections

Analog functions are connected directly between the analog blocks and the I/O pads using analog buses. However, selecting an analog peripheral function for a given pin will disable the corresponding digital features of the pad.

28.6 Functional Description

Figure 28-2. Overview of the PORT PULLENx OUTx DIRx INENx PORT PAD VDD INEN OE OUT PULLEN PAD Pull Resistor PG NG Input to Other Modules Analog Input/Output IN INx APB Bus Synchronizer Q D RR D Q DRIVEx DRIVE

28.6.1 Principle of Operation

Each PORT group of up to 32 pins is controlled by the registers in PORT, as described in the figure. These registers in PORT are duplicated for each PORT group, with increasing base addresses. The number of PORT groups may depend on the package/number of pins. SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 485

Figure 28-3. Overview of the peripheral functions multiplexing Port y PINCFG Port y Periph Signal 0 PORT bit y PMUXEN Data+Config Periph Signal 1 Periph Signal 15 Port y PMUX[3:0] Port y PMUX Select Port y Line Bundle PAD yPad y Peripheral Signals to be muxed to Pad y Port y Peripheral Mux Enable Line Bundle PORTMUX The I/O pins of the device are controlled by PORT peripheral registers. Each port pin has a corresponding bit in the Data Direction (DIR) and Data Output Value (OUT) registers to enable that pin as an output and to define the output state. The direction of each pin in a PORT group is configured by the DIR register. If a bit in DIR is set to '1', the corresponding pin is configured as an output pin. If a bit in DIR is set to '0', the corresponding pin is configured as an input pin. When the direction is set as output, the corresponding bit in the OUT register will set the level of the pin. If bit y in OUT is written to '1', pin y is driven HIGH. If bit y in OUT is written to '0', pin y is driven LOW. Pin configuration can be set by Pin Configuration (PINCFGy) registers, with y=00, 01, ..31 representing the bit position. The Data Input Value (IN) is set as the input value of a port pin with resynchronization to the PORT clock. To reduce power consumption, these input synchronizers can be clocked only when system requires reading the input value, as specified in the SAMPLING field of the Control register (CTRL). The value of the pin can always be read, whether the pin is configured as input or output. If the Input Enable bit in the Pin Configuration registers (PINCFGy.INEN) is '0', the input value will not be sampled. In PORT, the Peripheral Multiplexer Enable bit in the PINCFGy register (PINCFGy.PMUXEN) can be written to '1' to enable the connection between peripheral functions and individual I/O pins. The Peripheral Multiplexing n (PMUXn) registers select the peripheral function for the corresponding pin. This will override the connection between the PORT and that I/O pin, and connect the selected peripheral signal to the particular I/O pin instead of the PORT line bundle.

28.6.2 Basic Operation

28.6.2.1 Initialization

After reset, all standard function device I/O pads are connected to the PORT with outputs tri-stated and input buffers disabled, even if there is no clock running. However, specific pins, such as those used for connection to a debugger, may be configured differently, as required by their special function. SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 486

28.6.2.2 Operation

Each I/O pin Pxy can be controlled by the registers in PORT. Each PORT group x has its own set of PORT registers, with a base address at byte address (PORT + 0x80 * group index) (A corresponds to Refer to I/O Multiplexing and Considerations for details on available pin configuration and PORT groups. Configuring Pins as Output To use pin Pxy as an output, write bit y of the DIR register to '1'. This can also be done by writing bit y in the DIRSET register to '1' - this will avoid disturbing the configuration of other pins in that group. The y bit in the OUT register must be written to the desired output value. Similarly, writing an OUTSET bit to '1' will set the corresponding bit in the OUT register to '1'. Writing a bit in OUTCLR to '1' will set that bit in OUT to zero. Writing a bit in OUTTGL to '1' will toggle that bit in OUT. Configuring Pins as Input To use pin Pxy as an input, bit y in the DIR register must be written to '0'. This can also be done by writing bit y in the DIRCLR register to '1' - this will avoid disturbing the configuration of other pins in that group. The input value can be read from bit y in register IN as soon as the INEN bit in the Pin Configuration register (PINCFGy.INEN) is written to '1'. By default, the input synchronizer is clocked only when an input read is requested. This will delay the read operation by two cycles of the PORT clock. To remove the delay, the input synchronizers for each PORT group of eight pins can be configured to be always active, but this will increase power consumption. This is enabled by writing '1' to the corresponding SAMPLINGn bit field of the CTRL register, see CTRL.SAMPLING for details. Using Alternative Peripheral Functions To use pin Pxy as one of the available peripheral functions, the corresponding PMUXEN bit of the PINCFGy register must be '1'. The PINCFGy register for pin Pxy is at byte offset (PINCFG0 + y). The peripheral function can be selected by setting the PMUXO or PMUXE in the PMUXn register. The PMUXO/PMUXE is at byte offset PMUX0 + (y/2). The chosen peripheral must also be configured and enabled. Related Links 6. I/O Multiplexing and Considerations

28.6.3 I/O Pin Configuration

The Pin Configuration register (PINCFGy) is used for additional I/O pin configuration. A pin can be set in a totem-pole or pull configuration. As pull configuration is done through the Pin Configuration register, all intermediate PORT states during switching of pin direction and pin values are avoided. The I/O pin configurations are described further in this chapter, and summarized in Table 28-2.

28.6.3.1 Pin Configurations Summary

Table 28-2. Pin Configurations Summary DIR INEN PULLEN OUT Configuration 0 0 0 X Reset or analog I/O: all digital disabled SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 487

DIR INEN PULLEN OUT Configuration 0 0 1 0 Pull-down; input disabled 0 0 1 1 Pull-up; input disabled 0 1 0 X Input 0 1 1 0 Input with pull-down 0 1 1 1 Input with pull-up 1 0 X X Output; input disabled 1 1 X X Output; input enabled

28.6.3.2 Input Configuration

Figure 28-4. I/O configuration - Standard Input PULLEN DIR OUT IN INEN PULLEN INEN DIR 0 1 0 Figure 28-5. I/O Configuration - Input with Pull PULLEN DIR OUT IN INEN PULLEN INEN DIR 1 1 0 Note: When pull is enabled, the pull value is defined by the OUT value.

28.6.3.3 Totem-Pole Output

When configured for totem-pole (push-pull) output, the pin is driven low or high according to the corresponding bit setting in the OUT register. In this configuration there is no current limitation for sink or source other than what the pin is capable of. If the pin is configured for input, the pin will float if no external pull is connected. Note: Enabling the output driver will automatically disable pull. SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 488

Figure 28-6. I/O Configuration - Totem-Pole Output with Disabled Input PULLEN DIR OUT IN INEN PULLEN INEN DIR 0 0 1 Figure 28-7. I/O Configuration - Totem-Pole Output with Enabled Input PULLEN DIR OUT IN INEN PULLEN INEN DIR 0 1 1 Figure 28-8. I/O Configuration - Output with Pull PULLEN DIR OUT IN INEN PULLEN INEN DIR 1 0 0

28.6.3.4 Digital Functionality Disabled

Neither Input nor Output functionality are enabled. Figure 28-9. I/O Configuration - Reset or Analog I/O: Digital Output, Input and Pull Disabled PULLEN DIR OUT IN INEN PULLEN INEN DIR 0 0 0

28.6.4 Events

The PORT allows input events to control individual I/O pins. These input events are generated by the EVSYS module and can originate from a different clock domain than the PORT module. The PORT can perform the following actions: SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 489

Output (OUT): I/O pin will be set when the incoming event has a high level ('1') and cleared when the incoming event has a low-level ('0').
Set (SET): I/O pin will be set when an incoming event is detected.
Clear (CLR): I/O pin will be cleared when an incoming event is detected.
Toggle (TGL): I/O pin will toggle when an incoming event is detected. The event is output to pin without any internal latency. For SET, CLEAR and TOGGLE event actions, the action will be executed up to three clock cycles after a rising edge. The event actions can be configured with the Event Action m bit group in the Event Input Control register( EVCTRL.EVACTm). Writing a '1' to a PORT Event Enable Input m of the Event Control register (EVCTRL.PORTEIm) enables the corresponding action on input event. Writing '0' to this bit disables the corresponding action on input event. Note that several actions can be enabled for incoming events. If several events are connected to the peripheral, any enabled action will be taken for any of the incoming events. Refer to EVSYS – Event System. for details on configuring the Event System. Each event input can address one and only one I/O pin at a time. The selection of the pin is indicated by the PORT Event Pin Identifier of the Event Input Control register (EVCTR.PIDn). On the other hand, one I/O pin can be addressed by up to four different input events. To avoid action conflict on the output value of the register (OUT) of this particular I/O pin, only one action is performed according to the table below. Note that this truth table can be applied to any SET/CLR/TGL configuration from two to four active input events. Table 28-3. Priority on Simultaneous SET/CLR/TGL Event Actions EVACT0 EVACT1 EVACT2 EVACT3 Executed Event Action SET SET SET SET SET CLR CLR CLR CLR CLR All Other Combinations TGL Be careful when the event is output to pin. Due to the fact the events are received asynchronously, the I/O pin may have unpredictable levels, depending on the timing of when the events are received. When several events are output to the same pin, the lowest event line will get the access. All other events will be ignored. Related Links 29. EVSYS – Event System

28.6.5 PORT Access Priority

The PORT is accessed by different systems:

The ARM ® CPU through the high-speed matrix and the AHB/APB bridge (APB)
EVSYS through four asynchronous input events The following priority is adopted: 1. APB 2. EVSYS input events, except for events with EVCTRL.EVACTn=OUT, where the output pin directly follows the event input signal, independently of the OUT register value. For input events that require different actions on the same I/O pin, refer to 28.6.4 Events. SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 490

28.7 Register Summary

The I/O pins are assembled in pin groups with up to 32 pins. Group 0 consists of the PA pins, and group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Offset Name Bit Pos. 0x00 DIR 7:0 DIR[7:0] 15:8 DIR[15:8] 23:16 DIR[23:16] 31:24 DIR[31:24] 0x04 DIRCLR 7:0 DIRCLR[7:0] 15:8 DIRCLR[15:8] 23:16 DIRCLR[23:16] 31:24 DIRCLR[31:24] 0x08 DIRSET 7:0 DIRSET[7:0] 15:8 DIRSET[15:8] 23:16 DIRSET[23:16] 31:24 DIRSET[31:24] 0x0C DIRTGL 7:0 DIRTGL[7:0] 15:8 DIRTGL[15:8] 23:16 DIRTGL[23:16] 31:24 DIRTGL[31:24] 0x10 OUT 7:0 OUT[7:0] 15:8 OUT[15:8] 23:16 OUT[23:16] 31:24 OUT[31:24] 0x14 OUTCLR 7:0 OUTCLR[7:0] 15:8 OUTCLR[15:8] 23:16 OUTCLR[23:16] 31:24 OUTCLR[31:24] 0x18 OUTSET 7:0 OUTSET[7:0] 15:8 OUTSET[15:8] 23:16 OUTSET[23:16] 31:24 OUTSET[31:24] 0x1C OUTTGL 7:0 OUTTGL[7:0] 15:8 OUTTGL[15:8] 23:16 OUTTGL[23:16] 31:24 OUTTGL[31:24] 0x20 IN 7:0 IN[7:0] 15:8 IN[15:8] 23:16 IN[23:16] 31:24 IN[31:24] SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 491

Offset Name Bit Pos. 0x24 CTRL 7:0 SAMPLING[7:0] 15:8 SAMPLING[15:8] 23:16 SAMPLING[23:16] 31:24 SAMPLING[31:24] 0x28 WRCONFIG 7:0 PINMASK[7:0] 15:8 PINMASK[15:8] 23:16 DRVSTR PULLEN INEN PMUXEN 31:24 HWSEL WRPINCFG WRPMUX PMUX[3:0] 0x2C EVCTRL 7:0 PORTEIx EVACTx[1:0] PIDx[4:0] 15:8 PORTEIx EVACTx[1:0] PIDx[4:0] 23:16 PORTEIx EVACTx[1:0] PIDx[4:0] 31:24 PORTEIx EVACTx[1:0] PIDx[4:0] 0x30 PMUX0 7:0 PMUXO[3:0] PMUXE[3:0] ... 0x3F PMUX15 7:0 PMUXO[3:0] PMUXE[3:0] 0x40 PINCFG0 7:0 DRVSTR PULLEN INEN PMUXEN ... 0x5F PINCFG31 7:0 DRVSTR PULLEN INEN PMUXEN

28.8 Register Description

28.8.1 Data Direction

Name: DIR Offset: 0x00 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to configure one or more I/O pins as an input or output. This register can be manipulated without doing a read-modify-write operation by using the Data Direction Toggle (DIRTGL), Data Direction Clear (DIRCLR) and Data Direction Set (DIRSET) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 DIR[31:24] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIR[23:16] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIR[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIR[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DIR[31:0] Port Data Direction These bits set the data direction for the individual I/O pins in the PORT group. Value Description 0 The corresponding I/O pin in the PORT group is configured as an input. 1 The corresponding I/O pin in the PORT group is configured as an output. SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 493

28.8.2 Data Direction Clear

Name: DIRCLR Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to set one or more I/O pins as an input, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data Direction Set (DIRSET) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 DIRCLR[31:24] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIRCLR[23:16] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIRCLR[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIRCLR[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DIRCLR[31:0] Port Data Direction Clear Writing a '0' to a bit has no effect. Writing a '1' to a bit will clear the corresponding bit in the DIR register, which configures the I/O pin as an input. Value Description 0 The corresponding I/O pin in the PORT group will keep its configuration. 1 The corresponding I/O pin in the PORT group is configured as input. SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 494

28.8.3 Data Direction Set

Name: DIRSET Offset: 0x08 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to set one or more I/O pins as an output, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data Direction Clear (DIRCLR) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 DIRSET[31:24] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIRSET[23:16] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIRSET[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIRSET[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DIRSET[31:0] Port Data Direction Set Writing '0' to a bit has no effect. Writing '1' to a bit will set the corresponding bit in the DIR register, which configures the I/O pin as an output. Value Description 0 The corresponding I/O pin in the PORT group will keep its configuration. 1 The corresponding I/O pin in the PORT group is configured as an output. SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 495

28.8.4 Data Direction Toggle

Name: DIRTGL Offset: 0x0C Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to toggle the direction of one or more I/O pins, without doing a read-modify- write operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Set (DIRSET) and Data Direction Clear (DIRCLR) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 DIRTGL[31:24] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIRTGL[23:16] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIRTGL[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIRTGL[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DIRTGL[31:0] Port Data Direction Toggle Writing '0' to a bit has no effect. Writing '1' to a bit will toggle the corresponding bit in the DIR register, which reverses the direction of the I/O pin. Value Description 0 The corresponding I/O pin in the PORT group will keep its configuration. 1 The direction of the corresponding I/O pin is toggled. SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 496

28.8.5 Data Output Value

Name: OUT Offset: 0x10 Reset: 0x00000000 Property: PAC Write-Protection This register sets the data output drive value for the individual I/O pins in the PORT. This register can be manipulated without doing a read-modify-write operation by using the Data Output Value Clear (OUTCLR), Data Output Value Set (OUTSET), and Data Output Value Toggle (OUTTGL) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 OUT[31:24] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OUT[23:16] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 OUT[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OUT[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31:0 – OUT[31:0] PORT Data Output Value For pins configured as outputs via the Data Direction register (DIR), these bits set the logical output drive level. For pins configured as inputs via the Data Direction register (DIR) and with pull enabled via the Pull Enable bit in the Pin Configuration register (PINCFG.PULLEN), these bits will set the input pull direction. Value Description 0 The I/O pin output is driven low, or the input is connected to an internal pull-down. 1 The I/O pin output is driven high, or the input is connected to an internal pull-up. SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 497

28.8.6 Data Output Value Clear

Name: OUTCLR Offset: 0x14 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to set one or more output I/O pin drive levels low, without doing a read- modify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle (OUTTGL) and Data Output Value Set (OUTSET) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 OUTCLR[31:24] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OUTCLR[23:16] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 OUTCLR[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OUTCLR[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31:0 – OUTCLR[31:0] PORT Data Output Value Clear Writing '0' to a bit has no effect. Writing '1' to a bit will clear the corresponding bit in the OUT register. Pins configured as outputs via the Data Direction register (DIR) will be set to low output drive level. Pins configured as inputs via DIR and with pull enabled via the Pull Enable bit in the Pin Configuration register (PINCFG.PULLEN) will set the input pull direction to an internal pull-down. Value Description 0 The corresponding I/O pin in the PORT group will keep its configuration.

1 The corresponding I/O pin output is driven low, or the input is connected to an internal pull-

28.8.7 Data Output Value Set

Name: OUTSET Offset: 0x18 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to set one or more output I/O pin drive levels high, without doing a read- modify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle (OUTTGL) and Data Output Value Clear (OUTCLR) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 OUTSET[31:24] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OUTSET[23:16] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 OUTSET[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OUTSET[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31:0 – OUTSET[31:0] PORT Data Output Value Set Writing '0' to a bit has no effect. Writing '1' to a bit will set the corresponding bit in the OUT register, which sets the output drive level high for I/O pins configured as outputs via the Data Direction register (DIR). For pins configured as inputs via Data Direction register (DIR) with pull enabled via the Pull Enable register (PULLEN), these bits will set the input pull direction to an internal pull-up. Value Description 0 The corresponding I/O pin in the group will keep its configuration.

1 The corresponding I/O pin output is driven high, or the input is connected to an internal pull-

28.8.8 Data Output Value Toggle

Name: OUTTGL Offset: 0x1C Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to toggle the drive level of one or more output I/O pins, without doing a read- modify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Set (OUTSET) and Data Output Value Clear (OUTCLR) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 OUTTGL[31:24] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OUTTGL[23:16] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 OUTTGL[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OUTTGL[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31:0 – OUTTGL[31:0] PORT Data Output Value Toggle Writing '0' to a bit has no effect. Writing '1' to a bit will toggle the corresponding bit in the OUT register, which inverts the output drive level for I/O pins configured as outputs via the Data Direction register (DIR). For pins configured as inputs via Data Direction register (DIR) with pull enabled via the Pull Enable register (PULLEN), these bits will toggle the input pull direction. Value Description 0 The corresponding I/O pin in the PORT group will keep its configuration. 1 The corresponding OUT bit value is toggled. SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 500

28.8.9 Data Input Value

Name: IN Offset: 0x20 Reset: 0x00000000 Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 IN[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 IN[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 IN[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 IN[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – IN[31:0] PORT Data Input Value These bits are cleared when the corresponding I/O pin input sampler detects a logical low level on the input pin. These bits are set when the corresponding I/O pin input sampler detects a logical high level on the input pin. SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 501

28.8.10 Control

Name: CTRL Offset: 0x24 Reset: 0x00000000 Property: PAC Write-Protection Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 SAMPLING[31:24] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SAMPLING[23:16] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SAMPLING[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SAMPLING[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31:0 – SAMPLING[31:0] Input Sampling Mode Configures the input sampling functionality of the I/O pin input samplers, for pins configured as inputs via the Data Direction register (DIR). The input samplers are enabled and disabled in sub-groups of eight. Thus if any pins within a byte request continuous sampling, all pins in that eight pin sub-group will be continuously sampled. Value Description 0 On demand sampling of I/O pin is enabled. 1 Continuous sampling of I/O pin is enabled. SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 502

28.8.11 Write Configuration

Name: WRCONFIG Offset: 0x28 Reset: 0x00000000 Property: PAC Write-Protection, Write-Only Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. This write-only register is used to configure several pins simultaneously with the same configuration and/or peripheral multiplexing. In order to avoid side effect of non-atomic access, 8-bit or 16-bit writes to this register will have no effect. Reading this register always returns zero. Bit 31 30 29 28 27 26 25 24 HWSEL WRPINCFG WRPMUX PMUX[3:0] Access W W W W W W W Reset 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DRVSTR PULLEN INEN PMUXEN Access W W W W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 PINMASK[15:8] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PINMASK[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 31 – HWSEL Half-Word Select This bit selects the half-word field of a 32-PORT group to be reconfigured in the atomic write operation. This bit will always read as zero. Value Description 0 The lower 16 pins of the PORT group will be configured. 1 The upper 16 pins of the PORT group will be configured. SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 503

Bit 30 – WRPINCFG Write PINCFG This bit determines whether the atomic write operation will update the Pin Configuration register (PINCFGy) or not for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits. Writing '0' to this bit has no effect. Writing '1' to this bit updates the configuration of the selected pins with the written WRCONFIG.DRVSTR, This bit will always read as zero. Value Description 0 The PINCFGy registers of the selected pins will not be updated. 1 The PINCFGy registers of the selected pins will be updated. Bit 28 – WRPMUX Write PMUX This bit determines whether the atomic write operation will update the Peripheral Multiplexing register (PMUXn) or not for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits. Writing '0' to this bit has no effect. Writing '1' to this bit updates the pin multiplexer configuration of the selected pins with the written WRCONFIG. PMUX value. This bit will always read as zero. Value Description 0 The PMUXn registers of the selected pins will not be updated. 1 The PMUXn registers of the selected pins will be updated. Bits 27:24 – PMUX[3:0] Peripheral Multiplexing These bits determine the new value written to the Peripheral Multiplexing register (PMUXn) for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPMUX bit is set. These bits will always read as zero. Bit 22 – DRVSTR Output Driver Strength Selection This bit determines the new value written to PINCFGy.DRVSTR for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set. This bit will always read as zero. Bit 18 – PULLEN Pull Enable This bit determines the new value written to PINCFGy.PULLEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set. This bit will always read as zero. Bit 17 – INEN Input Enable This bit determines the new value written to PINCFGy.INEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set. This bit will always read as zero. Bit 16 – PMUXEN Peripheral Multiplexer Enable This bit determines the new value written to PINCFGy.PMUXEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set. This bit will always read as zero. SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 504

Bits 15:0 – PINMASK[15:0] Pin Mask for Multiple Pin Configuration These bits select the pins to be configured within the half-word group selected by the WRCONFIG.HWSEL bit. These bits will always read as zero. Value Description 0 The configuration of the corresponding I/O pin in the half-word group will be left unchanged. 1 The configuration of the corresponding I/O pin in the half-word PORT group will be updated. SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 505

28.8.12 Event Input Control

Name: EVCTRL Offset: 0x2C Reset: 0x00000000 Property: PAC Write-Protection Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. There are up to four input event pins for each PORT group. Each byte of this register addresses one Event input pin. Bit 31 30 29 28 27 26 25 24 PORTEIx EVACTx[1:0] PIDx[4:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 PORTEIx EVACTx[1:0] PIDx[4:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 PORTEIx EVACTx[1:0] PIDx[4:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PORTEIx EVACTx[1:0] PIDx[4:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31,23,15,7 – PORTEIx PORT Event Input Enable x [x = 3..0] Value Description 0 The event action x (EVACTx) will not be triggered on any incoming event. 1 The event action x (EVACTx) will be triggered on any incoming event. Bits 30:29, 22:21,14:13,6:5 – EVACTx PORT Event Action x [x = 3..0] These bits define the event action the PORT will perform on event input x. See also Table 28-4. Bits 28:24,20:16,12:8,4:0 – PIDx PORT Event Pin Identifier x [x = 3..0] These bits define the I/O pin on which the event action will be performed, according to Table 28-5. SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 506

Table 28-4. PORT Event x Action ( x = [3..0] ) Value Name Description 0x0 OUT Output register of pin will be set to level of event. 0x1 SET Set output register of pin on event. 0x2 CLR Clear output register of pin on event. 0x3 TGL Toggle output register of pin on event. Table 28-5. PORT Event x Pin Identifier ( x = [3..0] ) Value Name Description 0x0 PIN0 Event action to be executed on PIN 0. 0x1 PIN1 Event action to be executed on PIN 1. 0x31 PIN31 Event action to be executed on PIN 31. SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 507

28.8.13 Peripheral Multiplexing n

Name: PMUX Offset: 0x30 + n*0x01 [n=0..15] Property: PAC Write-Protection Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. There are up to 16 Peripheral Multiplexing registers in each group, one for every set of two subsequent I/O lines. The n denotes the number of the set of I/O lines. Bit 7 6 5 4 3 2 1 0 PMUXO[3:0] PMUXE[3:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 7:4 – PMUXO[3:0] Peripheral Multiplexing for Odd-Numbered Pin These bits select the peripheral function for odd-numbered pins (2*n + 1) of a PORT group, if the corresponding PINCFGy.PMUXEN bit is '1'. Not all possible values for this selection may be valid. For more details, refer to the I/O Multiplexing and Considerations. PMUXO[3:0] Name Description 0x0 A Peripheral function A selected 0x1 B Peripheral function B selected 0x2 C Peripheral function C selected 0x3 D Peripheral function D selected 0x4 E Peripheral function E selected 0x5 F Peripheral function F selected 0x6 G Peripheral function G selected 0x7 H Peripheral function H selected 0x8 I Peripheral function I selected 0x9 - Reserved 0xA - Reserved 0xB - Reserved 0xC - Reserved SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 508

PMUXO[3:0] Name Description 0xD - Reserved 0xE-0xF - Reserved Bits 3:0 – PMUXE[3:0] Peripheral Multiplexing for Even-Numbered Pin These bits select the peripheral function for even-numbered pins (2*n) of a PORT group, if the corresponding PINCFGy.PMUXEN bit is '1'. Not all possible values for this selection may be valid. For more details, refer to the I/O Multiplexing and Considerations. PMUXE[3:0] Name Description 0x0 A Peripheral function A selected 0x1 B Peripheral function B selected 0x2 C Peripheral function C selected 0x3 D Peripheral function D selected 0x4 E Peripheral function E selected 0x5 F Peripheral function F selected 0x6 G Peripheral function G selected 0x7 H Peripheral function H selected 0x8 I Peripheral function I selected 0x9 - Reserved 0xA - Reserved 0xB - Reserved 0xC - Reserved 0xD - Reserved 0xE-0xF - Reserved Related Links 6. I/O Multiplexing and Considerations SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 509

28.8.14 Pin Configuration

Name: PINCFG Offset: 0x40 + n*0x01 [n=0..31] Reset: 0x00 Property: PAC Write-Protection Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. There are up to 32 Pin Configuration registers in each PORT group, one for each I/O line. Bit 7 6 5 4 3 2 1 0 DRVSTR PULLEN INEN PMUXEN Access RW RW RW RW Reset 0 0 0 0 Bit 6 – DRVSTR Output Driver Strength Selection This bit controls the output driver strength of an I/O pin configured as an output. Value Description 0 Pin drive strength is set to normal drive strength. 1 Pin drive strength is set to stronger drive strength. Bit 2 – PULLEN Pull Enable This bit enables the internal pull-up or pull-down resistor of an I/O pin configured as an input. Value Description 0 Internal pull resistor is disabled, and the input is in a high-impedance configuration.

1 Internal pull resistor is enabled, and the input is driven to a defined logic level in the absence

of external input. Bit 1 – INEN Input Enable This bit controls the input buffer of an I/O pin configured as either an input or output. Writing a zero to this bit disables the input buffer completely, preventing read-back of the physical pin state when the pin is configured as either an input or output. Value Description 0 Input buffer for the I/O pin is disabled, and the input value will not be sampled. 1 Input buffer for the I/O pin is enabled, and the input value will be sampled when required. Bit 0 – PMUXEN Peripheral Multiplexer Enable This bit enables or disables the peripheral multiplexer selection set in the Peripheral Multiplexing register (PMUXn) to enable or disable alternative peripheral control over an I/O pin direction and output drive value. Writing a zero to this bit allows the PORT to control the pad direction via the Data Direction register (DIR) and output drive value via the Data Output Value register (OUT). The peripheral multiplexer value in SAM C20/C21 Family Data Sheet PORT - I/O Pin Controller © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 510

PMUXn is ignored. Writing '1' to this bit enables the peripheral selection in PMUXn to control the pad. In this configuration, the physical pin state may still be read from the Data Input Value register (IN) if PINCFGn.INEN is set. Value Description

0 The peripheral multiplexer selection is disabled, and the PORT registers control the direction

and output drive value.

1 The peripheral multiplexer selection is enabled, and the selected peripheral function controls

EVSYS – Event System

29.1 Overview

The Event System (EVSYS) allows autonomous, low-latency and configurable communication between peripherals. Several peripherals can be configured to generate and/or respond to signals known as events. The exact condition to generate an event, or the action taken upon receiving an event, is specific to each peripheral. Peripherals that respond to events are called event users. Peripherals that generate events are called event generators. A peripheral can have one or more event generators and can have one or more event users. Communication is made without CPU intervention and without consuming system resources such as bus or RAM bandwidth. This reduces the load on the CPU and other system resources, compared to a traditional interrupt-based system.

29.2 Features

12 configurable event channels, where each channel can: – Be connected to any event generator. – Provide a pure asynchronous, resynchronized or synchronous path
87 event generators.
47 event users.
Configurable edge detector.
Peripherals can be event generators, event users, or both.
SleepWalking and interrupt for operation in sleep modes.
Software event generation.
Each event user can choose which channel to respond to.

29.3 Block Diagram

Figure 29-1. Event System Block Diagram USER x+1 Event Channel m Event Channel 1 Event Channel 0 USER x D Q R Synchronized Path Asynchronous Path Edge Detector CHANNEL0.EDGSEL CHANNEL0.PATH EVT D Q R D Q R D Q R Resynchronized Path D Q R D Q R D Q R SWEVT.CHANNEL0 PERIPHERAL n PERIPHERAL0 CHANNEL0.EVGEN USER.CHANNELx Channel_EVT_0 EVT ACK Channel_EVT_m Clock Request [m:0] To Peripheral x Peripheral x GCLK_EVSYS_0 SleepWalking Detector Event Acknowledge SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 512

29.4 Signal Description

Not applicable.

29.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

29.5.1 I/O Lines

Not applicable.

29.5.2 Power Management

The EVSYS can be used to wake up the CPU from all sleep modes, even if the clock used by the EVSYS channel and the EVSYS bus clock are disabled. Refer to the PM – Power Manager for details on the different sleep modes. Although the clock for the EVSYS is stopped, the device still can wake up the EVSYS clock. Some event generators can generate an event when their clocks are stopped. The generic clock for the channel (GCLK_EVSYS_CHANNEL_n) will be restarted if that channel uses a synchronized path or a resynchronized path. It does not need to wake the system from sleep. Related Links 19. PM – Power Manager

29.5.3 Clocks

The EVSYS bus clock (CLK_EVSYS_APB) can be enabled and disabled in the Main Clock module, and the default state of CLK_EVSYS_APB can be found in Peripheral Clock Masking. Each EVSYS channel has a dedicated generic clock (GCLK_EVSYS_CHANNEL_n). These are used for event detection and propagation for each channel. These clocks must be configured and enabled in the generic clock controller before using the EVSYS. Refer to GCLK - Generic Clock Controller for details. Related Links

GCLK - Generic Clock Controller

29.5.4 DMA

Not applicable.

29.5.5 Interrupts

The interrupt request line is connected to the Interrupt Controller. Using the EVSYS interrupts requires the interrupt controller to be configured first. Refer to Nested Vector Interrupt Controller for details. Related Links

29.5.6 Events

Not applicable.

29.5.7 Debug Operation

When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper operation or SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 513

data loss may result during debugging. This peripheral can be forced to halt operation during debugging - refer to the Debug Control (DBGCTRL) register for details.

29.5.8 Register Access Protection

Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following:

Channel Status (CHSTATUS)
Interrupt Flag Status and Clear register (INTFLAG) Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. Write-protection does not apply for accesses through an external debugger.

29.5.9 Analog Connections

Not applicable.

29.6 Functional Description

29.6.1 Principle of Operation

The Event System consists of several channels which route the internal events from peripherals (generators) to other internal peripherals or I/O pins (users). Each event generator can be selected as source for multiple channels, but a channel cannot be set to use multiple event generators at the same time. A channel path can be configured in asynchronous, synchronous or resynchronized mode of operation. The mode of operation must be selected based on the requirements of the application. When using synchronous or resynchronized path, the Event System includes options to transfer events to users when rising, falling or both edges are detected on event generators. For further details, refer to the Channel Path section of this chapter.

29.6.2 Basic Operation

29.6.2.1 Initialization

Before enabling event routing within the system, the Event Users Multiplexer and Event Channels must be selected in the Event System (EVSYS), and the two peripherals that generate and use the event have to be configured. The recommended sequence is: 1. In the event generator peripheral, enable output of event by writing a '1' to the respective Event Output Enable bit ("EO") in the peripheral's Event Control register (e.g., TCC.EVCTRL.MCEO1, 2. Configure the EVSYS: 2.1. Configure the Event User multiplexer by writing the respective EVSYS.USERm register, see also 29.6.2.3 User Multiplexer Setup. 2.2. Configure the Event Channel by writing the respective EVSYS.CHANNELn register, see also 29.6.2.4 Event System Channel. 3. Configure the action to be executed by the event user peripheral by writing to the Event Action bits (EVACT) in the respective Event control register (e.g., TC.EVCTRL.EVACT, PDEC.EVCTRL.EVACT). Note: not all peripherals require this step. SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 514

In the event user peripheral, enable event input by writing a '1' to the respective Event Input Enable bit ("EI") in the peripheral's Event Control register (e.g., AC.EVCTRL.IVEI0, ADC.EVCTRL.STARTEI).

29.6.2.2 Enabling, Disabling, and Resetting

The EVSYS is always enabled. The EVSYS is reset by writing a ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the EVSYS will be reset to their initial state and all ongoing events will be canceled. Refer to CTRLA.SWRST register for details.

29.6.2.3 User Multiplexer Setup

The user multiplexer defines the channel to be connected to which event user. Each user multiplexer is dedicated to one event user. A user multiplexer receives all event channels output and must be configured to select one of these channels, as shown in Block Diagram section. The channel is selected with the Channel bit group in the User register (USERm.CHANNEL). The user multiplexer must always be configured before the channel. A list of all user multiplexers is found in the User (USERm) register description. Related Links

29.8.8 USERm

29.6.2.4 Event System Channel

An event channel can select one event from a list of event generators. Depending on configuration, the selected event could be synchronized, resynchronized or asynchronously sent to the users. When synchronization or resynchronization is required, the channel includes an internal edge detector, allowing the Event System to generate internal events when rising, falling or both edges are detected on the selected event generator. An event channel is able to generate internal events for the specific software commands. A channel block diagram is shown in Block Diagram section.

29.6.2.5 Event Generators

Each event channel can receive the events form all event generators. All event generators are listed in the Event Generator bit field in the Channel n register (CHANNELn.EVGEN). For details on event generation, refer to the corresponding module chapter. The channel event generator is selected by the Event Generator bit group in the Channel register (CHANNELn.EVGEN). By default, the channels are not connected to any event generators (ie, CHANNELn.EVGEN = 0)

29.6.2.6 Channel Path

There are three different ways to propagate the event from an event generator:

Asynchronous path
Synchronous path
Resynchronized path The path is decided by writing to the Path Selection bit group of the Channel register (CHANNELn.PATH). Asynchronous Path When using the asynchronous path, the events are propagated from the event generator to the event user without intervention from the Event System. The GCLK for this channel (GCLK_EVSYS_CHANNEL_n) is not mandatory, meaning that an event will be propagated to the user without any clock latency. SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 515

When the asynchronous path is selected, the channel cannot generate any interrupts, and the Channel Status register (CHSTATUS) is always zero. The edge detection is not required and must be disabled by software. Each peripheral event user has to select which event edge must trigger internal actions. For further details, refer to each peripheral chapter description. Synchronous Path The synchronous path should be used when the event generator and the event channel share the same generator for the generic clock. If they do not share the same clock, a logic change from the event generator to the event channel might not be detected in the channel, which means that the event will not be propagated to the event user. For details on generic clock generators, refer to GCLK - Generic Clock Controller. When using the synchronous path, the channel is able to generate interrupts. The channel busy n bit in the Channel Status register (CHSTATUS.CHBUSYn) are also updated and available for use. Resynchronized Path The resynchronized path are used when the event generator and the event channel do not share the same generator for the generic clock. When the resynchronized path is used, resynchronization of the event from the event generator is done in the channel. For details on generic clock generators, refer to GCLK - Generic Clock Controller. When the resynchronized path is used, the channel is able to generate interrupts. The channel busy n bits in the Channel Status register (CHSTATUS.CHBUSYn) are also updated and available for use. Related Links 16. GCLK - Generic Clock Controller

29.6.2.7 Edge Detection

When synchronous or resynchronized paths are used, edge detection must be enabled. The event system can execute edge detection in three different ways:

Generate an event only on the rising edge
Generate an event only on the falling edge
Generate an event on rising and falling edges. Edge detection is selected by writing to the Edge Selection bit group of the Channel register (CHANNELn.EDGSEL).

29.6.2.8 Event Latency

An event from an event generator is propagated to an event user with different latency, depending on event channel configuration.

Asynchronous Path: The maximum routing latency of an external event is related to the internal signal routing and it is device dependent.
Synchronous Path: The maximum routing latency of an external event is one GCLK_EVSYS_CHANNEL_n clock cycle.
Resynchronized Path: The maximum routing latency of an external event is three GCLK_EVSYS_CHANNEL_n clock cycles. The maximum propagation latency of a user event to the peripheral clock core domain is three peripheral clock cycles. SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 516

The event generators, event channel and event user clocks ratio must be selected in relation with the internal event latency constraints. Events propagation or event actions in peripherals may be lost if the clock setup violates the internal latencies.

29.6.2.9 The Overrun Channel n Interrupt

The Overrun Channel n interrupt flag in the Interrupt Flag Status and Clear register (CHINTFLAGn.OVR) will be set, and the optional interrupt will be generated in the following cases:

One or more event users on channel n is not ready when there is a new event.
An event occurs when the previous event on channel m has not been handled by all event users connected to that channel. The flag will only be set when using synchronous or resynchronized paths. In the case of asynchronous path, the CHINTFLAGn.OVR is always read as zero.

29.6.2.10 The Event Detected Channel n Interrupt

The Event Detected Channel n interrupt flag in the Interrupt Flag Status and Clear register (CHINTFLAGn.EVD) is set when an event coming from the event generator configured on channel n is detected. The flag will only be set when using a synchronous or resynchronized path. In the case of asynchronous path, the CHINTFLAGn.EVD is always zero.

29.6.2.11 Channel Status

The Channel Status register (CHSTATUS) shows the status of the channels when using a synchronous or resynchronized path. There are two different status bits in CHSTATUS for each of the available channels:

The CHSTATUSn.BUSYCH bit will be set when an event on the corresponding channel n has not been handled by all event users connected to that channel.
The CHSTATUSn.RDYUSR bit will be set when all event users connected to the corresponding channel are ready to handle incoming events on that channel.

29.6.2.12 Software Event

A software event can be initiated on a channel by setting the Channel n bit in the Software Event register (SWEVT.CHANNELn) to ‘1’. Then the software event can be serviced as any event generator; i.e., when the bit is set to ‘1’, an event will be generated on the respective channel.

29.6.3 Interrupts

The EVSYS has the following interrupt sources:

Overrun Channel n interrupt (OVRn): for details, refer to 29.6.2.9 The Overrun Channel n Interrupt.
Event Detected Channel n interrupt (EVDn): for details, refer to 29.6.2.10 The Event Detected Channel n Interrupt. These interrupts events are asynchronous wake-up sources. See Sleep Mode Controller. Each interrupt source has an interrupt flag which is in the Interrupt Flag Status and Clear (INTFLAG) register. The flag is set when the interrupt is issued. Each interrupt event can be individually enabled by setting a ‘1’ to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by setting a ‘1’ to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt event is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt event works until the interrupt flag is cleared, the interrupt is disabled, or the Event System is reset. See

29.8.5 INTFLAG

All interrupt events from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. Refer to the Nested Vector Interrupt Controller for details. The event user must read the INTFLAG register to determine what the interrupt condition is. Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector Interrupt Controller for details. Related Links

29.6.4 Sleep Mode Operation

The EVSYS can generate interrupts to wake up the device from any sleep mode. To be able to run in standby, the Run in Standby bit in the Channel register (CHANNELn.RUNSTDBY) must be set to ‘1’. When the Generic Clock On Demand bit in Channel register (CHANNELn.ONDEMAND) is set to ‘1’ and the event generator is detected, the event channel will request its clock (GCLK_EVSYS_CHANNEL_n). The event latency for a resynchronized channel path will increase by two GCLK_EVSYS_CHANNEL_n clock (i.e., up to five GCLK_EVSYS_CHANNEL_n clock cycles). A channel will behave differently in different sleep modes regarding to CHANNELn.RUNSTDBY and CHANNELn.ONDEMAND, as shown in the table below: Table 29-1. Event Channel Sleep Behavior CHANNELn.ONDEMAN D CHANNELn.RUNSTDB Y Sleep Behavior 0 0 Only run in IDLE sleep mode if an event must be propagated. Disabled in STANDBY sleep mode. 0 1 Always run in IDLE and STANDBY sleep modes. 1 0 Only run in IDLE sleep mode if an event must be propagated. Disabled in STANDBY sleep mode. Two GCLK_EVSYS_n latency added in RESYNC path before the event is propagated internally. 1 1 Always run in IDLE and STANDBY sleep modes. Two GCLK_EVSYS_n latency added in RESYNC path before the event is propagated internally.

29.7 Register Summary

29.7.1 Common Registers

Offset Name Bit Pos. 0x0C CHSTATUS 7:0 USRRDY7 USRRDY6 USRRDY5 USRRDY4 USRRDY3 USRRDY2 USRRDY1 USRRDY0 0x0D 15:8 USRRDY11 USRRDY10 USRRDY9 USRRDY8 0x0E 23:16 CHBUSY7 CHBUSY6 CHBUSY5 CHBUSY4 CHBUSY3 CHBUSY2 CHBUSY1 CHBUSY0 0x0F 31:24 CHBUSY11 CHBUSY10 CHBUSY9 CHBUSY8 0x10 INTENCLR 7:0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 0x11 15:8 OVR11 OVR10 OVR9 OVR8 0x12 23:16 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 0x13 31:24 EVD11 EVD10 EVD9 EVD8 0x14 INTENSET 7:0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 0x15 15:8 OVR11 OVR10 OVR9 OVR8 0x16 23:16 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 0x17 31:24 EVD11 EVD10 EVD9 EVD9 0x18 INTFLAG 7:0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 0x19 15:8 OVR11 OVR10 OVR9 OVR8 0x1A 23:16 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 0x1B 31:24 EVD11 EVD10 EVD9 EVD9 0x1C SWEVT 7:0 CHANNEL[7:0] 0x1D 15:8 CHANNEL[11:8] 0x1E 23:16 0x1F 31:24

29.7.2 CHANNELn

Pos. 0x20 + 0x4*n 7:0 EVGEN[7:0] 0x21 + 0x4*n 15:8 ONDEMAND RUNSTDBY EDGSEL[1:0] PATH[1:0] 0x22 + 0x4*n 23:16 0x23 + 0x4*n 31:24 SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 519

Pos. 0x80 + 0x4*m 7:0 CHANNEL[7:0] 0x81 + 0x4*m 15:8 0x82 + 0x4*m 23:16 0x83 + 0x4*m 31:24

29.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write- Protection" property in each individual register description. Refer to Register Access Protection and PAC - Peripheral Access Controller. Related Links 11. PAC - Peripheral Access Controller SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 520

29.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 SWRST Access W Reset 0 Bit 0 – SWRST Software Reset Writing '0' to this bit has no effect. Writing '1' to this bit resets all registers in the EVSYS to their initial state. Note: Before applying a Software Reset it is recommended to disable the event generators. Related Links 11. PAC - Peripheral Access Controller SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 521

29.8.2 Channel Status

Name: CHSTATUS Offset: 0x0C Reset: 0x000000FF Property: – Bit 31 30 29 28 27 26 25 24 CHBUSYn[11:8] Access R R R R Reset 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CHBUSYn[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 USRRDYn[11:8] Access R R R R Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 USRRDYn[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 1 Bits 27:16 – CHBUSYn[11:0] Channel Busy n [n = 11..0] This bit is cleared when channel n is idle. This bit is set if an event on channel n has not been handled by all event users connected to channel n. Bits 11:0 – USRRDYn[11:0] User Ready for Channel n [n = 11..0] This bit is cleared when at least one of the event users connected to the channel is not ready. This bit is set when all event users connected to channel n are ready to handle incoming events on channel n. Related Links 11. PAC - Peripheral Access Controller SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 522

29.8.3 Interrupt Enable Clear

Name: INTENCLR Offset: 0x10 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 31 30 29 28 27 26 25 24 EVDn[11:8] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 23 22 21 20 19 18 17 16 EVDn[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 OVRn[11:8] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OVRn[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 27:16 – EVDn[11:0] Event Detected Channel n Interrupt Enable [n = 11..0] Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Event Detected Channel n Interrupt Enable bit, which disables the Event Detected Channel n interrupt. Value Description 0 The Event Detected Channel n interrupt is disabled. 1 The Event Detected Channel n interrupt is enabled. Bits 11:0 – OVRn[11:0] Overrun Channel n Interrupt Enable[n = 11..0] Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Overrun Channel n Interrupt Enable bit, which disables the Overrun Channel n interrupt. Value Description 0 The Overrun Channel n interrupt is disabled. 1 The Overrun Channel n interrupt is enabled. Related Links 11. PAC - Peripheral Access Controller SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 523

29.8.4 Interrupt Enable Set

Name: INTENSET Offset: 0x14 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 31 30 29 28 27 26 25 24 EVDn[11:8] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 23 22 21 20 19 18 17 16 EVDn[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 OVRn[11:8] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OVRn[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 27:16 – EVDn[11:0] Event Detected Channel n Interrupt Enable [n = 11..0] Writing '0' to this bit has no effect. Writing '1' to this bit will set the Event Detected Channel n Interrupt Enable bit, which enables the Event Detected Channel n interrupt. Value Description 0 The Event Detected Channel n interrupt is disabled. 1 The Event Detected Channel n interrupt is enabled. Bits 11:0 – OVRn[11:0] Overrun Channel n Interrupt Enable [n = 11..0] Writing '0' to this bit has no effect. Writing '1' to this bit will set the Overrun Channel n Interrupt Enable bit, which disables the Overrun Channel n interrupt. Value Description 0 The Overrun Channel n interrupt is disabled. 1 The Overrun Channel n interrupt is enabled. Related Links 11. PAC - Peripheral Access Controller SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 524

29.8.5 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x18 Reset: 0x00000000 Property: – Bit 31 30 29 28 27 26 25 24 EVDn[11:8] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 23 22 21 20 19 18 17 16 EVDn[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 OVRn[11:8] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OVRn[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 27:16 – EVDn[11:0] Event Detected Channel n [n=11..0] This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and an interrupt request will be generated if INTENCLR/SET.EVDn is '1'. When the event channel path is asynchronous, the EVDn interrupt flag will not be set. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Event Detected Channel n interrupt flag. Bits 11:0 – OVRn[11:0] Overrun Channel n [n=11..0] This flag is set on the next CLK_EVSYS_APB cycle after an overrun channel condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVRn is '1'. There are two possible overrun channel conditions:

One or more of the event users on channel n are not ready when a new event occurs.
An event happens when the previous event on channel n has not yet been handled by all event users. When the event channel path is asynchronous, the OVRn interrupt flag will not be set. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Overrun Detected Channel n interrupt flag. Related Links 11. PAC - Peripheral Access Controller SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 525

29.8.6 Software Event

Name: SWEVT Offset: 0x1C Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 CHANNELn[11:8] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CHANNELn[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 11:0 – CHANNELn[11:0] Channel n Software [n=11..0] Selection Writing '0' to this bit has no effect. Writing '1' to this bit will trigger a software event for the channel n. These bits will always return zero when read. Related Links 11. PAC - Peripheral Access Controller SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 526

29.8.7 Channel

Name: CHANNELn Offset: 0x20+n*0x4 [0..11n=0..11] Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to configure channel n. To write to this register, do a single, 32-bit write of all the configuration data. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 ONDEMAND RUNSTDBY EDGSEL[1:0] PATH[1:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EVGEN[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – ONDEMAND Generic Clock On Demand Value Description

0 Generic clock for a channel is always on, if the channel is configured and generic clock

source is enabled.

1 Generic clock is requested on demand while an event is handled

Bit 14 – RUNSTDBY Run in Standby This bit is used to define the behavior during standby sleep mode. Value Description 0 The channel is disabled in standby sleep mode.

1 The channel is not stopped in standby sleep mode and depends on the

CHANNEL.ONDEMAND Bits 11:10 – EDGSEL[1:0] Edge Detection Selection These bits set the type of edge detection to be used on the channel. These bits must be written to zero when using the asynchronous path. Value Name Description 0x0 NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x1 RISING_EDGE Event detection only on the rising edge of the signal from the event generator SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 527

0x2 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator 0x3 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator Bits 9:8 – PATH[1:0] Path Selection These bits are used to choose which path will be used by the selected channel. The path choice can be limited by the channel source, see the table in 29.8.8 USERm. Value Name Description 0x0 SYNCHRONOUS Synchronous path 0x1 RESYNCHRONIZED Resynchronized path 0x2 ASYNCHRONOUS Asynchronous path 0x3 - Reserved Bits 7:0 – EVGEN[7:0] Event Generator These bits are used to choose the event generator to connect to the selected channel. Table 29-2. Event Generators Value Event Generator Description 0x00 NONE No event generator selected 0x01 OSCCTRL FAIL XOSC Clock Failure 0x02 OSC32KCTRL FAIL XOSC32K Clock Failure 0x03 RTC CMP0 Compare 0 (mode 0 and 1) or Alarm 0 (mode 2) 0x04 RTC CMP1 Compare 1 0x05 RTC OVF Overflow 0x06 RTC PER0 Period 0 0x07 RTC PER1 Period 1 0x08 RTC PER2 Period 2 0x09 RTC PER3 Period 3 0x0A RTC PER4 Period 4 0x0B RTC PER5 Period 5 0x0C RTC PER6 Period 6 0x0D RTC PER7 Period 7 0x0E EIC EXTINT0 External Interrupt 0 0x0F EIC EXTINT1 External Interrupt 1 0x10 EIC EXTINT2 External Interrupt 2 0x11 EIC EXTINT3 External Interrupt 3 0x12 EIC EXTINT4 External Interrupt 4 SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 528

Value Event Generator Description 0x13 EIC EXTINT5 External Interrupt 5 0x14 EIC EXTINT6 External Interrupt 6 0x15 EIC EXTINT7 External Interrupt 7 0x16 EIC EXTINT8 External Interrupt 8 0x17 EIC EXTINT9 External Interrupt 9 0x18 EIC EXTINT10 External Interrupt 10 0x19 EIC EXTINT11 External Interrupt 11 0x1A EIC EXTINT12 External Interrupt 12 0x1B EIC EXTINT13 External Interrupt 13 0x1C EIC EXTINT14 External Interrupt 14 0x1D EIC EXTINT15 External Interrupt 15 0x1E TSENS WINMON- Window Monitor 0x1F DMAC CH0 Channel 0 0x20 DMAC CH1 Channel 1 0x21 DMAC CH2 Channel 2 0x22 DMAC CH3 Channel 3 0x23 TCC0 OVF Overflow 0x24 TCC0 TRG Trig 0x25 TCC0 CNT Counter 0x26 TCC0 MC0 Match/Capture 1 0x27 TCC0 MC1 Match/Capture 1 0x28 TCC0 MC2 Match/Capture 2 0x29 TCC0 MC3 Match/Capture 3 0x2A TCC1 OVF Overflow 0x2B TCC1 TRG Trig 0x2C TCC1 CNT Counter 0x2D TCC1 MC0 Match/Capture 0 0x2E TCC1 MC1 Match/Capture 1 0x2F TCC2 OVF Overflow 0x30 TCC2 TRG Trig 0x31 TCC2 CNT Counter SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 529

Value Event Generator Description 0x32 TCC2 MC0 Match/Capture 0 0x33 TCC2 MC1 Match/Capture 1 0x34 TC0 OVF Overflow/Underflow 0x35 TC0 MC0 Match/Capture 0 0x36 TC0 MC1 Match/Capture 1 0x37 TC1 OVF Overflow/Underflow 0x38 TC1 MC0 Match/Capture 0 0x39 TC1 MC1 Match/Capture 1 0x3A TC2 OVF Overflow/Underflow 0x3B TC2 MC1 Match/Capture 0 0x3C TC2 MC0 Match/Capture 1 0x3D TC3 OVF Overflow/Underflow 0x3E TC3 MC0 Match/Capture 0 0x3F TC3 MC1 Match/Capture 1 0x40 TC4 OVF Overflow/Underflow 0x41 TC4 MC0 Match/Capture 0 0x42 TC4 MC1 Match/Capture 1 0x43 ADC0 RESRDY Result Ready 0x44 ADC0 WINMON Window Monitor 0x45 ADC1 RESRDY Result Ready 0x46 ADC1 WINMON Window Monitor 0x47 SDADC RESRDY Result Ready 0x48 SDADC WINMON Window Monitor 0x49 AC COMP0 Comparator 0 0x4A AC COMP1 Comparator 1 0x4B AC COMP2 Comparator 2 0x4C AC COMP3 Comparator 3 0x4D AC WIN0 Window 0 0x4E AC WIN1 Window 1 0x4F DAC EMPTY Data Buffer Empty 0x50 PTC EOC End of Conversion SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 530

Value Event Generator Description 0x51 PTC WCOMP Window Comparator 0x52 CCL LUTOUT0 CCL output 0x53 CCL LUTOUT1 CCL output 0x54 CCL LUTOUT2 CCL output 0x55 CCL LUT3 CCL output 0x56 PAC ACCERR Access Error 0x57 - Reserved 0x58 TC5 OVF Overflow/Underflow 0x59 TC5 MC0 Match/Capture 0 0x5A TC5 MC1 Match/Capture 1 0x5B TC6 OVF Overflow/Underflow 0x5C TC6 MC0 Match/Capture 0 0x5D TC6 MC1 Match/Capture 1 0x5E TC7 OVF Overflow/Underflow 0x5F TC7 MC0 Match/Capture 0 0x60 TC7 MC1 Match/Capture 1 0x61 - 0xFF - Reserved SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 531

29.8.8 Event User m

Name: USERm Offset: 0x80+m*0x4 [m=0..460..46] Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CHANNEL[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – CHANNEL[7:0] Channel Event Selection These bits are used to select the channel to connect to the event user. Note that to select channel m, the value (m+1) must be written to the USER.CHANNEL bit group. Value Channel Number 0x00 No channel output selected 0x01 0 0x02 1 0x03 2 0x04 3 0x05 4 0x06 5 0x07 6 0x08 7 0x09 8 0x0A 9 SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 532

Table 29-3. User Multiplexer Number USERm User Multiplexer Description Path Type m = 0 TSENS STARTReserved Start measurement- Asynchronous, synchronous, and resynchronized pathsReserved m = 1 PORT EV0 Event 0 Asynchronous path only m = 2 PORT EV1 Event 1 Asynchronous path only m = 3 PORT EV2 Event 2 Asynchronous path only m = 4 PORT EV3 Event 3 Asynchronous path only m = 5 DMAC CH0 Channel 0 Asynchronous, synchronous, and resynchronized paths m = 6 DMAC CH1 Channel 1 Asynchronous, synchronous, and resynchronized paths m = 7 DMAC CH2 Channel 2 Asynchronous, synchronous, and resynchronized paths m = 8 DMAC CH3 Channel 3 Asynchronous, synchronous, and resynchronized paths m = 9 TCC0 EV0 - Asynchronous, synchronous, and resynchronized paths m = 10 TCC0 EV1 - Asynchronous, synchronous, and resynchronized paths m = 11 TCC0 MC0 Match/Capture 0 Asynchronous, synchronous, and resynchronized paths m = 12 TCC0 MC1 Match/Capture 1 Asynchronous, synchronous, and resynchronized paths SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 533

USERm User Multiplexer Description Path Type m = 13 TCC0 MC2 Match/Capture 2 Asynchronous, synchronous, and resynchronized paths m = 14 TCC0 MC3 Match/Capture 3 Asynchronous, synchronous, and resynchronized paths m = 15 TCC1 EV0 - Asynchronous, synchronous, and resynchronized paths m = 16 TCC1 EV1 - Asynchronous, synchronous, and resynchronized paths m = 17 TCC1 MC0 Match/Capture 0 Asynchronous, synchronous, and resynchronized paths m = 18 TCC1 MC1 Match/Capture 1 Asynchronous, synchronous, and resynchronized paths m = 19 TCC2 EV0 - Asynchronous, synchronous, and resynchronized paths m = 20 TCC2 EV1 - Asynchronous, synchronous, and resynchronized paths m = 21 TCC2 MC0 Match/Capture 0 Asynchronous, synchronous, and resynchronized paths m = 22 TCC2 MC1 Match/Capture 1 Asynchronous, synchronous, and resynchronized paths m = 23 TC0 - Asynchronous, synchronous, and resynchronized paths m = 24 TC1 - Asynchronous, synchronous, and resynchronized paths m = 25 TC2 - Asynchronous, synchronous, and resynchronized paths SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 534

USERm User Multiplexer Description Path Type m = 26 TC3 - Asynchronous, synchronous, and resynchronized paths m = 27 TC4 - Asynchronous, synchronous, and resynchronized paths m = 28 ADC0 START ADC start conversion Asynchronous, synchronous, and resynchronized paths m = 29 ADC0 SYNC Flush ADC Asynchronous, synchronous, and resynchronized paths m = 30 ADC1 START ADC start conversion Asynchronous, synchronous, and resynchronized paths m = 31 ADC1 SYNC Flush ADC Asynchronous, synchronous, and resynchronized paths m = 32 SDADC START SADC start conversion Asynchronous path only m = 33 SDADC FLUSH Flush SADC Asynchronous path only m=30 to 33 Reserved - Reserved m = 34 AC COMP0 Start comparator 0 Asynchronous path only m = 35 AC COMP1 Start comparator 1 Asynchronous path only m = 36 AC COMP2 Start comparator 2 Asynchronous path only m = 37 AC COMP3 Start comparator 3 Asynchronous path only m = 38 DAC START DAC start conversion Asynchronous path only m=36 to 38 Reserved - Reserved m = 39 PTC STCONC PTC start conversion Asynchronous path only m = 40 CCL LUTIN 0 CCL input Asynchronous path only m = 41 CCL LUTIN 1 CCL input Asynchronous path only m = 42 CCL LUTIN 2 CCL input Asynchronous path only m = 43 CCL LUTIN 3 CCL input Asynchronous path only m=44 to 46 Reserved - Reserved m=47 TC5 - Asynchronous, synchronous, and resynchronized paths SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 535

USERm User Multiplexer Description Path Type m=48 TC6 - Asynchronous, synchronous, and resynchronized paths m=49 TC7 - Asynchronous, synchronous, and resynchronized paths others Reserved - Reserved SAM C20/C21 Family Data Sheet EVSYS – Event System © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 536

SERCOM – Serial Communication Interface

30.1 Overview

There are up to eight instances of the serial communication interface (SERCOM) peripheral. A SERCOM can be configured to support a number of modes: I2C, SPI, and USART. When an instance of SERCOM is configured and enabled, all of the resources of that SERCOM instance will be dedicated to the selected mode. The SERCOM serial engine consists of a transmitter and receiver, baud-rate generator and address matching functionality. It can use the internal generic clock or an external clock. Using an external clock allows the SERCOM to be operated in all Sleep modes. Related Links 31. SERCOM USART - SERCOM Synchronous and Asynchronous Receiver and Transmitter 32. SERCOM SPI – SERCOM Serial Peripheral Interface 33. SERCOM I2C – Inter-Integrated Circuit

30.2 Features

Interface for configuring into one of the following: – Inter-Integrated Circuit (I2C) Two-wire Serial Interface – System Management Bus (SMBus™) compatible – Serial Peripheral Interface (SPI) – Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
Single transmit buffer and double receive buffer
Baud-rate generator
Address match/mask logic
Operational in all Sleep modes with an external clock source
Can be used with DMA See the Related Links for full feature lists of the interface configurations. Related Links 31. SERCOM USART - SERCOM Synchronous and Asynchronous Receiver and Transmitter 32. SERCOM SPI – SERCOM Serial Peripheral Interface 33. SERCOM I2C – Inter-Integrated Circuit SAM C20/C21 Family Data Sheet SERCOM – Serial Communication Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 537

30.3 Block Diagram

Figure 30-1. SERCOM Block Diagram TX/RX DATACONTROL/STATUS Mode n SERCOM BAUD/ADDR Transmitter Register Interface Serial Engine Receiver Mode 0 Mode 1 Baud Rate Generator Address Match Mode Specific PAD[3:0]

30.4 Signal Description

See the respective SERCOM mode chapters for details. Related Links 31. SERCOM USART - SERCOM Synchronous and Asynchronous Receiver and Transmitter 32. SERCOM SPI – SERCOM Serial Peripheral Interface 33. SERCOM I2C – Inter-Integrated Circuit

30.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

30.5.1 I/O Lines

Using the SERCOM I/O lines requires the I/O pins to be configured using port configuration (PORT). The SERCOM has four internal pads, PAD[3:0], and the signals from I2C, SPI and USART are routed through these SERCOM pads through a multiplexer. The configuration of the multiplexer is available from the different SERCOM modes. Refer to the mode specific chapters for additional information. Related Links 31. SERCOM USART - SERCOM Synchronous and Asynchronous Receiver and Transmitter 32. SERCOM SPI – SERCOM Serial Peripheral Interface 33. SERCOM I2C – Inter-Integrated Circuit 28. PORT - I/O Pin Controller

31.3 Block Diagram

30.5.2 Power Management

The SERCOM can operate in any Sleep mode provided the selected clock source is running. SERCOM interrupts can be configured to wake the device from sleep modes. SAM C20/C21 Family Data Sheet SERCOM – Serial Communication Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 538

PM – Power Manager

30.5.3 Clocks

The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Main Clock Controller. Refer to Peripheral Clock Masking for details and default status of this clock. The SERCOM uses two generic clocks: GCLK_SERCOMx_CORE and GCLK_SERCOMx_SLOW. The core clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while working as a master. The slow clock (GCLK_SERCOMx_SLOW) is only required for certain functions. See specific mode chapters for details. These clocks must be configured and enabled in the Generic Clock Controller (GCLK) before using the SERCOM. The generic clocks are asynchronous to the user interface clock (CLK_SERCOMx_APB). Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains. Refer to 30.6.8 Synchronization for details. Related Links 16. GCLK - Generic Clock Controller 17. MCLK – Main Clock

30.5.4 DMA

The DMA request lines are connected to the DMA Controller (DMAC). The DMAC must be configured before the SERCOM DMA requests are used. Related Links 25. DMAC – Direct Memory Access Controller

30.5.5 Interrupts

The interrupt request line is connected to the Interrupt Controller (NVIC). The NVIC must be configured before the SERCOM interrupts are used. Related Links

30.5.6 Events

Not applicable.

30.5.7 Debug Operation

When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result during debugging. This peripheral can be forced to halt operation during debugging - refer to the Debug Control (DBGCTRL) register for details.

30.5.8 Register Access Protection

All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Interrupt Flag Clear and Status register (INTFLAG)
Status register (STATUS) SAM C20/C21 Family Data Sheet SERCOM – Serial Communication Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 539

Data register (DATA)
Address register (ADDR) Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write- Protection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger. Related Links 11. PAC - Peripheral Access Controller

30.5.9 Analog Connections

Not applicable.

30.6 Functional Description

30.6.1 Principle of Operation

The basic structure of the SERCOM serial engine is shown in Figure 30-2. Labels in capital letters are synchronous to the system clock and accessible by the CPU; labels in lowercase letters can be configured to run on the GCLK_SERCOMx_CORE clock or an external clock. Figure 30-2. SERCOM Serial Engine Transmitter Baud Rate Generator Equal Selectable Internal Clk (GCLK) Ext Clk Receiver Address Match Baud Rate Generator TX Shift Register RX Shift Register RX BufferStatus BAUD TX DATA ADDR/ADDRMASK RX DATASTATUS 1/- /2- /16 The transmitter consists of a single write buffer and a shift register. The receiver consists of a one-level (I2C), two-level (USART, SPI) receive buffer and a shift register. The baud-rate generator is capable of running on the GCLK_SERCOMx_CORE clock or an external clock. Address matching logic is included for SPI and I2C operation. SAM C20/C21 Family Data Sheet SERCOM – Serial Communication Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 540

30.6.2 Basic Operation

30.6.2.1 Initialization

The SERCOM must be configured to the desired mode by writing the Operating Mode bits in the Control A register (CTRLA.MODE). Refer to table SERCOM Modes for details. Table 30-1. SERCOM Modes CTRLA.MODE Description 0x0 USART with external clock 0x1 USART with internal clock 0x2 SPI in slave operation 0x3 SPI in master operation 0x4 I 2C slave operation 0x5 I 2C master operation 0x6-0x7 Reserved For further initialization information, see the respective SERCOM mode chapters: Related Links 31. SERCOM USART - SERCOM Synchronous and Asynchronous Receiver and Transmitter 32. SERCOM SPI – SERCOM Serial Peripheral Interface 33. SERCOM I2C – Inter-Integrated Circuit

30.6.2.2 Enabling, Disabling, and Resetting

This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and disabled by writing '0' to it. Writing ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of this peripheral to their initial states, except the DBGCTRL register, and the peripheral is disabled. Refer to the CTRLA register description for details.

30.6.2.3 Clock Generation – Baud-Rate Generator

The baud-rate generator, as shown in Figure 30-3, generates internal clocks for asynchronous and synchronous communication. The output frequency (fBAUD) is determined by the Baud register (BAUD) setting and the baud reference frequency (fref). The baud reference clock is the serial engine clock, and it can be internal or external. For asynchronous communication, the /16 (divide-by-16) output is used when transmitting, whereas the /1 (divide-by-1) output is used while receiving. For synchronous communication, the /2 (divide-by-2) output is used. This functionality is automatically configured, depending on the selected operating mode. SAM C20/C21 Family Data Sheet SERCOM – Serial Communication Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 541

Figure 30-3. Baud Rate Generator Base Period Selectable Internal Clk (GCLK) Ext Clk CTRLA.MODE[0] fref Clock Recovery Tx Clk Rx Clk CTRLA.MODE /2 /8 /1 /2 /16 Baud Rate Generator Table 30-2 contains equations for the baud rate (in bits per second) and the BAUD register value for each operating mode. For asynchronous operation, the BAUD register value is 16 bits (0 to 65,535). For synchronous operation, the BAUD register value is 8 bits (0 to 255). Table 30-2. Baud Rate Equations Operating Mode Condition Baud Rate (Bits Per Second) BAUD Register Value Calculation Asynchronous ???? ???? − ͳ The baud rate error is represented by the following formula: Error = ͳ − ExpectedBaudRate ActualBaudRate

30.6.2.3.1 Asynchronous Arithmetic Mode BAUD Value Selection

The formula given for fBAUD calculates the average frequency over 65536 fref cycles. Although the BAUD register can be set to any value between 0 and 65536, the actual average frequency of fBAUD over a single frame is more granular. The BAUD register values that will affect the average frequency over a single frame lead to an integer increase in the cycles per frame (CPF) ??? = ???? ? + ? where

D represent the data bits per frame
S represent the sum of start and first stop bits, if present. Table 30-3 shows the BAUD register value versus baud frequency fBAUD at a serial engine frequency of 48MHz. This assumes a D value of 8 bits and an S value of 2 bits (10 bits, including start and stop bits). SAM C20/C21 Family Data Sheet SERCOM – Serial Communication Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 542

Table 30-3. BAUD Register Value vs. Baud Frequency BAUD Register Value Serial Engine CPF f BAUD at 48MHz Serial Engine Frequency (fREF) 0 – 406 160 3MHz 407 – 808 161 2.981MHz 809 – 1205 162 2.963MHz 65206 31775 15.11kHz 65207 31871 15.06kHz 65208 31969 15.01kHz

30.6.3 Additional Features

30.6.3.1 Address Match and Mask

The SERCOM address match and mask feature is capable of matching either one address, two unique addresses, or a range of addresses with a mask, based on the mode selected. The match uses seven or eight bits, depending on the mode.

30.6.3.1.1 Address With Mask

An address written to the Address bits in the Address register (ADDR.ADDR), and a mask written to the Address Mask bits in the Address register (ADDR.ADDRMASK) will yield an address match. All bits that are masked are not included in the match. Note that writing the ADDR.ADDRMASK to 'all zeros' will match a single unique address, while writing ADDR.ADDRMASK to 'all ones' will result in all addresses being accepted. Figure 30-4. Address With Mask rx shift register ADDRMASK ADDR == Match

30.6.3.1.2 Two Unique Addresses

The two addresses written to ADDR and ADDRMASK will cause a match. Figure 30-5. Two Unique Addresses ADDRMASK rx shift register ADDR Match SAM C20/C21 Family Data Sheet SERCOM – Serial Communication Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 543

30.6.3.1.3 Address Range

The range of addresses between and including ADDR.ADDR and ADDR.ADDRMASK will cause a match. ADDR.ADDR and ADDR.ADDRMASK can be set to any two addresses, with ADDR.ADDR acting as the upper limit and ADDR.ADDRMASK acting as the lower limit. Figure 30-6. Address Range ADDRMASK rx shift register ADDR == Match

30.6.4 DMA Operation

The available DMA interrupts and their depend on the operation mode of the SERCOM peripheral. Refer to the Functional Description sections of the respective SERCOM mode. Related Links 31. SERCOM USART - SERCOM Synchronous and Asynchronous Receiver and Transmitter 32. SERCOM SPI – SERCOM Serial Peripheral Interface 33. SERCOM I2C – Inter-Integrated Circuit

30.6.5 Interrupts

Interrupt sources are mode-specific. See the respective SERCOM mode chapters for details. Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the interrupt condition is met. Each interrupt can be individually enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the SERCOM is reset. For details on clearing interrupt flags, refer to the INTFLAG register description. The value of INTFLAG indicates which interrupt condition occurred. The user must read the INTFLAG register to determine which interrupt condition is present. Note: Interrupts must be globally enabled for interrupt requests. Related Links

30.6.6 Events

Not applicable.

30.6.7 Sleep Mode Operation

The peripheral can operate in any sleep mode where the selected serial clock is running. This clock can be external or generated by the internal baud-rate generator. The SERCOM interrupts can be used to wake up the device from sleep modes. Refer to the different SERCOM mode chapters for details.

30.6.8 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. SAM C20/C21 Family Data Sheet SERCOM – Serial Communication Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 544

Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Required read-synchronization is denoted by the "Read-Synchronized" property in the register description. Related Links SAM C20/C21 Family Data Sheet SERCOM – Serial Communication Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 545

SERCOM USART - SERCOM Synchronous and Asynchronous Receiver and Transmitter

31.1 Overview

The Universal Synchronous and Asynchronous Receiver and Transmitter (USART) is one of the available modes in the Serial Communication Interface (SERCOM). The USART uses the SERCOM transmitter and receiver, see 31.3 Block Diagram. Labels in uppercase letters are synchronous to CLK_SERCOMx_APB and accessible for CPU. Labels in lowercase letters can be programmed to run on the internal generic clock or an external clock. The transmitter consists of a single write buffer, a shift register, and control logic for different frame formats. The write buffer support data transmission without any delay between frames. The receiver consists of a two-level receive buffer and a shift register. Status information of the received data is available for error checking. Data and clock recovery units ensure robust synchronization and noise filtering during asynchronous data reception. Related Links 30. SERCOM – Serial Communication Interface

31.2 USART Features

Full-duplex operation
Asynchronous (with clock reconstruction) or synchronous operation
Internal or external clock source for asynchronous and synchronous operation
Baud-rate generator
Supports serial frames with 5, 6, 7, 8 or 9 data bits and 1 or 2 stop bits
Odd or even parity generation and parity check
Selectable LSB- or MSB-first data transfer
Buffer overflow and frame error detection
Noise filtering, including false start-bit detection and digital low-pass filter
Collision detection
Can operate in all sleep modes
Operation at speeds up to half the system clock for internally generated clocks
Operation at speeds up to the system clock for externally generated clocks
RTS and CTS flow control
IrDA modulation and demodulation up to 115.2kbps
LIN master support
RS485 Support
Start-of-frame detection
Can work with DMA Related Links

Figure 31-1. USART Block Diagram GCLK (internal) XCK BAUD Baud Rate Generator TX DATA TX Shift Register RX Shift Register STATUS Status RX DATA RX Buffer TxD RxD CTRLA.MODE /1 - /2 - /16 CTRLA.MODE

31.4 Signal Description

Table 31-1. SERCOM USART Signals Signal Name Type Description PAD[3:0] Digital I/O General SERCOM pins One signal can be mapped to one of several pins. Related Links 6. I/O Multiplexing and Considerations

31.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

31.5.1 I/O Lines

Using the USART’s I/O lines requires the I/O pins to be configured using the I/O Pin Controller (PORT). When the SERCOM is used in USART mode, the SERCOM controls the direction and value of the I/O pins according to the table below. Both PORT control bits PINCFGn.PULLEN and PINCFGn.DRVSTR are still effective. If the receiver or transmitter is disabled, these pins can be used for other purposes. Table 31-2. USART Pin Configuration Pin Pin Configuration TxD Output RxD Input XCK Output or input SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 547

The combined configuration of PORT and the Transmit Data Pinout and Receive Data Pinout bit fields in the Control A register (CTRLA.TXPO and CTRLA.RXPO, respectively) will define the physical position of the USART signals in Table 31-2. Related Links 28. PORT - I/O Pin Controller

31.5.2 Power Management

This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake up the device from sleep modes. Related Links 19. PM – Power Manager

31.5.3 Clocks

The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Main Clock Controller. Refer to Peripheral Clock Masking for details and default status of this clock. A generic clock (GCLK_SERCOMx_CORE) is required to clock the SERCOMx_CORE. This clock must be configured and enabled in the Generic Clock Controller before using the SERCOMx_CORE. Refer to GCLK - Generic Clock Controller for details. This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Therefore, writing to certain registers will require synchronization to the clock domains. Refer to Synchronization for further details. Related Links

31.6.6 Synchronization

GCLK - Generic Clock Controller

31.5.4 DMA

31.5.5 Interrupts

The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral, the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt Controller for details. Related Links

31.5.6 Events

Not applicable.

31.5.7 Debug Operation

When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper operation or SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 548

data loss may result during debugging. This peripheral can be forced to halt operation during debugging - refer to the Debug Control (DBGCTRL) register for details. Related Links

31.8.12 DBGCTRL

31.5.8 Register Access Protection

Registers with write-access can be write-protected optionally by the peripheral access controller (PAC). PAC Write-Protection is not available for the following registers:

Interrupt Flag Clear and Status register (INTFLAG)
Status register (STATUS)
Data register (DATA) Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger. Related Links 11. PAC - Peripheral Access Controller

31.5.9 Analog Connections

Not applicable.

31.6 Functional Description

31.6.1 Principle of Operation

The USART uses the following lines for data transfer:

RxD for receiving
TxD for transmitting
XCK for the transmission clock in synchronous operation USART data transfer is frame based. A serial frame consists of:
1 start bit
From 5 to 9 data bits (MSB or LSB first)
No, even or odd parity bit
1 or 2 stop bits A frame starts with the start bit followed by one character of data bits. If enabled, the parity bit is inserted after the data bits and before the first stop bit. After the stop bit(s) of a frame, either the next frame can follow immediately, or the communication line can return to the idle (high) state. The figure below illustrates the possible frame formats. Brackets denote optional bits. Figure 31-2. Frame Formats Frame (IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] [St/IDL] SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 549

St Start bit. Signal is always low. n, [n] Data bits. 0 to [5..9] [P] Parity bit. Either odd or even. Sp, [Sp] Stop bit. Signal is always high. IDLE No frame is transferred on the communication line. Signal is always high in this state.

31.6.2 Basic Operation

31.6.2.1 Initialization

The following registers are enable-protected, meaning they can only be written when the USART is disabled (CTRL.ENABLE=0):

Control A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits.
Control B register (CTRLB), except the Receiver Enable (RXEN) and Transmitter Enable (TXEN) bits.
Baud register (BAUD) When the USART is enabled or is being enabled (CTRLA.ENABLE=1), any writing attempt to these registers will be discarded. If the peripheral is being disabled, writing to these registers will be executed after disabling is completed. Enable-protection is denoted by the "Enable-Protection" property in the register description. Before the USART is enabled, it must be configured by these steps: 1. Select either external (0x0) or internal clock (0x1) by writing the Operating Mode value in the CTRLA register (CTRLA.MODE). 2. Select either asynchronous (0) or or synchronous (1) communication mode by writing the Communication Mode bit in the CTRLA register (CTRLA.CMODE). 3. Select pin for receive data by writing the Receive Data Pinout value in the CTRLA register (CTRLA.RXPO). 4. Select pads for the transmitter and external clock by writing the Transmit Data Pinout bit in the CTRLA register (CTRLA.TXPO). 5. Configure the Character Size field in the CTRLB register (CTRLB.CHSIZE) for character size. 6. Set the Data Order bit in the CTRLA register (CTRLA.DORD) to determine MSB- or LSB-first data transmission. 7. To use parity mode: 7.1. Enable parity mode by writing 0x1 to the Frame Format field in the CTRLA register (CTRLA.FORM). 7.2. Configure the Parity Mode bit in the CTRLB register (CTRLB.PMODE) for even or odd parity. 8. Configure the number of stop bits in the Stop Bit Mode bit in the CTRLB register (CTRLB.SBMODE). 9. When using an internal clock, write the Baud register (BAUD) to generate the desired baud rate. 10. Enable the transmitter and receiver by writing '1' to the Receiver Enable and Transmitter Enable bits in the CTRLB register (CTRLB.RXEN and CTRLB.TXEN). SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 550

31.6.2.2 Enabling, Disabling, and Resetting

31.6.2.3 Clock Generation and Selection

For both synchronous and asynchronous modes, the clock used for shifting and sampling data can be generated internally by the SERCOM baud-rate generator or supplied externally through the XCK line. The synchronous mode is selected by writing a '1' to the Communication Mode bit in the Control A register (CTRLA.CMODE), the asynchronous mode is selected by writing a zero to CTRLA.CMODE. The internal clock source is selected by writing 0x1 to the Operation Mode bit field in the Control A register (CTRLA.MODE), the external clock source is selected by writing 0x0 to CTRLA.MODE. The SERCOM baud-rate generator is configured as in the figure below. In asynchronous mode (CTRLA.CMODE=0), the 16-bit Baud register value is used. In synchronous mode (CTRLA.CMODE=1), the eight LSBs of the Baud register are used. Refer to Clock Generation – Baud-Rate Generator for details on configuring the baud rate. Figure 31-3. Clock Generation XCK CTRLA.MODE[0] XCKInternal Clk (GCLK) Baud Rate Generator Base Period /2 /8 /2 /8/1 Tx Clk Rx Clk CTRLA.CMODE Related Links

31.6.2.3.1 Synchronous Clock Operation

In synchronous mode, the CTRLA.MODE bit field determines whether the transmission clock line (XCK) serves either as input or output. The dependency between clock edges, data sampling, and data change is the same for internal and external clocks. Data input on the RxD pin is sampled at the opposite XCK clock edge when data is driven on the TxD pin. The Clock Polarity bit in the Control A register (CTRLA.CPOL) selects which XCK clock edge is used for RxD sampling, and which is used for TxD change: When CTRLA.CPOL is '0', the data will be changed on the rising edge of XCK, and sampled on the falling edge of XCK. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 551

When CTRLA.CPOL is '1', the data will be changed on the falling edge of XCK, and sampled on the rising edge of XCK. Figure 31-4. Synchronous Mode XCK Timing XCK RxD / TxD CTRLA.CPOL=1 Change Sample XCK RxD / TxD CTRLA.CPOL=0 Change Sample When the clock is provided through XCK (CTRLA.MODE=0x0), the shift registers operate directly on the XCK clock. This means that XCK is not synchronized with the system clock and, therefore, can operate at frequencies up to the system frequency.

31.6.2.4 Data Register

The USART Transmit Data register (TxDATA) and USART Receive Data register (RxDATA) share the same I/O address, referred to as the Data register (DATA). Writing the DATA register will update the TxDATA register. Reading the DATA register will return the contents of the RxDATA register.

31.6.2.5 Data Transmission

Data transmission is initiated by writing the data to be sent into the DATA register. Then, the data in TxDATA will be moved to the shift register when the shift register is empty and ready to send a new frame. After the shift register is loaded with data, the data frame will be transmitted. When the entire data frame including stop bit(s) has been transmitted and no new data was written to DATA, the Transmit Complete interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set, and the optional interrupt will be generated. The Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) indicates that the register is empty and ready for new data. The DATA register should only be written to when INTFLAG.DRE is set.

31.6.2.5.1 Disabling the Transmitter

The transmitter is disabled by writing '0' to the Transmitter Enable bit in the CTRLB register (CTRLB.TXEN). Disabling the transmitter will complete only after any ongoing and pending transmissions are completed, i.e., there is no data in the transmit shift register and TxDATA to transmit.

31.6.2.6 Data Reception

The receiver accepts data when a valid start bit is detected. Each bit following the start bit will be sampled according to the baud rate or XCK clock, and shifted into the receive shift register until the first stop bit of a frame is received. The second stop bit will be ignored by the receiver. When the first stop bit is received and a complete serial frame is present in the receive shift register, the contents of the shift register will be moved into the two-level receive buffer. Then, the Receive Complete interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set, and the optional interrupt will be generated. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 552

The received data can be read from the DATA register when the Receive Complete interrupt flag is set.

31.6.2.6.1 Disabling the Receiver

Writing '0' to the Receiver Enable bit in the CTRLB register (CTRLB.RXEN) will disable the receiver, flush the two-level receive buffer, and data from ongoing receptions will be lost.

31.6.2.6.2 Error Bits

The USART receiver has three error bits in the Status (STATUS) register: Frame Error (FERR), Buffer Overflow (BUFOVF), and Parity Error (PERR). Once an error happens, the corresponding error bit will be set until it is cleared by writing ‘1’ to it. These bits are also cleared automatically when the receiver is disabled. There are two methods for buffer overflow notification, selected by the Immediate Buffer Overflow Notification bit in the Control A register (CTRLA.IBON): When CTRLA.IBON=1, STATUS.BUFOVF is raised immediately upon buffer overflow. Software can then empty the receive FIFO by reading RxDATA, until the receiver complete interrupt flag (INTFLAG.RXC) is cleared. When CTRLA.IBON=0, the buffer overflow condition is attending data through the receive FIFO. After the received data is read, STATUS.BUFOVF will be set along with INTFLAG.RXC.

31.6.2.6.3 Asynchronous Data Reception

The USART includes a clock recovery and data recovery unit for handling asynchronous data reception. The clock recovery logic can synchronize the incoming asynchronous serial frames at the RxD pin to the internally generated baud-rate clock. The data recovery logic samples and applies a low-pass filter to each incoming bit, thereby improving the noise immunity of the receiver.

31.6.2.6.4 Asynchronous Operational Range

The operational range of the asynchronous reception depends on the accuracy of the internal baud-rate clock, the rate of the incoming frames, and the frame size (in number of bits). In addition, the operational range of the receiver is depending on the difference between the received bit rate and the internally generated baud rate. If the baud rate of an external transmitter is too high or too low compared to the internally generated baud rate, the receiver will not be able to synchronize the frames to the start bit. There are two possible sources for a mismatch in baud rate: First, the reference clock will always have some minor instability. Second, the baud-rate generator cannot always do an exact division of the reference clock frequency to get the baud rate desired. In this case, the BAUD register value should be set to give the lowest possible error. Refer to Clock Generation – Baud-Rate Generator for details. Recommended maximum receiver baud-rate errors for various character sizes are shown in the table below. Table 31-3. Asynchronous Receiver Error for 16-fold Oversampling D (Data bits+Parity) RSLOW [%] R FAST [%] Max. total error [%] Recommended max. Rx error [%] SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 553

31.6.3 Additional Features

31.6.3.1 Parity

Even or odd parity can be selected for error checking by writing 0x1 to the Frame Format bit field in the Control A register (CTRLA.FORM). If even parity is selected (CTRLB.PMODE=0), the parity bit of an outgoing frame is '1' if the data contains an odd number of bits that are '1', making the total number of '1' even. If odd parity is selected (CTRLB.PMODE=1), the parity bit of an outgoing frame is '1' if the data contains an even number of bits that are '0', making the total number of '1' odd. When parity checking is enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit of the corresponding frame. If a parity error is detected, the Parity Error bit in the Status register (STATUS.PERR) is set.

31.6.3.2 Hardware Handshaking

The USART features an out-of-band hardware handshaking flow control mechanism, implemented by connecting the RTS and CTS pins with the remote device, as shown in the figure below. Figure 31-7. Connection with a Remote Device for Hardware Handshaking RXD CTS RTS USART TXD RTS CTS Remote Device TXD RXD Hardware handshaking is only available in the following configuration:

USART with internal clock (CTRLA.MODE=1),
Asynchronous mode (CTRLA.CMODE=0),
and Flow control pinout (CTRLA.TXPO=2). When the receiver is disabled or the receive FIFO is full, the receiver will drive the RTS pin high. This notifies the remote device to stop transfer after the ongoing transmission. Enabling and disabling the receiver by writing to CTRLB.RXEN will set/clear the RTS pin after a synchronization delay. When the receive FIFO goes full, RTS will be set immediately and the frame being received will be stored in the shift register until the receive FIFO is no longer full. Figure 31-8. Receiver Behavior when Operating with Hardware Handshaking RTS Rx FIFO Full RXD RXEN The current CTS Status is in the STATUS register (STATUS.CTS). Character transmission will start only if STATUS.CTS=0. When CTS is set, the transmitter will complete the ongoing transmission and stop transmitting. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 555

Figure 31-9. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD

31.6.3.3 IrDA Modulation and Demodulation

Transmission and reception can be encoded IrDA compliant up to 115.2 kb/s. IrDA modulation and demodulation work in the following configuration:

IrDA encoding enabled (CTRLB.ENC=1),
Asynchronous mode (CTRLA.CMODE=0),
and 16x sample rate (CTRLA.SAMPR[0]=0). During transmission, each low bit is transmitted as a high pulse. The pulse width is 3/16 of the baud rate period, as illustrated in the figure below. Figure 31-10. IrDA Transmit Encoding IrDA encoded TXD TXD 1 baud clock 3/16 baud clock The reception decoder has two main functions. The first is to synchronize the incoming data to the IrDA baud rate counter. Synchronization is performed at the start of each zero pulse. The second main function is to decode incoming Rx data. If a pulse width meets the minimum length set by configuration (RXPL.RXPL), it is accepted. When the baud rate counter reaches its middle value (1/2 bit length), it is transferred to the receiver. Note: Note that the polarity of the transmitter and receiver are opposite: During transmission, a '0' bit is transmitted as a '1' pulse. During reception, an accepted '0' pulse is received as a '0' bit. Example: The figure below illustrates reception where RXPL.RXPL is set to 19. This indicates that the pulse width should be at least 20 SE clock cycles. When using BAUD=0xE666 or 160 SE cycles per bit, this corresponds to 2/16 baud clock as minimum pulse width required. In this case the first bit is accepted as a '0', the second bit is a '1', and the third bit is also a '1'. A low pulse is rejected since it does not meet the minimum requirement of 2/16 baud clock. Figure 31-11. IrDA Receive Decoding IrDA encoded RXD RXD Baud clock

20 SE clock cycles

0 0.5 1 1.5 2 2.5

31.6.3.4 Break Character Detection and Auto-Baud

Break character detection and auto-baud are available in this configuration:

Auto-baud frame format (CTRLA.FORM = 0x04 or 0x05),
Asynchronous mode (CTRLA.CMODE = 0), SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 556

and 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1). The USART uses a break detection threshold of greater than 11 nominal bit times at the configured baud rate. At any time, if more than 11 consecutive dominant bits are detected on the bus, the USART detects a Break Field. When a Break Field has been detected, the Receive Break interrupt flag (INTFLAG.RXBRK) is set and the USART expects the Sync Field character to be 0x55. This field is used to update the actual baud rate in order to stay synchronized. If the received Sync character is not 0x55, then the Inconsistent Sync Field error flag (STATUS.ISF) is set along with the Error interrupt flag (INTFLAG.ERROR), and the baud rate is unchanged. After a break field is detected and the start bit of the Sync Field is detected, a counter is started. The counter is then incremented for the next 8 bit times of the Sync Field. At the end of these 8 bit times, the counter is stopped. At this moment, the 13 most significant bits of the counter (value divided by 8) give the new clock divider (BAUD.BAUD), and the 3 least significant bits of this value (the remainder) give the new Fractional Part (BAUD.FP). When the Sync Field has been received, the clock divider (BAUD.BAUD) and the Fractional Part (BAUD.FP) are updated after a synchronization delay. After the Break and Sync Fields are received, multiple characters of data can be received.

31.6.3.5 LIN Master

LIN master is available with the following configuration:

LIN master format (CTRLA.FORM = 0x02)
Asynchronous mode (CTRLA.CMODE = 0)
16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1) LIN frames start with a header transmitted by the master. The header consists of the break, sync, and identifier fields. After the master transmits the header, the addressed slave will respond with 1-8 bytes of data plus checksum. Figure 31-12. LIN Frame Format Header Slave response Break Sync ID 1-8 Data bytes Checksum TxD RxD Using the LIN command field (CTRLB.LINCMD), the complete header can be automatically transmitted, or software can control transmission of the various header components. When CTRLB.LINCMD=0x1, software controls transmission of the LIN header. In this case, software uses the following sequence.
CTRLB.LINCMD is written to 0x1.
DATA register written to 0x00. This triggers transmission of the break field by hardware. Note that writing the DATA register with any other value will also result in the transmission of the break field by hardware.
DATA register written to 0x55. The 0x55 value (sync) is transmitted.
DATA register written to the identifier. The identifier is transmitted. When CTRLB.LINCMD=0x2, hardware controls transmission of the LIN header. In this case, software uses the following sequence.
CTRLB.LINCMD is written to 0x2. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 557

DATA register written to the identifier. This triggers transmission of the complete header by hardware. First the break field is transmitted. Next, the sync field is transmitted, and finally the identifier is transmitted. In LIN master mode, the length of the break field is programmable using the break length field (CTRLC.BRKLEN). When the LIN header command is used (CTRLB.LINCMD=0x2), the delay between the break and sync fields, in addition to the delay between the sync and ID fields are configurable using the header delay field (CTRLC.HDRDLY). When manual transmission is used (CTRLB.LINCMD=0x1), software controls the delay between break and sync. Figure 31-13. LIN Header Generation Configurable Break Field Length Sync Field Identifier Field LIN Header Configurable delay using CTRLC.HDRDLY After header transmission is complete, the slave responds with 1-8 data bytes plus checksum.

31.6.3.6 RS485

RS485 is available with the following configuration:

USART frame format (CTRLA.FORM = 0x00 or 0x01)
RS485 pinout (CTRLA.TXPO=0x3). The RS485 feature enables control of an external line driver as shown in the figure below. While operating in RS485 mode, the transmit enable pin (TE) is driven high when the transmitter is active. Figure 31-14. RS485 Bus Connection TXD TE USART RXD Differential Bus The TE pin will remain high for the complete frame including stop bit(s). If a Guard Time is programmed in the Control C register (CTRLC.GTIME), the line will remain driven after the last character completion. The following figure shows a transfer with one stop bit and CTRLC.GTIME=3. Figure 31-15. Example of TE Drive with Guard Time TXD Start Stop Data GTIME=3 TE The Transmit Complete interrupt flag (INTFLAG.TXC) will be raised after the guard time is complete and TE goes low.

31.6.3.7 Collision Detection

When the receiver and transmitter are connected either through pin configuration or externally, transmit collision can be detected after selecting the Collision Detection Enable bit in the CTRLB register (CTRLB.COLDEN=1). To detect collision, the receiver and transmitter must be enabled (CTRLB.RXEN=1 and CTRLB.TXEN=1). SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 558

Collision detection is performed for each bit transmitted by comparing the received value with the transmit value, as shown in the figure below. While the transmitter is idle (no transmission in progress), characters can be received on RxD without triggering a collision. Figure 31-16. Collision Checking 8-bit character, single stop bit Collision checked TXD RXD The next figure shows the conditions for a collision detection. In this case, the start bit and the first data bit are received with the same value as transmitted. The second received data bit is found to be different than the transmitted bit at the detection point, which indicates a collision. Figure 31-17. Collision Detected Collision checked and ok TXD RXD Collision detected Tri-state TXEN When a collision is detected, the USART follows this sequence: 1. Abort the current transfer. 2. Flush the transmit buffer. 3. Disable transmitter (CTRLB.TXEN=0) – This is done after a synchronization delay. The CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB) will be set until this is complete. – After disabling, the TxD pin will be tri-stated. 4. Set the Collision Detected bit (STATUS.COLL) along with the Error interrupt flag (INTFLAG.ERROR). 5. Set the Transmit Complete interrupt flag (INTFLAG.TXC), since the transmit buffer no longer contains data. After a collision, software must manually enable the transmitter again before continuing, after assuring that the CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB) is not set.

31.6.3.8 Loop-Back Mode

For loop-back mode, configure the Receive Data Pinout (CTRLA.RXPO) and Transmit Data Pinout (CTRLA.TXPO) to use the same data pins for transmit and receive. The loop-back is through the pad, so the signal is also available externally.

31.6.3.9 Start-of-Frame Detection

The USART start-of-frame detector can wake up the CPU when it detects a start bit. In standby sleep mode, the internal fast startup oscillator must be selected as the GCLK_SERCOMx_CORE source. When a 1-to-0 transition is detected on RxD, the 8MHz Internal Oscillator is powered up and the USART clock is enabled. After startup, the rest of the data frame can be received, provided that the baud rate is SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 559

slow enough in relation to the fast startup internal oscillator start-up time. Refer to Electrical Characteristics for details. The start-up time of this oscillator varies with supply voltage and temperature. The USART start-of-frame detection works both in asynchronous and synchronous modes. It is enabled by writing ‘1’ to the Start of Frame Detection Enable bit in the Control B register (CTRLB.SFDE). If the Receive Start Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.RXS) is set, the Receive Start interrupt is generated immediately when a start is detected. When using start-of-frame detection without the Receive Start interrupt, start detection will force the 8MHz Internal Oscillator and USART clock active while the frame is being received. In this case, the CPU will not wake up until the Receive Complete interrupt is generated. Related Links 45. Electrical Characteristics 85°C (SAM C20/C21 E/G/J)

31.6.3.10 Sample Adjustment

In asynchronous mode (CTRLA.CMODE=0), three samples in the middle are used to determine the value based on majority voting. The three samples used for voting can be selected using the Sample Adjustment bit field in Control A register (CTRLA.SAMPA). When CTRLA.SAMPA=0, samples 7-8-9 are used for 16x oversampling, and samples 3-4-5 are used for 8x oversampling.

31.6.4 DMA, Interrupts and Events

Table 31-4. Module Request for SERCOM USART Condition Request DMA Interrupt Event Data Register Empty (DRE) Yes (request cleared when data is written) Yes NA Receive Complete (RXC) Yes (request cleared when data is read) Yes Transmit Complete (TXC) NA Yes Receive Start (RXS) NA Yes Clear to Send Input Change (CTSIC) NA Yes Receive Break (RXBRK) NA Yes Error (ERROR) NA Yes

31.6.4.1 DMA Operation

The USART generates the following DMA requests:

Data received (RX): The request is set when data is available in the receive FIFO. The request is cleared when DATA is read.
Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is cleared when DATA is written.

31.6.4.2 Interrupts

The USART has the following interrupt sources. These are asynchronous interrupts, and can wake up the device from any sleep mode: SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 560

Data Register Empty (DRE)
Receive Complete (RXC)
Transmit Complete (TXC)
Receive Start (RXS)
Clear to Send Input Change (CTSIC)
Received Break (RXBRK)
Error (ERROR) Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the interrupt condition is met. Each interrupt can be individually enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and if the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the USART is reset. For details on clearing interrupt flags, refer to the INTFLAG register description. The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for interrupt requests. Refer to Nested Vector Interrupt Controller for details. Related Links

31.6.4.3 Events

Not applicable.

31.6.5 Sleep Mode Operation

The behavior in sleep mode is depending on the clock source and the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY):

Internal clocking, CTRLA.RUNSTDBY=1: GCLK_SERCOMx_CORE can be enabled in all sleep modes. Any interrupt can wake up the device.
External clocking, CTRLA.RUNSTDBY=1: The Receive Start and the Receive Complete interrupt(s) can wake up the device.
Internal clocking, CTRLA.RUNSTDBY=0: Internal clock will be disabled, after any ongoing transfer was completed. The Receive Start and the Receive Complete interrupt(s) can wake up the device.
External clocking, CTRLA.RUNSTDBY=0: External clock will be disconnected, after any ongoing transfer was completed. All reception will be dropped.

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written:

Software Reset bit in the CTRLA register (CTRLA.SWRST)
Enable bit in the CTRLA register (CTRLA.ENABLE)
Receiver Enable bit in the CTRLB register (CTRLB.RXEN)
Transmitter Enable bit in the Control B register (CTRLB.TXEN) Note: CTRLB.RXEN is write-synchronized somewhat differently. See also 31.8.2 CTRLB for details. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 561

Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Related Links SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 562

31.7 Register Summary

Offset Name Bit Pos. 0x00 CTRLA 7:0 RUNSTDBY MODE[2:0] ENABLE SWRST 15:8 SAMPR[2:0] IBON 23:16 SAMPA[1:0] RXPO[1:0] TXPO[1:0] 31:24 DORD CPOL CMODE FORM[3:0] 0x04 CTRLB 7:0 SBMODE CHSIZE[2:0] 15:8 PMODE ENC SFDE COLDEN 23:16 RXEN TXEN 31:24 LINCMD[1:0] 0x08 CTRLC 7:0 GTIME[2:0] 15:8 HDRDLY[1:0] BRKLEN[1:0] 23:16 31:24 0x0C BAUD 7:0 BAUD[7:0] 15:8 BAUD[15:8] 0x0E RXPL 7:0 RXPL[7:0] 0x0F ... 0x13 Reserved 0x14 INTENCLR 7:0 ERROR RXBRK CTSIC RXS RXC TXC DRE 0x15 Reserved 0x16 INTENSET 7:0 ERROR RXBRK CTSIC RXS RXC TXC DRE 0x17 Reserved 0x18 INTFLAG 7:0 ERROR RXBRK CTSIC RXS RXC TXC DRE 0x19 Reserved 0x1A STATUS 7:0 TXE COLL ISF CTS BUFOVF FERR PERR 15:8 0x1C SYNCBUSY 7:0 CTRLB ENABLE SWRST 15:8 23:16 31:24 0x20 ... 0x27 Reserved 0x28 DATA 7:0 DATA[7:0] 15:8 DATA[8:8] 0x2A ... 0x2F Reserved 0x30 DBGCTRL 7:0 DBGSTOP SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 563

31.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-Synchronized" and/or "Write-Synchronized" property in each individual register description. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write- Protection" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 564

31.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 DORD CPOL CMODE FORM[3:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SAMPA[1:0] RXPO[1:0] TXPO[1:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SAMPR[2:0] IBON Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RUNSTDBY MODE[2:0] ENABLE SWRST Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 30 – DORD Data Order This bit selects the data order when a character is shifted out from the Data register. This bit is not synchronized. Value Description 0 MSB is transmitted first. 1 LSB is transmitted first. Bit 29 – CPOL Clock Polarity This bit selects the relationship between data output change and data input sampling in synchronous mode. This bit is not synchronized. CPOL TxD Change RxD Sample 0x0 Rising XCK edge Falling XCK edge 0x1 Falling XCK edge Rising XCK edge Bit 28 – CMODE Communication Mode This bit selects asynchronous or synchronous communication. This bit is not synchronized. Value Description 0 Asynchronous communication. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 565

1 Synchronous communication. Bits 27:24 – FORM[3:0] Frame Format These bits define the frame format. These bits are not synchronized. FORM[3:0] Description 0x0 USART frame 0x1 USART frame with parity 0x2 LIN Master - Break and sync generation. See LIN Command (CTRLB.LINCMD). 0x3 Reserved 0x4 Auto-baud (LIN Slave) - break detection and auto-baud. 0x5 Auto-baud - break detection and auto-baud with parity 0x6-0xF Reserved Bits 23:22 – SAMPA[1:0] Sample Adjustment These bits define the sample adjustment. These bits are not synchronized. SAMPA[1:0] 16x Over-sampling (CTRLA.SAMPR=0 or 8x Over-sampling (CTRLA.SAMPR=2 or 0x0 7-8-9 3-4-5 0x1 9-10-11 4-5-6 0x2 11-12-13 5-6-7 0x3 13-14-15 6-7-8 Bits 21:20 – RXPO[1:0] Receive Data Pinout These bits define the receive data (RxD) pin configuration. These bits are not synchronized. RXPO[1:0] Name Description 0x0 PAD[0] SERCOM PAD[0] is used for data reception 0x1 PAD[1] SERCOM PAD[1] is used for data reception 0x2 PAD[2] SERCOM PAD[2] is used for data reception 0x3 PAD[3] SERCOM PAD[3] is used for data reception Bits 17:16 – TXPO[1:0] Transmit Data Pinout These bits define the transmit data (TxD) and XCK pin configurations. This bit is not synchronized. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 566

TXPO TxD Pin Location XCK Pin Location (When Applicable) RTS/TE CTS 0x0 SERCOM PAD[0] SERCOM PAD[1] N/A N/A 0x1 SERCOM PAD[2] SERCOM PAD[3] N/A N/A 0x2 SERCOM PAD[0] N/A SERCOM PAD[2] SERCOM PAD[3] 0x3 SERCOM_PAD[0] SERCOM_PAD[1] SERCOM_PAD[2] N/A Bits 15:13 – SAMPR[2:0] Sample Rate These bits select the sample rate. These bits are not synchronized. SAMPR[2:0] Description 0x0 16x over-sampling using arithmetic baud rate generation. 0x1 16x over-sampling using fractional baud rate generation. 0x2 8x over-sampling using arithmetic baud rate generation. 0x3 8x over-sampling using fractional baud rate generation. 0x4 3x over-sampling using arithmetic baud rate generation. 0x5-0x7 Reserved Bit 8 – IBON Immediate Buffer Overflow Notification This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is asserted when a buffer overflow occurs. Value Description 0 STATUS.BUFOVF is asserted when it occurs in the data stream. 1 STATUS.BUFOVF is asserted immediately upon buffer overflow. Bit 7 – RUNSTDBY Run In Standby This bit defines the functionality in standby sleep mode. This bit is not synchronized. RUNSTDBY External Clock Internal Clock 0x0 External clock is disconnected when ongoing transfer is finished. All reception is dropped. Generic clock is disabled when ongoing transfer is finished. The device will not wake up on either Receive Start or Transfer Complete interrupt unless the appropriate ONDEMAND bits are set in the clocking chain. 0x1 Wake on Receive Start or Receive Complete interrupt. Generic clock is enabled in all sleep modes. Any interrupt can wake up the device. Bits 4:2 – MODE[2:0] Operating Mode These bits select the USART serial communication interface of the SERCOM. These bits are not synchronized. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 567

0x0 USART with external clock 0x1 USART with internal clock Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/ disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the operation is complete. This bit is not enable-protected. Value Description 0 The peripheral is disabled or being disabled. 1 The peripheral is enabled or being enabled. Bit 0 – SWRST Software Reset Writing '0' to this bit has no effect. Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Value Description 0 There is no reset operation ongoing. 1 The reset operation is ongoing. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 568

31.8.2 Control B

Name: CTRLB Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 LINCMD[1:0] Access R/W R/W Reset 0 0 Bit 23 22 21 20 19 18 17 16 RXEN TXEN Access R/W R/W Reset 0 0 Bit 15 14 13 12 11 10 9 8 PMODE ENC SFDE COLDEN Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SBMODE CHSIZE[2:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 25:24 – LINCMD[1:0] LIN Command These bits define the LIN header transmission control. This field is only valid in LIN master mode (CTRLA.FORM= LIN Master). These are strobe bits and will always read back as zero. These bits are not enable-protected. Value Description 0x0 Normal USART transmission. 0x1 Break field is transmitted when DATA is written. 0x2 Break, sync and identifier are automatically transmitted when DATA is written with the identifier. 0x3 Reserved Bit 17 – RXEN Receiver Enable Writing '0' to this bit will disable the USART receiver. Disabling the receiver will flush the receive buffer and clear the FERR, PERR and BUFOVF bits in the STATUS register. Writing '1' to CTRLB.RXEN when the USART is disabled will set CTRLB.RXEN immediately. When the USART is enabled, CTRLB.RXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until the receiver is enabled. When the receiver is enabled, CTRLB.RXEN will read back as '1'. Writing '1' to CTRLB.RXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain set until the receiver is enabled, and CTRLB.RXEN will read back as '1'. This bit is not enable-protected. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 569

0 The receiver is disabled or being enabled. 1 The receiver is enabled or will be enabled when the USART is enabled. Bit 16 – TXEN Transmitter Enable Writing '0' to this bit will disable the USART transmitter. Disabling the transmitter will not become effective until ongoing and pending transmissions are completed. Writing '1' to CTRLB.TXEN when the USART is disabled will set CTRLB.TXEN immediately. When the USART is enabled, CTRLB.TXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until the transmitter is enabled. When the transmitter is enabled, CTRLB.TXEN will read back as '1'. Writing '1' to CTRLB.TXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain set until the transmitter is enabled, and CTRLB.TXEN will read back as '1'. This bit is not enable-protected. Value Description 0 The transmitter is disabled or being enabled. 1 The transmitter is enabled or will be enabled when the USART is enabled. Bit 13 – PMODE Parity Mode This bit selects the type of parity used when parity is enabled (CTRLA.FORM is '1'). The transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and parity bit, compare it to the parity mode and, if a mismatch is detected, STATUS.PERR will be set. This bit is not synchronized. Value Description 0 Even parity. 1 Odd parity. Bit 10 – ENC Encoding Format This bit selects the data encoding format. This bit is not synchronized. Value Description 0 Data is not encoded. 1 Data is IrDA encoded. Bit 9 – SFDE Start of Frame Detection Enable This bit controls whether the start-of-frame detector will wake up the device when a start bit is detected on the RxD line. This bit is not synchronized. SFDE INTENSET.RXS INTENSET.RXC Description 0 X X Start-of-frame detection disabled. 1 0 0 Reserved 1 0 1 Start-of-frame detection enabled. RXC wakes up the device from all sleep modes. 1 1 0 Start-of-frame detection enabled. RXS wakes up the device from all sleep modes. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 570

SFDE INTENSET.RXS INTENSET.RXC Description 1 1 1 Start-of-frame detection enabled. Both RXC and RXS wake up the device from all sleep modes. Bit 8 – COLDEN Collision Detection Enable This bit enables collision detection. This bit is not synchronized. Value Description 0 Collision detection is not enabled. 1 Collision detection is enabled. Bit 6 – SBMODE Stop Bit Mode This bit selects the number of stop bits transmitted. This bit is not synchronized. Value Description 0 One stop bit. 1 Two stop bits. Bits 2:0 – CHSIZE[2:0] Character Size These bits select the number of bits in a character. These bits are not synchronized. CHSIZE[2:0] Description 0x0 8 bits 0x1 9 bits 0x2-0x4 Reserved 0x5 5 bits 0x6 6 bits 0x7 7 bits SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 571

31.8.3 Control C

Name: CTRLC Offset: 0x08 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 HDRDLY[1:0] BRKLEN[1:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GTIME[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 11:10 – HDRDLY[1:0] LIN Master Header Delay These bits define the delay between break and sync transmission in addition to the delay between the sync and identifier (ID) fields when in LIN master mode (CTRLA.FORM=0x2). This field is only valid when using the LIN header command (CTRLB.LINCMD=0x2). Value Description 0x0 Delay between break and sync transmission is 1 bit time. Delay between sync and ID transmission is 1 bit time. 0x1 Delay between break and sync transmission is 4 bit time. Delay between sync and ID transmission is 4 bit time. 0x2 Delay between break and sync transmission is 8 bit time. Delay between sync and ID transmission is 4 bit time. 0x3 Delay between break and sync transmission is 14 bit time. Delay between sync and ID transmission is 4 bit time. Bits 9:8 – BRKLEN[1:0] LIN Master Break Length These bits define the length of the break field transmitted when in LIN master mode (CTRLA.FORM=0x2). Value Description 0x0 Break field transmission is 13 bit times 0x1 Break field transmission is 17 bit times SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 572

0x2 Break field transmission is 21 bit times 0x3 Break field transmission is 26 bit times Bits 2:0 – GTIME[2:0] Guard Time These bits define the guard time when using RS485 mode (CTRLA.FORM=0x0 or CTRLA.FORM=0x1, and CTRLA.TXPO=0x3). For RS485 mode, the guard time is programmable from 0-7 bit times and defines the time that the transmit enable pin (TE) remains high after the last stop bit is transmitted and there is no remaining data to be transmitted. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 573

31.8.4 Baud

Name: BAUD Offset: 0x0C Reset: 0x0000 Property: Enable-Protected, PAC Write-Protection Bit 15 14 13 12 11 10 9 8 BAUD[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BAUD[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – BAUD[15:0] Baud Value Arithmetic Baud Rate Generation (CTRLA.SAMPR[0]=0): These bits control the clock generation, as described in the SERCOM Baud Rate section. If Fractional Baud Rate Generation (CTRLA.SAMPR[0]=1) bit positions 15 to 13 are replaced by FP[2:0] Fractional Part:

Bits 15:13 - FP[2:0]: Fractional Part These bits control the clock generation, as described in the SERCOM Clock Generation – Baud-Rate Generator section.
Bits 12:0 - BAUD[12:0]: Baud Value These bits control the clock generation, as described in the SERCOM Clock Generation – Baud-Rate Generator section. Related Links

31.8.5 Receive Pulse Length Register

Name: RXPL Offset: 0x0E Reset: 0x00 Property: Enable-Protected, PAC Write-Protection Bit 7 6 5 4 3 2 1 0 RXPL[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – RXPL[7:0] Receive Pulse Length When the encoding format is set to IrDA (CTRLB.ENC=1), these bits control the minimum pulse length that is required for a pulse to be accepted by the IrDA receiver with regards to the serial engine clock SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 575

31.8.6 Interrupt Enable Clear

Name: INTENCLR Offset: 0x14 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 5 4 3 2 1 0 ERROR RXBRK CTSIC RXS RXC TXC DRE Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 7 – ERROR Error Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. Value Description 0 Error interrupt is disabled. 1 Error interrupt is enabled. Bit 5 – RXBRK Receive Break Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Receive Break Interrupt Enable bit, which disables the Receive Break interrupt. Value Description 0 Receive Break interrupt is disabled. 1 Receive Break interrupt is enabled. Bit 4 – CTSIC Clear to Send Input Change Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Clear To Send Input Change Interrupt Enable bit, which disables the Clear To Send Input Change interrupt. Value Description 0 Clear To Send Input Change interrupt is disabled. 1 Clear To Send Input Change interrupt is enabled. Bit 3 – RXS Receive Start Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Receive Start Interrupt Enable bit, which disables the Receive Start interrupt. Value Description 0 Receive Start interrupt is disabled. 1 Receive Start interrupt is enabled. Bit 2 – RXC Receive Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete interrupt. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 576

0 Receive Complete interrupt is disabled. 1 Receive Complete interrupt is enabled. Bit 1 – TXC Transmit Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Transmit Complete Interrupt Enable bit, which disables the Receive Complete interrupt. Value Description 0 Transmit Complete interrupt is disabled. 1 Transmit Complete interrupt is enabled. Bit 0 – DRE Data Register Empty Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register Empty interrupt. Value Description 0 Data Register Empty interrupt is disabled. 1 Data Register Empty interrupt is enabled. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 577

31.8.7 Interrupt Enable Set

Name: INTENSET Offset: 0x16 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 5 4 3 2 1 0 ERROR RXBRK CTSIC RXS RXC TXC DRE Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 7 – ERROR Error Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. Value Description 0 Error interrupt is disabled. 1 Error interrupt is enabled. Bit 5 – RXBRK Receive Break Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Receive Break Interrupt Enable bit, which enables the Receive Break interrupt. Value Description 0 Receive Break interrupt is disabled. 1 Receive Break interrupt is enabled. Bit 4 – CTSIC Clear to Send Input Change Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Clear To Send Input Change Interrupt Enable bit, which enables the Clear To Send Input Change interrupt. Value Description 0 Clear To Send Input Change interrupt is disabled. 1 Clear To Send Input Change interrupt is enabled. Bit 3 – RXS Receive Start Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Receive Start Interrupt Enable bit, which enables the Receive Start interrupt. Value Description 0 Receive Start interrupt is disabled. 1 Receive Start interrupt is enabled. Bit 2 – RXC Receive Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive Complete interrupt. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 578

0 Receive Complete interrupt is disabled. 1 Receive Complete interrupt is enabled. Bit 1 – TXC Transmit Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete interrupt. Value Description 0 Transmit Complete interrupt is disabled. 1 Transmit Complete interrupt is enabled. Bit 0 – DRE Data Register Empty Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register Empty interrupt. Value Description 0 Data Register Empty interrupt is disabled. 1 Data Register Empty interrupt is enabled. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 579

31.8.8 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x18 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 ERROR RXBRK CTSIC RXS RXC TXC DRE Access R/W R/W R/W R/W R R/W R Reset 0 0 0 0 0 0 0 Bit 7 – ERROR Error This flag is cleared by writing '1' to it. This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS register. Errors that will set this flag are COLL, ISF, BUFOVF, FERR, and PERR.Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 5 – RXBRK Receive Break This flag is cleared by writing '1' to it. This flag is set when auto-baud is enabled (CTRLA.FORM) and a break character is received. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 4 – CTSIC Clear to Send Input Change This flag is cleared by writing a '1' to it. This flag is set when a change is detected on the CTS pin. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 3 – RXS Receive Start This flag is cleared by writing '1' to it. This flag is set when a start condition is detected on the RxD line and start-of-frame detection is enabled (CTRLB.SFDE is '1'). Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Receive Start interrupt flag. Bit 2 – RXC Receive Complete This flag is cleared by reading the Data register (DATA) or by disabling the receiver. This flag is set when there are unread data in DATA. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. Bit 1 – TXC Transmit Complete This flag is cleared by writing '1' to it or by writing new data to DATA. This flag is set when the entire frame in the transmit shift register has been shifted out and there are no new data in DATA. Writing '0' to this bit has no effect. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 580

Writing '1' to this bit will clear the flag. Bit 0 – DRE Data Register Empty This flag is cleared by writing new data to DATA. This flag is set when DATA is empty and ready to be written. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 581

31.8.9 Status

Name: STATUS Offset: 0x1A Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 TXE COLL ISF CTS BUFOVF FERR PERR Access R/W R/W R/W R R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 6 – TXE Transmitter Empty When CTRLA.FORM is set to LIN master mode, this bit is set when any ongoing transmission is complete and TxDATA is empty. When CTRLA.FORM is not set to LIN master mode, this bit will always read back as zero. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Bit 5 – COLL Collision Detected This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set when collision detection is enabled (CTRLB.COLDEN) and a collision is detected. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Bit 4 – ISF Inconsistent Sync Field This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set when the frame format is set to auto-baud (CTRLA.FORM) and a sync field not equal to 0x55 is received. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Bit 3 – CTS Clear to Send This bit indicates the current level of the CTS pin when flow control is enabled (CTRLA.TXPO). Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. Bit 2 – BUFOVF Buffer Overflow Reading this bit before reading the Data register will indicate the error status of the next character to be read. This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set when a buffer overflow condition is detected. A buffer overflow occurs when the receive buffer is full, there is a new character waiting in the receive shift register and a new start bit is detected. Writing '0' to this bit has no effect. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 582

Writing '1' to this bit will clear it. Bit 1 – FERR Frame Error Reading this bit before reading the Data register will indicate the error status of the next character to be read. This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set if the received character had a frame error, i.e., when the first stop bit is zero. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Bit 0 – PERR Parity Error Reading this bit before reading the Data register will indicate the error status of the next character to be read. This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set if parity checking is enabled (CTRLA.FORM is 0x1, 0x5) and a parity error is detected. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 583

31.8.10 Synchronization Busy

Name: SYNCBUSY Offset: 0x1C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CTRLB ENABLE SWRST Access R R R Reset 0 0 0 Bit 2 – CTRLB CTRLB Synchronization Busy Writing to the CTRLB register when the SERCOM is enabled requires synchronization. When writing to CTRLB the SYNCBUSY.CTRLB bit will be set until synchronization is complete. If CTRLB is written while SYNCBUSY.CTRLB is asserted, an APB error will be generated. Value Description 0 CTRLB synchronization is not busy. 1 CTRLB synchronization is busy. Bit 1 – ENABLE SERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNCBUSY.ENABLE bit will be set until synchronization is complete. Value Description 0 Enable synchronization is not busy. 1 Enable synchronization is busy. Bit 0 – SWRST Software Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will be set until synchronization is complete. Value Description 0 SWRST synchronization is not busy. 1 SWRST synchronization is busy. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 584

31.8.11 Data

Name: DATA Offset: 0x28 Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 DATA[8:8] Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 8:0 – DATA[8:0] Data Reading these bits will return the contents of the Receive Data register. The register should be read only when the Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set. The status bits in STATUS should be read before reading the DATA value in order to get any corresponding error. Writing these bits will write the Transmit Data register. This register should be written only when the Data Register Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 585

31.8.12 Debug Control

Name: DBGCTRL Offset: 0x30 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DBGSTOP Access R/W Reset 0 Bit 0 – DBGSTOP Debug Stop Mode This bit controls the baud-rate generator functionality when the CPU is halted by an external debugger. Value Description

0 The baud-rate generator continues normal operation when the CPU is halted by an external

debugger. 1 The baud-rate generator is halted when the CPU is halted by an external debugger. SAM C20/C21 Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 586

SERCOM SPI – SERCOM Serial Peripheral Interface

32.1 Overview

The serial peripheral interface (SPI) is one of the available modes in the Serial Communication Interface (SERCOM). The SPI uses the SERCOM transmitter and receiver configured as shown in 32.3 Block Diagram. Each side, master and slave, depicts a separate SPI containing a shift register, a transmit buffer and a two-level receive buffer. In addition, the SPI master uses the SERCOM baud-rate generator, while the SPI slave can use the SERCOM address match logic. Labels in capital letters are synchronous to CLK_SERCOMx_APB and accessible by the CPU, while labels in lowercase letters are synchronous to the SCK clock. Related Links 30. SERCOM – Serial Communication Interface

32.2 Features

SERCOM SPI includes the following features:

Full-duplex, four-wire interface (MISO, MOSI, SCK, SS)
One-level transmit buffer, two-level receive buffer
Supports all four SPI modes of operation
Single data direction operation allows alternate function on MISO or MOSI pin
Selectable LSB- or MSB-first data transfer
Can be used with DMA
Master operation: – Serial clock speed, fSCK=1/tSCK(1) – 8-bit clock generator – Hardware controlled SS
Slave Operation: – Serial clock speed, fSCK=1/tSSCK(1) – Optional 8-bit address match operation – Operation in all sleep modes – Wake on SS transition 1. For t SCK and tSSCK values, refer to SPI Timing Characteristics. Related Links

45.13.1 SERCOM in SPI Mode Timing

SERCOM – Serial Communication Interface

32.3 Block Diagram

Figure 32-1. Full-Duplex SPI Master Slave Interconnection BAUD baud rate generator Tx DATA shift register rx buffer Rx DATA Master Slave Tx DATA shift register rx buffer Rx DATA SCK _SS MISO MOSI ADDR/ADDRMASK Address Match

32.4 Signal Description

Table 32-1. SERCOM SPI Signals Signal Name Type Description PAD[3:0] Digital I/O General SERCOM pins One signal can be mapped to one of several pins. Related Links 6. I/O Multiplexing and Considerations

32.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

32.5.1 I/O Lines

In order to use the SERCOM’s I/O lines, the I/O pins must be configured using the IO Pin Controller (PORT). When the SERCOM is configured for SPI operation, the SERCOM controls the direction and value of the I/O pins according to the table below. Both PORT control bits PINCFGn.PULLEN and PINCFGn.DRVSTR are still effective. If the receiver is disabled, the data input pin can be used for other purposes. In master mode, the slave select line ( SS) is hardware controlled when the Master Slave Select Enable bit in the Control B register (CTRLB.MSSEN) is '1'. Table 32-2. SPI Pin Configuration Pin Master SPI Slave SPI MOSI Output Input MISO Input Output SCK Output Input SS Output (CTRLB.MSSEN=1) Input SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 588

The combined configuration of PORT, the Data In Pinout and the Data Out Pinout bit groups in the Control A register (CTRLA.DIPO and CTRLA.DOPO) define the physical position of the SPI signals in the table above. Related Links 28. PORT - I/O Pin Controller

32.5.2 Power Management

This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake up the device from sleep modes. Related Links 19. PM – Power Manager

32.5.3 Clocks

The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Main Clock Controller. Refer to Peripheral Clock Masking for details and default status of this clock. A generic clock (GCLK_SERCOMx_CORE) is required to clock the SPI. This clock must be configured and enabled in the Generic Clock Controller before using the SPI. This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Therefore, writes to certain registers will require synchronization to the clock domains. Related Links 16. GCLK - Generic Clock Controller

32.6.6 Synchronization

32.5.4 DMA

32.5.5 Interrupts

32.5.6 Events

Not applicable.

32.5.7 Debug Operation

When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result during debugging. This peripheral can be forced to halt operation during debugging - refer to the Debug Control (DBGCTRL) register for details. SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 589

32.5.8 Register Access Protection

Registers with write-access can be write-protected optionally by the peripheral access controller (PAC). PAC Write-Protection is not available for the following registers:

Interrupt Flag Clear and Status register (INTFLAG)
Status register (STATUS)
Data register (DATA) Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger. Related Links 11. PAC - Peripheral Access Controller

32.5.9 Analog Connections

Not applicable.

32.6 Functional Description

32.6.1 Principle of Operation

The SPI is a high-speed synchronous data transfer interface. It allows high-speed communication between the device and peripheral devices. The SPI can operate as master or slave. As master, the SPI initiates and controls all data transactions. The SPI is single buffered for transmitting and double buffered for receiving. When transmitting data, the Data register can be loaded with the next character to be transmitted during the current transmission. When receiving, the data is transferred to the two-level receive buffer, and the receiver is ready for a new character. The SPI transaction format is shown in SPI Transaction Format. Each transaction can contain one or more characters. The character size is configurable, and can be either 8 or 9 bits. Figure 32-2. SPI Transaction Format Character Transaction MOSI/MISO _SS Character 0 Character 1 Character 2 The SPI master must pull the slave select line (SS) of the desired slave low to initiate a transaction. The master and slave prepare data to send via their respective shift registers, and the master generates the serial clock on the SCK line. Data are always shifted from master to slave on the Master Output Slave Input line (MOSI); data is shifted from slave to master on the Master Input Slave Output line (MISO). Each time character is shifted out from the master, a character will be shifted out from the slave simultaneously. To signal the end of a transaction, the master will pull the SS line high SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 590

32.6.2 Basic Operation

32.6.2.1 Initialization

The following registers are enable-protected, meaning that they can only be written when the SPI is disabled (CTRL.ENABLE=0):

Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST)
Control B register (CTRLB), except Receiver Enable (CTRLB.RXEN)
Baud register (BAUD)
Address register (ADDR) When the SPI is enabled or is being enabled (CTRLA.ENABLE=1), any writing to these registers will be discarded. when the SPI is being disabled, writing to these registers will be completed after the disabling. Enable-protection is denoted by the Enable-Protection property in the register description. Initialize the SPI by following these steps: 1. Select SPI mode in master / slave operation in the Operating Mode bit group in the CTRLA register (CTRLA.MODE= 0x2 or 0x3 ). 2. Select transfer mode for the Clock Polarity bit and the Clock Phase bit in the CTRLA register (CTRLA.CPOL and CTRLA.CPHA) if desired. 3. Select the Frame Format value in the CTRLA register (CTRLA.FORM). 4. Configure the Data In Pinout field in the Control A register (CTRLA.DIPO) for SERCOM pads of the receiver. 5. Configure the Data Out Pinout bit group in the Control A register (CTRLA.DOPO) for SERCOM pads of the transmitter. 6. Select the Character Size value in the CTRLB register (CTRLB.CHSIZE). 7. Write the Data Order bit in the CTRLA register (CTRLA.DORD) for data direction. 8. If the SPI is used in master mode: 8.1. Select the desired baud rate by writing to the Baud register (BAUD). 8.2. If Hardware SS control is required, write '1' to the Master Slave Select Enable bit in CTRLB register (CTRLB.MSSEN). 9. Enable the receiver by writing the Receiver Enable bit in the CTRLB register (CTRLB.RXEN=1).

32.6.2.2 Enabling, Disabling, and Resetting

32.6.2.3 Clock Generation

In SPI master operation (CTRLA.MODE=0x3), the serial clock (SCK) is generated internally by the SERCOM baud-rate generator. In SPI mode, the baud-rate generator is set to synchronous mode. The 8-bit Baud register (BAUD) value is used for generating SCK and clocking the shift register. Refer to Clock Generation – Baud-Rate Generator for more details. SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 591

In SPI slave operation (CTRLA.MODE is 0x2), the clock is provided by an external master on the SCK pin. This clock is used to directly clock the SPI shift register. Related Links

32.6.2.4 Data Register

The SPI Transmit Data register (TxDATA) and SPI Receive Data register (RxDATA) share the same I/O address, referred to as the SPI Data register (DATA). Writing DATA register will update the Transmit Data register. Reading the DATA register will return the contents of the Receive Data register.

32.6.2.5 SPI Transfer Modes

There are four combinations of SCK phase and polarity to transfer serial data. The SPI data transfer modes are shown in SPI Transfer Modes (Table) and SPI Transfer Modes (Figure). SCK phase is configured by the Clock Phase bit in the CTRLA register (CTRLA.CPHA). SCK polarity is programmed by the Clock Polarity bit in the CTRLA register (CTRLA.CPOL). Data bits are shifted out and latched in on opposite edges of the SCK signal. This ensures sufficient time for the data signals to stabilize. Table 32-3. SPI Transfer Modes Mode CPOL CPHA Leading Edge Trailing Edge 0 0 0 Rising, sample Falling, setup 1 0 1 Rising, setup Falling, sample 2 1 0 Falling, sample Rising, setup 3 1 1 Falling, setup Rising, sample Note: Leading edge is the first clock edge in a clock cycle. Trailing edge is the second clock edge in a clock cycle. SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 592

Figure 32-3. SPI Transfer Modes Bit 1 Bit 6 LSB MSB Mode 0 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN Mode 2 SS MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 MSB first (DORD = 0) LSB first (DORD = 1) Mode 1 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN Mode 3 SS MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB MSB first (DORD = 0) LSB first (DORD = 1)

32.6.2.6 Transferring Data

32.6.2.6.1 Master

In master mode (CTRLA.MODE=0x3), when Master Slave Enable Select (CTRLB.MSSEN) is ‘1’, hardware will control the SS line. When Master Slave Select Enable (CTRLB.MSSEN) is '0', the SS line must be configured as an output. SS can be assigned to any general purpose I/O pin. When the SPI is ready for a data transaction, software must pull the SS line low. When writing a character to the Data register (DATA), the character will be transferred to the shift register. Once the content of TxDATA has been transferred to the shift register, the Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) will be set. And a new character can be written to DATA. Each time one character is shifted out from the master, another character will be shifted in from the slave simultaneously. If the receiver is enabled (CTRLA.RXEN=1), the contents of the shift register will be SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 593

transferred to the two-level receive buffer. The transfer takes place in the same clock cycle as the last data bit is shifted in. And the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set. The received data can be retrieved by reading DATA. When the last character has been transmitted and there is no valid data in DATA, the Transmit Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set. When the transaction is finished, the master must pull the SS line high to notify the slave. If Master Slave Select Enable (CTRLB.MSSEN) is set to '0', the software must pull the SS line high.

32.6.2.6.2 Slave

In slave mode (CTRLA.MODE=0x2), the SPI interface will remain inactive with the MISO line tri-stated as long as the SS pin is pulled high. Software may update the contents of DATA at any time as long as the Data Register Empty flag in the Interrupt Status and Clear register (INTFLAG.DRE) is set. When SS is pulled low and SCK is running, the slave will sample and shift out data according to the transaction mode set. When the content of TxDATA has been loaded into the shift register, INTFLAG.DRE will be set, and new data can be written to DATA. Similar to the master, the slave will receive one character for each character transmitted. A character will be transferred into the two-level receive buffer within the same clock cycle its last data bit is received. The received character can be retrieved from DATA when the Receive Complete interrupt flag (INTFLAG.RXC) is set. When the master pulls the SS line high, the transaction is done and the Transmit Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set. After DATA is written it takes up to three SCK clock cycles until the content of DATA is ready to be loaded into the shift register on the next character boundary. As a consequence, the first character transferred in a SPI transaction will not be the content of DATA. This can be avoided by using the preloading feature. Refer to 32.6.3.2 Preloading of the Slave Shift Register. When transmitting several characters in one SPI transaction, the data has to be written into DATA register with at least three SCK clock cycles left in the current character transmission. If this criteria is not met, the previously received character will be transmitted. Once the DATA register is empty, it takes three CLK_SERCOM_APB cycles for INTFLAG.DRE to be set.

32.6.2.7 Receiver Error Bit

The SPI receiver has one error bit: the Buffer Overflow bit (BUFOVF), which can be read from the Status register (STATUS). Once an error happens, the bit will stay set until it is cleared by writing '1' to it. The bit is also automatically cleared when the receiver is disabled. There are two methods for buffer overflow notification, selected by the immediate buffer overflow notification bit in the Control A register (CTRLA.IBON): If CTRLA.IBON=1, STATUS.BUFOVF is raised immediately upon buffer overflow. Software can then empty the receive FIFO by reading RxDATA until the receiver complete interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) goes low. If CTRLA.IBON=0, the buffer overflow condition travels with data through the receive FIFO. After the received data is read, STATUS.BUFOVF and INTFLAG.ERROR will be set along with INTFLAG.RXC, and RxDATA will be zero. SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 594

32.6.3 Additional Features

32.6.3.1 Address Recognition

When the SPI is configured for slave operation (CTRLA.MODE=0x2) with address recognition (CTRLA.FORM is 0x2), the SERCOM address recognition logic is enabled: the first character in a transaction is checked for an address match. If there is a match, the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set, the MISO output is enabled, and the transaction is processed. If the device is in sleep mode, an address match can wake up the device in order to process the transaction. If there is no match, the complete transaction is ignored. If a 9-bit frame format is selected, only the lower 8 bits of the shift register are checked against the Address register (ADDR). Preload must be disabled (CTRLB.PLOADEN=0) in order to use this mode. Related Links

32.6.3.2 Preloading of the Slave Shift Register

When starting a transaction, the slave will first transmit the contents of the shift register before loading new data from DATA. The first character sent can be either the reset value of the shift register (if this is the first transmission since the last reset) or the last character in the previous transmission. Preloading can be used to preload data into the shift register while SS is high: this eliminates sending a dummy character when starting a transaction. If the shift register is not preloaded, the current contents of the shift register will be shifted out. Only one data character will be preloaded into the shift register while the synchronized SS signal is high. If the next character is written to DATA before SS is pulled low, the second character will be stored in DATA until transfer begins. For proper preloading, sufficient time must elapse between SS going low and the first SCK sampling edge, as in Timing Using Preloading. See also Electrical Characteristics for timing details. Preloading is enabled by writing '1' to the Slave Data Preload Enable bit in the CTRLB register (CTRLB.PLOADEN). Figure 32-4. Timing Using Preloading _SS _SS synchronized to system domain SCK Synchronization to system domain MISO to SCK setup time Required _SS-to-SCK time using PRELOADEN

32.6.3.3 Master with Several Slaves

Master with multiple slaves in parallel is only available when Master Slave Select Enable (CTRLB.MSSEN) is set to zero and hardware SS control is disabled. If the bus consists of several SPI SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 595

slaves, an SPI master can use general purpose I/O pins to control the SS line to each of the slaves on the bus, as shown in Multiple Slaves in Parallel. In this configuration, the single selected SPI slave will drive the tri-state MISO line. Figure 32-5. Multiple Slaves in Parallel MOSI MISO SCK _SS MOSI MISO SCK _SS[0] MOSI MISO SCK _SS _SS[n-1] shift register shift register shift register SPI Master SPI Slave 0 SPI Slave n-1 Another configuration is multiple slaves in series, as in Multiple Slaves in Series. In this configuration, all n attached slaves are connected in series. A common SS line is provided to all slaves, enabling them simultaneously. The master must shift n characters for a complete transaction. Depending on the Master Slave Select Enable bit (CTRLB.MSSEN), the SS line can be controlled either by hardware or user software and normal GPIO. Figure 32-6. Multiple Slaves in Series MOSI MISO SCK _SS MOSI MISO SCK _SS MOSI MISO SCK _SS shift register shift register shift register SPI Master SPI Slave 0 SPI Slave n-1

32.6.3.4 Loop-Back Mode

For loop-back mode, configure the Data In Pinout (CTRLA.DIPO) and Data Out Pinout (CTRLA.DOPO) to use the same data pins for transmit and receive. The loop-back is through the pad, so the signal is also available externally.

32.6.3.5 Hardware Controlled

In master mode, a single SS chip select can be controlled by hardware by writing the Master Slave Select Enable (CTRLB.MSSEN) bit to '1'. In this mode, the SS pin is driven low for a minimum of one baud cycle before transmission begins, and stays low for a minimum of one baud cycle after transmission completes. If back-to-back frames are transmitted, the SS pin will always be driven high for a minimum of one baud cycle between frames. In Hardware Controlled SS, the time T is between one and two baud cycles depending on the SPI transfer mode. SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 596

Figure 32-7. Hardware Controlled SS _SS SCK T T = 1 to 2 baud cycles T T TT When CTRLB.MSSEN=0, the SS pin(s) is/are controlled by user software and normal GPIO.

32.6.3.6 Slave Select Low Detection

In slave mode, the SPI can wake the CPU when the slave select (SS) goes low. When the Slave Select Low Detect is enabled (CTRLB.SSDE=1), a high-to-low transition will set the Slave Select Low interrupt flag (INTFLAG.SSL) and the device will wake up if applicable.

32.6.4 DMA, Interrupts, and Events

Table 32-4. Module Request for SERCOM SPI Condition Request DMA Interrupt Event Data Register Empty (DRE) Yes (request cleared when data is written) Yes NA Receive Complete (RXC) Yes (request cleared when data is read) Yes Transmit Complete (TXC) NA Yes Slave Select low (SSL) NA Yes Error (ERROR) NA Yes

32.6.4.1 DMA Operation

The SPI generates the following DMA requests:

Data received (RX): The request is set when data is available in the receive FIFO. The request is cleared when DATA is read.
Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is cleared when DATA is written.

32.6.4.2 Interrupts

The SPI has the following interrupt sources. These are asynchronous interrupts, and can wake up the device from any sleep mode:

Data Register Empty (DRE)
Receive Complete (RXC)
Transmit Complete (TXC)
Slave Select Low (SSL)
Error (ERROR) SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 597

Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the interrupt condition is met. Each interrupt can be individually enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and if the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the SPI is reset. For details on clearing interrupt flags, refer to the INTFLAG register description. The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for interrupt requests. Refer to Nested Vector Interrupt Controller for details. Related Links

32.6.4.3 Events

Not applicable.

32.6.5 Sleep Mode Operation

The behavior in sleep mode is depending on the master/slave configuration and the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY):

Master operation, CTRLA.RUNSTDBY=1: The peripheral clock GCLK_SERCOM_CORE will continue to run in idle sleep mode and in standby sleep mode. Any interrupt can wake up the device.
Master operation, CTRLA.RUNSTDBY=0: GLK_SERCOMx_CORE will be disabled after the ongoing transaction is finished. Any interrupt can wake up the device.
Slave operation, CTRLA.RUNSTDBY=1: The Receive Complete interrupt can wake up the device.
Slave operation, CTRLA.RUNSTDBY=0: All reception will be dropped, including the ongoing transaction.

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written:

Software Reset bit in the CTRLA register (CTRLA.SWRST)
Enable bit in the CTRLA register (CTRLA.ENABLE)
Receiver Enable bit in the CTRLB register (CTRLB.RXEN) Note: CTRLB.RXEN is write-synchronized somewhat differently. See also CTRLB register for details. Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Related Links

32.7 Register Summary

Offset Name Bit Pos. 0x00 CTRLA 7:0 RUNSTDBY MODE[2:0] ENABLE SWRST 15:8 IBON 23:16 DIPO[1:0] DOPO[1:0] 31:24 DORD CPOL CPHA FORM[3:0] 0x04 CTRLB 7:0 PLOADEN CHSIZE[2:0] 15:8 AMODE[1:0] MSSEN SSDE 23:16 RXEN 31:24 0x08 ... 0x0B Reserved 0x0C BAUD 7:0 BAUD[7:0] 0x0D ... 0x13 Reserved 0x14 INTENCLR 7:0 ERROR SSL RXC TXC DRE 0x15 Reserved 0x16 INTENSET 7:0 ERROR SSL RXC TXC DRE 0x17 Reserved 0x18 INTFLAG 7:0 ERROR SSL RXC TXC DRE 0x19 Reserved 0x1A STATUS 7:0 BUFOVF 15:8 0x1C SYNCBUSY 7:0 CTRLB ENABLE SWRST 15:8 23:16 31:24 0x20 ... 0x23 Reserved 0x24 ADDR 7:0 ADDR[7:0] 15:8 23:16 ADDRMASK[7:0] 31:24 0x28 DATA 7:0 DATA[7:0] 15:8 DATA[8:8] 0x2A ... 0x2F Reserved 0x30 DBGCTRL 7:0 DBGSTOP SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 599

32.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-Synchronized" and/or "Write-Synchronized" property in each individual register description. Refer to Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write- Protection" property in each individual register description. Refer to 32.5.8 Register Access Protection. SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 600

32.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 DORD CPOL CPHA FORM[3:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIPO[1:0] DOPO[1:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 IBON Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 RUNSTDBY MODE[2:0] ENABLE SWRST Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 30 – DORD Data Order This bit selects the data order when a character is shifted out from the shift register. This bit is not synchronized. Value Description 0 MSB is transferred first. 1 LSB is transferred first. Bit 29 – CPOL Clock Polarity In combination with the Clock Phase bit (CPHA), this bit determines the SPI transfer mode. This bit is not synchronized. Value Description 0 SCK is low when idle. The leading edge of a clock cycle is a rising edge, while the trailing edge is a falling edge. 1 SCK is high when idle. The leading edge of a clock cycle is a falling edge, while the trailing edge is a rising edge. Bit 28 – CPHA Clock Phase In combination with the Clock Polarity bit (CPOL), this bit determines the SPI transfer mode. This bit is not synchronized. SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 601

Mode CPOL CPHA Leading Edge Trailing Edge 0x0 0 0 Rising, sample Falling, change 0x1 0 1 Rising, change Falling, sample 0x2 1 0 Falling, sample Rising, change 0x3 1 1 Falling, change Rising, sample Value Description 0 The data is sampled on a leading SCK edge and changed on a trailing SCK edge. 1 The data is sampled on a trailing SCK edge and changed on a leading SCK edge. Bits 27:24 – FORM[3:0] Frame Format This bit field selects the various frame formats supported by the SPI in slave mode. When the 'SPI frame with address' format is selected, the first byte received is checked against the ADDR register. FORM[3:0] Name Description 0x0 SPI SPI frame 0x1 - Reserved 0x2 SPI_ADDR SPI frame with address 0x3-0xF - Reserved Bits 21:20 – DIPO[1:0] Data In Pinout These bits define the data in (DI) pad configurations. In master operation, DI is MISO. In slave operation, DI is MOSI. These bits are not synchronized. DIPO[1:0] Name Description 0x0 PAD[0] SERCOM PAD[0] is used as data input 0x1 PAD[1] SERCOM PAD[1] is used as data input 0x2 PAD[2] SERCOM PAD[2] is used as data input 0x3 PAD[3] SERCOM PAD[3] is used as data input Bits 17:16 – DOPO[1:0] Data Out Pinout This bit defines the available pad configurations for data out (DO) and the serial clock (SCK). In slave operation, the slave select line ( SS) is controlled by DOPO, while in master operation the SS line is controlled by the port configuration. In master operation, DO is MOSI. In slave operation, DO is MISO. These bits are not synchronized. DOPO DO SCK Slave SS Master SS 0x0 PAD[0] PAD[1] PAD[2] System configuration 0x1 PAD[2] PAD[3] PAD[1] System configuration SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 602

DOPO DO SCK Slave SS Master SS 0x2 PAD[3] PAD[1] PAD[2] System configuration 0x3 PAD[0] PAD[3] PAD[1] System configuration Bit 8 – IBON Immediate Buffer Overflow Notification This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is set when a buffer overflow occurs. This bit is not synchronized. Value Description 0 STATUS.BUFOVF is set when it occurs in the data stream. 1 STATUS.BUFOVF is set immediately upon buffer overflow. Bit 7 – RUNSTDBY Run In Standby This bit defines the functionality in standby sleep mode. These bits are not synchronized. RUNSTDBY Slave Master 0x0 Disabled. All reception is dropped, including the ongoing transaction. Generic clock is disabled when ongoing transaction is finished. All interrupts can wake up the device. 0x1 Ongoing transaction continues, wake on Receive Complete interrupt. Generic clock is enabled while in sleep modes. All interrupts can wake up the device. Bits 4:2 – MODE[2:0] Operating Mode These bits must be written to 0x2 or 0x3 to select the SPI serial communication interface of the SERCOM. 0x2: SPI slave operation 0x3: SPI master operation These bits are not synchronized. Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/ disabled. The value written to CTRL.ENABLE will read back immediately and the Synchronization Enable Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the operation is complete. This bit is not enable-protected. Value Description 0 The peripheral is disabled or being disabled. 1 The peripheral is enabled or being enabled. Bit 0 – SWRST Software Reset Writing '0' to this bit has no effect. Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 603

Writing ''1' to CTRL.SWRST will always take precedence, meaning that all other writes in the same write- operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY. SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Value Description 0 There is no reset operation ongoing. 1 The reset operation is ongoing. SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 604

32.8.2 Control B

Name: CTRLB Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 RXEN Access R/W Reset 0 Bit 15 14 13 12 11 10 9 8 AMODE[1:0] MSSEN SSDE Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PLOADEN CHSIZE[2:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 17 – RXEN Receiver Enable Writing '0' to this bit will disable the SPI receiver immediately. The receive buffer will be flushed, data from ongoing receptions will be lost and STATUS.BUFOVF will be cleared. Writing '1' to CTRLB.RXEN when the SPI is disabled will set CTRLB.RXEN immediately. When the SPI is enabled, CTRLB.RXEN will be cleared, SYNCBUSY.CTRLB will be set and remain set until the receiver is enabled. When the receiver is enabled CTRLB.RXEN will read back as '1'. Writing '1' to CTRLB.RXEN when the SPI is enabled will set SYNCBUSY.CTRLB, which will remain set until the receiver is enabled, and CTRLB.RXEN will read back as '1'. This bit is not enable-protected. Value Description 0 The receiver is disabled or being enabled. 1 The receiver is enabled or it will be enabled when SPI is enabled. Bits 15:14 – AMODE[1:0] Address Mode These bits set the slave addressing mode when the frame format (CTRLA.FORM) with address is used. They are unused in master mode. AMODE[1:0] Name Description 0x0 MASK ADDRMASK is used as a mask to the ADDR register 0x1 2_ADDRS The slave responds to the two unique addresses in ADDR and ADDRMASK SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 605

AMODE[1:0] Name Description 0x2 RANGE The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit 0x3 - Reserved Bit 13 – MSSEN Master Slave Select Enable This bit enables hardware slave select (SS) control. Value Description 0 Hardware SS control is disabled. 1 Hardware SS control is enabled. Bit 9 – SSDE Slave Select Low Detect Enable This bit enables wake up when the slave select (SS) pin transitions from high to low. Value Description 0 SS low detector is disabled. 1 SS low detector is enabled. Bit 6 – PLOADEN Slave Data Preload Enable Setting this bit will enable preloading of the slave shift register when there is no transfer in progress. If the SS line is high when DATA is written, it will be transferred immediately to the shift register. Bits 2:0 – CHSIZE[2:0] Character Size CHSIZE[2:0] Name Description 0x0 8BIT 8 bits 0x1 9BIT 9 bits 0x2-0x7 - Reserved SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 606

32.8.3 Baud Rate

Name: BAUD Offset: 0x0C Reset: 0x00 Property: PAC Write-Protection, Enable-Protected Bit 7 6 5 4 3 2 1 0 BAUD[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – BAUD[7:0] Baud Register These bits control the clock generation, as described in the SERCOM Clock Generation – Baud-Rate Generator. Related Links SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 607

32.8.4 Interrupt Enable Clear

Name: INTENCLR Offset: 0x14 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 5 4 3 2 1 0 ERROR SSL RXC TXC DRE Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 – ERROR Error Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. Value Description 0 Error interrupt is disabled. 1 Error interrupt is enabled. Bit 3 – SSL Slave Select Low Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Slave Select Low Interrupt Enable bit, which disables the Slave Select Low interrupt. Value Description 0 Slave Select Low interrupt is disabled. 1 Slave Select Low interrupt is enabled. Bit 2 – RXC Receive Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete interrupt. Value Description 0 Receive Complete interrupt is disabled. 1 Receive Complete interrupt is enabled. Bit 1 – TXC Transmit Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Transmit Complete Interrupt Enable bit, which disable the Transmit Complete interrupt. Value Description 0 Transmit Complete interrupt is disabled. 1 Transmit Complete interrupt is enabled. Bit 0 – DRE Data Register Empty Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register Empty interrupt. SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 608

0 Data Register Empty interrupt is disabled. 1 Data Register Empty interrupt is enabled. SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 609

32.8.5 Interrupt Enable Set

Name: INTENSET Offset: 0x16 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 5 4 3 2 1 0 ERROR SSL RXC TXC DRE Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 – ERROR Error Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. Value Description 0 Error interrupt is disabled. 1 Error interrupt is enabled. Bit 3 – SSL Slave Select Low Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Slave Select Low Interrupt Enable bit, which enables the Slave Select Low interrupt. Value Description 0 Slave Select Low interrupt is disabled. 1 Slave Select Low interrupt is enabled. Bit 2 – RXC Receive Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive Complete interrupt. Value Description 0 Receive Complete interrupt is disabled. 1 Receive Complete interrupt is enabled. Bit 1 – TXC Transmit Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete interrupt. Value Description 0 Transmit Complete interrupt is disabled. 1 Transmit Complete interrupt is enabled. Bit 0 – DRE Data Register Empty Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register Empty interrupt. SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 610

32.8.6 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x18 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 ERROR SSL RXC TXC DRE Access R/W R/W R R/W R Reset 0 0 0 0 0 Bit 7 – ERROR Error This flag is cleared by writing '1' to it. This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS register. The BUFOVF error will set this interrupt flag. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 3 – SSL Slave Select Low This flag is cleared by writing '1' to it. This bit is set when a high to low transition is detected on the _SS pin in slave mode and Slave Select Low Detect (CTRLB.SSDE) is enabled. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 2 – RXC Receive Complete This flag is cleared by reading the Data (DATA) register or by disabling the receiver. This flag is set when there are unread data in the receive buffer. If address matching is enabled, the first data received in a transaction will be an address. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. Bit 1 – TXC Transmit Complete This flag is cleared by writing '1' to it or by writing new data to DATA. In master mode, this flag is set when the data have been shifted out and there are no new data in DATA. In slave mode, this flag is set when the _SS pin is pulled high. If address matching is enabled, this flag is only set if the transaction was initiated with an address match. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 0 – DRE Data Register Empty This flag is cleared by writing new data to DATA. This flag is set when DATA is empty and ready for new data to transmit. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 612

32.8.7 Status

Name: STATUS Offset: 0x1A Reset: 0x0000 Property: – Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 BUFOVF Access R/W Reset 0 Bit 2 – BUFOVF Buffer Overflow Reading this bit before reading DATA will indicate the error status of the next character to be read. This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set when a buffer overflow condition is detected. See also CTRLA.IBON for overflow handling. When set, the corresponding RxDATA will be zero. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Value Description 0 No Buffer Overflow has occurred. 1 A Buffer Overflow has occurred. SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 613

32.8.8 Synchronization Busy

Name: SYNCBUSY Offset: 0x1C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CTRLB ENABLE SWRST Access R R R Reset 0 0 0 Bit 2 – CTRLB CTRLB Synchronization Busy Writing to the CTRLB when the SERCOM is enabled requires synchronization. Ongoing synchronization is indicated by SYNCBUSY.CTRLB=1 until synchronization is complete. If CTRLB is written while SYNCBUSY.CTRLB=1, an APB error will be generated. Value Description 0 CTRLB synchronization is not busy. 1 CTRLB synchronization is busy. Bit 1 – ENABLE SERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. Ongoing synchronization is indicated by SYNCBUSY.ENABLE=1 until synchronization is complete. Value Description 0 Enable synchronization is not busy. 1 Enable synchronization is busy. Bit 0 – SWRST Software Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. Ongoing synchronization is indicated by SYNCBUSY.SWRST=1 until synchronization is complete. Value Description 0 SWRST synchronization is not busy. 1 SWRST synchronization is busy. SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 614

32.8.9 Address

Name: ADDR Offset: 0x24 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 ADDRMASK[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 23:16 – ADDRMASK[7:0] Address Mask These bits hold the address mask when the transaction format with address is used (CTRLA.FORM, CTRLB.AMODE). Bits 7:0 – ADDR[7:0] Address These bits hold the address when the transaction format with address is used (CTRLA.FORM, CTRLB.AMODE). SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 615

32.8.10 Data

Name: DATA Offset: 0x28 Reset: 0x0000 Property: – Bit 15 14 13 12 11 10 9 8 DATA[8:8] Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 8:0 – DATA[8:0] Data Reading these bits will return the contents of the receive data buffer. The register should be read only when the Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set. Writing these bits will write the transmit data buffer. This register should be written only when the Data Register Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set. SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 616

32.8.11 Debug Control

Name: DBGCTRL Offset: 0x30 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DBGSTOP Access R/W Reset 0 Bit 0 – DBGSTOP Debug Stop Mode This bit controls the functionality when the CPU is halted by an external debugger. Value Description debugger. 1 The baud-rate generator is halted when the CPU is halted by an external debugger. SAM C20/C21 Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 617

SERCOM I 2C – Inter-Integrated Circuit

33.1 Overview

The inter-integrated circuit ( I2C) interface is one of the available modes in the serial communication interface (SERCOM). The I2C interface uses the SERCOM transmitter and receiver configured as shown in Figure 33-1. Labels in capital letters are registers accessible by the CPU, while lowercase labels are internal to the SERCOM. A SERCOM instance can be configured to be either an I2C master or an I2C slave. Both master and slave have an interface containing a shift register, a transmit buffer and a receive buffer. In addition, the I2C master uses the SERCOM baud-rate generator, while the I2C slave uses the SERCOM address match logic. Related Links 30. SERCOM – Serial Communication Interface

33.2 Features

SERCOM I2C includes the following features:

Master or slave operation
Can be used with DMA
Philips I 2C compatible
SMBus ™ compatible
PMBus compatible
Support of 100kHz and 400kHz, 1MHz and 3.4MHz I 2C mode
4-Wire operation supported
Physical interface includes: – Slew-rate limited outputs – Filtered inputs
Slave operation: – Operation in all sleep modes – Wake-up on address match – 7-bit and 10-bit Address match in hardware for: – • Unique address and/or 7-bit general call address
Address range
Two unique addresses can be used with DMA Related Links

33.3 Block Diagram

Figure 33-1. I2C Single-Master Single-Slave Interconnection BAUD TxDATA RxDATA baud rate generator SCL hold low shift register TxDATA RxDATA shift register 0 0 0 0 SCL hold low ADDR/ADDRMASK SDA SCL Master Slave

33.4 Signal Description

Signal Name Type Description PAD[0] Digital I/O SDA PAD[1] Digital I/O SCL PAD[2] Digital I/O SDA_OUT (4-wire operation) PAD[3] Digital I/O SCL_OUT (4-wire operation) One signal can be mapped on several pins. Not all the pins are I2C pins. Related Links 6. I/O Multiplexing and Considerations 33.6.3.3 4-Wire Mode

33.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

33.5.1 I/O Lines

In order to use the I/O lines of this peripheral, the I/O pins must be configured using the I/O Pin Controller (PORT). When the SERCOM is used in I2C mode, the SERCOM controls the direction and value of the I/O pins. If the receiver or transmitter is disabled, these pins can be used for other purposes. Related Links 28. PORT - I/O Pin Controller SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 619

33.5.2 Power Management

This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake up the device from sleep modes. Related Links 19. PM – Power Manager

33.5.3 Clocks

The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Main Clock Controller. Refer to Peripheral Clock Masking for details and default status of this clock. Two generic clocks are used by SERCOM, GCLK_SERCOMx_CORE and GCLK_SERCOM_SLOW. The core clock (GCLK_SERCOMx_CORE) can clock the I2C when working as a master. The slow clock (GCLK_SERCOM_SLOW) is required only for certain functions, e.g. SMBus timing. These two clocks must be configured and enabled in the Generic Clock Controller (GCLK) before using the I2C. These generic clocks are asynchronous to the bus clock (CLK_SERCOMx_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to 33.6.6 Synchronization for further details. Related Links 16. GCLK - Generic Clock Controller

PM – Power Manager

33.5.4 DMA

33.5.5 Interrupts

33.5.6 Events

Not applicable.

33.5.7 Debug Operation

When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result during debugging. This peripheral can be forced to halt operation during debugging - refer to the Debug Control (DBGCTRL) register for details.

33.5.8 Register Access Protection

Registers with write-access can be write-protected optionally by the peripheral access controller (PAC). SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 620

PAC Write-Protection is not available for the following registers:

Interrupt Flag Clear and Status register (INTFLAG)
Status register (STATUS)
Data register (DATA)
Address register (ADDR) Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger. Related Links 11. PAC - Peripheral Access Controller

33.5.9 Analog Connections

Not applicable.

33.6 Functional Description

33.6.1 Principle of Operation

The I2C interface uses two physical lines for communication:

Serial Data Line (SDA) for data transfer
Serial Clock Line (SCL) for the bus clock A transaction starts with the I2C master sending the start condition, followed by a 7-bit address and a direction bit (read or write to/from the slave). The addressed I2C slave will then acknowledge (ACK) the address, and data packet transactions can begin. Every 9-bit data packet consists of 8 data bits followed by a one-bit reply indicating whether the data was acknowledged or not. If a data packet is not acknowledged (NACK), whether by the I2C slave or master, the I2C master takes action by either terminating the transaction by sending the stop condition, or by sending a repeated start to transfer more data. The figure below illustrates the possible transaction formats and Transaction Diagram Symbols explains the transaction symbols. These symbols will be used in the following descriptions. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 621

Figure 33-2. Transaction Diagram Symbols S Sr A A R W P START condition repeated START condition STOP condition Master driving bus Slave driving bus Either Master or Slave driving bus Acknowledge (ACK) Not Acknowledge (NACK) Master Read Master Write Bus Driver Special Bus Conditions Data Package Direction Acknowledge '1' '0' '0' '1' Figure 33-3. Basic I2C Transaction Diagram SDA SCL S ADDRESS R/W ACK DATA ACK DATA ACK/NACK P S ADDRESS R/W A DATA PA DATA A/A Direction Address Packet Data Packet #0 Data Packet #1 Transaction

33.6.2 Basic Operation

33.6.2.1 Initialization

The following registers are enable-protected, meaning they can be written only when the I2C interface is disabled (CTRLA.ENABLE is ‘0’):

Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST) bits
Control B register (CTRLB), except Acknowledge Action (CTRLB.ACKACT) and Command (CTRLB.CMD) bits
Baud register (BAUD)
Address register (ADDR) in slave operation. When the I2C is enabled or is being enabled (CTRLA.ENABLE=1), writing to these registers will be discarded. If the I2C is being disabled, writing to these registers will be completed after the disabling. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 622

Enable-protection is denoted by the "Enable-Protection" property in the register description. Before the I2C is enabled it must be configured as outlined by the following steps: 1. Select I 2C Master or Slave mode by writing 0x4 (Slave mode) or 0x5 (Master mode) to the Operating Mode bits in the CTRLA register (CTRLA.MODE). 2. If desired, select the SDA Hold Time value in the CTRLA register (CTRLA.SDAHOLD). 3. If desired, enable smart operation by setting the Smart Mode Enable bit in the CTRLB register (CTRLB.SMEN). 4. If desired, enable SCL low time-out by setting the SCL Low Time-Out bit in the Control A register (CTRLA.LOWTOUT). 5. In Master mode: 5.1. Select the inactive bus time-out in the Inactive Time-Out bit group in the CTRLA register (CTRLA.INACTOUT). 5.2. Write the Baud Rate register (BAUD) to generate the desired baud rate. In Slave mode: 5.1. Configure the address match configuration by writing the Address Mode value in the CTRLB register (CTRLB.AMODE). 5.2. Set the Address and Address Mask value in the Address register (ADDR.ADDR and ADDR.ADDRMASK) according to the address configuration.

33.6.2.2 Enabling, Disabling, and Resetting

33.6.2.3 I 2C Bus State Logic

The bus state logic includes several logic blocks that continuously monitor the activity on the I2C bus lines in all sleep modes with running GCLK_SERCOM_x clocks. The start and stop detectors and the bit counter are all essential in the process of determining the current bus state. The bus state is determined according to Bus State Diagram. Software can get the current bus state by reading the Master Bus State bits in the Status register (STATUS.BUSSTATE). The value of STATUS.BUSSTATE in the figure is shown in binary. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 623

Figure 33-4. Bus State Diagram RESET Write ADDR to generate Start Condition IDLE (0b01) Start Condition BUSY (0b11)Timeout or Stop Condition UNKNOWN (0b00) OWNER (0b10) Lost Arbitration Repeated Start Condition Write ADDR to generate Repeated Start Condition Stop Condition Timeout or Stop Condition The bus state machine is active when the I2C master is enabled. After the I2C master has been enabled, the bus state is UNKNOWN (0b00). From the UNKNOWN state, the bus will transition to IDLE (0b01) by either:

Forcing by writing 0b01 to STATUS.BUSSTATE
A stop condition is detected on the bus
If the inactive bus time-out is configured for SMBus compatibility (CTRLA.INACTOUT) and a time-out occurs. Note: Once a known bus state is established, the bus state logic will not re-enter the UNKNOWN state. When the bus is IDLE it is ready for a new transaction. If a start condition is issued on the bus by another I2C master in a multi-master setup, the bus becomes BUSY (0b11). The bus will re-enter IDLE either when a stop condition is detected, or when a time-out occurs (inactive bus time-out needs to be configured). If a start condition is generated internally by writing the Address bit group in the Address register (ADDR.ADDR) while IDLE, the OWNER state (0b10) is entered. If the complete transaction was performed without interference, i.e., arbitration was not lost, the I2C master can issue a stop condition, which will change the bus state back to IDLE. However, if a packet collision is detected while in OWNER state, the arbitration is assumed lost and the bus state becomes BUSY until a stop condition is detected. A repeated start condition will change the bus state only if arbitration is lost while issuing a repeated start. Note: Violating the protocol may cause the I2C to hang. If this happens it is possible to recover from this state by a software reset (CTRLA.SWRST='1'). Related Links

33.10.1 CTRLA

33.6.2.4 I 2C Master Operation

The I2C master is byte-oriented and interrupt based. The number of interrupts generated is kept at a minimum by automatic handling of most incidents. The software driver complexity and code size are reduced by auto-triggering of operations, and a special smart mode, which can be enabled by the Smart Mode Enable bit in the Control A register (CTRLA.SMEN). The I2C master has two interrupt strategies. When SCL Stretch Mode (CTRLA.SCLSM) is '0', SCL is stretched before or after the acknowledge bit . In this mode the I2C master operates according to Master Behavioral Diagram (SCLSM=0). The circles labelled "Mn" (M1, M2..) indicate the nodes the bus logic can jump to, based on software or hardware interaction. This diagram is used as reference for the description of the I2C master operation throughout the document. Figure 33-5. I2C Master Behavioral Diagram (SCLSM=0) IDLE S BUSYBUSY P Sr P R DATA Wait for IDLE ADDRESS W A/ADATA APPLICATION SW SW Sr P BUSY M4ASW A/A A/A A/A A IDLE IDLE Slave Bus INTERRUPT + SCL HOLD Master Bus INTERRUPT + SCL HOLD SW SW SW BUSYR/W SW Software interaction A A R/W BUSY M4 The master provides data on the bus Addressed slave provides data on the bus In the second strategy (CTRLA.SCLSM=1), interrupts only occur after the ACK bit, as in Master Behavioral Diagram (SCLSM=1). This strategy can be used when it is not necessary to check DATA before acknowledging. Note: I2C High-speed (Hs) mode requires CTRLA.SCLSM=1. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 625

Figure 33-6. I2C Master Behavioral Diagram (SCLSM=1) IDLE S BUSYBUSY P Sr P R DATA W A/ADATA APPLICATION SW SW Sr P BUSY M4SW A/A A IDLE IDLE Master Bus INTERRUPT + SCL HOLD SW SW SW BUSYR/W A A R/W BUSY M4 SW Software interaction The master provides data on the bus Addressed slave provides data on the bus Slave Bus INTERRUPT + SCL HOLD Wait for IDLE ADDRESS

33.6.2.4.1 Master Clock Generation

The SERCOM peripheral supports several I2C bidirectional modes:

Standard mode ( Sm) up to 100kHz
Fast mode ( Fm) up to 400kHz
Fast mode Plus ( Fm+) up to 1MHz
High-speed mode ( Hs) up to 3.4MHz The Master clock configuration for Sm, Fm, and Fm+ are described in Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus). For Hs, refer to Master Clock Generation (High-Speed Mode). Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus) In I2C Sm, Fm, and Fm+ mode, the Master clock (SCL) frequency is determined as described in this section: The low (TLOW) and high (THIGH) times are determined by the Baud Rate register (BAUD), while the rise (TRISE) and fall (TFALL) times are determined by the bus topology. Because of the wired-AND logic of the bus, TFALL will be considered as part of TLOW. Likewise, TRISE will be in a state between TLOW and THIGH until a high state has been detected. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 626

Figure 33-7. SCL Timing TSU;STO THD;STA TBUF TFALL TLOW TRISE THIGH SCL SDA P S TSU;STA Sr The following parameters are timed using the SCL low time period TLOW. This comes from the Master Baud Rate Low bit group in the Baud Rate register (BAUD.BAUDLOW). When BAUD.BAUDLOW=0, or the Master Baud Rate bit group in the Baud Rate register (BAUD.BAUD) determines it.

T LOW – Low period of SCL clock
T SU;STO – Set-up time for stop condition
T BUF – Bus free time between stop and start conditions
T HD;STA – Hold time (repeated) start condition
T SU;STA – Set-up time for repeated start condition
T HIGH is timed using the SCL high time count from BAUD.BAUD
T RISE is determined by the bus impedance; for internal pull-ups. Refer to Electrical Characteristics.
T FALL is determined by the open-drain current limit and bus impedance; can typically be regarded as zero. Refer to Electrical Characteristics for details. The SCL frequency is given by: ?SCL = ͳ ?LOW + ?HIGH + ?RISE When BAUD.BAUDLOW is zero, the BAUD.BAUD value is used to time both SCL high and SCL low. In this case the following formula will give the SCL frequency: ?SCL = ?GCLK When BAUD.BAUDLOW is non-zero, the following formula determines the SCL frequency: ?SCL = ?GCLK The following formulas can determine the SCL TLOW and THIGH times: ?GCLK ?GCLK SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 627

Note: The I2C standard Fm+ (Fast-mode plus) requires a nominal high to low SCL ratio of 1:2, and BAUD should be set accordingly. At a minimum, BAUD.BAUD and/or BAUD.BAUDLOW must be non- zero. Startup Timing The minimum time between SDA transition and SCL rising edge is 6 APB cycles when the DATA register is written in smart mode. If a greater startup time is required due to long rise times, the time between DATA write and IF clear must be controlled by software. Note: When timing is controlled by user, the Smart Mode cannot be enabled. Related Links 45. Electrical Characteristics 85°C (SAM C20/C21 E/G/J) Master Clock Generation (High-Speed Mode) For I2C Hs transfers, there is no SCL synchronization. Instead, the SCL frequency is determined by the GCLK_SERCOMx_CORE frequency (fGCLK) and the High-Speed Baud setting in the Baud register (BAUD.HSBAUD). When BAUD.HSBAUDLOW=0, the HSBAUD value will determine both SCL high and SCL low. In this case the following formula determines the SCL frequency. ?SCL = ?GCLK When HSBAUDLOW is non-zero, the following formula determines the SCL frequency. ?SCL = ?GCLK Note: The I2C standard Hs (High-speed) requires a nominal high to low SCL ratio of 1:2, and HSBAUD should be set accordingly. At a minimum, BAUD.HSBAUD and/or BAUD.HSBAUDLOW must be non- zero.

33.6.2.4.2 Transmitting Address Packets

The I2C master starts a bus transaction by writing the I2C slave address to ADDR.ADDR and the direction bit, as described in 33.6.1 Principle of Operation. If the bus is busy, the I2C master will wait until the bus becomes idle before continuing the operation. When the bus is idle, the I2C master will issue a start condition on the bus. The I2C master will then transmit an address packet using the address written to ADDR.ADDR. After the address packet has been transmitted by the I2C master, one of four cases will arise according to arbitration and transfer direction. Case 1: Arbitration lost or bus error during address packet transmission If arbitration was lost during transmission of the address packet, the Master on Bus bit in the Interrupt Flag Status and Clear register (INTFLAG.MB) and the Arbitration Lost bit in the Status register (STATUS.ARBLOST) are both set. Serial data output to SDA is disabled, and the SCL is released, which disables clock stretching. In effect the I2C master is no longer allowed to execute any operation on the bus until the bus is idle again. A bus error will behave similarly to the arbitration lost condition. In this case, the MB interrupt flag and Master Bus Error bit in the Status register (STATUS.BUSERR) are both set in addition to STATUS.ARBLOST. The Master Received Not Acknowledge bit in the Status register (STATUS.RXNACK) will always contain the last successfully received acknowledge or not acknowledge indication. In this case, software will typically inform the application code of the condition and then clear the interrupt flag before exiting the interrupt routine. No other flags have to be cleared at this moment, because all flags will be cleared automatically the next time the ADDR.ADDR register is written. Case 2: Address packet transmit complete – No ACK received SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 628

If there is no I2C slave device responding to the address packet, then the INTFLAG.MB interrupt flag and STATUS.RXNACK will be set. The clock hold is active at this point, preventing further activity on the bus. The missing ACK response can indicate that the I2C slave is busy with other tasks or sleeping. Therefore, it is not able to respond. In this event, the next step can be either issuing a stop condition (recommended) or resending the address packet by a repeated start condition. When using SMBus logic, the slave must ACK the address. If there is no response, it means that the slave is not available on the bus. Case 3: Address packet transmit complete – Write packet, Master on Bus set If the I2C master receives an acknowledge response from the I2C slave, INTFLAG.MB will be set and STATUS.RXNACK will be cleared. The clock hold is active at this point, preventing further activity on the bus. In this case, the software implementation becomes highly protocol dependent. Three possible actions can enable the I2C operation to continue:

Initiate a data transmit operation by writing the data byte to be transmitted into DATA.DATA.
Transmit a new address packet by writing ADDR.ADDR. A repeated start condition will automatically be inserted before the address packet.
Issue a stop condition, consequently terminating the transaction. Case 4: Address packet transmit complete – Read packet, Slave on Bus set If the I2C master receives an ACK from the I2C slave, the I2C master proceeds to receive the next byte of data from the I2C slave. When the first data byte is received, the Slave on Bus bit in the Interrupt Flag register (INTFLAG.SB) will be set and STATUS.RXNACK will be cleared. The clock hold is active at this point, preventing further activity on the bus. In this case, the software implementation becomes highly protocol dependent. Three possible actions can enable the I2C operation to continue:
Let the I 2C master continue to read data by acknowledging the data received. ACK can be sent by software, or automatically in smart mode.
Transmit a new address packet.
Terminate the transaction by issuing a stop condition. Note: An ACK or NACK will be automatically transmitted if smart mode is enabled. The Acknowledge Action bit in the Control B register (CTRLB.ACKACT) determines whether ACK or NACK should be sent.

33.6.2.4.3 Transmitting Data Packets

When an address packet with direction Master Write (see Figure 33-3) was transmitted successfully , INTFLAG.MB will be set. The I2C master will start transmitting data via the I2C bus by writing to DATA.DATA, and monitor continuously for packet collisions. I If a collision is detected, the I2C master will lose arbitration and STATUS.ARBLOST will be set. If the transmit was successful, the I2C master will receive an ACK bit from the I2C slave, and STATUS.RXNACK will be cleared. INTFLAG.MB will be set in both cases, regardless of arbitration outcome. It is recommended to read STATUS.ARBLOST and handle the arbitration lost condition in the beginning of the I2C Master on Bus interrupt. This can be done as there is no difference between handling address and data packet arbitration. STATUS.RXNACK must be checked for each data packet transmitted before the next data packet transmission can commence. The I2C master is not allowed to continue transmitting data packets if a NACK is received from the I2C slave. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 629

33.6.2.4.4 Receiving Data Packets (SCLSM=0)

When INTFLAG.SB is set, the I2C master will already have received one data packet. The I2C master must respond by sending either an ACK or NACK. Sending a NACK may be unsuccessful when arbitration is lost during the transmission. In this case, a lost arbitration will prevent setting INTFLAG.SB. Instead, INTFLAG.MB will indicate a change in arbitration. Handling of lost arbitration is the same as for data bit transmission.

33.6.2.4.5 Receiving Data Packets (SCLSM=1)

When INTFLAG.SB is set, the I2C master will already have received one data packet and transmitted an ACK or NACK, depending on CTRLB.ACKACT. At this point, CTRLB.ACKACT must be set to the correct value for the next ACK bit, and the transaction can continue by reading DATA and issuing a command if not in the smart mode.

33.6.2.4.6 High-Speed Mode

High-speed transfers are a multi-step process, see High Speed Transfer. First, a master code (0b00001nnn, where 'nnn' is a unique master code) is transmitted in Full-speed mode, followed by a NACK since no slaveshould acknowledge. Arbitration is performed only during the Full-speed Master Code phase. The master code is transmitted by writing the master code to the address register (ADDR.ADDR) and writing the high-speed bit (ADDR.HS) to '0'. After the master code and NACK have been transmitted, the master write interrupt will be asserted. In the meanwhile, the slave address can be written to the ADDR.ADDR register together with ADDR.HS=1. Now in High-speed mode, the master will generate a repeated start, followed by the slave address with RW-direction. The bus will remain in High-speed mode until a stop is generated. If a repeated start is desired, the ADDR.HS bit must again be written to '1', along with the new address ADDR.ADDR to be transmitted. Figure 33-8. High Speed Transfer S A A/ASr PA DATA N Data Packets Master Code R/WADDRESS Sr ADDRESS Hs-mode continues F/S-modeHs-modeF/S-mode Transmitting in High-speed mode requires the I2C master to be configured in High-speed mode (CTRLA.SPEED=0x2) and the SCL clock stretch mode (CTRLA.SCLSM) bit set to '1'. 33.6.2.4.7 10-Bit Addressing When 10-bit addressing is enabled by the Ten Bit Addressing Enable bit in the Address register (ADDR.TENBITEN=1) and the Address bit field ADDR.ADDR is written, the two address bytes will be transmitted, see 10-bit Address Transmission for a Read Transaction. The addressed slave acknowledges the two address bytes, and the transaction continues. Regardless of whether the transaction is a read or write, the master must start by sending the 10-bit address with the direction bit (ADDR.ADDR[0]) being zero. If the master receives a NACK after the first byte, the write interrupt flag will be raised and the STATUS.RXNACK bit will be set. If the first byte is acknowledged by one or more slaves, then the master will proceed to transmit the second address byte and the master will first see the write interrupt flag after the second byte is transmitted. If the transaction direction is read-from-slave, the 10-bit address transmission must be followed by a repeated start and the first 7 bits of the address with the read/write bit equal to '1'. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 630

Figure 33-9. 10-bit Address Transmission for a Read Transaction S AW addr[7:0] A11110 addr[9:8] Sr AR S W 11110 addr[9:8] MB INTERRUPT This implies the following procedure for a 10-bit read operation: 1. Write the 10-bit address to ADDR.ADDR[10:1]. ADDR.TENBITEN must be '1', the direction bit (ADDR.ADDR[0]) must be '0' (can be written simultaneously with ADDR). 2. Once the Master on Bus interrupt is asserted, Write ADDR[7:0] register to '11110 address[9:8] 1'. ADDR.TENBITEN must be cleared (can be written simultaneously with ADDR). 3. Proceed to transmit data.

33.6.2.5 I 2C Slave Operation

The I2C slave is byte-oriented and interrupt-based. The number of interrupts generated is kept at a minimum by automatic handling of most events. The software driver complexity and code size are reduced by auto-triggering of operations, and a special smart mode, which can be enabled by the Smart Mode Enable bit in the Control A register (CTRLA.SMEN). The I2C slave has two interrupt strategies. When SCL Stretch Mode bit (CTRLA.SCLSM) is '0', SCL is stretched before or after the acknowledge bit. In this mode, the I2C slave operates according to I2C Slave Behavioral Diagram (SCLSM=0). The circles labelled "Sn" (S1, S2..) indicate the nodes the bus logic can jump to, based on software or hardware interaction. This diagram is used as reference for the description of the I2C slave operation throughout the document. Figure 33-10. I2C Slave Behavioral Diagram (SCLSM=0) S ADDRESSS2 A R W DATA A/A DATA P S2 Sr S3 P S2 Sr S3 A S W S W S W S W A A/A A S1 S W Interrupt on STOP Condition Enabled S W Software interaction The master provides data on the bus Addressed slave provides data on the bus AMATCH INTERRUPT DRDY INTERRUPT PREC INTERRUPT SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 631

In the second strategy (CTRLA.SCLSM=1), interrupts only occur after the ACK bit is sent as shown in Slave Behavioral Diagram (SCLSM=1). This strategy can be used when it is not necessary to check DATA before acknowledging. For master reads, an address and data interrupt will be issued simultaneously after the address acknowledge. However, for master writes, the first data interrupt will be seen after the first data byte has been received by the slave and the acknowledge bit has been sent to the master. Note: For I2C High-speed mode (Hs), SCLSM=1 is required. Figure 33-11. I2C Slave Behavioral Diagram (SCLSM=1) S ADDRESSS2 R W DATA A/A DATA P S2 Sr S3 P S2 Sr S3 S W S W S WA/A S W Interrupt on STOP Condition Enabled S W Software interaction The master provides data on the bus Addressed slave provides data on the bus A/A A/A PREC INTERRUPT AMATCH INTERRUPT (+ DRDY INTERRUPT in Master Read mode) DRDY INTERRUPT

33.6.2.5.1 Receiving Address Packets (SCLSM=0)

When CTRLA.SCLSM=0, the I2C slave stretches the SCL line according to Figure 33-10. When the I2C slave is properly configured, it will wait for a start condition. When a start condition is detected, the successive address packet will be received and checked by the address match logic. If the received address is not a match, the packet will be rejected, and the I2C slave will wait for a new start condition. If the received address is a match, the Address Match bit in the Interrupt Flag register (INTFLAG.AMATCH) will be set. SCL will be stretched until the I2C slave clears INTFLAG.AMATCH. As the I2C slave holds the clock by forcing SCL low, the software has unlimited time to respond. The direction of a transaction is determined by reading the Read / Write Direction bit in the Status register (STATUS.DIR). This bit will be updated only when a valid address packet is received. If the Transmit Collision bit in the Status register (STATUS.COLL) is set, this indicates that the last packet addressed to the I2C slave had a packet collision. A collision causes the SDA and SCL lines to be released without any notification to software. Therefore, the next AMATCH interrupt is the first indication of the previous packet’s collision. Collisions are intended to follow the SMBus Address Resolution Protocol (ARP). After the address packet has been received from the I2C master, one of two cases will arise based on transfer direction. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 632

Case 1: Address packet accepted – Read flag set The STATUS.DIR bit is ‘1’, indicating an I2C master read operation. The SCL line is forced low, stretching the bus clock. If an ACK is sent, I2C slave hardware will set the Data Ready bit in the Interrupt Flag register (INTFLAG.DRDY), indicating data are needed for transmit. If a NACK is sent, the I2C slave will wait for a new start condition and address match. Typically, software will immediately acknowledge the address packet by sending an ACK/NACK bit. The I2C slave Command bit field in the Control B register (CTRLB.CMD) can be written to '0x3' for both read and write operations as the command execution is dependent on the STATUS.DIR bit. Writing ‘1’ to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit. Case 2: Address packet accepted – Write flag set The STATUS.DIR bit is cleared, indicating an I2C master write operation. The SCL line is forced low, stretching the bus clock. If an ACK is sent, the I2C slave will wait for data to be received. Data, repeated start or stop can be received. If a NACK is sent, the I2C slave will wait for a new start condition and address match. Typically, software will immediately acknowledge the address packet by sending an ACK/NACK. The I2C slave command CTRLB.CMD = 3 can be used for both read and write operation as the command execution is dependent on STATUS.DIR. Writing ‘1’ to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit.

33.6.2.5.2 Receiving Address Packets (SCLSM=1)

When SCLSM=1, the I2C slave will stretch the SCL line only after an ACK, see Slave Behavioral Diagram (SCLSM=1). When the I2C slave is properly configured, it will wait for a start condition to be detected. When a start condition is detected, the successive address packet will be received and checked by the address match logic. If the received address is not a match, the packet will be rejected and the I2C slave will wait for a new start condition. If the address matches, the acknowledge action as configured by the Acknowledge Action bit Control B register (CTRLB.ACKACT) will be sent and the Address Match bit in the Interrupt Flag register (INTFLAG.AMATCH) is set. SCL will be stretched until the I2C slave clears INTFLAG.AMATCH. As the I2C slave holds the clock by forcing SCL low, the software is given unlimited time to respond to the address. The direction of a transaction is determined by reading the Read/Write Direction bit in the Status register (STATUS.DIR). This bit will be updated only when a valid address packet is received. If the Transmit Collision bit in the Status register (STATUS.COLL) is set, the last packet addressed to the I2C slave had a packet collision. A collision causes the SDA and SCL lines to be released without any notification to software. The next AMATCH interrupt is, therefore, the first indication of the previous packet’s collision. Collisions are intended to follow the SMBus Address Resolution Protocol (ARP). After the address packet has been received from the I2C master, INTFLAG.AMATCH be set to ‘1’ to clear it.

33.6.2.5.3 Receiving and Transmitting Data Packets

After the I2C slave has received an address packet, it will respond according to the direction either by waiting for the data packet to be received or by starting to send a data packet by writing to DATA.DATA. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 633

When a data packet is received or sent, INTFLAG.DRDY will be set. After receiving data, the I2C slave will send an acknowledge according to CTRLB.ACKACT. Case 1: Data received INTFLAG.DRDY is set, and SCL is held low, pending for SW interaction. Case 2: Data sent When a byte transmission is successfully completed, the INTFLAG.DRDY interrupt flag is set. If NACK is received, indicated by STATUS.RXNACK=1, the I2C slave must expect a stop or a repeated start to be received. The I2C slave must release the data line to allow the I2C master to generate a stop or repeated start. Upon detecting a stop condition, the Stop Received bit in the Interrupt Flag register (INTFLAG.PREC) will be set and the I2C slave will return to IDLE state.

33.6.2.5.4 High-Speed Mode

When the I2C slave is configured in High-speed mode (Hs, CTRLA.SPEED=0x2) and CTRLA.SCLSM=1, switching between Full-speed and High-speed modes is automatic. When the slave recognizes a START followed by a master code transmission and a NACK, it automatically switches to High-speed mode and sets the High-speed status bit (STATUS.HS). The slave will then remain in High-speed mode until a STOP is received. 33.6.2.5.5 10-Bit Addressing When 10-bit addressing is enabled (ADDR.TENBITEN=1), the two address bytes following a START will be checked against the 10-bit slave address recognition. The first byte of the address will always be acknowledged, and the second byte will raise the address interrupt flag, see 10-bit Addressing. If the transaction is a write, then the 10-bit address will be followed by N data bytes. If the operation is a read, the 10-bit address will be followed by a repeated START and reception of '11110 ADDR[9:8] 1', and the second address interrupt will be received with the DIR bit set. The slave matches on the second address as it it was addressed by the previous 10-bit address. Figure 33-12. 10-bit Addressing S AW addr[7:0] A11110 addr[9:8] Sr RS W S W11110 addr[9:8] AMATCH INTERRUPT AMATCH INTERRUPT

33.6.2.5.6 PMBus Group Command

When the PMBus Group Command bit in the CTRLB register is set (CTRLB.GCMD=1) and 7-bit addressing is used, INTFLAG.PREC will be set if the slave has been addressed since the last STOP condition. When CTRLB.GCMD=0, a STOP condition without address match will not be set INTFLAG.PREC. The group command protocol is used to send commands to more than one device. The commands are sent in one continuous transmission with a single STOP condition at the end. When the STOP condition is detected by the slaves addressed during the group command, they all begin executing the command they received. PMBus Group Command Example shows an example where this slave, bearing ADDRESS 1, is addressed after a repeated START condition. There can be multiple slaves addressed before and after this slave. Eventually, at the end of the group command, a single STOP is generated by the master. At this point a STOP interrupt is asserted. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 634

Figure 33-13. PMBus Group Command Example AS A n BytesWADDRESS 0 Command/Data ASr A n BytesWADDRESS 1 (this slave) Command/Data S W S W ASr A n BytesWADDRESS 2 Command/Data P S W AMATCH INTERRUPT DRDY INTERRUPT PREC INTERRUPT

33.6.3 Additional Features

33.6.3.1 SMBus

The I2C includes three hardware SCL low time-outs which allow a time-out to occur for SMBus SCL low time-out, master extend time-out, and slave extend time-out. This allows for SMBus functionality These time-outs are driven by the GCLK_SERCOM_SLOW clock. The GCLK_SERCOM_SLOW clock is used to accurately time the time-out and must be configured to use a 32KHz oscillator. The I2C interface also allows for a SMBus compatible SDA hold time.

T TIMEOUT: SCL low time of 25..35ms – Measured for a single SCL low period. It is enabled by CTRLA.LOWTOUTEN.
T LOW:SEXT: Cumulative clock low extend time of 25 ms – Measured as the cumulative SCL low extend time by a slave device in a single message from the initial START to the STOP. It is enabled by CTRLA.SEXTTOEN.
T LOW:MEXT: Cumulative clock low extend time of 10 ms – Measured as the cumulative SCL low extend time by the master device within a single byte from START-to-ACK, ACK-to-ACK, or ACK-to- STOP. It is enabled by CTRLA.MEXTTOEN.

33.6.3.2 Smart Mode

The I2C interface has a smart mode that simplifies application code and minimizes the user interaction needed to adhere to the I2C protocol. The smart mode accomplishes this by automatically issuing an ACK or NACK (based on the content of CTRLB.ACKACT) as soon as DATA.DATA is read. 33.6.3.3 4-Wire Mode Writing a '1' to the Pin Usage bit in the Control A register (CTRLA.PINOUT) will enable 4-wire mode operation. In this mode, the internal I2C tri-state drivers are bypassed, and an external I2C compliant tri- state driver is needed when connecting to an I2C bus. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 635

Figure 33-14. I2C Pad Interface SCL/SDA pad I2C Driver SCL_OUT/ SDA_OUT padPINOUT PINOUT SCL_IN/ SDA_IN SCL_OUT/ SDA_OUT

33.6.3.4 Quick Command

Setting the Quick Command Enable bit in the Control B register (CTRLB.QCEN) enables quick command. When quick command is enabled, the corresponding interrupt flag (INTFLAG.SB or INTFLAG.MB) is set immediately after the slave acknowledges the address. At this point, the software can either issue a stop command or a repeated start by writing CTRLB.CMD or ADDR.ADDR.

33.6.4 DMA, Interrupts and Events

Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the interrupt condition is meet. Each interrupt can be individually enabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request is active until the interrupt flag is cleared, the interrupt is disabled or the I2C is reset. See the 33.8.5 INTFLAG (Slave) or 33.10.6 INTFLAG (Master) register for details on how to clear interrupt flags. Table 33-1. Module Request for SERCOM I2C Slave Condition Request DMA Interrupt Event Data needed for transmit (TX) (Slave transmit mode) Yes (request cleared when data is written) NA Data received (RX) (Slave receive mode) Yes (request cleared when data is read) Data Ready (DRDY) Yes Address Match (AMATCH) Yes Stop received (PREC) Yes Error (ERROR) Yes SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 636

Table 33-2. Module Request for SERCOM I2C Master Condition Request DMA Interrupt Event Data needed for transmit (TX) (Master transmit mode) Yes (request cleared when data is written) NA Data needed for transmit (RX) (Master transmit mode) Yes (request cleared when data is read) Master on Bus (MB) Yes Stop received (SB) Yes Error (ERROR) Yes

33.6.4.1 DMA Operation

Smart mode must be enabled for DMA operation in the Control B register by writing CTRLB.SMEN=1.

33.6.4.1.1 Slave DMA

When using the I2C slave with DMA, an address match will cause the address interrupt flag (INTFLAG.ADDRMATCH) to be raised. After the interrupt has been serviced, data transfer will be performed through DMA. The I2C slave generates the following requests:

Write data received (RX): The request is set when master write data is received. The request is cleared when DATA is read.
Read data needed for transmit (TX): The request is set when data is needed for a master read operation. The request is cleared when DATA is written.

33.6.4.1.2 Master DMA

When using the I2C master with DMA, the ADDR register must be written with the desired address (ADDR.ADDR), transaction length (ADDR.LEN), and transaction length enable (ADDR.LENEN). When ADDR.LENEN is written to 1 along with ADDR.ADDR, ADDR.LEN determines the number of data bytes in the transaction from 0 to 255. DMA is then used to transfer ADDR.LEN bytes followed by an automatically generated NACK (for master reads) and a STOP. If a NACK is received by the slave for a master write transaction before ADDR.LEN bytes, a STOP will be automatically generated and the length error (STATUS.LENERR) will be raised along with the INTFLAG.ERROR interrupt. The I2C master generates the following requests:

Read data received (RX): The request is set when master read data is received. The request is cleared when DATA is read.
Write data needed for transmit (TX): The request is set when data is needed for a master write operation. The request is cleared when DATA is written. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 637

33.6.4.2 Interrupts

The I2C slave has the following interrupt sources. These are asynchronous interrupts. They can wake-up the device from any sleep mode:

Error (ERROR)
Data Ready (DRDY)
Address Match (AMATCH)
Stop Received (PREC) The I2C master has the following interrupt sources. These are asynchronous interrupts. They can wake- up the device from any sleep mode:
Error (ERROR)
Slave on Bus (SB)
Master on Bus (MB) Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the interrupt condition is meet. Each interrupt can be individually enabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request active until the interrupt flag is cleared, the interrupt is disabled or the I2C is reset. See the INTFLAG register for details on how to clear interrupt flags. The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for interrupt requests. Refer to Nested Vector Interrupt Controller for details. Related Links

33.6.4.3 Events

Not applicable.

33.6.5 Sleep Mode Operation

The generic clock (GCLK_SERCOMx_CORE) will continue to run in idle sleep mode. If the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY) is '1', the GLK_SERCOMx_CORE will also run in standby sleep mode. Any interrupt can wake up the device. If CTRLA.RUNSTDBY=0, the GLK_SERCOMx_CORE will be disabled after any ongoing transaction is finished. Any interrupt can wake up the device. I2C Slave Operation Writing CTRLA.RUNSTDBY=1 will allow the Address Match interrupt to wake up the device. When CTRLA.RUNSTDBY=0, all receptions will be dropped.

33.6.6 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written:

Software Reset bit in the CTRLA register (CTRLA.SWRST) SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 638

Enable bit in the CTRLA register (CTRLA.ENABLE)
Command bits in CTRLB register (CTRLB.CMD)
Write to Bus State bits in the Status register (STATUS.BUSSTATE)
Address bits in the Address register (ADDR.ADDR) when in master operation. The following registers are synchronized when written:
Data (DATA) when in master operation Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Related Links

33.7 Register Summary - I2C Slave

Offset Name Bit Pos. 0x00 CTRLA 7:0 RUNSTDBY MODE[2:0] ENABLE SWRST 15:8 23:16 SEXTTOEN SDAHOLD[1:0] PINOUT 31:24 LOWTOUT SCLSM SPEED[1:0] 0x04 CTRLB 7:0 15:8 AMODE[1:0] AACKEN GCMD SMEN 23:16 ACKACT CMD[1:0] 31:24 0x08 ... 0x13 Reserved 0x14 INTENCLR 7:0 ERROR DRDY AMATCH PREC 0x15 Reserved 0x16 INTENSET 7:0 ERROR DRDY AMATCH PREC 0x17 Reserved 0x18 INTFLAG 7:0 ERROR DRDY AMATCH PREC 0x19 Reserved 0x1A STATUS 7:0 CLKHOLD LOWTOUT SR DIR RXNACK COLL BUSERR 15:8 HS SEXTTOUT 0x1C SYNCBUSY 7:0 ENABLE SWRST 15:8 23:16 31:24 0x20 ... 0x23 Reserved 0x24 ADDR 7:0 ADDR[6:0] GENCEN 15:8 TENBITEN ADDR[9:7] 23:16 ADDRMASK[6:0] 31:24 ADDRMASK[9:7] 0x28 DATA 7:0 DATA[7:0] 15:8

33.8 Register Description - I 2C Slave

Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write- Synchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to 33.6.6 Synchronization. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 641

33.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 LOWTOUT SCLSM SPEED[1:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SEXTTOEN SDAHOLD[1:0] PINOUT Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 RUNSTDBY MODE[2:0] ENABLE SWRST Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 30 – LOWTOUT SCL Low Time-Out This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the slave will release its clock hold, if enabled, and reset the internal state machine. Any interrupt flags set at the time of time-out will remain set. Value Description 0 Time-out disabled. 1 Time-out enabled. Bit 27 – SCLSM SCL Clock Stretch Mode This bit controls when SCL will be stretched for software interaction. This bit is not synchronized. Value Description

0 SCL stretch according to Figure 33-10

1 SCL stretch only after ACK bit according to Figure 33-11

Bits 25:24 – SPEED[1:0] Transfer Speed These bits define bus speed. These bits are not synchronized. Value Description 0x0 Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz 0x1 Fast-mode Plus (Fm+) up to 1 MHz SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 642

0x2 High-speed mode (Hs-mode) up to 3.4 MHz 0x3 Reserved Bit 23 – SEXTTOEN Slave SCL Low Extend Time-Out This bit enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine. Any interrupt flags set at the time of time-out will remain set. If the address was recognized, PREC will be set when a STOP is received. This bit is not synchronized. Value Description

0 Time-out disabled

1 Time-out enabled

Bits 21:20 – SDAHOLD[1:0] SDA Hold Time These bits define the SDA hold time with respect to the negative edge of SCL. These bits are not synchronized. Value Name Description 0x0 DIS Disabled 0x1 75 50-100ns hold time 0x2 450 300-600ns hold time 0x3 600 400-800ns hold time Bit 16 – PINOUT Pin Usage This bit sets the pin usage to either two- or four-wire operation: This bit is not synchronized. Value Description 0 4-wire operation disabled 1 4-wire operation enabled Bit 7 – RUNSTDBY Run in Standby This bit defines the functionality in standby sleep mode. This bit is not synchronized. Value Description 0 Disabled – All reception is dropped. 1 Wake on address match, if enabled. Bits 4:2 – MODE[2:0] Operating Mode These bits must be written to 0x04 to select the I2C slave serial communication interface of the SERCOM. These bits are not synchronized. Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/ disabled. The value written to CTRL.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not enable-protected. Value Description 0 The peripheral is disabled or being disabled. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 643

1 The peripheral is enabled. Bit 0 – SWRST Software Reset Writing '0' to this bit has no effect. Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Value Description 0 There is no reset operation ongoing. 1 The reset operation is ongoing. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 644

33.8.2 Control B

0 Send ACK

1 Send NACK

Bits 17:16 – CMD[1:0] Command This bit field triggers the slave operation as the below. The CMD bits are strobe bits, and always read as zero. The operation is dependent on the slave interrupt flags, INTFLAG.DRDY and INTFLAG.AMATCH, in addition to STATUS.DIR. All interrupt flags (INTFLAG.DRDY, INTFLAG.AMATCH and INTFLAG.PREC) are automatically cleared when a command is given. This bit is not enable-protected. Table 33-3. Command Description CMD[1:0] DIR Action 0x0 X (No action) 0x1 X (Reserved) SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 645

CMD[1:0] DIR Action 0x2 Used to complete a transaction in response to a data interrupt (DRDY) 0 (Master write) Execute acknowledge action succeeded by waiting for any start (S/Sr) condition 1 (Master read) Wait for any start (S/Sr) condition 0x3 Used in response to an address interrupt (AMATCH) 0 (Master write) Execute acknowledge action succeeded by reception of next byte 1 (Master read) Execute acknowledge action succeeded by slave data interrupt Used in response to a data interrupt (DRDY) 0 (Master write) Execute acknowledge action succeeded by reception of next byte 1 (Master read) Execute a byte read operation followed by ACK/NACK reception Bits 15:14 – AMODE[1:0] Address Mode These bits set the addressing mode. These bits are not write-synchronized. Value Name Description 0x0 MASK The slave responds to the address written in ADDR.ADDR masked by the value in ADDR.ADDRMASK. See SERCOM – Serial Communication Interface for additional information. 0x1 2_ADDRS The slave responds to the two unique addresses in ADDR.ADDR and ADDR.ADDRMASK. 0x2 RANGE The slave responds to the range of addresses between and including 0x3 - Reserved. Bit 10 – AACKEN Automatic Acknowledge Enable This bit enables the address to be automatically acknowledged if there is an address match. This bit is not write-synchronized. Value Description 0 Automatic acknowledge is disabled. 1 Automatic acknowledge is enabled. Bit 9 – GCMD PMBus Group Command This bit enables PMBus group command support. When enabled, the Stop Recived interrupt flag (INTFLAG.PREC) will be set when a STOP condition is detected if the slave has been addressed since the last STOP condition on the bus. This bit is not write-synchronized. Value Description 0 Group command is disabled. 1 Group command is enabled. Bit 8 – SMEN Smart Mode Enable When smart mode is enabled, data is acknowledged automatically when DATA.DATA is read. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 646

This bit is not write-synchronized. Value Description 0 Smart mode is disabled. 1 Smart mode is enabled. Related Links 30. SERCOM – Serial Communication Interface SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 647

33.8.3 Interrupt Enable Clear

Name: INTENCLR Offset: 0x14 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 5 4 3 2 1 0 ERROR DRDY AMATCH PREC Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 – ERROR Error Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. Value Description 0 Error interrupt is disabled. 1 Error interrupt is enabled. Bit 2 – DRDY Data Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Data Ready bit, which disables the Data Ready interrupt. Value Description 0 The Data Ready interrupt is disabled. 1 The Data Ready interrupt is enabled. Bit 1 – AMATCH Address Match Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Address Match Interrupt Enable bit, which disables the Address Match interrupt. Value Description 0 The Address Match interrupt is disabled. 1 The Address Match interrupt is enabled. Bit 0 – PREC Stop Received Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Stop Received Interrupt Enable bit, which disables the Stop Received interrupt. Value Description 0 The Stop Received interrupt is disabled. 1 The Stop Received interrupt is enabled. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 648

33.8.4 Interrupt Enable Set

Name: INTENSET Offset: 0x16 Reset: 0x00 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 5 4 3 2 1 0 ERROR DRDY AMATCH PREC Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 – ERROR Error Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. Value Description 0 Error interrupt is disabled. 1 Error interrupt is enabled. Bit 2 – DRDY Data Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Data Ready bit, which enables the Data Ready interrupt. Value Description 0 The Data Ready interrupt is disabled. 1 The Data Ready interrupt is enabled. Bit 1 – AMATCH Address Match Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Address Match Interrupt Enable bit, which enables the Address Match interrupt. Value Description 0 The Address Match interrupt is disabled. 1 The Address Match interrupt is enabled. Bit 0 – PREC Stop Received Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Stop Received Interrupt Enable bit, which enables the Stop Received interrupt. Value Description 0 The Stop Received interrupt is disabled. 1 The Stop Received interrupt is enabled. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 649

33.8.5 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x18 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 ERROR DRDY AMATCH PREC Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 – ERROR Error This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS register. The corresponding bits in STATUS are SEXTTOUT, LOWTOUT, COLL, and BUSERR. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 2 – DRDY Data Ready This flag is set when a I2C slave byte transmission is successfully completed. The flag is cleared by hardware when either:

Writing to the DATA register.
Reading the DATA register with smart mode enabled.
Writing a valid command to the CMD register. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Data Ready interrupt flag. Bit 1 – AMATCH Address Match This flag is set when the I2C slave address match logic detects that a valid address has been received. The flag is cleared by hardware when CTRL.CMD is written. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Address Match interrupt flag. When cleared, an ACK/NACK will be sent according to CTRLB.ACKACT. Bit 0 – PREC Stop Received This flag is set when a stop condition is detected for a transaction being processed. A stop condition detected between a bus master and another slave will not set this flag, unless the PMBus Group Command is enabled in the Control B register (CTRLB.GCMD=1). This flag is cleared by hardware after a command is issued on the next address match. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Stop Received interrupt flag. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 650

33.8.6 Status

Name: STATUS Offset: 0x1A Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 HS SEXTTOUT Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 CLKHOLD LOWTOUT SR DIR RXNACK COLL BUSERR Access R R/W R R R R/W R/W Reset 0 0 0 0 0 0 0 Bit 10 – HS High-speed This bit is set if the slave detects a START followed by a Master Code transmission. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the status. However, this flag is automatically cleared when a STOP is received. Bit 9 – SEXTTOUT Slave SCL Low Extend Time-Out This bit is set if a slave SCL low extend time-out occurs. This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD) or when INTFLAG.AMATCH is cleared. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the status. Value Description 0 No SCL low extend time-out has occurred. 1 SCL low extend time-out has occurred. Bit 7 – CLKHOLD Clock Hold The slave Clock Hold bit (STATUS.CLKHOLD) is set when the slave is holding the SCL line low, stretching the I2C clock. Software should consider this bit a read-only status flag that is set when INTFLAG.DRDY or INTFLAG.AMATCH is set. This bit is automatically cleared when the corresponding interrupt is also cleared. Bit 6 – LOWTOUT SCL Low Time-out This bit is set if an SCL low time-out occurs. This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD) or when INTFLAG.AMATCH is cleared. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the status. Value Description 0 No SCL low time-out has occurred. 1 SCL low time-out has occurred. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 651

Bit 4 – SR Repeated Start When INTFLAG.AMATCH is raised due to an address match, SR indicates a repeated start or start condition. This flag is only valid while the INTFLAG.AMATCH flag is one. Value Description

0 Start condition on last address match

1 Repeated start condition on last address match

Bit 3 – DIR Read / Write Direction The Read/Write Direction (STATUS.DIR) bit stores the direction of the last address packet received from a master. Value Description 0 Master write operation is in progress. 1 Master read operation is in progress. Bit 2 – RXNACK Received Not Acknowledge This bit indicates whether the last data packet sent was acknowledged or not. Value Description 0 Master responded with ACK. 1 Master responded with NACK. Bit 1 – COLL Transmit Collision If set, the I2C slave was not able to transmit a high data or NACK bit, the I2C slave will immediately release the SDA and SCL lines and wait for the next packet addressed to it. This flag is intended for the SMBus address resolution protocol (ARP). A detected collision in non-ARP situations indicates that there has been a protocol violation, and should be treated as a bus error. Note that this status will not trigger any interrupt, and should be checked by software to verify that the data were sent correctly. This bit is cleared automatically if responding to an address match with an ACK or a NACK (writing 0x3 to CTRLB.CMD), or INTFLAG.AMATCH is cleared. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the status. Value Description 0 No collision detected on last data byte sent. 1 Collision detected on last data byte sent. Bit 0 – BUSERR Bus Error The Bus Error bit (STATUS.BUSERR) indicates that an illegal bus condition has occurred on the bus, regardless of bus ownership. An illegal bus condition is detected if a protocol violating start, repeated start or stop is detected on the I2C bus lines. A start condition directly followed by a stop condition is one example of a protocol violation. If a time-out occurs during a frame, this is also considered a protocol violation, and will set STATUS.BUSERR. This bit is cleared automatically if responding to an address match with an ACK or a NACK (writing 0x3 to CTRLB.CMD) or INTFLAG.AMATCH is cleared. Writing a '1' to this bit will clear the status. Writing a '0' to this bit has no effect. Value Description 0 No bus error detected. 1 Bus error detected. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 652

33.8.7 Synchronization Busy

Name: SYNCBUSY Offset: 0x1C Reset: 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ENABLE SWRST Access R R Reset 0 0 Bit 1 – ENABLE SERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNCBUSY.ENABLE bit will be set until synchronization is complete. Value Description 0 Enable synchronization is not busy. 1 Enable synchronization is busy. Bit 0 – SWRST Software Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will be set until synchronization is complete. Value Description 0 SWRST synchronization is not busy. 1 SWRST synchronization is busy. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 653

33.8.8 Address

Name: ADDR Offset: 0x24 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 ADDRMASK[9:7] Access R/W R/W R/W Reset 0 0 0 Bit 23 22 21 20 19 18 17 16 ADDRMASK[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 TENBITEN ADDR[9:7] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[6:0] GENCEN Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 26:17 – ADDRMASK[9:0] Address Mask These bits act as a second address match register, an address mask register or the lower limit of an address range, depending on the CTRLB.AMODE setting. Bit 15 – TENBITEN Ten Bit Addressing Enable Value Description 0 10-bit address recognition disabled. 1 10-bit address recognition enabled. Bits 10:1 – ADDR[9:0] Address These bits contain the I2C slave address used by the slave address match logic to determine if a master has addressed the slave. When using 7-bit addressing, the slave address is represented by ADDR[6:0]. When using 10-bit addressing (ADDR.TENBITEN=1), the slave address is represented by ADDR[9:0] When the address match logic detects a match, INTFLAG.AMATCH is set and STATUS.DIR is updated to indicate whether it is a read or a write transaction. Bit 0 – GENCEN General Call Address Enable A general call address is an address consisting of all-zeroes, including the direction bit (master write). Value Description 0 General call address recognition disabled. 1 General call address recognition enabled. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 654

33.8.9 Data

Name: DATA Offset: 0x28 Reset: 0x0000 Property: Write-Synchronized, Read-Synchronized Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – DATA[7:0] Data The slave data register I/O location (DATA.DATA) provides access to the master transmit and receive data buffers. Reading valid data or writing data to be transmitted can be successfully done only when SCL is held low by the slave (STATUS.CLKHOLD is set). An exception occurs when reading the last data byte after the stop condition has been received. Accessing DATA.DATA auto-triggers I2C bus operations. The operation performed depends on the state of CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write). Writing or reading DATA.DATA when not in smart mode does not require synchronization. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 655

33.9 Register Summary - I2C Master

Offset Name Bit Pos. 0x00 CTRLA 7:0 RUNSTDBY MODE[2:0] ENABLE SWRST 15:8 23:16 SEXTTOEN MEXTTOEN SDAHOLD[1:0] PINOUT 31:24 LOWTOUT INACTOUT[1:0] SCLSM SPEED[1:0] 0x04 CTRLB 7:0 15:8 QCEN SMEN 23:16 ACKACT CMD[1:0] 31:24 0x08 ... 0x0B Reserved 0x0C BAUD 7:0 BAUD[7:0] 15:8 BAUDLOW[7:0] 23:16 HSBAUD[7:0] 31:24 HSBAUDLOW[7:0] 0x10 ... 0x13 Reserved 0x14 INTENCLR 7:0 ERROR SB MB 0x15 Reserved 0x16 INTENSET 7:0 ERROR SB MB 0x17 Reserved 0x18 INTFLAG 7:0 ERROR SB MB 0x19 Reserved 0x1A STATUS 7:0 CLKHOLD LOWTOUT BUSSTATE[1:0] RXNACK ARBLOST BUSERR 15:8 LENERR SEXTTOUT MEXTTOUT 0x1C SYNCBUSY 7:0 SYSOP ENABLE SWRST 15:8 23:16 31:24 0x20 ... 0x23 Reserved 0x24 ADDR 7:0 ADDR[7:0] 15:8 TENBITEN HS LENEN ADDR[10:8] 23:16 LEN[7:0] 31:24 0x28 DATA 7:0 DATA[7:0] 15:8 0x2A ... 0x2F Reserved 0x30 DBGCTRL 7:0 DBGSTOP SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 656

33.10 Register Description - I 2C Master

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 33.5.8 Register Access Protection. Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write- Synchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to 33.6.6 Synchronization. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 657

33.10.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 LOWTOUT INACTOUT[1:0] SCLSM SPEED[1:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SEXTTOEN MEXTTOEN SDAHOLD[1:0] PINOUT Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 RUNSTDBY MODE[2:0] ENABLE SWRST Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 30 – LOWTOUT SCL Low Time-Out This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the master will release its clock hold, if enabled, and complete the current transaction. A stop condition will automatically be transmitted. INTFLAG.SB or INTFLAG.MB will be set as normal, but the clock hold will be released. The STATUS.LOWTOUT and STATUS.BUSERR status bits will be set. This bit is not synchronized. Value Description 0 Time-out disabled. 1 Time-out enabled. Bits 29:28 – INACTOUT[1:0] Inactive Time-Out If the inactive bus time-out is enabled and the bus is inactive for longer than the time-out setting, the bus state logic will be set to idle. An inactive bus arise when either an I2C master or slave is holding the SCL low. Enabling this option is necessary for SMBus compatibility, but can also be used in a non-SMBus set-up. Calculated time-out periods are based on a 100kHz baud rate. These bits are not synchronized. Value Name Description 0x0 DIS Disabled 0x1 55US 5-6 SCL cycle time-out (50-60µs) 0x2 105US 10-11 SCL cycle time-out (100-110µs) SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 658

0x3 205US 20-21 SCL cycle time-out (200-210µs) Bit 27 – SCLSM SCL Clock Stretch Mode This bit controls when SCL will be stretched for software interaction. This bit is not synchronized. Value Description 0 SCL stretch according to Figure 33-5. 1 SCL stretch only after ACK bit, Figure 33-6. Bits 25:24 – SPEED[1:0] Transfer Speed These bits define bus speed. These bits are not synchronized. Value Description 0x0 Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz 0x1 Fast-mode Plus (Fm+) up to 1 MHz 0x2 High-speed mode (Hs-mode) up to 3.4 MHz 0x3 Reserved Bit 23 – SEXTTOEN Slave SCL Low Extend Time-Out This bit enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the master will release its clock hold if enabled, and complete the current transaction. A STOP will automatically be transmitted. SB or MB will be set as normal, but CLKHOLD will be release. The MEXTTOUT and BUSERR status bits will be set. This bit is not synchronized. Value Description Bit 22 – MEXTTOEN Master SCL Low Extend Time-Out This bit enables the master SCL low extend time-out. If SCL is cumulatively held low for greater than 10ms from START-to-ACK, ACK-to-ACK, or ACK-to-STOP the master will release its clock hold if enabled, and complete the current transaction. A STOP will automatically be transmitted. SB or MB will be set as normal, but CLKHOLD will be released. The MEXTTOUT and BUSERR status bits will be set. This bit is not synchronized. Value Description Bits 21:20 – SDAHOLD[1:0] SDA Hold Time These bits define the SDA hold time with respect to the negative edge of SCL. These bits are not synchronized. Value Name Description 0x0 DIS Disabled 0x1 75NS 50-100ns hold time 0x2 450NS 300-600ns hold time 0x3 600NS 400-800ns hold time SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 659

Bit 16 – PINOUT Pin Usage This bit set the pin usage to either two- or four-wire operation: This bit is not synchronized. Value Description 0 4-wire operation disabled. 1 4-wire operation enabled. Bit 7 – RUNSTDBY Run in Standby This bit defines the functionality in standby sleep mode. This bit is not synchronized. Value Description

0 GCLK_SERCOMx_CORE is disabled and the I2C master will not operate in standby sleep

mode. 1 GCLK_SERCOMx_CORE is enabled in all sleep modes. Bits 4:2 – MODE[2:0] Operating Mode These bits must be written to 0x5 to select the I2C master serial communication interface of the SERCOM. These bits are not synchronized. Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/ disabled. The value written to CTRL.ENABLE will read back immediately and the Synchronization Enable Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not enable-protected. Value Description 0 The peripheral is disabled or being disabled. 1 The peripheral is enabled. Bit 0 – SWRST Software Reset Writing '0' to this bit has no effect. Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register. Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Value Description 0 There is no reset operation ongoing. 1 The reset operation is ongoing. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 660

33.10.2 Control B

Name: CTRLB Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 ACKACT CMD[1:0] Access R/W W W Reset 0 0 0 Bit 15 14 13 12 11 10 9 8 QCEN SMEN Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 Access Reset Bit 18 – ACKACT Acknowledge Action This bit defines the I2C master's acknowledge behavior after a data byte is received from the I2C slave. The acknowledge action is executed when a command is written to CTRLB.CMD, or if smart mode is enabled (CTRLB.SMEN is written to one), when DATA.DATA is read. This bit is not enable-protected. This bit is not write-synchronized. Value Description 0 Send ACK. 1 Send NACK. Bits 17:16 – CMD[1:0] Command Writing these bits triggers a master operation as described below. The CMD bits are strobe bits, and always read as zero. The acknowledge action is only valid in master read mode. In master write mode, a command will only result in a repeated start or stop condition. The CTRLB.ACKACT bit and the CMD bits can be written at the same time, and then the acknowledge action will be updated before the command is triggered. Commands can only be issued when either the Slave on Bus interrupt flag (INTFLAG.SB) or Master on Bus interrupt flag (INTFLAG.MB) is '1'. If CMD 0x1 is issued, a repeated start will be issued followed by the transmission of the current address in ADDR.ADDR. If another address is desired, ADDR.ADDR must be written instead of the CMD bits. This will trigger a repeated start followed by transmission of the new address. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 661

Issuing a command will set the System Operation bit in the Synchronization Busy register (SYNCBUSY.SYSOP). Table 33-4. Command Description CMD[1:0] Direction Action 0x0 X (No action) 0x1 X Execute acknowledge action succeeded by repeated Start 0x2 0 (Write) No operation 1 (Read) Execute acknowledge action succeeded by a byte read operation 0x3 X Execute acknowledge action succeeded by issuing a stop condition These bits are not enable-protected. Bit 9 – QCEN Quick Command Enable This bit is not write-synchronized. Value Description 0 Quick Command is disabled. 1 Quick Command is enabled. Bit 8 – SMEN Smart Mode Enable When smart mode is enabled, acknowledge action is sent when DATA.DATA is read. This bit is not write-synchronized. Value Description 0 Smart mode is disabled. 1 Smart mode is enabled. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 662

33.10.3 Baud Rate

Name: BAUD Offset: 0x0C Reset: 0x0000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 HSBAUDLOW[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 HSBAUD[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 BAUDLOW[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BAUD[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:24 – HSBAUDLOW[7:0] High Speed Master Baud Rate Low HSBAUDLOW non-zero: HSBAUDLOW indicates the SCL low time in High-speed mode according to HSBAUDLOW = ?GCLK ⋅ ?LOW − ͳ HSBAUDLOW equal to zero: The HSBAUD register is used to time TLOW, THIGH, TSU;STO, THD;STA and TSU;STA.. TBUF is timed by the BAUD register. Bits 23:16 – HSBAUD[7:0] High Speed Master Baud Rate This bit field indicates the SCL high time in High-speed mode according to the following formula. When HSBAUDLOW is zero, TLOW, THIGH, TSU;STO, THD;STA and TSU;STA are derived using this formula. TBUF is timed by the BAUD register. HSBAUD = ?GCLK ⋅ ?HIGH − ͳ Bits 15:8 – BAUDLOW[7:0] Master Baud Rate Low If this bit field is non-zero, the SCL low time will be described by the value written. For more information on how to calculate the frequency, see SERCOM

30.6.2.3 Clock Generation –

Baud-Rate Generator. Bits 7:0 – BAUD[7:0] Master Baud Rate This bit field is used to derive the SCL high time if BAUD.BAUDLOW is non-zero. If BAUD.BAUDLOW is zero, BAUD will be used to generate both high and low periods of the SCL. For more information on how to calculate the frequency, see SERCOM Baud-Rate Generator. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 663

33.10.4 Interrupt Enable Clear

33.10.5 Interrupt Enable Set

Name: INTENSET Offset: 0x16 Reset: 0x00 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 5 4 3 2 1 0 ERROR SB MB Access R/W R/W R/W Reset 0 0 0 Bit 7 – ERROR Error Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. Value Description 0 Error interrupt is disabled. 1 Error interrupt is enabled. Bit 1 – SB Slave on Bus Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Slave on Bus Interrupt Enable bit, which enables the Slave on Bus interrupt. Value Description 0 The Slave on Bus interrupt is disabled. 1 The Slave on Bus interrupt is enabled. Bit 0 – MB Master on Bus Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Master on Bus Interrupt Enable bit, which enables the Master on Bus interrupt. Value Description 0 The Master on Bus interrupt is disabled. 1 The Master on Bus interrupt is enabled. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 665

33.10.6 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x18 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 ERROR SB MB Access R/W R/W R/W Reset 0 0 0 Bit 7 – ERROR Error This flag is cleared by writing '1' to it. This bit is set when any error is detected. Errors that will set this flag have corresponding status bits in the STATUS register. These status bits are LENERR, SEXTTOUT, MEXTTOUT, LOWTOUT, ARBLOST, and BUSERR. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 1 – SB Slave on Bus The Slave on Bus flag (SB) is set when a byte is successfully received in master read mode, i.e., no arbitration lost or bus error occurred during the operation. When this flag is set, the master forces the SCL line low, stretching the I2C clock period. The SCL line will be released and SB will be cleared on one of the following actions:

Writing to ADDR.ADDR
Writing to DATA.DATA
Reading DATA.DATA when smart mode is enabled (CTRLB.SMEN)
Writing a valid command to CTRLB.CMD Writing '1' to this bit location will clear the SB flag. The transaction will not continue or be terminated until one of the above actions is performed. Writing '0' to this bit has no effect. Bit 0 – MB Master on Bus This flag is set when a byte is transmitted in master write mode. The flag is set regardless of the occurrence of a bus error or an arbitration lost condition. MB is also set when arbitration is lost during sending of NACK in master read mode, or when issuing a start condition if the bus state is unknown. When this flag is set and arbitration is not lost, the master forces the SCL line low, stretching the I2C clock period. The SCL line will be released and MB will be cleared on one of the following actions:
Writing to ADDR.ADDR
Writing to DATA.DATA
Reading DATA.DATA when smart mode is enabled (CTRLB.SMEN)
Writing a valid command to CTRLB.CMD Writing '1' to this bit location will clear the MB flag. The transaction will not continue or be terminated until one of the above actions is performed. Writing '0' to this bit has no effect. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 666

33.10.7 Status

Name: STATUS Offset: 0x1A Reset: 0x0000 Property: Write-Synchronized Bit 15 14 13 12 11 10 9 8 LENERR SEXTTOUT MEXTTOUT Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 CLKHOLD LOWTOUT BUSSTATE[1:0] RXNACK ARBLOST BUSERR Access R R/W R/W R/W R R/W R/W Reset 0 0 0 0 0 0 0 Bit 10 – LENERR Transaction Length Error This bit is set when automatic length is used for a DMA transaction and the slave sends a NACK before ADDR.LEN bytes have been written by the master. Writing '1' to this bit location will clear STATUS.LENERR. This flag is automatically cleared when writing to the ADDR register. Writing '0' to this bit has no effect. This bit is not write-synchronized. Bit 9 – SEXTTOUT Slave SCL Low Extend Time-Out This bit is set if a slave SCL low extend time-out occurs. This bit is automatically cleared when writing to the ADDR register. Writing '1' to this bit location will clear SEXTTOUT. Normal use of the I2C interface does not require the SEXTTOUT flag to be cleared by this method. Writing '0' to this bit has no effect. This bit is not write-synchronized. Bit 8 – MEXTTOUT Master SCL Low Extend Time-Out This bit is set if a master SCL low time-out occurs. Writing '1' to this bit location will clear STATUS.MEXTTOUT. This flag is automatically cleared when writing to the ADDR register. Writing '0' to this bit has no effect. This bit is not write-synchronized. Bit 7 – CLKHOLD Clock Hold This bit is set when the master is holding the SCL line low, stretching the I2C clock. Software should consider this bit when INTFLAG.SB or INTFLAG.MB is set. This bit is cleared when the corresponding interrupt flag is cleared and the next operation is given. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. This bit is not write-synchronized. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 667

Bit 6 – LOWTOUT SCL Low Time-Out This bit is set if an SCL low time-out occurs. Writing '1' to this bit location will clear this bit. This flag is automatically cleared when writing to the ADDR register. Writing '0' to this bit has no effect. This bit is not write-synchronized. Bits 5:4 – BUSSTATE[1:0] Bus State These bits indicate the current I2C bus state. When in UNKNOWN state, writing 0x1 to BUSSTATE forces the bus state into the IDLE state. The bus state cannot be forced into any other state. Writing BUSSTATE to idle will set SYNCBUSY.SYSOP. Value Name Description 0x0 UNKNOWN The bus state is unknown to the I2C master and will wait for a stop condition to be detected or wait to be forced into an idle state by software 0x1 IDLE The bus state is waiting for a transaction to be initialized 0x2 OWNER The I 2C master is the current owner of the bus 0x3 BUSY Some other I 2C master owns the bus Bit 2 – RXNACK Received Not Acknowledge This bit indicates whether the last address or data packet sent was acknowledged or not. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. This bit is not write-synchronized. Value Description 0 Slave responded with ACK. 1 Slave responded with NACK. Bit 1 – ARBLOST Arbitration Lost This bit is set if arbitration is lost while transmitting a high data bit or a NACK bit, or while issuing a start or repeated start condition on the bus. The Master on Bus interrupt flag (INTFLAG.MB) will be set when STATUS.ARBLOST is set. Writing the ADDR.ADDR register will automatically clear STATUS.ARBLOST. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. This bit is not write-synchronized. Bit 0 – BUSERR Bus Error This bit indicates that an illegal bus condition has occurred on the bus, regardless of bus ownership. An illegal bus condition is detected if a protocol violating start, repeated start or stop is detected on the I2C bus lines. A start condition directly followed by a stop condition is one example of a protocol violation. If a time-out occurs during a frame, this is also considered a protocol violation, and will set BUSERR. If the I2C master is the bus owner at the time a bus error occurs, STATUS.ARBLOST and INTFLAG.MB will be set in addition to BUSERR. Writing the ADDR.ADDR register will automatically clear the BUSERR flag. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. This bit is not write-synchronized. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 668

33.10.8 Synchronization Busy

Name: SYNCBUSY Offset: 0x1C Reset: 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 SYSOP ENABLE SWRST Access R R R Reset 0 0 0 Bit 2 – SYSOP System Operation Synchronization Busy Writing CTRLB.CMD, STATUS.BUSSTATE, ADDR, or DATA when the SERCOM is enabled requires synchronization. When written, the SYNCBUSY.SYSOP bit will be set until synchronization is complete. Value Description 0 System operation synchronization is not busy. 1 System operation synchronization is busy. Bit 1 – ENABLE SERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNCBUSY.ENABLE bit will be set until synchronization is complete. Value Description 0 Enable synchronization is not busy. 1 Enable synchronization is busy. Bit 0 – SWRST Software Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will be set until synchronization is complete. Value Description 0 SWRST synchronization is not busy. 1 SWRST synchronization is busy. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 669

33.10.9 Address

Name: ADDR Offset: 0x24 Reset: 0x0000 Property: Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 LEN[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 TENBITEN HS LENEN ADDR[10:8] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 23:16 – LEN[7:0] Transaction Length These bits define the transaction length of a DMA transaction from 0 to 255 bytes. The Transfer Length Enable (LENEN) bit must be written to '1' in order to use DMA. Bit 15 – TENBITEN Ten Bit Addressing Enable This bit enables 10-bit addressing. This bit can be written simultaneously with ADDR to indicate a 10-bit or 7-bit address transmission. Value Description 0 10-bit addressing disabled. 1 10-bit addressing enabled. Bit 14 – HS High Speed This bit enables High-speed mode for the current transfer from repeated START to STOP. This bit can be written simultaneously with ADDR for a high speed transfer. Value Description 0 High-speed transfer disabled. 1 High-speed transfer enabled. Bit 13 – LENEN Transfer Length Enable Value Description 0 Automatic transfer length disabled. 1 Automatic transfer length enabled. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 670

Bits 10:0 – ADDR[10:0] Address When ADDR is written, the consecutive operation will depend on the bus state: UNKNOWN: INTFLAG.MB and STATUS.BUSERR are set, and the operation is terminated. BUSY: The I2C master will await further operation until the bus becomes IDLE. IDLE: The I2C master will issue a start condition followed by the address written in ADDR. If the address is acknowledged, SCL is forced and held low, and STATUS.CLKHOLD and INTFLAG.MB are set. OWNER: A repeated start sequence will be performed. If the previous transaction was a read, the acknowledge action is sent before the repeated start bus condition is issued on the bus. Writing ADDR to issue a repeated start is performed while INTFLAG.MB or INTFLAG.SB is set. STATUS.BUSERR, STATUS.ARBLOST, INTFLAG.MB and INTFLAG.SB will be cleared when ADDR is written. The ADDR register can be read at any time without interfering with ongoing bus activity, as a read access does not trigger the master logic to perform any bus protocol related operations. The I2C master control logic uses bit 0 of ADDR as the bus protocol’s read/write flag (R/W); 0 for write and 1 for read. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 671

33.10.10 Data

Name: DATA Offset: 0x28 Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – DATA[7:0] Data The master data register I/O location (DATA) provides access to the master transmit and receive data buffers. Reading valid data or writing data to be transmitted can be successfully done only when SCL is held low by the master (STATUS.CLKHOLD is set). An exception is reading the last data byte after the stop condition has been sent. Accessing DATA.DATA auto-triggers I2C bus operations. The operation performed depends on the state of CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write). Writing or reading DATA.DATA when not in Smart mode does not require synchronization. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 672

33.10.11 Debug Control

Name: DBGCTRL Offset: 0x30 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DBGSTOP Access R/W Reset 0 Bit 0 – DBGSTOP Debug Stop Mode This bit controls functionality when the CPU is halted by an external debugger. Value Description debugger. 1 The baud-rate generator is halted when the CPU is halted by an external debugger. SAM C20/C21 Family Data Sheet SERCOM I2C – Inter-Integrated Circuit © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 673

CAN - Control Area Network

34.1 Overview

The Control Area Network (CAN) performs communication according to ISO 11898-1:2015 (Bosch CAN specification 2.0 part A,B, ISO CAN FD). The message storage is intended to be a single- or dual-ported Message RAM outside of the module.

34.2 Features

Conform with CAN protocol version 2.0 part A, B and ISO 11898-1:2015
Up to two Controller Area Network CAN – Supporting CAN2.0 A/B and CAN-FD (ISO 11898-1:2015)
CAN FD with up to 64 data bytes supported
CAN Error Logging
AUTOSAR optimized
SAE J1939 optimized
Two configurable Receive FIFOs
Separate signaling on reception of High-Priority Messages
Up to 64 dedicated Receive Buffers and up to 32 dedicated Transmit Buffers
Configurable Transmit FIFO, Transmit Queue, Transmit Event FIFO
Direct Message RAM access for CPU
Programmable Loop-Back Test mode
Maskable module interrupts
Power-down support; Debug on CAN support
Transfer rates: – 1 Mb/s for CAN 2.0 mode – 10 Mb/s for CAN-FD mode SAM C20/C21 Family Data Sheet CAN - Control Area Network © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 674

34.3 Block Diagram

Figure 34-1. CAN Block Diagram CAN NVIC GCLK USER INTF CAN CORE CAN_TX CAN_RX GCLK_CAN CAN interrupts SRAM High-Speed Bus AHB

34.4 Signal Description

Table 34-1. Signal Description Signal Description Type CAN_TX CAN transmit Digital output CAN_RX CAN receive Digital input Refer to for details on the pin mapping for this peripheral. One signal can be mapped to one of several pins. Related Links 6. I/O Multiplexing and Considerations

34.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

34.5.1 I/O Lines

Using the CAN’s I/O lines requires the I/O pins to be configured. Related Links 28. PORT - I/O Pin Controller

34.5.2 Power Management

The CAN will continue to operate in any Idle Sleep mode where the selected source clock is running. The CAN interrupts can be used to wake up the device from sleep modes. Refer to the Power Manager chapter for details on the different sleep modes. SAM C20/C21 Family Data Sheet CAN - Control Area Network © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 675

The CAN module has its own Low-Power mode. The clock sources cannot be halted while the CAN is enabled unless this mode is used. Refer to the section "Sleep Mode Operation" for additional information. Related Links

34.5.3 Clocks

An AHB clock (CLK_CAN_AHB) is required to clock the CAN. This clock can be configured in the Main Clock peripheral (MCLK) before using the CAN, and the default state of CLK_CAN_AHB can be found in the MCLK.AHBMASK register. A generic clock (GCLK_CAN) is required to clock the CAN. This clock must be configured and enabled in the generic clock controller before using the CAN. This generic clock is asynchronous to the bus clock (CLK_CAN_AHB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Related Links

GCLK - Generic Clock Controller

34.5.4 DMA

The CAN has a built-in Direct Memory Access (DMA) and will read/write data to/from the system RAM when a CAN transaction takes place. No CPU or DMA Controller (DMAC) resources are required. The DMAC can be used for debug messages functionality. Related Links 25. DMAC – Direct Memory Access Controller

34.5.5 Interrupts

The interrupt request lines are connected to the interrupt controller. Using the CAN interrupts requires the interrupt controller to be configured first. Related Links

34.5.6 Events

Not applicable.

34.5.7 Debug Operation

Not applicable.

34.5.8 Register Access Protection

Not applicable.

34.5.9 Analog Connections

34.6 Functional Description

34.6.1 Principle of Operation

The CAN performs communication according to ISO 11898-1:2015 (identical to Bosch CAN protocol specification 2.0 part A,B, ISO CAN FD). The message storage is intended to be a single- or dual-ported Message RAM outside the module. It is connected to the CAN via AHB. All functions concerning the handling of messages are implemented by the Rx Handler and the Tx Handler. The Rx Handler manages message acceptance filtering, the transfer of received messages from the CAN Core to the Message RAM as well as providing receive message status information. The Tx Handler is responsible for the transfer of transmit messages from the Message RAM to the CAN Core as well as providing transmit status information. Acceptance filtering is implemented by a combination of up to 128 filter elements where each one can be configured as a range, as a bit mask, or as a dedicated ID filter.

34.6.2 Operating Modes

34.6.2.1 Software Initialization

Software initialization is started by setting bit CCCR.INIT, either by software or by a hardware reset, when an uncorrected bit error was detected in the Message RAM, or by going Bus_Off. While CCCR.INIT is set, message transfer from and to the CAN bus is stopped, the status of the CAN bus output CAN_TX is ”recessive” (HIGH). The counters of the Error Management Logic EML are unchanged. Setting CCCR.INIT does not change any configuration register. Resetting CCCR.INIT finishes the software initialization. Afterwards the Bit Stream Processor BSP synchronizes itself to the data transfer on the CAN bus by waiting for the occurrence of a sequence of 11 consecutive ”recessive” bits (= Bus_Idle) before it can take part in bus activities and start the message transfer. Access to the CAN configuration registers is only enabled when both bits CCCR.INIT and CCCR.CCE are set (protected write). CCCR.CCE can only be set/reset while CCCR.INIT = ‘1’. CCCR.CCE is automatically reset when CCCR.INIT is reset. The following registers are reset when CCCR.CCE is set

HPMS - High Priority Message Status
RXF0S - Rx FIFO 0 Status
RXF1S - Rx FIFO 1 Status
TXFQS - Tx FIFO/Queue Status
TXBRP - Tx Buffer Request Pending
TXBTO - Tx Buffer Transmission Occurred
TXBCF - Tx Buffer Cancellation Finished
TXEFS - Tx Event FIFO Status The Timeout Counter value TOCV.TOC is preset to the value configured by TOCC.TOP when CCCR.CCE is set. In addition the state machines of the Tx Handler and Rx Handler are held in idle state while CCCR.CCE = ‘1’. The following registers are only writable while CCCR.CCE = ‘0’ SAM C20/C21 Family Data Sheet CAN - Control Area Network © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 677

TXBAR - Tx Buffer Add Request
TXBCR - Tx Buffer Cancellation Request Both bits may be reset at any time. CCCR.DAR can only be set/reset while CCCR.INIT = ‘1’ and CCCR.CCE = ‘1’.

34.6.2.2 Normal Operation

Once the CAN is initialized and CCCR.INIT is reset to ‘0’, the CAN synchronizes itself to the CAN bus and is ready for communication. After passing the acceptance filtering, received messages including Message ID and DLC are stored into a dedicated Rx Buffer or into Rx FIFO0 or Rx FIFO1. For messages to be transmitted dedicated Tx Buffers and/or a Tx FIFO or a Tx Queue can be initialized or updated. Automated transmission on reception of remote frames is not implemented.

34.6.2.3 CAN FD Operation

There are two variants in the CAN FD frame format, first the CAN FD frame without bit rate switching where the data field of a CAN frame may be longer than 8 bytes. The second variant is the CAN FD frame where control field, data field, and CRC field of a CAN frame are transmitted with a higher bit rate than the beginning and the end of the frame. The previously reserved bit in CAN frames with 11-bit identifiers and the first previously reserved bit in CAN frames with 29-bit identifiers will now be decoded as FDF bit. FDF = recessive signifies a CAN FD frame, FDF = dominant signifies a Classic CAN frame. In a CAN FD frame, the two bits following FDF, res and BRS, decide whether the bit rate inside of this CAN FD frame is switched. A CAN FD bit rate switch is signified by res = dominant and BRS = recessive. The coding of res = recessive is reserved for future expansion of the protocol. In case the CAN receives a frame with FDF = recessive and res = recessive, it will signal a Protocol Exception Event by setting bit PSR.PXE. When Protocol Exception Handling is enabled (CCCR.PXHD = ‘0’), this causes the operation state to change from Receiver (PSR.ACT = “10”) to Integrating (PSR.ACT = “00”) at the next sample point. In case Protocol Exception Handling is disabled (CCCR.PXHD = ‘1’), the CAN will treat a recessive res bit as a form error and will respond with an error frame. CAN FD operation is enabled by programming CCCR.FDOE. In case CCCR.FDOE = ‘1’, transmission and reception of CAN FD frames is enabled. Transmission and reception of Classic CAN frames is always possible. Whether a CAN FD frame or a Classic CAN frame is transmitted can be configured via bit FDF in the respective Tx Buffer element. With CCCR.FDOE = ‘0’, received frames are interpreted as Classic CAN frames, witch leads to the transmission of an error frame when receiving a CAN FD frame. When CAN FD operation is disabled, no CAN FD frames are transmitted even if bit FDF of a Tx Buffer are both set. With CCCR.FDOE = ‘0’, the setting of bits FDF and BRS is ignored and frames are transmitted in Classic CAN format. With CCCR.FDOE = ‘1’ and CCCR.BRSE = ‘0’, only bit FDF of a Tx Buffer element is evaluated. With CCCR.FDOE = ‘1’ and CCCR.BRSE = ‘1’, transmission of CAN FD frames with bit rate switching is enabled. All Tx Buffer elements with bits FDF and BRS set are transmitted in CAN FD format with bit rate switching. A mode change during CAN operation is only recommended under the following conditions:

The failure rate in the CAN FD data phase is significantly higher than in the CAN FD arbitration phase. In this case disable the CAN FD bit rate switching option for transmissions. SAM C20/C21 Family Data Sheet CAN - Control Area Network © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 678

During system startup all nodes are transmitting Classic CAN messages until it is verified that they are able to communicate in CAN FD format. If this is true, all nodes switch to CAN FD operation.
Wake-up messages in CAN Partial Networking have to be transmitted in Classic CAN format.
End-of-line programming in case not all nodes are CAN FD capable. Non CAN FD nodes are held in silent mode until programming has completed. Then all nodes switch back to Classic CAN communication. In the CAN FD format, the coding of the DLC differs from the standard CAN format. The DLC codes 0 to 8 have the same coding as in standard CAN, the codes 9 to 15, which in standard CAN all code a data field of 8 bytes, are coded according to the table below. Table 34-2. Coding of DLC in CAN FD DLC 9 10 11 12 13 14 15 Number of Data Bytes 12 16 20 24 32 48 64 In CAN FD frames, the bit timing will be switched inside the frame, after the BRS (Bit Rate Switch) bit, if this bit is recessive. Before the BRS bit, in the CAN FD arbitration phase, the nominal CAN bit timing is used as defined by the Nominal Bit Timing & Prescaler Register NBTP. In the following CAN FD data phase, the fast CAN bit timing is used as defined by the Data Bit Timing & Prescaler Register DBTP. The bit timing is switched back from the fast timing at the CRC delimiter or when an error is detected, whichever occurs first. The maximum configurable bit rate in the CAN FD data phase depends on the CAN clock frequency (GCLK_CAN). Example: with a CAN clock frequency of 20MHz and the shortest configurable bit time of 4 tq, the bit rate in the data phase is 5 Mbit/s. In both data frame formats, CAN FD long and CAN FD fast, the value of the bit ESI (Error Status Indicator) is determined by the transmitter’s error state at the start of the transmission. If the transmitter is error passive, ESI is transmitted recessive, else it is transmitted dominant.

34.6.2.4 Transceiver Delay Compensation

During the data phase of a CAN FD transmission only one node is transmitting, all others are receivers. The length of the bus line has no impact. When transmitting via pin CAN_TX the CAN receives the transmitted data from its local CAN transceiver via pin CAN_RX. The received data is delayed by the CAN transceiver’s loop delay. In case this delay is greater than TSEG1 (time segment before sample point), a bit error is detected. In order to enable a data phase bit time that is even shorter than the transceiver loop delay, the delay compensation is introduced. Without transceiver delay compensation, the bit rate in the data phase of a CAN FD frame is limited by the transceivers loop delay. The CAN’s protocol unit has implemented a delay compensation mechanism to compensate the transmitter delay, thereby enabling transmission with higher bit rates during the CAN FD data phase independent of the delay of a specific CAN transceiver. To check for bit errors during the data phase of transmitting nodes, the delayed transmit data is compared against the received data at the Secondary Sample Point SSP. If a bit error is detected, the transmitter will react on this bit error at the next following regular sample point. During arbitration phase the delay compensation is always disabled. The transmitter delay compensation enables configurations where the data bit time is shorter than the transmitter delay, it is described in detail in the new ISO11898-1. It is enabled by setting bit DBTP.TDC. SAM C20/C21 Family Data Sheet CAN - Control Area Network © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 679

The received bit is compared against the transmitted bit at the SSP. The SSP position is defined as the sum of the measured delay from the CAN’s transmit output CAN_TX through the transceiver to the receive input CAN_RX plus the transmitter delay compensation offset as configured by TDCR.TDCO. The transmitter delay compensation offset is used to adjust the position of the SSP inside the received bit (e.g. half of the bit time in the data phase). The position of the secondary sample point is rounded down to the next integer number of mtq. PSR.TDCV shows the actual transmitter delay compensation value. PSR.TDCV is cleared when CCCR.INIT is set and is updated at each transmission of an FD frame while DBTP.TDC is set. The following boundary conditions have to be considered for the transmitter delay compensation implemented in the CAN:

The sum of the measured delay from CAN_TX to CAN_RX and the configured transceiver delay compensation offset FBTP.TDCO has to be less than 6 bit times in the data phase.
The sum of the measured delay from CAN_TX to CAN_RX and the configured transceiver delay compensation offset FBTP.TDCO has to be less or equal to 127 mtq. In case this sum exceeds 127 mtq, the maximum value of 127 mtq is used for transceiver delay compensation.
The data phase ends at the sample point of the CRC delimiter, that stops checking of receive bits at the SSPs. Transmitter Delay Compensation Measurement If transmitter delay compensation is enabled by programming DBTP.TDC = ‘1’, the measurement is started within each transmitted CAN FD frame at the falling edge of bit FDF to bit res. The measurement is stopped when this edge is seen at the receive input CAN_TX of the transmitter. The resolution of this measurement is one mtq. Figure 34-2. Transceiver delay measurement Delay Start Stop Delay Counter Delay Compensation Offset SSP Position CAN_TX CAN_RX GCLK_CAN TDCR.TDCO data phase data phasearbitration phase arbitration phase Transmitter Delay FDF res BRS ESI DLC To avoid that a dominant glitch inside the received FDF bit ends the delay compensation measurement before the falling edge of the received res bit, resulting in a too early SSP position, the use of a transmitter delay compensation filter window can be enabled by programming TDCR.TDCF. This defines a minimum value for the SSP position. Dominant edges of CAN_RX, that would result in an earlier SSP position are ignored for transmitter delay measurement. The measurement is stopped when the SSP position is at least TDCR.TDCF AND CAN _RX is low.

34.6.2.5 Restricted Operation Mode

In Restricted Operation Mode the node is able to receive data and remote frames and to give acknowledge to valid frames, but it does not send data frames, remote frames, active error frames, or overload frames. In case of an error condition or overload condition, it does not send dominant bits, SAM C20/C21 Family Data Sheet CAN - Control Area Network © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 680

instead it waits for the occurrence of bus idle condition to resynchronize itself to the CAN communication. The error counters (ECR.REC, ECR.TEC) are frozen while Error Logging (ECR.CEL) is still incremented. The CPU can set the CAN into Restricted Operation mode by setting bit CCCR.ASM. The bit can only be set by the CPU when both CCCR.CCE and CCCR.INIT are set to ‘1’. The bit can be reset by the CPU at any time. Restricted Operation Mode is automatically entered when the Tx Handler was not able to read data from the Message RAM in time. To leave Restricted Operation Mode, the CPU has to reset CCCR.ASM. The Restricted Operation Mode can be used in applications that adapt themselves to different CAN bit rates. In this case the application tests different bit rates and leaves the Restricted Operation Mode after it has received a valid frame.

34.6.2.6 Bus Monitoring Mode

The CAN is set in Bus Monitoring Mode by programming CCCR.MON to ‘1’. In Bus Monitoring Mode (see ISO 11898-1, 10.12 Bus monitoring), the CAN is able to receive valid data frames and valid remote frames, but cannot start a transmission. In this mode, it sends only recessive bits on the CAN bus. If the CAN is required to send a dominant bit (ACK bit, overload flag, active error flag), the bit is rerouted internally so that the CAN monitors this dominant bit, although the CAN bus may remain in recessive state. In Bus Monitoring Mode register TXBRP is held in reset state. The Bus Monitoring Mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits. The figure below shows the connection of signals CAN_TX and CAN_RX to the CAN in Bus Monitoring Mode. Figure 34-3. Pin Control in Bus Monitoring Mode CAN_TX CAN_RX TX HANDLER RX HANDLER CAN Bus Monitoring Mode

34.6.2.7 Disabled Automatic Retransmission

According to the CAN Specification (see ISO 11898-1, 6.3.3 Recovery Management), the CAN provides means for automatic retransmission of frames that have lost arbitration or that have been disturbed by errors during transmission. By default automatic retransmission is enabled. To support time-triggered communication as described in ISO 11898-1, chapter 9.2, the automatic retransmission may be disabled via CCCR.DAR. Frame Transmission in DAR Mode In DAR mode all transmissions are automatically cancelled after they started on the CAN bus. A Tx Buffer’s Tx Request Pending bit TXBRP.TRPx is reset after successful transmission, when a transmission has not yet been started at the point of cancellation, has been aborted due to lost arbitration, or when an error occurred during frame transmission. SAM C20/C21 Family Data Sheet CAN - Control Area Network © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 681

Successful transmission: – Corresponding Tx Buffer Transmission Occurred bit TXBTO.TOx set – Corresponding Tx Buffer Cancellation Finished bit TXBCF.CFx not set
Successful transmission in spite of cancellation: – Corresponding Tx Buffer Transmission Occurred bit TXBTO.TOx set – Corresponding Tx Buffer Cancellation Finished bit TXBCF.CFx set
Arbitration lost or frame transmission disturbed: – Corresponding Tx Buffer Transmission Occurred bit TXBTO.TOx not set – Corresponding Tx Buffer Cancellation Finished bit TXBCF.CFx set In case of a successful frame transmission, and if storage of Tx events is enabled, a Tx Event FIFO element is written with Event Type ET = “10” (transmission in spite of cancellation).

34.6.2.8 Test Modes

To enable write access to register TEST, bit CCCR.TEST has to be set to ‘1’. This allows the configuration of the test modes and test functions. Four output functions are available for the CAN transmit pin CAN_TX by programming TEST.TX. Additionally to its default function – the serial data output – it can drive the CAN Sample Point signal to monitor the CAN’s bit timing and it can drive constant dominant or recessive values. The actual value at pin CAN_RX can be read from TEST.RX. Both functions can be used to check the CAN bus’ physical layer. Due to the synchronization mechanism between GCLK_CAN and GCLK_CAN_APB domains, there may be a delay of several GCLK_CAN_APB periods between writing to TEST.TX until the new configuration is visible at output pin CAN_TX. This applies also when reading input pin CAN_RX via TEST.RX. Note: Test modes should be used for production tests or self test only. The software control for pin CAN_TX interferes with all CAN protocol functions. It is not recommended to use test modes for application. External Loop Back Mode The CAN can be set in External Loop Back Mode by programming TEST.LBCK to ‘1’. In Loop Back Mode, the CAN treats its own transmitted messages as received messages and stores them (if they pass acceptance filtering) into an Rx Buffer or an Rx FIFO. The figure below shows the connection of signals CAN_TX and CAN_RX to the CAN in External Loop Back Mode. This mode is provided for hardware self-test. To be independent from external stimulation, the CAN ignores acknowledge errors (recessive bit sampled in the acknowledge slot of a data/remote frame) in Loop Back Mode. In this mode the CAN performs an internal feedback from its Tx output to its Rx input. The actual value of the CAN_RX input pin is disregarded by the CAN. The transmitted messages can be monitored at the CAN_TX pin. Internal Loop Back Mode Internal Loop Back Mode is entered by programming bits TEST.LBCK and CCCR.MON to ‘1’. This mode can be used for a “Hot Selftest”, meaning the CAN can be tested without affecting a running CAN system connected to the pins CAN_TX and CAN_RX. In this mode pin CAN_RX is disconnected from the CAN and pin CAN_TX is held recessive. The figure below shows the connection of CAN_TX and CAN_RX to the CAN in case of Internal Loop Back Mode. SAM C20/C21 Family Data Sheet CAN - Control Area Network © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 682

Figure 34-4. Pin Control in Loop Back Modes CAN_TX CAN_RX CAN_TX CAN_RX TX HANDLER RX HANDLER TX HANDLER RX HANDLER CAN CAN External Loop Back Mode Internal Loop Back Mode

34.6.3 Timestamp Generation

For timestamp generation the CAN supplies a 16-bit wrap-around counter. A prescaler TSCC.TCP can be configured to clock the counter in multiples of CAN bit times (1…16). The counter is readable via TSCV.TSC. A write access to register TSCV resets the counter to zero. When the timestamp counter wraps around interrupt flag IR.TSW is set. On start of frame reception / transmission the counter value is captured and stored into the timestamp section of an Rx Buffer / Rx FIFO (RXTS[15:0]) or Tx Event FIFO (TXTS[15:0]) element.

34.6.4 Timeout Counter

To signal timeout conditions for Rx FIFO 0, Rx FIFO 1, and the Tx Event FIFO the CAN supplies a 16-bit Timeout Counter. It operates as down-counter and uses the same prescaler controlled by TSCC.TCP as the Timestamp Counter. The Timeout Counter is configured via register TOCC. The actual counter value can be read from TOCV.TOC. The Timeout Counter can only be started while CCCR.INIT = ‘0’. It is stopped when CCCR.INIT = ‘1’, e.g. when the CAN enters Bus_Off state. The operation mode is selected by TOCC.TOS. When operating in Continuous Mode, the counter starts when CCCR.INIT is reset. A write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. Writing to TOCV has no effect. When the counter reaches zero, interrupt flag IR.TOO is set. In Continuous Mode, the counter is immediately restarted at TOCC.TOP. Note: The clock signal for the Timeout Counter is derived from the CAN Core’s sample point signal. Therefore the point in time where the Timeout Counter is decremented may vary due to the synchronization / re-synchronization mechanism of the CAN Core. If the baud rate switch feature in CAN FD is used, the timeout counter is clocked differently in arbitration and data field.

34.6.5 Rx Handling

The Rx Handler controls the acceptance filtering, the transfer of received messages to the Rx Buffers or to one of the two Rx FIFOs, as well as the Rx FIFO’s Put and Get Indices. SAM C20/C21 Family Data Sheet CAN - Control Area Network © 2019 Microchip Technology Inc. Datasheet DS60001479C-page 683

PDF text was truncated. Refer to the original document for complete details.

Product Information

SAMC21 specifications and overview.

Summary

32-bit ARM Cortex-M0+ 5V Support, CAN-FD, PTC and Advanced Analog 2019

Description

32-bit ARM Cortex-M0+ 5V Support, CAN-FD, PTC and Advanced Analog 2019

Source title SAMC21 Datasheet(PDF) - Microchip Technology

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