SAM3X8ERT

SAM3X8ERT MICROCHIP | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1.0 Introduction
• 2.0 Features
• 3.0 Configuration Summary
• 4.0 Block Diagram
• 5.0 Signal Description
• 5.1 Design Considerations
• 6.0 Space Quality Grade
• 7.0 Package and Pinout
• 7.1 SAM3X8ERT Package and Pinout
• 8.0 Power Considerations
• 8.1 Power Supplies
• 8.2 Power-up Considerations
• 8.3 Voltage Regulator
• 8.4 Typical Powering Schematics
• 8.5 Active Mode
• 8.6 Low Power Modes
• 8.7 Wake-up Sources
• 8.8 Fast Startup
• 9.0 Input/Output Lines
• 9.1 General Purpose I/O Lines (GPIO)
• 9.2 System I/O Lines
• 9.3 Test Pin
• 9.4 NRST Pin
• 9.5 NRSTB Pin
• 9.6 ERASE Pin
• 10.0 Memories
• 10.1 Product Mapping
• 10.2 Embedded Memories
• 10.3 External Memories
• 11.0 System Controller
• 11.1 System Controller and Peripherals Mapping
• 11.2 Power-on-Reset, Brownout and Supply Monitor
• 12.0 Peripherals
• 12.1 Peripheral Identifiers
• 12.2 APB/AHB Bridge
• 12.3 Peripheral Signal Multiplexing on I/O Lines
• 13.0 ARM Cortex M3 Processor
• 13.1 About this section
• 13.2 Embedded Characteristics
• 13.3 About the Cortex-M3 Processor and Core Peripherals
• 13.4 Programmers Model
• 13.5 Memory Model
• 13.6 Exception Model
• 13.7 Fault Handling
• 13.8 Power Management
• 13.9 Instruction Set Summary
• 13.10 Intrinsic Functions
• 13.11 Instruction Descriptions
• 13.12 Memory Access Instructions
• 13.13 General Data Processing Instructions
• 13.14 Multiply and Divide Instructions
• 13.15 Saturating Instructions
• 13.16 Bitfield Instructions
• 13.17 Branch and Control Instructions
• 13.18 Miscellaneous Instructions
• 13.19 About the Cortex-M3 Peripherals
• 13.20 Nested Vectored Interrupt Controller
• 13.21 System Control Block
• 13.22 System Timer, SysTick

 2020 Microchip Technology Inc. DS60001614B-page 1 INTRODUCTION SAM3X8ERT is a radiation-tolerant Arm® Cortex®-M3 RISC processor. It operates at a maximum speed of 84 MHz and features 512 Kbytes of Flash and 100 Kbytes of SRAM. The peripheral set includes a High Speed USB Host and Device port with embedded transceiver, an Ethernet MAC, 2 CANs, a High Speed MCI for SDIO/SD/MMC, an External Bus Interface with NAND Flash Controller (NFC), 5 UARTs, 2 TWIs, 4 SPIs, as well as a PWM timer, three 3-channel gen- eral-purpose 32-bit timers, a low-power RTC, a low-power RTT, 256-bit General Purpose Backup Registers, a 12-bit ADC and a 12-bit DAC. SAM3X8ERT has three software-selectable low-power modes: Sleep, Wait, and Backup. In Sleep mode, the processor is stopped while all other functions can be kept running. In Wait mode, all clocks and functions are stopped but some peripherals can be configured to wake up the system based on predefined conditions. In Backup mode, only the RTC, RTT, and wake-up logic are kept running. The SAM3X8ERT architecture is specifically designed to sustain high-speed data transfers. It includes a multi-layer bus matrix as well as multiple SRAM banks, PDC and DMA channels that enable it to run tasks in parallel and maximize data throughput.

FEATURES

• ARM Cortex-M3 revision 2.0 running at up to 84 MHz
• Memory Protection Unit (MPU)
• Thumb®-2 instruction set
• 24-bit SysTick Counter
• Nested Vector Interrupt Controller Memories
• 512 Kbytes embedded Flash, 128-bit wide access, memory accelerator, dual bank
• 100 Kbytes embedded SRAM with dual banks
• 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines
• Static Memory Controller (SMC): SRAM, NOR, NAND support. NFC with 4 Kbyte RAM buffer and ECC
• Flash Data Retention: 20 years with TA = 105 °C System
• Embedded voltage regulator for single supply operation
• Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe reset
• Quartz or ceramic resonator oscillators: 3 to 20 MHz main and optional low power 32.768 kHz for RTC or device clock
• High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default frequency for fast device startup
• Slow Clock Internal RC oscillator as permanent clock for device clock in low-power mode
• One PLL for device clock and one dedicated PLL for USB 2.0 High Speed Mini Host/Device
• Temperature Sensor
• Up to 17 peripheral DMA (PDC) channels and 6-channel central DMA plus dedicated DMA for High-Speed USB Mini Host/Device and Ethernet MAC Radiation-Tolerant 32-bit Arm® Cortex®-M3 Microcontroller SAM3X8ERT

DS60001614B-page 2  2020 Microchip Technology Inc. Low-Power Modes

• Sleep, Wait and Backup modes, down to 2.5 ìA in Backup mode with RTC, RTT, and GPBR Peripherals
• USB 2.0 Device/Mini Host: 480 Mbps, 4 Kbyte FIFO, up to 10 bidirectional Endpoints, dedicated DMA
• Up to 4 USARTs (ISO7816, IrDA®, Flow Control, SPI, Manchester and LIN support) and one UART
• 2 TWI (I2C compatible), up to 6 SPIs, 1 SSC (I2S), 1 HSMCI (SDIO/SD/MMC) with up to 2 slots
• 9-channel 32-bit Timer Counter (TC) for capture, compare and PWM mode, Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor
• Up to 8-channel 16-bit PWM (PWMC) with Complementary Output, Fault Input, 12-bit Dead Time Generator Counter for Motor Control
• 32-bit low-power Real-time Timer (RTT) and low-power Real-time Clock (RTC) with calendar and alarm features
• 256-bit General Purpose Backup Registers (GPBR)
• 16-channel 12-bit 1 msps ADC with differential input mode and programmable gain stage
• 2-channel 12-bit 1 msps DAC
• Ethernet MAC 10/100 (EMAC) with dedicated DMA
• 2 CAN Controllers with 8 Mailboxes
• True Random Number Generator (TRNG)
• Register Write Protection I/O
• Up to 103 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on- die Series Resistor Termination
• Up to four 32-bit Parallel Input/Outputs (PIO) Operating Range
• Temperature: -40 °C to +105 °C
• Single Supply Voltage: 3.0V to 3.6V
• Dual Supply Voltage - VDDIO: 3.0V to 3.6V - VDDCORE: 1.8V to 1.95V Radiation Performances
• No Single Event Latch-up Below an LET Threshold of 62 MeV.cm2/mg @105 °C
• TID immunity successfully tested up to 30 Krads (si) according to ESCC-22900 test method Packages
• 144-lead LQFP – 20 x 20 mm, pitch 0.5 mm
• 144-lead CQFP – 22 x 22 mm, pitch 0.5 mm ESD
• HBM: 4000V
• CDM: - LQFP144: 1000V - CQFP144: 500V Mass
• LQFP144: 1.37g
• CQFP144: - Cropped and formed: 6.19g - With tie-bar: 8.87g

 2020 Microchip Technology Inc. DS60001614B-page 3 SAM3X8ERT TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur - rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.

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1.0 CONFIGURATION SUMMARY

The following table summarizes the configuration. TABLE 1-1: CONFIGURATION SUMMARY Feature SAM3X8ERT Flash 2 x 256 Kbytes SRAM 64 + 32 Kbytes NAND Flash Controller (NFC) Yes NFC SRAM 4 Kbytes (1) 1. RAM buffer of the NFC which can be used by the core if not used by the NFC. Number of PIOs 103 SHDN Pin Yes EMAC MII/RMII External Bus Interface 16-bit data, 8 chip selects, 23-bit address Central DMA 6 12-bit ADC 16 ch. (2) 2. One channel is reserved for internal temperature sensor. 12-bit DAC 2 ch. 32-bit Timer 9 ch. (3) 3. Six TC channels are accessible through PIO. PDC Channels 17 USART/UART 3/2 (4) 4. USART3 in UART mode (RXD3 and TXD3 available). SPI 1 SPI controller 4 chip selects + 3 USART with SPI mode HSMCI 1 slot, 8 bits

DS60001614B-page 12  2020 Microchip Technology Inc.

2.0 BLOCK DIAGRAM

FIGURE 2-1: SAM3X8ERT BLOCK DIAGRAM

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3.0 SIGNAL DESCRIPTION

Table 3-1 gives details on the signal names classified by peripheral. TABLE 3-1: SIGNAL DESCRIPTION LIST Signal Name Function Type Active Level Voltage Reference Comments Power Supplies VDDIO Peripherals I/O Lines Power Supply Power — — 1.8V to 3.6V VDDUTMI USB UTMI+ Interface Power Supply Power — — 3.0V to 3.6V VDDOUT Voltage Regulator Output Power — — — VDDIN Voltage Regulator, ADC and DAC Power Supply Power — — — GNDUTMI USB UTMI+ Interface Ground Ground — — — VDDBU Backup I/O Lines Power Sup- ply Power — — 1.8V to 3.6V GNDBU Backup Ground Ground — — — VDDPLL PLL A, UPLL and Oscillator Power Supply Power — — 1.8V to 1.95V GNDPLL PLL A, UPLL and Oscillator Ground Ground — — — VDDANA ADC and DAC Analog Power Supply Power — — 2.0V to 3.6V GNDANA ADC and DAC Analog Ground Ground — — — VDDCORE Core Chip Power Supply Power — — 1.8V to 1.95V GND Ground Ground — — — Clocks, Oscillators, and PLLs XIN Main Oscillator Input Input — VDDPLL — XOUT Main Oscillator Output Output — — XIN32 Slow Clock Oscillator Input Input — VDDBU — XOUT32 Slow Clock Oscillator Output Output — — VBG Bias Voltage Reference Analog — — — PCK0–PCK2 Programmable Clock Output Output — — — Shutdown, Wakeup Logic SHDN Shut-Down Control Output — VDDBU 0: Device is in backup mode 1: Device is running (not in backup mode) FWUP Force Wake-up Input Input — VDDBU Needs external pull-up

DS60001614B-page 14  2020 Microchip Technology Inc. ICE and JTAG TCK/SWCLK Test Clock/Serial Wire Clock Input — VDDIO Reset State: - SWJ-DP Mode - Internal pull-up disabled(1) TDI Test Data In Input — TDO/TRACES WO Test Data Out / Trace Asyn- chronous Data Out Output — TMS/SWDIO Test Mode Select /Serial Wire Input/Output Input / I/O JTAGSEL JTAG Selection Input High VDDBU Permanent Internal pull-down Flash Memory ERASE Flash and NVM Configura- tion Bits Erase Command Input High VDDIO Pull-down resistor Reset/Test NRST Microcontroller Reset I/O Low VDDIO Pull-up resistor NRSTB Asynchronous Microcontrol- ler Reset Input Low VDDBU Pull-up resistor TST Test Mode Select Input — VDDBU Pull-down resistor Universal Asynchronous Receiver Transceiver - UART URXD UART Receive Data Input — — — UTXD UART Transmit Data Output — — — PIO Controller - PIOA - PIOB - PIOC - PIOD PA0–PA29 Parallel IO Controller A I/O — VDDIO Schmitt Trigger(3) Reset State: - PIO Input - Internal pull-up enabled PB0–PB31 Parallel IO Controller B I/O — — Schmitt Trigger(4) Reset State: - PIO Input - Internal pull-up enabled PC0–PC30 Parallel IO Controller C I/O — — Schmitt Trigger(5) Reset State: - PIO Input - Internal pull-up enabled PD0–PD10 Parallel IO Controller D I/O — — Schmitt Trigger(3.1) Reset State: - PIO Input - Internal pull-up enabled TABLE 3-1: SIGNAL DESCRIPTION LIST (CONTINUED) Signal Name Function Type Active Level Voltage Reference Comments

 2020 Microchip Technology Inc. DS60001614B-page 15 SAM3X8ERT External Memory Bus D0–D15 Data Bus I/O — — Pulled-up input at reset A0–A23 Address Bus Output — — 0 at reset Static Memory Controller - SMC NCS0–NCS7 Chip Select Lines Output Low — — NWR0–NWR1 Write Signal Output Low — — NRD Read Signal Output Low — — NWE Write Enable Output Low — — NBS0–NBS1 Byte Mask Signal Output Low — — NWAIT External Wait Signal Input Low — — NAND Flash Controller - NFC NANDOE NAND Flash Output Enable Output Low — — NANDWE NAND Flash Write Enable Output Low — — NANDRDY NAND Ready Input — — — NANDCLE NAND Flash Command Line Enable Output Low — — NANDALE NAND Flash Address Line Enable Output Low — — High Speed Multimedia Card Interface - HSMCI MCCK Multimedia Card Clock I/O — — — MCCDA Multimedia Card Slot A Com- mand I/O — — — MCDA0– MCDA7 Multimedia Card Slot A Data I/O — — — MCCDB Multimedia Card Slot B Com- mand I/O — — — MCDB0– MCDB3 Multimedia Card Slot A Data I/O — — — Universal Synchronous Asynchronous Receiver Transmitter - USARTx SCKx USARTx Serial Clock I/O — — — TXDx USARTx Transmit Data I/O — — — RXDx USARTx Receive Data Input — — — RTSx USARTx Request To Send Output — — — CTSx USARTx Clear To Send Input — — — TABLE 3-1: SIGNAL DESCRIPTION LIST (CONTINUED) Signal Name Function Type Active Level Voltage Reference Comments

DS60001614B-page 16  2020 Microchip Technology Inc. Ethernet MAC 10/100 - EMAC EREFCK Reference Clock Input — RMII only — ETXCK Transmit Clock Input — MII only — ERXCK Receive Clock Input — MII only — ETXEN Transmit Enable Output — — — ETX0–ETX3 Transmit Data Output — ETX0– ETX1 only in RMII ETXER Transmit Coding Error Output — MII only — ERXDV Receive Data Valid Input — MII only — ECRSDV Carrier Sense and Data Valid Input — RMII only — ERX0–ERX3 Receive Data Input — ERX0– ERX1 only in RMII ERXER Receive Error Input — — — ECRS Carrier Sense Input — MII only — ECOL Collision Detected Input — MII only — EMDC Management Data Clock Output — — — EMDIO Management Data Input/Out- put I/O — — — CAN Controller - CANx CANRXx CAN Input Input — — — CANTXx CAN Output Output — — — Synchronous Serial Controller - SSC TD SSC Transmit Data Output — — — RD SSC Receive Data Input — — — TK SSC Transmit Clock I/O — — — RK SSC Receive Clock I/O — — — TF SSC Transmit Frame Sync I/O — — — RF SSC Receive Frame Sync I/O — — — Timer/Counter - TC TCLKx TC Channel x External Clock Input Input — — — TIOAx TC Channel x I/O Line A I/O — — — TIOBx TC Channel x I/O Line B I/O — — — Pulse Width Modulation Controller - PWMC PWMHx PWM Waveform Output High for channel x Output — — — PWMLx PWM Waveform Output Low for channel x Output — — Only output in complemen- tary mode when dead time insertion is enabled PWMFIx PWM Fault Input for channel x Input — — — TABLE 3-1: SIGNAL DESCRIPTION LIST (CONTINUED) Signal Name Function Type Active Level Voltage Reference Comments

 2020 Microchip Technology Inc. DS60001614B-page 17 SAM3X8ERT Note 1: TDO pin is set in input mode when the Cortex-M3 Core is not in debug mode. Thus the internal pull-up cor- responding to this PIO line must be enabled to avoid current consumption due to floating input. 2: PIOA: Schmitt Trigger on all, except PA0, PA9, PA26, PA29, PA30, PA31 3: PIOB: Schmitt Trigger on all, except PB14 and PB22 4: PIOC: Schmitt Trigger on all, except PC2 to PC9, PC15 to PC24 Serial Peripheral Interface - SPIx SPIx_MISO Master In Slave Out I/O — — — SPIx_MOSI Master Out Slave In I/O — — — SPIx_SPCK SPI Serial Clock I/O — — — SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low — — SPIx_NPCS1– SPIx_NPCS3 SPI Peripheral Chip Select Output Low — — Two-Wire Interface - TWIx TWDx TWIx Two-wire Serial Data I/O — — — TWCKx TWIx Two-wire Serial Clock I/O — — — Analog-to-Digital Converter - ADC AD0–AD14 Analog Inputs Analog — — — ADTRG ADC Trigger Input — — — ADVREF ADC and DAC Reference Analog — — — Digital-to-Analog Converter Controller - DACC DAC0 DAC channel 0 analog output Analog — — — DAC1 DAC channel 1 analog output Analog — — — DATRG DAC Trigger — — — — Fast Flash Programming Interface - FFPI PGMEN0– PGMEN2 Programming Enabling Input — VDDIO — PGMM0– PGMM3 Programming Mode Input — VDDIO — PGMD0– PGMD15 Programming Data I/O — VDDIO — PGMRDY Programming Ready Output High VDDIO — PGMNVALID Data Direction Output Low VDDIO — PGMNOE Programming Read Input Low VDDIO — PGMCK Programming Clock Input — VDDIO — PGMNCMD Programming Command Input Low VDDIO — USB High Speed Device VBUS USB Bus Power Measure- ment Mini Host/Device Analog — — — DFSDM USB Full Speed Data - Analog — VDDUTMI — DFSDP USB Full Speed Data + Analog — VDDUTMI — DHSDM USB High Speed Data - Analog — VDDUTMI — DHSDP USB High Speed Data + Analog — VDDUTMI — UOTGVBOF USB VBus On/Off: Bus Power Control Port — VDDIO — UOTGID USB Identification: Mini Con- nector Identification Port — VDDIO — TABLE 3-1: SIGNAL DESCRIPTION LIST (CONTINUED) Signal Name Function Type Active Level Voltage Reference Comments

DS60001614B-page 18  2020 Microchip Technology Inc. 5: PIOD: Schmitt Trigger on all, except PD10 to PD30

3.1 Design Considerations

To facilitate schematic capture when using a SAM3X8ERT design, refer to the application note AT03462: ATSAM3X and ATSAM3A Series - Checklist (literature No. 42187) available on http://www.microchip.com/.

 2020 Microchip Technology Inc. DS60001614B-page 19 SAM3X8ERT

4.0 SPACE QUALITY GRADE

The hermetic SAM3X8ERT is manufactured in compliance with MIL class Q or class V requirements: screening testing, qualification testing, and TCI/QCI-specifications. The plastic SAM3X8ERT is qualified in compliance with the AEC-Q100 automotive requirements, with specific additional tests necessary for space applications. Screening and qualification flows are described in Aerospace & Defense AEQA0242 specification, available on Microchip web site.

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5.0 PACKAGE AND PINOUT

5.1 SAM3X8ERT Package and Pinout

The SAM3X8ERT is available in 144-lead LQFP and 144-lead CQFP packages. FIGURE 5-1: ORIENTATION OF THE 144-LEAD LQFP/CQFP PACKAGES 5.1.1 144-LEAD LQFP/CQFP PINOUT TABLE 5-1: SAM3X8ERT PINOUT

1 PB26 37 DHSDP 73 VDDANA 109 PA26

2 PA9 38 DHSDM 74 GNDANA 110 PA27

3 PA10 39 VBUS 75 ADVREF 111 PA28

4 PA11 40 VBG 76 PB15 112 PA29

5 PA12 41 VDDUTMI 77 PB16 113 PB0

6 PA13 42 DFSDP 78 PA16 114 PB1

7 PA14 43 DFSDM 79 PA24 115 PB2

8 PA15 44 GNDUTMI 80 PA23 116 PC4

9 PA17 45 VDDCORE 81 PA22 117 PC10

10 VDDCORE 46 JTAGSEL 82 PA6 118 PB3

11 VDDIO 47 NRSTB 83 PA4 119 PB4

12 GND 48 XIN32 84 PA3 120 PB5

13 PD0 49 XOUT32 85 PA2 121 PB6

14 PD1 50 SHDN 86 PB12 122 PB7

15 PD2 51 TST 87 PB13 123 PB8

16 PD3 52 VDDBU 88 PB17 124 VDDCORE

17 PD4 53 FWUP 89 PB18 125 VDDIO

18 PD5 54 GNDBU 90 PB19 126 GND

19 PD6 55 PC1 91 PB20 127 PB9

20 PD7 56 VDDOUT 92 PB21 128 PB10

21 PD8 57 VDDIN 93 PC11 129 PB11

22 PD9 58 GND 94 PC12 130 PC0

23 PA0 59 PC2 95 PC13 131 PC20

24 PA1 60 PC3 96 PC14 132 PC21

25 PA5 61 VDDCORE 97 PC15 133 PC22

26 PA7 62 VDDIO 98 PC16 134 PC23

27 PA8 63 PC5 99 PC17 135 PC24

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28 PB28 64 PC6 100 PC18 136 PC25

29 PB29 65 PC7 101 PC19 137 PC26

30 PB30 66 PC8 102 PC29 138 PC27

31 PB31 67 PC9 103 PC30 139 PC28

32 PD10 68 PB27 104 VDDCORE 140 PB14

33 GNDPLL 69 NRST 105 VDDIO 141 PB22

34 VDDPLL 70 PA18 106 GND 142 PB23

35 XOUT 71 PA19 107 PA21 143 PB24

36 XIN 72 PA20 108 PA25 144 PB25

TABLE 5-1: SAM3X8ERT PINOUT (CONTINUED)

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6.0 POWER CONSIDERATIONS

6.1 Power Supplies

The SAM3X8ERT product has several types of power supply pins:

• VDDCORE pins: Power the core, the embedded memories and the peripherals logic.
• VDDIO pins: Power the peripherals I/O lines.
• VDDIN pin: Powers the voltage regulator, ADC and DAC peripherals.
• VDDOUT pin: Output of the voltage regulator
• VDDBU pin: Powers the Slow Clock oscillator, Backup I/O lines, and a part of the System Controller. VDDBU must be supplied before or at the same time as VDDIO and VDDCORE.
• VDDPLL pin: Powers the PLL A, UPLL and 3–20 MHz Oscillator.
• VDDUTMI pin: Powers the USB UTMI+ interface.
• VDDANA pin: Powers the analog ADC and DAC cells. Ground pins GND are common to VDDCORE and VDDIO pins power supplies. Separated ground pins are provided for VDDBU, VDDPLL, VDDUTMI and VDDANA. These ground pins are respec - tively GNDBU, GNDPLL, GNDUTMI and GNDANA.

6.2 Power-up Considerations

6.2.1 VDDIO VERSUS VDDCORE

VDDIO must always be higher than or equal to VDDCORE. VDDIO must reach its minimum operating voltage (1.80V) before VDDCORE has reached VDDCORE (min). The min- imum slope for VDDCORE is defined by (VDDCORE(min) - VT+)  tRST. If VDDCORE rises at the same time as VDDIO, the VDDIO rising slope must be higher than or equal to 5V/ms. If VDDCORE is powered by the internal regulator, all power-up considerations are met.

 2020 Microchip Technology Inc. DS60001614B-page 23 SAM3X8ERT FIGURE 6-1: VDDCORE AND VDDIO CONSTRAINTS AT STARTUP

6.2.2 VDDIO VERSUS VDDIN

At power-up, VDDIO needs to reach 0.6V before VDDIN reaches 1.0V. VDDIO voltage needs to be equal to or below (VDDIN voltage + 0.5V).

6.3 Voltage Regulator

The SAM3X8ERT embeds a voltage regulator that is managed by the Supply Controller. This internal regulator is intended to supply the internal core of the SAM3X8ERT but can be used to supply other parts in the application. It features two different operating modes:

• In Normal mode, the voltage regulator consumes less than 700µA static current and draws 150mA of output cur- rent. Internal adaptive biasing adjusts the regulator quiescent current depending on the required load current. In Wait Mode or when the output current is low, quiescent current is only 7µA.
• In Shutdown mode, the voltage regulator consumes less than 1µA while its output is driven internally to GND. The default output voltage is 1.80V and the startup time to reach Normal mode is inferior to 400µs. For adequate input and output power supply decoupling/bypassing, refer to TABLE 45-4:. Supply (V) Time (t) tRST VDDIO VT+ VDDCORE VDDIO(min) VDDCORE(min) Core supply POR output SLCK

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6.4 Typical Powering Schematics

The SAM3X8ERT supports a 1.8–3.6 V single supply mode. The internal regulator input connected to the source and its output feeds VDDCORE. Figure 6-2 shows the power schematics. FIGURE 6-2: SINGLE SUPPLY Note: Restrictions For USB, VDDUTMI needs to be greater than 3.0V. For ADC, VDDANA needs to be greater than 2.0V. For DAC, VDDANA needs to be greater than 2.4V. VDDIN Voltage Regulator VDDOUT Main Supply (3–3.6 V) VDDCORE VDDBU VDDUTMI VDDIO VDDANA VDDPLL

 2020 Microchip Technology Inc. DS60001614B-page 25 SAM3X8ERT FIGURE 6-3: CORE EXTERNALLY SUPPLIED Note: Restrictions For USB, VDDUTMI needs to be greater than 3.0V. For ADC, VDDANA needs to be greater than 2.0V. For DAC, VDDANA needs to be greater than 2.4V. VDDCORE Supply (1.8V-1.95V) Main Supply (3-3.6V)

DS60001614B-page 26  2020 Microchip Technology Inc. FIGURE 6-4: BACKUP BATTERIES USED Note 1: Restrictions For USB, VDDUTMI needs to be greater than 3.0V. For ADC, VDDANA needs to be greater than 2.0V. For DAC, VDDANA needs to be greater than 2.4V. 2: VDDUTMI and VDDANA cannot be left unpowered.

6.5 Active Mode

Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscil- lator or the PLLA. The power management controller can be used to adapt the frequency and to disable the peripheral clocks.

6.6 Low Power Modes

The SAM3X8ERT devices provide the following low-power modes: Backup, Wait, and Sleep.

6.6.1 BACKUP MODE

The purpose of backup mode is to achieve the lowest power consumption possible in a system which is performing peri- odic wake-ups to perform tasks but not requiring fast startup time (< 0.5 ms). The Supply Controller, zero-power power-on-reset, RTT, RTC, backup registers and 32 kHz oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The regulator and the core supply are off. Backup mode is based on the Cortex-M3 deep-sleep mode with the voltage regulator disabled. VDDIN Voltage Regulator VDDOUT Main Supply (3–3.6 V) VDDCORE Backup Batteries VDDBU VDDIO VDDANA VDDUTMI VDDPLL FWUP SHDN

 2020 Microchip Technology Inc. DS60001614B-page 27 SAM3X8ERT The SAM3X8ERT can be awakened from this mode through the Force Wake-up pin (FWUP), and Wake-up input pins WKUP0–15, Supply Monitor, RTT or RTC wake-up event. Current consumption is 2.5 µA typical on VDDBU. Backup mode can be entered by using the WFE instruction. The procedure to enter Backup mode using the WFE instruction is the following: 1. Write a 1 to the SLEEPDEEP bit in the Cortex-M3 processor System Control Register (SCR) (refer to Section 11.21.7 “System Control Register”). 2. Execute the WFE instruction of the processor. Exit from Backup mode happens if one of the following enable wake-up events occurs:

• Low level, configurable debouncing on FWUP pin
• Level transition, configurable debouncing on pins WKUPEN0–15
• SM alarm
• RTC alarm
• RTT alarm

6.6.2 WAIT MODE

The purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a pow- ered state for a startup time of less than 10 µs. In this mode, the clocks of the core, peripherals and memories are stopped. However, the core, peripherals and mem- ories power supplies are still powered. From this mode, a fast start up is available. This mode is entered via Wait for Event (WFE) instructions with LPM = 1 (Low Power Mode bit in PMC_FSMR). The Cortex-M3 is able to handle external events or internal events in order to wake-up the core (WFE). This is done by con- figuring the external lines WKUP0–15 as fast startup wake-up pins (refer to Section 6.8 “Fast Startup” ). RTC or RTT Alarm and USB wake-up events can be used to wake up the CPU (exit from WFE). Current consumption in Wait mode is typically 23 µA for total current consumption if the internal voltage regulator is used or 15 µA if an external regulator is used. The procedure to enter Wait mode is the following: 1. Select the 4/8/12 MHz Fast RC Oscillator as Main Clock. 2. Set the LPM bit in the PMC Fast Startup Mode Register (PMC_FSMR). 3. Execute the WFE instruction of the processor. Note: Internal Main clock resynchronization cycles are necessary between the writing of MOSCRCEN bit and the effective entry in Wait mode. Depending on the user application, Waiting for MOSCRCEN bit to be cleared is recommended to ensure that the core will not execute undesired instructions.

6.6.3 SLEEP MODE

The purpose of sleep mode is to optimize power consumption of the device versus response time. In this mode, only the core clock is stopped. The peripheral clocks can be enabled. This mode is entered via Wait for Interrupt (WFI) or WFE instructions with LPM = 0 in PMC_FSMR. The processor can be awakened from an interrupt if WFI instruction of the Cortex-M3 is used, or from an event if the WFE instruction is used to enter this mode.

6.6.4 LOW POWER MODE SUMMARY TABLE

The modes detailed above are the main low power modes. Each part can be set to on or off separately and wake-up sources can be individually configured. Table 6-1 shows a summary of the configurations of the low power modes.

DS60001614B-page 28  2020 Microchip Technology Inc. Note 1: SUPC, 32 kHz Oscillator, RTC, RTT, GPBR, POR. 2: The external loads on PIOs are not taken into account in the calculation. 3: BOD current consumption is not included. 4: When considering the wake-up time, the time required to start the PLL is not taken into account. Once started, the device works with the 4/8/12 MHz Fast RC oscillator. The user has to add the PLL startup time if it is needed in the system. The wake-up time is defined as the time taken for wake-up until the first instruc- tion is fetched. 5: Current consumption on VDDBU. 6: 18.4 µA on VDDCORE, 26.6 µA for total current consumption (using internal voltage regulator). 7: Depends on MCK frequency. In this mode, the core is supplied and not clocked but some peripherals can be clocked.

6.7 Wake-up Sources

The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply. See Figure 17-7.

6.8 Fast Startup

The SAM3X8ERT allows the processor to restart in a few microseconds while the processor is in wait mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up inputs (WKUP0–15 + RTC + RTT + USB). TABLE 6-1: LOW POWER MODE CONFIGURATION SUMMARY Mode VDD BU Regi on (1) Regul ator Core Memory Periphera ls Mode Entry Potential Wake-up Sources Core at Wake-up PIO State While in Low Power Mode PIO State at Wake- up Consump tion(2) (3) Wake -up Time( Back up Mode ON OFF SHD N = 0 OFF (not pow- ered) WFE SLEEP- DEEP = FWUP pin Pins WKUP0– BOD alarm RTC alarm RTT alarm Reset Previ- ous state saved PIOA & PIOB & PIOC & PIOD & with pull-ups 2.5 µA typ(5) < 0.5 ms Wait Mode ON ON SHD N = 1 Pow- ered (not clocked WFE SLEEP- DEEP = + LPM = Any event from Fast Startup: - through pins WKUP0–15 - RTC alarm - RTT alarm - USB wake-up Clocke d back Previ- ous state saved Unchan ged 18.4 µA/26.6 µA(6) < 10 µs Sleep Mode ON ON SHD N = 1 Pow- ered(7) (not clocked WFE or WFI SLEEP- DEEP = + LPM = Entry mode = WFI interrupt only Entry mode = WFE Any enabled interrupt and/or any event from Fast Startup: - through pins WKUP0–15 - RTC alarm - RTT alarm - USB wake-up Clocke d back Previ- ous state saved Unchan ged (7) (7)

 2020 Microchip Technology Inc. DS60001614B-page 29 SAM3X8ERT The fast restart circuitry (shown in Figure 28-4) is fully asynchronous and provides a fast startup signal to the Power Management Controller. As soon as the fast startup signal is asserted, the PMC automatically restarts the embedded 4/8/12 MHz fast RC oscillator, switches the master clock on this 4 MHz clock by default and reenables the processor clock.

DS60001614B-page 30  2020 Microchip Technology Inc.

7.0 INPUT/OUTPUT LINES

The SAM3X8ERT has different kinds of input/output (I/O) lines, such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functions thanks to multiplexing capabilities of the PIO controllers. The same PIO line can be used whether in IO mode or by the multiplexed peripheral. System I/Os include pins such as test pins, oscillators, erase or analog inputs. With a few exceptions, the I/Os have input Schmitt triggers. Refer to the footnotes associated with PIOA to PIOF on page 17, at the end of TABLE 3-1:.

7.1 General Purpose I/O Lines (GPIO)

GPIO Lines are managed by PIO Controllers. All I/Os have several input or output modes such as pull-up, input Schmitt triggers, multi-drive (open-drain), glitch filters, debouncing or input change interrupt. Programming of these modes is performed independently for each I/O line through the PIO controller user interface. For more details, refer to Section 31.0 “Parallel Input/Output Controller (PIO)”. The input output buffers of the PIO lines are supplied through VDDIO power supply rail. The SAM3X8ERT embeds high speed pads able to handle up to 65 MHz for HSMCI and SPI clock lines and 45 MHz on other lines. See Section 45.10 “AC Characteristics” for more details. Typical pull-up value is 100 k for all I/Os. Each I/O line also embeds an ODT (On-Die Termination) (see Figure 7-1). ODT consists of an internal series resistor termination scheme for impedance matching between the driver output (SAM3X8ERT) and the PCB track impedance preventing signal reflection. The series resistor helps to reduce IOs switching current (di/dt) thereby reducing in turn, EMI. It also decreases overshoot and undershoot (ringing) due to inductance of interconnect between devices or between boards. In conclusion, ODT helps reducing signal integrity issues. FIGURE 7-1: ON-DIE TERMINATION

7.2 System I/O Lines

Table 7-1 lists the SAM3X8ERT system I/O lines shared with PIO lines. These pins are software configurable as general purpose I/O or system pins. At startup, the default function of these pins is always used. TABLE 7-1: SYSTEM I/O CONFIGURATION PIN LIST CCFG_SYSI O Bit No. Periphera l Default Function After Reset Other Functio n Constraints for Normal Start Configuration 12 — ERASE PC0 Low Level at startup(1) In Matrix User Interface Regis- ters (refer to System I/O Config- uration Register in Section 22.0 “Bus Matrix (MATRIX)”) — A TCK/SWCLK PB28 — In PIO Controller — A TDI PB29 — — A TDO/TRACESW O PB30 — — A TMS/SWDIO PB31 — PCB Track Z0 ~ 50 Ω Receiver SAM3X8ERT Driver with RODT ZO ~ 10 Ω Z0 ~ ZO + RODT ODT 36 Ω Typ.

 2020 Microchip Technology Inc. DS60001614B-page 31 SAM3X8ERT Note 1: If PC0 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash erase before the user application sets PC0 into PIO mode.

7.2.1 SERIAL WIRE JTAG DEBUG PORT (SWJ-DP) PINS

The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/TRACESWO, TDI and commonly provided on a standard 20- pin JTAG connector defined by ARM. For more details about voltage reference and reset state, refer to Table 3-1. At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging probe. Refer to Section 12.0 “Debug and Test Features”. SWJ-DP pins can be used as standard I/Os to provide users with more general input/output pins when the debug port is not needed in the end application. Mode selection between SWJ-DP mode (System IO mode) and general IO mode is performed through the AHB Matrix Special Function Registers (MATRIX_SFR). Configuration of the pad for pull-up, triggers, de-bouncing and glitch filters is possible regardless of the mode. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pull-down resistor of about 15 k to GND, so that it can be left unconnected for normal operations. By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables the JTAG-DP and enables the SW-DP. When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be used with SW-DP, not JTAG-DP . For more information about SW-DP and JTAG-DP switching, refer to Section 12.0 “Debug and Test Features”. All JTAG signals are supplied with VDDIO except JTAGSEL, supplied by VDDBU.

7.3 Test Pin

The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM3X8ERT. The TST pin integrates a permanent pull-down resistor of about 15 k  to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, see Section 20.0 “Fast Flash Programming Interface (FFPI)”. For more information on the manufacturing and test mode, refer to Section 12.0 “Debug and Test Features”.

7.4 NRST Pin

The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components, or asserted low externally to reset the microcontroller. It will reset the Core and the periph- erals except the Backup region (RTC, RTT, and Supply Controller). There is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length. The NRST pin integrates a permanent pull-up resistor to VDDIO of about 100 k.

7.5 NRSTB Pin

The NRSTB pin is input only and enables asynchronous reset of the SAM3X8ERT when asserted low. The NRSTB pin integrates a permanent pull-up resistor of about 15 k. This allows connection of a simple push button on the NRSTB pin as a system-user reset. In all modes, this pin will reset the chip including the Backup region (RTC, RTT and Supply Controller). It reacts as the Power-on reset. It can be used as an external system reset source. In harsh environments, it is recommended to add an external capacitor (10 nF) between NRSTB and VDDBU. (For filtering values, refer to “I/O Characteristics” in Section 45.0 “Electrical Characteristics”.) It embeds an anti-glitch filter.

7.6 ERASE Pin

The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased state (all bits read as logic level 1). The ERASE pin and the ROM code ensure an in-situ reprogrammability of the Flash content without the use of a debug tool. When the security bit is activated, the ERASE pin provides the capability to reprogram the Flash content. It integrates a pull-down resistor of about 100 k to GND, so that it can be left unconnected for normal opera- tions. This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high during less than 100 ms, it is not taken into account. The pin must be tied high during more than 220 ms to perform a Flash erase operation.

DS60001614B-page 32  2020 Microchip Technology Inc. The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE pin is not configured as a PIO pin. If the ERASE pin is used as a standard I/O, the startup level of this pin must be low to prevent unwanted erasing. Refer to Section 10.3 “Peripheral Signal Multiplexing on I/O Lines”. Also, if the ERASE pin is used as a standard I/O output, asserting the pin to high does not erase the Flash.

 2020 Microchip Technology Inc. DS60001614B-page 33 SAM3X8ERT

8.0 MEMORIES

8.1 Product Mapping

FIGURE 8-1: SAM3X8ERT PRODUCT MAPPING

DS60001614B-page 34  2020 Microchip Technology Inc.

8.2 Embedded Memories

8.2.1 INTERNAL SRAM

Table 8-1 shows the embedded high-speed SRAM for the various devices. SRAM0 is accessible over the system Cortex-M3 bus at address 0x2000 0000 and SRAM1 at address 0x2008 0000. The user can see the SRAM as contiguous thanks to mirror effect, giving 0x2007 0000 - 0x2008 7FFF for SAM3X8ERT. SRAM0 and SRAM1 are in the bit band region. The bit band alias region is mapped from 0x2200 0000 to 0x23FFFFFF. The NAND Flash Controller (NFC) embeds 4224 bytes of internal SRAM. If the NFC is not used, these 4224Kbytes can be used as general-purpose SRAM. It can be seen at address 0x2010 0000.

8.2.2 INTERNAL ROM

The SAM3X8ERT product embeds an Internal ROM, which contains the SAM-BA and FFPI program. At any time, the ROM is mapped at address 0x0010 0000.

8.2.3 EMBEDDED FLASH

8.2.3.1 Flash Overview

Table 8-2 shows the Flash organization for the various devices. The Flash contains a 128-byte write buffer, accessible through a 32-bit interface.

8.2.3.2 Flash Power Supply

The Flash is supplied by VDDCORE.

8.2.3.3 Enhanced Embedded Flash Controller

The Enhanced Embedded Flash Controller (EEFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped within the Memory Con- troller on the APB. The EEFC ensures the interface of the Flash block with the 32-bit internal bus. Its 128-bit wide memory interface increases performance. The user can choose between high performance or lower current consumption by selecting either 128-bit or 64-bit access. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash orga- nization, thus making the software generic. TABLE 8-1: EMBEDDED HIGH-SPEED SRAM PER DEVICE Device Pin Count SRAM0 (KB) SRAM1 (KB) NFC SRAM (KB) Total SRAM (KB) SAM3X8ERT 144 64 32 4 100 TABLE 8-2: EMBEDDED FLASH MEMORY ORGANIZATION PER DEVICE Device Flash Size (Kbytes) Number of Banks Number of Pages Page Size (bytes) Plane SAM3X8ERT 512 2 1024 256 Dual

 2020 Microchip Technology Inc. DS60001614B-page 35 SAM3X8ERT

8.2.3.4 Lock Regions

Several lock bits are used to protect write and erase operations on lock regions. A lock region is composed of several consecutive pages, and each lock region has its associated lock bit. If a locked-region’s erase or program command occurs, the command is aborted and the EEFC triggers an interrupt. The lock bits are software programmable through the EEFC User Interface. The “Set Lock Bit” command enables the protection. The “Clear Lock Bit” command unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

8.2.3.5 Security Bit Feature

The SAM3X8ERT features a security bit, based on a specific General Purpose NVM bit (GPNVM bit 0). When the secu- rity is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Programming Inter- face (FFPI), is forbidden. This ensures the confidentiality of the code programmed in the Flash. This security bit can only be enabled through the “Set General Purpose NVM Bit 0” command of the EEFC0 User Inter- face. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated, all accesses to the Flash are permitted. Note: The assertion of the ERASE pin should always be longer than 200 ms. As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is safer to connect it directly to GND for the final application.

8.2.3.6 Calibration Bits

NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits.

8.2.3.7 Unique Identifier

Each device integrates its own 128-bit unique identifier. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the unique identifier.

8.2.3.8 Fast Flash Programming Interface (FFPI)

The FFPI allows device programming through multiplexed fully-handshaked parallel port. It allows gang programming with market-standard industrial programmers. The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The FFPI is enabled and the Fast Programming Mode is entered when TST, PA0, PA1 are set to high, PA2 and PA3 are set to low and NRST is toggled from 0 to 1. The table below shows the signal assignment of the PIO lines in FFPI mode TABLE 8-3: NUMBER OF LOCK BITS Product Number of Lock Bits Lock Region Size SAM3X8ERT 32 16 Kbytes (64 pages) TABLE 8-4: FFPI PIO ASSIGNMENT FFPI Signal PIO Used PGMNCMD PA0 PGMRDY PA1 PGMNOE PA2 PGMNVALID PA3 PGMM[0] PA4 PGMM[1] PA5 PGMM[2] PA6 PGMM[3] PA7 PGMD[0] PA8

DS60001614B-page 36  2020 Microchip Technology Inc.

8.2.3.9 SAM-BA Boot

The SAM-BA Boot is a default boot program which provides an easy way to program in-situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication via the UART and USB. The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0.

8.2.3.10 GPNVM Bits

The SAM3X8ERT features three GPNVM bits that can be cleared or set respectively through the “Clear GPNVM Bit” and “Set GPNVM Bit” commands of the EEFC0 User Interface. There is no GPNVM bit on Flash 1. The GPNVM0 is the security bit. The GPNVM1 is used to select the boot mode (boot always at 0x00) on ROM or Flash. The GPNVM2 is used only to swap the Flash 0 and Flash 1. If GPNVM2 is ENABLE, the Flash 1 is mapped at address 0x0008_0000 (Flash 1 and Flash 0 are continuous). If GPNVM2 is DISABLE, the Flash 0 is mapped at address 0x0008_0000 (Flash 0 and Flash 1 are continuous).

8.2.4 BOOT STRATEGIES

The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed via GPNVM. A general-purpose NVM (GPNVM1) bit is used to boot either on the ROM (default) or from the Flash. Setting GPNVM bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM. Asserting ERASE clears GPNVM bit 1 and thus selects the boot from the ROM by default. GPNVM2 enables to select if Flash 0 or Flash 1 is used for the boot. PGMD[1] PA9 PGMD[2] PA10 PGMD[3] PA11 PGMD[4] PA12 PGMD[5] PA13 PGMD[6] PA14 PGMD[7] PA15 PGMD[8] PA16 PGMD[9] PA17 PGMD[10] PA18 PGMD[11] PA19 PGMD[12] PA20 PGMD[13] PA21 PGMD[14] PA22 PGMD[15] PA23 TABLE 8-5: GENERAL PURPOSE NON-VOLATILE MEMORY BITS GPNVM Bit[#] Function

0 Security bit

1 Boot mode selection

2 Flash selection (Flash 0 or Flash 1)

TABLE 8-4: FFPI PIO ASSIGNMENT FFPI Signal PIO Used

 2020 Microchip Technology Inc. DS60001614B-page 37 SAM3X8ERT Setting GPNVM bit 2 selects the boot from Flash 1, clearing it selects the boot from Flash 0.

8.3 External Memories

The 144-pin SAM3X8ERT feature one External Memory Bus to offer interface to a wide range of external memories and to any parallel peripheral.

8.3.1 EXTERNAL MEMORY BUS

• Integrates Three External Memory Controllers: - Static Memory Controller - NAND Flash Controller - SLC NAND Flash ECC Controller
• Up to 24-bit Address Bus (up to 16 Mbytes linear per chip select)
• Up to 8 chip selects, Configurable Assignment

8.3.2 STATIC MEMORY CONTROLLER

• 8- or 16-bit Data Bus
• Multiple Access Modes supported - Byte Write or Byte Select Lines - Asynchronous read in Page Mode supported (4- up to 32-byte page size)
• Multiple device adaptability - Control signals programmable setup, pulse and hold time for each Memory Bank
• Multiple Wait State Management - Programmable Wait State Generation - External Wait Request - Programmable Data Float Time
• Slow Clock mode supported

8.3.3 NAND FLASH CONTROLLER

• Handles automatic Read/write transfer through 4224 bytes SRAM buffer
• DMA support
• Supports SLC NAND Flash technology
• Programmable timing on a per chip select basis
• Programmable Flash Data width 8-bit or 16-bit

8.3.4 NAND FLASH ERROR CORRECTED CODE CONTROLLER

• Integrated in the NAND Flash Controller
• Single bit error correction and 2-bit Random detection.
• Automatic Hamming Code Calculation while writing - ECC value available in a register
• Automatic Hamming Code Calculation while reading - Error Report, including error flag, correctable error flag and word address being detected erroneous - Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-byte pages

DS60001614B-page 38  2020 Microchip Technology Inc.

9.0 SYSTEM CONTROLLER

The System Controller is a set of peripherals which allow handling of key elements of the system such as but not limited to power, resets, clocks, time, interrupts, and watchdog. The System Controller User Interface also embeds the registers allowing to configure the Matrix.

9.1 System Controller and Peripherals Mapping

Refer to FIGURE 8-1:. All the peripherals are in the bit band region and are mapped in the bit band alias region.

9.2 Power-on-Reset, Brownout and Supply Monitor

The SAM3X8ERT embeds three features to monitor, warn and/or reset the chip:

• Power-on-Reset on VDDBU
• Brownout Detector on VDDCORE
• Supply Monitor on VDDUTMI

9.2.1 POWER-ON-RESET ON VDDBU

The Power-on-Reset monitors VDDBU. It is always activated and monitors voltage at start up but also during power down. If VDDBU goes below the threshold voltage, the entire chip is reset. For more information, refer to Section 45.0 “Electrical Characteristics”.

9.2.2 BROWNOUT DETECTOR ON VDDCORE

The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by software through the Supply Controller (SUPC_MR). It is especially recommended to disable it during low-power modes such as wait or sleep modes. If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For more information, refer to Section 17.0 “Supply Controller (SUPC)” and Section 45.0 “Electrical Characteristics”.

9.2.3 SUPPLY MONITOR ON VDDUTMI

The Supply Monitor monitors VDDUTMI. It is not active by default. It can be activated by software and is fully program- mable with 16 steps for the threshold (between 1.9V to 3.4V). It is controlled by the Supply Controller (SUPC). A sample mode is possible. It allows to divide the supply monitor power consumption by a factor of up to 2048. For more informa- tion, refer to Section 17.0 “Supply Controller (SUPC)” and Section 45.0 “Electrical Characteristics”.

 2020 Microchip Technology Inc. DS60001614B-page 39 SAM3X8ERT

10.0 PERIPHERALS

10.1 Peripheral Identifiers

Table 10-1 defines the Peripheral Identifiers of the SAM3X8ERT. A peripheral identifier is required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Some peripherals are always clocked. Refer to the table below. TABLE 10-1: PERIPHERAL IDENTIFIERS Instance ID Instance Name NVIC Interrupt PMC Clock Control Instance Description

0 SUPC X — Supply Controller

1 RSTC X — Reset Controller

2 RTC X — Real-time Clock

3 RTT X — Real-time Timer

4 WDG X — Watchdog Timer

5 PMC X — Power Management Controller

6 EEFC0 X — Enhanced Embedded Flash Controller 0

7 EEFC1 X — Enhanced Embedded Flash Controller 1

8 UART X — Universal Asynchronous Receiver Transceiver

9 SMC_S-

X X Static Memory Controller

10 Reserved

11 PIOA X X Parallel I/O Controller A

12 PIOB X X Parallel I/O Controller B

13 PIOC X X Parallel I/O Controller C

14 PIOD X X Parallel I/O Controller D

15 Reserved

16 Reserved

17 USART0 X X Universal Synchronous Asynchronous Receiver Transmitter

18 USART1 X X Universal Synchronous Asynchronous Receiver Transmitter

19 USART2 X X Universal Synchronous Asynchronous Receiver Transmitter

20 USART3 X X Universal Synchronous Asynchronous Receiver Transmitter

21 HSMCI X X High Speed Multimedia Card Interface

22 TWI0 X X Two-Wire Interface 0

23 TWI1 X X Two-Wire Interface 1

24 SPI0 X X Serial Peripheral Interface 0

25 SPI1 X X Serial Peripheral Interface 1

26 SSC X X Synchronous Serial Controller

27 TC0 X X Timer Counter Channel 0

28 TC1 X X Timer Counter Channel 1

29 TC2 X X Timer Counter Channel 2

30 TC3 X X Timer Counter Channel 3

DS60001614B-page 40  2020 Microchip Technology Inc.

10.2 APB/AHB Bridge

The SAM3X8ERT product embeds two separate APB/AHB bridges:

• a low speed bridge
• a high speed bridge This architecture enables a concurrent access on both bridges. SPI, SSC, and HSMCI peripherals are on the high-speed bridge connected to DMAC with the internal FIFO for Channel buffering. UART, ADC, TWI0–1, USART0–3, PWM, DAC, and CAN peripherals are on the low-speed bridge and have dedicated channels for the Peripheral DMA Channels (PDC). Note: USART0–1 can be used with the DMA as well. The peripherals on the high speed bridge are clocked by MCK. On the low-speed bridge, CAN controllers can be clocked at MCK divided by 2 or 4. Refer to Section 27.0 “Clock Generator”.

10.3 Peripheral Signal Multiplexing on I/O Lines

The SAM3X8ERT product features four PIO controllers (PIOA, PIOB, PIOC and PIOD) which multiplex the I/O lines of the peripheral set. Each PIO controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. The multiplexing tables in the following pages define how the I/O lines of the peripherals A and B are multiplexed on the PIO controllers. Note that some output-only peripheral functions might be duplicated within the tables.

10.3.1 PIO CONTROLLER A MULTIPLEXING

31 TC4 X X Timer Counter Channel 4

32 TC5 X X Timer Counter Channel 5

33 TC6 X X Timer Counter Channel 6

34 TC7 X X Timer Counter Channel 7

35 TC8 X X Timer Counter Channel 8

36 PWM X X Pulse Width Modulation Controller

37 ADC X X ADC Controller

38 DACC X X DAC Controller

39 DMAC X X DMA Controller

40 UOTGHS X X USB OTG High Speed

41 TRNG X X True Random Number Generator

42 EMAC X X Ethernet MAC

43 CAN0 X X CAN Controller 0

44 CAN1 X X CAN Controller 1

TABLE 10-2: MULTIPLEXING ON PIO CONTROLLER A (PIOA) I/O Line Peripheral A Peripheral B Extra Function Comments PA0 CANTX0 PWML3 — — PA1 CANRX0 PCK0 WKUP0(1) — PA2 TIOA1 NANDRDY AD0(2) — PA3 TIOB1 PWMFI1 AD1/WKUP1(3) — TABLE 10-1: PERIPHERAL IDENTIFIERS (CONTINUED) Instance ID Instance Name NVIC Interrupt PMC Clock Control Instance Description

 2020 Microchip Technology Inc. DS60001614B-page 41 SAM3X8ERT Note 1: WKUPx can be used, if PIO controller defines the I/O line as "input". 2: To select this extra function, refer to Section 43.5.3 “Analog Inputs”. 3: Analog input has priority over WKUPx pin.

10.3.2 PIO CONTROLLER B MULTIPLEXING

PA4 TCLK1 NWAIT AD2(2) — PA5 TIOA2 PWMFI0 WKUP2(1) — PA6 TIOB2 NCS0 AD3(2) — PA7 TCLK2 NCS1 WKUP3(1) — PA8 URXD PWMH0 WKUP4(1) — PA9 UTXD PWMH3 — — PA10 RXD0 DATRG WKUP5(1) — PA11 TXD0 ADTRG WKUP6(1) — PA12 RXD1 PWML1 WKUP7(1) — PA13 TXD1 PWMH2 — — PA14 RTS1 TK — — PA15 CTS1 TF WKUP8(1) — PA16 SPCK1 TD AD7(2) — PA17 TWD0 SPCK0 — — PA18 TWCK0 A20 WKUP9(1) — PA19 MCCK PWMH1 — — PA20 MCCDA PWML2 — — PA21 MCDA0 PWML0 — — PA22 MCDA1 TCLK3 AD4(2) — PA23 MCDA2 TCLK4 AD5(2) — PA24 MCDA3 PCK1 AD6(2) — PA25 SPI0_MISO A18 — — PA26 SPI0_MOSI A19 — — PA27 SPI0_SPCK A20 WKUP10(1) — PA28 SPI0_NPCS0 PCK2 WKUP11(1) — PA29 SPI0_NPCS1 NRD — — TABLE 10-3: MULTIPLEXING ON PIO CONTROLLER B (PIOB) I/O Line Peripheral A Peripheral B Extra Function Comments PB0 ETXCK/EREFCK — — — PB1 ETXEN — — — PB2 ETX0 — — — PB3 ETX1 — — — PB4 ECRSDV/ERXDV — — — PB5 ERX0 — — — PB6 ERX1 — — — PB7 ERXER — — — PB8 EMDC — — — PB9 EMDIO — — — PB10 UOTGVBOF A18 — — PB11 UOTGID A19 — — PB12 TWD1 PWMH0 AD8(4) — TABLE 10-2: MULTIPLEXING ON PIO CONTROLLER A (PIOA) I/O Line Peripheral A Peripheral B Extra Function Comments

DS60001614B-page 42  2020 Microchip Technology Inc. 4: To select this extra function, refer to Section 43.5.3 “Analog Inputs”. 5: Analog input has priority over WKUPx pin. 6: DAC0 is selected when DACC_CHER.CH0 is set. DAC1 is selected when DACC_CHER.CH1 is set. See Section 44.7.3 “DACC Channel Enable Register”. 7: WKUPx can be used if PIO controller defines the I/O line as "input".

10.3.3 PIO CONTROLLER C MULTIPLEXING

PB13 TWCK1 PWMH1 AD9(4) — PB14 CANTX1 PWMH2 — — PB15 CANRX1 PWMH3 DAC0/WKUP12(5) — PB16 TCLK5 PWML0 DAC1(6) — PB17 RF PWML1 AD10(4) — PB18 RD PWML2 AD11(4) — PB19 RK PWML3 AD12(4) — PB20 TXD2 SPI0_NPCS1 AD13(4) — PB21 RXD2 SPI0_NPCS2 AD14/WKUP13(5) — PB22 RTS2 PCK0 — — PB23 CTS2 SPI0_NPCS3 WKUP14(7) — PB24 SCK2 NCS2 — — PB25 RTS0 TIOA0 — — PB26 CTS0 TCLK0 WKUP15(7) — PB27 NCS3 TIOB0 — — PB28 TCK/SWCLK — — TCK after reset PB29 TDI — — TDI after reset PB30 TDO/TRACESWO — — TDO after reset PB31 TMS/SWDIO — — TMS after reset TABLE 10-4: MULTIPLEXING ON PIO CONTROLLER C (PIOC) I/O Line Peripheral A Peripheral B Extra Function PC0 — — ERASE(4) PC1 — — — PC2 D0 PWML0 — PC3 D1 PWMH0 — PC4 D2 PWML1 — PC5 D3 PWMH1 — PC6 D4 PWML2 — PC7 D5 PWMH2 — PC8 D6 PWML3 — PC9 D7 PWMH3 — PC10 D8 ECRS — PC11 D9 ERX2 — PC12 D10 ERX3 — PC13 D11 ECOL — PC14 D12 ERXCK — PC15 D13 ETX2 — PC16 D14 ETX3 — PC17 D15 ETXER — TABLE 10-3: MULTIPLEXING ON PIO CONTROLLER B (PIOB) I/O Line Peripheral A Peripheral B Extra Function Comments

 2020 Microchip Technology Inc. DS60001614B-page 43 SAM3X8ERT Notes: 1. To select this extra function, refer to Section 7.2 “System I/O Lines”.

10.3.4 PIO CONTROLLER D MULTIPLEXING

PC18 NWR0/NWE PWMH6 — PC19 NANDOE PWMH5 — PC20 NANDWE PWMH4 — PC21 A0/NBS0 PWML4 — PC22 A1 PWML5 — PC23 A2 PWML6 — PC24 A3 PWML7 — PC25 A4 TIOA6 — PC26 A5 TIOB6 — PC27 A6 TCLK6 — PC28 A7 TIOA7 — PC29 A8 TIOB7 — PC30 A9 TCLK7 — TABLE 10-5: MULTIPLEXING ON PIO CONTROLLER D (PIOD) I/O Line Peripheral A Peripheral B Extra Function PD0 A10 MCDA4 — PD1 A11 MCDA5 — PD2 A12 MCDA6 — PD3 A13 MCDA7 — PD4 A14 TXD3 — PD5 A15 RXD3 — PD6 A16/BA0 PWMFI2 — PD7 A17/BA1 TIOA8 — PD8 A21/NANDALE TIOB8 — PD9 A22/NANDCLE TCLK8 — PD10 NWR1/NBS1 — — TABLE 10-4: MULTIPLEXING ON PIO CONTROLLER C (PIOC) I/O Line Peripheral A Peripheral B Extra Function

DS60001614B-page 44  2020 Microchip Technology Inc.

11.0 ARM CORTEX M3 PROCESSOR

11.1 About this section

This section provides the information required for application and system-level software development. It does not pro - vide information on debug components, features, or operation. This material is for Microcontroller software and hardware engineers, including those who have no experience of ARM products. Note: The information in this section is reproduced from source material provided to Microchip by ARM Ltd. in terms of Microchip’s license for the ARM Cortex ™-M3 processor core. This information is copyright ARM Ltd., 2008 - 2009.

11.2 Embedded Characteristics

• Version 2.0
• Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit
• Harvard processor architecture enabling simultaneous instruction fetch with data load/store
• Three-stage pipeline
• Single cycle 32-bit multiply
• Hardware divide
• Thumb and Debug states
• Handler and Thread modes
• Low latency ISR entry and exit
• SysTick Timer - 24-bit down counter - Self-reload capability - Flexible system timer
• Nested Vectored Interrupt Controller - Thirty maskable interrupts - Sixteen priority levels - Dynamic reprioritization of interrupts - Priority grouping selection of preempting interrupt levels and non preempting interrupt levels. - Support for tail-chaining and late arrival of interrupts. back-to-back interrupt processing without the overhead of state saving and restoration between interrupts. - Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction over- head.

11.3 About the Cortex-M3 Processor and Core Peripherals

• The Cortex-M3 processor is a high performance 32-bit processor designed for the microcontroller market. It offers significant benefits to developers, including:
• Outstanding processing performance combined with fast interrupt handling
• Enhanced system debug with extensive breakpoint and trace capabilities
• Efficient processor core, system and memories
• Ultra-low power consumption with integrated sleep modes
• Platform security, with integrated Memory Protection Unit (MPU).

 2020 Microchip Technology Inc. DS60001614B-page 45 SAM3X8ERT FIGURE 11-1: TYPICAL CORTEX-M3 IMPLEMENTATION The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including single-cycle 32x32 multiplication and dedicated hardware division. To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly-coupled system compo - nents that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M3 processor implements a version of the Thumb instruction set, ensuring high code density and reduced pro- gram memory requirements. The Cortex-M3 instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. The Cortex-M3 processor closely integrates a configurable nested interrupt controller (NVIC), to deliver industry-leading interrupt performance. The NVIC provides up to 16 interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to suspend load-multiple and store-multiple oper- ations. Interrupt handlers do not require any assembler stubs, removing any code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that enables the entire device to be rapidly powered down.

11.3.1 SYSTEM LEVEL INTERFACE

The Cortex-M3 processor provides multiple interfaces using AMBA technology to provide high speed, low latency memory accesses. It supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe Boolean data handling. The Cortex-M3 processor has a memory protection unit (MPU) that provides fine grain memory control, enabling appli- cations to implement security privilege levels, separating code, data and stack on a task-by-task basis. Such require - ments are becoming critical in many embedded applications.

11.3.2 INTEGRATED CONFIGURABLE DEBUG

The Cortex-M3 processor implements a complete hardware debug solution. This provides high system visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices. Processor CoreNVIC Debug Access Port Memory Protection Unit Serial Wire Viewer Bus Matrix Code Interface SRAM and Peripheral Interface Data Watchpoints Flash Patch Cortex-M3 Processor

DS60001614B-page 46  2020 Microchip Technology Inc. For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system events these generate, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information through a single pin.

11.3.3 CORTEX-M3 PROCESSOR FEATURES AND BENEFITS SUMMARY

• Tight integration of system peripherals reduces area and development costs
• Thumb instruction set combines high code density with 32-bit performance
• Code-patch ability for ROM system updates
• Power control optimization of system components
• Integrated sleep modes for low power consumption
• Fast code execution permits slower processor clock or increases sleep mode time
• Hardware division and fast multiplier
• Deterministic, high-performance interrupt handling for time-critical applications
• Memory protection unit (MPU) for safety-critical applications
• Extensive debug and trace capabilities: - Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and tracing.

11.3.4 CORTEX-M3 CORE PERIPHERALS

These are:

11.3.4.1 Nested Vectored Interrupt Controller

The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that supports low latency interrupt processing.

11.3.4.2 System Control Block

The System control block (SCB) is the programmers model interface to the processor. It provides system implementa- tion information and system control, including configuration, control, and reporting of system exceptions.

11.3.4.3 System Timer

The system timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating System (RTOS) tick timer or as a simple counter.

11.3.4.4 Memory Protection Unit

The Memory Protection Unit (MPU) improves system reliability by defining the memory attributes for different memory regions. It provides up to eight different regions, and an optional predefined background region.

11.4 Programmers Model

This section describes the Cortex-M3 programmers model. In addition to the individual core register descriptions, it con- tains information about the processor modes and privilege levels for software execution and stacks.

11.4.1 PROCESSOR MODE AND PRIVILEGE LEVELS FOR SOFTWARE EXECUTION

The processor modes are:

11.4.1.1 Thread Mode

Used to execute application software. The processor enters Thread mode when it comes out of reset.

11.4.1.2 Handler Mode

Used to handle exceptions. The processor returns to Thread mode when it has finished exception processing. The privilege levels for software execution are:

11.4.1.3 Unprivileged

The software:

• Has limited access to the MSR and MRS instructions, and cannot use the CPS instruction

 2020 Microchip Technology Inc. DS60001614B-page 47 SAM3X8ERT

• Cannot access the system timer, NVIC, or system control block
• Might have restricted access to memory or peripherals. Unprivileged software executes at the unprivileged level.

11.4.1.4 Privileged

The software can use all the instructions and has access to all resources. Privileged software executes at the privileged level. In Thread mode, the CONTROL register controls whether software execution is privileged or unprivileged, see “CON- TROL Register” on page 53. In Handler mode, software execution is always privileged. Only privileged software can write to the CONTROL register to change the privilege level for software execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to privi- leged software.

11.4.2 STACKS

The processor uses a full descending stack. This means the stack pointer indicates the last stacked item on the stack memory. When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements two stacks, the main stack and the process stack, with independent copies of the stack pointer, see “Stack Pointer” on page 49. In Thread mode, the CONTROL register controls whether the processor uses the main stack or the process stack, see “CONTROL Register” on page 53. In Handler mode, the processor always uses the main stack. The options for proces- sor operations are: TABLE 11-1: SUMMARY OF PROCESSOR MODE, EXECUTION PRIVILEGE LEVEL, AND STACK USE OPTIONS Processor mode Used to execute Privilege level for software execution Stack used Thread Applications Privileged or unprivileged (1) 1. See “CONTROL Register” on page 53. Main stack or process stack(1) Handler Exception handlers Always privileged Main stack

DS60001614B-page 48  2020 Microchip Technology Inc.

11.4.3 CORE REGISTERS

The processor core registers are:

11.4.3.1 General-purpose registers

R0-R12 are 32-bit general-purpose registers for data operations. TABLE 11-2: CORE REGISTER SET SUMMARY Name Type (1) 1. Describes access type during program execution in thread mode and Handler mode. Debug access can differ. Required privilege (2) 2. An entry of Either means privileged and unprivileged software can access the register. Reset value Description R0-R12 RW Either Unknown “General-purpose registers” on page 48 MSP RW Privileged See description “Stack Pointer” on page 49 PSP RW Either Unknown “Stack Pointer” on page 49 LR RW Either 0xFFFFFFFF “Link Register” on page 49 PC RW Either See description “Program Counter” on page 49 PSR RW Privileged 0x01000000 “Program Status Register” on page 49 ASPR RW Either 0x00000000 “Application Program Status Register” on page 50 IPSR RO Privileged 0x00000000 “Interrupt Program Status Register” on page 51 EPSR RO Privileged 0x01000000 “Execution Program Status Register” on page 51 PRIMASK RW Privileged 0x00000000 “Priority Mask Register” on page 52 FAULTMASK RW Privileged 0x00000000 “Fault Mask Register” on page 52 BASEPRI RW Privileged 0x00000000 “Base Priority Mask Register” on page 53 CONTROL RW Privileged 0x00000000 “CONTROL Register” on page 53 SP (R13) LR (R14) PC (R15) R10 R11 R12 Low registers High registers MSP‡PSP‡ PSR PRIMASK FAULTMASK BASEPRI CONTROL General-purpose registers Stack Pointer Link Register Program Counter Program status register Exception mask registers CONTROL register Special registers ‡Banked version of SP

 2020 Microchip Technology Inc. DS60001614B-page 49 SAM3X8ERT

11.4.3.2 Stack Pointer

The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register indicates the stack pointer to use:

• 0 = Main Stack Pointer (MSP). This is the reset value
• 1 = Process Stack Pointer (PSP) On reset, the processor loads the MSP with the value from address 0x00000000.

11.4.3.3 Link Register

The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions. On reset, the processor loads the LR value 0xFFFFFFFF.

11.4.3.4 Program Counter

The Program Counter (PC) is register R15. It contains the current program address. Bit[0] is always 0 because instruc- tion fetches must be halfword aligned. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x00000004.

11.4.3.5 Program Status Register

The Program Status Register (PSR) combines:

• Application Program Status Register (APSR)
• Interrupt Program Status Register (IPSR)
• Execution Program Status Register (EPSR) These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignments are:
• APSR:
• IPSR:
• EPSR: 31 30 29 28 27 26 25 24 N Z C V Q Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved ISR_NUMBER 7 6 5 4 3 2 1 0 ISR_NUMBER 31 30 29 28 27 26 25 24 Reserved ICI/IT T 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 ICI/IT Reserved 7 6 5 4 3 2 1 0 Reserved

DS60001614B-page 50  2020 Microchip Technology Inc. The PSR bit assignments are: Access these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example:

• Read all of the registers using PSR with the MRS instruction
• Write to the APSR using APSR with the MSR instruction. The PSR combinations and attributes are: See the instruction descriptions “MRS” on page 111 and “MSR” on page 112 for more information about how to access the program status registers.

11.4.3.6 Application Program Status Register

The APSR contains the current state of the condition flags from previous instruction executions. See the register sum- mary in Table 11-2 for its attributes. The bit assignments are:

• N Negative or less than flag: 0 = Operation result was positive, zero, greater than, or equal 1 = Operation result was negative or less than.
• Z Zero flag: 0 = Operation result was not zero 1 = Operation result was zero.
• C Carry or borrow flag: 0 = Add operation did not result in a carry bit or subtract operation resulted in a borrow bit 1 = Add operation resulted in a carry bit or subtract operation did not result in a borrow bit.
• V Overflow flag: 0 = Operation did not result in an overflow 31 30 29 28 27 26 25 24 N Z C V Q ICI/IT T 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 ICI/IT Reserved ISR_NUM- BER 7 6 5 4 3 2 1 0 ISR_NUMBER TABLE 11-3: PSR REGISTER COMBINATIONS Register Type Combination PSR RW (1), (2) 1. The processor ignores writes to the IPSR bits. 2. Reads of the EPSR bits return zero, and the processor ignores writes to the these bits. APSR, EPSR, and IPSR IEPSR RO EPSR and IPSR IAPSR RW(1) APSR and IPSR EAPSR RW(2) APSR and EPSR

 2020 Microchip Technology Inc. DS60001614B-page 51 SAM3X8ERT 1 = Operation resulted in an overflow.

• Q Sticky saturation flag: 0 = Indicates that saturation has not occurred since reset or since the bit was last cleared to zero 1 = Indicates when an SSA T or USAT instruction results in saturation. This bit is cleared to zero by software using an MRS instruction.

11.4.3.7 Interrupt Program Status Register

The IPSR contains the exception type number of the current Interrupt Service Routine (ISR). See the register summary in Table 11-2 for its attributes. The bit assignments are:

• ISR_NUMBER This is the number of the current exception: 0 = Thread mode 1 = Reserved 2 = NMI 3 = Hard fault 4 = Memory management fault 5 = Bus fault 6 = Usage fault 7-10 = Reserved 11 = SVCall 12 = Reserved for Debug 13 = Reserved 14 = PendSV 15 = SysTick 16 = IRQ0 45 = IRQ29 see “Exception types” on page 62 for more information.

11.4.3.8 Execution Program Status Register

The EPSR contains the Thumb state bit, and the execution state bits for either the:

• If-Then (IT) instruction
• Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. See the register summary in Table 11-2 on page 48 for the EPSR attributes. The bit assignments are:
• ICI Interruptible-continuable instruction bits, see “Interruptible-continuable instructions” on page 51.
• IT Indicates the execution state bits of the IT instruction, see “IT” on page 106.
• T Always set to 1. Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write the EPSR using the MSR instruction in application software are ignored. Fault handlers can examine EPSR value in the stacked PSR to indicate the operation that is at fault. See “Exception entry and return” on page 66.

11.4.3.9 Interruptible-continuable instructions

When an interrupt occurs during the execution of an LDM or STM instruction, the processor:

DS60001614B-page 52  2020 Microchip Technology Inc.

• Stops the load multiple or store multiple instruction operation temporarily
• Stores the next register operand in the multiple operation to EPSR bits[15:12]. After servicing the interrupt, the processor:
• Returns to the register pointed to by bits[15:12]
• Resumes execution of the multiple load or store instruction. When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.

11.4.3.10 If-Then block

The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruction in the block is condi- tional. The conditions for the instructions are either all the same, or some can be the inverse of others. See “IT” on page 106 for more information.

11.4.3.11 Exception mask registers

The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they might impact on timing critical tasks. To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the value of PRIMASK or FAULTMASK. See “MRS” on page 111, “MSR” on page 112, and “CPS” on page 109 for more informa- tion.

11.4.3.12 Priority Mask Register

The PRIMASK register prevents activation of all exceptions with configurable priority. See the register summary in Table 11-2 for its attributes. The bit assignments are:

• PRIMASK 0: No effect 1: Prevents the activation of all exceptions with configurable priority.

11.4.3.13 Fault Mask Register

The FAULTMASK register prevents activation of all exceptions. See the register summary in Table 11-2 for its attributes. The bit assignments are:

• FAULTMASK 0: No effect 1: Prevents the activation of all exceptions. The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler. 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved PRIMASK 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved FAULTMASK

 2020 Microchip Technology Inc. DS60001614B-page 53 SAM3X8ERT

11.4.3.14 Base Priority Mask Register

The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the BASEPRI value. See the register sum- mary in Table 11-2 for its attributes. The bit assignments are:

• BASEPRI Priority mask bits: 0x0000 = No effect Nonzero = Defines the base priority for exception processing. The processor does not process any exception with a priority value greater than or equal to BASEPRI. This field is similar to the priority fields in the interrupt priority registers. The processor implements only bits[7:4] of this field, bits[3:0] read as zero and ignore writes. See “Interrupt Priority Registers” on page 119 for more information. Remember that higher priority field values correspond to lower exception priorities.

11.4.3.15 CONTROL Register

The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. See the register summary in Table 11-2 for its attributes. The bit assignments are:

• Active stack pointer Defines the current stack: 0: MSP is the current stack pointer 1: PSP is the current stack pointer. In Handler mode this bit reads as zero and ignores writes.
• Thread mode privilege level Defines the Thread mode privilege level: 0: Privileged 1: Unprivileged. Handler mode always uses the MSP , so the processor ignores explicit writes to the active stack pointer bit of the CON- TROL register when in Handler mode. The exception entry and return mechanisms update the CONTROL register. In an OS environment, ARM recommends that threads running in Thread mode use the process stack and the kernel and exception handlers use the main stack. By default, Thread mode uses the MSP . To switch the stack pointer used in Thread mode to the PSP , use the MSR instruction to set the Active stack pointer bit to 1, see “MSR” on page 112. 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 BASEPRI 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Active Stack Pointer Thread Mode Privilege Level

DS60001614B-page 54  2020 Microchip Technology Inc. When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction. This ensures that instructions after the ISB execute using the new stack pointer. See “ISB” on page 111

11.4.4 EXCEPTIONS AND INTERRUPTS

The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses handler mode to handle all exceptions except for reset. See “Exception Entry” on page 67 and “Excep- tion Return” on page 67 for more information. The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller” on page 115 for more informa- tion.

11.4.5 DATA TYPES

The processor:

• Supports the following data types: - 32-bit words - 16-bit halfwords - 8-bit bytes
• Supports 64-bit data transfer instructions.
• Manages all data memory accesses as little-endian. Instruction memory and Private Peripheral Bus (PPB) accesses are always little-endian. See “Memory regions, types and attributes” on page 55 for more information.

11.4.6 THE CORTEX MICROCONTROLLER SOFTWARE INTERFACE STANDARD

For a Cortex-M3 microcontroller system, the Cortex Microcontroller Software Interface Standard (CMSIS) defines:

• A common way to: - Access peripheral registers - Define exception vectors
• The names of: - The registers of the core peripherals - The core exception vectors
• A device-independent interface for RTOS kernels, including a debug channel. The CMSIS includes address definitions and data structures for the core peripherals in the Cortex-M3 processor. It also includes optional interfaces for middleware components comprising a TCP/IP stack and a Flash file system. CMSIS simplifies software development by enabling the reuse of template code and the combination of CMSIS-compli- ant software components from various middleware vendors. Software vendors can expand the CMSIS to include their peripheral definitions and access functions for those peripherals. This document includes the register names defined by the CMSIS, and gives short descriptions of the CMSIS functions that address the processor core and the core peripherals. This document uses the register short names defined by the CMSIS. In a few cases these differ from the architectural short names that might be used in other documents. The following sections give more information about the CMSIS:
• “Power management programming hints” on page 71
• “Intrinsic Functions” on page 74
• “The CMSIS mapping of the Cortex-M3 NVIC registers” on page 116
• “NVIC Programming Hints” on page 122.

 2020 Microchip Technology Inc. DS60001614B-page 55 SAM3X8ERT

11.5 Memory Model

This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4GB of addressable memory. The memory map is: The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to bit data, see “Bit-banding” on page 59. The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers, see “About the Cortex-M3 Peripherals” on page 115. This memory mapping is generic to ARM Cortex-M3 products. To get the specific memory mapping of this product, refer to the Memories section of the datasheet.

11.5.1 MEMORY REGIONS, TYPES AND ATTRIBUTES

The memory map and the programming of the MPU split the memory map into regions. Each region has a defined mem- ory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region. The memory types are:

11.5.1.1 Normal

The processor can re-order transactions for efficiency, or perform speculative reads. Vendor-specific memory External device External RAM Peripheral SRAM Code 0xFFFFFFFF Private peripheral bus 0xE0100000 0xE00FFFFF 0x9FFFFFFF 0xA0000000 0x5FFFFFFF 0x60000000 0x3FFFFFFF 0x40000000 0x1FFFFFFF 0x20000000 0x00000000 0x40000000 Bit band region Bit band alias32MB 1MB0x400FFFFF 0x42000000 0x43FFFFFF Bit band region Bit band alias32MB 1MB0x20000000 0x200FFFFF 0x22000000 0x23FFFFFF 1.0GB 1.0GB 0.5GB 0.5GB 0.5GB 0xDFFFFFFF 0xE0000000 1.0MB 511MB

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11.5.1.2 Device

The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory.

11.5.1.3 Strongly-ordered

The processor preserves transaction order relative to all other transactions. The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory. The additional memory attributes include.

11.5.1.4 Shareable

For a shareable memory region, the memory system provides data synchronization between bus masters in a system with multiple bus masters, for example, a processor with a DMA controller. Strongly-ordered memory is always shareable. If multiple bus masters can access a non-shareable memory region, software must ensure data coherency between the bus masters.

11.5.1.5 Execute Never (XN)

Means the processor prevents instruction accesses. Any attempt to fetch an instruction from an XN region causes a memory management fault exception.

11.5.2 MEMORY SYSTEM ORDERING OF MEMORY ACCESSES

For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing this does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses completing in program order, software must insert a memory barrier instruction between the memory access instructions, see “Software ordering of memory accesses” on page 58. However, the memory system does guarantee some ordering of accesses to Device and Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs before A2 in program order, the ordering of the memory accesses caused by two instructions is: Where: - Means that the memory system does not guarantee the ordering of the accesses. < Means that accesses are observed in program order, that is, A1 is always observed before A2. Normal access Device access, non-shareable Device access, shareable Strongly-ordered access Normal access Non-shareable Shareable Strongly- ordered access Device access

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11.5.3 BEHAVIOR OF MEMORY ACCESSES

The behavior of accesses to each region in the memory map is: The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends that programs always use the Code region. This is because the processor has separate buses that enable instruction fetches and data accesses to occur simultaneously. The MPU can override the default memory access behavior described in this section. For more informa - tion, see “Memory Protection Unit” on page 140.

11.5.3.1 Additional Memory Access Constraints for Shared Memory

When a system includes shared memory, some memory regions have additional access constraints, and some regions are subdivided, as Table 11-5 shows: TABLE 11-4: MEMORY ACCESS BEHAVIOR Address range Memory region Memory type XN Description 0x00000000- 0x1FFFFFFF Code Normal (1) 1. See “Memory regions, types and attributes” on page 55 for more information. — Executable region for program code. You can also put data here. 0x20000000- 0x3FFFFFFF SRAM Normal(1) — Executable region for data. You can also put code here. This region includes bit band and bit band alias areas, see Table 11-6 on page 59. 0x40000000- 0x5FFFFFFF Peripheral Device(1) XN This region includes bit band and bit band alias areas, see Table 11-6 on page 59. 0x60000000- 0x9FFFFFFF External RAM Normal(1) — Executable region for data. 0xA0000000- 0xDFFFFFFF External device Device(1) XN External Device memory 0xE0000000- 0xE00FFFFF Private Peripheral Bus Strongly- ordered(1) XN This region includes the NVIC, System timer, and sys- tem control block. 0xE0100000- 0xFFFFFFFF Reserved Device(1) XN Reserved TABLE 11-5: MEMORY REGION SHARE ABILITY POLICIES Address range Memory region Memory type Shareability 0x00000000- 0x1FFFFFFF Code Normal (1) - 0x20000000- 0x3FFFFFFF SRAM Normal(1) - 0x40000000- 0x5FFFFFFF Peripheral (2) Device(1) - 0x60000000- 0x7FFFFFFF External RAM Normal(1) - WBWA(2) 0x80000000- 0x9FFFFFFF WT(2)

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11.5.4 SOFTWARE ORDERING OF MEMORY ACCESSES

The order of instructions in the program flow does not always guarantee the order of the corresponding memory trans- actions. This is because:

• The processor can reorder some memory accesses to improve efficiency, providing this does not affect the behav- ior of the instruction sequence.
• The processor has multiple bus interfaces
• Memory or devices in the memory map have different wait states
• Some memory accesses are buffered or speculative. “Memory system ordering of memory accesses” on page 56 describes the cases where the memory system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is critical, software must include memory barrier instructions to force that ordering. The processor provides the following memory barrier instructions:

11.5.4.1 DMB

The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent memory transactions. See “DMB” on page 110.

11.5.4.2 DSB

The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before subsequent instructions execute. See “DSB” on page 110.

11.5.4.3 ISB

The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory transactions is recogniz- able by subsequent instructions. See “ISB” on page 111. Use memory barrier instructions in, for example:

• MPU programming: - Use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of context switch- ing. - Use an ISB instruction to ensure the new MPU setting takes effect immediately after programming the MPU region or regions, if the MPU configuration code was accessed using a branch or call. If the MPU configura- tion code is entered using exception mechanisms, then an ISB instruction is not required.
• Vector table. If the program changes an entry in the vector table, and then enables the corresponding exception, use a DMB instruction between the operations. This ensures that if the exception is taken immediately after being enabled the processor uses the new exception vector.
• Self-modifying code. If a program contains self-modifying code, use an ISB instruction immediately after the code modification in the program. This ensures subsequent instruction execution uses the updated program.
• Memory map switching. If the system contains a memory map switching mechanism, use a DSB instruction after switching the memory map in the program. This ensures subsequent instruction execution uses the updated memory map.
• Dynamic exception priority change. When an exception priority has to change when the exception is pending or 0xA0000000- 0xBFFFFFFF External device Device(1) Shareable(1) - 0xC0000000- 0xDFFFFFFF Non- shareable(1) 0xE0000000- 0xE- 00FFFFF Private Peripheral Bus Strongly- ordered(1) Shareable(1) - 0xE0100000- 0xFFFFFFFF Vendor-specific device(2) Device(1) - - 1. See “Memory regions, types and attributes” on page 55 for more information. 2. The Peripheral and Vendor-specific device regions have no additional access constraints. TABLE 11-5: MEMORY REGION SHARE ABILITY POLICIES (CONTINUED) Address range Memory region Memory type Shareability

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• Using a semaphore in multi-master system. If the system contains more than one bus master, for example, if another processor is present in the system, each processor must use a DMB instruction after any semaphore instructions, to ensure other bus masters see the memory transactions in the order in which they were executed. Memory accesses to Strongly-ordered memory, such as the system control block, do not require the use of DMB instruc- tions.

11.5.5 BIT-BANDING

A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions occupy the lowest 1MB of the SRAM and peripheral memory regions. The memory map has two 32MB alias regions that map to two 1MB bit-band regions:

• Accesses to the 32MB SRAM alias region map to the 1MB SRAM bit-band region, as shown in Table 11-6
• Accesses to the 32MB peripheral alias region map to the 1MB peripheral bit-band region, as shown in Table 11-7. A word access to the SRAM or peripheral bit-band alias regions map to a single bit in the SRAM or peripheral bit-band region. The following formula shows how the alias region maps onto the bit-band region: bit_word_offset = (byte_offset x 32) + (bit_number x 4) bit_word_addr = bit_band_base + bit_word_offset where:
• Bit_word_offset is the position of the target bit in the bit-band memory region.
• Bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit.
• Bit_band_base is the starting address of the alias region.
• Byte_offset is the number of the byte in the bit-band region that contains the targeted bit.
• Bit_number is the bit position, 0-7, of the targeted bit. Figure 11-2 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bit-band region:
• The alias word at 0x23FFFFE0 maps to bit[0] of the bit-band byte at 0x200FFFFF: 0x23FFFFE0= 0x22000000 + (0xFFFFF*32) + (0*4). TABLE 11-6: SRAM MEMORY BIT-BANDING REGIONS Address range Memory region Instruction and data accesses 0x20000000- 0x200FFFFF SRAM bit-band region Direct accesses to this memory range behave as SRAM mem- ory accesses, but this region is also bit addressable through bit-band alias. 0x22000000- 0x23FFFFFF SRAM bit-band alias Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruc- tion accesses are not remapped. TABLE 11-7: PERIPHERAL MEMORY BIT-BANDING REGIONS Address range Memory region Instruction and data accesses 0x40000000- 0x400FFFFF Peripheral bit-band alias Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias. 0x42000000- 0x43FFFFFF Peripheral bit-band region Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruc- tion accesses are not permitted.

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• The alias word at 0x23FFFFFC maps to bit[7] of the bit-band byte at 0x200FFFFF: 0x23FFFFFC= 0x22000000 + (0xFFFFF*32) + (7*4).
• The alias word at 0x22000000 maps to bit[0] of the bit-band byte at 0x20000000: 0x22000000= 0x22000000 + (0*32) + (0 *4).
• The alias word at 0x2200001C maps to bit[7] of the bit-band byte at 0x20000000: 0x2200001C= 0x22000000+ (0*32) + (7*4). FIGURE 11-2: BIT-BAND MAPPING

11.5.5.1 Directly Accessing an Alias Region

Writing to a word in the alias region updates a single bit in the bit-band region. Bit[0] of the value written to a word in the alias region determines the value written to the targeted bit in the bit-band region. Writing a value with bit[0] set to 1 writes a 1 to the bit-band bit, and writing a value with bit[0] set to 0 writes a 0 to the bit-band bit. Bits[31:1] of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as writing 0xFF. Writing 0x00 has the same effect as writing 0x0E. Reading a word in the alias region:

• 0x00000000 indicates that the targeted bit in the bit-band region is set to zero
• 0x00000001 indicates that the targeted bit in the bit-band region is set to 1

11.5.5.2 Directly Accessing a Bit-band Region

“Behavior of memory accesses” on page 57 describes the behavior of direct byte, halfword, or word accesses to the bit- band regions.

11.5.6 MEMORY ENDIANNESS

The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. or “Little-endian Format” describes how words of data are stored in memory. 0x23FFFFE4 0x22000004 0x23FFFFE00x23FFFFE80x23FFFFEC0x23FFFFF00x23FFFFF40x23FFFFF80x23FFFFFC 0x220000000x220000140x220000180x2200001C 0x220000080x22000010 0x2200000C 32MB alias region 7 0 0x200000000x200000010x200000020x20000003 6 5 4 3 2 1 07 6 5 4 3 2 1 7 6 5 4 3 2 1 07 6 5 4 3 2 1 07 6 5 4 3 2 1 6 5 4 3 2 107 6 5 4 3 2 1 07 6 5 4 3 2 1 0x200FFFFC0x200FFFFD0x200FFFFE0x200FFFFF 1MB SRAM bit-band region

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11.5.6.1 Little-endian Format

In little-endian format, the processor stores the least significant byte of a word at the lowest-numbered byte, and the most significant byte at the highest-numbered byte. For example:

11.5.7 SYNCHRONIZATION PRIMITIVES

The Cortex-M3 instruction set includes pairs of synchronization primitives. These provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. Software can use them to perform a guaranteed read-modify-write memory update sequence, or for a semaphore mechanism. A pair of synchronization primitives comprises:

11.5.7.1 A Load-Exclusive Instruction

Used to read the value of a memory location, requesting exclusive access to that location.

11.5.7.2 A Store-Exclusive Instruction

Used to attempt to write to the same memory location, returning a status bit to a register. If this bit is: 0: It indicates that the thread or process gained exclusive access to the memory, and the write succeeds, 1: It indicates that the thread or process did not gain exclusive access to the memory, and no write is performed, The pairs of Load-Exclusive and Store-Exclusive instructions are:

• The word instructions LDREX and STREX
• The halfword instructions LDREXH and STREXH
• The byte instructions LDREXB and STREXB. Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction. To perform a guaranteed read-modify-write of a memory location, software must:
• Use a Load-Exclusive instruction to read the value of the location.
• Update the value, as required.
• Use a Store-Exclusive instruction to attempt to write the new value back to the memory location, and tests the returned status bit. If this bit is: - 0: The read-modify-write completed successfully, - 1: No write was performed. This indicates that the value returned the first step might be out of date. The soft- ware must retry the read-modify-write sequence, Software can use the synchronization primitives to implement a semaphores as follows:
• Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free.
• If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore address.
• If the returned status bit from the second step indicates that the Store-Exclusive succeeded then the software has claimed the semaphore. However, if the Store-Exclusive failed, another process might have claimed the sema- phore after the software performed the first step. The Cortex-M3 includes an exclusive access monitor, that tags the fact that the processor has executed a Load-Exclu- sive instruction. If the processor is part of a multiprocessor system, the system also globally tags the memory locations addressed by exclusive accesses by each processor. The processor removes its exclusive access tag if: Memory Register Address A A+1 lsbyte msbyte A+2 A+3 0 7 B0B1B3 B2 31 2423 1615 8 7 0

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• It executes a CLREX instruction
• It executes a Store-Exclusive instruction, regardless of whether the write succeeds.
• An exception occurs. This means the processor can resolve semaphore conflicts between different threads. In a multiprocessor implementation:
• Executing a CLREX instruction removes only the local exclusive access tag for the processor
• Executing a Store-Exclusive instruction, or an exception. removes the local exclusive access tags, and all global exclusive access tags for the processor. For more information about the synchronization primitive instructions, see “LDREX and STREX” on page 88 and “CLREX” on page 89.

11.5.8 PROGRAMMING HINTS FOR THE SYNCHRONIZATION PRIMITIVES

ANSI C cannot directly generate the exclusive access instructions. Some Ccompilers provide intrinsic functions for gen- eration of these instructions: The actual exclusive access instruction generated depends on the data type of the pointer passed to the intrinsic func- tion. For example, the following C code generates the require LDREXB operation: __ldrex((volatile char *) 0xFF);

11.6 Exception Model

This section describes the exception model.

11.6.1 EXCEPTION STATES

Each exception is in one of the following states:

11.6.1.1 Inactive

The exception is not active and not pending.

11.6.1.2 Pending

The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending.

11.6.1.3 Active

An exception that is being serviced by the processor but has not completed. An exception handler can interrupt the execution of another exception handler. In this case both exceptions are in the active state.

11.6.1.4 Active and Pending

The exception is being serviced by the processor and there is a pending exception from the same source.

11.6.2 EXCEPTION TYPES

The exception types are: TABLE 11-8: C COMPILER INTRINSIC FUNCTIONS FOR EXCLUSIVE ACCESS INSTRUCTIONS Instruction Intrinsic function LDREX, LDREXH, or LDREXB unsigned int __ldrex(volatile void *ptr) STREX, STREXH, or STREXB int __strex (unsigned int val, volatile void *ptr) CLREX void __clrex(void)

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11.6.2.1 Reset

Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deas - serted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privi - leged execution in Thread mode.

11.6.2.2 Non Maskable Interrupt (NMI)

A non maskable interrupt (NMI) can be signaled by a peripheral or triggered by software. This is the highest priority exception other than reset. It is permanently enabled and has a fixed priority of -2. NMIs cannot be:

• Masked or prevented from activation by any other exception.
• Preempted by any exception other than Reset.

11.6.2.3 Hard Fault

A hard fault is an exception that occurs because of an error during exception processing, or because an exception can- not be managed by any other exception mechanism. Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority.

11.6.2.4 Memory Management Fault

A memory management fault is an exception that occurs because of a memory protection related fault. The MPU or the fixed memory protection constraints determines this fault, for both instruction and data memory transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is disabled.

11.6.2.5 Bus Fault

A bus fault is an exception that occurs because of a memory related fault for an instruction or data memory transaction. This might be from an error detected on a bus in the memory system.

11.6.2.6 Usage Fault

A usage fault is an exception that occurs because of a fault related to instruction execution. This includes:

• An undefined instruction
• An illegal unaligned access
• Invalid state on instruction execution
• An error on exception return. The following can cause a usage fault when the core is configured to report them:
• An unaligned address on word and halfword memory access
• Division by zero

11.6.2.7 SVCall

A Supervisor Call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers.

11.6.2.8 PendSV

PendSV is an interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active.

11.6.2.9 SysTick

A SysTick exception is an exception the system timer generates when it reaches zero. Software can also generate a SysTick exception. In an OS environment, the processor can use this exception as system tick.

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11.6.2.10 Interrupt (IRQ)

A interrupt, or IRQ, is an exception signaled by a peripheral, or generated by a software request. All interrupts are asyn- chronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler. Privileged software can disable the exceptions that Table 11-9 shows as having configurable priority, see:

• “System Handler Control and State Register” on page 131
• “Interrupt Clear-enable Registers” on page 117. For more information about hard faults, memory management faults, bus faults, and usage faults, see “Fault Handling” on page 68.

11.6.3 EXCEPTION HANDLERS

The processor handles exceptions using:

11.6.3.1 Interrupt Service Routines (ISRs)

Interrupts IRQ0 to IRQ29 are the exceptions handled by ISRs.

11.6.3.2 Fault Handlers

Hard fault, memory management fault, usage fault, bus fault are fault exceptions handled by the fault handlers.

11.6.3.3 System Handlers

NMI, PendSV, SVCall SysTick, and the fault exceptions are all system exceptions that are handled by system handlers. TABLE 11-9: PROPERTIES OF THE DIFFERENT EXCEPTION TYPES Exception number (1) 1. To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions other than interrupts. The IPSR returns the Exception number, see “Interrupt Program Status Register” on page 51. IRQ number(1) Exception type Priority Vector address or offset (2) 2. See “Vector table” on page 65 for more information. Activation 1 - Reset -3, the highest 0x00000004 Asynchronous 2 -14 NMI -2 0x00000008 Asynchronous 3 -13 Hard fault -1 0x0000000C — 4 -12 Memory management fault Configurable (3) 3. See “System Handler Priority Registers” on page 130. 0x00000010 Synchronous 5 -11 Bus fault Configurable(3) 0x00000014 Synchronous when precise, asynchronous when imprecise 6 -10 Usage fault Configurable(3) 0x00000018 Synchronous 7-10 - — — Reserved — 11 -5 SVCall Configurable(3) 0x0000002C Synchronous 12-13 - — — Reserved — 14 -2 PendSV Configurable(3) 0x00000038 Asynchronous 15 -1 SysTick Configurable(3) 0x0000003C Asynchronous 16 and above 0 and above (4) 4. See the “Peripheral Identifiers” section of the datasheet. Interrupt (IRQ) Configurable (5) 5. See “Interrupt Priority Registers” on page 119. 0x00000040 and above (6) 6. Increasing in steps of 4. Asynchronous

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11.6.4 VECTOR TABLE

The vector table contains the reset value of the stack pointer, and the start addresses, also called exception vectors, for all exception handlers. Figure 11-3 shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code. FIGURE 11-3: VECTOR TABLE On system reset, the vector table is fixed at address 0x00000000. Privileged software can write to the VTOR to relocate the vector table start address to a different memory location, in the range 0x00000080 to 0x3FFFFF80, see “Vector Table Offset Register” on page 126.

11.6.5 EXCEPTION PRIORITIES

As Table 11-9 shows, all exceptions have an associated priority, with:

• A lower priority value indicating a higher priority
• Configurable priorities for all exceptions except Reset, Hard fault. If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. For infor- mation about configuring exception priorities see
• “System Handler Priority Registers” on page 130 Initial SP value Reset Hard fault Reserved Memory management fault Usage fault Bus fault 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 Reserved SVCall PendSV Reserved for Debug Systick IRQ0 Reserved 0x002C 0x0038 0x003C 0x0040 OffsetException number Vector IRQ1 IRQ2 0x0044 IRQ29 0x0048 0x004C 0x00B4 IRQ number -14 -13 -12 -11 -10

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• “Interrupt Priority Registers” on page 119. Configurable priority values are in the range 0-15. This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always have higher priority than any other exception. For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0]. If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1]. When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is not preempted, irre- spective of the exception number. However, the status of the new interrupt changes to pending.

11.6.6 INTERRUPT PRIORITY GROUPING

To increase priority control in systems with interrupts, the NVIC supports priority grouping. This divides each interrupt priority register entry into two fields:

• An upper field that defines the group priority
• A lower field that defines a subpriority within the group. Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler, If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first. For information about splitting the interrupt priority fields into group priority and subpriority, see “Application Interrupt and Reset Control Register” on page 127.

11.6.7 EXCEPTION ENTRY AND RETURN

Descriptions of exception handling use the following terms:

11.6.7.1 Preemption

When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. See “Interrupt priority grouping” on page 66 for more information about preemption by an interrupt. When one exception preempts another, the exceptions are called nested exceptions. See “Exception Entry” on page 67 more information.

11.6.7.2 Return

This occurs when the exception handler is completed, and:

• There is no pending exception with sufficient priority to be serviced
• The completed exception handler was not handling a late-arriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred. See “Exception Return” on page 67 for more information.

11.6.7.3 Tail-chaining

This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler.

11.6.7.4 Late-arriving

This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous excep - tion, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State saving is not affected by late arrival because the state saved is the same for both exceptions. Therefore the state saving

 2020 Microchip Technology Inc. DS60001614B-page 67 SAM3X8ERT continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. On return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply.

11.6.7.5 Exception Entry

Exception entry occurs when there is a pending exception with sufficient priority and either:

• The processor is in Thread mode
• The new exception is of higher priority than the exception being handled, in which case the new exception pre- empts the original exception. When one exception preempts another, the exceptions are nested. Sufficient priority means the exception has more priority than any limits set by the mask registers, see “Exception mask registers” on page 52. An exception with less priority than this is pending but is not handled by the processor. When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack. This operation is referred as stacking and the structure of eight data words is referred as stack frame. The stack frame contains the following information:
• R0-R3, R12
• Return address
• PSR
• LR. Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. Unless stack alignment is disabled, the stack frame is aligned to a double-word address. If the STKALIGN bit of the Configuration Control Register (CCR) is set to 1, stack align adjustment is performed during stacking. The stack frame includes the return address. This is the address of the next instruction in the interrupted program. This value is restored to the PC at exception return so that the interrupted program resumes. In parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler start address from the vector table. When stacking is complete, the processor starts executing the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR. This indicates which stack pointer corresponds to the stack frame and what operation mode the was processor was in before the entry occurred. If no higher priority exception occurs during exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active. If another higher priority exception occurs during exception entry, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. This is the late arrival case.

11.6.7.6 Exception Return

Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC:

• A POP instruction that includes the PC
• A BX instruction with any register.
• An LDR or LDM instruction with the PC as the destination. EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest four bits of this value provide information on the return stack and processor mode. Table 11-10 shows the EXC_RETURN[3:0] values with a description of the exception return behavior.

DS60001614B-page 68  2020 Microchip Technology Inc. The processor sets EXC_RETURN bits[31:4] to 0xFFFFFFF. When this value is loaded into the PC it indicates to the pro- cessor that the exception is complete, and the processor initiates the exception return sequence.

11.7 Fault Handling

Faults are a subset of the exceptions, see “Exception Model” on page 62. The following generate a fault: - A bus error on: - An instruction fetch or vector table load - A data access

• An internally-detected error such as an undefined instruction or an attempt to change state with a BX instruction
• Attempting to execute an instruction from a memory region marked as Non-Executable (XN).
• An MPU fault because of a privilege violation or an attempt to access an unmanaged region.

11.7.1 FAULT TYPES

Table 11-11 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the reg- ister bit that indicates that the fault has occurred. See “Configurable Fault Status Register” on page 133 for more infor- mation about the fault status registers. TABLE 11-10: EXCEPTION RETURN BEHAVIOR EXC_RETURN[3:0] Description bXXX0 Reserved. b0001 Return to Handler mode. Exception return gets state from MSP. Execution uses MSP after return. b0011 Reserved. b01X1 Reserved. b1001 Return to Thread mode. Exception return gets state from MSP. Execution uses MSP after return. b1101 Return to Thread mode. Exception return gets state from PSP . Execution uses PSP after return. b1X11 Reserved. TABLE 11-11: FAULTS Fault Handler Bit name Fault status register Bus error on a vector read Hard fault VECTTBL “Hard Fault Status Register” on page 136 Fault escalated to a hard fault FORCED MPU mismatch: Memory man- agement fault - - on instruction access IACCVIOL (1) “Memory Management Fault Address Register” on page 137on data access DACCVIOL during exception stacking MSTKERR during exception unstacking MUNSKERR Bus error: Bus fault - - during exception stacking STKERR “Bus Fault Status Register” on page 134 during exception unstacking UNSTKERR during instruction prefetch IBUSERR Precise data bus error PRECISERR Imprecise data bus error IMPRECISERR

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11.7.2 FAULT ESCALATION AND HARD FAULTS

All faults exceptions except for hard fault have configurable exception priority, see “System Handler Priority Registers” on page 130. Software can disable execution of the handlers for these faults, see “System Handler Control and State Register” on page 131. Usually, the exception priority, together with the values of the exception mask registers, determines whether the proces- sor enters the fault handler, and whether a fault handler can preempt another fault handler. as described in “Exception Model” on page 62. In some situations, a fault with configurable priority is treated as a hard fault. This is called priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault occurs when:

• A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault occurs because a fault handler cannot preempt itself because it must have the same priority as the current priority level.
• A fault handler causes a fault with the same or lower priority as the fault it is servicing. This is because the handler for the new fault cannot preempt the currently executing fault handler.
• An exception handler causes a fault for which the priority is the same as or lower than the currently executing exception.
• A fault occurs and the handler for that fault is not enabled. If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault. This means that if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler failed. The fault handler operates but the stack contents are corrupted. Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any exception other than Reset, NMI, or another hard fault.

11.7.3 FAULT STATUS REGISTERS AND FAULT ADDRESS REGISTERS

The fault status registers indicate the cause of a fault. For bus faults and memory management faults, the fault address register indicates the address accessed by the operation that caused the fault, as shown in Table 11-12. Attempt to access a coprocessor Usage fault NOCP “Usage Fault Status Register” on page 135 Undefined instruction UNDEFINSTR Attempt to enter an invalid instruction set state (2) INVSTATE Invalid EXC_RETURN value INVPC Illegal unaligned load or store UNALIGNED Divide By 0 DIVBYZERO 1. Occurs on an access to an XN region even if the MPU is disabled. 2. Attempting to use an instruction set other than the Thumb instruction set. TABLE 11-12: FAULT STATUS AND FAULT ADDRESS REGISTERS Handler Status register name Address register name Register description Hard fault HFSR — “Hard Fault Status Register” on page 136 Memory manage- ment fault MMFSR MMFAR “Memory Management Fault Status Register” on page 133 “Memory Management Fault Address Register” on page 137 Bus fault BFSR BFAR “Bus Fault Status Register” on page 134 “Bus Fault Address Register” on page 137 Usage fault UFSR — “Usage Fault Status Register” on page 135 TABLE 11-11: FAULTS (CONTINUED) Fault Handler Bit name Fault status register

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11.7.4 LOCKUP

The processor enters a lockup state if a hard fault occurs when executing the hard fault handlers. When the processor is in lockup state it does not execute any instructions. The processor remains in lockup state until:

• It is reset

11.8 Power Management

The Cortex-M3 processor sleep modes reduce power consumption:

• Backup Mode
• Wait Mode
• Sleep Mode The SLEEPDEEP bit of the SCR selects which sleep mode is used, see “System Control Register” on page 128 . For more information about the behavior of the sleep modes see “Low Power Modes” in the PMC section of the datasheet. This section describes the mechanisms for entering sleep mode, and the conditions for waking up from sleep mode.

11.8.1 ENTERING SLEEP MODE

This section describes the mechanisms software can use to put the processor into sleep mode. The system can generate spurious wakeup events, for example a debug operation wakes up the processor. Therefore software must be able to put the processor back into sleep mode after such an event. A program might have an idle loop to put the processor back to sleep mode.

11.8.1.1 Wait for Interrupt

The wait for interrup t instruction, WFI, causes immediate entry to sleep mode. When the processor executes a WFI instruction it stops executing instructions and enters sleep mode. See “WFI” on page 115 for more information.

11.8.1.2 Wait for Event

The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of an one-bit event register. When the processor executes a WFE instruction, it checks this register:

• If the register is 0 the processor stops executing instructions and enters sleep mode
• If the register is 1 the processor clears the register to 0 and continues executing instructions without entering sleep mode. See “WFE” on page 113 for more information.

11.8.1.3 Sleep-on-exit

If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the execution of an exception handler it returns to Thread mode and immediately enters sleep mode. Use this mechanism in applications that only require the processor to run when an exception occurs.

11.8.2 WAKEUP FROM SLEEP MODE

The conditions for the processor to wakeup depend on the mechanism that cause it to enter sleep mode.

11.8.2.1 Wakeup from WFI or sleep-on-exit

Normally, the processor wakes up only when it detects an exception with sufficient priority to cause exception entry. Some embedded systems might have to execute system restore tasks after the processor wakes up, and before it exe- cutes an interrupt handler. To achieve this set the PRIMASK bit to 1 and the FAULTMASK bit to 0. If an interrupt arrives that is enabled and has a higher priority than current exception priority, the processor wakes up but does not execute the interrupt handler until the processor sets PRIMASK to zero. For more information about PRIMASK and FAULTMASK see “Exception mask registers” on page 52.

11.8.2.2 Wakeup from WFE

The processor wakes up if:

• It detects an exception with sufficient priority to cause exception entry

 2020 Microchip Technology Inc. DS60001614B-page 71 SAM3X8ERT In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry. For more information about the SCR see “System Control Register” on page 128.

11.8.3 POWER MANAGEMENT PROGRAMMING HINTS

ANSI C cannot directly generate the WFI and WFE instructions. The CMSIS provides the following intrinsic functions for these instructions: void __WFE(void) // Wait for Event void __WFE(void) // Wait for Interrupt

11.9 Instruction Set Summary

The processor implements a version of the Thumb instruction set. Table 11-13 lists the supported instructions. In Table 11-13:

• Angle brackets, <>, enclose alternative forms of the operand
• Braces, {}, enclose optional operands
• The Operands column is not exhaustive
• Op2 is a flexible second operand that can be either a register or a constant
• Most instructions can use an optional condition code suffix. For more information on the instructions and operands, see the instruction descriptions. TABLE 11-13: CORTEX-M3 INSTRUCTIONS Mnemonic Operands Brief description Flags Page ADC, ADCS {Rd,} Rn, Op2 Add with Carry N,Z,C,V page 90 ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V page 90 ADD, ADDW {Rd,} Rn, #imm12 Add N,Z,C,V page 90 ADR Rd, label Load PC-relative address — page 81 AND, ANDS {Rd,} Rn, Op2 Logical AND N,Z,C page 92 ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic Shift Right N,Z,C page 93 B label Branch — page 104 BFC Rd, #lsb, #width Bit Field Clear — page 102 BFI Rd, Rn, #lsb, #width Bit Field Insert — page 102 BIC, BICS {Rd,} Rn, Op2 Bit Clear N,Z,C page 92 BKPT #imm Breakpoint — page 109 BL label Branch with Link — page 104 BLX Rm Branch indirect with Link — page 104 BX Rm Branch indirect — page 104 CBNZ Rn, label Compare and Branch if Non Zero — page 105 CBZ Rn, label Compare and Branch if Zero — page 105 CLREX — Clear Exclusive — page 89 CLZ Rd, Rm Count leading zeros — page 94 CMN, CMNS Rn, Op2 Compare Negative N,Z,C,V page 94 CMP , CMPS Rn, Op2 Compare N,Z,C,V page 94 CPSID iflags Change Processor State, Disable Interrupts — page 109 CPSIE iflags Change Processor State, Enable Interrupts — page 109 DMB — Data Memory Barrier — page 110 DSB — Data Synchronization Barrier — page 110 EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C page 92 ISB — Instruction Synchronization Barrier — page 111

DS60001614B-page 72  2020 Microchip Technology Inc. IT — If-Then condition block — page 106 LDM Rn{!}, reglist Load Multiple registers, increment after — page 86 LDMDB, LDMEA Rn{!}, reglist Load Multiple registers, decrement before — page 86 LDMFD, LDMIA Rn{!}, reglist Load Multiple registers, increment after — page 86 LDR Rt, [Rn, #offset] Load Register with word — page 83 LDRB, LDRBT Rt, [Rn, #offset] Load Register with byte — page 83 LDRD Rt, Rt2, [Rn, #off- set] Load Register with two bytes — page 83 LDREX Rt, [Rn, #offset] Load Register Exclusive — page 83 LDREXB Rt, [Rn] Load Register Exclusive with byte — page 83 LDREXH Rt, [Rn] Load Register Exclusive with halfword — page 83 LDRH, LDRHT Rt, [Rn, #offset] Load Register with halfword — page 83 LDRSB, LDRSBT Rt, [Rn, #offset] Load Register with signed byte — page 83 LDRSH, LDRSHT Rt, [Rn, #offset] Load Register with signed halfword — page 83 LDRT Rt, [Rn, #offset] Load Register with word — page 83 LSL, LSLS Rd, Rm, <Rs|#n> Logical Shift Left N,Z,C page 93 LSR, LSRS Rd, Rm, <Rs|#n> Logical Shift Right N,Z,C page 93 MLA Rd, Rn, Rm, Ra Multiply with Accumulate, 32-bit result — page 98 MLS Rd, Rn, Rm, Ra Multiply and Subtract, 32-bit result — page 98 MOV, MOVS Rd, Op2 Move N,Z,C page 95 MOVT Rd, #imm16 Move Top — page 96 MOVW, MOV Rd, #imm16 Move 16-bit constant N,Z,C page 95 MRS Rd, spec_reg Move from special register to general regis- ter — page 111 MSR spec_reg, Rm Move from general register to special regis- ter N,Z,C,V page 112 MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N,Z page 98 MVN, MVNS Rd, Op2 Move NOT N,Z,C page 95 NOP — No Operation — page 112 ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N,Z,C page 92 ORR, ORRS {Rd,} Rn, Op2 Logical OR N,Z,C page 92 POP reglist Pop registers from stack — page 87 PUSH reglist Push registers onto stack — page 87 RBIT Rd, Rn Reverse Bits — page 96 REV Rd, Rn Reverse byte order in a word — page 96 REV16 Rd, Rn Reverse byte order in each halfword — page 96 REVSH Rd, Rn Reverse byte order in bottom halfword and sign extend — page 96 ROR, RORS Rd, Rm, <Rs|#n> Rotate Right N,Z,C page 93 RRX, RRXS Rd, Rm Rotate Right with Extend N,Z,C page 93 TABLE 11-13: CORTEX-M3 INSTRUCTIONS (CONTINUED) Mnemonic Operands Brief description Flags Page

 2020 Microchip Technology Inc. DS60001614B-page 73 SAM3X8ERT RSB, RSBS {Rd,} Rn, Op2 Reverse Subtract N,Z,C,V page 90 SBC, SBCS {Rd,} Rn, Op2 Subtract with Carry N,Z,C,V page 90 SBFX Rd, Rn, #lsb, #width Signed Bit Field Extract — page 102 SDIV {Rd,} Rn, Rm Signed Divide — page 100 SEV — Send Event — page 113 SMLAL RdLo, RdHi, Rn, Rm Signed Multiply with Accumulate (32 x 32 + 64), 64-bit result — page 99 SMULL RdLo, RdHi, Rn, Rm Signed Multiply (32 x 32), 64-bit result — page 99 SSAT Rd, #n, Rm {,shift #s} Signed Saturate Q page 100 STM Rn{!}, reglist Store Multiple registers, increment after — page 86 STMDB, STMEA Rn{!}, reglist Store Multiple registers, decrement before — page 86 STMFD, STMIA Rn{!}, reglist Store Multiple registers, increment after — page 86 STR Rt, [Rn, #offset] Store Register word — page 83 STRB, STRBT Rt, [Rn, #offset] Store Register byte — page 83 STRD Rt, Rt2, [Rn, #off- set] Store Register two words — page 83 STREX Rd, Rt, [Rn, #offset] Store Register Exclusive — page 88 STREXB Rd, Rt, [Rn] Store Register Exclusive byte — page 88 STREXH Rd, Rt, [Rn] Store Register Exclusive halfword — page 88 STRH, STRHT Rt, [Rn, #offset] Store Register halfword — page 83 STRT Rt, [Rn, #offset] Store Register word — page 83 SUB, SUBS {Rd,} Rn, Op2 Subtract N,Z,C,V page 90 SUB, SUBW {Rd,} Rn, #imm12 Subtract N,Z,C,V page 90 SVC #imm Supervisor Call — page 113 SXTB {Rd,} Rm {,ROR #n} Sign extend a byte — page 103 SXTH {Rd,} Rm {,ROR #n} Sign extend a halfword — page 103 TBB [Rn, Rm] Table Branch Byte — page 108 TBH [Rn, Rm, LSL #1] Table Branch Halfword — page 108 TEQ Rn, Op2 Test Equivalence N,Z,C page 97 TST Rn, Op2 Test N,Z,C page 97 UBFX Rd, Rn, #lsb, #width Unsigned Bit Field Extract — page 102 UDIV {Rd,} Rn, Rm Unsigned Divide — page 100 UMLAL RdLo, RdHi, Rn, Rm Unsigned Multiply with Accumulate (32 x 32 + 64), 64-bit result — page 99 UMULL RdLo, RdHi, Rn, Rm Unsigned Multiply (32 x 32), 64-bit result — page 99 USAT Rd, #n, Rm {,shift #s} Unsigned Saturate Q page 100 UXTB {Rd,} Rm {,ROR #n} Zero extend a byte — page 103 TABLE 11-13: CORTEX-M3 INSTRUCTIONS (CONTINUED) Mnemonic Operands Brief description Flags Page

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11.10 Intrinsic Functions

ANSI cannot directly access some Cortex-M3 instructions. This section describes intrinsic functions that can generate these instructions, provided by the CMIS and that might be provided by a C compiler. If a C compiler does not support an appropriate intrinsic function, you might have to use inline assembler to access some instructions. The CMSIS provides the following intrinsic functions to generate instructions that ANSI cannot directly access: The CMSIS also provides a number of functions for accessing the special registers using MRS and MSR instructions UXTH {Rd,} Rm {,ROR #n} Zero extend a halfword — page 103 WFE — Wait For Event — page 113 WFI — Wait For Interrupt — page 115 TABLE 11-14: CMSIS INTRINSIC FUNCTIONS TO GENERATE SOME CORTEX-M3 INSTRUCTIONS Instruction CMSIS intrinsic function CPSIE I void __enable_irq(void) CPSID I void __disable_irq(void) CPSIE F void __enable_fault_irq(void) CPSID F void __disable_fault_irq(void) ISB void __ISB(void) DSB void __DSB(void) DMB void __DMB(void) REV uint32_t __REV(uint32_t int value) REV16 uint32_t __REV16(uint32_t int value) REVSH uint32_t __REVSH(uint32_t int value) RBIT uint32_t __RBIT(uint32_t int value) SEV void __SEV(void) WFE void __WFE(void) WFI void __WFI(void) TABLE 11-15: CMSIS INTRINSIC FUNCTIONS TO ACCESS THE SPECIAL REGISTERS Special register Access CMSIS function PRIMASK Read uint32_t __get_PRIMASK (void) Write void __set_PRIMASK (uint32_t value) FAULTMASK Read uint32_t __get_FAULTMASK (void) Write void __set_FAULTMASK (uint32_t value) BASEPRI Read uint32_t __get_BASEPRI (void) Write void __set_BASEPRI (uint32_t value) CONTROL Read uint32_t __get_CONTROL (void) Write void __set_CONTROL (uint32_t value) MSP Read uint32_t __get_MSP (void) Write void __set_MSP (uint32_t TopOfMainStack) PSP Read uint32_t __get_PSP (void) Write void __set_PSP (uint32_t TopOfProcStack) TABLE 11-13: CORTEX-M3 INSTRUCTIONS (CONTINUED) Mnemonic Operands Brief description Flags Page

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11.11 Instruction Descriptions

The following sections give more information about using the instructions:

• “Operands” on page 75
• “Restrictions when using PC or SP” on page 75
• “Flexible second operand” on page 75
• “Shift Operations” on page 76
• “Address alignment” on page 78
• “PC-relative expressions” on page 78
• “Conditional execution” on page 79
• “Instruction width selection” on page 80.

11.11.1 OPERANDS

An instruction operand can be an ARM register, a constant, or another instruction-specific parameter. Instructions act on the operands and often store the result in a destination register. When there is a destination register in the instruction, it is usually specified before the operands. Operands in some instructions are flexible in that they can either be a register or a constant. See “Flexible second oper- and” .

11.11.2 RESTRICTIONS WHEN USING PC OR SP

Many instructions have restrictions on whether you can use the Program Counter (PC) or Stack Pointer (SP) for the operands or destination register. See instruction descriptions for more information. Bit[0] of any address you write to the PC with a BX, BLX, LDM, LDR, or POP instruction must be 1 for correct execution, because this bit indicates the required instruction set, and the Cortex-M3 processor only supports Thumb instructions.

11.11.3 FLEXIBLE SECOND OPERAND

Many general data processing instructions have a flexible second operand. This is shown as Operand2 in the descrip- tions of the syntax of each instruction. Operand2 can be a:

• “Constant”
• “Register with Optional Shift” on page 76

11.11.3.1 Constant

You specify an Operand2 constant in the form: #constant where constant can be:

• Any constant that can be produced by shifting an 8-bit value left by any number of bits within a 32-bit word
• Any constant of the form 0x00XY00XY
• Any constant of the form 0xXY00XY00
• Any constant of the form 0xXYXYXYXY. In the constants shown above, X and Y are hexadecimal digits. In addition, in a small number of instructions, constant can take a wider range of values. These are described in the individual instruction descriptions. When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be produced by shift- ing an 8-bit value. These instructions do not affect the carry flag if Operand2 is any other constant.

11.11.3.2 Instruction Substitution

Your assembler might be able to produce an equivalent instruction in cases where you specify a constant that is not permitted. For example, an assembler might assemble the instruction CMP Rd, #0xFFFFFFFE as the equivalent instruction CMN Rd, #0x2.

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11.11.3.3 Register with Optional Shift

You specify an Operand2 register in the form: Rm {, shift} where:

• Rm is the register holding the data for the second operand.
• shift is an optional shift to be applied to Rm. It can be one of: - ASR #n arithmetic shift right n bits, 1  n  32. - LSL #n logical shift left n bits, 1  n  31. - LSR #n logical shift right n bits, 1  n  32. - ROR #n rotate right n bits, 1 n  31. - RRX rotate right one bit, with extend. - if omitted, no shift occurs, equivalent to LSL #0. If you omit the shift, or specify LSL #0, the instruction uses the value in Rm. If you specify a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is used by the instruction. However, the contents in the register Rm remains unchanged. Specifying a register with shift also updates the carry flag when used with certain instructions. For information on the shift operations and how they affect the carry flag, see “Shift Operations”

11.11.4 SHIFT OPERATIONS

Register shift operations move the bits in a register left or right by a specified number of bits, the shift length. Register shift can be performed:

• Directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the result is written to a destination register
• During the calculation of Operand2 by the instructions that specify the second operand as a register with shift, see “Flexible second operand” on page 75. The result is used by the instruction. The permitted shift lengths depend on the shift type and the instruction, see the individual instruction description or “Flexible second operand” on page 75. If the shift length is 0, no shift occurs. Register shift operations update the carry flag except when the specified shift length is 0. The following sub-sections describe the various shift operations and how they affect the carry flag. In these descriptions, Rm is the register containing the value to be shifted, and n is the shift length.

11.11.4.1 ASR

Arithmetic shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right- hand 32-n bits of the result. And it copies the original bit[31] of the register into the left -hand n bits of the result. See Figure 11-4. You can use the ASR #n operation to divide the value in the register Rm by 2n, with the result being rounded towards negative-infinity. When the instruction is ASRS or when ASR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the register Rm.

• If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.
• If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm. FIGURE 11-4: ASR #3 31 10 Carry Flag ... 2 34 5

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11.11.4.2 LSR

Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result. And it sets the left-hand n bits of the result to 0. See Figure 11-5. You can use the LSR #n operation to divide the value in the register Rm by 2n, if the value is regarded as an unsigned integer. When the instruction is LSRS or when LSR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the register Rm.

• If n is 32 or more, then all the bits in the result are cleared to 0.
• If n is 33 or more and the carry flag is updated, it is updated to 0. FIGURE 11-5: LSR #3

11.11.4.3 LSL

Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n places, into the left-hand 32- n bits of the result. And it sets the right-hand n bits of the result to 0. See Figure 11-6. You can use he LSL #n operation to multiply the value in the register Rm by 2n, if the value is regarded as an unsigned integer or a two’s complement signed integer. Overflow can occur without warning. When the instruction is LSLS or when LSL #n, with non-zero n, is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[32- n], of the register Rm. These instructions do not affect the carry flag when used with LSL #0.

• If n is 32 or more, then all the bits in the result are cleared to 0.
• If n is 33 or more and the carry flag is updated, it is updated to 0. FIGURE 11-6: LSL #3

11.11.4.4 ROR

Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result. And it moves the right-hand n bits of the register into the left-hand n bits of the result. See Figure 11-7. When the instruction is RORS or when ROR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit rotation, bit[n-1], of the register Rm.

• If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is updated, it is updated to bit[31] of Rm.
• ROR with shift length, n, more than 32 is the same as ROR with shift length n-32. 31 10 Carry Flag ... 000 2 3 4 5 31 10 Carry Flag ... 000 2 3 4 5

DS60001614B-page 78  2020 Microchip Technology Inc. FIGURE 11-7: ROR #3

11.11.4.5 RRX

Rotate right with extend moves the bits of the register Rm to the right by one bit. And it copies the carry flag into bit[31] of the result. See Figure 11-8. When the instruction is RRXS or when RRX is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[0] of the register Rm. FIGURE 11-8: RRX

11.11.5 ADDRESS ALIGNMENT

An aligned access is an operation where a word-aligned address is used for a word, dual word, or multiple word access, or where a halfword-aligned address is used for a halfword access. Byte accesses are always aligned. The Cortex-M3 processor supports unaligned access only for the following instructions:

• LDR, LDRT
• LDRH, LDRHT
• LDRSH, LDRSHT
• STR, STRT
• STRH, STRHT All other load and store instructions generate a usage fault exception if they perform an unaligned access, and therefore their accesses must be address aligned. For more information about usage faults see “Fault Handling” on page 68. Unaligned accesses are usually slower than aligned accesses. In addition, some memory regions might not support unaligned accesses. Therefore, ARM recommends that programmers ensure that accesses are aligned. To avoid acci- dental generation of unaligned accesses, use the UNALIGN_TRP bit in the Configuration and Control Register to trap all unaligned accesses, see “Configuration and Control Register” on page 129.

11.11.6 PC-RELATIVE EXPRESSIONS

A PC-relative expression or label is a symbol that represents the address of an instruction or literal data. It is represented in the instruction as the PC value plus or minus a numeric offset. The assembler calculates the required offset from the label and the address of the current instruction. If the offset is too big, the assembler produces an error.

• For B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current instruction plus 4 bytes.
• For all other instructions that use labels, the value of the PC is the address of the current instruction plus 4 bytes, with bit[1] of the result cleared to 0 to make it word-aligned.
• Your assembler might permit other syntaxes for PC-relative expressions, such as a label plus or minus a number, or an expression of the form [PC, #number]. 31 10 Carry Flag ... 2 3 4 5 31 30 1 0 Carry Flag

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11.11.7 CONDITIONAL EXECUTION

Most data processing instructions can optionally update the condition flags in the Application Program Status Register (APSR) according to the result of the operation, see “Application Program Status Register” on page 50. Some instruc- tions update all flags, and some only update a subset. If a flag is not updated, the original value is preserved. See the instruction descriptions for the flags they affect. You can execute an instruction conditionally, based on the condition flags set in another instruction, either:

• Immediately after the instruction that updated the flags
• After any number of intervening instructions that have not updated the flags. Conditional execution is available by using conditional branches or by adding condition code suffixes to instructions. See Table 11-16 for a list of the suffixes to add to instructions to make them conditional instructions. The condition code suffix enables the processor to test a condition based on the flags. If the condition test of a conditional instruction fails, the instruction:
• Does not execute
• Does not write any value to its destination register
• Does not affect any of the flags
• Does not generate any exception. Conditional instructions, except for conditional branches, must be inside an If-Then instruction block. See “IT” on page 106 for more information and restrictions when using the IT instruction. Depending on the vendor, the assembler might automatically insert an IT instruction if you have conditional instructions outside the IT block. Use the CBZ and CBNZ instructions to compare the value of a register against zero and branch on the result. This section describes:
• “The Condition Flags”
• “Condition Code Suffixes” .

11.11.7.1 The Condition Flags

The APSR contains the following condition flags:

• N: Set to 1 when the result of the operation was negative, cleared to 0 otherwise.
• Z: Set to 1 when the result of the operation was zero, cleared to 0 otherwise.
• C: Set to 1 when the operation resulted in a carry, cleared to 0 otherwise.
• V: Set to 1 when the operation caused overflow, cleared to 0 otherwise. For more information about the APSR see “Program Status Register” on page 49. A carry occurs:
• If the result of an addition is greater than or equal to 232
• If the result of a subtraction is positive or zero
• As the result of an inline barrel shifter operation in a move or logical instruction. Overflow occurs if the result of an add, subtract, or compare is greater than or equal to 231, or less than –231. Most instructions update the status flags only if the S suffix is specified. See the instruction descriptions for more infor- mation.

11.11.7.2 Condition Code Suffixes

The instructions that can be conditional have an optional condition code, shown in syntax descriptions as {cond}. Con- ditional execution requires a preceding IT instruction. An instruction with a condition code is only executed if the condi- tion code flags in the APSR meet the specified condition. Table 11-16 shows the condition codes to use. You can use conditional execution with the IT instruction to reduce the number of branch instructions in code.

DS60001614B-page 80  2020 Microchip Technology Inc. Table 11-16 also shows the relationship between condition code suffixes and the N, Z, C, and V flags.

11.11.7.3 Absolute Value

The example below shows the use of a conditional instruction to find the absolute value of a number. R0 = ABS(R1). MOVS R0, R1 ; R0 = R1, setting flags IT MI ; IT instruction for the negative condition RSBMI R0, R1, #0 ; If negative, R0 = -R1

11.11.7.4 Compare and Update Value

The example below shows the use of conditional instructions to update the value of R4 if the signed values R0 is greater than R1 and R2 is greater than R3. CMP R0, R1 ; Compare R0 and R1, setting flags ITT GT ; IT instruction for the two GT conditions CMPGT R2, R3 ; If 'greater than', compare R2 and R3, setting flags MOVGT R4, R5 ; If still 'greater than', do R4 = R5

11.11.8 INSTRUCTION WIDTH SELECTION

There are many instructions that can generate either a 16-bit encoding or a 32-bit encoding depending on the operands and destination register specified. For some of these instructions, you can force a specific instruction size by using an instruction width suffix. The.W suffix forces a 32-bit instruction encoding. The.N suffix forces a 16-bit instruction encod- ing. If you specify an instruction width suffix and the assembler cannot generate an instruction encoding of the requested width, it generates an error. In some cases it might be necessary to specify the .W suffix, for example if the operand is the label of an instruction or literal data, as in the case of branch instructions. This is because the assembler might not automatically generate the right size encoding.

11.11.8.1 Instruction Width Selection

To use an instruction width suffix, place it immediately after the instruction mnemonic and condition code, if any. The example below shows instructions with the instruction width suffix. BCS.W label ; creates a 32-bit instruction even for a short branch TABLE 11-16: CONDITION CODE SUFFIXES Suffix Flags Meaning EQ Z = 1 Equal NE Z = 0 Not equal CS or HS C = 1 Higher or same, unsigned  CC or LO C = 0 Lower, unsigned < MI N = 1 Negative PL N = 0 Positive or zero VS V = 1 Overflow VC V = 0 No overflow HI C = 1 and Z = 0 Higher, unsigned > LS C = 0 or Z = 1 Lower or same, unsigned  GE N = V Greater than or equal, signed  LT N = V Less than, signed < GT Z = 0 and N = V Greater than, signed > LE Z = 1 and N  V Less than or equal, signed  AL Can have any value Always. This is the default when no suffix is speci- fied.

 2020 Microchip Technology Inc. DS60001614B-page 81 SAM3X8ERT ADDS.W R0, R0, R1 ; creates a 32-bit instruction even though the same ; operation can be done by a 16-bit instruction

11.12 Memory Access Instructions

Table 11-17 shows the memory access instructions:

11.12.1 ADR

Load PC-relative address.

11.12.1.1 Syntax

ADR{cond} Rd, label where:

• cond is an optional condition code, see “Conditional execution” on page 79.
• Rd is the destination register.
• label is a PC-relative expression. See “PC-relative expressions” on page 78.

11.12.1.2 Operation

ADR determines the address by adding an immediate value to the PC, and writes the result to the destination register. ADR produces position-independent code, because the address is PC-relative. If you use ADR to generate a target address for a BX or BLX instruction, you must ensure that bit[0] of the address you generate is set to1 for correct execution. Values of label must be within the range of 4095 to +4095 from the address in the PC. You might have to use the.W suffix to get the maximum offset range or to generate addresses that are not word-aligned. See “Instruction width selection” on page 80.

11.12.1.3 Restrictions

Rd must not be SP and must not be PC.

11.12.1.4 Condition Flags

This instruction does not change the flags. TABLE 11-17: MEMORY ACCESS INSTRUCTIONS Mnemonic Brief description See ADR Load PC-relative address “ADR” on page 81 CLREX Clear Exclusive “CLREX” on page 89 LDM{mode} Load Multiple registers “LDM and STM” on page 86 LDR{type} Load Register using immediate offset “LDR and STR, immediate offset” on page 82 LDR{type} Load Register using register offset “LDR and STR, register offset” on page 83 LDR{type}T Load Register with unprivileged access “LDR and STR, unprivileged” on page 84 LDR Load Register using PC-relative address “LDR, PC-relative” on page 85 LDREX{type} Load Register Exclusive “LDREX and STREX” on page 88 POP Pop registers from stack “PUSH and POP” on page 87 PUSH Push registers onto stack “PUSH and POP” on page 87 STM{mode} Store Multiple registers “LDM and STM” on page 86 STR{type} Store Register using immediate offset “LDR and STR, immediate offset” on page 82 STR{type} Store Register using register offset “LDR and STR, register offset” on page 83 STR{type}T Store Register with unprivileged access “LDR and STR, unprivileged” on page 84 STREX{type} Store Register Exclusive “LDREX and STREX” on page 88

DS60001614B-page 82  2020 Microchip Technology Inc.

11.12.1.5 Examples

ADR R1, TextMessage ; Write address value of a location labelled as ; TextMessage to R1

11.12.2 LDR AND STR, IMMEDIATE OFFSET

Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset.

11.12.2.1 Syntax

op{type}{cond} Rt, [Rn {, #offset}] ; immediate offset op{type}{cond} Rt, [Rn, #offset]! ; pre-indexed op{type}{cond} Rt, [Rn], #offset ; post-indexed opD{cond} Rt, Rt2, [Rn {, #offset}] ; immediate offset, two words opD{cond} Rt, Rt2, [Rn, #offset]! ; pre-indexed, two words opD{cond} Rt, Rt2, [Rn], #offset ; post-indexed, two words where:

• op is one of:
• LDR: Load Register.
• STR: Store Register.
• Type is one of: - B: unsigned byte, zero extend to 32 bits on loads. - SB: signed byte, sign extend to 32 bits (LDR only). - H: unsigned halfword, zero extend to 32 bits on loads. - SH: signed halfword, sign extend to 32 bits (LDR only). omit, for word.
• cond is an optional condition code, see “Conditional execution” on page 79.
• Rt is the register to load or store.
• Rn is the register on which the memory address is based.
• offset is an offset from Rn. If offset is omitted, the address is the contents of Rn.
• Rt2 is the additional register to load or store for two-word operations.

11.12.2.2 Operation

LDR instructions load one or two registers with a value from memory. STR instructions store one or two register values to memory. Load and store instructions with immediate offset can use the following addressing modes:

11.12.2.3 Offset Addressing

The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access. The register Rn is unaltered. The assembly language syntax for this mode is: [Rn, #offset]

11.12.2.4 Pre-indexed Addressing

The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access and written back into the register Rn. The assembly language syntax for this mode is: [Rn, #offset]!

11.12.2.5 Post-indexed Addressing

The address obtained from the register Rn is used as the address for the memory access. The offset value is added to or subtracted from the address, and written back into the register Rn. The assembly language syntax for this mode is: [Rn], #offset The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either be signed or unsigned. See “Address alignment” on page 78.

 2020 Microchip Technology Inc. DS60001614B-page 83 SAM3X8ERT Table 11-18 shows the ranges of offset for immediate, pre-indexed and post-indexed forms.

11.12.2.6 Restrictions

For load instructions:

• Rt can be SP or PC for word loads only
• Rt must be different from Rt2 for two-word loads
• Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms. When Rt is PC in a word load instruction:
• Bit[0] of the loaded value must be 1 for correct execution
• A branch occurs to the address created by changing bit[0] of the loaded value to 0
• If the instruction is conditional, it must be the last instruction in the IT block. For store instructions:
• Rt can be SP for word stores only
• Rt must not be PC
• Rn must not be PC
• Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.

11.12.2.7 Condition Flags

These instructions do not change the flags.

11.12.2.8 Examples

LDR R8, [R10] ; Loads R8 from the address in R10. LDRNE R2, [R5, #960]! ; Loads (conditionally) R2 from a word ; 960 bytes above the address in R5, and ; increments R5 by 960. STR R2, [R9,#const-struc] ; const-struc is an expression evaluating ; to a constant in the range 0-4095. STRH R3, [R4], #4 ; Store R3 as halfword data into address in ; R4, then increment R4 by 4 LDRD R8, R9, [R3, #0x20] ; Load R8 from a word 32 bytes above the ; address in R3, and load R9 from a word 36 ; bytes above the address in R3 STRD R0, R1, [R8], #-16 ; Store R0 to address in R8, and store R1 to ; a word 4 bytes above the address in R8, ; and then decrement R8 by 16.

11.12.3 LDR AND STR, REGISTER OFFSET

Load and Store with register offset.

11.12.3.1 Syntax

op{type}{cond} Rt, [Rn, Rm {, LSL #n}] where:

• op is one of: - LDR: Load Register. - STR: Store Register. TABLE 11-18: OFFSET RANGES Instruction type Immediate offset Pre-indexed Post-indexed Word, halfword, signed halfword, byte, or signed byte 255 to 4095 255 to 255 255 to 255 Two words multiple of 4 in the range  1020 to 1020 multiple of 4 in the range  1020 to 1020 multiple of 4 in the range  1020 to 1020

DS60001614B-page 84  2020 Microchip Technology Inc.

• Type is one of: - B: unsigned byte, zero extend to 32 bits on loads. - SB: signed byte, sign extend to 32 bits (LDR only). - H: unsigned halfword, zero extend to 32 bits on loads. - SH: signed halfword, sign extend to 32 bits (LDR only). omit, for word.
• cond is an optional condition code, see “Conditional execution” on page 79.
• Rt is the register to load or store.
• Rn is the register on which the memory address is based.
• Rm is a register containing a value to be used as the offset.
• LSL #n is an optional shift, with n in the range 0 to 3.

11.12.3.2 Operation

LDR instructions load a register with a value from memory. STR instructions store a register value into memory. The memory address to load from or store to is at an offset from the register Rn. The offset is specified by the register Rm and can be shifted left by up to 3 bits using LSL. The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either be signed or unsigned. See “Address alignment” on page 78.

11.12.3.3 Restrictions

In these instructions:

• Rn must not be PC
• Rm must not be SP and must not be PC
• Rt can be SP only for word loads and word stores
• Rt can be PC only for word loads. When Rt is PC in a word load instruction:
• Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address
• If the instruction is conditional, it must be the last instruction in the IT block.

11.12.3.4 Condition Flags

These instructions do not change the flags.

11.12.3.5 Examples

STR R0, [R5, R1] ; Store value of R0 into an address equal to ; sum of R5 and R1 LDRSB R0, [R5, R1, LSL #1] ; Read byte value from an address equal to ; sum of R5 and two times R1, sign extended it ; to a word value and put it in R0 STR R0, [R1, R2, LSL #2] ; Stores R0 to an address equal to sum of R1 ; and four times R2

11.12.4 LDR AND STR, UNPRIVILEGED

Load and Store with unprivileged access.

11.12.4.1 Syntax

op{type}T{cond} Rt, [Rn {, #offset}] ; immediate offset where:

• op is one of: - LDR: Load Register. - STR: Store Register.
• Type is one of: - B: unsigned byte, zero extend to 32 bits on loads.

 2020 Microchip Technology Inc. DS60001614B-page 85 SAM3X8ERT - SB: signed byte, sign extend to 32 bits (LDR only). - H: unsigned halfword, zero extend to 32 bits on loads. - SH: signed halfword, sign extend to 32 bits (LDR only). omit, for word.

• cond is an optional condition code, see “Conditional execution” on page 79.
• Rt is the register to load or store.
• Rn is the register on which the memory address is based.
• offset is an offset from Rn and can be 0 to 255. - If offset is omitted, the address is the value in Rn.

11.12.4.2 Operation

These load and store instructions perform the same function as the memory access instructions with immediate offset, see “LDR and STR, immediate offset” on page 82 . The difference is that these instructions have only unprivileged access even when used in privileged software. When used in unprivileged software, these instructions behave in exactly the same way as normal memory access instructions with immediate offset.

11.12.4.3 Restrictions

In these instructions:

• Rn must not be PC
• Rt must not be SP and must not be PC.

11.12.4.4 Condition flags

These instructions do not change the flags.

11.12.4.5 Examples

STRBTEQ R4, [R7] ; Conditionally store least significant byte in ; R4 to an address in R7, with unprivileged access LDRHT R2, [R2, #8] ; Load halfword value from an address equal to ; sum of R2 and 8 into R2, with unprivileged access

11.12.5 LDR, PC-RELATIVE

Load register from memory.

11.12.5.1 Syntax

LDR{type}{cond} Rt, label LDRD{cond} Rt, Rt2, label ; Load two words where:

• Type is one of: - B: unsigned byte, zero extend to 32 bits - SB: signed byte, sign extend to 32 bits - H: unsigned halfword, zero extend to 32 bits - SH: signed halfword, sign extend to 32 bits a) omit, for word
• cond is an optional condition code, see “Conditional execution” on page 79
• Rt is the register to load or store
• Rt2 is the second register to load or store
• label is a PC-relative expression. See “PC-relative expressions” on page 78

11.12.5.2 Operation

LDR loads a register with a value from a PC-relative memory address. The memory address is specified by a label or by an offset from the PC. The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either be signed or unsigned. See “Address alignment” on page 78.

DS60001614B-page 86  2020 Microchip Technology Inc. label must be within a limited range of the current instruction. Table 11-19 shows the possible offsets between label and the PC. You might have to use the .W suffix to get the maximum offset range. See “Instruction width selection” on page 80.

11.12.5.3 Restrictions

In these instructions:

• Rt can be SP or PC only for word loads
• Rt2 must not be SP and must not be PC
• Rt must be different from Rt2. When Rt is PC in a word load instruction:
• Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address
• If the instruction is conditional, it must be the last instruction in the IT block.

11.12.5.4 Condition Flags

These instructions do not change the flags.

11.12.5.5 Examples

LDR R0, LookUpTable ; Load R0 with a word of data from an address ; labelled as LookUpTable LDRSB R7, localdata ; Load a byte value from an address labelled ; as localdata, sign extend it to a word ; value, and put it in R7

11.12.6 LDM AND STM

Load and Store Multiple registers.

11.12.6.1 Syntax

where:

• op is one of: - LDM: Load Multiple registers. - STM: Store Multiple registers.
• addr_mode is any one of the following: - IA: Increment address After each access. This is the default. - DB: Decrement address Before each access.
• cond is an optional condition code, see “Conditional execution” on page 79.
• Rn is the register on which the memory addresses are based.
• ! is an optional writeback suffix. - If ! is present the final address, that is loaded from or stored to, is written back into Rn.
• reglist is a list of one or more registers to be loaded or stored, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range, see “Examples” on page 87. LDM and LDMFD are synonyms for LDMIA. LDMFD refers to its use for popping data from Full Descending stacks. LDMEA is a synonym for LDMDB, and refers to its use for popping data from Empty Ascending stacks. TABLE 11-19: OFFSET RANGES Instruction type Offset range Word, halfword, signed halfword, byte, signed byte 4095 to 4095 Two words 1020 to 1020

 2020 Microchip Technology Inc. DS60001614B-page 87 SAM3X8ERT STM and STMEA are synonyms for STMIA. STMEA refers to its use for pushing data onto Empty Ascending stacks. STMFD is s synonym for STMDB, and refers to its use for pushing data onto Full Descending stacks

11.12.6.2 Operation

LDM instructions load the registers in reglist with word values from memory addresses based on Rn. STM instructions store the word values in the registers in reglist to memory addresses based on Rn. For LDM, LDMIA, LDMFD, STM, STMIA, and STMEA the memory addresses used for the accesses are at 4-byte inter- vals ranging from Rn to Rn + 4 * (n-1), where n is the number of registers in reglist. The accesses happens in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest num- ber register using the highest memory address. If the writeback suffix is specified, the value of Rn + 4 * (n-1) is written back to Rn. For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn - 4 * ( n-1), where n is the number of registers in reglist. The accesses happen in order of decreasing register numbers, with the highest numbered register using the highest memory address and the lowest number register using the lowest memory address. If the writeback suffix is specified, the value of Rn - 4 * (n-1) is written back to Rn. The PUSH and POP instructions can be expressed in this form. See “PUSH and POP” on page 87 for details.

11.12.6.3 Restrictions

In these instructions:

• Rn must not be PC
• reglist must not contain SP
• in any STM instruction, reglist must not contain PC
• in any LDM instruction, reglist must not contain PC if it contains LR
• reglist must not contain Rn if you specify the writeback suffix. When PC is in reglist in an LDM instruction:
• Bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfword-aligned address
• If the instruction is conditional, it must be the last instruction in the IT block.

11.12.6.4 Condition Flags

These instructions do not change the flags.

11.12.6.5 Examples

LDM R8,{R0,R2,R9} ; LDMIA is a synonym for LDM STMDB R1!,{R3-R6,R11,R12}

11.12.6.6 Incorrect examples

STM R5!,{R5,R4,R9} ; Value stored for R5 is unpredictable LDM R2, {} ; There must be at least one register in the list

11.12.7 PUSH AND POP

Push registers onto, and pop registers off a full-descending stack.

11.12.7.1 Syntax

PUSH{cond} reglist POP{cond} reglist where:

• cond is an optional condition code, see “Conditional execution” on page 79.
• reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges. It must be comma sepa- rated if it contains more than one register or register range.

DS60001614B-page 88  2020 Microchip Technology Inc. PUSH and POP are synonyms for STMDB and LDM (or LDMIA) with the memory addresses for the access based on SP , and with the final address for the access written back to the SP . PUSH and POP are the preferred mnemonics in these cases.

11.12.7.2 Operation

PUSH stores registers on the stack in order of decreasing the register numbers, with the highest numbered register using the highest memory address and the lowest numbered register using the lowest memory address. POP loads registers from the stack in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest numbered register using the highest memory address. See “LDM and STM” on page 86 for more information.

11.12.7.3 Restrictions

In these instructions:

• reglist must not contain SP
• For the PUSH instruction, reglist must not contain PC
• For the POP instruction, reglist must not contain PC if it contains LR When PC is in reglist in a POP instruction:
• Bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfword-aligned address
• If the instruction is conditional, it must be the last instruction in the IT block.

11.12.7.4 Condition Flags

These instructions do not change the flags.

11.12.7.5 Examples

PUSH {R0,R4-R7} PUSH {R2,LR} POP {R0,R10,PC}

11.12.8 LDREX AND STREX

Load and Store Register Exclusive.

11.12.8.1 Syntax

LDREX{cond} Rt, [Rn {, #offset}] STREX{cond} Rd, Rt, [Rn {, #offset}] LDREXB{cond} Rt, [Rn] STREXB{cond} Rd, Rt, [Rn] LDREXH{cond} Rt, [Rn] STREXH{cond} Rd, Rt, [Rn] where:

• cond is an optional condition code, see “Conditional execution” on page 79.
• Rd is the destination register for the returned status.
• Rt is the register to load or store.
• Rn is the register on which the memory address is based.
• offset is an optional offset applied to the value in Rn. - If offset is omitted, the address is the value in Rn.

11.12.8.2 Operation

LDREX, LDREXB, and LDREXH load a word, byte, and halfword respectively from a memory address. STREX, STREXB, and STREXH attempt to store a word, byte, and halfword respectively to a memory address. The address used in any Store-Exclusive instruction must be the same as the address in the most recently executed Load- exclusive instruction. The value stored by the Store-Exclusive instruction must also have the same data size as the value

 2020 Microchip Technology Inc. DS60001614B-page 89 SAM3X8ERT loaded by the preceding Load-exclusive instruction. This means software must always use a Load-exclusive instruction and a matching Store-Exclusive instruction to perform a synchronization operation, see “Synchronization primitives” on page 61 If an Store-Exclusive instruction performs the store, it writes 0 to its destination register. If it does not perform the store, it writes 1 to its destination register. If the Store-Exclusive instruction writes 0 to the destination register, it is guaranteed that no other process in the system has accessed the memory location between the Load-exclusive and Store-Exclusive instructions. For reasons of performance, keep the number of instructions between corresponding Load-Exclusive and Store-Exclu- sive instruction to a minimum. The result of executing a Store-Exclusive instruction to an address that is different from that used in the preceding Load- Exclusive instruction is unpredictable.

11.12.8.3 Restrictions

In these instructions:

• Do not use PC
• Do not use SP for Rd and Rt
• For STREX, Rd must be different from both Rt and Rn
• The value of offset must be a multiple of four in the range 0-1020

11.12.8.4 Condition Flags

These instructions do not change the flags.

11.12.8.5 Examples

MOV R1, #0x1 ; Initialize the ‘lock taken’ value try LDREX R0, [LockAddr] ; Load the lock value CMP R0, #0 ; Is the lock free? ITT EQ ; IT instruction for STREXEQ and CMPEQ STREXEQ R0, R1, [LockAddr] ; Try and claim the lock CMPEQ R0, #0 ; Did this succeed? BNE try ; No – try again .... ; Yes – we have the lock

11.12.9 CLREX

Clear Exclusive.

11.12.9.1 Syntax

CLREX{cond} where:

• cond is an optional condition code, see “Conditional execution” on page 79. Operation Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination register and fail to perform the store. It is useful in exception handler code to force the failure of the store exclusive if the exception occurs between a load exclusive instruction and the matching store exclusive instruction in a synchronization operation. See “Synchronization primitives” on page 61 for more information.

11.12.9.2 Condition Flags

These instructions do not change the flags.

11.12.9.3 Examples

DS60001614B-page 90  2020 Microchip Technology Inc.

11.13 General Data Processing Instructions

Table 11-20 shows the data processing instructions:

11.13.1 ADD, ADC, SUB, SBC, AND RSB

Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.

11.13.1.1 Syntax

op{S}{cond} {Rd,} Rn, Operand2 op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only where:

• op is one of: - ADD: Add. - ADC: Add with Carry. - SUB: Subtract. TABLE 11-20: DATA PROCESSING INSTRUCTIONS Mnemonic Brief description See ADC Add with Carry “ADD, ADC, SUB, SBC, and RSB” on page 90 ADD Add “ADD, ADC, SUB, SBC, and RSB” on page 90 ADDW Add “ADD, ADC, SUB, SBC, and RSB” on page 90 AND Logical AND “AND, ORR, EOR, BIC, and ORN” on page 92 ASR Arithmetic Shift Right “ASR, LSL, LSR, ROR, and RRX” on page 93 BIC Bit Clear “AND, ORR, EOR, BIC, and ORN” on page 92 CLZ Count leading zeros “CLZ” on page 94 CMN Compare Negative “CMP and CMN” on page 94 CMP Compare “CMP and CMN” on page 94 EOR Exclusive OR “AND, ORR, EOR, BIC, and ORN” on page 92 LSL Logical Shift Left “ASR, LSL, LSR, ROR, and RRX” on page 93 LSR Logical Shift Right “ASR, LSL, LSR, ROR, and RRX” on page 93 MOV Move “MOV and MVN” on page 95 MOVT Move Top “MOVT” on page 96 MOVW Move 16-bit constant “MOV and MVN” on page 95 MVN Move NOT “MOV and MVN” on page 95 ORN Logical OR NOT “AND, ORR, EOR, BIC, and ORN” on page 92 ORR Logical OR “AND, ORR, EOR, BIC, and ORN” on page 92 RBIT Reverse Bits “REV, REV16, REVSH, and RBIT” on page 96 REV Reverse byte order in a word “REV, REV16, REVSH, and RBIT” on page 96 REV16 Reverse byte order in each halfword “REV, REV16, REVSH, and RBIT” on page 96 REVSH Reverse byte order in bottom half- word and sign extend “REV, REV16, REVSH, and RBIT” on page 96 ROR Rotate Right “ASR, LSL, LSR, ROR, and RRX” on page 93 RRX Rotate Right with Extend “ASR, LSL, LSR, ROR, and RRX” on page 93 RSB Reverse Subtract “ADD, ADC, SUB, SBC, and RSB” on page 90 SBC Subtract with Carry “ADD, ADC, SUB, SBC, and RSB” on page 90 SUB Subtract “ADD, ADC, SUB, SBC, and RSB” on page 90 SUBW Subtract “ADD, ADC, SUB, SBC, and RSB” on page 90 TEQ Test Equivalence “TST and TEQ” on page 97 TST Test “TST and TEQ” on page 97

 2020 Microchip Technology Inc. DS60001614B-page 91 SAM3X8ERT - SBC: Subtract with Carry. - RSB: Reverse Subtract.

• S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional execution” on page 79.
• cond is an optional condition code, see “Conditional execution” on page 79.
• Rd is the destination register. If Rd is omitted, the destination register is Rn.
• Rn is the register holding the first operand.
• Operand2 is a flexible second operand. See “Flexible second operand” on page 75 for details of the options.
• imm12 is any value in the range 0-4095.

11.13.1.2 Operation

The ADD instruction adds the value of Operand2 or imm12 to the value in Rn. The ADC instruction adds the values in Rn and Operand2, together with the carry flag. The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn. The SBC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is clear, the result is reduced by one. The RSB instruction subtracts the value in Rn from the value of Operand2. This is useful because of the wide range of options for Operand2. Use ADC and SBC to synthesize multiword arithmetic, see “Multiword Arithmetic Examples” on page 92. See also “ADR” on page 81. ADDW is equivalent to the ADD syntax that uses the imm12 operand. SUBW is equivalent to the SUB syntax that uses the imm12 operand.

11.13.1.3 Restrictions

In these instructions:

• Operand2 must not be SP and must not be PC
• Rd can be SP only in ADD and SUB, and only with the additional restrictions: - Rn must also be SP - any shift in Operand2 must be limited to a maximum of 3 bits using LSL
• Rn can be SP only in ADD and SUB
• Rd can be PC only in the ADD{cond} PC, PC, Rm instruction where: - you must not specify the S suffix - Rm must not be PC and must not be SP - if the instruction is conditional, it must be the last instruction in the IT block
• with the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and SUB, and only with the additional restrictions: - you must not specify the S suffix - the second operand must be a constant in the range 0 to 4095. - When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to b00 before performing the calculation, making the base address for the calculation word-aligned. - If you want to generate the address of an instruction, you have to adjust the constant based on the value of the PC. ARM recommends that you use the ADR instruction instead of ADD or SUB with Rn equal to the PC, because your assembler automatically calculates the correct constant for the ADR instruction. When Rd is PC in the ADD{cond} PC, PC, Rm instruction:
• Bit[0] of the value written to the PC is ignored
• A branch occurs to the address created by forcing bit[0] of that value to 0.

11.13.1.4 Condition Flags

If S is specified, these instructions update the N, Z, C and V flags according to the result.

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11.13.1.5 Examples

ADD R2, R1, R3 SUBS R8, R6, #240 ; Sets the flags on the result RSB R4, R4, #1280 ; Subtracts contents of R4 from 1280 ADCHI R11, R0, R3 ; Only executed if C flag set and Z ; flag clear

11.13.1.6 Multiword Arithmetic Examples

11.13.1.7 64-bit Addition The example below shows two instructions that add a 64 -bit integer contained in R2 and R3 to another 64 -bit integer contained in R0 and R1, and place the result in R4 and R5. ADDS R4, R0, R2 ; add the least significant words ADC R5, R1, R3 ; add the most significant words with carry 11.13.1.8 96-bit Subtraction Multiword values do not have to use consecutive registers. The example below shows instructions that subtract a 96-bit integer contained in R9, R1, and R11 from another contained in R6, R2, and R8. The example stores the result in R6, R9, and R2. SUBS R6, R6, R9 ; subtract the least significant words SBCS R9, R2, R1 ; subtract the middle words with carry SBC R2, R8, R11 ; subtract the most significant words with carry

11.13.2 AND, ORR, EOR, BIC, AND ORN

Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT.

11.13.2.1 Syntax

op{S}{cond} {Rd,} Rn, Operand2 where:

• op is one of: - AND: logical AND. - ORR: logical OR, or bit set. - EOR: logical Exclusive OR. - BIC: logical AND NOT, or bit clear. - ORN: logical OR NOT.
• S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional execution” on page 79.
• cond is an optional condition code, see “Conditional execution” on page 79.
• Rd is the destination register.
• Rn is the register holding the first operand.
• Operand2 is a flexible second operand. See “Flexible second operand” on page 75 for details of the options.

11.13.2.2 Operation

The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations on the values in Rn and Operand2. The BIC instruction performs an AND operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2. The ORN instruction performs an OR operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2.

11.13.2.3 Restrictions

Do not use SP and do not use PC.

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11.13.2.4 Condition Flags

If S is specified, these instructions:

• Update the N and Z flags according to the result
• Can update the C flag during the calculation of Operand2, see “Flexible second operand” on page 75
• Do not affect the V flag.

11.13.2.5 Examples

AND R9, R2, #0xFF00 ORREQ R2, R0, R5 ANDS R9, R8, #0x19 EORS R7, R11, #0x18181818 BIC R0, R1, #0xab ORN R7, R11, R14, ROR #4 ORNS R7, R11, R14, ASR #32

11.13.3 ASR, LSL, LSR, ROR, AND RRX

Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend.

11.13.3.1 Syntax

op{S}{cond} Rd, Rm, Rs RRX{S}{cond} Rd, Rm where:

• op is one of: - ASR: Arithmetic Shift Right. - LSL: Logical Shift Left. - LSR: Logical Shift Right. - ROR: Rotate Right.
• S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional execution” on page 79.
• Rd is the destination register.
• Rm is the register holding the value to be shifted.
• Rs is the register holding the shift length to apply to the value in Rm. Only the least significant byte is used and can be in the range 0 to 255.
• n is the shift length. The range of shift length depends on the instruction: - ASR: shift length from 1 to 32 - LSL: shift length from 0 to 31 - LSR: shift length from 1 to 32 - ROR: shift length from 1 to 31. MOV{S}{cond} Rd, Rm is the preferred syntax for LSL{S}{cond} Rd, Rm, #0.

11.13.3.2 Operation

ASR, LSL, LSR, and ROR move the bits in the register Rm to the left or right by the number of places specified by con- stant n or register Rs. RRX moves the bits in register Rm to the right by 1. In all these instructions, the result is written to Rd, but the value in register Rm remains unchanged. For details on what result is generated by the different instructions, see “Shift Operations” on page 76.

11.13.3.3 Restrictions

Do not use SP and do not use PC.

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11.13.3.4 Condition Flags

If S is specified:

• These instructions update the N and Z flags according to the result
• The C flag is updated to the last bit shifted out, except when the shift length is 0, see “Shift Operations” on page 76.

11.13.3.5 Examples

ASR R7, R8, #9 ; Arithmetic shift right by 9 bits LSLS R1, R2, #3 ; Logical shift left by 3 bits with flag update LSR R4, R5, #6 ; Logical shift right by 6 bits ROR R4, R5, R6 ; Rotate right by the value in the bottom byte of R6 RRX R4, R5 ; Rotate right with extend

11.13.4 CLZ

Count Leading Zeros.

11.13.4.1 Syntax

CLZ{cond} Rd, Rm where:

• cond is an optional condition code, see “Conditional execution” on page 79.
• Rd is the destination register.
• Rm is the operand register.

11.13.4.2 Operation

The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd. The result value is 32 if no bits are set in the source register, and zero if bit[31] is set.

11.13.4.3 Restrictions

Do not use SP and do not use PC.

11.13.4.4 Condition Flags

This instruction does not change the flags.

11.13.4.5 Examples

CLZ R4,R9 CLZNE R2,R3

11.13.5 CMP AND CMN

Compare and Compare Negative.

11.13.5.1 Syntax

CMP{cond} Rn, Operand2 CMN{cond} Rn, Operand2 where:

• cond is an optional condition code, see “Conditional execution” on page 79.
• Rn is the register holding the first operand.
• Operand2 is a flexible second operand. See “Flexible second operand” on page 75 for details of the options.

11.13.5.2 Operation

These instructions compare the value in a register with Operand2. They update the condition flags on the result, but do not write the result to a register. The CMP instruction subtracts the value of Operand2 from the value in Rn. This is the same as a SUBS instruction, except that the result is discarded.

 2020 Microchip Technology Inc. DS60001614B-page 95 SAM3X8ERT The CMN instruction adds the value of Operand2 to the value in Rn. This is the same as an ADDS instruction, except that the result is discarded.

11.13.5.3 Restrictions

In these instructions:

• Do not use PC
• Operand2 must not be SP .

11.13.5.4 Condition Flags

These instructions update the N, Z, C and V flags according to the result.

11.13.5.5 Examples

CMP R2, R9 CMN R0, #6400 CMPGT SP, R7, LSL #2

11.13.6 MOV AND MVN

Move and Move NOT.

11.13.6.1 Syntax

MOV{S}{cond} Rd, Operand2 MOV{cond} Rd, #imm16 MVN{S}{cond} Rd, Operand2 where:

• S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional execution” on page 79.
• cond is an optional condition code, see “Conditional execution” on page 79.
• Rd is the destination register.
• Operand2 is a flexible second operand. See “Flexible second operand” on page 75 for details of the options.
• imm16 is any value in the range 0-65535.

11.13.6.2 Operation

The MOV instruction copies the value of Operand2 into Rd. When Operand2 in a MOV instruction is a register with a shift other than LSL #0, the preferred syntax is the correspond- ing shift instruction:

• ASR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ASR #n
• LSL{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSL #n if n != 0
• LSR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSR #n
• ROR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ROR #n
• RRX{S}{cond} Rd, Rm is the preferred syntax for MOV{S}{cond} Rd, Rm, RRX. Also, the MOV instruction permits additional forms of Operand2 as synonyms for shift instructions:
• MOV{S}{cond} Rd, Rm, ASR Rs is a synonym for ASR{S}{cond} Rd, Rm, Rs
• MOV{S}{cond} Rd, Rm, LSL Rs is a synonym for LSL{S}{cond} Rd, Rm, Rs
• MOV{S}{cond} Rd, Rm, LSR Rs is a synonym for LSR{S}{cond} Rd, Rm, Rs
• MOV{S}{cond} Rd, Rm, ROR Rs is a synonym for ROR{S}{cond} Rd, Rm, Rs See “ASR, LSL, LSR, ROR, and RRX” on page 93. The MVN instruction takes the value of Operand2, performs a bitwise logical NOT operation on the value, and places the result into Rd. The MOVW instruction provides the same function as MOV, but is restricted to using the imm16 operand.

11.13.6.3 Restrictions

You can use SP and PC only in the MOV instruction, with the following restrictions:

DS60001614B-page 96  2020 Microchip Technology Inc.

• The second operand must be a register without shift
• You must not specify the S suffix. When Rd is PC in a MOV instruction:
• Bit[0] of the value written to the PC is ignored
• A branch occurs to the address created by forcing bit[0] of that value to 0. Though it is possible to use MOV as a branch instruction, ARM strongly recommends the use of a BX or BLX instruction to branch for software portability to the ARM instruction set.

11.13.6.4 Condition Flags

If S is specified, these instructions:

• Update the N and Z flags according to the result
• Can update the C flag during the calculation of Operand2, see “Flexible second operand” on page 75
• Do not affect the V flag.

11.13.6.5 Example

MOVS R11, #0x000B ; Write value of 0x000B to R11, flags get updated MOV R1, #0xFA05 ; Write value of 0xFA05 to R1, flags are not updated MOVS R10, R12 ; Write value in R12 to R10, flags get updated MOV R3, #23 ; Write value of 23 to R3 MOV R8, SP ; Write value of stack pointer to R8 MVNS R2, #0xF ; Write value of 0xFFFFFFF0 (bitwise inverse of 0xF) ; to the R2 and update flags

11.13.7 MOVT

Move Top.

11.13.7.1 Syntax

MOVT{cond} Rd, #imm16 where:

• cond is an optional condition code, see “Conditional execution” on page 79.
• Rd is the destination register.
• imm16 is a 16-bit immediate constant.

11.13.7.2 Operation

MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register. The write does not affect Rd[15:0]. The MOV, MOVT instruction pair enables you to generate any 32-bit constant.

11.13.7.3 Restrictions

Rd must not be SP and must not be PC.

11.13.7.4 Condition Flags

This instruction does not change the flags.

11.13.7.5 Examples

MOVT R3, #0xF123 ; Write 0xF123 to upper halfword of R3, lower halfword ; and APSR are unchanged

11.13.8 REV, REV16, REVSH, AND RBIT

Reverse bytes and Reverse bits.

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11.13.8.1 Syntax

op{cond} Rd, Rn where:

• op is any of: - REV: Reverse byte order in a word. - REV16: Reverse byte order in each halfword independently. - REVSH: Reverse byte order in the bottom halfword, and sign extend to 32 bits. - RBIT: Reverse the bit order in a 32-bit word.
• cond is an optional condition code, see “Conditional execution” on page 79.
• Rd is the destination register.
• Rn is the register holding the operand.

11.13.8.2 Operation

Use these instructions to change endianness of data:

• REV converts 32-bit big-endian data into little-endian data or 32-bit little-endian data into big-endian data.
• REV16 converts 16-bit big-endian data into little-endian data or 16-bit little-endian data into big-endian data.
• REVSH converts either: - 16-bit signed big-endian data into 32-bit signed little-endian data - 16-bit signed little-endian data into 32-bit signed big-endian data.

11.13.8.3 Restrictions

Do not use SP and do not use PC.

11.13.8.4 Condition Flags

These instructions do not change the flags.

11.13.8.5 Examples

REV R3, R7 ; Reverse byte order of value in R7 and write it to R3 REV16 R0, R0 ; Reverse byte order of each 16-bit halfword in R0 REVSH R0, R5 ; Reverse Signed Halfword REVHS R3, R7 ; Reverse with Higher or Same condition RBIT R7, R8 ; Reverse bit order of value in R8 and write the result to R7

11.13.9 TST AND TEQ

Test bits and Test Equivalence.

11.13.9.1 Syntax

TST{cond} Rn, Operand2 TEQ{cond} Rn, Operand2 where:

• cond is an optional condition code, see “Conditional execution” on page 79.
• Rn is the register holding the first operand.
• Operand2 is a flexible second operand. See “Flexible second operand” on page 75 for details of the options.

11.13.9.2 Operation

These instructions test the value in a register against Operand2. They update the condition flags based on the result, but do not write the result to a register. The TST instruction performs a bitwise AND operation on the value in Rn and the value of Operand2. This is the same as the ANDS instruction, except that it discards the result. To test whether a bit of Rn is 0 or 1, use the TST instruction with an Operand2 constant that has that bit set to 1 and all other bits cleared to 0.

DS60001614B-page 98  2020 Microchip Technology Inc. The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the value of Operand2. This is the same as the EORS instruction, except that it discards the result. Use the TEQ instruction to test if two values are equal without affecting the V or C flags. TEQ is also useful for testing the sign of a value. After the comparison, the N flag is the logical Exclusive OR of the sign bits of the two operands.

11.13.9.3 Restrictions

Do not use SP and do not use PC.

11.13.9.4 Condition Flags

These instructions:

• Update the N and Z flags according to the result
• Can update the C flag during the calculation of Operand2, see “Flexible second operand” on page 75
• Do not affect the V flag.

11.13.9.5 Examples

TST R0, #0x3F8 ; Perform bitwise AND of R0 value to 0x3F8, ; APSR is updated but result is discarded TEQEQ R10, R9 ; Conditionally test if value in R10 is equal to ; value in R9, APSR is updated but result is discarded

11.14 Multiply and Divide Instructions

Table 11-21 shows the multiply and divide instructions:

11.14.1 MUL, MLA, AND MLS

Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and producing a 32-bit result.

11.14.1.1 Syntax

MUL{S}{cond} {Rd,} Rn, Rm ; Multiply MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract where:

• cond is an optional condition code, see “Conditional execution” on page 79.
• S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional execution” on page 79.
• Rd is the destination register. If Rd is omitted, the destination register is Rn.
• Rn, Rm are registers holding the values to be multiplied. TABLE 11-21: MULTIPLY AND DIVIDE INSTRUCTIONS Mnemonic Brief description See MLA Multiply with Accumulate, 32-bit result “MUL, MLA, and MLS” on page 98 MLS Multiply and Subtract, 32-bit result “MUL, MLA, and MLS” on page 98 MUL Multiply, 32-bit result “MUL, MLA, and MLS” on page 98 SDIV Signed Divide “SDIV and UDIV” on page 100 SMLAL Signed Multiply with Accumulate (32x32+64), 64-bit result “UMULL, UMLAL, SMULL, and SMLAL” on page 99 SMULL Signed Multiply (32x32), 64-bit result “UMULL, UMLAL, SMULL, and SMLAL” on page 99 UDIV Unsigned Divide “SDIV and UDIV” on page 100 UMLAL Unsigned Multiply with Accumulate (32x32+64), 64-bit result “UMULL, UMLAL, SMULL, and SMLAL” on page 99 UMULL Unsigned Multiply (32x32), 64-bit result “UMULL, UMLAL, SMULL, and SMLAL” on page 99

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• Ra is a register holding the value to be added or subtracted from. Operation The MUL instruction multiplies the values from Rn and Rm, and places the least significant 32 bits of the result in Rd. The MLA instruction multiplies the values from Rn and Rm, adds the value from Ra, and places the least significant 32 bits of the result in Rd. The MLS instruction multiplies the values from Rn and Rm, subtracts the product from the value from Ra, and places the least significant 32 bits of the result in Rd. The results of these instructions do not depend on whether the operands are signed or unsigned.

11.14.1.2 Restrictions

In these instructions, do not use SP and do not use PC. If you use the S suffix with the MUL instruction:

• Rd, Rn, and Rm must all be in the range R0 to R7
• Rd must be the same as Rm
• you must not use the cond suffix.

11.14.1.3 Condition Flags

If S is specified, the MUL instruction:

• Updates the N and Z flags according to the result
• Does not affect the C and V flags.

11.14.1.4 Examples

MUL R10, R2, R5 ; Multiply, R10 = R2 x R5 MLA R10, R2, R1, R5 ; Multiply with accumulate, R10 = (R2 x R1) + R5 MULS R0, R2, R2 ; Multiply with flag update, R0 = R2 x R2 MULLT R2, R3, R2 ; Conditionally multiply, R2 = R3 x R2 MLS R4, R5, R6, R7 ; Multiply with subtract, R4 = R7 - (R5 x R6)

11.14.2 UMULL, UMLAL, SMULL, AND SMLAL

Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result.

11.14.2.1 Syntax

op{cond} RdLo, RdHi, Rn, Rm where:

• op is one of: - UMULL Unsigned Long Multiply. - UMLAL Unsigned Long Multiply, with Accumulate. - SMULL Signed Long Multiply. - SMLAL Signed Long Multiply, with Accumulate.
• cond is an optional condition code, see “Conditional execution” on page 79.
• RdHi, RdLo are the destination registers. - For UMLAL and SMLAL they also hold the accumulating value.
• Rn, Rm are registers holding the operands.

11.14.2.2 Operation

The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi. The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers, adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo, and writes the result back to RdHi and RdLo. The SMULL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi.

DS60001614B-page 100  2020 Microchip Technology Inc. The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers, adds the 64-bit result to the 64-bit signed integer contained in RdHi and RdLo, and writes the result back to RdHi and RdLo.

11.14.2.3 Restrictions

In these instructions:

• Do not use SP and do not use PC
• RdHi and RdLo must be different registers.

11.14.2.4 Condition Flags

These instructions do not affect the condition code flags.

11.14.2.5 Examples

UMULL R0, R4, R5, R6 ; Unsigned (R4,R0) = R5 x R6 SMLAL R4, R5, R3, R8 ; Signed (R5,R4) = (R5,R4) + R3 x R8

11.14.3 SDIV AND UDIV

Signed Divide and Unsigned Divide.

11.14.3.1 Syntax

SDIV{cond} {Rd,} Rn, Rm UDIV{cond} {Rd,} Rn, Rm where:

• cond is an optional condition code, see “Conditional execution” on page 79.
• Rd is the destination register. If Rd is omitted, the destination register is Rn.
• Rn is the register holding the value to be divided.
• Rm is a register holding the divisor.

11.14.3.2 Operation

SDIV performs a signed integer division of the value in Rn by the value in Rm. UDIV performs an unsigned integer division of the value in Rn by the value in Rm. For both instructions, if the value in Rn is not divisible by the value in Rm, the result is rounded towards zero.

11.14.3.3 Restrictions

Do not use SP and do not use PC.

11.14.3.4 Condition Flags

These instructions do not change the flags.

11.14.3.5 Examples

SDIV R0, R2, R4 ; Signed divide, R0 = R2/R4 UDIV R8, R8, R1 ; Unsigned divide, R8 = R8/R1

11.15 Saturating Instructions

This section describes the saturating instructions, SSAT and USAT.

11.15.1 SSAT AND USAT

Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating.

11.15.1.1 Syntax

op{cond} Rd, #n, Rm {, shift #s} where:

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• op is one of: - SSAT Saturates a signed value to a signed range. - USAT Saturates a signed value to an unsigned range.
• cond is an optional condition code, see “Conditional execution” on page 79.
• Rd is the destination register.
• n specifies the bit position to saturate to: - n ranges from 1 to 32 for SSAT - n ranges from 0 to 31 for USAT.
• Rm is the register containing the value to saturate.
• shift #s is an optional shift applied to Rm before saturating. It must be one of the following: - ASR #s where s is in the range 1 to 31 - LSL #s where s is in the range 0 to 31.

11.15.1.2 Operation

These instructions saturate to a signed or unsigned n-bit value. The SSAT instruction applies the specified shift, then saturates to the signed range 2n–1 x  2n–11. The USAT instruction applies the specified shift, then saturates to the unsigned range 0 x  2n1. For signed n-bit saturation using SSAT, this means that:

• If the value to be saturated is less than 2n1, the result returned is 2n-1
• If the value to be saturated is greater than 2n11, the result returned is 2n-11
• Otherwise, the result returned is the same as the value to be saturated. For unsigned n-bit saturation using USAT, this means that:
• If the value to be saturated is less than 0, the result returned is 0
• If the value to be saturated is greater than 2n1, the result returned is 2n1
• Otherwise, the result returned is the same as the value to be saturated. If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the instruction sets the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. To clear the Q flag to 0, you must use the MSR instruction, see “MSR” on page 112. To read the state of the Q flag, use the MRS instruction, see “MRS” on page 111.

11.15.1.3 Restrictions

Do not use SP and do not use PC.

11.15.1.4 Condition Flags

These instructions do not affect the condition code flags. If saturation occurs, these instructions set the Q flag to 1.

11.15.1.5 Examples

SSAT R7, #16, R7, LSL #4 ; Logical shift left value in R7 by 4, then ; saturate it as a signed 16-bit value and ; write it back to R7 USATNE R0, #7, R5 ; Conditionally saturate value in R5 as an ; unsigned 7 bit value and write it to R0

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11.16 Bitfield Instructions

Table 11-22 shows the instructions that operate on adjacent sets of bits in registers or bitfields:

11.16.1 BFC AND BFI

Bit Field Clear and Bit Field Insert.

11.16.1.1 Syntax

BFC{cond} Rd, #lsb, #width BFI{cond} Rd, Rn, #lsb, #width where:

• cond is an optional condition code, see “Conditional execution” on page 79.
• Rd is the destination register.
• Rn is the source register.
• lsb is the position of the least significant bit of the bitfield. - lsb must be in the range 0 to 31.
• width is the width of the bitfield and must be in the range 1 to 32lsb.

11.16.1.2 Operation

BFC clears a bitfield in a register. It clears width bits in Rd, starting at the low bit position lsb. Other bits in Rd are unchanged. BFI copies a bitfield into one register from another register. It replaces width bits in Rd starting at the low bit position lsb, with width bits from Rn starting at bit[0]. Other bits in Rd are unchanged.

11.16.1.3 Restrictions

Do not use SP and do not use PC.

11.16.1.4 Condition Flags

These instructions do not affect the flags.

11.16.1.5 Examples

BFC R4, #8, #12 ; Clear bit 8 to bit 19 (12 bits) of R4 to 0 BFI R9, R2, #8, #12 ; Replace bit 8 to bit 19 (12 bits) of R9 with ; bit 0 to bit 11 from R2

11.16.2 SBFX AND UBFX

Signed Bit Field Extract and Unsigned Bit Field Extract.

11.16.2.1 Syntax

SBFX{cond} Rd, Rn, #lsb, #width TABLE 11-22: PACKING AND UNPACKING INSTRUCTIONS Mnemonic Brief description See BFC Bit Field Clear “BFC and BFI” on page 102 BFI Bit Field Insert “BFC and BFI” on page 102 SBFX Signed Bit Field Extract “SBFX and UBFX” on page 102 SXTB Sign extend a byte “SXT and UXT” on page 103 SXTH Sign extend a halfword “SXT and UXT” on page 103 UBFX Unsigned Bit Field Extract “SBFX and UBFX” on page 102 UXTB Zero extend a byte “SXT and UXT” on page 103 UXTH Zero extend a halfword “SXT and UXT” on page 103

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• cond is an optional condition code, see “Conditional execution” on page 79.
• Rd is the destination register.
• Rn is the source register.
• lsbis the position of the least significant bit of the bitfield. - lsb must be in the range 0 to 31.
• width is the width of the bitfield and must be in the range 1 to 32lsb.

11.16.2.2 Operation

SBFX extracts a bitfield from one register, sign extends it to 32 bits, and writes the result to the destination register. UBFX extracts a bitfield from one register, zero extends it to 32 bits, and writes the result to the destination register.

11.16.2.3 Restrictions

Do not use SP and do not use PC.

11.16.2.4 Condition Flags

These instructions do not affect the flags.

11.16.2.5 Examples

SBFX R0, R1, #20, #4 ; Extract bit 20 to bit 23 (4 bits) from R1 and sign ; extend to 32 bits and then write the result to R0. UBFX R8, R11, #9, #10 ; Extract bit 9 to bit 18 (10 bits) from R11 and zero ; extend to 32 bits and then write the result to R8

11.16.3 SXT AND UXT

Sign extend and Zero extend.

11.16.3.1 Syntax

SXTextend{cond} {Rd,} Rm {, ROR #n} UXTextend{cond} {Rd}, Rm {, ROR #n} where: extend is one of:

• B: Extends an 8-bit value to a 32-bit value.
• H: Extends a 16-bit value to a 32-bit value. cond is an optional condition code, see “Conditional execution” on page 79.
• Rd is the destination register.
• Rm is the register holding the value to extend. ROR #n is one of:
• ROR #8: Value from Rm is rotated right 8 bits.
• ROR #16: Value from Rm is rotated right 16 bits.
• ROR #24: Value from Rm is rotated right 24 bits. - If ROR #n is omitted, no rotation is performed.

11.16.3.2 Operation

These instructions do the following:

• Rotate the value from Rm right by 0, 8, 16 or 24 bits.
• Extract bits from the resulting value: - SXTB extracts bits[7:0] and sign extends to 32 bits. - UXTB extracts bits[7:0] and zero extends to 32 bits. - SXTH extracts bits[15:0] and sign extends to 32 bits.

DS60001614B-page 104  2020 Microchip Technology Inc. - UXTH extracts bits[15:0] and zero extends to 32 bits.

11.16.3.3 Restrictions

Do not use SP and do not use PC.

11.16.3.4 Condition Flags

These instructions do not affect the flags.

11.16.3.5 Examples

SXTH R4, R6, ROR #16 ; Rotate R6 right by 16 bits, then obtain the lower ; halfword of the result and then sign extend to ; 32 bits and write the result to R4. UXTB R3, R10 ; Extract lowest byte of the value in R10 and zero ; extend it, and write the result to R3

11.17 Branch and Control Instructions

Table 11-23 shows the branch and control instructions:

11.17.1 B, BL, BX, AND BLX

Branch instructions.

11.17.1.1 Syntax

B{cond} label BL{cond} label BX{cond} Rm BLX{cond} Rm where:

• B is branch (immediate).
• BL is branch with link (immediate).
• BX is branch indirect (register).
• BLX is branch indirect with link (register).
• cond is an optional condition code, see “Conditional execution” on page 79.
• label is a PC-relative expression. See “PC-relative expressions” on page 78.
• Rm is a register that indicates an address to branch to. Bit[0] of the value in Rm must be 1, but the address to branch to is created by changing bit[0] to 0.

11.17.1.2 Operation

All these instructions cause a branch to label, or to the address indicated in Rm. In addition:

• The BL and BLX instructions write the address of the next instruction to LR (the link register, R14). TABLE 11-23: BRANCH AND CONTROL INSTRUCTIONS Mnemonic Brief description See B Branch “B, BL, BX, and BLX” on page 104 BL Branch with Link “B, BL, BX, and BLX” on page 104 BLX Branch indirect with Link “B, BL, BX, and BLX” on page 104 BX Branch indirect “B, BL, BX, and BLX” on page 104 CBNZ Compare and Branch if Non Zero “CBZ and CBNZ” on page 105 CBZ Compare and Branch if Non Zero “CBZ and CBNZ” on page 105 IT If-Then “IT” on page 106 TBB Table Branch Byte “TBB and TBH” on page 108 TBH Table Branch Halfword “TBB and TBH” on page 108

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• The BX and BLX instructions cause a UsageFault exception if bit[0] of Rm is 0. Bcond label is the only conditional instruction that can be either inside or outside an IT block. All other branch instruc - tions must be conditional inside an IT block, and must be unconditional outside the IT block, see “IT” on page 106. Table 11-24 shows the ranges for the various branch instructions. You might have to use the .W suffix to get the maximum branch range. See “Instruction width selection” on page 80.

11.17.1.3 Restrictions

The restrictions are:

• Do not use PC in the BLX instruction
• For BX and BLX, bit[0] of Rm must be 1 for correct execution but a branch occurs to the target address created by changing bit[0] to 0
• When any of these instructions is inside an IT block, it must be the last instruction of the IT block. Bcond is the only conditional instruction that is not required to be inside an IT block. However, it has a longer branch range when it is inside an IT block.

11.17.1.4 Condition Flags

These instructions do not change the flags.

11.17.1.5 Examples

B loopA ; Branch to loopA BLE ng ; Conditionally branch to label ng B.W target ; Branch to target within 16MB range BEQ target ; Conditionally branch to target BEQ.W target ; Conditionally branch to target within 1MB BL funC ; Branch with link (Call) to function funC, return address ; stored in LR BX LR ; Return from function call BXNE R0 ; Conditionally branch to address stored in R0 BLX R0 ; Branch with link and exchange (Call) to a address stored ; in R0

11.17.2 CBZ AND CBNZ

Compare and Branch on Zero, Compare and Branch on Non-Zero.

11.17.2.1 Syntax

CBZ Rn, label CBNZ Rn, label where:

• Rn is the register holding the operand.
• label is the branch destination. TABLE 11-24: BRANCH RANGES Instruction Branch range B label 16 MB to +16 MB Bcond label (outside IT block) 1 MB to +1 MB Bcond label (inside IT block) 16 MB to +16 MB BL{cond} label 16 MB to +16 MB BX{cond} Rm Any value in register BLX{cond} Rm Any value in register

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11.17.2.2 Operation

Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce the number of instructions. CBZ Rn, label does not change condition flags but is otherwise equivalent to: CMP Rn, #0 BEQ label CBNZ Rn, label does not change condition flags but is otherwise equivalent to: CMP Rn, #0 BNE label

11.17.2.3 Restrictions

The restrictions are:

• Rn must be in the range of R0 to R7
• The branch destination must be within 4 to 130 bytes after the instruction
• These instructions must not be used inside an IT block

11.17.2.4 Condition Flags

These instructions do not change the flags.

11.17.2.5 Examples

CBZ R5, target ; Forward branch if R5 is zero CBNZ R0, target ; Forward branch if R0 is not zero 11.17.3 IT If-Then condition instruction.

11.17.3.1 Syntax

where:

• x: specifies the condition switch for the second instruction in the IT block.
• y: specifies the condition switch for the third instruction in the IT block.
• z: specifies the condition switch for the fourth instruction in the IT block.
• cond: specifies the condition for the first instruction in the IT block. The condition switch for the second, third and fourth instruction in the IT block can be either:
• T: Then. Applies the condition cond to the instruction.
• E: Else. Applies the inverse condition of cond to the instruction. It is possible to use AL (the always condition) for cond in an IT instruction. If this is done, all of the instructions in the IT block must be unconditional, and each of x, y, and z must be T or omitted but not E.

11.17.3.2 Operation

The IT instruction makes up to four following instructions conditional. The conditions can be all the same, or some of them can be the logical inverse of the others. The conditional instructions following the IT instruction form the IT block. The instructions in the IT block, including any branches, must specify the condition in the {cond} part of their syntax. Your assembler might be able to generate the required IT instructions for conditional instructions automatically, so that you do not need to write them yourself. See your assembler documentation for details. A BKPT instruction in an IT block is always executed, even if its condition fails. Exceptions can be taken between an IT instruction and the corresponding IT block, or within an IT block. Such an excep- tion results in entry to the appropriate exception handler, with suitable return information in LR and stacked PSR. Instructions designed for use for exception returns can be used as normal to return from the exception, and execution of the IT block resumes correctly. This is the only way that a PC-modifying instruction is permitted to branch to an instruc- tion in an IT block.

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11.17.3.3 Restrictions

The following instructions are not permitted in an IT block:

• IT
• CBZ and CBNZ
• CPSID and CPSIE. Other restrictions when using an IT block are:
• A branch or any instruction that modifies the PC must either be outside an IT block or must be the last instruction inside the IT block. These are: - ADD PC, PC, Rm - MOV PC, Rm - B, BL, BX, BLX - any LDM, LDR, or POP instruction that writes to the PC - TBB and TBH
• Do not branch to any instruction inside an IT block, except when returning from an exception handler
• All conditional instructions except Bcond must be inside an IT block. Bcond can be either outside or inside an IT block but has a larger branch range if it is inside one
• Each instruction inside the IT block must specify a condition code suffix that is either the same or logical inverse as for the other instructions in the block. Your assembler might place extra restrictions on the use of IT blocks, such as prohibiting the use of assembler directives within them.

11.17.3.4 Condition Flags

This instruction does not change the flags.

11.17.3.5 Example

ITTE NE ; Next 3 instructions are conditional ANDNE R0, R0, R1 ; ANDNE does not update condition flags ADDSNE R2, R2, #1 ; ADDSNE updates condition flags MOVEQ R2, R3 ; Conditional move CMP R0, #9 ; Convert R0 hex value (0 to 15) into ASCII ITE GT ; Next 2 instructions are conditional ADDGT R1, R0, #55 ; Convert 0xA -> 'A' ADDLE R1, R0, #48 ; Convert 0x0 -> '0' IT GT ; IT block with only one conditional instruction ADDGT R1, R1, #1 ; Increment R1 conditionally ITTEE EQ ; Next 4 instructions are conditional MOVEQ R0, R1 ; Conditional move ADDEQ R2, R2, #10 ; Conditional add ANDNE R3, R3, #1 ; Conditional AND BNE.W dloop ; Branch instruction can only be used in the last ; instruction of an IT block IT NE ; Next instruction is conditional ADD R0, R0, R1 ; Syntax error: no condition code used in IT block

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11.17.4 TBB AND TBH

Table Branch Byte and Table Branch Halfword.

11.17.4.1 Syntax

TBB [Rn, Rm] TBH [Rn, Rm, LSL #1] where:

• Rn is the register containing the address of the table of branch lengths. If Rn is PC, then the address of the table is the address of the byte immediately following the TBB or TBH instruction.
• Rm is the index register. This contains an index into the table. For halfword tables, LSL #1 doubles the value in Rm to form the right offset into the table.

11.17.4.2 Operation

These instructions cause a PC-relative forward branch using a table of single byte offsets for TBB, or halfword offsets for TBH. Rn provides a pointer to the table, and Rm supplies an index into the table. For TBB the branch offset is twice the unsigned value of the byte returned from the table. and for TBH the branch offset is twice the unsigned value of the halfword returned from the table. The branch occurs to the address at that offset from the address of the byte immedi- ately after the TBB or TBH instruction.

11.17.4.3 Restrictions

The restrictions are:

• Rn must not be SP
• Rm must not be SP and must not be PC
• When any of these instructions is used inside an IT block, it must be the last instruction of the IT block.

11.17.4.4 Condition Flags

These instructions do not change the flags.

11.17.4.5 Examples

ADR.W R0, BranchTable_Byte TBB [R0, R1] ; R1 is the index, R0 is the base address of the ; branch table Case1 ; an instruction sequence follows Case2 ; an instruction sequence follows Case3 ; an instruction sequence follows BranchTable_Byte DCB 0 ; Case1 offset calculation DCB ((Case2-Case1)/2) ; Case2 offset calculation DCB ((Case3-Case1)/2) ; Case3 offset calculation TBH [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the ; branch table BranchTable_H DCI ((CaseA - BranchTable_H)/2) ; CaseA offset calculation DCI ((CaseB - BranchTable_H)/2) ; CaseB offset calculation DCI ((CaseC - BranchTable_H)/2) ; CaseC offset calculation CaseA ; an instruction sequence follows CaseB ; an instruction sequence follows CaseC ; an instruction sequence follows

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11.18 Miscellaneous Instructions

Table 11-25 shows the remaining Cortex-M3 instructions:

11.18.1 BKPT

Breakpoint.

11.18.1.1 Syntax

BKPT #imm where: imm is an expression evaluating to an integer in the range 0-255 (8-bit value).

11.18.1.2 Operation

The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. imm is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. The BKPT instruction can be placed inside an IT block, but it executes unconditionally, unaffected by the condition spec- ified by the IT instruction.

11.18.1.3 Condition Flags

This instruction does not change the flags.

11.18.1.4 Examples

BKPT 0xAB ; Breakpoint with immediate value set to 0xAB (debugger can ; extract the immediate value by locating it using the PC)

11.18.2 CPS

Change Processor State.

11.18.2.1 Syntax

where: effect is one of: TABLE 11-25: MISCELLANEOUS INSTRUCTIONS Mnemonic Brief description See BKPT Breakpoint “BKPT” on page 109 CPSID Change Processor State, Disable Interrupts “CPS” on page 109 CPSIE Change Processor State, Enable Interrupts “CPS” on page 109 DMB Data Memory Barrier “DMB” on page 110 DSB Data Synchronization Barrier “DSB” on page 110 ISB Instruction Synchronization Barrier “ISB” on page 111 MRS Move from special register to register “MRS” on page 111 MSR Move from register to special register “MSR” on page 112 NOP No Operation “NOP” on page 112 SEV Send Event “SEV” on page 113 SVC Supervisor Call “SVC” on page 113 WFE Wait For Event “WFE” on page 113 WFI Wait For Interrupt “WFI” on page 115

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• IE Clears the special purpose register.
• ID Sets the special purpose register. iflags is a sequence of one or more flags:
• i Set or clear PRIMASK.
• f Set or clear FAULTMASK.

11.18.2.2 Operation

CPS changes the PRIMASK and FAULTMASK special register values. See “Exception mask registers” on page 52 for more information about these registers.

11.18.2.3 Restrictions

The restrictions are:

• Use CPS only from privileged software, it has no effect if used in unprivileged software
• CPS cannot be conditional and so must not be used inside an IT block.

11.18.2.4 Condition Flags

This instruction does not change the condition flags.

11.18.2.5 Examples

CPSID i ; Disable interrupts and configurable fault handlers (set PRIMASK) CPSID f ; Disable interrupts and all fault handlers (set FAULTMASK) CPSIE i ; Enable interrupts and configurable fault handlers (clear PRIMASK) CPSIE f ; Enable interrupts and fault handlers (clear FAULTMASK)

11.18.3 DMB

Data Memory Barrier.

11.18.3.1 Syntax

DMB{cond} where: cond is an optional condition code, see “Conditional execution” on page 79.

11.18.3.2 Operation

DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before the DMB instruction are completed before any explicit memory accesses that appear, in program order, after the DMB instruction. DMB does not affect the ordering or execution of instructions that do not access memory.

11.18.3.3 Condition Flags

This instruction does not change the flags.

11.18.3.4 Examples

DMB ; Data Memory Barrier

11.18.4 DSB

Data Synchronization Barrier.

11.18.4.1 Syntax

DSB{cond} where: cond is an optional condition code, see “Conditional execution” on page 79.

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11.18.4.2 Operation

DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do not execute until the DSB instruction completes. The DSB instruction completes when all explicit memory accesses before it complete.

11.18.4.3 Condition Flags

This instruction does not change the flags.

11.18.4.4 Examples

DSB ; Data Synchronisation Barrier

11.18.5 ISB

Instruction Synchronization Barrier.

11.18.5.1 Syntax

ISB{cond} where: cond is an optional condition code, see “Conditional execution” on page 79.

11.18.5.2 Operation

ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from memory again, after the ISB instruction has been completed.

11.18.5.3 Condition Flags

This instruction does not change the flags.

11.18.5.4 Examples

ISB ; Instruction Synchronisation Barrier

11.18.6 MRS

Move the contents of a special register to a general-purpose register.

11.18.6.1 Syntax

MRS{cond} Rd, spec_reg where:

• cond is an optional condition code, see “Conditional execution” on page 79.
• Rd is the destination register.
• spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP , PSP , PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.

11.18.6.2 Operation

Use MRS in combination with MSR as part of a read -modify-write sequence for updating a PSR, for example to clear the Q flag. In process swap code, the programmers model state of the process being swapped out must be saved, including rele- vant PSR contents. Similarly, the state of the process being swapped in must also be restored. These operations use MRS in the state-saving instruction sequence and MSR in the state-restoring instruction sequence. BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction. See “MSR” on page 112.

11.18.6.3 Restrictions

Rd must not be SP and must not be PC.

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11.18.6.4 Condition Flags

This instruction does not change the flags.

11.18.6.5 Examples

MRS R0, PRIMASK ; Read PRIMASK value and write it to R0

11.18.7 MSR

Move the contents of a general-purpose register into the specified special register.

11.18.7.1 Syntax

MSR{cond} spec_reg, Rn where:

• cond is an optional condition code, see “Conditional execution” on page 79.
• Rn is the source register.
• spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP , PSP , PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.

11.18.7.2 Operation

The register access operation in MSR depends on the privilege level. Unprivileged software can only access the APSR, see “Application Program Status Register” on page 50. Privileged software can access all special registers. In unprivileged software writes to unallocated or execution state bits in the PSR are ignored. When you write to BASEPRI_MAX, the instruction writes to BASEPRI only if either:

• Rn is non-zero and the current BASEPRI value is 0
• Rn is non-zero and less than the current BASEPRI value. See “MRS” on page 111.

11.18.7.3 Restrictions

Rn must not be SP and must not be PC.

11.18.7.4 Condition Flags

This instruction updates the flags explicitly based on the value in Rn.

11.18.7.5 Examples

MSR CONTROL, R1 ; Read R1 value and write it to the CONTROL register

11.18.8 NOP

No Operation.

11.18.8.1 Syntax

NOP{cond} where:

• cond is an optional condition code, see “Conditional execution” on page 79.

11.18.8.2 Operation

NOP does nothing. NOP is not necessarily a time -consuming NOP . The processor might remove it from the pipeline before it reaches the execution stage. Use NOP for padding, for example to place the following instruction on a 64-bit boundary.

11.18.8.3 Condition Flags

This instruction does not change the flags.

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11.18.8.4 Examples

NOP ; No operation

11.18.9 SEV

Send Event.

11.18.9.1 Syntax

SEV{cond} where:

• cond is an optional condition code, see “Conditional execution” on page 79.

11.18.9.2 Operation

SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system. It also sets the local event register to 1, see “Power Management” on page 70.

11.18.9.3 Condition Flags

This instruction does not change the flags.

11.18.9.4 Examples

SEV ; Send Event

11.18.10 SVC

Supervisor Call.

11.18.10.1 Syntax

SVC{cond} #imm where:

• cond is an optional condition code, see “Conditional execution” on page 79.
• imm is an expression evaluating to an integer in the range 0-255 (8-bit value).

11.18.10.2 Operation

The SVC instruction causes the SVC exception. imm is ignored by the processor. If required, it can be retrieved by the exception handler to determine what service is being requested.

11.18.10.3 Condition Flags

This instruction does not change the flags.

11.18.10.4 Examples

SVC 0x32 ; Supervisor Call (SVC handler can extract the immediate value ; by locating it via the stacked PC)

11.18.11 WFE

Wait For Event.

11.18.11.1 Syntax

WFE{cond} where:

• cond is an optional condition code, see “Conditional execution” on page 79.

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11.18.11.2 Operation

WFE is a hint instruction. If the event register is 0, WFE suspends execution until one of the following events occurs:

• An exception, unless masked by the exception mask registers or the current priority level
• An exception enters the Pending state, if SEVONPEND in the System Control Register is set
• A Debug Entry request, if Debug is enabled
• An event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction. If the event register is 1, WFE clears it to 0 and returns immediately. For more information see “Power Management” on page 70.

11.18.11.3 Condition Flags

This instruction does not change the flags.

11.18.11.4 Examples

WFE ; Wait for event

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11.18.12 WFI

Wait for Interrupt.

11.18.12.1 Syntax

WFI{cond} where:

• cond is an optional condition code, see “Conditional execution” on page 79.

11.18.12.2 Operation

WFI is a hint instruction that suspends execution until one of the following events occurs:

• An exception
• A Debug Entry request, regardless of whether Debug is enabled.

11.18.12.3 Condition Flags

This instruction does not change the flags.

11.18.12.4 Examples

WFI ; Wait for interrupt

11.19 About the Cortex-M3 Peripherals

The address map of the Private peripheral bus (PPB) is: In register descriptions:

• The register type is described as follows: - RW: Read and write. - RO: Read-only. - WO: Write-only.
• The required privilege gives the privilege level required to access the register, as follows: - Privileged: Only privileged software can access the register. - Unprivileged: Both unprivileged and privileged software can access the register.

11.20 Nested Vectored Interrupt Controller

This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports:

• 1 to 30 interrupts.
• A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority.
• Level detection of interrupt signals.
• Dynamic reprioritization of interrupts.
• Grouping of priority values into group priority and subpriority fields. TABLE 11-26: CORE PERIPHERAL REGISTER REGIONS Address Core peripheral Description 0xE000E008-0xE000E00F System control block Table 11-30 0xE000E010-0xE000E01F System timer Table 11-33 0xE000E100-0xE000E4EF Nested Vectored Interrupt Controller Table 11-27 0xE000ED00-0xE000ED3F System control block Table 11-30 0xE000ED90-0xE000EDB8 Memory protection unit Table 11-35 0xE000EF00-0xE000EF03 Nested Vectored Interrupt Controller Table 11-27

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• Interrupt tail-chaining. The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruc- tion overhead. This provides low latency exception handling. The hardware implementation of the NVIC registers is:

11.20.1 THE CMSIS MAPPING OF THE CORTEX-M3 NVIC REGISTERS

To improve software efficiency, the CMSIS simplifies the NVIC register presentation. In the CMSIS:

• The Set-enable, Clear-enable, Set-pending, Clear-pending and Active Bit registers map to arrays of 32-bit inte- gers, so that: - The array ISER[0] to ISER[1] corresponds to the registers ISER0-ISER1 - The array ICER[0] to ICER[1] corresponds to the registers ICER0-ICER1 - The array ISPR[0] to ISPR[1] corresponds to the registers ISPR0-ISPR1 - The array ICPR[0] to ICPR[1] corresponds to the registers ICPR0-ICPR1 - The array IABR[0] to IABR[1] corresponds to the registers IABR0-IABR1
• The 4-bit fields of the Interrupt Priority Registers map to an array of 4-bit integers, so that the array IP[0] to IP[29] corresponds to the registers IPR0-IPR7, and the array entry IP[n] holds the interrupt priority for interrupt n. The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Registers. For more information see the description of the NVIC_SetPriority function in “NVIC Programming Hints” on page 122. Table 11-28 shows how the interrupts, or IRQ numbers, map onto the interrupt registers and corresponding CMSIS variables that have one bit per interrupt. TABLE 11-27: NVIC REGISTER SUMMARY Address Name Type Required privilege Reset value Description 0xE000E100-0xE- 000E104 ISER0- ISER1 RW Privileged 0x00000000 “Interrupt Set-enable Registers” on page 117 0xE000E180- 0xE000E184 ICER0- ICER1 RW Privileged 0x00000000 “Interrupt Clear-enable Registers” on page 117 0xE000E200- 0xE000E204 ISPR0- ISPR1 RW Privileged 0x00000000 “Interrupt Set-pending Registers” on page 118 0xE000E280- 0xE000E284 ICPR0- ICPR1 RW Privileged 0x00000000 “Interrupt Clear-pending Registers” on page 118 0xE000E300- 0xE000E304 IABR0- IABR1 RO Privileged 0x00000000 “Interrupt Active Bit Registers” on page 119 0xE000E400- 0xE000E41C IPR0- IPR7 RW Privileged 0x00000000 “Interrupt Priority Registers” on page 119 0xE000EF00 STIR WO Configura ble (1) 1. See the register description for more information. 0x00000000 “Software Trigger Interrupt Register” on page 121 TABLE 11-28: MAPPING OF INTERRUPTS TO THE INTERRUPT VARIABLES Interrupts CMSIS array elements (1) 1. Each array element corresponds to a single NVIC register, for example the ele- ment ICER[0] corresponds to the ICER0 register. Set-enable Clear-enable Set-pending Clear-pending Active Bit 0-29 ISER[0] ICER[0] ISPR[0] ICPR[0] IABR[0] 30-63 ISER[1] ICER[1] ISPR[1] ICPR[1] IABR[1]

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11.20.2 INTERRUPT SET-ENABLE REGISTERS

The ISER0-ISER1 register enables interrupts, and show which interrupts are enabled. See:

• The register summary in Table 11-27 for the register attributes
• Table 11-28 for which interrupts are controlled by each register. The bit assignments are:
• SETENA Interrupt set-enable bits. Write: 0: no effect 1: enable interrupt. Read: 0: interrupt disabled 1: interrupt enabled. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regard- less of its priority.

11.20.3 INTERRUPT CLEAR-ENABLE REGISTERS

The ICER0-ICER1 register disables interrupts, and shows which interrupts are enabled. See:

• The register summary in Table 11-27 for the register attributes
• Table 11-28 for which interrupts are controlled by each register The bit assignments are:
• CLRENA Interrupt clear-enable bits. Write: 0: no effect 1: disable interrupt. Read: 0: interrupt disabled 1: interrupt enabled. 31 30 29 28 27 26 25 24 SETENA bits 23 22 21 20 19 18 17 16 SETENA bits 15 14 13 12 11 10 9 8 SETENA bits 7 6 5 4 3 2 1 0 SETENA bits 31 30 29 28 27 26 25 24 CLRENA 23 22 21 20 19 18 17 16 CLRENA 15 14 13 12 11 10 9 8 CLRENA 7 6 5 4 3 2 1 0 CLRENA

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11.20.4 INTERRUPT SET-PENDING REGISTERS

The ISPR0-ISPR1 register forces interrupts into the pending state, and shows which interrupts are pending. See:

• The register summary in Table 11-27 for the register attributes
• Table 11-28 for which interrupts are controlled by each register. The bit assignments are:
• SETPEND Interrupt set-pending bits. Write: 0: no effect. 1: changes interrupt state to pending. Read: 0: interrupt is not pending. 1: interrupt is pending. Writing 1 to the ISPR bit corresponding to:
• An interrupt that is pending has no effect
• A disabled interrupt sets the state of that interrupt to pending

11.20.5 INTERRUPT CLEAR-PENDING REGISTERS

The ICPR0-ICPR1 register removes the pending state from interrupts, and show which interrupts are pending. See:

• The register summary in Table 11-27 for the register attributes
• Table 11-28 for which interrupts are controlled by each register. The bit assignments are:
• CLRPEND Interrupt clear-pending bits. Write: 0: no effect. 1: removes pending state an interrupt. Read: 31 30 29 28 27 26 25 24 SETPEND 23 22 21 20 19 18 17 16 SETPEND 15 14 13 12 11 10 9 8 SETPEND 7 6 5 4 3 2 1 0 SETPEND 31 30 29 28 27 26 25 24 CLRPEND 23 22 21 20 19 18 17 16 CLRPEND 15 14 13 12 11 10 9 8 CLRPEND 7 6 5 4 3 2 1 0 CLRPEND

 2020 Microchip Technology Inc. DS60001614B-page 119 SAM3X8ERT 0: interrupt is not pending. 1: interrupt is pending. Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt.

11.20.6 INTERRUPT ACTIVE BIT REGISTERS

The IABR0-IABR1 register indicates which interrupts are active. See:

• The register summary in Table 11-27 for the register attributes
• Table 11-28 for which interrupts are controlled by each register. The bit assignments are:
• ACTIVE Interrupt active flags: 0: interrupt not active 1: interrupt active. A bit reads as one if the status of the corresponding interrupt is active or active and pending.

11.20.7 INTERRUPT PRIORITY REGISTERS

The IPR0-IPR7 registers provide a 4-bit priority field for each interrupt (See the “Peripheral Identifiers” section of the datasheet for more details). These registers are byte-accessible. See the register summary in Table 11-27 for their attri- butes. Each register holds four priority fields, that map up to four elements in the CMSIS interrupt priority array IP[0] to IP[29], as shown:

11.20.7.1 IPRm

11.20.7.2 IPR4

IP[4m+3] 23 22 21 20 19 18 17 16 IP[4m+2] 15 14 13 12 11 10 9 8 IP[4m+1] 7 6 5 4 3 2 1 0 IP[4m] 31 30 29 28 27 26 25 24 IP[19] 23 22 21 20 19 18 17 16 IP[18] 15 14 13 12 11 10 9 8 IP[17]

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11.20.7.3 IPR3

11.20.7.4 IPR2

11.20.7.5 IPR1

11.20.7.6 IPR0

• Priority, byte offset 3
• Priority, byte offset 2
• Priority, byte offset 1
• Priority, byte offset 0 7 6 5 4 3 2 1 0 IP[16] 31 30 29 28 27 26 25 24 IP[15] 23 22 21 20 19 18 17 16 IP[14] 15 14 13 12 11 10 9 8 IP[13] 7 6 5 4 3 2 1 0 IP[12] 31 30 29 28 27 26 25 24 IP[11] 23 22 21 20 19 18 17 16 IP[10] 15 14 13 12 11 10 9 8 IP[9] 7 6 5 4 3 2 1 0 IP[8] 31 30 29 28 27 26 25 24 IP[7] 23 22 21 20 19 18 17 16 IP[6] 15 14 13 12 11 10 9 8 IP[5] 7 6 5 4 3 2 1 0 IP[4] 31 30 29 28 27 26 25 24 IP[3] 23 22 21 20 19 18 17 16 IP[2] 15 14 13 12 11 10 9 8 IP[1] 7 6 5 4 3 2 1 0 IP[0]

 2020 Microchip Technology Inc. DS60001614B-page 121 SAM3X8ERT Each priority field holds a priority value, 0-15. The lower the value, the greater the priority of the corresponding interrupt. The processor implements only bits[7:4] of each field, bits[3:0] read as zero and ignore writes. See “The CMSIS mapping of the Cortex-M3 NVIC registers” on page 116 for more information about the IP[0] to IP[29] interrupt priority array, that provides the software view of the interrupt priorities. Find the IPR number and byte offset for interrupt N as follows:

• The corresponding IPR number, M, is given by M = N DIV 4
• The byte offset of the required Priority field in this register is N MOD 4, where: - Byte offset 0 refers to register bits[7:0] - Byte offset 1 refers to register bits[15:8] - Byte offset 2 refers to register bits[23:16] - Byte offset 3 refers to register bits[31:24].

11.20.8 SOFTWARE TRIGGER INTERRUPT REGISTER

Write to the STIR to generate a Software Generated Interrupt (SGI). See the register summary in Table 11-27 for the STIR attributes. When the USERSETMPEND bit in the SCR is set to 1, unprivileged software can access the STIR, see “System Control Register” on page 128. Only privileged software can enable unprivileged access to the STIR. The bit assignments are:

• INTID Interrupt ID of the required SGI, in the range 0-239. For example, a value of b000000011 specifies interrupt IRQ3.

11.20.9 LEVEL-SENSITIVE INTERRUPTS

The processor supports level-sensitive interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. When the processor enters the ISR, it automatically removes the pending state from the interrupt, see “Hardware and Software Control of Interrupts” . For a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. This means that the peripheral can hold the interrupt signal asserted until it no longer needs servicing.

11.20.9.1 Hardware and Software Control of Interrupts

The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons:

• The NVIC detects that the interrupt signal is HIGH and the interrupt is not active
• The NVIC detects a rising edge on the interrupt signal
• Software writes to the corresponding interrupt set-pending register bit, see “Interrupt Set-pending Registers” on page 118, or to the STIR to make an SGI pending, see “Software Trigger Interrupt Register” on page 121. A pending interrupt remains pending until one of the following: The processor enters the ISR for the interrupt. This changes the state of the interrupt from pending to active. Then:
• For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the processor to immedi- ately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive. 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved INTID 7 6 5 4 3 2 1 0 INTID

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• If the interrupt signal is not pulsed while the processor is in the ISR, when the processor returns from the ISR the state of the interrupt changes to inactive.
• Software writes to the corresponding interrupt clear-pending register bit. For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive.

11.20.10 NVIC DESIGN HINTS AND TIPS

Ensure software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers. See the individual register descriptions for the supported access sizes. A interrupt can enter pending state even it is disabled. Before programming VTOR to relocate the vector table, ensure the vector table entries of the new vector table are setup for fault handlers and all enabled exception like interrupts. For more information see “Vector Table Offset Register” on page 126.

11.20.10.1 NVIC Programming Hints

Software uses the CPSIE I and CPSID I instructions to enable and disable interrupts. The CMSIS provides the following intrinsic functions for these instructions: void __disable_irq(void) // Disable Interrupts void __enable_irq(void) // Enable Interrupts In addition, the CMSIS provides a number of functions for NVIC control, including: For more information about these functions see the CMSIS documentation.

11.21 System Control Block

The System control block (SCB) provides system implementation information, and system control. This includes con - figuration, control, and reporting of the system exceptions. The system control block registers are: TABLE 11-29: CMSIS FUNCTIONS FOR NVIC CONTROL CMSIS interrupt control function Description void NVIC_SetPriorityGrouping(uint32_t priority_grouping) Set the priority grouping void NVIC_EnableIRQ(IRQn_t IRQn) Enable IRQn void NVIC_DisableIRQ(IRQn_t IRQn) Disable IRQn uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn) Return true if IRQn is pending void NVIC_SetPendingIRQ (IRQn_t IRQn) Set IRQn pending void NVIC_ClearPendingIRQ (IRQn_t IRQn) Clear IRQn pending status uint32_t NVIC_GetActive (IRQn_t IRQn) Return the IRQ number of the active interrupt void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority) Set priority for IRQn uint32_t NVIC_GetPriority (IRQn_t IRQn) Read priority of IRQn void NVIC_SystemReset (void) Reset the system TABLE 11-30: SUMMARY OF THE SYSTEM CONTROL BLOCK REGISTERS Address Name Type Required privilege Reset value Description 0xE000E008 ACTLR RW Privileged 0x00000000 “Auxiliary Control Register” on page 123 0xE000ED00 CPUID RO Privileged 0x412FC230 “CPUID Base Register” on page 124 0xE000ED04 ICSR RW(1) Privileged 0x00000000 “Interrupt Control and State Register” on page 125 0xE000ED08 VTOR RW Privileged 0x00000000 “Vector Table Offset Register” on page 126

 2020 Microchip Technology Inc. DS60001614B-page 123 SAM3X8ERT Note 1: See the register description for more information. 2: A subregister of the CFSR.

11.21.1 THE CMSIS MAPPING OF THE CORTEX-M3 SCB REGISTERS

To improve software efficiency, the CMSIS simplifies the SCB register presentation. In the CMSIS, the byte array SHP[0] to SHP[12] corresponds to the registers SHPR1-SHPR3.

11.21.2 AUXILIARY CONTROL REGISTER

The ACTLR provides disable bits for the following processor functions:

• IT folding
• Write buffer use for accesses to the default memory map
• Interruption of multi-cycle instructions. See the register summary in Table 11-30 for the ACTLR attributes. The bit assignments are: 0xE000ED0C AIRCR RW(1) Privileged 0xFA050000 “Application Interrupt and Reset Control Register” on page 127 0xE000ED10 SCR RW Privileged 0x00000000 “System Control Register” on page 128 0xE000ED14 CCR RW Privileged 0x00000200 “Configuration and Control Register” on page 129 0xE000ED18 SHPR1 RW Privileged 0x00000000 “System Handler Priority Register 1” on page 130 0xE000ED1C SHPR2 RW Privileged 0x00000000 “System Handler Priority Register 2” on page 131 0xE000ED20 SHPR3 RW Privileged 0x00000000 “System Handler Priority Register 3” on page 131 0xE000ED24 SHCRS RW Privileged 0x00000000 “System Handler Control and State Register” on page 131 0xE000ED28 CFSR RW Privileged 0x00000000 “Configurable Fault Status Register” on page 133 0xE000ED28 MMSR(2) RW Privileged 0x00 “Memory Management Fault Address Register” on page 137 0xE000ED29 BFSR(2) RW Privileged 0x00 “Bus Fault Status Register” on page 134 0xE000ED2A UFSR(2) RW Privileged 0x0000 “Usage Fault Status Register” on page 135 0xE000ED2C HFSR RW Privileged 0x00000000 “Hard Fault Status Register” on page 136 0xE000ED34 MMAR RW Privileged Unknown “Memory Management Fault Address Register” on page 137 0xE000ED38 BFAR RW Privileged Unknown “Bus Fault Address Register” on page 137 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 TABLE 11-30: SUMMARY OF THE SYSTEM CONTROL BLOCK REGISTERS (CONTINUED) Address Name Type Required privilege Reset value Description

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• DISFOLD When set to 1, disables IT folding. see “About IT Folding” on page 124 for more information.
• DISDEFWBUF When set to 1, disables write buffer use during default memory map accesses. This causes all bus faults to be precise bus faults but decreases performance because any store to memory must complete before the processor can execute the next instruction. This bit only affects write buffers implemented in the Cortex-M3 processor.
• DISMCYCINT When set to 1, disables interruption of load multiple and store multiple instructions. This increases the interrupt latency of the processor because any LDM or STM must complete before the processor can stack the current state and enter the interrupt handler.

11.21.2.1 About IT Folding

In some situations, the processor can start executing the first instruction in an IT block while it is still executing the IT instruction. This behavior is called IT folding, and improves performance, However, IT folding can cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit to 1 before executing the task, to disable IT folding.

11.21.3 CPUID BASE REGISTER

The CPUID register contains the processor part number, version, and implementation information. See the register sum- mary in Table 11-30 for its attributes. The bit assignments are:

• Implementer Implementer code: 0x41 = ARM
• Variant Variant number, the r value in the rnpn product revision identifier: 0x2 = r2p0
• Constant Reads as 0xF
• PartNo Part number of the processor: 0xC23 = Cortex-M3
• Revision Revision number, the p value in the rnpn product revision identifier: 0x0 = r2p0 Reserved 7 6 5 4 3 2 1 0 Reserved DISFOLD DISDEFWBUF DISMCYCINT 31 30 29 28 27 26 25 24 Implementer 23 22 21 20 19 18 17 16 Variant Constant 15 14 13 12 11 10 9 8 PartNo 7 6 5 4 3 2 1 0 PartNo Revision

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11.21.4 INTERRUPT CONTROL AND STATE REGISTER

The ICSR:

• Provides: - Set-pending and clear-pending bits for the PendSV and SysTick exceptions
• Indicates: - The exception number of the exception being processed - Whether there are preempted active exceptions - The exception number of the highest priority pending exception - Whether any interrupts are pending. See the register summary in Table 11-30, and the Type descriptions in Table 11-33, for the ICSR attributes. The bit assignments are:
• PENDSVSET RW PendSV set-pending bit. Write: 0: no effect 1: changes PendSV exception state to pending. Read: 0: PendSV exception is not pending 1: PendSV exception is pending. Writing 1 to this bit is the only way to set the PendSV exception state to pending.
• PENDSVCLR WO PendSV clear-pending bit. Write: 0: no effect 1: removes the pending state from the PendSV exception.
• PENDSTSET RW SysTick exception set-pending bit. Write: 0: no effect 1: changes SysTick exception state to pending. 31 30 29 28 27 26 25 24 Reserved Reserved PENDSV SET PENDSV CLR PENDSTSET PENDSTCLR Reserved 23 22 21 20 19 18 17 16 Reserved for Debug ISRPEND ING VECTPENDING 15 14 13 12 11 10 9 8 VECTPENDING RETTOB ASE Reserved VECTACTIV E 7 6 5 4 3 2 1 0 VECTACTIVE

DS60001614B-page 126  2020 Microchip Technology Inc. Read: 0: SysTick exception is not pending 1: SysTick exception is pending.

• PENDSTCLR WO SysTick exception clear-pending bit. Write: 0: no effect 1: removes the pending state from the SysTick exception. This bit is WO. On a register read its value is Unknown.
• Reserved for Debug use RO This bit is reserved for Debug use and reads-as-zero when the processor is not in Debug.
• ISRPENDING RO Interrupt pending flag, excluding Faults: 0: interrupt not pending 1: interrupt pending.
• VECTPENDING RO Indicates the exception number of the highest priority pending enabled exception: 0: no pending exceptions Nonzero = the exception number of the highest priority pending enabled exception. The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register.
• RETTOBASE RO Indicates whether there are preempted active exceptions: 0: there are preempted active exceptions to execute 1: there are no active exceptions, or the currently-executing exception is the only active exception.
• VECTACTIVE RO Contains the active exception number: 0: Thread mode Nonzero = The exception number (Note:) of the currently active exception. Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Clear-Enable, Set-Enable, Clear-Pending, Set-Pending, or Priority Registers, see “Interrupt Program Status Register” on page 51. When you write to the ICSR, the effect is Unpredictable if you:
• Write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit
• Write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit. Note: This is the same value as IPSR bits [8:0] see “Interrupt Program Status Register” on page 51.

11.21.5 VECTOR TABLE OFFSET REGISTER

The VTOR indicates the offset of the vector table base address from memory address 0x00000000. See the register summary in Table 11-30 for its attributes.

 2020 Microchip Technology Inc. DS60001614B-page 127 SAM3X8ERT The bit assignments are:

• TBLOFF Vector table base offset field. It contains bits[29:7] of the offset of the table base from the bottom of the memory map. Bit[29] determines whether the vector table is in the code or SRAM memory region: 0: code 1: SRAM. Bit[29] is sometimes called the TBLBASE bit. When setting TBLOFF, you must align the offset to the number of exception entries in the vector table. The minimum alignment is 32 words, enough for up to 16 interrupts. For more interrupts, adjust the alignment by rounding up to the next power of two. For example, if you require 21 interrupts, the alignment must be on a 64-word boundary because the required table size is 37 words, and the next power of two is 64. Table alignment requirements mean that bits[6:0] of the table offset are always zero.

11.21.6 APPLICATION INTERRUPT AND RESET CONTROL REGISTER

The AIRCR provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. See the register summary in Table 11-30 and Table 11-33 for its attributes. To write to this register, you must write 0x05FA to the VECTKEY field, otherwise the processor ignores the write. The bit assignments are:

• VECTKEYSTAT Register Key: Reads as 0xFA05
• VECTKEY Register key: On writes, write 0x5FA to VECTKEY , otherwise the write is ignored.
• ENDIANESS RO Data endianness bit: 0: Little-endian ENDIANESS is set from the BIGEND configuration signal during reset. 31 30 29 28 27 26 25 24 Reserved TBLOFF 23 22 21 20 19 18 17 16 TBLOFF 15 14 13 12 11 10 9 8 TBLOFF 7 6 5 4 3 2 1 0 TBLOFF Reserved 31 30 29 28 27 26 25 24 On Read: VECTKEYSTAT, On Write: VECTKEY 23 22 21 20 19 18 17 16 On Read: VECTKEYSTAT, On Write: VECTKEY 15 14 13 12 11 10 9 8 ENDIA- NESS Reserved PRIGROUP 7 6 5 4 3 2 1 0 Reserved SYSRESE- TREQ VECTCLR- ACTIVE VEC- TRESET

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• PRIGROUP R/W Interrupt priority grouping field. This field determines the split of group priority from subpriority, see “Binary Point” on page 128.
• SYSRESETREQ WO System reset request: 0: no effect 1: asserts a proc_reset_signal. This is intended to force a large system reset of all major components except for debug. This bit reads as 0.
• VECTCLRACTIVE WO Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable.
• VECTRESET WO Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable.

11.21.6.1 Binary Point

The PRIGROUP field indicates the position of the binary point that splits the PRI_n fields in the Interrupt Priority Regis- ters into separate group priority and subpriority fields. Table 11-31 shows how the PRIGROUP value controls this split. Determining preemption of an exception uses only the group priority field, see “Interrupt priority grouping” on page 66.

11.21.7 SYSTEM CONTROL REGISTER

The SCR controls features of entry to and exit from low power state. See the register summary in Table 11-30 for its attributes. The bit assignments are: TABLE 11-31: PRIORITY GROUPING Interrupt priority level value, PRI_N[7:0] Number of PRIGROUP Binary point (1) 1. PRI_n[7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a subpriority field bit. Group priority bits Subpriority bits Group priorities Sub-priorities b011 bxxxx.0000 [7:4] None 16 1 b100 bxxx.y0000 [7:5] [4] 8 2 b101 bxx.yy0000 [7:6] [5:4] 4 4 b110 bx.yyy0000 [7] [6:4] 2 8 b111 b.yyyy0000 None [7:4] 1 16 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved

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• SEVONPEND Send Event on Pending bit: 0: only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 1: enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event.
• SLEEPDEEP Controls whether the processor uses sleep or deep sleep as its low power mode: 0: sleep 1: deep sleep.
• SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0: do not sleep when returning to Thread mode. 1: enter sleep, or deep sleep, on return from an ISR. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.

11.21.8 CONFIGURATION AND CONTROL REGISTER

The CCR controls entry to Thread mode and enables:

• The handlers for hard fault and faults escalated by FAULTMASK to ignore bus faults
• Trapping of divide by zero and unaligned accesses
• Access to the STIR by unprivileged software, see “Software Trigger Interrupt Register” on page 121. See the register summary in Table 11-30 for the CCR attributes. The bit assignments are:
• STKALIGN Indicates stack alignment on exception entry: 0: 4-byte aligned 1: 8-byte aligned. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment.
• BFHFNMIGN Enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. This applies to the hard fault and FAULTMASK escalated handlers: 0: data bus faults caused by load and store instructions cause a lock-up 7 6 5 4 3 2 1 0 Reserved SEVONPEND Reserved SLEEPDEEP SLEEONEXIT Reserved 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved STKALIGN BFHFN- MIGN 7 6 5 4 3 2 1 0 Reserved DIV_0_TR P UNALIGN _TRP Reserved USERSET- MPEND NONBASE- THRDENA

DS60001614B-page 130  2020 Microchip Technology Inc. 1: handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them.

• DIV_0_TRP Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0: 0: do not trap divide by 0 1: trap divide by 0. When this bit is set to 0,a divide by zero returns a quotient of 0.
• UNALIGN_TRP Enables unaligned access traps: 0: do not trap unaligned halfword and word accesses 1: trap unaligned halfword and word accesses. If this bit is set to 1, an unaligned access generates a usage fault. Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1.
• USERSETMPEND Enables unprivileged software access to the STIR, see “Software Trigger Interrupt Register” on page 121: 0: disable 1: enable.
• NONEBASETHRDENA Indicates how the processor enters Thread mode: 0: processor can enter Thread mode only when no exception is active. 1: processor can enter Thread mode from any level under the control of an EXC_RETURN value, see “Exception Return” on page 67.

11.21.9 SYSTEM HANDLER PRIORITY REGISTERS

The SHPR1-SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have configurable priority. SHPR1-SHPR3 are byte accessible. See the register summary in Table 11-30 for their attributes. The system fault handlers and the priority field and register for each handler are: Each PRI_N field is 8 bits wide, but the processor implements only bits[7:4] of each field, and bits[3:0] read as zero and ignore writes.

11.21.9.1 System Handler Priority Register 1

The bit assignments are: TABLE 11-32: SYSTEM FAULT HANDLER PRIORITY FIELDS Handler Field Register description Memory management fault PRI_4 “System Handler Priority Register 1” on page 130 Bus fault PRI_5 Usage fault PRI_6 SVCall PRI_11 “System Handler Priority Register 2” on page 131 PendSV PRI_14 “System Handler Priority Register 3” on page 131 SysTick PRI_15 31 30 29 28 27 26 25 24 PRI_7: Reserved 23 22 21 20 19 18 17 16 PRI_6

 2020 Microchip Technology Inc. DS60001614B-page 131 SAM3X8ERT

• PRI_7 Reserved
• PRI_6 Priority of system handler 6, usage fault
• PRI_5 Priority of system handler 5, bus fault
• PRI_4 Priority of system handler 4, memory management fault

11.21.9.2 System Handler Priority Register 2

The bit assignments are:

• PRI_11 Priority of system handler 11, SVCall

11.21.9.3 System Handler Priority Register 3

The bit assignments are:

• PRI_15 Priority of system handler 15, SysTick exception
• PRI_14 Priority of system handler 14, PendSV

11.21.10 SYSTEM HANDLER CONTROL AND STATE REGISTER

The SHCSR enables the system handlers, and indicates:

• The pending status of the bus fault, memory management fault, and SVC exceptions
• The active status of the system handlers 15 14 13 12 11 10 9 8 PRI_5 7 6 5 4 3 2 1 0 PRI_4 31 30 29 28 27 26 25 24 PRI_11 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved 31 30 29 28 27 26 25 24 PRI_15 23 22 21 20 19 18 17 16 PRI_14 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved

DS60001614B-page 132  2020 Microchip Technology Inc. See the register summary in Table 11-30 for the SHCSR attributes. The bit assignments are:

• USGFAULTENA Usage fault enable bit, set to 1 to enable (1)
• BUSFAULTENA Bus fault enable bit, set to 1 to enable(3)
• MEMFAULTENA Memory management fault enable bit, set to 1 to enable(3)
• SVCALLPENDED SVC call pending bit, reads as 1 if exception is pending (2)
• BUSFAULTPENDED Bus fault exception pending bit, reads as 1 if exception is pending(2)
• MEMFAULTPENDED Memory management fault exception pending bit, reads as 1 if exception is pending(2)
• USGFAULTPENDED Usage fault exception pending bit, reads as 1 if exception is pending(2)
• SYSTICKACT SysTick exception active bit, reads as 1 if exception is active (3)
• PENDSVACT PendSV exception active bit, reads as 1 if exception is active
• MONITORACT Debug monitor active bit, reads as 1 if Debug monitor is active
• SVCALLACT SVC call active bit, reads as 1 if SVC call is active
• USGFAULTACT Usage fault exception active bit, reads as 1 if exception is active
• BUSFAULTACT Bus fault exception active bit, reads as 1 if exception is active
• MEMFAULTACT Memory management fault exception active bit, reads as 1 if exception is active 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved USGFAULT ENA BUS- FAULTENA MEM- FAULTENA 15 14 13 12 11 10 9 8 SVCALL- PENDED BUS- FAULT- PENDED MEM- FAULT- PENDED USGFAUL TPENDED SYSTICK- ACT PENDS- VACT Reserved MONITO- RACT 7 6 5 4 3 2 1 0 SVCAL- LAVCT Reserved USGFAULT ACT Reserved BUS- FAULTACT MEM- FAULTACT 1. Enable bits, set to 1 to enable the exception, or set to 0 to disable the exception. 2. Pending bits, read as 1 if the exception is pending, or as 0 if it is not pending. You can write to these bits to change the pending status of the exceptions. 3. Active bits, read as 1 if the exception is active, or as 0 if it is not active. You can write to these bits to change the active status of the exceptions, but see the Caution in this section.

 2020 Microchip Technology Inc. DS60001614B-page 133 SAM3X8ERT If you disable a system handler and the corresponding fault occurs, the processor treats the fault as a hard fault. You can write to this register to change the pending or active status of system exceptions. An OS kernel can write to the active bits to perform a context switch that changes the current exception type.

• Software that changes the value of an active bit in this register without correct adjustment to the stacked content can cause the processor to generate a fault exception. Ensure software that writes to this register retains and sub- sequently restores the current active status.
• After you have enabled the system handlers, if you have to change the value of a bit in this register you must use a read-modify-write procedure to ensure that you change only the required bit.

11.21.11 CONFIGURABLE FAULT STATUS REGISTER

The CFSR indicates the cause of a memory management fault, bus fault, or usage fault. See the register summary in Table 11-30 for its attributes. The bit assignments are: The following subsections describe the subregisters that make up the CFSR:

• “Memory Management Fault Status Register” on page 133
• “Bus Fault Status Register” on page 134
• “Usage Fault Status Register” on page 135. The CFSR is byte accessible. You can access the CFSR or its subregisters as follows:
• Access the complete CFSR with a word access to 0xE000ED28
• Access the MMFSR with a byte access to 0xE000ED28
• Access the MMFSR and BFSR with a halfword access to 0xE000ED28
• Access the BFSR with a byte access to 0xE000ED29
• Access the UFSR with a halfword access to 0xE000ED2A.

11.21.11.1 Memory Management Fault Status Register

The flags in the MMFSR indicate the cause of memory access faults. The bit assignments are:

• MMARVALID Memory Management Fault Address Register (MMAR) valid flag: 0: value in MMAR is not a valid fault address 1: MMAR holds a valid fault address. If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set this bit to 0. This prevents problems on return to a stacked active memory management fault handler whose MMAR value has been overwritten.
• MSTKERR Memory manager fault on stacking for exception entry: 0: no stacking fault 1: stacking for an exception entry has caused one or more access violations. When this bit is 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The proces- sor has not written a fault address to the MMAR. 31 30 29 28 27 26 25 24 Usage Fault Status Register: UFSR 23 22 21 20 19 18 17 16 Usage Fault Status Register: UFSR 15 14 13 12 11 10 9 8 Bus Fault Status Register: BFSR 7 6 5 4 3 2 1 0 Memory Management Fault Status Register: MMFSR 7 6 5 4 3 2 1 0 MMARVALID Reserved MSTKERR MUNSTKERR Reserved DACCVIOL IACCVIOL

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• MUNSTKERR Memory manager fault on unstacking for a return from exception: 0: no unstacking fault 1: unstack for an exception return has caused one or more access violations. This fault is chained to the handler. This means that when this bit is 1, the original return stack is still present. The pro- cessor has not adjusted the SP from the failing return, and has not performed a new save. The processor has not written a fault address to the MMAR.
• DACCVIOL Data access violation flag: 0: no data access violation fault 1: the processor attempted a load or store at a location that does not permit the operation. When this bit is 1, the PC value stacked for the exception return points to the faulting instruction. The processor has loaded the MMAR with the address of the attempted access.
• IACCVIOL Instruction access violation flag: 0: no instruction access violation fault 1: the processor attempted an instruction fetch from a location that does not permit execution. This fault occurs on any access to an XN region, even when the MPU is disabled or not present. When this bit is 1, the PC value stacked for the exception return points to the faulting instruction. The processor has not written a fault address to the MMAR.

11.21.11.2 Bus Fault Status Register

The flags in the BFSR indicate the cause of a bus access fault. The bit assignments are:

• BFARVALID Bus Fault Address Register (BFAR) valid flag: 0: value in BFAR is not a valid fault address 1: BFAR holds a valid fault address. The processor sets this bit to 1 after a bus fault where the address is known. Other faults can set this bit to 0, such as a memory management fault occurring later. If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set this bit to 0. This prevents problems if returning to a stacked active bus fault handler whose BFAR value has been overwritten.
• STKERR Bus fault on stacking for exception entry: 0: no stacking fault 1: stacking for an exception entry has caused one or more bus faults. When the processor sets this bit to 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor does not write a fault address to the BFAR.
• UNSTKERR Bus fault on unstacking for a return from exception: 0: no unstacking fault 1: unstack for an exception return has caused one or more bus faults. This fault is chained to the handler. This means that when the processor sets this bit to 1, the original return stack is still present. The processor does not adjust the SP from the failing return, does not performed a new save, and does not write a fault address to the BFAR. 7 6 5 4 3 2 1 0 BFRVALID Reserved STKERR UNSTKERR IMPRECISERR PRECISERR IBUSERR

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• IMPRECISERR Imprecise data bus error: 0: no imprecise data bus error 1: a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. When the processor sets this bit to 1, it does not write a fault address to the BFAR. This is an asynchronous fault. Therefore, if it is detected when the priority of the current process is higher than the bus fault priority, the bus fault becomes pending and becomes active only when the processor returns from all higher priority processes. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects both IMPRECISERR set to 1 and one of the precise fault status bits set to 1.
• PRECISERR Precise data bus error: 0: no precise data bus error 1: a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. When the processor sets this bit is 1, it writes the faulting address to the BFAR.
• IBUSERR Instruction bus error: 0: no instruction bus error 1: instruction bus error. The processor detects the instruction bus error on prefetching an instruction, but it sets the IBUSERR flag to 1 only if it attempts to issue the faulting instruction. When the processor sets this bit is 1, it does not write a fault address to the BFAR.

11.21.11.3 Usage Fault Status Register

The UFSR indicates the cause of a usage fault. The bit assignments are:

• DIVBYZERO Divide by zero usage fault: 0: no divide by zero fault, or divide by zero trapping not enabled 1: the processor has executed an SDIV or UDIV instruction with a divisor of 0. When the processor sets this bit to 1, the PC value stacked for the exception return points to the instruction that per - formed the divide by zero. Enable trapping of divide by zero by setting the DIV_0_TRP bit in the CCR to 1, see “Configuration and Control Register” on page 129.
• UNALIGNED Unaligned access usage fault: 0: no unaligned access fault, or unaligned access trapping not enabled 1: the processor has made an unaligned memory access. Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the CCR to 1, see “Configuration and Control Register” on page 129. Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of UNALIGN_TRP.
• NOCP No coprocessor usage fault. The processor does not support coprocessor instructions: 15 14 13 12 11 10 9 8 Reserved DIVBYZERO UNALIGNED 7 6 5 4 3 2 1 0 Reserved NOCP INVPC INVSTATE UNDEFINSTR

DS60001614B-page 136  2020 Microchip Technology Inc. 0: no usage fault caused by attempting to access a coprocessor 1: the processor has attempted to access a coprocessor.

• INVPC Invalid PC load usage fault, caused by an invalid PC load by EXC_RETURN: 0: no invalid PC load usage fault 1: the processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid EXC_RETURN value. When this bit is set to 1, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC.
• INVSTATE Invalid state usage fault: 0: no invalid state usage fault 1: the processor has attempted to execute an instruction that makes illegal use of the EPSR. When this bit is set to 1, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the EPSR. This bit is not set to 1 if an undefined instruction uses the EPSR.
• UNDEFINSTR Undefined instruction usage fault: 0: no undefined instruction usage fault 1: the processor has attempted to execute an undefined instruction. When this bit is set to 1, the PC value stacked for the exception return points to the undefined instruction. An undefined instruction is an instruction that the processor cannot decode. The UFSR bits are sticky. This means as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is cleared to 0 only by writing 1 to that bit, or by a reset.

11.21.12 HARD FAULT STATUS REGISTER

The HFSR gives information about events that activate the hard fault handler. See the register summary in Table 11-30 for its attributes. This register is read, write to clear. This means that bits in the register read normally, but writing 1 to any bit clears that bit to 0. The bit assignments are:

• DEBUGEVT Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable.
• FORCED Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either because of priority or because it is disabled: 0: no forced hard fault 1: forced hard fault. When this bit is set to 1, the hard fault handler must read the other fault status registers to find the cause of the fault. 31 30 29 28 27 26 25 24 DEBUGEVT FORCED Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved VECTTBL Reserved

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• VECTTBL Indicates a bus fault on a vector table read during exception processing: 0: no bus fault on vector table read 1: bus fault on vector table read. This error is always handled by the hard fault handler. When this bit is set to 1, the PC value stacked for the exception return points to the instruction that was preempted by the exception. The HFSR bits are sticky. This means as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is cleared to 0 only by writing 1 to that bit, or by a reset.

11.21.13 MEMORY MANAGEMENT FAULT ADDRESS REGISTER

The MMFAR contains the address of the location that generated a memory management fault. See the register sum - mary in Table 11-30 for its attributes. The bit assignments are:

• ADDRESS When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the mem- ory management fault When an unaligned access faults, the address is the actual address that faulted. Because a single read or write instruc- tion can be split into multiple aligned accesses, the fault address can be any address in the range of the requested access size. Flags in the MMFSR indicate the cause of the fault, and whether the value in the MMFAR is valid. See “Memory Man- agement Fault Status Register” on page 133.

11.21.14 BUS FAULT ADDRESS REGISTER

The BFAR contains the address of the location that generated a bus fault. See the register summary in Table 11-30 for its attributes. The bit assignments are:

• ADDRESS When the BFARVALID bit of the BFSR is set to 1, this field holds the address of the location that generated the bus fault When an unaligned access faults the address in the BFAR is the one requested by the instruction, even if it is not the address of the fault. Flags in the BFSR indicate the cause of the fault, and whether the value in the BFAR is valid. See “Bus Fault Status Register” on page 134. 31 30 29 28 27 26 25 24 ADDRESS 23 22 21 20 19 18 17 16 ADDRESS 15 14 13 12 11 10 9 8 ADDRESS 7 6 5 4 3 2 1 0 ADDRESS 31 30 29 28 27 26 25 24 ADDRESS 23 22 21 20 19 18 17 16 ADDRESS 15 14 13 12 11 10 9 8 ADDRESS 7 6 5 4 3 2 1 0 ADDRESS

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11.21.15 SYSTEM CONTROL BLOCK DESIGN HINTS AND TIPS

Ensure software uses aligned accesses of the correct size to access the system control block registers:

• Except for the CFSR and SHPR1-SHPR3, it must use aligned word accesses
• For the CFSR and SHPR1-SHPR3 it can use byte or aligned halfword or word accesses. The processor does not support unaligned accesses to system control block registers. In a fault handler. to determine the true faulting address:
• Read and save the MMFAR or BFAR value.
• Read the MMARVALID bit in the MMFSR, or the BFARVALID bit in the BFSR. The MMFAR or BFAR address is valid only if this bit is 1. Software must follow this sequence because another higher priority exception might change the MMFAR or BFAR value. For example, if a higher priority handler preempts the current fault handler, the other fault might change the MMFAR or BFAR value.

11.22 System Timer, SysTick

The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps to) the value in the LOAD register on the next clock edge, then counts down on subsequent clocks. When the processor is halted for debugging the counter does not decrement. The system timer registers are:

11.22.1 SYSTICK CONTROL AND STATUS REGISTER

The SysTick CTRL register enables the SysTick features. See the register summary in Table 11-33 for its attributes. The bit assignments are:

• COUNTFLAG Returns 1 if timer counted to 0 since last time this was read.
• CLKSOURCE Indicates the clock source: 0: MCK/8 1: MCK TABLE 11-33: SYSTEM TIMER REGISTERS SUMMARY Address Name Type Required privilege Reset value Description 0xE000E010 CTRL RW Privileged 0x00000004 “SysTick Control and Status Register” on page 138 0xE000E014 LOAD RW Privileged 0x00000000 “SysTick Reload Value Register” on page 139 0xE000E018 VAL RW Privileged 0x00000000 “SysTick Current Value Register” on page 139 0xE000E01C CALIB RO Privileged 0x0002904 (1) 1. SysTick calibration value. “SysTick Calibration Value Register” on page 140 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved COUNTFLAG 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CLKSOURCE TICKINT ENABLE

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• TICKINT Enables SysTick exception request: 0: counting down to zero does not assert the SysTick exception request 1: counting down to zero to asserts the SysTick exception request. Software can use COUNTFLAG to determine if SysTick has ever counted to zero.
• ENABLE Enables the counter: 0: counter disabled 1: counter enabled. When ENABLE is set to 1, the counter loads the RELOAD value from the LOAD register and then counts down. On reaching 0, it sets the COUNTFLAG to 1 and optionally asserts the SysTick depending on the value of TICKINT. It then loads the RELOAD value again, and begins counting.

11.22.2 SYSTICK RELOAD VALUE REGISTER

The LOAD register specifies the start value to load into the VAL register. See the register summary in Table 11-33 for its attributes. The bit assignments are:

• RELOAD Value to load into the VAL register when the counter is enabled and when it reaches 0, see “Calculating the RELOAD Value” .

11.22.2.1 Calculating the RELOAD Value

The RELOAD value can be any value in the range 0x00000001-0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick exception request and COUNTFLAG are activated when counting from 1 to 0. The RELOAD value is calculated according to its use:

• To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For exam- ple, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.
• To deliver a single SysTick interrupt after a delay of N processor clock cycles, use a RELOAD of value N. For example, if a SysTick interrupt is required after 400 clock pulses, set RELOAD to 400.

11.22.3 SYSTICK CURRENT VALUE REGISTER

The VAL register contains the current value of the SysTick counter. See the register summary in Table 11-33 for its attri- butes. The bit assignments are: 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 RELOAD 15 14 13 12 11 10 9 8 RELOAD 7 6 5 4 3 2 1 0 -RELOAD 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CURRENT 15 14 13 12 11 10 9 8 CURRENT

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• CURRENT Reads return the current value of the SysTick counter. A write of any value clears the field to 0, and also clears the SysTick CTRL.COUNTFLAG bit to 0.

11.22.4 SYSTICK CALIBRATION VALUE REGISTER

The CALIB register indicates the SysTick calibration properties. See the register summary in Table 11-33 for its attri - butes. The bit assignments are:

• NOREF Reads as zero.
• SKEW Reads as zero
• TENMS Read as 0x0002904. The SysTick calibration value is fixed at 0x0002904 (10500), which allows the generation of a time base of 1 ms with SysTick clock at 10.5 MHz (84/8 = 10.5 MHz)

11.22.5 SYSTICK DESIGN HINTS AND TIPS

The SysTick counter runs on the processor clock. If this clock signal is stopped for low power mode, the SysTick counter stops. Ensure software uses aligned word accesses to access the SysTick registers.

11.23 Memory Protection Unit

This section describes the Memory protection unit (MPU). The MPU divides the memory map into a number of regions, and defines the location, size, access permissions, and memory attributes of each region. It supports:

• Independent attribute settings for each region
• Overlapping regions
• Export of memory attributes to the system. The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 MPU defines:
• Eight separate memory regions, 0-7
• A background region. When memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7. The background region has the same memory access attributes as the default memory map, but is accessible from priv- ileged software only. The Cortex-M3 MPU memory map is unified. This means instruction accesses and data accesses have same region settings. 7 6 5 4 3 2 1 0 CURRENT 31 30 29 28 27 26 25 24 NOREF SKEW Reserved 23 22 21 20 19 18 17 16 TENMS 15 14 13 12 11 10 9 8 TENMS 7 6 5 4 3 2 1 0 TENMS

 2020 Microchip Technology Inc. DS60001614B-page 141 SAM3X8ERT If a program accesses a memory location that is prohibited by the MPU, the processor generates a memory manage - ment fault. This causes a fault exception, and might cause termination of the process in an OS environment. In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection. Configuration of MPU regions is based on memory types, see “Memory regions, types and attributes” on page 55. Table 11-34 shows the possible MPU region attributes. These include Share ability and cache behavior attributes that are not relevant to most microcontroller implementations. See “MPU Configuration for a Microcontroller” on page 149 for guidelines for programming such an implementation. Use the MPU registers to define the MPU regions and their attributes. The MPU registers are:

11.23.1 MPU TYPE REGISTER

The TYPE register indicates whether the MPU is present, and if so, how many regions it supports. See the register sum- mary in Table 11-35 for its attributes. The bit assignments are: TABLE 11-34: MEMORY ATTRIBUTES SUMMARY Memory type Shareability Other attributes Description Strongly- ordered - - All accesses to Strongly-ordered memory occur in program order. All Strongly-ordered regions are assumed to be shared. Device Shared - Memory-mapped peripherals that several processors share. Non-shared - Memory-mapped peripherals that only a single processor uses. Normal Shared Normal memory that is shared between several processors. Non-shared Normal memory that only a single processor uses. TABLE 11-35: MPU REGISTERS SUMMARY Address Name Type Required privilege Reset value Description 0xE000ED90 TYPE RO Privileged 0x00000800 “MPU Type Register” on page 141 0xE000ED94 CTRL RW Privileged 0x00000000 “MPU Control Register” on page 142 0xE000ED98 RNR RW Privileged 0x00000000 “MPU Region Number Register” on page 143 0xE000ED9C RBAR RW Privileged 0x00000000 “MPU Region Base Address Register” on page 143 0xE000EDA0 RASR RW Privileged 0x00000000 “MPU Region Attribute and Size Register” on page 144 0xE000EDA4 RBAR _A1 RW Privileged 0x00000000 Alias of RBAR, see “MPU Region Base Address Reg- ister” on page 143 0xE000EDA8 RAS- R_A1 RW Privileged 0x00000000 Alias of RASR, see “MPU Region Attribute and Size Register” on page 144 0xE000EDAC RBAR _A2 RW Privileged 0x00000000 Alias of RBAR, see “MPU Region Base Address Reg- ister” on page 143 0xE000EDB0 RAS- R_A2 RW Privileged 0x00000000 Alias of RASR, see “MPU Region Attribute and Size Register” on page 144 0xE000EDB4 RBAR _A3 RW Privileged 0x00000000 Alias of RBAR, see “MPU Region Base Address Reg- ister” on page 143 0xE000EDB8 RAS- R_A3 RW Privileged 0x00000000 Alias of RASR, see “MPU Region Attribute and Size Register” on page 144 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 IREGION

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• IREGION Indicates the number of supported MPU instruction regions. Always contains 0x00. The MPU memory map is unified and is described by the DREGION field.
• DREGION Indicates the number of supported MPU data regions: 0x08 = Eight MPU regions.
• SEPARATE Indicates support for unified or separate instruction and date memory maps: 0: unified.

11.23.2 MPU CONTROL REGISTER

The MPU CTRL register:

• Enables the MPU
• Enables the default memory map background region
• Enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated han- dlers. See the register summary in Table 11-35 for the MPU CTRL attributes. The bit assignments are:
• PRIVDEFENA Enables privileged software access to the default memory map: 0: If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. 1: If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has pri- ority over this default map. If the MPU is disabled, the processor ignores this bit.
• HFNMIENA Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers. When the MPU is enabled: 0: MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit 1: the MPU is enabled during hard fault, NMI, and FAULTMASK handlers. When the MPU is disabled, if this bit is set to 1 the behavior is Unpredictable. 15 14 13 12 11 10 9 8 DREGION 7 6 5 4 3 2 1 0 Reserved SEPARATE 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved PRIVDEFENA HFNMIEN A ENABLE

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• ENABLE Enables the MPU: 0: MPU disabled 1: MPU enabled. When ENABLE and PRIVDEFENA are both set to 1: For privileged accesses, the default memory map is as described in “Memory Model” on page 55. Any access by privi- leged software that does not address an enabled memory region behaves as defined by the default memory map. Any access by unprivileged software that does not address an enabled memory region causes a memory management fault. XN and Strongly-ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit. When the ENABLE bit is set to 1, at least one region of the memory map must be enabled for the system to function unless the PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit is set to 1 and no regions are enabled, then only privi- leged software can operate. When the ENABLE bit is set to 0, the system uses the default memory map. This has the same memory attributes as if the MPU is not implemented, see Table 11-34. The default memory map applies to accesses from both privileged and unprivileged software. When the MPU is enabled, accesses to the System Control Space and vector table are always permitted. Other areas are accessible based on regions and whether PRIVDEFENA is set to 1. Unless HFNMIENA is set to 1, the MPU is not enabled when the processor is executing the handler for an exception with priority –1 or –2. These priorities are only possible when handling a hard fault or NMI exception, or when FAULT- MASK is enabled. Setting the HFNMIENA bit to 1 enables the MPU when operating with these two priorities.

11.23.3 MPU REGION NUMBER REGISTER

The RNR selects which memory region is referenced by the RBAR and RASR registers. See the register summary in Table 11-35 for its attributes. The bit assignments are:

• REGION Indicates the MPU region referenced by the RBAR and RASR registers. The MPU supports 8 memory regions, so the permitted values of this field are 0-7. Normally, you write the required region number to this register before accessing the RBAR or RASR. However you can change the region number by writing to the RBAR with the VALID bit set to 1, see “MPU Region Base Address Register” on page 143. This write updates the value of the REGION field.

11.23.4 MPU REGION BASE ADDRESS REGISTER

The RBAR defines the base address of the MPU region selected by the RNR, and can update the value of the RNR. See the register summary in Table 11-35 for its attributes. Write RBAR with the VALID bit set to 1 to change the current region number and update the RNR. The bit assignments are: 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 REGION 31 30 29 28 27 26 25 24 ADDR 23 22 21 20 19 18 17 16

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• ADDR Region base address field. The value of N depends on the region size. For more information see “The ADDR field” .
• VALID MPU Region Number valid bit: Write: 0: RNR not changed, and the processor: updates the base address for the region specified in the RNR ignores the value of the REGION field 1: the processor: updates the value of the RNR to the value of the REGION field updates the base address for the region specified in the REGION field. Always reads as zero.
• REGION MPU region field: For the behavior on writes, see the description of the VALID field. On reads, returns the current region number, as specified by the RNR. The ADDR field The ADDR field is bits[31:N] of the RBAR. The region size, as specified by the SIZE field in the RASR, defines the value of N: N = Log2(Region size in bytes), If the region size is configured to 4GB, in the RASR, there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x00000000. The base address is aligned to the size of the region. For example, a 64KB region must be aligned on a multiple of 64KB, for example, at 0x00010000 or 0x00020000.

11.23.5 MPU REGION ATTRIBUTE AND SIZE REGISTER

The RASR defines the region size and memory attributes of the MPU region specified by the RNR, and enables that region and any subregions. See the register summary in Table 11-35 for its attributes. RASR is accessible using word or halfword accesses:

• the most significant halfword holds the region attributes
• the least significant halfword holds the region size and the region and subregion enable bits. The bit assignments are: ADDR 15 14 13 12 11 10 9 N ADDR N-1 6 5 4 3 2 1 0 Reserved VALID REGION 31 30 29 28 27 26 25 24 Reserved XN Reserved AP 23 22 21 20 19 18 17 16 Reserved TEX S C B 15 14 13 12 11 10 9 8 SRD

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• XN Instruction access disable bit: 0: instruction fetches enabled 1: instruction fetches disabled.
• AP Access permission field, see Table 11-39.
• TEX, C, B Memory access attributes, see Table 11-37.
• S Shareable bit, see Table 11-36.
• SRD Subregion disable bits. For each bit in this field: 0: corresponding sub-region is enabled 1: corresponding sub-region is disabled See “Subregions” on page 148 for more information. Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, write the SRD field as 0x00.
• SIZE Specifies the size of the MPU protection region. The minimum permitted value is 3 (b00010), see See “SIZE Field Val- ues” on page 145 for more information.
• ENABLE Region enable bit. For information about access permission, see “MPU access permission attributes” .

11.23.5.1 SIZE Field Values

The SIZE field defines the size of the MPU memory region specified by the RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. Table 11-36 gives example SIZE values, with the corresponding region size and value of N in the RBAR. 7 6 5 4 3 2 1 0 Reserved SIZE ENABLE TABLE 11-36: EXAMPLE SIZE FIELD VALUES SIZE value Region size Value of N (1) 1. In the RBAR, see “MPU Region Base Address Register” on page 143. Note b00100 (4) 32B 5 Minimum permitted size b01001 (9) 1KB 10 - b10011 (19) 1MB 20 - b11101 (29) 1GB 30 - b11111 (31) 4GB b01100 Maximum possible size

DS60001614B-page 146  2020 Microchip Technology Inc.

11.23.6 MPU ACCESS PERMISSION ATTRIBUTES

This section describes the MPU access permission attributes. The access permission bits, TEX, C, B, S, AP , and XN, of the RASR, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. Table 11-37 shows the encodings for the TEX, C, B, and S access permission bits. Table 11-38 shows the cache policy for memory attribute encodings with a TEX value is in the range 4-7. Table 11-39 shows the AP encodings that define the access permissions for privileged and unprivileged software. TABLE 11-37: TEX, C, B, AND S ENCODING TEX C B S Memory type Shareability Other attributes b000 0 0 x (1) 1. The MPU ignores the value of this bit. Strongly-ordered Shareable - 1 x(1) Device Shareable - 1 0 0 Normal Not shareable Outer and inner write-through. No write allocate.

1 Shareable

1 0 Normal Not shareable Outer and inner write-back. No write allocate. 1 x(1) Reserved encoding - 1 0 x(1) Implementation defined attributes. - 1 0 Normal Not shareable Outer and inner write-back. Write and read allocate. b010 0 0 x(1) Device Not shareable Nonshared Device. 1 x(1) Reserved encoding - 1 x(1) x(1) Reserved encoding - b1BB A A 0 Normal Not shareable TABLE 11-38: CACHE POLICY FOR MEMORY ATTRIBUTE ENCODING Encoding, AA or BB Corresponding cache policy

00 Non-cacheable

01 Write back, write and read allocate

10 Write through, no write allocate

11 Write back, no write allocate

TABLE 11-39: AP ENCODING AP[2:0] Privileged permissions Unprivileged permissions Description

000 No access No access All accesses generate a permission fault

001 RW No access Access from privileged software only

010 RW RO Writes by unprivileged software generate a permission fault

011 RW RW Full access

100 Unpredictable Unpredictable Reserved

 2020 Microchip Technology Inc. DS60001614B-page 147 SAM3X8ERT

11.23.7 MPU MISMATCH

When an access violates the MPU permissions, the processor generates a memory management fault, see “Exceptions and interrupts” on page 54. The MMFSR indicates the cause of the fault. See See “Memory Management Fault Status Register” on page 133. for more information.

11.23.8 UPDATING AN MPU REGION

To update the attributes for an MPU region, update the RNR, RBAR and RASR registers. You can program each register separately, or use a multiple-word write to program all of these registers. You can use the RBAR and RASR aliases to program up to four regions simultaneously using an STM instruction.

11.23.8.1 Updating an MPU Region using Separate Words

Simple code to configure one region: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number STR R4, [R0, #0x4] ; Region Base Address STRH R2, [R0, #0x8] ; Region Size and Enable STRH R3, [R0, #0xA] ; Region Attribute Disable a region before writing new region settings to the MPU if you have previously enabled the region being changed. For example: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number BIC R2, R2, #1 ; Disable STRH R2, [R0, #0x8] ; Region Size and Enable STR R4, [R0, #0x4] ; Region Base Address STRH R3, [R0, #0xA] ; Region Attribute ORR R2, #1 ; Enable STRH R2, [R0, #0x8] ; Region Size and Enable Software must use memory barrier instructions:

• Before MPU setup if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in MPU settings
• After MPU setup if it includes memory transfers that must use the new MPU settings. However, memory barrier instructions are not required if the MPU setup process starts by entering an exception handler, or is followed by an exception return, because the exception entry and exception return mechanism cause memory bar- rier behavior. Software does not need any memory barrier instructions during MPU setup, because it accesses the MPU through the PPB, which is a Strongly-Ordered memory region.

101 RO No access Reads by privileged software only

110 RO RO Read only, by privileged or unprivileged software

111 RO RO Read only, by privileged or unprivileged software

TABLE 11-39: AP ENCODING (CONTINUED) AP[2:0] Privileged permissions Unprivileged permissions Description

DS60001614B-page 148  2020 Microchip Technology Inc. For example, if you want all of the memory access behavior to take effect immediately after the programming sequence, use a DSB instruction and an ISB instruction. A DSB is required after changing MPU settings, such as at the end of context switch. An ISB is required if the code that programs the MPU region or regions is entered using a branch or call. If the programming sequence is entered using a return from exception, or by taking an exception, then you do not require an ISB.

11.23.8.2 Updating an MPU Region using Multi-word Writes

You can program directly using multi-word writes, depending on how the information is divided. Consider the following reprogramming: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPU_RNR ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number STR R2, [R0, #0x4] ; Region Base Address STR R3, [R0, #0x8] ; Region Attribute, Size and Enable Use an STM instruction to optimize this: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPU_RNR ; 0xE000ED98, MPU region number register STM R0, {R1-R3} ; Region Number, address, attribute, size and enable You can do this in two words for pre-packed information. This means that the RBAR contains the required region number and had the VALID bit set to 1, see “MPU Region Base Address Register” on page 143. Use this when the data is stat- ically packed, for example in a boot loader: ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0, =MPU_RBAR ; 0xE000ED9C, MPU Region Base register STR R1, [R0, #0x0] ; Region base address and ; region number combined with VALID (bit 4) set to 1 STR R2, [R0, #0x4] ; Region Attribute, Size and Enable Use an STM instruction to optimize this: ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0,=MPU_RBAR ; 0xE000ED9C, MPU Region Base register STM R0, {R1-R2} ; Region base address, region number and VALID bit, ; and Region Attribute, Size and Enable

11.23.8.3 Subregions

Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in the SRD field of the RASR to disable a subregion, see “MPU Region Attribute and Size Register” on page 144. The least significant bit of SRD controls the first subregion, and the most significant bit controls the last subregion. Disabling a subregion means another region overlapping the disabled range matches instead. If no other enabled region overlaps the disabled subregion the MPU issues a fault. Regions of 32, 64, and 128 bytes do not support subregions, With regions of these sizes, you must set the SRD field to 0x00, otherwise the MPU behavior is Unpredictable.

11.23.8.4 Example of SRD use

Two regions with the same base address overlap. Region one is 128KB, and region two is 512KB. To ensure the attri- butes from region one apply to the first128KB region, set the SRD field for region two to b00000011 to disable the first two subregions, as Figure 11-9 shows

 2020 Microchip Technology Inc. DS60001614B-page 149 SAM3X8ERT FIGURE 11-9: SRD USE

11.23.9 MPU DESIGN HINTS AND TIPS

To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access. Ensure software uses aligned accesses of the correct size to access MPU registers:

• except for the RASR, it must use aligned word accesses
• for the RASR it can use byte or aligned halfword or word accesses. The processor does not support unaligned accesses to MPU registers. When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to prevent any previous region settings from affecting the new MPU setup.

11.23.9.1 MPU Configuration for a Microcontroller

Usually, a microcontroller system has only a single processor and no caches. In such a system, program the MPU as follows: In most microcontroller implementations, the share ability and cache policy attributes do not affect the system behavior. However, using these settings for the MPU regions can make the application code more portable. The values given are for typical situations. In special systems, such as multiprocessor designs or designs with a separate DMA engine, the share ability attribute might be important. In these cases refer to the recommendations of the memory device manufac- turer.

11.24 Glossary

This glossary describes some of the terms used in technical documents from ARM. Abort A mechanism that indicates to a processor that the value associated with a memory access is invalid. An abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction or data memory. Aligned A data item stored at an address that is divisible by the number of bytes that defines the data size is said to be aligned. Aligned words and halfwords have addresses that are divisible by four and two respectively. The terms word-aligned and halfword-aligned therefore stipulate addresses that are divisible by four and two respectively. Banked register TABLE 11-40: MEMORY REGION ATTRIBUTES FOR A MICROCONTROLLER Memory region TEX C B S Memory type and attributes Flash memory b000 1 0 0 Normal memory, Non-shareable, write-through Internal SRAM b000 1 0 1 Normal memory, Shareable, write-through External SRAM b000 1 1 1 Normal memory, Shareable, write-back, write-allocate Peripherals b000 0 1 1 Device memory, Shareable Region 1 Disabled subregion Disabled subregion Region 2, with subregions Base address of both regions Offset from base address 64KB 128KB 192KB 256KB 320KB 384KB 448KB 512KB

DS60001614B-page 150  2020 Microchip Technology Inc. A register that has multiple physical copies, where the state of the processor determines which copy is used. The Stack Pointer, SP (R13) is a banked register. Base register In instruction descriptions, a register specified by a load or store instruction that is used to hold the base value for the instruction’s address calculation. Depending on the instruction and its addressing mode, an offset can be added to or subtracted from the base register value to form the address that is sent to memory. See also “Index register” Breakpoint A breakpoint is a mechanism provided by debuggers to identify an instruction at which program execution is to be halted. Breakpoints are inserted by the programmer to enable inspection of register contents, memory locations, variable values at fixed points in the program execution to test that the program is operating correctly. Breakpoints are removed after the program is successfully tested. Condition field A four-bit field in an instruction that specifies a condition under which the instruction can execute. Conditional execution If the condition code flags indicate that the corresponding condition is true when the instruction starts executing, it exe- cutes normally. Otherwise, the instruction does nothing. Context The environment that each process operates in for a multitasking operating system. In ARM processors, this is limited to mean the physical address range that it can access in memory and the associated memory access permissions. Coprocessor A processor that supplements the main processor. Cortex-M3 does not support any coprocessors. Debugger A debugging system that includes a program, used to detect, locate, and correct software faults, together with custom hardware that supports software debugging. Direct Memory Access (DMA) An operation that accesses main memory directly, without the processor performing any accesses to the data con - cerned. Doubleword A 64-bit data item. The contents are taken as being an unsigned integer unless otherwise stated. Doubleword-aligned A data item having a memory address that is divisible by eight. Endianness Byte ordering. The scheme that determines the order that successive bytes of a data word are stored in memory. An aspect of the system’s memory mapping. See also “Little-endian (LE)” Exception An event that interrupts program execution. When an exception occurs, the processor suspends the normal program flow and starts execution at the address indicated by the corresponding exception vector. The indicated address con - tains the first instruction of the handler for the exception. An exception can be an interrupt request, a fault, or a software-generated system exception. Faults include attempting an invalid memory access, attempting to execute an instruction in an invalid processor state, and attempting to execute an undefined instruction. Exception service routine See “Interrupt handler” Exception vector See “Interrupt vector” Flat address mapping

 2020 Microchip Technology Inc. DS60001614B-page 151 SAM3X8ERT A system of organizing memory in which each physical address in the memory space is the same as the corresponding virtual address. Halfword A 16-bit data item. Illegal instruction An instruction that is architecturally Undefined. Implementation-defined The behavior is not architecturally defined, but is defined and documented by individual implementations. Implementation-specific The behavior is not architecturally defined, and does not have to be documented by individual implementations. Used when there are a number of implementation options available and the option chosen does not affect software compati- bility. Index register In some load and store instruction descriptions, the value of this register is used as an offset to be added to or subtracted from the base register value to form the address that is sent to memory. Some addressing modes optionally enable the index register value to be shifted prior to the addition or subtraction. See also “Base register” Instruction cycle count The number of cycles that an instruction occupies the Execute stage of the pipeline. Interrupt handler A program that control of the processor is passed to when an interrupt occurs. Interrupt vector One of a number of fixed addresses in low memory, or in high memory if high vectors are configured, that contains the first instruction of the corresponding interrupt handler. Little-endian (LE) Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing addresses in memory. See also “Little-endian memory” , “Endianness” Little-endian memory Memory in which: a byte or halfword at a word-aligned address is the least significant byte or halfword within the word at that address a byte at a halfword-aligned address is the least significant byte within the halfword at that address. Load/store architecture A processor architecture where data-processing operations only operate on register contents, not directly on memory contents. Memory Protection Unit (MPU) Hardware that controls access permissions to blocks of memory. An MPU does not perform any address translation. Prefetching In pipelined processors, the process of fetching instructions from memory to fill up the pipeline before the preceding instructions have finished executing. Prefetching an instruction does not mean that the instruction has to be executed. Read Reads are defined as memory operations that have the semantics of a load. Reads include the Thumb instructions LDM, LDR, LDRSH, LDRH, LDRSB, LDRB, and POP . Region A partition of memory space.

DS60001614B-page 152  2020 Microchip Technology Inc. Reserved A field in a control register or instruction format is reserved if the field is to be defined by the implementation, or produces Unpredictable results if the contents of the field are not zero. These fields are reserved for use in future extensions of the architecture or are implementation-specific. All reserved bits not used by the implementation must be written as 0 and read as 0. Should Be One (SBO) Write as 1, or all 1s for bit fields, by software. Writing as 0 produces Unpredictable results. Should Be Zero (SBZ) Write as 0, or all 0s for bit fields, by software. Writing as 1 produces Unpredictable results. Should Be Zero or Preserved (SBZP) Write as 0, or all 0s for bit fields, by software, or preserved by writing the same value back that has been previously read from the same field on the same processor. Thread-safe In a multi-tasking environment, thread-safe functions use safeguard mechanisms when accessing shared resources, to ensure correct operation without the risk of shared access conflicts. Thumb instruction One or two halfwords that specify an operation for a processor to perform. Thumb instructions must be halfword-aligned. Unaligned A data item stored at an address that is not divisible by the number of bytes that defines the data size is said to be unaligned. For example, a word stored at an address that is not divisible by four. Undefined Indicates an instruction that generates an Undefined instruction exception. Unpredictable (UNP) You cannot rely on the behavior. Unpredictable behavior must not represent security holes. Unpredictable behavior must not halt or hang the processor, or any parts of the system. Warm reset Also known as a core reset. Initializes the majority of the processor excluding the debug controller and debug logic. This type of reset is useful if you are using the debugging features of a processor. Word A 32-bit data item. Write Writes are defined as operations that have the semantics of a store. Writes include the Thumb instructions STM, STR, STRH, STRB, and PUSH.

 2020 Microchip Technology Inc. DS60001614B-page 153 SAM3X8ERT

12.0 DEBUG AND TEST FEATURES

12.1 Description

The SAM3X8ERT microcontrollers feature a number of complementary debug and test capabilities. The Serial Wire/JTAG Debug Port (SWJ-DP) combining a Serial Wire Debug Port (SW-DP) and JTAG Debug (JTAG-DP) port is used for standard debugging functions, such as downloading code and single-stepping through programs. It also embeds a serial wire trace.

12.2 Embedded Characteristics

• Debug access to all memory and registers in the system, including Cortex-M3 register bank when the core is run- ning, halted, or held in reset.
• Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access
• Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches
• Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling
• Instrumentation Trace Macrocell (ITM) for support of printf style debugging
• IEEE1149.1 JTAG Boundary-scan on all digital pins FIGURE 12-1: DEBUG AND TEST BLOCK DIAGRAM TST TMS TCK/SWCLK TDI JTAGSEL TDO/TRACESWO Boundary TAP SWJ-DP Reset and Test POR

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12.3 Application Examples

12.3.1 DEBUG ENVIRONMENT

Figure 12-2 shows a complete debug environment example. The SWJ-DP interface is used for standard debugging functions, such as downloading code and single-stepping through the program and viewing core and peripheral regis - ters. FIGURE 12-2: APPLICATION DEBUG ENVIRONMENT EXAMPLE

12.3.2 TEST ENVIRONMENT

Figure 12-3 shows a test environment example (JTAG Boundary scan). Test vectors are sent and interpreted by the tes- ter. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. SAM3X8ERT Host Debugger PC SAM3X8ERT-based Application Board SWJ-DP Connector SWJ-DP Emulator/Probe

 2020 Microchip Technology Inc. DS60001614B-page 155 SAM3X8ERT FIGURE 12-3: APPLICATION TEST ENVIRONMENT EXAMPLE

12.4 Debug and Test Pin Description

Note 1: TDO pin is set in input mode when the Cortex-M3 Core is not in debug mode. Thus the internal pull-up cor- responding to this PIO line must be enabled to avoid current consumption due to floating input. TABLE 12-1: DEBUG AND TEST SIGNAL LIST Signal Name Function Type Active Level Reset/Test NRST Microcontroller Reset Input/Output Low TST Test Select Input SWD/JTAG TCK/SWCLK Test Clock/Serial Wire Clock Input TDI Test Data In Input TDO/TRACESWO Test Data Out/Trace Asynchronous Data Out Output (1) TMS/SWDIO Test Mode Select/Serial Wire Input/Output Input JTAGSEL JTAG Selection Input High Chip 2Chip n Chip 1SAM3X8ERT SAM3X8ERT-based Application Board In Test JTAG Connector Tester Test Adaptor JTAG Probe

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12.5 Functional Description

12.5.1 TEST PIN

One dedicated pin, TST, is used to define the device operating mode. When this pin is at low level during power-up, the device is in normal operating mode. When at high level, the device is in test mode or FFPI mode. The TST pin integrates a permanent pull-down resistor of about 15 kso that it can be left unconnected for normal operation. Note: When setting the TST pin to low or high level at power up, it must remain in the same state during the dura- tion of the whole operation.

12.5.2 DEBUG ARCHITECTURE

Figure 12-4 shows the SAM3X8ERT debug architecture. The Cortex-M3 embeds five functional units for debug:

• SWJ-DP (Serial Wire/JTAG Debug Port)
• FPB (Flash Patch Breakpoint)
• DWT (Data Watchpoint and Trace)
• ITM (Instrumentation Trace Macrocell)
• TPIU (Trace Port Interface Unit) The debug architecture information that follows is mainly dedicated to developers of SWJ-DP Emulators/Probes and debugging tool vendors for Cortex M3-based microcontrollers. For further details on SWJ-DP see the Cortex M3 tech- nical reference manual. FIGURE 12-4: DEBUG ARCHITECTURE

12.5.3 SERIAL WIRE/JTAG DEBUG PORT (SWJ-DP)

The Cortex-M3 embeds a SWJ-DP Debug port which is the standard CoreSight ™ debug port. It combines Serial Wire Debug Port (SW-DP), from 2 to 3 pins and JTAG debug Port (JTAG-DP), 5 pins. By default, the JTAG Debug Port is active. If the host debugger wants to switch to the Serial Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables JTAG-DP and enables SW-DP . When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be used with SW-DP , not JTAG-DP . 4 watchpoints PC sampler data address sampler data sampler interrupt trace CPU statistics DWT 6 breakpoints FPB software trace 32 channels time stamping ITM SWD/JTAG SWJ-DP SWO trace TPIU

 2020 Microchip Technology Inc. DS60001614B-page 157 SAM3X8ERT SW-DP or JTAG-DP mode is selected when JTAGSEL is low. It is not possible to switch directly between SWJ-DP and JTAG boundary scan operations. A chip reset must be performed after JTAGSEL is changed.

12.5.3.1 SW-DP and JTAG-DP Selection Mechanism

Debug port selection mechanism is done by sending specific SWDIOTMS sequence. The JTAG-DP is selected by default after reset.

• Switch from JTAG-DP to SW-DP . The sequence is: - Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1 - Send the 16-bit sequence on SWDIOTMS = 0111100111100111 (0x79E7 MSB first) - Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
• Switch from SWD to JTAG. The sequence is: - Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1 - Send the 16-bit sequence on SWDIOTMS = 0011110011100111 (0x3CE7 MSB first) - Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1

12.5.4 FPB (FLASH PATCH BREAKPOINT)

The FPB:

• Implements hardware breakpoints
• Patches code and data from code space to system space. The FPB unit contains:
• Two literal comparators for matching against literal loads from Code space, and remapping to a corresponding area in System space.
• Six instruction comparators for matching against instruction fetches from Code space and remapping to a corre- sponding area in System space.
• Alternatively, comparators can also be configured to generate a Breakpoint instruction to the processor core on a match.

12.5.5 DWT (DATA WATCHPOINT AND TRACE)

The DWT contains four comparators which can be configured to generate the following:

• PC sampling packets at set intervals
• PC or Data watchpoint packets
• Watchpoint event to halt core The DWT contains counters for the following items:
• Clock cycle (CYCCNT)
• Folded instructions
• Load Store Unit (LSU) operations
• Sleep Cycles
• CPI (all instruction cycles except for the first cycle)
• Interrupt overhead TABLE 12-2: SWJ-DP PIN LIST Pin Name JTAG Port Serial Wire Debug Port TMS/SWDIO TMS SWDIO TCK/SWCLK TCK SWCLK TDI TDI — TDO/TRACESWO TDO TRACESWO (optional: trace)

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12.5.6 ITM (INSTRUMENTATION TRACE MACROCELL)

The ITM is an application driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets which can be generated by three different sources with several priority levels:

• Software trace: Software can write directly to ITM stimulus registers. This can be done thanks to the “printf” func- tion. For more information, refer to “How to Configure the ITM” on page 158.
• Hardware trace: The ITM emits packets generated by the DWT.
• Time stamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate the timestamp.

12.5.6.1 How to Configure the ITM

The following example describes how to output trace data in asynchronous trace mode.

• Configure the TPIU for asynchronous trace mode (refer to “5.4.3. How to Configure the TPIU” on page 158)
• Enable the write accesses into the ITM registers by writing “0xC5ACCE55” into the Lock Access Register (Address: 0xE0000FB0)
• Write 0x00010015 into the Trace Control Register: - Enable ITM - Enable Synchronization packets - Enable SWO behavior - Fix the ATB ID to 1
• Write 0x1 into the Trace Enable Register: - Enable the Stimulus port 0
• Write 0x1 into the Trace Privilege Register: - Stimulus port 0 only accessed in privileged mode (Clearing a bit in this register will result in the corresponding stimulus port being accessible in user mode.)
• Write into the Stimulus port 0 register: TPIU (Trace Port Interface Unit) The TPIU acts as a bridge between the on-chip trace data and the Instruction Trace Macrocell (ITM). The TPIU formats and transmits trace data off-chip at frequencies asynchronous to the core.

12.5.6.2 Asynchronous Mode

The TPIU is configured in asynchronous mode, trace data are output using the single TRACESWO pin. The TRACESWO signal is multiplexed with the TDO signal of the JTAG Debug Port. As a consequence, asynchronous trace mode is only available when the Serial Wire Debug mode is selected since TDO signal is used in JTAG debug mode. Two encoding formats are available for the single pin output:

• Manchester encoded stream. This is the reset value.
• NRZ_based UART byte structure This example only concerns the asynchronous trace mode.
• Set the TRCENA bit to 1 into the Debug Exception and Monitor Register (0xE000EDFC) to enable the use of trace and debug blocks.
• Write 0x2 into the Selected Pin Protocol Register - Select the Serial Wire Output – NRZ
• Write 0x100 into the Formatter and Flush Control Register
• Set the suitable clock prescaler value into the Async Clock Prescaler Register to scale the baud rate of the asyn- chronous output (this can be done automatically by the debugging tool). 12.5.7 IEEE® 1149.1 JTAG BOUNDARY SCAN IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology.

 2020 Microchip Technology Inc. DS60001614B-page 159 SAM3X8ERT IEEE 1149.1 JTAG Boundary Scan is enabled when FWUP, NRSTB and JTAGSEL are high while TST is tied low during power-up and must be kept in this state during the whole boundary scan operation. VDDCORE must be externally sup- plied between 1.8V and 1.95V. The SAMPLE, EXTEST and BYPASS functions are implemented. In SWD/JTAG debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG Boundary Scan and SWJ Debug Port operations. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file to set up the test is provided on www.Microchip.com.

12.5.7.1 JTAG Boundary-scan Register

The Boundary-scan Register (BSR) contains a number of bits which correspond to active pins and associated control signals. Each SAM3X8ERT input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. For more information, refer to BDSL files available for the SAM3X8ERT.

DS60001614B-page 160  2020 Microchip Technology Inc.

12.5.8 ID CODE REGISTER

Access: Read-only

• VERSION[31:28]: Product Version Number Set to 0x0.
• PART NUMBER[27:12]: Product Part Number
• MANUFACTURER IDENTITY[11:1] Set to 0x01F.
• Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. 31 30 29 28 27 26 25 24 VERSION PART NUMBER 23 22 21 20 19 18 17 16 PART NUMBER 15 14 13 12 11 10 9 8 PART NUMBER MANUFACTURER IDENTITY 7 6 5 4 3 2 1 0 MANUFACTURER IDENTITY 1 Chip Name Chip ID SAM3X8ERT 0x05B2B Chip Name JTAG ID Code SAM3X8ERT 0x05B2B03F

 2020 Microchip Technology Inc. DS60001614B-page 161 SAM3X8ERT

13.0 RESET CONTROLLER (RSTC)

13.1 Description

The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets.

13.2 Embedded Characteristics

• Manages all Resets of the System, Including - External Devices through the NRST Pin - Processor Reset - Peripheral Set Reset
• Based on Embedded Power-on Cell
• Reset Source Status - Status of the Last Reset - Either Software Reset, User Reset, Watchdog Reset
• External Reset Signal Shaping
• AMBA™-compliant Interface - Interface to the ARM® Advanced Peripheral Bus

13.3 Block Diagram

FIGURE 13-1: RESET CONTROLLER BLOCK DIAGRAM

13.4 Functional Description

13.4.1 RESET CONTROLLER OVERVIEW

The Reset Controller is made up of an NRST Manager and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: NRST proc_nreset wd_fault periph_nreset SLCK Reset State Manager Reset Controller rstc_irq NRST Manager exter_nresetnrst_out core_backup_reset WDRPROC user_reset vddcore_nreset

DS60001614B-page 162  2020 Microchip Technology Inc.

• proc_nreset: Processor reset line. It also resets the Watchdog Timer.
• periph_nreset: Affects the whole set of embedded peripherals.
• nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Controller, is powered with VDDIO, so that its configuration is saved as long as VDDIO is on.

13.4.2 NRST MANAGER

After power-up, NRST is an output during the ERSTL time period defined in the RSTC_MR. When ERSTL has elapsed, the pin behaves as an input and all the system is held in reset if NRST is tied to GND by an external signal. The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 13-2 shows the block diagram of the NRST Manager. FIGURE 13-2: NRST MANAGER

13.4.2.1 NRST Signal or Interrupt

The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger. The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1.

13.4.2.2 NRST External Reset Control

The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2 (ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note: ERSTL at 0 defines a two-cycle duration for the NRST pulse. External Reset Timer URSTS URSTEN ERSTL exter_nreset URSTIEN RSTC_MR RSTC_MR RSTC_MR RSTC_SR NRSTL nrst_out NRST rstc_irq Other interrupt sources user_reset

 2020 Microchip Technology Inc. DS60001614B-page 163 SAM3X8ERT This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. As the ERSTL field is within RSTC_MR register, which is backed-up, it can be used to shape the system power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator.

13.4.3 BROWNOUT MANAGER

The Brownout manager is embedded within the Supply Controller, refer to the product Supply Controller section for a detailed description.

13.4.4 RESET STATES

The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released.

13.4.4.1 General Reset

A general reset occurs when a Power-on-reset is detected, an Asynchronous Master Reset (NRSTB pin) is requested, a Brownout or a Voltage regulation loss is detected by the Supply controller. The vddcore_nreset signal is asserted by the Supply Controller when a general reset occurs. All the reset signals are released and the field RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR is reset, the NRST line rises 2 cycles after the vddcore_nreset, as ERSTL defaults at value 0x0. Figure 13-3 shows how the General Reset affects the reset signals. FIGURE 13-3: GENERAL RESET STATE

13.4.4.2 Backup Reset

A Backup reset occurs when the chip returns from Backup mode. The core_backup_reset signal is asserted by the Supply Controller when a Backup reset occurs. The field RSTTYP in RSTC_SR is updated to report a Backup Reset. SLCK h_nreset c_nreset NRST nrst_out) EXTERNAL RESET LENGTH = 2 cycles MCK Processor Startup = 2 cycles p_nreset Any Freq. STTYP XXX 0x0 = General Reset XX

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13.4.4.3 User Reset

The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset. The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. FIGURE 13-4: USER RESET STATE

13.4.4.4 Software Reset

The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1:

• PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.
• PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in partic- ular, the Remap Command. The Peripheral Reset is generally used for debug purposes. Except for debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and PRO- CRST set both at 1 simultaneously).
• EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles. SLCK riph_nreset proc_nreset NRST NRST (nrst_out) >= EXTERNAL RESET LENGTH MCK Processor Startup = 2 cycles Any Freq. Resynch. 2 cycles RSTTYP Any XXX Resynch. 2 cycles 0x4 = User Rese

 2020 Microchip Technology Inc. DS60001614B-page 165 SAM3X8ERT The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK. If EXTRS T is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. FIGURE 13-5: SOFTWARE RESET

13.4.4.5 Watchdog Reset

The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR:

• If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state.
• If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. SLCK periph_nreset if PERRST=1 proc_nreset if PR OCRST=1 Write RSTC_CR NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) MCK Processor Startup = 2 cycles Any Freq. RSTTYP Any XXX 0x3 = Software Reset Resynch. 1 cycle SRCMP in RSTC_SR

DS60001614B-page 166  2020 Microchip Technology Inc. FIGURE 13-6: WATCHDOG RESET

13.4.5 RESET STATE PRIORITIES

The Reset State Manager manages the following priorities between the different reset sources, given in descending order:

• General Reset
• Backup Reset
• Watchdog Reset
• Software Reset
• User Reset Particular cases are listed below:
• When in User Reset: - A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. - A software reset is impossible, since the processor reset is being activated.
• When in Software Reset: - A watchdog event has priority over the current state. - The NRST has no effect.
• When in Watchdog Reset: - The processor reset is active and so a Software Reset cannot be programmed. - A User Reset cannot be entered.

13.4.6 RESET CONTROLLER STATUS REGISTER

The Reset Controller status register (RSTC_SR) provides several status fields:

• RSTTYP field: This field gives the type of the last reset, as explained in previous sections.
• SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current soft- ware reset.
• NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge.
• URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition Only if WDRPROC = 0 SLCK periph_nreset proc_nreset wd_fault NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) MCK Processor Startup = 2 cycles Any Freq. RSTTYP Any XXX 0x2 = Watchdog Reset

 2020 Microchip Technology Inc. DS60001614B-page 167 SAM3X8ERT is also detected on the Master Clock (MCK) rising edge (see Figure 13-7). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. FIGURE 13-7: RESET CONTROLLER STATUS AND INTERRUPT MCK NRST NRSTL 2 cycle resynchronization 2 cycle resynchronization URSTS read RSTC_SRPeripheral Access rstc_irq if (URSTEN = 0) and (URSTIEN = 1)

DS60001614B-page 168  2020 Microchip Technology Inc.

13.5 Reset Controller (RSTC) User Interface

The following table lists the register mapping details. TABLE 13-1: REGISTER MAPPING Offset Register Name Access Reset 0x00 Control Register RSTC_CR Write-only - 0x04 Status Register RSTC_SR Read-only 0x0000_0000 0x08 Mode Register RSTC_MR Read-write 0x0000 0001

 2020 Microchip Technology Inc. DS60001614B-page 169 SAM3X8ERT

13.5.1 RESET CONTROLLER CONTROL REGISTER

Name:RSTC_CR Address:0x400E1A00 Access:Write-only

• PROCRST: Processor Reset 0: No effect. 1: If KEY is correct, resets the processor.
• PERRST: Peripheral Reset 0: No effect. 1: If KEY is correct, resets the peripherals.
• EXTRST: External Reset 0: No effect. 1: If KEY is correct, asserts the NRST pin.
• KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 – – – – EXTRST PERRST – PROCRST

DS60001614B-page 170  2020 Microchip Technology Inc.

13.5.2 RESET CONTROLLER STATUS REGISTER

Name:RSTC_SR Address:0x400E1A04 Access:Read-only

• URSTS: User Reset Status 0: No high-to-low edge on NRST happened since the last read of RSTC_SR. 1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
• RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.
• NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK).
• SRCMP: Software Reset Command in Progress 0: No software command is being performed by the reset controller. The reset controller is ready for a software com - mand. 1: A software reset command is being performed by the reset controller. The reset controller is busy. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSTTYP Reset Type Comments 0 0 0 General Reset First power-up Reset 0 0 1 Backup Reset Return from Backup mode 0 1 0 Watchdog Reset Watchdog fault occurred 0 1 1 Software Reset Processor reset required by the software 1 0 0 User Reset NRST pin detected low

 2020 Microchip Technology Inc. DS60001614B-page 171 SAM3X8ERT

13.5.3 RESET CONTROLLER MODE REGISTER

Name:RSTC_MR Address:0x400E1A08 Access:Read-write

• URSTEN: User Reset Enable 0: The detection of a low level on the pin NRST does not generate a User Reset. 1: The detection of a low level on the pin NRST triggers a User Reset.
• URSTIEN: User Reset Interrupt Enable 0: USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1: USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.
• ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds.
• KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – – – ERSTL 7 6 5 4 3 2 1 0

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14.0 REAL-TIME TIMER (RTT)

14.1 Description

The Real-time Timer is built around a 32-bit counter used to count roll-over events of the programmable 16-bit prescaler which enables counting elapsed seconds from a 32 kHz slow clock source. It generates a periodic interrupt and/or trig- gers an alarm on a programmed value.

14.2 Embedded Characteristics

• 32-bit Free-running Counter on prescaled slow clock
• 16-bit Configurable Prescaler
• Interrupt on Alarm

14.3 Block Diagram

FIGURE 14-1: REAL-TIME TIMER

14.4 Functional Description

The Real-time Timer can be used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 kHz). The 32-bit counter can count up to 2 32 seconds, corresponding to more than 136 years, then roll over to 0. The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the inter- rupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear. SLCK RTPRES RTTINC ALMS 16-bit Divider 32-bit Counter ALMV CRTV RTT_MR RTT_VR RTT_AR RTT_SR RTTINCIEN RTT_MR ALMIEN rtt_int RTT_MR set set RTT_SR read RTT_SR reset reset RTT_MR reload rtt_alarm RTTRST RTT_MR RTTRST

 2020 Microchip Technology Inc. DS60001614B-page 173 SAM3X8ERT The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value. The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Reg- ister). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF, after a reset. The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32.768 Hz. Reading the RTT_SR status register resets the RTTINC and ALMS fields. Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. 2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the RTT_SR (Status Register). FIGURE 14-2: RTT COUNTING Prescaler ALMVALMV-10 ALMV+1 RTPRES - 1 RTT APB cycle read RTT_SR ALMS (RTT_SR) APB Interface SCLK RTTINC (RTT_SR) ALMV+2 ALMV+3... APB cycle

DS60001614B-page 174  2020 Microchip Technology Inc.

14.5 Real-time Timer (RTT) User Interface

The following table lists the register mapping details of RTT user interface.

14.5.1 REAL-TIME TIMER MODE REGISTER

Name:RTT_MR Address:0x400E1A30 Access: Read-write

• RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216 * SCLK period. RTPRES  0: The prescaler period is equal to RTPRES * SCLK period.
• ALMIEN: Alarm Interrupt Enable 0 = The bit ALMS in RTT_SR has no effect on interrupt. 1 = The bit ALMS in RTT_SR asserts interrupt.
• RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt. 1 = The bit RTTINC in RTT_SR asserts interrupt.
• RTTRST: Real-time Timer Restart 0 = No effect. 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. TABLE 14-1: REGISTER MAPPING Offset Register Name Access Reset 0x00 Mode Register RTT_MR Read-write 0x0000_8000 0x04 Alarm Register RTT_AR Read-write 0xFFFF_FFFF 0x08 Value Register RTT_VR Read-only 0x0000_0000 0x0C Status Register RTT_SR Read-only 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — — RTTRST RTTINCIE N ALMIEN 15 14 13 12 11 10 9 8 RTPRES 7 6 5 4 3 2 1 0 RTPRES

 2020 Microchip Technology Inc. DS60001614B-page 175 SAM3X8ERT

14.5.2 REAL-TIME TIMER ALARM REGISTER

Name:RTT_AR Address:0x400E1A34 Access:Read-write

• ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 31 30 29 28 27 26 25 24 ALMV 23 22 21 20 19 18 17 16 ALMV 15 14 13 12 11 10 9 8 ALMV 7 6 5 4 3 2 1 0 ALMV

DS60001614B-page 176  2020 Microchip Technology Inc.

14.5.3 REAL-TIME TIMER VALUE REGISTER

Name:RTT_VR Address:0x400E1A38 Access:Read-only

• CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 31 30 29 28 27 26 25 24 CRTV 23 22 21 20 19 18 17 16 CRTV 15 14 13 12 11 10 9 8 CRTV 7 6 5 4 3 2 1 0 CRTV

 2020 Microchip Technology Inc. DS60001614B-page 177 SAM3X8ERT

14.5.4 REAL-TIME TIMER STATUS REGISTER

Name:RTT_SR Address:0x400E1A3C Access:Read-only

• ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred since the last read of RTT_SR. 1 = The Real-time Alarm occurred since the last read of RTT_SR.
• RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR. 1 = The Real-time Timer has been incremented since the last read of the RTT_SR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DS60001614B-page 178  2020 Microchip Technology Inc.

15.0 REAL-TIME CLOCK (RTC)

15.1 Description

The Real-time Clock (RTC) peripheral is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus. The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator. Updating time and calendar fields and configuring the alarm fields are performed by a parallel capture on the 32-bit data bus. An entry control is performed to avoid loading registers with incompatible BCD format data or with an incompatible date according to the current month/year/century.

15.2 Embedded Characteristics

• Low Power Consumption
• Full Asynchronous Design
• Two Hundred Year Gregorian Calendar
• Programmable Periodic Interrupt
• Time, Date and Alarm 32-bit Parallel Load
• Write Protected Registers

15.3 Block Diagram

FIGURE 15-1: RTC BLOCK DIAGRAM

15.4 Product Dependencies

15.4.1 POWER MANAGEMENT

The Real-time Clock is continuously clocked at 32768 Hz. The Power Management Controller has no effect on RTC behavior.

15.4.2 INTERRUPT

RTC interrupt line is connected on one of the internal sources of the interrupt controller. RTC interrupt requires the inter- rupt controller to be programmed first.

15.5 Functional Description

The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds. The valid year range is 1900 to 2099 in Gregorian mode, a two-hundred-year calendar. The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator. Bus Interface

32768 Divider TimeSlow Clock: SLCK

 2020 Microchip Technology Inc. DS60001614B-page 179 SAM3X8ERT Corrections for leap years are included (all years divisible by 4 being leap years). This is correct up to the year 2099.

15.5.1 REFERENCE CLOCK

The reference clock is Slow Clock (SLCK). It can be driven internally or by an external 32.768 kHz crystal. During low power modes of the processor, the oscillator runs and power consumption is critical. The crystal selection has to take into account the current consumption for power saving and the frequency drift due to temperature effect on the circuit for time accuracy.

15.5.2 TIMING

The RTC is updated in real time at one-second intervals in normal mode for the counters of seconds, at one-minute intervals for the counter of minutes and so on. Due to the asynchronous operation of the RTC with respect to the rest of the chip, to be certain that the value read in the RTC registers (century, year, month, date, day, hours, minutes, seconds) are valid and stable, it is necessary to read these registers twice. If the data is the same both times, then it is valid. Therefore, a minimum of two and a maximum of three accesses are required.

15.5.3 ALARM

The RTC has five programmable fields: month, date, hours, minutes and seconds. Each of these fields can be enabled or disabled to match the alarm condition:

• If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt gener- ated if enabled) at a given month, date, hour/minute/second.
• If only the “seconds” field is enabled, then an alarm is generated every minute. Depending on the combination of fields enabled, a large number of possibilities are available to the user ranging from minutes to 365/366 days.

15.5.4 ERROR CHECKING

Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year and century configured. If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity reg- ister. The user can not reset this flag. It is reset as soon as an acceptable value is programmed. This avoids any further side effects in the hardware. The same procedure is done for the alarm. The following checks are performed: 1. Century (check if it is in range 19 - 20) 2. Year (BCD entry check) 3. Date (check range 01 - 31) 4. Month (check if it is in BCD range 01 - 12, check validity regarding “date”) 5. Day (check range 1 - 7) 6. Hour (BCD checks: in 24-hour mode, check range 00 - 23 and check that AM/PM flag is not set if RTC is set in 24-hour mode; in 12-hour mode check range 01 - 12) 7. Minute (check BCD and range 00 - 59) 8. Second (check BCD and range 00 - 59) Note: If the 12-hour mode is selected by means of the RTC_MODE register, a 12-hour value can be programmed and the returned value on RTC_TIME will be the corresponding 24-hour value. The entry control checks the value of the AM/PM indicator (bit 22 of RTC_TIME register) to determine the range to be checked.

15.5.5 UPDATING TIME/CALENDAR

To update any of the time/calendar fields, the user must first stop the RTC by setting the corresponding field in the Con- trol Register. Bit UPDTIM must be set to update time fields (hour, minute, second) and bit UPDCAL must be set to update calendar fields (century, year, month, date, day). Then the user must poll or wait for the interrupt (if enabled) of bit ACKUPD in the Status Register. Once the bit reads 1, it is mandatory to clear this flag by writing the corresponding bit in RTC_SCCR. The user can now write to the appropri- ate Time and Calendar register.

DS60001614B-page 180  2020 Microchip Technology Inc. When the update is finished, the user must reset (0) UPDTIM and/or UPDCAL in the Control When entering programming mode of the calendar fields, the time fields remain enabled. When entering the program- ming mode of the time fields, both time and calendar fields are stopped. This is due to the location of the calendar logic circuity (downstream for low-power considerations). It is highly recommended to prepare all the fields to be updated before entering programming mode. In successive update operations, the user must wait at least one second after reset- ting the UPDTIM/UPDCAL bit in the RTC_CR (Control Register) before setting these bits again. This is done by waiting for the SEC flag in the Status Register before setting UPDTIM/UPDCAL bit. After resetting UPDTIM/UPDCAL, the SEC flag must also be cleared.

 2020 Microchip Technology Inc. DS60001614B-page 181 SAM3X8ERT FIGURE 15-2: UPDATE SEQUENCE Prepare TIme or Calendar Fields Set UPDTIM and/or UPDCAL bit(s) in RTC_CR Read RTC_SR ACKUPD = 1 ? Clear ACKUPD bit in RTC_SCCR Update Time and/or Calendar values in RTC_TIMR/RTC_CALR Clear UPDTIM and/or UPDCAL bit in RTC_CR No Ye s Begin End Polling or IRQ (if enabled)

DS60001614B-page 182  2020 Microchip Technology Inc.

15.6 Real-Time Clock (RTC) User Interface

Note: If an offset is not listed in the table it must be considered as reserved. TABLE 15-1: REGISTER MAPPING Offset Register Name Access Reset 0x00 Control Register RTC_CR Read-write 0x0 0x04 Mode Register RTC_MR Read-write 0x0 0x08 Time Register RTC_TIMR Read-write 0x0 0x0C Calendar Register RTC_CALR Read-write 0x01210720 0x10 Time Alarm Register RTC_TIMALR Read-write 0x0 0x14 Calendar Alarm Register RTC_CALALR Read-write 0x01010000 0x18 Status Register RTC_SR Read-only 0x0 0x1C Status Clear Command Register RTC_SCCR Write-only — 0x20 Interrupt Enable Register RTC_IER Write-only — 0x24 Interrupt Disable Register RTC_IDR Write-only — 0x28 Interrupt Mask Register RTC_IMR Read-only 0x0 0x2C Valid Entry Register RTC_VER Read-only 0x0 0x30–0xE0 Reserved Register — — — 0xE4 Write Protect Mode Register RTC_WPMR Read-write 0x00000000 0xE8–0xF8 Reserved Register — — — 0xFC Reserved Register — — —

 2020 Microchip Technology Inc. DS60001614B-page 183 SAM3X8ERT

15.6.1 RTC CONTROL REGISTER

Name: RTC_CR Address:0x400E1A60 Access: Read-write This register can only be written if the WPEN bit is cleared in “RTC Write Protect Mode Register” on page 195.

• UPDTIM: Update Request Time Register 0: No effect. 1: Stops the RTC time counting. Time counting consists of second, minute and hour counters. Time counters can be programmed once this bit is set and acknowledged by the bit ACKUPD of the Status Register.
• UPDCAL: Update Request Calendar Register 0: No effect. 1: Stops the RTC calendar counting. Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once this bit is set.
• TIMEVSEL: Time Event Selection The event that generates the flag TIMEV in RTC_SR (Status Register) depends on the value of TIMEVSEL.
• CALEVSEL: Calendar Event Selection The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL

15.6.2 RTC MODE REGISTER

Name: RTC_MR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value Name Description

0 MINUTE Minute change

1 HOUR Hour change

2 MIDNIGHT Every day at midnight

3 NOON Every day at noon

0 WEEK Week change (every Monday at time 00:00:00)

1 MONTH Month change (every 01 of each month at time 00:00:00)

2 YEAR Year change (every January 1 at time 00:00:00)

3 — —

DS60001614B-page 184  2020 Microchip Technology Inc. Address:0x400E1A64 Access: Read-write

• HRMOD: 12-/24-hour Mode 0: 24-hour mode is selected. 1: 12-hour mode is selected. All non-significant bits read zero. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

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15.6.3 RTC TIME REGISTER

Name: RTC_TIMR Address:0x400E1A68 Access: Read-write

• SEC: Current Second The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens.
• MIN: Current Minute The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens.
• HOUR: Current Hour The range that can be set is 1 - 12 (BCD) in 12-hour mode or 0 - 23 (BCD) in 24-hour mode.
• AMPM: Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode. 0: AM. 1: PM. All non-significant bits read zero. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — AMPM HOUR 15 14 13 12 11 10 9 8 — MIN 7 6 5 4 3 2 1 0 — SEC

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15.6.4 RTC CALENDAR REGISTER

Name: RTC_CALR Address:0x400E1A6C Access: Read-write

• CENT: Current Century The range that can be set is 19 - 20 (BCD). The lowest four bits encode the units. The higher bits encode the tens.
• YEAR: Current Year The range that can be set is 00 - 99 (BCD). The lowest four bits encode the units. The higher bits encode the tens.
• MONTH: Current Month The range that can be set is 01 - 12 (BCD). The lowest four bits encode the units. The higher bits encode the tens.
• DAY: Current Day in Current Week The range that can be set is 1 - 7 (BCD). The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter.
• DATE: Current Day in Current Month The range that can be set is 01 - 31 (BCD). The lowest four bits encode the units. The higher bits encode the tens. All non-significant bits read zero. 31 30 29 28 27 26 25 24 — — DATE 23 22 21 20 19 18 17 16 DAY MONTH 15 14 13 12 11 10 9 8 YEAR 7 6 5 4 3 2 1 0 — CENT

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15.6.5 RTC TIME ALARM REGISTER

Name: RTC_TIMALR Address:0x400E1A70 Access: Read-write This register can only be written if the WPEN bit is cleared in “RTC Write Protect Mode Register” on page 195.

• SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter.
• SECEN: Second Alarm Enable 0: The second-matching alarm is disabled. 1: The second-matching alarm is enabled.
• MIN: Minute Alarm This field is the alarm field corresponding to the BCD-coded minute counter.
• MINEN: Minute Alarm Enable 0: The minute-matching alarm is disabled. 1: The minute-matching alarm is enabled.
• HOUR: Hour Alarm This field is the alarm field corresponding to the BCD-coded hour counter.
• AMPM: AM/PM Indicator This field is the alarm field corresponding to the BCD-coded hour counter.
• HOUREN: Hour Alarm Enable 0: The hour-matching alarm is disabled. 1: The hour-matching alarm is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HOUREN AMPM HOUR 15 14 13 12 11 10 9 8 MINEN MIN 7 6 5 4 3 2 1 0 SECEN SEC

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15.6.6 RTC CALENDAR ALARM REGISTER

Name: RTC_CALALR Address:0x400E1A74 Access: Read-write This register can only be written if the WPEN bit is cleared in “RTC Write Protect Mode Register” on page 195.

• MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded month counter.
• MTHEN: Month Alarm Enable 0: The month-matching alarm is disabled. 1: The month-matching alarm is enabled.
• DATE: Date Alarm This field is the alarm field corresponding to the BCD-coded date counter.
• DATEEN: Date Alarm Enable 0: The date-matching alarm is disabled. 1: The date-matching alarm is enabled. 31 30 29 28 27 26 25 24 DATEEN — DATE 23 22 21 20 19 18 17 16 MTHEN — — MONTH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

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15.6.7 RTC STATUS REGISTER

Name: RTC_SR Address:0x400E1A78 Access: Read-only

• ACKUPD: Acknowledge for Update 0: Time and calendar registers cannot be updated. 1: Time and calendar registers can be updated.
• ALARM: Alarm Flag 0: No alarm matching condition occurred. 1: An alarm matching condition has occurred.
• SEC: Second Event 0: No second event has occurred since the last clear. 1: At least one second event has occurred since the last clear.
• TIMEV: Time Event 0: No time event has occurred since the last clear. 1: At least one time event has occurred since the last clear. The time event is selected in the TIMEVSEL field in RTC_CR (Control Register) and can be any one of the following events: minute change, hour change, noon, midnight (day change).
• CALEV: Calendar Event 0: No calendar event has occurred since the last clear. 1: At least one calendar event has occurred since the last clear. The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week change, month change and year change. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — CALEV TIMEV SEC ALARM ACKUPD

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15.6.8 RTC STATUS CLEAR COMMAND REGISTER

Name: RTC_SCCR Address:0x400E1A7C Access: Write-only

• ACKCLR: Acknowledge Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR).
• ALRCLR: Alarm Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR).
• SECCLR: Second Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR).
• TIMCLR: Time Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR).
• CALCLR: Calendar Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — CALCLR TIMCLR SECCLR ALRCLR ACKCLR

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15.6.9 RTC INTERRUPT ENABLE REGISTER

Name: RTC_IER Address:0x400E1A80 Access: Write-only

• ACKEN: Acknowledge Update Interrupt Enable 0: No effect. 1: The acknowledge for update interrupt is enabled.
• ALREN: Alarm Interrupt Enable 0: No effect. 1: The alarm interrupt is enabled.
• SECEN: Second Event Interrupt Enable 0: No effect. 1: The second periodic interrupt is enabled.
• TIMEN: Time Event Interrupt Enable 0: No effect. 1: The selected time event interrupt is enabled.
• CALEN: Calendar Event Interrupt Enable 0: No effect. 1: The selected calendar event interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — CALEN TIMEN SECEN ALREN ACKEN

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15.6.10 RTC INTERRUPT DISABLE REGISTER

Name: RTC_IDR Address:0x400E1A84 Access: Write-only

• ACKDIS: Acknowledge Update Interrupt Disable 0: No effect. 1: The acknowledge for update interrupt is disabled.
• ALRDIS: Alarm Interrupt Disable 0: No effect. 1: The alarm interrupt is disabled.
• SECDIS: Second Event Interrupt Disable 0: No effect. 1: The second periodic interrupt is disabled.
• TIMDIS: Time Event Interrupt Disable 0: No effect. 1: The selected time event interrupt is disabled.
• CALDIS: Calendar Event Interrupt Disable 0: No effect. 1: The selected calendar event interrupt is disabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — CALDIS TIMDIS SECDIS ALRDIS ACKDIS

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15.6.11 RTC INTERRUPT MASK REGISTER

Name: RTC_IMR Address:0x400E1A88 Access: Read-only

• ACK: Acknowledge Update Interrupt Mask 0: The acknowledge for update interrupt is disabled. 1: The acknowledge for update interrupt is enabled.
• ALR: Alarm Interrupt Mask 0: The alarm interrupt is disabled. 1: The alarm interrupt is enabled.
• SEC: Second Event Interrupt Mask 0: The second periodic interrupt is disabled. 1: The second periodic interrupt is enabled.
• TIM: Time Event Interrupt Mask 0: The selected time event interrupt is disabled. 1: The selected time event interrupt is enabled.
• CAL: Calendar Event Interrupt Mask 0: The selected calendar event interrupt is disabled. 1: The selected calendar event interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — CAL TIM SEC ALR ACK

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15.6.12 RTC VALID ENTRY REGISTER

Name: RTC_VER Address:0x400E1A8C Access: Read-only

• NVTIM: Non-valid Time 0: No invalid data has been detected in RTC_TIMR (Time Register). 1: RTC_TIMR has contained invalid data since it was last programmed.
• NVCAL: Non-valid Calendar 0: No invalid data has been detected in RTC_CALR (Calendar Register). 1: RTC_CALR has contained invalid data since it was last programmed.
• NVTIMALR: Non-valid Time Alarm 0: No invalid data has been detected in RTC_TIMALR (Time Alarm Register). 1: RTC_TIMALR has contained invalid data since it was last programmed.
• NVCALALR: Non-valid Calendar Alarm 0: No invalid data has been detected in RTC_CALALR (Calendar Alarm Register). 1: RTC_CALALR has contained invalid data since it was last programmed. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — — NVCALAL R NVTIMAL R NVCAL NVTIM

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15.6.13 RTC WRITE PROTECT MODE REGISTER

Name:RTC_WPMR Address:0x400E1B44 Access:Read-write

• WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x525443 (“RTC” in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x525443 (“RTC” in ASCII). Protects the registers: “RTC Mode Register” on page 183 “RTC Time Alarm Register” on page 187 “RTC Calendar Alarm Register” on page 188 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 7 6 5 4 3 2 1 0

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16.0 WATCHDOG TIMER (WDT)

16.1 Description

The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode.

16.2 Embedded Characteristics

• 12-bit Key-protected Programmable Counter
• Provides Reset or Interrupt Signals to the System
• Counter May Be Stopped While the Processor is in Debug State or in Idle Mode
• AMBA - compliant Interface - Interfaces to the ARM Advanced Peripheral Bus

16.3 Block Diagram

FIGURE 16-1: WATCHDOG TIMER BLOCK DIAGRAM

16.4 Functional Description

The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. = 0 set resetread WDT_SR or reset wdt_fault (to Reset Controller) set reset WDFIEN wdt_int WDT_MR SLCK1/128 12-bit Down Counter Current Value WDD WDT_MR <= WDD WDV WDRSTT WDT_MR WDT_CR reload WDUNF WDERR reload write WDT_MR WDT_MR WDRSTEN

 2020 Microchip Technology Inc. DS60001614B-page 197 SAM3X8ERT The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz). After a Processor Reset, the value of WDV is 0xFFF, corresponding to the maximum value of the counter with the exter- nal reset generation enabled (field WDRSTEN at 1 after a Backup Reset). This means that a default Watchdog is run- ning at reset, i.e., at power-up. The user must either disable it (by setting the WDDIS bit in WDT_MR) if he does not expect to use it or must reprogram it to meet the maximum Watchdog period the application requires. The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset resets it. Writing the WDT_MR register reloads the timer with the newly programmed mode parameters. In normal operation, the user reloads the Watchdog at regular intervals before the timer underflow occurs, by writing the Control Register (WDT_CR) with the bit WDRSTT to 1. The Watchdog counter is then immediately reloaded from WDT_MR and restarted, and the Slow Clock 128 divider is reset and restarted. The WDT_CR register is write-protected. As a result, writing WDT_CR without the correct hard-coded key has no effect. If an underflow does occur, the “wdt_ - fault” signal to the Reset Controller is asserted if the bit WDRSTEN is set in the Mode Register (WDT_MR). Moreover, the bit WDUNF is set in the Watchdog Status Register (WDT_SR). To prevent a software deadlock that continuously triggers the Watchdog, the reload of the Watchdog must occur while the Watchdog counter is within a window between 0 and WDD, WDD is defined in the WatchDog Mode Register WDT_MR. Any attempt to restart the Watchdog while the Watchdog counter is between WDV and WDD results in a Watchdog error, even if the Watchdog is disabled. The bit WDERR is updated in the WDT_SR and the “wdt_fault” signal to the Reset Controller is asserted. Note: This feature can be disabled by programming a WDD value greater than or equal to the WDV value. In such a configuration, restarting the Watchdog Timer is permitted in the whole range [0; WDV] and does not gen- erate an error. This is the default configuration on reset (the WDD and WDV values are equal). The status bits WDUNF (Watchdog Underflow) and WDERR (Watchdog Error) trigger an interrupt, provided the bit WDFIEN is set in the mode register. The signal “wdt_fault” to the reset controller causes a Watchdog reset if the WDRSTEN bit is set as already explained in the reset controller programmer datasheet. In that case, the processor and the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset. If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault” signal to the reset controller is deasserted. Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. FIGURE 16-2: WATCHDOG BEHAVIOR WDV WDD WDT_CR = WDRSTT Watchdog Fault Normal behavior Watchdog Error Watchdog Underflow FFF if WDRSTEN is 1 if WDRSTEN is 0 den ow tted ow

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16.5 Watchdog Timer (WDT) User Interface

TABLE 16-1: REGISTER MAPPING Offset Register Name Access Reset 0x00 Control Register WDT_CR Write-only — 0x04 Mode Register WDT_MR Read-write Once 0x3FFF_2FFF 0x08 Status Register WDT_SR Read-only 0x0000_0000

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16.5.1 WATCHDOG TIMER CONTROL REGISTER

Name:WDT_CR Address:0x400E1A50 Access:Write-only

• WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog.
• KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

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16.5.2 WATCHDOG TIMER MODE REGISTER

Name: WDT_MR Address:0x400E1A54 Access: Read-write Once

• WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter.
• WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt. 1: A Watchdog fault (underflow or error) asserts interrupt.
• WDRSTEN: Watchdog Reset Enable 0: A Watchdog fault (underflow or error) has no effect on the resets. 1: A Watchdog fault (underflow or error) triggers a Watchdog reset.
• WDRPROC: Watchdog Reset Processor 0: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates all resets. 1: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset.
• WDD: Watchdog Delta Value Defines the permitted range for reloading the Watchdog Timer. If the Watchdog Timer value is less than or equal to WDD, writing WDT_CR with WDRSTT = 1 restarts the timer. If the Watchdog Timer value is greater than WDD, writing WDT_CR with WDRSTT = 1 causes a Watchdog error.
• WDDBGHLT: Watchdog Debug Halt 0: The Watchdog runs when the processor is in debug state. 1: The Watchdog stops when the processor is in debug state.
• WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state.
• WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. 31 30 29 28 27 26 25 24 WDIDLEH LT WDDBGHL T WDD 23 22 21 20 19 18 17 16 WDD 15 14 13 12 11 10 9 8 WDDIS WDRPRO C WDRSTEN WDFIEN WDV 7 6 5 4 3 2 1 0 WDV

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16.5.3 WATCHDOG TIMER STATUS REGISTER

Name:WDT_SR Address:0x400E1A58 Access:Read-only

• WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR.
• WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR. 1: At least one Watchdog error occurred since the last read of WDT_SR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

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17.0 SUPPLY CONTROLLER (SUPC)

17.1 Description

The Supply Controller (SUPC) controls the supply voltage of the Core of the system and manages the Backup Low Power Mode. In this mode, the current consumption is reduced to a few microamps for Backup power retention. Exit from this mode is possible on multiple wake-up sources including events on FWUP or WKUP pins, or a Clock alarm. The SUPC also generates the Slow Clock by selecting either the Low Power RC oscillator or the Low Power Crystal oscillator.

17.2 Embedded Characteristics

• Manages the Core Power Supply VDDCORE and the Backup Low Power Mode by Controlling the Embedded Voltage Regulator
• Generates the Slow Clock SLCK, by Selecting Either the 22-42 kHz Low Power RC Oscillator or the 32 kHz Low Power Crystal Oscillator
• Supports Multiple Wake Up Sources, for Exit from Backup Low Power Mode - Force Wake Up Pin, with Programmable Debouncing - 16 Wake Up Inputs, with Programmable Debouncing - Real Time Clock Alarm - Real Time Timer Alarm - Supply Monitor Detection on VDDUTMI, with Programmable Scan Period and Voltage Threshold
• A Supply Monitor Detection on VDDUTMI or a Brownout Detection on VDDCORE can Trigger a Core Reset
• Embeds: - One 22 to 42 kHz Low Power RC Oscillator - One 32 kHz Low Power Crystal Oscillator - One Zero-Power Power-On Reset Cell - One Software Programmable Supply Monitor, on VDDUTMI Located in Backup Section - One Brownout Detector on VDDCORE Located in the Core

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17.3 Block Diagram

FIGURE 17-1: SUPPLY CONTROLLER BLOCK DIAGRAM Software Controlled Voltage Regulator ADC (front-end) DAC (front-end) Matrix SRAM Watchdog Timer Flash Peripherals Peripheral Bridge Zero-Power Power-on Reset Supply Monitor RTC Power Management Controller Embedded 32 kHz RC Oscillator Xtal 32 kHz Oscillator Supply Controller Embedded 12 / 8 / 4 MHz RC Oscillator Brownout Detector General Purpose Backup Registers Cortex-M3Reset Controller Backup Power Supply Core Power Supply PLLA vr_standby vr_vdd rtc_alarmSLCK proc_nreset periph_nreset ice_nreset Master Clock MCK SLCK vddcore_nreset Main Clock MAINCK SLCK NRST MAINCK PLLACK FSTT0 - FSTT15(1) XIN32 XOUT32 osc32k_xtal_en XTALSEL Slow Clock SLCK osc32k_rc_en vddcore_nreset VDDIO VDDCORE VDDOUT ADVREF ADx FWUP bodcore_on bodcore_in RTT rtt_alarmSLCK XIN XOUT VDDBU VDDIN SHDN PIOx VDDANA USB VDDUTMI USBx vr_deep sm_in sm_on supc_interrupt 3 - 20 MHz XTAL Oscillator WKUP0 - WKUP15 NRSTB PIOA/B/C Input / Output Buffers FSTT0 - FSTT15 are possible Fast Startup Sources, generated by WKUP0-WKUP15 Pins, but are not physical pins. UPLL MAINCK UPLLCK DACx

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17.4 Supply Controller Functional Description

17.4.1 SUPPLY CONTROLLER OVERVIEW

The device can be divided into two power supply areas:

• The Backup VDDBU Power Supply: including the Supply Controller, a part of the Reset Controller, the Slow Clock switch, the General Purpose Backup Registers, the Supply Monitor and the Clock which includes the Real Time Timer and the Real Time Clock
• The Core Power Supply: including the other part of the Reset Controller, the Brownout Detector, the Processor, the SRAM memory, the FLASH memory and the Peripherals The Supply Controller (SUPC) controls the supply voltage of the core power supply. The SUPC intervenes when the VDDUTMI power supply rises (when the system is starting) or when the Backup Low Power Mode is entered. The SUPC also integrates the Slow Clock generator which is based on a 32 kHz crystal oscillator and an embedded 32 kHz RC oscillator. The Slow Clock defaults to the RC oscillator, but the software can enable the crystal oscillator and select it as the Slow Clock source. The Supply Controller and the VDDUTMI power supply have a reset circuitry based on the NRSTB pin and a zero-power power-on reset cell. The zero-power power-on reset allows the SUPC to start properly as soon as the VDDUTMI voltage becomes valid. The NRSTB pin allows to reset the system from outside. At startup of the system, once the backup voltage VDDUTMI is valid and the reset pin NRSTB is not driven low and the embedded 32 kHz RC oscillator is stabilized, the SUPC starts up the core by sequentially enabling the internal Voltage Regulator, waiting that the core voltage VDDCORE is valid, then releasing the reset signal of the core “vddcore_nreset” signal. Once the system has started, the user can program a supply monitor and/or a brownout detector. If the supply monitor detects a voltage on VDDUTMI that is too low, the SUPC can assert the reset signal of the core “vddcore_nreset” signal until VDDUTMI is valid. Likewise, if the brownout detector detects a core voltage VDDCORE that is too low, the SUPC can assert the reset signal “vddcore_nreset” until VDDCORE is valid. When the Backup Low Power Mode is entered, the SUPC sequentially asserts the reset signal of the core power supply “vddcore_nreset” and disables the voltage regulator, in order to supply only the VDDUTMI power supply. In this mode the current consumption is reduced to a few microamps for Backup part retention. Exit from this mode is possible on multiple wake-up sources including an event on FWUP pin or WKUP pins, or a Clock alarm. To exit this mode, the SUPC operates in the same way as system startup.

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17.4.2 SLOW CLOCK GENERATOR

The Supply Controller embeds a slow clock generator that is supplied with the VDDBU power supply. As soon as the VDDBU is supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the embedded RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 µs). The user can select the crystal oscillator to be the source of the slow clock, as it provides a more accurate frequency. The command is made by writing the Supply Controller Control Register (SUPC_CR) with the XTALSEL bit at 1. This results in a sequence which first enables the crystal oscillator, then waits for 32,768 slow clock cycles, then switches the slow clock on the output of the crystal oscillator and then disables the RC oscillator to save power. The switch of the slow clock source is glitch free. The OSCSEL bit of the Supply Controller Status Register (SUPC_SR) allows knowing when the switch sequence is done. Coming back on the RC oscillator is only possible by shutting down the VDDBU power supply. If the user does not need the crystal oscillator, the XIN32 and XOUT32 pins should be left unconnected. The user can also set the crystal oscillator in bypass mode instead of connecting a crystal. In this case, the user has to provide the external clock signal on XIN32. The input characteristics of the XIN32 pin are given in the product electrical characteristics section. In order to set the bypass mode, the OSCBYPASS bit of the Supply Controller Mode Register (SUPC_MR) needs to be set at 1.

17.4.3 VOLTAGE REGULATOR CONTROL/BACKUP LOW POWER MODE

The Supply Controller can be used to control the embedded 1.8V voltage regulator. The voltage regulator automatically adapts its quiescent current depending on the required load current. Refer to the electrical characteristics section. The programmer can switch off the voltage regulator, and thus put the device in Backup mode, by writing the Supply Controller Control Register (SUPC_CR) with the VROFF bit at 1. This can be done also by using WFE (Wait for Event) Cortex-M3 instruction with the deep mode bit set to 1. The Backup mode can also be entered by executing the WFI (Wait for Interrupt) or WFE (Wait for Event) Cortex-M3 instructions. To select the Backup mode entry mechanism, two options are available, depending on the SLEEPONEXIT bit in the Cortex-M3 System Control register:

• Sleep-now: if the SLEEPONEXIT bit is cleared, the device enters Backup mode as soon as the WFI or WFE instruction is executed.
• Sleep-on-exit: if the SLEEPONEXIT bit is set when the WFI instruction is executed, the device enters Backup mode as soon as it exits the lowest priority ISR. This asserts the vddcore_nreset signal after the write resynchronization time which lasts, in the worse case, two slow clock cycles. Once the vddcore_nreset signal is asserted, the processor and the peripherals are stopped one slow clock cycle before the core power supply shuts off. When the user does not use the internal voltage regulator and wants to supply VDDCORE by an external supply, it is possible to disable the voltage regulator. Note: It is different from the Backup mode. Depending on the application, disabling the voltage regulator can reduce power consumption as the voltage regulator input (VDDIN) is shared with the ADC and DAC. This is done through ONREG bit in SUPC_MR.

17.4.4 USING BACKUP BATTERIES/BACKUP SUPPLY

The product can be used with or without backup batteries, or more generally a backup supply. When a backup supply is used (See Figure 17-2), only VDDBU voltage is present in Backup mode and no other external supply is applied on the chip. In this case the user needs to clear VDDIORDY bit in the Supply Controller Mode Register (SUPC_MR) at least two slow clock periods before VDDIO voltage is removed. When waking up from Backup mode, the programmer needs to set VDDIORDY .

DS60001614B-page 206  2020 Microchip Technology Inc. FIGURE 17-2: SEPARATED BACKUP SUPPLY POWERING SCHEME Note: Restrictions: With Main Supply < 3V, some peripherals such as USB and ADC might not be operational. Refer to the DC Characteristics of the product for actual possible ranges for such peripherals. When a separated backup supply for VDDBU is not used (See Figure 17-3), since the external voltage applied on VDDIO is kept, all of the I/O configurations (i.e. WKUP pin configuration) are kept during backup mode. When not using backup batteries, VDDIORDY is set so the user does not need to program it. VDDBU VDDIN Vo l t ag e Reg u l at o r VDDOUT Main Supply (3V-3.6V) VDDC ORE Back up Batteries VDDIO VDD ANA VDDUTMI VDDPLL FWUP SHDN

 2020 Microchip Technology Inc. DS60001614B-page 207 SAM3X8ERT FIGURE 17-3: NO SEPARATED BACKUP SUPPLY POWERING SCHEME Note: Restrictions: With Main Supply < 3V, some peripherals such as USB and ADC might not be operational. Refer to the DC Characteristics of the product for actual possible ranges for such peripherals.

17.4.5 SUPPLY MONITOR

The Supply Controller embeds a supply monitor which is located in the VDDBU Backup Power Supply and which mon- itors VDDUTMI power supply. The supply monitor can be used to prevent the processor from falling into an unpredictable state if the Main power sup- ply drops below a certain level. The threshold of the supply monitor is programmable. It can be selected from 1.9V to 3.4V by steps of 100 mV. This threshold is programmed in the SMTH field of the Supply Controller Supply Monitor Mode Register (SUPC_SMMR). The supply monitor can also be enabled during one slow clock period on every one of either 32, 256 or 2048 slow clock periods, according to the choice of the user. This can be configured by programming the SMSMPL field in SUP - C_SMMR. Enabling the supply monitor for such reduced times allows to divide the typical supply monitor power consumption respectively by factors of 32, 256 or 2048, if the user does not need a continuous monitoring of the VDDUTMI power supply. A supply monitor detection can either generate a reset of the core power supply or a wake up of the core power supply. Generating a core reset when a supply monitor detection occurs is enabled by writing the SMRSTEN bit to 1 in SUP - C_SMMR. Waking up the core power supply when a supply monitor detection occurs can be enabled by programming the SMEN bit to 1 in the Supply Controller Wake Up Mode Register (SUPC_WUMR). The Supply Controller provides two status bits in the Supply Controller Status Register for the supply monitor which allows to determine whether the last wake up was due to the supply monitor: VDDBU VDDIN Vo l t ag e Reg u l at o r VDDOUT Main Supply (3V-3.6V) VDDC ORE VDDIO VDD ANA VDDUTMI VDDPLL

DS60001614B-page 208  2020 Microchip Technology Inc.

• The SMOS bit provides real time information, which is updated at each measurement cycle or updated at each Slow Clock cycle, if the measurement is continuous.
• The SMS bit provides saved information and shows a supply monitor detection has occurred since the last read of SUPC_SR. The SMS bit can generate an interrupt if the SMIEN bit is set to 1 in the Supply Controller Supply Monitor Mode Register (SUPC_SMMR). FIGURE 17-4: SUPPLY MONITOR STATUS BIT AND ASSOCIATED INTERRUPT

17.4.6 BACKUP POWER SUPPLY RESET

17.4.6.1 Raising the Backup Power Supply

As soon as the backup voltage VDDUTMI rises, the RC oscillator is powered up and the zero-power power-on reset cell maintains its output low as long as VDDUTMI has not reached its target voltage. During this time, the Supply Controller is entirely reset. When the VDDUTMI voltage becomes valid and zero-power power-on reset signal is released, a counter is started for 5 slow clock cycles. This is the time it takes for the 32 kHz RC oscillator to stabilize. After this time, the SHDN pin is asserted and the voltage regulator is enabled. The core power supply rises and the brownout detector provides the bodcore_in signal as soon as the core voltage VDDCORE is valid. This results in releas- ing the vddcore_nreset signal to the Reset Controller after the bodcore_in signal has been confirmed as being valid for at least one slow clock cycle. Supply Monitor ON 3.3 V 0 V Threshold SMS and SUPC interrupt Read SUPC_SR Periodic Sampling Continuous Sampling (SMSMPL = 1)

 2020 Microchip Technology Inc. DS60001614B-page 209 SAM3X8ERT FIGURE 17-5: RAISING THE VDDUTMI POWER SUPPLY

17.4.6.2 NRSTB Asynchronous Reset Pin

The NRSTB pin is an asynchronous reset input, which acts exactly like the zero-power power-on reset cell. As soon as NRSTB is tied to GND, the supply controller is reset generating in turn, a reset of the whole system. When NRSTB is released, the system can start as described in “Raising the Backup Power Supply” on page 208. The NRSTB pin does not need to be driven during power-up phase to allow a reset of the system, it is done by the zero- power power-on cell. wer Power-On Cell output - 42 kHz RC cillator output Fast RC cillator output Power Supply SHDN / vr_on bodcore_in dcore_nreset NRST proc_nreset Note: After “proc_nreset” rising, the core starts fecthing instructions from Flash at 4 MHz. periph_nreset 7 x Slow Clock Cycles 3 x Slow Clock Cycles 3 x Slow Clock Cycles 6.5 x Slow Clock Cycles TON Voltage Regulator Zero-Power POR Power Supply

DS60001614B-page 210  2020 Microchip Technology Inc. FIGURE 17-6: NRSTB RESET Note: periph_nreset, ice_reset and proc_nreset are not shown, but are asserted low thanks to the vddcore_nreset signal controlling the Reset controller.

17.4.6.3 SHDN output pin

As shown in Figure 17-6, the SHDN pin acts like the vr_standby signal making it possible to use the SHDN pin to control external voltage regulator with shutdown capabilities.

17.4.7 CORE RESET

The Supply Controller manages the vddcore_nreset signal to the Reset Controller, as described previously in “Backup Power Supply Reset” on page 208. The vddcore_nreset signal is normally asserted before shutting down the core power supply and released as soon as the core power supply is correctly regulated. There are two additional sources which can be programmed to activate vddcore_nreset:

• a supply monitor detection
• a brownout detection

17.4.7.1 Supply Monitor Reset

The supply monitor is capable of generating a reset of the system. This can be enabled by setting the SMRSTEN bit in the Supply Controller Supply Monitor Mode Register (SUPC_SMMR). If SMRSTEN is set and if a supply monitor detection occurs, the vddcore_nreset signal is immediately activated for a minimum of 1 slow clock cycle.

17.4.7.2 Brownout Detector Reset

The brownout detector provides the bodcore_in signal to the SUPC which indicates that the voltage regulation is oper- ating as programmed. If this signal is lost for longer than 1 slow clock period while the voltage regulator is enabled, the Supply Controller can assert vddcore_nreset. This feature is enabled by writing the bit, BODRSTEN (Brownout Detector Reset Enable) to 1 in the Supply Controller Mode Register (SUPC_MR). If BODRSTEN is set and the voltage regulation is lost (output voltage of the regulator too low), the vddcore_nreset signal is asserted for a minimum of 1 slow clock cycle and then released if bodcore_in has been reactivated. The BODRSTS bit is set in the Supply Controller Status Register (SUPC_SR) so that the user can know the source of the last reset. Until bodcore_in is deactivated, the vddcore_nreset signal remains active.

17.4.8 WAKE UP SOURCES

The wake up events allow the device to exit backup mode. When a wake up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply.

30 Slow Clock Cycles = about 1ms between 2 and 3 Slow Clock Cy

SHDN / vr_standby bodcore_in vddcore_nreset

 2020 Microchip Technology Inc. DS60001614B-page 211 SAM3X8ERT FIGURE 17-7: WAKE UP SOURCE

17.4.8.1 Force Wake Up

The FWUP pin is enabled as a wake up source by writing the FWUPEN bit to 1 in the Supply Controller Wake Up Mode Register (SUPC_WUMR). Then, the FWUPDBC field in the same register selects the debouncing period, which can be selected between 3, 32, 512, 4,096 or 32,768 slow clock cycles. This corresponds respectively to about 100 µs, about 1 ms, about 16 ms, about 128 ms and about 1 second (for a typical slow clock frequency of 32 kHz). Programming FWUPDBC to 0x0 selects an immediate wake up, i.e., the FWUP must be low during a minimum of one slow clock period to wake up the core power supply. If the FWUP pin is asserted for a time longer than the debouncing period, a wake up of the core power supply is started and the FWUP bit in the Supply Controller Status Register (SUPC_SR) is set and remains high until the register is read.

17.4.8.2 Wake Up Inputs

The wake up inputs, WKUP0 to WKUP15, can be programmed to perform a wake up of the core power supply. Each input can be enabled by writing to 1 the corresponding bit, WKUPEN0 to WKUPEN 15, in the Wake Up Inputs Register (SUPC_WUIR). The wake up level can be selected with the corresponding polarity bit, WKUPPL0 to WKUPPL15, also located in SUPC_WUIR. All the resulting signals are wired-ORed to trigger a debounce counter, which can be programmed with the WKUPDBC field in the Supply Controller Wake Up Mode Register (SUPC_WUMR). The WKUPDBC field can select a debouncing period of 3, 32, 512, 4,096 or 32,768 slow clock cycles. This corresponds respectively to about 100 µs, about 1 ms, about 16 ms, about 128 ms and about 1 second (for a typical slow clock frequency of 32 kHz). Programming WKUPDBC to 0x0 selects an immediate wake up, i.e., an enabled WKUP pin must be active according to its polarity during a min- imum of one slow clock period to wake up the core power supply. P15 UP rtt_alarm rtc_alarm sm_int UP0 UP1 WKUPT1 C S R Debouncer WKUPDBC WKUPS Debouncer FWUPDBC FWUP WKUPIS0 WKUPIS1 WKUPIS15 RTTEN RTCEN SMEN WKUPEN15 WKUPEN1 WKUPEN0 FWUPEN WKUPT15 Falling/Rising Edge Detector WKUPT0 Falling/Rising Edge Detector Falling/Rising Edge Detector Falling Edge Detector SLCK SLCK

DS60001614B-page 212  2020 Microchip Technology Inc. If an enabled WKUP pin is asserted for a time longer than the debouncing period, a wake up of the core power supply is started and the signals, WKUP0 to WKUP15 as shown in Figure 17-7, are latched in the Supply Controller Status Register (SUPC_SR). This allows the user to identify the source of the wake up, however, if a new wake up condition occurs, the primary information is lost. No new wake up can be detected since the primary wake up condition has dis - appeared.

17.4.8.3 Clock Alarms

The RTC and the RTT alarms can generate a wake up of the core power supply. This can be enabled by writing respec- tively, the bits RTCEN and RTTEN to 1 in the Supply Controller Wake Up Mode Register (SUPC_WUMR). The Supply Controller does not provide any status as the information is available in the User Interface of either the Real Time Timer or the Real Time Clock.

17.4.8.4 Supply Monitor Detection

The supply monitor can generate a wakeup of the core power supply. See “Supply Monitor” on page 207.

 2020 Microchip Technology Inc. DS60001614B-page 213 SAM3X8ERT

17.5 Supply Controller (SUPC) User Interface

The User Interface of the Supply Controller is part of the System Controller User Interface.

17.5.1 SYSTEM CONTROLLER (SYSC) USER INTERFACE

17.5.2 SYSTEM CONTROLLER (SYSC) USER INTERFACE

TABLE 17-1: SYSTEM CONTROLLER REGISTERS Offset System Controller Peripheral Name 0x00-0x0c Reset Controller RSTC 0x10-0x2C Supply Controller SUPC 0x30-0x3C Real Time Timer RTT 0x50-0x5C Watchdog WDT 0x60-0x7C Real Time Clock RTC 0x90-0xDC General Purpose Backup Register GPBR TABLE 17-2: REGISTER MAPPING Offset Register Name Access Reset 0x00 Supply Controller Control Register SUPC_CR Write-only N/A 0x04 Supply Controller Supply Monitor Mode Register SUPC_SMMR Read-write 0x0000_0000 0x08 Supply Controller Mode Register SUPC_MR Read-write 0x0000_5A00 0x0C Supply Controller Wake Up Mode Register SUPC_WUMR Read-write 0x0000_0000 0x10 Supply Controller Wake Up Inputs Register SUPC_WUIR Read-write 0x0000_0000 0x14 Supply Controller Status Register SUPC_SR Read-only 0x0000_0800 0x18 Reserved — — —

DS60001614B-page 214  2020 Microchip Technology Inc.

17.5.3 SUPPLY CONTROLLER CONTROL REGISTER

Name:SUPC_CR Address:0x400E1A10 Access:Write-only

• VROFF: Voltage Regulator Off 0 (NO_EFFECT) = no effect. 1 (STOP_VREG) = if KEY is correct, asserts vddcore_nreset and stops the voltage regulator.
• XTALSEL: Crystal Oscillator Select 0 (NO_EFFECT) = no effect. 1 (CRYSTAL_SEL) = if KEY is correct, switches the slow clock on the crystal oscillator output.
• KEY: Password Should be written to value 0xA5. Writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

 2020 Microchip Technology Inc. DS60001614B-page 215 SAM3X8ERT

17.5.4 SUPPLY CONTROLLER SUPPLY MONITOR MODE REGISTER

Name:SUPC_SMMR Address:0x400E1A14 Access:Read-write

• SMTH: Supply Monitor Threshold 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — — SMIEN SMRSTEN — SMSMPL 7 6 5 4 3 2 1 0 — — — — SMTH Value Name Description 0x0 1_9V 1.9 V 0x1 2_0V 2.0 V 0x2 2_1V 2.1 V 0x3 2_2V 2.2 V 0x4 2_3V 2.3 V 0x5 2_4V 2.4 V 0x6 2_5V 2.5 V 0x7 2_6V 2.6 V 0x8 2_7V 2.7 V 0x9 2_8V 2.8 V 0xA 2_9V 2.9 V 0xB 3_0V 3.0 V 0xC 3_1V 3.1 V 0xD 3_2V 3.2 V 0xE 3_3V 3.3 V 0xF 3_4V 3.4 V

DS60001614B-page 216  2020 Microchip Technology Inc.

• SMSMPL: Supply Monitor Sampling Period
• SMRSTEN: Supply Monitor Reset Enable 0 (NOT_ENABLE) = the core reset signal “vddcore_nreset” is not affected when a supply monitor detection occurs. 1 (ENABLE) = the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs.
• SMIEN: Supply Monitor Interrupt Enable 0 (NOT_ENABLE) = the SUPC interrupt signal is not affected when a supply monitor detection occurs. 1 (ENABLE) = the SUPC interrupt signal is asserted when a supply monitor detection occurs. Value Name Description 0x0 SMD Supply Monitor disabled 0x1 CSM Continuous Supply Monitor 0x2 32SLCK Supply Monitor enabled one SLCK period every 32 SLCK periods 0x3 256SLCK Supply Monitor enabled one SLCK period every 256 SLCK periods 0x4 2048SLCK Supply Monitor enabled one SLCK period every 2,048 SLCK periods 0x5-0x7 Reserved Reserved

 2020 Microchip Technology Inc. DS60001614B-page 217 SAM3X8ERT

17.5.5 SUPPLY CONTROLLER MODE REGISTER

Name:SUPC_MR Address:0x400E1A18 Access:Read-write

• BODRSTEN: Brownout Detector Reset Enable 0 (NOT_ENABLE) = the core reset signal “vddcore_nreset” is not affected when a brownout detection occurs. 1 (ENABLE) = the core reset signal, vddcore_nreset is asserted when a brownout detection occurs.
• BODDIS: Brownout Detector Disable 0 (ENABLE) = the core brownout detector is enabled. 1 (DISABLE) = the core brownout detector is disabled.
• VDDIORDY: VDDIO Ready 0 (VDDIO_REMOVED) = VDDIO is removed (used before going to backup mode when backup batteries are used) 1 (VDDIO_PRESENT) = VDDIO is present (used before going to backup mode when backup batteries are used) If the backup batteries are not used, VDDIORDY must be kept set to 1.
• ONREG: Voltage Regulator enable 0 (ONREG_UNUSED) = Voltage Regulator is not used 1 (ONREG_USED) = Voltage Regulator is used
• OSCBYPASS: Oscillator Bypass 0 (NO_EFFECT) = no effect. Clock selection depends on XTALSEL value. 1 (BYPASS) = the 32-KHz XTAL oscillator is selected and is put in bypass mode.
• KEY: Password Key Should be written to value 0xA5. Writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 — — — OSCBYPA SS — — — — 15 14 13 12 11 10 9 8 — VDDIORD Y ONREG BODDIS BODRSTE N — — — — 7 6 5 4 3 2 1 0

DS60001614B-page 218  2020 Microchip Technology Inc.

17.5.6 SUPPLY CONTROLLER WAKE UP MODE REGISTER

Name:SUPC_WUMR Address:0x400E1A1C Access:Read-write

• FWUPEN: Force Wake Up Enable 0 (NOT_ENABLE) = the Force Wake Up pin has no wake up effect. 1 (ENABLE) = the Force Wake Up pin low forces the wake up of the core power supply.
• SMEN: Supply Monitor Wake Up Enable 0 (NOT_ENABLE) = the supply monitor detection has no wake up effect. 1 (ENABLE) = the supply monitor detection forces the wake up of the core power supply.
• RTTEN: Real Time Timer Wake Up Enable 0 (NOT_ENABLE) = the RTT alarm signal has no wake up effect. 1 (ENABLE) = the RTT alarm signal forces the wake up of the core power supply.
• RTCEN: Real Time Clock Wake Up Enable 0 (NOT_ENABLE) = the RTC alarm signal has no wake up effect. 1 (ENABLE) = the RTC alarm signal forces the wake up of the core power supply.
• FWUPDBC: Force Wake Up Debouncer Period 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — WKUPDBC — FWUPDBC 7 6 5 4 3 2 1 0 — — — — RTCEN RTTEN SMEN FWUPEN Value Name Description 0 IMMEDIATE Immediate, no debouncing, detected active at least on one Slow Clock edge. 1 3_SCLK FWUP shall be low for at least 3 SLCK periods 2 32_SCLK FWUP shall be low for at least 32 SLCK periods 3 512_SCLK FWUP shall be low for at least 512 SLCK periods 4 4096_SCLK FWUP shall be low for at least 4,096 SLCK periods 5 32768_SCLK FWUP shall be low for at least 32,768 SLCK periods

6 Reserved Reserved

7 Reserved Reserved

 2020 Microchip Technology Inc. DS60001614B-page 219 SAM3X8ERT

• WKUPDBC: Wake Up Inputs Debouncer Period Value Name Description 0 IMMEDIATE Immediate, no debouncing, detected active at least on one Slow Clock edge. 1 3_SCLK WKUPx shall be in its active state for at least 3 SLCK periods 2 32_SCLK WKUPx shall be in its active state for at least 32 SLCK periods 3 512_SCLK WKUPx shall be in its active state for at least 512 SLCK periods 4 4096_SCLK WKUPx shall be in its active state for at least 4,096 SLCK periods 5 32768_SCLK WKUPx shall be in its active state for at least 32,768 SLCK periods

DS60001614B-page 220  2020 Microchip Technology Inc.

17.5.7 SYSTEM CONTROLLER WAKE UP INPUTS REGISTER

Name:SUPC_WUIR Address:0x400E1A20 Access:Read-write

• WKUPEN0 - WKUPEN15: Wake Up Input Enable 0 to 15 0 (NOT_ENABLE) = the corresponding wake-up input has no wake up effect. 1 (ENABLE) = the corresponding wake-up input forces the wake up of the core power supply.
• WKUPT0 - WKUPT15: Wake Up Input Transition 0 to 15 0 (HIGH_TO_LOW) = a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. 1 (LOW_TO_HIGH) = a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. 31 30 29 28 27 26 25 24 WKUPT1 WKUPT1 WKUPT1 WKUPT1

2 WKUPT11 WKUPT10 WKUPT9 WKUPT8

WKUPT7 WKUPT6 WKUPT5 WKUPT4 WKUPT3 WKUPT2 WKUPT1 WKUPT0 15 14 13 12 11 10 9 8 WKUPEN WKUPEN WKUPEN WKUPEN

12 WKUPEN11 WKUPEN10 WKUPEN9 WKUPEN8

4 WKUPEN3 WKUPEN2 WKUPEN1 WKUPEN0

 2020 Microchip Technology Inc. DS60001614B-page 221 SAM3X8ERT

17.5.8 SUPPLY CONTROLLER STATUS REGISTER

Name:SUPC_SR Address:0x400E1A24 Access:Read-write Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK), the status reg- ister flag reset is taken into account only 2 slow clock cycles after the read of the SUPC_SR.

• FWUPS: FWUP Wake Up Status 0 (NO) = no wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. 1 (PRESENT) = at least one wake up due to the assertion of the FWUP pin has occurred since the last read of SUP - C_SR.
• WKUPS: WKUP Wake Up Status 0 (NO) = no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. 1 (PRESENT) = at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUP- C_SR.
• SMWS: Supply Monitor Detection Wake Up Status 0 (NO) = no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. 1 (PRESENT) = at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR.
• BODRSTS: Brownout Detector Reset Status 0 (NO) = no core brownout rising edge event has been detected since the last read of the SUPC_SR. 1 (PRESENT) = at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. When the voltage remains below the defined threshold, there is no rising edge event at the output of the brownout detec- tion cell. The rising edge event occurs only when there is a voltage transition below the threshold.
• SMRSTS: Supply Monitor Reset Status 0 (NO) = no supply monitor detection has generated a core reset since the last read of the SUPC_SR. 1 (PRESENT) = at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR.
• SMS: Supply Monitor Status 0 (NO) = no supply monitor detection since the last read of SUPC_SR. 1 (PRESENT) = at least one supply monitor detection since the last read of SUPC_SR.
• SMOS: Supply Monitor Output Status 0 (HIGH) = the supply monitor detected VDDUTMI higher than its threshold at its last measurement. 1 (LOW) = the supply monitor detected VDDUTMI lower than its threshold at its last measurement.
• OSCSEL: 32-kHz Oscillator Selection Status 0 (RC) = the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. 1 (CRYST) = the slow clock, SLCK is generated by the 32-kHz crystal oscillator. 31 30 29 28 27 26 25 24 WKUPIS15 WKUPIS14 WKUPIS13 WKUPIS12 WKUPIS11 WKUPIS10 WKUPIS9 WKUPIS8 23 22 21 20 19 18 17 16 WKUPIS7 WKUPIS6 WKUPIS5 WKUPIS4 WKUPIS3 WKUPIS2 WKUPIS1 WKUPIS0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSCSEL SMOS SMS SMRSTS BODRSTS SMWS WKUPS FWUPS

DS60001614B-page 222  2020 Microchip Technology Inc.

• FWUPIS: FWUP Input Status 0 (LOW) = FWUP input is tied low. 1 (HIGH) = FWUP input is tied high.
• WKUPIS0-WKUPIS15: WKUP Input Status 0 to 15 0 (DIS) = the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. 1 (EN) = the corresponding wake-up input was active at the time the debouncer triggered a wake up event.

 2020 Microchip Technology Inc. DS60001614B-page 223 SAM3X8ERT

18.0 GENERAL PURPOSE BACKUP REGISTERS (GPBR)

18.1 Description

The System Controller embeds Eight general-purpose backup registers.

18.2 Embedded Characteristics

• Eight 32-bit General Purpose Backup Registers

18.3 General Purpose Backup Registers (GPBR) User Interface

TABLE 18-1: REGISTER MAPPING Offset Register Name Access Reset 0x0 General Purpose Backup Register 0 SYS_GPBR0 Read-write — 0x1c General Purpose Backup Register 7 SYS_GPBR7 Read-write —

DS60001614B-page 224  2020 Microchip Technology Inc.

18.3.1 GENERAL PURPOSE BACKUP REGISTER X

Name: SYS_GPBRx Address: 0x400E1A90 [0] .. 0x400E1AAC [7] Access: Read-write

• GPBR_VALUEx: Value of GPBR x 31 30 29 28 27 26 25 24 GPBR_VALUEx 23 22 21 20 19 18 17 16 GPBR_VALUEx 15 14 13 12 11 10 9 8 GPBR_VALUEx 7 6 5 4 3 2 1 0 GPBR_VALUEx

 2020 Microchip Technology Inc. DS60001614B-page 225 SAM3X8ERT

19.0 ENHANCED EMBEDDED FLASH CONTROLLER (EEFC)

19.1 Description

The Enhanced Embedded Flash Controller (EEFC) ensures the interface of the Flash block with the 32-bit internal bus. Its 128-bit or 64-bit wide memory interface increases performance. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash organization, thus making the software generic.

19.2 Embedded Characteristics

• Interface of the Flash Block with the 32-bit Internal Bus
• Increases Performance in Thumb2® Mode with 128-bit or -64 bit Wide Memory Interface up to 23 MHz
• 16 Lock Bits, Each Protecting a Lock Region
• 3 General-purpose GPNVM Bits
• One-by-one Lock Bit Programming
• Commands Protected by a Keyword
• Erases the Entire Flash
• Possibility of Erasing before Programming
• Locking and Unlocking Operations
• Consecutive Programming and Locking Operations
• Possibility to read the Calibration Bits

19.3 Product Dependencies

19.3.1 POWER MANAGEMENT

The Enhanced Embedded Flash Controller (EEFC) is continuously clocked. The Power Management Controller has no effect on its behavior.

19.3.2 INTERRUPT SOURCES

The Enhanced Embedded Flash Controller (EEFC) interrupt line is connected to the Nested Vectored Interrupt Control- ler (NVIC). Using the Enhanced Embedded Flash Controller (EEFC) interrupt requires the NVIC to be programmed first. The EEFC interrupt is generated only on FRDY bit rising.

19.4 Functional Description

19.4.1 EMBEDDED FLASH ORGANIZATION

The embedded Flash interfaces directly with the 32-bit internal bus. The embedded Flash is composed of:

• One memory plane organized in several pages of the same size.
• Two 128-bit or 64-bit read buffers used for code read optimization.
• One 128-bit or 64-bit read buffer used for data read optimization.
• One write buffer that manages page programming. The write buffer size is equal to the page size. This buffer is write-only and accessible all along the 1 MByte address space, so that each word can be written to its final address.
• Several lock bits used to protect write/erase operation on several pages (lock region). A lock bit is associated with a lock region composed of several pages in the memory plane.
• Several bits that may be set and cleared through the Enhanced Embedded Flash Controller (EEFC) interface, called General Purpose Non Volatile Memory bits (GPNVM bits). TABLE 19-1: PERIPHERAL IDS Instance ID EFC0 6 EFC1 7

DS60001614B-page 226  2020 Microchip Technology Inc. The embedded Flash size, the page size, the lock regions organization and GPNVM bits definition are described in the product definition section. The Enhanced Embedded Flash Controller (EEFC) returns a descriptor of the Flash con - trolled after a get descriptor command issued by the application (see “Getting Embedded Flash Descriptor” on page 230). FIGURE 19-1: EMBEDDED FLASH ORGANIZATION Start Address Page 0 Lock Region 0 Lock Region 1 Memory Plane Page (m-1) Lock Region (n-1) Page (n*m-1)Start Address + Flash size -1 Lock Bit 0 Lock Bit 1 Lock Bit (n-1)

 2020 Microchip Technology Inc. DS60001614B-page 227 SAM3X8ERT

19.4.2 READ OPERATIONS

An optimized controller manages embedded Flash reads, thus increasing performance when the processor is running in Thumb2 mode by means of the 128- or 64- bit wide memory interface. The Flash memory is accessible through 8-, 16- and 32-bit reads. As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded Flash wraps around the address space and appears to be repeated within it. The read operations can be performed with or without wait states. Wait states must be programmed in the field FWS (Flash Read Wait State) in the Flash Mode Register (EEFC_FMR). Defining FWS to be 0 enables the single-cycle access of the embedded Flash. Refer to the Electrical Characteristics for more details. 19.4.2.1 128-bit or 64-bit Access Mode By default the read accesses of the Flash are performed through a 128-bit wide memory interface. It enables better sys- tem performance especially when 2 or 3 wait state needed. For systems requiring only 1 wait state, or to privilege current consumption rather than performance, the user can select a 64-bit wide memory access via the FAM bit in the Flash Mode Register (EEFC_FMR) Refer to the electrical characteristics section of the product datasheet for more details.

19.4.2.2 Code Read Optimization

A system of 2 x 128-bit or 2 x 64-bit buffers is added in order to optimize sequential Code Fetch. Note: Immediate consecutive code read accesses are not mandatory to benefit from this optimization. FIGURE 19-2: CODE READ OPTIMIZATION FOR FWS = 0 Note: When FWS is equal to 0, all the accesses are performed in a single-cycle access. sh Access 0 (128bits) ster Clock Request (32-bit) XXX ta To ARM Bytes 0-15 Bytes 16-31 Bytes 32-47 Bytes 0-15 1 (128bits) Bytes 32-47 Bytes 0-3 Bytes 4-7 Bytes 8-11 Bytes 12-15 Bytes 16-19 Bytes 20-23 Bytes 24-27XXX XXX Bytes 16-31 @Byte 0 @Byte 4 @Byte 8 @Byte 12 @Byte 16 @Byte 20 @Byte 24 @Byte 28 @By Byte

DS60001614B-page 228  2020 Microchip Technology Inc. FIGURE 19-3: CODE READ OPTIMIZATION FOR FWS = 3 Note: When FWS is included between 1 and 3, in case of sequential reads, the first access takes (FWS+1) cycles, the other ones only 1 cycle.

19.4.2.3 Data Read Optimization

The organization of the Flash in 128 bits (or 64 bits) is associated with two 128-bit (or 64-bit) prefetch buffers and one 128-bit (or 64-bit) data read buffer, thus providing maximum system performance. This buffer is added in order to store the requested data plus all the data contained in the 128-bit (64-bit) aligned data. This speeds up sequential data reads if, for example, FWS is equal to 1 (see Figure 19-4). Note: No consecutive data read accesses are mandatory to benefit from this optimization. FIGURE 19-4: DATA READ OPTIMIZATION FOR FWS = 1

19.4.3 FLASH COMMANDS

The Enhanced Embedded Flash Controller (EEFC) offers a set of commands such as programming the memory Flash, locking and unlocking lock regions, consecutive programming and locking and full Flash erasing, etc. lash Access r 0 (128bits) aster Clock RM Request (32-bit) ata To ARM r 1 (128bits) 0-3 XXX XXX Bytes 16-31 @Byte 0 @4 @8 Bytes 0-15 Bytes 16-31 Bytes 32-47 Bytes 48-63 XXX Bytes 0-15 4-7 8-11 12-15 @12 @16 @20 24-27 28-31 32-35 36-3916-19 20-23 40-43 44-47 Bytes 32-47 sh Access r (128bits) ster Clock Request (32-bit) XXX a To ARM Bytes 0-15 Bytes 16-31 Bytes 0-15 Bytes 0-3 4-7 8-11 12-15 16-19 20-23XXX Bytes 16-31 XXX Bytes 32-4 24-27 28-31

 2020 Microchip Technology Inc. DS60001614B-page 229 SAM3X8ERT Commands and read operations can be performed in parallel only on different memory planes. Code can be fetched from one memory plane while a write or an erase operation is performed on another. In order to perform one of these commands, the Flash Command Register (EEFC_FCR) has to be written with the cor- rect command using the FCMD field. As soon as the EEFC_FCR register is written, the FRDY flag and the FVALUE field in the EEFC_FRR register are automatically cleared. Once the current command is achieved, then the FRDY flag is automatically set. If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the corresponding interrupt line of the NVIC is activated. Note: This is true for all commands except for the STUI Command. The FRDY flag is not set when the STUI com- mand is achieved. All the commands are protected by the same keyword, which has to be written in the 8 highest bits of the EEFC_FCR register. Writing EEFC_FCR with data that does not contain the correct key and/or with an invalid command has no effect on the whole memory plane, but the FCMDE flag is set in the EEFC_FSR register. This flag is automatically cleared by a read access to the EEFC_FSR register. When the current command writes or erases a page in a locked region, the command has no effect on the whole mem- ory plane, but the FLOCKE flag is set in the EEFC_FSR register. This flag is automatically cleared by a read access to the EEFC_FSR register. TABLE 19-2: SET OF COMMANDS Command Value Mnemonic Get Flash Descriptor 0x00 GETD Write page 0x01 WP Write page and lock 0x02 WPL Erase page and write page 0x03 EWP Erase page and write page then lock 0x04 EWPL Erase all 0x05 EA Set Lock Bit 0x08 SLB Clear Lock Bit 0x09 CLB Get Lock Bit 0x0A GLB Set GPNVM Bit 0x0B SGPB Clear GPNVM Bit 0x0C CGPB Get GPNVM Bit 0x0D GGPB Start Read Unique Identifier 0x0E STUI Stop Read Unique Identifier 0x0F SPUI Get CALIB Bit 0x10 GCALB

DS60001614B-page 230  2020 Microchip Technology Inc. FIGURE 19-5: COMMAND STATE CHART

19.4.3.1 Getting Embedded Flash Descriptor

This command allows the system to learn about the Flash organization. The system can take full advantage of this infor- mation. For instance, a device could be replaced by one with more Flash capacity, and so the software is able to adapt itself to the new configuration. To get the embedded Flash descriptor, the application writes the GETD command in the EEFC_FCR register. The first word of the descriptor can be read by the software application in the EEFC_FRR register as soon as the FRDY flag in the EEFC_FSR register rises. The next reads of the EEFC_FRR register provide the following word of the descriptor. If extra read operations to the EEFC_FRR register are done after the last word of the descriptor has been returned, then the EEFC_FRR register value is 0 until the next valid command. Check if FRDY flag Set No Yes Read Status: MC_FSR Write FCMD and PAGENB in Flash Command Register Check if FLOCKE flag Set Check if FRDY flag Set No Read Status: MC_FSR Yes Yes Locking region violation No Check if FCMDE flag Set Yes No Bad keyword violation Command Successfull

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19.4.3.2 Write Commands

Several commands can be used to program the Flash. Flash technology requires that an erase is done before programming. The full memory plane can be erased at the same time, or several pages can be erased at the same time (refer to Section ”The Partial Programming mode works only with 128-bit (or higher) boundaries. It cannot be used with boundaries lower than 128 bits (8, 16 or 32-bit for example).”). Also, a page erase can be automatically done before a page write using EWP or EWPL commands. After programming, the page (the whole lock region) can be locked to prevent miscellaneous write or erase sequences. The lock bit can be automatically set after page programming using WPL or EWPL commands. Data to be written are stored in an internal latch buffer. The size of the latch buffer corresponds to the page size. The latch buffer wraps around within the internal memory area address space and is repeated as many times as the number of pages within this address space. Note: riting of 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption. Write operations are performed in a number of wait states equal to the number of wait states for read operations. Data are written to the latch buffer before the programming command is written to the Flash Command Register EEF - C_FCR. The sequence is as follows:

• Write the full page, at any page address, within the internal memory area address space.
• Programming starts as soon as the page number and the programming command are written to the Flash Com- mand Register. The FRDY bit in the Flash Programming Status Register (EEFC_FSR) is automatically cleared.
• When programming is completed, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in EEFC_FMR, the corresponding interrupt line of the NVIC is activated. Two errors can be detected in the EEFC_FSR register after a programming sequence:
• a Command Error: a bad keyword has been written in the EEFC_FCR register.
• a Lock Error: the page to be programmed belongs to a locked region. A command must be previously run to unlock the corresponding region. By using the WP command, a page can be programmed in several steps if it has been erased before (see Figure 19-6). TABLE 19-3: FLASH DESCRIPTOR DEFINITION Symbol Word Index Description FL_ID 0 Flash Interface Description FL_SIZE 1 Flash size in bytes FL_PAGE_SIZE 2 Page size in bytes FL_NB_PLANE 3 Number of planes. FL_PLANE[0] 4 Number of bytes in the first plane. ... FL_PLANE[FL_NB_PLANE- 4 + FL_NB_PLANE - 1 Number of bytes in the last plane. FL_NB_LOCK 4 + FL_NB_PLANE Number of lock bits. A bit is associated with a lock region. A lock bit is used to prevent write or erase operations in the lock region. FL_LOCK[0] 4 + FL_NB_PLANE + 1 Number of bytes in the first lock region. ...

DS60001614B-page 232  2020 Microchip Technology Inc. FIGURE 19-6: EXAMPLE OF PARTIAL PAGE PROGRAMMING The Partial Programming mode works only with 128-bit (or higher) boundaries. It cannot be used with boundaries lower than 128 bits (8, 16 or 32-bit for example).

19.4.3.3 Erase Commands

Erase commands are allowed only on unlocked regions. The erase sequence is:

• Erase starts as soon as one of the erase commands and the FARG field are written in the Flash Command Regis- ter.
• When the programming completes, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) rises. If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the NVIC is activated. Two errors can be detected in the EEFC_FSR register after a programming sequence:
• a Command Error: a bad keyword has been written in the EEFC_FCR register.
• a Lock Error: at least one page to be erased belongs to a locked region. The erase command has been refused, no page has been erased. A command must be run previously to unlock the corresponding region.

19.4.3.4 Lock Bit Protection

Lock bits are associated with several pages in the embedded Flash memory plane. This defines lock regions in the embedded Flash memory plane. They prevent writing/erasing protected pages. The lock sequence is:

• The Set Lock command (SLB) and a page number to be protected are written in the Flash Command Register.
• When the locking completes, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) rises. If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the NVIC is activated.
• If the lock bit number is greater than the total number of lock bits, then the command has no effect. The result of the SLB command can be checked running a GLB (Get Lock Bit) command. An error can be detected in the EEFC_FSR register after a programming sequence:
• a Command Error: a bad keyword has been written in the EEFC_FCR register. It is possible to clear lock bits previously set. Then the locked region can be erased or programmed. The unlock sequence is:
• The Clear Lock command (CLB) and a page number to be unprotected are written in the Flash Command Regis- ter.
• When the unlock completes, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) rises. If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the NVIC is activated. Erase All Flash Programming of the second part of Page Y Programming of the third part of P 32-bit wide 32-bit wide 32-bit wide rds FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ... CA FE CA FE CA FE CA FE CA FE CA FE FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF CA FE CA FE CA FE CA FE CA FE CA FE DE CA DE CA DE CA DE CA DE CA DE CA FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF Step 1. Step 2. Step 3. ... ... ... ... ... ... ... ... ... ... ... rds rds rds So Page Y erased

 2020 Microchip Technology Inc. DS60001614B-page 233 SAM3X8ERT

• If the lock bit number is greater than the total number of lock bits, then the command has no effect. One error can be detected in the EEFC_FSR register after a programming sequence:
• a Command Error: a bad keyword has been written in the EEFC_FCR register. The status of lock bits can be returned by the Enhanced Embedded Flash Controller (EEFC). The Get Lock Bit status sequence is:
• The Get Lock Bit command (GLB) is written in the Flash Command Register, FARG field is meaningless.
• Lock bits can be read by the software application in the EEFC_FRR register. The first word read corresponds to the 32 first lock bits, next reads providing the next 32 lock bits as long as it is meaningful. Extra reads to the EEF- C_FRR register return 0. For example, if the third bit of the first word read in the EEFC_FRR is set, then the third lock region is locked. One error can be detected in the EEFC_FSR register after a programming sequence:
• a Command Error: a bad keyword has been written in the EEFC_FCR register. Note: Access to the Flash in read is permitted when a set, clear or get lock bit command is performed.

19.4.3.5 GPNVM Bit

GPNVM bits do not interfere with the embedded Flash memory plane. Refer to the product definition section for infor - mation on the GPNVM Bit Action. The set GPNVM bit sequence is:

• Start the Set GPNVM Bit command (SGPB) by writing the Flash Command Register with the SGPB command and the number of the GPNVM bit to be set.
• When the GPVNM bit is set, the bit FRDY in the Flash Programming Status Register (EEFC_FSR) rises. If an interrupt was enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the NVIC is activated.
• If the GPNVM bit number is greater than the total number of GPNVM bits, then the command has no effect. The result of the SGPB command can be checked by running a GGPB (Get GPNVM Bit) command. One error can be detected in the EEFC_FSR register after a programming sequence:
• A Command Error: a bad keyword has been written in the EEFC_FCR register. It is possible to clear GPNVM bits previously set. The clear GPNVM bit sequence is:
• Start the Clear GPNVM Bit command (CGPB) by writing the Flash Command Register with CGPB and the number of the GPNVM bit to be cleared.
• When the clear completes, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) rises. If an inter- rupt has been enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the NVIC is activated.
• If the GPNVM bit number is greater than the total number of GPNVM bits, then the command has no effect. One error can be detected in the EEFC_FSR register after a programming sequence:
• A Command Error: a bad keyword has been written in the EEFC_FCR register. The status of GPNVM bits can be returned by the Enhanced Embedded Flash Controller (EEFC). The sequence is:
• Start the Get GPNVM bit command by writing the Flash Command Register with GGPB. The FARG field is mean- ingless.
• GPNVM bits can be read by the software application in the EEFC_FRR register. The first word read corresponds to the 32 first GPNVM bits, following reads provide the next 32 GPNVM bits as long as it is meaningful. Extra reads to the EEFC_FRR register return 0. For example, if the third bit of the first word read in the EEFC_FRR is set, then the third GPNVM bit is active. One error can be detected in the EEFC_FSR register after a programming sequence:
• a Command Error: a bad keyword has been written in the EEFC_FCR register. Note: Access to the Flash in read is permitted when a set, clear or get GPNVM bit command is performed.

19.4.3.5.1 Calibration Bit

Calibration bits do not interfere with the embedded Flash memory plane. It is impossible to modify the calibration bits. The status of calibration bits can be returned by the Enhanced Embedded Flash Controller (EEFC). The sequence is:

DS60001614B-page 234  2020 Microchip Technology Inc.

• Issue the Get CALIB Bit command by writing the Flash Command Register with GCALB (see Table 19-2). The FARG field is meaningless.
• Calibration bits can be read by the software application in the EEFC_FRR register. The first word read corre- sponds to the 32 first calibration bits, following reads provide the next 32 calibration bits as long as it is meaning- ful. Extra reads to the EEFC_FRR register return 0. The 4/8/12 MHz Fast RC oscillator is calibrated in production. This calibration can be read through the Get CALIB Bit command. The table below shows the bit implementation for each frequency: The RC calibration for 4 MHz is set to 1,000,000.

19.4.3.5.2 Security Bit Protection

When the security is enabled, access to the Flash, either through the JTAG/SWD interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash. The security bit is GPNVM0. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated, all accesses to the Flash are permitted.

19.4.3.5.3 Unique Identifier

Each part is programmed with a 128-bit Unique Identifier. It can be used to generate keys for example. To read the Unique Identifier the sequence is:

• Send the Start Read unique Identifier command (STUI) by writing the Flash Command Register with the STUI command.
• When the Unique Identifier is ready to be read, the FRDY bit in the Flash Programming Status Register (EEF- C_FSR) falls.
• The Unique Identifier is located in the first 128 bits of the Flash memory mapping. So, at the address 0x80000- 0xFFFFF.
• To stop the Unique Identifier mode, the user needs to send the Stop Read unique Identifier command (SPUI) by writing the Flash Command Register with the SPUI command.
• When the Stop read Unique Identifier command (SPUI) has been performed, the FRDY bit in the Flash Program- ming Status Register (EEFC_FSR) rises. If an interrupt was enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the NVIC is activated. Note: During the sequence, the software can not run out of Flash (or the second plane in case of dual plane).

19.5 Enhanced Embedded Flash Controller (EEFC) User Interface

The User Interface of the Enhanced Embedded Flash Controller (EEFC) is integrated within the System Controller with base address 0x400E0A00 and 0x400E0C00. RC Calibration Frequency EEFC_FRR Bits

8 MHz output [28 - 22]

12 MHz output [38 - 32]

TABLE 19-4: REGISTER MAPPING Offset Register Name Access Reset State 0x00 EEFC Flash Mode Register EEFC_FMR Read-write 0x0 0x04 EEFC Flash Command Register EEFC_FCR Write-only — 0x08 EEFC Flash Status Register EEFC_FSR Read-only 0x00000001 0x0C EEFC Flash Result Register EEFC_FRR Read-only 0x0 0x10 Reserved — — —

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19.5.1 EEFC FLASH MODE REGISTER

Name:EEFC_FMR Address:0x400E0A00 (0), 0x400E0C00 (1) Access:Read-write Offset:0x00

• FRDY: Ready Interrupt Enable 0: Flash Ready does not generate an interrupt. 1: Flash Ready (to accept a new command) generates an interrupt.
• FWS: Flash Wait State This field defines the number of wait states for read and write operations: - Number of cycles for Read/Write operations = FWS+1
• FAM: Flash Access Mode 0: 128-bit access in read Mode only, to enhance access speed. 1: 64-bit access in read Mode only, to enhance power consumption. No Flash read should be done during change of this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — — — — FWS 7 6 5 4 3 2 1 0

DS60001614B-page 236  2020 Microchip Technology Inc.

19.5.2 EEFC FLASH COMMAND REGISTER

Name:EEFC_FCR Address:0x400E0A04 (0), 0x400E0C04 (1) Access:Write-only Offset:0x04

• FCMD: Flash Command This field defines the flash commands. Refer to “Flash Commands” on page 228.
• FARG: Flash Command Argument
• FKEY: Flash Writing Protection Key This field should be written with the value 0x5A to enable the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. 31 30 29 28 27 26 25 24 FKEY 23 22 21 20 19 18 17 16 FARG 15 14 13 12 11 10 9 8 FARG 7 6 5 4 3 2 1 0 FCMD Erase command For erase all command, this field is meaningless. Programming command FARG defines the page number to be programmed. Lock command FARG defines the page number to be locked. GPNVM command FARG defines the GPNVM number. Get commands Field is meaningless. Unique Identifier commands Field is meaningless.

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19.5.3 EEFC FLASH STATUS REGISTER

Name:EEFC_FSR Address:0x400E0A08 (0), 0x400E0C08 (1) Access:Read-only Offset:0x08

• FRDY: Flash Ready Status 0: The Enhanced Embedded Flash Controller (EEFC) is busy. 1: The Enhanced Embedded Flash Controller (EEFC) is ready to start a new command. When it is set, this flags triggers an interrupt if the FRDY flag is set in the EEFC_FMR register. This flag is automatically cleared when the Enhanced Embedded Flash Controller (EEFC) is busy.
• FCMDE: Flash Command Error Status 0: No invalid commands and no bad keywords were written in the Flash Mode Register EEFC_FMR. 1: An invalid command and/or a bad keyword was/were written in the Flash Mode Register EEFC_FMR. This flag is automatically cleared when EEFC_FSR is read or EEFC_FCR is written.
• FLOCKE: Flash Lock Error Status 0: No programming/erase of at least one locked region has happened since the last read of EEFC_FSR. 1: Programming/erase of at least one locked region has happened since the last read of EEFC_FSR. This flag is automatically cleared when EEFC_FSR is read or EEFC_FCR is written. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — — — FLOCKE FCMDE FRDY

DS60001614B-page 238  2020 Microchip Technology Inc.

19.5.4 EEFC FLASH RESULT REGISTER

Name:EEFC_FRR Address:0x400E0A0C (0), 0x400E0C0C (1) Access:Read-only Offset:0x0C

• FVALUE: Flash Result Value The result of a Flash command is returned in this register. If the size of the result is greater than 32 bits, then the next resulting value is accessible at the next register read. 31 30 29 28 27 26 25 24 FVALUE 23 22 21 20 19 18 17 16 FVALUE 15 14 13 12 11 10 9 8 FVALUE 7 6 5 4 3 2 1 0 FVALUE

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20.0 FAST FLASH PROGRAMMING INTERFACE (FFPI)

20.1 Description

The Fast Flash Programming Interface provides solutions for high-volume programming using a standard gang pro - grammer. The parallel interface is fully handshaked and the device is considered to be a standard EEPROM. Addition- ally, the parallel protocol offers an optimized access to all the embedded Flash functionalities. Although the Fast Flash Programming Mode is a dedicated mode for high volume programming, this mode is not designed for in-situ programming.

20.2 Parallel Fast Flash Programming

20.2.1 DEVICE CONFIGURATION

In Fast Flash Programming Mode, the device is in a specific test mode. Only a certain set of pins is significant. Other pins must be left unconnected. The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when TST, PA0, PA1 are set to high, PA2 and PA3 are set to low and NRST is toggled from 0 to 1. FIGURE 20-1: PARALLEL PROGRAMMING INTERFACE DATA[15:0] PGMNCMD PGMRDY PGMNOE PGMNVALID PGMM[3:0] PGMD[15:0] XIN TST NRSTB FWUP NCMD RDY NOE NVALID MODE[3:0] VDDBU 0 - 50MHz (VDDCORE) VDDBU VDDBU VDDIO GND VDDBU GNDBU GNDANA GNDPLL VDDCORE VDDPLL VDDANA VDDUTMI GNDUTMI VDDIN PA0VDDIO PA1VDDIO PA2GND PA3GND NRSTGND (togggle to VDDIO)

DS60001614B-page 240  2020 Microchip Technology Inc. The table below shows the signal assignment of the PIO lines in FFPI mode TABLE 20-1: SIGNAL DESCRIPTION LIST Signal Name Function Type Active Level Comments Power VDDIO I/O Lines Power Supply Power — Apply external 3.0V-3.6V VDDBU Backup I/O Lines Power Supply Power — Apply external 3.0V-3.6V VDDUTMI UTMI+ Interface Power Supply Power — Apply external 3.0V-3.6V VDDANA ADC Analog Power Supply Power — Apply external 3.0V-3.6V VDDIN Voltage Regulator Input Power — Apply external 3.0V-3.6V VDDCORE Core Power Supply Power — Apply external 1.8V-1.95V VDDPLL PLLs and Oscillator Power Supply Power — Apply external 1.8V-1.95V GND Ground Ground — — GNDPLL Ground Ground — — GNDBU Ground Ground — — GNDANA Ground Ground — — GNDUTMI Ground Ground — — Clocks XIN Clock Input Input — 0 to 50MHz (0-VDDCORE square wave) Test TST Test Mode Select Input High Must be connected to VDDIO NRSTB Asynchronous Microcontroller Reset Input High Must be connected to VDDIO FWUP Wake-up pin Input High Must be connected to VDDIO PIO PGMNCMD Valid command available Input Low Pulled-up input at reset PGMRDY 0: Device is busy 1: Device is ready for a new com- mand Output High Pulled-up input at reset PGMNOE Output Enable (active high) Input Low Pulled-up input at reset PGMNVALID 0: DATA[15:0] is in input mode 1: DATA[15:0] is in output mode Output Low Pulled-up input at reset PGMM[3:0] Specifies DATA type (See Table 20-3) Input — Pulled-up input at reset PGMD[15:0] Bi-directional data bus Input/Output — Pulled-up input at reset PA0 — Input — Must be connected to VDDIO at power-up PA1 — Input — Must be connected to VDDIO at power-up PA2 — Input — Must be connected to GND at power- up PA3 — Input — Must be connected to GND at power- up NRST — Input — Must be connected at start-up. And toggle at VDDIO

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20.2.2 SIGNAL NAMES

Depending on the MODE settings, DATA is latched in different internal registers. When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] signals) is stored in the command reg- ister. TABLE 20-2: FFPI PIO ASSIGNMENT FFPI Signal PIO Used PGMNCMD PA0 PGMRDY PA1 PGMNOE PA2 PGMNVALID PA3 PGMM[0] PA4 PGMM[1] PA5 PGMM[2] PA6 PGMM[3] PA7 PGMD[0] PA8 PGMD[1] PA9 PGMD[2] PA10 PGMD[3] PA11 PGMD[4] PA12 PGMD[5] PA13 PGMD[6] PA14 PGMD[7] PA15 PGMD[8] PA16 PGMD[9] PA17 PGMD[10] PA18 PGMD[11] PA19 PGMD[12] PA20 PGMD[13] PA21 PGMD[14] PA22 PGMD[15] PA23 TABLE 20-3: MODE CODING MODE[3:0] Symbol Data

0000 CMDE Command Register

0001 ADDR0 Address Register LSBs

0010 ADDR1 Address Register MSBs

0101 DATA Data Register

TABLE 20-4: COMMAND BIT CODING DATA[15:0] Symbol Command Executed 0x0011 READ Read Flash 0x0012 WP Write Page Flash 0x0022 WPL Write Page and Lock Flash 0x0032 EWP Erase Page and Write Page 0x0042 EWPL Erase Page and Write Page then Lock

DS60001614B-page 242  2020 Microchip Technology Inc. Note 1: Applies to 256 kbytes Flash version (dual EEFC)

20.2.3 ENTERING PROGRAMMING MODE

The following algorithm puts the device in Parallel Programming Mode:

• Apply GND, TST, NRTSB, FWUP , PA0, PA1, PA2, PA3, NRST and the supplies as described in Table 20-1.
• Wait for 20 ms
• Toggle NRST from 0 to 1 (GND to VDDIO).
• Apply XIN clock
• Wait for 20 ms
• Start a read or write handshaking.

20.2.4 PROGRAMMER HANDSHAKING

A handshake is defined for read and write operations. When the device is ready to start a new operation (RDY signal set), the programmer starts the handshake by clearing the NCMD signal. The handshaking is achieved once NCMD signal is high and RDY is high.

20.2.4.1 Write Handshaking

For details on the write handshaking sequence, refer to Figure 20-2 and Table 20-5. FIGURE 20-2: PARALLEL PROGRAMMING TIMING, WRITE SEQUENCE 0x0013 EA Erase All 0x0014 SLB Set Lock Bit 0x0024 CLB Clear Lock Bit 0x0015 GLB Get Lock Bit 0x0034 SGPB Set General Purpose NVM bit 0x0044 CGPB Clear General Purpose NVM bit 0x0025 GGPB Get General Purpose NVM bit 0x0054 SSE Set Security Bit 0x0035 GSE Get Security Bit 0x001F WRAM Write Memory 0x0016 SEFC Select EEFC Controller(1) 0x001E GVE Get Version TABLE 20-4: COMMAND BIT CODING (CONTINUED) DATA[15:0] Symbol Command Executed NCMD RDY NOE NVALID DATA[15:0] MODE[3:0]

 2020 Microchip Technology Inc. DS60001614B-page 243 SAM3X8ERT TABLE 20-5: WRITE HANDSHAKE Step Programmer Action Device Action Data I/O

1 Sets MODE and DATA signals Waits for NCMD low Input

2 Clears NCMD signal Latches MODE and DATA Input

3 Waits for RDY low Clears RDY signal Input

4 Releases MODE and DATA signals Executes command and polls NCMD high Input

5 Sets NCMD signal Executes command and polls NCMD high Input

6 Waits for RDY high Sets RDY Input

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20.2.4.2 Read Handshaking

For details on the read handshaking sequence, refer to Figure 20-3 and Table 20-6. FIGURE 20-3: PARALLEL PROGRAMMING TIMING, READ SEQUENCE

20.2.5 DEVICE OPERATIONS

Several commands on the Flash memory are available. These commands are summarized in Table 20-4. Each com- mand is driven by the programmer through the parallel interface running several read/write handshaking sequences. When a new command is executed, the previous one is automatically achieved. Thus, chaining a read command after a write automatically flushes the load buffer in the Flash. TABLE 20-6: READ HANDSHAKE Step Programmer Action Device Action DATA I/O

2 Clears NCMD signal Latch MODE and DATA Input

4 Sets DATA signal in tristate Waits for NOE Low Input

5 Clears NOE signal — Tristate

6 Waits for NVALID low Sets DATA bus in output mode and out-

puts the flash contents. Output 7 — Clears NVALID signal Output

8 Reads value on DATA Bus Waits for NOE high Output

9 Sets NOE signal — Output

10 Waits for NVALID high Sets DATA bus in input mode X

11 Sets DATA in output mode Sets NVALID signal Input

12 Sets NCMD signal Waits for NCMD high Input

13 Waits for RDY high Sets RDY signal Input

DATA[15:0] MODE[3:0] Adress IN Z Data OUT X IN ADDR 8 10

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20.2.5.1 Flash Read Command

This command is used to read the contents of the Flash memory. The read command can start at any valid address in the memory plane and is optimized for consecutive reads. Read handshaking can be chained; an internal address buffer is automatically increased.

20.2.5.2 Flash Write Command

This command is used to write the Flash contents. The Flash memory plane is organized into several pages. Data to be written are stored in a load buffer that corresponds to a Flash memory page. The load buffer is automatically flushed to the Flash:

• before access to any page other than the current one
• when a new command is validated (MODE = CMDE) The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. The Flash command Write Page and Lock (WPL) is equivalent to the Flash Write Command. However, the lock bit is automatically set at the end of the Flash write operation. As a lock region is composed of several pages, the programmer writes to the first pages of the lock region using Flash write commands and writes to the last page of the lock region using a Flash write and lock command. The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command. However, before pro - gramming the load buffer, the page is erased. The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL commands.

20.2.5.3 Flash Full Erase Command

This command is used to erase the Flash memory planes. TABLE 20-7: READ COMMAND Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE READ

2 Write handshaking ADDR0 Memory Address LSB

3 Write handshaking ADDR1 Memory Address

4 Read handshaking DATA *Memory Address++

5 Read handshaking DATA *Memory Address++

n Write handshaking ADDR0 Memory Address LSB n+1 Write handshaking ADDR1 Memory Address n+2 Read handshaking DATA *Memory Address++ n+3 Read handshaking DATA *Memory Address++ TABLE 20-8: WRITE COMMAND Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE WP or WPL or EWP or EWPL

4 Write handshaking DATA *Memory Address++

5 Write handshaking DATA *Memory Address++

n Write handshaking ADDR0 Memory Address LSB n+1 Write handshaking ADDR1 Memory Address n+2 Write handshaking DATA *Memory Address++ n+3 Write handshaking DATA *Memory Address++

DS60001614B-page 246  2020 Microchip Technology Inc. All lock regions must be unlocked before the Full Erase command by using the CLB command. Otherwise, the erase command is aborted and no page is erased.

20.2.5.4 Flash Lock Commands

Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command (SLB). With this command, several lock bits can be activated. A Bit Mask is provided as argument to the command. When bit 0 of the bit mask is set, then the first lock bit is activated. Likewise, the Clear Lock command (CLB) is used to clear lock bits. Lock bits can be read using Get Lock Bit command (GLB). The nth lock bit is active when the bit n of the bit mask is set..

20.2.5.5 Flash General-purpose NVM Commands

General-purpose NVM bits (GP NVM bits) can be set using the Set GPNVM command (SGPB). This command also activates GP NVM bits. A bit mask is provided as argument to the command. When bit 0 of the bit mask is set, then the first GP NVM bit is activated. Likewise, the Clear GPNVM command (CGPB) is used to clear general-purpose NVM bits. All the general-purpose NVM bits are also cleared by the EA command. The general-purpose NVM bit is deactivated when the corresponding bit in the pattern value is set to 1. General-purpose NVM bits can be read using the Get GPNVM Bit command (GGPB). The nth GP NVM bit is active when bit n of the bit mask is set.. TABLE 20-9: FULL ERASE COMMAND Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE EA

2 Write handshaking DATA 0

TABLE 20-10: SET AND CLEAR LOCK BIT COMMAND Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE SLB or CLB

2 Write handshaking DATA Bit Mask

TABLE 20-11: GET LOCK BIT COMMAND Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE GLB

2 Read handshaking DATA Lock Bit Mask Status

0 = Lock bit is cleared 1 = Lock bit is set TABLE 20-12: SET/CLEAR GP NVM COMMAND Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE SGPB or CGPB

2 Write handshaking DATA GP NVM bit pattern value

TABLE 20-13: GET GP NVM BIT COMMAND Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE GGPB

2 Read handshaking DATA GP NVM Bit Mask Status

0 = GP NVM bit is cleared 1 = GP NVM bit is set

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20.2.5.6 Flash Security Bit Command

A security bit can be set using the Set Security Bit command (SSE). Once the security bit is active, the Fast Flash programming is disabled. No other command can be run. An event on the Erase pin can erase the security bit once the contents of the Flash have been erased. The SAM3X8ERT security bit is controlled by the EEFC0. To use the Set Security Bit command, the EEFC0 must be selected using the Select EFC command. Once the security bit is set, it is not possible to access FFPI. The only way to erase the security bit is to erase the Flash. In order to erase the Flash, the user must perform the following:

• Power-off the chip
• Power-on the chip with TST = 0
• Assert Erase during a period of more than 220 ms
• Power-off the chip Then it is possible to return to FFPI mode and check that Flash is erased.

20.2.5.7 SAM3X8ERT Flash Select EEFC Command

The commands WPx, EA, xLB, xFB are executed using the current EFC controller. The default EEFC controller is EEFC0. The Select EEFC command (SEFC) allows selection of the current EEFC controller.

20.2.5.8 Memory Write Command

This command is used to perform a write access to any memory location. The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking can be chained; an inter- nal address buffer is automatically increased. TABLE 20-14: SET SECURITY BIT COMMAND Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE SSE

TABLE 20-15: SELECT EFC COMMAND Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE SEFC

2 Write handshaking DATA 0 = Select EEFC0

1 = Select EEFC1 TABLE 20-16: WRITE COMMAND Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE WRAM

n Write handshaking ADDR0 Memory Address LSB n+1 Write handshaking ADDR1 Memory Address n+2 Write handshaking DATA *Memory Address++ n+3 Write handshaking DATA *Memory Address++

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20.2.5.9 Get Version Command

The Get Version (GVE) command retrieves the version of the FFPI interface. TABLE 20-17: GET VERSION COMMAND Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE GVE

2 Write handshaking DATA Version

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21.0 SAM3X8ERT BOOT PROGRAM

21.1 Description

The SAM-BA Boot Program integrates an array of programs permitting download and/or upload into the different mem- ories of the product.

21.2 Flow Diagram

The Boot Program implements the algorithm illustrated in Figure 21-1. FIGURE 21-1: BOOT PROGRAM ALGORITHM FLOW DIAGRAM The SAM-BA Boot program seeks to detect a source clock either from the embedded main oscillator with external crystal (main oscillator enabled) or from a 12 MHz signal applied to the XIN pin (Main oscillator in Bypass mode). If a clock is found from the two possible sources above, the boot program checks to verify that the frequency is 12 MHz (taking into account the frequency range of the 32 kHz RC oscillator). If the frequency is 12 MHz, USB activation is allowed, else (no clock or frequency other than 12 MHz), the internal 12 MHz RC oscillator is used as main clock and USB clock is not allowed due to frequency drift of the 12 MHz RC oscillator.

21.3 Device Initialization

The initialization sequence is the following: 1. Stack setup 2. Set up the Embedded Flash Controller 3. External Clock detection (quartz or external clock on XIN) 4. If quartz or external clock is 12.000 MHz, allow USB activation 5. Else, does not allow USB activation and use internal RC 12 MHz 6. Main oscillator frequency detection if no external clock detected 7. Switch Master Clock on Main Oscillator 8. C variable initialization 9. PLLA setup: PLLA is initialized to generate a 48 MHz clock 10. UPLL setup in case of USB activation allowed 11. Disable of the Watchdog 12. Initialization of the UART (115200 bauds, 8, N, 1) 13. Initialization of the USB Device Port (in case of USB activation allowed) 14. Wait for one of the following events a) Check if USB device enumeration has occurred b) Check if characters have been received in the UART 15. Jump to SAM-BA Monitor (see “SAM-BA Monitor” on page 250) Device Setup Character # received from UART? Run SAM-BA Monitor USB Enumeration Successful ? Ye s Run SAM-BA Monitor Ye s No No

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21.4 SAM-BA Monitor

Once the communication interface is identified, the monitor runs in an infinite loop waiting for different commands as shown in Table 21-1.

• Mode commands: - Normal mode configures SAM-BA Monitor to send/receive data in binary format, - Terminal mode configures SAM-BA Monitor to send/receive data in ascii format.
• Write commands: Write a byte (O), a halfword (H) or a word (W) to the target. - Address: Address in hexadecimal. - Value: Byte, halfword or word to write in hexadecimal. - Output: ‘>’.
• Read commands: Read a byte (o), a halfword (h) or a word (w) from the target. - Address: Address in hexadecimal - Output: The byte, halfword or word read in hexadecimal following by ‘>’
• Send a file (S): Send a file to a specified address - Address: Address in hexadecimal - Output: ‘>’. Note: There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution.
• Receive a file (R): Receive data into a file from a specified address - Address: Address in hexadecimal - NbOfBytes: Number of bytes in hexadecimal to receive - Output: ‘>’
• Go (G): Jump to a specified address and execute the code - Address: Address to jump in hexadecimal - Output: ‘>’
• Get Version (V): Return the SAM-BA boot version - Output: ‘>’

21.4.1 UART SERIAL PORT

Communication is performed through the UART initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work. See “Hardware and Software Constraints” on page 253. TABLE 21-1: COMMANDS AVAILABLE THROUGH THE SAM-BA BOOT Command Action Argument(s) Example N set Normal mode No argument N# T set Terminal mode No argument T# O write a byte Address, Value# O200001,CA# o read a byte Address,# o200001,# H write a half word Address, Value# H200002,CAFE# h read a half word Address,# h200002,# W write a word Address, Value# W200000,CAFEDECA# w read a word Address,# w200000,# S send a file Address,# S200000,# R receive a file Address, NbOfBytes# R200000,1234# G go Address# G200200# V display version No argument V#

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21.4.2 XMODEM PROTOCOL

The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to guarantee detection of a maximum bit error. Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of the transfer looks like: <SOH><blk #><255-blk #><--128 data bytes--><checksum> in which:

• <SOH> = 01 hex
• <blk #> = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01)
• <255-blk #> = 1’s complement of the blk#.
• <checksum> = 2 bytes CRC16 Figure 21-1 shows a transmission using this protocol. FIGURE 21-1: XMODEM TRANSFER EXAMPLE

21.4.3 USB DEVICE PORT

The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 soft- ware to talk over the USB. The CDC class is implemented in all releases of Windows® beginning with Windows 98SE. The CDC document, available at www.usb.org, describes a way to implement devices such as ISDN modems and virtual COM ports. The Vendor ID (VID) is Microchip’s vendor ID 0x03EB. The product ID (PID) is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. For more details about VID/PID for End Product/Systems, refer to the Vendor ID form available from the USB Imple - menters Forum on www.usb.org. Microchip provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the application note Basic USB Application (Microchip literature num- ber 6123) for more details. Host Device SOH 01 FE Data[128] CRC CRC C ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK

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21.4.3.1 Enumeration Process

The USB protocol is a master/slave protocol. This is the host that starts the enumeration sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. The device also handles some class requests defined in the CDC class. Unhandled requests are STALLed.

21.4.3.2 Communication Endpoints

There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAM-BA Boot commands are sent by the host through endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response.

21.4.4 IN APPLICATION PROGRAMMING (IAP) FEATURE

The IAP feature is a function located in ROM that can be called by any software application. When called, this function sends the desired FLASH command to the EEFC and waits for the Flash to be ready (looping while the FRDY bit is not set in the EEFC_FSR). Since this function is executed from ROM, this allows Flash programming (such as sector write) to be done by code running in Flash. The IAP function entry point is retrieved by reading the NMI vector in ROM (0x00100008). This function takes one argument in parameter: the command to be sent to the EEFC. This function returns the value of the EEFC_FSR. IAP software code example: (unsigned int) (*IAP_Function)(unsigned long); void main (void){ unsigned long FlashSectorNum = 200; // unsigned long flash_cmd = 0; unsigned long flash_status = 0; unsigned long EFCIndex = 0; // 0:EEFC0, 1: EEFC1 /* Initialize the function pointer (retrieve function address from NMI vector) */ TABLE 21-2: HANDLED STANDARD REQUESTS Request Definition GET_DESCRIPTOR Returns the current device configuration value. SET_ADDRESS Sets the device address for all future device access. SET_CONFIGURATION Sets the device configuration. GET_CONFIGURATION Returns the current device configuration value. GET_STATUS Returns status for the specified recipient. SET_FEATURE Set or Enable a specific feature. CLEAR_FEATURE Clear or Disable a specific feature. TABLE 21-3: HANDLED CLASS REQUESTS Request Definition SET_LINE_CODING Configures DTE rate, stop bits, parity and number of character bits. GET_LINE_CODING Requests current DTE rate, stop bits, parity and number of character bits. SET_CONTROL_LINE_STATE RS-232 signal used to tell the DCE device the DTE device is now present.

 2020 Microchip Technology Inc. DS60001614B-page 253 SAM3X8ERT IAP_Function = ((unsigned long) (*)(unsigned long)) 0x00800008; /* Send your data to the sector here */ /* build the command to send to EEFC */ flash_cmd = (0x5A << 24) | (FlashSectorNum << 8) | AT91C_MC_FCMD_EWP; /* Call the IAP function with appropriate command */ flash_status = IAP_Function (EFCIndex, flash_cmd);

21.5 Hardware and Software Constraints

• SAM-BA Boot uses the first 2048 bytes of the SRAM for variables and stacks. The remaining available size can be used for user's code.
• UART requirements: - 12.000 MHz quartz or 12.000 MHz external clock on XIN, or - No quartz or external clock on XIN, or - Below 5.0 MHz quartz or below 5.0 MHz external clock on XIN
• USB requirements: - 12.000 MHz quartz or 12.000 MHz external clock on XIN. 12 MHz must be ±500 ppm and 1.8V Square Wave Signal. TABLE 21-1: PINS DRIVEN DURING BOOT PROGRAM EXECUTION Peripheral Pin PIO Line UART URXD PA8 UART UTXD PA9

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22.0 BUS MATRIX (MATRIX)

22.1 Description

Bus Matrix implements a multi-layer AHB, based on AHB-Lite protocol, that enables parallel access paths between mul- tiple AHB masters and slaves in a system, which increases the overall bandwidth. Bus Matrix interconnects 6 AHB Mas- ters to 9 AHB Slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency). The Bus Matrix user interface is compliant with the ARM Advance Peripheral Bus (APB) and provides a Chip Configu- ration User Interface with Registers that allow the Bus Matrix to support application specific features.

22.2 Embedded Characteristics

22.2.1 MATRIX MASTERS

The Bus Matrix of the SAM3X8ERT product manages 6 masters, which means that each master can perform an access concurrently with others, to an available slave. Each master has its own decoder, which is defined specifically for each master. In order to simplify the addressing, all the masters have the same decoding.

22.2.2 MATRIX SLAVES

The Bus Matrix of the SAM3X8ERT product manages 9 slaves. Each slave has its own arbiter, allowing a different arbi- tration per slave.

22.2.3 MASTER TO SLAVE ACCESS

All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the USB High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown as “-” in the following table. TABLE 22-1: LIST OF BUS MATRIX MASTERS Master 0 Cortex-M3 Instruction/Data Master 1 Cortex-M3 System Master 2 Peripheral DMA Controller (PDC) Master 3 USB OTG High Speed DMA Master 4 DMA Controller Master 5 Ethernet MAC (AT91SAM3X) TABLE 22-2: LIST OF BUS MATRIX SLAVES Slave 0 Internal SRAM0 Slave 1 Internal SRAM1 Slave 2 Internal ROM Slave 3 Internal Flash Slave 4 USB High Speed Dual Port RAM (DPR) Slave 5 NAND Flash Controller RAM Slave 6 External Bus Interface Slave 7 High Speed Peripheral Bridge Slave 8 Low Speed Peripheral Bridge

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22.3 Memory Mapping

Bus Matrix provides one decoder for every AHB Master Interface. The decoder offers each AHB Master several memory mappings. In fact, depending on the product, each memory area may be assigned to several slaves. Booting at the same address while using different AHB slaves (i.e. internal ROM or internal Flash) becomes possible. The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that allows to perform remap action for every master independently.

22.4 Special Bus Granting Techniques

The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters. This mechanism allows to reduce latency at first accesses of a burst or single transfer. The bus granting mech- anism allows to set a default master for every slave. At the end of the current access, if no other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters: no default master, last access master and fixed default master.

22.4.1 NO DEFAULT MASTER

At the end of the current access, if no other request is pending, the slave is disconnected from all masters. No Default Master suits low power mode.

22.4.2 LAST ACCESS MASTER

At the end of the current access, if no other request is pending, the slave remains connected to the last master that performed an access request.

22.4.3 FIXED DEFAULT MASTER

At the end of the current access, if no other request is pending, the slave connects to its fixed default master. Unlike last access master, the fixed master doesn’t change unless the user modifies it by a software action (field FIXED_DEFMSTR of the related MATRIX_SCFG). To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration Registers, one for each slave, that allow to set a default master for each slave. The Slave Configuration Register con- tains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field allows to choose the default master type (no default, last access master, fixed default master) whereas the 4-bit FIXED_DEFMSTR field allows to choose a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Refer to the Bus Matrix user interface description. TABLE 22-3: SAM3X8ERT MASTER TO SLAVE ACCESS Masters 0 1 2 3 4 5 Slaves Cortex-M3 I/D Bus Cortex-M3 S Bus PDC USB High Speed DMA DMA Controll er EMAC DMA

0 Internal SRAM0 — X X X X X

1 Internal SRAM1 — X X X X X

2 Internal ROM X — X X X X

3 Internal Flash X — — — — —

4 USB High Speed Dual Port RAM — X — — X -

5 Nand Flash Controller RAM — X X X X X

6 External Bus Interface — X X X X X

7 High Speed Peripheral Bridge — X X — X —

8 Low Speed Peripheral Bridge — X — — X —

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22.5 Arbitration

The Bus Matrix provides an arbitration mechanism that allows to reduce latency when conflict cases occur, basically when two or more masters try to access the same slave at the same time. One arbiter per AHB slave is provided, allow- ing to arbitrate each slave differently. The Bus Matrix provides the user the possibility to choose between 2 arbitration types for each slave: 1. Round-Robin Arbitration (the default) 2. Fixed Priority Arbitration This choice is given through the ARBT field of the Slave Configuration Registers (MATRIX_SCFG). Each algorithm may be complemented by selecting a default master configuration for each slave. When re-arbitration has to be done, it is realized only under specific conditions as detailed in the following paragraph.

22.5.1 ARBITRATION RULES

Each arbiter has the ability to arbitrate between two or more different master’s requests. In order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitration may only take place during the following cycles: 1. Idle Cycles: when a slave is not connected to any master or is connected to a master which is not currently accessing it. 2. Single Cycles: when a slave is currently doing a single access. 3. End of Burst Cycles: when the current cycle is the last cycle of a burst transfer. For defined length burst, predicted end of burst matches the size of the transfer but is managed differently for undefined length burst (See “Unde- fined Length Burst Arbitration” on page 256“). 4. Slot Cycle Limit: when the slot cycle counter has reached the limit value indicating that the current master access is too long and must be broken (See “Slot Cycle Limit Arbitration” on page 256).

22.5.1.1 Undefined Length Burst Arbitration

In order to avoid too long slave handling during undefined length bursts (INCR), the Bus Matrix provides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end of burst is used as for defined length burst transfer, which is selected between the following: 1. Infinite: no predicted end of burst is generated and therefore INCR burst transfer will never be broken. 2. Four beat bursts: predicted end of burst is generated at the end of each four beat boundary inside INCR transfer. 3. Eight beat bursts: predicted end of burst is generated at the end of each eight beat boundary inside INCR trans- fer. 4. Sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat boundary inside INCR transfer. This selection can be done through the ULBT field of the Master Configuration Registers (MATRIX_MCFG).

22.5.1.2 Slot Cycle Limit Arbitration

The Bus Matrix contains specific logic to break too long accesses such as very long bursts on a very slow slave (e.g. an external low speed memory). At the beginning of the burst access, a counter is loaded with the value previously writ- ten in the SLOT_CYCLE field of the related Slave Configuration Register (MATRIX_SCFG) and decreased at each clock cycle. When the counter reaches zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half word or word transfer.

22.5.2 ROUND-ROBIN ARBITRATION

This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave in a round-robin manner. If two or more master’s requests arise at the same time, the master with the lowest number is first serviced then the others are serviced in a round-robin manner. There are three round-robin algorithm implemented:

• Round-Robin arbitration without default master
• Round-Robin arbitration with last access master
• Round-Robin arbitration with fixed default master

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22.5.2.1 Round-Robin arbitration without default master

This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch requests from different mas- ters to the same slave in a pure round-robin manner. At the end of the current access, if no other request is pending, the slave is disconnected from all masters. This configuration incurs one latency cycle for the first access of a burst. Arbitration without default master can be used for masters that perform significant bursts.

22.5.2.2 Round-Robin arbitration with last access master

This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. In fact, at the end of the current transfer, if no other master request is pending, the slave remains connected to the last master that performs the access. Other non privileged masters will still get one latency cycle if they want to access the same slave. This technique can be used for masters that mainly perform single accesses.

22.5.2.3 Round-Robin arbitration with fixed default master

This is another biased round-robin algorithm, it allows the Bus Matrix arbiters to remove the one latency cycle for the fixed default master per slave. At the end of the current access, the slave remains connected to its fixed default master. Every request attempted by this fixed default master will not cause any latency whereas other non privileged masters will still get one latency cycle. This technique can be used for masters that mainly perform single accesses.

22.5.3 FIXED PRIORITY ARBITRATION

This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user. If two or more master’s requests are active at the same time, the master with the highest priority number is serviced first. If two or more master’s requests with the same priority are active at the same time, the master with the highest number is serviced first. For each slave, the priority of each master may be defined through the Priority Registers for Slaves (MATRIX_PRAS and MATRIX_PRBS).

22.6 System I/O Configuration

The System I/O Configuration register (CCFG_SYSIO) allows to configure I/O lines in System I/O mode (such as ERASE) or as general purpose I/O lines. Enabling or disabling the corresponding I/O lines in peripheral mode, or in PIO mode (PIO_PER or PIO_PDR registers) in the PIO controller, has no effect. However, the direction (input or output), pull-up and other mode control, is still managed by the PIO controller.

22.7 Write Protect Registers

To prevent any single software error that may corrupt MATRIX behavior, the entire MATRIX address space from address offset 0x000 to 0x1FC can be write-protected by setting the WPEN bit in the MATRIX Write Protect Mode Register (MATRIX_WPMR). If a write access to anywhere in the MATRIX address space from address offset 0x000 to 0x1FC is detected, then the WPVS flag in the MATRIX Write Protect Status Register (MATRIX_WPSR) is set and the WPVSRC field indicates in which register the write access has been attempted. The WPVS flag is reset by writing the MATRIX Write Protect Mode Register (MATRIX_WPMR) with the appropriate access key, WPKEY . The protected registers are:

• “Bus Matrix Master Configuration Registers” on page 260
• “Bus Matrix Slave Configuration Registers” on page 261
• “Bus Matrix Priority Registers For Slaves” on page 263
• “Bus Matrix Master Remap Control Register” on page 264
• “System I/O Configuration Register” on page 265

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22.8 Bus Matrix (MATRIX) User Interface

TABLE 22-1: REGISTER MAPPING Offset Register Name Access Reset 0x0000 Master Configuration Register 0 MATRIX_MCFG0 Read-write 0x00000000 0x0004 Master Configuration Register 1 MATRIX_MCFG1 Read-write 0x00000000 0x0008 Master Configuration Register 2 MATRIX_MCFG2 Read-write 0x00000000 0x000C Master Configuration Register 3 MATRIX_MCFG3 Read-write 0x00000000 0x0010 Master Configuration Register 4 MATRIX_MCFG4 Read-write 0x00000000 0x0014 Master Configuration Register 5 MATRIX_MCFG5 Read-write 0x00000000 0x0018 - 0x003C Reserved — — — 0x0040 Slave Configuration Register 0 MATRIX_SCFG0 Read-write 0x00010010 0x0044 Slave Configuration Register 1 MATRIX_SCFG1 Read-write 0x00050010 0x0048 Slave Configuration Register 2 MATRIX_SCFG2 Read-write 0x00000010 0x004C Slave Configuration Register 3 MATRIX_SCFG3 Read-write 0x00000010 0x0050 Slave Configuration Register 4 MATRIX_SCFG4 Read-write 0x00000010 0x0054 Slave Configuration Register 5 MATRIX_SCFG5 Read-write 0x00000010 0x0058 Slave Configuration Register 6 MATRIX_SCFG6 Read-write 0x00000010 0x005C Slave Configuration Register 7 MATRIX_SCFG7 Read-write 0x00000010 0x0060 Slave Configuration Register 8 MATRIX_SCFG8 Read-write 0x00000010 0x0064 - 0x007C Reserved — — — 0x0080 Priority Register A for Slave 0 MATRIX_PRAS0 Read-write 0x00000000 0x0084 Reserved — — — 0x0088 Priority Register A for Slave 1 MATRIX_PRAS1 Read-write 0x00000000 0x008C Reserved — — — 0x0090 Priority Register A for Slave 2 MATRIX_PRAS2 Read-write 0x00000000 0x0094 Reserved — — — 0x0098 Priority Register A for Slave 3 MATRIX_PRAS3 Read-write 0x00000000 0x009C Reserved — — — 0x00A0 Priority Register A for Slave 4 MATRIX_PRAS4 Read-write 0x00000000 0x00A4 Reserved — — — 0x00A8 Priority Register A for Slave 5 MATRIX_PRAS5 Read-write 0x00000000 0x00AC Reserved — — — 0x00B0 Priority Register A for Slave 6 MATRIX_PRAS6 Read-write 0x00000000 0x00B4 Reserved — — — 0x00B8 Priority Register A for Slave 7 MATRIX_PRAS7 Read-write 0x00000000 0x00BC Reserved — — — 0x00C0 Priority Register A for Slave 8 MATRIX_PRAS8 Read-write 0x00000000 0x00C4- 0x00FC Reserved — — — 0x0100 Master Remap Control Register MATRIX_MRCR Read-write 0x00000000 0x0104 - 0x0110 Reserved — — — 0x0114 System I/O Configuration register CCFG_SYSIO Read/Write 0x00000000

 2020 Microchip Technology Inc. DS60001614B-page 259 SAM3X8ERT 0x0118 - 0x01E0 Reserved — — — 0x1E4 Write Protect Mode Register MATRIX_WPMR Read-write 0x0 0x1E8 Write Protect Status Register MATRIX_WPSR Read-only 0x0 0x01EC- 0x01FC Reserved — — — TABLE 22-1: REGISTER MAPPING (CONTINUED) Offset Register Name Access Reset

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22.8.1 BUS MATRIX MASTER CONFIGURATION REGISTERS

Name: MATRIX_MCFG0..MATRIX_MCFG5 Address: 0x400E0400 Access: Read-write This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register” on page 266.

• ULBT: Undefined Length Burst Type 0: Infinite Length Burst No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken. 1: Single Access The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst. 2: Four Beat Burst The undefined length burst is split into 4 beats burst allowing rearbitration at each 4 beats burst end. 3: Eight Beat Burst The undefined length burst is split into 8 beats burst allowing rearbitration at each 8 beats burst end. 4: Sixteen Beat Burst The undefined length burst is split into 16 beats burst allowing rearbitration at each 16 beats burst end. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

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22.8.2 BUS MATRIX SLAVE CONFIGURATION REGISTERS

Name: MATRIX_SCFG0..MATRIX_SCFG8 Address: 0x400E0440 Access: Read-write This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register” on page 266.

• SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst When the SLOT_CYCLE limit is reach for a burst it may be broken by another master trying to access this slave. This limit has been placed to avoid locking very slow slave by when very long burst are used. This limit should not be very small though. Unreasonable small value will break every burst and Bus Matrix will spend its time to arbitrate without performing any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE.
• DEFMSTR_TYPE: Default Master Type 0: No Default Master At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters. This results in having a one cycle latency for the first access of a burst transfer or for a single access. 1: Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-tries access on the slave again. 2: Fixed Default Master At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master which number has been written in the FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-tries access on the slave again.
• FIXED_DEFMSTR: Fixed Default Master This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.
• ARBT: Arbitration Type 0: Round-Robin Arbitration 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — FIXED_DEFMSTR DEFMSTR_TYPE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLOT_CYCLE

DS60001614B-page 262  2020 Microchip Technology Inc. 1: Fixed Priority Arbitration 2: Reserved 3: Reserved

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22.8.3 BUS MATRIX PRIORITY REGISTERS FOR SLAVES

Name:MATRIX_PRAS0..MATRIX_PRAS8 Address:0x400E0480 [0], 0x400E0488 [1], 0x400E0490 [2], 0x400E0498 [3], 0x400E04A0 [4], 0x400E04A8 [5], 0x400E04B0 [6], 0x400E04B8 [7], 0x400E04C0 [8] Access:Read-write This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register” on page 266.

• MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave.The higher the number, the higher the priority. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — M5PR — — M4PR 15 14 13 12 11 10 9 8 — — M3PR — — M2PR 7 6 5 4 3 2 1 0 — — M1PR — — M0PR

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22.8.4 BUS MATRIX MASTER REMAP CONTROL REGISTER

Name:MATRIX_MRCR Address:0x400E0500 Access:Read-write Reset:0x0000_0000 This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register” on page 266.

• RCBx: Remap Command Bit for AHB Master x 0: Disable remapped address decoding for the selected Master 1: Enable remapped address decoding for the selected Master 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — RCB5 RCB4 RCB4 RCB3 RCB2 RCB1 RCB0

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22.8.5 SYSTEM I/O CONFIGURATION REGISTER

Name:CCFG_SYSIO Address:0x400E0514 Access: Read-write Reset:0x0000_1000

• SYSIO12: PC0 or ERASE Assignment 1: ERASE function selected (Default at reset). 0: PC0 function selected. When ERASE function is selected, pull down of PC0 is enabled, and pull up of PC0 is disabled. When PC0 function is selected, pull down of PC0 is disabled and pull up of PC0 is configurable through PIO block. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

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22.8.6 WRITE PROTECT MODE REGISTER

Name:MATRIX_WPMR Address:0x400E05E4 Access:Read-write For more details on MATRIX_WPMR, refer to “Write Protect Registers” on page 257.

• WPEN: Write Protect ENable 0: Disables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII). Protects the entire MATRIX address space from address offset 0x000 to 0x1FC.
• WPKEY: Write Protect KEY (Write-only) Should be written at value 0x4D4154 (“MAT” in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 7 6 5 4 3 2 1 0

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22.8.7 WRITE PROTECT STATUS REGISTER

Name:MATRIX_WPSR Address:0x400E05E8 Access:Read-only For more details on MATRIX_WPSR, refer to “Write Protect Registers” on page 257.

• WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last write of MATRIX_WPMR. 1: At least one Write Protect Violation has occurred since the last write of MATRIX_WPMR.
• WPVSRC: Write Protect Violation Source Should be written at value 0x4D4154 (“MAT” in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. The protected registers are:
• “Bus Matrix Master Configuration Registers” on page 260
• “Bus Matrix Slave Configuration Registers” on page 261
• “Bus Matrix Priority Registers For Slaves” on page 263
• “Bus Matrix Master Remap Control Register” on page 264
• “System I/O Configuration Register” on page 265 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WPVSRC 15 14 13 12 11 10 9 8 WPVSRC 7 6 5 4 3 2 1 0

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23.0 AHB DMA CONTROLLER (DMAC)

23.1 Description

The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a source peripheral to a destination peripheral over one or more AMBA buses. One channel is required for each source/destination pair. In the most basic configuration, the DMAC has one master interface and one channel. The master interface reads the data from a source and writes it to a destination. Two AMBA transfers are required for each DMAC data transfer. This is also known as a dual-access transfer. The DMAC is programmed via the APB interface. The DMAC embeds 6 channels:

23.2 Embedded Characteristics

• Programmable Arbitration Policy, Modified Round Robin and Fixed Priority are Available
• Acting as one Matrix Master
• Embeds six channels
• Linked List support with Status Write Back operation at End of Transfer
• Word, HalfWord, Byte transfer support.
• Handles high speed transfer of SPI0-1, SSC and HSMCI (peripheral to memory, memory to peripheral)
• Memory to memory transfer The DMA controller can handle the transfer between peripherals and memory and so receives the triggers from the peripherals below. The hardware interface numbers are also given in Table 23-2. DMAC Channel Number FIFO Size 0 8 1 8 2 8 3 32 4 8 5 32 TABLE 23-1: DMA CHANNELS DMA Channel Size 144-pin SAM3X8ERT 8 bytes FIFO for Channel Buffering 4 (Channels 0, 1, 2 and 4) 32 bytes FIFO for Channel Buffering 2 (Channels 3 and 5) TABLE 23-2: DMA CONTROLLER Instance Name Channel T/R DMA Channel HW Interface Number HSMCI Transmit/Receive 0 SPI0 Transmit 1 SPI0 Receive 2 SSC Transmit 3 SSC Receive 4 SPI1 Transmit 5 SPI1 Receive 6

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23.3 Block Diagram

FIGURE 23-1: DMA CONTROLLER (DMAC) BLOCK DIAGRAM TWI0 Transmit 7 TWI0 Receive 8 - - - - - - USART0 Transmit 11 USART0 Receive 12 USART1 Transmit 13 USART1 Receive 14 PWM Transmit 15 TABLE 23-2: DMA CONTROLLER Instance Name Channel T/R DMA Channel HW Interface Number DMA Destination DMA Channel 0 DMA Destination Control State Machine Destination Pointer Management DMA Source Control State Machine Source Pointer Management DMA FIFO Controller DMA FIFO Up to 64 bytes DMA Channel 0 Read data path from source DMA Channel 0 Write data path to destination DMA Channel 1 DMA Channel 2 DMA Channel n External Triggers Soft Triggers DMA REQ/ACK Interface Trigger Manager DMA Interrupt Controller Status Registers Configuration Registers Atmel APB rev2 Interface DMA AHB Lite Master Interface 0 DMA Global Control and Data Mux DMA Global Request Arbiter DMA Source Requests Pool DMA Read Datapath Bundles DMA Atmel APB Interface DMA Interrupt DMA Hardware Handshaking Interface AMBA AHB Layer 0

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23.4 Functional Description

23.4.1 BASIC DEFINITIONS

Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form a channel. Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previously read from the source peripheral). Memory: Source or destination that is always “ready” for a DMAC transfer and does not require a handshaking interface to interact with the DMAC. Programmable Arbitration Policy: Modified Round Robin and Fixed Priority are available by means of the ARB_CFG bit in the Global Configuration Register (DMAC_GCFG). The fixed priority is linked to the channel number. The highest DMAC channel number has the highest priority. Channel: Read/write datapath between a source peripheral on one configured AMBA layer and a destination peripheral on the same or different AMBA layer that occurs through the channel FIFO. If the source peripheral is not memory, then a source handshaking interface is assigned to the channel. If the destination peripheral is not memory, then a destination handshaking interface is assigned to the channel. Source and destination handshaking interfaces can be assigned dynamically by programming the channel registers. Master interface: DMAC is a master on the AHB bus reading data from the source and writing it to the destination over the AHB bus. Slave interface: The APB interface over which the DMAC is programmed. The slave interface in practice could be on the same layer as any of the master interfaces or on a separate layer. Handshaking interface: A set of signal registers that conform to a protocol and handshake between the DMAC and source or destination peripheral to control the transfer of a single or chunk transfer between them. This interface is used to request, acknowledge, and control a DMAC transaction. A channel can receive a request through one of two types of handshaking interface: hardware or software. Hardware handshaking interface: Uses hardware signals to control the transfer of a single or chunk transfer between the DMAC and the source or destination peripheral. Software handshaking interface: Uses software registers to control the transfer of a single or chunk transfer between the DMAC and the source or destination peripheral. No special DMAC handshaking signals are needed on the I/O of the peripheral. This mode is useful for interfacing an existing peripheral to the DMAC without modifying it. Flow controller: The device (either the DMAC or source/destination peripheral) that determines the length of and ter- minates a DMAC buffer transfer. If the length of a buffer is known before enabling the channel, then the DMAC should be programmed as the flow controller. If the length of a buffer is not known prior to enabling the channel, the source or destination peripheral needs to terminate a buffer transfer. In this mode, the peripheral is the flow controller. Transfer hierarchy: Figure 23-2 illustrates the hierarchy between DMAC transfers, buffer transfers, chunk or single, and AMBA transfers (single or burst) for non-memory peripherals. Figure 23-3 shows the transfer hierarchy for memory.

DS60001614B-page 272  2020 Microchip Technology Inc. the next linked list item (LLI) exists. The LLI is a set of registers that describe the next buffer (buffer descrip- tor) and a descriptor pointer register. The DMAC fetches the LLI at the beginning of every buffer when buffer chaining is enabled. - Contiguous buffers – Where the address of the next buffer is selected to be a continuation from the end of the previous buffer. Channel locking: Software can program a channel to keep the AHB master interface by locking the arbitration for the master bus interface for the duration of a DMAC transfer, buffer, or chunk. Bus locking: Software can program a channel to maintain control of the AMBA bus by asserting hmastlock for the dura- tion of a DMAC transfer, buffer, or transaction (single or chunk). Channel locking is asserted for the duration of bus lock- ing at a minimum.

23.4.2 MEMORY PERIPHERALS

Figure 23-3 shows the DMAC transfer hierarchy of the DMAC for a memory peripheral. There is no handshaking inter- face with the DMAC, and therefore the memory peripheral can never be a flow controller. Once the channel is enabled, the transfer proceeds immediately without waiting for a transaction request. The alternative to not having a transaction- level handshaking interface is to allow the DMAC to attempt AMBA transfers to the peripheral once the channel is enabled. If the peripheral slave cannot accept these AMBA transfers, it inserts wait states onto the bus until it is ready; it is not recommended that more than 16 wait states be inserted onto the bus. By using the handshaking interface, the peripheral can signal to the DMAC that it is ready to transmit/receive data, and then the DMAC can access the peripheral without the peripheral inserting wait states onto the bus.

23.4.3 HANDSHAKING INTERFACE

Handshaking interfaces are used at the transaction level to control the flow of single or chunk transfers. The operation of the handshaking interface is different and depends on whether the peripheral or the DMAC is the flow controller. The peripheral uses the handshaking interface to indicate to the DMAC that it is ready to transfer/accept data over the AMBA bus. A non-memory peripheral can request a DMAC transfer through the DMAC using one of two handshaking interfaces:

• Hardware handshaking
• Software handshaking Software selects between the hardware or software handshaking interface on a per-channel basis. Software handshak- ing is accomplished through memory-mapped registers, while hardware handshaking is accomplished using a dedi - cated handshaking interface.

23.4.3.1 Software Handshaking

When the slave peripheral requires the DMAC to perform a DMAC transaction, it communicates this request by sending an interrupt to the CPU or interrupt controller. The interrupt service routine then uses the software registers to initiate and control a DMAC transaction. These software registers are used to implement the software handshaking interface. The SRC_H2SEL/DST_H2SEL bit in the DMAC_CFGx channel configuration register must be set to zero to enable soft- ware handshaking. When the peripheral is not the flow controller, then the last transaction register DMAC_LAST is not used, and the values in these registers are ignored. Chunk Transactions Writing a 1 to the DMAC_CREQ[2x] register starts a source chunk transaction request, where x is the channel number. Writing a 1 to the DMAC_CREQ[2x+1] register starts a destination chunk transfer request, where x is the channel num- ber. Upon completion of the chunk transaction, the hardware clears the DMAC_CREQ[2x] or DMAC_CREQ[2x+1]. Single Transactions Writing a 1 to the DMAC_SREQ[2x] register starts a source single transaction request, where x is the channel number. Writing a 1 to the DMAC_SREQ[2x+1] register starts a destination single transfer request, where x is the channel num- ber. Upon completion of the chunk transaction, the hardware clears the DMAC_SREQ[x] or DMAC_SREQ[2x+1].

 2020 Microchip Technology Inc. DS60001614B-page 273 SAM3X8ERT The software can poll the relevant channel bit in the DMAC_CREQ[2x]/DMAC_CREQ[2x+1] and DMAC_S - REQ[x]/DMAC_SREQ[2x+1] registers. When both are 0, then either the requested chunk or single transaction has com- pleted.

23.4.4 DMAC TRANSFER TYPES

A DMAC transfer may consist of single or multi-buffer transfers. On successive buffers of a multi-buffer transfer, the DMAC_SADDRx/DMAC_DADDRx registers in the DMAC are reprogrammed using either of the following methods:

• Buffer chaining using linked lists
• Contiguous address between buffers On successive buffers of a multi-buffer transfer, the DMAC_CTRLAx and DMAC_CTRLBx registers in the DMAC are re-programmed using either of the following methods:
• Buffer chaining using linked lists When buffer chaining using linked lists is the multi-buffer method of choice, and on successive buffers, the DMAC_D - SCRx register in the DMAC is re-programmed using the following method:
• Buffer chaining using linked lists A buffer descriptor (LLI) consists of following registers, DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_C- TRLAx, DMAC_CTRLBx.These registers, along with the DMAC_CFGx register, are used by the DMAC to set up and describe the buffer transfer.

23.4.4.1 Multi-buffer Transfers

Buffer Chaining Using Linked Lists In this case, the DMAC re-programs the channel registers prior to the start of each buffer by fetching the buffer descriptor for that buffer from system memory. This is known as an LLI update. DMAC buffer chaining is supported by using a Descriptor Pointer register (DMAC_DSCRx) that stores the address in memory of the next buffer descriptor. Each buffer descriptor contains the corresponding buffer descriptor (DMAC_SAD- DRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx DMAC_CTRLBx). To set up buffer chaining, a sequence of linked lists must be programmed in memory. The DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx and DMAC_CTRLBx registers are fetched from system memory on an LLI update. The updated content of the DMAC_CTRLAx register is written back to memory on buffer completion. Figure 23-4 shows how to use chained linked lists in memory to define multi-buffer transfers using buffer chaining. The Linked List multi-buffer transfer is initiated by programming DMAC_DSCRx with DSCRx(0) (LLI(0) base address) different from zero. Other fields and registers are ignored and overwritten when the descriptor is retrieved from memory. The last transfer descriptor must be written to memory with its next descriptor address set to 0.

DS60001614B-page 274  2020 Microchip Technology Inc. FIGURE 23-4: MULTI BUFFER TRANSFER USING LINKED LIST

23.4.4.2 Programming DMAC for Multiple Buffer Transfers

Note 1: USR means that the register field is manually programmed by the user. 2: CONT means that address are contiguous. 3: Channel stalled is true if the relevant BTC interrupt is not masked. 4: LLI means that the register field is updated with the content of the linked list item. Contiguous Address Between Buffers In this case, the address between successive buffers is selected to be a continuation from the end of the previous buffer. Enabling the source or destination address to be contiguous between buffers is a function of DMAC_CTRLAx.SRC_D- SCR and DMAC_CTRLAx.DST_DSCR registers. Suspension of Transfers Between Buffers At the end of every buffer transfer, an end of buffer interrupt is asserted if:

• the channel buffer interrupt is unmasked, DMAC_EBCIMR.BTCx = ‘1’, where x is the channel number. Note: The Buffer Transfer Completed Interrupt is generated at the completion of the buffer transfer to the destina- tion. At the end of a chain of multiple buffers, an end of linked list interrupt is asserted if:
• the channel end of the Chained Buffer Transfer Completed Interrupt is unmasked, DMAC_EBCIMR.CBTCx = ‘1’, when n is the channel number. TABLE 23-3: MULTIPLE BUFFERS TRANSFER MANAGEMENT Transfer Type SRC_DSC R DST_DSC R BTSIZ E DSC R SADD R DADD R Other Fields 1) Single Buffer or Last buffer of a multiple buffer transfer — — USR 0 USR USR USR 2) Multi Buffer transfer with contiguous DADDR 0 1 LLI USR LLI CONT LLI 3) Multi Buffer transfer with contiguous SADDR 1 0 LLI USR CONT LLI LLI 4) Multi Buffer transfer with LLI support 0 0 LLI USR LLI LLI LLI System Memory SADDRx= DSCRx(0) + 0x0 DADDRx= DSCRx(0) + 0x4 CTRLAx= DSCRx(0) + 0x8 CTRLBx= DSCRx(0) + 0xC DSCRx(1)= DSCRx(0) + 0x10 SADDRx= DSCRx(1) + 0x0 DADDRx= DSCRx(1) + 0x4 CTRLBx= DSCRx(1) + 0x8 CTRLBx= DSCRx(1) + 0xC DSCRx(2)= DSCRx(1) + 0x10 DSCRx(0) DSCRx(2) (points to 0 if LLI(1) is the last transfer descriptor DSCRx(1) LLI(0) LLI(1)

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23.4.4.3 Ending Multi-buffer Transfers

All multi-buffer transfers must end as shown in Row 1 of Table 23-3. At the end of every buffer transfer, the DMAC sam- ples the row number, and if the DMAC is in Row 1 state, then the previous buffer transferred was the last buffer and the DMAC transfer is terminated. For rows 2, 3, 4, 5, and 6 (DMAC_CRTLBx.AUTO cleared), the user must set up the last buffer descriptor in memory so that LLI.DMAC_CTRLBx.SRC_DSCR is set to 0.

23.4.5 PROGRAMMING A CHANNEL

Four registers, the DMAC_DSCRx, the DMAC_CTRLAx, the DMAC_CTRLBx and DMAC_CFGx, need to be pro - grammed to set up whether single or multi-buffer transfers take place, and which type of multi-buffer transfer is used. The different transfer types are shown in Table 23-3. The “BTSIZE, SADDR and DADDR” columns indicate where the values of DMAC_SARx, DMAC_DARx, DMAC_CTLx, and DMAC_LLPx are obtained for the next buffer transfer when multi-buffer DMAC transfers are enabled.

23.4.5.1 Programming Examples

Single-buffer Transfer (Row 1) 1. Read the Channel Handler Status Register DMAC_CHSR.ENAx Field to choose a free (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status reg- ister, DMAC_EBCISR. 3. Program the following channel registers: - Write the starting source address in the DMAC_SADDRx register for channel x. - Write the starting destination address in the DMAC_DADDRx register for channel x. - Write the next descriptor address in the DMA_DSCRx register for channel x with 0x0.. - Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 1 as shown in Table 23-3. - Write the control information for the DMAC transfer in the DMAC_CTRLAx and DMAC_CTRLBx registers for channel x. For example, in the register, you can program the following:

• Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register.
• Set up the transfer characteristics, such as:
• Transfer width for the source in the SRC_WIDTH field.
• Transfer width for the destination in the DST_WIDTH field.
• Incrementing/decrementing or fixed address for source in SRC_INC field.
• Incrementing/decrementing or fixed address for destination in DST_INC field. - Write the channel configuration information into the DMAC_CFGx register for channel x.
• Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests. Writing a ‘0’ activates the software handshaking interface to handle source/destination requests.
• If the hardware handshaking interface is activated for the source or destination peripheral, assign a handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DST_PER bits, respectively. 4. After the DMAC selected channel has been programmed, enable the channel by writing a ‘1’ to the DMAC_CHER.ENAx bit, where x is the channel number. Make sure that bit 0 of DMAC_EN.ENABLE register is enabled. 5. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming non-memory peripherals). The DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer. 6. Once the transfer completes, the hardware sets the interrupts and disables the channel. At this time, you can either respond to the Buffer Transfer Completed Interrupt or Chained Buffer Transfer Completed Interrupt, or poll for the Channel Handler Status Register (DMAC_CHSR.ENAx) bit until it is cleared by hardware, to detect when the transfer is complete. Multi-buffer Transfer with Linked List for Source and Linked List for Destination (Row 4) 1. Read the Channel Handler Status register to choose a free (disabled) channel.

DS60001614B-page 276  2020 Microchip Technology Inc. 2. Set up the chain of Linked List Items (otherwise known as buffer descriptors) in memory. Write the control infor- mation in the LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx registers location of the buffer descriptor for each LLI in memory (see Table 23-3) for channel x. For example, in the register, you can program the following: - Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register. - Set up the transfer characteristics, such as:

• Transfer width for the source in the SRC_WIDTH field.
• Transfer width for the destination in the DST_WIDTH field.
• Incrementing/decrementing or fixed address for source in SRC_INCR field.
• Incrementing/decrementing or fixed address for destination DST_INCR field. 3. Write the channel configuration information into the DMAC_CFGx register for channel x. - Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respec- tively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘0’ activates the software handshaking interface to handle source/destination requests. - If the hardware handshaking interface is activated for the source or destination peripheral, assign the hand- shaking interface to the source and destination peripheral. This requires programming the SRC_PER and DST_PER bits, respectively. 4. Make sure that the LLI.DMAC_CTRLBx register locations of all LLI entries in memory (except the last) are set as shown in Row 4 of Table 23-3. The LLI.DMAC_CTRLBx register of the last Linked List Item must be set as described in Row 1 of Table 23-3. Figure 23-4 shows a Linked List example with two list items. 5. Make sure that the LLI.DMAC_DSCRx register locations of all LLI entries in memory (except the last) are non- zero and point to the base address of the next Linked List Item. 6. Make sure that the LLI.DMAC_SADDRx/LLI.DMAC_DADDRx register locations of all LLI entries in memory point to the start source/destination buffer address preceding that LLI fetch. 7. Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register locations of all LLI entries in memory are cleared. 8. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the status register: DMAC_EBCISR. 9. Program the DMAC_CTRLBx, DMAC_CFGx registers according to Row 4 as shown in Table 23-3. 10. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first Linked List item. 11. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENAx bit, where x is the channel number. The transfer is performed. 12. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0). Note: The LLI.DMAC_SADDRx, LLI. DMAC_DADDRx, LLI.DMAC_DSCRx, LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx registers are fetched. The DMAC automatically reprograms the DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLBx and DMAC_CTRLAx channel registers from the DMAC_DSCRx(0). 13. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming non-memory peripheral). The DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer. 14. Once the buffer of data is transferred, the DMAC_CTRLAx register is written out to system memory at the same location and on the same layer where it was originally fetched, that is, the location of the DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer transfer. Only DMAC_CTRLAx register is written out because only the DMAC_CTRLAx.BTSIZE and DMAC_CTRLAX.DONE bits have been updated by DMAC hard- ware. Additionally, the DMAC_CTRLAx.DONE bit is asserted when the buffer transfer has completed. Note: Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the LLI.DMAC_CTR - LAx.DONE bit in the LLI for that buffer. If the poll LLI.DMAC_CTRLAx.DONE bit is asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared at the start of the transfer. 15. The DMAC does not wait for the buffer interrupt to be cleared, but continues fetching the next LLI from the mem- ory location pointed to by current DMAC_DSCRx register and automatically reprograms the DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx and DMAC_CTRLBx channel registers. The DMAC transfer continues until the DMAC determines that the DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buf- fer transfer match described in Row 1 of Table 23-3. The DMAC then knows that the previous buffer transferred

 2020 Microchip Technology Inc. DS60001614B-page 277 SAM3X8ERT was the last buffer in the DMAC transfer. The DMAC transfer might look like that shown in Figure 23-5. FIGURE 23-5: MULTI-BUFFER WITH LINKED LIST ADDRESS FOR SOURCE AND DESTINATION If the user needs to execute a DMAC transfer where the source and destination address are contiguous but the amount of data to be transferred is greater than the maximum buffer size DMAC_CTRLAx.BTSIZE, then this can be achieved using the type of multi-buffer transfer as shown in Figure 23-6. SADDR(2) SADDR(1) SADDR(0) DADDR(2) DADDR(1) DADDR(0) Buffer 2 Buffer 1 Buffer 0 Buffer 0 Buffer 1 Buffer 2 Address of Source Layer Address of Destination Layer Source Buffers Destination Buffers

DS60001614B-page 278  2020 Microchip Technology Inc. FIGURE 23-6: MULTI-BUFFER WITH LINKED ADDRESS FOR SOURCE AND DESTINATION BUFFERS ARE CONTIGUOUS The DMAC transfer flow is shown in Figure 23-7. SADDR(2) SADDR(1) SADDR(0) DADDR(2) DADDR(1) DADDR(0) Buffer 2 Buffer 1 Buffer 0 Buffer 0 Buffer 1 Buffer 2 Address of Source Layer Address of Destination Layer Source Buffers Destination Buffers SADDR(3) Buffer 2 DADDR(3) Buffer 2

 2020 Microchip Technology Inc. DS60001614B-page 279 SAM3X8ERT FIGURE 23-7: DMAC TRANSFER FLOW FOR SOURCE AND DESTINATION LINKED LIST ADDRESS 1. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register. 2. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_h2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘0’ activates the software handshaking interface to handle source/destination requests. 3. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DST_PER bits, respectively. Channel enabled by software LLI Fetch Hardware reprograms SADDRx, DADDRx, CTRLA/Bx, DSCRx DMAC buffer transfer Writeback of DMAC_CTRLAx register in system memory Is DMAC in Row 1 of DMAC State Machine Table? Channel disabled by hardware Chained Buffer Transfer Completed Interrupt generated here DMAC Chained Buffer Transfer Completed Interrupt generated here yes no

DS60001614B-page 280  2020 Microchip Technology Inc. 4. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming non-memory peripherals). The DMAC acknowledges on completion of each chunk/single transaction and carries out the buffer transfer. - Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control peripheral by programming the FC of the DMAC_CTRLBx register. - Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respec- tively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘0’ activates the software handshaking interface source/destination requests. - If the hardware handshaking interface is activated for the source or destination peripheral, assign handshak- ing interface to the source and destination peripheral. This requires programming the SRC_PER and DST_PER bits, respectively. 5. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming non-memory peripherals). DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer. - Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register. - Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respec- tively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘0’ activates the software handshaking interface to handle source/destination requests. - If the hardware handshaking interface is activated for the source or destination peripheral, assign the hand- shaking interface to the source and destination peripheral. This requires programming the SRC_PER and DST_PER bits, respectively. 6. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming non-memory peripherals). The DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer. Multi-buffer DMAC Transfer with Linked List for Source and Contiguous Destination Address (Row 2) 1. Read the Channel Handler Status register to choose a free (disabled) channel. 2. Set up the linked list in memory. Write the control information in the LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx register location of the buffer descriptor for each LLI in memory for channel x. For example, in the register, you can program the following: - Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register. - Set up the transfer characteristics, such as:

• Transfer width for the source in the SRC_WIDTH field.
• Transfer width for the destination in the DST_WIDTH field.
• Incrementing/decrementing or fixed address for source in SRC_INCR field.
• Incrementing/decrementing or fixed address for destination DST_INCR field. 3. Write the starting destination address in the DMAC_DADDRx register for channel x. Note: The values in the LLI.DMAC_DADDRx register location of each Linked List Item (LLI) in memory, although fetched during an LLI fetch, are not used. 4. Write the channel configuration information into the DMAC_CFGx register for channel x. - Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respec- tively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘0’ activates the software handshaking interface to handle source/destination requests. - If the hardware handshaking interface is activated for the source or destination peripheral, assign the hand- shaking interface to the source and destination peripherals. This requires programming the SRC_PER and DST_PER bits, respectively. 5. Make sure that all LLI.DMAC_CTRLBx register locations of the LLI (except the last) are set as shown in Row 2 of Table 23-3, while the LLI.DMAC_CTRLBx register of the last Linked List item must be set as described in Row 1 of Table 23-3. Figure 23-4 shows a Linked List example with two list items.

 2020 Microchip Technology Inc. DS60001614B-page 281 SAM3X8ERT 6. Make sure that the LLI.DMAC_DSCRx register locations of all LLIs in memory (except the last) are non-zero and point to the next Linked List Item. 7. Make sure that the LLI.DMAC_SADDRx register locations of all LLIs in memory point to the start source buffer address proceeding that LLI fetch. 8. Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register locations of all LLIs in memory is cleared. 9. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status reg- ister. 10. Program the DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx registers according to Row 2 as shown in Table 23-3 11. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first Linked List item. 12. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENAx bit. The transfer is performed. Make sure that bit 0 of the DMAC_EN register is enabled. 13. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0). Note: The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI.DMAC_DSCRx and LLI.DMAC_CTRLA/Bx registers are fetched. The LLI.DMAC_DADDRx register location of the LLI, although fetched, is not used. The DMAC_DADDRx register in the DMAC remains unchanged. 14. Source and destination requests single and chunk DMAC transactions to transfer the buffer of data (assuming non-memory peripherals). The DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer. 15. Once the buffer of data is transferred, the DMAC_CTRLAx register is written out to the system memory at the same location and on the same layer (DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is, the loca- tion of the DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer transfer. Only DMAC_CTRLAx register is written out because only the DMAC_CTRLAx.BTSIZE and DMAC_CTRLAX.DONE fields have been updated by DMAC hardware. Additionally, the DMAC_CTRLAx.DONE bit is asserted when the buffer transfer has completed. Note: Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the LLI.DMAC_CTR - LAx.DONE bit in the LLI for that buffer. If the poll LLI.DMAC_CTRLAx.DONE bit is asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared at the start of the transfer. 16. The DMAC does not wait for the buffer interrupt to be cleared, but continues and fetches the next LLI from the memory location pointed to by the current DMAC_DSCRx register, then automatically reprograms the DMAC_SADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers. The DMAC_DAD - DRx register is left unchanged. The DMAC transfer continues until the DMAC samples the DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer transfer match that described in Row 1 of Table 23-3. The DMAC then knows that the previous buffer transferred was the last buffer in the DMAC transfer. The DMAC transfer might look like that shown in Figure 23-8. Note: The destination address is decrementing.

DS60001614B-page 282  2020 Microchip Technology Inc. FIGURE 23-8: DMAC TRANSFER WITH LINKED LIST SOURCE ADDRESS AND CONTIGUOUS DESTINATION ADDRESS The DMAC transfer flow is shown in Figure 23-9. SADDR(2) SADDR(1) SADDR(0) DADDR(2) DADDR(1) DADDR(0) Buffer 2 Buffer 1 Buffer 0 Buffer 0 Buffer 1 Buffer 2 Address of Source Layer Address of Destination Layer Source Buffers Destination Buffers

 2020 Microchip Technology Inc. DS60001614B-page 283 SAM3X8ERT FIGURE 23-9: DMAC TRANSFER FLOW FOR LINKED LIST SOURCE ADDRESS AND CONTIGUOUS DESTINATION ADDRESS

23.4.6 DISABLING A CHANNEL PRIOR TO TRANSFER COMPLETION

Under normal operation, the software enables a channel by writing a ‘1’ to the Channel Handler Enable Register, DMAC_CHER.ENAx, and the hardware disables a channel on transfer completion by clearing the DMAC_CHSR.ENAx register bit. The recommended way for software to disable a channel without losing data is to use the SUSPx bit in conjunction with the EMPTx bit in the Channel Handler Status Register. 1. If the software wishes to disable a channel n prior to the DMAC transfer completion, then it can set the DMAC_CHER.SUSPx bit to tell the DMAC to halt all transfers from the source peripheral. Therefore, the channel FIFO receives no new data. Channel enabled by software LLI Fetch Hardware reprograms SADDRx, CTRLAx,CTRLBx, DSCRx DMAC buffer transfer Writeback of control information of LLI Is DMAC in Row 1 ? Channel disabled by hardware Buffer Transfer Completed Interrupt generated here DMAC Chained Buffer Transfer Completed Interrupt generated here yes no

DS60001614B-page 284  2020 Microchip Technology Inc. 2. The software can now poll the DMAC_CHSR.EMPTx bit until it indicates that the channeln FIFO is empty, where n is the channel number. 3. The DMAC_CHER.ENAx bit can then be cleared by software once the channel n FIFO is empty, where n is the channel number. When DMAC_CTRLAx.SRC_WIDTH is less than DMAC_CTRLAx.DST_WIDTH and the DMAC_CHSRx.SUSPx bit is high, the DMAC_CHSRx.EMPTx is asserted once the contents of the FIFO does not permit a single word of DMAC_C- TRLAx.DST_WIDTH to be formed. However, there may still be data in the channel FIFO but not enough to form a single transfer of DMAC_CTLx.DST_WIDTH width. In this configuration, once the channel is disabled, the remaining data in the channel FIFO are not transferred to the destination peripheral. It is permitted to remove the channel from the sus - pension state by writing a ‘1’ to the DMAC_CHER.RESx field register. The DMAC transfer completes in the normal man- ner. n defines the channel number. Note: If a channel is disabled by software, an active single or chunk transaction is not guaranteed to receive an acknowledgment.

23.4.6.1 Abnormal Transfer Termination

A DMAC transfer may be terminated abruptly by software by clearing the channel enable bit, DMAC_CHDR.ENAx, where x is the channel number. This does not mean that the channel is disabled immediately after the DMAC_CHSR.ENAx bit is cleared over the APB interface. Consider this as a request to disable the channel. The DMAC_CHSR.ENAx must be polled and then it must be confirmed that the channel is disabled by reading back 0. The software may terminate all channels abruptly by clearing the global enable bit in the DMAC Configuration Register (DMAC_EN.ENABLE bit). Again, this does not mean that all channels are disabled immediately after the DMAC_EN.ENABLE is cleared over the APB slave interface. Consider this as a request to disable all channels. The DMAC_CHSR.ENABLE must be polled and then it must be confirmed that all channels are disabled by reading back ‘0’. Note: If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to the des- tination peripheral and is not present when the channel is re-enabled. For read sensitive source peripherals, such as a source FIFO, this data is therefore lost. When the source is not a read sensitive device (i.e., mem- ory), disabling a channel without waiting for the channel FIFO to empty may be acceptable as the data is available from the source peripheral upon request and is not lost. Note: If a channel is disabled by software, an active single or chunk transaction is not guaranteed to receive an acknowledgment.

23.5 DMAC Software Requirements

• There must not be any write operation to Channel registers in an active channel after the channel enable is made HIGH. If any channel parameters must be reprogrammed, this can only be done after disabling the DMAC chan- nel.
• When the destination peripheral has been defined as the flow controller, source single transfer requests are not serviced until the destination peripheral has asserted its Last Transfer Flag.
• When the source peripheral has been defined as the flow controller, destination single transfer requests are not serviced until the source peripheral has asserted its Last Transfer Flag.
• When the destination peripheral has been defined as the flow controller, if the destination width is smaller than the source width, then a data loss may occur, and the loss is equal to the Source Single Transfer size in bytes- desti- nation Single Transfer size in bytes.
• When a Memory to Peripheral transfer occurs, if the destination peripheral has been defined as the flow controller, then a prefetch operation is performed. It means that data is extracted from the memory before any request from the peripheral is generated.
• You must program the DMAC_SADDRx and DMAC_DADDRx channel registers with a byte, half-word and word aligned address depending on the source width and destination width.
• After the software disables a channel by writing into the channel disable register, it must re-enable the channel only after it has polled a 0 in the corresponding channel enable status register. This is because the current AHB Burst must terminate properly.
• If you program the BTSIZE field in the DMAC_CTRLA as zero, and the DMAC has been defined as the flow con- troller, then the channel is automatically disabled.
• When hardware handshaking interface protocol is fully implemented, a peripheral is expected to deassert any sreq or breq signals on receiving the ack signal irrespective of the request the ack was asserted in response to.
• Multiple Transfers involving the same peripheral must not be programmed and enabled on different channels,

 2020 Microchip Technology Inc. DS60001614B-page 285 SAM3X8ERT unless this peripheral integrates several hardware handshaking interfaces.

• When a Peripheral has been defined as the flow controller, the targeted DMAC Channel must be enabled before the Peripheral. If you do not ensure this and the First DMAC request is also the last transfer, the DMAC Channel might miss a Last Transfer Flag.

DS60001614B-page 286  2020 Microchip Technology Inc.

23.6 Write Protection Registers

To prevent any single software error that may corrupt the DMAC behavior, the DMAC address space can be write-pro- tected by setting the WPEN bit in the “DMAC Write Protect Mode Register” on page 310 (DMAC_WPMR). If a write access to anywhere in the DMAC address space is detected, then the WPVS flag in the DMAC Write Protect Status Register (MCI_WPSR) is set, and the WPVSRC field indicates in which register the write access has been attempted. The WPVS flag is reset by writing the DMAC Write Protect Mode Register (DMAC_WPMR) with the appropriate access key, WPKEY . The protected registers are:

• “DMAC Global Configuration Register” on page 289
• “DMAC Enable Register” on page 290
• “DMAC Channel x [x = 0..5] Source Address Register” on page 301
• “DMAC Channel x [x = 0..5] Destination Address Register” on page 302
• “DMAC Channel x [x = 0..5] Descriptor Address Register” on page 303
• “DMAC Channel x [x = 0..5] Control A Register” on page 304
• “DMAC Channel x [x = 0..5] Control B Register” on page 306
• “DMAC Channel x [x = 0..5] Configuration Register” on page 308

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23.7 AHB DMA Controller (DMAC) User Interface

TABLE 23-4: REGISTER MAPPING Offset Register Name Access Reset 0x000 DMAC Global Configuration Register DMAC_GCFG Read- write 0x10 0x004 DMAC Enable Register DMAC_EN Read- write 0x0 0x008 DMAC Software Single Request Register DMAC_SREQ Read- write 0x0 0x00C DMAC Software Chunk Transfer Request Register DMAC_CREQ Read- write 0x0 0x010 DMAC Software Last Transfer Flag Register DMAC_LAST Read- write 0x0 0x014 Reserved — — — 0x018 DMAC Error, Chained Buffer Transfer Com- pleted Interrupt and Buffer Transfer Com- pleted Interrupt Enable register. DMAC_EB- CIER Write- only 0x01C DMAC Error, Chained Buffer Transfer Com- pleted Interrupt and Buffer Transfer Com- pleted Interrupt Disable register. DMAC_EB- CIDR Write- only 0x020 DMAC Error, Chained Buffer Transfer Com- pleted Interrupt and Buffer transfer com- pleted Mask Register. DMAC_EB- CIMR Read- only 0x0 0x024 DMAC Error, Chained Buffer Transfer Com- pleted Interrupt and Buffer transfer com- pleted Status Register. DMAC_EB- CISR Read- only 0x0 0x028 DMAC Channel Handler Enable Register DMAC_CHER Write- only 0x02C DMAC Channel Handler Disable Register DMAC_CHDR Write- only 0x030 DMAC Channel Handler Status Register DMAC_CHSR Read- only 0x00FF00 0x034 Reserved — — — 0x038 Reserved — — — 0x03C+ch_- num*(0x28)+(0x0) DMAC Channel Source Address Register DMAC_SADD R Read- write 0x0 0x03C+ch_- num*(0x28)+(0x4) DMAC Channel Destination Address Regis- ter DMAC_- DADDR Read- write 0x0 0x03C+ch_- num*(0x28)+(0x8) DMAC Channel Descriptor Address Register DMAC_DSCR Read- write 0x0 0x03C+ch_- num*(0x28)+(0xC) DMAC Channel Control A Register DMAC_CTRLA Read- write 0x0 0x03C+ch_- num*(0x28)+(0x10) DMAC Channel Control B Register DMAC_CTRLB Read- write 0x0 0x03C+ch_- num*(0x28)+(0x14) DMAC Channel Configuration Register DMAC_CFG Read- write 0x0100000 0x03C+ch_- num*(0x28)+(0x18) Reserved — — — 0x03C+ch_- num*(0x28)+(0x1C) Reserved — — — 0x03C+ch_- num*(0x28)+(0x20) Reserved — — — 0x03C+ch_- num*(0x28)+(0x24) Reserved — — —

DS60001614B-page 288  2020 Microchip Technology Inc. 0x1E4 DMAC Write Protect Mode Register DMAC_WPMR Read- write 0x0 0x1E8 DMAC Write Protect Status Register DMAC_WPSR Read- only 0x0 0x01EC- 0x1FC Reserved — — — TABLE 23-4: REGISTER MAPPING Offset Register Name Access Reset

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23.7.1 DMAC GLOBAL CONFIGURATION REGISTER

Name: DMAC_GCFG Address:0x400C4000 Access: Read-write Reset: 0x00000010 Note: Bit fields 0, 1, 2, 3, have a default value of 0. This should not be changed. This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” on page 310.

• ARB_CFG: Arbiter Configuration 0 (FIXED): Fixed priority arbiter. 1 (ROUND_ROBIN): Modified round robin arbiter. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

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23.7.2 DMAC ENABLE REGISTER

Name: DMAC_EN Address:0x400C4004 Access: Read-write Reset: 0x00000000 This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” on page 310.

• ENABLE 0: DMA Controller is disabled. 1: DMA Controller is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

 2020 Microchip Technology Inc. DS60001614B-page 291 SAM3X8ERT

23.7.3 DMAC SOFTWARE SINGLE REQUEST REGISTER

Name: DMAC_SREQ Address:0x400C4008 Access: Read-write Reset: 0x00000000

• DSREQx: Destination Request Request a destination single transfer on channel i.
• SSREQx: Source Request Request a source single transfer on channel i. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — — — — DSREQ5 SSREQ5 DSREQ4 SSREQ4 7 6 5 4 3 2 1 0 DSREQ3 SSREQ3 DSREQ2 SSREQ2 DSREQ1 SSREQ1 DSREQ0 SSREQ0

DS60001614B-page 292  2020 Microchip Technology Inc.

23.7.4 DMAC SOFTWARE CHUNK TRANSFER REQUEST REGISTER

Name: DMAC_CREQ Address:0x400C400C Access: Read-write Reset: 0x00000000

• DCREQx: Destination Chunk Request Request a destination chunk transfer on channel i.
• SCREQx: Source Chunk Request Request a source chunk transfer on channel i. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — — — — DCREQ5 SCREQ5 DCREQ4 SCREQ4 7 6 5 4 3 2 1 0 DCREQ3 SCREQ3 DCREQ2 SCREQ2 DCREQ1 SCREQ1 DCREQ0 SCREQ0

 2020 Microchip Technology Inc. DS60001614B-page 293 SAM3X8ERT

23.7.5 DMAC SOFTWARE LAST TRANSFER FLAG REGISTER

Name: DMAC_LAST Address:0x400C4010 Access: Read-write Reset: 0x00000000

• DLASTx: Destination Last Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer.
• SLASTx: Source Last Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — — — — DLAST5 SLAST5 DLAST4 SLAST4 7 6 5 4 3 2 1 0 DLAST3 SLAST3 DLAST2 SLAST2 DLAST1 SLAST1 DLAST0 SLAST0

DS60001614B-page 294  2020 Microchip Technology Inc.

23.7.6 DMAC ERROR, BUFFER TRANSFER AND CHAINED BUFFER TRANSFER INTERRUPT

Name: DMAC_EBCIER Address:0x400C4018 Access: Write-only Reset: 0x00000000

• BTCx: Buffer Transfer Completed [5:0] Buffer Transfer Completed Interrupt Enable Register. Set the relevant bit in the BTC field to enable the interrupt for chan- nel i.
• CBTCx: Chained Buffer Transfer Completed [5:0] Chained Buffer Transfer Completed Interrupt Enable Register. Set the relevant bit in the CBTC field to enable the inter- rupt for channel i.
• ERRx: Access Error [5:0] Access Error Interrupt Enable Register. Set the relevant bit in the ERR field to enable the interrupt for channel i. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — ERR5 ERR4 ERR3 ERR2 ERR1 ERR0 15 14 13 12 11 10 9 8 — — CBTC5 CBTC4 CBTC3 CBTC2 CBTC1 CBTC0 7 6 5 4 3 2 1 0 — — BTC5 BTC4 BTC3 BTC2 BTC1 BTC0

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23.7.7 DMAC ERROR, BUFFER TRANSFER AND CHAINED BUFFER TRANSFER INTERRUPT

Name: DMAC_EBCIDR Address:0x400C401C Access: Write-only Reset: 0x00000000

• BTCx: Buffer Transfer Completed [5:0] Buffer transfer completed Disable Interrupt Register. When set, a bit of the BTC field disables the interrupt from the rel- evant DMAC channel.
• CBTCx: Chained Buffer Transfer Completed [5:0] Chained Buffer transfer completed Disable Register. When set, a bit of the CBTC field disables the interrupt from the relevant DMAC channel.
• ERRx: Access Error [5:0] Access Error Interrupt Disable Register. When set, a bit of the ERR field disables the interrupt from the relevant DMAC channel. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — ERR5 ERR4 ERR3 ERR2 ERR1 ERR0 15 14 13 12 11 10 9 8 — — CBTC5 CBTC4 CBTC3 CBTC2 CBTC1 CBTC0 7 6 5 4 3 2 1 0 — — BTC5 BTC4 BTC3 BTC2 BTC1 BTC0

DS60001614B-page 296  2020 Microchip Technology Inc.

23.7.8 DMAC ERROR, BUFFER TRANSFER AND CHAINED BUFFER TRANSFER INTERRUPT

Name:DMAC_EBCIMR Address:0x400C4020 Access: Read-only Reset:0x00000000

• BTCx: Buffer Transfer Completed [5:0] 0: Buffer Transfer Completed Interrupt is disabled for channel i. 1: Buffer Transfer Completed Interrupt is enabled for channel i.
• CBTCx: Chained Buffer Transfer Completed [5:0] 0: Chained Buffer Transfer interrupt is disabled for channel i. 1: Chained Buffer Transfer interrupt is enabled for channel i.
• ERRx: Access Error [5:0] 0: Transfer Error Interrupt is disabled for channel i. 1: Transfer Error Interrupt is enabled for channel i. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — ERR5 ERR4 ERR3 ERR2 ERR1 ERR0 15 14 13 12 11 10 9 8 — — CBTC5 CBTC4 CBTC3 CBTC2 CBTC1 CBTC0 7 6 5 4 3 2 1 0 — — BTC5 BTC4 BTC3 BTC2 BTC1 BTC0

 2020 Microchip Technology Inc. DS60001614B-page 297 SAM3X8ERT

23.7.9 DMAC ERROR, BUFFER TRANSFER AND CHAINED BUFFER TRANSFER STATUS

Name:DMAC_EBCISR Address:0x400C4024 Access:Read-only Reset:0x00000000

• BTCx: Buffer Transfer Completed [5:0] When BTC[i] is set, Channel i buffer transfer has terminated.
• CBTCx: Chained Buffer Transfer Completed [5:0] When CBTC[i] is set, Channel i Chained buffer has terminated. LLI Fetch operation is disabled.
• ERRx: Access Error [5:0] When ERR[i] is set, Channel i has detected an AHB Read or Write Error Access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — ERR5 ERR4 ERR3 ERR2 ERR1 ERR0 15 14 13 12 11 10 9 8 — — CBTC5 CBTC4 CBTC3 CBTC2 CBTC1 CBTC0 7 6 5 4 3 2 1 0 — — BTC5 BTC4 BTC3 BTC2 BTC1 BTC0

DS60001614B-page 298  2020 Microchip Technology Inc.

23.7.10 DMAC CHANNEL HANDLER ENABLE REGISTER

Name: DMAC_CHER Address:0x400C4028 Access:Write-only Reset:0x00000000

• ENAx: Enable [5:0] When set, a bit of the ENA field enables the relevant channel.
• SUSPx: Suspend [5:0] When set, a bit of the SUSP field freezes the relevant channel and its current context.
• KEEPx: Keep on [5:0] When set, a bit of the KEEP field resumes the current channel from an automatic stall state. 31 30 29 28 27 26 25 24 — — KEEP5 KEEP4 KEEP3 KEEP2 KEEP1 KEEP0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — — SUSP5 SUSP4 SUSP3 SUSP2 SUSP1 SUSP0 7 6 5 4 3 2 1 0 — — ENA5 ENA4 ENA3 ENA2 ENA1 ENA0

 2020 Microchip Technology Inc. DS60001614B-page 299 SAM3X8ERT

23.7.11 DMAC CHANNEL HANDLER DISABLE REGISTER

Name: DMAC_CHDR Address:0x400C402C Access: Write-only Reset:0x00000000

• DISx: Disable [5:0] Write one to this field to disable the relevant DMAC Channel. The content of the FIFO is lost and the current AHB access is terminated. Software must poll DIS[5:0] field in the DMAC_CHSR register to be sure that the channel is disabled.
• RESx: Resume [5:0] Write one to this field to resume the channel transfer restoring its context. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — — RES5 RES4 RES3 RES2 RES1 RES0 7 6 5 4 3 2 1 0 — — DIS5 DIS4 DIS3 DIS2 DIS1 DIS0

DS60001614B-page 300  2020 Microchip Technology Inc.

23.7.12 DMAC CHANNEL HANDLER STATUS REGISTER

Name: DMAC_CHSR Address:0x400C4030 Access: Read-only Reset: 0x00FF0000

• ENAx: Enable [5:0] A one in any position of this field indicates that the relevant channel is enabled.
• SUSPx: Suspend [5:0] A one in any position of this field indicates that the channel transfer is suspended.
• EMPTx: Empty [5:0] A one in any position of this field indicates that the relevant channel is empty.
• STALx: Stalled [5:0] A one in any position of this field indicates that the relevant channel is stalling. 31 30 29 28 27 26 25 24 — — STAL5 STAL4 STAL3 STAL2 STAL1 STAL0 23 22 21 20 19 18 17 16 — — EMPT5 EMPT4 EMPT3 EMPT2 EMPT1 EMPT0 15 14 13 12 11 10 9 8 — — SUSP5 SUSP4 SUSP3 SUSP2 SUSP1 SUSP0 7 6 5 4 3 2 1 0 — — ENA5 ENA4 ENA3 ENA2 ENA1 ENA0

 2020 Microchip Technology Inc. DS60001614B-page 301 SAM3X8ERT 23.7.13 DMAC CHANNEL X [X = 0..5] SOURCE ADDRESS REGISTER Name: DMAC_SADDRx [x = 0..5] Address:0x400C403C [0], 0x400C4064 [1], 0x400C408C [2], 0x400C40B4 [3], 0x400C40DC [4], 0x400C4104 [5] Access: Read-write Reset: 0x00000000 This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” on page 310.

• SADDR: Channel x Source Address This register must be aligned with the source transfer width. 31 30 29 28 27 26 25 24 SADDR 23 22 21 20 19 18 17 16 SADDR 15 14 13 12 11 10 9 8 SADDR 7 6 5 4 3 2 1 0 SADDR

DS60001614B-page 302  2020 Microchip Technology Inc. 23.7.14 DMAC CHANNEL X [X = 0..5] DESTINATION ADDRESS REGISTER Name:DMAC_DADDRx [x = 0..5] Address:0x400C4040 [0], 0x400C4068 [1], 0x400C4090 [2], 0x400C40B8 [3], 0x400C40E0 [4], 0x400C4108 [5] Access: Read-write Reset: 0x00000000 This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” on page 310.

• DADDR: Channel x Destination Address This register must be aligned with the destination transfer width. 31 30 29 28 27 26 25 24 DADDR 23 22 21 20 19 18 17 16 DADDR 15 14 13 12 11 10 9 8 DADDR 7 6 5 4 3 2 1 0 DADDR

 2020 Microchip Technology Inc. DS60001614B-page 303 SAM3X8ERT 23.7.15 DMAC CHANNEL X [X = 0..5] DESCRIPTOR ADDRESS REGISTER Name: DMAC_DSCRx [x = 0..5] Address:0x400C4044 [0], 0x400C406C [1], 0x400C4094 [2], 0x400C40BC [3], 0x400C40E4 [4], 0x400C410C [5] Access: Read-write Reset:0x00000000 This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” on page 310.

• DSCR: Buffer Transfer Descriptor Address This address is word aligned. 31 30 29 28 27 26 25 24 DSCR 23 22 21 20 19 18 17 16 DSCR 15 14 13 12 11 10 9 8 DSCR 7 6 5 4 3 2 1 0 DSCR –

DS60001614B-page 304  2020 Microchip Technology Inc. 23.7.16 DMAC CHANNEL X [X = 0..5] CONTROL A REGISTER Name: DMAC_CTRLAx [x = 0..5] Address:0x400C4048 [0], 0x400C4070 [1], 0x400C4098 [2], 0x400C40C0 [3], 0x400C40E8 [4], 0x400C4110 [5] Access: Read-write Reset: 0x00000000 This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” on page 310

• BTSIZE: Buffer Transfer Size The transfer size relates to the number of transfers to be performed, that is, for writes it refers to the number of source width transfers to perform when DMAC is flow controller. For Reads, BTSIZE refers to the number of transfers com - pleted on the Source Interface. When this field is set to 0, the DMAC module is automatically disabled when the relevant channel is enabled.
• SCSIZE: Source Chunk Transfer Size. 31 30 29 28 27 26 25 24 DONE – DST_WIDTH – – SRC_WIDTH 23 22 21 20 19 18 17 16 – DCSIZE – SCSIZE 15 14 13 12 11 10 9 8 BTSIZE 7 6 5 4 3 2 1 0 BTSIZE Value Name Description

000 CHK_1 1 data transferred

001 CHK_4 4 data transferred

010 CHK_8 8 data transferred

011 CHK_16 16 data transferred

100 CHK_32 32 data transferred

101 CHK_64 64 data transferred

110 CHK_128 128 data transferred

111 CHK_256 256 data transferred

 2020 Microchip Technology Inc. DS60001614B-page 305 SAM3X8ERT

• DCSIZE: Destination Chunk Transfer Size
• SRC_WIDTH: Transfer Width for the Source
• DST_WIDTH: Transfer Width for the Destination
• DONE 0: The transfer is performed. 1: If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the content of this register. The DONE field is written back to memory at the end of the transfer. Value Name Description

00 BYTE the transfer size is set to 8-bit width

01 HALF_WORD the transfer size is set to 16-bit width

1X WORD the transfer size is set to 32-bit width Value Name Description 1X WORD the transfer size is set to 32-bit width

DS60001614B-page 306  2020 Microchip Technology Inc. 23.7.17 DMAC CHANNEL X [X = 0..5] CONTROL B REGISTER Name:DMAC_CTRLBx [x = 0..5] Address:0x400C404C [0], 0x400C4074 [1], 0x400C409C [2], 0x400C40C4 [3], 0x400C40EC [4], 0x400C4114 [5] Access:Read-write Reset: 0x00000000 This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” on page 310.

• SRC_DSCR: Source Address Descriptor 0 (FETCH_FROM_MEM): Source address is updated when the descriptor is fetched from the memory. 1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the source.
• DST_DSCR: Destination Address Descriptor 0 (FETCH_FROM_MEM): Destination address is updated when the descriptor is fetched from the memory. 1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the destination.
• FC: Flow Control This field defines which device controls the size of the buffer transfer, also referred to as the Flow Controller.
• SRC_INCR: Incrementing, Decrementing or Fixed Address for the Source 31 30 29 28 27 26 25 24 — IEN DST_INCR — — SRC_INCR 23 22 21 20 19 18 17 16 FC DST_DSC R — — — SRC_DSC R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value Name Description

000 MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller

001 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller

010 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller

011 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow

00 INCREMENTING The source address is incremented

01 DECREMENTING The source address is decremented

10 FIXED The source address remains unchanged

 2020 Microchip Technology Inc. DS60001614B-page 307 SAM3X8ERT

• DST_INCR: Incrementing, Decrementing or Fixed Address for the Destination
• IEN If this bit is cleared, when the buffer transfer is completed, the BTCx flag is set in the EBCISR status register. This bit is active low. Value Name Description

00 INCREMENTING The destination address is incremented

01 DECREMENTING The destination address is decremented

10 FIXED The destination address remains unchanged

DS60001614B-page 308  2020 Microchip Technology Inc. 23.7.18 DMAC CHANNEL X [X = 0..5] CONFIGURATION REGISTER Name: DMAC_CFGx [x = 0..5] Address:0x400C4050 [0], 0x400C4078 [1], 0x400C40A0 [2], 0x400C40C8 [3], 0x400C40F0 [4], 0x400C4118 [5] Access:Read-write Reset:0x0100000000 This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” on page 310

• SRC_PER: Source with Peripheral identifier Channel x Source Request is associated with peripheral identifier coded SRC_PER handshaking interface.
• DST_PER: Destination with Peripheral identifier Channel x Destination Request is associated with peripheral identifier coded DST_PER handshaking interface.
• SRC_H2SEL: Software or Hardware Selection for the Source 0 (SW): Software handshaking interface is used to trigger a transfer request. 1 (HW): Hardware handshaking interface is used to trigger a transfer request.
• DST_H2SEL: Software or Hardware Selection for the Destination 0 (SW): Software handshaking interface is used to trigger a transfer request. 1 (HW): Hardware handshaking interface is used to trigger a transfer request.
• SOD: Stop On Done 0 (DISABLE): STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 1 (ENABLE): STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.
• LOCK_IF: Interface Lock 0 (DISABLE): Interface Lock capability is disabled 1 (ENABLE): Interface Lock capability is enabled
• LOCK_B: Bus Lock 0 (DISABLE): AHB Bus Locking capability is disabled. 1(ENABLE): AHB Bus Locking capability is enabled.
• LOCK_IF_L: Master Interface Arbiter Lock 0 (HUNK): The Master Interface Arbiter is locked by the channel x for a chunk transfer. 1 (BUFFER): The aster Interface Arbiter is locked by the channel x for a buffer transfer.
• AHB_PROT: AHB Protection 31 30 29 28 27 26 25 24 — — FIFOCFG — AHB_PROT 23 22 21 20 19 18 17 16 — LOCK_IF_ L LOCK_B LOCK_IF — — — SOD 15 14 13 12 11 10 9 8 — — DST_H2S 7 6 5 4 3 2 1 0 DST_PER SRC_PER

 2020 Microchip Technology Inc. DS60001614B-page 309 SAM3X8ERT AHB_PROT field rovides additional information about a bus access and is primarily used to implement some level of protection.

• FIFOCFG: FIFO Configuration HPROT[3] HPROT[2] HPROT[1] HPROT[0] Description — — — 1 Data access — — AHB_PROT[0] — 0: User Access 1: Privileged Access — AHB_PROT[1] — — 0: Not Bufferable 1: Bufferable AHB_PROT[2] — — — 0: Not cacheable 1: Cacheable Value Name Description

00 ALAP_CFG The largest defined length AHB burst is performed on the destination AHB

interface.

01 HALF_CFG When half FIFO size is available/filled, a source/destination request is

serviced.

10 ASAP_CFG When there is enough space/data available to perform a single AHB access,

then the request is serviced.

DS60001614B-page 310  2020 Microchip Technology Inc.

23.7.19 DMAC WRITE PROTECT MODE REGISTER

• WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x444D4143 (“DMAC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x444D4143 (“DMAC” in ASCII). Protects the registers:
• “DMAC Global Configuration Register” on page 289
• “DMAC Enable Register” on page 290
• “DMAC Channel x [x = 0..5] Source Address Register” on page 301
• “DMAC Channel x [x = 0..5] Destination Address Register” on page 302
• “DMAC Channel x [x = 0..5] Descriptor Address Register” on page 303
• “DMAC Channel x [x = 0..5] Control A Register” on page 304
• “DMAC Channel x [x = 0..5] Control B Register” on page 306
• “DMAC Channel x [x = 0..5] Configuration Register” on page 308
• WPKEY: Write Protect KEY Should be written at value 0x50494F (“DMAC” in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 7 6 5 4 3 2 1 0

 2020 Microchip Technology Inc. DS60001614B-page 311 SAM3X8ERT

23.7.20 DMAC WRITE PROTECT STATUS REGISTER

Name:DMAC_WPSR Address:0x400C41E8 Access:Read-only Reset:See Table 23-4

• WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the DMAC_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the DMAC_WPSR register. If this violation is an unau- thorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. Note: Reading DMAC_WPSR automatically clears all fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WPVSRC 15 14 13 12 11 10 9 8 WPVSRC 7 6 5 4 3 2 1 0

DS60001614B-page 312  2020 Microchip Technology Inc.

24.0 EXTERNAL MEMORY BUS

24.1 Description

The external memory bus allows external devices connection to the various embedded memory controllers of the micro- controller. The external memory bus handles control, address and data bus of each embedded memory controllers. The SAM3X8ERT embeds a Static Memory/NAND Flash/ECC Controller (SMC/NFC/ECC). Furthermore, the external mem- ory bus handles data transfers with up to eight external devices, each assigned to eight address spaces. Data transfers are performed through a 8-bit or 16-bit data bus, an address bus of up to 24 bits, up to eight chip select lines (NCS[7:0]) and several control pins that are generally multiplexed between the different embedded memory controllers.

24.2 Embedded Characteristics

• Only present on 144-pin SAM3X8ERT versions
• Managing SMC and NAND Flash Controller accesses offering: - Up to 8 configurable chip selects - Programmable timing on a per chip select basis - 16 Mbyte Address Space per Chip Select - 8- or 16-bit Data Bus - Word, Halfword, Byte Transfers - Byte Write or Byte Select Lines - Programmable Setup, Pulse and Hold Time for Read Signals per Chip Select - Programmable Setup, Pulse and Hold Time for Write Signals per Chip Select - Programmable Data Float Time per Chip Select - External Wait Request - Automatic Switch to Slow Clock Mode - Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 bytes - NAND Flash Controller supporting NAND Flash with Multiplexed Data/Address buses - Supports SLC NAND Flash technology - Supports Hardware Error Correcting Code (ECC), 1-bit error correction, 2-bit error detection - Detection and Correction by Software

 2020 Microchip Technology Inc. DS60001614B-page 313 SAM3X8ERT

24.3 Block Diagram

FIGURE 24-1: ORGANIZATION OF THE EXTERNAL BUS INTERFACE

DS60001614B-page 314  2020 Microchip Technology Inc.

24.4 I/O Lines Description

The connection of some signals through the Mux logic is not direct and depends on the Memory Controller in use at the moment. Table 24-2 details the connections between the two memory controllers and the bus pins.

24.5 Application Example

24.5.1 HARDWARE INTERFACE

Table 24-3 details the connections to be applied between the External Memory Bus pins and the external devices for each memory controller. TABLE 24-1: I/O LINES DESCRIPTION Name Function Type Active Level External Memory Bus D[15:0] Data Bus I/O — A[23:0] Address Bus Output — Static Memory Controller (SMC) NCS[7:0] Chip Select Lines Output Low NWR0/NWE Write Signals Output Low NRD Read Signal Output Low NWR1/NBS1 Write Enable/Upper Byte Select Output Low A0/NBS0 Lower Byte Select Output Low NWAIT External Wait Signal Input Low NAND Flash Controller (NFC) NCS[7:0] Chip Select Lines Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low NANDCLE NAND Flash Command Line Enable Output Low NANDALE NAND Flash Address Line Enable Output Low NANDRDY NAND Flash Ready/Busy Input Low TABLE 24-2: EXTERNAL MEMORY BUS PINS AND MEMORY CONTROLLERS I/O LINES CONNECTIONS EBI Pins SMC I/O Lines NWR1/NBS1 NWR1/NBS1 A0/NBS0 A0/NBS0 A1 A1 A[11:2] A[11:2] A12 A12 A[14:13] A[14:13] A[23:15] A[23:15] D[15:0] D[15:0]

 2020 Microchip Technology Inc. DS60001614B-page 315 SAM3X8ERT Note 1: I/O8–I/O15 bits used only for 16-bit NAND Flash. 2: NWR1 enables upper byte writes. NWR0 enables lower byte writes. 3: CE connection depends on the NAND Flash. For standard NAND Flash devices, it must be connected to any free PIO line. For “CE don’t care” 8-bit NAND Flash devices, it can be either connected to any NCS For “CE don’t care” 16-bit NAND Flash devices, it must be connected to any free PIO line. TABLE 24-3: EBI PINS AND EXTERNAL STATIC DEVICE CONNECTIONS EBI Pins SMC Pins 8-bit Static Device 2 x 8-bit Static Devices 16-bit Static Device NAND Flash D0–D7 D0–D7 D0–D7 D0–D7 I/O0–I/O7 D8–D15 — D8–D15 D8–D15 I/O8–I/O15(1) A0/NBS0 A0 — NLB — A1 A1 A0 A0 — A2–A9 A2–A9 A1–A8 A1–A8 — A10 A10 A9 A9 — A11 A11 A10 A10 — SDCS — — — — SDA10 — — — — A12 A12 A11 A11 — A13–A14 A13–A14 A12–A13 A12–A13 — A15 A15 A14 A14 — A16/BA0 A16 A15 A15 — A17/BA1 A17 A16 A16 — A18–A20 A18–A20 A17–A19 A17–A19 — A21/NANDALE A21 A20 A20 ALE A22/NANDCLE A22 A21 A21 CLE A23 A23 A22 A22 — NCS0 CS CS CS CE(3) NCS1 CS CS CS — NCS2 CS CS CS CE(3) NCS3 CS CS CS CE(3) NCS4 CS CS CS CE(3) NCS5 CS CS CS CE(3) NCS6 CS CS CS CE(3) NCS7 CS CS CS CE(3) NANDOE — — — RE NANDWE — — — WE NRD OE OE OE — NWR0/NWE WE WE(2) WE — NWR1/NBS1 WE WE(2) NUB — SDCK — — — — SDCKE — — — — RAS — — — — CAS — — — — SDWE — — — — NWAIT — — — — NANDRDY — — — RDY

DS60001614B-page 316  2020 Microchip Technology Inc.

24.6 Product Dependencies

24.6.1 I/O LINES

The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the External Bus Interface are not used by the application, they can be used for other purposes by the PIO Controller.

24.7 Functional Description

The external memory bus transfers data between the internal AHB Bus (handled by the memory controllers) and the external memories or peripheral devices. It controls the waveforms and the parameters of the external address, data and control buses and is composed of the following elements:

• Static Memory Controller (SMC)
• NAND Flash Controller (NFC)
• ECC Controller (ECC)

24.7.1 BUS MULTIPLEXING

The external memory bus offers a complete set of control signals that share the 16-bit data lines, the address lines of up to 24 bits and the control signals through a multiplex logic operating in function of the memory area requests. Multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines at a stable state while no external access is being performed. Multiplexing is also designed to respect the data float times defined in the Memory Controllers.

24.7.2 STATIC MEMORY CONTROLLER

For information on the Static Memory Controller, refer to “Static Memory Controller (SMC)” on page 319.

24.7.3 NAND FLASH CONTROLLER

For information on the NAND Flash Controller, refer to “Static Memory Controller (SMC)” on page 319.

24.7.4 ECC CONTROLLER

For information on the ECC Controller, refer to “Static Memory Controller (SMC)” on page 319.

24.8 Implementation Examples

24.8.1 8-BIT AND 16-BIT NAND FLASH

24.8.1.1 Software Configuration (8-bit and 16-bit NAND Flash)

The following configuration must be respected:

• NADNCLE, NANDALE, NANDOE, NANDRDY and NANDWE signals are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. D[0:7] or D[0:15] must be pro- grammed in peripheral mode in the PIO controller.
• Assign the SMC chip select line CSx to the NAND Flash by setting the CSID field in the NFCADDR_CMD Regis- ter.
• Configure Static Memory Controller CSx Setup, Pulse, Cycle and Mode according to NAND Flash timings, the data bus width and the system bus frequency.

 2020 Microchip Technology Inc. DS60001614B-page 317 SAM3X8ERT FIGURE 24-2: 8-BIT AND 16-BIT NAND FLASH HARDWARE CONFIGURATION

24.8.2 NOR FLASH ON NCS0

24.8.2.1 Software Configuration (NOR Flash on NCS0)

Address lines A[1..22], NCS0, NRD, NWE and data lines D[0..15] are multiplexed with PIO lines and thus dedicated PIOs must be programmed in peripheral mode in the PIO controller. The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows access on 16-bit non-volatile memory at slow clock. For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending on Flash timings and system bus frequency. WE CE RE R/B I/O0 ALE CLE I/O1 I/O3 I/O2 I/O7 I/O6 I/O5 I/O4 I/O0 I/O1 I/O3 I/O2 I/O7 I/O6 I/O5 I/O4 NCSx NANDRDY 8-bit NAND D14 D11 D12 D10 D13 D15 WE CE RE R/B I/O8 ALE CLE I/O9 I/O11 I/O10 I/O15 I/O14 I/O13 I/O12 16-bit NAND NANDWE NANDOE NANDALE NANDCLE D[0:15]

DS60001614B-page 318  2020 Microchip Technology Inc. FIGURE 24-3: NOR FLASH ON NCS0 HARDWARE CONFIGURATION A21 A22 A15 A12 A13 A11 A10 A14 A16 D14 D11 D12 D10 D13 D15 A17 A20 A18 A19 D[0..15] A[1..22] NRST NWE NCS0 NRD 3V3 3V3 TSOP48 PACKAGE 100NF 100NF 100NF 100NF AT49BV6416 AT49BV6416 A025 A124 A223 A322 A421 A520 A619 A718 A88 A97 A106 A115 A124 A133 A142 A151 A1648 A1717 A1816 A219 A2010 A1915 WE11 RESET12 WP14 OE28 CE26 VPP13 DQ0 29 DQ1 31 DQ2 33 DQ3 35 DQ4 38 DQ5 40 DQ6 42 DQ7 44 DQ8 30 DQ9 32 DQ10 34 DQ11 36 DQ12 39 DQ13 41 DQ14 43 DQ15 45 VCCQ 47 VSS 27VSS 46 VCC 37

 2020 Microchip Technology Inc. DS60001614B-page 319 SAM3X8ERT

25.0 STATIC MEMORY CONTROLLER (SMC)

25.1 Description

The External Bus Interface is designed to ensure the successful data transfer between several external devices and the Cortex-M3 based device. The External Bus Interface of the SAM3X8ERT consists of a Static Memory Controller (SMC). This SMC is capable of handling several types of external memory and peripheral devices, such as SRAM, PSRAM, PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash. The SMC generates the signals that control the access to external memory devices or peripheral devices. It has 8 Chip Selects and a 24-bit address bus. The 16-bit data bus can be configured to interface with 8- or 16-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal wave- forms are fully parametrizable. The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with an automatic slow clock mode. In slow clock mode, it switches from user-programmed waveforms to slow-rate specific waveforms on read and write signals. The SMC embeds a NAND Flash Controller (NFC). The NFC can handle automatic transfers, sending the commands and address cycles to the NAND Flash and transferring the contents of the page (for read and write) to the NFC SRAM. It minimizes the CPU overhead. The SMC includes programmable hardware error correcting code with one bit error correction capability and supports two bits error detection. In order to improve overall system performance the DATA phase of the transfer can be DMA assisted. The External Data Bus can be scrambled/unscrambled by means of user keys.

25.2 Embedded Characteristics

• 16-Mbyte Address Space per Chip Select
• 8- or 16-bit Data Bus
• Word, Halfword, Byte Transfers
• Byte Write or Byte Select Lines
• Programmable Setup, Pulse and Hold Time for Read Signals per Chip Select
• Programmable Setup, Pulse and Hold Time for Write Signals per Chip Select
• Programmable Data Float Time per Chip Select
• External Data Bus Scrambling/Unscrambling Function
• External Wait Request
• Automatic Switch to Slow Clock Mode
• NAND Flash Controller Supporting NAND Flash with Multiplexed Data/Address Buses
• Supports SLC NAND Flash Technology
• Hardware Configurable Number of Chip Selects from 1 to 8
• Programmable Timing on a per Chip Select Basis
• AHB Slave Interface
• Microchip APB Configuration Interface
• Programmable Flash Data Width 8 Bits or 16 Bits
• Supports Hardware Error Correcting Code (ECC), 1-bit Error Correction, 2-bit Error Detection
• Detection and Correction by Software
• Supports NAND Flash and SmartMedia™ Devices with 8- or 16-bit Data Path
• Supports NAND Flash/SmartMedia with Page Sizes of 528, 1056, 2112 and 4224 Bytes, Specified by Software
• Supports 1-bit Correction for a Page of 512, 1024, 2048 and 4096 Bytes with 8- or 16-bit Data Path
• Supports 1-bit Correction per 512 Bytes of Data for a Page Size of 512, 2048 and 4096 Bytes with 8-bit Data Path
• Supports 1-bit Correction per 256 Bytes of Data for a Page Size of 512, 2048 and 4096 Bytes with 8-bit Data Path

DS60001614B-page 320  2020 Microchip Technology Inc.

25.3 Block Diagram

FIGURE 25-1: BLOCK DIAGRAM

25.4 I/O Lines Description

TABLE 25-1: I/O LINE DESCRIPTION Name Description Type Active Level NCS[3:0] Static Memory Controller Chip Select Lines Output Low NRD Read Signal Output Low NWR0/NWE Write 0/Write Enable Signal Output Low A0/NBS0 Address Bit 0/Byte 0 Select Signal Output Low NWR1/NBS1 Write 1/Byte 1 Select Signal Output Low A1 Address Bit 1 Output Low A[23:2] Address Bus Output — D[15:0] Data Bus I/O — NWAIT External Wait Signal Input Low NANDRDY NAND Flash Ready/Busy Input — NANDWE NAND Flash Write Enable Output Low NANDOE NAND Flash Output Enable Output Low NANDALE NAND Flash Address Latch Enable Output — NANDCLE NAND Flash Command Latch Enable Output — SMC Interface NANDRDY D[15:0] NFC Internal SRAM NAND Flash Controller (NFC) ECC NWR0/NWE NCS[3:0] NWAIT NANDOE NANDWE A23 NRD A[0]/NBS0 A[20:1] NWR1/NBS1 A21/NANDALE A22/NANDCLE Control & Status Registers SRAM AHB Interface AHB arbiter Scrambler SMC AHB Interface (4 K bytes) User Interface

 2020 Microchip Technology Inc. DS60001614B-page 321 SAM3X8ERT

25.5 Multiplexed Signals

25.6 Application Example

25.6.1 IMPLEMENTATION EXAMPLES

For Hardware implementation examples, refer to ATSAM3X-EK schematics which show examples of connection to an LCD module, PSRAM and NAND Flash.

25.6.2 HARDWARE INTERFACE

FIGURE 25-2: SMC CONNECTIONS TO STATIC MEMORY DEVICES

25.7 Product Dependencies

25.7.1 I/O LINES

The pins used for interfacing the Static Memory Controller are multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the Static Memory Controller pins to their peripheral function. If I/O Lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller.

25.7.2 POWER MANAGEMENT

The SMC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SMC clock. TABLE 25-2: STATIC MEMORY CONTROLLER (SMC) MULTIPLEXED SIGNALS Multiplexed Signals Related Function NWR0 NWE Byte-write or byte-select access, see Figure 25-4 and Figure 25-5 A0 NBS0 8-bit or 16-bit data bus, see “Data Bus Width” on page 323 A22 NANDCLE NAND Flash Command Latch Enable A21 NANDALE NAND Flash Address Latch Enable NWR1 NBS1 Byte-write or byte-select access, see Figure 25-4 and Figure 25-5 A1 – 8-/16-bit data bus, see “Data Bus Width” on page 323 Byte-write or byte-select access, see Figure 25-4 and Figure 25-5 Static Memory Controller D0-D15 A2 - A23 A0/NBS0 NWR0/NWE NWR1/NBS1 128K x 8 SRAM D0 - D7 A0 - A16 OE WE CS D0 - D7 D8-D15 A2 - A18 128K x 8 SRAM D0-D7 CS NWR1/NBS1 NRD NWR0/NWE NCS0 NCS1 NCS2 NCS3 NCS4 NCS5 NCS6 NCS7 NRD OE WE A2 - A18A0 - A16

DS60001614B-page 322  2020 Microchip Technology Inc.

25.7.3 INTERRUPT

The SMC has an interrupt line connected to the Nested Vector Interrupt Controller (NVIC). Handling the SMC interrupt requires programming the NVIC before configuring the SMC.

25.8 External Memory Mapping

Note 1: See “NFC Control Registers” on page 347, i.e., CMD_ADDR description. The SMC provides up to 24 address lines, A[23:0]. This allows each chip select line to address up to 16 Mbytes of mem- ory. If the physical memory device connected on one chip select is smaller than 16 Mbytes, it wraps around and appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see Figure 25-3). A[23:0] is only significant for 8-bit memory, A[23:1] is used for 16-bit memory. FIGURE 25-3: MEMORY CONNECTIONS FOR EXTERNAL DEVICES TABLE 25-3: PERIPHERAL IDS Instance ID SMC 9 TABLE 25-4: EXTERNAL MEMORY MAPPING Address Use Access 0x60000000-0x60FFFFFF Chip Select 0 (16 MB) Read-write 0x61000000-0x61FFFFFF Chip Select 1 Read-write 0x62000000-0x62FFFFFF Chip Select 2 Read-write 0x63000000-0x63FFFFFF Chip Select 3 Read-write 0x64000000-0x64FFFFFF Chip Select 4 Read-write 0x65000000-0x65FFFFFF Chip Select 5 Read-write 0x66000000-0x66FFFFFF Chip Select 6 Read-write 0x67000000-0x67FFFFFF Chip Select 7 Read-write 0x68000000-0x6FFFFFFF NFC Command Registers(1) Read-write NRD NWE A[23:0] D[15:0] 8 or 16 Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Output Enable Write Enable A[25:0] D[15:0] or D[7:0] NCS3 NCS0 NCS1 NCS2 NCS7 NCS4 NCS5 NCS6 NCS[0] - NCS[7] SMC

 2020 Microchip Technology Inc. DS60001614B-page 323 SAM3X8ERT

25.9 Connection to External Devices

25.9.1 DATA BUS WIDTH

A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by the field DBW in SMC_- MODE (Mode Register) for the corresponding chip select. Figure 25-4 shows how to connect a 512K x 8-bit memory on NCS2. Figure 25-5 shows how to connect a 512K x 16- bit memory on NCS2.

25.9.2 BYTE WRITE OR BYTE SELECT ACCESS

Each chip select with a 16-bit data bus can operate with one of two different types of write access: byte write or byte select access. This is controlled by the BAT field of the SMC_MODE register for the corresponding chip select. FIGURE 25-4: MEMORY CONNECTION FOR AN 8-BIT DATA BUS FIGURE 25-5: MEMORY CONNECTION FOR A 16-BIT DATA BUS

25.9.2.1 Byte Write Access

Byte write access supports one byte write signal per byte of the data bus and a single read signal. Note: SMC does not allow boot in Byte Write Access mode.

• For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively, byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided. Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory.

25.9.2.2 Byte Select Access

In this mode, read/write operations can be enabled/disabled at byte level. One byte-select line per byte of the data bus is provided. One NRD and one NWE signal control read and write.

• For 16-bit devices: the SMC provides NBS0 and NBS1 selection signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. Byte Select Access is used to connect one 16-bit device. SMC NWE NRD NCS[2] Write Enable Output Enable Memory Enable D[7:0] D[7:0] A[18:2]A[18:2] A1 A1 SMC NBS0 NWE NRD NCS[2] Low Byte Enable Write Enable Output Enable Memory Enable NBS1 High Byte Enable D[15:0] D[15:0] A[19:2] A[18:1] A[0]A1

DS60001614B-page 324  2020 Microchip Technology Inc. FIGURE 25-6: CONNECTION OF 2 X 8-BIT DEVICES ON A 16-BIT BUS: BYTE WRITE OPTION

25.9.2.3 Signal Multiplexing

Depending on the byte access type (BAT), only the write signals or the byte select signals are used. To save IOs at the external bus interface, control signals at the SMC interface are multiplexed. Table 25-5 shows signal multiplexing depending on the data bus width and the byte access type. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 is unused. When Byte Write option is selected, NBS0 is unused. TABLE 25-5: SMC MULTIPLEXED SIGNAL TRANSLATION Signal Name 16-bit Bus 8-bit Bus Device Type 1x16-bit 2 x 8-bit 1 x 8-bit Byte Access Type (BAT) Byte Select Byte Write NBS0_A0 NBS0 A0 NWE_NWR0 NWE NWR0 NWE NBS1_NWR1 NBS1 NWR1 A1 A1 A1 A1 SMC A1 NWR0 NRD NCS[3] Write Enable Read Enable Memory Enable NWR1 Write Enable Read Enable Memory Enable D[7:0] D[7:0] D[15:8] D[15:8] A[24:2] A[23:1] A[23:1] A[0] A[0]

 2020 Microchip Technology Inc. DS60001614B-page 325 SAM3X8ERT

25.10 Standard Read and Write Protocols

In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS1) always have the same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the byte write lines (NWR0 to NWR1) in byte write access type. NWR0 to NWR3 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..7] chip select lines.

25.10.1 READ WAVEFORMS

The read cycle is shown on Figure 25-7. The read cycle starts with the address setting on the memory address bus, i.e.: {A[23:2], A1, A0} for 8-bit devices {A[23:2], A1} for 16-bit devices FIGURE 25-7: STANDARD READ CYCLE

25.10.1.1 NRD Waveform

The NRD signal is characterized by a setup timing, a pulse width and a hold timing. 1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge. 2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge. 3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge. A[23:2] NBS0,NBS1, A0, A1 NCS NRD_SETUP NRD_PULSE NRD_HOLD MCK NRD D[15:0] NCS_RD_SETUP NCS_RD_PULSE NCS_RD_HOLD NRD_CYCLE

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25.10.1.2 NCS Waveform

Similarly, the NCS signal can be divided into a setup time, pulse length and hold time: 1. NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_RD_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge. 3. NCS_RD_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge.

25.10.1.3 Read Cycle

The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. The total read cycle time is equal to: NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD = NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the NRD and NCS timings are coherent, the user must define the total read cycle instead of the hold timing. NRD_CYCLE implicitly defines the NRD hold time and NCS hold time as: NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE

25.10.2 READ MODE

As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is available on the data bus. The SMC does not compare NCS and NRD timings to know which signal rises first. The READ_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal of NRD and NCS controls the read operation.

25.10.2.1 Read is Controlled by NRD (READ_MODE = 1):

Figure 25-8 shows the waveforms of a read operation of a typical asynchronous RAM. The read data is available tPACC after the falling edge of NRD, and turns to ‘Z’ after the rising edge of NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD, whatever the programmed waveform of NCS may be. FIGURE 25-8: READ_MODE = 1: DATA IS SAMPLED BY SMC BEFORE THE RISING EDGE OF NRD Data Sampling tPACC MCK A[23:2] NBS0,NBS1, A0, A1 NCS NRD D[15:0]

 2020 Microchip Technology Inc. DS60001614B-page 327 SAM3X8ERT

25.10.2.2 Read is Controlled by NCS (READ_MODE = 0)

Figure 25-9 shows the typical read cycle. The read data is valid tPACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised. In that case, the READ_MODE must be set to 0 (read is controlled by NCS): the SMC internally samples the data on the rising edge of Master Clock that gen - erates the rising edge of NCS, whatever the programmed waveform of NRD may be. FIGURE 25-9: READ_MODE = 0: DATA IS SAMPLED BY SMC BEFORE THE RISING EDGE OF NCS Data Sampling tPACC MCK D[15:0] A[23:2] NBS0,NBS1, A0, A1 NCS NRD

DS60001614B-page 328  2020 Microchip Technology Inc.

25.10.3 WRITE WAVEFORMS

The write protocol is similar to the read protocol. It is depicted in Figure 25-10. The write cycle starts with the address setting on the memory address bus.

25.10.3.1 NWE Waveforms

The NWE signal is characterized by a setup timing, a pulse width and a hold timing. 1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before the NWE falling edge. 2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE rising edge. 3. NWE_HOLD: The NWE hold time is defined as the hold time of address and data after the NWE rising edge. The NWE waveforms apply to all byte-write lines in Byte Write access mode: NWR0 to NWR3.

25.10.3.2 NCS Waveforms

The NCS signal waveforms in write operation are not the same as those applied in read operations, but are separately defined: 1. NCS_WR_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_WR_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge. 3. NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. FIGURE 25-10: WRITE CYCLE

25.10.3.3 Write Cycle

The write cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. The total write cycle time is equal to: NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD = NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the NWE and NCS timings are coherent, the user must define the total write cycle instead of the hold timing. This implicitly defines the NWE hold time and NCS (write) hold times as: NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE A[23:2] NBS0, NBS1, A0, A1 NCS NWE_SETUP NWE_PULSE NWE_HOLD MCK NWE NCS_WR_SETUP NCS_WR_PULSE NCS_WR_HOLD NWE_CYCLE

 2020 Microchip Technology Inc. DS60001614B-page 329 SAM3X8ERT NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE

25.10.4 WRITE MODE

The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal con- trols the write operation.

25.10.4.1 Write is Controlled by NWE (WRITE_MODE = 1)

Figure 25-11 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is put on the bus during the pulse and hold steps of the NWE signal. The internal data buffers are turned out after the NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS. FIGURE 25-11: WRITE_MODE = 1. THE WRITE OPERATION IS CONTROLLED BY NWE

25.10.4.2 Write is Controlled by NCS (WRITE_MODE = 0)

Figure 25-12 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. FIGURE 25-12: WRITE_MODE = 0. THE WRITE OPERATION IS CONTROLLED BY NCS MCK D[15:0] NCS A[23:2] NBS0, NBS1, A0, A1 NWE, NWR0, NWR1 MCK D[15:0] NCS NWE, NWR0, NWR1 A[23:2] NBS0, NBS1, A0, A1

DS60001614B-page 330  2020 Microchip Technology Inc.

25.10.5 CODING TIMING PARAMETERS

All timing parameters are defined for one chip select and are grouped together in one SMC_REGISTER according to their type.

• The SMC_SETUP register groups the definition of all setup parameters: NRD_SETUP , NCS_RD_SETUP, NWE_- SETUP , NCS_WR_SETUP
• The SMC_PULSE register groups the definition of all pulse parameters: NRD_PULSE, NCS_RD_PULSE, NWE_- PULSE, NCS_WR_PULSE
• The SMC_CYCLE register groups the definition of all cycle parameters: NRD_CYCLE, NWE_CYCLE Table 25-6 shows how the timing parameters are coded and their permitted range.

25.10.6 RESET VALUES OF TIMING PARAMETERS

Table 25-7 gives the default value of timing parameters at reset.

25.10.7 USAGE RESTRICTION

The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE parameters is larger than the corresponding CYCLE parameter, this leads to unpredictable behavior of the SMC.

25.10.7.1 For Read Operations

Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the memory interface because of the propagation delay of theses signals through external logic and pads. If positive setup and hold values must be verified, then it is strictly recommended to program non-null values so as to cover possible skews between address, NCS and NRD signals.

25.10.7.2 For Write Operations

If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address, byte select lines, and NCS signal after the rising edge of NWE. This is true for WRITE_MODE = 1 only. See “Early Read Wait State” on page 332. For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior. In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For external devices that require setup and hold time between NCS and NRD signals (read), or between NCS and NWE signals (write), these setup and hold times must be converted into setup and hold times in reference to the address bus. TABLE 25-6: CODING AND RANGE OF TIMING PARAMETERS Coded Value Number of Bits Effective Value Permitted Range Coded Value Effective Value setup [5:0] 6 128 x setup[5] + setup[4:0] 0   31 128   128+31 pulse [6:0] 7 256 x pulse[6] + pulse[5:0] 0   63 256   256+63 cycle [8:0] 9 256 x cycle[8:7] + cycle[6:0] 0   127 256   256+127 512   512+127 768   768+127 TABLE 25-7: RESET VALUES OF TIMING PARAMETERS Register Reset Value Description SMC_SETUP 0x01010101 All setup timings are set to 1 SMC_PULSE 0x01010101 All pulse timings are set to 1 SMC_CYCLE 0x00030003 The read and write operation last 3 Master Clock cycles and provide one hold cycle WRITE_MODE 1 Write is controlled with NWE READ_MODE 1 Read is controlled with NRD

 2020 Microchip Technology Inc. DS60001614B-page 331 SAM3X8ERT

25.11 Scrambling/Unscrambling Function

The external data bus D[15:0] can be scrambled in order to prevent intellectual property data located in off-chip mem - ories from being easily recovered by analyzing data at the package pin level of either microcontroller or memory device. The scrambling and unscrambling are performed on-the-fly without additional wait states. The scrambling method depends on two user-configurable key registers, SMC_KEY1 and SMC_KEY2. These key reg- isters are only accessible in write mode. The key must be securely stored in a reliable non-volatile memory in order to recover data from the off-chip memory. Any data scrambled with a given key cannot be recovered if the key is lost. The scrambling/unscrambling function can be enabled or disabled by programming the SMC_OCMS register. One bit is dedicated to enable/disable NAND Flash scrambling and one bit is dedicated enable/disable scrambling the off chip SRAM. When at least one external SRAM is scrambled, the SMSC field must be set in the SMC_OCMS register. When multiple chip selects (external SRAM) are handled, it is possible to configure the scrambling function per chip select using the OCMS field in the SMC_TIMINGS registers. To scramble the NAND Flash contents, the SRSE field must be set in the SMC_OCMS register. When NAND Flash memory content is scrambled, the on-chip SRAM page buffer associated for the transfer is also scrambled.

25.12 Automatic Wait States

Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or operation conflict.

25.12.1 CHIP SELECT WAIT STATES

The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one. During chip select wait state, all control lines are turned inactive: NBS0 to NBS1, NWR0 to NWR1, NCS[0..7], NRD lines are all set to 1. Figure 25-13 illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2.

DS60001614B-page 332  2020 Microchip Technology Inc. FIGURE 25-13: CHIP SELECT WAIT STATE BETWEEN A READ ACCESS ON NCS0 AND A WRITE ACCESS ON NCS2

25.12.2 EARLY READ WAIT STATE

In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state. The early read cycle thus only occurs between a write and read access to the same memory device (same chip select). An early read wait state is automatically inserted if at least one of the following conditions is valid:

• if the write controlling signal has no hold time and the read controlling signal has no setup time (Figure 25-14).
• in NCS write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS signal and the NCS_RD_SETUP parameter is set to 0, regardless of the read mode (Figure 25-15). The write operation must end with a NCS rising edge. Without an Early Read Wait State, the write operation could not complete properly.
• in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD = 0), the feedback of the write control signal is used to control address, data, chip select and byte select lines. If the external write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address, data and control signals are maintained one more cycle. See Figure 25-16. A[23:2] NBS0, NBS1, A0,A1 NCS0 NRD_CYCLE Chip Select Wait State NWE_CYCLE MCK NCS2 NRD NWE D[15:0] Read to Write Wait State

DS60001614B-page 334  2020 Microchip Technology Inc. FIGURE 25-16: EARLY READ WAIT STATE: NWE-CONTROLLED WRITE WITH NO HOLD FOLLOWED BY A READ WITH ONE SET-UP CYCLE

25.12.3 RELOAD USER CONFIGURATION WAIT STATE

The user may change any of the configuration parameters by writing the SMC user interface. When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state before starting the next access. The so called “Reload User Configuration Wait State” is used by the SMC to load the new set of parameters to apply to next accesses. The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State. If accesses before and after re-programming the user interface are made to different devices (Chip Selects), then one single Chip Select Wait State is applied. On the other hand, if accesses before and after writing the user interface are made to the same device, a Reload Con- figuration Wait State is inserted, even if the change does not concern the current Chip Select.

25.12.3.1 User Procedure

To insert a Reload Configuration Wait State, the SMC detects a write access to any SMC_MODE register of the user interface. If only the timing registers are modified (SMC_SETUP , SMC_PULSE, SMC_CYCLE registers) in the user interface, the user must validate the modification by writing the SMC_MODE register, even if no change was made on the mode parameters.

25.12.3.2 Slow Clock Mode Transition

A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the current transfer (see “Slow Clock Mode” on page 345).

25.12.4 READ TO WRITE WAIT STATE

Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred to as a read to write wait state in this document. This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted. See Figure 25-13. A[23:2] NBS0, NBS1, A0, A1 write cycle (WRITE_MODE = 1) Early Read wait state MCK NRD internal write controlling signal external write controlling signal (NWE) D[15:0] read cycle (READ_MODE = 0 or READ_MODE = 1) no hold read setup = 1

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25.13 Data Float Wait States

Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data float wait states) after a read access:

• before starting a read access to a different external memory,
• before starting a write access to the same device or to a different external one. The Data Float Output Time (t DF) for each external memory device is programmed in the TDF_CYCLES field of the SMC_MODE register for the corresponding chip select. The value of TDF_CYCLES indicates the number of data float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed for the data output to go to high impedance after the memory is disabled. Data float wait states do not delay internal memory accesses. Hence, a single access to an external memory with long tDF will not slow down the execution of a program from internal memory. The data float wait states management depends on the READ_MODE and the TDF_MODE fields of the SMC_MODE register for the corresponding chip select.

25.13.1 READ_MODE

Setting READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turning off the tri-state buffers of the external memory device. The Data Float Period then begins after the rising edge of the NRD signal and lasts TDF_- CYCLES MCK cycles. When the read operation is controlled by the NCS signal (READ_MODE = 0), the TDF field gives the number of MCK cycles during which the data bus remains busy after the rising edge of NCS. Figure 25-17 illustrates the Data Float Period in NRD-controlled mode (READ_MODE =1), assuming a data float period of 2 cycles (TDF_CYCLES = 2). Figure 25-18 shows the read operation when controlled by NCS (READ_MODE = 0) and the TDF_CYCLES parameter equals 3. FIGURE 25-17: TDF PERIOD IN NRD CONTROLLED READ ACCESS (TDF = 2) NBS0, NBS1, A0, A1 NCS NRD controlled read operation tpacc MCK NRD D[15:0] TDF = 2 clock cycles A[23:2]

DS60001614B-page 336  2020 Microchip Technology Inc. FIGURE 25-18: TDF PERIOD IN NCS CONTROLLED READ OPERATION (TDF = 3)

25.13.2 TDF OPTIMIZATION ENABLED (TDF_MODE = 1)

When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. Figure 25-19 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0. Chip Select 0 has been programmed with: NRD_HOLD = 4; READ_MODE = 1 (NRD controlled) NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled) TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled). NCS TDF = 3 clock cycles tpacc MCK D[15:0] NCS controlled read operation A[23:2] NBS0, NBS1, A0,A1 NRD

 2020 Microchip Technology Inc. DS60001614B-page 337 SAM3X8ERT FIGURE 25-19: TDF OPTIMIZATION: NO TDF WAIT STATES ARE INSERTED IF THE TDF PERIOD IS OVER WHEN THE NEXT ACCESS BEGINS

25.13.3 TDF OPTIMIZATION DISABLED (TDF_MODE = 0)

When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float period ends when the second access begins. If the hold period of the read1 controlling signal overlaps the data float period, no additional tdf wait states will be inserted. Figure 25-20, Figure 25-21, and Figure 25-22 illustrate the cases:

• read access followed by a read access on another chip select,
• read access followed by a write access on another chip select,
• read access followed by a write access on the same chip select, with no TDF optimization. K D E Read to Write Wait State TDF_CYCLES = 6 read access on NCS0 (NRD controlled) NRD_HOLD= 4 NWE_SETUP= 3 write access on NCS0 (NWE controlled)

DS60001614B-page 338  2020 Microchip Technology Inc. FIGURE 25-20: TDF OPTIMIZATION DISABLED (TDF MODE = 0). TDF WAIT STATES BETWEEN

2 READ ACCESSES ON DIFFERENT CHIP SELECTS

FIGURE 25-21: TDF MODE = 0: TDF WAIT STATES BETWEEN A READ AND A WRITE ACCESS ON DIFFERENT CHIP SELECTS TDF_CYCLES = 6 TDF_CYCLES = 6 TDF_MODE = 0 (optimization disabled) A[23:2] read1 cycle Chip Select Wait State MCK read1 controlling signal (NRD) read2 controlling signal (NRD) D[15:0] read1 hold = 1 read 2 cycle read2 setup = 1

5 TDF WAIT STATES

NBS0, NBS1, A0, A1 TDF_CYCLES = 4 TDF_CYCLES = 4 TDF_MODE = 0 (optimization disabled) A[23:2] read1 cycle Chip Select Wait State Read to Write Wait State MCK read1 controlling signal (NRD) write2 controlling signal (NWE) D[15:0] read1 hold = 1 write2 cycle write2 setup = 1

2 TDF WAIT STATES

NBS0, NBS1, A0, A1

 2020 Microchip Technology Inc. DS60001614B-page 339 SAM3X8ERT FIGURE 25-22: TDF MODE = 0: TDF WAIT STATES BETWEEN READ AND WRITE ACCESSES ON THE SAME CHIP SELECT

25.14 External Wait

Any access can be extended by an external device using the NWAIT input signal of the SMC. The EXNW_MODE field of the SMC_MODE register on the corresponding chip select must be set to either to “10” (frozen mode) or “11” (ready mode). When the EXNW_MODE is set to “00” (disabled), the NWAIT signal is simply ignored on the corresponding chip select. The NWAIT signal delays the read or write operation in regards to the read or write controlling signal, depending on the read and write modes of the corresponding chip select.

25.14.1 RESTRICTION

When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold cycle for the read/write con - trolling signal. For that reason, the NWAIT signal cannot be used in Slow Clock Mode (“Slow Clock Mode” on page 345). The NWAIT signal is assumed to be a response of the external device to the read/write request of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write controlling signal. The assertion of the NWAIT signal outside the expected period has no impact on SMC behavior.

25.14.2 FROZEN MODE

When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resyn- chronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See Figure 25-23. This mode must be selected when the external device uses the NWAIT signal to delay the access and to freeze the SMC. The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure 25-24. TDF_CYCLES = 5 TDF_CYCLES = 5 TDF_MODE = 0 (optimization disabled) A[23:2] read1 cycle Read to Write Wait State MCK read1 controlling signal (NRD) write2 controlling signal (NWE) D[15:0] read1 hold = 1 write2 cycle write2 setup = 1

4 TDF WAIT STATES

NBS0, NBS1, A0, A1

DS60001614B-page 340  2020 Microchip Technology Inc. FIGURE 25-23: WRITE ACCESS WITH NWAIT ASSERTION IN FROZEN MODE (EXNW_MODE = 10) EXNW_MODE = 10 (Frozen) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 A[23:2] MCK NWE NCS 43 2 1 1 10 1 4563 2 2 2 2 1 0 Write cycle D[15:0] NWAIT FROZEN STATE NBS0, NBS1, A0,A1 Internally synchronized NWAIT signal

 2020 Microchip Technology Inc. DS60001614B-page 341 SAM3X8ERT FIGURE 25-24: READ ACCESS WITH NWAIT ASSERTION IN FROZEN MODE (EXNW_MODE = 10) EXNW_MODE = 10 (Frozen) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 2, NRD_HOLD = 6 NCS_RD_PULSE =5, NCS_RD_HOLD =3 A[23:2] MCK NCS NRD 55 5 22 0 21 0 21 0 Read cycle Assertion is ignored NWAIT synchronized NWAIT signal FROZEN STATE NBS0, NBS1, A0,A1

DS60001614B-page 342  2020 Microchip Technology Inc.

25.14.3 READY MODE

In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resyn- chronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 25-25 and Figure 25-26. After deassertion, the access is completed: the hold step of the access is performed. This mode must be selected when the external device uses deassertion of the NWAIT signal to indicate its ability to complete the read or write operation. If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling read/write signal, it has no impact on the access length as shown in Figure 25-26. FIGURE 25-25: NWAIT ASSERTION IN WRITE ACCESS: READY MODE (EXNW_MODE = 11) EXNW_MODE = 11 (Ready mode) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 A[23:2] MCK NWE NCS 43 2 1 0 0 0 4563 2 1 1 1 0 Write cycle D[15:0] NWAIT y synchronized NWAIT signal Wait STATE NBS0, NBS1, A0,A1

 2020 Microchip Technology Inc. DS60001614B-page 343 SAM3X8ERT FIGURE 25-26: NWAIT ASSERTION IN READ ACCESS: READY MODE (EXNW_MODE = 11) EXNW_MODE = 11(Ready mode) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 7 NCS_RD_PULSE =7 A[23:2] MCK NCS NRD 4563 2 0 0 4563 2 1 1 Read cycle Assertion is ignored NWAIT y synchronized NWAIT signal Wait STATE Assertion is NBS0, NBS1, A0,A1

DS60001614B-page 344  2020 Microchip Technology Inc.

25.14.4 NWAIT LATENCY AND READ/WRITE TIMINGS

There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated on Figure 25-27. When EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the read and write controlling signal of at least: minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle FIGURE 25-27: NWAIT LATENCY EXNW_MODE = 10 or 11 READ_MODE = 1 (NRD_controlled) NRD_PULSE = 5 A[23:2] MCK NRD 43 21 0 0 0 Read cycle minimal pulse length NWAIT latency NWAIT ly synchronized NWAIT signal WAIT STATE 2 cycle resynchronization NBS0, NBS1, A0,A1

 2020 Microchip Technology Inc. DS60001614B-page 345 SAM3X8ERT

25.15 Slow Clock Mode

The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32 kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate. When activated, the slow mode is active on all chip selects.

25.15.1 SLOW CLOCK MODE WAVEFORMS

Figure 25-28 illustrates the read and write operations in slow clock mode. They are valid on all chip selects. Table 25-8 indicates the value of read and write parameters in slow clock mode. FIGURE 25-28: READ/WRITE CYCLES IN SLOW CLOCK MODE

25.15.2 SWITCHING FROM (TO) SLOW CLOCK MODE TO (FROM) NORMAL MODE

When switching from slow clock mode to normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters. See Figure 25-29. The external device may not be fast enough to support such timings. Figure 25-30 illustrates the recommended procedure to properly switch from one mode to the other. TABLE 25-8: READ AND WRITE TIMING PARAMETERS IN SLOW CLOCK MODE Read Parameters Duration (cycles) Write Parameters Duration (cycles) NRD_SETUP 1 NWE_SETUP 1 NRD_PULSE 1 NWE_PULSE 1 NCS_RD_SETUP 0 NCS_WR_SETUP 0 NCS_RD_PULSE 2 NCS_WR_PULSE 3 NRD_CYCLE 2 NWE_CYCLE 3 A[23:2] NCS MCK NWE 1 NWE_CYCLE = 3 A[23:2] MCK NRD NRD_CYCLE = 2 NCS SLOW CLOCK MODE WRITE SLOW CLOCK MODE READ BS0, NBS1, A0,A1 NBS0, NBS1, A0,A1

 2020 Microchip Technology Inc. DS60001614B-page 347 SAM3X8ERT

25.16 NAND Flash Controller Operations

25.16.1 NFC OVERVIEW

The NFC can handle automatic transfers, sending the commands and address to the NAND Flash and transferring the contents of the page (for read and write) to the NFC SRAM. It minimizes the CPU overhead.

25.16.2 NFC CONTROL REGISTERS

NAND Flash Read and NAND Flash Program operations can be performed through the NFC Command Registers. In order to minimize CPU intervention and latency, commands are posted in a command buffer. This buffer provides zero wait state latency. The detailed description of the command encoding scheme is explained below. The NFC handles automatic transfer between the external NAND Flash and the chip via the NFC SRAM. It is done via NFC Command Registers. The NFC Command Registers are very efficient to use. When writing to these registers:

• the address of the register (NFCADDR_CMD) contains the command used,
• the data of the register (NFCDATA_ADDT) contains the address to be sent to the NAND Flash. So, in one single access the command is sent and immediately executed by the NFC. Even two commands can be pro- gramed within a single access (CMD1, CMD2) depending on the VCMD2 value. The NFC can send up to 5 Address cycles. Figure 25-31 below shows a typical NAND Flash Page Read Command of a NAND Flash Memory and correspondence with NFC Address Command Register. FIGURE 25-31: NFC/NAND FLASH ACCESS EXAMPLE For more details refer to “NFC Address Command” on page 349. The NFC Command Registers can be found at address 0x68000000 - 0x6FFFFFFF. (See Table 25-4.) Reading the NFC command register (to any address) will give the status of the NFC. Especially useful to know if the NFC is busy, for example. 25.16.2.1 Building NFC Address Command Example. The base address is made of address 0x60000000 + NFCCMD bit set = 0x68000000. Page read operation example: // Build the Address Command (NFCADDR_CMD) AddressCommand = (0x60000000 | NFCCMD=1 | // NFC Command Enable NFCWR=0 |// NFC Read Data from NAND Flash NFCEN=1 | // NFC Enable. CSID=1 | // Chip Select ID = 1 ACYCLE= 5 | // Number of address cycle. VCMD2=1 | // CMD2 is sent after Address Cycles CMD2=0x30 | // CMD2 = 30h CMD1=0x0) // CMD1 = Read Command = 00h Depends on ACYCLE value CMD1 ADD cycles (0 to 5) CMD2 If VCMD2 = 1 00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 30h Column Address Row Address

DS60001614B-page 348  2020 Microchip Technology Inc. // Set the Address for Cycle 0 SMC_ADDR = Col. Add1 // Write command with the Address Command built above *AddressCommand = (Col. Add2 |// ADDR_CYCLE1 Row Add1 | // ADDR_CYCLE2 Row Add2 |// ADDR_CYCLE3 Row Add3 )// ADDR_CYCLE4

 2020 Microchip Technology Inc. DS60001614B-page 349 SAM3X8ERT

25.16.2.2 NFC Address Command

Name: NFCADDR_CMD Access: Read-write Reset: 0x00000000

• CMD1: Command Register Value for Cycle 1 If NFCCMD is set, when a read or write access occurs, the NFC sends this command.
• CMD2: Command Register Value for Cycle 2 If NFCCMD and VCMD2 field are set to one, the NFC sends this command after CMD1.
• VCMD2: Valid Cycle 2 Command When set to true, the CMD2 field is issued after addressing cycle.
• ACYCLE: Number of Address required for the current command When ACYCLE field is different from zero, ACYCLE Address cycles are performed after Command Cycle 1. The max- imum number of cycles is 5.
• CSID: Chip Select Identifier Chip select used
• NFCEN: NFC Enable When set to true, the NFC will automatically read or write data after the command.
• NFCWR: NFC Write Enable 0: The NFC reads data from the NAND Flash. 1: The NFC writes data into the NAND Flash.
• NFCCMD: NFC Command Enable If set to true, CMD indicates that the NFC shall execute the command encoded in the NFCADDR_CMD. 31 30 29 28 27 26 25 24 — — — — NFCCMD NFCWR NFCEN CSID 23 22 21 20 19 18 17 16 CSID ACYCLE VCMD2 CMD2 15 14 13 12 11 10 9 8 CMD2 CMD1 7 6 5 4 3 2 1 0 CMD1 — —

DS60001614B-page 350  2020 Microchip Technology Inc.

25.16.2.3 NFC Data Address

Name: NFCDATA_ADDT Access: Write Reset: 0x00000000

• ADDR_CYCLE1: NAND Flash Array Address Cycle 1 When less than 5 address cycles are used ADDR_CYCLE1 is the first byte written to NAND Flash When 5 address cycles are used ADDR_CYCLE1 is the second byte written to NAND Flash
• ADDR_CYCLE2: NAND Flash Array Address Cycle 2 When less than 5 address cycles are used ADDR_CYCLE2 is the second byte written to NAND Flash When 5 address cycles are used ADDR_CYCLE2 is the third byte written to NAND Flash
• ADDR_CYCLE3: NAND Flash Array Address Cycle 3 When less than 5 address cycles are used ADDR_CYCLE3 is the third byte written to NAND Flash When 5 address cycles are used ADDR_CYCLE3 is the fourth byte written to NAND Flash
• ADDR_CYCLE4: NAND Flash Array Address Cycle 4 When less than 5 address cycles are used ADDR_CYCLE4 is the fourth byte written to NAND Flash When 5 address cycles are used ADDR_CYCLE4 is the fifth byte written to NAND Flash Note: If 5 address cycles are used, the first address cycle is ADDR_CYCLE0. Refer to SMC_ADDR register. 31 30 29 28 27 26 25 24 ADDR_CYCLE4 23 22 21 20 19 18 17 16 ADDR_CYCLE3 15 14 13 12 11 10 9 8 ADDR_CYCLE2 7 6 5 4 3 2 1 0 ADDR_CYCLE1

 2020 Microchip Technology Inc. DS60001614B-page 351 SAM3X8ERT

25.16.2.4 NFC DATA Status

Name: NFCDATA_Status Access: Read Reset: 0x00000000

• CMD1: Command Register Value for Cycle 1 When a Read or Write Access occurs, the Physical Memory Interface drives the IO bus with CMD1 field during the Com- mand Latch cycle 1.
• CMD2: Command Register Value for Cycle 2 When VCMD2 field is set to true, the Physical Memory Interface drives the IO bus with CMD2 field during the Command Latch cycle 2.
• VCMD2: Valid Cycle 2 Command When set to true, the CMD2 field is issued after addressing cycle.
• ACYCLE: Number of Address required for the current command When ACYCLE field is different from zero, ACYCLE Address cycles are performed after Command Cycle 1.
• CSID: Chip Select Identifier Chip select used
• NFCEN: NFC Enable When set to true, The NFC is enabled.
• NFCWR: NFC Write Enable 0: The NFC is in read mode. 1: The NFC is in write mode.
• NFCBUSY: NFC Busy Status Flag If set to true, it indicates that the NFC is busy.

25.16.3 NFC INITIALIZATION

Prior to any Command and Data Transfer, the SMC User Interface must be configured to meet the device timing require- ments.

• Write enable Configuration Use NWE_SETUP , NWE_PULSE and NWE_CYCLE to define the write enable waveform according to datasheet of the device. Use TADL field in the SMC_TIMINGS register to configure the timing between the last address latch cycle and the first rising edge of WEN for data input. 31 30 29 28 27 26 25 24 — — — — NFCBUSY NFCWR NFCEN CSID 23 22 21 20 19 18 17 16 CSID ACYCLE VCMD2 CMD2 15 14 13 12 11 10 9 8 CMD2 CMD1 7 6 5 4 3 2 1 0 CMD1 — —

DS60001614B-page 354  2020 Microchip Technology Inc.

25.16.3.1 NAND Flash Controller Timing Engine

When the NFC Command register is written, the NFC issues a NAND Flash Command and optionally performs a data transfer between the NFC SRAM and the NAND Flash device. The NAND Flash Controller Timing Engine guarantees valid NAND Flash timings, depending on the set of parameters decoded from the address bus. These timings are defined in the SMC_TIMINGS register. For information of the timing used depending on the command, see Figure 25-36: FIGURE 25-36: NAND FLASH CONTROLLER TIMING ENGINE See “NFC Address Command” on page 349 register description and “SMC Timings Register” on page 389. NFCEN=1 NFCWR =1 TADL =1 NFCEN=1 NFCWR=0 TWB != 0 NFCEN=0 VCMD2=1 TCLR != 0 !NFCEN=1 VCMD2=0 ACYCLE!=0 NFCWR=1 TADL != 0 !NFCEN=1 VCMD2=0 ACYCLE!=0 NFCWR=0 TAR != 0 !NFCEN=1 VCMD2=0 ACYCLE!=0 TCLR != 0 Wait TADL Wait TADL Wait TAR Wait TWB Wait TCLR Wait TCLR Timing Check Engine

 2020 Microchip Technology Inc. DS60001614B-page 355 SAM3X8ERT

25.16.4 NFC SRAM

25.16.4.1 NFC SRAM Mapping

If the NFC is used to read and write Data from and to the NAND Flash, the configuration depends on the page size. See Table 25-9and Table 25-10 for detailed mapping. The NFC SRAM size is 4 Kbytes. The NFC can handle NAND Flash with a page size of 4 Kbytes or of course lower size (such as 2 Kbytes for example). In the case of 2 Kbytes or lower page size, the NFC SRAM can be split into several banks. The SMC_BANK field enables to select the bank used. Note: A “ping-pong” mode (write or read to a bank while the NFC writes or reads to another bank) is not accessible with the NFC (using 2 different banks). If the NFC is not used, the NFC SRAM can be used as general purpose by the application. TABLE 25-9: NFC SRAM MAPPING WITH NAND FLASH PAGE SIZE OF 2 KBYTES + 64 BYTES Offset Use Access 0x00000000-0x000001FF Bank 0 Main Area Buffer 0 Read-write 0x00000200-0x000003FF Bank 0 Main Area Buffer 1 Read-write 0x00000400-0x000005FF Bank 0 Main Area Buffer 2 Read-write 0x00000600-0x000007FF Bank 0 Main Area Buffer 3 Read-write 0x00000800-0x0000080F Bank 0 Spare Area 0 Read-write 0x00000810-0x0000081F Bank 0 Spare Area 1 Read-write 0x00000820-0x0000082F Bank 0 Spare Area 2 Read-write 0x00000830-0x0000083F Bank 0 Spare Area 3 Read-write 0x00000840-0x00000A3F Bank 1 Main Area Buffer 0 Read-write 0x00000A40-0x00000C3F Bank 1 Main Area Buffer 1 Read-write 0x00000C40-0x00000E3F Bank 1 Main Area Buffer 2 Read-write 0x00000E40-0x0000103F Bank 1 Main Area Buffer 3 Read-write 0x00001040-0x0000104F Bank 1 Spare Area 0 Read-write 0x00001050-0x0000105F Bank 1 Spare Area 1 Read-write 0x00001060-0x0000106F Bank 1 Spare Area 2 Read-write 0x00001070-0x0000107F Bank 1 Spare Area 3 Read-write 0x00001080-0x00001FFF Reserved — TABLE 25-10: NFC SRAM MAPPING WITH NAND FLASH PAGE SIZE OF 4 KBYTES + 128 BYTES Offset Use Access 0x00000000-0x000001FF Bank 0 Main Area Buffer 0 Read-write 0x00000200-0x000003FF Bank 0 Main Area Buffer 1 Read-write 0x00000400-0x000005FF Bank 0 Main Area Buffer 2 Read-write 0x00000600-0x000007FF Bank 0 Main Area Buffer 3 Read-write 0x00000800-0x000009FF Bank 0 Main Area Buffer 4 Read-write 0x00000A00-0x00000BFF Bank 0 Main Area Buffer 5 Read-write 0x00000C00-0x00000DFF Bank 0 Main Area Buffer 6 Read-write 0x00000E00-0x00000FFF Bank 0 Main Area Buffer 7 Read-write 0x00001000-0x0000100F Bank 0 Spare Area 0 Read-write 0x00001010-0x0000101F Bank 0 Spare Area 1 Read-write 0x00001020-0x0000102F Bank 0 Spare Area 2 Read-write 0x00001030-0x0000103F Bank 0 Spare Area 3 Read-write 0x00001040-0x0000104F Bank 0 Spare Area 4 Read-write 0x00001050-0x0000105F Bank 0 Spare Area 5 Read-write 0x00001060-0x0000106F Bank 0 Spare Area 6 Read-write 0x00001070-0x0000107F Bank 0 Spare Area 7 Read-write 0x00001080-0x00001FFF Reserved —

DS60001614B-page 356  2020 Microchip Technology Inc.

25.16.4.2 NFC SRAM Access Prioritization Algorithm

When the NAND Flash Controller (NFC) is reading from or writing to the NFC SRAM, the internal memory is no longer accessible. If an NFC SRAM access occurs when the NFC performs a read or write operation then the access is dis - carded. The write operation is not performed. The read operation returns undefined data. If this situation is encountered, the status flag AWB located in the NFC status Register is raised and indicates that a shared resource access violation has occurred.

25.16.5 NAND FLASH OPERATIONS

This section describes the software operations needed to issue commands to the NAND Flash device and perform data transfers using NFC.

25.16.5.1 Page Read

FIGURE 25-37: PAGE READ FLOW CHART Note: Instead of using the interrupt one can poll the NFCBUSY Flag. For more information on the NFC Control Register, see “NFC Address Command” on page 349. Configure Device, writing in theUser Interface Write the NFC Command registersEnable XFRDONE interrupt (SMC_IER)Wait for Interrupt Copy the data from NFC SRAM to application memory (via DMA for example) Using NFC Check Error Correcting Codes

 2020 Microchip Technology Inc. DS60001614B-page 357 SAM3X8ERT

25.16.5.2 Program Page

FIGURE 25-38: PROGRAM PAGE FLOW CHART Writing the ECC can not be done using the NFC so it needs to be done “manually”. Note: Instead of using the interrupt one can poll the NFCBUSY Flag. For more information on the NFC Control Register, see “NFC Address Command” on page 349.

25.17 SMC Error Correcting Code Functional Description

A page in NAND Flash and SmartMedia memories contains an area for main data and an additional area used for redun- dancy (ECC). The page is organized in 8-bit or 16-bit words. The page size corresponds to the number of words in the main area plus the number of words in the extra area used for redundancy. Over time, some memory locations may fail to program or erase properly. In order to ensure that data is stored properly over the life of the NAND Flash device, NAND Flash providers recommend to utilize either 1 ECC per 256 bytes of data, 1 ECC per 512 bytes of data or 1 ECC for all of the page. The only configurations required for ECC are the NAND Flash or the SmartMedia page size (528/2112/4224) and the type of correction wanted (1 ECC for all the page/1 ECC per 256 bytes of data /1 ECC per 512 bytes of data). Page size is configured setting the PAGESIZE field in the ECC Mode Register (ECC_MR). Type of correction is configured setting the TYPCORRECT field in the ECC Mode Register (ECC_MR). Configure Device, writing in the User interface Write Data in the NFC SRAM (CPU or DMA) Enable XFRDONE Write the Command Register through the AHB interface Write ECC Wait for interruptWait for Ready/Busy interrupt

DS60001614B-page 358  2020 Microchip Technology Inc. Note: There is a limitation when using 16-bit NAND Flash: only 1 ECC for all of page is possible. For 8-bit NAND Flash there is no limitation. ECC is automatically computed as soon as a read (00h)/write (80h) command to the NAND Flash or the SmartMedia is detected. Read and write access must start at a page boundary. ECC results are available as soon as the counter reaches the end of the main area. Values in the ECC Parity Registers (ECC_PR0 to ECC_PR15) are then valid and locked until a new start condition occurs (read/write command followed by address cycles).

25.17.1 WRITE ACCESS

Once the Flash memory page is written, the computed ECC codes are available in the ECC Parity (ECC_PR0 to ECC_PR15) registers. The ECC code values must be written by the software application in the extra area used for redundancy. The number of write accesses in the extra area is a function of the value of the type of correction field. For example, for 1 ECC per 256 bytes of data for a page of 512 bytes, only the values of ECC_PR0 and ECC_PR1 must be written by the software application. Other registers are meaningless.

25.17.2 READ ACCESS

After reading the whole data in the main area, the application must perform read accesses to the extra area where ECC code has been previously stored. Error detection is automatically performed by the ECC controller. Note: It is mandatory to read consecutively the entire main area and the locations where Parity and NParity values have been previously stored to let the ECC controller perform error detection. The application can check the ECC Status Registers (ECC_SR1/ECC_SR2) for any detected errors. It is up to the appli- cation to correct any detected error. ECC computation can detect four different circumstances:

• No error: XOR between the ECC computation and the ECC code stored at the end of the NAND Flash or Smart- Media page is equal to 0. No error flags in the ECC Status Registers (ECC_SR1/ECC_SR2).
• Recoverable error: Only the RECERR flags in the ECC Status registers (ECC_SR1/ECC_SR2) are set. The cor- rupted word offset in the read page is defined by the WORDADDR field in the ECC Parity Registers (ECC_PR0 to ECC_PR15). The corrupted bit position in the concerned word is defined in the BITADDR field in the ECC Parity Registers (ECC_PR0 to ECC_PR15).
• ECC error: The ECCERR flag in the ECC Status Registers (ECC_SR1/ECC_SR2) is set. An error has been detected in the ECC code stored in the Flash memory. The position of the corrupted bit can be found by the appli- cation performing an XOR between the Parity and the NParity contained in the ECC code stored in the Flash memory.
• Non correctable error: The MULERR flag in the ECC Status Registers (ECC_SR1/ECC_SR2) is set. Several unre- coverable errors have been detected in the Flash memory page. ECC Status Registers, ECC Parity Registers are cleared when a read/write command is detected or a software reset is performed. For Single-bit Error Correction and Double-bit Error Detection (SEC-DED) Hsiao code is used. 24-bit ECC is generated in order to perform one bit correction per 256 or 512 bytes for pages of 512/2048/4096 8-bit words. 32-bit ECC is gen- erated in order to perform one bit correction per 512/1024/2048/4096 8- or 16-bit words. They are generated according to the schemes shown in Figure 25-39 and Figure 25-40.

 2020 Microchip Technology Inc. DS60001614B-page 359 SAM3X8ERT FIGURE 25-39: PARITY GENERATION FOR 512/1024/2048/4096 8-BIT WORDS To calculate P8’ to PX’ and P8 to PX, apply the algorithm that follows. Page size = 2n for i =0 to n begin for (j = 0 to page_size_byte) begin if(j[i] ==1) P[2i+3]=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)P[2i+3] else P[2i+3]’=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)P[2i+3]' end end Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P8' Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P8' P16 P16' Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P8' Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P8' P16 P16' P32 P32 1st byte P322nd byte 3rd byte 4 th byte Page size th byte (page size -1 )th byte PX PX' Page size = 512 Px = 2048 Page size = 1024 Px = 4096 Page size = 2048 Px = 8192 Page size = 4096 Px = 16384 (page size -2 )th byte (page size -3 )th byte P1 P1' P1'P1 P1 P1' P1'P1 P2 P2' P2 P2' P4 P4' P1=bit7(+)bit5(+)bit3(+)bit1(+)P1 P2=bit7(+)bit6(+)bit3(+)bit2(+)P2 P4=bit7(+)bit6(+)bit5(+)bit4(+)P4 P1'=bit6(+)bit4(+)bit2(+)bit0(+)P1' P2'=bit5(+)bit4(+)bit1(+)bit0(+)P2' P4'=bit7(+)bit6(+)bit5(+)bit4(+)P4'

DS60001614B-page 360  2020 Microchip Technology Inc. FIGURE 25-40: PARITY GENERATION FOR 512/1024/2048/4096 16-BIT WORDS To calculate P8’ to PX’ and P8 to PX, apply the algorithm that follows. Page size = 2n for i =0 to n begin for (j = 0 to page_size_word) begin if(j[i] ==1) P[2i+3]= bit15(+)bit14(+)bit13(+)bit12(+) bit11(+)bit10(+)bit9(+)bit8(+) bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)P[2n+3] else P[2i+3]’=bit15(+)bit14(+)bit13(+)bit12(+) bit11(+)bit10(+)bit9(+)bit8(+) bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)P[2i+3]' end end 1st word 2nd word 3rd word 4th word -3 )th word -2 )th word -1 )th word size th word (+) (+)

 2020 Microchip Technology Inc. DS60001614B-page 361 SAM3X8ERT

25.18 Static Memory Controller (SMC) User Interface

The SMC is programmed using the fields listed in Table 25-11. For each chip select a set of 4 registers is used to pro- gram the parameters of the external device. In Table 25-11, “CS_number” denotes chip select number. 16 bytes per chip select are required. TABLE 25-11: REGISTER MAPPING Offset Register Name Access Reset 0x000 SMC NFC Configuration Register SMC_CFG Read-write 0x0 0x004 SMC NFC Control Register SMC_CTRL Write-only 0x0 0x008 SMC NFC Status Register SMC_SR Read-only 0x0 0x00C SMC NFC Interrupt Enable Register SMC_IER Write-only 0x0 0x010 SMC NFC Interrupt Disable Register SMC_IDR Write-only 0x0 0x014 SMC NFC Interrupt Mask Register SMC_IMR Read-only 0x0 0x018 SMC NFC Address Cycle Zero Reg- ister SMC_ADDR Read-write 0x0 0x01C SMC Bank Address Register SMC_BANK Read-write 0x0 0x020 SMC ECC Control Register SMC_ECC_C- TRL Write-only 0x0 0x024 SMC ECC Mode Register SMC_ECC_MD Read-write 0x0 0x028 SMC ECC Status 1 Register SMC_EC- C_SR1 Read-only 0x0 0x02C SMC ECC Parity 0 Register SMC_EC- C_PR0 Read-only 0x0 0x030 SMC ECC parity 1 Register SMC_EC- C_PR1 Read-only 0x0 0x034 SMC ECC status 2 Register SMC_EC- C_SR2 Read-only 0x0 0x038 SMC ECC parity 2 Register SMC_EC- C_PR2 Read-only 0x0 0x03C SMC ECC parity 3 Register SMC_EC- C_PR3 Read-only 0x0 0x040 SMC ECC parity 4 Register SMC_EC- C_PR4 Read-only 0x0 0x044 SMC ECC parity 5 Register SMC_EC- C_PR5 Read-only 0x0 0x048 SMC ECC parity 6 Register SMC_EC- C_PR6 Read-only 0x0 0x04C SMC ECC parity 7 Register SMC_EC- C_PR7 Read-only 0x0 0x050 SMC ECC parity 8 Register SMC_EC- C_PR8 Read-only 0x0 0x054 SMC ECC parity 9 Register SMC_EC- C_PR9 Read-only 0x0 0x058 SMC ECC parity 10 Register SMC_EC- C_PR10 Read-only 0x0 0x05C SMC ECC parity 11 Register SMC_EC- C_PR11 Read-only 0x0 0x060 SMC ECC parity 12 Register SMC_EC- C_PR12 Read-only 0x0 0x064 SMC ECC parity 13 Register SMC_EC- C_PR13 Read-only 0x0 0x068 SMC ECC parity 14 Register SMC_EC- C_PR14 Read-only 0x0

DS60001614B-page 362  2020 Microchip Technology Inc. 0x06C SMC ECC parity 15 Register SMC_EC- C_PR15 Read-only 0x0 0x14*CS_num- ber+0x070 SMC SETUP Register SMC_SETUP Read-write 0x01010101 0x14*CS_num- ber+0x074 SMC PULSE Register SMC_PULSE Read-write 0x01010101 0x14*CS_num- ber+0x078 SMC CYCLE Register SMC_CYCLE Read-write 0x00030003 0x14*CS_num- ber+0x7C SMC TIMINGS Register SMC_TIMINGS Read-write 0x00000000 0x14*CS_num- ber+0x80 SMC MODE Register SMC_MODE Read-write 0x10000003 0x110 SMC OCMS MODE Register SMC_OCMS Read-write 0x0 0x114 SMC KEY1 Register SMC_KEY1 Write-only 0x0 0x118 SMC KEY2 Register SMC_KEY2 Write-only 0x0 0x1E4 Write Protection Control Register SMC_WPCR Write-only 0x0 0x1E8 Write Protection Status Register SMC_WPSR Read-only 0x0 0x1FC Reserved – – – TABLE 25-11: REGISTER MAPPING (CONTINUED) Offset Register Name Access Reset

 2020 Microchip Technology Inc. DS60001614B-page 363 SAM3X8ERT

25.18.1 SMC NFC CONFIGURATION REGISTER

Name:SMC_CFG Address:0x400E0000 Access:Read-write Reset:0x00000000

• PAGESIZE This field defines the page size of the NAND Flash device.
• WSPARE: Write Spare Area 0: The NFC skips the spare area in write mode. 1: The NFC writes both main area and spare area in write mode.
• RSPARE: Read Spare Area 0: The NFC skips the spare area in read mode. 1: The NFC reads both main area and spare area in read mode.
• EDGECTRL: Rising/Falling Edge Detection Control 0: Rising edge is detected. 1: Falling edge is detected.
• RBEDGE: Ready/Busy Signal Edge Detection 0: When set to zero, RB_EDGE fields indicate the level of the Ready/Busy lines. 1: When set to one, RB_EDGE fields indicate only transition on Ready/Busy lines.
• DTOCYC: Data Timeout Cycle Number
• DTOMUL: Data Timeout Multiplier These fields determine the maximum number of Master Clock cycles that the SMC waits until the detection of a rising edge on Ready/Busy signal. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — DTOMUL DTOCYC 15 14 13 12 11 10 9 8 — — RBEDGE EDGECTR L — — RSPARE WSPARE 7 6 5 4 3 2 1 0 Value Name Description

0 PS512_16 Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes

1 PS1024_32 Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes

2 PS2048_64 Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes

3 PS4096_128 Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes

DS60001614B-page 364  2020 Microchip Technology Inc. Multiplier is defined by DTOMUL as shown in the following table: If the data timeout set by DTOCYC and DTOMUL has been exceeded, the Data Timeout Error flag (DTOE) in the SMC Status Register (SMC_SR) raises. Value Name Description

0 X1 DTOCYC

1 X16 DTOCYC x 16

2 X128 DTOCYC x 128

3 X256 DTOCYC x 256

4 X1024 DTOCYC x 1024

5 X4096 DTOCYC x 4096

6 X65536 DTOCYC x 65536

7 X1048576 DTOCYC x 1048576

 2020 Microchip Technology Inc. DS60001614B-page 365 SAM3X8ERT

25.18.2 SMC NFC CONTROL REGISTER

Name: SMC_CTRL Address:0x400E0004 Access: Write-only Reset: 0x00000000

• NFCEN: NAND Flash Controller Enable
• NFCDIS: NAND Flash Controller Disable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DS60001614B-page 366  2020 Microchip Technology Inc.

25.18.3 SMC NFC STATUS REGISTER

Name: SMC_SR Address:0x400E0008 Access: Read-only Reset: 0x00000000

• SMCSTS: NAND Flash Controller status (this field cannot be reset) 0: NAND Flash Controller is disabled. 1: NAND Flash Controller is enabled.
• RB_RISE: Selected Ready Busy Rising Edge Detected When set to one, this flag indicates that a rising edge on Ready/Busy Line has been detected. This flag is reset after a status read operation. The Ready/Busy line selected is the decoding of the set NFCCSID, RBNSEL fields.
• RB_FALL: Selected Ready Busy Falling Edge Detected When set to one, this flag indicates that a falling edge on Ready/Busy Line has been detected. This flag is reset after a status read operation. The Ready/Busy line is selected through the decoding of the set NFCSID, RBNSEL fields.
• NFCBUSY: NFC Busy (this field cannot be reset) When set to one this flag indicates that the Controller is activated and accesses the memory device.
• NFCWR: NFC Write/Read Operation (this field cannot be reset) When a command is issued, this field indicates the current Read or Write Operation. This field can be manually updated with the use of the SMC_CTRL register.
• NFCSID: NFC Chip Select ID (this field cannot be reset) When a command is issued, this field indicates the value of the targeted chip select. This field can be manually updated with the use of the SMC_CTRL register.
• XFRDONE: NFC Data Transfer Terminated When set to one, this flag indicates that the NFC has terminated the Data Transfer. This flag is reset after a status read operation.
• CMDDONE: Command Done When set to one, this flag indicates that the NFC has terminated the Command. This flag is reset after a status read operation.
• DTOE: Data Timeout Error When set to one this flag indicates that the Data timeout set be by DTOMUL and DTOCYC has been exceeded. This flag is reset after a status read operation.
• UNDEF: Undefined Area Error When set to one this flag indicates that the processor performed an access in an undefined memory area. This flag is reset after a status read operation.
• AWB: Accessing While Busy 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NFCASE AWB UNDEF DTOE — — CMDDONE XFRDONE 15 14 13 12 11 10 9 8 — NFCSID NFCWR — — NFCBUSY 7 6 5 4 3 2 1 0

 2020 Microchip Technology Inc. DS60001614B-page 367 SAM3X8ERT If set to one this flag indicates that an AHB master has performed an access during the busy phase. This flag is reset after a status read operation.

• NFCASE: NFC Access Size Error If set to one, this flag indicates that an illegal access has been detected in the NFC Memory Area. Only Word Access is allowed within the NFC memory area. This flag is reset after a status read operation.
• RB_EDGEx: Ready/Busy Line x Edge Detected If set to one, this flag indicates that an edge has been detected on the Ready/Busy Line x. Depending on the EDGE CTRL field located in the SMC_MODE register, only rising or falling edge is detected. This flag is reset after a status read operation.

DS60001614B-page 368  2020 Microchip Technology Inc.

25.18.4 SMC NFC INTERRUPT ENABLE REGISTER

Name: SMC_IER Address:0x400E000C Access: Write-only Reset: 0x00000000

• RB_RISE: Ready Busy Rising Edge Detection Interrupt Enable
• RB_FALL: Ready Busy Falling Edge Detection Interrupt Enable
• XFRDONE: Transfer Done Interrupt Enable
• CMDDONE: Command Done Interrupt Enable
• DTOE: Data Timeout Error Interrupt Enable
• UNDEF: Undefined Area Access Interrupt Enable
• AWB: Accessing While Busy Interrupt Enable
• NFCASE: NFC Access Size Error Interrupt Enable
• RB_EDGEx: Ready/Busy Line x Interrupt Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NFCASE AWB UNDEF DTOE — — CMDDONE XFRDONE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

 2020 Microchip Technology Inc. DS60001614B-page 369 SAM3X8ERT

25.18.5 SMC NFC INTERRUPT DISABLE REGISTER

Name: SMC_IDR Address:0x400E0010 Access: Write-only Reset: 0x00000000

• RB_RISE: Ready Busy Rising Edge Detection Interrupt Disable
• RB_FALL: Ready Busy Falling Edge Detection Interrupt Disable
• XFRDONE: Transfer Done Interrupt Disable
• CMDDONE: Command Done Interrupt Disable
• DTOE: Data Timeout Error Interrupt Disable
• UNDEF: Undefined Area Access Interrupt Disable
• AWB: Accessing While Busy Interrupt Disable
• NFCASE: NFC Access Size Error Interrupt Disable
• RB_EDGEx: Ready/Busy Line x Interrupt Disable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NFCASE AWB UNDEF DTOE — — CMDDONE XFRDONE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DS60001614B-page 370  2020 Microchip Technology Inc.

25.18.6 SMC NFC INTERRUPT MASK REGISTER

Name: SMC_IMR Address:0x400E0014 Access: Read-only Reset: 0x00000000

• RB_RISE: Ready Busy Rising Edge Detection Interrupt Mask
• RB_FALL: Ready Busy Falling Edge Detection Interrupt Mask
• XFRDONE: Transfer Done Interrupt Mask
• CMDDONE: Command Done Interrupt Mask
• DTOE: Data Timeout Error Interrupt Mask
• UNDEF: Undefined Area Access Interrupt Mask5
• AWB: Accessing While Busy Interrupt Mask
• NFCASE: NFC Access Size Error Interrupt Mask
• RB_EDGEx: Ready/Busy Line x Interrupt Mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NFCASE AWB UNDEF DTOE — — CMDDONE XFRDONE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

 2020 Microchip Technology Inc. DS60001614B-page 371 SAM3X8ERT

25.18.7 SMC NFC ADDRESS CYCLE ZERO REGISTER

Name: SMC_ADDR Address:0x400E0018 Access: Read-Write Reset: 0x00000000

• ADDR_CYCLE0: NAND Flash Array Address cycle 0 When 5 address cycles are used, ADDR_CYCLE0 is the first byte written to NAND Flash (used by the NFC). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR_CYCLE0

DS60001614B-page 372  2020 Microchip Technology Inc.

25.18.8 SMC NFC BANK REGISTER

Name: SMC_BANK Address:0x400E001C Access: Read-write Reset: 0x00000000

• BANK: Bank Identifier Number of the Bank used 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

 2020 Microchip Technology Inc. DS60001614B-page 373 SAM3X8ERT

25.18.9 SMC ECC CONTROL REGISTER

Name: SMC_ECC_CTRL Address:0x400E0020 Access: Write-only Reset: 0x00000000

• RST: Reset ECC
• SWRST: Software Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DS60001614B-page 374  2020 Microchip Technology Inc.

25.18.10 SMC ECC MODE REGISTER

Name: SMC_ECC_MD Address:0x400E0024 Access: Read-write Reset: 0x00000000

• ECC_PAGESIZE This field defines the page size of the NAND Flash device.
• TYPCORREC: Type of Correction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — TYPCORREC — — ECC_PAGESIZE Value Name Description

0 CPAGE 1 bit correction for a page of 512/1024/2048/4096 Bytes

(for 8 or 16-bit NAND Flash)

1 C256B 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit

NAND Flash only)

2 C512B 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit

NAND Flash only)

 2020 Microchip Technology Inc. DS60001614B-page 375 SAM3X8ERT

25.18.11 SMC ECC STATUS REGISTER 1

Name: SMC_ECC_SR1 Address:0x400E0028 Access: Read-only Reset: 0x00000000

• RECERR0: Recoverable Error 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected.
• ECCERR0: ECC Error 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes. If TYPECORRECT = 0, read both ECC Parity 0 and ECC Parity 1 registers, the error occurred at the location which contains a 1 in the least significant 16 bits; else read ECC Parity 0 register, the error occurred at the location which con- tains a 1 in the least significant 24 bits.
• MULERR0: Multiple Error 0: No Multiple Errors Detected. 1: Multiple Errors Detected.
• RECERR1: Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected.
• ECCERR1: ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes Fixed to 0 if TYPECORREC = 0 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes. Read ECC Parity 1 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR1: Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected.
• RECERR2: Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes Fixed to 0 if TYPECORREC = 0. 31 30 29 28 27 26 25 24 — ECCERR7 ECCERR7 RECERR7 — ECCERR6 ECCERR6 RECERR6 23 22 21 20 19 18 17 16 — ECCERR5 ECCERR5 RECERR5 — ECCERR4 ECCERR4 RECERR4 15 14 13 12 11 10 9 8 — MULERR3 ECCERR3 RECERR3 — MULERR2 ECCERR2 RECERR2 7 6 5 4 3 2 1 0 — MULERR1 ECCERR1 RECERR1 — ECCERR0 ECCERR0 RECERR0

DS60001614B-page 376  2020 Microchip Technology Inc. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected.

• ECCERR2: ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes. Read ECC Parity 2 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR2: Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected.
• RECERR3: Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected.
• ECCERR3: ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes. Read ECC Parity 3 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR3: Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected.
• RECERR4: Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected.
• ECCERR4: ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes. Read ECC Parity 4 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR4: Multiple Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected.

 2020 Microchip Technology Inc. DS60001614B-page 377 SAM3X8ERT 1: Multiple Errors Detected.

• RECERR5: Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected
• ECCERR5: ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes. Read ECC Parity 5 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR5: Multiple Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected.
• RECERR6: Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected.
• ECCERR6: ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes. Read ECC Parity 6 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR6: Multiple Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected.
• RECERR7: Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected.
• ECCERR7: ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes. Read ECC Parity 7 register, the error occurred at the location which contains a 1 in the least significant 24 bits.

DS60001614B-page 378  2020 Microchip Technology Inc.

• MULERR7: Multiple Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected.

 2020 Microchip Technology Inc. DS60001614B-page 379 SAM3X8ERT

25.18.12 SMC ECC STATUS REGISTER 2

Name: SMC_ECC_SR2 Address:0x400E0034 Access: Read-only Reset: 0x00000000

• RECERR8: Recoverable Error in the page between the 2048th and the 2303rd bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected
• ECCERR8: ECC Error in the page between the 2048th and the 2303rd bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes. Read ECC Parity 8 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR8: Multiple Error in the page between the 2048th and the 2303rd bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected.
• RECERR9: Recoverable Error in the page between the 2304th and the 2559th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected.
• ECCERR9: ECC Error in the page between the 2304th and the 2559th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes. Read ECC Parity 9 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR9: Multiple Error in the page between the 2304th and the 2559th bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected.
• RECERR10: Recoverable Error in the page between the 2560th and the 2815th bytes 31 30 29 28 27 26 25 24 — ECCERR1 ECCERR1 RECERR1 5 — ECCERR1 ECCERR1 RECERR1 23 22 21 20 19 18 17 16 — ECCERR1 ECCERR1 RECERR1 3 — ECCERR1 ECCERR1 RECERR1 15 14 13 12 11 10 9 8 — MULERR1 ECCERR1 RECERR1 1 — MULERR1 ECCERR1 RECERR1 7 6 5 4 3 2 1 0 — MULERR9 ECCERR9 RECERR9 — ECCERR8 ECCERR8 RECERR8

DS60001614B-page 380  2020 Microchip Technology Inc. Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected.

• ECCERR10: ECC Error in the page between the 2560th and the 2815th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes. Read ECC Parity 10 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR10: Multiple Error in the page between the 2560th and the 2815th bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected.
• RECERR11: Recoverable Error in the page between the 2816th and the 3071st bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected
• ECCERR11: ECC Error in the page between the 2816th and the 3071st bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes. Read ECC Parity 11 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR11: Multiple Error in the page between the 2816th and the 3071st bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected.
• RECERR12: Recoverable Error in the page between the 3072nd and the 3327th bytes Fixed to 0 if TYPECORREC = 0 0: No Errors Detected 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected
• ECCERR12: ECC Error in the page between the 3072nd and the 3327th bytes Fixed to 0 if TYPECORREC = 0 0: No Errors Detected 1: A single bit error occurred in the ECC bytes. Read ECC Parity 12 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR12: Multiple Error in the page between the 3072nd and the 3327th bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected.
• RECERR13: Recoverable Error in the page between the 3328th and the 3583rd bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected.

 2020 Microchip Technology Inc. DS60001614B-page 381 SAM3X8ERT 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected.

• ECCERR13: ECC Error in the page between the 3328th and the 3583rd bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes. Read ECC Parity 13 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR13: Multiple Error in the page between the 3328th and the 3583rd bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected.
• RECERR14: Recoverable Error in the page between the 3584th and the 3839th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected.
• ECCERR14: ECC Error in the page between the 3584th and the 3839th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes. Read ECC Parity 14 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR14: Multiple Error in the page between the 3584th and the 3839th bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected.
• RECERR15: Recoverable Error in the page between the 3840th and the 4095th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected.
• ECCERR15: ECC Error in the page between the 3840th and the 4095th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes. Read ECC Parity 15 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
• MULERR15: Multiple Error in the page between the 3840th and the 4095th bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected.

DS60001614B-page 382  2020 Microchip Technology Inc.

25.18.13 SMC ECC PARITY REGISTER 0 FOR A PAGE OF 512/1024/2048/4096 BYTES

Name: SMC_ECC_PR0 Address:0x400E002C Access: Read-only Reset: 0x00000000 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.

• BITADDR: Bit Address During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless.
• WORDADDR: Word Address During a page read, this value contains the word address (8-bit or 16-bit word depending on the memory plane organi- zation).where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaning - less. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 WORDADDR 7 6 5 4 3 2 1 0 WORDADDR BITADDR

 2020 Microchip Technology Inc. DS60001614B-page 383 SAM3X8ERT

25.18.14 SMC ECC PARITY REGISTER 1 FOR A PAGE OF 512/1024/2048/4096 BYTES

Name: SMC_ECC_PR1 Address:0x400E0030 Access: Read-only Reset: 0x00000000

• NPARITY: Parity N 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 NPARITY 7 6 5 4 3 2 1 0 NPARITY

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25.18.15 SMC ECC PARITY REGISTERS FOR 1 ECC PER 512 BYTES FOR A PAGE OF

512/2048/4096 BYTES, 9-BIT WORD Name: SMC_ECC_PRx [x=0..7] (W9BIT) Address:0x400E0038 [2] .. 0x400E006C [15] Access: Read-only Reset: 0x00000000 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.

• BITADDR: Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless.
• WORDADDR: Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes During a page read, this value contains the word address (9-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless.
• NPARITY: Parity N 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NPARITY 15 14 13 12 11 10 9 8 NPARITY WORDADDR 7 6 5 4 3 2 1 0 WORDADDR BITADDR

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25.18.16 SMC ECC PARITY REGISTERS FOR 1 ECC PER 256 BYTES FOR A PAGE OF

512/2048/4096 BYTES, 8-BIT WORD Name: SMC_ECC_PRx [x=0..15] (W8BIT) Address:0x400E0038 [2] .. 0x400E006C [15] Access: Read-only Reset: 0x00000000 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.

• BITADDR: Corrupted Bit Address in the page between (i x 256) and ((i + 1) x 512) - 1) Bytes
• During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless.
• WORDADDR: Corrupted Word Address in the page between (i x 256) and ((i + 1) x 512) - 1) Bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless.
• NPARITY: Parity N 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

0 NPARITY

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25.18.17 SMC SETUP REGISTER

Name: SMC_SETUPx [x=0..7] Address:0x400E0070 [0], 0x400E0084 [1], 0x400E0098 [2], 0x400E00AC [3], 0x400E00C0 [4], 0x400E00D4 [5], 0x400E00E8 [6], 0x400E00FC [7] Access: Write-only Reset: 0x00000000

• NWE_SETUP: NWE Setup Length The NWE signal setup length is defined as: NWE setup length = (128 * NWE_SETUP[5] + NWE_SETUP[4:0]) clock cycles.
• NCS_WR_SETUP: NCS Setup length in Write access In write access, the NCS signal setup length is defined as: NCS setup length = (128 * NCS_WR_SETUP[5] + NCS_WR_SETUP[4:0]) clock cycles.
• NRD_SETUP: NRD Setup length The NRD signal setup length is defined as: NRD setup length = (128 * NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles.
• NCS_RD_SETUP: NCS Setup length in Read access In Read access, the NCS signal setup length is defined as: NCS setup length = (128 * NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles. 31 30 29 28 27 26 25 24 — — NCS_RD_SETUP 23 22 21 20 19 18 17 16 — — NRD_SETUP 15 14 13 12 11 10 9 8 — — NCS_WR_SETUP 7 6 5 4 3 2 1 0 — — NWE_SETUP

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25.18.18 SMC PULSE REGISTER

Name: SMC_PULSEx [x=0..7] Address:0x400E0074 [0], 0x400E0088 [1], 0x400E009C [2], 0x400E00B0 [3], 0x400E00C4 [4], 0x400E00D8 [5], 0x400E00EC [6], 0x400E0100 [7] Access: Write-only Reset: 0x00000000

• NWE_PULSE: NWE Pulse Length The NWE signal pulse length is defined as: NWE pulse length = (256 * NWE_PULSE[6]+NWE_PULSE[5:0]) clock cycles. The NWE pulse must be at least one clock cycle.
• NCS_WR_PULSE: NCS Pulse Length in WRITE Access In Write access, The NCS signal pulse length is defined as: NCS pulse length = (256 * NCS_WR_PULSE[6] + NCS_WR_PULSE[5:0]) clock cycles. the NCS pulse must be at least one clock cycle.
• NRD_PULSE: NRD Pulse Length The NRD signal pulse length is defined as: NRD pulse length = (256 * NRD_PULSE[6] + NRD_PULSE[5:0]) clock cycles. The NRD pulse width must be as least 1 clock cycle.
• NCS_RD_PULSE: NCS Pulse Length in READ Access In READ mode, The NCS signal pulse length is defined as: NCS pulse length = (256 * NCS_RD_PULSE[6] + NCS_RD_PULSE[5:0]) clock cycles. 31 30 29 28 27 26 25 24 — — NCS_RD_PULSE 23 22 21 20 19 18 17 16 — — NRD_PULSE 15 14 13 12 11 10 9 8 — — NCS_WR_PULSE 7 6 5 4 3 2 1 0 — — NWE_PULSE

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25.18.19 SMC CYCLE REGISTER

Name: SMC_CYCLEx [x=0..7] Address:0x400E0078 [0], 0x400E008C [1], 0x400E00A0 [2], 0x400E00B4 [3], 0x400E00C8 [4], 0x400E00DC [5], 0x400E00F0 [6], 0x400E0104 [7] Access: Read-write Reset: 0x00000000

• NWE_CYCLE: Total Write Cycle Length The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pulse and hold steps of the NWE and NCS signals. It is defined as: Write cycle length = (NWE_CYCLE[8:7] * 256) + NWE_CYCLE[6:0] clock cycles.
• NRD_CYCLE: Total Read Cycle Length The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse and hold steps of the NRD and NCS signals. It is defined as: Read cycle length = (NRD_CYCLE[8:7] * 256) + NRD_CYCLE[6:0] clock cycles. 31 30 29 28 27 26 25 24 E 23 22 21 20 19 18 17 16 NRD_CYCLE 15 14 13 12 11 10 9 8 E 7 6 5 4 3 2 1 0 NWE_CYCLE

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25.18.20 SMC TIMINGS REGISTER

Name: SMC_TIMINGSx [x=0..7] Address:0x400E007C [0], 0x400E0090 [1], 0x400E00A4 [2], 0x400E00B8 [3], 0x400E00CC [4], 0x400E00E0 [5], 0x400E00F4 [6], 0x400E0108 [7] Access: Read-write Reset: 0x00000000

• TCLR: CLE to REN Low Delay Command Latch Enable falling edge to Read Enable falling edge timing. Latch Enable Falling to Read Enable Falling = (TCLR[3] * 64) + TCLR[2:0] clock cycles.
• TADL: ALE to Data Start Last address latch cycle to the first rising edge of WEN for data input. Last address latch to first rising edge of WEN = (TADL[3] * 64) + TADL[2:0] clock cycles.
• TAR: ALE to REN Low Delay Address Latch Enable falling edge to Read Enable falling edge timing. Address Latch Enable to Read Enable = (TAR[3] * 64) + TAR[2:0] clock cycles.
• OCMS: Off Chip Memory Scrambling Enable When set to one, the memory scrambling is activated.
• TRR: Ready to REN Low Delay Ready/Busy signal to Read Enable falling edge timing. Read to REN = (TRR[3] * 64) + TRR[2:0] clock cycles.
• TWB: WEN High to REN to Busy Write Enable rising edge to Ready/Busy falling edge timing. Write Enable to Read/Busy = (TWB[3] * 64) + TWB[2:0] clock cycles.
• RBNSEL: Ready/Busy Line Selection This field indicates the selected Ready/Busy Line from the RBN bundle.
• NFSEL: NAND Flash Selection If this bit is set to one, the chip select is assigned to NAND Flash write enable and read enable lines drive the Error Correcting Code module. 31 30 29 28 27 26 25 24 NFSEL RBNSEL TWB 23 22 21 20 19 18 17 16 — — — — TRR 15 14 13 12 11 10 9 8 — — — OCMS TAR 7 6 5 4 3 2 1 0 TADL TCLR

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25.18.21 SMC MODE REGISTER

Name: SMC_MODEx [x=0..7] Address:0x400E0080 [0], 0x400E0094 [1], 0x400E00A8 [2], 0x400E00BC [3], 0x400E00D0 [4], 0x400E00E4 [5], 0x400E00F8 [6], 0x400E010C [7] Access: Read-write Reset: 0x00000000

• READ_MODE 1: The Read operation is controlled by the NRD signal. 0: The Read operation is controlled by the NCS signal.
• WRITE_MODE 1: The Write operation is controlled by the NWE signal. 0: The Write operation is controller by the NCS signal.
• EXNW_MODE: NWAIT Mode The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase Read and Write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be pro - grammed for the read and write controlling signal
• Disabled Mode: The NWAIT input signal is ignored on the corresponding Chip Select.
• Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped.
• Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — TDF_MODE TDF_CYCLES 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DE READ_MOD E Value Name Description

0 DISABLED Disabled

1 — Reserved

2 FROZEN Frozen Mode

3 READY Ready Mode

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• BAT: Byte Access Type This field is used only if DBW defines a 16-bit data bus.
• 1: Byte write access type: – Write operation is controlled using NCS, NWR0, NWR1. – Read operation is controlled using NCS and NRD.
• 0: Byte select access type: – Write operation is controlled using NCS, NWE, NBS0, NBS1. – Read operation is controlled using NCS, NRD, NBS0, NBS1.
• DBW: Data Bus Width
• TDF_CYCLES: Data Float Time This field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF_CYCLES period. The external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_- CYCLES can be set.
• TDF_MODE: TDF Optimization 1: TDF optimization is enabled. – The number of TDF wait states is optimized using the setup period of the next read/write access. 0: TDF optimization is disabled. – The number of TDF wait states is inserted before the next access begins. Value Name Description

0 BIT_8 8-bit bus

1 BIT_16 16-bit bus

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25.18.22 SMC OCMS REGISTER

Name: SMC_OCMS Address:0x400E0110 Access: Read-write Reset: 0x00000000

• SMSE: Static Memory Controller Scrambling Enable 0: Disable “Off Chip” Scrambling for SMC access. 1: Enable “Off Chip” Scrambling for SMC access. (If OCMS field is set to 1 in the relevant SMC_TIMINGS register.)
• SRSE: SRAM Scrambling Enable 0: Disable SRAM Scrambling for SRAM access. 1: Enable SRAM Scrambling for SRAM access. (If OCMS field is set to 1 in the relevant SMC_TIMINGS register.) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

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25.18.23 SMC OCMS KEY1 REGISTER

Name: SMC_KEY1 Address:0x400E0114 Access: Write Once Reset: 0x00000000

• KEY1: Off Chip Memory Scrambling (OCMS) Key Part 1 When Off Chip Memory Scrambling is enabled by setting the SMC_OMCS and SMC_TIMINGS registers in accordance, the data scrambling depends on KEY1 and KEY2 values. 31 30 29 28 27 26 25 24 KEY1 23 22 21 20 19 18 17 16 KEY1 15 14 13 12 11 10 9 8 KEY1 7 6 5 4 3 2 1 0 KEY1

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25.18.24 SMC OCMS KEY2 REGISTER

Name: SMC_KEY2 Address:0x400E0118 Access: Write Once Reset: 0x00000000

• KEY2: Off Chip Memory Scrambling (OCMS) Key Part 2 When Off Chip Memory Scrambling is enabled by setting the SMC_OMCS and SMC_TIMINGS registers in accordance, the data scrambling depends on KEY2 and KEY1 values. 31 30 29 28 27 26 25 24 KEY2 23 22 21 20 19 18 17 16 KEY2 15 14 13 12 11 10 9 8 KEY2 7 6 5 4 3 2 1 0 KEY2

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25.18.25 SMC WRITE PROTECTION CONTROL

Name:SMC_WPCR Address:0x400E01E4 Access: Write-only

• WP_EN: Write Protection Enable 0: Disables the Write Protection if WP_KEY corresponds. 1: Enables the Write Protection if WP_KEY corresponds.
• WP_KEY: Write Protection KEY password Should be written at value 0x534D43 (ASCII code for “SMC”). Writing any other value in this field has no effect. 31 30 29 28 27 26 25 24 WP_KEY 23 22 21 20 19 18 17 16 WP_KEY 15 14 13 12 11 10 9 8 WP_KEY 7 6 5 4 3 2 1 0 WP_EN

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25.18.26 SMC WRITE PROTECTION STATUS

Name:SMC_WPSR Address:0x400E01E8 Access: Read-only

• WP_VS: Write Protection Violation Status 0: No Write Protect Violation has occurred since the last read of the SMC_WPSR register. 1: A Write Protect Violation has occurred since the last read of the SMC_WPSR register. If this violation is an unautho- rized attempt to write a protected register, the associated violation is reported into field WP_VSRC.
• WP_VSRC: Write Protection Violation Source WP_VSRC field Indicates the Register offset where the last violation occurred. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WP_VSRC 15 14 13 12 11 10 9 8 WP_VSRC 7 6 5 4 3 2 1 0

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26.0 PERIPHERAL DMA CONTROLLER (PDC)

26.1 Description

The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the on- and/or off-chip memories. The link between the PDC and a serial peripheral is operated by the AHB to APB bridge. The user interface of each PDC channel is integrated into the user interface of the peripheral it serves. The user inter- face of mono directional channels (receive only or transmit only), contains two 32-bit memory pointers and two 16-bit counters, one set (pointer, counter) for current transfer and one set (pointer, counter) for next transfer. The bi-directional channel user interface contains four 32-bit memory pointers and four 16-bit counters. Each set (pointer, counter) is used by current transmit, next transmit, current receive and next receive. Using the PDC removes processor overhead by reducing its intervention during the transfer. This significantly reduces the number of clock cycles required for a data transfer, which improves microcontroller performance. To launch a transfer, the peripheral triggers its associated PDC channels by using transmit and receive signals. When the programmed data is transferred, an end of transfer interrupt is generated by the peripheral itself.

26.2 Embedded Characteristics

• Handles data transfer between peripherals and memories
• Low bus arbitration overhead - One Master Clock cycle needed for a transfer from memory to peripheral - Two Master Clock cycles needed for a transfer from peripheral to memory
• Next Pointer management for reducing interrupt latency requirement

DS60001614B-page 398  2020 Microchip Technology Inc. The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities): TABLE 26-1: Peripheral DMA Controller Instance Name Channel T/R 144 Pins DAC Transmit X PWM Transmit X TWI1 Transmit X TWI0 Transmit X USART3 Transmit X USART2 Transmit X USART1 Transmit X USART0 Transmit X UART Transmit X ADC Receive X TWI1 Receive X TWI0 Receive X USART3 Receive X USART2 Receive X USART1 Receive X USART0 Receive X UART Receive X

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26.3 Block Diagram

FIGURE 26-1: BLOCK DIAGRAM

26.4 Functional Description

26.4.1 CONFIGURATION

The PDC channel user interface enables the user to configure and control data transfers for each channel. The user interface of each PDC channel is integrated into the associated peripheral user interface. The user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit pointers (RPR, RNPR, TPR, TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR). However, the transmit and receive parts of each type are programmed differently: the transmit and receive parts of a full duplex peripheral can be programmed at the same time, whereas only one part (transmit or receive) of a half duplex peripheral can be programmed at a time. PDCFULL DUPLEX PERIPHERAL THR RHR PDC Channel A PDC Channel B Control Status & Control Control PDC Channel C HALF DUPLEX PERIPHERAL THR Status & Control RECEIVE or TRANSMIT PERIPHERAL RHR or THR Control Control RHR PDC Channel D Status & Control

DS60001614B-page 400  2020 Microchip Technology Inc. 32-bit pointers define the access location in memory for current and next transfer, whether it is for read (transmit) or write (receive). 16-bit counters define the size of current and next transfers. It is possible, at any moment, to read the number of transfers left for each channel. The PDC has dedicated status registers which indicate if the transfer is enabled or disabled for each channel. The status for each channel is located in the associated peripheral status register. Transfers can be enabled and/or disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS in the peripheral’s Transfer Control Register. At the end of a transfer, the PDC channel sends status flags to its associated peripheral. These flags are visible in the peripheral status register (ENDRX, ENDTX, RXBUFF, and TXBUFE). Refer to “Transfer Counters” on page 400 and to the associated peripheral user interface.

26.4.2 MEMORY POINTERS

Each full duplex peripheral is connected to the PDC by a receive channel and a transmit channel. Both channels have 32-bit memory pointers that point respectively to a receive area and to a transmit area in on- and/or off-chip memory. Each half duplex peripheral is connected to the PDC by a bidirectional channel. This channel has two 32-bit memory pointers, one for current transfer and the other for next transfer. These pointers point to transmit or receive data depend- ing on the operating mode of the peripheral. Depending on the type of transfer (byte, half-word or word), the memory pointer is incremented respectively by 1, 2 or 4 bytes. If a memory pointer address changes in the middle of a transfer, the PDC channel continues operating using the new address.

26.4.3 TRANSFER COUNTERS

Each channel has two 16-bit counters, one for current transfer and the other one for next transfer. These counters define the size of data to be transferred by the channel. The current transfer counter is decremented first as the data addressed by current memory pointer starts to be transferred. When the current transfer counter reaches zero, the channel checks its next transfer counter. If the value of next counter is zero, the channel stops transferring data and sets the appropriate flag. But if the next counter value is greater then zero, the values of the next pointer/next counter are copied into the current pointer/current counter and the channel resumes the transfer whereas next pointer/next counter get zero/zero as values. At the end of this transfer the PDC channel sets the appropriate flags in the Peripheral Status Register. The following list gives an overview of how status register flags behave depending on the counters’ values:

• ENDRX flag is set when the PERIPH_RCR register reaches zero.
• RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero.
• ENDTX flag is set when the PERIPH_TCR register reaches zero.
• TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero. These status flags are described in the Peripheral Status Register.

26.4.4 DATA TRANSFERS

The serial peripheral triggers its associated PDC channels’ transfers using transmit enable (TXEN) and receive enable (RXEN) flags in the transfer control register integrated in the peripheral’s user interface. When the peripheral receives an external data, it sends a Receive Ready signal to its PDC receive channel which then requests access to the Matrix. When access is granted, the PDC receive channel starts reading the peripheral Receive Holding Register (RHR). The read data are stored in an internal buffer and then written to memory. When the peripheral is about to send data, it sends a Transmit Ready to its PDC transmit channel which then requests access to the Matrix. When access is granted, the PDC transmit channel reads data from memory and puts them to Transmit Holding Register (THR) of its associated peripheral. The same peripheral sends data according to its mecha- nism.

26.4.5 PDC FLAGS AND PERIPHERAL STATUS REGISTER

Each peripheral connected to the PDC sends out receive ready and transmit ready flags and the PDC sends back flags to the peripheral. All these flags are only visible in the Peripheral Status Register. Depending on the type of peripheral, half or full duplex, the flags belong to either one single channel or two different channels.

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26.4.5.1 Receive Transfer End

This flag is set when PERIPH_RCR register reaches zero and the last data has been transferred to memory. It is reset by writing a non zero value in PERIPH_RCR or PERIPH_RNCR.

26.4.5.2 Transmit Transfer End

This flag is set when PERIPH_TCR register reaches zero and the last data has been written into peripheral THR. It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.

26.4.5.3 Receive Buffer Full

This flag is set when PERIPH_RCR register reaches zero with PERIPH_RNCR also set to zero and the last data has been transferred to memory. It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.

26.4.5.4 Transmit Buffer Empty

This flag is set when PERIPH_TCR register reaches zero with PERIPH_TNCR also set to zero and the last data has been written into peripheral THR. It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.

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26.5 Peripheral DMA Controller (PDC) User Interface

Note 1: PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user according to the function and the desired peripheral.) TABLE 26-2: REGISTER MAPPING Offset Register Name Access Reset 0x100 Receive Pointer Register PERIPH(1)_RPR Read-write 0 0x104 Receive Counter Register PERIPH_RCR Read-write 0 0x108 Transmit Pointer Register PERIPH_TPR Read-write 0 0x10C Transmit Counter Register PERIPH_TCR Read-write 0 0x110 Receive Next Pointer Register PERIPH_RNPR Read-write 0 0x114 Receive Next Counter Register PERIPH_RNCR Read-write 0 0x118 Transmit Next Pointer Register PERIPH_TNPR Read-write 0 0x11C Transmit Next Counter Register PERIPH_TNCR Read-write 0 0x120 Transfer Control Register PERIPH_PTCR Write-only 0 0x124 Transfer Status Register PERIPH_PTSR Read-only 0

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26.5.1 RECEIVE POINTER REGISTER

Name:PERIPH_RPR Access:Read-write

• RXPTR: Receive Pointer Register RXPTR must be set to receive buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR. 31 30 29 28 27 26 25 24 RXPTR 23 22 21 20 19 18 17 16 RXPTR 15 14 13 12 11 10 9 8 RXPTR 7 6 5 4 3 2 1 0 RXPTR

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26.5.2 RECEIVE COUNTER REGISTER

Name:PERIPH_RCR Access:Read-write

• RXCTR: Receive Counter Register RXCTR must be set to receive buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR. 0: Stops peripheral data transfer to the receiver 1 - 65535: Starts peripheral data transfer if corresponding channel is active

26.5.3 TRANSMIT POINTER REGISTER

Name:PERIPH_TPR Access:Read-write

• TXPTR: Transmit Counter Register TXPTR must be set to transmit buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RXCTR 7 6 5 4 3 2 1 0 RXCTR 31 30 29 28 27 26 25 24 TXPTR 23 22 21 20 19 18 17 16 TXPTR 15 14 13 12 11 10 9 8 TXPTR 7 6 5 4 3 2 1 0 TXPTR

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26.5.4 TRANSMIT COUNTER REGISTER

Name:PERIPH_TCR Access:Read-write

• TXCTR: Transmit Counter Register TXCTR must be set to transmit buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR. 0: Stops peripheral data transfer to the transmitter 1- 65535: Starts peripheral data transfer if corresponding channel is active 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TXCTR 7 6 5 4 3 2 1 0 TXCTR

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26.5.5 RECEIVE NEXT POINTER REGISTER

Name:PERIPH_RNPR Access:Read-write

• RXNPTR: Receive Next Pointer RXNPTR contains next receive buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR. 31 30 29 28 27 26 25 24 RXNPTR 23 22 21 20 19 18 17 16 RXNPTR 15 14 13 12 11 10 9 8 RXNPTR 7 6 5 4 3 2 1 0 RXNPTR

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26.5.6 RECEIVE NEXT COUNTER REGISTER

Name:PERIPH_RNCR Access:Read-write

• RXNCTR: Receive Next Counter RXNCTR contains next receive buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RXNCTR 7 6 5 4 3 2 1 0 RXNCTR

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26.5.7 TRANSMIT NEXT POINTER REGISTER

Name:PERIPH_TNPR Access:Read-write

• TXNPTR: Transmit Next Pointer TXNPTR contains next transmit buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR. 31 30 29 28 27 26 25 24 TXNPTR 23 22 21 20 19 18 17 16 TXNPTR 15 14 13 12 11 10 9 8 TXNPTR 7 6 5 4 3 2 1 0 TXNPTR

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26.5.8 TRANSMIT NEXT COUNTER REGISTER

Name:PERIPH_TNCR Access:Read-write

• TXNCTR: Transmit Counter Next TXNCTR contains next transmit buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TXNCTR 7 6 5 4 3 2 1 0 TXNCTR

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26.5.9 TRANSFER CONTROL REGISTER

Name:PERIPH_PTCR Access:Write-only

• RXTEN: Receiver Transfer Enable 0: No effect. 1: Enables PDC receiver channel requests if RXTDIS is not set. When a half duplex peripheral is connected to the PDC, enabling the receiver channel requests automatically disables the transmitter channel requests. It is forbidden to set both TXTEN and RXTEN for a half duplex peripheral.
• RXTDIS: Receiver Transfer Disable 0: No effect. 1: Disables the PDC receiver channel requests. When a half duplex peripheral is connected to the PDC, disabling the receiver channel requests also disables the trans- mitter channel requests.
• TXTEN: Transmitter Transfer Enable 0: No effect. 1: Enables the PDC transmitter channel requests. When a half duplex peripheral is connected to the PDC, it enables the transmitter channel requests only if RXTEN is not set. It is forbidden to set both TXTEN and RXTEN for a half duplex peripheral.
• TXTDIS: Transmitter Transfer Disable 0: No effect. 1: Disables the PDC transmitter channel requests. When a half duplex peripheral is connected to the PDC, disabling the transmitter channel requests disables the receiver channel requests. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

 2020 Microchip Technology Inc. DS60001614B-page 411 SAM3X8ERT

26.5.10 TRANSFER STATUS REGISTER

Name:PERIPH_PTSR Access:Read-only

• RXTEN: Receiver Transfer Enable 0: PDC Receiver channel requests are disabled. 1: PDC Receiver channel requests are enabled.
• TXTEN: Transmitter Transfer Enable 0: PDC Transmitter channel requests are disabled. 1: PDC Transmitter channel requests are enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DS60001614B-page 412  2020 Microchip Technology Inc.

27.0 CLOCK GENERATOR

27.1 Description

The Clock Generator User Interface is embedded within the Power Management Controller and is described in “Power Management Controller (PMC) User Interface” on page 431 . However, the Clock Generator registers are named CKGR_.

27.2 Embedded Characteristics

The Clock Generator is made up of: A Low Power 32,768 Hz Slow Clock Oscillator with bypass mode.

• A Low Power RC Oscillator
• A 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator, which can be bypassed.
• A factory programmed Fast RC Oscillator. 3 output frequencies can be selected: 4, 8 or 12MHz. By default 4MHz is selected.
• A 480 MHz UTMI PLL, providing a clock for the USB High Speed Controller.
• A 96 to 192 MHz programmable PLL (input from 8 to 16 MHz), capable of providing the clock MCK to the proces- sor and to the peripherals. It provides the following clocks:
• SLCK, the Slow Clock, which is the only permanent clock within the system.
• MAINCK is the output of the Main Clock Oscillator selection: either the Crystal or Ceramic Resonator-based Oscil- lator or 4/8/12 MHz Fast RC Oscillator.
• PLLACK is the output of the Divider and 96 to 192 MHz programmable PLL (PLLA).
• UPLLCK is the output of the 480 MHz UTMI PLL (UPLL).

 2020 Microchip Technology Inc. DS60001614B-page 413 SAM3X8ERT

27.3 Block Diagram

FIGURE 27-1: CLOCK GENERATOR BLOCK DIAGRAM

27.4 Slow Clock

The Supply Controller embeds a slow clock generator that is supplied with the VDDBU power supply. As soon as the VDDBU is supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the embedded RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 µs). The Slow Clock is generated either by the Slow Clock Crystal Oscillator or by the Slow Clock RC Oscillator. The selection between the RC or the crystal oscillator is made by writing the XTALSEL bit in the Supply Controller Con- trol Register (SUPC_CR).

27.4.1 SLOW CLOCK RC OSCILLATOR

By default, the Slow Clock RC Oscillator is enabled and selected. The user has to take into account the possible drifts of the RC Oscillator. More details are given in the section “DC Characteristics” of the product datasheet. It can be disabled via the XTALSEL bit in the Supply Controller Control Register (SUPC_CR). Power Management Controller Main Clock MAINCK PLLA Clock PLLACK ControlStatus 3-20 MHz Crystal Oscillator MOSCSEL Clock Generator PLLA and Divider Embedded 12/8/4 MHz Fast RC Oscillator XIN XOUT XIN32 XOUT32 Slow Clock SLCK XTALSEL (Supply Controller) Embedded 32 kHz RC Oscillator 32768 Hz Crystal Oscillator UPLL Clock UPLLCK USB UTMI PLL

DS60001614B-page 414  2020 Microchip Technology Inc.

27.4.2 SLOW CLOCK CRYSTAL OSCILLATOR

The Clock Generator integrates a 32,768 Hz low-power oscillator. In order to use this oscillator, the XIN32 and XOUT32 pins must be connected to a 32,768 Hz crystal. Two external capacitors must be wired as shown in Figure 27-2. More details are given in the section “DC Characteristics” of the product datasheet. Note: The user is not obliged to use the Slow Clock Crystal and can use the RC oscillator instead. FIGURE 27-2: TYPICAL SLOW CLOCK CRYSTAL OSCILLATOR CONNECTION The user can select the crystal oscillator to be the source of the slow clock, as it provides a more accurate frequency. The command is made by writing the Supply Controller Control Register (SUPC_CR) with the XTALSEL bit at 1. This results in a sequence which enables the crystal oscillator and then disables the RC oscillator to save power. The switch of the slow clock source is glitch free. The OSCSEL bit of the Supply Controller Status Register (SUPC_SR) tracks the oscillator frequency downstream. It must be read in order to be informed when the switch sequence, initiated when a new value is written in MOSCSEL bit of CKGR_MOR, is done. Coming back on the RC oscillator is only possible by shutting down the VDDBU power supply. If the user does not need the crystal oscillator, the XIN32 and XOUT32 pins can be left unconnected. The user can also set the crystal oscillator in bypass mode instead of connecting a crystal. In this case, the user has to provide the external clock signal on XIN32. The input characteristics of the XIN32 pin are given in the product electrical characteristics section. In order to set the bypass mode, the OSCBYPASS bit of the Supply Controller Mode Register (SUPC_MR) needs to be set at 1. The user can set the Slow Clock Crystal Oscillator in bypass mode instead of connecting a crystal. In this case, the user has to provide the external clock signal on XIN32. The input characteristics of the XIN32 pin under these conditions are given in the product electrical characteristics section. The programmer has to be sure to set the OSCBYPASS bit in the Supply Controller Mode Register (SUPC_MR) and XTALSEL bit in the Supply Controller Control Register (SUPC_CR).

27.5 Main Clock

Figure 27-3 shows the Main Clock block diagram. XIN32 XOUT32 GND 32,768 Hz Crystal

 2020 Microchip Technology Inc. DS60001614B-page 415 SAM3X8ERT FIGURE 27-3: MAIN CLOCK BLOCK DIAGRAM The Main Clock has two sources:

• 4/8/12 MHz Fast RC Oscillator which starts very quickly and is used at startup.
• 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator which can be bypassed. 27.5.1 4/8/12 MHZ FAST RC OSCILLATOR After reset, the 4/8/12 MHz Fast RC Oscillator is enabled with the 4 MHz frequency selected and it is selected as the source of MAINCK. MAINCK is the default clock selected to start up the system. The Fast RC Oscillator 8 and 12 MHz frequencies are calibrated in production. Note: It is not the case for the 4 MHz frequency. Refer to the “DC Characteristics” section of the product datasheet. The software can disable or enable the 4/8/12 MHz Fast RC Oscillator with the MOSCRCEN bit in the Clock Generator Main Oscillator Register (CKGR_MOR). The user can also select the output frequency of the Fast RC Oscillator, either 4 MHz, 8 MHz or 12 MHz are available. It can be done through MOSCRCF bits in CKGR_MOR. When changing this frequency selection, the MOSCRCS bit in the Power Management Controller Status Register (PMC_SR) is automatically cleared and MAINCK is stopped until the oscillator is stabilized. Once the oscillator is stabilized, MAINCK restarts and MOSCRCS is set. When disabling the Main Clock by clearing the MOSCRCEN bit in CKGR_MOR, the MOSCRCS bit in the Power Man- agement Controller Status Register (PMC_SR) is automatically cleared, indicating the Main Clock is off. Setting the MOSCRCS bit in the Power Management Controller Interrupt Enable Register (PMC_IER) can trigger an interrupt to the processor. It is recommended to disable the Main Clock as soon as the processor no longer uses it and runs out of SLCK, PLLACKor UPLLCK. XIN XOUT MOSCXTEN MOSCXTCNT MOSCXTS Main Clock Frequency Counter MAINF MAINRDY SLCK Slow Clock 3-20 MHz Crystal or Ceramic Resonator Oscillator 3-20 MHz Oscillator Counter MOSCRCEN 4/8/12 MHz Fast RC Oscillator MOSCRCS MOSCRCF MOSCRCEN MOSCXTEN MOSCSEL MOSCSEL MOSCSELS MAINCK Main Clock MAINCK Main Clock Ref.

DS60001614B-page 416  2020 Microchip Technology Inc. The CAL4, CAL8 and CAL12 values in the PMC Oscillator Calibration Register (PMC_OCR) are the default values set by Microchip during production. These values are stored in a specific Flash memory area different from the main mem- ory plane. These values cannot be modified by the user and cannot be erased by a Flash erase command or by the ERASE pin. Values written by the user's application in PMC_OCR are reset after each power up or peripheral reset. 27.5.2 3 TO 20 MHZ CRYSTAL OR CERAMIC RESONATOR-BASED OSCILLATOR After reset, the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator is disabled and it is not selected as the source of MAINCK. The user can select the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator to be the source of MAINCK, as it provides a more accurate frequency. The software enables or disables the main oscillator so as to reduce power con - sumption by clearing the MOSCXTEN bit in the Main Oscillator Register (CKGR_MOR). When disabling the main oscillator by clearing the MOSCXTEN bit in CKGR_MOR, the MOSCXTS bit in PMC_SR is automatically cleared, indicating the Main Clock is off. When enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to the startup time of the oscillator. This startup time depends on the crystal frequency connected to the oscillator. When the MOSCXTEN bit and the MOSCXTCNT are written in CKGR_MOR to enable the main oscillator, the XIN and XOUT pins are automatically switched into oscillator mode and MOSCXTS bit in the Power Management Controller Sta- tus Register (PMC_SR) is cleared and the counter starts counting down on the slow clock divided by 8 from the MOSCX- TCNT value. Since the MOSCXTCNT value is coded with 8 bits, the maximum startup time is about 62 ms. When the counter reaches 0, the MOSCXTS bit is set, indicating that the main clock is valid. Setting the MOSCXTS bit in PMC_IMR can trigger an interrupt to the processor.

27.5.3 MAIN CLOCK OSCILLATOR SELECTION

The user can select either the 4/8/12 MHz Fast RC oscillator or the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator to be the source of Main Clock. The advantage of the 4/8/12 MHz Fast RC oscillator is that it provides fast startup time, this is why it is selected by default (to start up the system) and when entering Wait Mode. The advantage of the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator is that it is very accurate. The selection is made by writing the MOSCSEL bit in the Main Oscillator Register (CKGR_MOR). The switch of the Main Clock source is glitch free, so there is no need to run out of SLCK, PLLACK or UPLLCK in order to change the selection. The MOSCSELS bit of the Power Management Controller Status Register (PMC_SR) allows knowing when the switch sequence is done. Setting the MOSCSELS bit in PMC_IMR can trigger an interrupt to the processor.

27.5.4 MAIN CLOCK FREQUENCY COUNTER

The device features a Main Clock frequency counter that provides the frequency of the Main Clock. The Main Clock frequency counter is reset and starts incrementing at the Main Clock speed after the next rising edge of the Slow Clock in the following cases:

• when the 4/8/12 MHz Fast RC oscillator clock is selected as the source of Main Clock and when this oscillator becomes stable (i.e., when the MOSCRCS bit is set)
• when the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator is selected as the source of Main Clock and when this oscillator becomes stable (i.e., when the MOSCXTS bit is set)
• when the Main Clock Oscillator selection is modified Then, at the 16th falling edge of Slow Clock, the MAINFRDY bit in the Clock Generator Main Clock Frequency Register (CKGR_MCFR) is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of Slow Clock, so that the frequency of the 4/8/12 MHz Fast RC oscillator or 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator can be determined.

27.6 Divider and PLL Block

The device features one Divider/PLL Block that permits a wide range of frequencies to be selected on either the master clock, the processor clock or the programmable clock outputs. Additionally, they provide a 48 MHz signal to the embed- ded USB device port regardless of the frequency of the main clock.

 2020 Microchip Technology Inc. DS60001614B-page 417 SAM3X8ERT Figure 27-4 shows the block diagram of the dividers and PLL blocks. FIGURE 27-4: DIVIDERS AND PLL BLOCK DIAGRAM

27.6.1 DIVIDER AND PHASE LOCK LOOP PROGRAMMING

The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the corre - sponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the cor- responding PLL input clock is set to 0. The PLL (PLLA) allows multiplication of the divider’s outputs. The PLL clock signal has a frequency that depends on the respective source signal frequency and on the parameters DIV (DIVA ) and MUL (MULA ). The factor applied to the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0, the PLL is disabled and its power consumption is saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field. Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK (LOCKA) bit in PMC_SR is automati- cally cleared. The values written in the PLLCOUNT field (PLLACOUNT) in CKGR_PLLR (CKGR_PLLAR) are loaded in the PLL counter. The PLL counter then decrements at the speed of the Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field. The PLL clock can be divided by 2 by writing the PLLDIV2 (PLLADIV2) bit in PMC Master Clock Register (PMC_MCKR). It is forbidden to change 4/8/12 MHz Fast RC oscillator, or main selection in CKGR_MOR register while Master clock source is PLL and PLL reference clock is the Fast RC oscillator. The user must:

• Switch on the Main RC oscillator by writing 1 in CSS field of PMC_MCKR.
• Change the frequency (MOSCRCF) or oscillator selection (MOSCSEL) in CKGR_MOR.
• Wait for MOSCRCS (if frequency changes) or MOSCSELS (if oscillator selection changes) in PMC_IER.
• Disable and then enable the PLL (LOCK in PMC_IDR and PMC_IER).
• Wait for PLLRDY .
• Switch back to PLL.

27.7 UTMI Phase Lock Loop Programming

The source clock of the UTMI PLL is the 3-20 MHz crystal oscillator. A 12 MHz crystal is needed to use the USB. Divider DIVA PLLA MULA PLLACOUNT LOCKA OUTA SLCK MAINCK PLLACK PLLA C ounter

DS60001614B-page 418  2020 Microchip Technology Inc. FIGURE 27-5: UTMI PLL BLOCK DIAGRAM Whenever the UTMI PLL is enabled by writing UPLLEN in CKGR_UCKR, the LOCKU bit in PMC_SR is automatically cleared. The values written in the PLLCOUNT field in CKGR_UCKR are loaded in the UTMI PLL counter. The UTMI PLL counter then decrements at the speed of the Slow Clock divided by 8 until it reaches 0. At this time, the LOCKU bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the UTMI PLL transient time into the PLLCOUNT field. UTMI PLL UPLLEN UPLLCOUNT LOCKUSLCK MAINCK UPLLCK UTMI PLL Counter

 2020 Microchip Technology Inc. DS60001614B-page 419 SAM3X8ERT

28.0 POWER MANAGEMENT CONTROLLER (PMC)

28.1 Description

The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Cortex-M3 Processor. The Supply Controller selects between the 32 kHz RC oscillator or the crystal oscillator. The unused oscillator is dis - abled automatically so that power consumption is optimized. By default, at startup the chip runs out of the Master Clock using the Fast RC oscillator running at 4 MHz. The user can trim the 8 and 12 MHz RC Oscillator frequencies by software.

28.2 Embedded Characteristics

The Power Management Controller provides the following clocks:

• MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the device. It is available to the modules running permanently, such as the Enhanced Embedded Flash Controller.
• Processor Clock (HCLK) is automatically switched off when the processor enters Sleep Mode.
• Free running processor Clock (FCLK)
• the Cortex-M3 SysTick external clock
• UDP Clock (UDPCK), required by USB Device Port operations.
• Peripheral Clocks, typically MCK, provided to the embedded peripherals (USART, SSC, SPI, TWI, TC, HSMCI, etc.) and independently controllable. Some of the peripherals can be configured to be driven by MCK divided by 2, 4.In order to reduce the number of clock names in a product, the Peripheral Clocks are named MCK in the product datasheet. Programmable Clock Outputs can be selected from the clocks provided by the clock generator and driven on the PCKx pins. The Power Management Controller also provides the following operations on clocks:
• a main crystal oscillator clock failure detector.
• a frequency counter on main clock .

DS60001614B-page 420  2020 Microchip Technology Inc.

28.3 Block Diagram

FIGURE 28-1: GENERAL CLOCK BLOCK DIAGRAM Power Management Controller Main Clock MAINCK PLLA Clock PLLACK ControlStatus 3-20 MHz Crystal or Ceramic Resonator Oscillator MOSCSEL Clock Generator PLLA and Divider /2 XIN XOUT XIN32 XOUT32 Slow Clock SLCK XTALSEL (Supply Controller) Embedded 32 kHz RC Oscillator 32768 Hz Crystal Oscillator UPLL Clock UPLLCK MCK periph_clk[..] int SLCK MAINCK PLLACK Prescaler /1,/2,/3,/4,/8, /16,/32,/64 HCLK Processor Clock Controller Sleep Mode Master Clock Controller (PMC_MCKR) Peripherals Clock Controller (PMC_PCERx) ON/OFF USB FS Clock Prescaler /1,/2,/4,/8, /16,/32,/64 pck[..] ON/OFF FCLK SysTick Divider SLCK MAINCK PLLACK UPLLCK/2 Processor clock Free running clock Master clock USB UTMI PLL Embedded 4/8/12 MHz Fast RC Oscillator Programmable Clock Controller (PMC_PCKx) PRES PLLADIV2 PRESCSS CSS Divider /1, /2 USB_48M UPLLDIV Divider /1,/2,/3,...,/16 USB Clock Controller (PMC_USB) USBDIVUSBS ON/OFF UPLLCK/2 USB_480M USB HS Clock PLLACK UPLLCK/2 MCK

 2020 Microchip Technology Inc. DS60001614B-page 421 SAM3X8ERT FIGURE 28-2: PERIPHERAL CLOCK DIVIDER BLOCK DIAGRAM

28.4 Master Clock Controller

The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all the peripherals. The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock saves power consumption of the PLLs. The Master Clock Controller is made up of a clock selector and a prescaler. The Master Clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the selected clock between 1 and 64, and the division by 3. The PRES field in PMC_MCKR programs the prescaler. Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done. FIGURE 28-3: MASTER CLOCK CONTROLLER

28.5 Processor Clock Controller

The PMC features a Processor Clock Controller (HCLK) that implements the Processor Sleep Mode. The Processor Clock can be disabled by executing the WFI (WaitForInterrupt) or the WFE (WaitForEvent) processor instruction while the LPM bit is at 0 in the PMC Fast Startup Mode Register (PMC_FSMR). The Processor Clock HCLK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The Pro- cessor Sleep Mode is achieved by disabling the Processor Clock, which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product. MCK periph_clk[n] int SLCK MAINCK PLLACK Prescaler /1,/2,/3,/4,/8, /16,/32,/64 HCLK Processor Clock Controller Sleep Mode Master Clock Controller (PMC_MCKR) Peripherals Clock Controller (PMC_PCERx) PLLBCK Processor clock c Master clock PRESCSS ON/OFF ON/OFF ON/OFF periph_clk[n+1] periph_clk[n+2] Peripherals Control Register (PMC_PCR) DIV(PID = n+1) DIV(PID = n+2) Divider /2, /4 MCK MCK div4 div2 div4 div2 div4 div2 SLCK Master Clock Prescaler MCK PRESCSS MAINCK PLLACK UPLLCK/2 To the Processor Clock Controller (PCK) PMC_MCKR PMC_MCKR

DS60001614B-page 422  2020 Microchip Technology Inc. When Processor Sleep Mode is entered, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus.

28.6 SysTick Clock

The SysTick calibration value is fixed to 10500 which allows the generation of a time base of 1 ms with SysTick clock to the maximum frequency on MCK divided by 8.

28.7 Peripheral Clock Controller

The Power Management Controller controls the clocks of each embedded peripheral by means of the Peripheral Clock Controller. The user can individually enable and disable the Clock on the peripherals. The user can also enable and disable these clocks by writing Peripheral Clock Enable 0 (PMC_PCER0), Peripheral Clock Disable 0 (PMC_PCDR0), Peripheral Clock Enable 1 (PMC_PCER1) and Peripheral Clock Disable 1 (PMC_PC- DR1) registers . The status of the peripheral clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR0) and Peripheral Clock Status Register (PMC_PCSR1). When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically disabled after a reset. In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system. The bit number within the Peripheral Clock Control registers (PMC_PCER0-1, PMC_PCDR0-1, and PMC_PCSR0-1) is the Peripheral Identifier defined at the product level. The bit number corresponds to the interrupt source number assigned to the peripheral. In order to save power consumption, the clock of CAN0, CAN1 peripherals can be MCK divided by a division factor of 1, 2, 4. This is done by setting the PMC_PCR register. It features a command and acts like a mailbox. To write the division factor, the user needs to write a WRITE command, the peripheral ID and the chosen division factor. To read the current division factor, the user just needs to write the READ command and the peripheral ID. Then a read access on PMC_PCR must be performed. DIV must not be changed while peripheral is in use or when the peripheral clock is enabled.To change the clock division factor (DIV) of a peripheral, its clock must first be disabled by writing either EN to 0 for the corresponding PID (DIV must be kept the same if this method is used), or writing to PMC_PCDR register. Then a second write must be performed into PMC_PCR with the new value of DIV and a third write must be performed to enable the peripheral clock (either by using PMC_PCR or PMC_PCER register). Code Example to select divider 4 for peripheral index 43 (0x2B) and enable its clock: write_register(PMC_PCR,0x1002102B) Code Example to read the divider of the same peripheral: write_register(PMC_PCR,0x0000002B) read_register(PMC_PCR)

28.8 Free Running Processor Clock

The Free Running Processor Clock (FCLK) used for sampling interrupts and clocking debug blocks ensures that inter- rupts can be sampled, and sleep events can be traced, while the processor is sleeping. It is connected to Master Clock (MCK).

28.9 Programmable Clock Output Controller

The PMC controls 3 signals to be output on external pins, PCKx. Each signal can be independently programmed via the Programmable Clock Registers (PMC_PCKx). PCKx can be independently selected between the Slow Clock (SLCK), the Main Clock (MAINCK), the PLLA Clock (PLLACK), UTMI PLL Clock (UPLLCK/2) and the Master Clock (MCK) by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx.

 2020 Microchip Technology Inc. DS60001614B-page 423 SAM3X8ERT Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of PMC_SCSR (System Clock Status Register). Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actually what has been pro- grammed in the Programmable Clock registers. As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly rec- ommended to disable the Programmable Clock before any configuration change and to re-enable it after the change is actually performed.

28.10 Fast Startup

The device allows the processor to restart in less than 10 microseconds while the device is in Wait mode. The system enters Wait mode by executing the WaitForEvent (WFE) instruction of the processor while the LPM bit is at 1 in the PMC Fast Startup Mode Register (PMC_FSMR). Important: Prior to asserting any WFE instruction to the processor, the internal sources of wakeup provided by RTT, RTC and USB must be cleared and verified too, that none of the enabled external wakeup inputs (WKUP) hold an active polarity. A Fast Startup is enabled upon the detection of a programmed level on one of the 16 wake-up inputs (WKUP) or upon an active alarm from the RTC, RTT and USB Controller. The polarity of the 16 wake-up inputs is programmable by writ- ing the PMC Fast Startup Polarity Register (PMC_FSPR). The Fast Restart circuitry, as shown in Figure 28-4, is fully asynchronous and provides a fast startup signal to the Power Management Controller. As soon as the fast startup signal is asserted, the embedded 4/8/12 MHz Fast RC oscillator restarts automatically. FIGURE 28-4: FAST STARTUP CIRCUITRY Each wake-up input pin and alarm can be enabled to generate a Fast Startup event by writing 1 to the corresponding bit in the Fast Startup Mode Register PMC_FSMR. fast_restartWKUP15 FSTT15 FSTP15 WKUP1 FSTT1 FSTP1 WKUP0 FSTT0 FSTP0 RTTAL RTCAL USBAL RTT Alarm RTC Alarm USB Alarm

DS60001614B-page 424  2020 Microchip Technology Inc. The user interface does not provide any status for Fast Startup, but the user can easily recover this information by read- ing the PIO Controller, and the status registers of the RTC, RTT and USB Controller.

28.11 Main Crystal Clock Failure Detector

The clock failure detector monitors the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator to identify an even- tual defect of this oscillator (for example, if the crystal is unconnected). The clock failure detector can be enabled or disabled by means of the CFDEN bit in the PMC Clock Generator Main Oscillator Register (CKGR_MOR). After reset, the detector is disabled. However, if the 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator is disabled, the clock failure detector is disabled too. A failure is detected by means of a counter incrementing on the 3 to 20 MHz Crystal oscillator or Ceramic Resonator- based oscillator clock edge and timing logic clocked on the slow clock RC oscillator controlling the counter. The counter is cleared when the slow clock RC oscillator signal is low and enabled when the slow clock RC oscillator is high. Thus the failure detection time is 1 slow clock RC oscillator clock period. If, during the high level period of the slow clock RC oscillator, less than 8 fast crystal oscillator clock periods have been counted, then a failure is declared. If a failure of the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator clock is detected, the CFDEV flag is set in the PMC Status Register (PMC_SR), and generates an interrupt if it is not masked. The interrupt remains active until a read operation in the PMC_SR register. The user can know the status of the clock failure detector at any time by reading the CFDS bit in the PMC_SR register. If the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator clock is selected as the source clock of MAINCK (MOSCSEL = 1), and if the Master Clock Source is PLLACK or UPLLCK (CSS = 2 or 3), a clock failure detection auto- matically forces MAINCK to be the source clock for the master clock (MCK).Then, regardless of the PMC configuration, a clock failure detection automatically forces the 4/8/12 MHz Fast RC oscillator to be the source clock for MAINCK. If the Fast RC oscillator is disabled when a clock failure detection occurs, it is automatically re-enabled by the clock failure detection mechanism. It takes 2 slow clock RC oscillator cycles to detect and switch from the 3 to 20 MHz Crystal, or Ceramic Resonator-based oscillator, to the 4/8/12 MHz Fast RC Oscillator if the Master Clock source is Main Clock, or 3 slow clock RC oscillator cycles if the Master Clock source is PLLACK or UPLLCK. A clock failure detection activates a fault output that is connected to the Pulse Width Modulator (PWM) Controller. With this connection, the PWM controller is able to force its outputs and to protect the driven device, if a clock failure is detected. This fault output remains active until the defect is detected and until it is cleared by the bit FOCLR in the PMC Fault Output Clear Register (PMC_FOCR). The user can know the status of the fault output at any time by reading the FOS bit in the PMC_SR register.

28.12 Programming Sequence

1. Enabling the Main Oscillator: The main oscillator is enabled by setting the MOSCXTEN field in the Main Oscillator Register (CKGR_MOR). The user can define a start-up time. This can be achieved by writing a value in the MOSCXTST field in CKGR_MOR. Once this register has been correctly configured, the user must wait for MOSCXTS field in the PMC_SR register to be set. This can be done either by polling the status register, or by waiting the interrupt line to be raised if the associated interrupt to MOSCXTS has been enabled in the PMC_IER register. Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles. The main oscillator will be enabled (MOSCXTS bit set) after 56 Slow Clock Cycles. 2. Checking the Main Oscillator Frequency (Optional): In some situations the user may need an accurate measure of the main clock frequency. This measure can be accomplished via the Main Clock Frequency Register (CKGR_MCFR). Once the MAINFRDY field is set in CKGR_MCFR, the user may read the MAINF field in CKGR_MCFR. This pro- vides the number of main clock cycles within sixteen slow clock cycles. 3. Setting PLL and Divider: All parameters needed to configure PLLA and the divider are located in CKGR_PLLAR. The DIV field is used to control the divider itself. It must be set to 1 when PLL is used. By default, DIV parameter is set to 0 which means that the divider is turned off. The MUL field is the PLL multiplier factor. This parameter can be programmed between 0 and 2047. If MUL is set to 0, PLL will be turned off, otherwise the PLL output frequency is PLL input frequency multiplied by (MUL + 1).

 2020 Microchip Technology Inc. DS60001614B-page 425 SAM3X8ERT The PLLCOUNT field specifies the number of slow clock cycles before the LOCK bit is set in PMC_SR, after CKGR_PLLAR has been written. Once the CKGR_PLL register has been written, the user must wait for the LOCK bit to be set in the PMC_SR. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to LOCK has been enabled in PMC_IER. All parameters in CKGR_PLLAR can be programmed in a sin- gle write operation. If at some stage one of the following parameters, MUL or DIV is modified, the LOCK bit will go low to indicate that PLL is not ready yet. When PLL is locked, LOCK will be set again. The user is constrained to wait for LOCK bit to be set before using the PLL output clock. 4. Selection of Master Clock and Processor Clock The Master Clock and the Processor Clock are configurable via the Master Clock Register (PMC_MCKR). The CSS field is used to select the Master Clock divider source. By default, the selected clock source is main clock. The PRES field is used to control the Master Clock prescaler. The user can choose between different values (1, 2, 3, 4, 8, 16, 32, 64). Master Clock output is prescaler input divided by PRES parameter. By default, PRES parameter is set to 1 which means that master clock is equal to main clock. Once PMC_MCKR has been written, the user must wait for the MCKRDY bit to be set in PMC_SR. This can be done either by polling the status register or by waiting for the interrupt line to be raised if the associated interrupt to MCKRDY has been enabled in the PMC_IER register. The PMC_MCKR must not be programmed in a single write operation. The preferred programming sequence for PMC_MCKR is as follows: - If a new value for CSS field corresponds to PLL Clock,

• Program the PRES field in PMC_MCKR.
• Wait for the MCKRDY bit to be set in PMC_SR.
• Program the CSS field in PMC_MCKR.
• Wait for the MCKRDY bit to be set in PMC_SR. - If a new value for CSS field corresponds to Main Clock or Slow Clock,
• Program the CSS field in PMC_MCKR.
• Wait for the MCKRDY bit to be set in the PMC_SR.
• Program the PRES field in PMC_MCKR.
• Wait for the MCKRDY bit to be set in PMC_SR. If at some stage one of the following parameters, CSS or PRES is modified, the MCKRDY bit will go low to indicate that the Master Clock and the Processor Clock are not ready yet. The user must wait for MCKRDY bit to be set again before using the Master and Processor Clocks. Note: IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLR, the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again, LOCK goes high and MCK- RDY is set. While PLL is unlocked, the Master Clock selection is automatically changed to Slow Clock. For further infor- mation, see “Clock Switching Waveforms” on page 428. Code Example: write_register(PMC_MCKR,0x00000001) wait (MCKRDY=1) write_register(PMC_MCKR,0x00000011) wait (MCKRDY=1) The Master Clock is main clock divided by 2. The Processor Clock is the Master Clock. 5. Selection of Programmable Clocks Programmable clocks are controlled via registers, PMC_SCER, PMC_SCDR and PMC_SCSR. Programmable clocks can be enabled and/or disabled via PMC_SCER and PMC_SCDR. 3 Programmable clocks can be enabled or disabled. The PMC_SCSR provides a clear indication as to which Programmable clock is enabled. By default all Programmable clocks are disabled. Programmable Clock Registers (PMC_PCKx) are used to configure Programmable clocks. The CSS field is used to select the Programmable clock divider source. Four clock options are available: main clock, slow clock, PLLACK, UPLLCK. By default, the clock source selected is slow clock. The PRES field is used to control the Programmable clock prescaler. It is possible to choose between different

DS60001614B-page 426  2020 Microchip Technology Inc. values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES parameter. By default, the PRES parameter is set to 0 which means that master clock is equal to slow clock. Once PMC_PCKx has been programmed, The corresponding Programmable clock must be enabled and the user is constrained to wait for the PCKRDYx bit to be set in PMC_SR. This can be done either by polling the status register or by waiting the interrupt line to be raised, if the associated interrupt to PCKRDYx has been enabled in the PMC_IER register. All parameters in PMC_PCKx can be programmed in a single write operation. If the CSS and PRES parameters are to be modified, the corresponding Programmable clock must be disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the Programmable clock and wait for the PCKRDYx bit to be set. 6. Enabling Peripheral Clocks Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers PMC_PCER0, PMC_PCER, PMC_PCDR0 and PMC_PCDR.

 2020 Microchip Technology Inc. DS60001614B-page 427 SAM3X8ERT

28.13 Clock Switching Details

28.13.0.1 Master Clock Switching Timings

Table 0-2 and Table 0-3 give the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the newly selected clock has to be added. Note 1: PLL designates either the PLLA or the UPLL clock. 2: PLLCOUNT designates either PLLACOUNT or UPLLCOUNT. Table 0-2. Clock Switching Timings (Worst Case) To From Main Clock SLCK PLL Clock Main Clock — 4 x SLCK + 2.5 x Main Clock 3 x PLL Clock + 4 x SLCK + 1 x Main Clock SLCK 0.5 x Main Clock + 4.5 x SLCK — 3 x PLL Clock + 5 x SLCK PLL Clock 0.5 x Main Clock + 4 x SLCK + PLLCOUNT x SLCK + 2.5 x PLLx Clock 2.5 x PLL Clock + 5 x SLCK + PLLCOUNT x SLCK 2.5 x PLL Clock + 4 x SLCK + PLLCOUNT x SLCK Table 0-3. Clock Switching Timings between Two PLLs (Worst Case) To From PLLA Clock UPLL Clock PLLA Clock 2.5 x PLLA Clock + 4 x SLCK + PLLACOUNT x SLCK 3 x PLLA Clock + 4 x SLCK + 1.5 x PLLA Clock UPLL Clock 3 x UPLL Clock + 4 x SLCK + 1.5 x UPLL Clock 2.5 x UPLL Clock + 4 x SLCK + x SLCK

DS60001614B-page 428  2020 Microchip Technology Inc.

28.13.0.2 Clock Switching Waveforms

FIGURE 28-5: SWITCH MASTER CLOCK FROM SLOW CLOCK TO PLLX CLOCK FIGURE 28-6: SWITCH MASTER CLOCK FROM MAIN CLOCK TO SLOW CLOCK Slow Clock LOCK MCKRDY Master Clock Write PMC_MCKR PLLx Clock Slow Clock Main Clock MCKRDY Master Clock Write PMC_MCKR

 2020 Microchip Technology Inc. DS60001614B-page 429 SAM3X8ERT FIGURE 28-7: CHANGE PLLX PROGRAMMING FIGURE 28-8: PROGRAMMABLE CLOCK OUTPUT PROGRAMMING

28.14 Write Protection Registers

To prevent any single software error that may corrupt PMC behavior, certain address spaces can be write protected by setting the WPEN bit in the “PMC Write Protect Mode Register” on page 452 (PMC_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the PMC Write Protect Status Register (PMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. Slow Clock Slow Clock PLLx Clock LOCKx MCKRDY Master Clock Write CKGR_PLLxR PLLx Clock PCKRDY PCKx Output Write PMC_PCKx Write PMC_SCER Write PMC_SCDR PCKx is disabled PCKx is enabled PLL Clock is selected

DS60001614B-page 430  2020 Microchip Technology Inc. The WPVS flag is reset by writing the PMC Write Protect Mode Register (PMC_WPMR) with the appropriate access key, WPKEY . The protected registers are:

• “PMC System Clock Enable Register” on page 432
• “PMC System Clock Disable Register” on page 433
• “PMC Peripheral Clock Enable Register 0” on page 434
• “PMC Peripheral Clock Disable Register 0” on page 435
• “PMC Clock Generator Main Oscillator Register” on page 438
• “PMC Clock Generator PLLA Register” on page 439
• “PMC UTMI Clock Configuration Register” on page 437
• “PMC Master Clock Register” on page 441
• “PMC USB Clock Register” on page 442
• “PMC Programmable Clock Register” on page 443
• “PMC Fast Startup Mode Register” on page 449
• “PMC Fast Startup Polarity Register” on page 450
• “PMC Peripheral Clock Enable Register 1” on page 454
• “PMC Peripheral Clock Disable Register 1” on page 454

 2020 Microchip Technology Inc. DS60001614B-page 431 SAM3X8ERT

28.15 Power Management Controller (PMC) User Interface

Note: If an offset is not listed in the table it must be considered as “reserved”. TABLE 28-1: REGISTER MAPPING Offset Register Name Access Reset 0x0000 System Clock Enable Register PMC_SCER Write-only — 0x0004 System Clock Disable Register PMC_SCDR Write-only — 0x0008 System Clock Status Register PMC_SCSR Read-only 0x0000_0001 0x000C Reserved — — — 0x0010 Peripheral Clock Enable Register 0 PMC_PCER0 Write-only — 0x0014 Peripheral Clock Disable Register 0 PMC_PCDR0 Write-only — 0x0018 Peripheral Clock Status Register 0 PMC_PCSR0 Read-only 0x0000_0000 0x001C UTMI Clock Register CKGR_UCKR Read-write 0x1020_0800 0x0020 Main Oscillator Register CKGR_MOR Read-write 0x0000_0001 0x0024 Main Clock Frequency Register CKGR_MCFR Read-only 0x0000_0000 0x0028 PLLA Register CKGR_PLLAR Read-write 0x0000_3F00 0x002C Reserved — — — 0x0030 Master Clock Register PMC_MCKR Read-write 0x0000_0001 0x0034 Reserved — — — 0x0038 USB Clock Register PMC_USB Read/Write 0x0000_0000 0x003C Reserved — — — 0x0040 Programmable Clock 0 Register PMC_PCK0 Read-write 0x0000_0000 0x0044 Programmable Clock 1 Register PMC_PCK1 Read-write 0x0000_0000 0x0048 Programmable Clock 2 Register PMC_PCK2 Read-write 0x0000_0000 0x004C - 0x005C Reserved — — — 0x0060 Interrupt Enable Register PMC_IER Write-only — 0x0064 Interrupt Disable Register PMC_IDR Write-only — 0x0068 Status Register PMC_SR Read-only 0x0001_0008 0x006C Interrupt Mask Register PMC_IMR Read-only 0x0000_0000 0x0070 Fast Startup Mode Register PMC_FSMR Read-write 0x0000_0000 0x0074 Fast Startup Polarity Register PMC_FSPR Read-write 0x0000_0000 0x0078 Fault Output Clear Register PMC_FOCR Write-only — 0x007C- 0x00E0 Reserved — — — 0x00E4 Write Protect Mode Register PMC_WPMR Read-write 0x0 0x00E8 Write Protect Status Register PMC_WPSR Read-only 0x0 0x00EC- 0x00FC Reserved — — — 0x0100 Peripheral Clock Enable Register 1 PMC_PCER1 Write-only — 0x0104 Peripheral Clock Disable Register 1 PMC_PCDR1 Write-only — 0x0108 Peripheral Clock Status Register 1 PMC_PCSR1 Read-only 0x0000_0000 0x010C Peripheral Control Register PMC_PCR Read-write 0x0000_0000

DS60001614B-page 432  2020 Microchip Technology Inc.

28.15.1 PMC SYSTEM CLOCK ENABLE REGISTER

Name:PMC_SCER Address:0x400E0600 Access:Write-only This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 452.

• UOTGCLK: Enable USB OTG Clock (48 MHz, USB_48M) for UTMI Enable only when UOTGHS module is in low-power mode (SPDCONF =1). 0 = No effect. 1 = Enable USB_48M (to use if SPDCONF =1).
• PCKx: Programmable Clock x Output Enable 0 = No effect. 1 = Enables the corresponding Programmable Clock output. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

 2020 Microchip Technology Inc. DS60001614B-page 433 SAM3X8ERT

28.15.2 PMC SYSTEM CLOCK DISABLE REGISTER

Name:PMC_SCDR Address:0x400E0604 Access:Write-only This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 452.

• UOTGCLK: Disable USB OTG Clock (48 MHz, USB_48M) for UTMI Enable only when UOTGHS module is in low-power mode (SPDCONF =1). 0: No effect. 1: Disable USB_48M (to use if SPDCONF =1).
• PCKx: Programmable Clock x Output Disable 0 = No effect. 1 = Disables the corresponding Programmable Clock output. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DS60001614B-page 434  2020 Microchip Technology Inc.

28.15.3 PMC SYSTEM CLOCK STATUS REGISTER

Name:PMC_SCSR Address:0x400E0608 Access:Read-only

• UOTGCLK: USB OTG Clock (48 MHz, USB_48M) Clock Status 0 = The 48 MHz clock (UOTGCK) of the USB OTG FS Port is disabled. 1 = The 48 MHz clock (UOTGCK) of the USB OTG FS Port is enabled.
• PCKx: Programmable Clock x Output Status 0 = The corresponding Programmable Clock output is disabled. 1 = The corresponding Programmable Clock output is enabled.

28.15.4 PMC PERIPHERAL CLOCK ENABLE REGISTER 0

Name: PMC_PCER0 Address:0x400E0610 Access:Write-only This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 452.

• PIDx: Peripheral Clock x Enable 0 = No effect. 1 = Enables the corresponding peripheral clock. Note: To get PIDx, refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. Other peripherals can be enabled in PMC_PCER1 ( “PMC Peripheral Clock Enable Register 1” on page 454). Note: Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 — —

 2020 Microchip Technology Inc. DS60001614B-page 435 SAM3X8ERT

28.15.5 PMC PERIPHERAL CLOCK DISABLE REGISTER 0

Name:PMC_PCDR0 Address:0x400E0614 Access:Write-only This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 452.

• PIDx: Peripheral Clock x Disable 0 = No effect. 1 = Disables the corresponding peripheral clock. Note: To get PIDx, refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. Other peripherals can be disabled in PMC_PCDR1 ( “PMC Peripheral Clock Disable Register 1” on page 454). 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 — —

DS60001614B-page 436  2020 Microchip Technology Inc.

28.15.6 PMC PERIPHERAL CLOCK STATUS REGISTER 0

Name:PMC_PCSR0 Address:0x400E0618 Access:Read-only

• PIDx: Peripheral Clock x Status 0 = The corresponding peripheral clock is disabled. 1 = The corresponding peripheral clock is enabled. Note: To get PIDx, refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. Other peripherals status can be read in PMC_PCSR1 (“PMC Peripheral Clock Status Register 1” on page 454). 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 — —

 2020 Microchip Technology Inc. DS60001614B-page 437 SAM3X8ERT

28.15.7 PMC UTMI CLOCK CONFIGURATION REGISTER

Name:CKGR_UCKR Address:0x400E061C Access:Read-write This register can only be written if the WPEN bit is cleared in the “PMC Write Protect Mode Register” on page 452.

• UPLLEN: UTMI PLL Enable 0: The UTMI PLL is disabled. 1: The UTMI PLL is enabled. When UPLLEN is set, the LOCKU flag is set once the UTMI PLL startup time is achieved.
• UPLLCOUNT: UTMI PLL Start-up Time Specifies the number of Slow Clock cycles multiplied by 8 for the UTMI PLL start-up time. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UPLLCOUNT — — — UPLLEN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DS60001614B-page 438  2020 Microchip Technology Inc.

28.15.8 PMC CLOCK GENERATOR MAIN OSCILLATOR REGISTER

Name:CKGR_MOR Address:0x400E0620 Access:Read-write This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 452.

• KEY: Password Should be written at value 0x37. Writing any other value in this field aborts the write operation.
• MOSCXTEN: Main Crystal Oscillator Enable A crystal must be connected between XIN and XOUT. 0 = The Main Crystal Oscillator is disabled. 1 = The Main Crystal Oscillator is enabled. MOSCXTBY must be set to 0. When MOSCXTEN is set, the MOSCXTS flag is set once the Main Crystal Oscillator startup time is achieved.
• MOSCXTBY: Main Crystal Oscillator Bypass 0 = No effect. 1 = The Main Crystal Oscillator is bypassed. MOSCXTEN must be set to 0. An external clock must be connected on XIN. When MOSCXTBY is set, the MOSCXTS flag in PMC_SR is automatically set. Clearing MOSCXTEN and MOSCXTBY bits allows resetting the MOSCXTS flag.
• MOSCRCEN: Main On-Chip RC Oscillator Enable 0 = The Main On-Chip RC Oscillator is disabled. 1 = The Main On-Chip RC Oscillator is enabled. When MOSCRCEN is set, the MOSCRCS flag is set once the Main On-Chip RC Oscillator startup time is achieved.
• MOSCRCF: Main On-Chip RC Oscillator Frequency Selection At start-up, the Main On-Chip RC Oscillator frequency is 4 MHz.
• MOSCXTST: Main Crystal Oscillator Start-up Time Specifies the number of Slow Clock cycles multiplied by 8 for the Main Crystal Oscillator start-up time.
• MOSCSEL: Main Oscillator Selection 0 = The Main On-Chip RC Oscillator is selected. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEY 15 14 13 12 11 10 9 8 MOSCXTST 7 6 5 4 3 2 1 0 — MOSCRCF MOSCRCEN — MOSCXTBY MOSCXTEN Value Name Description 0x0 4_MHz The Fast RC Oscillator Frequency is at 4 MHz (default) 0x1 8_MHz The Fast RC Oscillator Frequency is at 8 MHz 0x2 12_MHz The Fast RC Oscillator Frequency is at 12 MHz

 2020 Microchip Technology Inc. DS60001614B-page 439 SAM3X8ERT 1 = The Main Crystal Oscillator is selected.

• CFDEN: Clock Failure Detector Enable 0 = The Clock Failure Detector is disabled. 1 = The Clock Failure Detector is enabled.

28.15.9 PMC CLOCK GENERATOR MAIN CLOCK FREQUENCY REGISTER

Name:CKGR_MCFR Address:0x400E0624 Access:Read-only This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 452.

• MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods.
• MAINFRDY: Main Clock Ready 0 = MAINF value is not valid or the Main Oscillator is disabled . 1 = The Main Oscillator has been enabled previously and MAINF value is available.

28.15.10 PMC CLOCK GENERATOR PLLA REGISTER

Name:CKGR_PLLAR Address:0x400E0628 Access:Read-write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 MAINF 7 6 5 4 3 2 1 0 MAINF 31 30 29 28 27 26 25 24 — — ONE — — MULA 23 22 21 20 19 18 17 16 MULA 15 14 13 12 11 10 9 8 — — PLLACOUNT 7 6 5 4 3 2 1 0 DIVA

DS60001614B-page 440  2020 Microchip Technology Inc. Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register. This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 452.

• DIVA: Divider
• PLLACOUNT: PLLA Counter Specifies the number of Slow Clock cycles x8 before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
• MULA: PLLA Multiplier 0 = The PLLA is deactivated. 1 up to 2047 = The PLLA Clock frequency is the PLLA input frequency multiplied by MULA + 1.
• ONE: Must Be Set to 1 Bit 29 must always be set to 1 when programming the CKGR_PLLAR register. DIVA Divider Selected

0 Divider output is 0

1 Divider is bypassed (DIVA=1)

2 - 255 Divider output is DIVA

 2020 Microchip Technology Inc. DS60001614B-page 441 SAM3X8ERT

28.15.11 PMC MASTER CLOCK REGISTER

Name:PMC_MCKR Address:0x400E0630 Access:Read-write This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 452.

• CSS: Master Clock Source Selection
• PRES: Processor Clock Prescaler
• PLLADIV2: PLLA Divisor by 2
• UPLLDIV2:UPLLDivisor by 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — PRES — — CSS Value Name Description

0 SLOW_CLK Slow Clock is selected

1 MAIN_CLK Main Clock is selected

2 PLLA_CLK PLLA Clock is selected

3 UPLL_CLK UPLL Clock is selected

0 CLK Selected clock

1 CLK_2 Selected clock divided by 2

2 CLK_4 Selected clock divided by 4

3 CLK_8 Selected clock divided by 8

4 CLK_16 Selected clock divided by 16

5 CLK_32 Selected clock divided by 32

6 CLK_64 Selected clock divided by 64

7 CLK_3 Selected clock divided by 3

PLLADIV2 PLLA Clock Division 0 PLLA clock frequency is divided by 1. 1 PLLA clock frequency is divided by 2. UPLLDIV2 UPLL Clock Division 0 UPLL clock frequency is divided by 1. 1 UPLL clock frequency is divided by 2.

DS60001614B-page 442  2020 Microchip Technology Inc.

28.15.12 PMC USB CLOCK REGISTER

Name:PMC_USB Address:0x400E0638 Access:Read-write This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 452.

• USBS: USB Input Clock Selection 0 = USB Clock Input is PLLA. 1 = USB Clock Input is PLLB.
• USBDIV: Divider for USB Clock. USB Clock is Input clock divided by USBDIV+1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — — — — USBDIV 7 6 5 4 3 2 1 0

 2020 Microchip Technology Inc. DS60001614B-page 443 SAM3X8ERT

28.15.13 PMC PROGRAMMABLE CLOCK REGISTER

Name:PMC_PCKx Address:0x400E0640 Access:Read-write This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 452.

• CSS: Master Clock Source Selection
• PRES: Programmable Clock Prescaler 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — PRES — CSS Value Name Description

4 MCK Master Clock is selected

DS60001614B-page 444  2020 Microchip Technology Inc.

28.15.14 PMC INTERRUPT ENABLE REGISTER

Name:PMC_IER Address:0x400E0660 Access:Write-only

• MOSCXTS: Main Crystal Oscillator Status Interrupt Enable
• LOCKA: PLLA Lock Interrupt Enable
• MCKRDY: Master Clock Ready Interrupt Enable
• LOCKU: UTMI PLL Lock Interrupt Enable
• PCKRDYx: Programmable Clock Ready x Interrupt Enable
• MOSCSELS: Main Oscillator Selection Status Interrupt Enable
• MOSCRCS: Main On-Chip RC Status Interrupt Enable
• CFDEV: Clock Failure Detector Event Interrupt Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — — CFDEV MOSCRCS MOSCSEL S 15 14 13 12 11 10 9 8 — — — — — PCKRDY2 PCKRDY1 PCKRDY0 7 6 5 4 3 2 1 0 — LOCKU– — — MCKRDY — LOCKA MOSCXTS

 2020 Microchip Technology Inc. DS60001614B-page 445 SAM3X8ERT

28.15.15 PMC INTERRUPT DISABLE REGISTER

Name:PMC_IDR Address:0x400E0664 Access:Write-only

• MOSCXTS: Main Crystal Oscillator Status Interrupt Disable
• LOCKA: PLLA Lock Interrupt Disable
• MCKRDY: Master Clock Ready Interrupt Disable
• LOCKU: UTMI PLL Lock Interrupt Disable
• PCKRDYx: Programmable Clock Ready x Interrupt Disable
• MOSCSELS: Main Oscillator Selection Status Interrupt Disable
• MOSCRCS: Main On-Chip RC Status Interrupt Disable
• CFDEV: Clock Failure Detector Event Interrupt Disable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — — CFDEV MOSCRCS MOSCSELS 15 14 13 12 11 10 9 8 — — — — — PCKRDY2 PCKRDY1 PCKRDY0 7 6 5 4 3 2 1 0 — LOCKU– — — MCKRDY — LOCKA MOSCXTS

DS60001614B-page 446  2020 Microchip Technology Inc.

28.15.16 PMC STATUS REGISTER

Name:PMC_SR Address:0x400E0668 Access:Read-only

• MOSCXTS: Main XTAL Oscillator Status 0 = Main XTAL oscillator is not stabilized. 1 = Main XTAL oscillator is stabilized.
• LOCKA: PLLA Lock Status 0 = PLLA is not locked 1 = PLLA is locked.
• MCKRDY: Master Clock Status 0 = Master Clock is not ready. 1 = Master Clock is ready.
• LOCKU: UTMI PLL Lock Status 0 = UTMI PLL is not locked 1 = UTMI PLL is locked.
• OSCSELS: Slow Clock Oscillator Selection 0 = Internal slow clock RC oscillator is selected. 1 = External slow clock 32 kHz oscillator is selected.
• PCKRDYx: Programmable Clock Ready Status 0 = Programmable Clock x is not ready. 1 = Programmable Clock x is ready.
• MOSCSELS: Main Oscillator Selection Status 0 = Selection is done. 1 = Selection is in progress.
• MOSCRCS: Main On-Chip RC Oscillator Status 0 = Main on-chip RC oscillator is not stabilized. 1 = Main on-chip RC oscillator is stabilized.
• CFDEV: Clock Failure Detector Event 0 = No clock failure detection of the main on-chip RC oscillator clock has occurred since the last read of PMC_SR. 1 = At least one clock failure detection of the main on-chip RC oscillator clock has occurred since the last read of PMC_SR.
• CFDS: Clock Failure Detector Status 0 = A clock failure of the main on-chip RC oscillator clock is not detected. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — FOS CFDS CFDEV MOSCRCS MOSCSEL S 15 14 13 12 11 10 9 8 — — — — — PCKRDY2 PCKRDY1 PCKRDY0 7 6 5 4 3 2 1 0 OSCSELS LOCKU– — — MCKRDY — LOCKA MOSCXTS

 2020 Microchip Technology Inc. DS60001614B-page 447 SAM3X8ERT 1 = A clock failure of the main on-chip RC oscillator clock is detected.

• FOS: Clock Failure Detector Fault Output Status 0 = The fault output of the clock failure detector is inactive. 1 = The fault output of the clock failure detector is active.

DS60001614B-page 448  2020 Microchip Technology Inc.

28.15.17 PMC INTERRUPT MASK REGISTER

Name:PMC_IMR Address:0x400E066C Access:Read-only

• MOSCXTS: Main Crystal Oscillator Status Interrupt Mask
• LOCKA: PLLA Lock Interrupt Mask
• MCKRDY: Master Clock Ready Interrupt Mask
• LOCKU: UTMI PLL Lock Interrupt Mask
• PCKRDYx: Programmable Clock Ready x Interrupt Mask
• MOSCSELS: Main Oscillator Selection Status Interrupt Mask
• MOSCRCS: Main On-Chip RC Status Interrupt Mask
• CFDEV: Clock Failure Detector Event Interrupt Mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — — CFDEV MOSCRCS MOSCSEL S 15 14 13 12 11 10 9 8 — — — — — PCKRDY2 PCKRDY1 PCKRDY0 7 6 5 4 3 2 1 0 — LOCKU– — — MCKRDY — LOCKA MOSCXTS

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28.15.18 PMC FAST STARTUP MODE REGISTER

Name: PMC_FSMR Address:0x400E0670 Access:Read-write This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 452.

• FSTT0 - FSTT15: Fast Startup Input Enable 0 to 15 0 = The corresponding wake up input has no effect on the Power Management Controller. 1 = The corresponding wake up input enables a fast restart signal to the Power Management Controller.
• RTTAL: RTT Alarm Enable 0 = The RTT alarm has no effect on the Power Management Controller. 1 = The RTT alarm enables a fast restart signal to the Power Management Controller.
• RTCAL: RTC Alarm Enable 0 = The RTC alarm has no effect on the Power Management Controller. 1 = The RTC alarm enables a fast restart signal to the Power Management Controller.
• USBAL: USB Alarm Enable 0 = The USB alarm has no effect on the Power Management Controller. 1 = The USB alarm enables a fast restart signal to the Power Management Controller.
• LPM: Low Power Mode 0 = The WaitForInterrupt (WFI) or WaitForEvent (WFE) instruction of the processor makes the processor enter Sleep Mode. 1 = The WaitForEvent (WFE) instruction of the processor makes the system to enter in Wait Mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — LPM — USBAL RTCAL RTTAL 15 14 13 12 11 10 9 8 FSTT15 FSTT14 FSTT13 FSTT12 FSTT11 FSTT10 FSTT9 FSTT8 7 6 5 4 3 2 1 0 FSTT7 FSTT6 FSTT5 FSTT4 FSTT3 FSTT2 FSTT1 FSTT0

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28.15.19 PMC FAST STARTUP POLARITY REGISTER

Name: PMC_FSPR Address:0x400E0674 Access:Read-write This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 452.

• FSTPx: Fast Startup Input Polarityx Defines the active polarity of the corresponding wake up input. If the corresponding wake up input is enabled and at the FSTP level, it enables a fast restart signal. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 FSTP15 FSTP14 FSTP13 FSTP12 FSTP11 FSTP10 FSTP9 FSTP8 7 6 5 4 3 2 1 0 FSTP7 FSTP6 FSTP5 FSTP4 FSTP3 FSTP2 FSTP1 FSTP0

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28.15.20 PMC FAULT OUTPUT CLEAR REGISTER

Name: PMC_FOCR Address:0x400E0678 Access:Write-only

• FOCLR: Fault Output Clear Clears the clock failure detector fault output. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

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28.15.21 PMC WRITE PROTECT MODE REGISTER

Name:PMC_WPMR Address:0x400E06E4 Access:Read-write Reset:See Table 28-1

• WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). Protects the registers:
• “PMC System Clock Enable Register” on page 432
• “PMC System Clock Disable Register” on page 433
• “PMC Peripheral Clock Enable Register 0” on page 434
• “PMC Peripheral Clock Disable Register 0” on page 435
• “PMC Clock Generator Main Oscillator Register” on page 438
• “PMC Clock Generator PLLA Register” on page 439
• “PMC Master Clock Register” on page 441
• “PMC USB Clock Register” on page 442
• “PMC Programmable Clock Register” on page 443
• “PMC Fast Startup Mode Register” on page 449
• “PMC Fast Startup Polarity Register” on page 450
• “PMC Peripheral Clock Enable Register 1” on page 454
• “PMC Peripheral Clock Disable Register 1” on page 454
• WPKEY: Write Protect KEY Should be written at value 0x504D43 (“PMC” in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

28.15.22 PMC WRITE PROTECT STATUS REGISTER

Name:PMC_WPSR Address:0x400E06E8 Access:Read-only Reset:See Table 28-1 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WPVSRC 15 14 13 12 11 10 9 8

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• WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the PMC_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the PMC_WPSR register. If this violation is an unau - thorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. Reading PMC_WPSR automatically clears all fields. WPVSRC 7 6 5 4 3 2 1 0

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28.15.23 PMC PERIPHERAL CLOCK ENABLE REGISTER 1

Name:PMC_PCER1 Address:0x400E0700 Access:Write-only This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 452.

• PIDx: Peripheral Clock x Enable 0 = No effect. 1 = Enables the corresponding peripheral clock. Note 1: To get PIDx, refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. 2: Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC.

28.15.24 PMC PERIPHERAL CLOCK DISABLE REGISTER 1

Name:PMC_PCDR1 Address:0x400E0704 Access:Write-only This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 452.

• PIDx: Peripheral Clock x Disable 0 = No effect. 1 = Disables the corresponding peripheral clock. Note: To get PIDx, refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.

28.15.25 PMC PERIPHERAL CLOCK STATUS REGISTER 1

Name:PMC_PCSR1 Address:0x400E0708 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — — — PID44 PID43 PID42 PID41 PID40 7 6 5 4 3 2 1 0 PID39 PID38 PID37 PID36 PID35 PID34 PID33 PID32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — — — PID44 PID43 PID42 PID41 PID40 7 6 5 4 3 2 1 0 PID39 PID38 PID37 PID36 PID35 PID34 PID33 PID32

 2020 Microchip Technology Inc. DS60001614B-page 455 SAM3X8ERT Access:Read-only

• PIDx: Peripheral Clock x Status 0 = The corresponding peripheral clock is disabled. 1 = The corresponding peripheral clock is enabled. Note: To get PIDx, refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — — — PID44 PID43 PID42 PID41 PID40 7 6 5 4 3 2 1 0 PID39 PID38 PID37 PID36 PID35 PID34 PID33 PID32

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28.15.26 PMC PERIPHERAL CONTROL REGISTER

Name:PMC_PCR Address:0x400E070C Access:Read-write

• PID: Peripheral ID Peripheral ID selection from PID2 to PID63 PID2 to PID63 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. Not all PID can be configured with divided clock. Only the following PID can be configured with divided clock: CAN0, CAN1.
• CMD: Command 0 = Read mode. 1 = Write mode.
• DIV: Divisor Value DIV must not be changed while peripheral is in use or when the peripheral clock is enabled. To change the clock division factor (DIV) of a peripheral, its clock must first be disabled by writing either EN to 0 for the corresponding PID (DIV must be kept the same if this method is used), or writing to PMC_PCDR register. Then a second write must be performed into PMC_PCR with the new value of DIV and a third write must be performed to enable the peripheral clock (either by using PMC_PCR or PMC_PCER register).
• EN: Enable 0 = Selected Peripheral clock is disabled. 1 = Selected Peripheral clock is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — PID Value Name Description

0 PERIPH_DIV_MCK Peripheral clock is MCK

1 PERIPH_DIV2_MCK Peripheral clock is MCK/2

2 PERIPH_DIV4_MCK Peripheral clock is MCK/4

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29.0 CHIP IDENTIFIER (CHIPID)

29.1 Description

Chip Identifier registers permit recognition of the device and its revision. These registers provide the sizes and types of the on-chip memories, as well as the set of embedded peripherals. Two chip identifier registers are embedded: CHIPID_CIDR (Chip ID Register) and CHIPID_EXID (Extension ID). Both registers contain a hard-wired value that is read-only. The first register contains the following fields:

• EXT - shows the use of the extension identifier register
• NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size
• ARCH - identifies the set of embedded peripherals
• SRAMSIZ - indicates the size of the embedded SRAM
• EPROC - indicates the embedded ARM processor
• VERSION - gives the revision of the silicon The second register is device-dependent and reads 0 if the bit EXT is 0.

29.2 Embedded Characteristics

• Chip ID Registers - Identification of the Device Revision, Sizes of the Embedded Memories, Set of Peripherals, Embedded Pro- cessor

29.3 Chip Identifier (CHIPID) User Interface

TABLE 29-1: SAM3X8ERT CHIP IDS REGISTER Chip Name CHIPID_CIDR CHIPID_EXID SAM3X8ERT 0x285E0A60 0x0 TABLE 29-2: REGISTER MAPPING Offset Register Name Access Reset 0x0 Chip ID Register CHIPID_CIDR Read-only — 0x4 Chip ID Extension Register CHIPID_EXID Read-only —

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29.3.1 CHIP ID REGISTER

Name:CHIPID_CIDR Address:0x400E0940 Access:Read-only

• VERSION: Version of the Device Current version of the device.
• EPROC: Embedded Processor
• NVPSIZ: Nonvolatile Program Memory Size
• NVPSIZ2 Second Nonvolatile Program Memory Size
• SRAMSIZ: Internal SRAM Size
• ARCH: Architecture Identifier
• NVPTYP: Nonvolatile Program Memory Type 31 30 29 28 27 26 25 24 EXT NVPTYP ARCH 23 22 21 20 19 18 17 16 ARCH SRAMSIZ 15 14 13 12 11 10 9 8 NVPSIZ2 NVPSIZ 7 6 5 4 3 2 1 0 EPROC VERSION Value Name Description

3 CM3 Cortex-M3

0x85 SAM3XxE SAM3XxE Series (144-pin version) Value Name Description

3 ROM_FLASH ROM and Embedded Flash Memory

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• EXT: Extension Flag 0 = Chip ID has a single register definition without extension 1 = An extended Chip ID exists.

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29.3.2 CHIP ID EXTENSION REGISTER

Name:CHIPID_EXID Address:0x400E0944 Access:Read-only

• EXID: Chip ID Extension Reads 0 if the bit EXT in CHIPID_CIDR is 0. 31 30 29 28 27 26 25 24 EXID 23 22 21 20 19 18 17 16 EXID 15 14 13 12 11 10 9 8 EXID 7 6 5 4 3 2 1 0 EXID

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30.0 SYNCHRONOUS SERIAL CONTROLLER (SSC)

30.1 Description

The Microchip Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the transmit- ter each interface with three signals: the TD/RD signal for data, the TK/RK signal for the clock and the TF/RF signal for the Frame Sync. The transfers can be programmed to start automatically or on different events detected on the Frame Sync signal. The SSC’s high-level of programmability and its use of DMA permit a continuous high bit rate data transfer without pro- cessor intervention. Featuring connection to the DMA, the SSC permits interfacing with low processor overhead to the following:

• CODEC’s in master or slave mode
• DAC through dedicated serial interface, particularly I2S
• Magnetic card reader

30.2 Embedded Characteristics

• Provides Serial Synchronous Communication Links Used in Audio and Telecom Applications
• Contains an Independent Receiver and Transmitter and a Common Clock Divider
• Interfaced with the DMA Controller (DMAC) to Reduce Processor Overhead
• Offers a Configurable Frame Sync and Data Length
• Receiver and Transmitter Can be Programmed to Start Automatically or on Detection of Different Events on the Frame Sync Signal
• Receiver and Transmitter Include a Data Signal, a Clock Signal and a Frame Synchronization Signal

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30.3 Block Diagram

FIGURE 30-1: BLOCK DIAGRAM

30.4 Application Block Diagram

FIGURE 30-2: APPLICATION BLOCK DIAGRAM SSC Interface PIO DMA APB Bridge MCK System Bus Peripheral Bus TF TK TD RF RK RD Interrupt Control SSC Interrupt PMC Interrupt Management Power Management Test Management SSC Serial AUDIO OS or RTOS Driver Codec Frame Management Line Interface Time Slot Management

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30.5 Pin Name List

30.6 Product Dependencies

30.6.1 I/O LINES

The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the SSC peripheral mode. Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to the SSC peripheral mode.

30.6.2 POWER MANAGEMENT

The SSC is not continuously clocked. The SSC interface may be clocked through the Power Management Controller (PMC), therefore the programmer must first configure the PMC to enable the SSC clock.

30.6.3 INTERRUPT

The SSC interface has an interrupt line connected to the Nested Vector Interrupt Controller (NVIC). Handling interrupts requires programming the NVIC before configuring the SSC. All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin by reading the SSC interrupt status register. TABLE 30-1: I/O LINES DESCRIPTION Pin Name Pin Description Type RF Receiver Frame Synchro Input/Output RK Receiver Clock Input/Output RD Receiver Data Input TF Transmitter Frame Synchro Input/Output TK Transmitter Clock Input/Output TD Transmitter Data Output TABLE 30-2: I/O LINES Instance Signal I/O Line Peripheral SSC RD PB18 A SSC RF PB17 A SSC RK PB19 A SSC TD PA16 B SSC TF PA15 B SSC TK PA14 B TABLE 30-3: PERIPHERAL IDS Instance ID SSC 26

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30.7 Functional Description

This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data for - mat, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by pro- gramming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK and RK pins is the master clock divided by 2. FIGURE 30-3: SSC FUNCTIONAL BLOCK DIAGRAM

30.7.1 CLOCK MANAGEMENT

The transmitter clock can be generated by:

• an external clock received on the TK I/O pad
• the receiver clock
• the internal clock divider The receiver clock can be generated by:
• an external clock received on the RK I/O pad
• the transmitter clock NVIC Frame Sync Controller Clock Output Controller Data Controller Start Selector Start Selector RF RXEN RC0R TX Start TXEN TF RX Start TX Start Interrupt Control User Interface APB MCK Receive Clock ControllerTX Clock RK Input Transmit Clock Controller Transmit Shift Register Transmit Sync Holding Register Transmit Holding Register RX clock TX cloc kTK Input RD RF RK Clock Output Controller Frame Sync Controller Receive Shift Register Receive Sync Holding Register Receive Holding Register TD TF TK RX Clock Receiver Transmitter Data Controller Clock Divider RX Start

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• the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can gener- ate an external clock on the RK I/O pad. This allows the SSC to support many Master and Slave Mode data transfers.

30.7.1.1 Clock Divider

FIGURE 30-4: DIVIDED CLOCK BLOCK DIAGRAM The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inac- tive. When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Master Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless of whether the DIV value is even or odd. FIGURE 30-5: DIVIDED CLOCK GENERATION

30.7.1.2 Transmitter Clock Management

The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR register. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the TCMR register to select TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results. Maximum Minimum MCK / 2 MCK / 8190 MCK Divided Clock Clock Divider / 2 12-bit Counter SSC_CMR Master Clock Divided Clock DIV = 1 Master Clock Divided Clock DIV = 3 Divided Clock Frequency = MCK/2 Divided Clock Frequency = MCK/6

DS60001614B-page 466  2020 Microchip Technology Inc. FIGURE 30-6: TRANSMITTER CLOCK MANAGEMENT

30.7.1.3 Receiver Clock Management

The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR. The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs. Pro- gramming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO field) can lead to unpredictable results. FIGURE 30-7: RECEIVER CLOCK MANAGEMENT

30.7.1.4 Serial Clock Ratio Considerations

The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on the RK pin is: - Master Clock divided by 2 if Receiver Frame Synchro is input - Master Clock divided by 3 if Receiver Frame Synchro is output TK (pin) Receiver Clock Divider Clock CKS CKO Data Transfer CKI CKG Transmitter Clock Clock Output MUX Tri_state Controller Tri-state Controller INV MUX RK (pin) Transmitter Clock Divider Clock CKS CKO Data Transfer CKI CKG Receiver Clock Clock Output MUX Tri-state Controller Tri-state Controller INV MUX

 2020 Microchip Technology Inc. DS60001614B-page 467 SAM3X8ERT In addition, the maximum clock speed allowed on the TK pin is: - Master Clock divided by 6 if Transmit Frame Synchro is input - Master Clock divided by 2 if Transmit Frame Synchro is output

30.7.2 TRANSMITTER OPERATIONS

A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See “Start” on page 468 The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See “Frame Sync” on page 470 To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR register then transferred to the shift register according to the data format selected. When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding register. FIGURE 30-8: TRANSMITTER BLOCK DIAGRAM

30.7.3 RECEIVER OPERATIONS

A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See “Start” on page 468 The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). See “Frame Sync” on page 470 The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR. The data is transferred from the shift register depending on the data format selected. When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in SSC_SR and the data can be read in the receiver holding register. If another transfer occurs before read of the RHR register, the status flag OVERUN is set in SSC_SR and the receiver shift register is transferred in the RHR register. Transmit Shift Register TD SSC_TFMR.FSLENSSC_TFMR.DATLEN SSC_TCMR.STTDLY SSC_TFMR.FSDEN SSC_TFMR.DATNB SSC_TFMR.DATDEF SSC_TFMR.MSBF SSC_TCMR.STTDLY != 0 SSC_TFMR.FSDEN 1 0 TX Controller SSC_TCMR.START RF Start Selector TXEN RX Start TXEN RF Start Selector RXEN RC0R TX Start TX Start Transmitter Clock TX Controller counter reached STTDLY SSC_RCMR.START SSC_THR SSC_TSHR SSC_CRTXEN SSC_SRTXEN SSC_CRTXDIS

DS60001614B-page 468  2020 Microchip Technology Inc. FIGURE 30-9: RECEIVER BLOCK DIAGRAM

30.7.4 START

The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection (START) field of SSC_TCMR and in the Receive Start Selection (START) field of SSC_RCMR. Under the following conditions the start event is independently programmable:

• Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR and the reception starts as soon as the Receiver is enabled.
• Synchronously with the transmitter/receiver
• On detection of a falling/rising edge on TF/RF
• On detection of a low level/high level on TF/RF
• On detection of a level change or an edge on TF/RF A start can be programmed in the same manner on either side of the Transmit/Receive Clock Register (RCMR/TCMR). Thus, the start could be on TF (Transmit) or RF (Receive). Moreover, the Receiver can start when data is detected in the bit stream with the Compare Functions. Detection on TF/RF input/output is done by the field FSOS of the Transmit/Receive Frame Mode Register (TFMR/RFMR). SSC_RFMR.MSBF SSC_RFMR.DATNB SSC_TCMR.START SSC_RCMR.START SSC_RHRSSC_RSHR SSC_RFMR.FSLEN SSC_RFMR.DATLEN RX Controller counter reached STTDLY RX Controller SSC_CR.RXEN SSC_CR.RXDIS SSC_SR.RXEN Receiver Clock RF TXEN RX Start RF RXEN RC0R RCMR.STTDLY != 0 Receive Shift Register Start Selector Start Selector RX Start load load

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30.7.5 FRAME SYNC

The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform.

• Programmable low or high levels during data transfer are supported.
• Programmable high levels before the start of data transfers or toggling are also supported. If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and SSC_TFMR programs the length of the pulse, from 1 bit time up to 256 bit time. The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR.

30.7.5.1 Frame Sync Data

Frame Sync Data transmits or receives a specific tag during the Frame Sync signal. During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR and has a maximum value of 16. Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the Receive Sync Holding Register through the Receive Shift Register. The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable (FSDEN) in SSC_TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding Register is transferred in the Transmit Register, then shifted out.

30.7.5.2 Frame Sync Edge Detection

The Frame Sync Edge detection is programmed by the FSEDGE field in SSC_RFMR/SSC_TFMR. This sets the corre- sponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on frame synchro edge detection (signals RF/TF).

30.7.6 RECEIVE COMPARE MODES

FIGURE 30-12: RECEIVE COMPARE MODES

30.7.6.1 Compare Functions

Length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they are compared to is defined by FSLEN, but with a maximum value of 16 bits. Comparison is always done by comparing the last bits received with the comparison pattern. Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each new sample the last bits received at the Compare 0 pattern contained in the Compare 0 Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start a new data transfer either by writing a new Com- pare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the bit (STOP) in SSC_RCMR. CMP0 CMP3CMP2CMP1 Ignored B0 B2B1 Start RK RD (Input) FSLEN Up to 16 Bits (4 in This Example) STDL Y DATLEN

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30.7.7 DATA FORMAT

The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can inde - pendently select:

• the event that starts the data transfer (START)
• the delay in number of bit periods between the start event and the first data bit (STTDLY)
• the length of the data (DATLEN)
• the number of data to be transferred for each start event (DATNB).
• the length of synchronization transferred for each start event (FSLEN)
• the bit sense: most or lowest significant bit first (MSBF) Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in SSC_TFMR. FIGURE 30-13: TRANSMIT AND RECEIVE FRAME FORMAT IN EDGE/PULSE START MODES Note: 1. Example of input on falling edge of TF/RF. TABLE 30-4: DATA FRAME REGISTERS Transmitter Receiver Field Length Comment SSC_TFMR SSC_RFMR DATLEN Up to 32 Size of word SSC_TFMR SSC_RFMR DATNB Up to 16 Number of words transmitted in frame SSC_TFMR SSC_RFMR MSBF — Most significant bit first SSC_TFMR SSC_RFMR FSLEN Up to 16 Size of Synchro data register SSC_TFMR — DATDEF 0 or 1 Data default value ended SSC_TFMR — FSDEN — Enable send SSC_TSHR SSC_TCMR SSC_RCMR PERIOD Up to 512 Frame size SSC_TCMR SSC_RCMR STTDLY Up to 255 Size of transmit start delay Sync Data Default STTDLY Sync Data IgnoredRD Default Data DATLEN Data Data Data DATLEN Data Data Default Default Ignored Sync Data Sync Data FSLEN TF/RF (1) StartStart From SSC_TSHR From SSC_THR From SSC_THR From SSC_THR From SSC_THR To SSC_RHR To SSC_RHRTo SSC_RSHR TD (If FSDEN = 0) TD (If FSDEN = 1) DATNB PERIOD From DATDEF From DATDEF From DATDEF From DATDEF

DS60001614B-page 472  2020 Microchip Technology Inc. FIGURE 30-14: TRANSMIT FRAME FORMAT IN CONTINUOUS MODE Note 1: STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the trans - mission. SyncData cannot be output in continuous mode. FIGURE 30-15: RECEIVE FRAME FORMAT IN CONTINUOUS MODE Note 1: STTDLY is set to 0.

30.7.8 LOOP MODE

The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK.

30.7.9 INTERRUPT

Most bits in SSC_SR have a corresponding bit in interrupt management registers. The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Register) These registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR (Interrupt Mask Reg- ister), which controls the generation of interrupts by asserting the SSC interrupt line connected to the NVIC. DATLEN Data DATLEN Data Default Start From SSC_THR From SSC_THR TD Start: 1. TXEMPTY set to 1 2. Write into the SSC_THR Data DATLEN Data DATLEN Start = Enable Receiver To SSC_RHR To SSC_RHR RD

 2020 Microchip Technology Inc. DS60001614B-page 473 SAM3X8ERT FIGURE 30-16: INTERRUPT BLOCK DIAGRAM

30.8 SSC Application Examples

The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. FIGURE 30-17: AUDIO APPLICATION BLOCK DIAGRAM SSC_IMR Interrupt Control SSC Interrupt Set RXRDY OVRUN RXSYNC Receiver Transmitter TXRDY TXEMPTY TXSYNC Clear SSC_IER SSC_IDR SSC RK RF RD TD TF TK Clock SCK Word Select WS Data SD I2S RECEIVER Clock SCK Word Select WS Data SD Right ChannelLeft Channel MSB MSBLSB

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30.8.1 WRITE PROTECTION REGISTERS

To prevent any single software error that may corrupt SSC behavior, certain address spaces can be write-protected by setting the WPEN bit in the “SSC Write Protect Mode Register” on page 497 (SSC_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the SSC Write Protect Status Register (US_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. The WPVS flag is reset by writing the SSC Write Protect Mode Register (SSC_WPMR) with the appropriate access key, WPKEY . The protected registers are:

• “SSC Clock Mode Register” on page 477
• “SSC Receive Clock Mode Register” on page 478
• “SSC Receive Frame Mode Register” on page 480
• “SSC Transmit Clock Mode Register” on page 482
• “SSC Transmit Frame Mode Register” on page 484
• “SSC Receive Compare 0 Register” on page 490
• “SSC Receive Compare 1 Register” on page 491

30.9 Synchronous Serial Controller (SSC) User Interface

TABLE 30-5: REGISTER MAPPING Offset Register Name Access Reset 0x0 Control Register SSC_CR Write-only — 0x4 Clock Mode Register SSC_CMR Read-write 0x0 0x8 Reserved — — — 0xC Reserved — — — 0x10 Receive Clock Mode Register SSC_RCMR Read-write 0x0 0x14 Receive Frame Mode Register SSC_RFMR Read-write 0x0 0x18 Transmit Clock Mode Register SSC_TCMR Read-write 0x0 0x1C Transmit Frame Mode Register SSC_TFMR Read-write 0x0 0x20 Receive Holding Register SSC_RHR Read-only 0x0 0x24 Transmit Holding Register SSC_THR Write-only — 0x28 Reserved — — — 0x2C Reserved — — — 0x30 Receive Sync. Holding Register SSC_RSHR Read-only 0x0 0x34 Transmit Sync. Holding Register SSC_TSHR Read-write 0x0 0x38 Receive Compare 0 Register SSC_RC0R Read-write 0x0 0x3C Receive Compare 1 Register SSC_RC1R Read-write 0x0 0x40 Status Register SSC_SR Read-only 0x000000CC 0x44 Interrupt Enable Register SSC_IER Write-only — 0x48 Interrupt Disable Register SSC_IDR Write-only — 0x4C Interrupt Mask Register SSC_IMR Read-only 0x0 0xE4 Write Protect Mode Register SSC_WPMR Read-write 0x0 0xE8 Write Protect Status Register SSC_WPSR Read-only 0x0 0x50-0xFC Reserved — — — 0x100- 0x124 Reserved — — —

DS60001614B-page 476  2020 Microchip Technology Inc.

30.9.1 SSC CONTROL REGISTER

Name:SSC_CR Address:0x40004000 Access:Write-only

• RXEN: Receive Enable
• 0 = No effect. 1 = Enables Receive if RXDIS is not set.
• RXDIS: Receive Disable 0 = No effect. 1 = Disables Receive. If a character is currently being received, disables at end of current character reception.
• TXEN: Transmit Enable 0 = No effect. 1 = Enables Transmit if TXDIS is not set.
• TXDIS: Transmit Disable 0 = No effect. 1 = Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission.
• SWRST: Software Reset 0 = No effect. 1 = Performs a software reset. Has priority on any other bit in SSC_CR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 SWRST — — — — — TXDIS TXEN 7 6 5 4 3 2 1 0

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30.9.2 SSC CLOCK MODE REGISTER

Name:SSC_CMR Address:0x40004004 Access:Read-write This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” on page 497.

• DIV: Clock Divider 0 = The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — — — — DIV 7 6 5 4 3 2 1 0 DIV

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30.9.3 SSC RECEIVE CLOCK MODE REGISTER

Name:SSC_RCMR Address:0x40004010 Access:Read-write This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” on page 497.

• CKS: Receive Clock Selection
• CKO: Receive Clock Output Mode Selection
• CKI: Receive Clock Inversion 0 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is shifted out on Receive Clock rising edge. 1 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal output is shifted out on Receive Clock falling edge. CKI affects only the Receive Clock and not the output clock signal. 31 30 29 28 27 26 25 24 PERIOD 23 22 21 20 19 18 17 16 STTDLY 15 14 13 12 11 10 9 8 — — — STOP START 7 6 5 4 3 2 1 0 CKG CKI CKO CKS Value Name Description

0 MCK Divided Clock

1 TK TK Clock signal

2 RK RK pin

3 Reserved

Value Name Description RK Pin

0 NONE None Input-only

1 CONTINUOUS Continuous Receive Clock Output

2 TRANSFER Receive Clock only during data transfers Output

3-7 — Reserved —

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• CKG: Receive Clock Gating Selection
• START: Receive Start Selection
• STOP: Receive Stop Selection 0 = After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new compare 0. 1 = After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
• STTDLY: Receive Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception. When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied. Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive Sync Data) reception.
• PERIOD: Receive Period Divider Selection This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock. Value Name Description RK Pin

3-7 — Reserved — Value Name Description

0 CONTINUOUS Continuous, as soon as the receiver is enabled, and imme-

diately after the end of transfer of the previous data.

1 TRANSMIT Transmit start

2 RF_LOW Detection of a low level on RF signal

3 RF_HIGH Detection of a high level on RF signal

4 RF_FALLING Detection of a falling edge on RF signal

5 RF_RISING Detection of a rising edge on RF signal

6 RF_LEVEL Detection of any level change on RF signal

7 RF_EDGE Detection of any edge on RF signal

8 CMP_0 Compare 0

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30.9.4 SSC RECEIVE FRAME MODE REGISTER

Name:SSC_RFMR Address:0x40004014 Access:Read-write This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” on page 497.

• DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits.
• LOOP: Loop Mode 0 = Normal operating mode. 1 = RD is driven by TD, RF is driven by TF and TK drives RK.
• MSBF: Most Significant Bit First 0 = The lowest significant bit of the data register is sampled first in the bit stream. 1 = The most significant bit of the data register is sampled first in the bit stream.
• DATNB: Data Number per Frame This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1).
• FSLEN: Receive Frame Sync Length This field defines the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be com - pared to the Compare 0 or Compare 1 register. This field is used with FSLEN_EXT to determine the pulse length of the Receive Frame Sync signal. Pulse length is equal to FSLEN + (FSLEN_EXT * 16) + 1 Receive Clock periods. 31 30 29 28 27 26 25 24 FSLEN_EX T FSLEN_EX T FSLEN_EX T FSLEN_EXT — — — FSEDGE 23 22 21 20 19 18 17 16 — FSOS FSLEN 15 14 13 12 11 10 9 8 — — — — DATNB 7 6 5 4 3 2 1 0 MSBF — LOOP DATLEN

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• FSOS: Receive Frame Sync Output Selection
• FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
• FSLEN_EXT: FSLEN Field Extension Extends FSLEN field. For details, refer to FSLEN bit description on page 480. Value Name Description RF Pin

1 NEGATIVE Negative Pulse Output

2 POSITIVE Positive Pulse Output

3 LOW Driven Low during data transfer Output

4 HIGH Driven High during data transfer Output

5 TOGGLING Toggling at each start of data transfer Output

6-7 — Reserved Undefined Value Name Description

0 POSITIVE Positive Edge Detection

1 NEGATIVE Negative Edge Detection

DS60001614B-page 482  2020 Microchip Technology Inc.

30.9.5 SSC TRANSMIT CLOCK MODE REGISTER

Name:SSC_TCMR Address:0x40004018 Access:Read-write This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” on page 497.

• CKS: Transmit Clock Selection
• CKO: Transmit Clock Output Mode Selection
• CKI: Transmit Clock Inversion 0 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal input is sampled on Transmit clock rising edge. 1 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal input is sampled on Transmit clock falling edge. CKI affects only the Transmit Clock and not the output clock signal.
• CKG: Transmit Clock Gating Selection 31 30 29 28 27 26 25 24 PERIOD 23 22 21 20 19 18 17 16 STTDLY 15 14 13 12 11 10 9 8 — — — — START 7 6 5 4 3 2 1 0 CKG CKI CKO CKS Value Name Description

3 — Reserved Value Name Description TK Pin

2 TRANSFER Transmit Clock only during data transfers Output

3-7 — Reserved — Value Name Description

0 NONE None

1 CONTINUOUS Transmit Clock enabled only if TF Low

2 TRANSFER Transmit Clock enabled only if TF High

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• START: Transmit Start Selection
• STTDLY: Transmit Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmis- sion of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied. Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted instead of the end of TAG.
• PERIOD: Transmit Period Divider Selection This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock. Value Name Description

0 CONTINUOUS Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is

enabled), and immediately after the end of transfer of the previous data.

1 RECEIVE Receive start

2 RF_LOW Detection of a low level on TF signal

3 RF_HIGH Detection of a high level on TF signal

4 RF_FALLING Detection of a falling edge on TF signal

5 RF_RISING Detection of a rising edge on TF signal

6 RF_LEVEL Detection of any level change on TF signal

7 RF_EDGE Detection of any edge on TF signal

DS60001614B-page 484  2020 Microchip Technology Inc.

30.9.6 SSC TRANSMIT FRAME MODE REGISTER

Name:SSC_TFMR Address:0x4000401C Access:Read-write This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” on page 497.

• DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. .
• DATDEF: Data Default Value This bit defines the level driven on the TD pin while out of transmission. Note: If the pin is defined as multi-drive by the PIO Controller, the pin is enabled only if the SCC TD output is 1.
• MSBF: Most Significant Bit First 0 = The lowest significant bit of the data register is shifted out first in the bit stream. 1 = The most significant bit of the data register is shifted out first in the bit stream.
• DATNB: Data Number per frame This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1).
• FSLEN: Transmit Frame Sync Length This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. This field is used with FSLEN_EXT to determine the pulse length of the Transmit Frame Sync signal. Pulse length is equal to FSLEN + (FSLEN_EXT * 16) + 1 Transmit Clock period. 31 30 29 28 27 26 25 24 FSLEN_EX T FSLEN_EX T FSLEN_EX T FSLEN_EXT — — — FSEDGE 23 22 21 20 19 18 17 16 FSDEN FSOS FSLEN 15 14 13 12 11 10 9 8 — — — — DATNB 7 6 5 4 3 2 1 0 MSBF — DATDEF DATLEN

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• FSOS: Transmit Frame Sync Output Selection
• FSDEN: Frame Sync Data Enable 0 = The TD line is driven with the default value during the Transmit Frame Sync signal. 1 = SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
• FSEDGE: Frame Sync Edge Detection Determines which edge on frame sync will generate the interrupt TXSYN (Status Register).
• FSLEN_EXT: FSLEN Field Extension Extends FSLEN field. For details, refer to FSLEN bit description on page 484. Value Name Description RF Pin

6-7 — Reserved Undefined Value Name Description

DS60001614B-page 486  2020 Microchip Technology Inc.

30.9.7 SSC RECEIVE HOLDING REGISTER

Name:SSC_RHR Address:0x40004020 Access:Read-only

• RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR. 31 30 29 28 27 26 25 24 RDAT 23 22 21 20 19 18 17 16 RDAT 15 14 13 12 11 10 9 8 RDAT 7 6 5 4 3 2 1 0 RDAT

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30.9.8 SSC TRANSMIT HOLDING REGISTER

Name:SSC_THR Address:0x40004024 Access:Write-only

• TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR. 31 30 29 28 27 26 25 24 TDAT 23 22 21 20 19 18 17 16 TDAT 15 14 13 12 11 10 9 8 TDAT 7 6 5 4 3 2 1 0 TDAT

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30.9.9 SSC RECEIVE SYNCHRONIZATION HOLDING REGISTER

Name:SSC_RSHR Address:0x40004030 Access:Read-only

• RSDAT: Receive Synchronization Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RSDAT 7 6 5 4 3 2 1 0 RSDAT

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30.9.10 SSC TRANSMIT SYNCHRONIZATION HOLDING REGISTER

Name:SSC_TSHR Address:0x40004034 Access:Read-write

• TSDAT: Transmit Synchronization Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TSDAT 7 6 5 4 3 2 1 0 TSDAT

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30.9.11 SSC RECEIVE COMPARE 0 REGISTER

Name:SSC_RC0R Address:0x40004038 Access:Read-write This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” on page 497.

• CP0: Receive Compare Data 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CP0 7 6 5 4 3 2 1 0 CP0

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30.9.12 SSC RECEIVE COMPARE 1 REGISTER

Name:SSC_RC1R Address:0x4000403C Access:Read-write This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” on page 497.

• CP1: Receive Compare Data 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CP1 7 6 5 4 3 2 1 0 CP1

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30.9.13 SSC STATUS REGISTER

Name:SSC_SR Address:0x40004040 Access:Read-only

• TXRDY: Transmit Ready 0 = Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1 = SSC_THR is empty.
• TXEMPTY: Transmit Empty 0 = Data remains in SSC_THR or is currently transmitted from TSR. 1 = Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted.
• RXRDY: Receive Ready 0 = SSC_RHR is empty. 1 = Data has been received and loaded in SSC_RHR.
• OVRUN: Receive Overrun 0 = No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Reg- ister. 1 = Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register.
• CP0: Compare 0 0 = A compare 0 has not occurred since the last read of the Status Register. 1 = A compare 0 has occurred since the last read of the Status Register.
• CP1: Compare 1 0 = A compare 1 has not occurred since the last read of the Status Register. 1 = A compare 1 has occurred since the last read of the Status Register.
• TXSYN: Transmit Sync 0 = A Tx Sync has not occurred since the last read of the Status Register. 1 = A Tx Sync has occurred since the last read of the Status Register.
• RXSYN: Receive Sync 0 = An Rx Sync has not occurred since the last read of the Status Register. 1 = An Rx Sync has occurred since the last read of the Status Register.
• TXEN: Transmit Enable 0 = Transmit is disabled. 1 = Transmit is enabled.
• RXEN: Receive Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — — — — RXSYN TXSYN CP1 CP0 7 6 5 4 3 2 1 0 — — OVRUN RXRDY — — TXEMPTY TXRDY

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30.9.14 SSC INTERRUPT ENABLE REGISTER

Name:SSC_IER Address:0x40004044 Access:Write-only

• TXRDY: Transmit Ready Interrupt Enable 0 = 0 = No effect. 1 = Enables the Transmit Ready Interrupt.
• TXEMPTY: Transmit Empty Interrupt Enable 0 = No effect. 1 = Enables the Transmit Empty Interrupt.
• RXRDY: Receive Ready Interrupt Enable 0 = No effect. 1 = Enables the Receive Ready Interrupt.
• OVRUN: Receive Overrun Interrupt Enable 0 = No effect. 1 = Enables the Receive Overrun Interrupt.
• CP0: Compare 0 Interrupt Enable 0 = No effect. 1 = Enables the Compare 0 Interrupt.
• CP1: Compare 1 Interrupt Enable 0 = No effect. 1 = Enables the Compare 1 Interrupt.
• TXSYN: Tx Sync Interrupt Enable 0 = No effect. 1 = Enables the Tx Sync Interrupt.
• RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Enables the Rx Sync Interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — — — — RXSYN TXSYN CP1 CP0 7 6 5 4 3 2 1 0 — — OVRUN RXRDY — — TXEMPTY TXRDY

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30.9.15 SSC INTERRUPT DISABLE REGISTER

Name:SSC_IDR Address:0x40004048 Access:Write-only

• TXRDY: Transmit Ready Interrupt Disable 0 = No effect. 1 = Disables the Transmit Ready Interrupt.
• TXEMPTY: Transmit Empty Interrupt Disable 0 = No effect. 1 = Disables the Transmit Empty Interrupt.
• RXRDY: Receive Ready Interrupt Disable 0 = No effect. 1 = Disables the Receive Ready Interrupt.
• OVRUN: Receive Overrun Interrupt Disable 0 = No effect. 1 = Disables the Receive Overrun Interrupt.
• CP0: Compare 0 Interrupt Disable 0 = No effect. 1 = Disables the Compare 0 Interrupt.
• CP1: Compare 1 Interrupt Disable 0 = No effect. 1 = Disables the Compare 1 Interrupt.
• TXSYN: Tx Sync Interrupt Enable 0 = No effect. 1 = Disables the Tx Sync Interrupt.
• RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Disables the Rx Sync Interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — — — — RXSYN TXSYN CP1 CP0 7 6 5 4 3 2 1 0 — — OVRUN RXRDY — — TXEMPTY TXRDY

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30.9.16 SSC INTERRUPT MASK REGISTER

Name:SSC_IMR Address:0x4000404C Access:Read-only

• TXRDY: Transmit Ready Interrupt Mask 0 = The Transmit Ready Interrupt is disabled. 1 = The Transmit Ready Interrupt is enabled.
• TXEMPTY: Transmit Empty Interrupt Mask 0 = The Transmit Empty Interrupt is disabled. 1 = The Transmit Empty Interrupt is enabled.
• RXRDY: Receive Ready Interrupt Mask 0 = The Receive Ready Interrupt is disabled. 1 = The Receive Ready Interrupt is enabled.
• OVRUN: Receive Overrun Interrupt Mask 0 = The Receive Overrun Interrupt is disabled. 1 = The Receive Overrun Interrupt is enabled.
• CP0: Compare 0 Interrupt Mask 0 = The Compare 0 Interrupt is disabled. 1 = The Compare 0 Interrupt is enabled.
• CP1: Compare 1 Interrupt Mask 0 = The Compare 1 Interrupt is disabled. 1 = The Compare 1 Interrupt is enabled.
• TXSYN: Tx Sync Interrupt Mask 0 = The Tx Sync Interrupt is disabled. 1 = The Tx Sync Interrupt is enabled.
• RXSYN: Rx Sync Interrupt Mask 0 = The Rx Sync Interrupt is disabled. 1 = The Rx Sync Interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — — — — RXSYN TXSYN CP1 CP0 7 6 5 4 3 2 1 0 — — OVRUN RXRDY — — TXEMPTY TXRDY

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30.9.17 SSC WRITE PROTECT MODE REGISTER

Name:SSC_WPMR Address:0x400040E4 Access:Read-write Reset:See Table 30-5

• WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x535343 (“SSC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x535343 (“SSC” in ASCII). Protects the registers:
• “SSC Clock Mode Register” on page 477
• “SSC Receive Clock Mode Register” on page 478
• “SSC Receive Frame Mode Register” on page 480
• “SSC Transmit Clock Mode Register” on page 482
• “SSC Transmit Frame Mode Register” on page 484
• “SSC Receive Compare 0 Register” on page 490
• “SSC Receive Compare 1 Register” on page 491
• WPKEY: Write Protect KEY Should be written at value 0x535343 (“SSC” in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 7 6 5 4 3 2 1 0

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30.9.18 SSC WRITE PROTECT STATUS REGISTER

Name:SSC_WPSR Address:0x400040E8 Access:Read-only Reset:See Table 30-5

• WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the SSC_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the SSC_WPSR register. If this violation is an unautho- rized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. Note: Reading SSC_WPSR automatically clears all fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WPVSRC 15 14 13 12 11 10 9 8 WPVSRC 7 6 5 4 3 2 1 0

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31.0 PARALLEL INPUT/OUTPUT CONTROLLER (PIO)

31.1 Description

The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface. Each I/O line of the PIO Controller features:

• An input change interrupt enabling level change detection on any I/O line.
• Additional Interrupt modes enabling rising edge, falling edge, low level or high level detection on any I/O line.
• A glitch filter providing rejection of glitches lower than one-half of system clock cycle.
• A debouncing filter providing rejection of unwanted pulses from key or push button operations.
• Multi-drive capability similar to an open drain I/O line.
• Control of the pull-up of the I/O line.
• Input visibility and output control. The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation.

31.2 Embedded Characteristics

• Up to 4 PIO Controllers, PIOA, PIOB, PIOC and PIOD controlling a maximum of 103 I/O Lines
• Each PIO Controller controls up to 32 programmable I/O Lines
• Fully programmable through Set/Clear Registers
• Multiplexing of four peripheral functions per I/O Line
• For each I/O Line (whether assigned to a peripheral or used as general purpose I/O) - Input change, rising edge, falling edge, low level and level interrupt - Debouncing and Glitch filter - Multi-drive option enables driving in open drain - Programmable pull-up on each I/O line - Pin data status register, supplies visibility of the level on the pin at any time
• Synchronous output, provides Set and Clear of several I/O lines in a single write FIGURE 31-1: PIO LINES PER PIO Version 144 pin SAM3X8ERT PIOA 30 PIOB 32 PIOC 31 PIOD 10 Total 103

DS60001614B-page 500  2020 Microchip Technology Inc.

31.3 Block Diagram

FIGURE 31-1: BLOCK DIAGRAM

31.4 Product Dependencies

31.4.1 PIN MULTIPLEXING

Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line mul- tiplexed with one or two peripheral I/Os. As the multiplexing is hardware defined and thus product-dependent, the hard- ware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product.

31.4.2 POWER MANAGEMENT

The Power Management Controller controls the PIO Controller clock in order to save power. Writing any of the registers of the user interface does not require the PIO Controller clock to be enabled. This means that the configuration of the I/O lines does not require the PIO Controller clock to be enabled. However, when the clock is disabled, not all of the features of the PIO Controller are available, including glitch filtering. Note that the Input Change Interrupt, Interrupt Modes on a programmable event and the read of the pin level require the clock to be validated. After a hardware reset, the PIO clock is disabled by default. Embedded Peripheral Embedded Peripheral PIO Interrupt PIO Controller Up to 32 pi PMC Up to 32 peripheral IOs Up to 32 peripheral IOs PIO Clock APB NVIC Data, Enable PIN 31 PIN 1 PIN 0 Data, Enable

 2020 Microchip Technology Inc. DS60001614B-page 501 SAM3X8ERT The user must configure the Power Management Controller before any access to the input line information.

31.4.3 INTERRUPT GENERATION

The PIO COntroller is connected on one of the sources of the Nested Vectored Interrupt Controller (NVIC). Using the PIO Controller requires the NVIC to be programmed first. The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled.

DS60001614B-page 502  2020 Microchip Technology Inc.

31.5 Functional Description

The PIO Controller features up to 32 fully-programmable I/O lines. In this description, each signal shown represents but one of up to 32 possible indexes.

31.5.1 PULL-UP RESISTOR CONTROL

Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled. Control of the pull-up resistor is possible regardless of the configuration of the I/O line. After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0.

31.5.2 I/O LINE OR PERIPHERAL FUNCTION SELECTION

When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status Register) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the PIO_ABSR (AB Select Register). A value of 1 indicates the pin is controlled by the PIO controller. If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit. After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR resets at 1. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level, depending on the multiplexing of the device.

31.5.3 PERIPHERAL A OR B SELECTION

The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The selection is performed by writing PIO_ABSR (AB Select Register). For each pin, the corresponding bit at level 0 means peripheral A is selected whereas the corresponding bit at level 1 indicates that peripheral B is selected. Note: Multiplexing of peripheral lines A and B only affects the output line. The peripheral input lines are always connected to the pin input. After reset, PIO_ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode. Writing in PIO_ABSR manages the multiplexing regardless of the configuration of the pin. However, assignment of a pin to a peripheral function requires a write in the peripheral selection register (PIO_ABSR) in addition to a write in PIO_PDR.

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31.5.4 OUTPUT CONTROL

When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B depending on the value in PIO_ABSR (AB Select Register) deter- mines whether the pin is driven or not. When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register). The results of these write operations are detected in PIO_OSR (Output Status Register). When a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller. The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set and clear PIO_ODSR (Output Data Status Reg- ister), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven on the I/O line.

31.5.5 SYNCHRONOUS DATA OUTPUT

Clearing one (or more) PIO line(s) and setting another one (or more) PIO line(s) synchronously cannot be done by using PIO_SODR and PIO_CODR registers. It requires two successive write operations into two different registers. To over- come this, the PIO Controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output Data Status Register).Only bits unmasked by PIO_OWSR (Output Write Status Register) are written. The mask bits in PIO_OWSR are set by writing to PIO_OWER (Output Write Enable Register) and cleared by writing to PIO_OWDR (Output Write Disable Register). After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0.

31.5.6 MULTI DRIVE CONTROL (OPEN DRAIN)

Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line. The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or assigned to a periph- eral function. PIO_MDSR (Multi-driver Status Register) indicates the pins that are configured to support external drivers. After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0.

31.5.7 INPUTS

The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral. Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.

31.5.8 INPUT GLITCH AND DEBOUNCING FILTERS

Optional input glitch and debouncing filters are independently programmable on each I/O line. The glitch filter can filter a glitch with a duration of less than 1/2 Master Clock (MCK) and the debouncing filter can filter a pulse of less than 1/2 Period of a Programmable Divided Slow Clock. The selection between glitch filtering or debounce filtering is done by writing in the registers PIO_SCIFSR (System Clock Glitch Input Filter Select Register) and PIO_DIFSR (Debouncing Input Filter Select Register). Writing PIO_SCIFSR and PIO_DIFSR respectively, sets and clears bits in PIO_IFDGSR. The current selection status can be checked by reading the register PIO_IFDGSR (Glitch or Debouncing Input Filter Selection Status Register).

• If PIO_IFDGSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 Period of Master Clock.
• If PIO_IFDGSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2 Period of the Pro- grammable Divided Slow Clock.

DS60001614B-page 504  2020 Microchip Technology Inc. For the debouncing filter, the Period of the Divided Slow Clock is performed by writing in the DIV field of the PIO_SCDR (Slow Clock Divider Register) Tdiv_slclk = ((DIV+1)*2).Tslow_clock When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2 Selected Clock Cycle (Selected Clock represents MCK or Divided Slow Clock depending on PIO_SCIFSR and PIO_DIFSR programming) is automatically rejected, while a pulse with a duration of 1 Selected Clock (MCK or Divided Slow Clock) cycle or more is accepted. For pulse durations between 1/2 Selected Clock cycle and 1 Selected Clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1 Selected Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 Selected Clock cycle. The glitch filters are controlled by the register set: PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter Dis- able Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines. When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch and debouncing filters require that the PIO Controller clock is enabled.

31.5.9 INPUT EDGE/LEVEL INTERRUPT

The PIO Controller can be programmed to generate an interrupt when it detects an edge or a level on an I/O line. The Input Edge/Level Interrupt is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask Register). As Input change detection is possible only by comparing two successive sam- plings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or assigned to a peripheral function. By default, the interrupt can be generated at any time an edge is detected on the input. Some additional Interrupt modes can be enabled/disabled by writing in the PIO_AIMER (Additional Interrupt Modes Enable Register) and PIO_AIMDR (Additional Interrupt Modes Disable Register). The current state of this selection can be read through the PIO_AIMMR (Additional Interrupt Modes Mask Register) These Additional Modes are:

• Rising Edge Detection
• Falling Edge Detection
• Low Level Detection
• High Level Detection In order to select an Additional Interrupt Mode:
• The type of event detection (Edge or Level) must be selected by writing in the set of registers; PIO_ESR (Edge Select Register) and PIO_LSR (Level Select Register) which enable respectively, the Edge and Level Detection. The current status of this selection is accessible through the PIO_ELSR (Edge/Level Status Register).
• The Polarity of the event detection (Rising/Falling Edge or High/Low Level) must be selected by writing in the set of registers; PIO_FELLSR (Falling Edge /Low Level Select Register) and PIO_REHLSR (Rising Edge/High Level Select Register) which allow to select Falling or Rising Edge (if Edge is selected in the PIO_ELSR) Edge or High or Low Level Detection (if Level is selected in the PIO_ELSR). The current status of this selection is accessible through the PIO_FRLHSR (Fall/Rise - Low/High Status Register). When an input Edge or Level is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to generate a single interrupt signal to the Nested Vector Interrupt Control- ler (NVIC). When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled. When an Interrupt is enabled on a “Level”, the interrupt is gener- ated as long as the interrupt source is not cleared, even if some read accesses in PIO_ISR are performed.

 2020 Microchip Technology Inc. DS60001614B-page 505 SAM3X8ERT

31.5.9.1 Example

If generating an interrupt is required on the following:

• Rising edge on PIO line 0
• Falling edge on PIO line 1
• Rising edge on PIO line 2
• Low Level on PIO line 3
• High Level on PIO line 4
• High Level on PIO line 5
• Falling edge on PIO line 6
• Rising edge on PIO line 7
• Any edge on the other lines The configuration required is described below.

31.5.9.2 Interrupt Mode Configuration

All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER. Then the Additional Interrupt Mode is enabled for line 0 to 7 by writing 32’h0000_00FF in PIO_AIMER.

31.5.9.3 Edge or Level Detection Configuration

Lines 3, 4 and 5 are configured in Level detection by writing 32’h0000_0038 in PIO_LSR. The other lines are configured in Edge detection by default, if they have not been previously configured. Otherwise, lines 0, 1, 2, 6 and 7 must be configured in Edge detection by writing 32’h0000_00C7 in PIO_ESR. 31.5.9.4 Falling/Rising Edge or Low/High Level Detection Configuration. Lines 0, 2, 4, 5 and 7 are configured in Rising Edge or High Level detection by writing 32’h0000_00B5 in PIO_REHLSR. The other lines are configured in Falling Edge or Low Level detection by default, if they have not been previously con- figured. Otherwise, lines 1, 3 and 6 must be configured in Falling Edge/Low Level detection by writing 32’h0000_004A in PIO_FELLSR.

31.5.10 I/O LINES LOCK

When an I/O line is controlled by a peripheral (particularly the Pulse Width Modulation Controller PWM), it can become locked by the action of this peripheral via an input of the PIO controller. When an I/O line is locked, the write of the cor- responding bit in the registers PIO_PER, PIO_PDR, PIO_MDER, PIO_MDDR, PIO_PUDR, PIO_PUER and PIO_ABSR is discarded in order to lock its configuration. The user can know at anytime which I/O line is locked by reading the PIO Lock Status register PIO_LOCKSR. Once an I/O line is locked, the only way to unlock it is to apply an hardware reset to the PIO Controller.

DS60001614B-page 506  2020 Microchip Technology Inc.

31.6 I/O Lines Programming Example

The programing example as shown in Table 31-1 below is used to obtain the following configuration.

• 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor
• Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor
• Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts
• Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter
• I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor
• I/O lines 20 to 23 assigned to peripheral B functions, no pull-up resistor
• I/O line 24 to 27 assigned to peripheral A with Input Change Interrupt and pull-up resistor FIGURE 31-1: PROGRAMMING EXAMPLE Register Value to be Written PIO_PER 0x0000 FFFF PIO_PDR 0xFFFF 0000 PIO_OER 0x0000 00FF PIO_ODR 0xFFFF FF00 PIO_IFER 0x0000 0F00 PIO_IFDR 0xFFFF F0FF PIO_SODR 0x0000 0000 PIO_CODR 0x0FFF FFFF PIO_IER 0x0F00 0F00 PIO_IDR 0xF0FF F0FF PIO_MDER 0x0000 000F PIO_MDDR 0xFFFF FFF0 PIO_PUDR 0xF0F0 00F0 PIO_PUER 0x0F0F FF0F PIO_ABSR 0x00F0 0000 PIO_OWER 0x0000 000F PIO_OWDR 0x0FFF FFF0

 2020 Microchip Technology Inc. DS60001614B-page 507 SAM3X8ERT

31.6.1 WRITE PROTECTION REGISTERS

To prevent any single software error that may corrupt PIO behavior, certain address spaces can be write-protected by setting the WPEN bit in the “PIO Write Protect Mode Register” on page 532 (PIO_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the PIO Write Protect Status Register (PIO_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. The WPVS flag is reset by writing the PIO Write Protect Mode Register (PIO_WPMR) with the appropriate access key, WPKEY . The protected registers are:

• “PIO Controller PIO Enable Register” on page 511
• “PIO Controller PIO Disable Register” on page 511
• “PIO Controller Output Enable Register” on page 512
• “PIO Controller Output Disable Register” on page 513
• “PIO Controller Input Filter Enable Register” on page 514
• “PIO Controller Input Filter Disable Register” on page 514
• “PIO Multi-driver Enable Register” on page 519
• “PIO Multi-driver Disable Register” on page 520
• “PIO Pull Up Disable Register” on page 521
• “PIO Pull Up Enable Register” on page 521
• “PIO Peripheral AB Select Register” on page 522
• “PIO Output Write Enable Register” on page 525
• “PIO Output Write Disable Register” on page 525

DS60001614B-page 508  2020 Microchip Technology Inc.

31.7 Parallel Input/Output Controller (PIO) User Interface

Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface reg - isters. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Con- troller and PIO_PSR returns 1 systematically. FIGURE 31-1: REGISTER MAPPING Offset Register Name Access Reset 0x0000 PIO Enable Register PIO_PER Write-only — 0x0004 PIO Disable Register PIO_PDR Write-only — 0x0008 PIO Status Register PIO_PSR Read-only (1) 0x000C Reserved — — — 0x0010 Output Enable Register PIO_OER Write-only — 0x0014 Output Disable Register PIO_ODR Write-only — 0x0018 Output Status Register PIO_OSR Read-only 0x0000 0000 0x001C Reserved — — — 0x0020 Glitch Input Filter Enable Register PIO_IFER Write-only — 0x0024 Glitch Input Filter Disable Register PIO_IFDR Write-only — 0x0028 Glitch Input Filter Status Register PIO_IFSR Read-only 0x0000 0000 0x002C Reserved — — — 0x0030 Set Output Data Register PIO_SODR Write-only — 0x0034 Clear Output Data Register PIO_CODR Write-only — 0x0038 Output Data Status Register PIO_ODSR Read-only or(2) Read-write 0x003C Pin Data Status Register PIO_PDSR Read-only (3) 0x0040 Interrupt Enable Register PIO_IER Write-only — 0x0044 Interrupt Disable Register PIO_IDR Write-only — 0x0048 Interrupt Mask Register PIO_IMR Read-only 0x00000000 0x004C Interrupt Status Register(4) PIO_ISR Read-only 0x00000000 0x0050 Multi-driver Enable Register PIO_MDER Write-only — 0x0054 Multi-driver Disable Register PIO_MDDR Write-only — 0x0058 Multi-driver Status Register PIO_MDSR Read-only 0x00000000 0x005C Reserved — — — 0x0060 Pull-up Disable Register PIO_PUDR Write-only — 0x0064 Pull-up Enable Register PIO_PUER Write-only — 0x0068 Pad Pull-up Status Register PIO_PUSR Read-only 0x00000000 0x006C Reserved — — —

 2020 Microchip Technology Inc. DS60001614B-page 509 SAM3X8ERT Note 1: Reset value of PIO_PSR depends on the product implementation. 2: PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. 3: Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 4: PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred. 0x0070 Peripheral AB Select Register(5) PIO_ABSR Read-Write 0x00000000 0x0074 to 0x007C Reserved — — — 0x0080 System Clock Glitch Input Filter Select Register PIO_SCIFSR Write-Only — 0x0084 Debouncing Input Filter Select Register PIO_DIFSR Write-Only — 0x0088 Glitch or Debouncing Input Filter Clock Selection Status Register PIO_IFDGSR Read-Only 0x00000000 0x008C Slow Clock Divider Debouncing Register PIO_SCDR Read-Write 0x00000000 0x0090 to 0x009C Reserved — — — 0x00A0 Output Write Enable PIO_OWER Write-only — 0x00A4 Output Write Disable PIO_OWDR Write-only — 0x00A8 Output Write Status Register PIO_OWSR Read-only 0x00000000 0x00AC Reserved — — — 0x00B0 Additional Interrupt Modes Enable Register PIO_AIMER Write-Only — 0x00B4 Additional Interrupt Modes Disables Register PIO_AIMDR Write-Only — 0x00B8 Additional Interrupt Modes Mask Register PIO_AIMMR Read-Only 0x00000000 0x00BC Reserved — — — 0x00C0 Edge Select Register PIO_ESR Write-Only — 0x00C4 Level Select Register PIO_LSR Write-Only — 0x00C8 Edge/Level Status Register PIO_ELSR Read-Only 0x00000000 0x00CC Reserved — — — 0x00D0 Falling Edge/Low Level Select Register PIO_FELLSR Write-Only — 0x00D4 Rising Edge/ High Level Select Register PIO_REHLSR Write-Only — 0x00D8 Fall/Rise - Low/High Status Register PIO_FRLHSR Read-Only 0x00000000 0x00DC Reserved — — — 0x00E0 Lock Status PIO_LOCKSR Read-Only 0x00000000 0x00E4 Write Protect Mode Register PIO_WPMR Read-write 0x0 0x00E8 Write Protect Status Register PIO_WPSR Read-only 0x0 0x00EC to 0x00F8 Reserved — — — 0x0100 to 0x0144 Reserved — — — FIGURE 31-1: REGISTER MAPPING (CONTINUED) Offset Register Name Access Reset

DS60001614B-page 510  2020 Microchip Technology Inc. 5: Only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the second register.

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31.7.1 PIO CONTROLLER PIO ENABLE REGISTER

Name:PIO_PER Address:0x400E0E00 (PIOA), 0x400E1000 (PIOB), 0x400E1200 (PIOC), 0x400E1400 (PIOD), 0x400E1600 (PIOE), 0x400E1800 (PIOF) Access:Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” on page 532.

• P0-P31: PIO Enable 0: No effect. 1: Enables the PIO to control the corresponding pin (disables peripheral control of the pin).

31.7.2 PIO CONTROLLER PIO DISABLE REGISTER

Name:PIO_PDR Address:0x400E0E04 (PIOA), 0x400E1004 (PIOB), 0x400E1204 (PIOC), 0x400E1404 (PIOD), 0x400E1604 (PIOE), 0x400E1804 (PIOF) Access:Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” on page 532.

• P0-P31: PIO Disable 0: No effect. 1: Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin). 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

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31.7.3 PIO CONTROLLER PIO STATUS REGISTER

Name:PIO_PSR Address:0x400E0E08 (PIOA), 0x400E1008 (PIOB), 0x400E1208 (PIOC), 0x400E1408 (PIOD), 0x400E1608 (PIOE), 0x400E1808 (PIOF) Access:Read-only

• P0-P31: PIO Status 0: PIO is inactive on the corresponding I/O line (peripheral is active). 1: PIO is active on the corresponding I/O line (peripheral is inactive).

31.7.4 PIO CONTROLLER OUTPUT ENABLE REGISTER

Name:PIO_OER Address:0x400E0E10 (PIOA), 0x400E1010 (PIOB), 0x400E1210 (PIOC), 0x400E1410 (PIOD), 0x400E1610 (PIOE), 0x400E1810 (PIOF) Access:Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” on page 532.

• P0-P31: Output Enable 0: No effect. 1: Enables the output on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

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31.7.5 PIO CONTROLLER OUTPUT DISABLE REGISTER

Name:PIO_ODR Address:0x400E0E14 (PIOA), 0x400E1014 (PIOB), 0x400E1214 (PIOC), 0x400E1414 (PIOD), 0x400E1614 (PIOE), 0x400E1814 (PIOF) Access:Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” on page 532.

• P0-P31: Output Disable 0: No effect. 1: Disables the output on the I/O line.

31.7.6 PIO CONTROLLER OUTPUT STATUS REGISTER

Name:PIO_OSR Address:0x400E0E18 (PIOA), 0x400E1018 (PIOB), 0x400E1218 (PIOC), 0x400E1418 (PIOD), 0x400E1618 (PIOE), 0x400E1818 (PIOF) Access:Read-only

• P0-P31: Output Status 0: The I/O line is a pure input. 1: The I/O line is enabled in output. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

DS60001614B-page 514  2020 Microchip Technology Inc.

31.7.7 PIO CONTROLLER INPUT FILTER ENABLE REGISTER

Name:PIO_IFER Address:0x400E0E20 (PIOA), 0x400E1020 (PIOB), 0x400E1220 (PIOC), 0x400E1420 (PIOD), 0x400E1620 (PIOE), 0x400E1820 (PIOF) Access:Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” on page 532.

• P0-P31: Input Filter Enable 0: No effect. 1: Enables the input glitch filter on the I/O line.

31.7.8 PIO CONTROLLER INPUT FILTER DISABLE REGISTER

Name:PIO_IFDR Address:0x400E0E24 (PIOA), 0x400E1024 (PIOB), 0x400E1224 (PIOC), 0x400E1424 (PIOD), 0x400E1624 (PIOE), 0x400E1824 (PIOF) Access:Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” on page 532.

• P0-P31: Input Filter Disable 0: No effect. 1: Disables the input glitch filter on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

 2020 Microchip Technology Inc. DS60001614B-page 515 SAM3X8ERT

31.7.9 PIO CONTROLLER INPUT FILTER STATUS REGISTER

Name:PIO_IFSR Address:0x400E0E28 (PIOA), 0x400E1028 (PIOB), 0x400E1228 (PIOC), 0x400E1428 (PIOD), 0x400E1628 (PIOE), 0x400E1828 (PIOF) Access:Read-only

• P0-P31: Input Filer Status 0: The input glitch filter is disabled on the I/O line. 1: The input glitch filter is enabled on the I/O line.

31.7.10 PIO CONTROLLER SET OUTPUT DATA REGISTER

Name:PIO_SODR Address:0x400E0E30 (PIOA), 0x400E1030 (PIOB), 0x400E1230 (PIOC), 0x400E1430 (PIOD), 0x400E1630 (PIOE), 0x400E1830 (PIOF) Access:Write-only

• P0-P31: Set Output Data 0: No effect. 1: Sets the data to be driven on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

DS60001614B-page 516  2020 Microchip Technology Inc.

31.7.11 PIO CONTROLLER CLEAR OUTPUT DATA REGISTER

Name:PIO_CODR Address:0x400E0E34 (PIOA), 0x400E1034 (PIOB), 0x400E1234 (PIOC), 0x400E1434 (PIOD), 0x400E1634 (PIOE), 0x400E1834 (PIOF) Access:Write-only

• P0-P31: Clear Output Data 0: No effect. 1: Clears the data to be driven on the I/O line.

31.7.12 PIO CONTROLLER OUTPUT DATA STATUS REGISTER

Name:PIO_ODSR Address:0x400E0E38 (PIOA), 0x400E1038 (PIOB), 0x400E1238 (PIOC), 0x400E1438 (PIOD), 0x400E1638 (PIOE), 0x400E1838 (PIOF) Access:Read-only or Read/Write

• P0-P31: Output Data Status 0: The data to be driven on the I/O line is 0. 1: The data to be driven on the I/O line is 1. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

 2020 Microchip Technology Inc. DS60001614B-page 517 SAM3X8ERT

31.7.13 PIO CONTROLLER PIN DATA STATUS REGISTER

Name:PIO_PDSR Address:0x400E0E3C (PIOA), 0x400E103C (PIOB), 0x400E123C (PIOC), 0x400E143C (PIOD), 0x400E163C (PIOE), 0x400E183C (PIOF) Access:Read-only

• P0-P31: Output Data Status 0: The I/O line is at level 0. 1: The I/O line is at level 1.

31.7.14 PIO CONTROLLER INTERRUPT ENABLE REGISTER

Name:PIO_IER Address:0x400E0E40 (PIOA), 0x400E1040 (PIOB), 0x400E1240 (PIOC), 0x400E1440 (PIOD), 0x400E1640 (PIOE), 0x400E1840 (PIOF) Access:Write-only

• P0-P31: Input Change Interrupt Enable 0: No effect. 1: Enables the Input Change Interrupt on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

DS60001614B-page 518  2020 Microchip Technology Inc.

31.7.15 PIO CONTROLLER INTERRUPT DISABLE REGISTER

Name:PIO_IDR Address:0x400E0E44 (PIOA), 0x400E1044 (PIOB), 0x400E1244 (PIOC), 0x400E1444 (PIOD), 0x400E1644 (PIOE), 0x400E1844 (PIOF) Access:Write-only

• P0-P31: Input Change Interrupt Disable 0: No effect. 1: Disables the Input Change Interrupt on the I/O line.

31.7.16 PIO CONTROLLER INTERRUPT MASK REGISTER

Name:PIO_IMR Address:0x400E0E48 (PIOA), 0x400E1048 (PIOB), 0x400E1248 (PIOC), 0x400E1448 (PIOD), 0x400E1648 (PIOE), 0x400E1848 (PIOF) Access:Read-only

• P0-P31: Input Change Interrupt Mask 0: Input Change Interrupt is disabled on the I/O line. 1: Input Change Interrupt is enabled on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

 2020 Microchip Technology Inc. DS60001614B-page 519 SAM3X8ERT

31.7.17 PIO CONTROLLER INTERRUPT STATUS REGISTER

Name:PIO_ISR Address:0x400E0E4C (PIOA), 0x400E104C (PIOB), 0x400E124C (PIOC), 0x400E144C (PIOD), 0x400E164C (PIOE), 0x400E184C (PIOF) Access:Read-only

• P0-P31: Input Change Interrupt Status 0: No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 1: At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.

31.7.18 PIO MULTI-DRIVER ENABLE REGISTER

Name:PIO_MDER Address:0x400E0E50 (PIOA), 0x400E1050 (PIOB), 0x400E1250 (PIOC), 0x400E1450 (PIOD), 0x400E1650 (PIOE), 0x400E1850 (PIOF) Access:Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” on page 532.

• P0-P31: Multi Drive Enable. 0: No effect. 1: Enables Multi Drive on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

DS60001614B-page 520  2020 Microchip Technology Inc.

31.7.19 PIO MULTI-DRIVER DISABLE REGISTER

Name:PIO_MDDR Address:0x400E0E54 (PIOA), 0x400E1054 (PIOB), 0x400E1254 (PIOC), 0x400E1454 (PIOD), 0x400E1654 (PIOE), 0x400E1854 (PIOF) Access:Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” on page 532.

• P0-P31: Multi Drive Disable. 0: No effect. 1: Disables Multi Drive on the I/O line.

31.7.20 PIO MULTI-DRIVER STATUS REGISTER

Name:PIO_MDSR Address:0x400E0E58 (PIOA), 0x400E1058 (PIOB), 0x400E1258 (PIOC), 0x400E1458 (PIOD), 0x400E1658 (PIOE), 0x400E1858 (PIOF) Access:Read-only

• P0-P31: Multi Drive Status. 0: The Multi Drive is disabled on the I/O line. The pin is driven at high and low level. 1: The Multi Drive is enabled on the I/O line. The pin is driven at low level only. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

 2020 Microchip Technology Inc. DS60001614B-page 521 SAM3X8ERT

31.7.21 PIO PULL UP DISABLE REGISTER

Name:PIO_PUDR Address:0x400E0E60 (PIOA), 0x400E1060 (PIOB), 0x400E1260 (PIOC), 0x400E1460 (PIOD), 0x400E1660 (PIOE), 0x400E1860 (PIOF) Access:Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” on page 532.

• P0-P31: Pull Up Disable. 0: No effect. 1: Disables the pull up resistor on the I/O line.

31.7.22 PIO PULL UP ENABLE REGISTER

Name:PIO_PUER Address:0x400E0E64 (PIOA), 0x400E1064 (PIOB), 0x400E1264 (PIOC), 0x400E1464 (PIOD), 0x400E1664 (PIOE), 0x400E1864 (PIOF) Access:Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” on page 532.

• P0-P31: Pull Up Enable. 0: No effect. 1: Enables the pull up resistor on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

DS60001614B-page 522  2020 Microchip Technology Inc.

31.7.23 PIO PULL UP STATUS REGISTER

Name:PIO_PUSR Address:0x400E0E68 (PIOA), 0x400E1068 (PIOB), 0x400E1268 (PIOC), 0x400E1468 (PIOD), 0x400E1668 (PIOE), 0x400E1868 (PIOF) Access:Read-only

• P0-P31: Pull Up Status. 0: Pull Up resistor is enabled on the I/O line. 1: Pull Up resistor is disabled on the I/O line.

31.7.24 PIO PERIPHERAL AB SELECT REGISTER

Name:PIO_ABSR Address:0x400E0E70 (PIOA), 0x400E1070 (PIOB), 0x400E1270 (PIOC), 0x400E1470 (PIOD), 0x400E1670 (PIOE), 0x400E1870 (PIOF) Access:Read-Write This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” on page 532.

• P0-P31: Peripheral A Select. 0: Assigns the I/O line to the Peripheral A function. 1: Assigns the I/O line to the Peripheral B function. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

 2020 Microchip Technology Inc. DS60001614B-page 523 SAM3X8ERT

31.7.25 PIO SYSTEM CLOCK GLITCH INPUT FILTERING SELECT REGISTER

Name:PIO_SCIFSR Address:0x400E0E80 (PIOA), 0x400E1080 (PIOB), 0x400E1280 (PIOC), 0x400E1480 (PIOD), 0x400E1680 (PIOE), 0x400E1880 (PIOF) Access:Write-only

• P0-P31: System Clock Glitch Filtering Select. 0: No Effect. 1: The Glitch Filter is able to filter glitches with a duration < Tmck/2.

31.7.26 PIO DEBOUNCING INPUT FILTERING SELECT REGISTER

Name:PIO_DIFSR Address:0x400E0E84 (PIOA), 0x400E1084 (PIOB), 0x400E1284 (PIOC), 0x400E1484 (PIOD), 0x400E1684 (PIOE), 0x400E1884 (PIOF) Access:Write-only

• P0-P31: Debouncing Filtering Select. 0: No Effect. 1: The Debouncing Filter is able to filter pulses with a duration < Tdiv_slclk/2. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

DS60001614B-page 524  2020 Microchip Technology Inc.

31.7.27 PIO GLITCH OR DEBOUNCING INPUT FILTER SELECTION STATUS REGISTER

Name:PIO_IFDGSR Address:0x400E0E88 (PIOA), 0x400E1088 (PIOB), 0x400E1288 (PIOC), 0x400E1488 (PIOD), 0x400E1688 (PIOE), 0x400E1888 (PIOF) Access:Read-only

• P0-P31: Glitch or Debouncing Filter Selection Status 0: The Glitch Filter is able to filter glitches with a duration < Tmck2. 1: The Debouncing Filter is able to filter pulses with a duration < Tdiv_slclk/2.

31.7.28 PIO SLOW CLOCK DIVIDER DEBOUNCING REGISTER

Name:PIO_SCDR Address:0x400E0E8C (PIOA), 0x400E108C (PIOB), 0x400E128C (PIOC), 0x400E148C (PIOD), 0x400E168C (PIOE), 0x400E188C (PIOF) Access:Read-Write

• DIV: Slow Clock Divider Selection for Debouncing Tdiv_slclk = 2*(DIV+1)*Tslow_clock. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - DIV13 DIV12 DIV11 DIV10 DIV9 DIV8 7 6 5 4 3 2 1 0 DIV7 DIV6 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0

 2020 Microchip Technology Inc. DS60001614B-page 525 SAM3X8ERT

31.7.29 PIO OUTPUT WRITE ENABLE REGISTER

Name:PIO_OWER Address:0x400E0EA0 (PIOA), 0x400E10A0 (PIOB), 0x400E12A0 (PIOC), 0x400E14A0 (PIOD), 0x400E16A0 (PIOE), 0x400E18A0 (PIOF) Access:Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” on page 532.

• P0-P31: Output Write Enable. 0: No effect. 1: Enables writing PIO_ODSR for the I/O line.

31.7.30 PIO OUTPUT WRITE DISABLE REGISTER

Name:PIO_OWDR Address:0x400E0EA4 (PIOA), 0x400E10A4 (PIOB), 0x400E12A4 (PIOC), 0x400E14A4 (PIOD), 0x400E16A4 (PIOE), 0x400E18A4 (PIOF) Access:Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” on page 532.

• P0-P31: Output Write Disable. 0: No effect. 1: Disables writing PIO_ODSR for the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

DS60001614B-page 526  2020 Microchip Technology Inc.

31.7.31 PIO OUTPUT WRITE STATUS REGISTER

Name:PIO_OWSR Address:0x400E0EA8 (PIOA), 0x400E10A8 (PIOB), 0x400E12A8 (PIOC), 0x400E14A8 (PIOD), 0x400E16A8 (PIOE), 0x400E18A8 (PIOF) Access:Read-only

• P0-P31: Output Write Status. 0: Writing PIO_ODSR does not affect the I/O line. 1: Writing PIO_ODSR affects the I/O line.

31.7.32 ADDITIONAL INTERRUPT MODES ENABLE REGISTER

Name:PIO_AIMER Address:0x400E0EB0 (PIOA), 0x400E10B0 (PIOB), 0x400E12B0 (PIOC), 0x400E14B0 (PIOD), 0x400E16B0 (PIOE), 0x400E18B0 (PIOF) Access:Write-only

• P0-P31: Additional Interrupt Modes Enable. 0: No effect. 1: The interrupt source is the event described in PIO_ELSR and PIO_FRLHSR. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

 2020 Microchip Technology Inc. DS60001614B-page 527 SAM3X8ERT

31.7.33 ADDITIONAL INTERRUPT MODES DISABLE REGISTER

Name:PIO_AIMDR Address:0x400E0EB4 (PIOA), 0x400E10B4 (PIOB), 0x400E12B4 (PIOC), 0x400E14B4 (PIOD), 0x400E16B4 (PIOE), 0x400E18B4 (PIOF) Access:Write-only

• P0-P31: Additional Interrupt Modes Disable. 0: No effect. 1: The interrupt mode is set to the default interrupt mode (Both Edge detection).

31.7.34 ADDITIONAL INTERRUPT MODES MASK REGISTER

Name:PIO_AIMMR Address:0x400E0EB8 (PIOA), 0x400E10B8 (PIOB), 0x400E12B8 (PIOC), 0x400E14B8 (PIOD), 0x400E16B8 (PIOE), 0x400E18B8 (PIOF) Access:Read-only

• P0-P31: Peripheral CD Status. 0: The interrupt source is a Both Edge detection event 1: The interrupt source is described by the registers PIO_ELSR and PIO_FRLHSR 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

DS60001614B-page 528  2020 Microchip Technology Inc.

31.7.35 EDGE SELECT REGISTER

Name:PIO_ESR Address:0x400E0EC0 (PIOA), 0x400E10C0 (PIOB), 0x400E12C0 (PIOC), 0x400E14C0 (PIOD), 0x400E16C0 (PIOE), 0x400E18C0 (PIOF) Access:Write-only

• P0-P31: Edge Interrupt Selection. 0: No effect. 1: The interrupt source is an Edge detection event.

31.7.36 LEVEL SELECT REGISTER

Name:PIO_LSR Address:0x400E0EC4 (PIOA), 0x400E10C4 (PIOB), 0x400E12C4 (PIOC), 0x400E14C4 (PIOD), 0x400E16C4 (PIOE), 0x400E18C4 (PIOF) Access:Write-only

• P0-P31: Level Interrupt Selection. 0: No effect. 1: The interrupt source is a Level detection event. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

 2020 Microchip Technology Inc. DS60001614B-page 529 SAM3X8ERT

31.7.37 EDGE/LEVEL STATUS REGISTER

Name:PIO_ELSR Address:0x400E0EC8 (PIOA), 0x400E10C8 (PIOB), 0x400E12C8 (PIOC), 0x400E14C8 (PIOD), 0x400E16C8 (PIOE), 0x400E18C8 (PIOF) Access:Read-only

• P0-P31: Edge/Level Interrupt source selection. 0: The interrupt source is an Edge detection event. 1: The interrupt source is a Level detection event.

31.7.38 FALLING EDGE/LOW LEVEL SELECT REGISTER

Name:PIO_FELLSR Address:0x400E0ED0 (PIOA), 0x400E10D0 (PIOB), 0x400E12D0 (PIOC), 0x400E14D0 (PIOD), 0x400E16D0 (PIOE), 0x400E18D0 (PIOF) Access:Write-only

• P0-P31: Falling Edge/Low Level Interrupt Selection. 0: No effect. 1: The interrupt source is set to a Falling Edge detection or Low Level detection event, depending on PIO_ELSR. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

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31.7.39 RISING EDGE/HIGH LEVEL SELECT REGISTER

Name:PIO_REHLSR Address:0x400E0ED4 (PIOA), 0x400E10D4 (PIOB), 0x400E12D4 (PIOC), 0x400E14D4 (PIOD), 0x400E16D4 (PIOE), 0x400E18D4 (PIOF) Access:Write-only

• P0-P31: Rising Edge /High Level Interrupt Selection. 0: No effect. 1: The interrupt source is set to a Rising Edge detection or High Level detection event, depending on PIO_ELSR.

31.7.40 FALL/RISE - LOW/HIGH STATUS REGISTER

Name:PIO_FRLHSR Address:0x400E0ED8 (PIOA), 0x400E10D8 (PIOB), 0x400E12D8 (PIOC), 0x400E14D8 (PIOD), 0x400E16D8 (PIOE), 0x400E18D8 (PIOF) Access:Read-only

• P0-P31: Edge /Level Interrupt Source Selection. 0: The interrupt source is a Falling Edge detection (if PIO_ELSR = 0) or Low Level detection event (if PIO_ELSR = 1). 1: The interrupt source is a Rising Edge detection (if PIO_ELSR = 0) or High Level detection event (if PIO_ELSR = 1). 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

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31.7.41 LOCK STATUS REGISTER

Name:PIO_LOCKSR Address:0x400E0EE0 (PIOA), 0x400E10E0 (PIOB), 0x400E12E0 (PIOC), 0x400E14E0 (PIOD), 0x400E16E0 (PIOE), 0x400E18E0 (PIOF) Access:Read-only

• P0-P31: Lock Status. 0: The I/O line is not locked. 1: The I/O line is locked. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

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31.7.42 PIO WRITE PROTECT MODE REGISTER

Name:PIO_WPMR Address:0x400E0EE4 (PIOA), 0x400E10E4 (PIOB), 0x400E12E4 (PIOC), 0x400E14E4 (PIOD), 0x400E16E4 (PIOE), 0x400E18E4 (PIOF) Access:Read-write Reset:See Table 31-1 For more information on Write Protection Registers, refer to “Write Protection Registers” on page 507.

• WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x50494F (“PIO” in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x50494F (“PIO” in ASCII). Protects the registers:
• “PIO Controller PIO Enable Register” on page 511
• “PIO Controller PIO Disable Register” on page 511
• “PIO Controller Output Enable Register” on page 512
• “PIO Controller Output Disable Register” on page 513
• “PIO Controller Input Filter Enable Register” on page 514
• “PIO Controller Input Filter Disable Register” on page 514
• “PIO Multi-driver Enable Register” on page 519
• “PIO Multi-driver Disable Register” on page 520
• “PIO Pull Up Disable Register” on page 521
• “PIO Pull Up Enable Register” on page 521
• “PIO Peripheral AB Select Register” on page 522
• “PIO Output Write Enable Register” on page 525
• “PIO Output Write Disable Register” on page 525
• WPKEY: Write Protect KEY Should be written at value 0x50494F (“PIO” in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 7 6 5 4 3 2 1 0

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31.7.43 PIO WRITE PROTECT STATUS REGISTER

Name:PIO_WPSR Address:0x400E0EE8 (PIOA), 0x400E10E8 (PIOB), 0x400E12E8 (PIOC), 0x400E14E8 (PIOD), 0x400E16E8 (PIOE), 0x400E18E8 (PIOF) Access:Read-only Reset:See Table 31-1

• WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last read of the PIO_WPSR register. 1: A Write Protect Violation has occurred since the last read of the PIO_WPSR register. If this violation is an unautho - rized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. Note: Reading PIO_WPSR automatically clears all fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WPVSRC 15 14 13 12 11 10 9 8 WPVSRC 7 6 5 4 3 2 1 0

DS60001614B-page 534  2020 Microchip Technology Inc.

32.0 SERIAL PERIPHERAL INTERFACE (SPI)

32.1 Description

The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is con - nected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as “slaves'' which have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple Master Protocol oppo- site to Single Master Protocol where one CPU is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines:

• Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s).
• Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer.
• Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted.
• Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.

32.2 Embedded Characteristics

• Supports Communication with Serial External Devices - Four Chip Selects with External Decoder Support Allow Communication with Up to 15 Peripherals - Serial Memories, such as DataFlash and 3-wire EEPROMs - Serial Peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors - External Co-processors
• Master or Slave Serial Peripheral Bus Interface - 8- to 16-bit Programmable Data Length Per Chip Select - Programmable Phase and Polarity Per Chip Select - Programmable Transfer Delay Between Consecutive Transfers and Delay Before SPI Clock per Chip Select - Programmable Delay Between Chip Selects - Selectable Mode Fault Detection
• Connection to PDC Channel Capabilities Optimizes Data Transfers - One Channel for the Receiver, One Channel for the Transmitter - Next Buffer Support
• Connection to DMA Channel Capabilities Optimizes Data Transfers - One channel for the Receiver, One Channel for the Transmitter

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32.3 Block Diagram

FIGURE 32-1: BLOCK DIAGRAM FIGURE 32-2: BLOCK DIAGRAM SPI Interface Interrupt Control PIO PDC PMC MCK SPI Interrupt SPCK MISO MOSI NPCS0/NSS NPCS1 NPCS2 NPCS3 APB SPI Interface Interrupt Control PIO Peripheral Bridge DMA Ch.AHB Matrix PMC MCK SPI Interrupt SPCK MISO MOSI NPCS0/NSS NPCS1 NPCS2 NPCS3 APB

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32.4 Application Block Diagram

FIGURE 32-3: APPLICATION BLOCK DIAGRAM: SINGLE MASTER/MULTIPLE SLAVE IMPLEMENTATION

32.5 Signal Description

32.6 Product Dependencies

32.6.1 I/O LINES

The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions. TABLE 32-1: SIGNAL DESCRIPTION Pin Name Pin Description Type Master Slave MISO Master In Slave Out Input Output MOSI Master Out Slave In Output Input SPCK Serial Clock Output Input NPCS1-NPCS3 Peripheral Chip Selects Output Unused NPCS0/NSS Peripheral Chip Select/Slave Select Output Input TABLE 32-2: I/O LINES Instance Signal I/O Line Peripheral SPI0 SPI0_MISO PA25 A SPI0 SPI0_MOSI PA26 A SPI0 SPI0_NPCS0 PA28 A SPI0 SPI0_NPCS1 PA29 A SPI0 SPI0_NPCS1 PB20 B SPI Master SPCK MISO MOSI NPCS0 NPCS1 NPCS2 SPCK MISO MOSI NSS Slave 0 SPCK MISO MOSI NSS Slave 1 SPCK MISO MOSI NSS Slave 2 NC NPCS3

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32.6.2 POWER MANAGEMENT

The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SPI clock.

32.6.3 INTERRUPT

The SPI interface has an interrupt line connected to the Interrupt Controller. Handling the SPI interrupt requires pro - gramming the interrupt controller before configuring the SPI.

32.6.4 PERIPHERAL DMA CONTROLLER (PDMA) DIRECT MEMORY ACCESS CONTROLLER

(DMAC) The SPI interface can be used in conjunction with the PDMA DMAC in order to reduce processor overhead. For a full description of the PDMA DMAC, refer to the corresponding section in the full datasheet.

32.7 Functional Description

32.7.1 MODES OF OPERATION

The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other purposes. The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in Master Mode.

32.7.2 DATA TRANSFER

Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the Chip Select Register. The clock phase is programmed with the NCPHA bit. These two parameters deter- mine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 32-4 shows the four modes and corresponding parameter settings. SPI0 SPI0_NPCS2 PB21 B SPI0 SPI0_NPCS3 PB23 B SPI0 SPI0_SPCK PA27 A TABLE 32-3: PERIPHERAL IDS Instance ID SPI0 24 SPI1 25 TABLE 32-4: SPI BUS PROTOCOL MODE SPI Mode CPOL NCPHA Shift SPCK Edge Capture SPCK Edge SPCK Inactive Level 0 0 1 Falling Rising Low 1 0 0 Rising Falling Low 2 1 1 Rising Falling High 3 1 0 Falling Rising High TABLE 32-2: I/O LINES

DS60001614B-page 538  2020 Microchip Technology Inc. Figure 32-4 and Figure 32-5 show examples of data transfers. FIGURE 32-4: SPI TRANSFER FORMAT (NCPHA = 1, 8 BITS PER TRANSFER) FIGURE 32-5: SPI TRANSFER FORMAT (NCPHA = 0, 8 BITS PER TRANSFER)

32.7.3 MASTER MODE OPERATIONS

When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register. The holding registers maintain the data flow at a constant rate. SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MISO (from slave) NSS (to slave) SPCK cycle (for reference) MSB MSB LSB LSB * Not defined, but normally MSB of previous character received. 1 2345 786 SPCK (CPOL = 0) SPCK (CPOL = 1) 1 2 345 7 MOSI (from master) MISO (from slave) NSS (to slave) SPCK cycle (for reference) 8 MSB MSB LSB LSB * Not defined but normally LSB of previous character transmitted.

 2020 Microchip Technology Inc. DS60001614B-page 539 SAM3X8ERT After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Transmit Data Register). The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Receiving data cannot occur without transmitting data. If receiving mode is not needed, for example when communicating with a slave receiver only (such as an LCD), the receive status flags in the status register can be discarded. Before writing the TDR, the PCS field in the SPI_MR register must be set in order to select a slave. After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Transmit Data Register). The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Transmission cannot occur without reception. Before writing the TDR, the PCS field must be set in order to select a slave. If new data is written in SPI_TDR during the transfer, it stays in it until the current transfer is completed. Then, the received data is transferred from the Shift Register to SPI_RDR, the data in SPI_TDR is loaded in the Shift Register and a new transfer starts. The transfer of a data written in SPI_TDR in the Shift Register is indicated by the TDRE bit (Transmit Data Register Empty) in the Status Register (SPI_SR). When new data is written in SPI_TDR, this bit is cleared. The TDRE bit is used to trigger the Transmit PDCDMA channel. The end of transfer is indicated by the TXEMPTY flag in the SPI_SR register. If a transfer delay (DLYBCT) is greater than 0 for the last transfer, TXEMPTY is set after the completion of said delay. The master clock (MCK) can be switched off at this time. The transfer of received data from the Shift Register in SPI_RDR is indicated by the RDRF bit (Receive Data Register Full) in the Status Register (SPI_SR). When the received data is read, the RDRF bit is cleared. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. Figure 32-6, shows a block diagram of the SPI when operating in Master Mode. Figure 32-7 shows a flow chart describ- ing how transfers are handled.

DS60001614B-page 540  2020 Microchip Technology Inc.

32.7.3.1 Master Mode Block Diagram

FIGURE 32-6: MASTER MODE BLOCK DIAGRAM Shift Register SPCK MOSILSB MSBMISO SPI_RDR RD SPI Clock TDRE SPI_TDR TD RDRF OVRES SPI_CSR0..3 CPOL NCPHA BITS MCK Baud Rate Generator SPI_CSR0..3 SCBR NPCS3 NPCS0 NPCS2 NPCS1 NPCS0 PS SPI_MR PCS SPI_TDR PCS MODF Current Peripheral SPI_RDR PCS SPI_CSR0..3 CSAAT PCSDEC MODFDIS MSTR

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32.7.3.2 Master Mode Flow Diagram

FIGURE 32-7: MASTER MODE FLOW DIAGRAM SPI Enable CSAAT ? PS ? NPCS = SPI_TDR(PCS) NPCS = SPI_MR(PCS) Delay DLYBS Serializer = SPI_TDR(TD) TDRE = 1 Data Transfer SPI_RDR(RD) = Serializer RDRF = 1 TDRE ? NPCS = 0xF Delay DLYBCS Fixed peripheral Variable peripheral Delay DLYBCT CSAAT ? TDRE ? PS ? SPI_TDR(PCS) = NPCS ? no yes SPI_MR(PCS) = NPCS ? no NPCS = 0xF Delay DLYBCS NPCS = SPI_TDR(PCS) NPCS = 0xF Delay DLYBCS NPCS = SPI_MR(PCS), SPI_TDR(PCS) Fixed peripheral Variable peripheral - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.

DS60001614B-page 542  2020 Microchip Technology Inc. Figure 32-8 shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission Register Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Register) during an 8-bit data transfer in fixed mode and no Peripheral Data Controller involved. FIGURE 32-8: STATUS REGISTER FLAGS BEHAVIOR Figure 32-9 shows Transmission Register Empty (TXEMPTY), End of RX buffer (ENDRX), End of TX buffer (ENDTX), RX Buffer Full (RXBUFF) and TX Buffer Empty (TXBUFE) status flags behavior within the SPI_SR (Status Register) during an 8-bit data transfer in fixed mode with the Peripheral Data Controller involved. The PDC is programmed to transfer and receive three data. The next pointer and counter are not used. The RDRF and TDRE are not shown because these flags are managed by the PDC when using the PDC. FIGURE 32-9: PDC STATUS REGISTER FLAGS BEHAVIOR

32.7.3.3 Clock Generation

The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255. SPCK MOSI (from master) MISO (from slave) NPCS0 MSB MSB LSB LSB 1 2345 78 6 RDRF TDRE TXEMPTY Write in SPI_TDR RDR read shift register empty MSB LSB65432 1 SPCK MOSI (from master) NPCS0 MSB LSB65432 1 12 3 ENDTX TXEMPTY MSB LSB65432 1 MSB LSB65432 1MISO (from slave) MSB LSB65432 1 MSB LSB65432 1 ENDRX TXBUFE RXBUFF

 2020 Microchip Technology Inc. DS60001614B-page 543 SAM3X8ERT This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by 255. Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without repro- gramming.

32.7.3.4 Transfer Delays

Figure 32-10 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be programmed to modify the transfer waveforms:

• The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field in the Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one.
• The delay before SPCK, independently programmable for each chip select by writing the field DLYBS. Allows the start of SPCK to be delayed after the chip select has been asserted.
• The delay between consecutive transfers, independently programmable for each chip select by writing the DLY- BCT field. Allows insertion of a delay between two transfers occurring on the same chip select These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time. FIGURE 32-10: PROGRAMMABLE DELAYS

32.7.3.5 Peripheral Selection

The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS sig- nals are high before and after each transfer.

• Fixed Peripheral Select: SPI exchanges data with only one peripheral Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS field in the SPI_TDR has no effect.
• Variable Peripheral Select: Data can be exchanged with more than one peripheral without having to reprogram the NPCS field in the SPI_MR register. Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the current peripheral. This means that the peripheral selection can be defined for each new data. The value to write in the SPI_TDR register as the following format. [xxxxxxx(7-bit) + LASTXFER(1-bit)(1)+ xxxx(4-bit) + PCS (4-bit) + DATA (8 to 16-bit)] with PCS equals to the chip select to assert as defined in “SPI Transmit Data Register” on page 553 (SPI Transmit Data Register) and LASTXFER bit at 0 or 1 depending on CSAAT bit. Note 1: Optional. CSAAT, LASTXFER and CSNAAT bits are discussed in “Peripheral Deselection with PDC” on page 546 and “Peripheral Deselection with DMAC” on page 546. DLYBCS DLYBS DLYBCT DLYBCT Chip Select 1 Chip Select 2 SPCK

DS60001614B-page 544  2020 Microchip Technology Inc. If LASTXFER is used, the command must be issued before writing the last character. Instead of LASTXFER, the user can use the SPIDIS command. After the end of the DMAPDC transfer, wait for the TXEMPTY flag, then write SPIDIS into the SPI_CR register (this will not change the configuration register values); the NPCS will be deactivated after the last character transfer. Then, another DMAPDC transfer can be started if the SPIEN was previously written in the SPI_CR register.

32.7.3.6 SPI Peripheral DMA Controller (PDC)

In both fixed and variable mode the Peripheral DMA Controller (PDC) can be used to reduce processor overhead. The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed. The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the PDC in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTX- FER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. Transfer Size Depending on the data size to transmit, from 8 to 16 bits, the PDC manages automatically the type of pointer's size it has to point to. The PDC will perform the following transfer size depending on the mode and number of bits per data. Fixed Mode:

• 8-bit Data: Byte transfer, PDC Pointer Address = Address + 1 byte, PDC Counter = Counter - 1
• 8-bit to 16-bit Data: 2 bytes transfer. n-bit data transfer with don’t care data (MSB) filled with 0’s, PDC Pointer Address = Address + 2 bytes, PDC Counter = Counter - 1 Variable Mode: In variable Mode, PDC Pointer Address = Address +4 bytes and PDC Counter = Counter - 1 for 8 to 16-bit transfer size. When using the PDC, the TDRE and RDRF flags are handled by the PDC, thus the user’s application does not have to check those bits. Only End of RX Buffer (ENDRX), End of TX Buffer (ENDTX), Buffer Full (RXBUFF), TX Buffer Empty (TXBUFE) are significant. For further details about the Peripheral DMA Controller and user interface, refer to the PDC section of the product datasheet.

32.7.3.7 SPI Direct Access Memory Controller (DMAC)

In both fixed and variable mode the Direct Memory Access Controller (DMAC) can be used to reduce processor over - head. The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the DMAC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the periph- eral selection requires the Mode Register to be reprogrammed. The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the DMAC in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor.

32.7.3.8 Peripheral Chip Select Decoding

The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to NPCS3 with 1 of up to 16 decoder/demultiplexer. This can be enabled by writing the PCSDEC bit at 1 in the Mode Reg- ister (SPI_MR).

 2020 Microchip Technology Inc. DS60001614B-page 545 SAM3X8ERT When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e., one NPCS line driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low. When operating with decoding, the SPI directly outputs the value defined by the PCS field on NPCS lines of either the Mode Register or the Transmit Data Register (depending on PS). As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. Figure 32-11 below shows such an implementation. If the CSAAT bit is used, with or without the PDC, the Mode Fault detection for NPCS0 line must be disabled. This is not needed for all other chip select lines since Mode Fault Detection is only on NPCS0. If the CSAAT bit is used, with or without the DMAC, the Mode Fault detection for NPCS0 line must be disabled. This is not needed for all other chip select lines since Mode Fault Detection is only on NPCS0. FIGURE 32-11: CHIP SELECT DECODING APPLICATION BLOCK DIAGRAM: SINGLE MASTER/MULTIPLE SLAVE IMPLEMENTATION

32.7.3.9 Peripheral Deselection without DMAC

32.7.3.10 Peripheral Deselection without PDC

During a transfer of more than one data on a Chip Select without the PDCDMAC, the SPI_TDR is loaded by the pro - cessor, the flag TDRE rises as soon as the content of the SPI_TDR is transferred into the internal shift register. When this flag is detected high, the SPI_TDR can be reloaded. If this reload by the processor occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the Chip Select is not de-asserted between the two transfers. But depending on the application software handling the SPI status register flags (by interrupt or polling method) or servicing other interrupts or other tasks, the processor may not reload the SPI_TDR in time to keep the chip select active (low). A null Delay Between Consecutive Transfer (DLYBCT) value in the SPI_CSR register, will give even less time for the processor to reload the SPI_TDR. With some SPI slave peripher- als, requiring the chip select line to remain active (low) during a full set of transfers might lead to communication errors. SPI Master SPCK MISO MOSI NPCS0 NPCS1 NPCS2 SPCK 1-of-n Decoder/Demultiplexer MISO MOSI NSS Slave 0 SPCK MISO MOSI NSS Slave 1 SPCK MISO MOSI NSS Slave 14 NPCS3

DS60001614B-page 546  2020 Microchip Technology Inc. To facilitate interfacing with such devices, the Chip Select Register [CSR0...CSR3] can be programmed with the CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active) until transfer to another chip select is required. Even if the SPI_TDR is not reloaded the chip select will remain active. To have the chip select line to raise at the end of the transfer the Last transfer Bit (LASTXFER) in the SPI_MR register must be set at 1 before writing the last data to transmit into the SPI_TDR.

32.7.3.11 Peripheral Deselection with PDC

When the Peripheral DMA Controller is used, the chip select line will remain low during the whole transfer since the TDRE flag is managed by the PDC itself. The reloading of the SPI_TDR by the PDC is done as soon as TDRE flag is set to one. In this case the use of CSAAT bit might not be needed. However, it may happen that when other PDC chan- nels connected to other peripherals are in use as well, the SPI PDC might be delayed by another (PDC with a higher priority on the bus). Having PDC buffers in slower memories like flash memory compared to fast internal SRAM, may lengthen the reload time of the SPI_TDR by the PDC as well. This means that the SPI_TDR might not be reloaded in time to keep the chip select line low. In this case the chip select line may toggle between data transfer and according to some SPI Slave devices, the communication might get lost. The use of the CSAAT bit might be needed.

32.7.3.12 Peripheral Deselection with DMAC

When the Direct Memory Access Controller is used, the chip select line will remain low during the whole transfer since the TDRE flag is managed by the DMAC itself. The reloading of the SPI_TDR by the DMAC is done as soon as TDRE flag is set to one. In this case the use of CSAAT bit might not be needed. However, it may happen that when other DMAC channels connected to other peripherals are in use as well, the SPI DMAC might be delayed by another (DMAC with a higher priority on the bus). Having DMAC buffers in slower memories like flash memory compared to fast internal SRAM, may lengthen the reload time of the SPI_TDR by the DMAC as well. This means that the SPI_TDR might not be reloaded in time to keep the chip select line low. In this case the chip select line may toggle between data transfer and according to some SPI Slave devices, the communication might get lost. The use of the CSAAT bit might be needed. If chip select must be deasserted between each data when communicating with a slave device such as an SPI ADC for example, one can workaround this by using another “ghost” chip select line. In this case, the variable mode must be used. In this mode, the assertion of the corresponding chip select (CS) depends on the PCS field within SPI_TDR.

• Thereafter, an example of such implementation: NPCS0(1): Actual SPI Slave Device
• NPCS1(1): Ghost SPI Slave Device Transmit Buffer must be initialized in the following way according to the SPI_TDR register (See “SPI Transmit Data Reg- ister” on page 553) to send data equal to 0xAB with NPCS0 and to send data equal to 0xCD on NPCS1. Note: In this case, the size of the buffer will be twice the actual size needed. Note 1: Can be any other chip select line. 2: Transmit Buffer address. Figure 32-13 shows different peripheral deselection cases and the effect of the CSAAT bit. When the CSAAT bit is set at 0, the NPCS does not rise in all cases between two transfers on the same peripheral. During a transfer on a Chip Select, the flag TDRE rises as soon as the content of the SPI_TDR is transferred into the internal shifter. When this flag is detected the SPI_TDR can be reloaded. If this reload occurs before the end of the cur- rent transfer and if the next transfer is performed on the same chip select as the current transfer, the Chip Select is not de-asserted between the two transfers. This might lead to difficulties for interfacing with some serial peripherals requir- ing the chip select to be de-asserted after each transfer. To facilitate interfacing with such devices, the Chip Select Reg- ister can be programmed with the CSNAAT bit (Chip Select Not Active After Transfer) at 1. This allows to de-assert systematically the chip select lines during a time DLYBCS. (The value of the CSNAAT bit is taken into account only if the CSAAT bit is set at 0 for the same Chip Select). Figure 32-12 shows different peripheral deselection cases and the effect of the CSAAT and CSNAAT bits.

 2020 Microchip Technology Inc. DS60001614B-page 547 SAM3X8ERT FIGURE 32-12: PERIPHERAL DESELECTION A NPCS[0..3] Write SPI_TDR TDRE NPCS[0..3] Write SPI_TDR TDRE NPCS[0..3] Write SPI_TDR TDRE DLYBCS PCS = A DLYBCS DLYBCT A PCS = B B DLYBCS PCS = A DLYBCS DLYBCT A PCS = B B DLYBCS DLYBCT PCS=A A DLYBCS DLYBCT A PCS = A AA DLYBCT AA CSAAT = 0 and CSNAAT = 0 DLYBCT AA CSAAT = 1 and CSNAAT= 0 / 1 A DLYBCS PCS = A DLYBCT AA CSAAT = 0 and CSNAAT = 1 NPCS[0..3] Write SPI_TDR TDRE PCS = A DLYBCT AA CSAAT = 0 and CSNAAT = 0

DS60001614B-page 548  2020 Microchip Technology Inc. FIGURE 32-13: PERIPHERAL DESELECTION

32.7.3.13 Mode Fault Detection

A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. In this case, multi-master configuration, NPCS0, MOSI, MISO and SPCK pins must be con- figured in open drain (through the PIO controller). When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR (Control Register) at 1. By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR).

32.7.4 SPI SLAVE MODE

When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the SPI_CSR0. Note: BITS, CPOL, and NCPHA of the other Chip Select Registers have no effect when the SPI is programmed in Slave Mode. The bits are shifted out on the MISO line and sampled on the MOSI line. (For more information on BITS field, see also, the (Note:) below the register table; “SPI Chip Select Register” on page 557.) When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit rises. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in the Transmit Data Register (SPI_TDR), the last data received is transferred. If no data has been received since the last reset, all bits are transmitted low, as the Shift Register resets at 0. A NPCS[0..3] Write SPI_TDR TDRE NPCS[0..3] Write SPI_TDR TDRE NPCS[0..3] Write SPI_TDR TDRE DLYBCS PCS = A DLYBCS DLYBCT A PCS = B B DLYBCS PCS = A DLYBCS DLYBCT A PCS = B B DLYBCS DLYBCT PCS=A A DLYBCS DLYBCT A PCS = A AA DLYBCT AA CSAAT = 0 DLYBCT AA CSAAT = 1 A

 2020 Microchip Technology Inc. DS60001614B-page 549 SAM3X8ERT When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the TDRE bit rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in SPI_TDR is transferred in the Shift Register and the TDRE bit rises. This enables frequent updates of critical variables with single transfers. Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no character is ready to be transmitted, i.e. no character has been written in SPI_TDR since the last load from SPI_TDR to the Shift Register, the Shift Register is not modified and the last received character is retransmitted. In this case the Underrun Error Status Flag (UNDES) is set in the SPI_SR. Figure 32-14 shows a block diagram of the SPI when operating in Slave Mode. FIGURE 32-14: SLAVE MODE FUNCTIONAL BLOC DIAGRAM

32.7.5 WRITE PROTECTED REGISTERS

To prevent any single software error that may corrupt SPI behavior, the registers listed below can be write-protected by setting the WPEN bit in the SPI Write Protection Mode Register (SPI_WPMR). If a write access in a write-protected register is detected, then the WPVS flag in the SPI Write Protection Status Register (SPI_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. The WPVS flag is automatically reset after reading the SPI Write Protection Status Register (SPI_WPSR). List of the write-protected registers:

• “SPI Mode Register” on page 551
• “SPI Chip Select Register” on page 557

32.8 Serial Peripheral Interface (SPI) User Interface

TABLE 32-5: REGISTER MAPPING Offset Register Name Access Reset 0x00 Control Register SPI_CR Write-only — 0x04 Mode Register SPI_MR Read-write 0x0 0x08 Receive Data Register SPI_RDR Read-only 0x0 0x0C Transmit Data Register SPI_TDR Write-only — 0x10 Status Register SPI_SR Read-only 0x000000F0 0x14 Interrupt Enable Register SPI_IER Write-only — 0x18 Interrupt Disable Register SPI_IDR Write-only — 0x1C Interrupt Mask Register SPI_IMR Read-only 0x0 Shift Register SPCK SPIENS LSB MSB NSS MOSI SPI_RDR RD SPI Clock TDRE SPI_TDR TD RDRF OVRES SPI_CSR0 CPOL NCPHA BITS SPIEN SPIDIS MISO

DS60001614B-page 550  2020 Microchip Technology Inc. Note 1: Values in the Version Register vary with the version of the IP block implementation.

32.8.1 SPI CONTROL REGISTER

Name: SPI_CR Address:0x40008000 (0), 0x4000C000 (1) Access: Write-only

• SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data.
• SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI. As soon as SPIDIS is set, SPI finishes its transfer. All pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled.
• SWRST: SPI Software Reset 0 = No effect. 1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed. 0x20 - 0x2C Reserved — — — 0x30 Chip Select Register 0 SPI_CSR0 Read-write 0x0 0x34 Chip Select Register 1 SPI_CSR1 Read-write 0x0 0x38 Chip Select Register 2 SPI_CSR2 Read-write 0x0 0x3C Chip Select Register 3 SPI_CSR3 Read-write 0x0 0x4C - 0xE0 Reserved — — — 0xE4 Write Protection Control Register SPI_WPMR Read-write 0x0 0xE8 Write Protection Status Register SPI_WPSR Read-only 0x0 0x00E8 - 0x00F8 Reserved — — — 0x004C - 0x00F8 Reserved — — — 0x00FC Version Register SPI_VERSION Read-only 0x- (1) 0x00FC Reserved — — — 0x100 - 0x124 Reserved for PDC Registers — — — 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWRST — — — — — SPIDIS SPIEN TABLE 32-5: REGISTER MAPPING Offset Register Name Access Reset

 2020 Microchip Technology Inc. DS60001614B-page 551 SAM3X8ERT The SPI is in slave mode after software reset. PDCDMAC channels are not affected by software reset.

• LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. Refer to “Peripheral Selection” on page 543 for more details.

32.8.2 SPI MODE REGISTER

Name: SPI_MR Address:0x40008004 (0), 0x4000C004 (1) Access: Read-write This register can only be written if the WPEN bit is cleared in “SPI Write Protection Mode Register” on page 558.

• MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode.
• PS: Peripheral Select 0 = Fixed Peripheral Select. 1 = Variable Peripheral Select.
• PCSDEC: Chip Select Decode 0 = The chip selects are directly connected to a peripheral device. 1 = The four chip select lines are connected to a 4- to 16-bit decoder. When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules: SPI_CSR0 defines peripheral chip select signals 0 to 3. SPI_CSR1 defines peripheral chip select signals 4 to 7. SPI_CSR2 defines peripheral chip select signals 8 to 11. SPI_CSR3 defines peripheral chip select signals 12 to 14.
• MODFDIS: Mode Fault Detection 0 = Mode fault detection is enabled. 1 = Mode fault detection is disabled.
• WDRBT: Wait Data Read Before Transfer 0 = No Effect. In master mode, a transfer can be initiated whatever the state of the Receive Data Register is. 31 30 29 28 27 26 25 24 DLYBCS 23 22 21 20 19 18 17 16 — — — — PCS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LLB — WDRBT– MODFDIS — PCSDEC PS MSTR

DS60001614B-page 552  2020 Microchip Technology Inc. 1 = In Master Mode, a transfer can start only if the Receive Data Register is empty, i.e. does not contain any unread data. This mode prevents overrun error in reception.

• LLB: Local Loopback Enable 0 = Local loopback path disabled. 1 = Local loopback path enabled LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on MOSI.)
• PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0NPCS[3:0] = 1110 PCS = xx01NPCS[3:0] = 1101 PCS = x011NPCS[3:0] = 1011 PCS = 0111NPCS[3:0] = 0111 PCS = 1111forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS.
• DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non- overlapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is less than or equal to six, six MCK periods will be inserted by default. Otherwise, the following equation determines the delay:

32.8.3 SPI RECEIVE DATA REGISTER

Name: SPI_RDR Address: 0x40008008 (0), 0x4000C008 (1) Access: Read-only

• RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
• PCS: Peripheral Chip Select 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — PCS 15 14 13 12 11 10 9 8 RD 7 6 5 4 3 2 1 0 RD Delay Between Chip Selects DLYBCS

 2020 Microchip Technology Inc. DS60001614B-page 553 SAM3X8ERT In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero. Note: When using variable peripheral select mode (PS = 1 in SPI_MR) it is mandatory to also set the WDRBT field to 1 if the SPI_RDR PCS field is to be processed. Note: When using variable peripheral select mode (PS = 1 in SPI_MR) it is mandatory to read SPI_RDR prior to writing into SPI_TDR, else the PCS value returned by SPI_RDR may not be accurate.

32.8.4 SPI TRANSMIT DATA REGISTER

Name: SPI_TDR Address: 0x4000800C (0), 0x4000C00C (1) Access: Write-only

• TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
• PCS: Peripheral Chip Select This field is only used if Variable Peripheral Select is active (PS = 1). If PCSDEC = 0: PCS = xxx0NPCS[3:0] = 1110 PCS = xx01NPCS[3:0] = 1101 PCS = x011NPCS[3:0] = 1011 PCS = 0111NPCS[3:0] = 0111 PCS = 1111forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS
• LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. This field is only used if Variable Peripheral Select is active (PS = 1).

32.8.5 SPI STATUS REGISTER

Name: SPI_SR Address:0x40008010 (0), 0x4000C010 (1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — PCS 15 14 13 12 11 10 9 8 TD 7 6 5 4 3 2 1 0 TD

DS60001614B-page 554  2020 Microchip Technology Inc. Access: Read-only

• RDRF: Receive Data Register Full 0 = No data has been received since the last read of SPI_RDR 1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of SPI_RDR.
• TDRE: Transmit Data Register Empty 0 = Data has been written to SPI_TDR and not yet transferred to the serializer. 1 = The last data written in the Transmit Data Register has been transferred to the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
• MODF: Mode Fault Error 0 = No Mode Fault has been detected since the last read of SPI_SR. 1 = A Mode Fault occurred since the last read of the SPI_SR.
• OVRES: Overrun Error Status 0 = No overrun has been detected since the last read of SPI_SR. 1 = An overrun has occurred since the last read of SPI_SR. An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.
• ENDRX: End of RX buffer 0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1). 1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1).
• ENDTX: End of TX buffer 0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1). 1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1).
• RXBUFF: RX Buffer Full 0 = SPI_RCR(1) or SPI_RNCR(1) has a value other than 0. 1 = Both SPI_RCR(1) and SPI_RNCR(1) have a value of 0.
• TXBUFE: TX Buffer Empty 0 = SPI_TCR(1) or SPI_TNCR(1) has a value other than 0. 1 = Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0.
• NSSR: NSS Rising 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occurred on NSS pin since last read.
• TXEMPTY: Transmission Registers Empty 0 = As soon as data is written in SPI_TDR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — — — — — UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 — — — — OVRES MODF TDRE RDRF

 2020 Microchip Technology Inc. DS60001614B-page 555 SAM3X8ERT 1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.

• UNDES: Underrun Error Status (Slave Mode Only) 0 = No underrun has been detected since the last read of SPI_SR. 1 = A transfer begins whereas no data has been loaded in the Transmit Data Register.
• SPIENS: SPI Enable Status 0 = SPI is disabled. 1 = SPI is enabled. Note 1: SPI_RCR, SPI_RNCR, SPI_TCR, SPI_TNCR are physically located in the PDC.

32.8.6 SPI INTERRUPT ENABLE REGISTER

Name: SPI_IER Address:0x40008014 (0), 0x4000C014 (1) Access: Write-only 0 = No effect. 1 = Enables the corresponding interrupt.

• RDRF: Receive Data Register Full Interrupt Enable
• TDRE: SPI Transmit Data Register Empty Interrupt Enable
• MODF: Mode Fault Error Interrupt Enable
• OVRES: Overrun Error Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable
• NSSR: NSS Rising Interrupt Enable
• TXEMPTY: Transmission Registers Empty Enable
• UNDES: Underrun Error Interrupt Enable

32.8.7 SPI INTERRUPT DISABLE REGISTER

Name: SPI_IDR Address:0x40008018 (0), 0x4000C018 (1) Access: Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — — — — — UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 — — — — OVRES MODF TDRE RDRF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DS60001614B-page 556  2020 Microchip Technology Inc. 0 = No effect. 1 = Disables the corresponding interrupt.

• RDRF: Receive Data Register Full Interrupt Disable
• TDRE: SPI Transmit Data Register Empty Interrupt Disable
• MODF: Mode Fault Error Interrupt Disable
• OVRES: Overrun Error Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• ENDTX: End of Transmit Buffer Interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
• TXBUFE: Transmit Buffer Empty Interrupt Disable
• NSSR: NSS Rising Interrupt Disable
• TXEMPTY: Transmission Registers Empty Disable
• UNDES: Underrun Error Interrupt Disable

32.8.8 SPI INTERRUPT MASK REGISTER

Name: SPI_IMR Address:0x4000801C (0), 0x4000C01C (1) Access: Read-only 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.

• RDRF: Receive Data Register Full Interrupt Mask
• TDRE: SPI Transmit Data Register Empty Interrupt Mask
• MODF: Mode Fault Error Interrupt Mask
• OVRES: Overrun Error Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• ENDTX: End of Transmit Buffer Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
• TXBUFE: Transmit Buffer Empty Interrupt Mask
• NSSR: NSS Rising Interrupt Mask
• TXEMPTY: Transmission Registers Empty Mask 15 14 13 12 11 10 9 8 — — — — — UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 — — — — OVRES MODF TDRE RDRF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — — — — — UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 — — — — OVRES MODF TDRE RDRF

 2020 Microchip Technology Inc. DS60001614B-page 557 SAM3X8ERT

• UNDES: Underrun Error Interrupt Mask

32.8.9 SPI CHIP SELECT REGISTER

Name: SPI_CSRx[x=0..3] Address:0x40008030 (0), 0x4000C030 (1) Access: Read/Write This register can only be written if the WPEN bit is cleared in “SPI Write Protection Mode Register” on page 558. Note: SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with the translated value unless the register is written.

• CPOL: Clock Polarity 0 = The inactive state value of SPCK is logic level zero. 1 = The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
• NCPHA: Clock Phase 0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices.
• CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 0 = The Peripheral Chip Select does not rise between two transfers if the SPI_TDR is reloaded before the end of the first transfer and if the two transfers occur on the same Chip Select. 1 = The Peripheral Chip Select rises systematically after each transfer performed on the same slave. It remains active after the end of transfer for a minimal duration of: - (if DLYBCT field is different from 0) - (if DLYBCT field equals 0)
• CSAAT: Chip Select Active After Transfer 0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved. 1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select.
• BITS: Bits Per Transfer (See the (Note:) below the register table; “SPI Chip Select Register” on page 557.) 31 30 29 28 27 26 25 24 DLYBCT 23 22 21 20 19 18 17 16 DLYBS 15 14 13 12 11 10 9 8 SCBR 7 6 5 4 3 2 1 0 BITS CSAAT CSNAAT– NCPHA CPOL DLYBCT DLYBCT 1+

DS60001614B-page 558  2020 Microchip Technology Inc. The BITS field determines the number of data bits transferred. Reserved values should not be used.

• SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. Note: If one of the SCBR fields inSPI_CSRx is set to 1, the other SCBR fields in SPI_CSRx must be set to 1 as well, if they are required to process transfers. If they are not used to transfer data, they can be set at any value.
• DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay:
• DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay:

32.8.10 SPI WRITE PROTECTION MODE REGISTER

Name:SPI_WPMR Address:0x400080E4 (0), 0x4000C0E4 (1) Value Name Description 0 8_BIT 8 bits for transfer 1 9_BIT 9 bits for transfer 2 10_BIT 10 bits for transfer 3 11_BIT 11 bits for transfer 4 12_BIT 12 bits for transfer 5 13_BIT 13 bits for transfer 6 14_BIT 14 bits for transfer 7 15_BIT 15 bits for transfer 8 16_BIT 16 bits for transfer 9 — Reserved 10 — Reserved 11 — Reserved 12 — Reserved 13 — Reserved 14 — Reserved 15 — Reserved SPCK Baudrate MCK Delay Before SPCK DLYBS Delay Between Consecutive Transfers 32 DLYBCT

 2020 Microchip Technology Inc. DS60001614B-page 559 SAM3X8ERT Access:Read-write

• WPEN: Write Protection Enable 0: The Write Protection is Disabled 1: The Write Protection is Enabled
• WPKEY: Write Protection Key Password If a value is written in WPEN, the value is taken into account only if WPKEY is written with “SPI” (SPI written in ASCII Code, ie 0x535049 in hexadecimal). List of the write-protected registers:
• “SPI Mode Register” on page 551
• “SPI Chip Select Register” on page 557

32.8.11 SPI WRITE PROTECTION STATUS REGISTER

Name:SPI_WPSR Address:0x400080E8 (0), 0x4000C0E8 (1) Access:Read-only

• WPVS: Write Protection Violation Status 0 = No Write Protect Violation has occurred since the last read of the SPI_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the SPI_WPSR register. If this violation is an unautho- rized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source This Field indicates the APB Offset of the register concerned by the violation (SPI_MR or SPI_CSRx) 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 WPVSRC 7 6 5 4 3 2 1 0

DS60001614B-page 560  2020 Microchip Technology Inc.

33.0 TWO-WIRE INTERFACE (TWI)

33.1 Description

The Microchip Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Microchip Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few. The TWI is programmable as a master or a slave with sequential or single-byte access. Multiple master capability is supported. 20 Arbitration of the bus is performed internally and puts the TWI in slave mode automatically if the bus arbitration is lost. A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. Below, Table 33-1 lists the compatibility level of the Microchip Two-wire Interface in Master Mode and a full I2C compat- ible device. Note 1: START + b000000001 + Ack + Sr

33.2 Embedded Characteristics

• 2 x TWI
• Compatible with Microchip Two-wire Interface Serial Memory and I²C Compatible Devices(Note:)
• One, Two or Three Bytes for Slave Address
• Sequential Read-write Operations
• Master, Multi-master and Slave Mode Operation
• Bit Rate: Up to 400 Kbits
• General Call Supported in Slave mode
• SMBUS Quick Command Supported in Master Mode
• Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode Only - One Channel for the Receiver, One Channel for the Transmitter - Next Buffer Support
• Connection to DMA Controller (DMAC) Channel Capabilities Optimizes Data Transfers in Master Mode Only Note: See Table 33-1 for details on compatibility with I²C Standard.

33.3 List of Abbreviations

TABLE 33-1: MICROCHIP TWI COMPATIBILITY WITH I2C STANDARD I2C Standard Microchip TWI Standard Mode Speed (100 KHz) Supported Fast Mode Speed (400 KHz) Supported 7 or 10 bits Slave Addressing Supported START BYTE(1) Not Supported Repeated Start (Sr) Condition Supported ACK and NACK Management Supported Slope control and input filtering (Fast mode) Not Supported Clock stretching Supported Multi Master Capability Supported TABLE 33-2: ABBREVIATIONS Abbreviation Description TWI Two-wire Interface A Acknowledge NA Non Acknowledge

 2020 Microchip Technology Inc. DS60001614B-page 561 SAM3X8ERT

33.4 Block Diagram

FIGURE 33-1: BLOCK DIAGRAM FIGURE 33-2: BLOCK DIAGRAM P Stop S Start Sr Repeated Start SADR Slave Address ADR Any address except SADR R Read W Write TABLE 33-2: ABBREVIATIONS Abbreviation Description APB Bridge PMC MCK Two-wire Interface PIO AIC TWI Interrupt TWCK TWD APB Bridge PMC MCK Two-wire Interface PIO NVIC TWI Interrupt TWCK TWD

DS60001614B-page 562  2020 Microchip Technology Inc.

33.5 Application Block Diagram

FIGURE 33-3: APPLICATION BLOCK DIAGRAM

33.5.1 I/O LINES DESCRIPTION

33.6 Product Dependencies

33.6.1 I/O LINES

Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resis- tor (see Figure 33-3). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer must perform the following step:

• Program the PIO controller to dedicate TWD and TWCK as peripheral lines. The user must not program TWD and TWCK as open-drain. It is already done by the hardware.

33.6.2 POWER MANAGEMENT

• Enable the peripheral clock. The TWI interface may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the TWI clock. TABLE 33-3: I/O LINES DESCRIPTION Pin Name Pin Description Type TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output TABLE 33-4: I/O LINES Instance Signal I/O Line Peripheral TWI0 TWCK0 PA18 A TWI0 TWD0 PA17 A TWI1 TWCK1 PB13 A TWI1 TWD1 PB12 A Host with TWI Interface TWD TWCK Atmel TWI Serial EEPROM I²C RTC I²C LCD Controller Slave 1 Slave 2 Slave 3 VDD I²C Temp. Sensor Slave 4 Rp: Pull up value as given by the I²C Standard Rp Rp

 2020 Microchip Technology Inc. DS60001614B-page 563 SAM3X8ERT

33.6.3 INTERRUPT

The TWI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC) Nested Vector Interrupt Controller (NVIC). In order to handle interrupts, the AICNVIC must be programmed before configuring the TWI.

33.7 Functional Description

33.7.1 TRANSFER FORMAT

The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 33-5). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 33-4).

• A high-to-low transition on the TWD line while TWCK is high defines the START condition.
• A low-to-high transition on the TWD line while TWCK is high defines a STOP condition. FIGURE 33-4: START AND STOP CONDITIONS FIGURE 33-5: TRANSFER FORMAT

33.7.2 MODES OF OPERATION

The TWI has six modes of operations:

• Master transmitter mode
• Master receiver mode
• Multi-master transmitter mode
• Multi-master receiver mode
• Slave transmitter mode
• Slave receiver mode These modes are described in the following chapters. TABLE 33-5: PERIPHERAL IDS Instance ID TWI0 22 TWI1 23 TWD TWCK Start Stop TWD TWCK Start Address R/W Ack Data Ack Data Ack Stop

DS60001614B-page 564  2020 Microchip Technology Inc.

33.8 Master Mode

33.8.1 DEFINITION

The Master is the device that starts a transfer, generates a clock and stops it.

33.8.2 APPLICATION BLOCK DIAGRAM

FIGURE 33-6: MASTER MODE TYPICAL APPLICATION BLOCK DIAGRAM

33.8.3 PROGRAMMING MASTER MODE

The following registers have to be programmed before entering Master mode: 1. DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used to access slave devices in read or write mode. 2. CKDIV + CHDIV + CLDIV: Clock Waveform. 3. SVDIS: Disable the slave mode. 4. MSEN: Enable the master mode.

33.8.4 MASTER TRANSMITTER MODE

After the master initiates a Start condition when writing into the Transmit Holding Register, TWI_THR, it sends a 7-bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer direction, 0 in this case (MREAD = 0 in TWI_MMR). The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the Not Acknowledge bit (NACK) in the status register if the slave does not acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (TWI_IER). If the slave acknowledges the byte, the data written in the TWI_THR, is then shifted in the internal shifter and transferred. When an acknowledge is detected, the TXRDY bit is set until a new write in the TWI_THR. TXRDY is used as Transmit Ready for the PDC transmit channel. While no new data is written in the TWI_THR, the Serial Clock Line is tied low. When new data is written in the TWI_THR, the SCL is released and the data is sent. To generate a STOP event, the STOP command must be performed by writing in the STOP field of TWI_CR. After a Master Write transfer, the Serial Clock line is stretched (tied low) while no new data is written in the TWI_THR or until a STOP command is performed. See Figure 33-7, Figure 33-8, and Figure 33-9. Host with TWI Interface TWD TWCK Atmel TWI Serial EEPROM I²C RTC I²C LCD Controller Slave 1 Slave 2 Slave 3 VDD I²C Temp. Sensor Slave 4 Rp: Pull up value as given by the I²C Standard Rp Rp

DS60001614B-page 566  2020 Microchip Technology Inc. FIGURE 33-10: MASTER WRITE WITH ONE DATA BYTE FIGURE 33-11: MASTER WRITE WITH MULTIPLE DATA BYTE FIGURE 33-12: MASTER WRITE WITH ONE BYTE INTERNAL ADDRESS AND MULTIPLE DATA BYTES

33.8.5 MASTER RECEIVER MODE

The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte. If an acknowledge is received, the master is then ready to receive data from the slave. After data has been received, the master sends an acknowledge condition to notify the slave that the data has been received except for the last data, after the stop condition. See Figure 33-13. When the RXRDY bit is set in the status register, a character has been received in the receive-holding register (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR. When a single data byte read is performed, with or without internal address (IADR), the START and STOP bits must be set at the same time. See Figure 33-13. When a multiple data byte read is performed, with or without internal address (IADR), the STOP bit must be set after the next-to-last data received. See Figure 33-14. For Internal Address usage see “Internal Address” on page 568. TXCOMP TXRDY Write THR (DATA) STOP sent automaticaly (ACK received and TXRDY = 1) TWD A DATA AS DADR W P A DATA n AS DADR W DATA n+5 A P DATA n+x A TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+x) Last data sent STOP sent automaticaly (ACK received and TXRDY = 1) TWD A IADR(7:0) A DATA n AS DADR W DATA n+5 A P DATA n+x A TXCOMP TXRDY TWD Write THR (Data n) Write THR (Data n+1) Write THR (Data n+x) Last data sent STOP sent automaticaly (ACK received and TXRDY = 1)

DS60001614B-page 568  2020 Microchip Technology Inc. FIGURE 33-15: MASTER READ CLOCK STRETCHING WITH MULTIPLE DATA BYTES RXRDY is used as Receive Ready for the PDC receive channel.

33.8.6 INTERNAL ADDRESS

The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave address devices. 33.8.6.1 7-bit Slave Addressing When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example. When per- forming read operations with an internal address, the TWI performs a write operation to set the internal address into the slave device, and then switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See Figure 33-17, Figure 33-16, and Figure 33-18 for Master Write operation with internal address. The three internal address bytes are configurable through the Master Mode register (TWI_MMR). If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to 0. In the figures below the following abbreviations are used:

• S Start
• Sr Repeated Start
• P Stop
• W Write
• R Read
• A Acknowledge
• N Not Acknowledge
• DADR Device Address
• IADR Internal Address A DATA n AS DADR W DATA n+1 A P DATA n+2 A TXCOMP RXRDY Read RHR (Data n) STOP command performed (by writing in the TWI_CR) TWD TWCK Read RHR (Data n+1) Read RHR (Data n+2) Clock Streching

DS60001614B-page 570  2020 Microchip Technology Inc.

33.8.7 USING THE PERIPHERAL DMA CONTROLLER (PDC)

The use of the PDC significantly reduces the CPU load. To assure correct implementation, respect the following programming sequences:

33.8.7.1 Data Transmit with the PDC

1. Initialize the transmit PDC (memory pointers, size, etc.). 2. Configure the master mode (DADR, CKDIV, etc.). 3. Start the transfer by setting the PDC TXTEN bit. 4. Wait for the PDC end TX flag. 5. Disable the PDC by setting the PDC TXDIS bit.

33.8.7.2 Data Receive with the PDC

1. Initialize the receive PDC (memory pointers, size - 1, etc.). 2. Configure the master mode (DADR, CKDIV, etc.). 3. Start the transfer by setting the PDC RXTEN bit. 4. Wait for the PDC end RX flag. 5. Disable the PDC by setting the PDC RXDIS bit.

33.8.8 USING THE DMA CONTROLLER (DMAC)

The use of the DMAC significantlly reduces the CPU load. To assure correct implementation, respect the following programming sequence. 1. Initialize the DMAC (channels, memory pointers , size, etc.); 2. Configure the master mode (DADR, CKDIV, etc.). 3. Enable the DMAC. 4. Wait for the DMAC flag. 5. Disable the DMAC.

33.8.9 SMBUS QUICK COMMAND (MASTER MODE ONLY)

The TWI interface can perform a Quick Command: 1. Configure the master mode (DADR, CKDIV, etc.). 2. Write the MREAD bit in the TWI_MMR register at the value of the one-bit command to be sent. 3. Start the transfer by setting the QUICK bit in the TWI_CR. FIGURE 33-19: SMBUS QUICK COMMAND TXCOMP TXRDY Write QUICK command in TWI_CR TWD AS DADR R/W P

 2020 Microchip Technology Inc. DS60001614B-page 571 SAM3X8ERT

33.8.10 READ-WRITE FLOWCHARTS

The following flowcharts shown in Figure 33-21, Figure 33-22, Figure 33-24, Figure 33-25, Figure 33-26, Figure 33-27, and Figure 33-28 give examples for read and write operations. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. FIGURE 33-20: TWI WRITE OPERATION WITH SINGLE DATA BYTE WITHOUT INTERNAL ADDRESS Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Transfer direction bit Write ==> bit MREAD = 0 Load Transmit register TWI_THR = Data to send Read Status register TXRDY = 1? Read Status register TXCOMP = 1? Transfer finished Ye s Ye s BEGIN No No Write STOP Command TWI_CR = STOP

DS60001614B-page 572  2020 Microchip Technology Inc. FIGURE 33-21: TWI WRITE OPERATION WITH SINGLE DATA BYTE AND INTERNAL ADDRESS BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Internal address size (IADRSZ) - Transfer direction bit Write ==> bit MREAD = 0 Load transmit register TWI_THR = Data to send Read Status register TXRDY = 1? Read Status register TXCOMP = 1? Transfer finished Set the internal address TWI_IADR = address Yes Yes No No Write STOP command TWI_CR = STOP

 2020 Microchip Technology Inc. DS60001614B-page 573 SAM3X8ERT FIGURE 33-22: TWI WRITE OPERATION WITH MULTIPLE DATA BYTES WITH OR WITHOUT INTERNAL ADDRESS Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Write ==> bit MREAD = 0 Internal address size = 0? Load Transmit register TWI_THR = Data to send Read Status register TXRDY = 1? Data to send? Read Status register TXCOMP = 1? END BEGIN Set the internal address TWI_IADR = address Ye s TWI_THR = data to send Ye s Ye s Ye s No No No Write STOP Command TWI_CR = STOP Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once)

DS60001614B-page 574  2020 Microchip Technology Inc. FIGURE 33-23: TWI WRITE OPERATION WITH SINGLE DATA BYTE WITHOUT INTERNAL ADDRESS Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Transfer direction bit Write ==> bit MREAD = 0 Load Transmit register TWI_THR = Data to send Read Status register TXRDY = 1? Read Status register TXCOMP = 1? Transfer finished Ye s Ye s BEGIN No No

 2020 Microchip Technology Inc. DS60001614B-page 575 SAM3X8ERT FIGURE 33-24: TWI WRITE OPERATION WITH SINGLE DATA BYTE AND INTERNAL ADDRESS BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Internal address size (IADRSZ) - Transfer direction bit Write ==> bit MREAD = 0 Load transmit register TWI_THR = Data to send Read Status register TXRDY = 1? Read Status register TXCOMP = 1? Transfer finished Set the internal address TWI_IADR = address Ye s Ye s No No

DS60001614B-page 576  2020 Microchip Technology Inc. FIGURE 33-25: TWI WRITE OPERATION WITH MULTIPLE DATA BYTES WITH OR WITHOUT INTERNAL ADDRESS Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Write ==> bit MREAD = 0 Internal address size = 0? Load Transmit register TWI_THR = Data to send Read Status register TXRDY = 1? Data to send? Read Status register TXCOMP = 1? END BEGIN Set the internal address TWI_IADR = addressYe s TWI_THR = data to send Ye s Ye s Ye s No No No Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once)

 2020 Microchip Technology Inc. DS60001614B-page 577 SAM3X8ERT FIGURE 33-26: TWI READ OPERATION WITH SINGLE DATA BYTE WITHOUT INTERNAL ADDRESS Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Transfer direction bit Read ==> bit MREAD = 1 Start the transfer TWI_CR = START | STOP Read status register RXRDY = 1? Read Status register TXCOMP = 1? END BEGIN Ye s Ye s Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Read Receive Holding Register No No

DS60001614B-page 578  2020 Microchip Technology Inc. FIGURE 33-27: TWI READ OPERATION WITH SINGLE DATA BYTE AND INTERNAL ADDRESS Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (IADRSZ) - Transfer direction bit Read ==> bit MREAD = 1 Read Status register TXCOMP = 1? END BEGIN Ye s Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Ye s Set the internal address TWI_IADR = address Start the transfer TWI_CR = START | STOP Read Status register RXRDY = 1? Read Receive Holding register No No

 2020 Microchip Technology Inc. DS60001614B-page 579 SAM3X8ERT FIGURE 33-28: TWI READ OPERATION WITH MULTIPLE DATA BYTES WITH OR WITHOUT INTERNAL ADDRESS Internal address size = 0? Start the transfer TWI_CR = START Stop the transfer TWI_CR = STOP Read Status register RXRDY = 1? Last data to read but one? Read status register TXCOMP = 1? END Set the internal address TWI_IADR = address Ye s Ye s Ye s No Ye s Read Receive Holding register (TWI_RHR) No Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Read ==> bit MREAD = 1 BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) No Read Status register RXRDY = 1? Ye s Read Receive Holding register (TWI_RHR) No

DS60001614B-page 580  2020 Microchip Technology Inc.

33.9 Multi-master Mode

33.9.1 DEFINITION

More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop. When the stop is detected, the master who has lost arbitration may put its data on the bus by respecting arbitration. Arbitration is illustrated in Figure 33-30.

33.9.2 DIFFERENT MULTI-MASTER MODES

Two multi-master modes may be distinguished: 1. TWI is considered as a Master only and will never be addressed. 2. TWI may be either a Master or a Slave and may be addressed. Note: In both Multi-master modes arbitration is supported.

33.9.2.1 TWI as Master Only

In this mode, TWI is considered as a Master only (MSEN is always at one) and must be driven like a Master with the ARBLST (ARBitration Lost) flag in addition. If arbitration is lost (ARBLST = 1), the programmer must reinitiate the data transfer. If the user starts a transfer (ex.: DADR + START + W + Write in THR) and if the bus is busy, the TWI automatically waits for a STOP condition on the bus to initiate the transfer (see Figure 33-29). Note: The state of the bus (busy or free) is not indicated in the user interface.

33.9.2.2 TWI as Master or Slave

The automatic reversal from Master to Slave is not supported in case of a lost arbitration. Then, in the case where TWI may be either a Master or a Slave, the programmer must manage the pseudo Multi-master mode described in the steps below. 1. Program TWI in Slave mode (SADR + MSDIS + SVEN) and perform Slave Access (if TWI is addressed). 2. If TWI has to be set in Master mode, wait until TXCOMP flag is at 1. 3. Program Master mode (DADR + SVDIS + MSEN) and start the transfer (ex: START + Write in THR). 4. As soon as the Master mode is enabled, TWI scans the bus in order to detect if it is busy or free. When the bus is considered as free, TWI initiates the transfer. 5. As soon as the transfer is initiated and until a STOP condition is sent, the arbitration becomes relevant and the user must monitor the ARBLST flag. 6. If the arbitration is lost (ARBLST is set to 1), the user must program the TWI in Slave mode in the case where the Master that won the arbitration wanted to access the TWI. 7. If TWI has to be set in Slave mode, wait until TXCOMP flag is at 1 and then program the Slave mode. Note: In the case where the arbitration is lost and TWI is addressed, TWI will not acknowledge even if it is pro - grammed in Slave mode as soon as ARBLST is set to 1. Then, the Master must repeat SADR.

DS60001614B-page 582  2020 Microchip Technology Inc. FIGURE 33-31: MULTI-MASTER FLOWCHART Programm the SLAVE mode: SADR + MSDIS + SVEN SVACC = 1 ? TXCOMP = 1 ? GACC = 1 ? Decoding of the programming sequence Prog seq OK ? Change SADR SVREAD = 1 ? Read Status Register RXRDY= 1 ? Read TWI_RHR TXRDY= 1 ?EOSACC = 1 ? Write in TWI_THR Need to perform a master access ? Program the Master mode DADR + SVDIS + MSEN + CLK + R / W Read Status Register ARBLST = 1 ? MREAD = 1 ? TXRDY= 0 ? Write in TWI_THRData to send ? RXRDY= 0 ? Read TWI_RHR Data to read? Read Status Register TXCOMP = 0 ? GENERAL CALL TREATMENT Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Stop Transfer TWI_CR = STOP No No No No No No No No No No No No No No No No START

 2020 Microchip Technology Inc. DS60001614B-page 583 SAM3X8ERT FIGURE 33-32: MULTI-MASTER FLOWCHART Programm the SLAVE mode: SADR + MSDIS + SVEN SVACC = 1 ? TXCOMP = 1 ? GACC = 1 ? Decoding of the programming sequence Prog seq OK ? Change SADR SVREAD = 1 ? Read Status Register RXRDY= 1 ? Read TWI_RHR TXRDY= 1 ?EOSACC = 1 ? Write in TWI_THR Need to perform a master access ? Program the Master mode DADR + SVDIS + MSEN + CLK + R / W Read Status Register ARBLST = 1 ? MREAD = 1 ? TXRDY= 0 ? Write in TWI_THRData to send ? RXRDY= 0 ? Read TWI_RHR Data to read? Stop transfer Read Status Register TXCOMP = 0 ? GENERAL CALL TREATMENT Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s No No No No No No No No No No No No No No No No START

DS60001614B-page 584  2020 Microchip Technology Inc.

33.10 Slave Mode

33.10.1 DEFINITION

The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master).

33.10.2 APPLICATION BLOCK DIAGRAM

FIGURE 33-33: SLAVE MODE TYPICAL APPLICATION BLOCK DIAGRAM

33.10.3 PROGRAMMING SLAVE MODE

The following fields must be programmed before entering Slave mode: 1. SADR (TWI_SMR): The slave device address is used in order to be accessed by master devices in read or write mode. 2. MSDIS (TWI_CR): Disable the master mode. 3. SVEN (TWI_CR): Enable the slave mode. As the device receives the clock, values written in TWI_CWGR are not taken into account.

33.10.4 RECEIVING DATA

After a Start or Repeated Start condition is detected and if the address sent by the Master matches with the Slave address programmed in the SADR (Slave ADdress) field, SVACC (Slave ACCess) flag is set and SVREAD (Slave READ) indicates the direction of the transfer. SVACC remains high until a STOP condition or a repeated START is detected. When such a condition is detected, EOSACC (End Of Slave ACCess) flag is set.

33.10.4.1 Read Sequence

In the case of a Read sequence (SVREAD is high), TWI transfers data written in the TWI_THR (TWI Transmit Holding Register) until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note: At the end of the read sequence, the TXCOMP (Transmission Complete) flag is set and SVACC reset. As soon as data is written in the TWI_THR, TXRDY (Transmit Holding Register Ready) flag is reset, and it is set when the shift register is empty and the sent data acknowledged or not. If the data is not acknowledged, the NACK flag is set. Note: A STOP or a repeated START always follows a NACK. See Figure 33-34.

33.10.4.2 Write Sequence

In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. Host with TWI Interface TWD TWCK LCD Controller Slave 1 Slave 2 Slave 3 RR VDD Host with TWI Interface Host with TWI Interface Master

 2020 Microchip Technology Inc. DS60001614B-page 585 SAM3X8ERT TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note: At the end of the write sequence, the TXCOMP flag is set and SVACC reset. See Figure 33-35.

33.10.4.3 Clock Synchronization Sequence

In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock synchronization. Clock stretching information is given by the SCLWS (Clock Wait state) bit. See Figure 33-37 and Figure 33-38.

33.10.4.4 General Call

In the case where a GENERAL CALL is performed, GACC (General Call Access) flag is set. After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL and to decode the new address programming sequence. See Figure 33-36.

33.10.4.5 PDC

As it is impossible to know the exact number of data to receive/send, the use of PDC is NOT recommended in SLAVE mode.

33.10.4.6 DMAC

As it is impossible to know the exact number of data to receive/send, the use of DMAC is NOT recommended in SLAVE mode.

33.10.5 DATA TRANSFER

33.10.5.1 Read Operation

The read mode is defined as a data requirement from the master. After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer. Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR register. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 33-34 describes the write operation. FIGURE 33-34: READ ACCESS ORDERED BY A MASTER Note 1: When SVACC is low, the state of SVREAD becomes irrelevant. 2: TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been acknowledged or non acknowledged. Write THR Read RHR SVREAD has to be taken into account only while SVACC is active TWD TXRDY NACK SVACC SVREAD EOSVACC SADRS ADR R NA R A DATA A A DATA NA S/SrDATA NA P/S/Sr SADR matches, TWI answers with an ACK SADR does not match, TWI answers with a NACK ACK/NACK from the Master

DS60001614B-page 586  2020 Microchip Technology Inc.

33.10.5.2 Write Operation

The write mode is defined as a data transmission from the master. After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case). Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR register. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 33-35 describes the Write operation. FIGURE 33-35: WRITE ACCESS ORDERED BY A MASTER Note 1: When SVACC is low, the state of SVREAD becomes irrelevant. 2: RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is read.

33.10.5.3 General Call

The general call is performed in order to change the address of the slave. If a GENERAL CALL is detected, GACC is set. After the detection of General Call, it is up to the programmer to decode the commands which come afterwards. In case of a WRITE command, the programmer has to decode the programming sequence and program a new SADR if the programming sequence matches. Figure 33-36 describes the General Call access. FIGURE 33-36: MASTER PERFORMS A GENERAL CALL Note: This method allows the user to create an own programming sequence by choosing the programming bytes and the number of them. The programming sequence has to be provided to the master.

33.10.5.4 Clock Synchronization

In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emis - sion/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. RXRDY Read RHR SVREAD has to be taken into account only while SVACC is active TWD SVACC SVREAD EOSVACC SADR does not match, TWI answers with a NACK SADRS ADR W NA W A DATA A A DATA NA S/SrDATA NA P/S/Sr SADR matches, TWI answers with an ACK 0000000 + W GENERAL CALL PS AGENERAL CALL Reset or write DADD A New SADRDATA1 A DATA2 AA New SADR Programming sequence TXD GCACC SVACC RESET command = 00000110X WRITE command = 00000100X Reset after read

 2020 Microchip Technology Inc. DS60001614B-page 587 SAM3X8ERT

33.10.5.4.1 Clock Synchronization in Read Mode

The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded. Figure 33-37 describes the clock synchronization in Read mode. FIGURE 33-37: CLOCK SYNCHRONIZATION IN READ MODE Note 1: TXRDY is reset when data has been written in the TWI_THR to the shift register and set when this data has been acknowledged or non acknowledged. 2: At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 3: SCLWS is automatically set when the clock synchronization mechanism is started.

33.10.5.4.2 Clock Synchronization in Write Mode

The clock is tied low if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read. Figure 33-38 describes the clock synchronization in Read mode. FIGURE 33-38: CLOCK SYNCHRONIZATION IN WRITE MODE Note 1: At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address DATA1 The clock is stretched after the ACK, the state of TWD is undefined during clock stretching SCLWS SVACC SVREAD TXRDY TWCK TWI_THR TXCOMP The data is memorized in TWI_THR until a new value is written TWI_THR is transmitted to the shift register Ack or Nack from the master DATA0 DATA0 DATA2 CLOCK is tied low by the TWI as long as THR is empty S SADRS R DATA0A A DATA1 A DATA2 NA SXXXXXXX Write THR As soon as a START is detected Rd DATA0 Rd DATA1 Rd DATA2 SVACC SVREAD RXRDY SCLWS TXCOMP DATA1 DATA2 SCL is stretched on the last bit of DATA1 As soon as a START is detected TWCK TWD TWI_RHR CLOCK is tied low by the TWI as long as RHR is full DATA0 is not read in the RHR ADRS SADR W A DATA0A A DATA2 DATA1 S NA

DS60001614B-page 588  2020 Microchip Technology Inc. different from SADR. 2: SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mechanism is finished.

33.10.5.5 Reversal after a Repeated Start

33.10.5.5.1 Reversal of Read to Write

The master initiates the communication by a read command and finishes it by a write command. Figure 33-39 describes the repeated start + reversal from Read to Write mode. FIGURE 33-39: REPEATED START + REVERSAL FROM READ TO WRITE MODE 1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.

33.10.5.5.2 Reversal of Write to Read

The master initiates the communication by a write command and finishes it by a read command. Figure 33-40 describes the repeated start + reversal from Write to Read mode. FIGURE 33-40: REPEATED START + REVERSAL FROM WRITE TO READ MODE Note 1: In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stretched before the ACK. 2: TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.

33.10.6 READ WRITE FLOWCHARTS

The flowchart shown in Figure 33-41 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. S SADR R ADATA0A DATA1 SADRSrNA W A DATA2 A DATA3 A P Cleared after read DATA0 DATA1 DATA2 DATA3 SVACC SVREAD TWD TWI_THR TWI_RHR EOSACC TXRDY RXRDY TXCOMP As soon as a START is detected S SADR W ADATA0A DATA1 SADRSrA R A DATA2 A DATA3 NA P Cleared after read DATA0 DATA2 DATA3 DATA1 TXCOMP TXRDY RXRDY As soon as a START is detected Read TWI_RHR SVACC SVREAD TWD TWI_RHR TWI_THR EOSACC

 2020 Microchip Technology Inc. DS60001614B-page 589 SAM3X8ERT FIGURE 33-41: READ WRITE FLOWCHART IN SLAVE MODE

33.11 Write Protection System

In order to bring security to the TWI, a write protection system has been implemented. The write protection mode prevents the write of “TWI Clock Waveform Generator Register” on page 593 and “TWI Slave Mode Register” on page 592. When this mode is enabled and one of the protected registers is written , an error is gen- erated in the “TWI Write Protection Status Register” on page 599 and the register write request is canceled. When a write protection error occurs the WPROTERR flag is set and the address of the corresponding canceled register write is available in the WPROTADRR field of the TWI_WPROT_STATUS register. Due to the nature of the write protection feature, enabling and disabling the write protection mode requires the use of a security code. Thus when enabling or disabling the write protection mode the SECURITY_CODE field of the “TWI Write Protection Mode Register” on page 599 must be filled with the “TWI” ASCII code (0x545749) otherwise the register write will be canceled. Set the SLAVE mode: SADR + MSDIS + SVEN SVACC = 1 ? TXCOMP = 1 ? GACC = 1 ? Decoding of the programming sequence Prog seq OK ? Change SADR SVREAD = 0 ? Read Status Register RXRDY= 0 ? Read TWI_RHR TXRDY= 1 ?EOSACC = 1 ? Write in TWI_THR END GENERAL CALL TREATMENT No No No No No No No No

DS60001614B-page 590  2020 Microchip Technology Inc.

33.12 Two-wire Interface (TWI) User Interface

Note 1: All unlisted offset values are considered as “reserved”. 2: Values in the Version Register vary with the version of the IP block implementation.

33.12.1 TWI CONTROL REGISTER

Name: TWI_CR Address:0x4008C000 (0), 0x40090000 (1) Access: Write-only Reset: 0x00000000

• START: Send a START Condition 0 = No effect. TABLE 33-6: REGISTER MAPPING Offset Register Name Access Reset 0x00 Control Register TWI_CR Write-only N / A 0x04 Master Mode Register TWI_MMR Read-write 0x00000000 0x08 Slave Mode Register TWI_SMR Read-write 0x00000000 0x0C Internal Address Register TWI_IADR Read-write 0x00000000 0x10 Clock Waveform Generator Register TWI_CWGR Read-write 0x00000000 0x14 - 0x1C Reserved — — — 0x20 Status Register TWI_SR Read-only 0x0000F009 0x24 Interrupt Enable Register TWI_IER Write-only N / A 0x28 Interrupt Disable Register TWI_IDR Write-only N / A 0x2C Interrupt Mask Register TWI_IMR Read-only 0x00000000 0x30 Receive Holding Register TWI_RHR Read-only 0x00000000 0x34 Transmit Holding Register TWI_THR Write-only 0x00000000 0xE4 Protection Mode Register TWI_WPROT_- MODE Read-write 0x00000000 0xE8 Protection Status Register TWI_WPROT_STA- TUS Read-only 0x00000000 0xEC - 0xF8(1) Reserved — — — 0xFC Version Register(2) TWI_VER Read-only 0x00000000(1) 0xEC - 0xFC(1) Reserved — — — 0x100 - 0x124 Reserved for the PDC — — — 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWRST QUICK SVDIS SVEN MSDIS MSEN STOP START

 2020 Microchip Technology Inc. DS60001614B-page 591 SAM3X8ERT 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register. This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWI_THR).

• STOP: Send a STOP Condition 0 = No effect. 1 = STOP Condition is sent just after completing the current byte transmission in master read mode. - In single data byte master read, the START and STOP must both be set. - In multiple data bytes master read, the STOP must be set after the last data received but one. - In master read mode, if a NACK bit is received, the STOP is automatically performed. - In multiple data write operation, when both THR and shift register are empty, a STOP condition is automati- cally sent. - In master data write operation, a STOP condition will be sent after the transmission of the current data is fin- ished.
• MSEN: TWI Master Mode Enabled 0 = No effect. 1 = If MSDIS = 0, the master mode is enabled. Note: Switching from Slave to Master mode is only permitted when TXCOMP = 1.
• MSDIS: TWI Master Mode Disabled 0 = No effect. 1 = The master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling.
• SVEN: TWI Slave Mode Enabled 0 = No effect. 1 = If SVDIS = 0, the slave mode is enabled. Note: Switching from Master to Slave mode is only permitted when TXCOMP = 1.
• SVDIS: TWI Slave Mode Disabled 0 = No effect. 1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling.
• QUICK: SMBUS Quick Command 0 = No effect. 1 = If Master mode is enabled, a SMBUS Quick Command is sent.
• SWRST: Software Reset 0 = No effect. 1 = Equivalent to a system reset.

DS60001614B-page 592  2020 Microchip Technology Inc.

33.12.2 TWI MASTER MODE REGISTER

Name: TWI_MMR Address:0x4008C004 (0), 0x40090004 (1) Access: Read-write Reset: 0x00000000

• IADRSZ: Internal Device Address Size
• MREAD: Master Read Direction 0 = Master write direction. 1 = Master read direction.
• DADR: Device Address The device address is used to access slave devices in read or write mode. Those bits are only used in Master mode.

33.12.3 TWI SLAVE MODE REGISTER

Name: TWI_SMR Address:0x4008C008 (0), 0x40090008 (1) Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — DADR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value Name Description

0 NONE No internal device address

1 1_BYTE One-byte internal device address 2 2_BYTE Two-byte internal device address 3 3_BYTE Three-byte internal device address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — SADR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

 2020 Microchip Technology Inc. DS60001614B-page 593 SAM3X8ERT This register can only be written if the WPEN bit is cleared in the “TWI Write Protection Mode Register” on page 599.

• SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode. SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect.

33.12.4 TWI INTERNAL ADDRESS REGISTER

Name: TWI_IADR Address:0x4008C00C (0), 0x4009000C (1) Access: Read-write Reset: 0x00000000

• IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ.

33.12.5 TWI CLOCK WAVEFORM GENERATOR REGISTER

Name: TWI_CWGR Address:0x4008C010 (0), 0x40090010 (1) Access: Read-write Reset: 0x00000000 This register can only be written if the WPEN bit is cleared in the “TWI Write Protection Mode Register” on page 599. TWI_CWGR is only used in Master mode.

• CLDIV: Clock Low Divider The SCL low period is defined as follows: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IADR 15 14 13 12 11 10 9 8 IADR 7 6 5 4 3 2 1 0 IADR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CKDIV 15 14 13 12 11 10 9 8 CHDIV 7 6 5 4 3 2 1 0 CLDIV Tlow CLDIV 2CKDIV  4 + TMCK=

DS60001614B-page 594  2020 Microchip Technology Inc.

• CHDIV: Clock High Divider The SCL high period is defined as follows:
• CKDIV: Clock Divider The CKDIV is used to increase both SCL high and low periods.

33.12.6 TWI STATUS REGISTER

Name: TWI_SR Address:0x4008C020 (0), 0x40090020 (1) Access: Read-only Reset: 0x0000F009

• TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0 = During the length of the current frame. 1 = When both holding and shifter registers are empty and STOP condition has been sent. TXCOMP behavior in Master mode can be seen in Figure 33-9 and in Figure 33-14. TXCOMP used in Slave mode: 0 = As soon as a Start is detected. 1 = After a Stop or a Repeated Start + an address different from SADR is detected. TXCOMP behavior in Slave mode can be seen in Figure 33-37, Figure 33-38, Figure 33-39, and Figure 33-40.
• RXRDY: Receive Holding Register Ready (automatically set / reset) 0 = No character has been received since the last TWI_RHR read operation. 1 = A byte has been received in the TWI_RHR since the last read. RXRDY behavior in Master mode can be seen in Figure 33-14. RXRDY behavior in Slave mode can be seen in Figure 33-35, Figure 33-38, Figure 33-39, and Figure 33-40.
• TXRDY: Transmit Holding Register Ready (automatically set / reset) TXRDY used in Master mode: 0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register. 1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI). TXRDY behavior in Master mode can be seen in Figure 33-9. TXRDY used in Slave mode: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TXBUFE RXBUFF ENDTX ENDRX EOSACC SCLWS ARBLST NACK 7 6 5 4 3 2 1 0 — OVRE GACC SVACC SVREAD TXRDY RXRDY TXCOMP Thigh CHDIV 2CKDIV  4 + TMCK=

 2020 Microchip Technology Inc. DS60001614B-page 595 SAM3X8ERT 0 = As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK). 1 = It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it. TXRDY behavior in Slave mode can be seen in Figure 33-34, Figure 33-37, Figure 33-39, and Figure 33-40.

• SVREAD: Slave Read (automatically set / reset) This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant. 0 = Indicates that a write access is performed by a Master. 1 = Indicates that a read access is performed by a Master. SVREAD behavior can be seen in Figure 33-34, Figure 33-35, Figure 33-39, and Figure 33-40.
• SVACC: Slave Access (automatically set / reset) This bit is only used in Slave mode. 0 = TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected. 1 = Indicates that the address decoding sequence has matched (A Master has sent SADR). SVACC remains high until a NACK or a STOP condition is detected. SVACC behavior can be seen in Figure 33-34, Figure 33-35, Figure 33-39 and Figure 33-34.
• GACC: General Call Access (clear on read) This bit is only used in Slave mode. 0 = No General Call has been detected. 1 = A General Call has been detected. After the detection of General Call, if need be, the programmer may acknowledge this access and decode the following bytes and respond according to the value of the bytes. GACC behavior can be seen in Figure 33-36.
• OVRE: Overrun Error (clear on read) This bit is only used in Master mode. 0 = TWI_RHR has not been loaded while RXRDY was set 1 = TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.
• NACK: Not Acknowledged (clear on read) NACK used in Master mode: 0 = Each data byte has been correctly received by the far-end side TWI slave component. 1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP . NACK used in Slave Read mode: 0 = Each data byte has been correctly received by the Master. 1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it. Note: In Slave Write mode, all data are acknowledged by the TWI.
• ARBLST: Arbitration Lost (clear on read) This bit is only used in Master mode. 0: Arbitration won. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time.
• SCLWS: Clock Wait State (automatically set / reset) This bit is only used in Slave mode. 0 = The clock is not stretched. 1 = The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character. SCLWS behavior can be seen in Figure 33-37 and Figure 33-38.

DS60001614B-page 596  2020 Microchip Technology Inc.

• EOSACC: End Of Slave Access (clear on read) This bit is only used in Slave mode. 0 = A slave access is being performing. 1 = The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset. EOSACC behavior can be seen in Figure 33-39 and Figure 33-40.
• ENDRX: End of RX buffer This bit is only used in Master mode. 0 = The Receive Counter Register has not reached 0 since the last write in TWI_RCR or TWI_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in TWI_RCR or TWI_RNCR.
• ENDTX: End of TX buffer This bit is only used in Master mode. 0 = The Transmit Counter Register has not reached 0 since the last write in TWI_TCR or TWI_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in TWI_TCR or TWI_TNCR.
• RXBUFF: RX Buffer Full This bit is only used in Master mode. 0 = TWI_RCR or TWI_RNCR have a value other than 0. 1 = Both TWI_RCR and TWI_RNCR have a value of 0.
• TXBUFE: TX Buffer Empty This bit is only used in Master mode. 0 = TWI_TCR or TWI_TNCR have a value other than 0. 1 = Both TWI_TCR and TWI_TNCR have a value of 0.

33.12.7 TWI INTERRUPT ENABLE REGISTER

Name: TWI_IER Address:0x4008C024 (0), 0x40090024 (1) Access: Write-only Reset: 0x00000000

• TXCOMP: Transmission Completed Interrupt Enable
• RXRDY: Receive Holding Register Ready Interrupt Enable
• TXRDY: Transmit Holding Register Ready Interrupt Enable
• SVACC: Slave Access Interrupt Enable
• GACC: General Call Access Interrupt Enable
• OVRE: Overrun Error Interrupt Enable
• NACK: Not Acknowledge Interrupt Enable
• ARBLST: Arbitration Lost Interrupt Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TXBUFE RXBUFF ENDTX ENDRX EOSACC SCL_WS ARBLST NACK 7 6 5 4 3 2 1 0 — OVRE GACC SVACC — TXRDY RXRDY TXCOMP

 2020 Microchip Technology Inc. DS60001614B-page 597 SAM3X8ERT

• SCL_WS: Clock Wait State Interrupt Enable
• EOSACC: End Of Slave Access Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt.

33.12.8 TWI INTERRUPT DISABLE REGISTER

Name: TWI_IDR Address:0x4008C028 (0), 0x40090028 (1) Access: Write-only Reset: 0x00000000

• TXCOMP: Transmission Completed Interrupt Disable
• RXRDY: Receive Holding Register Ready Interrupt Disable
• TXRDY: Transmit Holding Register Ready Interrupt Disable
• SVACC: Slave Access Interrupt Disable
• GACC: General Call Access Interrupt Disable
• OVRE: Overrun Error Interrupt Disable
• NACK: Not Acknowledge Interrupt Disable
• ARBLST: Arbitration Lost Interrupt Disable
• SCL_WS: Clock Wait State Interrupt Disable
• EOSACC: End Of Slave Access Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• ENDTX: End of Transmit Buffer Interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
• TXBUFE: Transmit Buffer Empty Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt.

33.12.9 TWI INTERRUPT MASK REGISTER

Name: TWI_IMR Address:0x4008C02C (0), 0x4009002C (1) Access: Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TXBUFE RXBUFF ENDTX ENDRX EOSACC SCL_WS ARBLST NACK 7 6 5 4 3 2 1 0 — OVRE GACC SVACC — TXRDY RXRDY TXCOMP

DS60001614B-page 598  2020 Microchip Technology Inc. Reset: 0x00000000

• TXCOMP: Transmission Completed Interrupt Mask
• RXRDY: Receive Holding Register Ready Interrupt Mask
• TXRDY: Transmit Holding Register Ready Interrupt Mask
• SVACC: Slave Access Interrupt Mask
• GACC: General Call Access Interrupt Mask
• OVRE: Overrun Error Interrupt Mask
• NACK: Not Acknowledge Interrupt Mask
• ARBLST: Arbitration Lost Interrupt Mask
• SCL_WS: Clock Wait State Interrupt Mask
• EOSACC: End Of Slave Access Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• ENDTX: End of Transmit Buffer Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
• TXBUFE: Transmit Buffer Empty Interrupt Mask 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled.

33.12.10 TWI RECEIVE HOLDING REGISTER

Name: TWI_RHR Address:0x4008C030 (0), 0x40090030 (1) Access: Read-only Reset: 0x00000000

• RXDATA: Master or Slave Receive Holding Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TXBUFE RXBUFF ENDTX ENDRX EOSACC SCL_WS ARBLST NACK 7 6 5 4 3 2 1 0 — OVRE GACC SVACC — TXRDY RXRDY TXCOMP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXDATA

 2020 Microchip Technology Inc. DS60001614B-page 599 SAM3X8ERT

33.12.11 TWI TRANSMIT HOLDING REGISTER

Name: TWI_THR Address:0x4008C034 (0), 0x40090034 (1) Access: Read-write Reset: 0x00000000

• TXDATA: Master or Slave Transmit Holding Data

33.12.12 TWI WRITE PROTECTION MODE REGISTER

Register Name:TWI_WPROT_MODE Access Type:Read-write

• SECURITY_CODE: Write protection mode security code This security code is needed to set/reset the WPROT bit value (see “Write Protection System” on page 589 for details). Must be filled with 0x545749 (ASCII code for TWI).
• WPROT: Write protection bit Enables/Disables write protection mode. The write protected registers are:
• “TWI Clock Waveform Generator Register” on page 593
• “TWI Slave Mode Register” on page 592

33.12.13 TWI WRITE PROTECTION STATUS REGISTER

Register Name:TWI_WPROT_STATUS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXDATA 31 30 29 28 27 26 25 24 SECURITY_CODE 23 22 21 20 19 18 17 16 SECURITY_CODE 15 14 13 12 11 10 9 8 SECURITY_CODE 7 6 5 4 3 2 1 0

DS60001614B-page 600  2020 Microchip Technology Inc. Access Type:Read-only

• WPROTADDR: Write Protection Error Address Indicates the address of the register write request which generated the error.
• WPROTERR: Write Protection Error Indicates a write protection error.

33.12.14 TWI VERSION REGISTER

Name: TWI_VER Access:Read-only Reset: 0x00000000

• VERSION Reserved. Value subject to change. No functionality associated. This is the Microchip internal version of the macrocell.
• MFN Reserved. Value subject to change. No functionality associated. 31 30 29 28 27 26 25 24 WPROTADDR 23 22 21 20 19 18 17 16 WPROTADDR 15 14 13 12 11 10 9 8 WPROTADDR 7 6 5 4 3 2 1 0 R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 — — — — VERSION 7 6 5 4 3 2 1 0 VERSION

 2020 Microchip Technology Inc. DS60001614B-page 601 SAM3X8ERT

34.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSCEIVER (UART)

34.1 Description

The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for communication and trace purposes and offers an ideal medium for in-situ programming solutions. Moreover, the association with two periph- eral DMA controller (PDC) channels permits packet handling for these tasks with processor time reduced to a minimum.

34.2 Embedded Characteristics

• Two-pin UART - Implemented Features are USART Compatible - Independent Receiver and Transmitter with a Common Programmable Baud Rate Generator - Even, Odd, Mark or Space Parity Generation - Parity, Framing and Overrun Error Detection - Automatic Echo, Local Loopback and Remote Loopback Channel Modes - Interrupt Generation - Support for Two PDCDMA Channels with Connection to Receiver and Transmitter

34.3 Block Diagram

FIGURE 34-1: UART FUNCTIONAL BLOCK DIAGRAM DMA Controller Baud Rate Generator Transmit Receive Interrupt Control Peripheral Bridge Parallel Input/ Output UTXD URXD Power Management Controller MCK uart_irq APB UART

DS60001614B-page 602  2020 Microchip Technology Inc. FIGURE 34-2: UART FUNCTIONAL BLOCK DIAGRAM

34.4 Product Dependencies

34.4.1 I/O LINES

The UART pins are multiplexed with PIO lines. The programmer must first configure the corresponding PIO Controller to enable I/O line operations of the UART.

34.4.2 POWER MANAGEMENT

The UART clock is controllable through the Power Management Controller. In this case, the programmer must first con- figure the PMC to enable the UART clock. Usually, the peripheral identifier used for this purpose is 1.

34.4.3 INTERRUPT SOURCE

The UART interrupt line is connected to one of the interrupt sources of the Nested Vectored Interrupt Controller (NVIC). Interrupt handling requires programming of the NVIC before configuring the UART.

34.5 UART Operations

The UART operates in asynchronous mode only and supports only 8-bit character handling (with parity). It has no clock pin. The UART is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. Receiver timeout and transmitter time guard are not implemented. However, all the implemented features are compat- ible with those of a standard USART. TABLE 34-1: UART PIN DESCRIPTION Pin Name Description Type URXD UART Receive Data Input UTXD UART Transmit Data Output TABLE 34-2: I/O LINES Instance Signal I/O Line Peripheral UART URXD PA8 A UART UTXD PA9 A Peripheral DMA Controller Baud Rate Generator Transmit Receive Interrupt Control Peripheral Bridge Parallel Input/ Output UTXD URXD Power Management Controller MCK uart_irq APB UART

 2020 Microchip Technology Inc. DS60001614B-page 603 SAM3X8ERT

34.5.1 BAUD RATE GENERATOR

The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter. The baud rate clock is the master clock divided by 16 times the value (CD) written in UART_BRGR (Baud Rate Generator Register). If UART_BRGR is set to 0, the baud rate clock is disabled and the UART remains inactive. The maximum allowable baud rate is Master Clock divided by 16. The minimum allow - able baud rate is Master Clock divided by (16 x 65536). FIGURE 34-3: BAUD RATE GENERATOR

34.5.2 RECEIVER

34.5.2.1 Receiver Reset, Enable and Disable

After device reset, the UART receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register UART_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writing UART_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. The programmer can also put the receiver in its reset state by writing UART_CR with the bit RSTRX at 1. In doing so, the receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data is being processed, this data is lost.

34.5.2.2 Start Detection and Data Sampling

The UART only supports asynchronous operations, and this affects only its receiver. The UART receiver detects the start of a received character by sampling the URXD signal until it detects a valid start bit. A low level (space) on URXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. When a valid start bit has been detected, the receiver samples the URXD at the theoretical midpoint of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5- bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. Baud Rate MCK MCK 16-bit Counter Baud Rate Clock CD CD OUT Divide by 16 Receiver Sampling Clock

DS60001614B-page 604  2020 Microchip Technology Inc. FIGURE 34-4: START BIT DETECTION FIGURE 34-5: CHARACTER RECEPTION

34.5.2.3 Receiver Ready

When a complete character is received, it is transferred to the UART_RHR and the RXRDY status bit in UART_SR (Sta- tus Register) is set. The bit RXRDY is automatically cleared when the receive holding register UART_RHR is read. FIGURE 34-6: RECEIVER READY

34.5.2.4 Receiver Overrun

If UART_RHR has not been read by the software (or the Peripheral Data Controller or DMA Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in UART_SR is set. OVRE is cleared when the software writes the control register UART_CR with the bit RSTSTA (Reset Status) at 1. FIGURE 34-7: RECEIVER OVERRUN Sampling Clock URXD True Start Detection Baud Rate Clock D0 D1 D2 D3 D4 D5 D6 D7 URXD True Start Detection Sampling Parity Bit Stop Bit Example: 8-bit, parity enabled 1 stop 1 bit period 0.5 bit period D0 D1 D2 D3 D4 D5 D6 D7 PS S D0 D1 D2 D3 D4 D5 D6 D7 PURXD Read UART_RHR RXRDY D0 D1 D2 D3 D4 D5 D6 D7 PS S D0 D1 D2 D3 D4 D5 D6 D7 PURXD RSTSTA RXRDY OVRE stop stop

 2020 Microchip Technology Inc. DS60001614B-page 605 SAM3X8ERT

34.5.2.5 Parity Error

Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field PAR in UART_MR. It then compares the result with the received parity bit. If different, the parity error bit PARE in UART_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register UART_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is writ- ten, the PARE bit remains at 1. FIGURE 34-8: PARITY ERROR

34.5.2.6 Receiver Framing Error

When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in UART_SR is set at the same time the RXRDY bit is set. The FRAME bit remains high until the control register UART_CR is written with the bit RSTSTA at 1. FIGURE 34-9: RECEIVER FRAMING ERROR

34.5.3 TRANSMITTER

34.5.3.1 Transmitter Reset, Enable and Disable

After device reset, the UART transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register UART_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be written in the Transmit Holding Register (UART_THR) before actually starting the transmission. The programmer can disable the transmitter by writing UART_CR with the bit TXDIS at 1. If the transmitter is not oper- ating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a character has been written in the Transmit Holding Register, the characters are completed before the transmitter is actually stopped. The programmer can also put the transmitter in its reset state by writing the UART_CR with the bit RSTTX at 1. This immediately stops the transmitter, whether or not it is processing characters.

34.5.3.2 Transmit Format

The UART transmitter drives the pin UTXD at the baud rate clock speed. The line is driven depending on the format defined in the Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown in the following figure. The field PARE in the mode register UART_MR defines whether or not a parity bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. stopD0 D1 D2 D3 D4 D5 D6 D7 PSURXD RSTSTA RXRDY PARE Wrong Parity Bit D0 D1 D2 D3 D4 D5 D6 D7 PSURXD RSTSTA RXRDY FRAME Stop Bit Detected at 0 stop

DS60001614B-page 606  2020 Microchip Technology Inc. FIGURE 34-10: CHARACTER TRANSMISSION

34.5.3.3 Transmitter Control

When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register UART_SR. The trans- mission starts when the programmer writes in the Transmit Holding Register (UART_THR), and after the written char - acter is transferred from UART_THR to the Shift Register. The TXRDY bit remains high until a second character is written in UART_THR. As soon as the first character is completed, the last character written in UART_THR is transferred into the shift register and TXRDY rises again, showing that the holding register is empty. When both the Shift Register and UART_THR are empty, i.e., all the characters written in UART_THR have been pro- cessed, the TXEMPTY bit rises after the last stop bit has been completed. FIGURE 34-11: TRANSMITTER CONTROL

34.5.4 PERIPHERAL DMA CONTROLLER

Both the receiver and the transmitter of the UART are connected to a Peripheral DMA Controller (PDC) channel. The peripheral data controller channels are programmed via registers that are mapped within the UART user interface from the offset 0x100. The status bits are reported in the UART status register (UART_SR) and can generate an inter- rupt. The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of the data in UART_RHR. The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of data in UART_THR.

34.5.5 DMA SUPPORT

Both the receiver and the transmitter of the UART are connected to a DMA Controller (DMAC) channel. The DMA Controller channels are programmed via registers that are mapped within the DMAC user interface.

34.5.6 TEST MODES

The UART supports three test modes. These modes of operation are programmed by using the field CHMODE (Channel Mode) in the mode register (UART_MR). The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the URXD line, it is sent to the UTXD line. The transmitter operates normally, but has no effect on the UTXD line. The Local Loopback mode allows the transmitted characters to be received. UTXD and URXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The URXD pin level has no effect and the UTXD line is held high, as in idle state. D0 D1 D2 D3 D4 D5 D6 D7 UTXD Start Bit Parity Bit Stop Bit Example: Parity enabled Baud Rate Clock UART_THR Shift Register UTXD TXRDY TXEMPTY Data 0 Data 1 Data 0 Data 0 Data 1 Data 1S S PP Write Data 0 in UART_THR Write Data 1 in UART_THR stopstop

 2020 Microchip Technology Inc. DS60001614B-page 607 SAM3X8ERT The Remote Loopback mode directly connects the URXD pin to the UTXD line. The transmitter and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission. FIGURE 34-12: TEST MODES Receiver Transmitter Disabled RXD TXD Receiver Transmitter Disabled RXD TXD VDD Disabled Receiver Transmitter Disabled RXD TXD Disabled Automatic Echo Local Loopback Remote Loopback VDD

DS60001614B-page 608  2020 Microchip Technology Inc.

34.6 Universal Asynchronous Receiver Transceiver (UART) User Interface

Note 1: Values in the Address Size, Feature and Version Registers vary with the version of the IP block imple- mented.

34.6.1 UART CONTROL REGISTER

Name:UART_CR Address:0x400E0800 Access: Write-only

• RSTRX: Reset Receiver TABLE 34-3: REGISTER MAPPING Offset Register Name Access Reset 0x0000 Control Register UART_CR Write-only — 0x0004 Mode Register UART_MR Read-write 0x0 0x0008 Interrupt Enable Register UART_IER Write-only — 0x000C Interrupt Disable Register UART_IDR Write-only — 0x0010 Interrupt Mask Register UART_IMR Read-only 0x0 0x0014 Status Register UART_SR Read-only — 0x0018 Receive Holding Register UART_RHR Read-only 0x0 0x001C Transmit Holding Register UART_THR Write-only — 0x0020 Baud Rate Generator Register UART_BRGR Read-write 0x0 0x0024 - 0x003C Reserved — — — 0x004C - 0x00E8 Reserved — — — 0x00EC Address Size Register UART_AD- DRSIZE — — 0x00F0 IP Name 1 Register UART_IP- NAME1 — — 0x00F4 IP Name 2 Register UART_IP- NAME2 — — 0x00F8 Feature Register UART_FEA- TURE — — 0x00FC Version Register UART_VER- SION Read-only 0x- (1) 0x004C - 0x00FC Reserved — — — 0x0100 - 0x0124 PDC Area — — — 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX — —

 2020 Microchip Technology Inc. DS60001614B-page 609 SAM3X8ERT 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted.

• RSTTX: Reset Transmitter 0 = No effect. 1 = The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted.
• RXEN: Receiver Enable 0 = No effect. 1 = The receiver is enabled if RXDIS is 0.
• RXDIS: Receiver Disable 0 = No effect. 1 = The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped.
• TXEN: Transmitter Enable 0 = No effect. 1 = The transmitter is enabled if TXDIS is 0.
• TXDIS: Transmitter Disable 0 = No effect. 1 = The transmitter is disabled. If a character is being processed and a character has been written in the UART_THR and RSTTX is not set, both characters are completed before the transmitter is stopped.
• RSTSTA: Reset Status Bits 0 = No effect. 1 = Resets the status bits PARE, FRAME and OVRE in the UART_SR.

34.6.2 UART MODE REGISTER

Name:UART_MR Address:0x400E0804 Access: Read-write

• PAR: Parity Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CHMODE — — PAR – 7 6 5 4 3 2 1 0 Value Name Description

0 EVEN Even parity

1 ODD Odd parity

DS60001614B-page 610  2020 Microchip Technology Inc.

• CHMODE: Channel Mode

34.6.3 UART INTERRUPT ENABLE REGISTER

Name:UART_IER Address:0x400E0808 Access: Write-only

• RXRDY: Enable RXRDY Interrupt
• TXRDY: Enable TXRDY Interrupt
• ENDRX: Enable End of Receive Transfer Interrupt
• ENDTX: Enable End of Transmit Interrupt
• OVRE: Enable Overrun Error Interrupt
• FRAME: Enable Framing Error Interrupt
• PARE: Enable Parity Error Interrupt
• TXEMPTY: Enable TXEMPTY Interrupt
• TXBUFE: Enable Buffer Empty Interrupt
• RXBUFF: Enable Buffer Full Interrupt 0 = No effect. 1 = Enables the corresponding interrupt.

34.6.4 UART INTERRUPT DISABLE REGISTER

Name: UART_IDR Address:0x400E080C

2 SPACE Space: parity forced to 0

3 MARK Mark: parity forced to 1

4 NO No parity

0 NORMAL Normal Mode

1 AUTOMATIC Automatic Echo

2 LOCAL_LOOPBACK Local Loopback

3 REMOTE_LOOPBACK Remote Loopback

PARE FRAME OVRE ENDTX– ENDRX– — TXRDY RXRDY Value Name Description

 2020 Microchip Technology Inc. DS60001614B-page 611 SAM3X8ERT Access: Write-only

• RXRDY: Disable RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• ENDRX: Disable End of Receive Transfer Interrupt
• ENDTX: Disable End of Transmit Interrupt
• OVRE: Disable Overrun Error Interrupt
• FRAME: Disable Framing Error Interrupt
• PARE: Disable Parity Error Interrupt
• TXEMPTY: Disable TXEMPTY Interrupt
• TXBUFE: Disable Buffer Empty Interrupt
• RXBUFF: Disable Buffer Full Interrupt 0 = No effect. 1 = Disables the corresponding interrupt.

34.6.5 UART INTERRUPT MASK REGISTER

Name: UART_IMR Address:0x400E0810 Access: Read-only

• RXRDY: Mask RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• ENDRX: Mask End of Receive Transfer Interrupt
• ENDTX: Mask End of Transmit Interrupt
• OVRE: Mask Overrun Error Interrupt
• FRAME: Mask Framing Error Interrupt
• PARE: Mask Parity Error Interrupt
• TXEMPTY: Mask TXEMPTY Interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX — TXRDY RXRDY 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX– ENDRX– — TXRDY RXRDY

DS60001614B-page 612  2020 Microchip Technology Inc.

• TXBUFE: Mask TXBUFE Interrupt
• RXBUFF: Mask RXBUFF Interrupt 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled.

34.6.6 UART STATUS REGISTER

Name:UART_SR Address:0x400E0814 Access: Read-only

• RXRDY: Receiver Ready 0 = No character has been received since the last read of the UART_RHR or the receiver is disabled. 1 = At least one complete character has been received, transferred to UART_RHR and not yet read.
• TXRDY: Transmitter Ready 0 = A character has been written to UART_THR and not yet transferred to the Shift Register, or the transmitter is dis - abled. 1 = There is no character written to UART_THR not yet transferred to the Shift Register.
• ENDRX: End of Receiver Transfer 0 = The End of Transfer signal from the receiver Peripheral Data Controller channel is inactive. 1 = The End of Transfer signal from the receiver Peripheral Data Controller channel is active.
• ENDTX: End of Transmitter Transfer 0 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is inactive. 1 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is active.
• OVRE: Overrun Error 0 = No overrun error has occurred since the last RSTSTA. 1 = At least one overrun error has occurred since the last RSTSTA.
• FRAME: Framing Error 0 = No framing error has occurred since the last RSTSTA. 1 = At least one framing error has occurred since the last RSTSTA.
• PARE: Parity Error 0 = No parity error has occurred since the last RSTSTA. 1 = At least one parity error has occurred since the last RSTSTA.
• TXEMPTY: Transmitter Empty 0 = There are characters in UART_THR, or characters being processed by the transmitter, or the transmitter is disabled. 1 = There are no characters in UART_THR and there are no characters being processed by the transmitter. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX– ENDRX– — TXRDY RXRDY

 2020 Microchip Technology Inc. DS60001614B-page 613 SAM3X8ERT

• TXBUFE: Transmission Buffer Empty 0 = The buffer empty signal from the transmitter PDC channel is inactive. 1 = The buffer empty signal from the transmitter PDC channel is active.
• RXBUFF: Receive Buffer Full 0 = The buffer full signal from the receiver PDC channel is inactive. 1 = The buffer full signal from the receiver PDC channel is active.

34.6.7 UART RECEIVER HOLDING REGISTER

Name: UART_RHR Address:0x400E0818 Access: Read-only

• RXCHR: Received Character Last received character if RXRDY is set.

34.6.8 UART TRANSMIT HOLDING REGISTER

Name:UART_THR Address:0x400E081C Access:Write-only

• TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.

34.6.9 UART BAUD RATE GENERATOR REGISTER

Name:UART_BRGR Address:0x400E0820 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXCHR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXCHR

DS60001614B-page 614  2020 Microchip Technology Inc. Access:Read-write

• CD: Clock Divisor 0 = Baud Rate Clock is disabled 1 to 65,535 = MCK / (CD x 16) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CD 7 6 5 4 3 2 1 0 CD

 2020 Microchip Technology Inc. DS60001614B-page 615 SAM3X8ERT

35.0 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER

(USART)

35.1 Description

The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchro- nous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit handling in reception and trans- mission. The USART features three test modes: remote loopback, local loopback and automatic echo. The USART supports specific operating modes providing interfaces on RS485 , LIN and SPI buses, with ISO7816 T = 0 or T = 1 smart card slots, and infrared transceivers and connection to modem ports. The hardware handshaking fea- ture enables an out-of-band flow control by automatic management of the pins RTS and CTS. The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the transmitter and from the receiver. The PDCDMAC provides chained buffer management without any intervention of the processor.

35.2 Embedded Characteristics

• Programmable Baud Rate Generator
• 5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications - 1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode - Parity Generation and Error Detection - Framing Error Detection, Overrun Error Detection - MSB- or LSB-first - Optional Break Generation and Detection - By 8 or by 16 Over-sampling Receiver Frequency - Optional Hardware Handshaking RTS-CTS - Optional Modem Signal Management DTR-DSR-DCD-RI - Receiver Time-out and Transmitter Timeguard - Optional Multidrop Mode with Address Generation and Detection
• RS485 with Driver Control Signal
• ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards - NACK Handling, Error Counter with Repetition and Iteration Limit
• IrDA Modulation and Demodulation - Communication at up to 115.2 Kbps
• SPI Mode - Master or Slave - Serial Clock Programmable Phase and Polarity - SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency MCK/6
• LIN Mode (USART0 only) - Compliant with LIN 1.3 and LIN 2.0 specifications - Master or Slave - Processing of frames with up to 256 data bytes - Response Data length can be configurable or defined automatically by the Identifier - Self synchronization in Slave node configuration - Automatic processing and verification of the “Synch Break” and the “Synch Field” - The “Synch Break” is detected even if it is partially superimposed with a data byte - Automatic Identifier parity calculation/sending and verification - Parity sending and verification can be disabled - Automatic Checksum calculation/sending and verification

DS60001614B-page 616  2020 Microchip Technology Inc. - Checksum sending and verification can be disabled - Support both “Classic” and “Enhanced” checksum types - Full LIN error checking and reporting - Frame Slot Mode: the Master allocates slots to the scheduled frames automatically. - Generation of the Wakeup signal

• Test Modes - Remote Loopback, Local Loopback, Automatic Echo
• Supports Connection of Two Peripheral DMA Controller Channels (PDC)(DMAC) - Offers Buffer Transfer without Processor Intervention

35.3 Block Diagram

FIGURE 35-1: USART BLOCK DIAGRAM (Peripheral) DMA Controller Channel Channel Interrupt Controller Receiver USART Interrupt RXD TXD SCK USART PIO Controller CTS RTS DTR DSR DCD RI Transmitter Modem Signals Control Baud Rate Generator User Interface PMC MCK SLCK DIV MCK/DIV APB

 2020 Microchip Technology Inc. DS60001614B-page 617 SAM3X8ERT FIGURE 35-2: USART BLOCK DIAGRAM TABLE 35-1: SPI OPERATING MODE PIN USART SPI Slave SPI Master RXD RXD MOSI MISO TXD TXD MISO MOSI RTS RTS — CS CTS CTS CS — (Peripheral) DMA Controller Channel Channel Interrupt Controller Receiver USART Interrupt RXD TXD SCK USART PIO Controller CTS RTS Transmitter Baud Rate Generator User Interface PMC MCK SLCK DIV MCK/DIV APB

DS60001614B-page 618  2020 Microchip Technology Inc.

35.4 Application Block Diagram

FIGURE 35-3: APPLICATION BLOCK DIAGRAM FIGURE 35-4: APPLICATION BLOCK DIAGRAM Smart Card Slot USART RS232 Drivers Modem RS485 Drivers Differential Bus IrDA Transceivers Modem Driver Field Bus Driver EMV Driver IrDA Driver IrLAP RS232 Drivers Serial Port Serial Driver PPP PSTN LIN Driver LIN Transceiver SPI Driver SPI Bus Smart Card Slot USART RS232 Drivers Modem RS485 Drivers Differential Bus IrDA Transceivers Modem Driver Field Bus Driver EMV Driver IrDA Driver IrLAP RS232 Drivers Serial Port Serial Driver PPP PSTN LIN Driver LIN Transceiver

DS60001614B-page 622  2020 Microchip Technology Inc.

35.5 I/O Lines Description

TABLE 35-2: I/O LINE DESCRIPTION Name Description Type Active Level SCK Serial Clock I/O — TXD Transmit Serial Data or Master Out Slave In (MOSI) in SPI Master Mode or Master In Slave Out (MISO) in SPI Slave Mode I/O — RXD Receive Serial Data or Master In Slave Out (MISO) in SPI Master Mode or Master Out Slave In (MOSI) in SPI Slave Mode Input — RI Ring Indicator Input Low DSR Data Set Ready Input Low DCD Data Carrier Detect Input Low DTR Data Terminal Ready Output Low CTS Clear to Send or Slave Select (NSS) in SPI Slave Mode Input Low RTS Request to Send or Slave Select (NSS) in SPI Master Mode Output Low

 2020 Microchip Technology Inc. DS60001614B-page 623 SAM3X8ERT

35.6 Product Dependencies

35.6.1 I/O LINES

The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory. If the hard- ware handshaking feature or Modem mode is used, the internal pull up on TXD must also be enabled. All the pins of the modems may or may not be implemented on the USART. Only USART(s) x is/are fully equipped with all the modem signals. On USARTs not equipped with the corresponding pin, the associated control bits and statuses have no effect on the behavior of the USART.

35.6.2 POWER MANAGEMENT

The USART is not continuously clocked. The programmer must first enable the USART Clock in the Power Management Controller (PMC) before using the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where it left off. Configuring the USART does not require the USART clock to be enabled. TABLE 35-3: I/O LINES Instance Signal I/O Line Peripheral USART0 CTS0 PB26 A USART0 RTS0 PB25 A USART0 RXD0 PA10 A USART0 SCK0 PA17 B USART0 TXD0 PA11 A USART1 CTS1 PA15 A USART1 RTS1 PA14 A USART1 RXD1 PA12 A USART1 SCK1 PA16 A USART1 TXD1 PA13 A USART2 CTS2 PB23 A USART2 RTS2 PB22 A USART2 RXD2 PB21 A USART2 SCK2 PB24 A USART2 TXD2 PB20 A USART3 CTS3 PF4 A USART3 RTS3 PF5 A USART3 RXD3 PD5 B USART3 SCK3 PE16 B USART3 TXD3 PD4 B

DS60001614B-page 624  2020 Microchip Technology Inc.

35.6.3 INTERRUPT

The USART interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the USART inter- rupt requires the Interrupt Controller to be programmed first. Note: It is not recommended to use the USART interrupt line in edge sensitive mode.

35.7 Functional Description

The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes:

• 5- to 9-bit full-duplex asynchronous serial communication - MSB- or LSB-first - 1, 1.5 or 2 stop bits - Parity even, odd, marked, space or none - By 8 or by 16 over-sampling receiver frequency - Optional hardware handshaking - Optional modem signals management - Optional break management - Optional multidrop serial communication
• High-speed 5- to 9-bit full-duplex synchronous serial communication - MSB- or LSB-first - 1 or 2 stop bits - Parity even, odd, marked, space or none - By 8 or by 16 over-sampling frequency - Optional hardware handshaking - Optional modem signals management - Optional break management - Optional multidrop serial communication
• RS485 with driver control signal
• ISO7816, T0 or T1 protocols for interfacing with smart cards - NACK handling, error counter with repetition and iteration limit, inverted data.
• InfraRed IrDA Modulation and Demodulation
• SPI Mode - Master or Slave - Serial Clock Programmable Phase and Polarity - SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency MCK/6
• LIN Mode (USART0 only) - Compliant with LIN 1.3 and LIN 2.0 specifications - Master or Slave - Processing of frames with up to 256 data bytes - Response Data length can be configurable or defined automatically by the Identifier - Self synchronization in Slave node configuration - Automatic processing and verification of the “Synch Break” and the “Synch Field” - The “Synch Break” is detected even if it is partially superimposed with a data byte TABLE 35-4: PERIPHERAL IDS Instance ID USART0 17 USART1 18 USART2 19 USART3 20

 2020 Microchip Technology Inc. DS60001614B-page 625 SAM3X8ERT - Automatic Identifier parity calculation/sending and verification - Parity sending and verification can be disabled - Automatic Checksum calculation/sending and verification - Checksum sending and verification can be disabled - Support both “Classic” and “Enhanced” checksum types - Full LIN error checking and reporting - Frame Slot Mode: the Master allocates slots to the scheduled frames automatically. - Generation of the Wakeup signal

• Test modes - Remote loopback, local loopback, automatic echo

35.7.1 BAUD RATE GENERATOR

The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the trans- mitter. The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (US_MR) between:

• the Master Clock MCK
• a division of the Master Clock, the divider being product dependent, but generally set to 8
• the external clock, available on the SCK pin The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate Gen- erator Register (US_BRGR). If CD is programmed to 0, the Baud Rate Generator does not generate any clock. If CD is programmed to 1, the divider is bypassed and becomes inactive. If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 4.5 3 times lower than MCK in USART mode, or 6 in SPI mode. FIGURE 35-11: BAUD RATE GENERATOR

35.7.1.1 Baud Rate in Asynchronous Mode

If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiver as a sam- pling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR. If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock. MCK/DIV 16-bit Counter Baud Rate Clock CD CD Sampling Divider Sampling Clock Reserved MCK SCK USCLKS OVER SCK SYNC SYNC USCLKS = 3 FIDI

DS60001614B-page 626  2020 Microchip Technology Inc. The following formula performs the calculation of the Baud Rate. This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that OVER is programmed to 1.

35.7.1.1.1 Baud Rate Calculation Example

Table 35-5 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. The baud rate is calculated with the following formula: The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%.

35.7.1.2 Fractional Baud Rate in Asynchronous Mode

The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the ref- erence source clock. This fractional part is programmed with the FP field in the Baud Rate Generator Register (US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock divider. This feature is only available when using USART normal mode. The fractional Baud Rate is calculated using the following formula: TABLE 35-5: BAUD RATE EXAMPLE (OVER = 0) Source Clock Expected Baud Rate Calculation Result CD Actual Baud Rate Error MHz Bit/s Bit/s 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.16% 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.00% 14 318 180 38 400 23.30 23 38 908.10 1.31% 14 745 600 38 400 24.00 24 38 400.00 0.00% 18 432 000 38 400 30.00 30 38 400.00 0.00% 24 000 000 38 400 39.06 39 38 461.54 0.16% 24 576 000 38 400 40.00 40 38 400.00 0.00% 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.71 54 38 194.44 0.54% 40 000 000 38 400 65.10 65 38 461.54 0.16% 50 000 000 38 400 81.38 81 38 580.25 0.47% 60 000 000 38 400 97.66 98 38 265.31 0.35% 70 000 000 38 400 113.93 114 38 377.19 0.06% Baudrate SelectedClock BaudRate MCK CD 16= Error 1 ExpectedBaudRate  –=

 2020 Microchip Technology Inc. DS60001614B-page 627 SAM3X8ERT The modified architecture is presented below: FIGURE 35-12: FRACTIONAL BAUD RATE GENERATOR

35.7.1.3 Baud Rate in Synchronous Mode or SPI Mode

If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR. In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must be at least 4.5 3 times lower than the system clock. In synchronous mode master (USCLKS = 0 or 1, CLK0 set to 1), the receive part limits the SCK maximum frequency to MCK/4.5 MCK/3 in USART mode, or MCK/6 in SPI mode. When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd.

35.7.1.4 Baud Rate in ISO 7816 Mode

The ISO7816 specification defines the bit rate with the following formula: where:

• B is the bit rate
• Di is the bit-rate adjustment factor
• Fi is the clock frequency division factor
• f is the ISO7816 clock frequency (Hz) Baudrate SelectedClock 8 2 Over–  CD FP       MCK/DIV 16-bit Counter Baud Rate Clock CD CD Sampling Divider Sampling Clock Reserved MCK SCK USCLKS OVER SCK SYNC SYNC USCLKS = 3 FIDIglitch-free logic Modulus Control FP FP BaudRate SelectedClock B Di

DS60001614B-page 628  2020 Microchip Technology Inc. Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 35-6. Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table35-7. Table 35-8 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the Mode Register (US_MR) is first divided by the value programmed in the field CD in the Baud Rate Generator Register (US_BRGR). The resulting clock can be provided to the SCK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in US_MR. This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value. The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1). Figure 35-13 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock. FIGURE 35-13: ELEMENTARY TIME UNIT (ETU) TABLE 35-6: BINARY AND DECIMAL VALUES FOR DI DI field 0001 0010 0011 0100 0101 0110 1000 1001 Di (decimal) 1 2 4 8 16 32 12 20 TABLE 35-7: BINARY AND DECIMAL VALUES FOR FI FI field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 Fi (decimal) 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 TABLE 35-8: POSSIBLE VALUES FOR THE FI/DI RATIO Fi/Di 372 558 774 1116 1488 1806 512 768 1024 1536 2048 1 372 558 744 1116 1488 1860 512 768 1024 1536 2048 2 186 279 372 558 744 930 256 384 512 768 1024 4 93 139.5 186 279 372 465 128 192 256 384 512 8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256 12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6

1 ETU

FI_DI_RATIO ISO7816 Clock Cycles

 2020 Microchip Technology Inc. DS60001614B-page 629 SAM3X8ERT

35.7.2 RECEIVER AND TRANSMITTER CONTROL

After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR). However, the transmitter registers can be programmed before being enabled. The Receiver and the Transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the correspond- ing bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a timeguard is programmed, it is handled normally.

35.7.3 SYNCHRONOUS AND ASYNCHRONOUS MODES

35.7.3.1 Transmitter Operations

The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US_MR configures which data bit is sent first. If written to 1, the most significant bit is sent first. If written to 0, the less significant bit is sent first. The number of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in asynchronous mode only. FIGURE 35-14: CHARACTER TRANSMIT The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY , which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and US_THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY is low has no effect and the written character is lost. D0 D1 D2 D3 D4 D5 D6 D7 TXD Start Bit Parity Bit Stop Bit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock

DS60001614B-page 630  2020 Microchip Technology Inc. FIGURE 35-15: TRANSMITTER STATUS

35.7.3.2 Manchester Encoder

When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase Manchester II format. To enable this mode, set the MAN field in the US_MR register to 1. Depending on polarity config- uration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus, a transition always occurs at the midpoint of each bit time. It consumes more bandwidth than the original NRZ signal (2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell. An example of Manches- ter encoded sequence is: the byte 0xB1 or 10110001 encodes to 10 01 10 10 01 01 01 10, assuming the default polarity of the encoder. Figure 35-16 illustrates this coding scheme. FIGURE 35-16: NRZ TO MANCHESTER ENCODING The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a pre-defined pat- tern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the preamble waveform is not generated prior to any character. The preamble pattern is chosen among the following sequences: ALL_ONE, ALL_ZERO, ONE_ZERO or ZERO_ONE, writing the field TX_PP in the US_MAN register, the field TX_PL is used to configure the preamble length. Figure 35-17 illustrates and defines the valid patterns. To improve flexibility, the encoding scheme can be configured using the TX_MPOL field in the US_MAN register. If the TX_MPOL field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero transition. If the TX_MPOL field is set to one, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a zero-to-one transition. D0 D1 D2 D3 D4 D5 D6 D7 TXD Start Bit Parity Bit Stop Bit Baud Rate Clock Start Bit Write US_THR D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit TXRDY TXEMPTY NRZ encoded data Manchester encoded data 10110001 Txd

 2020 Microchip Technology Inc. DS60001614B-page 631 SAM3X8ERT FIGURE 35-17: PREAMBLE PATTERNS, DEFAULT POLARITY ASSUMED A start frame delimiter is to be configured using the ONEBIT field in the US_MR register. It consists of a user-defined pattern that indicates the beginning of a valid data. Figure 35-18 illustrates these patterns. If the start frame delimiter, also known as start bit, is one bit, (ONEBIT to 1), a logic zero is Manchester encoded and indicates that a new character is being sent serially on the line. If the start frame delimiter is a synchronization pattern also referred to as sync (ONEBIT to 0), a sequence of 3 bit times is sent serially on the line to indicate the start of a new character. The sync waveform is in itself an invalid Manchester waveform as the transition occurs at the middle of the second bit time. Two distinct sync patterns are used: the command sync and the data sync. The command sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half bit times. If the MODSYNC field in the US_MR register is set to 1, the next character is a command. If it is set to 0, the next character is a data. When direct memory access is used, the MODSYNC field can be immediately updated with a modified character located in memory. To enable this mode, VAR_SYNC field in US_MR register must be set to 1. In this case, the MODSYNC field in US_MR is bypassed and the sync configuration is held in the TXSYNH in the US_THR register. The USART character format is modified and includes sync information. Manchester encoded data Txd SFD DATA 8 bit width "ALL_ONE" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ALL_ZERO" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ZERO_ONE" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ONE_ZERO" Preamble

DS60001614B-page 632  2020 Microchip Technology Inc. FIGURE 35-18: START FRAME DELIMITER

35.7.3.2.1 Drift Compensation

Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the USART_MAN register must be set. If the RXD edge is one 16X clock cycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. If the RXD event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one clock cycle. If the RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is lengthened by one clock cycle. These intervals are considered to be drift and so corrective actions are automatically taken. FIGURE 35-19: BIT RESYNCHRONIZATION

35.7.3.3 Asynchronous Receiver

If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (US_MR). The receiver samples the RXD line. If the line is sampled during one half of a bit time to 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16, (OVER to 0), a start is detected at the eighth sample to 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER to 1), a start bit is detected at the fourth sample to 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. Manchester encoded data Txd SFD DATA One bit start frame delimiter Preamble Length is set to 0 Manchester encoded data Txd SFD DATA Command Sync start frame delimiter Manchester encoded data Txd SFD DATA Data Sync start frame delimiter RXD Oversampling 16x Clock Sampling point Expected edge ToleranceSynchro. Jump Sync JumpSynchro. Error Synchro. Error

 2020 Microchip Technology Inc. DS60001614B-page 633 SAM3X8ERT The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP , so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 35-20 and Figure 35-21 illustrate start detection and character reception when USART operates in asynchronous mode. FIGURE 35-20: ASYNCHRONOUS START DETECTION FIGURE 35-21: ASYNCHRONOUS CHARACTER RECEPTION

35.7.3.4 Manchester Decoder

When the MAN field in US_MR register is set to 1, the Manchester decoder is enabled. The decoder performs both pre- amble and start frame delimiter detection. One input line is dedicated to Manchester encoded input data. An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. Use RX_PL in US_MAN register to configure the length of the preamble sequence. If the length is set to 0, no preamble is detected and the function is disabled. In addition, the polarity of the input stream is programmable with RX_MPOL field in US_MAN register. Depending on the desired application the preamble pattern matching is to be defined via the RX_PP field in US_MAN. See Figure 35-17 for available preamble patterns. Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder. So, if ONEBIT field is set to 1, only a zero encoded Manchester can be detected as a valid start frame delimiter. If ONEBIT is set to 0, only a sync pattern is detected as a valid start frame delimiter. Decoder operates by detecting transition on incoming stream. If RXD is sampled during one quarter of a bit time to zero, a start bit is detected. See Figure 35-22. The sample pulse rejection mechanism applies. Sampling Clock (x16) RXD Start Detection Sampling Baud Rate Clock RXD Start Rejection Sampling 12345678 12345670 1234 12345678 9 1 01 11 21 31 41 51 6 D0 Sampling D0 D1 D2 D3 D4 D5 D6 D7 RXD Parity Bit Stop Bit Example: 8-bit, Parity Enabled Baud Rate Clock Start Detection samples samples samples samples samples samples samples samples samples samples

 2020 Microchip Technology Inc. DS60001614B-page 635 SAM3X8ERT

35.7.3.5 Radio Interface: Manchester Encoded USART Application

This section describes low data rate RF transmission systems and their integration with a Manchester encoded USART. These systems are based on transmitter and receiver ICs that support ASK and FSK modulation schemes. The goal is to perform full duplex radio transmission of characters using two different frequency carriers. See the con - figuration in Figure 35-25. FIGURE 35-25: MANCHESTER ENCODED CHARACTERS RF TRANSMISSION The USART module is configured as a Manchester encoder/decoder. Looking at the downstream communication chan- nel, Manchester encoded characters are serially sent to the RF emitter. This may also include a user defined preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish between a valid data from a trans- mitter and signals due to noise. The Manchester stream is then modulated. See Figure 35-26 for an example of ASK modulation scheme. When a logic one is sent to the ASK modulator, the power amplifier, referred to as PA, is enabled and transmits an RF signal at downstream frequency. When a logic zero is transmitted, the RF signal is turned off. If the FSK modulator is activated, two different frequencies are used to transmit data. When a logic 1 is sent, the modulator outputs an RF signal at frequency F0 and switches to F1 if the data sent is a 0. See Figure 35-27. From the receiver side, another carrier frequency is used. The RF receiver performs a bit check operation examining demodulated data stream. If a valid pattern is detected, the receiver switches to receiving mode. The demodulated stream is sent to the Manchester decoder. Because of bit checking inside RF IC, the data transferred to the microcon- troller is reduced by a user-defined number of bits. The Manchester preamble length is to be defined in accordance with the RF IC configuration. FIGURE 35-26: ASK MODULATOR OUTPUT LNA VCO RF filter Demod control bi-dir line PA RF filter Mod VCO control Manchester decoder Manchester encoder USART Receiver USART Emitter ASK/FSK Upstream Receiver ASK/FSK downstream transmitter Upstream Emitter Downstream Receiver Serial Configuration Interface Fup frequency Carrier Fdown frequency Carrier Manchester encoded data default polarity unipolar output Txd ASK Modulator Output Uptstream Frequency F0 NRZ stream 10 0 1

DS60001614B-page 636  2020 Microchip Technology Inc. FIGURE 35-27: FSK MODULATOR OUTPUT

35.7.3.6 Synchronous Receiver

In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability. Configuration fields and bits are the same as in asynchronous mode. Figure 35-28 illustrates a character reception in synchronous mode. FIGURE 35-28: SYNCHRONOUS MODE CHARACTER RECEPTION

35.7.3.7 Receiver Operations

When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit to 1. Manchester encoded data default polarity unipolar output Txd FSK Modulator Output Uptstream Frequencies [F0, F0+offset] NRZ stream 10 0 1 D0 D1 D2 D3 D4 D5 D6 D7 RXD Start Sampling Parity Bit Stop Bit Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock

 2020 Microchip Technology Inc. DS60001614B-page 637 SAM3X8ERT FIGURE 35-29: RECEIVER STATUS

35.7.3.8 Parity

The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see “Multidrop Mode” on page 638. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a number of 1s in the character data bit is even, and to 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit to 1 if a number of 1s in the character data bit is even, and to 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit to 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled to 0. If the space parity is used, the parity generator of the transmitter drives the parity bit to 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled to 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 35-9 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the configura- tion of the USART. Because there are two bits to 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit to 1. Figure 35-30 illustrates the parity bit status setting and clearing. TABLE 35-9: PARITY BIT EXAMPLES Character Hexa Binary Parity Bit Parity Mode A 0x41 0100 0001 1 Odd A 0x41 0100 0001 0 Even A 0x41 0100 0001 1 Mark A 0x41 0100 0001 0 Space A 0x41 0100 0001 None None D0 D1 D2 D3 D4 D5 D6 D7 RXD Start Bit Parity Bit Stop Bit Baud Rate Clock Write US_CR RXRDY OVRE D0 D1 D2 D3 D4 D5 D6 D7Start Bit Parity Bit Stop Bit RSTSTA = 1 Read US_RHR

DS60001614B-page 638  2020 Microchip Technology Inc. FIGURE 35-30: PARITY ERROR

35.7.3.9 Multidrop Mode

If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit to 0 and addresses are transmitted with the parity bit to 1. If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit to 1. To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA to 1. The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this case, the next byte writ- ten to US_THR is transmitted as an address. Any character written in US_THR without having written the command SENDA is transmitted normally with the parity to 0.

35.7.3.10 Transmitter Timeguard

The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When this field is programmed to zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 35-31, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains to 0 during the timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted. D0 D1 D2 D3 D4 D5 D6 D7 RXD Start Bit Bad Parity Bit Stop Bit Baud Rate Clock Write US_CR PARE RXRDY RSTSTA = 1

 2020 Microchip Technology Inc. DS60001614B-page 639 SAM3X8ERT FIGURE 35-31: TIMEGUARD OPERATIONS Table 35-10 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the func- tion of the Baud Rate.

35.7.3.11 Receiver Time-out

The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed to 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR remains to 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user can either:

• Stop the counter clock until a new character is received. This is performed by writing the Control Register (US_CR) with the STTTO (Start Time-out) bit to 1. In this case, the idle state on RXD before a new character is received will not provide a time-out. This prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received.
• Obtain an interrupt while no character is received. This is performed by writing US_CR with the RETTO (Reload and Start Time-out) bit to 1. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. TABLE 35-10: MAXIMUM TIMEGUARD LENGTH DEPENDING ON BAUD RATE Baud Rate Bit time Timeguard Bit/sec µs ms 1 200 833 212.50 9 600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21 D0 D1 D2 D3 D4 D5 D6 D7 TXD Start Bit Parity Bit Stop Bit Baud Rate Clock Start Bit TG = 4 Write US_THR D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit TXRDY TXEMPTY TG = 4

DS60001614B-page 640  2020 Microchip Technology Inc. Figure 35-32 shows the block diagram of the Receiver Time-out feature. FIGURE 35-32: RECEIVER TIME-OUT BLOCK DIAGRAM Table 35-11 gives the maximum time-out period for some standard baud rates.

35.7.3.12 Framing Error

The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit to 1. TABLE 35-11: MAXIMUM TIME-OUT PERIOD Baud Rate Bit Time Time-out bit/sec µs ms 600 1 667 109 225 1 200 833 54 613 2 400 417 27 306 4 800 208 13 653 9 600 104 6 827 14400 69 4 551 19200 52 3 413 28800 35 2 276 33400 30 1 962 56000 18 1 170 57600 17 1 138 200000 5 328 16-bit Time-out Counter TO TIMEOUT Baud Rate Clock Character Received RETTO Load Clock 16-bit Value STTTO DQ1 Clear

 2020 Microchip Technology Inc. DS60001614B-page 641 SAM3X8ERT FIGURE 35-33: FRAMING ERROR STATUS

35.7.3.13 Transmit Break

The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits to 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed. A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit to 1. This can be performed at any time, either while the transmitter is empty (no character in either the Shift Register or in US_THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing US_CR with the STPBRK bit to 1. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in US_CSR is to 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with both STTBRK and STPBRK bits to 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding Register while a break is pending, but not started, is ignored. After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations. Figure 35-34 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD line. D0 D1 D2 D3 D4 D5 D6 D7 RXD Start Bit Parity Bit Stop Bit Baud Rate Clock Write US_CR FRAME RXRDY RSTSTA = 1

DS60001614B-page 642  2020 Microchip Technology Inc. FIGURE 35-34: BREAK TRANSMISSION

35.7.3.14 Receive Break

The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a fram- ing error with data to 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the Control Register (US_CR) with the bit RSTSTA to 1. An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit.

35.7.3.15 Hardware Handshaking

The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 35-35. FIGURE 35-35: CONNECTION WITH A REMOTE DEVICE FOR HARDWARE HANDSHAKING Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2. The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin mod- ifies the behavior of the transmitter as described below. Using this mode requires using the PDCDMAC channel for reception. The transmitter can handle hardware handshaking in any case. Figure 35-36 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer to the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low. D0 D1 D2 D3 D4 D5 D6 D7 TXD Start Bit Parity Bit Stop Bit Baud Rate Clock Write US_CR TXRDY TXEMPTY STPBRK = 1STTBRK = 1 Break Transmission End of Break USART TXD CTS Remote Device RXD TXDRXD RTS RTS CTS

 2020 Microchip Technology Inc. DS60001614B-page 643 SAM3X8ERT FIGURE 35-36: RECEIVER BEHAVIOR WHEN OPERATING WITH HARDWARE HANDSHAKING Figure 35-37 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the trans- mitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. FIGURE 35-37: TRANSMITTER BEHAVIOR WHEN OPERATING WITH HARDWARE HANDSHAKING

35.7.4 ISO7816 MODE

The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1.

35.7.4.1 ISO7816 Mode Overview

The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (see “Baud Rate Generator” on page 625). The USART connects to a smart card as shown in Figure 35-38. The TXD line becomes bidirectional and the Baud Rate Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock. FIGURE 35-38: CONNECTION OF A SMART CARD TO THE USART When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode. Refer to “USART Mode Register” on page 669 and “PAR: Parity Type” on page 670. The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the trans- mitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpre- dictable results. RTS RXBUFF Write US_CR RXEN = 1 RXD RXDIS = 1 CTS TXD Smart Card SCK CLK TXD I/O USART

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