Microcontroller

SAM-L22

Microchip Technology

32-bit ARM Cortex-M0+ Ultra-Low-Power MCU family with Peripheral Touch Controller (PTC), Segment LCD Controller, Advanced Analog, USB and AES Rev A - 08/2015

Manufacturer: Microchip Technology

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Technical content

Features

1.62V – 3.63V, -40°C to +85°C, DC up to 32 MHz Core: 32 MHz ARM® Cortex®-M0+
Single-cycle hardware multiplier
Micro Trace Buffer
Memory Protection Unit (MPU) Memories
64/128/256 KB in-system self-programmable Flash
2/4/8 KB Flash Read-While-Write section
8/16/32 KB SRAM main memory System
Power-on Reset (POR) and programmable Brown-out Detection (BOD)
Internal and external clock options
External Interrupt Controller (EIC) – 16 external interrupts that can use any I/O pin – One Non-maskable Interrupt (NMI) on one I/O pin
2-pin Serial Wire Debug (SWD) Low-Power
Idle, Standby, Backup, and Off Sleep modes
SleepWalking peripherals
Battery backup support
Two runtime selectable power/performance levels
Embedded Buck/LDO regulator supporting on-the-fly selection
Active mode: < 50 µA/MHz
Standby with full retention, RTC and LCD = 3.47 µA – 2.1 µs wake-up time
Standby with full retention and RTC: 1.87 µA – 2.1 µs wake-up time
Ultra low-power Backup mode with RTC: 490 nA – 90 µs wake-up time Peripherals
Segment LCD controller – Up to 8 (4) common and 40 (44) segment terminals to drive 320 (176) segments – Static, one-half, one-third, and one-fourth bias © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 1

– Internal charge pump able to generate VLCD higher than VDDIO

16-channel Direct Memory Access Controller (DMAC)
8-channel Event System
Up to four 16-bit Timer/Counters (TC), each configurable as: – 16-bit TC with two compare/capture channels – 8-bit TC with two compare/capture channels – 32-bit TC with two compare/capture channels, by using two TCs
One 24-bit Timer/Counters for Control (TCC), with extended functions: – Four compare channels with optional complementary output – Generation of synchronized pulse width modulation (PWM) pattern across port pins – Deterministic fault protection, fast decay and configurable dead-time between complementary output – Dithering that increase resolution with up to 5-bit and reduce quantization error – PWM Channels using TC and TCC peripherals:
Up to four PWM channels on each 24-bit TCC
Up to two PWM channels on each 16-bit TC
Frequency Meter
32-bit Real-Time Counter (RTC) with Clock/Calendar function – 8x32-bit Backup Register – Tamper Detection
Watchdog Timer (WDT)
CRC-32 generator
One Full-Speed (12 Mbps) Universal Serial Bus (USB) 2.0 Device – Eight endpoints – Crystal less operation
Up to six Serial Communication Interfaces (SERCOM), each configurable as: – USART with full-duplex and single-wire half-duplex configuration – ISO7816 – I 2C up to 3.4 MHz (maximum of 1 High-Speed mode and maximum of 3 Fast mode I2C) – SPI
One AES encryption engine
One True Random Generator (TRNG)
One Configurable Custom Logic (CCL)
One 12-bit, 1 Msps Analog-to-Digital Converter (ADC) with up to 20 channels – Differential and single-ended input – Oversampling and decimation in hardware to support 13-bit, 14-bit, 15-bit, or 16-bit resolution
Two Analog Comparators (AC) with Window Compare function
Peripheral Touch Controller (PTC) – Up to 256-Channel capacitive touch sensing
Maximum Mutual-Cap up to 16x16 channels
Maximum Self-Cap up to 24 channels – Wake-up on touch in Standby mode Oscillators
32.768 kHz crystal oscillator (XOSC32K)
0.4-32 MHz crystal oscillator (XOSC)
32.768 kHz ultra-low-power internal oscillator (OSCULP32K)
16/12/8/4 MHz high-accuracy internal oscillator (OSC16M)
48 MHz Digital Frequency Locked Loop (DFLL48M)
96 MHz Fractional Digital Phased Locked Loop (FDPLL96M) I/O SAM L22 Family © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 2

Up to 82 programmable I/O pins
Up to 52 segment LCD pins can be used as GPIO/GPI
Up to five wake-up pins with optional debouncing
Up to five tamper input pins
One tamper output pin Packages
100-pin TQFP
64-pin TQFP, QFN
49-pin WLCSP
48-pin TQFP, QFN SAM L22 Family © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 3

SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter SAM L22 Family © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 9

Configuration Summary SAM L22N SAM L22J SAM L22G Pins 100 64 48 (QFN and TQFP) 49 (WLCSP) General Purpose I/O-pins (GPIOs)(1) 82 50 36 Flash 256/128/64KB 256/128/64KB 256/128/64KB Flash RWW section 8/4/2KB 8/4/2KB 8/4/2KB System SRAM 32/16/8KB 32/16/8KB 32/16/8KB Segment LCD (SLCD) Pins(1) 48 selectable from 52 31 23 Timer Counter (TC) instances 4 4 4 Waveform/PWM output or Capture input channels per TC instance 2 2 2 Timer Counter for Control (TCC) instances 1 1 1 Waveform/PWM output or Capture input channels per TCC instance 4 4 4 DMA channels 16 16 16 USB interface 1 1 1 AES engine 1 1 1 Configurable Custom Logic (CCL) (LUTs) 4 4 4 True Random Generator (TRNG) 1 1 1 Serial Communication Interface (SERCOM) instances 6 4(2) 4(2) Analog-to-Digital Converter (ADC) channels 20 16 10 Two Analog Comparators (AC) with number of external input channels 4 4 2 Tamper Input Pins 5 3 2 Wake-up Pins with debouncing 5 3 2 Real-Time Counter (RTC) Yes Yes Yes RTC alarms 1 1 1 SAM L22 Family Configuration Summary © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 14

SAM L22N SAM L22J SAM L22G RTC compare values One 32-bit value or two 16-bit values One 32-bit value or two 16-bit values One 32-bit value or two 16-bit values External Interrupt lines 16 16 16 Peripheral Touch Controller (PTC) channels (X- x Y-lines) for mutual capacitance(3) 256 (16x16) 182 (13x14) 132 (11x12) Peripheral Touch Controller (PTC) channels for self capacitance (Y-lines only)(4) 24 19 15 Maximum CPU frequency 32MHz 32MHz 32MHz Packages TQFP UFBGA QFN TQFP QFN TQFP WLCSP Oscillators 32.768 kHz crystal oscillator (XOSC32K) 0.4-32MHz crystal oscillator (XOSC) 32.768 kHz ultra-low-power internal oscillator (OSCULP32K) 16/12/8/4MHz high-accuracy internal oscillator (OSC16M) 48MHz Digital Frequency Locked Loop (DFLL48M) 96MHz Fractional Digital Phased Locked Loop (FDPLL96M) Event System channels 8 8 8 SW Debug Interface Yes Yes Yes Watchdog Timer (WDT) Yes Yes Yes Notes: 1. L22J, L22G: All SLCD Pins can be configured also as GPIOs. L22N: 44 SLCD Pins can be configured as GPIOs, 8 SLCD Pins can be used as GP input. 2. SAM L22N: SERCOM[5:0]. L22G, L22J: SERCOM[3:0]. 3. The number of X- and Y-lines depends on the configuration of the device, as some I/O lines can be configured as either X-lines or Y-lines. 4. The number of Y-lines depends on the configuration of the device, as some I/O lines can be configured as either X-lines or Y-lines. The number given here is the maximum number of Y-lines that can be obtained. SAM L22 Family Configuration Summary © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 15

Ordering Information SAML 22 G 16 A - M U T Product Family SAML = Low Power GP Microcontroller 22 = Cortex M0 + CPU, Advanced Feature Set G = 48 Pins J = 64 Pins N = 100 Pins T = Tape and Reel A = TQFP M = QFN U = WLCSP CF = UFBGA + DMA + USB + SLCD Product Series Flash Memory Density Device Variant A = Default Variant Pin Count Package Carrier Package Grade Package Type 18 = 256KB 17 = 128KB 16 = 64KB U = -40 to +85°C Matte Sn Plating Note: The device variant (last letter of the ordering number) is independent of the die revision (DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks evolution of the die.

2.1 SAM L22N

Table 2-1. SAM L22N Ordering Codes Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type ATSAML22N16A-AUT 64K 8K TQFP100 Tape & Reel ATSAML22N16A-CFUT UFBGA100 ATSAML22N17A-AUT 128K 16K TQFP100 Tape & Reel ATSAML22N17A-CFUT UFBGA100 ATSAML22N18A-AUT 256K 32K TQFP100 Tape & Reel ATSAML22N18A-CFUT UFBGA100

2.2 SAM L22J

Table 2-2. SAM L22J Ordering Codes Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type ATSAML22J16A-AUT 64K 8K TQFP64 Tape & Reel ATSAML22J16A-MUT QFN64 SAM L22 Family

Ordering Information

Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type ATSAML22J17A-AUT 128K 16K TQFP64 Tape & Reel ATSAML22J17A-MUT QFN64 ATSAML22J18A-AUT 256K 32K TQFP64 Tape & Reel ATSAML22J18A-MUT QFN64

2.3 SAM L22G

Table 2-3. SAM L22G Ordering Codes Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type ATSAML22G16A-AUT 64K 8K TQFP48 Tape & Reel ATSAML22G16A-MUT QFN48 ATSAML22G17A-AUT 128K 16K TQFP48 Tape & Reel ATSAML22G17A-MUT QFN48 ATSAML22G17A-UUT WLCSP49 ATSAML22G18A-AUT 256K 32K TQFP48 Tape & Reel ATSAML22G18A-MUT QFN48 ATSAML22G18A-UUT WLCSP49

2.4 Device Identification

The DSU - Device Service Unit peripheral provides the Device Selection bits in the Device Identification register (DID.DEVSEL) in order to identify the device by software. The SAM L22 variants have a reset value of DID=0x10820xxx, with the last digits identifying the variant: Table 2-4. SAM L22 Device Identification Values DSU DID.DEVSEL Device 0x0 L22N18 0x1 L22N17 0x2 L22N16 0x3-0x4 Reserved 0x5 L22J18 0x6 L22J17 0x7 L22J16 0x8-0x9 Reserved 0xA L22G18 0xB L22G17 0xC L22G16 0xD-0xFF Reserved SAM L22 Family © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 17

Note: The device variant (last letter of the ordering number) is independent of the die revision (DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks evolution of the die. SAM L22 Family © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 18

Block Diagram 6 x SERCOM 8 x Timer Counter AHB-APB BRIDGE C M MHIGH SPEED BUS MATRIX PORT PORT SERIAL WIRESWDIO S CORTEX-M0+ PROCESSOR Fmax 32MHz SWCLK DEVICE SERVICE UNIT AHB-APB BRIDGE A 20-CHANNEL 12-bit ADC 1MSPS AIN[19..0] VREFA AIN[3..0] S SRAM CONTROLLER 32/16/8KB RAM M 4x TIMER / COUNTER EVENT SYSTEM S 6/4/4x SERCOM

2 ANALOG

XY[23..0] X[31..24] PERIPHERAL TOUCH CONTROLLER AHB-APB BRIDGE B LP[51:0] PERIPHERAL ACCESS CONTROLLER S PAD0 WO1 PAD1 PAD2 PAD3 WO0 VREFB 256/128/64KB 8/4/2KB RWW NVM NVM CONTROLLER Cache M DMA 1x TIMER / COUNTER FOR CONTROL WO7 IOBUS DMA DMA DMA DMA DMA MEMORY TRACE BUFFER S WO0 WO1 REAL TIME COUNTER WATCHDOG TIMER RESETN OSCILLATORS CONTROLLER XOUT XIN XOUT32 XIN32 OSCULP32K OSC16M XOSC32K XOSC EXTERNAL INTERRUPT CONTROLLER MAIN CLOCKS CONTROLLER EXTINT[15..0] NMI GCLK_IO[4..0] FDPLL96M GENERIC CLOCK CONTROLLER POWER MANAGER RESET CONTROLLER OSC32K CONTROLLER SUPPLY CONTROLLER VREFBOD33 VREG SLCD CONTROLLER COM[7:0] USB FS DEVICE DP DM SOF-1KHz IN[11..0] OUT[3..0]4 x CCLFREQUENCY METER DMA TAMPER[4:0] DFLL48M EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT SAM L22 Family Block Diagram © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 19

Note: 1. Some device configurations have different number of SERCOM instances, Timer/Counter instances, PTC signals and ADC signals. The number of PTC X and Y signals is configurable. SAM L22 Family Block Diagram © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 20

Pinout

4.1 SAM L22G

Figure 4-1. 48-Pin QFN, TQFP PA5 GND PB11 PB2 PB3 RESET VDDIO GNDANA VDDOUT PA6 PA7 PA13 PA4 PB8 PB9 PB23 PB22 PA12 PA31 PA30 PA27 PA9 PA10 PA11 PA8 PA14 PA15 VDDIO GND PA24 PA25 PA21 PA22 PA20 PA23 PA16 PA17 PA18 PA19 GND VLCD PA3 PA2 PA1 PA0 SAM L22 48-pins VDDCORE VDDANA VDDIO Digital PinGround Power Supply Reset LCDAnalog Pin Oscillators Battery Backup SAM L22 Family Pinout © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 21

Figure 4-2. 49-Pin WLCSP PA00 PA01 GNDA VDDANA PA02 PA03PB08 PB09 PA05 PA04 PA06 PA07 GND PA08 PA09 PA10 PA11 GND VDDIO3 VLCD PB11 PA12 PA13 PA14 PA15 GND VDDIO2 PA25 PA24 PA16 PA17 PA18 PA19 PA20 PA21PA22 PA23 PB03 PB02 (1) PA31 PA30 VDDIO1 VDDOUT VDD CORE RESET PA27 PB23 PB22 GND Digital PinGround Power Supply Reset Digital/LCD Analog Pin Battery Backup/ Oscillators Analog/LCD Analog/Battery BackupDigital/Oscillators A B C D E F G A B C D E F G 1 23456 7 1 23456 7 (BOTTOM VIEW) Note: 1. PB02 has an internal connection to PB00. PB00 is not available on any other pin of the device and is only enabled with PS_OK function. The connection between PB02 and PB00 is only available on ASTAML22G17A- UUTA2. ATSAML22G17A-UUTA0/1 have the same pin function as standard product ATSAML22G17A-UUT. SAM L22 Family Pinout © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 22

4.2 SAM L22J

4.3 SAM L22N

Figure 4-3. TQFP100 SAM L22 100 RESET VDDIO GND VDDOUT VDDIO GND VDDANA PB1 PB0 PB3 PB2 PB30 PB31 PC2 PC3 PC5 PA7 PA6 PA4 PA5 PB8 PB9 PA12 PA13 PA14 PA15 PB25 PB24 PC7 PB23 PB22 PA1 PA0 PC26 PC24 PC25 PC6 PC27 PA31 PA30 VDDCORE PA27 PA16 PA17 PA18 PA19 VDDIO PA24 PA25 PA21 PA22 PA20 PA23 PB18 PB19 PB16 PB17 PC17 PC18 PC16 VDDIO GND PB5 PB4 PA2 PA3 PB7 PB6 PC19 PC20 GND VDDANA PB11 PB14 PB15 PB12 PB13 PA8 PA9 PA10 PA11 PC14 PC10 PC9 PC8 PC15 PC13 PC11 PC12 GND VDDIO VLCD GND GND PB20 PB21 PC28 PC0 PC1 PC21 100-pins Digital PinGround Power Supply Reset LCDAnalog Pin Oscillators Battery Backup SAM L22 Family Pinout © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 24

Figure 4-4. UFBGA100 RESET PA00 PA01 PC02 PA02 PB04 PB06 PB16 PB18 PB19 GNDIO07 PC28 PA27 PC21 PB17 PB20 PA30 PB03 PC00 PB05 GNDANA00 PB02 PB30 PC01 PC03 PA03 PB01 PB00 VDDIO07- VDDIN01 GNDIO04 PA31 VDDANA00 PB31 A B C D E F 1 2 3 4 5 6 7 8 9 10 11 G H J K L VDDCORE01 PC27 PB23 PB22 PA25 PA24 PC26 PC25 PC24 PA23 PA22 GNDIO05 PB25 PB24 PA21 PA20 PB21VDDIO05 VDDIO04 PB08 PB07 VDDANA02 GNDIO03 PC19 PC20 PA04 PB09 PA05 GNDANA02 VDDIO03 PA18 PC17 PC18 PA06 VDDIO02PC09PC07PA07 PA10 GNDIO02 PC14 PA16 PA19 PC16 PC05 PB11PC12PA11PC06 PC10 PB12 PB14 PA12 PA14 PA17 PA08 VLCD0PC13PC08PA09 PC11 PB13 PB15 PC15 PA13 PA15 VDDOUT Digital PinGround Power Supply Reset Digital/LCD Analog Pin Battery Backup/ Oscillators Analog/LCD Analog/Battery BackupDigital/Oscillators (TOP VIEW) SAM L22 Family Pinout © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 25

Signal Descriptions List The following table gives details on signal names classified by peripheral. Table 5-1. Signal Descriptions List Signal Name Function Type Active Level Analog Comparators - AC AIN[3:0] AC Analog Inputs Analog CMP[1:0] AC Analog Output Analog Analog Digital Converter - ADC AIN[19:0] ADC Analog Inputs Analog VREFA ADC Voltage External Reference A Analog VREFB ADC Voltage External Reference B Analog External Interrupt Controller - EIC EXTINT[15:0] External Interrupts inputs Digital NMI External Non-Maskable Interrupt input Digital Generic Clock Generator - GCLK GCLK_IO[4:0] Generic Clock (source clock inputs or generic clock generator output) Digital Custom Control Logic - CCL IN[11:0] Logic Inputs Digital OUT[3:0] Logic Outputs Digital Supply Controller - SUPC VBAT External battery supply Inputs Analog PSOK Main Power Supply OK input Digital OUT[1:0] Logic Outputs Digital Power Manager - PM RESETN Reset input Digital Low Serial Communication Interface - SERCOMx PAD[3:0] SERCOM Inputs/Outputs Pads Digital Oscillators Control - OSCCTRL XIN Crystal or external clock Input Analog/Digital XOUT Crystal Output Analog 32KHz Oscillators Control - OSC32KCTRL XIN32 32KHz Crystal or external clock Input Analog/Digital XOUT32 32KHz Crystal Output Analog Timer Counter - TCx SAM L22 Family Signal Descriptions List © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 26

Signal Name Function Type Active Level WO[1:0] Waveform/PWM outputs or Capture Inputs Digital Timer Counter - TCCx WO[7:0] Waveform/PWM outputs or Capture Inputs Digital Peripheral Touch Controller - PTC X[7:0] PTC Input/Output Analog Y[23:0] PTC Input/Output Analog X[31:24] PTC Output Analog General Purpose I/O - PORT PA25 - PA00 Parallel I/O Controller I/O Port A Digital PA27 Parallel I/O Controller I/O Port A Digital PA31 - PA30 Parallel I/O Controller I/O Port A Digital PB09 - PB00 Parallel I/O Controller I/O Port B Digital PB25 - PB11 Parallel I/O Controller I/O Port B Digital PB31 - PB30 Parallel I/O Controller I/O Port B Digital PC03 - PC00 Parallel I/O Controller I/O Port C Digital PC07 - PC05 Parallel I/O Controller I/O Port C Digital PC17 - PC12 Parallel I/O Controller I/O Port C Digital PC28 - PC24 Parallel I/O Controller I/O Port C Digital General Purpose input - PORT PC11 - PC08 Parallel I/O Controller input Port C Digital PC21 - PC18 Parallel I/O Controller input Port C Digital Segment LCD SLCD51 - SLCD00 Segment LCD Analog VLCD Bias Voltage Analog Universal Serial Bus - USB DP DP for USB Digital DM DM for USB Digital SOF 1kHz USB Start of Frame Digital Real Timer Clock - RTC RTC_IN[4:0] Tamper or external wake-up pins Digital RTC_OUT Tamper output Digital SAM L22 Family Signal Descriptions List © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 27

I/O Multiplexing and Considerations

6.1 Multiplexed Signals

Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned a different peripheral functions. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to '1'. The selection of peripheral function A to I is done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) of the PORT. This table describes the peripheral signals multiplexed to the PORT I/O pins. Table 6-1. PORT Function Multiplexing Function - A B C D E F G H I Type L22G(5) L22J L22N Pad Name EIC ANAREF ADC AC PTC SLCD SERCOM(6) SERCOM(6) TC/TCC TCC/RTC COM/RTC AC/GCLK CCL Battery backup 1 1 1 PA00 EIC/EXTINT[0] SERCOM1/PAD[0] 2 2 2 PA01 EIC/EXTINT[1] SERCOM1/PAD[1]

3 PC00 EIC/EXTINT[8] ADC/AIN[16] RTC/IN[3]

4 PC01 EIC/EXTINT[9] ADC/AIN[17] RTC/IN[4]

5 PC02 EIC/EXTINT[10] ADC/AIN[18] PTC/XY[6]

6 PC03 EIC/EXTINT[11] ADC/AIN[19] PTC/XY[7]

3 3 7 PA02 EIC/EXTINT[2] ADC/VREFB ADC/AIN[0] AC/AIN[0] PTC/XY[8] RTC/IN[2] 4 4 8 PA03 EIC/EXTINT[3] ADC/VREFA ADC/AIN[1] AC/AIN[1] PTC/XY[9] 5 9 PB04 EIC/EXTINT[4] ADC/AIN[12] AC/AIN[2] PTC/XY[10] 6 10 PB05 EIC/EXTINT[5] ADC/AIN[13] AC/AIN[3] PTC/XY[11] 9 13 PB06 EIC/EXTINT[6] ADC/AIN[14] PTC/XY[12] SLCD/LP[0] CCL/IN[6] 10 14 PB07 EIC/EXTINT[7] ADC/AIN[15] PTC/XY[13] SLCD/LP[1] CCL/IN[7] 7 11 15 PB08 EIC/EXTINT[8] ADC/AIN[2] PTC/XY[14] SLCD/LP[2] SERCOM3/PAD[0] TC/0/WO[0] CCL/IN[8] 8 12 16 PB09 EIC/EXTINT[9] ADC/AIN[3] PTC/XY[15] SLCD/LP[3] SERCOM3/PAD[1] TC/0/WO[1] CCL/OUT[2] 9 13 17 PA04 EIC/EXTINT[4] ADC/AIN[4] PTC/X[24] SLCD/LP[4] SERCOM0/PAD[0] TCC/WO[0] CCL/IN[0] 10 14 18 PA05 EIC/EXTINT[5] ADC/AIN[5] PTC/X[25] SLCD/LP[5] SERCOM0/PAD[1] TCC/WO[1] CCL/IN[1] 11 15 19 PA06 EIC/EXTINT[6] ADC/AIN[6] PTC/X[26] SLCD/LP[6] SERCOM0/PAD[2] CCL/IN[2] 12 16 20 PA07 EIC/EXTINT[7] ADC/AIN[7] PTC/X[27] SLCD/LP[7] SERCOM0/PAD[3] CCL/OUT[0]

21 PC05 EIC/EXTINT[13] PTC/XY[4] SLCD/LP[8]

22 PC06 EIC/EXTINT[14] PTC/XY[5] SLCD/LP[9]

23 PC07 EIC/EXTINT[15] SLCD/LP[10]

13 17 26 PA08 EIC/NMI PTC/XY[3] SLCD/LP[11] SERCOM0/PAD[0] SERCOM4/PAD[0] TCC/WO[0] CCL/IN[3] 14 18 27 PA09 EIC/EXTINT[9] PTC/XY[2] SLCD/LP[12] SERCOM0/PAD[1] SERCOM4/PAD[1] TCC/WO[1] CCL/IN[4] 15 19 28 PA10 EIC/EXTINT[10] PTC/XY[1] SLCD/LP[13] SERCOM0/PAD[2] SERCOM4/PAD[2] TCC/WO[2] GCLK/IO[4] CCL/IN[5] 16 20 29 PA11 EIC/EXTINT[11] PTC/XY[0] SLCD/LP[14] SERCOM0/PAD[3] SERCOM4/PAD[3] TCC/WO[3] CCL/OUT[1]

30 PC08 EIC/EXTINT[0] SLCD/LP[15]

31 PC09 EIC/EXTINT[1] SLCD/LP[16]

32 PC10 EIC/EXTINT[2] SLCD/LP[17] SERCOM1/PAD[2]

33 PC11 EIC/EXTINT[3] SLCD/LP[18] SERCOM1/PAD[3]

34 PC12 EIC/EXTINT[4] SLCD/LP[19] SERCOM1/PAD[0]

35 PC13 EIC/EXTINT[5] SLCD/LP[20] SERCOM1/PAD[1]

20 24 39 PB11 EIC/EXTINT[11] SLCD/LP[21] SERCOM3/PAD[3] TC/1/WO[1] TCC/WO[5] CCL/OUT[1] I2C: full Fm+. Limited currents for Sm, Fm 25 40 PB12 EIC/EXTINT[12] SLCD/LP[22] SERCOM3/PAD[0] TC/0/WO[0] TCC/WO[6] 26 41 PB13 EIC/EXTINT[13] SLCD/LP[23] SERCOM3/PAD[1] TC/0/WO[1] TCC/WO[7] 27 42 PB14 EIC/EXTINT[14] SLCD/LP[24] SERCOM3/PAD[2] TC/1/WO[0] GCLK/IO[0] CCL/IN[9] 28 43 PB15 EIC/EXTINT[15] SLCD/LP[25] SERCOM3/PAD[3] TC/1/WO[1] GCLK/IO[1] CCL/IN[10]

44 PC14 EIC/EXTINT[6] SLCD/LP[26]

45 PC15 EIC/EXTINT[7] SLCD/LP[27]

I2C: Sm, Fm, Fm+ 21 29 46 PA12 EIC/EXTINT[12] SLCD/LP[28] SERCOM4/PAD[0] SERCOM3/PAD[0] TCC/WO[6] AC/CMP[0] 22 30 47 PA13 EIC/EXTINT[13] SLCD/LP[29] SERCOM4/PAD[1] SERCOM3/PAD[1] TCC/WO[7] AC/CMP[1] 23 31 48 PA14 EIC/EXTINT[14] SLCD/LP[30] SERCOM4/PAD[2] SERCOM3/PAD[2] TCC/WO[4] GCLK/IO[0] 24 32 49 PA15 EIC/EXTINT[15] SLCD/LP[31] SERCOM4/PAD[3] SERCOM3/PAD[3] TCC/WO[5] GCLK/IO[1] 25 35 52 PA16 EIC/EXTINT[0] PTC/X[28] SLCD/LP[32] SERCOM1/PAD[0] SERCOM2/PAD[0] TCC/WO[6] GCLK/IO[2] CCL/IN[0] 26 36 53 PA17 EIC/EXTINT[1] PTC/X[29] SLCD/LP[33] SERCOM1/PAD[1] SERCOM2/PAD[1] TCC/WO[7] GCLK/IO[3] CCL/IN[1] 27 37 54 PA18 EIC/EXTINT[2] PTC/X[30] SLCD/LP[34] SERCOM1/PAD[2] SERCOM2/PAD[2] TCC/WO[2] AC/CMP[0] CCL/IN[2] 28 38 55 PA19 EIC/EXTINT[3] PTC/X[31] SLCD/LP[35] SERCOM1/PAD[3] SERCOM2/PAD[3] TCC/WO[3] AC/CMP[1] CCL/OUT[0]

56 PC16 EIC/EXTINT[8] SLCD/LP[36]

57 PC17 EIC/EXTINT[9] SLCD/LP[37]

Function - A B C D E F G H I Type L22G(5) L22J L22N Pad Name EIC ANAREF ADC AC PTC SLCD SERCOM(6) SERCOM(6) TC/TCC TCC/RTC COM/RTC AC/GCLK CCL

58 PC18 EIC/EXTINT[10] SLCD/LP[38]

59 PC19 EIC/EXTINT[11] SLCD/LP[39]

60 PC20 EIC/EXTINT[12] SLCD/LP[40] CCL/IN[9]

61 PC21 EIC/EXTINT[13] SLCD/LP[41] CCL/IN[10]

39 64 PB16 EIC/EXTINT[0] SLCD/LP[42] SERCOM5/PAD[0] TC/2/WO[0] TCC/WO[4] GCLK/IO[2] CCL/IN[11] 40 65 PB17 EIC/EXTINT[1] SLCD/LP[43] SERCOM5/PAD[1] TC/2/WO[1] TCC/WO[5] GCLK/IO[3] CCL/OUT[3]

66 PB18 EIC/EXTINT[2] SLCD/LP[44] SERCOM5/PAD[2] SERCOM3/PAD[2] TCC/WO[0]

67 PB19 EIC/EXTINT[3] SLCD/LP[45] SERCOM5/PAD[3] SERCOM3/PAD[3] TCC/WO[1]

68 PB20 EIC/EXTINT[4] SLCD/LP[46] SERCOM3/PAD[0] SERCOM5/PAD[0] TCC/WO[2]

69 PB21 EIC/EXTINT[5] SLCD/LP[47] SERCOM3/PAD[1] SERCOM5/PAD[1] TCC/WO[3]

29 41 70 PA20 EIC/EXTINT[4] PTC/XY[16] SLCD/LP[48] SERCOM0/PAD[0] SERCOM2/PAD[2] TC/3/WO[0] TCC/WO[6] GCLK/IO[4] 30 42 71 PA21 EIC/EXTINT[5] PTC/XY[17] SLCD/LP[49] SERCOM0/PAD[1] SERCOM2/PAD[3] TC/3/WO[1] TCC/WO[7] I2C: Sm, Fm, Fm+ 31 43 72 PA22 EIC/EXTINT[6] PTC/XY[18] SLCD/LP[50] SERCOM0/PAD[2] SERCOM2/PAD[0] TC/0/WO[0] TCC/WO[4] CCL/IN[6] 32 44 73 PA23 EIC/EXTINT[7] PTC/XY[19] SLCD/LP[51] SERCOM0/PAD[3] SERCOM2/PAD[1] TC/0/WO[1] TCC/WO[5] USB/SOF_1KHZ CCL/IN[7] 33 45 74 PA24 EIC/EXTINT[12] SERCOM2/PAD[2] SERCOM5/PAD[0] TC/1/WO[0] TCC/WO[0] USB/DM CCL/IN[8] 34 46 75 PA25 EIC/EXTINT[13] SERCOM2/PAD[3] SERCOM5/PAD[1] TC/1/WO[1] TCC/WO[1] USB/DP CCL/OUT[2] 37 49 78 PB22 EIC/EXTINT[6] SERCOM0/PAD[2] SERCOM5/PAD[2] TC/3/WO[0] TCC/WO[2] USB/SOF_1KHZ GCLK/IO[0] CCL/IN[0] 38 50 79 PB23 EIC/EXTINT[7] SERCOM0/PAD[3] SERCOM5/PAD[3] TC/3/WO[1] TCC/WO[3] GCLK/IO[1] CCL/OUT[0]

80 PB24 EIC/EXTINT[8] SERCOM0/PAD[0] SERCOM4/PAD[0] TCC/WO[6] AC/CMP[0]

81 PB25 EIC/EXTINT[9] SERCOM0/PAD[1] SERCOM4/PAD[1] TCC/WO[7] AC/CMP[1]

82 PC24 EIC/EXTINT[0] SERCOM0/PAD[2] SERCOM4/PAD[2] TC/2/WO[0] TCC/WO[0]

83 PC25 EIC/EXTINT[1] SERCOM0/PAD[3] SERCOM4/PAD[3] TC/2/WO[1] TCC/WO[1]

84 PC26 EIC/EXTINT[2] TC/3/WO[0] TCC/WO[2]

85 PC27 EIC/EXTINT[3] SERCOM1/PAD[0] TC/3/WO[1] TCC/WO[3] CCL/IN[4]

86 PC28 EIC/EXTINT[4] PTC/XY[20] SERCOM1/PAD[1] TCC/WO[4] CCL/IN[5]

recommended for GCLK IO 39 51 87 PA27 EIC/EXTINT[15] PTC/XY[21] TCC/WO[5] GCLK/IO[0] 40 52 88 RESET_N 45 57 93 PA30 EIC/EXTINT[10] PTC/XY[22] SERCOM1/PAD[2] CORTEX_M0P/SWCLK GCLK/IO[0] CCL/IN[3] 46 58 94 PA31 EIC/EXTINT[11] PTC/XY[23] SERCOM1/PAD[3] SWDIO CCL/OUT[1] I2C: Sm, Fm, Fm+, Hs 59 95 PB30 EIC/EXTINT[14] SERCOM1/PAD[0] SERCOM5/PAD[0] TCC/WO[0] 60 96 PB31 EIC/EXTINT[15] SERCOM1/PAD[1] SERCOM5/PAD[1] TCC/WO[1] Battery backup 61 97 PB00 EIC/EXTINT[0] ADC/AIN[8] SERCOM3/PAD[2] SERCOM5/PAD[2] TC/3/WO[0] RTC/IN[0] CCL/IN[1] 62 98 PB01 EIC/EXTINT[1] ADC/AIN[9] SERCOM3/PAD[3] SERCOM5/PAD[3] TC/3/WO[1] RTC/IN[2] RTC/OUT CCL/IN[2] 47 63 99 PB02 EIC/EXTINT[2] ADC/AIN[10] SERCOM3/PAD[0] SERCOM5/PAD[0] TC/2/WO[0] RTC/IN[1] CCL/OUT[0] 48 64 100 PB03 EIC/EXTINT[3] ADC/AIN[11] SERCOM3/PAD[1] SERCOM5/PAD[1] TC/2/WO[1] Notes: 1. All analog pin functions are on peripheral function B. Peripheral function B must be selected to disable the digital control of the pin. 2. Only some pins can be used in SERCOM I 2C mode. See the Type column for supported I2C modes. – Sm: Standard mode, up to 100kHz – Fm: Fast mode, up to 400kHz – Fm+: Fast mode Plus, up to 1MHz – Hs: High-speed mode, up to 3.4MHz 3. These pins are High Sink pins and have different properties than regular pins: PA12, PA13, PA22, PA23, PA27, PA31, PB30, PB31. 4. Clusters of multiple GPIO pins are sharing the same supply pin. 5. The 49 th pin of the WLCSP49 package is an additional GND pin. 6. SAM L22N: SERCOM[0:5]. SAM L22G, L22J: SERCOM[0:3].

6.2 Other Functions

6.2.1 Oscillator Pinout

The oscillators are not mapped to the normal PORT functions and their multiplexing is controlled by registers in the Oscillators Controller (OSCCTRL) and in the 32K Oscillators Controller (OSC32KCTRL). SAM L22 Family I/O Multiplexing and Considerations © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 29

Table 6-2. Oscillator Pinout Oscillator Supply Signal I/O pin XOSC VDDIO XIN PB22 XOUT PB23 XOSC32K VSWOUT XIN32 PA00 XOUT32 PA01 Note: In order to minimize the cycle-to-cycle jitter of the external oscillator, keep the neighboring pins as steady as possible. For neighboring pin details, refer to the Oscillator Pinout section. Table 6-3. XOSC32K Jitter Minimization Package Steady Signal Recommended L22N PB00, PB01, PB02, PB03, PC00, PC01 L22J PB00, PB01, PB02, PB03, PA02, PA03 L22G PB02, PB03, PA02, PA03

6.2.2 Serial Wire Debug Interface Pinout

Only the SWCLK pin is mapped to the normal PORT functions. A debugger cold-plugging or hot-plugging detection will automatically switch the SWDIO port to the SWDIO function. Table 6-4. Serial Wire Debug Interface Pinout Signal Supply I/O pin SWCLK VDDIO PA30 SWDIO VDDIO PA31

6.2.3 SERCOM USART and I2C Configurations

The SAM L22 has up to six instances of the serial communication interface (SERCOM) peripheral. The following table lists the supported communication protocols for each SERCOM instance. Table 6-5. SERCOM USART and I2C Protocols SERCOM Instance Protocol SERCOM0 SERCOM1 SERCOM2 SERCOM3 SERCOM4 SERCOM5 I2C no yes yes yes yes yes I2C at 3.4MHz no yes no no no yes USART including RS485 and ISO 7816 yes yes yes yes yes yes SPI yes yes yes yes yes yes Note: Not all available I2C pins support I2C mode at 3.4MHz. SAM L22 Family I/O Multiplexing and Considerations © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 30

6.2.4 GPIO Pin Clusters

Table 6-6. GPIO Clusters Package Cluster GPIO Supplies Pin connected to the cluster 100 pins 1 PA02, PA03, PB04, PB05, PC02, PC03 VDDANA pin12 GNDANA pin11 2 PA04, PA05, PA06, PA07, PB06, PB07, PB08, PB09, PC05, PC06, PC07 VDDANA pin12, VDDANA pin25 GNDANA pin11, GNDANA pin24

3 PA08, PA09, PA10, PA11, PC08, PC09, PC10, PC11, PC12, PC13 VDDIO pin36 GND pin37

4 PA12, PA13, PA14, PA15, PB11, PB12, PB13, PB14, PB15, PC14, PC15 VDDIO pin36, VDDIO pin51 GND pin37, GND pin50 5 PA16, PA17, PA18, PA19, PC16, PC17, PC18, PC19, PC20, PC21 VDDIO pin51, VDDIO pin63 GND pin50, GND pin62 6 PA20, PA21, PA22, PA23, PA24, PA25, PB16, PB17, PB18, PB19, PB20, PB21 VDDIO pin63, VDDIO pin77 GND pin62, GND pin76 7 PA27, PB22, PB23, PB24, PB25, PC24, PC25, PC26, PC27, PC28 VDDIO pin77, VDDIO pin92 GND pin76, GND pin90

8 PA00, PA01, PA30, PA31, PB00, PB01, PB02, PB03, PB30, PB31, PC00, PC01 VDDIO pin92 GND pin90

64 pins 1 PA02, PA03, PA04, PA05, PA06, PA07, PB04, PB05, PB06, PB07, PB08, PB09 VDDANA pin8 GNDANA pin7

2 PA08, PA09, PA10, PA11 VDDIO pin21 GND pin22

3 PA12, PA13, PA14, PA15, PB11, PB12, PB13, PB14, PB15 VDDIO pin21, VDDIO pin34 GND pin22, GND pin33

4 PA16, PA17, PA18, PA19, PA20, PA21, PA22, PA23, PA24, PA25, PB16, PB17 VDDIO pin34, VDDIO pin48 GND pin33, GND pin47

5 PA27, PB22, PB23 VDDIO pin48, VDDIO pin56 GND pin47, GND pin54

6 PA00, PA01, PA30, PA31, PB00, PB01, PB02, PB03, PB30, PB31 VDDIO pin56 GND pin54

48 pins 1 PA02, PA03, PA04, PA05, PA06, PA07, PB08, PB09 VDDANA pin6 GNDANA pin5

2 PA08, PA09, PA10, PA11 VDDIO pin17 GND pin18

3 PA12, PA13, PA14, PA15, PA16, PA17, PA18, PA19, PA20, PA21, PA22, PA23, PA24, PA25, PB11 VDDIO pin17, VDDIO pin36 GND pin18, GND pin35

4 PA27, PB22, PB23 VDDIO pin36, VDDIO pin44 GND pin35, GND pin42

5 PA00, PA01, PA30, PA31, PB02, PB03 VDDIO pin44 GND pin42

49 pins 1 PA02, PA03, PA04, PA05, PA06, PA07, PB08, PB09 VDDANA pin D7 GNDANA pin C7

2 PA08, PA09, PA10, PA11 VDDIO pin G5 GND pin F5

3 PA12, PA13, PA14, PA15, PA16, PA17, PA18, PA19, PB11 VDDIO pin G5, VDDIO pin E1 GND pin F5, GND pin E2

4 PA20, PA21, PA22, PA23, PA24, PA25 VDDIO pin E1, VDDIO pin A5 GND pin E2, GND pin D4

4 PA27, PB22, PB23 VDDIO pin E1, VDDIO pin A5 GND pin D4, GND pin B3

5 PA00, PA01, PA30, PA31, PB02, PB03 VDDIO pin A5 GND pin B3

Power Supply and Start-Up Considerations

7.1 Power Domain Overview

PA[7:2] PB[9:4] PA[1:0] BOD33 POR BOD12 VBAT(PB[3]) XOSC32KOSCULP32K PB[3:0] OSC16M VDDOUT PB[31:11] PA[31:8] VDDIO VBAT VSWOUT RTC, PM, SUPC, RSTC VOLTAGE REGULATOR VDDBU VDDANA DFLL48M FDPLL96M Digital Logic CPU, Peripherals VDDCORE XOSC PC[1:0] PC[7:5] PC[3:2] PC[28:8] VLCD The SAM L22 power domains are not independent of each other:

VDDCORE and VDDIO share GND, whereas VDDANA refers to GNDANA.
VDDCORE serves as the internal voltage regulator output.
VSWOUT and VDDBU are internal power domains.

7.2 Power Supply Considerations

7.2.1 Power Supplies

The SAM L22 has several different power supply pins:

VDDIO powers I/O lines and OSC16M, XOSC, the internal regulator for VDDCORE and the Automatic Power Switch. Voltage is 1.62V to 3.63V
VDDANA powers I/O lines and the ADC, AC, LCD and PTC. Voltage is 1.62V to 3.63V
VLCD has two alternative functions: – Output of the LCD voltage pump when VLCD is generated internally. Output voltage is 2.5V to 3.5V. – Supply input for the bias generator when VLCD is provided externally by the application. Input voltage is 2.4 to 3.6V.
VBAT powers the Automatic Power Switch. Voltage is 1.62V to 3.63V
VDDCORE serves as the internal voltage regulator output. It powers the core, memories, peripherals, DFLL48M and FDPLL96M. Voltage is 0.9V to 1.2V typical.
The Automatic Power Switch is a configurable switch that selects between VDDIO and VBAT as supply for the internal output VSWOUT, see the figure in 7.1. Power Domain Overview. The same voltage must be applied to both VDDIO and VDDANA. This common voltage is referred to as VDD in the datasheet. The ground pins, GND, are common to VDDCORE, and VDDIO. The ground pin for VDDANA is GNDANA. SAM L22 Family Power Supply and Start-Up ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 32

For decoupling recommendations for the different power supplies, refer to the schematic checklist.

7.2.2 Voltage Regulator

The SAM L22 internal Voltage Regulator has four different modes:

Linear mode : This is the default mode when CPU and peripherals are running. It does not require an external inductor.
Switching mode. This is the most efficient mode when the CPU and peripherals are running. This mode can be selected by software on the fly.
Low Power (LP) mode. This is the default mode used when the chip is in standby mode.
Shutdown mode. When the chip is in backup mode, the internal regulator is off. Note that the Voltage Regulator modes are controlled by the Power Manager.

7.2.3 Typical Powering Schematic

SAM L22 uses a single supply from 1.62V to 3.63V. The following figure shows the recommended power supply connection. Figure 7-1. Power Supply Connection for Linear Mode Only VDDANA VDDIO VDDCORE GND GNDANA SAM L22 VDDOUT VBAT (PB03) (1.62V — 3.63V) Main Supply Note: Refer to the Schematic Checklist chapter for additional information. SAM L22 Family Power Supply and Start-Up ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 33

Figure 7-2. Power Supply Connection for Switching/Linear Mode VDDANA VDDIO VDDCORE GND GNDANA VDDOUT (1.62V — 3.63V) Main Supply VBAT (PB03)SAM L22 Note: Refer to the Schematic Checklist chapter for additional information. Figure 7-3. Power Supply Connection for Battery Backup VDDANA VDDIO VDDCORE GND GNDANA VDDOUT (1.62V — 3.63V) Main Supply VBAT (PB03)SAM L22 Note: Refer to the Schematic Checklist chapter for additional information.

7.2.4 Power-Up Sequence

7.2.4.1 Supply Order

VDDIO and VDDANA must have the same supply sequence. Ideally, they must be connected together. SAM L22 Family Power Supply and Start-Up ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 34

7.2.4.2 Minimum Rise Rate

One integrated power-on reset (POR) circuits monitoring VDDIO requires a minimum rise rate.

7.2.4.3 Maximum Rise Rate

The rise rate of the power supplies must not exceed the values described in Electrical Characteristics.

7.3 Power-Up

This section summarizes the power-up sequence of the SAM L22. The behavior after power-up is controlled by the Power Manager.

7.3.1 Starting of Internal Regulator

After power-up, the device is set to its initial state and kept in Reset, until the power has stabilized throughout the device. The default performance level after power-up is PL0. The internal regulator provides the internal VDDCORE corresponding to this performance level. Once the external voltage VDDIO and the internal VDDCORE reach a stable value, the internal Reset is released.

7.3.2 Starting of Clocks

Once the power has stabilized and the internal Reset is released, the device will use a 4MHz clock by default. The clock source for this clock signal is OSC16M, which is enabled and configured at 4MHz after a reset by default. This is also the default time base for Generic Clock Generator 0. In turn, Generator 0 provides the main clock GCLK_MAIN which is used by the Power Manager (PM). Some synchronous system clocks are active after Start-Up, allowing software execution. Refer to the “Clock Mask Register” section in the PM-Power Manager documentation for the list of clocks that are running by default. Synchronous system clocks that are running receive the 4MHz clock from Generic Clock Generator 0. Other generic clocks are disabled.

7.3.3 I/O Pins

After power-up, the I/O pins are tri-stated except PA30, which is pull-up enabled and configured as input.

7.3.4 Fetching of Initial Instructions

After Reset has been released, the CPU starts fetching PC and SP values from the Reset address, 0x00000000. This points to the first executable address in the internal Flash memory. The code read from the internal Flash can be used to configure the clock system and clock sources. See the related peripheral documentation for details. Refer to the ARM Architecture Reference Manual for more information on CPU startup (www.arm.com).

7.4 Power-On Reset and Brown-Out Detector

The SAM L22 embeds three features to monitor, warn and/or reset the device:

POR: Power-on Reset on VSWOUT and VDDIO
BOD33: Brown-out detector on VSWOUT/VBAT
Brown-out detector internal to the voltage regulator for VDDCORE. BOD12 is calibrated in production and its calibration parameters are stored in the NVM User Row. This data should not be changed if the User Row is written to in order to assure correct behavior.

7.4.1 Power-On Reset on VSWOUT

VSWOUT is monitored by POR. Monitoring is always activated, including startup and all sleep modes. If VSWOUT goes below the threshold voltage, the entire chip is reset.

7.4.2 Power-On Reset on VDDIO

VDDIO is monitored by POR. Monitoring is always activated, including startup and all sleep modes. If VDDIO goes below the threshold voltage, all I/Os supplied by VDDIO are reset. SAM L22 Family Power Supply and Start-Up ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 35

7.4.3 Brown-Out Detector on VSWOUT/VBAT

BOD33 monitors VSWOUT or VBAT depending on configuration.

7.4.4 Brown-Out Detector on VDDCORE

Once the device has started up, BOD12 monitors the internal VDDCORE.

7.5 Performance Level Overview

By default, the device will start in Performance Level 0. This PL0 is aiming for the lowest power consumption by limiting logic speeds and the CPU frequency. As a consequence, all GCLK will have limited capabilities, and some peripherals and clock sources will not work or with limited capabilities: List of peripherals/clock sources not available in PL0:

USB (limited by logic frequency)
DFLL48M List of peripherals/clock sources with limited capabilities in PL0:
All AHB/APB peripherals are limited by CPU frequency
DPLL96M: may be able to generate 48MHz internally, but the output cannot be used by logic
GCLK: the maximum frequency is by factor 4 compared to PL2
SW interface: the maximum frequency is by factor 4 compared to PL2
TC: the maximum frequency is by factor 4 compared to PL2
TCC:the maximum frequency is by factor 4 compared to PL2
SERCOM: the maximum frequency is by factor 4 compared to PL2 List of peripherals/clock sources with full capabilities in PL0:
AC
ADC
EIC
OPAMP
OSC16M
PTC
All 32KHz clock sources and peripherals Full functionality and capability will be ensured in PL2. When transitioning between performance levels, the Supply Controller (SUPC) will provide a configurable smooth voltage scaling transition. SAM L22 Family Power Supply and Start-Up ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 36

Product Mapping Figure 8-1. SAM L22 Product Mapping 0x00000000 Code 0x20000000 SRAM Reserved 0x20008000 0x40000000 Peripherals 0x60000000 Undefined 0x80000000 System 0xE0000000 0xFFFFFFFF 0x00000000 Internal 0x00040000 Reserved 0x1FFFFFFF Flash Global Memory Space Code 0x40000000 AHB-APB Peripherals Bridge A 0x41000000 AHB-APB Bridge B 0x42000000 AHB-APB Bridge C 0x40000000 PAC PM MCLK RSTC OSCTRL OSC32KCTRL SUPC GCLK WDT RTC EIC FREQM Reserved AHB-APB Bridge A 0x40000400 0x40000800 0x40000C00 0x40001000 0x40001400 0x40001800 0x40001C00 0x40002000 0x40002400 0x40002800 0x40002C00 0x40003000 0x41000000 USB DSU NVMCTRL PORT DMAC MTB HMATRIXHS AHB-APB Bridge B 0x41002000 0x40004000 0x40006000 0x40008000 0x4000A000 0x4000C000 0x42000000 EVSYS SERCOM0 SERCOM1 SERCOM2 SERCOM3 SERCOM4 SERCOM5 TCC0 TC0 TC1 TC2 TC3 ADC PTC SLCD AES TRNG CCL Reserved AHB-APB Bridge C 0x42000400 0x42000800 0x42000C00 0x42001000 0x42001400 0x42001800 0x42001C00 0x42002000 0x42002400 0x42002800 0x42002C00 0x42003000 0x42003800 0x42003C00 0x42004000 0x42004400 0x42004800 0x42004C00 0x40FFFFFF Reserved SAM L22 Family Product Mapping © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 37

Memories

9.1 Embedded Memories

Internal high-speed Flash with Read-While-Write (RWW) capability on a section of the array
Internal high-speed RAM, single-cycle access at full speed

9.2 Physical Memory Map

The high-speed bus is implemented as a bus matrix. All high-speed bus addresses are fixed, and they are never remapped in any way, even during boot. The 32-bit physical address space is mapped as follows: Table 9-1. SAM L22 Physical Memory Map Memory Start address Size [KB] SAML22x18(1) SAML22x17(1) SAML22x16(1) Embedded Flash 0x00000000 256 128 64 Embedded RWW section 0x00400000 8 4 2 Embedded SRAM 0x20000000 32 16 8 Peripheral Bridge A 0x40000000 64 64 64 Peripheral Bridge B 0x41000000 64 64 64 Peripheral Bridge C 0x42000000 64 64 64 IOBUS 0x60000000 0.5 0.5 0.5 Note: 1. x = G, J, or N. Table 9-2. Flash Memory Parameters Device Flash size [KB] Number of pages Page size [Bytes] SAML22x18(1) 256 4096 64 SAML22x17(1) 128 2048 64 SAML22x16(1) 64 1024 64 Note: 1. x = G, J, or N. Table 9-3. RWW Section Parameters(1) Device Flash size [KB] Number of pages Page size [Bytes] SAML22x18(1) 8 128 64 SAML22x17(1) 4 64 64 SAML22x16(1) 2 32 64 Note: 1. x = G, J, or N.

9.3 NVM User Row Mapping

The Non Volatile Memory (NVM) User Row contains calibration data that are automatically read at device power-on. SAM L22 Family Memories © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 38

The NVM User Row can be read at address 0x00804000. To write the NVM User Row refer to the documentation of the NVMCTRL - Non-Volatile Memory Controller. Note: When writing to the User Row, the new values do not get loaded by the other peripherals on the device until a device Reset occurs. Table 9-4. NVM User Row Mapping Bit Pos. Name Usage Factory Setting Related Peripheral Register 2:0 BOOTPROT Used to select one of eight different bootloader sizes. 0x7 NVMCTRL

3 Reserved — 0x1 —

6:4 EEPROM Used to select one of eight different EEPROM sizes. 0x7 NVMCTRL

7 Reserved — 0x1 —

13:8 BOD33 Level BOD33 threshold level at power-on. 0x06 SUPC.BOD33 14 BOD33 Disable BOD33 Disable at power-on. 0x0 SUPC.BOD33 16:15 BOD33 Action BOD33 Action at power-on. 0x1 SUPC.BOD33 25:17 Reserved Factory settings - do not change. 0x08F - 26 WDT Enable WDT Enable at power-on. 0x0 WDT.CTRLA 27 WDT Always-On WDT Always-On at power-on. 0x0 WDT.CTRLA 31:28 WDT Period WDT Period at power-on. 0xB WDT.CONFIG 35:32 WDT Window WDT Window mode time-out at power-on. 0xB WDT.CONFIG 39:36 WDT EWOFFSET WDT Early Warning Interrupt Time Offset at power-on. 0xB WDT.EWCTRL

40 WDT WEN WDT Timer Window Mode Enable at

power-on. 0x0 WDT.CTRLA

41 BOD33 Hysteresis BOD33 Hysteresis configuration at power-

on. 0x0 SUPC.BOD33 47:42 Reserved Factory settings - do not change. 0x3E — 63:48 LOCK NVM Region Lock Bits. 0xFFFF NVMCTRL

9.4 NVM Software Calibration Area Mapping

The NVM Software Calibration Area contains calibration data that are determined and written during production test. These calibration values should be read by the application software and written back to the corresponding register. The NVM Software Calibration Area can be read at address 0x00806020. The NVM Software Calibration Area can not be written. Table 9-5. NVM Software Calibration Area Mapping Bit Position Name Description 2:0 ADC BIASREFBUF ADC Bias Reference Buffer Scaling. Must be written to ADC CALIB.BIASREFBUF. 5:3 ADC BIASCOMP ADC Bias Comparator Scaling. Must be written to ADC CALIB.BIASCOMP. SAM L22 Family Memories © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 39

Bit Position Name Description 12:6 Reserved Reserved for future use. 17:13 USB TRANSN USB TRANSN calibration value. Should be written to the USB PADCAL register. 22:18 USB TRANSP USB TRANSP calibration value. Should be written to the USB PADCAL register. 25:23 USB TRIM USB TRIM calibration value. Should be written to the USB PADCAL register. 31:26 DFLL48M COARSE CAL DFLL48M Coarse calibration value. Should be written to the OSCCTRL DFLLVAL register.

9.5 Serial Number

Each device has a unique 128-bit serial number which is a concatenation of four 32-bit words contained at the following addresses: Word 0: 0x0080A00C Word 1: 0x0080A040 Word 2: 0x0080A044 Word 3: 0x0080A048 The uniqueness of the serial number is guaranteed only when using all 128 bits. SAM L22 Family Memories © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 40

Processor and Architecture

10.1 Cortex M0+ Processor

The SAM L22 devices implement the Arm®Cortex®-M0+ processor, based on the ARMv6 Architecture and Thumb®-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0 core, and upward compatible to Cortex-M3 and M4 cores. The implemented Arm Cortex-M0+ is revision r0p1. For additional information, refer to www.arm.com.

10.1.1 Cortex M0+ Configuration

Table 10-1. Cortex M0+ Configuration Features Cortex-M0+ options SAM L22 configuration Interrupts External interrupts 0-32 27 Data endianness Little-endian or big-endian Little-endian SysTick timer Present or absent Present Number of watchpoint comparators 0, 1, 2 2 Number of breakpoint comparators 0, 1, 2, 3, 4 4 Halting debug support Present or absent Present Multiplier Fast or small Fast (single cycle) Single-cycle I/O port Present or absent Present Wake-up interrupt controller Supported or not supported Not supported Vector Table Offset Register Present or absent Present Unprivileged/Privileged support Present or absent Present Memory Protection Unit Not present or 8-region 8-region Reset all registers Present or absent Absent Instruction fetch width 16-bit only or mostly 32-bit 32-bit The Arm Cortex-M0+ core has the following bus interfaces:

Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all system memory, which includes Flash and RAM.
Single 32-bit I/O port bus interfacing to the PORT and DIVAS with 1-cycle loads and stores.

10.1.2 Cortex M0+ Peripherals

System Control Space (SCS) – The processor provides debug through registers in the SCS. Refer to the Cortex-M0+ Technical Reference Manual for details (www.arm.com)
Nested Vectored Interrupt Controller (NVIC) – External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software can set the priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely coupled, providing low latency interrupt processing and efficient processing of late arriving interrupts. Refer to NVIC-Nested Vector Interrupt Controller and the Cortex-M0+ Technical Reference Manual for details (www.arm.com). Note: When the CPU frequency is much higher than the APB frequency it is recommended to insert a memory read barrier after each CPU write to registers mapped on the APB. Failing to do so in such conditions may lead to unexpected behavior such as e.g. re-entering a peripheral interrupt handler just after leaving it. SAM L22 Family Processor and Architecture © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 41

System Timer (SysTick) – The System Timer is a 24-bit timer clocked by CLK_CPU that extends the functionality of both the processor and the NVIC. Refer to the Cortex-M0+ Technical Reference Manual for details (www.arm.com).
System Control Block (SCB) – The System Control Block provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions. Refer to the Cortex-M0+ Devices Generic User Guide for details (www.arm.com).
Micro Trace Buffer (MTB) – The CoreSight MTB-M0+ (MTB) provides a simple execution trace capability to the Cortex-M0+ processor. Refer to section MTB-Micro Trace Buffer and the CoreSight MTB-M0+ Technical Reference Manual for details (www.arm.com).
Memory Protection Unit (MPU) – The Memory Protection Unit divides the memory map into a number of regions, and defines the location, size, access permissions and memory attributes of each region. Refer to the Cortex-M0+ Devices Generic User Guide for details (www.arm.com)

10.1.3 Cortex M0+ Address Map

Table 10-2. Cortex-M0+ Address Map Address Peripheral 0xE000E000 System Control Space (SCS) 0xE000E010 System Timer (SysTick) 0xE000E100 Nested Vectored Interrupt Controller (NVIC) 0xE000ED00 System Control Block (SCB) 0xE000ED90 Memory Protection Unit (MPU) 0x41006000 Micro Trace Buffer (MTB)

10.1.4 I/O Interface

The device allows direct access to PORT registers. Accesses to the AMBA® AHB-Lite™ and the single cycle I/O interface can be made concurrently, so the Cortex M0+ processor can fetch the next instructions while accessing the I/Os. This enables single cycle I/O access to be sustained for as long as necessary.

10.2 Nested Vector Interrupt Controller

10.2.1 Overview

The Nested Vectored Interrupt Controller (NVIC) in the SAM L22 supports 32 interrupts with four different priority levels. For more details, refer to the Cortex-M0+ Technical Reference Manual (www.arm.com).

10.2.2 Interrupt Line Mapping

Each of the interrupt lines is connected to one peripheral instance, as shown in the table below. Each peripheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register. An interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by writing a '1' to the corresponding bit in the peripheral’s Interrupt Enable Set (INTENSET) register, and disabled by writing '1' to the corresponding bit in the peripheral’s Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt requests for one peripheral are ORed together on system level, generating one interrupt request for each peripheral. An interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending registers (SETPEND/CLRPEND bits in ISPR/ICPR). SAM L22 Family Processor and Architecture © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 42

For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for each interrupt. Table 10-3. Interrupt Line Mapping Peripheral source NVIC line EIC NMI – External Interrupt Controller NMI PM – Power Manager MCLK - Main Clock OSCCTRL - Oscillators Controller OSC32KCTRL - 32KHz Oscillators Controller PAC - Peripheral Access Controller SUPC - Supply Controller WDT – Watchdog Timer 1 RTC – Real Time Counter 2 EIC – External Interrupt Controller 3 FREQM - Frequency Meter 4 USB - Universal Serial Bus 5 NVMCTRL – Non-Volatile Memory Controller 6 DMAC - Direct Memory Access Controller 7 EVSYS – Event System 8 SERCOM0 – Serial Communication Interface 0 9 SERCOM1 – Serial Communication Interface 1 10 SERCOM2 – Serial Communication Interface 2 11 SERCOM3 – Serial Communication Interface 3 12 SERCOM4 – Serial Communication Interface 4 13 SERCOM5 – Serial Communication Interface 5 14 TCC0 – Timer Counter for Control 0 15 TC0 – Timer Counter 0 16 TC1 – Timer Counter 1 17 TC2 – Timer Counter 2 18 TC3 – Timer Counter 3 19 ADC – Analog-to-Digital Converter 20 AC – Analog Comparator 21 PTC – Peripheral Touch Controller 22 SLCD - Segmented LCD Controller 23 AES - Advanced Encryption Standard module 24 TRNG - True Random Number Generator 25 SAM L22 Family Processor and Architecture © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 43

10.3 Micro Trace Buffer

10.3.1 Features

Program flow tracing for the Cortex-M0+ processor
MTB SRAM can be used for both trace and general purpose storage by the processor
The position and size of the trace buffer in SRAM is configurable by software
CoreSight compliant

10.3.2 Overview

When enabled, the MTB records the changes in program flow that are reported by the Cortex-M0+ processor over the execution trace interface. This interface is shared between the Cortex-M0+ processor and the CoreSight MTB-M0+. The information is stored by the MTB in the SRAM as trace packets. An off-chip debugger can extract the trace information using the Debug Access Port to read the trace information from the SRAM. The debugger can then reconstruct the program flow from this information. The MTB stores trace information into the SRAM and gives the processor access to the SRAM simultaneously. The MTB ensures that trace write accesses have priority over processor accesses. An execution trace packet consists of a pair of 32-bit words that the MTB generates when it detects a non-sequential change of the program pounter (PC) value. A non-sequential PC change can occur during branch instructions or during exception entry. See the CoreSight MTB-M0+ Technical Reference Manual for more details on the MTB execution trace packet format. Tracing is enabled when the MASTER.EN bit in the Host Trace Control Register is 1. There are various ways to set the bit to 1 to start tracing, or to 0 to stop tracing. See the CoreSight Cortex-M0+ Technical Reference Manual for more details on the Trace start and stop and for a detailed description of the MTB’s MASTER register. The MTB can be programmed to stop tracing automatically when the memory fills to a specified watermark level or to start or stop tracing by writing directly to the MASTER.EN bit. If the watermark mechanism is not being used and the trace buffer overflows, then the buffer wraps around overwriting previous trace packets. The base address of the MTB registers is 0x41006000; this address is also written in the CoreSight ROM Table. The offset of each register from the base address is fixed and as defined by the CoreSight MTB-M0+ Technical Reference Manual. The MTB has four programmable registers to control the behavior of the trace features:

POSITION: Contains the trace write pointer and the wrap bit
MASTER: Contains the main trace enable bit and other trace control fields
FLOW: Contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits
BASE: Indicates where the SRAM is located in the processor memory map. This register is provided to enable auto discovery of the MTB SRAM location by a debug agent See the CoreSight MTB-M0+ Technical Reference Manual for a detailed description of these registers.

10.4 High-Speed Bus System

10.4.1 Overview

10.4.2 Features

High-Speed Bus Matrix has the following features:

Symmetric crossbar bus switch implementation
Allows concurrent accesses from different Hosts to different Clients
32-bit data bus
Operation at a one-to-one clock frequency with the bus Hosts SAM L22 Family Processor and Architecture © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 44

10.4.3 Configuration

Figure 10-1. Host-Client Relations High-Speed Bus Matrix CM0+ 0 DSU 1 High-Speed Bus CLIENTS Internal Flash AHB-APB Bridge A AHB-APB Bridge B AHB-APB Bridge C Multi-Client HOSTS CM0+ DSU SRAM DSU 1 DSU 40 1 2 3 65 CLIENT ID SRAM PORT ID HOST ID DMAC Data 2 DMAC Data DMAC Fetch 0 DMAC Fetch 1 DMAC WB 0 DMAC WB 1 MTB USB 7 8 4 5 1 DMAC Fetch 0 DSU Privileged SRAM-access HOSTS DMAC Fetch 1 DSUDMAC WB 0 DMAC WB 1 DSUUSB DSUMTB Table 10-4. High Speed Bus Matrix Hosts High-Speed Bus Matrix Hosts Host ID CM0+ - Cortex M0+ Processor 0 DSU - Device Service Unit 1 DMAC - Direct Memory Access Controller / Data Access 2 Table 10-5. High-Speed Bus Matrix Clients High-Speed Bus Matrix Clients Client ID Internal Flash Memory 0 SRAM Port 0 - CM0+ Access 1 SRAM Port 1 - DSU Access 2 AHB-APB Bridge B 3 AHB-APB Bridge A 4 AHB-APB Bridge C 5 SAM L22 Family Processor and Architecture © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 45

High-Speed Bus Matrix Clients Client ID SRAM Port 2 - DMAC Data Access 6

10.4.4 SRAM Quality of Service

To ensure that Hosts with latency requirements get sufficient priority when accessing RAM, priority levels can be assigned to the Hosts for different types of access. The Quality of Service (QoS) level is independently selected for each Host accessing the RAM. For any access to the RAM, the RAM also receives the QoS level. The QoS levels and their corresponding bit values for the QoS level configuration is shown in the table below. Table 10-6. Quality of Service Value Name Description 0x0 DISABLE Background (no sensitive operation) 0x1 LOW Sensitive Bandwidth 0x2 MEDIUM Sensitive Latency 0x3 HIGH Critical Latency If a Host is configured with QoS level DISABLE (0x0) or LOW (0x1) there will be a minimum latency of one cycle for the RAM access. The priority order for concurrent accesses are decided by two factors. First, the QoS level for the Host and second, a static priority given by the port ID. The lowest port ID has the highest static priority. See the tables below for details. The MTB has a fixed QoS level HIGH (0x3). The CPU QoS level can be written/read, using 32-bit access only, at address 0x4100C114, bits [1:0]. Its reset value is 0x3. Refer to different Host QOSCTRL registers for configuring QoS for the other Hosts (USB, DMAC). Table 10-7. SRAM Port Connections QoS SRAM Port Connection Port ID Connection Type QoS default QoS CM0+ - Cortex M0+ Processor

0 Bus Matrix 0x4100C114, bits[1:0]

(1) 0x3 DSU - Device Service Unit

1 Bus Matrix 0x4100201C,

bits1:0 0x2 DMAC - Direct Memory Access Controller - Data Access 2 Bus Matrix IP-QOSCTRL.DQOS 0x2 DMAC - Direct Memory Access Controller - Fetch Access 3, 4 Direct IP-QOSCTRL.FQOS 0x2 DMAC - Direct Memory Access Controller - Write- Back Access 5, 6 Direct IP- QOSCTRL.WRBQO S 0x2 SAM L22 Family Processor and Architecture © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 46

Port ID Connection Type QoS default QoS USB - Universal Serial Bus

7 Direct IP-QOSCTRL 0x3

8 Direct STATIC-3 0x3

PAC - Peripheral Access Controller

11.1 Overview

The Peripheral Access Controller provides an interface for the locking and unlocking of peripheral registers within the device. It reports all violations that could happen when accessing a peripheral: write protected access, illegal access, enable protected access, access when clock synchronization or software reset is on-going. These errors are reported in a unique interrupt flag for a peripheral. The PAC module also reports errors occurring at the client bus level, when an access to a non-existing address is detected.

11.2 Features

Manages write protection access and reports access errors for the peripheral modules or bridges

11.3 Block Diagram

Figure 11-1. PAC Block Diagram INTFLAG PERIPHERAL m PERIPHERAL 0 BUSn BUS0 Peripheral ERROR Peripheral ERROR WRITE CONTROL WRITE CONTROL PAC CONTROL PERIPHERAL m PERIPHERAL 0 CLIENTs PAC IRQ APB Client ERROR

11.4 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

11.4.1 I/O Lines

Not applicable.

11.4.2 Power Management

The PAC can continue to operate in any sleep mode where the selected source clock is running. The PAC interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes. References: PM - Power Manager SAM L22 Family PAC - Peripheral Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 48

11.4.3 Clocks

The PAC bus clock (CLK_PAC_APB) can be enabled and disabled in the Main Clock module. The default state of CLK_PAC_APB can be found in the referenced links. References: MCLK - Main Clock Peripheral Clock Masking

11.4.4 DMA

Not applicable.

11.4.5 Interrupts

The interrupt request line is connected to the Interrupt Controller. Using the PAC interrupt requires the Interrupt Controller to be configured first. Refer to the Nested Vector Interrupt Controller for more details. Table 11-1. Interrupt Lines Instances NVIC Line PAC PACERR

11.4.6 Events

The events are connected to the Event System, which may need configuration. References: 29. EVSYS – Event System

11.4.7 Debug Operation

When the CPU is halted in debug mode, write protection of all peripherals is disabled and the PAC continues normal operation.

11.4.8 Register Access Protection

All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Write Control (WRCTRL) register
AHB Client Bus Interrupt Flag Status and Clear (INTFLAGAHB) register
Peripheral Interrupt Flag Status and Clear n (INTFLAG A/B/C...) registers Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger.

11.5 Functional Description

11.5.1 Principle of Operation

The Peripheral Access Control module allows the user to set a write protection on peripheral modules and generate an interrupt in case of a peripheral access violation. The peripheral’s protection can be set, cleared or locked at the user discretion. A set of Interrupt Flag and Status registers informs the user on the status of the violation in the peripherals. In addition, clients bus errors can be also reported in the cases where reserved area is accessed by the application.

11.5.2 Basic Operation

11.5.2.1 Initialization

11.5.2.2 Enabling and Resetting

The PAC is always enabled after reset. Only a hardware reset will reset the PAC module.

11.5.2.3 Operations

The PAC module allows the user to set, clear or lock the write protection status of all peripherals on all Peripheral Bridges. If a peripheral register violation occurs, the Peripheral Interrupt Flag n registers (INTFLAGn) are updated to inform the user on the status of the violation in the peripherals connected to the Peripheral Bridge n (n = A,B,C ...). The corresponding Peripheral Write Control Status n register (STATUSn) gives the state of the write protection for all details. The PAC module also reports the errors occurring at client bus level when an access to reserved area is detected. AHB Client Bus Interrupt Flag register (INTFLAGAHB) informs the user on the status of the violation in the

11.5.2.4 Peripheral Access Errors

The following events will generate a Peripheral Access Error:

Protected write: To avoid unexpected writes to a peripheral's registers, each peripheral can be write protected. Only the registers denoted as “PAC Write-Protection” in the module’s data sheet can be protected. If a peripheral is not write protected, write data accesses are performed normally. If a peripheral is write protected and if a write access is attempted, data will not be written and peripheral returns an access error. The corresponding interrupt flag bit in the INTFLAGn register will be set.
Illegal access: Access to an unimplemented register within the module.
Synchronized write error: For write-synchronized registers an error will be reported if the register is written while a synchronization is ongoing. When any of the INTFLAGn registers bit are set, an interrupt will be requested if the PAC interrupt enable bit is set. References: Register Synchronization

11.5.2.5 Write Access Protection Management

Peripheral access control can be enabled or disabled by writing to the WRCTRL register. The data written to the WRCTRL register is composed of two fields; WRCTRL.PERID and WRCTRL.KEY. The WRCTRL.PERID is an unique identifier corresponding to a peripheral. The WRCTRL.KEY is a key value that defines the operation to be done on the control access bit. These operations can be “clear protection”, “set protection” and “set and lock protection bit”. The “clear protection” operation will remove the write access protection for the peripheral selected by WRCTRL.PERID. Write accesses are allowed for the registers in this peripheral. The “set protection” operation will set the write access protection for the peripheral selected by WRCTRL.PERID. Write accesses are not allowed for the registers with write protection property in this peripheral. The "set and lock protection" operation will permanently set the write access protection for the peripheral selected by WRCTRL.PERID. The write access protection will only be cleared by a hardware reset. The peripheral access control status can be read from the corresponding STATUSn register.

11.5.2.6 Write Access Protection Management Errors

Only word-wise writes to the WRCTRL register will effectively change the access protection. Other type of accesses will have no effect and will cause a PAC write access error. This error is reported in the INTFLAGn.PAC bit corresponding to the PAC module. PAC also offers an additional safety feature for correct program execution with an interrupt generated on double write clear protection or double write set protection. If a peripheral is write protected and a subsequent set protection operation is detected then the PAC returns an error, and similarly for a double clear protection operation. SAM L22 Family PAC - Peripheral Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 50

In addition, an error is generated when writing a “set and lock” protection to a write-protected peripheral or when a write access is done to a locked set protection. This can be used to ensure that the application follows the intended program flow by always following a write protect with an unprotect and conversely. However in applications where a write protected peripheral is used in several contexts, e.g. interrupt, care should be taken so that either the interrupt can not happen while the main application or other interrupt levels manipulates the write protection status or when the interrupt handler needs to unprotect the peripheral based on the current protection status by reading the STATUS register. The errors generated while accessing the PAC module registers (eg. key error, double protect error...) will set the INTFLAGn.PAC flag.

11.5.2.7 AHB Client Bus Errors

The PAC module reports errors occurring at the AHB Client bus level. These errors are generated when an access is performed at an address where no Client (bridge or peripheral) is mapped . These errors are reported in the corresponding bits of the INTFLAGAHB register.

11.5.2.8 Generating Events

The PAC module can also generate an event when any of the Interrupt Flag registers bit are set. To enable the PAC event generation, the control bit EVCTRL.ERREO must be set to '1'.

11.5.3 DMA Operation

Not applicable.

11.5.4 Interrupts

The PAC has the following interrupt source:

Error (ERR): Indicates that a peripheral access violation occurred in one of the peripherals controlled by the PAC module, or a bridge error occurred in one of the bridges reported by the PAC – This interrupt is a synchronous wake-up source. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAGAHB and INTFLAGn) registers is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the PAC is reset. All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. The user must read the INTFLAGAHB and INTFLAGn registers to determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be generated. References: Sleep Mode Controller Nested Vector Interrupt Controller

11.5.5 Events

The PAC can generate the following output event:

Error (ERR): Generated when one of the interrupt flag registers bits is set Writing a '1' to an Event Output bit in the Event Control Register (EVCTRL.ERREO) enables the corresponding output event. Writing a '0' to this bit disables the corresponding output event. References: 29. EVSYS – Event System

11.5.6 Sleep Mode Operation

In Sleep mode, the PAC is kept enabled if an available host (CPU, DMA) is running. The PAC will continue to catch access errors from the module and generate interrupts or events. SAM L22 Family PAC - Peripheral Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 51

11.5.7 Synchronization

11.6 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 WRCTRL 7:0 PERID[7:0] 15:8 PERID[15:8] 23:16 KEY[7:0] 31:24 0x04 EVCTRL 7:0 ERREO 0x05 ... 0x07 Reserved 0x08 INTENCLR 7:0 ERR 0x09 INTENSET 7:0 ERR 0x0A ... 0x0F Reserved 0x10 INTFLAGAHB 7:0 HSRAMDMA C HPB2 HPB0 HPB1 HSRAMDSU HSRAMCM0P FLASH 15:8 23:16 31:24 0x14 INTFLAGA 7:0 GCLK SUPC OSC32KCTR L OSCCTRL RSTC MCLK PM PAC 15:8 FREQM EIC RTC WDT 23:16 31:24 0x18 INTFLAGB 7:0 MTB DMAC PORT NVMCTRL DSU USB 15:8 23:16 31:24 0x1C INTFLAGC 7:0 TCC0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS 15:8 SLCD PTC AC ADC TC3 TC2 TC1 TC0 23:16 CCL TRNG AES 31:24 0x20 ... 0x33 Reserved 0x34 STATUSA 7:0 GCLK SUPC OSC32KCTR L OSCCTRL RSTC MCLK PM PAC 15:8 FREQM EIC RTC WDT 23:16 31:24 0x38 STATUSB 7:0 MTB DMAC PORT NVMCTRL DSU USB 15:8 23:16 31:24 0x3C STATUSC 7:0 TCC0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS 15:8 SLCD PTC AC ADC TC3 TC2 TC1 TC0 23:16 CCL TRNG AES 31:24

11.7 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. SAM L22 Family PAC - Peripheral Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 53

Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write- protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to the Register Synchronization chapter. SAM L22 Family PAC - Peripheral Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 54

11.7.1 Write Control

Name: WRCTRL Offset: 0x00 Reset: 0x00000000 Property: – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 KEY[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 PERID[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PERID[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 23:16 – KEY[7:0] Peripheral Access Control Key These bits define the peripheral access control key: Value Name Description 0x0 OFF No action 0x1 CLR Clear the peripheral write control 0x2 SET Set the peripheral write control 0x3 SETLCK Set and lock the peripheral write control until the next hardware reset Bits 15:0 – PERID[15:0] Peripheral Identifier The PERID represents the peripheral whose control is changed using the WRCTRL.KEY. The Peripheral Identifier is calculated following formula: PE RI D = 32* BridgeNumber + N Where BridgeNumber represents the Peripheral Bridge Number (0 for Peripheral Bridge A, 1 for Peripheral Bridge B, etc). N represents the peripheral index from the respective Bridge Number: Table 11-2. PERID Values Periph. Bridge Name BridgeNumber PERID Values A 0 0+N B 1 32+N C 2 64+N D 3 96+N E 4 128+N SAM L22 Family PAC - Peripheral Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 55

11.7.2 Event Control

Name: EVCTRL Offset: 0x04 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 ERREO Access R/W Reset 0 Bit 0 – ERREO Peripheral Access Error Event Output This bit indicates if the Peripheral Access Error Event Output is enabled or disabled. When enabled, an event will be generated when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set: Value Description 0 Peripheral Access Error Event Output is disabled. 1 Peripheral Access Error Event Output is enabled. SAM L22 Family PAC - Peripheral Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 56

11.7.3 Interrupt Enable Clear

Name: INTENCLR Offset: 0x08 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 5 4 3 2 1 0 ERR Access R/W Reset 0 Bit 0 – ERR Peripheral Access Error Interrupt Disable This bit indicates that the Peripheral Access Error Interrupt is disabled and an interrupt request will be generated when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set: Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Peripheral Access Error interrupt Enable bit and disables the corresponding interrupt request. Value Description 0 Peripheral Access Error interrupt is disabled. 1 Peripheral Access Error interrupt is enabled. SAM L22 Family PAC - Peripheral Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 57

11.7.4 Interrupt Enable Set

Name: INTENSET Offset: 0x09 Reset: 0x00 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENCLR). Bit 7 6 5 4 3 2 1 0 ERR Access R/W Reset 0 Bit 0 – ERR Peripheral Access Error Interrupt Enable This bit indicates that the Peripheral Access Error Interrupt is enabled and an interrupt request will be generated when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set: Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Peripheral Access Error interrupt Enable bit and enables the corresponding interrupt request. Value Description 0 Peripheral Access Error interrupt is disabled. 1 Peripheral Access Error interrupt is enabled. SAM L22 Family PAC - Peripheral Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 58

11.7.5 AHB Client Bus Interrupt Flag Status and Clear

Name: INTFLAGAHB Offset: 0x10 Reset: 0x00000000 Property: – This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the CLIENT n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 HSRAMDMAC HPB2 HPB0 HPB1 HSRAMDSU HSRAMCM0P FLASH Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 6 – HSRAMDMAC Interrupt Flag for CLIENT HSRAMDMAC Bit 5 – HPB2 Interrupt Flag for CLIENT HPB2 Bit 4 – HPB0 Interrupt Flag for CLIENT HPB0 Bit 3 – HPB1 Interrupt Flag for CLIENT HPB1 Bit 2 – HSRAMDSU Interrupt Flag for CLIENT HSRAMDSU Bit 1 – HSRAMCM0P Interrupt Flag for CLIENT HSRAMCM0P Bit 0 – FLASH Interrupt Flag for CLIENT FLASH SAM L22 Family PAC - Peripheral Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 59

11.7.6 Peripheral Interrupt Flag Status and Clear A

Name: INTFLAGA Offset: 0x14 Reset: 0x00000000 Property: – This flag is cleared by writing a one to the flag. This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGA bit, and will generate an interrupt request if INTENCLR/SET.ERR is one. Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding INTFLAGA interrupt flag. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 FREQM EIC RTC WDT Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GCLK SUPC OSC32KCTRL OSCCTRL RSTC MCLK PM PAC Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 11 – FREQM Interrupt Flag for FREQM Bit 10 – EIC Interrupt Flag for EIC Bit 9 – RTC Interrupt Flag for RTC Bit 8 – WDT Interrupt Flag for WDT Bit 7 – GCLK Interrupt Flag for GCLK Bit 6 – SUPC Interrupt Flag for SUPC Bit 5 – OSC32KCTRL Interrupt Flag for OSC32KCTRL Bit 4 – OSCCTRL Interrupt Flag for OSCCTRL Bit 3 – RSTC Interrupt Flag for RSTC Bit 2 – MCLK Interrupt Flag for MCLK Bit 1 – PM Interrupt Flag for PM SAM L22 Family PAC - Peripheral Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 60

11.7.7 Peripheral Interrupt Flag Status and Clear B

Name: INTFLAGB Offset: 0x18 Reset: 0x00000000 Property: – This flag is cleared by writing a '1' to the flag. This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGB bit, and will generate an interrupt request if INTENCLR/SET.ERR is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGB interrupt flag. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 MTB DMAC PORT NVMCTRL DSU USB Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 5 – MTB Interrupt Flag for MTB Bit 4 – DMAC Interrupt Flag for DMAC Bit 3 – PORT Interrupt Flag for PORT Bit 2 – NVMCTRL Interrupt Flag for NVMCTRL Bit 1 – DSU Interrupt Flag for DSU Bit 0 – USB Interrupt Flag for USB SAM L22 Family PAC - Peripheral Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 62

11.7.8 Peripheral Interrupt Flag Status and Clear C

Name: INTFLAGC Offset: 0x1C Reset: 0x00000000 Property: – This flag is cleared by writing a one to the flag. This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGC bit, and will generate an interrupt request if INTENCLR/SET.ERR is one. Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding INTFLAGC interrupt flag. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 CCL TRNG AES Access R/W R/W R/W Reset 0 0 0 Bit 15 14 13 12 11 10 9 8 SLCD PTC AC ADC TC3 TC2 TC1 TC0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TCC0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 18 – CCL Interrupt Flag for CCL Bit 17 – TRNG Interrupt Flag for TRNG Bit 16 – AES Interrupt Flag for AES Bit 15 – SLCD Interrupt Flag for SLCD Bit 14 – PTC Interrupt Flag for PTC Bit 13 – AC Interrupt Flag for AC Bit 12 – ADC Interrupt Flag for ADC Bits 8, 9, 10, 11 – TC Interrupt Flag for TCn [n = 3..0] Bit 7 – TCC0 Interrupt Flag for TCC0 Bits 1, 2, 3, 4, 5, 6 – SERCOM Interrupt Flag for SERCOMn [n = 5..0] Bit 0 – EVSYS Interrupt Flag for EVSYS SAM L22 Family PAC - Peripheral Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 63

11.7.9 Peripheral Write Protection Status A

Name: STATUSA Offset: 0x34 Reset: 0x00000000 Property: – Writing to this register has no effect. Reading STATUS register returns peripheral write protection status: Value Description 0 Peripheral is not write protected. 1 Peripheral is write protected. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 FREQM EIC RTC WDT Access R R R R Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GCLK SUPC OSC32KCTRL OSCCTRL RSTC MCLK PM PAC Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 11 – FREQM Peripheral FREQM Write Protection Status Bit 10 – EIC Peripheral EIC Write Protection Status Bit 9 – RTC Peripheral RTC Write Protection Status Bit 8 – WDT Peripheral WDT Write Protection Status Bit 7 – GCLK Peripheral GCLK Write Protection Status Bit 6 – SUPC Peripheral SUPC Write Protection Status Bit 5 – OSC32KCTRL Peripheral OSC32KCTRL Write Protection Status Bit 4 – OSCCTRL Peripheral OSCCTRL Write Protection Status Bit 3 – RSTC Peripheral RSTC Write Protection Status Bit 2 – MCLK Peripheral MCLK Write Protection Status Bit 1 – PM Peripheral PM Write Protection Status SAM L22 Family PAC - Peripheral Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 64

11.7.10 Peripheral Write Protection Status B

Name: STATUSB Offset: 0x38 Reset: 0x00000000 Property: – Writing to this register has no effect. Reading STATUS register returns peripheral write protection status: Value Description 0 Peripheral is not write protected. 1 Peripheral is write protected. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 MTB DMAC PORT NVMCTRL DSU USB Access R R R R R R Reset 0 0 0 0 0 0 Bit 5 – MTB Peripheral MTB Write Protection Status Bit 4 – DMAC Peripheral DMAC Write Protection Status Bit 3 – PORT Peripheral PORT Write Protection Status Bit 2 – NVMCTRL Peripheral NVMCTRL Write Protection Status Bit 1 – DSU Peripheral DSU Write Protection Status Bit 0 – USB Peripheral USB Write Protection Status SAM L22 Family PAC - Peripheral Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 66

11.7.11 Peripheral Write Protection Status C

Name: STATUSC Offset: 0x3C Reset: 0x00000000 Property: – Writing to this register has no effect. Reading STATUS register returns peripheral write protection status: Value Description 0 Peripheral is not write protected. 1 Peripheral is write protected. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 CCL TRNG AES Access R R R Reset 0 0 0 Bit 15 14 13 12 11 10 9 8 SLCD PTC AC ADC TC3 TC2 TC1 TC0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TCC0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 18 – CCL Peripheral CCL Write Protection Status Bit 17 – TRNG Peripheral TRNG Write Protection Status Bit 16 – AES Peripheral AES Write Protection Status Bit 15 – SLCD Peripheral SLCD Write Protection Status Bit 14 – PTC Peripheral PTC Write Protection Status Bit 13 – AC Peripheral ADC Write Protection Status Bit 12 – ADC Peripheral ADC Write Protection Status Bits 8, 9, 10, 11 – TC Peripheral TCn Write Protection Status [n = 3..0] Bit 7 – TCC0 Peripheral TCC0 Write Protection Status Bits 1, 2, 3, 4, 5, 6 – SERCOM Peripheral SERCOMn Write Protection Status [n = 5..0] Bit 0 – EVSYS Peripheral EVSYS Write Protection Status SAM L22 Family PAC - Peripheral Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 67

Peripherals Configuration Summary Table 12-1. Peripherals Configuration Summary Peripheral name Base address IRQ line AHB clock APB clock Bus Clock Domain Generic Clock PAC Events DMA Power domain Index Enabled at Reset Index Enabled at Reset Name Index Index Prot at Reset User Generator Index Sleep Walking Name AHB-APB Bridge A 0x40000000 — 0 Y — — CPU — — — — — — N/A PDTOP PAC 0x40000000 0 7 Y 0 Y CPU — 0 — — 69 : ACCERR — N/A PDTOP PM 0x40000400 0 — — 1 Y Backup — 1 N — — — N/A PDBACKUP MCLK 0x40000800 0 — — 2 Y CPU — 2 N — — — Y PDTOP RSTC 0x40000C00 — — — 3 Y Backup — 3 N — — — N/A PDBACKUP OSCCTRL 0x40001000 0 — — 4 Y CPU 0: DFLL48M reference 1: FDPLL96M clk source 2: FDPLL96M 32kHz

4 N — 0: CFD — Y PDTOP

OSC32KCTRL 0x40001400 0 — — 5 Y Backup — 5 N — 1: CFD — — PDBACKUP SUPC 0x40001800 0 — — 6 Y Backup — 6 N — — — N/A PDBACKUP GCLK 0x40001C00 — — — 7 Y CPU — 7 N — — — N/A PDTOP WDT 0x40002000 1 — — 8 Y CPU — 8 N — — — Y PDTOP RTC 0x40002400 2 — — 9 Y Backup — 9 N 0: TAMPEVT 2: CMP0/ ALARM0 3: CMP1 4: TAMPER 5: OVF 6-13: PER0-7 1: TIMESTAMP Y PDBACKUP EIC 0x40002800 3, NMI — — 10 Y CPU 3 10 N — 14-29: EXTINT0-15 — Y PDTOP FREQM 0x40002C00 4 — — 11 Y CPU 4: FREQM_MSR 5: FREQM_REF

11 N — 4: DONE — Y PDTOP

AHB-APB Bridge B 0x41000000 — 1 Y — — CPU — — — — — — N/A PDTOP USB 0x41000000 5 4 Y 0 Y CPU 6 0 N — — — Y PDTOP DSU 0x41002000 — 5 Y 1 Y CPU — 1 Y — — — N/A PDTOP NVMCTRL 0x41004000 6 8 Y 2 Y CPU — 2 N — — — Y PDTOP PORT 0x41006000 — — — 10 Y CPU — 3 N 1-4 : EV0-3 — — Y PDTOP DMAC 0x41008000 7 4 Y — — CPU — 4 — 5-8: CH0-4 30-33: CH0-4 — Y PDTOP AHB-APB Bridge C 0x42000000 — 2 Y — — CPU — — — — — — N/A PDTOP EVSYS 0x42000000 8 — — 0 Y CPU 7-14: one per CHANNEL

0 N — — — Y PDTOP

SERCOM0 0x42000400 9 — — 1 Y CPU 16: CORE 15: SLOW

1 N — — 2: RX

SERCOM1 0x42000800 10 — — 2 Y CPU 17: CORE 15: SLOW

2 N — — 4: RX

5: TX Y PDTOP SERCOM2 0x42000A00 11 — — 3 Y CPU 18: CORE 15: SLOW

3 N — — 6: RX

7: TX Y PDTOP SERCOM3 0x42001000 12 — — 4 Y CPU 19: CORE 15: SLOW

4 N — — 8: RX

9: TX Y PDTOP SERCOM4 0x42001400 13 — — 5 Y CPU 20: CORE 15: SLOW

5 N — — 10: RX

11: TX Y PDTOP SERCOM5 0x42001800 14 — — 6 Y CPU 21: CORE 15: SLOW

6 N — — 12: RX

13: TX Y PDTOP TCC0 0x42001C00 15 — — 7 Y CPU 22 7 N 9-10: EV0-1 11-14: MC0-3 34: OVF 35: TRG 36: CNT 37-40: MC0-3 14: OVF 15-18: MC0-3 Y PDTOP TC0 0x42002000 16 — — 8 Y CPU 23 8 N 15: EVU 41: OVF 42-43: MC0-1 19: OVF 20-21: MC0-1 Y PDTOP TC1 0x42002400 17 — — 9 Y CPU 23 9 N 16: EVU 44: OVF 45-46: MC0-1 22: OVF 23-24: MC0-1 Y PDTOP TC2 0x42002800 18 — — 10 Y CPU 24 10 N 17: EVU 47: OVF 48-49: MC0-1 25: OVF 26-27: MC0-1 Y PDTOP TC3 0x42002C00 19 — — 11 Y CPU 24 11 N 18: EVU 50: OVF 51-52: MC0-1 28: OVF 29-30: MC0-1 Y PDTOP ADC 0x42003000 20 — — 12 Y CPU 25 12 N 19: START 20: SYNC 53: RESRDY 54: WINMON 31: RESRDY Y PDTOP AC 0x42003400 21 — — 13 Y CPU 26 13 N 21-22: SOC0-1 55-56: COMP0-1 57: WIN0 — Y PDTOP PTC 0x42003800 22 — — 14 Y CPU 27 14 N 23: STCONV 58: EOC 59: WCOMP — — PDTOP SLCD 0x42003C00 23 — — 15 Y CPU — 15 N — 60-62: FC0-2 63: DT 32: DMU 33: ACMDRDY 34: ABMRDY — PDTOP AES 0x42004000 24 — — 16 Y CPU — 16 N — — 35 : WR 36 : RD Y PDTOP TRNG 0x42004400 25 — — 17 Y CPU — 17 N — 64 : READY — Y PDTOP CCL 0x42004800 — — — 18 Y CPU 28 18 N 24 : LUTIN0 25 : LUTIN1 26: LUTIN2 27: LUTIN3 65 : LUTOUT0 66 : LUTOUT1 67: LUTOUT2 68: LUTOUT3 — Y PDTOP SAM L22 Family Peripherals Configuration Summary © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 69

DSU - Device Service Unit

13.1 Overview

The Device Service Unit (DSU) provides a means of detecting debugger probes. It enables the ARM Debug Access Port (DAP) to have control over multiplexed debug pads and CPU reset. The DSU also provides system-level services to debug adapters in an ARM debug system. It implements a CoreSight Debug ROM that provides device identification as well as identification of other debug components within the system. Hence, it complies with the ARM Peripheral Identification specification. The DSU also provides system services to applications that need memory testing, as required for IEC60730 Class B compliance, for example. The DSU can be accessed simultaneously by a debugger and the CPU, as it is connected on the High-Speed Bus Matrix. For security reasons, some of the DSU features will be limited or unavailable when the device is protected by the NVMCTRL security bit. References: 27. NVMCTRL – Non-Volatile Memory Controller 27.6.6. Security Bit

13.2 Features

CPU reset extension
Debugger probe detection (Cold- and Hot-Plugging)
Chip-Erase command and status
32-bit cyclic redundancy check (CRC32) of any memory accessible through the bus matrix
ARM ® CoreSight™ compliant device identification
Two debug communications channels
Debug access port security filter
Onboard memory built-in self-test (MBIST)

13.3 Block Diagram

Figure 13-1. DSU Block Diagram DSU SWCLK CORESIGHT ROM DAP SECURITY FILTER CRC-32 MBIST CHIP ERASE RESET cpu_reset_extension CPUDAP SWDIO NVMCTRL DBG M HIGH-SPEED BUS MATRIXM S debugger_present DEBUGGER PROBE INTERFACE AHB-AP PORT SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 70

13.4 Signal Description

The DSU uses three signals to function. Signal Name Type Description RESET Digital Input External reset SWCLK Digital Input SW clock SWDIO Digital I/O SW bidirectional data pin References: I/O Multiplexing and Considerations

13.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

13.5.1 IO Lines

The SWCLK pin is by default assigned to the DSU module to allow debugger probe detection and to stretch the CPU on the PORT configuration. If the SWCLK pin function is changed in the PORT or if the PORT_MUX is disabled, the Hot-Plugging feature is disabled until a power-reset or an external reset.

13.5.2 Power Management

The DSU will continue to operate in any sleep mode where the selected source clock is running. References: PM - Power Manager

13.5.3 Clocks

The DSU bus clocks (CLK_DSU_APB and CLK_DSU_AHB) can be enabled and disabled by the Main Clock Controller References: 19. PM - Power Manager 16. MCLK – Main Clock 16.6.2.6. Peripheral Clock Masking

13.5.4 Interrupts

Not applicable.

13.5.5 Events

Not applicable.

13.5.6 Register Access Protection

Registers with write-access can be optionally write-protected by the 11. PAC - Peripheral Access Controller, except for the following:

Debug Communication Channel 0 register (DCC0)
Debug Communication Channel 1 register (DCC1) Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection does not apply for accesses through an external debugger. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 71

13.5.7 Analog Connections

Not applicable.

13.6 Debug Operation

13.6.1 Principle of Operation

The DSU provides basic services to allow on-chip debug using the ARM Debug Access Port and the ARM processor debug resources:

CPU reset extension
Debugger probe detection For more details on the ARM debug components, refer to the ARM Debug Interface v5 Architecture Specification.

13.6.2 CPU Reset Extension

“CPU reset extension” refers to the extension of the reset phase of the CPU core after the external reset is released. This ensures that the CPU is not executing code at startup while a debugger connects to the system. The debugger is detected on a RESET release event when SWCLK is low. At startup, SWCLK is internally pulled up to avoid false detection of a debugger if the SWCLK pin is left unconnected. When the CPU is held in the reset extension phase, the CPU Reset Extension bit of the Status A register (STATUSA.CRSTEXT) is set. To release the CPU, has no effect. For security reasons, it is not possible to release the CPU reset extension when the device is protected by the NVMCTRL security bit. Trying to do so sets the Protection Error bit (PERR) of the Status A register (STATUSA.PERR). Figure 13-2. Typical CPU Reset Extension Set and Clear Timing Diagram DSU CRSTEXT Clear SWCLK CPU reset extension CPU_STATE reset running RESET References: 27.6.6. Security Bit 27. NVMCTRL – Non-Volatile Memory Controller

13.6.3 Debugger Probe Detection

13.6.3.1 Cold Plugging

Cold-Plugging is the detection of a debugger when the system is in reset. Cold-Plugging is detected when the CPU reset extension is requested, as described above.

13.6.3.2 Hot Plugging

Hot-Plugging is the detection of a debugger probe when the system is not in reset. Hot-Plugging is not possible under reset because the detector is reset when POR or RESET are asserted. Hot-Plugging is active when a SWCLK SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 72

falling edge is detected. The SWCLK pad is multiplexed with other functions and the user must ensure that its default function is assigned to the debug system. If the SWCLK function is changed, the Hot-Plugging feature is disabled until a power-reset or external reset occurs. Availability of the Hot-Plugging feature can be read from the Hot-Plugging Enable bit of the Status B register (STATUSB.HPE). Figure 13-3. Hot-Plugging Detection Timing Diagram SWCLK Hot-Plugging CPU_STATE reset running RESET The presence of a debugger probe is detected when either Hot-Plugging or Cold-Plugging is detected. Once detected, the Debugger Present bit of the Status B register (STATUSB.DBGPRES) is set. For security reasons, Hot-Plugging is not available when the device is protected by the NVMCTRL security bit. This detection requires that pads are correctly powered. Thus, at cold startup, this detection cannot be done until POR is released. If the device is protected, Cold-Plugging is the only way to detect a debugger probe, and so the external reset timing must be longer than the POR timing. If external reset is deasserted before POR release, the user must retry the procedure above until it gets connected to the device. References: 27. NVMCTRL – Non-Volatile Memory Controller 27.6.6. Security Bit

13.7 Chip Erase

Chip-Erase consists of removing all sensitive information stored in the chip and clearing the NVMCTRL security bit. Therefore, all volatile memories and the Flash memory (including the EEPROM emulation area) will be erased. The Flash auxiliary rows, including the user row, will not be erased. When the device is protected, the debugger must reset the device in order to be detected. This ensures that internal registers are reset after the protected state is removed. The Chip-Erase operation is triggered by writing a '1' to the Chip-Erase bit in the Control register (CTRL.CE). This command will be discarded if the DSU is protected by the Peripheral Access Controller (PAC). Once issued, the module clears volatile memories prior to erasing the Flash array. To ensure that the Chip-Erase operation is completed, check the Done bit of the Status A register (STATUSA.DONE). The Chip-Erase operation depends on clocks and power management features that can be altered by the CPU. For that reason, it is recommended to issue a Chip- Erase after a Cold-Plugging procedure to ensure that the device is in a known and safe state. The recommended sequence is as follows: a. Detects the debugger probe. b. Holds the CPU in reset. 2. Issue the Chip-Erase command by writing a '1' to CTRL.CE. The device then: a. Clears the system volatile memories. b. Erases the whole Flash array (including the EEPROM emulation area, not including auxiliary rows). c. Erases the lock row, removing the NVMCTRL security bit protection. 3. Check for completion by polling STATUSA.DONE (read as '1' when completed). 4. Reset the device to let the NVMCTRL update the fuses. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 73

13.8 Programming

Programming the Flash or RAM memories is only possible when the device is not protected by the NVMCTRL security bit. The programming procedure is as follows: 1. At power up, RESET is driven low by a debugger. The on-chip regulator holds the system in a POR state until the input supply is above the POR threshold (refer to Power-On Reset (POR) Characteristics). The system continues to be held in this static state until the internally regulated supplies have reached a safe operating state. 2. The PM starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash Clock and any Bus Clocks that do not have clock gate control). Internal resets are maintained due to the external reset. 3. The debugger maintains a low level on SWCLK. RESET is released, resulting in a debugger Cold-Plugging procedure. 4. The debugger generates a clock signal on the SWCLK pin, the Debug Access Port (DAP) receives a clock. 5. The CPU remains in Reset due to the Cold-Plugging procedure; meanwhile, the rest of the system is released. 6. A Chip-Erase is issued to ensure that the Flash is fully erased prior to programming. 7. Programming is available through the AHB-AP. 8. After the operation is completed, the chip can be restarted either by asserting RESET, toggling power, or writing a '1' to the Status A register CPU Reset Phase Extension bit (STATUSA.CRSTEXT). Make sure that the SWCLK pin is high when releasing RESET to prevent extending the CPU reset. References:

Electrical Characteristics

13.9 Intellectual Property Protection

Intellectual property protection consists of restricting access to internal memories from external tools when the device is protected, and this is accomplished by setting the NVMCTRL security bit. This protected state can be removed by issuing a Chip-Erase (refer to 13.7. Chip Erase). When the device is protected, read/write accesses using the AHB-AP are limited to the DSU address range and DSU commands are restricted. When issuing a Chip-Erase, sensitive information is erased from volatile memory and Flash. The DSU implements a security filter that monitors the AHB transactions generated by the ARM AHB-AP inside the DAP. If the device is protected, then AHB-AP read/write accesses outside the DSU external address range are discarded, causing an error response that sets the ARM AHB-AP sticky error bits (refer to the ARM Debug Interface v5 Architecture Specification on www.arm.com). The DSU is intended to be accessed either:

Internally from the CPU, without any limitation, even when the device is protected
Externally from a debug adapter, with some restrictions when the device is protected For security reasons, DSU features have limitations when used from a debug adapter. To differentiate external accesses from internal ones, the first 0x100 bytes of the DSU register map has been replicated at offset 0x100:
The first 0x100 bytes form the internal address range
The next 0x100 bytes form the external address range When the device is protected, the DAP can only issue MEM-AP accesses in the DSU address range limited to the 0x100 - 0x2000 offset range. The DSU operating registers are located in the 0x0000-0x00FF area and remapped in 0x0100-0x01FF to differentiate accesses coming from a debugger and the CPU. If the device is protected and an access is issued in the region 0x0100-0x01FF, it is subject to security restrictions. For more information, refer to the Feature Availability Under Protection table. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 74

Figure 13-4. APB Memory Mapping 0x0000 0x00FC 0x0100 0x01FD 0x1000 0x1FFC DSU operating registers Replicated DSU operating registers DSU CoreSight ROM Empty Internal address range (cannot be accessed from debug tools when the device is protected by the NVMCTRL security bit) External address range (can be accessed from debug tools with some restrictions) Some features not activated by APB transactions are not available when the device is protected: Table 13-1. Feature Availability Under Protection Features Availability when the device is protected CPU Reset Extension Yes Clear CPU Reset Extension No Debugger Cold-Plugging Yes Debugger Hot-Plugging No References: 27. NVMCTRL – Non-Volatile Memory Controller Security Bit

13.10 Device Identification

Device identification relies on the ARM CoreSight component identification scheme, which allows the chip to be identified as a SAM device implementing a DSU. The DSU contains identification registers to differentiate the device.

13.10.1 CoreSight Identification

A system-level ARM CoreSight ROM table is present in the device to identify the vendor and the chip identification method. Its address is provided in the MEM-AP BASE register inside the ARM Debug Access Port. The CoreSight ROM implements a 64-bit conceptual ID composed as follows from the PID0 to PID7 CoreSight ROM Table registers: SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 75

Figure 13-5. Conceptual 64-bit Peripheral ID Table 13-2. Conceptual 64-Bit Peripheral ID Bit Descriptions Field Size Description Location JEP-106 CC code 4 Continuation code: 0x0 PID4 JEP-106 ID code 7 Device ID: 0x1F PID1+PID2 4KB count 4 Indicates that the CoreSight component is a ROM: 0x0 PID4 RevAnd 4 Not used; read as 0 PID3 CUSMOD 4 Not used; read as 0 PID3 PARTNUM 12 Contains 0xCD0 to indicate that DSU is present PID0+PID1 REVISION 4 DSU revision (starts at 0x0 and increments by 1 at both major and minor revisions). Identifies DSU identification method variants. If 0x0, this indicates that device identification can be completed by reading the Device Identification register (DID) PID3 For more information, refer to the ARM Debug Interface Version 5 Architecture Specification.

13.10.2 Chip Identification Method

The DSU DID register identifies the device by implementing the following information:

Processor identification
Product family identification
Product series identification
Device select

13.11 Functional Description

13.11.1 Principle of Operation

The DSU provides memory services such as CRC32 or MBIST that require almost the same interface. Hence, the Address, Length and Data registers (ADDR, LENGTH, DATA) are shared. These shared registers must be configured first; then a command can be issued by writing the Control register. When a command is ongoing, other commands are discarded until the current operation is completed. Hence, the user must wait for the STATUSA.DONE bit to be set prior to issuing another one.

13.11.2 Basic Operation

13.11.2.1 Initialization

The module is enabled by enabling its clocks. For more details, refer to Clocks. The DSU registers can be PAC write-protected. References: SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 76

PAC - Peripheral Access Controller

13.11.2.2 Operation From a Debug Adapter

Debug adapters should access the DSU registers in the external address range 0x100 – 0x2000. If the device is protected by the NVMCTRL security bit, accessing the first 0x100 bytes causes the system to return an error. Refer to 13.9. Intellectual Property Protection. References: 27. NVMCTRL – Non-Volatile Memory Controller Security Bit

13.11.2.3 Operation From the CPU

There are no restrictions when accessing DSU registers from the CPU. However, the user should access DSU registers in the internal address range (0x0 – 0x100) to avoid external security restrictions. Refer to 13.9. Intellectual Property Protection. 13.11.3 32-bit Cyclic Redundancy Check CRC32 The DSU unit provides support for calculating a cyclic redundancy check (CRC32) value for a memory area (including Flash and AHB RAM). When the CRC32 command is issued from:

The internal range, the CRC32 can be operated at any memory location
The external range, the CRC32 operation is restricted; DATA, ADDR, and LENGTH values are forced (see below) Table 13-3. AMOD Bit Descriptions when Operating CRC32 AMOD[1:0] Short name External range restrictions

0 ARRAY CRC32 is restricted to the full Flash array area (EEPROM emulation area not included)

DATA forced to 0xFFFFFFFF before calculation (no seed)

1 EEPROM CRC32 of the whole EEPROM emulation area DATA forced to 0xFFFFFFFF before

calculation (no seed) 2-3 Reserved The algorithm employed is the industry standard CRC32 algorithm using the generator polynomial 0xEDB88320 (reversed representation).

13.11.3.1 Starting CRC32 Calculation

CRC32 calculation for a memory range is started after writing the start address into the Address register (ADDR) and the size of the memory range into the Length register (LENGTH). Both must be word-aligned. The initial value used for the CRC32 calculation must be written to the Data register (DATA). This value will usually be 0xFFFFFFFF, but can be, for example, the result of a previous CRC32 calculation if generating a common CRC32 of separate memory blocks. Once completed, the calculated CRC32 value can be read out of the Data register. The read value must be complemented to match standard CRC32 implementations or kept non-inverted if used as starting point for subsequent CRC32 calculations. If the device is in protected state by the NVMCTRL security bit, it is only possible to calculate the CRC32 of the whole flash array when operated from the external address space. In most cases, this area will be the entire onboard non-volatile memory. The Address, Length and Data registers will be forced to predefined values once the CRC32 operation is started, and values written by the user are ignored. This allows the user to verify the contents of a protected device. The actual test is started by writing a '1' in the 32-bit Cyclic Redundancy Check bit of the Control register (CTRL.CRC). A running CRC32 operation can be canceled by resetting the module (writing '1' to CTRL.SWRST). References: 27. NVMCTRL – Non-Volatile Memory Controller SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 77

13.11.3.2 Interpreting the Results

The user should monitor the Status A register. When the operation is completed, STATUSA.DONE is set. Then the Bus Error bit of the Status A register (STATUSA.BERR) must be read to ensure that no bus error occurred.

13.11.4 Debug Communication Channels

The Debug Communication Channels (DCCO and DCC1) consist of a pair of registers with associated handshake logic, accessible by both CPU and debugger even if the device is protected by the NVMCTRL security bit. The registers can be used to exchange data between the CPU and the debugger, during run time as well as in debug mode. This enables the user to build a custom debug protocol using only these registers. The DCC0 and DCC1 registers are accessible when the protected state is active. When the device is protected, however, it is not possible to connect a debugger while the CPU is running (STATUSA.CRSTEXT is not writable and the CPU is held under Reset). Two Debug Communication Channel status bits in the Status B registers (STATUS.DCCDx) indicate whether a new value has been written in DCC0 or DCC1. These bits, DCC0D and DCC1D, are located in the STATUSB registers. They are automatically set on write and cleared on read. Note: The DCC0 and DCC1 registers are shared with the on-board memory testing logic (MBIST). Accordingly, DCC0 and DCC1 must not be used while performing MBIST operations. References: NVMCTRL 27.6.6. Security Bit

13.11.5 Testing of On-Board Memories MBIST

The DSU implements a feature for automatic testing of memory also known as MBIST (memory built-in self test). This is primarily intended for production test of on-board memories. MBIST cannot be operated from the external address range when the device is protected by the NVMCTRL security bit. If an MBIST command is issued when the device is protected, a protection error is reported in the Protection Error bit in the Status A register (STATUSA.PERR). 1. Algorithm The algorithm used for testing is a type of March algorithm called "March LR". This algorithm is able to detect a wide range of memory defects, while still keeping a linear run time. The algorithm is: a. Write entire memory to '0', in any order. b. Bit for bit read '0', write '1', in descending order. c. Bit for bit read '1', write '0', read '0', write '1', in ascending order. d. Bit for bit read '1', write '0', in ascending order. e. Bit for bit read '0', write '1', read '1', write '0', in ascending order. f. Read '0' from entire memory, in ascending order. The specific implementation used has a run time which depends on the CPU clock frequency and the number of bytes tested in the RAM. The detected faults are: – Address decoder faults – Stuck-at faults – Transition faults – Coupling faults – Linked Coupling faults 2. Starting MBIST To test a memory, you need to write the start address of the memory to the ADDR.ADDR bit field, and the size of the memory into the Length register. For best test coverage, an entire physical memory block should be tested at once. It is possible to test only a subset of a memory, but the test coverage will then be somewhat lower. The actual test is started by writing a '1' to CTRL.MBIST. A running MBIST operation can be canceled by writing a '1' to CTRL.SWRST. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 78

Interpreting the Results The tester should monitor the STATUSA register. When the operation is completed, STATUSA.DONE is set. There are two different modes: – ADDR.AMOD=0: exit-on-error (default) In this mode, the algorithm terminates either when a fault is detected or on successful completion. In both cases, STATUSA.DONE is set. If an error was detected, STATUSA.FAIL will be set. User then can read the DATA and ADDR registers to locate the fault. – ADDR.AMOD=1: pause-on-error In this mode, the MBIST algorithm is paused when an error is detected. In such a situation, only STATUSA.FAIL is asserted. The state machine waits for user to clear STATUSA.FAIL by writing a '1' in STATUSA.FAIL to resume. Prior to resuming, user can read the DATA and ADDR registers to locate the fault. 4. Locating Faults If the test stops with STATUSA.FAIL set, one or more bits failed the test. The test stops at the first detected error. The position of the failing bit can be found by reading the following registers: – ADDR: Address of the word containing the failing bit – DATA: contains data to identify which bit failed, and during which phase of the test it failed. The DATA register will in this case contains the following bit groups: Figure 13-6. DATA bits Description When MBIST Operation Returns an Error Bit Bit Bit Bit phase bit_index 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

bit_index: contains the bit number of the failing bit
phase: indicates which phase of the test failed and the cause of the error, as listed in the following table. Table 13-4. MBIST Operation Phases Phase Test actions 0 Write all bits to zero. This phase cannot fail.

1 Read '0', write '1', increment address

2 Read '1', write '0'

3 Read '0', write '1', decrement address

4 Read '1', write '0', decrement address

5 Read '0', write '1'

6 Read '1', write '0', decrement address

Table 13-5. AMOD Bit Descriptions for MBIST AMOD[1:0] Description 0x0 Exit on Error 0x1 Pause on Error 0x2, 0x3 Reserved References: NVMCTRL Security Bit

13.11.6 System Services Availability when Accessed Externally

External access: Access performed in the DSU address offset 0x200-0x1FFF range. Internal access: Access performed in the DSU address offset 0x0-0x100 range. Table 13-6. Available Features when Operated From The External Address Range and Device is Protected Features Availability From The External Address Range and Device is Protected Chip-Erase command and status Yes CRC32 Yes, only full array or full EEPROM CoreSight Compliant Device identification Yes Debug communication channels Yes Testing of onboard memories (MBIST) No STATUSA.CRSTEXT clearing No (STATUSA.PERR is set when attempting to do so) SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 80

13.12 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRL 7:0 CE MBIST CRC SWRST 0x01 STATUSA 7:0 PERR FAIL BERR CRSTEXT DONE 0x02 STATUSB 7:0 HPE DCCD1 DCCD0 DBGPRES PROT 0x03 Reserved 0x04 ADDR 7:0 ADDR[5:0] AMOD[1:0] 15:8 ADDR[13:6] 23:16 ADDR[21:14] 31:24 ADDR[29:22] 0x08 LENGTH 7:0 LENGTH[5:0] 15:8 LENGTH[13:6] 23:16 LENGTH[21:14] 31:24 LENGTH[29:22] 0x0C DATA 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] 0x10 DCC0 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] 0x14 DCC1 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] 0x18 DID 7:0 DEVSEL[7:0] 15:8 DIE[3:0] REVISION[3:0] 23:16 FAMILY[0] SERIES[5:0] 31:24 PROCESSOR[3:0] FAMILY[4:1] 0x1C ... 0x0FFF Reserved 0x1000 ENTRY0 7:0 FMT EPRES 15:8 ADDOFF[3:0] 23:16 ADDOFF[11:4] 31:24 ADDOFF[19:12] 0x1004 ENTRY1 7:0 FMT EPRES 15:8 ADDOFF[3:0] 23:16 ADDOFF[11:4] 31:24 ADDOFF[19:12] 0x1008 END 7:0 END[7:0] 15:8 END[15:8] 23:16 END[23:16] 31:24 END[31:24] 0x100C ... 0x1FCB Reserved 0x1FCC MEMTYPE 7:0 SMEMP 15:8 23:16 31:24 0x1FD0 PID4 7:0 FKBC[3:0] JEPCC[3:0] 15:8 23:16 31:24 SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 81

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x1FD4 ... 0x1FDF Reserved 0x1FE0 PID0 7:0 PARTNBL[7:0] 15:8 23:16 31:24 0x1FE4 PID1 7:0 JEPIDCL[3:0] PARTNBH[3:0] 15:8 23:16 31:24 0x1FE8 PID2 7:0 REVISION[3:0] JEPU JEPIDCH[2:0] 15:8 23:16 31:24 0x1FEC PID3 7:0 REVAND[3:0] CUSMOD[3:0] 15:8 23:16 31:24 0x1FF0 CID0 7:0 PREAMBLEB0[7:0] 15:8 23:16 31:24 0x1FF4 CID1 7:0 CCLASS[3:0] PREAMBLE[3:0] 15:8 23:16 31:24 0x1FF8 CID2 7:0 PREAMBLEB2[7:0] 15:8 23:16 31:24 0x1FFC CID3 7:0 PREAMBLEB3[7:0] 15:8 23:16 31:24

13.13 Register Description

13.13.1 Control

Name: CTRL Offset: 0x0000 Reset: 0x00 Property: PAC Write Protection Bit 7 6 5 4 3 2 1 0 CE MBIST CRC SWRST Access W W W W Reset 0 0 0 0 Bit 4 – CE Chip Erase Writing a '0' to this bit has no effect. Writing a '1' to this bit starts the chip erase operation. Bit 3 – MBIST Memory Built-In Self-Test Writing a '0' to this bit has no effect. Writing a '1' to this bit starts the memory BIST algorithm. Bit 2 – CRC 32-Bit Cyclic Redundancy Check Writing a '0' to this bit has no effect. Writing a '1' to this bit starts the cyclic redundancy check algorithm. Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets the module. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 83

13.13.2 Status A

Name: STATUSA Offset: 0x0001 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 PERR FAIL BERR CRSTEXT DONE Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 4 – PERR Protection Error Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Protection Error bit. This bit is set when a command that is not allowed in protected state is issued. Bit 3 – FAIL Failure Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Failure bit. This bit is set when a DSU operation failure is detected. Bit 2 – BERR Bus Error Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Bus Error bit. This bit is set when a bus error is detected. Bit 1 – CRSTEXT CPU Reset Phase Extension Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the CPU Reset Phase Extension bit. This bit is set when a debug adapter Cold-Plugging is detected, which extends the CPU reset phase. Bit 0 – DONE Done Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Done bit. This bit is set when a DSU operation is completed. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 84

13.13.3 Status B

Name: STATUSB Offset: 0x0002 Reset: 0x10000 Property: PAC Write Protection Bit 7 6 5 4 3 2 1 0 HPE DCCD1 DCCD0 DBGPRES PROT Access R R R R R Reset 1 0 0 0 0 Bit 4 – HPE Hot-Plugging Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit has no effect. This bit is set when Hot-Plugging is enabled. This bit is cleared when Hot-Plugging is disabled. This is the case when the SWCLK function is changed. Only a power Reset or a external Reset can set it again. Bits 2, 3 – DCCDx Debug Communication Channel x Dirty [x=1..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit has no effect. This bit is set when DCCx is written. This bit is cleared when DCCx is read. Bit 1 – DBGPRES Debugger Present Writing a '0' to this bit has no effect. Writing a '1' to this bit has no effect. This bit is set when a debugger probe is detected. This bit is never cleared. Bit 0 – PROT Protected Writing a '0' to this bit has no effect. Writing a '1' to this bit has no effect. This bit is set at power-up when the device is protected. This bit is never cleared. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 85

13.13.4 Address

Name: ADDR Offset: 0x0004 Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 ADDR[29:22] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 ADDR[21:14] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ADDR[13:6] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[5:0] AMOD[1:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:2 – ADDR[29:0] Address Initial word start address needed for memory operations. Bits 1:0 – AMOD[1:0] Access Mode The functionality of these bits is dependent on the operation mode. Bit description when operating CRC32: refer to 13.11.3. 32-bit Cyclic Redundancy Check CRC32 Bit description when testing onboard memories (MBIST): refer to 13.11.5. Testing of On-Board Memories MBIST SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 86

13.13.5 Length

Name: LENGTH Offset: 0x0008 Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 LENGTH[29:22] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 LENGTH[21:14] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 LENGTH[13:6] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LENGTH[5:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bits 31:2 – LENGTH[29:0] Length Length in words needed for memory operations. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 87

13.13.6 Data

Name: DATA Offset: 0x000C Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 DATA[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DATA[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DATA[31:0] Data Memory operation initial value or result value. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 88

13.13.7 Debug Communication Channel 0

Name: DCC0 Offset: 0x0010 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 DATA[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DATA[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DATA[31:0] Data Data register. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 89

13.13.8 Debug Communication Channel 1

Name: DCC1 Offset: 0x0014 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 DATA[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DATA[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DATA[31:0] Data Data register. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 90

13.13.9 Device Identification

Name: DID Offset: 0x0018 Reset: See References below Property: PAC Write-Protection The information in this register is related to the Ordering Information. Bit 31 30 29 28 27 26 25 24 PROCESSOR[3:0] FAMILY[4:1] Access R R R R R R R R Reset p p p p f f f f Bit 23 22 21 20 19 18 17 16 FAMILY[0] SERIES[5:0] Access R R R R R R R Reset f s s s s s s Bit 15 14 13 12 11 10 9 8 DIE[3:0] REVISION[3:0] Access R R R R R R R R Reset d d d d r r r r Bit 7 6 5 4 3 2 1 0 DEVSEL[7:0] Access R R R R R R R R Reset x x x x x x x x Bits 31:28 – PROCESSOR[3:0] Processor The value of this field defines the processor used on the device. Bits 27:23 – FAMILY[4:0] Product Family The value of this field corresponds to the Product Family part of the ordering code. Bits 21:16 – SERIES[5:0] Product Series The value of this field corresponds to the Product Series part of the ordering code. Bits 15:12 – DIE[3:0] Die Number Identifies the die family. Bits 11:8 – REVISION[3:0] Revision Number Identifies the die revision number. 0x0=rev.A, 0x1=rev.B etc. Note: The device variant (last letter of the ordering number) is independent of the die revision (DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks evolution of the die. Bits 7:0 – DEVSEL[7:0] Device Selection This bit field identifies a device within a product family and product series. Refer to the Ordering Information for device configurations and corresponding values for Flash memory density, pin count and device variant. For further information, refer to Device Identification. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 91

13.13.10 CoreSight ROM Table Entry 0

Name: ENTRY0 Offset: 0x1000 Reset: 0xXXXXX00X Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 ADDOFF[19:12] Access R R R R R R R R Reset x x x x x x x x Bit 23 22 21 20 19 18 17 16 ADDOFF[11:4] Access R R R R R R R R Reset x x x x x x x x Bit 15 14 13 12 11 10 9 8 ADDOFF[3:0] Access R R R R Reset x x x x Bit 7 6 5 4 3 2 1 0 FMT EPRES Access R R Reset 1 x Bits 31:12 – ADDOFF[19:0] Address Offset The base address of the component, relative to the base address of this ROM table. Bit 1 – FMT Format Always reads as '1', indicating a 32-bit ROM table. Bit 0 – EPRES Entry Present This bit indicates whether an entry is present at this location in the ROM table. This bit is set at power-up if the device is not protected indicating that the entry is not present. This bit is cleared at power-up if the device is not protected indicating that the entry is present. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 92

13.13.11 CoreSight ROM Table Entry 1

Name: ENTRY1 Offset: 0x1004 Reset: 0xXXXXX00X Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 ADDOFF[19:12] Access R R R R R R R R Reset x x x x x x x x Bit 23 22 21 20 19 18 17 16 ADDOFF[11:4] Access R R R R R R R R Reset x x x x x x x x Bit 15 14 13 12 11 10 9 8 ADDOFF[3:0] Access R R R R Reset x x x x Bit 7 6 5 4 3 2 1 0 FMT EPRES Access R R Reset 1 x Bits 31:12 – ADDOFF[19:0] Address Offset The base address of the component, relative to the base address of this ROM table. Bit 1 – FMT Format Always read as '1', indicating a 32-bit ROM table. Bit 0 – EPRES Entry Present This bit indicates whether an entry is present at this location in the ROM table. This bit is set at power-up if the device is not protected indicating that the entry is not present. This bit is cleared at power-up if the device is not protected indicating that the entry is present. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 93

13.13.12 CoreSight ROM Table End

Name: END Offset: 0x1008 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 END[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 END[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 END[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 END[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – END[31:0] End Marker Indicates the end of the CoreSight ROM table entries. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 94

13.13.13 CoreSight ROM Table Memory Type

Name: MEMTYPE Offset: 0x1FCC Reset: 0x0000000X Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 SMEMP Access R Reset x Bit 0 – SMEMP System Memory Present This bit indicates whether system memory is present on the bus that connects to the ROM table. This bit is set at power-up if the device is not protected, indicating that the system memory is accessible from a debug adapter. This bit is cleared at power-up if the device is protected, indicating that the system memory is not accessible from a debug adapter. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 95

13.13.14 Peripheral Identification 4

Name: PID4 Offset: 0x1FD0 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 FKBC[3:0] JEPCC[3:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:4 – FKBC[3:0] 4KB Count These bits will always return zero when read, indicating that this debug component occupies one 4KB block. Bits 3:0 – JEPCC[3:0] JEP-106 Continuation Code These bits will always return zero when read. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 96

13.13.15 Peripheral Identification 0

Name: PID0 Offset: 0x1FE0 Reset: 0x000000D0 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PARTNBL[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:0 – PARTNBL[7:0] Part Number Low These bits will always return 0xD0 when read, indicating that this device implements a DSU module instance. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 97

13.13.16 Peripheral Identification 1

Name: PID1 Offset: 0x1FE4 Reset: 0x000000FC Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 JEPIDCL[3:0] PARTNBH[3:0] Access R R R R R R R R Reset 1 1 1 1 1 1 0 0 Bits 7:4 – JEPIDCL[3:0] Low part of the JEP-106 Identity Code These bits will always return 0xF when read (JEP-106 identity code is 0x1F). Bits 3:0 – PARTNBH[3:0] Part Number High These bits will always return 0xC when read, indicating that this device implements a DSU module instance. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 98

13.13.17 Peripheral Identification 2

Name: PID2 Offset: 0x1FE8 Reset: 0x00000009 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 REVISION[3:0] JEPU JEPIDCH[2:0] Access R R R R R R R R Reset 0 0 0 0 1 0 0 1 Bits 7:4 – REVISION[3:0] Revision Number Revision of the peripheral. Starts at 0x0 and increments by one at both major and minor revisions. Bit 3 – JEPU JEP-106 Identity Code is used This bit will always return one when read, indicating that JEP-106 code is used. Bits 2:0 – JEPIDCH[2:0] JEP-106 Identity Code High These bits will always return 0x1 when read (JEP-106 identity code is 0x1F). SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 99

13.13.18 Peripheral Identification 3

Name: PID3 Offset: 0x1FEC Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 REVAND[3:0] CUSMOD[3:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:4 – REVAND[3:0] Revision Number These bits will always return 0x0 when read. Bits 3:0 – CUSMOD[3:0] ARM CUSMOD These bits will always return 0x0 when read. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 100

13.13.19 Component Identification 0

Name: CID0 Offset: 0x1FF0 Reset: 0x0000000D Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PREAMBLEB0[7:0] Access R R R R R R R R Reset 0 0 0 0 1 1 0 1 Bits 7:0 – PREAMBLEB0[7:0] Preamble Byte 0 These bits will always return 0x0000000D when read. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 101

13.13.20 Component Identification 1

Name: CID1 Offset: 0x1FF4 Reset: 0x00000010 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CCLASS[3:0] PREAMBLE[3:0] Access R R R R R R R R Reset 0 0 0 1 0 0 0 0 Bits 7:4 – CCLASS[3:0] Component Class These bits will always return 0x1 when read indicating that this ARM CoreSight component is ROM table (refer to the ARM Debug Interface v5 Architecture Specification at http://www.arm.com). Bits 3:0 – PREAMBLE[3:0] Preamble These bits will always return 0x00 when read. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 102

13.13.21 Component Identification 2

Name: CID2 Offset: 0x1FF8 Reset: 0x00000005 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PREAMBLEB2[7:0] Access R R R R R R R R Reset 0 0 0 0 0 1 0 1 Bits 7:0 – PREAMBLEB2[7:0] Preamble Byte 2 These bits will always return 0x00000005 when read. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 103

13.13.22 Component Identification 3

Name: CID3 Offset: 0x1FFC Reset: 0x000000B1 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PREAMBLEB3[7:0] Access R R R R R R R R Reset 1 0 1 1 0 0 0 1 Bits 7:0 – PREAMBLEB3[7:0] Preamble Byte 3 These bits will always return 0x000000B1when read. SAM L22 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 104

Clock System This chapter summarizes the clock distribution and terminology in the SAM L22 device. It does not explain every detail of its configuration. For in-depth documentation, see the respective peripherals descriptions and the Generic Clock documentation.

14.1 Clock Distribution

Figure 14-1. Clock Distribution GCLK Generator 0 OSCCTRL GCLK GCLK Generator 1 GCLK Generator x Peripheral Channel 0 (DFLL48M Reference) Peripheral Channel 1 (FDPLL96M Reference) Peripheral z Peripheral 0 Syncronous Clock Controller MCLK AHB/APB System Clocks GCLK_MAIN OSC16M DFLL48M XOSC Generic Clocks OSCK32CTRL OSCULP32K XOSC32K FDPLL96M Peripheral Channel 3 GCLK_DFLL48M_REF GCLK_FDPLL Peripheral Channel y GCLK_FDPLL_32K GCLK_FDPLL GCLK_FDPLL_32K RTC CLK_RTC_OSC CLK_WDT_OSC Peripheral Channel 2 (FDPLL96M Reference) WDT 32kHz 1kHz 32kHz 1kHz CLK_ULP32K EIC SLCD CLK_SLCD_OSC The SAM L22 clock system consists of:

Clock sources, that is oscillators controlled by OSCCTRL and OSC32KCTRL – A clock source provides a time base that is used by other components, such as Generic Clock Generators. Example clock sources include the internal 16 MHz oscillator (OSC16M), external crystal oscillator (XOSC0) and the Digital Frequency Locked Loop (DFLL48M).
Generic Clock Controller (GCLK), which generates, controls, and distributes the asynchronous clocks consisting of the following: – Generic Clock Generators: These are programmable prescalers that can use any of the system clock sources as a time base. The Generic Clock Generator 0 generates the clock signal GCLK_MAIN, which is used by the Power Manager and the Main Clock (MCLK) module, which in turn generates synchronous clocks. – Generic Clocks: These are clock signals generated by Generic Clock Generators and output by the Peripheral Channels, and serve as clocks for the peripherals of the system. Multiple instances of a peripheral will typically have a separate Generic Clock for each instance. Generic Clock 0 serves as the clock source for the DFLL48M clock input (when multiplying another clock source).
Main Clock Controller (MCLK) SAM L22 Family Clock System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 105

– The MCLK generates and controls the synchronous clocks on the system. This includes the CPU, bus clocks (APB, AHB), and the synchronous (to the CPU) user interfaces of the peripherals. It contains clock masks that can turn on/off the user interface of a peripheral and prescalers for the CPU and bus clocks. The figure below illustrates where SERCOM0 is clocked by the DFLL48M in open loop mode. The DFLL48M is enabled, the Generic Clock Generator 1 uses the DFLL48M as its clock source and feeds into Peripheral Channel 16. The Generic Clock 16, also called GCLK_SERCOM0_CORE, is connected to SERCOM0. The SERCOM0 interface, clocked by CLK_SERCOM0_APB, has been unmasked in the APBC Mask register in the MCLK. Figure 14-2. Example of SERCOM Clock OSCCTRL DFLL48M Generic Clock Generator 1 Peripheral Channel 16 SERCOM 0 Synchronous Clock Controller MCLK CLK_SERCOM0_APB GCLK_SERCOM0_CORE GCLK To customize the clock distribution, refer to these registers and bit fields:

The source oscillator for a Generic Clock Generator n is selected by writing to the Source bit field in the Generator Control n register (GCLK.GENCTRLn.SRC).
A Peripheral Channel m can be configured to use a specific Generic Clock Generator by writing to the Generic Clock Generator bit field in the respective Peripheral Channel m register (GCLK.PCHCTRLm.GEN)
The Peripheral Channel number, m, is fixed for a given peripheral. See the PCHCTRLm Mapping table in the description of GCLK.PCHCTRLm.
The AHB clocks are enabled and disabled by writing to the respective bit in the AHB Mask register (MCLK.AHBMASK).
The APB clocks are enabled and disabled by writing to the respective bit in the APB x Mask registers (MCLK.APBxMASK).

14.2 Synchronous and Asynchronous Clocks

As the CPU and the peripherals can be in different clock domains, that is they are clocked from different clock sources and with different clock speeds, some peripheral accesses by the CPU need to be synchronized. In this case the peripheral includes a Synchronization Busy (SYNCBUSY) register that can be used to check if a sync operation is in progress. For a general description, refer to 14.3. Register Synchronization. Some peripherals have specific properties described in their individual sub-chapter “Synchronization”. In the data sheet, references to Synchronous Clocks are referring to the CPU and bus clocks (MCLK), while asynchronous clocks are generated by the Generic Clock Controller (GCLK).

14.3 Register Synchronization

14.3.1 Overview

All peripherals are composed of one digital bus interface connected to the APB or AHB bus and running from a corresponding clock in the Main Clock domain, and one peripheral core running from the peripheral Generic Clock (GCLK). SAM L22 Family Clock System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 106

Communication between these clock domains must be synchronized. This mechanism is implemented in hardware, so the synchronization process takes place even if the peripheral generic clock is running from the same clock source and on the same frequency as the bus interface. All registers in the bus interface are accessible without synchronization. All registers in the peripheral core are synchronized when written. Some registers in the peripheral core are synchronized when read. Each individual register description will have the properties "Read-Synchronized" and/or "Write-Synchronized" if a register is synchronized. As shown in the figure below, each register that requires synchronization has its individual synchronizer and its individual synchronization status bit in the Synchronization Busy register (SYNCBUSY). Note: For registers requiring both read- and write-synchronization, the corresponding bit in SYNCBUSY is shared. Figure 14-3. Register Synchronization Overview Synchronous Domain(CLK_APB) Asynchronous Domain(GCLK ) Non Sync’d reg Periperal Bus Write-Sync’d reg SYNCBUSY R/W-Sync’d reg SyncSync Read-Sync’d reg Sync Write-only register Read-only register R/W register Write-Sync’d reg Sync R/W register Non Sync’d regRead-only register SyncINTFLAG

14.3.2 General Write Synchronization

Write-Synchronization is triggered by writing to a register in the peripheral clock domain. The respective bit in the Synchronization Busy register (SYNCBUSY) will be set when the write-synchronization starts and cleared when the When write-synchronization is ongoing for a register, any subsequent write attempts to this register will be discarded, and an error will be reported through the Peripheral Access Controller (PAC). Example: REGA, REGB are 8-bit core registers. REGC is a 16-bit core register. SAM L22 Family Clock System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 107

Synchronization is per register, so multiple registers can be synchronized in parallel. Consequently, after REGA (8-bit access) was written, REGB (8-bit access) can be written immediately without error. REGC (16-bit access) can be written without affecting REGA or REGB. If REGC is written to in two consecutive 8-bit accesses without waiting for synchronization, the second write attempt will be discarded and an error is generated through the PAC. A 32-bit access to offset 0x00 will write all three registers. Note that REGA, REGB and REGC can be updated at different times because of independent write synchronization.

14.3.3 General Read Synchronization

Read-synchronized registers are synchronized each time the register value is updated but the corresponding SYNCBUSY bits are not set. Reading a read-synchronized register does not start a new synchronization, it returns the last synchronized value. Note: The corresponding bits in SYNCBUSY will automatically be set when the device wakes up from sleep because read-synchronized registers need to be synchronized. Therefore reading a read-synchronized register before its corresponding SYNCBUSY bit is cleared will return the last synchronized value before sleep mode. Moreover, if a register is also write-synchronized, any write access while the SYNCBUSY bit is set will be discarded and generate an error.

14.3.4 Completion of Synchronization

In order to check if synchronization is complete, the user can either poll the relevant bits in SYNCBUSY or use the Synchronisation Ready interrupt (if available). The Synchronization Ready interrupt flag will be set when all ongoing synchronizations are complete, i.e. when all bits in SYNCBUSY are '0'. 14.3.5 Write Synchronization for CTRLA.ENABLE Setting the Enable bit in a module's Control A register (CTRLA.ENABLE) will trigger write-synchronization and set SYNCBUSY.ENABLE. CTRLA.ENABLE will read its new value immediately after being written. SYNCBUSY.ENABLE will be cleared by hardware when the operation is complete. The Synchronization Ready interrupt (if available) cannot be used to enable write-synchronization.

14.3.6 Write-Synchronization for Software Reset Bit

Setting the Software Reset bit in CTRLA (CTRLA.SWRST=1) will trigger write-synchronization and set SYNCBUSY.SWRST. When writing a ‘1’ to the CTRLA.SWRST bit it will immediately read as ‘1’. CTRL.SWRST and SYNCBUSY.SWRST will be cleared by hardware when the peripheral has been reset. Writing a '0' to the CTRL.SWRST bit has no effect. The Ready interrupt (if available) cannot be used for Software Reset write-synchronization. Note: Not all peripherals have the SWRST bit in the respective CTRLA register.

14.3.7 Synchronization Delay

The synchronization will delay write and read accesses by a certain amount. This delay D is within the range of: 5×PGCLK + 2×PAPB < D < 6×PGCLK + 3×PAPB Where PGCLK is the period of the generic clock and PAPB is the period of the peripheral bus clock. A normal peripheral bus register access duration is 2×PAPB. SAM L22 Family Clock System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 108

14.4 Enabling a Peripheral

In order to enable a peripheral that is clocked by a Generic Clock, the following parts of the system needs to be configured:

A running Clock Source
A clock from the Generic Clock Generator must be configured to use one of the running Clock Sources, and the Generator must be enabled.
The Peripheral Channel that provides the Generic Clock signal to the peripheral must be configured to use a running Generic Clock Generator, and the Generic Clock must be enabled.
The user interface of the peripheral needs to be unmasked in the PM. If this is not done the peripheral registers will read all 0’s and any writing attempts to the peripheral will be discarded.

14.5 On Demand Clock Requests

Figure 14-4. Clock Request Routing DFLL48M Generic Clock Generator Clock request Generic Clock Periph. Channel Clock request Peripheral Clock request ENABLE RUNSTDBY ONDEMAND CHEN RUNSTDBY ENABLE RUNSTDBY GENEN All clock sources in the system can be run in an on-demand mode: the clock source is in a stopped state unless a peripheral is requesting the clock source. Clock requests propagate from the peripheral, via the GCLK, to the clock source. If one or more peripheral is using a clock source, the clock source will be started/kept running. As soon as the clock source is no longer needed and no peripheral has an active request, the clock source will be stopped until requested again. The clock request can reach the clock source only if the peripheral, the generic clock and the clock from the Generic Clock Generator in-between are enabled. The time taken from a clock request being asserted to the clock source being ready is dependent on the clock source startup time, clock source frequency as well as the divider used in the Generic Clock Generator. The total startup time Tstart from a clock request until the clock is available for the peripheral is between: Tstart_max = Clock source startup time + 2 × clock source periods + 2 × divided clock source periods Tstart_min = Clock source startup time + 1 × clock source period + 1 × divided clock source period The time between the last active clock request stopped and the clock is shut down, Tstop, is between: Tstop_min = 1 × divided clock source period + 1 × clock source period Tstop_max = 2 × divided clock source periods + 2 × clock source periods The On-Demand function can be disabled individually for each clock source by clearing the ONDEMAND bit located in each clock source controller. Consequently, the clock will always run whatever the clock request status is. This has the effect of removing the clock source startup time at the cost of power consumption. The clock request mechanism can be configured to work in standby mode by setting the RUNSDTBY bits of the modules, see Figure 14-4. 14.6 Power Consumption vs. Speed When targeting for either a low-power or a fast acting system, some considerations have to be taken into account due to the nature of the asynchronous clocking of the peripherals: If clocking a peripheral with a very low clock, the active power consumption of the peripheral will be lower. At the same time the synchronization to the synchronous (CPU) clock domain is dependent on the peripheral clock speed, SAM L22 Family Clock System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 109

and will take longer with a slower peripheral clock. This will cause worse response times and longer synchronization delays.

14.7 Clocks after Reset

On any Reset the synchronous clocks start to their initial state:

OSC16M is enabled and configured to run at 4MHz
Generic Generator 0 uses OSC16M as source and generates GCLK_MAIN
CPU and BUS clocks are undivided On a Power-on Reset, the 32KHz clock sources are reset and the GCLK module starts to its initial state:
All Generic Clock Generators are disabled except – Generator 0 is using OSC16M at 4MHz as source and generates GCLK_MAIN
All Peripheral Channels in GCLK are disabled On a User Reset the GCLK module starts to its initial state, except for:
Generic Clocks that are write-locked, i.e., the according WRTLOCK is set to 1 prior to Reset References: RSTC - Reset Controller SAM L22 Family Clock System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 110

GCLK - Generic Clock Controller

15.1 Overview

Depending on the application, peripherals may require specific clock frequencies to operate correctly. The Generic Clock controller (GCLK) provides five Generic Clock Generators that can provide a wide range of clock frequencies. Generators can be set to use different external and internal oscillators as source. The clock of each Generator can be divided. The outputs from the Generators are used as sources for the Peripheral Channels, which provide the Generic Clock (GCLK_PERIPH) to the peripheral modules, as shown in Figure 15-2. The number of Peripheral Clocks depends on how many peripherals the device has. Note: The Generator 0 is always the direct source of the GCLK_MAIN signal.

15.2 Features

Provides a device-defined, configurable number of Peripheral Channel clocks
Wide frequency range

15.3 Block Diagram

The generation of Peripheral Clock signals (GCLK_PERIPH) and the Main Clock (GCLK_MAIN) can be seen in Device Clocking Diagram. Figure 15-1. Device Clocking Diagram GCLK_IO Generic Clock Generator OSC16M OSCCTR Clock Divider & Masker Clock Gate Peripheral Channel GCLK_PERIPH PERIPHERAL GENERIC CLOCK CONTROLLER MCLKGCLK_MAIN DFLL48M XOSC OSC32CTRL OSCULP32K XOSC32K DPLL96M The GCLK block diagram is shown below: SAM L22 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 111

Figure 15-2. Generic Clock Controller Block Diagram Generic Clock Generator 0 GCLK_IO[0] (I/O input) Clock Divider & Masker Clock Sources GCLKGEN[0] GCLK_IO[1] (I/O input) GCLKGEN[1] GCLK_IO[n] (I/O input) GCLKGEN[n] Clock Gate Peripheral Channel 0 GCLK_PERIPH[0] Clock Gate Peripheral Channel 1 Clock Gate Peripheral Channel m GCLKGEN[n:0] GCLK_MAIN GCLK_IO[1] (I/O output) GCLK_IO[0] (I/O output) GCLK_IO[n] (I/O output) Generic Clock Generator 1 Clock Divider & Masker Generic Clock Generator n Clock Divider & Masker GCLK_PERIPH[1] GCLK_PERIPH[m]

15.4 Signal Description

Table 15-1. GCLK Signal Description Signal Name Type Description GCLK_IO[4:0] Digital I/O Clock source for Generators when input Generic Clock signal when output Note: One signal can be mapped on several pins. References: I/O Multiplexing and Considerations

15.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

15.5.1 I/O Lines

Using the GCLK I/O lines requires the I/O pins to be configured. References: 28. PORT - I/O Pin Controller

15.5.2 Power Management

References: PM- Power Manager

15.5.3 Clocks

The GCLK bus clock (CLK_GCLK_APB) can be enabled and disabled in the Main Clock Controller. References: Peripheral Clock Masking OSC32KCTRL - 32kHz Oscillators Controller

15.5.4 DMA

Not applicable.

15.5.5 Interrupts

Not applicable.

15.5.6 Events

Not applicable.

15.5.7 Debug Operation

When the CPU is halted in debug mode the GCLK continues normal operation. If the GCLK is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging.

15.5.8 Register Access Protection

All registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC). Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection does not apply for accesses through an external debugger. References: 11. PAC - Peripheral Access Controller

15.5.9 Analog Connections

Not applicable.

15.6 Functional Description

15.6.1 Principle of Operation

The GCLK module is comprised of five Generic Clock Generators (Generators) sourcing up to 64 Peripheral Channels and the Main Clock signal GCLK_MAIN. A clock source selected as input to a Generator can either be used directly, or it can be prescaled in the Generator. A generator output is used by one or more Peripheral Channels to provide a peripheral generic clock signal (GCLK_PERIPH) to the peripherals.

15.6.1.1 Basic Operation

15.6.1.1.1 Initialization

Before a Generator is enabled, the corresponding clock source should be enabled. The Peripheral clock must be configured as outlined by the following steps: 1. The Generator must be enabled (GENCTRLn.GENEN=1) and the division factor must be set (GENTRLn.DIVSEL and GENCTRLn.DIV) by performing a single 32-bit write to the Generator Control register (GENCTRLn). SAM L22 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 113

The Generic Clock for a peripheral must be configured by writing to the respective Peripheral Channel Control register (PCHCTRLm). The Generator used as the source for the Peripheral Clock must be written to the GEN bit field in the Peripheral Channel Control register (PCHCTRLm.GEN). Note: Each Generator n is configured by one dedicated register GENCTRLn. Note: Each Peripheral Channel m is configured by one dedicated register PCHCTRLm.

15.6.1.1.2 Enabling, Disabling, and Resetting

The GCLK module has no enable/disable bit to enable or disable the whole module. The GCLK is reset by setting the Software Reset bit in the Control A register (CTRLA.SWRST) to 1. All registers in the GCLK will be reset to their initial state, except for Peripheral Channels and associated Generators that have their

15.6.1.1.3 Generic Clock Generator

Each Generator (GCLK_GEN) can be set to run from one of nine different clock sources except GCLK_GEN[1], which can be set to run from one of eight sources. GCLK_GEN[1] is the only Generator that can be selected as source to others Generators. Each generator GCLK_GEN[x] can be connected to one specific pin (GCLK_IO[y]). The GCLK_IO[y] can be set to act as source to GCLK_GEN[x] or to output the clock signal generated by GCLK_GEN[x]. The selected source can be divided. Each Generator can be enabled or disabled independently. Each GCLK_GEN clock signal can then be used as clock source for Peripheral Channels. Each Generator output is allocated to one or several Peripherals. GCLK_GEN[0] is used as GCLK_MAIN for the synchronous clock controller inside the Main Clock Controller. Refer to the Main Clock Controller description for details on the synchronous clock generation. Figure 15-3. Generic Clock Generator

15.6.1.1.4 Enabling a Generator

A Generator is enabled by writing a '1' to the Generator Enable bit in the Generator Control register (GENCTRLn.GENEN=1).

15.6.1.1.5 Disabling a Generator

A Generator is disabled by writing a '0' to GENCTRLn.GENEN. When GENCTRLn.GENEN=0, the GCLK_GEN[n] clock is disabled and gated.

15.6.1.1.6 Selecting a Clock Source for the Generator

Each Generator can individually select a clock source by setting the Source Select bit group in the Generator Control register (GENCTRLn.SRC). Changing from one clock source, for example A, to another clock source, B, can be done on the fly: If clock source B is not ready, the Generator will continue using clock source A. As soon as source B is ready, the Generator will switch to it. During the switching operation, the Generator maintains clock requests to both clock sources A and B, and will release source A as soon as the switch is done. The according bit in SYNCBUSY register (SYNCBUSY.GENCTRLn) will remain '1' until the switch operation is completed. SAM L22 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 114

The available clock sources are device dependent (usually the oscillators, RC oscillators, DPLL, and DFLL). Only Generator 1 can be used as a common source for all other generators.

15.6.1.1.7 Changing the Clock Frequency

The selected source for a Generator can be divided by writing a division value in the Division Factor bit field of the Generator Control register (GENCTRLn.DIV). How the actual division factor is calculated is depending on the Divide Selection bit (GENCTRLn.DIVSEL). If GENCTRLn.DIVSEL=0 and GENCTRLn.DIV is either 0 or 1, the output clock will be undivided. Note: The number of DIV bits for each Generator is device dependent.

15.6.1.1.8 Duty Cycle

When dividing a clock with an odd division factor, the duty-cycle will not be 50/50. Setting the Improve Duty Cycle bit of the Generator Control register (GENCTRLn.IDC) will result in a 50/50 duty cycle.

15.6.1.1.9 External Clock

The output clock (GCLK_GEN) of each Generator can be sent to I/O pins (GCLK_IO). If the Output Enable bit in the Generator Control register is set (GENCTRLn.OE = 1) and the generator is enabled (GENCTRLn.GENEN=1), the Generator requests its clock source and the GCLK_GEN clock is output to an I/O pin. If GENCTRLn.OE is 0, the according I/O pin is set to an Output Off Value, which is selected by GENCTRLn.OOV: If GENCTRLn.OOV is '0', the output clock will be low when turned off. If this bit is '1', the output clock will be high when turned off. In Standby mode, if the clock is output (GENCTRLn.OE=1), the clock on the I/O pin is frozen to the OOV value if the Run In Standby bit of the Generic Control register (GENCTRLn.RUNSTDBY) is zero. If GENCTRLn.RUNSTDBY is '1', the GCLKGEN clock is kept running and output to the I/O pin.

15.6.2 Peripheral Clock

Figure 15-4. Peripheral Clock

15.6.2.1 Enabling a Peripheral Clock

Before a Peripheral Clock is enabled, one of the Generators must be enabled (GENCTRLn.GENEN) and selected as source for the Peripheral Channel by setting the Generator Selection bits in the Peripheral Channel Control register (PCHCTRL.GEN). Any available Generator can be selected as clock source for each Peripheral Channel. When a Generator has been selected, the peripheral clock is enabled by setting the Channel Enable bit in the Peripheral Channel Control register, PCHCTRLm.CHEN = 1. The PCHCTRLm.CHEN bit must be synchronized to the generic clock domain. PCHCTRLm.CHEN will continue to read as its previous state until the synchronization is complete.

15.6.2.2 Disabling a Peripheral Clock

A Peripheral Clock is disabled by writing PCHCTRLm.CHEN=0. The PCHCTRLm.CHEN bit must be synchronized to the Generic Clock domain. PCHCTRLm.CHEN will stay in its previous state until the synchronization is complete. The Peripheral Clock is gated when disabled. SAM L22 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 115

15.6.2.3 Selecting the Clock Source for a Peripheral

When changing a peripheral clock source by writing to PCHCTRLm.GEN, the peripheral clock must be disabled before re-enabling it with the new clock source setting. This prevents glitches during the transition: 1. Disable the Peripheral Channel by writing PCHCTRLm.CHEN=0. 2. Assert that PCHCTRLm.CHEN reads '0'. 3. Change the source of the Peripheral Channel by writing PCHCTRLm.GEN. 4. Re-enable the Peripheral Channel by writing PCHCTRLm.CHEN=1. References: Peripheral Channel Control

15.6.2.4 Configuration Lock

The peripheral clock configuration can be locked for further write accesses by setting the Write Lock bit in the Peripheral Channel Control register PCHCTRLm.WRTLOCK=1). All writing to the PCHCTRLm register will be ignored. It can only be unlocked by a Power Reset. The Generator source of a locked Peripheral Channel will be locked, too: The corresponding GENCTRLn register is locked, and can be unlocked only by a Power Reset. There is one exception concerning the Generator 0. As it is used as GCLK_MAIN, it cannot be locked. It is reset by any Reset and will start up in a known configuration. The software reset (CTRLA.SWRST) can not unlock the registers. In case of an external Reset, the Generator source will be disabled. Even if the WRTLOCK bit is written to '1' the peripheral channels are disabled (PCHCTRLm.CHEN set to '0') until the Generator source is enabled again. Then, the PCHCTRLm.CHEN are set to '1' again. References: Peripheral Channel Control CTRLA

15.7 Additional Features

15.7.1 Peripheral Clock Enable after Reset

The Generic Clock Controller must be able to provide a generic clock to some specific peripherals after a Reset. That means that the configuration of the Generators and Peripheral Channels after Reset is device-dependent. Refer to GENCTRLn.SRC for details on GENCTRLn reset. Refer to PCHCTRLm.SRC for details on PCHCTRLm reset.

15.8 Sleep Mode Operation

15.8.1 SleepWalking

The GCLK module supports the SleepWalking feature. If the system is in a sleep mode where the Generic Clocks are stopped, a peripheral that needs its clock in order to execute a process must request it from the Generic Clock Controller. The Generic Clock Controller receives this request, determines which Generic Clock Generator is involved and which clock source needs to be awakened. It then wakes up the respective clock source, enables the Generator and Peripheral Channel stages successively, and delivers the clock to the peripheral. The RUNSTDBY bit in the Generator Control register controls clock output to pin during standby sleep mode. If the bit is cleared, the Generator output is not available on pin. When set, the GCLK can continuously output the References: SAM L22 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 116

15.8.2 Minimize Power Consumption in Standby

The following table identifies when a Clock Generator is off in Standby Mode, minimizing the power consumption: Table 15-2. Clock Generator n Activity in Standby Mode Request for Clock n present GENCTRLn.RUNSTDBY GENCTRLn.OE Clock Generator n yes - - active no 1 1 active no 1 0 OFF no 0 1 OFF no 0 0 OFF

15.8.3 Entering Standby Mode

There may occur a delay when the device is put into Standby, until the power is turned off. This delay is caused by running Clock Generators: if the Run in Standby bit in the Generator Control register (GENCTRLn.RUNSTDBY) is '0', GCLK must verify that the clock is turned of properly. The duration of this verification is frequency-dependent. References: PM - Power Manager

15.9 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. An exception is the Channel Enable bit in the Peripheral Channel Control registers (PCHCTRLm.CHEN). When changing this bit, the bit value must be read-back to ensure the synchronization is complete and to assert glitch free internal operation. Note that changing the bit value under ongoing synchronization will not generate an error. The following registers are synchronized when written:

Generic Clock Generator Control register (GENCTRLn)
Control A register (CTRLA) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. References: Peripheral Channel Control CTRLA SAM L22 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 117

15.10 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 SWRST 0x01 ... 0x03 Reserved 0x04 SYNCBUSY 7:0 GENCTRL4 GENCTRL3 GENCTRL2 GENCTRL1 GENCTRL0 SWRST 15:8 23:16 31:24 0x08 ... 0x1F Reserved 0x20 GENCTRL0 7:0 SRC[3:0] 15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN 23:16 DIV[7:0] 31:24 DIV[15:8] 0x24 GENCTRL1 7:0 SRC[3:0] 15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN 23:16 DIV[7:0] 31:24 DIV[15:8] 0x28 GENCTRL2 7:0 SRC[3:0] 15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN 23:16 DIV[7:0] 31:24 DIV[15:8] 0x2C GENCTRL3 7:0 SRC[3:0] 15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN 23:16 DIV[7:0] 31:24 DIV[15:8] 0x30 GENCTRL4 7:0 SRC[3:0] 15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN 23:16 DIV[7:0] 31:24 DIV[15:8] 0x34 ... 0x7F Reserved 0x80 PCHCTRL0 7:0 WRTLOCK CHEN GEN[3:0] 15:8 23:16 31:24 ... 0xF0 PCHCTRL28 7:0 WRTLOCK CHEN GEN[3:0] 15:8 23:16 31:24

15.11 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write- protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 15.5.8. Register Access Protection. Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write- Synchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to 15.9. Synchronization. SAM L22 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 118

15.11.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00 Property: PAC Write-Protection, Write-Synchronized Bit 7 6 5 4 3 2 1 0 SWRST Access R/W Reset 0 Bit 0 – SWRST Software Reset Writing a zero to this bit has no effect. Setting this bit to 1 will reset all registers in the GCLK to their initial state after a Power Reset, except for generic clocks and associated Generators that have their WRTLOCK bit in PCHCTRLm set to 1. Refer to GENCTRL Reset Value for details on GENCTRL register reset. Refer to PCHCTRL Reset Value for details on PCHCTRL register reset. Due to synchronization, there is a waiting period between setting CTRLA.SWRST and a completed Reset. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. Value Description 0 There is no Reset operation ongoing. 1 A Reset operation is ongoing. SAM L22 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 119

15.11.2 Synchronization Busy

Name: SYNCBUSY Offset: 0x04 Reset: 0x00000000 Property: – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 GENCTRL4 GENCTRL3 GENCTRL2 GENCTRL1 GENCTRL0 SWRST Access R R R R R R Reset 0 0 0 0 0 0 Bits 2, 3, 4, 5, 6 – GENCTRLn Generator Control n Synchronization Busy This bit is cleared when the synchronization of the Generator Control n register (GENCTRLn) between clock domains is complete, or when clock switching operation is complete. This bit is set when the synchronization of the Generator Control n register (GENCTRLn) between clock domains is started. Bit 0 – SWRST Software Reset Synchronization Busy This bit is cleared when the synchronization of the CTRLA.SWRST register bit between clock domains is complete. This bit is set when the synchronization of the CTRLA.SWRST register bit between clock domains is started. SAM L22 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 120

15.11.3 Generator Control

Name: GENCTRLn Offset: 0x20 + n*0x04 [n=0..4] Reset: 0x00010005 for Generator n=0, else 0x00000000 Property: PAC Write-Protection, Write-Synchronized GENCTRLn controls the settings of Generic Generator n (n=0..4). Bit 31 30 29 28 27 26 25 24 DIV[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIV[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 RUNSTDBY DIVSEL OE OOV IDC GENEN Access Reset Bit 7 6 5 4 3 2 1 0 SRC[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 31:16 – DIV[15:0] Division Factor These bits represent a division value for the corresponding Generator. The actual division factor is dependent on the state of DIVSEL. The number of relevant DIV bits for each Generator can be seen in this table. Written bits outside of the specified range will be ignored. Table 15-3. Division Factor Bits Generic Clock Generator Division Factor Bits Generator 0 8 division factor bits - DIV[7:0] Generator 1 16 division factor bits - DIV[15:0] Generator 2 - 4 8 division factor bits - DIV[7:0] Bit 13 – RUNSTDBY Run in Standby This bit is used to keep the Generator running in Standby as long as it is configured to output to a dedicated GCLK_IO pin. If GENCTRLn.OE is zero, this bit has no effect and the generator will only be running if a peripheral requires the clock. Value Description

0 The Generator is stopped in Standby and the GCLK_IO pin state (one or zero) will be dependent on

the setting in GENCTRL.OOV. 1 The Generator is kept running and output to its dedicated GCLK_IO pin during Standby mode. Bit 12 – DIVSEL Divide Selection This bit determines how the division factor of the clock source of the Generator will be calculated from DIV. If the clock source should not be divided, DIVSEL must be 0 and the GENCTRLn.DIV value must be either 0 or 1. Value Description 0 The Generator clock frequency equals the clock source frequency divided by GENCTRLn.DIV. 1 The Generator clock frequency equals the clock source frequency divided by 2^(GENCTRLn.DIV+1). SAM L22 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 121

Bit 11 – OE Output Enable This bit is used to output the Generator clock output to the corresponding pin (GCLK_IO), as long as GCLK_IO is not defined as the Generator source in the GENCTRLn.SRC bit field. Value Description 0 No Generator clock signal on pin GCLK_IO.

1 The Generator clock signal is output on the corresponding GCLK_IO, unless GCLK_IO is selected as a

generator source in the GENCTRLn.SRC bit field. Bit 10 – OOV Output Off Value This bit is used to control the clock output value on pin (GCLK_IO) when the Generator is turned off or the OE bit is zero, as long as GCLK_IO is not defined as the Generator source in the GENCTRLn.SRC bit field. Value Description 0 The GCLK_IO will be LOW when generator is turned off or when the OE bit is zero. 1 The GCLK_IO will be HIGH when generator is turned off or when the OE bit is zero. Bit 9 – IDC Improve Duty Cycle This bit is used to improve the duty cycle of the Generator output to 50/50 for odd division factors. Value Description 0 Generator output clock duty cycle is not balanced to 50/50 for odd division factors. 1 Generator output clock duty cycle is 50/50. Bit 8 – GENEN Generator Enable This bit is used to enable and disable the Generator. Value Description 0 Generator is disabled. 1 Generator is enabled. Bits 3:0 – SRC[3:0] Generator Clock Source Selection These bits select the Generator clock source, as shown in this table. Table 15-4. Generator Clock Source Selection Value Name Description 0x0 XOSC XOSC oscillator output 0x1 GCLK_IN Generator input pad (GCLK_IO) 0x2 GCLK_GEN1 Generic clock generator 1 output 0x3 OSCULP32K OSCULP32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC16M OSC16M oscillator output 0x6 DFLL48M DFLL48M output 0x7 DPLL96M DPLL96M output 0x8-0xF Reserved Reserved for future use A Power Reset will reset all GENCTRLn registers. the Reset values of the GENCTRLn registers are shown in table below. Table 15-5. GENCTRLn Reset Value after a Power Reset GCLK Generator Reset Value after a Power Reset 0 0x00010005 others 0x00000000 A User Reset will reset the associated GENCTRL register unless the Generator is the source of a locked Peripheral Channel (PCHCTRLm.WRTLOCK=1). The reset values of the GENCTRL register are as shown in the table below. Table 15-6. GENCTRLn Reset Value after a User Reset GCLK Generator Reset Value after a User Reset 0 0x00000105 SAM L22 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 122

GCLK Generator Reset Value after a User Reset others No change if the generator is used by a Peripheral Channel m with PCHCTRLm.WRTLOCK=1 else 0x00000000 SAM L22 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 123

15.11.4 Peripheral Channel Control

Name: PCHCTRLm Offset: 0x80 + m*0x04 [m=0..28] Reset: 0x00000000 Property: PAC Write-Protection PCHTRLm controls the settings of Peripheral Channel number m (m = 0..28). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 WRTLOCK CHEN GEN[3:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 – WRTLOCK Write Lock After this bit is set to '1', further writes to the PCHCTRLm register will be discarded. The control register of the corresponding Generator n (GENCTRLn), as assigned in PCHCTRLm.GEN, will also be locked. It can only be unlocked by a Power Reset. Note that Generator 0 cannot be locked. Value Description

0 The Peripheral Channel register and the associated Generator register are not locked

1 The Peripheral Channel register and the associated Generator register are locked

Bit 6 – CHEN Channel Enable This bit is used to enable and disable a Peripheral Channel. Value Description

0 The Peripheral Channel is disabled

1 The Peripheral Channel is enabled

Bits 3:0 – GEN[3:0] Generator Selection This bit field selects the Generator to be used as the source of a peripheral clock, as shown in the table below: Table 15-7. Generator Selection Value Description 0x0 Generic Clock Generator 0 0x1 Generic Clock Generator 1 0x2 Generic Clock Generator 2 0x3 Generic Clock Generator 3 0x4 Generic Clock Generator 4 0x5 - 0xF Reserved SAM L22 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 124

Table 15-8. Reset Value after a User Reset or a Power Reset Reset PCHCTRLm.GEN PCHCTRLm.CHEN PCHCTRLm.WRTLOCK Power Reset 0x0 0x0 0x0 User Reset If WRTLOCK = 0 : 0x0 If WRTLOCK = 1: no change If WRTLOCK = 0 : 0x0 If WRTLOCK = 1: no change No change A Power Reset will reset all the PCHCTRLm registers. A User Reset will reset a PCHCTRL if WRTLOCK = 0, or else, the content of that PCHCTRL remains unchanged. The PCHCTRL register Reset values are shown in the table PCHCTRLm Mapping. Table 15-9. PCHCTRLm Mapping index(m) Name Description

0 GCLK_DFLL48M_REF DFLL48M Reference

1 GCLK_FDPLL FDPLL96M input clock source for reference

2 GCLK_FDPLL_32K FDPLL96M 32kHz clock for FDPLL96M internal lock timer

3 GCLK_EIC EIC

4 GCLK_FREQM_MSR FREQM Measure

5 GCLK_FREQM_REF FREQM Reference

6 GLCK_USB USB

7 GCLK_EVSYS_CHANNEL_0 EVSYS_CHANNEL_0

8 GCLK_EVSYS_CHANNEL_1 EVSYS_CHANNEL_1

9 GCLK_EVSYS_CHANNEL_2 EVSYS_CHANNEL_2

10 GCLK_EVSYS_CHANNEL_3 EVSYS_CHANNEL_3

11 GCLK_EVSYS_CHANNEL_4 EVSYS_CHANNEL_4

12 GCLK_EVSYS_CHANNEL_5 EVSYS_CHANNEL_5

13 GCLK_EVSYS_CHANNEL_6 EVSYS_CHANNEL_6

14 GCLK_EVSYS_CHANNEL_7 EVSYS_CHANNEL_7

15 GCLK_SERCOM[0,1,2,3,4,5]_SLOW SERCOM[0,1,2,3,4,5]_SLOW

16 GCLK_SERCOM0_CORE SERCOM0_CORE

17 GCLK_SERCOM1_CORE SERCOM1_CORE

18 GCLK_SERCOM2_CORE SERCOM2_CORE

19 GCLK_SERCOM3_CORE SERCOM3_CORE

20 GCLK_SERCOM4_CORE SERCOM4_CORE

21 GCLK_SERCOM5_CORE SERCOM5_CORE

22 GCLK_TCC0 TCC0

23 GCLK_TC0, GCLK_TC1 TC0, TC1

24 GCLK_TC2, GCLK_TC3 TC2, TC3

25 GCLK_ADC ADC

26 GCLK_AC AC

27 GCLK_PTC PTC

28 GCLK_CCL CCL

MCLK – Main Clock

16.1 Overview

The Main Clock (MCLK) controls the synchronous clock generation of the device. Using a clock provided by the Generic Clock Module (GCLK_MAIN), the Main Clock Controller provides synchronous system clocks to the CPU and the modules connected to the AHBx and the APBx buses. The synchronous system clocks are divided into a number of clock domains. Each clock domain can run at different frequencies, enabling the user to save power by running peripherals at a relatively low clock frequency, while maintaining high CPU performance or vice versa. In addition, the clock can be masked for individual modules, enabling the user to minimize power consumption .

16.2 Features

Generates CPU, AHB, and APB system clocks – Clock source and division factor from GCLK – Clock prescaler with 1x to 128x division
Safe run-time clock switching from GCLK
Module-level clock gating through maskable peripheral clocks

16.3 Block Diagram

Figure 16-1. MCLK Block Diagram MAIN CLOCK CONTROLLER CPU GCLK GCLK_MAIN PERIPHERALS CLK_APBx CLK_AHBx CLK_CPU x = A, B, C or D

16.4 Signal Description

Not applicable.

16.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

16.5.1 I/O Lines

16.5.2 Power Management

The MCLK will operate in all sleep modes if a synchronous clock is required in these modes.

16.5.3 Clocks

The MCLK bus clock (CLK_MCLK_APB) can be enabled and disabled in the Main Clock module, and the default state of CLK_MCLK_APB can be found in the Peripheral Clock Masking section. If this clock is disabled, it can only be re-enabled by a reset. The Generic Clock GCLK_MAIN is required to generate the Main Clocks. GCLK_MAIN is configured in the Generic Clock Controller, and can be re-configured by the user if needed.

16.5.3.1 Main Clock

The main clock CLK_MAIN is the common source for the synchronous clocks. This is fed into the common 8-bit prescaler that is used to generate synchronous clocks to the CPU, AHBx, and APBx modules.

16.5.3.2 CPU Clock

The CPU clock (CLK_CPU) is routed to the CPU. Halting the CPU clock inhibits the CPU from executing instructions.

16.5.3.3 APBx and AHBx Clock

The APBx clocks (CLK_APBx) and the AHBx clocks (CLK_AHBx) are the root clock sources used by modules requiring a clock on the APBx and the AHBx buses. These clocks are always synchronous to the CPU clock, and can run even when the CPU clock is turned off in sleep mode. A clock gater is inserted after the common APB clock to gate any APBx clock of a module on APBx bus, as well as the AHBx clock serving that module.

16.5.3.4 Clock Domains

The device has these synchronous clock domains:

High-Speed synchronous clock domain (HS Clock Domain). Frequency is f HS.
CPU synchronous clock domain (CPU Clock Domain). Frequency is f CPU.
Backup synchronous clock domain. (BUP Clock Domain). Frequency is f BUP. See also the related links for the clock domain partitioning.

16.5.4 DMA

Not applicable.

16.5.5 Interrupts

The interrupt request line is connected to the Interrupt Controller. Using the MCLK interrupt requires the Interrupt Controller to be configured first.

16.5.6 Events

Not applicable.

16.5.7 Debug Operation

When the CPU is halted in debug mode, the MCLK continues normal operation. In sleep mode, the clocks generated from the MCLK are kept running to allow the debugger accessing any module. As a consequence, power measurements are incorrect in debug mode.

16.5.8 Register Access Protection

All registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Interrupt Flag register (INTFLAG) Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. PAC write protection does not apply to accesses through an external debugger. SAM L22 Family MCLK – Main Clock © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 127

16.5.9 Analog Connections

Not applicable.

16.6 Functional Description

16.6.1 Principle of Operation

The GCLK_MAIN clock signal from the GCLK module is the source for the main clock, which in turn is the common root for the synchronous clocks for the CPU, APBx, and AHBx modules. The GCLK_MAIN is divided by an 8-bit prescaler. Each of the derived clocks can run from any divided or undivided main clock, ensuring synchronous clock sources for each clock domain. Each clock domain (CPU, BUP) can be changed on the fly to respond to variable load in the application as long as fCPU ≥ fBUP. The clocks for each module in a clock domain can be masked individually to avoid power consumption in inactive modules. Depending on the sleep mode, some clock domains can be turned off.

16.6.2 Basic Operation

16.6.2.1 Initialization

After a Reset, the default clock source of the CLK_MAIN clock (GCLK_MAIN) is started and calibrated before the CPU starts running. The GCLK_MAIN clock is selected as the main clock without any prescaler division. By default, only the necessary clocks are enabled.

16.6.2.2 Enabling, Disabling, and Resetting

The MCLK module is always enabled and cannot be reset.

16.6.2.3 Selecting the Main Clock Source

Refer to the Generic Clock Controller description for details on how to configure the clock source of the GCLK_MAIN clock.

16.6.2.4 Selecting the Synchronous Clock Division Ratio

The main clock CLK_MAIN feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By default, the synchronous clocks run on the undivided main clock. The user can select a prescaler division for the CPU clock domain by writing the Division (DIV) bits in the CPU Clock Division register CPUDIV, resulting in a CPU clock domain frequency determined by this equation: f C PU = f mai n C PU DI V Similarly, the clock for the Backup Clock Domain can be divided by writing the BUPDIV register. To ensure correct operation, frequencies must be selected so that fCPU ≥ fBUP. Also, frequencies must never exceed the specified maximum frequency for each clock domain given in the electrical characteristics specifications. If the application attempts to write forbidden values in CPUDIV or BUPDIV registers, registers are written but these bad values are not used and a violation is reported to the PAC module. Division bits (DIV) can be written without halting or disabling peripheral modules. Writing DIV bits allows a new clock setting to be written to all synchronous clocks belonging to the corresponding clock domain at the same time. Each clock domain can be changed without changing others. This way, it is possible to, for example, scale the CPU clock domain speed according to the required performance, while keeping the Backup Clock Domain frequency constant. SAM L22 Family MCLK – Main Clock © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 128

Figure 16-2. Synchronous Clock Selection and Prescaler Prescaler Sleep Controller Sleep mode BUPDIV CPUDIV CLK_CPU GCLK GCLK_MAIN Clock gate Clock gate Clock gateCLK_AHB_HS clk_ahb_ip0 clk_ahb_ip1 clk_ahb_ipn Clock gate Clock gate CLK_APB_HS clk_apb_ip0 clk_apb_ip1 clk_apb_ipn Clock gate Clock gate PERIPHERALS CPU Clock gate Clock gateCLK_APBx clk_apb_ip0 clk_apb_ip1 clk_apb_ipn Clock gate Clock gate MASK PERIPHERALS Backup Clock Domain: fBUP CPU Clock Domain: fCPU MASK MASK

16.6.2.5 Clock Ready Flag

There is a slight delay between writing to CPUDIV and BUPDIV until the new clock settings become effective. During this interval, the Clock Ready flag in the Interrupt Flag Status and Clear register (INTFLAG.CKRDY) will return zero when read. If CKRDY in the INTENSET register is set to '1', the Clock Ready interrupt will be triggered when the new clock settings are effective. The clock settings (CPUDIV, BUPDIV) must not be re-written while INTFLAG.CKRDY reads '0'. The system may become unstable or hang, and a violation is reported to the PAC module.

16.6.2.6 Peripheral Clock Masking

The user can disable or enable the AHB or APB clock for a peripheral by writing the corresponding bit in the Clock Mask registers (APBxMASK) to '0' or '1'. The default state of the peripheral clocks is given in the table below: Table 16-1. Peripheral Clock Default State CPU Clock Domain Peripheral Clock Default State CLK_AC_APB Enabled CLK_ADC_APB Enabled CLK_AES_APB Enabled CLK_BRIDGE_A_AHB Enabled CLK_BRIDGE_B_AHB Enabled CLK_BRIDGE_C_AHB Enabled CLK_CCL_APB Enabled CLK_DMAC_AHB Enabled CLK_DSU_AHB Enabled CLK_EIC_APB Enabled SAM L22 Family MCLK – Main Clock © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 129

Peripheral Clock Default State CLK_EVSYS_APB Enabled CLK_FREQM_APB Enabled CLK_GCLK_APB Enabled CLK_MCLK_APB Enabled CLK_NVMCTRL_AHB Enabled CLK_NVMCTRL_APB Enabled CLK_OSCCTRL_APB Enabled CLK_PAC_AHB Enabled CLK_PAC_APB Enabled CLK_PORT_APB Enabled CLK_PTC_APB Enabled CLK_SERCOM0_APB Enabled CLK_SERCOM1_APB Enabled CLK_SERCOM2_APB Enabled CLK_SERCOM3_APB Enabled CLK_SERCOM4_APB Enabled CLK_SERCOM5_APB Enabled CLK_SLCD_APB Enabled CLK_TC0_APB Enabled CLK_TC1_APB Enabled CLK_TC2_APB Enabled CLK_TC3_APB Enabled CLK_TCC0_APB Enabled CLK_TRNG_APB Enabled CLK_USB_AHB Enabled CLK_USB_APB Enabled CLK_WDT_APB Enabled Table 16-2. Backup Clock Domain Backup Clock Domain Peripheral Clock Default State CLK_OSC32KCTRL_APB Enabled CLK_PM_APB Enabled CLK_SUPC_APB Enabled CLK_RSTC_APB Enabled CLK_RTC_APB Enabled SAM L22 Family MCLK – Main Clock © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 130

When the APB clock is not provided to a module, its registers cannot be read or written. The module can be re-enabled later by writing the corresponding mask bit to '1'. A module may be connected to several clock domains (for example, AHB and APB), in which case it will have several mask bits. The clocks should only be switched off if it is certain that the module will not be used: Switching off the clock for the NVM Controller (NVMCTRL) will cause a problem if the CPU needs to read from the Flash memory. Switching off the clock to the MCLK module (which contains the mask registers) or the corresponding APBx bridge, will make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset.

16.6.3 DMA Operation

Not applicable.

16.6.4 Interrupts

The peripheral has the following interrupt sources:

Clock Ready (CKRDY): indicates that CPU and BUP clocks are ready. This interrupt is a synchronous wake-up source. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be enabled individually by writing a '1' to the corresponding enabling bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the corresponding clearing bit in the Interrupt Enable Clear (INTENCLR) register. The status of enabled interrupts can be read from either INTENSET or INTENCLR. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the peripheral is reset. An interrupt flag is cleared by writing a '1' to the corresponding bit in the INTFLAG register. Each peripheral can have one interrupt request line per interrupt source or one common interrupt request line for all the interrupt sources. If the peripheral has one common interrupt request line for all the interrupt sources, the user must read the INTFLAG register to determine which interrupt condition is present.

16.6.5 Events

Not applicable.

16.6.6 Sleep Mode Operation

In IDLE sleep mode, the MCLK is still running on the selected main clock. In STANDBY sleep mode, the MCLK is frozen if no synchronous clock is required. SAM L22 Family MCLK – Main Clock © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 131

16.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 Reserved 0x01 INTENCLR 7:0 CKRDY 0x02 INTENSET 7:0 CKRDY 0x03 INTFLAG 7:0 CKRDY 0x04 CPUDIV 7:0 CPUDIV[7:0] 0x05 Reserved 0x06 BUPDIV 7:0 BUPDIV[7:0] 0x07 ... 0x0F Reserved 0x10 AHBMASK 7:0 PAC Reserved DSU USB DMAC APBC APBB APBA 15:8 Reserved Reserved NVMCTRL 23:16 31:24 0x14 APBAMASK 7:0 GCLK SUPC OSC32KCTR L OSCCTRL RSTC MCLK PM PAC 15:8 FREQM EIC RTC WDT 23:16 31:24 0x18 APBBMASK 7:0 PORT NVMCTRL DSU USB 15:8 23:16 31:24 0x1C APBCMASK 7:0 TCC0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS 15:8 SLCD PTC AC ADC TC3 TC2 TC1 TC0 23:16 CCL TRNG AES 31:24

16.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers can be write-protected optionally by the Peripheral Access Controller (PAC). This is denoted by the property "PAC Write-Protection" in each individual register description. Refer to the 16.5.8. Register Access Protection for details. SAM L22 Family MCLK – Main Clock © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 132

16.8.1 Interrupt Enable Clear

Name: INTENCLR Offset: 0x01 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 7 6 5 4 3 2 1 0 CKRDY Access R/W Reset 0 Bit 0 – CKRDY Clock Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Clock Ready Interrupt Enable bit and the corresponding interrupt request. Value Description 0 The Clock Ready interrupt is disabled.

1 The Clock Ready interrupt is enabled and will generate an interrupt request when the Clock Ready

16.8.2 Interrupt Enable Set

Name: INTENSET Offset: 0x02 Reset: 0x00 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 7 6 5 4 3 2 1 0 CKRDY Access R/W Reset 0 Bit 0 – CKRDY Clock Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Clock Ready Interrupt Enable bit and enable the Clock Ready interrupt. Value Description 0 The Clock Ready interrupt is disabled. 1 The Clock Ready interrupt is enabled. SAM L22 Family MCLK – Main Clock © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 134

16.8.3 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x03 Reset: 0x01 Property: – Bit 7 6 5 4 3 2 1 0 CKRDY Access R/W Reset 1 Bit 0 – CKRDY Clock Ready This flag is cleared by writing a '1' to the flag. This flag is set when the synchronous CPU, APBx, and AHBx clocks are stable and will generate an interrupt if INTENCLR/SET.CKRDY is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Clock Ready interrupt flag. SAM L22 Family MCLK – Main Clock © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 135

16.8.4 CPU Clock Division

Name: CPUDIV Offset: 0x04 Reset: 0x01 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CPUDIV[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 1 Bits 7:0 – CPUDIV[7:0] CPU Clock Division Factor These bits define the division ratio of the main clock prescaler related to the CPU clock domain. To ensure correct operation, frequencies must be selected so that FCPU≥ FBUP (i.e., BUPDIV ≥ CPUDIV). Frequencies must never exceed the specified maximum frequency for each clock domain. Value Name Description 0x01 DIV1 Divide by 1 0x02 DIV2 Divide by 2 0x04 DIV4 Divide by 4 0x08 DIV8 Divide by 8 0x10 DIV16 Divide by 16 0x20 DIV32 Divide by 32 0x40 DIV64 Divide by 64 0x80 DIV128 Divide by 128 others - Reserved SAM L22 Family MCLK – Main Clock © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 136

16.8.5 Backup Clock Division

Name: BUPDIV Offset: 0x06 Reset: 0x01 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 BUPDIV[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – BUPDIV[7:0] Backup Clock Division Factor These bits define the division ratio of the main clock prescaler (2n) related to the Backup clock domain. To ensure correct operation, frequencies must be selected so that FCPU ≥ FBUP (i.e. BUPDIV ≥ CPUDIV). Also, frequencies must never exceed the specified maximum frequency for each clock domain. Refer to the Maximum Clock Frequencies in the Electrical Characterization section for maximum frequencies in each performance level. Value Name Description 0x01 DIV1 Divide by 1 0x02 DIV2 Divide by 2 0x04 DIV4 Divide by 4 0x08 DIV8 Divide by 8 0x10 DIV16 Divide by 16 0x20 DIV32 Divide by 32 0x40 DIV64 Divide by 64 0x80 DIV128 Divide by 128 others - Reserved SAM L22 Family MCLK – Main Clock © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 137

16.8.6 AHB Mask

Name: AHBMASK Offset: 0x10 Reset: 0x000007FF Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Reserved Reserved NVMCTRL Access R/W R/W R/W Reset 1 1 1 Bit 7 6 5 4 3 2 1 0 PAC Reserved DSU USB DMAC APBC APBB APBA Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bits 10,9,6 – Reserved Reserved bits Reserved bits are unused and reserved for future use. For compatibility with future devices, always write reserved bits to their reset value. If no reset value is given, write 0. Bit 8 – NVMCTRL NVMCTRL AHB Clock Enable Value Description

0 The AHB clock for the NVMCTRL is stopped

1 The AHB clock for the NVMCTRL is enabled

Bit 7 – PAC PAC AHB Clock Enable Value Description 0 The AHB clock for the PAC is stopped. 1 The AHB clock for the PAC is enabled. Bit 5 – DSU DSU AHB Clock Enable Value Description 0 The AHB clock for the DSU is stopped. 1 The AHB clock for the DSU is enabled. Bit 4 – USB USB AHB Clock Enable Value Description 0 The AHB clock for the USB is stopped. 1 The AHB clock for the USB is enabled. Bit 3 – DMAC DMAC AHB Clock Enable Value Description 0 The AHB clock for the DMAC is stopped. 1 The AHB clock for the DMAC is enabled. SAM L22 Family MCLK – Main Clock © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 138

Bit 2 – APBC APBC AHB Clock Enable Value Description 0 The AHB clock for the APBC is stopped.

1 The AHB clock for the APBC is enabled

Bit 1 – APBB APBB AHB Clock Enable Value Description 0 The AHB clock for the APBB is stopped. 1 The AHB clock for the APBB is enabled. Bit 0 – APBA APBA AHB Clock Enable Value Description 0 The AHB clock for the APBA is stopped. 1 The AHB clock for the APBA is enabled. SAM L22 Family MCLK – Main Clock © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 139

16.8.7 APBA Mask

Name: APBAMASK Offset: 0x14 Reset: 0x00000FFF Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 FREQM EIC RTC WDT Access R/W R/W R/W R/W Reset 1 1 1 1 Bit 7 6 5 4 3 2 1 0 GCLK SUPC OSC32KCTRL OSCCTRL RSTC MCLK PM PAC Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 11 – FREQM FREQM APBA Clock Enable Value Description 0 The APBA clock for the FREQM is stopped. 1 The APBA clock for the FREQM is enabled. Bit 10 – EIC EIC APBA Clock Enable Value Description 0 The APBA clock for the EIC is stopped. 1 The APBA clock for the EIC is enabled. Bit 9 – RTC RTC APBA Clock Enable Value Description 0 The APBA clock for the RTC is stopped. 1 The APBA clock for the RTC is enabled. Bit 8 – WDT WDT APBA Clock Enable Value Description 0 The APBA clock for the WDT is stopped. 1 The APBA clock for the WDT is enabled. Bit 7 – GCLK GCLK APBA Clock Enable Value Description 0 The APBA clock for the GCLK is stopped. 1 The APBA clock for the GCLK is enabled. Bit 6 – SUPC SUPC APBA Clock Enable Value Description 0 The APBA clock for the SUPC is stopped. SAM L22 Family MCLK – Main Clock © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 140

1 The APBA clock for the SUPC is enabled. Bit 5 – OSC32KCTRL OSC32KCTRL APBA Clock Enable Value Description 0 The APBA clock for the OSC32KCTRL is stopped. 1 The APBA clock for the OSC32KCTRL is enabled. Bit 4 – OSCCTRL OSCCTRL APBA Clock Enable Value Description 0 The APBA clock for the OSCCTRL is stopped. 1 The APBA clock for the OSCCTRL is enabled. Bit 3 – RSTC RSTC APBA Clock Enable Value Description 0 The APBA clock for the RSTC is stopped. 1 The APBA clock for the RSTC is enabled. Bit 2 – MCLK MCLK APBA Clock Enable Value Description 0 The APBA clock for the MCLK is stopped. 1 The APBA clock for the MCLK is enabled. Bit 1 – PM PM APBA Clock Enable Value Description 0 The APBA clock for the PM is stopped. 1 The APBA clock for the PM is enabled. Bit 0 – PAC PAC APBA Clock Enable Value Description 0 The APBA clock for the PAC is stopped. 1 The APBA clock for the PAC is enabled. SAM L22 Family MCLK – Main Clock © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 141

16.8.8 APBB Mask

Name: APBBMASK Offset: 0x18 Reset: 0x0000004F Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PORT NVMCTRL DSU USB Access R/W R/W R/W R/W Reset 1 1 1 1 Bit 3 – PORT PORT APBB Clock Enable Value Description 0 The APBB clock for the PORT is stopped. 1 The APBB clock for the PORT is enabled. Bit 2 – NVMCTRL NVMCTRL APBB Clock Enable Value Description

0 The APBB clock for the NVMCTRL is stopped

1 The APBB clock for the NVMCTRL is enabled

Bit 1 – DSU DSU APBB Clock Enable Value Description

0 The APBB clock for the DSU is stopped

1 The APBB clock for the DSU is enabled

Bit 0 – USB USB APBB Clock Enable Value Description

0 The APBB clock for the USB is stopped

1 The APBB clock for the USB is enabled

Reserved bits are unused and reserved for future use. For compatibility with future devices, always write reserved bits to their reset value. If no reset value is given, write 0. SAM L22 Family MCLK – Main Clock © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 142

16.8.9 APBC Mask

Name: APBCMASK Offset: 0x1C Reset: 0x0007FFFF Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 CCL TRNG AES Access R/W R/W R/W Reset 1 1 1 Bit 15 14 13 12 11 10 9 8 SLCD PTC AC ADC TC3 TC2 TC1 TC0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 TCC0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 18 – CCL CCL APBC Mask Clock Enable Value Description 0 The APBC clock for the CCL is stopped. 1 The APBC clock for the CCL is enabled. Bit 17 – TRNG TRNG APBC Mask Clock Enable Value Description 0 The APBC clock for the TRNG is stopped. 1 The APBC clock for the TRNG is enabled. Bit 16 – AES AES APBC Mask Clock Enable Value Description 0 The APBC clock for the AES is stopped. 1 The APBC clock for the AES is enabled. Bit 15 – SLCD SLCD Value Description 0 The APBC clock for the SLCD is stopped. 1 The APBC clock for the SLCD is enabled. Bit 14 – PTC PTC APBC Mask Clock Enable Value Description 0 The APBC clock for the PTC is stopped. 1 The APBC clock for the PTC is enabled. Bit 13 – AC AC APBC Mask Clock Enable Value Description 0 The APBC clock for the AC is stopped. SAM L22 Family MCLK – Main Clock © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 143

1 The APBC clock for the AC is enabled. Bit 12 – ADC ADC APBC Mask Clock Enable Value Description 0 The APBC clock for the ADC is stopped. 1 The APBC clock for the ADC is enabled. Bits 8, 9, 10, 11 – TCx TCx APBC Mask Clock Enable Value Description 0 The APBC clock for the TCx is stopped. 1 The APBC clock for the TCx is enabled. Bit 7 – TCC0 TCC0 APBC Mask Clock Enable Value Description 0 The APBC clock for the TCC0 is stopped. 1 The APBC clock for the TCC0 is enabled. Bits 1, 2, 3, 4, 5, 6 – SERCOMx SERCOMx APBC Mask Clock Enable Value Description 0 The APBC clock for the SERCOMx is stopped. 1 The APBC clock for the SERCOMx is enabled. Bit 0 – EVSYS EVSYS APBC Clock Enable Value Description 0 The APBC clock for the EVSYS is stopped. 1 The APBC clock for the EVSYS is enabled. SAM L22 Family MCLK – Main Clock © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 144

FREQM - Frequency Meter

17.1 Overview

The Frequency Meter (FREQM) can be used to accurately measure the frequency of a clock by comparing it to a known reference clock.

17.2 Features

Accurately measures a clock frequency
A selectable reference clock from GCLK_FREQM_REF sources
A selectable clock from GCLK_FREQM_MSR sources can be measured
Ratio can be measured with 24-bit accuracy

17.3 Block Diagram

Figure 17-1. FREQM Block Diagram ENABLE VALUE REFNUM INTFLAG GCLK_FREQM_REF GCLK_FREQM_MSR DONE START COUNTER TIMER CLK_MSR CLK_REF EN EN

17.4 Signal Description

Not applicable.

17.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below. SAM L22 Family FREQM - Frequency Meter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 145

17.5.1 I/O Lines

Not applicable.

17.5.2 Power Management

The FREQM will continue to operate in idle sleep mode where the selected source clock is running. The FREQM’s interrupts can be used to wake up the device from idle sleep mode. Refer to the 19. PM - Power Manager chapter for details on the different sleep modes.

17.5.3 Clocks

The clock for the FREQM bus interface (CLK_APB_FREQM) is enabled and disabled by the Main Clock Controller, Two generic clocks are used by the FREQM(GCLK_FREQM_REF and GCLK_FREQM_MSR). The reference clock (GCLK_FREQM_REF) is required to clock the internal reference timer while operating as a frequency reference, while the measurement clock (GCLK_FREQM_MSR) is required to clock a ripple counter for frequency measurement. These clocks must be configured and enabled in the Generic Clock Controller before using the FREQM.

17.5.4 DMA

Not applicable.

17.5.5 Interrupts

The interrupt request line is connected to the Nested Vector Interrupt Controller. Using FREQM interrupt requires the interrupt controller to be configured first.

17.5.6 Events

Not applicable.

17.5.7 Debug Operation

When the CPU is halted in debug mode the FREQM continues its normal operation. The FREQM cannot be halted when the CPU is halted in debug mode. If the FREQM is configured in a way that requires it to be periodically serviced by the CPU, improper operation or data loss may result during debugging.

17.5.8 Register Access Protection

All registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC), except the following registers:

Control B register (CTRLB)
Interrupt Flag Status and Clear register (INTFLAG)
Status register (STATUS) Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger.

17.6 Functional Description

17.6.1 Principle of Operation

During a period of REFNUM/f CLK_REF, the FREQM is counting the number of periods of the clock to be measured, VALUE. Here, REFNUM is the Number of Reference Clock Cycles selected in the Configuration A register (CFGA.REFNUM), VALUE is the Measurement result stored to the Value register (VALUE.VALUE), and f CLK_REF is the frequency of the reference clock. The frequency of the measured clock, f CLK_MSR, is calculated by SAM L22 Family FREQM - Frequency Meter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 146

f CLK_MSR = VALUE REFNUM f CLK_REF

17.6.2 Basic Operation

17.6.2.1 Initialization

Before enabling FREQM, the device and peripheral must be configured:

Each of the generic clocks (GCLK_FREQM_REF and GCLK_FREQM_MSR) should be configured and enabled. Note that the reference clock should be slower than the measurement clock.
The Number of Reference Clock Cycles value in the Configuration A register ( CFGA.REFNUM) must be written to a value greater than 0x00. The following register is enable-protected, meaning that it can only be written when the FREQM is disabled (CTRLA.ENABLE is zero):
Configuration A register ( CFGA) Enable-protection is denoted by the "Enable-Protected" property in the register description. For further information, refer to the GCLK.

17.6.2.2 Enabling, Disabling and Resetting

The FREQM is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The peripheral is disabled by writing CTRLA.ENABLE=0. The FREQM is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). On software reset, all registers in the FREQM will be reset to their initial state, and the FREQM will be disabled. Then ENABLE and SWRST bits are write-synchronized. For more information, refer to Synchronization.

17.6.2.3 Measurement

In the Configuration A register, the Number of Reference Clock Cycles field (CFGA.REFNUM) selects the duration of the measurement. The measurement is given in number of GCLK_FREQM_REF periods. Note: The REFNUM field must be written before the FREQM is enabled. After the FREQM is enabled, writing a '1' to the START bit in the Control B register (CTRLB.START) starts the measurement. The BUSY bit in Status register (STATUS.BUSY) is cleared when the measurement is done. There is also an interrupt request for Measurement Done: When the Measurement Done bit in Interrupt Enable Set register (INTENSET.DONE) is '1' and a measurement is finished, the Measurement Done bit in the Interrupt Flag Status and Clear register (INTFLAG.DONE) will be set and an interrupt request is generated. The result of the measurement can be read from the Value register (VALUE.VALUE). The frequency of the measured clock GCLK_FREQM_MSR is then: f CLK_MSR = VALUE REFNUM f CLK_REF Note: In order to make sure the measurement result (VALUE.VALUE[23:0]) is valid, the overflow status (STATUS.OVF) should be checked. In case an overflow condition occurred, indicated by the Overflow bit in the STATUS register (STATUS.OVF), either the number of reference clock cycles must be reduced (CFGA.REFNUM), or a faster reference clock must be configured. Once the configuration is adjusted, clear the overflow status by writing a '1' to STATUS.OVF. Then another measurement can be started by writing a '1' to CTRLB.START.

17.6.3 DMA Operation

Not applicable.

17.6.4 Interrupts

The FREQM has one interrupt source:

DONE: A frequency measurement is done SAM L22 Family FREQM - Frequency Meter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 147

Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the FREQM is reset. See INTFLAG for details on how to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. The user must read the INTFLAG register to determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be generated.

17.6.5 Events

Not applicable.

17.6.6 Sleep Mode Operation

The FREQM will continue to operate in idle sleep modes where the selected source clock is running. The FREQM’s interrupts can be used to wake up the device from idle sleep modes. For lowest chip power consumption in sleep modes, FREQM should be disabled before entering a sleep mode. For further information, refer to the Power Manager.

17.6.7 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits and registers are write-synchronized:

Software Reset bit in Control A register (CTRLA.SWRST)
Enable bit in Control A register (CTRLA.ENABLE) Required write synchronization is denoted by the "Write-Synchronized" property in the register description. For more information refer to Register Synchronization. SAM L22 Family FREQM - Frequency Meter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 148

17.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 ENABLE SWRST 0x01 CTRLB 7:0 START 0x02 CFGA 7:0 REFNUM[7:0] 15:8 0x04 ... 0x07 Reserved 0x08 INTENCLR 7:0 DONE 0x09 INTENSET 7:0 DONE 0x0A INTFLAG 7:0 DONE 0x0B STATUS 7:0 OVF BUSY 0x0C SYNCBUSY 7:0 ENABLE SWRST 15:8 23:16 31:24 0x10 VALUE 7:0 VALUE[7:0] 15:8 VALUE[15:8] 23:16 VALUE[23:16] 31:24

17.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read- Synchronized" and/or "Write-Synchronized" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable protection is denoted by the "Enable-Protected" property in each individual register description. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the "PAC Write-Protection" property in each individual register description. SAM L22 Family FREQM - Frequency Meter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 149

17.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 ENABLE SWRST Access R/W R/W Reset 0 0 Bit 1 – ENABLE Enable Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled or disabled. The value written to CTRLA.ENABLE will read back immediately and the ENABLE bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. Value Description 0 The peripheral is disabled. 1 The peripheral is enabled. Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the FREQM to their initial state, and the FREQM will be disabled. Writing a '1' to this bit will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the Reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will be cleared when the Reset is complete. Value Description 0 There is no ongoing Reset operation. 1 The Reset operation is ongoing. SAM L22 Family FREQM - Frequency Meter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 150

17.8.2 Control B

Name: CTRLB Offset: 0x01 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 START Access W Reset 0 Bit 0 – START Start Measurement Value Description 0 Writing a '0' has no effect. 1 Writing a '1' starts a measurement. SAM L22 Family FREQM - Frequency Meter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 151

17.8.3 Configuration A

Name: CFGA Offset: 0x02 Reset: 0x0000 Property: PAC Write-Protection, Enable-protected Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 REFNUM[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – REFNUM[7:0] Number of Reference Clock Cycles Selects the duration of a measurement in number of CLK_FREQM_REF cycles. This must be a non-zero value, i.e. 0x01 (one cycle) to 0xFF (255 cycles). SAM L22 Family FREQM - Frequency Meter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 152

17.8.4 Interrupt Enable Clear

Name: INTENCLR Offset: 0x08 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DONE Access R/W Reset 0 Bit 0 – DONE Measurement Done Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Measurement Done Interrupt Enable bit, which disables the Measurement Done interrupt. Value Description 0 The Measurement Done interrupt is disabled. 1 The Measurement Done interrupt is enabled. SAM L22 Family FREQM - Frequency Meter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 153

17.8.5 Interrupt Enable Set

Name: INTENSET Offset: 0x09 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DONE Access R/W Reset 0 Bit 0 – DONE Measurement Done Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Measurement Done Interrupt Enable bit, which enables the Measurement Done interrupt. Value Description 0 The Measurement Done interrupt is disabled. 1 The Measurement Done interrupt is enabled. SAM L22 Family FREQM - Frequency Meter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 154

17.8.6 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x0A Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 DONE Access R/W Reset 0 Bit 0 – DONE Mesurement Done This flag is cleared by writing a '1' to it. This flag is set when the STATUS.BUSY bit has a one-to-zero transition. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the DONE interrupt flag. SAM L22 Family FREQM - Frequency Meter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 155

17.8.7 Status

Name: STATUS Offset: 0x0B Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 OVF BUSY Access R/W R Reset 0 0 Bit 1 – OVF Sticky Count Value Overflow This bit is cleared by writing a '1' to it. This bit is set when an overflow condition occurs to the value counter. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the OVF status. Bit 0 – BUSY FREQM Status Value Description 0 No ongoing frequency measurement. 1 Frequency measurement is ongoing. SAM L22 Family FREQM - Frequency Meter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 156

17.8.8 Synchronization Busy

Name: SYNCBUSY Offset: 0x0C Reset: 0x00000000 Property: – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ENABLE SWRST Access R R Reset 0 0 Bit 1 – ENABLE Enable This bit is cleared when the synchronization of CTRLA.ENABLE is complete. This bit is set when the synchronization of CTRLA.ENABLE is started. Bit 0 – SWRST Synchronization Busy This bit is cleared when the synchronization of CTRLA.SWRST is complete. This bit is set when the synchronization of CTRLA.SWRST is started. SAM L22 Family FREQM - Frequency Meter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 157

17.8.9 Value

Name: VALUE Offset: 0x10 Reset: 0x00000000 Property: – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 VALUE[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 VALUE[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 VALUE[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 23:0 – VALUE[23:0] Measurement Value Result from measurement. SAM L22 Family FREQM - Frequency Meter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 158

RSTC – Reset Controller

18.1 Overview

The Reset Controller (RSTC) manages the reset of the microcontroller. It issues a microcontroller reset, sets the device to its initial state and allows the reset source to be identified by software.

18.2 Features

Reset the microcontroller and set it to an initial state according to the reset source
Reset cause register for reading the reset source from the application code
Multiple reset sources – Power supply reset sources: POR, BOD12, BOD33 – User reset sources: External reset (RESETN pin), Watchdog reset, and System Reset Request – Backup exit sources: Real-Time Counter (RTC) and Battery Backup Power Switch (BBPS)

18.3 Block Diagram

Figure 18-1. Reset System RESET CONTROLLER BOD12 BOD33 POR WDT RESETN RESET SOURCES RTC 32KHz clock sources WDT with ALWAYSON GCLK with WRTLOCK Debug Logic Other ModulesCPU RCAUSE RTC BBPS SUPC BKUPEXIT BACKUP EXIT

18.4 Signal Description

Signal Name Type Description RESETN Digital input External reset pin One signal can be mapped on several pins. SAM L22 Family RSTC – Reset Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 159

18.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

18.5.1 I/O Lines

Not applicable.

18.5.2 Power Management

The Reset Controller module is always on.

18.5.3 Clocks

The RSTC bus clock (CLK_RSTC_APB) can be enabled and disabled in the Main Clock Controller.

18.5.4 DMA

Not applicable.

18.5.5 Interrupts

Not applicable.

18.5.6 Events

Not applicable.

18.5.7 Debug Operation

When the CPU is halted in debug mode, the RSTC continues normal operation.

18.5.8 Register Access Protection

All registers with write access can be optionally write-protected by the Peripheral Access Controller (PAC). Note: Optional write protection is indicated by the "PAC Write Protection" property in the register description. When the CPU is halted in debug mode, all write protection is automatically disabled. Write protection does not apply for accesses through an external debugger.

18.5.9 Analog Connections

Not applicable.

18.6 Functional Description

18.6.1 Principle of Operation

The Reset Controller collects the various Reset sources and generates Reset for the device.

18.6.2 Basic Operation

18.6.2.1 Initialization

After a power-on Reset, the RSTC is enabled and the Reset Cause (RCAUSE) register indicates the POR source.

18.6.2.2 Enabling, Disabling, and Resetting

The RSTC module is always enabled.

18.6.2.3 Reset Causes and Effects

The latest Reset cause is available in RCAUSE register, and can be read during the application boot sequence in order to determine proper action. These are the groups of Reset sources: SAM L22 Family RSTC – Reset Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 160

Power supply Reset: Resets caused by an electrical issue. It covers POR and BODs Resets
User Reset: Resets caused by the application. It covers external Resets, system Reset requests and watchdog Resets
Backup reset: Resets caused by a Backup Mode exit condition The following table lists the parts of the device that are reset, depending on the Reset type. Table 18-1. Effects of the Different Reset Causes Power Supply Reset User Reset Backup Reset POR, BOD33 BOD12 External Reset WDT Reset, System Reset Request RTC, BBPS RTC, OSC32KCTRL, RSTC, CTRLA.IORET bit of PM Y N N N N GCLK with WRTLOCK Y Y N N Y Debug logic Y Y Y N Y Others Y Y Y Y Y The external Reset is generated when pulling the RESET pin low. The POR, BOD12, and BOD33 Reset sources are generated by their corresponding module in the Supply Controller Interface (SUPC). The WDT Reset is generated by the Watchdog Timer. The System Reset Request is a Reset generated by the CPU when asserting the SYSRESETREQ bit located in the Reset Control register of the CPU (for details refer to the ARM® Cortex™ Technical Reference Manual on http:// www.arm.com). From Backup Mode, the chip can be waken-up upon these conditions:
Battery Backup Power Switch (BBPS): generated by the SUPC controller when the 3.3V VDDIO is restored.
Real-Time Counter interrupt. For details refer to the applicable INTFLAG in the RTC for details. If one of these conditions is triggered in Backup Mode, the RCAUSE.BACKUP bit is set and the Backup Exit Register (BKUPEXIT) is updated.

18.6.3 Additional Features

Not applicable.

18.6.4 DMA Operation

Not applicable.

18.6.5 Interrupts

Not applicable.

18.6.6 Events

Not applicable.

18.6.7 Sleep Mode Operation

18.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 RCAUSE 7:0 BACKUP SYST WDT EXT BOD33 BOD12 POR 0x01 Reserved 0x02 BKUPEXIT 7:0 BBPS RTC

18.8 Register Description

18.8.1 Reset Cause

Name: RCAUSE Offset: 0x00 Reset: Latest Reset Source Property: – When a Reset occurs, the bit corresponding to the Reset source is set to '1' and all other bits are written to '0'. Bit 7 6 5 4 3 2 1 0 BACKUP SYST WDT EXT BOD33 BOD12 POR Access R R R R R R R Reset x x x x x x x Bit 7 – BACKUP Backup Reset This bit is set if a Backup Reset has occurred. Refer to BKUPEXIT register to identify the source of the Backup Reset. Bit 6 – SYST System Reset Request This bit is set if a System Reset Request has occurred. Refer to the Cortex processor documentation for more details. Bit 5 – WDT Watchdog Reset This bit is set if a Watchdog Timer Reset has occurred. Bit 4 – EXT External Reset This bit is set if an external Reset has occurred. Bit 2 – BOD33 Brown Out 33 Detector Reset This bit is set if a BOD33 Reset has occurred. Bit 1 – BOD12 Brown Out 12 Detector Reset This bit is set if a BOD12 Reset has occurred. Bit 0 – POR Power On Reset This bit is set if a POR has occurred. SAM L22 Family RSTC – Reset Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 163

18.8.2 Backup Exit Source

Name: BKUPEXIT Offset: 0x02 Reset: Latest Backup Exit Source Property: – When a Backup Reset occurs, the bit corresponding to the exit condition is set to '1', the other bits are written to '0'. In some specific cases, the RTC and BBPS bits can be set together, e.g. when the device leaves the battery Backup Mode caused by a BBPS condition, and a RTC event was generated during the Battery Backup Mode period. Bit 7 6 5 4 3 2 1 0 BBPS RTC Access R R Reset x x Bit 2 – BBPS Battery Backup Power Switch This bit is set if the Battery Backup Power Switch of the Supply Controller changes back from battery mode to main power mode. Bit 1 – RTC Real Timer Counter Interrupt This bit is set if an RTC interrupt flag is set in Backup Mode. For more information, refer to the 24. RTC – Real-Time Counter. SAM L22 Family RSTC – Reset Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 164

PM - Power Manager

19.1 Overview

The Power Manager (PM) controls the sleep modes of the device. Various sleep modes are provided in order to fit power consumption requirements. This enables the PM to stop unused modules in order to save power. In active mode, the CPU is executing application code. When the device enters a sleep mode, program execution is stopped and some modules and clock domains are automatically switched off by the PM according to the sleep mode. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals and all enabled reset sources can restore the device from a sleep mode to active mode. Performance level technique consists of adjusting the regulator output voltage to reduce power consumption. The user can select on the fly the performance level configuration which best suits the application. In backup mode, the PM allows retaining the state of the I/O lines, preventing I/O lines from toggling during wake-up.

19.2 Features

Power management control – Sleep modes: Idle, Standby, Backup, and Off – Performance levels: PL0 and PL2 – SleepWalking available in Standby mode. – I/O lines retention in Backup mode

19.3 Block Diagram

Figure 19-1. PM Block Diagram SLEEP MODE CONTROLLER PERFORMANCE LEVEL CONTROLLER SUPPLY CONTROLLER MAIN CLOCK CONTROLLER SLEEPCFG PLCF POWER DOMAIN CONTROLLER POWER MANAGER STDBYCFG POWER LEVEL SWITCHES FOR POWER DOMAINS

19.4 Signal Description

Not applicable.

19.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

19.5.1 I/O Lines

19.5.2 Clocks

The PM bus clock (CLK_PM_APB) can be enabled and disabled in the Main Clock module. If this clock is disabled, it can only be re-enabled by a system reset.

19.5.3 DMA

Not applicable.

19.5.4 Interrupts

The interrupt request line is connected to the interrupt controller. Using the PM interrupt requires the interrupt controller to be configured first.

19.5.5 Events

Not applicable.

19.5.6 Debug Operation

When the CPU is halted in debug mode, the PM continues normal operation. If standby sleep mode is requested by the system while in debug mode, the power domains are not turned off. As a consequence, power measurements while in debug mode are not relevant. If Backup sleep mode is requested by the system while in debug mode, the core domains are kept on, and the debug modules are kept running to allow the debugger to access internal registers. When exiting the backup mode upon a reset condition, the core domains are reset except the debug logic, allowing users to keep using their current debug session. Hot plugging in standby mode is supported. Cold or Hot plugging in OFF or Backup mode is not supported.

19.5.7 Register Access Protection

Registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC). PAC write protection is not available for the following registers:

Interrupt Flag register (INTFLAG). Optional PAC write protection is denoted by the "PAC Write-Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger.

19.5.8 Analog Connections

Not applicable.

19.6 Functional Description

19.6.1 Terminology

The following is a list of terms used to describe the Power Managemement features of this microcontroller.

19.6.1.1 Performance Levels

To help balance between performance and power consumption, the device has two performance levels. Each of the performance levels has a maximum operating frequency and a corresponding maximum consumption in µA/MHz. It is the application's responsibility to configure the appropriate PL depending on the application activity level. When the application selects a new PL, the voltage applied on the full logic area moves from one value to another. This voltage scaling technique allows to reduce the active power consumption while decreasing the maximum frequency of the device.

19.6.1.1.1 PL0

Performance Level 0 (PL0) provides the maximum energy efficiency configuration. SAM L22 Family PM - Power Manager © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 166

Refer to the Electrical Characteristics chapters for details on energy consumption and maximum operating frequency.

19.6.1.1.2 PL2

Performance Level 2 (PL2) provides the maximum operating frequency. Refer to the Electrical Characteristics chapters for details on energy consumption and maximum operating frequency.

19.6.1.2 Power Domains

In addition to the supply domains, such as VDDIO and VDDANA, the device provides these power domains:

PDTOP
PDBACKUP

19.6.1.2.1 PDTOP

PDTOP contains all controllers located in the core domain. It is powered when in Active, Idle or Standby mode. When in Backup or Off mode, this domain is completely powered down.

19.6.1.2.2 PDBACKUP

The Backup Power Domain (PDBACKUP) is always on, except in the off sleep mode. It contains the 32KHz oscillator sources, the Supply Controller, the Reset Controller, the Real Time Counter, and the Power Manager itself.

19.6.1.3 Sleep Modes

The device can be set in a sleep mode. In sleep mode, the CPU is stopped and the peripherals are either active or idle, according to the sleep mode depth:

Idle sleep mode: The CPU is stopped. Synchronous clocks are stopped except when requested. The logic is retained.
Standby sleep mode: The CPU is stopped as well as the peripherals.
Backup sleep mode: Only the backup domain is kept powered to allow few features to run (RTC, 32KHz clock sources, and wake-up from external pins).
Off sleep mode: The entire device is powered off.

19.6.2 Principle of Operation

In active mode, all clock domains and power domains are active, allowing software execution and peripheral operation. The PM Sleep Mode Controller allows to save power by choosing between different sleep modes The PM Performance Level Controller allows to optimize either for low power consumption or high performance. The PM Power Domain Controller allows to reduce the power consumption in standby mode even further.

19.6.3 Basic Operation

19.6.3.1 Initialization

After a Power-on Reset (POR), the PM is enabled, the device is in Active mode, the performance level is PL0 (the lowest power consumption) and all the power domains are in active state.

19.6.3.2 Enabling, Disabling and Resetting

The PM is always enabled and can not be reset.

19.6.3.3 Sleep Mode Controller

Sleep mode is entered by executing the Wait For Interrupt instruction (WFI). The Sleep Mode bits in the Sleep Configuration register (SLEEPCFG.SLEEPMODE) select the level of the sleep mode. Note: A small latency happens between the store instruction and actual writing of the SLEEPCFG register due to bridges. Software must ensure that the SLEEPCFG register reads the desired value before issuing a WFI instruction. Table 19-1. Sleep Mode Entry and Exit Table Mode Mode Entry Wake-Up Sources IDLE SLEEPCFG.SLEEPMODE = IDLE Synchronous (2) (APB, AHB), asynchronous (1) SAM L22 Family PM - Power Manager © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 167

Mode Mode Entry Wake-Up Sources STANDBY SLEEPCFG.SLEEPMODE = STANDBY Synchronous(3), Asynchronous BACKUP SLEEPCFG.SLEEPMODE = BACKUP Backup reset detected by the RSTC OFF SLEEPCFG.SLEEPMODE = OFF External Reset Notes: 1. Asynchronous: interrupt generated on generic clock, external clock, or external event. 2. Synchronous: interrupt generated on the APB clock. 3. Synchronous interrupt only for peripherals configured to run in standby. Note: The type of wake-up sources (synchronous or asynchronous) is given in each module interrupt section. The sleep modes (idle, standby, backup, and off) and their effect on the clocks activity, the regulator and the NVM state are described in the table and the sections below. Table 19-2. Sleep Mode Overview Mode Main clock CPU AHBx and APBx clock GCLK clocks Oscillators Regulator NVM ONDEMAND = 0 ONDEMAND = 1 Active Run Run Run Run(3) Run Run if requested MAINVREG active IDLE Run Stop Stop(1) Run(3) Run Run if requested MAINVREG active STANDBY Stop(1) Stop Stop(1) Stop(1) Run if requested or RUNSTDBY=1 Run if requested MAINVREG in low power mode Ultra Low- power BACKUP Stop Stop Stop Stop Stop Stop Backup regulator ( LPVREG) OFF OFF Stop Stop Stop OFF OFF OFF OFF OFF Notes: 1. Running if requested by peripheral during SleepWalking. 2. Running during SleepWalking. 3. Following On-Demand Clock Request principle.

19.6.3.3.1 IDLE Mode

IDLE mode allows power optimization with the fastest wake-up time. The CPU is stopped, and peripherals are still working. As in Active mode, the AHBx and APBx clocks for peripheral are still provided if requested. As the main clock source is still running, wake-up time is very fast.

Entering Idle mode: The Idle mode is entered by executing the WFI instruction. Additionally, if the SLEEPONEXIT bit in the Cortex System Control register (SCR) is set, the Idle mode will be entered when the CPU exits the lowest priority ISR (Interrupt Service Routine, refer to the ARM Cortex documentation for details). This mechanism can be useful for applications that only require the processor to run when an interrupt occurs. Before entering the Idle mode, the user must select the Idle Sleep mode in the Sleep Configuration register (SLEEPCFG.SLEEPMODE=IDLE).
Exiting Idle mode: The processor wakes the system up when it detects any non-masked interrupt with sufficient priority to cause exception entry. The system goes back to the Active mode. The CPU and affected modules are restarted. GCLK clocks, regulators and RAM are not affected by the Idle Sleep mode and operate in normal mode.

19.6.3.3.2 STANDBY Mode

The Standby mode is the lowest power configuration while keeping the state of the logic and the content of the RAM. SAM L22 Family PM - Power Manager © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 168

In this mode, all clocks are stopped except those configured to be running sleepwalking tasks. The clocks can also be active on request or at all times, depending on their on-demand and run-in-standby settings. Either synchronous (CLK_APBx or CLK_AHBx) or generic (GCLK_x) clocks or both can be involved in sleepwalking tasks. This is the case when for example the SERCOM RUNSTDBY bit is written to '1'.

Entering Standby mode: This mode is entered by executing the WFI instruction after writing the Sleep Mode bit in the Sleep Configuration register (SLEEPCFG.SLEEPMODE=STANDBY). The SLEEPONEXIT feature is also available as in Idle mode.
Exiting Standby mode: Any peripheral able to generate an asynchronous interrupt can wake up the system. For example, a peripheral running on a GCLK clock can trigger an interrupt. When the enabled asynchronous wake-up event occurs and the system is woken up, the device will either execute the interrupt service routine or continue the normal program execution according to the Priority Mask Register (PRIMASK) configuration of the CPU. The regulator operates in Low-Power mode by default and switches automatically to the normal mode in case of a sleepwalking task requiring more power. It returns automatically to low power mode when the sleepwalking task is completed.

19.6.3.3.3 BACKUP Mode

The BACKUP mode allows achieving the lowest power consumption aside from OFF. The device is entirely powered off except for the backup domain. All peripherals in backup domain are allowed to run, e.g. the RTC can be clocked by a 32.768kHz oscillator. All PM registers are reset except the CTRLA.IORET bit.

Entering Backup mode: This mode is entered by executing the WFI instruction after selecting the Backup mode by writing the Sleep Mode bits in the Sleep Configuration register (SLEEPCFG.SLEEPMODE=BACKUP).
Exiting Backup mode: is triggered when a Backup Reset is detected by the Reset Controller (RSTC).

19.6.3.3.4 OFF Mode

In Off mode, the device is entirely powered-off.

Entering Off mode: This mode is entered by selecting the Off mode in the Sleep Configuration register by writing the Sleep Mode bits (SLEEPCFG.SLEEPMODE=OFF), and subsequent execution of the WFI instruction.
Exiting Off mode: This mode is left by pulling the RESET pin low, or when a power Reset is done.

19.6.3.4 I/O Lines Retention in BACKUP Mode

When entering BACKUP mode, the PORT is powered off but the pin configuration is retained. When the device exits the BACKUP mode, the I/O line configuration can either be released or stretched, based on the I/O Retention bit in the CTRLA register (CTRLA.IORET).

If IORET=0 when exiting BACKUP mode, the I/O lines configuration is released and driven by the reset value of the PORT.
If the IORET=1 when exiting BACKUP mode, the configuration of the I/O lines is retained until the IORET bit is written to 0. It allows the I/O lines to be retained until the application has programmed the PORT.

19.6.3.5 Performance Level

The application can change the performance level on the fly writing to the by Performance Level Select bit in the Performance Level Configuration register (PLCFG.PLSEL). When changing to a lower performance level, the bus frequency must be reduced before writing PLCFG.PLSEL in order to avoid exceeding the limit of the target performance level. When changing to a higher performance level, the bus frequency can be increased only after the Performance Level Ready flag in the Interrupt Flag Status and Clear (INTFLAG.PLRDY) bit set to '1', indicating that the performance level transition is complete. After a reset, the device starts in the lowest PL (lowest power consumption and lowest max frequency). The application can then switch to another PL at anytime without any stop in the code execution. As shown in Figure 19-2, performance level transition is possible only when the device is in active mode. The Performance Level Disable bit in the Performance Level Configuration register (PLCFG.PLDIS) can be used to freeze the performance level to PL0. This disables the performance level hardware mechanism in order to reduce both the power consumption and the wake-up startup time from standby sleep mode. SAM L22 Family PM - Power Manager © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 169

Note: This bit PLCFG.PLDIS must be changed only when the current performance level is PL0. Any attempt to modify this bit while the performance level is not PL0 is discarded and a violation is reported to the PAC module. Any attempt to change the performance level to PLn (with n>0) while PLCFG.PLDIS=1 is discarded and a violation is reported to the PAC module. Figure 19-2. Sleep Modes and Performance Level Transitions BACKUP ACTIVE PLn IDLE PLn SLEEPCFG. IDLE IRQ SLEEPCFG. STANDBY IRQ SLEEPCFG. BACKUP OFF ACTIVE PL0 RESET PLCFG.PLSEL STANDBYBackup Reset ext reset SLEEPCFG. OFF

19.6.3.6 Regulators, RAMs, and NVM State in Sleep Mode

By default, in Standby Sleep mode and backup sleep mode, the RAMs, NVM, and regulators are automatically set in Low-Power mode to reduce power consumption:

The RAM is in Low-Power mode if the device is in standby mode. Refer to RAM Automatic Low Power Mode for details.
Non-Volatile Memory - the NVM is automatically set in low power mode in these conditions: – When the device is in Standby Sleep mode and the NVM is not accessed. This behavior can be changed by software by configuring the SLEEPPRM bit group of the CTRLB register in the NVMCTRL peripheral. SAM L22 Family PM - Power Manager © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 170

– When the device is in Idle Sleep mode and the NVM is not accessed. This behavior can be changed by software by configuring the SLEEPPRM bit group of the CTRLB register in the NVMCTRL peripheral.

Regulators: by default, in Standby Sleep mode, the PM analyzes the device activity to use either the main or the low-power voltage regulator to supply the VDDCORE. GCLK clocks, regulators and RAM are not affected in Idle Sleep mode and will operate as normal. Table 19-3. Regulators, RAMs, and NVM state in Sleep Mode Sleep Mode SRAM Mode(1) NVM Regulators VDDCORE VDDBU main ULP Active normal normal on on on Idle auto(2) on on on on Standby - case 1 normal auto(2) auto(3) on on Standby - case 2 low power low power auto(3) on on Standby - case 3 low power low power auto(3) on on Standby - case 4 low power low power off on on Backup off off off off on Off off off off off off Notes: 1. RAMs mode by default: STDBYCFG.BBIAS bits are set to their default value. 2. auto: by default, NVM is in low-power mode if not accessed. 3. auto: by default, the main voltage regulator is on if GCLK, APBx, or AHBx clock is running during SleepWalking. Related Links: RAM Automatic Low Power Mode Regulator Automatic Low Power Mode

19.6.4 Advanced Features

19.6.4.1 RAM Automatic Low Power Mode

The RAM is by default put in low power mode (back-biased) if the device is in standby sleep mode. This behavior can be changed by configuring the Back Bias bit groups in the Standby Configuration register (STDBYCFG.BBIASxx), refer to the table below for details. Note: In standby sleep mode, the RAM is put in low-power mode by default. This means that the RAM is back-biased, and the DMAC cannot access it. The DMAC can only access the RAM when it is not back biased (PM.STDBYCFG.BBIASxx=0x0). Table 19-4. RAM Back-Biasing Mode STBYCDFG.BBIASxx config RAM 0x0 No Back Biasing mode No Back Biasing in Standby mode 0x1 Standby Back Biasing mode RAM is back-biased if the device is in standby sleep mode 0x2 Standby OFF mode RAM is OFF if the device is in standby sleep mode 0x3 Always OFF mode RAM is OFF if its power domain is in retention state SAM L22 Family PM - Power Manager © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 171

19.6.4.2 Regulator Automatic Low-Power Mode

In Standby mode, the PM selects either the main or the low-power voltage regulator to supply the VDDCORE. If a sleepwalking task is working on either asynchronous clocks (generic clocks) or synchronous clock (APB/AHB clocks), the main voltage regulator is used. This behavior can be changed by writing the Voltage Regulator Standby Mode bits in the Standby Configuration register (STDBYCFG.VREGSMOD). Refer to the following table for details. Table 19-5. Regulator State in Sleep Mode Sleep Modes STDBYCFG. VREGSMOD SleepWalking(1) Regulator state for VDDCORE Active - - main voltage regulator Idle - - main voltage regulator Standby 0x0: AUTO NO low-power regulator YES main voltage regulator 0x1: PERFORMANCE - main voltage regulator 0x2: LP(2) -(2) low-power regulator Notes: 1. SleepWalking is running on GCLK clock or synchronous clock. This is not related to XOSC32K or OSCULP32K clocks. 2. Must only be used when SleepWalking is running on GCLK with 32.768 kHz source.

19.6.4.3 SleepWalking and Performance Level

SleepWalking is the capability for a device to temporarily wake up clocks for a peripheral to perform a task without waking up the CPU from STANDBY sleep mode. At the end of the sleepwalking task, the device can either be woken up by an interrupt (from a peripheral involved in SleepWalking) or enter again into STANDBY sleep mode. In this device, SleepWalking is supported only on GCLK clocks by using the on-demand clock principle of the clock sources. In standby mode, when SleepWalking is ongoing, the performance level used to execute the sleepwalking task is the current configured performance level (used in active mode), and the main voltage regulator used to execute the SleepWalking task is the selected regulator used in active mode (LDO or Buck converter). These are illustrated in the figure below. SAM L22 Family PM - Power Manager © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 172

Figure 19-3. Operating Conditions and SleepWalking BUCKLDO STANDBY BACKUP SleepWalkingPL0 ACTIVE ACTIVE RESET IDLE ACTIVE IDLE IDLE STANDBY PL0 PL2 BACKUP RESET SUPC.VREG.SEL LP VREG MAIN VREG OFF LDO BUCK Regulator modes SleepWalkingPL2 Performance Level Sleep Mode Sleep Mode

19.6.4.4 Wake-Up Time

The total wake-up time depends on the following:

Latency due to Performance Level and Regulator effect: Performance Level has to be taken into account for the global wake-up time. As example, if PL2 is selected and the device is in Standby Sleep mode, the voltage level supplied by the ULP voltage regulator is lower than the one used in Active mode. When the device wakes up, it takes a certain amount of time for the main regulator to transition to the voltage level corresponding to PL2, causing additional wake-up time.
Latency due to the CPU clock source wake-up time.
Latency due to the NVM memory access.
Latency due to Switchable Power Domain back-bias wake-up time: If back-bias is enabled, and the device wakes up from retention, it takes a certain amount of time for the regulator to settle.

19.6.5 DMA Operation

Not applicable.

19.6.6 Interrupts

The peripheral has the following interrupt sources:

Performance Level Ready (PLRDY) This interrupt is a synchronous wake-up source. See Table 19-1 for details. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. SAM L22 Family PM - Power Manager © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 173

An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the peripheral is reset. An interrupt flag is cleared by writing a '1' to the corresponding bit in the INTFLAG register. Each peripheral can have one interrupt request line per interrupt source or one common interrupt request line for all the interrupt sources. Refer to the Nested Vector Interrupt Controller (NVIC) for details. If the peripheral has one common interrupt request line for all the interrupt sources, the user must read the INTFLAG register to determine which interrupt condition is present.

19.6.7 Events

Not applicable.

19.6.8 Sleep Mode Operation

19.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 IORET 0x01 SLEEPCFG 7:0 SLEEPMODE[2:0] 0x02 PLCFG 7:0 PLDIS PLSEL[1:0] 0x03 Reserved 0x04 INTENCLR 7:0 PLRDY 0x05 INTENSET 7:0 PLRDY 0x06 INTFLAG 7:0 PLRDY 0x07 Reserved 0x08 STDBYCFG 7:0 VREGSMOD[1:0] 15:8 BBIASHS[1:0]

19.8 Register Description

19.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 IORET Access R/W Reset 0 Bit 2 – IORET I/O Retention Note: This bit is not reset by a backup reset. Value Description 0 After waking up from Backup mode, I/O lines are not held. 1 After waking up from Backup mode, I/O lines are held until IORET is written to 0. SAM L22 Family PM - Power Manager © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 176

19.8.2 Sleep Configuration

Name: SLEEPCFG Offset: 0x01 Reset: 0x02 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 SLEEPMODE[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 2:0 – SLEEPMODE[2:0] Sleep Mode Note: A small latency happens between the store instruction and actual writing of the SLEEPCFG register due to bridges. Software has to make sure the SLEEPCFG register reads the wanted value before issuing WFI instruction. Value Name Definition 0x0 Reserved Reserved 0x1 Reserved Reserved 0x2 IDLE CPU, AHBx, and APBx clocks are OFF 0x3 Reserved Reserved 0x4 STANDBY ALL clocks are OFF, unless requested by sleepwalking peripheral 0x5 BACKUP Only Backup domain is powered ON 0x6 OFF All power domains are powered OFF 0x7 Reserved Reserved SAM L22 Family PM - Power Manager © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 177

19.8.3 Performance Level Configuration

Name: PLCFG Offset: 0x02 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 PLDIS PLSEL[1:0] Access R/W R/W R/W Reset 0 0 0 Bit 7 – PLDIS Performance Level Disable Disabling the PL selection forces the device to run in PL0, reducing the power consumption, and the wake-up time from Standby Sleep mode. Changing this bit when the current performance level is not PL0 is discarded, and a violation is reported to the PAC module. Value Description 0 The Performance Level mechanism is enabled. 1 The Performance Level mechanism is disabled. Bits 1:0 – PLSEL[1:0] Performance Level Select Value Name Definition 0x0 PL0 Performance Level 0 0x1 Reserved Reserved 0x2 PL2 Performance Level 2 0x3 Reserved Reserved SAM L22 Family PM - Power Manager © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 178

19.8.4 Interrupt Enable Clear

Name: INTENCLR Offset: 0x04 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 7 6 5 4 3 2 1 0 PLRDY Access R/W Reset 0 Bit 0 – PLRDY Performance Level Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Performance Ready Interrupt Enable bit and the corresponding interrupt request. Value Description 0 The Performance Ready interrupt is disabled.

1 The Performance Ready interrupt is enabled and will generate an interrupt request when the

19.8.5 Interrupt Enable Set

Name: INTENSET Offset: 0x05 Reset: 0x00 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 7 6 5 4 3 2 1 0 PLRDY Access R/W Reset 0 Bit 0 – PLRDY Performance Level Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Performance Ready Interrupt Enable bit and enable the Performance Ready interrupt. Value Description 0 The Performance Ready interrupt is disabled. 1 The Performance Ready interrupt is enabled. SAM L22 Family PM - Power Manager © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 180

19.8.6 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x06 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 PLRDY Access R/W Reset 0 Bit 0 – PLRDY Performance Level Ready This flag is set when the performance level is ready and will generate an interrupt if INTENCLR/SET.PLRDY is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Performance Ready interrupt flag. SAM L22 Family PM - Power Manager © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 181

19.8.7 Standby Configuration

Name: STDBYCFG Offset: 0x08 Reset: 0x0400 Property: PAC Write-Protection Bit 15 14 13 12 11 10 9 8 BBIASHS[1:0] Access R R Reset 0 0 Bit 7 6 5 4 3 2 1 0 VREGSMOD[1:0] Access R R Reset 0 0 Bits 11:10 – BBIASHS[1:0] Back Bias for HMCRAMCHS Refer to Table 19-4 for details. Value Description

0 No Back Biasing in Standby mode

1 Back Biasing in Standby mode

2 Standby OFF mode

3 Always OFF mode

Bits 7:6 – VREGSMOD[1:0] VREG Switching Mode Value Name Description 0x0 AUTO Automatic Mode 0x1 PERFORMANCE Performance oriented 0x2 LP Low Power consumption oriented SAM L22 Family PM - Power Manager © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 182

OSCCTRL – Oscillators Controller

20.1 Overview

The Oscillators Controller (OSCCTRL) provides a user interface to the XOSC, OSC16M, DFLL48M and FDPLL96M. Through the interface registers, it is possible to enable, disable, calibrate, and monitor the OSCCTRL sub- peripherals. All sub-peripheral statuses are collected in the Status register (STATUS). They can additionally trigger interrupts upon status changes via the INTENSET, INTENCLR, and INTFLAG registers.

20.2 Features

The following are key features of the OSCCTRL module.

0.4-32 MHz Crystal Oscillator (XOSC) – Tunable gain control – Programmable start-up time – Crystal or external input clock on XIN I/O – Clock failure detection with safe clock switch – Clock failure event output
16 MHz Internal Oscillator (OSC16M) – Fast startup – 4/8/12/16 MHz output frequencies available
Digital Frequency Locked Loop (DFLL48M) – Internal oscillator with no external components – 48 MHz output frequency – Operates stand-alone as a high-frequency programmable oscillator in open loop mode – Operates as an accurate frequency multiplier against a known frequency in closed loop mode
Fractional Digital Phase Locked Loop (FDPLL96M) – 48 MHz to 96 MHz output frequency – 32 kHz to 2 MHz reference clock – A selection of sources for the reference clock – Adjustable proportional integral controller – Fractional part used to achieve 1/16th of reference clock step SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 183

20.3 Block Diagram

Figure 20-1. OSCCTRL Block Diagram OSCILLATORS CONTROL STATUS INTERRUPTS GENERATOR Interrupts OSCCTRL XIN XOUT XOSC OSC16M DFLL48M DPLL96M CLK_XOSC CLK_OSC16M CLK_DFLL48M CLK_DPLL CFD CFD Event register

20.4 Signal Description

XIN Multipurpose Crystal Oscillator or external clock generator input Analog input XOUT Multipurpose Crystal Oscillator output Analog output The I/O lines are automatically selected when XOSC is enabled.

20.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

20.5.1 I/O Lines

I/O lines are configured by OSCCTRL when XOSC is enabled, and need no user configuration.

20.5.2 Power Management

The OSCCTRL can continue to operate in any sleep mode where the selected source clock is running. The OSCCTRL interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes. References: 19. PM - Power Manager

20.5.3 Clocks

The OSCCTRL gathers controls for all device oscillators and provides clock sources to the Generic Clock Controller (GCLK). The available clock sources are: XOSC, OSC16M, DFLL48M, and FDPLL96M. The OSCCTRL bus clock (CLK_OSCCTRL_APB) can be enabled and disabled in the Main Clock module (MCLK). The DFLL48M control logic uses the DFLL oscillator output, which is also asynchronous to the user interface clock (CLK_OSCCTRL_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to Synchronization for further details. References: SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 184

20.5.4 DMA

Not applicable.

20.5.5 Interrupts

The interrupt request line is connected to the Interrupt Controller. Using the OSCCTRL interrupts requires the interrupt controller to be configured first.

20.5.6 Events

The events of this peripheral are connected to the Event System.

20.5.7 Debug Operation

When the CPU is halted in debug mode the OSCCTRL continues normal operation. If the OSCCTRL is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging.

20.5.8 Register Access Protection

All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Interrupt Flag Status and Clear register (INTFLAG) Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection does not apply for accesses through an external debugger. References: Peripheral Access Controller

20.5.9 Analog Connections

The 0.4-32MHz crystal must be connected between the XIN and XOUT pins, along with any required load capacitors.

20.6 Functional Description

20.6.1 Principle of Operation

XOSC, OSC16M, DFLL48M, and FDPLL96M are configured via OSCCTRL control registers. Through this interface, the sub-peripherals are enabled, disabled, or have their calibration values updated. The Status register gathers different status signals coming from the sub-peripherals controlled by the OSCCTRL. The status signals can be used to generate system interrupts, and in some cases wake up the system from standby mode, provided the corresponding interrupt is enabled.

20.6.2 External Multipurpose Crystal Oscillator (XOSC) Operation

The XOSC can operate in two different modes:

External clock, with an external clock signal connected to the XIN pin
Crystal oscillator, with an external 0.4-32MHz crystal The XOSC can be used as a clock source for generic clock generators. This is configured by the Generic Clock Controller. At reset, the XOSC is disabled, and the XIN/XOUT pins can be used as General Purpose I/O (GPIO) pins or by other peripherals in the system. When XOSC is enabled, the operating mode determines the GPIO usage. When in crystal oscillator mode, the XIN and XOUT pins are controlled by the OSCCTRL, and GPIO functions are overridden on both SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 185

pins. When in external clock mode, only the XIN pin will be overridden and controlled by the OSCCTRL, while the XOUT pin can still be used as a GPIO pin. The XOSC is enabled by writing a '1' to the Enable bit in the External Multipurpose Crystal Oscillator Control register (XOSCCTRL.ENABLE). To enable XOSC as an external crystal oscillator, the XTAL Enable bit (XOSCCTRL.XTALEN) must written to '1'. If XOSCCTRL.XTALEN is zero, the external clock input on XIN will be enabled. When in crystal oscillator mode (XOSCCTRL.XTALEN=1), the External Multipurpose Crystal Oscillator Gain (XOSCCTRL.GAIN) must be set to match the external crystal oscillator frequency. If the External Multipurpose Crystal Oscillator Automatic Amplitude Gain Control (XOSCCTRL.AMPGC) is '1', the oscillator amplitude will be automatically adjusted, and in most cases result in a lower power consumption. The XOSC will behave differently in different sleep modes, based on the settings of XOSCCTRL.RUNSTDBY, For XOSCCTRL.ENABLE=1, this table is valid: Table 20-1. XOSC Sleep Behavior CPU Mode XOSCCTRL.RUNSTDB Y XOSCCTRL.ONDEMA ND Sleep Behavior Active or Idle - 0 Always run Active or Idle - 1 Run if requested by peripheral Standby 1 0 Always run Standby 1 1 Run if requested by peripheral Standby 0 - Run if requested by peripheral After a hard reset, or when waking up from a sleep mode where the XOSC was disabled, the XOSC will need a certain amount of time to stabilize on the correct frequency. This start-up time can be configured by changing the Oscillator Start-Up Time bit group (XOSCCTRL.STARTUP) in the External Multipurpose Crystal Oscillator Control register. During the start-up time, the oscillator output is masked to ensure that no unstable clock propagates to the digital logic. The External Multipurpose Crystal Oscillator Ready bit in the Status register (STATUS.XOSCRDY) is set once the external clock or crystal oscillator is stable and ready to be used as a clock source. An interrupt is generated on a zero-to-one transition on STATUS.XOSCRDY if the External Multipurpose Crystal Oscillator Ready bit in the Interrupt Enable Set register (INTENSET.XOSCRDY) is set. References: GCLK

20.6.3 Clock Failure Detection Operation

The Clock Failure Detector (CFD) allows the user to monitor the external clock or crystal oscillator signal provided by the external oscillator (XOSC). The CFD detects failing operation of the XOSC clock with reduced latency, and allows to switch to a safe clock source in case of clock failure. The user can also switch from the safe clock back to XOSC in case of recovery. The safe clock is derived from the OSC16M oscillator with a configurable prescaler. This allows to configure the safe clock in order to fulfill the operative conditions of the microcontroller. In sleep modes, CFD operation is automatically disabled when the external oscillator is not requested to run by a peripheral. See the Sleep Behavior table above when this is the case. The user interface registers allow to enable, disable, and configure the CFD. The Status register provides status flags on failure and clock switch conditions. The CFD can optionally trigger an interrupt or an event when a failure is detected. Clock Failure Detection The CFD is reset only at power-on (POR). The CFD does not monitor the XOSC clock when the oscillator is disabled (XOSCCTRL.ENABLE=0). SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 186

Before starting CFD operation, the user must start and enable the safe clock source (OSC16M oscillator). CFD operation is started by writing a '1' to the CFD Enable bit in the External Oscillator Control register (XOCCTRL.CFDEN). After starting or restarting the XOSC, the CFD does not detect failure until the start-up time has elapsed. The start-up time is configured by the Oscillator Start-Up Time in the External Multipurpose Crystal Oscillator Control register (XOSCCTRL.STARTUP). Once the XOSC Start-Up Time is elapsed, the XOSC clock is constantly monitored. During a period of 4 safe clocks (monitor period), the CFD watches for a clock activity from the XOSC. There must be at least one rising and one falling XOSC clock edge during 4 safe clock periods to meet non-failure conditions. If no or insufficient activity is detected, the failure status is asserted: The Clock Failure Detector status bit in the Status register (STATUS.CLKFAIL) and the Clock Failure Detector interrupt flag bit in the Interrupt Flag register (INTFLAG.CLKFAIL) are set. If the CLKFAIL bit in the Interrupt Enable Set register (INTENSET.CLKFAIL) is set, an interrupt is generated as well. If the Event Output enable bit in the Event Control register (EVCTRL.CFDEO) is set, an output event is generated, too. After a clock failure was issued the monitoring of the XOSC clock is continued, and the Clock Failure Detector status bit in the Status register (STATUS.CLKFAIL) reflects the current XOSC activity. Clock Switch When a clock failure is detected, the XOSC clock is replaced by the safe clock in order to maintain an active clock during the XOSC clock failure. The safe clock source is the OSC16M oscillator clock. The safe clock source can be scaled down by a configurable prescaler to ensure that the safe clock frequency does not exceed the operating conditions selected by the application. When the XOSC clock is switched to the safe clock, the Clock Switch bit in the Status register (STATUS.CLKSW) is set. When the CFD has switched to the safe clock, the XOSC is not disabled. If desired, the application must take the necessary actions to disable the oscillator. The application must also take the necessary actions to configure the system clocks to continue normal operations. In the case the application can recover the XOSC, the application can switch back to the XOSC clock by writing a '1' to Switch Back Enable bit in the Clock Failure Control register (XOSCCTRL.SWBACK). Once the XOSC clock is switched back, the Switch Back bit (XOSCCTRL.SWBACK) is cleared by hardware. Prescaler The CFD has an internal configurable prescaler to generate the safe clock from the OSC16M oscillator. The prescaler size allows to scale down the OSC16M oscillator so the safe clock frequency is not higher than the XOSC clock frequency monitored by the CFD. The division factor is 2^P, with P being the value of the CFD Prescaler bits in the CFD Prescaler Register (CFDPRESC.CFDPRESC). Example 20-1. For an external crystal oscillator at 0.4MHz and the OSC16M frequency at 16MHz, the CFDPRESC.CFDPRESC value should be set scale down by more than factor 16/0.4=80, e.g. to 128, for a safe clock of adequate frequency. Event If the Event Output Enable bit in the Event Control register (EVCTRL.CFDEO) is set, the CFD clock failure will be output on the Event Output. When the CFD is switched to the safe clock, the CFD clock failure will not be output on the Event Output. Sleep Mode The CFD is halted depending on configuration of the XOSC and the peripheral clock request. For further details, refer to the Sleep Behavior table above. The CFD interrupt can be used to wake up the device from sleep modes. 20.6.4 16MHz Internal Oscillator (OSC16M) Operation The OSC16M is an internal oscillator operating in open-loop mode and generating 4, 8, 12, or 16MHz frequency. The OSC16M frequency is selected by writing to the Frequency Select field in the OSC16M register (OSC16MCTRL.FSEL). OSC16M is enabled by writing '1' to the Oscillator Enable bit in the OSC16M Control register SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 187

(OSC16MCTRL.ENABLE), and disabled by writing a '0' to this bit. Frequency selection must be done when OSC16M is disabled. After enabling OSC16M, the OSC16M clock is output as soon as the oscillator is ready (STATUS.OSC16MRDY=1). User must ensure that the OSC16M is fully disabled before enabling it by reading STATUS.OSC16MRDY=0. After reset, OSC16M is enabled and serves as the default clock source at 4MHz. OSC16M will behave differently in different sleep modes based on the settings of OSC16MCTRL.RUNSTDBY, OSC16MCTRL.ONDEMAND, and OSC16MCTRL.ENABLE. If OSC16MCTRL.ENABLE=0, the OSC16M will be always stopped. For OSC16MCTRL.ENABLE=1, this table is valid: Table 20-2. OSC16M Sleep Behavior CPU Mode OSC16MCTRL.RUNST DBY OSC16MCTRL.ONDEM AND Sleep Behavior Active or Idle - 0 Always run Active or Idle - 1 Run if requested by peripheral Standby 1 0 Always run Standby 1 1 Run if requested by peripheral Standby 0 - Run if requested by peripheral OSC16M is used as a clock source for the generic clock generators. This is configured by the Generic Clock Generator Controller. References: GCLK

20.6.5 Digital Frequency Locked Loop (DFLL48M) Operation

The DFLL48M can operate in both open-loop mode and closed-loop mode. In closed-loop mode, a low-frequency clock with high accuracy should be used as the DFLL48M reference clock to get high accuracy on the output clock (CLK_DFLL48M). The DFLL48M's output can be used as a source for the generic clock generators (GCLK.GENCTRLn.SRC = DFLL).

20.6.5.1 Basic Operation

20.6.5.1.1 Open-Loop Operation

After any reset, the open-loop mode is selected. When operating in open-loop mode, the output frequency of the DFLL48M clock, CLK_DFLL48M, will be determined by the values written to the DFLL Coarse Value bit group and the DFLL Fine Value bit group (DFLLVAL.COARSE and DFLLVAL.FINE) in the DFLL Value register. Using "DFLL48M COARSE CAL" value from the Non Volatile Memory Software Calibration Area in DFLL.COARSE helps to output a frequency close to 48MHz. It is possible to change the values of DFLLVAL.COARSE and DFLLVAL.FINE while the DFLL48M is enabled and in use, and thereby to adjust the output frequency of CLK_DFLL48M.

20.6.5.1.2 Closed-Loop Operation

In closed-loop operation, the DFLL48M output frequency is continuously regulated against a precise reference clock of relatively low frequency. This will improve the accuracy and stability of the CLK_DFLL48M clock in comparison to the open-loop (free-running) configuration. Before closed-loop operation can be enabled, the DFLL48M must be enabled and configured in the following way: 1. Enable and select a reference clock (CLK_DFLL48M_REF). CLK_DFLL48M_REF is Generic Clock Channel 0 (DFLL48M_Reference). 2. Select the maximum step size allowed for finding the Coarse and Fine values by writing the appropriate values to the DFLL Coarse Maximum Step and DFLL Fine Maximum Step bit groups (DFLLMUL.CSTEP and DFLLMUL.FSTEP) in the DFLL Multiplier register. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 188

A small step size will ensure low overshoot on the output frequency, but it will typically take longer until locking is achieved. A high value might give a large overshoot, but will typically provide faster locking. DFLLMUL.CSTEP and DFLLMUL.FSTEP should not be higher than 50% of the maximum value of DFLLVAL.COARSE and DFLLVAL.FINE, respectively. 3. Select the multiplication factor in the DFLL Multiply Factor bit group (DFLLMUL.MUL) in the DFLL Multiplier register. Note: When choosing DFLLMUL.MUL, the output frequency must not exceed the maximum frequency of the device. If the target frequency is below the minimum frequency of the DFLL48M, the output frequency will be equal to the DFLL minimum frequency. 4. Start the closed loop mode by writing '1' to the DFLL Mode Selection bit in the DFLL Control register The frequency of CLK_DFLL48M (Fclkdfll48m) is given by: F clkdfll48m = DFLLMUL ⋅ MUL × F clkdfll48m_ref where Fclkdfll48m_ref is the frequency of the reference clock (CLK_DFLL48M_REF).

20.6.5.1.3 Frequency Locking

After enabling closed-loop operation by writing DFLLCTRL.MODE=1, the Coarse Value and the Fine Value bit fields in the DFLL48M Value register (DFLLVAL.COARSE and DFLLVAL.FINE) are used as starting parameters for the locking procedure. Note: DFLLVAL.COARSE and DFLLVAL.FINE are read-only in closed-loop mode, and are controlled by the frequency tuner to meet user specified frequency. The frequency locking is divided into two stages: coarse and fine lock. Coarse Lock. Starting from the original DFLLVAL.COARSE and DFLLVAL.FINE, the control logic quickly finds the correct value for DFLLVAL.COARSE and sets the output frequency to a value close to the correct frequency. On coarse lock, the DFLL Locked on Coarse Value bit (STATUS.DFLLLCKC) in the Status register will be set. Fine Lock. In this stage, the control logic tunes the value in DFLLVAL.FINE so that the output frequency is very close to the desired frequency. On fine lock, the DFLL Locked on Fine Value bit (STATUS.DFLLLCKF) in the Status register will be set. Interrupts are generated by STATUS.DFLLLCKC and STATUS.DFLLLCKF, if INTENSET.DFLLLCKC or INTENSET.DFLLLCKF, respectively, are written to '1'. The accuracy of the output frequency depends on which locks are set. Note: Writing DFLLVAL.COARSE to a value close to the final value before entering closed-loop mode will reduce the time needed to get a lock on Coarse. For a DFLL48M output frequency of 48MHz, the bit field "DFLL48M COARSE CAL" in the NVM Software Calibration Area provides a matching value for DFLL.COARSE, and will start DFLL with a frequency close to 48MHz. This procedure will reduce the locking time to only the DFLL Fine Lock time: 1. Load the "DFLL48M COARSE CAL" value from the NVM Software Calibration Area into the DFLL.COARSE bit field. 2. Enable the Bypass Coarse Lock (DFLLCTRL.BPLCKC=1). 3. Start DFLL close loop (DFLLCTRL.MODE=1).

20.6.5.1.4 Frequency Error Measurement

The ratio between CLK_DFLL48M_REF and CLK48M_DFLL is measured automatically when the DFLL48M is in closed-loop mode. The difference between this ratio and the value in DFLLMUL.MUL is stored in the DFLL Multiplication Ratio Difference bit group (DFLLVAL.DIFF) in the DFLL Value register. The relative error of CLK_DFLL48M with respect to the target frequency is calculated as follows: E RROR = DFLLVAL.DIFF DFLLMUL.MUL SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 189

20.6.5.1.5 Drift Compensation

If the Stable DFLL Frequency bit (DFLLCTRL.STABLE) in the DFLL Control register is '0', the frequency tuner will automatically compensate for drift in the CLK_DFLL48M without losing either of the locks. Note: This means that DFLLVAL.FINE can change after every measurement of CLK_DFLL48M. The DFLLVAL.FINE value may overflow or underflow in closed-loop mode due to large drift/instability of the clock source reference, and the DFLL Out Of Bounds bit (STATUS.DFLLOOB) in the Status register will be set. After an Out of Bounds error condition, the user must rewrite DFLLMUL.MUL to ensure correct CLK_DFLL48M frequency. A zero-to-one transition of STATUS.DFLLOOB will generate an interrupt, if the DFLL Out Of Bounds bit in the Interrupt Enable Set register (INTENSET.DFLLOOB) is '1'. This interrupt will also be set if the tuner is not able to lock on the correct Coarse value. To avoid this out-of-bounds error, the reference clock must be stable; an external oscillator XOSC32K is recommended.

20.6.5.1.6 Reference Clock Stop Detection

If CLK_DFLL48M_REF stops or is running at a very low frequency (slower than CLK_DFLL48M/(2 * MULMAX)), the DFLL Reference Clock Stopped bit in the Status register (STATUS.DFLLRCS) will be set. Detecting a stopped reference clock can take a long time, in the order of 217 CLK_DFLL48M cycles. When the reference clock is stopped, the DFLL48M will operate as if in open-loop mode. Closed-loop mode operation will automatically resume when the CLK_DFLL48M_REF is restarted. A zero-to-one transition of the DFLL Reference Clock Stopped bit in the Status register (STATUS.DFLLRCS) will generate an interrupt, if the DFLL Reference Clock Stopped bit in the Interrupt Enable Set register (INTENSET.DFLLRCS) is '1'.

20.6.5.2 Additional Features

20.6.5.2.1 Dealing with Settling Time in Closed-Loop Mode

The time from selecting a new CLK_DFLL48M output frequency until this frequency is output by the DFLL48M can be up to several microseconds. A small value in DFLLMUL.MUL can lead to instability in the DFLL48M locking mechanism, which can prevent the DFLL48M from achieving locks. To avoid this, a chill cycle can be enabled, during which the CLK_DFLL48M frequency is not measured. The chill cycle is enabled by default, but can be disabled by writing '1' to the DFLL Chill Cycle Disable bit in the DFLL Control register (DFLLCTRL.CCDIS). Enabling chill cycles might double the lock time. Another solution to this problem is using less strict lock requirements. This is called Quick Lock (QL). QL is enabled by default as well, but it can be disabled by writing '1' to the Quick Lock Disable bit in the DFLL Control register (DFLLCTRL.QLDIS). The Quick Lock might lead to a larger spread in the output frequency than chill cycles, but the average output frequency is the same.

20.6.5.2.2 USB Clock Recovery Mode

USB Clock Recovery mode can be used to create the 48MHz USB clock from the USB Start Of Frame (SOF). This mode is enabled by writing a '1' to both the USB Clock Recovery Mode bit and the Mode bit in DFLL Control register (DFLLCTRL.USBCRM and DFLLCTRL.MODE). Note: In USB Clock Recovery mode, the status bits of the DFLL in OSCCTRL.STATUS are determined by the USB bus activity, and have no valid meaning. The SOF signal from USB device will be used as reference clock (CLK_DFLL_REF), ignoring the selected generic clock reference. When the USB device is connected, a SOF will be sent every 1ms, thus DFLLVAL.MUX bits should be written to 0xBB80 to obtain a 48MHz clock. In USB clock recovery mode, the DFLLCTRL.BPLCKC bit state is ignored, and the value stored in the DFLLVAL.COARSE will be used as final Coarse Value. The COARSE calibration value can be loaded from NVM OTP row by software. The locking procedure will also go instantaneously to the fine lock search. The DFLLCTRL.QLDIS bit must be cleared and DFLLCTRL.CCDIS should be set to speed up the lock phase. The DFLLCTRL.STABLE bit state is ignored, an auto jitter reduction mechanism is used instead. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 190

20.6.5.2.3 Wake from Sleep Modes

DFLL48M can optionally reset its lock bits when it is disabled. This is configured by the Lose Lock After Wake bit in the DFLL Control register (DFLLCTRL.LLAW). If DFLLCTRL.LLAW is zero, the DFLL48M will be re-enabled and start running with the same configuration as before being disabled, even if the reference clock is not available. The locks will not be lost. After the reference clock has restarted, the fine lock tracking will quickly compensate for any frequency drift during sleep if DFLLCTRL.STABLE is zero. If DFLLCTRL.LLAW is '1' when disabling the DFLL48M, the DFLL48M will lose all its locks, and needs to regain these through the full lock sequence.

20.6.5.2.4 Accuracy

There are three main factors that determine the accuracy of Fclkdfll48m. These can be tuned to obtain maximum accuracy when fine lock is achieved.

Fine resolution. The frequency step between two Fine values. This is relatively smaller for higher output frequencies.
Resolution of the measurement: If the resolution of the measured Fclkdfll48m is low, i.e., the ratio between the CLK_DFLL48M frequency and the CLK_DFLL48M_REF frequency is small, the DFLL48M might lock at a frequency that is lower than the targeted frequency. It is recommended to use a reference clock frequency of 32KHz or lower to avoid this issue for low target frequencies.
The accuracy of the reference clock.

20.6.6 Digital Phase Locked Loop (DPLL) Operation

The task of the DPLL is to maintain coherence between the input (reference) signal and the respective output frequency, CLK_DPLL, via phase comparison. The DPLL controller supports three independent sources of reference clocks:

XOSC32K: this clock is provided by the 32K External Crystal Oscillator (XOSC32K).
XOSC: this clock is provided by the External Multipurpose Crystal Oscillator (XOSC).
GCLK: this clock is provided by the Generic Clock Controller. When the controller is enabled, the relationship between the reference clock frequency and the output clock frequency is: f CK = f CKR × LDR + 1 + LDRFRAC 16 × 1 2PRESC Where fCK is the frequency of the DPLL output clock, LDR is the loop divider ratio integer part, LDRFRAC is the loop divider ratio fractional part, fCKR is the frequency of the selected reference clock, and PRESC is the output prescaler value. Figure 20-2. DPLL Block Diagram XIN XOUT XOSC XIN32 XOUT32 XOSC32K GCLK DIVIDER DPLLCTRLB.DIV DPLLCTRLB.REFCLK DIGITAL FILTERTDC DPLLCTRLB.FILTER DCO CKDIV4 CKDIV2 CKDIV1 DPLLPRESC CLK_DPLL RATIO DPLLRATIO CK CKR CG When the controller is disabled, the output clock is low. If the Loop Divider Ratio Fractional part bit field in the DPLL Ratio register (DPLLRATIO.LDRFRAC) is zero, the DPLL works in integer mode. Otherwise, the fractional mode is activated. Note that the fractional part has a negative impact on the jitter of the DPLL. Example (integer mode only): assuming FCKR = 32kHz and FCK = 48MHz, the multiplication ratio is 1500. It means that LDR shall be set to 1499. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 191

Example (fractional mode): assuming FCKR = 32kHz and FCK = 48.006MHz, the multiplication ratio is 1500.1875 (1500 + 3/16). Thus LDR is set to 1499 and LDRFRAC to 3. References: 15. GCLK - Generic Clock Controller 21. OSC32KCTRL – 32.768 kHz Oscillators Controller

20.6.6.1 Basic Operation

20.6.6.1.1 Initialization, Enabling, Disabling, and Resetting

The DPLLC is enabled by writing a '1' to the Enable bit in the DPLL Control A register (DPLLCTRLA.ENABLE). The DPLLC is disabled by writing a zero to this bit. The DPLLSYNCBUSY.ENABLE is set when the DPLLCTRLA.ENABLE bit is modified. It is cleared when the DPLL output clock CK has sampled the bit at the high level after enabling the DPLL. When disabling the DPLL, DPLLSYNCBUSY.ENABLE is cleared when the output clock is no longer running. Figure 20-3. Enable Synchronization Busy Operation ENABLE CK SYNCBUSY.ENABLE CLK_APB_OSCCTRL The frequency of the DPLL output clock CK is stable when the module is enabled and when the Lock bit in the DPLL Status register is set (DPLLSTATUS.LOCK). When the Lock Time bit field in the DPLL Control B register (DPLLCTRLB.LTIME) is non-zero, a user defined lock time is used to validate the lock operation. In this case the lock time is constant. If DPLLCTRLB.LTIME = 0, the lock signal is linked with the status bit of the DPLL, and the lock time varies depending on the filter selection and the final target frequency. Note: GCLK_FDPLL_32K is responsible for counting the user defined lock time (LTIME different from 0x0), hence must be enabled. When the Wake Up Fast bit (DPLLCTRLB.WUF) is set, the wake up fast mode is activated. In this mode, the clock gating cell is enabled at the end of the startup time. At this time the final frequency is not stable, as it is still during the acquisition period, but it allows to save several milliseconds. After first acquisition, the clock gater (CG) generating the output clock CLK_DPLL is gated by the LOCK signal when the Lock Bypass bit (DPLLCTRLB.LBYPASS) is cleared or is not gated and delivers the output clock CLK_DPLL immediately when DPLLCTRLB.LBYPASS is set. Table 20-3. CLK_DPLL Behavior from Startup to First Edge Detection WUF LTIME CLK_DPLL Behavior 0 0 Normal Mode: First Edge when lock is asserted 0 Not Equal To Zero Lock Timer Timeout mode: First Edge when the timer down-counts to 0.

1 X Wake Up Fast Mode: First Edge when CK is active (startup time)

Table 20-4. CLK_DPLL Behavior after First Edge Detection LBYPASS CLK_DPLL Behavior 0 Normal Mode: the CLK_DPLL is turned off when lock signal is low. 1 Lock Bypass Mode: the CLK_DPLL is always running, lock is irrelevant. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 192

Figure 20-4. CK and CLK_DPLL Output from DPLL Off Mode to Running Mode CKR ENABLE CK LOCK CK STABLEtstartup_time tlock_time CLK_DPLL

20.6.6.1.2 Reference Clock Switching

When a software operation requires reference clock switching, the recommended procedure is to turn the DPLL into the standby mode, modify the DPLLCTRLB.REFCLK to select the desired reference source, and activate the DPLL again.

20.6.6.1.3 Output Clock Prescaler

The DPLL controller includes an output prescaler. This prescaler provides three selectable output clocks CK, CKDIV2 and CKDIV4. The Prescaler bit field in the DPLL Prescaler register (DPLLPRESC.PRESC) is used to select a new output clock prescaler. When the prescaler field is modified, the DPLLSYNCBUSY.DPLLPRESC bit is set. It will be cleared by hardware when the synchronization is over. Figure 20-5. Output Clock Switching Operation CKR PRESC CLK_DPLL DPLL_LOCK 0 1 CK STABLECK STABLE CK SWITCHING SYNCBUSY .PRESC CK CKDIV2

20.6.6.1.4 Loop Divider Ratio Updates

The DPLL Controller supports on-the-fly update of the DPLL Ratio Control (DPLLRATIO) register, allowing to modify the loop divider ratio and the loop divider ratio fractional part when the DPLL is enabled. STATUS.DPLLLDRTO is set when the DPLLRATIO register has been modified and the DPLL analog cell has successfully sampled the updated value. At that time the DPLLSTATUS.LOCK bit is cleared and set again by hardware when the output frequency reached a stable state. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 193

Figure 20-6. RATIOCTRL register update operation CKR LDR LDRFRAC CK CLK_DPLL mult0 mult1 LOCK LOCKL

20.6.6.1.5 Digital Filter Selection

The PLL digital filter (PI controller) is automatically adjusted in order to provide a good compromise between stability and jitter. Nevertheless a software operation can override the filter setting using the Filter bit field in the DPLL Control B register (DPLLCTRLB.FILTER). The Low Power Enable bit (DPLLCTRLB.LPEN) can be use to bypass the Time to Digital Converter (TDC) module.

20.6.7 DMA Operation

Not applicable.

20.6.8 Interrupts

The OSCCTRL has the following interrupt sources:

XOSCRDY - Multipurpose Crystal Oscillator Ready: A 0-to-1 transition on the STATUS.XOSCRDY bit is detected
CLKFAIL - Clock Failure. A 0-to-1 transition on the STATUS.CLKFAIL bit is detected
OSC16MRDY - 16MHz Internal Oscillator Ready: A 0-to-1 transition on the STATUS.OSC16MRDY bit is detected
DFLL-related: – DFLLRDY - DFLL48M Ready: A 0-to-1 transition of the STATUS.DFLLRDY bit is detected – DFLLOOB - DFLL48M Out Of Boundaries: A 0-to-1 transition of the STATUS.DFLLOOB bit is detected – DFLLLOCKF - DFLL48M Fine Lock: A 0-to-1 transition of the STATUS.DFLLLOCKF bit is detected – DFLLLOCKC - DFLL48M Coarse Lock: A 0-to-1 transition of the STATUS.DFLLLOCKC bit is detected – DFLLRCS - DFLL48M Reference Clock has Stopped: A 0-to-1 transition of the STATUS.DFLLRCS bit is detected
DPLL-related: – DPLLLOCKR - DPLL Lock Rise: A 0-to-1 transition of the STATUS.DPLLLOCKR bit is detected – DPLLLOCKF - DPLL Lock Fall: A 0-to-1 transition of the STATUS.DPLLLOCKF bit is detected – DPLLLTTO - DPLL Lock Timer Time-out: A 0-to-1 transition of the STATUS.DPLLLTTO bit is detected – DPLLLDRTO - DPLL Loop Divider Ratio Update Complete. A 0-to-1 transition of the STATUS.DPLLLDRTO bit is detected All these interrupts are synchronous wake-up source. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the OSCCTRL is reset. See the INTFLAG register for details on how to clear interrupt flags. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 194

The OSCCTRL has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register to determine which interrupt condition is present. Refer to the INTFLAG register for details. Note: The interrupts must be globally enabled for interrupt requests to be generated.

20.6.9 Events

The CFD can generate the following output event:

Clock Failure (CLKFAIL): Generated when the Clock Failure status bit is set in the Status register (STATUS.CLKFAIL). The CFD event is not generated when the Clock Switch bit (STATUS.CLKSW) in the Status register is set. Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.CFDEO) enables the CFD output event. Writing a '0' to this bit disables the CFD output event. Refer to the Event System chapter for details on configuring the event system.

20.6.10 Synchronization

Due to the multiple clock domains, values in the DFLL48M control registers need to be synchronized to other clock domains. Once the DFLL is enabled, any read and write operation requires the DFLL Ready bit in the Status register (STATUS.DFLLRDY) to read '1'. Note: Once the DFLL48M is enabled in on-demand mode (DFLLCTRL.ONDEMAND=1), the STATUS.DFLLRDY bit will keep to '0' until the DFLL48M is requested by a peripheral. Before writing to any of the DFLL48M control registers, the user must check that the DFLL Ready bit (STATUS.DFLLRDY) is set to '1'. When this bit is set, the DFLL48M can be configured and CLK_DFLL48M is ready to be used. Any write to any of the DFLL48M control registers while DFLLRDY is '0' will be ignored. In order to read from the DFLLVAL register in closed loop mode, the user must request a read synchronization by writing a '1' to the Read Request bit in the DFLL Synchronization register (DFLLSYNC.READREQ). This is required because the DFLL controller may change the content of the DFLLVAL register any time. If a read operation is issued while the DFLL controller is updating the DFLLVAL content, a zero will be returned. Note: Issuing a read on any register while a write-synchronization is still on-going will return a zero. Read-Synchronized registers using DFLLSYNC.READREQ:

DFLL48M Value register (DFLLVAL) Write-Synchronized registers:
DFLL48M Control register (DFLLCTRL)
DFLL48M Value register (DFLLVAL)
DFLL48M Multiplier register (DFLLMUL) DPLL96M Due to the multiple clock domains, some registers in the DPLL96M must be synchronized when accessed. When executing an operation that requires synchronization, the relevant synchronization bit in the Synchronization Busy register (DPLLSYNCBUSY) will be set immediately, and cleared when synchronization is complete. The following bits need synchronization when written:
Enable bit in control register A (DPLLCTRLA.ENABLE)
DPLL Ratio register (DPLLRATIO)
DPLL Prescaler register (DPLLPRESC) SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 195

20.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 INTENCLR 7:0 OSC16MRDY XOSCFAIL XOSCRDY 15:8 DFLLRCS DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY 23:16 DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR 31:24 0x04 INTENSET 7:0 OSC16MRDY XOSCFAIL XOSCRDY 15:8 DFLLRCS DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY 23:16 DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR 31:24 0x08 INTFLAG 7:0 OSC16MRDY XOSCFAIL XOSCRDY 15:8 DFLLRCS DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY 23:16 DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR 31:24 0x0C STATUS 7:0 OSC16MRDY XOSCCKSW XOSCFAIL XOSCRDY 15:8 DFLLRCS DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY 23:16 DPLLLDRTO DPLLTO DPLLLCKF DPLLLCKR 31:24 0x10 XOSCCTRL 7:0 ONDEMAND RUNSTDBY SWBEN CFDEN XTALEN ENABLE 15:8 STARTUP[3:0] AMPGC GAIN[2:0] 0x12 CFDPRESC 7:0 CFDPRESC[2:0] 0x13 EVCTRL 7:0 CFDEO 0x14 OSC16MCTRL 7:0 ONDEMAND RUNSTDBY FSEL[1:0] ENABLE 0x15 ... 0x17 Reserved 0x18 DFLLCTRL 7:0 ONDEMAND RUNSTDBY USBCRM LLAW STABLE MODE ENABLE 15:8 WAITLOCK BPLCKC QLDIS CCDIS 0x1A ... 0x1B Reserved 0x1C DFLLVAL 7:0 FINE[7:0] 15:8 COARSE[5:0] FINE[9:8] 23:16 DIFF[7:0] 31:24 DIFF[15:8] 0x20 DFLLMUL 7:0 MUL[7:0] 15:8 MUL[15:8] 23:16 FSTEP[7:0] 31:24 CSTEP[5:0] FSTEP[9:8] 0x24 DFLLSYNC 7:0 READREQ 0x25 ... 0x27 Reserved 0x28 DPLLCTRLA 7:0 ONDEMAND RUNSTDBY ENABLE 0x29 ... 0x2B Reserved 0x2C DPLLRATIO 7:0 LDR[7:0] 15:8 LDR[11:8] 23:16 LDRFRAC[3:0] 31:24 0x30 DPLLCTRLB 7:0 REFCLK[1:0] WUF LPEN FILTER[1:0] 15:8 LBYPASS LTIME[2:0] 23:16 DIV[7:0] 31:24 DIV[10:8] 0x34 DPLLPRESC 7:0 PRESC[1:0] SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 196

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x35 ... 0x37 Reserved 0x38 DPLLSYNCBUSY 7:0 DPLLPRESC DPLLRATIO ENABLE 0x39 ... 0x3B Reserved 0x3C DPLLSTATUS 7:0 CLKRDY LOCK

20.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the "PAC Write-Protection" property in each individual register description. Refer to the 20.5.8. Register Access Protection section and the 11. PAC - Peripheral Access Controller chapter for details. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read- Synchronized" or "Write.Synchronized" property in each individual register description. Refer to Synchronization section for details. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 197

20.8.1 Interrupt Enable Clear

1 The DPLL Loop Divider Ratio Update Complete interrupt is enabled, and an interrupt request will be

generated when the DPLL Loop Divider Ratio Update Complete Interrupt flag is set. Bit 18 – DPLLLTO DPLL Lock Timeout Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the DPLL Lock Timeout Interrupt Enable bit, which disables the DPLL Lock Timeout interrupt. Value Description 0 The DPLL Lock Timeout interrupt is disabled.

1 The DPLL Lock Timeout interrupt is enabled, and an interrupt request will be generated when the DPLL

Lock Timeout Interrupt flag is set. Bit 17 – DPLLLCKF DPLL Lock Fall Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the DPLL Lock Fall Interrupt Enable bit, which disables the DPLL Lock Fall interrupt. Value Description 0 The DPLL Lock Fall interrupt is disabled.

1 The DPLL Lock Fall interrupt is enabled, and an interrupt request will be generated when the DPLL

Bit 16 – DPLLLCKR DPLL Lock Rise Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the DPLL Lock Rise Interrupt Enable bit, which disables the DPLL Lock Rise interrupt. Value Description 0 The DPLL Lock Rise interrupt is disabled.

1 The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL

Lock Rise Interrupt flag is set. Bit 12 – DFLLRCS DFLL Reference Clock Stopped Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the DFLL Reference Clock Stopped Interrupt Enable bit, which disables the DFLL Reference Clock Stopped interrupt. Value Description 0 The DFLL Reference Clock Stopped interrupt is disabled.

1 The DFLL Reference Clock Stopped interrupt is enabled, and an interrupt request will be generated

when the DFLL Reference Clock Stopped Interrupt flag is set. Bit 11 – DFLLLCKC DFLL Lock Coarse Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the DFLL Lock Coarse Interrupt Enable bit, which disables the DFLL Lock Coarse interrupt. Value Description 0 The DFLL Lock Coarse interrupt is disabled.

1 The DFLL Lock Coarse interrupt is enabled, and an interrupt request will be generated when the DFLL

Lock Coarse Interrupt flag is set. Bit 10 – DFLLLCKF DFLL Lock Fine Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the DFLL Lock Fine Interrupt Enable bit, which disables the DFLL Lock Fine interrupt. Value Description 0 The DFLL Lock Fine interrupt is disabled.

1 The DFLL Lock Fine interrupt is enabled, and an interrupt request will be generated when the DFLL

Lock Fine Interrupt flag is set. Bit 9 – DFLLOOB DFLL Out Of Bounds Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the DFLL Out Of Bounds Interrupt Enable bit, which disables the DFLL Out Of Bounds interrupt. Value Description 0 The DFLL Out Of Bounds interrupt is disabled.

1 The DFLL Out Of Bounds interrupt is enabled, and an interrupt request will be generated when the

DFLL Out Of Bounds Interrupt flag is set. Bit 8 – DFLLRDY DFLL Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the DFLL Ready Interrupt Enable bit, which disables the DFLL Ready interrupt. Value Description 0 The DFLL Ready interrupt is disabled.

1 The DFLL Ready interrupt is enabled, and an interrupt request will be generated when the DFLL Ready

Interrupt flag is set. Bit 4 – OSC16MRDY OSC16M Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the OSC16M Ready Interrupt Enable bit, which disables the OSC16M Ready interrupt. Value Description 0 The OSC16M Ready interrupt is disabled. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 199

1 The OSC16M Ready interrupt is enabled, and an interrupt request will be generated when the

OSC16M Ready Interrupt flag is set. Bit 1 – XOSCFAIL Clock Failure Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the XOSC Clock Failure Interrupt Enable bit, which disables the XOSC Clock Failure interrupt. Value Description 0 The XOSC Clock Failure interrupt is disabled.

1 The XOSC Clock Failure interrupt is enabled, and an interrupt request will be generated when the

XOSC Clock Failure Interrupt flag is set. Bit 0 – XOSCRDY XOSC Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the XOSC Ready Interrupt Enable bit, which disables the XOSC Ready interrupt. Value Description 0 The XOSC Ready interrupt is disabled.

1 The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC

20.8.2 Interrupt Enable Set

1 The DPLL Loop Ratio Update Complete interrupt is enabled, and an interrupt request will be generated

when the DPLL Loop Ratio Update Complete Interrupt flag is set. Bit 18 – DPLLLTO DPLL Lock Timeout Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the DPLL Lock Timeout Interrupt Enable bit, which enables the DPLL Lock Timeout interrupt. Value Description 0 The DPLL Lock Timeout interrupt is disabled. Lock Timeout Interrupt flag is set. Bit 17 – DPLLLCKF DPLL Lock Fall Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the DPLL Lock Fall Interrupt Enable bit, which enables the DPLL Lock Fall interrupt. Value Description 0 The DPLL Lock Fall interrupt is disabled. Lock Fall Interrupt flag is set. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 201

Bit 16 – DPLLLCKR DPLL Lock Rise Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the DPLL Lock Rise Interrupt Enable bit, which enables the DPLL Lock Rise interrupt. Value Description 0 The DPLL Lock Rise interrupt is disabled. Lock Rise Interrupt flag is set. Bit 12 – DFLLRCS DFLL Reference Clock Stopped Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the DFLL Reference Clock Stopped Interrupt Enable bit, which enables the DFLL Reference Clock Stopped interrupt. Value Description 0 The DFLL Reference Clock Stopped interrupt is disabled. when the DFLL Reference Clock Stopped Interrupt flag is set. Bit 11 – DFLLLCKC DFLL Lock Coarse Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the DFLL Lock Coarse Interrupt Enable bit, which enables the DFLL Lock Coarse interrupt. Value Description 0 The DFLL Lock Coarse interrupt is disabled. Lock Coarse Interrupt flag is set. Bit 10 – DFLLLCKF DFLL Lock Fine Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the DFLL Lock Fine Interrupt Disable/Enable bit, disable the DFLL Lock Fine interrupt and set the corresponding interrupt request. Value Description 0 The DFLL Lock Fine interrupt is disabled. Lock Fine Interrupt flag is set. Bit 9 – DFLLOOB DFLL Out Of Bounds Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the DFLL Out Of Bounds Interrupt Enable bit, which enables the DFLL Out Of Bounds interrupt. Value Description 0 The DFLL Out Of Bounds interrupt is disabled. DFLL Out Of Bounds Interrupt flag is set. Bit 8 – DFLLRDY DFLL Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the DFLL Ready Interrupt Enable bit, which enables the DFLL Ready interrupt and set the corresponding interrupt request. Value Description 0 The DFLL Ready interrupt is disabled. Interrupt flag is set. Bit 4 – OSC16MRDY OSC16M Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the OSC16M Ready Interrupt Enable bit, which enables the OSC16M Ready interrupt. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 202

0 The OSC16M Ready interrupt is disabled. OSC16M Ready Interrupt flag is set. Bit 1 – XOSCFAIL XOSC Clock Failure Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the XOSC Clock Failure Interrupt Enable bit, which enables the XOSC Clock Failure Interrupt. Value Description 0 The XOSC Clock Failure Interrupt is disabled. XOSC Clock Failure Interrupt flag is set. Bit 0 – XOSCRDY XOSC Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the XOSC Ready Interrupt Enable bit, which enables the XOSC Ready interrupt. Value Description 0 The XOSC Ready interrupt is disabled. Ready Interrupt flag is set. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 203

20.8.3 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x08 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DFLLRCS DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OSC16MRDY XOSCFAIL XOSCRDY Access R/W R/W R/W Reset 0 0 0 Bit 19 – DPLLLDRTO DPLL Loop Divider Ratio Update Complete This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the DPLL Loop Divider Ratio Update Complete bit in the Status register (STATUS.DPLLLDRTO) and will generate an interrupt request if INTENSET.DPLLLDRTO is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DPLL Loop Divider Ratio Update Complete interrupt flag. Bit 18 – DPLLLTO DPLL Lock Timeout This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the DPLL Lock Timeout bit in the Status register (STATUS.DPLLLTO) and will generate an interrupt request if INTENSET.DPLLLTO is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DPLL Lock Timeout interrupt flag. Bit 17 – DPLLLCKF DPLL Lock Fall This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the DPLL Lock Fall bit in the Status register (STATUS.DPLLLCKF) and will generate an interrupt request if INTENSET.DPLLLCKF is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DPLL Lock Fall interrupt flag. Bit 16 – DPLLLCKR DPLL Lock Rise This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the DPLL Lock Rise bit in the Status register (STATUS.DPLLLCKR) and will generate an interrupt request if INTENSET.DPLLLCKR is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DPLL Lock Rise interrupt flag. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 204

Bit 12 – DFLLRCS DFLL Reference Clock Stopped This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the DFLL Reference Clock Stopped bit in the Status register (STATUS.DFLLRCS) and will generate an interrupt request if INTENSET.DFLLRCS is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DFLL Reference Clock Stopped interrupt flag. Bit 11 – DFLLLCKC DFLL Lock Coarse This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the DFLL Lock Coarse bit in the Status register (STATUS.DFLLLCKC) and will generate an interrupt request if INTENSET.DFLLLCKC is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DFLL Lock Coarse interrupt flag. Bit 10 – DFLLLCKF DFLL Lock Fine This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the DFLL Lock Fine bit in the Status register (STATUS.DFLLLCKF) and will generate an interrupt request if INTENSET.DFLLLCKF is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DFLL Lock Fine interrupt flag. Bit 9 – DFLLOOB DFLL Out Of Bounds This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the DFLL Out Of Bounds bit in the Status register (STATUS.DFLLOOB) and will generate an interrupt request if INTENSET.DFLLOOB is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DFLL Out Of Bounds interrupt flag. Bit 8 – DFLLRDY DFLL Ready This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the DFLL Ready bit in the Status register (STATUS.DFLLRDY) and will generate an interrupt request if INTENSET.DFLLRDY is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DFLL Ready interrupt flag. Bit 4 – OSC16MRDY OSC16M Ready This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the OSC16M Ready bit in the Status register (STATUS.OSC16MRDY) and will generate an interrupt request if INTENSET.OSC16MRDY is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the OSC16M Ready interrupt flag. Bit 1 – XOSCFAIL XOSC Failure Detection This flag is cleared by writing '1' to it. This flag is set on a 0-to-1 transition of the XOSC Clock Failure bit in the Status register (STATUS.XOSCFAIL) and will generate an interrupt request if INTENSET.XOSCFAIL is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the XOSC Clock Fail interrupt flag. Bit 0 – XOSCRDY XOSC Ready This flag is cleared by writing '1' to it. This flag is set on a 0-to-1 transition of the XOSC Ready bit in the Status register (STATUS.XOSCRDY) and will generate an interrupt request if INTENSET.XOSCRDY is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the XOSC Ready interrupt flag. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 205

20.8.4 Status

Name: STATUS Offset: 0x0C Reset: 0x00000100 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 DPLLLDRTO DPLLTO DPLLLCKF DPLLLCKR Access R R R R Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DFLLRCS DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY Access R R R R R Reset 0 0 0 0 1 Bit 7 6 5 4 3 2 1 0 OSC16MRDY XOSCCKSW XOSCFAIL XOSCRDY Access R R R R Reset 0 0 0 0 Bit 19 – DPLLLDRTO DPLL Loop Divider Ratio Update Complete Value Description 0 DPLL Loop Divider Ratio Update Complete not detected. 1 DPLL Loop Divider Ratio Update Complete detected. Bit 18 – DPLLTO DPLL Lock Timeout Value Description 0 DPLL Lock time-out not detected. 1 DPLL Lock time-out detected. Bit 17 – DPLLLCKF DPLL Lock Fall Value Description 0 DPLL Lock fall edge not detected. 1 DPLL Lock fall edge detected. Bit 16 – DPLLLCKR DPLL Lock Rise Value Description 0 DPLL Lock rise edge not detected. 1 DPLL Lock fall edge detected. Bit 12 – DFLLRCS DFLL Reference Clock Stopped Value Description 0 DFLL reference clock is running. 1 DFLL reference clock has stopped. Bit 11 – DFLLLCKC DFLL Lock Coarse Value Description 0 No DFLL coarse lock detected. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 206

1 DFLL coarse lock detected. Bit 10 – DFLLLCKF DFLL Lock Fine Value Description 0 No DFLL fine lock detected. 1 DFLL fine lock detected. Bit 9 – DFLLOOB DFLL Out Of Bounds Value Description 0 No DFLL Out Of Bounds detected. 1 DFLL Out Of Bounds detected. Bit 8 – DFLLRDY DFLL Ready Value Description 0 DFLL registers update is ongoing. Registers update is requested through DFLLSYNC.READREQ, or after a write access in DFLLCTRL, DFLLVAL or DFLLMUL register. 1 DFLL registers are stable and ready for read/write access. Bit 4 – OSC16MRDY OSC16M Ready Value Description 0 OSC16M is not ready. 1 OSC16M is stable and ready to be used as a clock source. Bit 2 – XOSCCKSW XOSC Clock Switch Value Description 0 XOSC is not switched and provides the external clock or crystal oscillator clock. 1 XOSC is switched and provides the safe clock. Bit 1 – XOSCFAIL XOSC Clock Failure Value Description 0 No XOSC failure detected. 1 A XOSC failure was detected. Bit 0 – XOSCRDY XOSC Ready Value Description 0 XOSC is not ready. 1 XOSC is stable and ready to be used as a clock source. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 207

20.8.5 Clock Failure Detector Prescaler

Name: CFDPRESC Offset: 0x12 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CFDPRESC[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 2:0 – CFDPRESC[2:0] Clock Failure Detector Prescaler These bits select the prescaler for the clock failure detector. The OSC16M oscillator is used to clock the CFD prescaler. The CFD safe clock frequency is the OSC16M frequency divided by 2^CFDPRESC. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 208

20.8.6 Event Control

Name: EVCTRL Offset: 0x13 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CFDEO Access R/W Reset 0 Bit 0 – CFDEO Clock Failure Detector Event Output Enable This bit indicates whether the Clock Failure detector event output is enabled or not and an output event will be generated when the Clock Failure detector detects a clock failure Value Description 0 Clock Failure detector event output is disabled and no event will be generated. 1 Clock Failure detector event output is enabled and an event will be generated. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 209

20.8.7 16MHz Internal Oscillator (OSC16M) Control Name: OSC16MCTRL Offset: 0x14 Reset: 0x82 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY FSEL[1:0] ENABLE Access R/W R/W R/W R/W R/W Reset 1 0 0 0 1 Bit 7 – ONDEMAND On Demand Control The On Demand operation mode allows the oscillator to be enabled or disabled depending on peripheral clock requests. If the ONDEMAND bit has been previously written to '1', the oscillator will only be running when requested by a peripheral. If there is no peripheral requesting the oscillator’s clock source, the oscillator will be in a disabled state. If On Demand is disabled the oscillator will always be running when enabled. In standby sleep mode, the On Demand operation is still active. Value Description 0 The oscillator is always on, if enabled. 1 The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is disabled if no peripheral is requesting the clock source. Bit 6 – RUNSTDBY Run in Standby This bit controls how the OSC16M behaves during standby sleep mode. Value Description 0 The OSC16M is disabled in standby sleep mode if no peripheral requests the clock. 1 The OSC16M is not stopped in standby sleep mode. If ONDEMAND=1, the OSC16M will be running when a peripheral is requesting the clock. If ONDEMAND=0, the clock source will always be running in standby sleep mode. Bits 3:2 – FSEL[1:0] Oscillator Frequency Selection These bits control the oscillator frequency range. Value Name Description 0x0 4 4MHz 0x1 8 8MHz 0x2 12 12MHz 0x3 16 16MHz Bit 1 – ENABLE Oscillator Enable Value Description 0 The oscillator is disabled. 1 The oscillator is enabled. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 210

20.8.8 External Multipurpose Crystal Oscillator (XOSC) Control

Name: XOSCCTRL Offset: 0x10 Reset: 0x0080 Property: PAC Write-Protection Bit 15 14 13 12 11 10 9 8 STARTUP[3:0] AMPGC GAIN[2:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY SWBEN CFDEN XTALEN ENABLE Access R/W R/W R/W R/W R/W R/W Reset 1 0 0 0 0 0 Bits 15:12 – STARTUP[3:0] Start-Up Time These bits select start-up time for the oscillator. The OSCULP32K oscillator is used to clock the start-up counter. Table 20-5. Start-Up Time for External Multipurpose Crystal Oscillator STARTUP[3:0] Number of OSCULP32K Clock Cycles Number of XOSC Clock Cycles Approximate Equivalent Time [µs] 0x0 1 3 31 0x1 2 3 61 0x2 4 3 122 0x3 8 3 244 0x4 16 3 488 0x5 32 3 977 0x6 64 3 1953 0x7 128 3 3906 0x8 256 3 7813 0x9 512 3 15625 0xA 1024 3 31250 0xB 2048 3 62500µs 0xC 4096 3 125000 0xD 8192 3 250000 0xE 16384 3 500000 0xF 32768 3 1000000 Notes: 1. Actual startup time is 1 OSCULP32K cycle + 3 XOSC cycles. 2. The given time neglects the three XOSC cycles before OSCULP32K cycle. Bit 11 – AMPGC Automatic Amplitude Gain Control Note: The configuration of the oscillator gain is mandatory even if AMPGC feature is enabled at startup. Value Description 0 The automatic amplitude gain control is disabled. 1 The automatic amplitude gain control is enabled. Amplitude gain will be automatically adjusted during Crystal Oscillator operation. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 211

Bits 10:8 – GAIN[2:0] Oscillator Gain These bits select the gain for the oscillator. The listed maximum frequencies are recommendations, and might vary based on capacitive load and crystal characteristics. The Gain bits must be properly configured even when the Automatic Amplitude Gain Control is active. Value Recommended Max Frequency [MHz] 0x0 2 0x1 4 0x2 8 0x3 16 0x4 30 0x5-0x7 Reserved Bit 7 – ONDEMAND On Demand Control The On Demand operation mode allows the oscillator to be enabled or disabled, depending on peripheral clock requests. If the ONDEMAND bit has been previously written to '1', the oscillator will be running only when requested by a peripheral. If there is no peripheral requesting the oscillator’s clock source, the oscillator will be in a disabled state. If On Demand is disabled, the oscillator will always be running when enabled. In standby sleep mode, the On Demand operation is still active. Value Description 0 The oscillator is always on, if enabled. 1 The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is disabled if no peripheral is requesting the clock source. Bit 6 – RUNSTDBY Run in Standby This bit controls how the XOSC behaves during standby sleep mode, together with the ONDEMAND bit: Value Description 0 The XOSC is not running in Standby sleep mode if no peripheral requests the clock. 1 The XOSC is running in Standby sleep mode. If ONDEMAND=1, the XOSC will be running when a peripheral is requesting the clock. If ONDEMAND=0, the clock source will always be running in Standby sleep mode. Bit 4 – SWBEN Clock Switch Back This bit controls the XOSC output switch back to the external clock or crystal oscillator in case of clock recovery: Value Description 0 The clock switch back is disabled. 1 The clock switch back is enabled. This bit is reset once the XOSC putput clock is switched back to the external clock or crystal oscillator. Bit 3 – CFDEN Clock Failure Detector Enable This bit controls the clock failure detector: Value Description 0 The Clock Failure Detector is disabled. 1 the Clock Failure Detector is enabled. Bit 2 – XTALEN Crystal Oscillator Enable This bit controls the connections between the I/O pads and the external clock or crystal oscillator: Value Description 0 External clock connected on XIN. XOUT can be used as general-purpose I/O. 1 Crystal connected to XIN/XOUT. Bit 1 – ENABLE Oscillator Enable Value Description 0 The oscillator is disabled. 1 The oscillator is enabled. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 212

20.8.9 DFLL48M Control

Name: DFLLCTRL Offset: 0x18 Reset: 0x0080 Property: PAC Write-Protection, Write-Synchronized using STATUS.DFLLRDY=1 Bit 15 14 13 12 11 10 9 8 WAITLOCK BPLCKC QLDIS CCDIS Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY USBCRM LLAW STABLE MODE ENABLE Access R/W R/W R/W R/W R/W R/W R/W Reset 1 0 0 0 0 0 0 Bit 11 – WAITLOCK Wait Lock This bit controls the DFLL output clock, depending on lock status. Value Description 0 Output clock before the DFLL is locked. 1 Output clock when DFLL is locked. Bit 10 – BPLCKC Bypass Coarse Lock This bit controls the coarse lock procedure. Value Description 0 Bypass coarse lock is disabled. 1 Bypass coarse lock is enabled. Bit 9 – QLDIS Quick Lock Disable Value Description 0 Quick Lock is enabled. 1 Quick Lock is disabled. Bit 8 – CCDIS Chill Cycle Disable Value Description 0 Chill Cycle is enabled. 1 Chill Cycle is disabled. Bit 7 – ONDEMAND On Demand Control The On Demand operation mode allows the DFLL to be enabled or disabled depending on peripheral clock requests. If the ONDEMAND bit has been previously written to '1', the DFLL will only be running when requested by a peripheral. If there is no peripheral requesting the DFLL clock source, the DFLL will be in a disabled state. If On Demand is disabled, the DFLL will always be running when enabled. In standby sleep mode, the On Demand operation is still active. Value Description 0 The DFLL is always on, if enabled. 1 The DFLL is enabled when a peripheral is requesting the DFLL to be used as a clock source. The DFLL is disabled if no peripheral is requesting the clock source. Bit 6 – RUNSTDBY Run in Standby This bit controls how the DFLL behaves during standby sleep mode: Value Description 0 The DFLL is disabled in standby sleep mode if no peripheral requests the clock. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 213

1 The DFLL is not stopped in standby sleep mode. If ONDEMAND is one, the DFLL will be running when a peripheral is requesting the clock. If ONDEMAND is zero, the clock source will always be running in standby sleep mode. Bit 5 – USBCRM USB Clock Recovery Mode Value Description 0 USB Clock Recovery Mode is disabled. 1 USB Clock Recovery Mode is enabled. Bit 4 – LLAW Lose Lock After Wake Value Description 0 Locks will not be lost after waking up from sleep modes if the DFLL clock has been stopped. 1 Locks will be lost after waking up from sleep modes if the DFLL clock has been stopped. Bit 3 – STABLE Stable DFLL Frequency Value Description 0 FINE calibration tracks changes in output frequency. 1 FINE calibration register value will be fixed after a fine lock. Bit 2 – MODE Operating Mode Selection Value Description 0 The DFLL operates in open-loop operation. 1 The DFLL operates in closed-loop operation. Bit 1 – ENABLE DFLL Enable Due to synchronization, there is delay from updating the register until the peripheral is enabled/disabled. The value written to DFLLCTRL.ENABLE will read back immediately after written. Value Description 0 The DFLL oscillator is disabled. 1 The DFLL oscillator is enabled. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 214

20.8.10 DFLL48M Value

Name: DFLLVAL Offset: 0x1C Reset: 0x00000000 Property: PAC Write-Protection, Read-Synchronized using DFLLSYNC.READREQ, Write-Synchronized using STATUS.DFLLRDY=1 Bit 31 30 29 28 27 26 25 24 DIFF[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIFF[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COARSE[5:0] FINE[9:8] Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FINE[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:16 – DIFF[15:0] Multiplication Ratio Difference In closed-loop mode (DFLLCTRL.MODE=1), this bit group indicates the difference between the ideal number of DFLL cycles and the counted number of cycles. In open-loop mode, this value is not updated and hence, invalid. Bits 15:10 – COARSE[5:0] Coarse Value Set the value of the Coarse Calibration register. In closed-loop mode, this field is read-only. Bits 9:0 – FINE[9:0] Fine Value Set the value of the Fine Calibration register. In closed-loop mode, this field is read-only. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 215

20.8.11 DFLL48M Multiplier

Name: DFLLMUL Offset: 0x20 Reset: 0x00000000 Property: PAC Write-Protection, Write-Synchronized using STATUS.DFLLRDY=1 Bit 31 30 29 28 27 26 25 24 CSTEP[5:0] FSTEP[9:8] Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 FSTEP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 MUL[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MUL[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:26 – CSTEP[5:0] Coarse Maximum Step This bit group indicates the maximum step size allowed during coarse adjustment in closed-loop mode. When adjusting to a new frequency, the expected output frequency overshoot depends on this step size. Bits 25:16 – FSTEP[9:0] Fine Maximum Step This bit group indicates the maximum step size allowed during fine adjustment in closed-loop mode. When adjusting to a new frequency, the expected output frequency overshoot depends on this step size. Bits 15:0 – MUL[15:0] DFLL Multiply Factor This field determines the ratio of the CLK_DFLL output frequency to the CLK_DFLL_REF input frequency. Writing to the MUL bits will cause locks to be lost and the fine calibration value to be reset to its midpoint. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 216

20.8.12 DFLL48M Synchronization

Name: DFLLSYNC Offset: 0x24 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 READREQ Access W Reset 0 Bit 7 – READREQ Read Request To be able to read the current value of the DFLLVAL register in closed-loop mode, this bit must be written to '1'. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 217

20.8.13 DPLL Control A

Name: DPLLCTRLA Offset: 0x28 Reset: 0x80 Property: PAC Write-Protection, Write-Synchronized (ENABLE) Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY ENABLE Access R/W R/W R/W Reset 1 0 0 Bit 7 – ONDEMAND On Demand Clock Activation The On Demand operation mode allows the DPLL to be enabled or disabled depending on peripheral clock requests. If the ONDEMAND bit has been previously written to '1', the DPLL will only be running when requested by a peripheral. If there is no peripheral requesting the DPLL’s clock source, the DPLL will be in a disabled state. If On Demand is disabled the DPLL will always be running when enabled. In standby sleep mode, the On Demand operation is still active. Value Description 0 The DPLL is always on, if enabled. 1 The DPLL is enabled when a peripheral is requesting the DPLL to be used as a clock source. The DPLL is disabled if no peripheral is requesting the clock source. Bit 6 – RUNSTDBY Run in Standby This bit controls how the DPLL behaves during standby sleep mode: Value Description 0 The DPLL is disabled in standby sleep mode if no peripheral requests the clock. 1 The DPLL is not stopped in standby sleep mode. If ONDEMAND=1, the DPLL will be running when a peripheral is requesting the clock. If ONDEMAND=0, the clock source will always be running in standby sleep mode. Bit 1 – ENABLE DPLL Enable The software operation of enabling or disabling the DPLL takes a few clock cycles, so the DPLLSYNCBUSY.ENABLE status bit indicates when the DPLL is successfully enabled or disabled. Value Description 0 The DPLL is disabled. 1 The DPLL is enabled. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 218

20.8.14 DPLL Ratio Control

Name: DPLLRATIO Offset: 0x2C Reset: 0x00000000 Property: PAC Write-Protection, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 LDRFRAC[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 LDR[11:8] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 19:16 – LDRFRAC[3:0] Loop Divider Ratio Fractional Part Writing these bits selects the fractional part of the frequency multiplier. Due to synchronization there is a delay between writing these bits and the effect on the DPLL output clock. The value written will read back immediately and the DPLLRATIO bit in the DPLL Synchronization Busy register (DPLLSYNCBUSY.DPLLRATIO) will be set. DPLLSYNCBUSY.DPLLRATIO will be cleared when the operation is completed. Bits 11:0 – LDR[11:0] Loop Divider Ratio Writing these bits selects the integer part of the frequency multiplier. The value written to these bits will read back immediately, and the DPLLRATIO bit in the DPLL Synchronization busy register (DPLLSYNCBUSY.DPLLRATIO), will be set. DPLLSYNCBUSY.DPLLRATIO will be cleared when the operation is completed. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 219

20.8.15 DPLL Control B

Name: DPLLCTRLB Offset: 0x30 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 DIV[10:8] Access R/W R/W R/W Reset 0 0 0 Bit 23 22 21 20 19 18 17 16 DIV[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 LBYPASS LTIME[2:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 REFCLK[1:0] WUF LPEN FILTER[1:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bits 26:16 – DIV[10:0] Clock Divider These bits set the XOSC clock division factor and can be calculated with following formula: fD I V = f XOSC 2x D I V + 1 Bit 12 – LBYPASS Lock Bypass Value Description 0 DPLL Lock signal drives the DPLL controller internal logic. 1 DPLL Lock signal is always asserted. Bits 10:8 – LTIME[2:0] Lock Time These bits select the lock time-out value: Value Name Description 0x0 Default No time-out. Automatic lock. 0x1 Reserved 0x2 Reserved 0x3 Reserved 0x4 8MS Time-out if no lock within 8ms 0x5 9MS Time-out if no lock within 9ms 0x6 10MS Time-out if no lock within 10ms 0x7 11MS Time-out if no lock within 11ms Bits 5:4 – REFCLK[1:0] Reference Clock Selection Write these bits to select the DPLL clock reference: Value Name Description 0x0 XOSC32K XOSC32K clock reference 0x1 XOSC XOSC clock reference 0x2 GCLK GCLK clock reference SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 220

Bit 3 – WUF Wake Up Fast Value Description 0 DPLL clock is output after startup and lock time. 1 DPLL clock is output after startup time. Bit 2 – LPEN Low-Power Enable Value Description 0 The low-power mode is disabled. Time to Digital Converter is enabled. 1 The low-power mode is enabled. Time to Digital Converter is disabled. This will improve power consumption but increase the output jitter. Bits 1:0 – FILTER[1:0] Proportional Integral Filter Selection These bits select the DPLL filter type: Value Name Description 0x0 DEFAULT Default filter mode 0x1 LBFILT Low bandwidth filter 0x2 HBFILT High bandwidth filter 0x3 HDFILT High damping filter SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 221

20.8.16 DPLL Prescaler

Name: DPLLPRESC Offset: 0x34 Reset: 0x00 Property: PAC Write-Protection, Write-Synchronized Bit 7 6 5 4 3 2 1 0 PRESC[1:0] Access R/W R/W Reset 0 0 Bits 1:0 – PRESC[1:0] Output Clock Prescaler These bits define the output clock prescaler setting. Value Name Description 0x0 DIV1 DPLL output is divided by 1 0x1 DIV2 DPLL output is divided by 2 0x2 DIV4 DPLL output is divided by 4 0x3 Reserved SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 222

20.8.17 DPLL Synchronization Busy

Name: DPLLSYNCBUSY Offset: 0x38 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 DPLLPRESC DPLLRATIO ENABLE Access R R R Reset 0 0 0 Bit 3 – DPLLPRESC DPLL Prescaler Synchronization Status Value Description 0 The DPLLRESC register has been synchronized. 1 The DPLLRESC register value has changed and its synchronization is in progress. Bit 2 – DPLLRATIO DPLL Loop Divider Ratio Synchronization Status Value Description 0 The DPLLRATIO register has been synchronized. 1 The DPLLRATIO register value has changed and its synchronization is in progress. Bit 1 – ENABLE DPLL Enable Synchronization Status Value Description 0 The DPLLCTRLA.ENABLE bit has been synchronized. 1 The DPLLCTRLA.ENABLE bit value has changed and its synchronization is in progress. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 223

20.8.18 DPLL Status

Name: DPLLSTATUS Offset: 0x3C Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 CLKRDY LOCK Access R R Reset 0 0 Bit 1 – CLKRDY DPLL Clock Ready Value Description 0 The DPLL output clock is off. 1 The DPLL output clock in on. Bit 0 – LOCK DPLL Lock Value Description

0 The DPLL Lock signal is cleared, when the DPLL is disabled or when the DPLL is trying to reach the

target frequency. 1 The DPLL Lock signal is asserted when the desired frequency is reached. SAM L22 Family OSCCTRL – Oscillators Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 224

OSC32KCTRL – 32.768 kHz Oscillators Controller

21.1 Overview

The 32.768 kHz Oscillators Controller (OSC32KCTRL) provides a user interface to the 32.768 kHz oscillators:

A 32.768 kHz crystal oscillator (XOSC32K)
A 32.768 kHz ultra low-power internal RC oscillator (OSCULP32K)

21.2 Features

32.768 kHz Crystal Oscillator (XOSC32K) – Programmable start-up time – Crystal or external input clock on XIN32 I/O – Clock failure detection with safe clock switch – Clock failure event output
32.768 kHz Ultra Low-Power Internal Oscillator (OSCULP32K) – Ultra low-power, always-on oscillator – Frequency fine tuning
1.024 kHz clock outputs available

21.3 Block Diagram

Figure 21-1. OSC32KCTRL Block Diagram

21.4 Signal Description

XIN32 Analog Input 32.768 kHz Crystal Oscillator or external clock input XOUT32 Analog Output 32.768 kHz Crystal Oscillator output The I/O lines are automatically selected when XOSC32K is enabled. Note: The signal of the external crystal oscillator may affect the jitter of neighboring pads.

21.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

21.5.1 I/O Lines

I/O lines are configured by OSC32KCTRL when XOSC32K is enabled and need no user configuration.

21.5.2 Power Management

The OSC32KCTRL will continue to operate in any sleep mode where a 32.768 kHz oscillator is running as source clock. The OSC32KCTRL interrupts can be used to wake up the device from sleep modes. SAM L22 Family OSC32KCTRL – 32.768 kHz Oscillators Controll... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 225

21.5.3 Clocks

The OSC32KCTRL gathers controls for both 32.768 kHz oscillators and provides clock sources to the Generic Clock Controller (GCLK), Real-Time Counter (RTC), Segment Liquid Crystal Controller (SLCD) and Watchdog Timer (WDT). The available clock sources are: XOSC32K and OSCULP32K. The OSC32KCTRL bus clock (CLK_OSC32KCTRL_APB) can be enabled and disabled in the Main Clock module (MCLK).

21.5.4 Interrupts

The interrupt request lines are connected to the interrupt controller. Using the OSC32KCTRL interrupts requires the interrupt controller to be configured first.

21.5.5 Events

The events of this peripheral are connected to the Event System.

21.5.6 Debug Operation

When the CPU is halted in debug mode, OSC32KCTRL will continue normal operation. If OSC32KCTRL is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging.

21.5.7 Register Access Protection

All registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Interrupt Flag Status and Clear (INTFLAG) register Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. PAC write protection does not apply to accesses through an external debugger.

21.5.8 Analog Connections

The external 32.768 kHz crystal must be connected between the XIN32 and XOUT32 pins, along with any required load capacitors. For details on recommended oscillator characteristics and capacitor load, refer to the related links.

21.6 Functional Description

21.6.1 Principle of Operation

XOSC32K and OSCULP32K are configured via OSC32KCTRL control registers. Through this interface, the sub- peripherals are enabled, disabled. The STATUS register gathers different status signals coming from the sub-peripherals of OSC32KCTRL. The status signals can be used to generate system interrupts, and in some cases wake up the system from standby mode, provided the corresponding interrupt is enabled. 21.6.2 32.768 kHz External Crystal Oscillator (XOSC32K) Operation The XOSC32K can operate in the following two modes:

External clock, with an external clock signal connected to XIN32
Crystal oscillator, with an external 32.768 kHz crystal connected between XIN32 and XOUT32 At reset, the XOSC32K is disabled, and the XIN32/XOUT32 pins can either be used as General Purpose I/O (GPIO) pins or by other peripherals in the system. When XOSC32K is enabled, the operating mode determines the GPIO usage. When in crystal oscillator mode, the XIN32 and XOUT32 pins are controlled by the OSC32KCTRL, and GPIO functions are overridden on both pins. SAM L22 Family OSC32KCTRL – 32.768 kHz Oscillators Controll... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 226

When in external clock mode, the only XIN32 pin will be overridden and controlled by the OSC32KCTRL, while the XOUT32 pin can still be used as a GPIO pin. The XOSC32K is enabled by writing a '1' to the Enable bit in the 32.768 kHz External Crystal Oscillator Control register (XOSC32K.ENABLE = 1). The XOSC32K is disabled by writing a '0' to the Enable bit in the 32.768 kHz External Crystal Oscillator Control register (XOSC32K.ENABLE = 0). To enable the XOSC32K as a crystal oscillator, the XTALEN bit in the 32.768 kHz External Crystal Oscillator Control register must be set (XOSC32K.XTALEN = 1). If XOSC32K.XTALEN is '0', the external clock input will be enabled. The XOSC32K 32.768 kHz output is enabled by setting the 32.768 kHz Output Enable bit in the 32.768 kHz External Crystal Oscillator Control register (XOSC32K.EN32K = 1). The XOSC32K also has a 1.024 kHz clock output, which can only be used by the RTC. This clock output is enabled by setting the 1.024 kHz Output Enable bit in the 32.768 kHz External Crystal Oscillator Control register (XOSC32K.EN1K = 1). It is also possible to lock the XOSC32K configuration by setting the Write Lock bit in the 32.768 kHz External Crystal Oscillator Control register (XOSC32K.WRTLOCK = 1). If set, the XOSC32K configuration is locked until a Power-On Reset (POR) is detected. The XOSC32K will behave differently in different sleep modes based on the settings of XOSC32K.RUNSTDBY, XOSC32K.ONDEMAND, and XOSC32K.ENABLE. If XOSC32KCTRL.ENABLE = 0, the XOSC32K will be always stopped. For XOS32KCTRL.ENABLE = 1, the following table is valid: Table 21-1. XOSC32K Sleep Behavior CPU Mode XOSC32K. RUNSTDBY XOSC32K. ONDEMAND Sleep Behavior of XOSC32K and CFD Active or Idle - 0 Always run Active or Idle - 1 Run if requested by peripheral Standby 1 0 Always run Standby 1 1 Run if requested by peripheral Standby 0 - Run if requested by peripheral As a crystal oscillator usually requires a very long start-up time, the 32.768 kHz External Crystal Oscillator will keep running across resets when XOSC32K.ONDEMAND = 0, except for Power-on Reset (POR). After a reset or when waking up from a Sleep mode where the XOSC32K was disabled, the XOSC32K will need a certain amount time to stabilize on the correct frequency. This stabilization time can be configured by changing the Oscillator Start-Up Time bit group (XOSC32K.STARTUP) in the 32.768 kHz External Crystal Oscillator Control register. During the start-up time, the oscillator output is masked to ensure that no unstable clock propagates to the digital logic. Once the external clock or crystal oscillator is stable and ready to be used as a clock source, the XOSC32K Ready bit in the Status register is set (STATUS.XOSC32KRDY = 1). The transition of STATUS.XOSC32KRDY from '0' to '1' generates an interrupt if the XOSC32K Ready bit in the Interrupt Enable Set register is set (INTENSET.XOSC32KRDY = 1). Important: The right XOSC32K.STARTUP stabilization time must be selected by considering the Crystal Start-up Time parameter given in the “XOSC32K Electrical Specification” section of the “Electrical Characteristics” chapter. The XOSC32K can be used as a source for Generic Clock Generators (GCLK) or for the Real-Time Counter (RTC). Before enabling the GCLK or the RTC module, the corresponding oscillator output must be enabled (XOSC32K.EN32K or XOSC32K.EN1K) in order to ensure proper operation. In the same way, the GCLK or RTC modules must be disabled before the clock selection is changed. For additional information on RTC clock configuration, refer to 21.6.6. Real-Time Counter Clock Selection. SAM L22 Family OSC32KCTRL – 32.768 kHz Oscillators Controll... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 227

21.6.3 Clock Failure Detection Operation

The Clock Failure Detector (CFD) allows the user to monitor the external clock or crystal oscillator signal provided by the external oscillator (XOSC32K). The CFD detects failing operation of the XOSC32K clock with reduced latency, and allows to switch to a safe clock source in case of clock failure. The user can also switch from the safe clock back to XOSC32K in case of recovery. The safe clock is derived from the OSCULP32K oscillator with a configurable prescaler. This allows to configure the safe clock in order to fulfill the operative conditions of the microcontroller. In sleep modes, CFD operation is automatically disabled when the external oscillator is not requested to run by a peripheral, see XOSC32K Sleep Behavior for additional information. The user interface registers allow to enable, disable, and configure the CFD. The Status register provides status flags on failure and clock switch conditions. The CFD can optionally trigger an interrupt or an event when a failure is detected. Clock Failure Detection The CFD is reset only at Power-on Reset (POR). The CFD does not monitor the XOSC32K clock when the oscillator is disabled (XOSC32K.ENABLE = 0). Before starting CFD operation, the user must start and enable the safe clock source (OSCULP32K oscillator). CFD operation is started by writing a '1' to the CFD Enable bit in the External Oscillator Control register (CFDCTRL.CFDEN). After starting or restarting the XOSC32K, the CFD does not detect failure until the crystal oscillator stabilization time has elapsed (XOSC32K.STARTUP). Once this stabilization time is elapsed, the XOSC32K clock is constantly monitored. Important: The right XOSC32K.STARTUP stabilization time must be selected by considering the Crystal Start-up Time parameter given in the “XOSC32K Electrical Specification” section of the “Electrical Characteristics” chapter. During a period of 4 safe clocks (monitor period), the CFD watches for a clock activity from the XOSC32K. There must be at least one rising and one falling XOSC32K clock edge during 4 safe clock periods to meet non-failure conditions. If no or insufficient activity is detected, the failure status is asserted: The Clock Failure Detector status bit in the Status register (STATUS.CLKFAIL) and the Clock Failure Detector interrupt flag bit in the Interrupt Flag register (INTFLAG.CLKFAIL) are set. If the CLKFAIL bit in the Interrupt Enable Set register (INTENSET.CLKFAIL) is set, an interrupt is generated as well. If the Event Output enable bit in the Event Control register (EVCTRL.CFDEO) is set, an output event is generated, too. After a clock failure was issued the monitoring of the XOSC32K clock is continued, and the Clock Failure Detector status bit in the Status register (STATUS.CLKFAIL) reflects the current XOSC32K activity. Clock Switch When a clock failure is detected, the XOSC32K clock is replaced by the safe clock in order to maintain an active clock during the XOSC32K clock failure. The safe clock source is the OSCULP32K oscillator clock. Both 32.768 kHz and 1.024 kHz outputs of the XOSC32K are replaced by the respective OSCULP32K 32.768 kHz and 1.024 kHz outputs. The safe clock source can be scaled down by a configurable prescaler to ensure that the safe clock frequency does not exceed the operating conditions selected by the application. When the XOSC32K clock is switched to the safe clock, the Clock Switch bit in the Status register (STATUS.CLKSW) is set. When the CFD has switched to the safe clock, the XOSC32K is not disabled. If desired, the application must take the necessary actions to disable the oscillator. The application must also take the necessary actions to configure the system clocks to continue normal operations. In the case the application can recover the XOSC32K, the application can switch back to the XOSC32K clock by writing a '1' to Switch Back Enable bit in the Clock Failure Control register (CFDCTRL.SWBACK). Once the XOSC32K clock is switched back, the Switch Back bit (CFDCTRL.SWBACK) is cleared by hardware. SAM L22 Family OSC32KCTRL – 32.768 kHz Oscillators Controll... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 228

The CFD has an internal configurable prescaler to generate the safe clock from the OSCULP32K oscillator. The prescaler size allows to scale down the OSCULP32K oscillator so the safe clock frequency is not higher than the XOSC32K clock frequency monitored by the CFD. The maximum division factor is 2. The prescaler is applied on both outputs (32.768 kHz and 1.024 kHz) of the safe clock. Example 21-1. For an external crystal oscillator at 32.768 kHz and the OSCULP32K frequency is 32.768 kHz, the XOSC32K.CFDPRESC should be set to ‘0’ for a safe clock of equal frequency. Event If the Event Output Enable bit in the Event Control register (EVCTRL.CFDEO) is set, the CFD clock failure will be output on the Event Output. When the CFD is switched to the safe clock, the CFD clock failure will not be output on the Event Output. Sleep Mode The CFD is halted depending on configuration of the XOSC32K and the peripheral clock request. For additional information, refer to the Sleep Behavior table above. The CFD interrupt can be used to wake up the device from sleep modes. 21.6.4 32.768 kHz Ultra Low-Power Internal Oscillator (OSCULP32K) Operation The OSCULP32K provides a tunable, low-speed, and ultra low-power clock source. Note: The OSCULP32K is factory-calibrated under typical voltage and temperature conditions. The OSCULP32K is enabled by default after a Power-on Reset (POR), and will always run except during POR. Users can lock the OSCULP32K configuration by setting the Write Lock bit in the 32.768 kHz Ultra Low-Power Internal Oscillator Control register (OSCULP32K.WRTLOCK = 1). If set, the OSCULP32K configuration is locked until POR is detected. The OSCULP32K can be used as a source for Generic Clock Generators (GCLK) or for the Real-Time Counter (RTC). To ensure proper operation, the GCLK or RTC modules must be disabled before the clock selection is changed.

21.6.5 Watchdog Timer Clock Selection

The Watchdog Timer (WDT) uses the internal 1.024 kHz OSCULP32K output clock. This clock is running all the time and internally enabled when requested by the WDT module.

21.6.6 Real-Time Counter Clock Selection

Before enabling the RTC module, the RTC clock must be selected first. All oscillator outputs are valid as RTC clock. The selection is done in the RTC Control register (RTCCTRL). To ensure a proper operation, it is highly recommended to disable the RTC module first, before the RTC clock source selection is changed.

21.6.7 SLCD Clock Selection

Before enabling the SLCD module, the SLCD clock must be selected first. the 32.768kHz outputs of OSCULP32K and XOSC32K are valid as SLCD clock. The selection is done by the SLCD Selection bit in the SLCD Control register (SLCDCTRL.SLCDSEL). To ensure proper operation, it is highly recommended to first disable the SLCD module before the SLCD clock source is selected. changed.

21.6.8 Interrupts

The OSC32KCTRL has the following interrupt sources:

XOSC32KRDY - 32.768 kHz Crystal Oscillator Ready: A 0-to-1 transition on the STATUS.XOSC32KRDY bit is detected SAM L22 Family OSC32KCTRL – 32.768 kHz Oscillators Controll... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 229

CLKFAIL - Clock Failure Detector: A 0-to-1 transition on the STATUS.CLKFAIL bit is detected All these interrupts are synchronous wake-up source. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be enabled individually by setting the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by setting the corresponding bit in the Interrupt Enable Clear register (INTENCLR). The status of enabled interrupts can be read from either INTENSET or INTENCLR. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the OSC32KCTRL is reset. See the INTFLAG register for details on how to clear interrupt flags. The OSC32KCTRL has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register to determine which interrupt condition is present. Refer to the INTFLAG register for details. Note: Interrupts must be globally enabled for interrupt requests to be generated.

21.6.9 Events

The CFD can generate the following output event:

Clock Failure Detector (CFDEO): Generated when the Clock Failure Detector status bit is set in the Status register (STATUS.CLKFAIL). The CFD event is not generated when the Clock Switch bit (STATUS.SWBACK) in the Status register is set. Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.CFDEO) enables the CFD output event. Writing a '0' to this bit disables the CFD output event. Refer to the Event System chapter for details on configuring the event system. SAM L22 Family OSC32KCTRL – 32.768 kHz Oscillators Controll... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 230

21.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 INTENCLR 7:0 CLKFAIL XOSC32KRD Y 15:8 23:16 31:24 0x04 INTENSET 7:0 CLKFAIL XOSC32KRD Y 15:8 23:16 31:24 0x08 INTFLAG 7:0 CLKFAIL XOSC32KRD Y 15:8 23:16 31:24 0x0C STATUS 7:0 CLKSW CLKFAIL XOSC32KRD Y 15:8 23:16 31:24 0x10 RTCCTRL 7:0 RTCSEL[2:0] 0x11 SLCDCTRL 7:0 SLCDSEL 0x12 ... 0x13 Reserved 0x14 XOSC32K 7:0 ONDEMAND RUNSTDBY EN1K EN32K XTALEN ENABLE 15:8 WRTLOCK STARTUP[2:0] 0x16 CFDCTRL 7:0 CFDPRESC SWBACK CFDEN 0x17 EVCTRL 7:0 CFDEO 0x18 ... 0x1B Reserved 0x1C OSCULP32K 7:0 15:8 WRTLOCK CALIB[4:0] 23:16 31:24

21.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. All registers with write-access can be write-protected optionally by the peripheral access controller (PAC). Optional Write-Protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in the register description. Write-protection does not apply to accesses through an external debugger. SAM L22 Family OSC32KCTRL – 32.768 kHz Oscillators Controll... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 231

21.8.1 Interrupt Enable Clear

Name: INTENCLR Offset: 0x00 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CLKFAIL XOSC32KRDY Access R/W R/W Reset 0 0 Bit 2 – CLKFAIL XOSC32K Clock Failure Detection Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the XOSC32K Clock Failure Interrupt Enable bit, which disables the XOSC32K Clock Failure interrupt. Value Description 0 The XOSC32K Clock Failure Detection is disabled. 1 The XOSC32K Clock Failure Detection is enabled. An interrupt request will be generated when the XOSC32K Clock Failure Detection interrupt flag is set. Bit 0 – XOSC32KRDY XOSC32K Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the XOSC32K Ready Interrupt Enable bit, which disables the XOSC32K Ready interrupt. Value Description 0 The XOSC32K Ready interrupt is disabled. 1 The XOSC32K Ready interrupt is enabled. SAM L22 Family OSC32KCTRL – 32.768 kHz Oscillators Controll... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 232

21.8.2 Interrupt Enable Set

Name: INTENSET Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CLKFAIL XOSC32KRDY Access R/W R/W Reset 0 0 Bit 2 – CLKFAIL XOSC32K Clock Failure Detection Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the XOSC32K Clock Failure Interrupt Enable bit, which enables the XOSC32K Clock Failure interrupt. Value Description 0 The XOSC32K Clock Failure Detection is disabled. 1 The XOSC32K Clock Failure Detection is enabled. An interrupt request will be generated when the XOSC32K Clock Failure Detection interrupt flag is set. Bit 0 – XOSC32KRDY XOSC32K Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the XOSC32K Ready Interrupt Enable bit, which enables the XOSC32K Ready interrupt. Value Description 0 The XOSC32K Ready interrupt is disabled. 1 The XOSC32K Ready interrupt is enabled. SAM L22 Family OSC32KCTRL – 32.768 kHz Oscillators Controll... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 233

21.8.3 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x08 Reset: 0x00000000 Property: – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CLKFAIL XOSC32KRDY Access R/W R/W Reset 0 0 Bit 2 – CLKFAIL XOSC32K Clock Failure Detection This flag is cleared by writing a '1' to it. This flag is set on a zero-to-one transition of the XOSC32K Clock Failure Detection bit in the Status register (STATUS.CLKFAIL) and will generate an interrupt request if INTENSET.CLKFAIL is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the XOSC32K Clock Failure Detection flag. Bit 0 – XOSC32KRDY XOSC32K Ready This flag is cleared by writing a '1' to it. This flag is set by a zero-to-one transition of the XOSC32K Ready bit in the Status register (STATUS.XOSC32KRDY), and will generate an interrupt request if INTENSET.XOSC32KRDY=1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the XOSC32K Ready interrupt flag. SAM L22 Family OSC32KCTRL – 32.768 kHz Oscillators Controll... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 234

21.8.4 Status

Name: STATUS Offset: 0x0C Reset: 0x00000000 Property: – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CLKSW CLKFAIL XOSC32KRDY Access R R R Reset 0 0 0 Bit 3 – CLKSW XOSC32K Clock Switch Value Description 0 XOSC32K is not switched and provided the crystal oscillator. 1 XOSC32K is switched to be provided by the safe clock. Bit 2 – CLKFAIL XOSC32K Clock Failure Detector Value Description 0 No XOSC32K failure is detected. 1 A XOSC32K failure is detected. Bit 0 – XOSC32KRDY XOSC32K Ready Value Description 0 XOSC32K is not ready. 1 XOSC32K is stable and ready to be used as a clock source. SAM L22 Family OSC32KCTRL – 32.768 kHz Oscillators Controll... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 235

21.8.5 RTC Clock Selection Control

Name: RTCCTRL Offset: 0x10 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 RTCSEL[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 2:0 – RTCSEL[2:0] RTC Clock Selection These bits select the source for the RTC. Value Name Description 0x0 ULP1K 1.024 kHz from 32.768 kHz internal ULP oscillator 0x1 ULP32K 32.768 kHz from 32.768 kHz internal ULP oscillator 0x2, 0x3 Reserved - 0x4 XOSC1K 1.024 kHz from 32.768 kHz external oscillator 0x5 XOSC32K 32.768 kHz from 32.768 kHz external crystal oscillator 0x6 Reserved - 0x7 Reserved - SAM L22 Family OSC32KCTRL – 32.768 kHz Oscillators Controll... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 236

21.8.6 SLCD Clock Selection Control

Name: SLCDCTRL Offset: 0x11 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 SLCDSEL Access R/W Reset 0 Bit 0 – SLCDSEL SLCD Clock Source Selection This bit selects the clock source for the SLCD Value Description 0 32.768 kHz from 32.768 kHz internal ULP oscillator 1 32.768 kHz from external oscillator SAM L22 Family OSC32KCTRL – 32.768 kHz Oscillators Controll... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 237

21.8.7 32.768 kHz External Crystal Oscillator (XOSC32K) Control Name: XOSC32K Offset: 0x14 Reset: 0x00000080 Property: PAC Write-Protection Bit 15 14 13 12 11 10 9 8 WRTLOCK STARTUP[2:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY EN1K EN32K XTALEN ENABLE Access R/W R/W R/W R/W R/W R/W Reset 1 0 0 0 0 0 Bit 12 – WRTLOCK Write Lock This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration. Value Description 0 The XOSC32K configuration is not locked. 1 The XOSC32K configuration is locked. Bits 10:8 – STARTUP[2:0] Oscillator Start-Up Time This bit field selects the XOSC32K crystal oscillator stabilization time. Important: This stabilization time is for guidance only. A major component of crystal start-up time is based on the second party crystal MFG parasitics that are outside the scope of this specification. If this is a major concern, the customer would need to characterize this based on their design choices. Table 21-2. Stabilization Time for 32.768 kHz External Crystal Oscillator (1) STARTUP[2:0] Number of OSCULP32K Clock Cycles Approximate Equivalent Time (2)[s] 0x0 2048 0.06 0x1 4096 0.13 0x2 16384 0.5 0x3 32768 1 0x4 65536 2 0x5 131072 4 0x6 262144 8 0x7 Reserved Reserved Notes: 1. The OSCULP32K oscillator is used to clock the start-up counter. 2. Actual Start-Up time is the number of selected OSCULP32K cycles + 3 XOSC32K cycles. Bit 7 – ONDEMAND On Demand Control This bit controls how the XOSC32K behaves when a peripheral clock request is detected. For details, refer to XOSC32K Sleep Behavior. Bit 6 – RUNSTDBY Run in Standby This bit controls how the XOSC32K behaves during Standby sleep mode. For details, refer to XOSC32K Sleep Behavior. SAM L22 Family OSC32KCTRL – 32.768 kHz Oscillators Controll... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 238

Bit 4 – EN1K 1.024 kHz Output Enable Value Description 0 The 1.024 kHz output is disabled. 1 The 1.024 kHz output is enabled. Bit 3 – EN32K 32.768 kHz Output Enable Value Description 0 The 32.768 kHz output is disabled. 1 The 32.768 kHz output is enabled. Bit 2 – XTALEN Crystal Oscillator Enable This bit controls the connections between the I/O pads and the external clock or crystal oscillator. Value Description 0 External clock connected on XIN32. XOUT32 can be used as general-purpose I/O. 1 Crystal connected to XIN32/XOUT32. Bit 1 – ENABLE Oscillator Enable Value Description 0 The oscillator is disabled. 1 The oscillator is enabled. SAM L22 Family OSC32KCTRL – 32.768 kHz Oscillators Controll... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 239

21.8.8 Clock Failure Detector Control

Name: CFDCTRL Offset: 0x16 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CFDPRESC SWBACK CFDEN Access R/W R/W R/W Reset 0 0 0 Bit 2 – CFDPRESC Clock Failure Detector Prescaler This bit selects the prescaler for the Clock Failure Detector. Value Description

0 The CFD safe clock frequency is the OSCULP32K frequency

1 The CFD safe clock frequency is the OSCULP32K frequency divided by 2

Bit 1 – SWBACK Clock Switch Back This bit clontrols the XOSC32K output switch back to the external clock or crystal scillator in case of clock recovery. Value Description 0 The clock switch is disabled. 1 The clock switch is enabled. This bit is reset when the XOSC32K output is switched back to the external clock or crystal oscillator. Bit 0 – CFDEN Clock Failure Detector Enable This bit selects the Clock Failure Detector state. Value Description 0 The CFD is disabled. 1 The CFD is enabled. SAM L22 Family OSC32KCTRL – 32.768 kHz Oscillators Controll... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 240

21.8.9 Event Control

Name: EVCTRL Offset: 0x17 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CFDEO Access R/W Reset 0 Bit 0 – CFDEO Clock Failure Detector Event Out Enable This bit controls whether the Clock Failure Detector event output is enabled and an event will be generated when the CFD detects a clock failure. Value Description 0 Clock Failure Detector Event output is disabled, no event will be generated. 1 Clock Failure Detector Event output is enabled, an event will be generated. SAM L22 Family OSC32KCTRL – 32.768 kHz Oscillators Controll... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 241

21.8.10 32.768 kHz Ultra Low-Power Internal Oscillator (OSCULP32K) Control Name: OSCULP32K Offset: 0x1C Reset: 0x0000XX00 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 WRTLOCK CALIB[4:0] Access R/W R/W R/W R/W R/W R/W Reset 0 x x x x x Bit 7 6 5 4 3 2 1 0 Access Reset Bit 15 – WRTLOCK Write Lock This bit locks the OSCULP32K register for future writes to fix the OSCULP32K configuration. Value Description 0 The OSCULP32K configuration is not locked. 1 The OSCULP32K configuration is locked. Bits 12:8 – CALIB[4:0] Oscillator Calibration These bits control the oscillator calibration. These bits are loaded from Flash Calibration at startup. SAM L22 Family OSC32KCTRL – 32.768 kHz Oscillators Controll... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 242

SUPC – Supply Controller

22.1 Overview

The Supply Controller (SUPC) manages the voltage reference, power supply, and supply monitoring of the device. It is also able to control two output pins. The SUPC controls the voltage regulators for the core (VDDCORE) and backup (VDDBU) domains. It sets the voltage regulators according to the sleep modes, or the user configuration. In active mode, the voltage regulators can be selected on the fly between LDO (low-dropout) type regulator or Buck converter. The SUPC supports connection of a battery backup to the VBAT power pin. It includes functionality that enables automatic power switching between main power and battery backup power. This ensures power to the backup domain when the main battery or power source is unavailable. The SUPC embeds two Brown-Out Detectors. BOD33 monitors the voltage applied to the device (VDD or VBAT) and BOD12 monitors the internal voltage to the core (VDDCORE). The BOD can monitor the supply voltage continuously (continuous mode) or periodically (sampling mode). The SUPC generates also a selectable reference voltage which can be used by analog modules like the ADC.

22.2 Features

Voltage Regulator System – Main voltage regulator: LDO or Buck Converter in active mode (MAINVREG) – Low Power voltage regulator in standby mode (LPVREG) – Backup voltage regulator for backup domains – Adjustable VDDCORE to the sleep mode or the performance level – Controlled VDDCORE voltage slope when changing VDDCORE
Battery Backup Power Switch – Automatic switching from main power to battery backup power
Automatic entry to backup mode when switched to battery backup power – Automatic switching from battery backup power to main power
Automatic exit from backup mode when switched back to main power
Stay in backup mode when switched back to main power – Main power request upon wake-up sources from backup mode
Voltage Reference System – Reference voltage for ADC
3.3V Brown-Out Detector (BOD33) – Programmable threshold – Threshold value loaded from NVM User Row at startup – Triggers resets, interrupts, or Battery Backup Power Switch. Action loaded from NVM User Row – Operating modes:
Continuous mode
Sampled mode for low power applications with programmable sample frequency – Hysteresis value from Flash User Calibration – Monitor VDD or VBAT
1.2V Brown-Out Detector (BOD12) – Internal non-configurable Brown-Out Detector
Output pins – Pin toggling on RTC event SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 243

22.3 Block Diagram

Figure 22-1. SUPC Block Diagram LDO Buck Converter LP VREG VDDCORE Backup VREG VDDBU BOD12 VDD BOD33 VBAT Battery Backup Power Switch BOD33 BOD12 VREG BBPS Backup domain Core domain PM performance level sleep mode OUT[1:0] PSOK Wakeup from RTC VREF reference voltages Main VREG Automatic Power Switch BKOUT DETREF

22.4 Signal Description

Signal Name Type Description OUT[1:0] Digital Output SUPC Outputs PSOK Digital Input Main Power Supply OK One signal can be mapped on several pins.

22.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

22.5.1 I/O Lines

I/O lines are configured by SUPC either when the SUPC output (signal OUT) is enabled or when the PSOK input is enabled. The I/O lines need no user configuration.

22.5.2 Power Management

The SUPC can operate in all sleep modes except backup sleep mode. BOD33 and Battery backup Power Switch can operate in backup mode.

22.5.3 Clocks

The SUPC bus clock (CLK_SUPC_APB) can be enabled and disabled in the Main Clock module. SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 244

A 32KHz clock, asynchronous to the user interface clock (CLK_SUPC_APB), is required to run BOD33 and BOD12 in sampled mode. Due to this asynchronicity, writing to certain registers will require synchronization between the clock References: 32KHz Oscillators Controller - OSC32KCTRL Peripheral Clock Masking

22.5.4 DMA

Not applicable.

22.5.5 Interrupts

The interrupt request lines are connected to the Nested Vector Interrupt Controller. Using the SUPC interrupts requires the interrupt controller to be configured first.

22.5.6 Events

Not applicable.

22.5.7 Debug Operation

When the CPU is halted in debug mode, the SUPC continues normal operation. If the SUPC is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. If debugger cold-plugging is detected by the system, BOD33 and BOD12 resets will be masked. The BOD resets keep running under hot-plugging. This allows to correct a BOD33 user level too high for the available supply.

22.5.8 Register Access Protection

Registers with write-access can be write-protected optionally by the peripheral access controller (PAC). Note: Not all registers with write-access can be write-protected. PAC Write-Protection is not available for the following registers:

Interrupt Flag Status and Clear register (INTFLAG) Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register description.

22.5.9 Analog Connections

Not applicable.

22.6 Functional Description

22.6.1 Voltage Regulator System Operation

22.6.1.1 Enabling, Disabling, and Resetting

The LDO main voltage regulator is enabled after any Reset. The main voltage regulator (MAINVREG) can not be disabled, therefore the Enable bit in the VREG register (VREG.ENABLE) must be set to one. The main voltage regulator output supply level is automatically defined by the sleep mode selected in the 19. PM - Power Manager module. References: Power Manager

22.6.1.2 Initialization

After a Reset, the LDO voltage regulator supplying VDDCORE is enabled. SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 245

22.6.1.3 Selecting a Voltage Regulator

In active mode, the type of the main voltage regulator supplying VDDCORE can be switched on the fly. The two alternatives are a LDO regulator and a Buck converter. The main voltage regulator switching sequence:

The user changes the value of the Voltage Regulator Selection bit in the Voltage Regulator System Control register (VREG.SEL)
The start of the switching sequence is indicated by clearing the Voltage Regulator Ready bit in the STATUS register (STATUS.VREGRDY=0)
Once the switching sequence is completed, STATUS.VREGRDY will read '1' The Voltage Regulator Ready (VREGRDY) interrupt can also be used to detect a zero-to-one transition of the STATUS.VREGRDY bit.

22.6.1.4 Voltage Scaling Control

The VDDCORE supply will change under certain circumstances:

When a new performance level (PL) is set
When the standby sleep mode is entered or left
When a sleepwalking task is requested in standby sleep mode To prevent high peak current on the main power supply and to have a smooth transition of VDDCORE, both the voltage scaling step size and the voltage scaling frequency can be controlled: VDDCORE is changed by the selected step size of the selected period until the target voltage is reached. The Voltage Scaling Voltage Step field is in the VREG register, VREG.VSVSTEP. The Voltage Scaling Period field is VREG.VSPER. The following waveform shows an example of changing performance level from PL0 to PL2. VDDCORE time V(PL0) V(PL2) VSVSTEP VSPER Setting VREG.VSVSTEP to the maximum value allows to transition in one voltage step. The STATUS.VCORERDY bit is set to '1' as soon as the VDDCORE voltage has reached the target voltage. During voltage transition, STATUS.VCORERDY will read '0'. The Voltage Ready interrupt (VCORERDY) can be used to When entering the standby sleep mode and when no sleepwalking task is requested, the VDDCORE Voltage scaling control is not used.

22.6.1.5 Sleep Mode Operation

In Standby mode, the low-power voltage regulator (LPVREG) is used to supply VDDCORE. When the Run in Standby bit in the VREG register (VREG.RUNSTDBY) is written to '1', VDDCORE is supplied by the main voltage regulator. Depending on the Standby in PL0 bit in the Voltage Regulator register (VREG.STDBYPL0), the VDDCORE level is either set to the PL0 voltage level, or remains in the current performance level. SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 246

Table 22-1. VDDCORE Level in Standby Mode VREG.RUNSTDBY VREG.STDBYPL0 VDDCORE Supply in Standby Mode 0 - LPVREG 1 0 MAINVREG in current performance level(1) 1 1 MAINVREG in PL0 Note: 1. When the device is in PL0 but VREG.STDBYPL0 = 0, the MAINVREG is operating in normal power mode. To minimize power consumption, operate MAINVREG in PL0 mode by selecting VREG.STDBYPL0 = 1. By writing the Low-Power mode Efficiency bit in the VREG register (VREG.LPEFF) to '1', the efficiency of the regulator in LPVREG can be improved when the application uses a limited VDD range (2.5 to 3.6V). It is also possible to use the BOD33 to monitor the VDD and change this LPEFF value on the fly according to VDD level. References:

22.6.2 Voltage Reference System Operation

The reference voltages are generated by a functional block DETREF inside of the SUPC. DETREF is providing a fixed-voltage source, BANDGAP =1.1V, and a variable voltage, INTREF.

22.6.2.1 Initialization

The voltage reference output is disabled after any Reset.

22.6.2.2 Enabling, Disabling, and Resetting

The voltage reference output is enabled or disabled by setting or clearing the Voltage Reference Output Enable bit in the Voltage Reference register (VREF.VREFOE).

22.6.2.3 Selecting a Voltage Reference

The Voltage Reference Selection bit field in the VREF register (VREF.SEL) selects the voltage of INTREF to be applied to analog modules, for example the ADC.

22.6.2.4 Sleep Mode Operation

The Voltage Reference output behavior during Sleep mode can be configured using the Run in Standby bit and the On Demand bit in the Voltage Reference register (VREF.RUNSTDBY, VREF.ONDEMAND), see the following table: Table 22-2. VREF Sleep Mode Operation VREF.ONDEMAND VREF.RUNSTDBY Voltage Reference Sleep behavior - - Disable 0 0 Always run in all sleep modes except Standby Sleep mode 0 1 Always run in all sleep modes including Standby Sleep mode 1 0 Only run if requested by the ADC, in all sleep modes except Standby sleep mode 1 1 Only run if requested by the ADC, in all sleep modes including Standby sleep mode

22.6.3 Battery Backup Power Switch

22.6.3.1 Initialization

The Battery Backup Power Switch (BBPS) is disabled at power-up, and the backup domain is supplied by main power. SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 247

22.6.3.2 Forced Battery Backup Power Switch

The Backup domain is always supplied by the VBAT supply pin when the Configuration bit field in the Battery Backup Power Switch Control register (BBPS.CONF) is written to 0x2 (FORCED).

22.6.3.3 Automatic Battery Backup Power Switch

The supply of the backup domain can be switched automatically to VBAT supply pin by the Automatic Power Switch or by using the BOD33. The supply of the backup domain can be switched automatically to VDD supply pin either by the Automatic Power Switch or the Main Power Pin when VDD and VDDCORE are restored. Automatic Power Switch (APWS) When the Configuration bit field in the Battery Backup Power Switch register (BBPS.CONF) is selecting the APWS, the Automatic Power Switch will function as Battery Backup Power Switch. The Automatic Power switch allows to switch the supply of the backup domain from VDD to VBAT power and vice-versa. When the Automatic Power Switch configuration is selected, the Automatic Power Switch Ready bit in the Status register (STATUS.APWSRDY) is set when the Automatic Power Switch is ready to operate. The Automatic Power Switch Ready bit in the Interrupt Flag Status and Clear (INTFLAG.APSWRDY) will be set at the same time. BOD33 Power Switch When the Configuration bit field in the Battery Backup Power Switch register (BBPS.CONF) are selecting the BOD33, BOD33 will function as Battery Backup Power Switch. In this case, when the VDD voltage is below the BOD33 threshold, the backup domain supply is switched to VBAT. Main Power Supply OK (PSOK) Pin Enable The state of the Main Power VDD can be used to switch between supply sources as long as the Battery Backup Power Switch is not configured as Automatic Power Switch (i.e., BBPS.CONF not set to APWS): when the Main Power Supply OK Pin Enable bit in the BBPS register is written to '1' (BBPS.PSOKEN), restoring VDD will form a low-to-high transition on the PSOK pin. This low-to-high transition will switch the Backup Power Supply back to VDD. Note: With BBPS.PSOKEN=0 and BBPS.CONF not configured to APWS, the device can not be restarted. Backup Battery Power Switch Status The Battery Backup Power Switch bit in the Status register (STATUS.BBPS) indicates whether the backup domain is currently powered by VDD or VBAT.

22.6.3.4 Sleep Mode Operation

The Battery Backup Power Switch is not stopped in any sleep mode. Entering Battery Backup Mode Entering backup mode can be triggered by either:

Wait-for-interrupt (WFI) instruction.
Automatic Power Switch (BBPS.CONF=APWS). When the Automatic Power Switch detects loss of Main Power, the Backup Domain will be powered by battery and the device will enter the backup mode.
BOD33 detection: When the BOD33 detects loss of Main Power, the Backup Domain will be powered by battery and the device will enter the backup mode. For this trigger, the following register configuration is required: BOD33.ACTION=BKUP, BOD33.VMON=VDD, and BBPS.CONF=BOD33. Leaving Battery Backup Mode Leaving backup mode can be triggered by either:
RTC requests and externally triggered RSTC requests, under one of these conditions: – The Backup Domain is supplied by Main Power, and the Battery Backup Power Switch is not forced (BBPS.CONF not set to FORCED) – The Battery Backup Power Switch is forced (BBPS.CONF is FORCED) SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 248

The device is kept in battery-powered backup mode until Main Power is restored to supply the device. Then, the backup domain will be powered by Main Power.

Automatic Power Switch. Leaving backup mode will happen when Main Power is restored and the Battery Backup Power Switch configuration (BBPS.CONF) is set to APWS: When BBPS.WAKEEN=1, the device will leave backup mode and wake up. When BBPS.WAKEEN=0, the backup domain will be powered by Main Power, but the device will stay in backup mode.
PSOK pin. A low-to-high transition on PSOK will wake up the device if BBPS.PSOKEN=1, BBPS.WAKEEN=1, and the Battery Backup Power Switch is different from APWS (BBPS.CONF is not APWS). When BBPS.WAKEEN=0, the backup domain will be powered by Main Power, but the device will stay in backup mode.

22.6.4 Output Pins

The SUPC can drive two outputs. By writing a '1' to the corresponding Output Enable bit in the Backup Output Control register (BKOUT.EN), the OUTx pin is driven by the SUPC. The OUT pin can be set by writing a '1' to the corresponding Set Output bit in the Backup Output Control register (BKOUT.SETx). The OUT pin can be cleared by writing a '1' to the corresponding CLR bit (BKOUT.CLRx). If a RTC Toggle Enable bit is written to '1' (BKOUT.RTCTGLx), the corresponding OUTx pin will toggle when an RTC event occurs.

22.6.5 Brown-Out Detectors

22.6.5.1 Initialization

Before a Brown-Out Detector (BOD33) is enabled, it must be configured, as outlined by the following:

Set the BOD threshold level (BOD33.LEVEL)
Set the configuration in active, standby, backup modes (BOD33.ACTCDG, BOD33.STDBYCFG, BODVDD.BKUP)
Set the prescaling value if the BOD will run in sampling mode (BOD33.PSEL)
Set the action and hysteresis (BOD33.ACTION and BOD33.HYST) The BOD33 register is Enable-Protected, meaning that they can only be written when the BOD is disabled (BOD33.ENABLE=0 and SYNCBUSY.BOD33EN=0). As long as the Enable bit is '1', any writes to Enable-Protected registers will be discarded, and an APB error will be generated. The Enable bits are not Enable-Protected.

22.6.5.2 Enabling, Disabling, and Resetting

After power or user reset, the BOD33 and BOD12 register values are loaded from the NVM User Row. The BODVDD is enabled by writing a '1' to the Enable bit in the BOD control register (BOD33.ENABLE). The BOD is disabled by writing a '0' to the BODVDD.ENABLE. References: NVM User Row Mapping 22.6.5.3 3.3V Brown-Out Detector (BOD33) The 3.3V Brown-Out Detector (BOD33) is able to monitor either the VDD or the VBAT supply . The Voltage Monitored bit in the BOD33 Control register (BOD33.VMON) selects which supply is monitored in active and standby mode. In backup mode, BOD33 will always monitor the supply of the backup domain, i.e. either VDD or VBAT. If VDD is monitored, the BOD33 compares the voltage with the brown-out threshold level. This level is set in the BOD33 Level field in the BOD33 register (BOD33.LEVEL). This level is used in all modes except the backup sleep modes. In backup sleep modes, a different voltage reference is used, which is configured by the BOD33.BKUPLEVEL bits. When VDD crosses below the brown-out threshold level, the BOD33 can generate either an interrupt, a Reset, or an Automatic Battery Backup Power Switch, depending on the BOD33 Action bit field (BOD33.ACTION). SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 249

If VBAT is monitored, the BOD33 compares the voltage with the brown-out threshold level set in the BOD33 Backup Level field in the BOD33 register (BOD33.BKUPLEVEL). When VBAT crosses below the backup brown-out threshold level, the BOD33 can generate either an interrupt or a Reset. The BOD33 detection status can be read from the BOD33 Detection bit in the Status register (STATUS.BOD33DET). At start-up or at Power-On Reset (POR), the BOD33 register values are loaded from the NVM User Row. References: 9.3. NVM User Row Mapping 22.6.5.4 1.2V Brown-Out Detector (BOD12) The BOD12 is calibrated in production and its calibration configuration is stored in the NVM User Row. This configuration must not be changed to assure the correct behavior of the BOD12. The BOD12 generates a reset when 1.2V crosses below the preset brown-out level. The BODCORE is always disabled in standby sleep mode. References: NVM User Row Mapping

22.6.5.5 Continuous Mode

Continuous mode is the default mode for BOD33. The BOD33 is continuously monitoring the supply voltage (VDD or VBAT, depending on BOD33.VMON) if it is enabled (BOD33.ENABLE=1) and if the BOD33 Configuration bit in the BOD33 register is cleared (BOD33.ACTCFG=0 for active mode, BOD33.STDBYCFG=0 for standby mode).

22.6.5.6 Sampling Mode

The Sampling Mode is a low-power mode where the BOD33 is being repeatedly enabled on a sampling clock’s ticks. The BOD33 will monitor the supply voltage for a short period of time and then go to a low-power disabled state until the next sampling clock tick. Sampling mode is enabled in Active mode for BOD33 by writing the ACTCFG bit (BOD33.ACTCFG=1). Sampling mode is enabled in Standby mode by writing to the STDBYCFG bit (BOD33.STBYCFG=1). The frequency of the clock ticks (Fclksampling) is controlled by the Prescaler Select bit groups in the BOD33 register (BOD33.PSEL). F c l k s amp l i n g = F c l k p res c al er

2 PSEL + 1

The prescaler signal (Fclkprescaler) is a 1KHz clock, output by the 32KHz Ultra Low Power Oscillator OSCULP32K. As the sampling clock is different from the APB clock domain, synchronization among the clocks is necessary. See also 22.6.7. Synchronization.

22.6.5.7 Hysteresis

A hysteresis on the trigger threshold of a BOD will reduce the sensitivity to ripples on the monitored voltage: instead of switching RESET at each crossing of VBOD, the thresholds for switching RESET on and off are separated (VBOD- and VBOD+, respectively). Figure 22-2. BOD Hysteresis Principle Hysteresis OFF: VCC RESET VBOD Hysteresis ON: SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 250

Enabling the BOD33 hysteresis by writing the Hysteresis bit in the BOD33 register (BOD33.HYST) to '1' will add hysteresis to the BOD33 threshold level. The hysteresis functionality can be used in both Continuous and Sampling Mode.

22.6.5.8 Sleep Mode Operation

22.6.5.8.1 Standby Mode

The BOD33 can be used in standby mode if the BOD is enabled and the corresponding Run in Standby bit is written to '1' (BOD33.RUNSTDBY). The BOD33 can be configured to work in either Continuous or Sampling Mode by writing a '1' to the Configuration in Standby Sleep Mode bit (BOD33.STDBYCFG).

22.6.5.8.2 Backup Mode

In Backup mode, the BOD12 is automatically disabled. If the BOD33 is enabled and the Run in Backup sleep mode bit in the BOD33 register (BOD33.RUNBKUP) is written to '1', the BOD33 will operate in Sampling mode. In this state, the voltage monitored by BOD33 is always the supply of the backup domain, i.e. VDD or VBAT.

22.6.6 Interrupts

The SUPC has the following interrupt sources, which are either synchronous or asynchronous wake-up sources:

VDDCORE Voltage Ready (VCORERDY), asynchronous
Automatic Power Switch Ready Ready (APSWRDY), asynchronous
Voltage Regulator Ready (VREGRDY) asynchronous
BOD33 Ready (BOD33RDY), synchronous
BOD33 Detection (BOD33DET), asynchronous
BOD33 Synchronization Ready (B33SRDY), synchronous Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the SUPC is reset. See the INTFLAG register for details on how to clear interrupt flags. The SUPC has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register to determine which interrupt condition is present. Note: Interrupts must be globally enabled for interrupt requests to be generated. References: Nested Vector Interrupt Controller Sleep Mode Controller

22.6.7 Synchronization

The prescaler counters that are used to trigger brown-out detections operate asynchronously from the peripheral bus. As a consequence, the BOD33 Enable bit (BOD33.ENABLE) need synchronization when written. The Write-Synchronization of the Enable bit is triggered by writing a '1' to the Enable bit of the BOD33 Control register. The Synchronization Ready bit (STATUS.B33SRDY) in the STATUS register will be cleared when the Write-Synchronization starts, and set again when the Write-Synchronization is complete. Writing to the same register SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 251

while the Write-Synchronization is ongoing (STATUS.B33SRDY is '0') will generate an error without stalling the APB bus. SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 252

22.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 INTENCLR 7:0 B33SRDY BOD33DET BOD33RDY 15:8 VCORERDY APWSRDY VREGRDY 23:16 31:24 0x04 INTENSET 7:0 B33SRDY BOD33DET BOD33RDY 15:8 VCORERDY APWSRDY VREGRDY 23:16 31:24 0x08 INTFLAG 7:0 B33SRDY BOD33DET BOD33RDY 15:8 VCORERDY APWSRDY VREGRDY 23:16 31:24 0x0C STATUS 7:0 B33SRDY BOD33DET BOD33RDY 15:8 BBPS VCORERDY APWSRDY VREGRDY 23:16 31:24 0x10 BOD33 7:0 RUNBKUP RUNSTDBY STDBYCFG ACTION[1:0] HYST ENABLE 15:8 PSEL[3:0] VMON ACTCFG 23:16 LEVEL[5:0] 31:24 BKUPLEVEL[5:0] 0x14 ... 0x17 Reserved 0x18 VREG 7:0 RUNSTDBY STDBYPL0 SEL[1:0] ENABLE 15:8 LPEFF 23:16 VSVSTEP[3:0] 31:24 VSPER[7:0] 0x1C VREF 7:0 ONDEMAND RUNSTDBY VREFOE 15:8 23:16 SEL[3:0] 31:24 0x20 BBPS 7:0 PSOKEN WAKEEN CONF[1:0] 15:8 23:16 31:24 0x24 BKOUT 7:0 EN[1:0] 15:8 CLR[1:0] 23:16 SET[1:0] 31:24 RTCTGL[1:0] 0x28 BKIN 7:0 BKIN[2:0] 15:8 23:16 31:24

22.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). PAC Write-protection is denoted by the "PAC Write-Protection" property in each individual register description. Refer to 22.5.8. Register Access Protection for details. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Write-Synchronized" or the "Read-Synchronized" property in each individual register description. Refer to 22.6.7. Synchronization for details. SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 253

22.8.1 Interrupt Enable Clear

1 The VDDCORE Ready interrupt is enabled and an interrupt request will be generated when the

VCORERDY Interrupt Flag is set. Bit 9 – APWSRDY Automatic Power Switch Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Automatic Power Switch Ready Interrupt Enable bit, which disables the Automatic Power Switch Ready interrupt. Value Description 0 The Automatic Power Switch Ready interrupt is disabled.

1 The Automatic Power Switch Ready interrupt is enabled and an interrupt request will be generated

when the APWSRDY Interrupt Flag is set. Bit 8 – VREGRDY Voltage Regulator Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Voltage Regulator Ready Interrupt Enable bit, which disables the Voltage Regulator Ready interrupt. Value Description 0 The Voltage Regulator Ready interrupt is disabled.

1 The Voltage Regulator Ready interrupt is enabled and an interrupt request will be generated when the

Bit 2 – B33SRDY BOD33 Synchronization Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the BOD33 Synchronization Ready Interrupt Enable bit, which disables the BOD33 Synchronization Ready interrupt. Value Description 0 The BOD33 Synchronization Ready interrupt is disabled.

1 The BOD33 Synchronization Ready interrupt is enabled, and an interrupt request will be generated

when the BOD33 Synchronization Ready Interrupt flag is set. Bit 1 – BOD33DET BOD33 Detection Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the BOD33 Detection Interrupt Enable bit, which disables the BOD33 Detection interrupt. Value Description 0 The BOD33 Detection interrupt is disabled.

1 The BOD33 Detection interrupt is enabled, and an interrupt request will be generated when the BOD33

Detection Interrupt flag is set. Bit 0 – BOD33RDY BOD33 Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the BOD33 Ready Interrupt Enable bit, which disables the BOD33 Ready interrupt. Value Description 0 The BOD33 Ready interrupt is disabled.

1 The BOD33 Ready interrupt is enabled, and an interrupt request will be generated when the BOD33

22.8.2 Interrupt Enable Set

Name: INTENSET Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 VCORERDY APWSRDY VREGRDY Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 B33SRDY BOD33DET BOD33RDY Access R/W R/W R/W Reset 0 0 0 Bit 10 – VCORERDY VDDCORE Voltage Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the VDDCORE Ready Interrupt Enable bit, which enables the VDDCORE Ready interrupt. Value Description 0 The VDDCORE Ready interrupt is disabled. VCORERDY Interrupt Flag is set. Bit 9 – APWSRDY Automatic Power Switch Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Automatic Power Switch Ready Interrupt Enable bit, which enables the Automatic Power Switch Ready interrupt. Value Description 0 The Automatic Power Switch Ready interrupt is disabled. when the Automatic Power Switch Ready Interrupt Flag is set. Bit 8 – VREGRDY Voltage Regulator Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Voltage Regulator Ready Interrupt Enable bit, which enables the Voltage Regulator Ready interrupt. Value Description 0 The Voltage Regulator Ready interrupt is disabled. Voltage Regulator Ready Interrupt Flag is set. SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 256

Bit 2 – B33SRDY BOD33 Synchronization Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the BOD33 Synchronization Ready Interrupt Enable bit, which enables the BOD33 Synchronization Ready interrupt. Value Description 0 The BOD33 Synchronization Ready interrupt is disabled. when the BOD33 Synchronization Ready Interrupt flag is set. Bit 1 – BOD33DET BOD33 Detection Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the BOD33 Detection Interrupt Enable bit, which enables the BOD33 Detection interrupt. Value Description 0 The BOD33 Detection interrupt is disabled. Detection Interrupt flag is set. Bit 0 – BOD33RDY BOD33 Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the BOD33 Ready Interrupt Enable bit, which enables the BOD33 Ready interrupt. Value Description 0 The BOD33 Ready interrupt is disabled. Ready Interrupt flag is set. SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 257

22.8.3 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x08 Reset: 0x0000010x - x initially determined from NVM User Row after Reset Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 VCORERDY APWSRDY VREGRDY Access R/W R/W R/W Reset 0 0 1 Bit 7 6 5 4 3 2 1 0 B33SRDY BOD33DET BOD33RDY Access R/W R/W R/W Reset 0 0 x Bit 10 – VCORERDY VDDCORE Voltage Ready This flag is cleared by writing a '1 to it. This flag is set on a zero-to-one transition of the VDDCORE Ready bit in the Status register (STATUS.VCORERDY) and will generate an interrupt request if INTENSET.VCORERDY = 1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the VCORERDY interrupt flag. Bit 9 – APWSRDY Automatic Power Switch Ready This flag is cleared by writing a '1' to it. This flag is set on a zero-to-one transition of the Automatic Power Switch Ready bit in the Status register (STATUS.APWSRDY) and will generate an interrupt request if INTENSET.APWSRDY = 1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the APWSRDY interrupt flag. Bit 8 – VREGRDY Voltage Regulator Ready This flag is cleared by writing a '1' to it. This flag is set on a zero-to-one transition of the Voltage Regulator Ready bit in the Status register (STATUS.VREGRDY) and will generate an interrupt request if INTENSET.VREGRDY = 1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the VREGRDY interrupt flag. Bit 2 – B33SRDY BOD33 Synchronization Ready This flag is cleared by writing a '1' to it. This flag is set on a zero-to-one transition of the BOD33 Synchronization Ready bit in the Status register (STATUS.B33SRDY) and will generate an interrupt request if INTENSET.B33SRDY = 1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the BOD33 Synchronization Ready interrupt flag. SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 258

Bit 1 – BOD33DET BOD33 Detection This flag is cleared by writing a '1' to it. This flag is set on a zero-to-one transition of the BOD33 Detection bit in the Status register (STATUS.BOD33DET) and will generate an interrupt request if INTENSET.BOD33DET = 1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the BOD33 Detection interrupt flag. Bit 0 – BOD33RDY BOD33 Ready This flag is cleared by writing a '1' to it. This flag is set on a zero-to-one transition of the BOD33 Ready bit in the Status register (STATUS.BOD33RDY) and will generate an interrupt request if INTENSET.BOD33RDY = 1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the BOD33 Ready interrupt flag. The BOD33 can be enabled. References: 9.3. NVM User Row Mapping SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 259

22.8.4 Status

Name: STATUS Offset: 0x0C Reset: x initially determined from NVM User Row after Reset Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 BBPS VCORERDY APWSRDY VREGRDY Access R R R R Reset 0 1 0 1 Bit 7 6 5 4 3 2 1 0 B33SRDY BOD33DET BOD33RDY Access R R R Reset 0 0 x Bit 11 – BBPS Battery Backup Power Switch Value Description 0 The backup domain is supplied by VDD. 1 The backup domain is supplied by VBAT. Bit 10 – VCORERDY VDDCORE Voltage Ready Value Description 0 The VDDCORE voltage is not as expected. 1 The VDDCORE voltage is the target voltage. Bit 9 – APWSRDY Automatic Power Switch Ready Value Description 0 The Automatic Power Switch is not ready. 1 The Automatic Power Switch is ready. Bit 8 – VREGRDY Voltage Regulator Ready Value Description 0 The selected voltage regulator in VREG.SEL is not ready. 1 The voltage regulator selected in VREG.SEL is ready and the core domain is supplied by this voltage regulator. Bit 2 – B33SRDY BOD33 Synchronization Ready Value Description 0 BOD33 synchronization is ongoing. 1 BOD33 synchronization is complete. Bit 1 – BOD33DET BOD33 Detection Value Description 0 No BOD33 detection. SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 260

1 BOD33 has detected that the I/O power supply is going below the BOD33 reference value. Bit 0 – BOD33RDY BOD33 Ready The BOD33 can be enabled at start-up from the NVM User Row. The state of this bit is only applicable in BODVDD continuous mode. In sampling mode, this bit is never set. References: 0 BOD33 is not ready. 1 BOD33 is ready. SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 261

22.8.5 Brown-Out Detector (BOD33) Control

Name: BOD33 Offset: 0x10 Reset: Determined from NVM User Row Property: PAC Write-Protection, Enable-Protected bits, Write-Synchronized bits Bit 31 30 29 28 27 26 25 24 BKUPLEVEL[5:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 LEVEL[5:0] Access R/W R/W R/W R/W R/W R/W Reset x x x x x x Bit 15 14 13 12 11 10 9 8 PSEL[3:0] VMON ACTCFG Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RUNBKUP RUNSTDBY STDBYCFG ACTION[1:0] HYST ENABLE Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 y y 0 z Bits 29:24 – BKUPLEVEL[5:0] BOD33 Threshold Level on VBAT or in Backup Sleep Mode These bits set the triggering voltage threshold for the BOD33 when the BOD33 monitors VBAT or in backup sleep mode. Note: This bit field is enable-protected. This bit field is not write-synchronized. Bits 21:16 – LEVEL[5:0] BOD33 Threshold Level on VDD These bits set the triggering voltage threshold for the BOD33 when the BOD33 monitors the VDD except in backup sleep mode. These bits are loaded from NVM User Row at start-up. Note: This bit field is enable-protected. This bit field is not write-synchronized. Bits 15:12 – PSEL[3:0] Prescaler Select Selects the prescaler divide-by output for the BOD33 sampling mode. The input clock comes from the OSCULP32K 1.024 kHz output. Note: This bit field is enable-protected. This bit field is not write-synchronized. Value Name Description 0x0 DIV2 Divide clock by 2 0x1 DIV4 Divide clock by 4 0x2 DIV8 Divide clock by 8 0x3 DIV16 Divide clock by 16 0x4 DIV32 Divide clock by 32 0x5 DIV64 Divide clock by 64 0x6 DIV128 Divide clock by 128 0x7 DIV256 Divide clock by 256 0x8 DIV512 Divide clock by 512 0x9 DIV1024 Divide clock by 1024 0xA DIV2048 Divide clock by 2048 0xB DIV4096 Divide clock by 4096 SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 262

0xC DIV8192 Divide clock by 8192 0xD DIV16384 Divide clock by 16384 0xE DIV32768 Divide clock by 32768 0xF DIV65536 Divide clock by 65536 Bit 10 – VMON Voltage Monitored in Active and Standby Mode Note: This bit is enable-protected. This bit is not write-synchronized. Value Description 0 The BOD33 monitors the VDD power pin in active and standby mode. 1 The BOD33 monitors the VBAT power pin in active and standby mode. Bit 8 – ACTCFG BOD33 Configuration in Active Sleep Mode Note: This bit is enable-protected. This bit is not write-synchronized. Value Description 0 In active mode, the BOD33 operates in continuous mode. 1 In active mode, the BOD33 operates in sampling mode. Bit 7 – RUNBKUP BOD33 Configuration in Backup Sleep Mode Note: This bit is enable-protected. This bit is not write-synchronized. Value Description 0 In backup sleep mode, the BOD33 is disabled. 1 In backup sleep mode, the BOD33 is enabled and configured in sampling mode. Bit 6 – RUNSTDBY Run in Standby Note: This bit is enable-protected. This bit is not write-synchronized. Value Description 0 In standby sleep mode, the BOD33 is disabled. 1 In standby sleep mode, the BOD33 is enabled. Bit 5 – STDBYCFG BOD33 Configuration in Standby Sleep Mode If the RUNSTDBY bit is set to '1', the STDBYCFG bit sets the BOD33 configuration in standby sleep mode. Note: This bit is enable-protected. This bit is not write-synchronized. Value Description 0 In standby sleep mode, the BOD33 is enabled and configured in continuous mode. 1 In standby sleep mode, the BOD33 is enabled and configured in sampling mode. Bits 4:3 – ACTION[1:0] BOD33 Action These bits are used to select the BOD33 action when the supply voltage crosses below the BOD33 threshold. These bits are loaded from NVM User Row at start-up. Note: This bit field is enable-protected. This bit field is not write-synchronized. Value Name Description 0x0 NONE No action 0x1 RESET The BOD33 generates a reset 0x2 INT The BOD33 generates an interrupt 0x3 BKUP The BOD33 puts the device in backup sleep mode if VMON=0. No action if VMON=1. Bit 2 – HYST Hysteresis This bit indicates whether hysteresis is enabled for the BOD33 threshold voltage. This bit is loaded from NVM User Row at start-up. Note: This bit is enable-protected. This bit is not write-synchronized. SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 263

0 No hysteresis. 1 Hysteresis enabled. Bit 1 – ENABLE Enable This bit is loaded from NVM User Row at start-up. Notes:

This bit is not enable-protected
This bit is write-synchronized: STATUS.B33SRDY must be checked to ensure the BOD33.ENABLE synchronization is complete Value Description 0 BOD33 is disabled. 1 BOD33 is enabled. SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 264

22.8.6 Voltage Regulator System (VREG) Control

Name: VREG Offset: 0x18 Reset: 0x00000002 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 VSPER[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 VSVSTEP[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 LPEFF Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 RUNSTDBY STDBYPL0 SEL[1:0] ENABLE Access R/W R/W R/W R/W R/W Reset 0 1 0 0 1 Bits 31:24 – VSPER[7:0] Voltage Scaling Period This bitfield sets the period between the voltage steps when the VDDCORE voltage is changing in µs. If VSPER=0, the period between two voltage steps is 1µs. Bits 19:16 – VSVSTEP[3:0] Voltage Scaling Voltage Step This field sets the voltage step height when the VDDCORE voltage is changing to reach the target VDDCORE voltage. The voltage step is equal to 2VSVSTEP* min_step. See the Electrical Characteristics chapter for the min_step voltage level. Bit 8 – LPEFF Low power Mode Efficiency Value Description

0 The voltage regulator in Low power mode has the default efficiency and supports the whole VDD range

(1.62V to 3.6V).

1 The voltage regulator in Low power mode has the highest efficiency and supports a limited VDD range

(2.5V to 3.6V). Bit 6 – RUNSTDBY Run in Standby Value Description 0 The voltage regulator is in low power mode in Standby sleep mode. 1 The voltage regulator is in normal mode in Standby sleep mode. Bit 5 – STDBYPL0 Standby in PL0 This bit selects the performance level (PL) of the main voltage regulator for the Standby sleep mode. This bit is only considered when RUNSTDBY=1. Value Description 0 In Standby sleep mode, the voltage regulator remains in the current performance level. 1 In Standby sleep mode, the voltage regulator is used in PL0. SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 265

Bits 3:2 – SEL[1:0] Voltage Regulator Selection This bit is loaded from NVM User Row at start-up. Value Name Description 0 LDO The voltage regulator in active mode is a LDO voltage regulator. 1 BUCK The voltage regulator in active mode is a buck converter. 2-3 Reserved Reserved Bit 1 – ENABLE Enable Must be set to 1. SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 266

22.8.7 Voltage References System (VREF) Control

Name: VREF Offset: 0x1C Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 SEL[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY VREFOE Access R/W R/W R/W Reset 0 0 0 Bits 19:16 – SEL[3:0] Voltage Reference Selection These bits select the Voltage Reference for the ADC / SDADC/ DAC. Value Name Description 0x0 1V0 1.0V voltage reference typical value 0x1 1V1 1.1V voltage reference typical value 0x2 1V2 1.2V voltage reference typical value 0x3 1V25 1.25V voltage reference typical value 0x4 2V0 2.0V voltage reference typical value 0x5 2V2 2.2V voltage reference typical value 0x6 2V4 2.4V voltage reference typical value 0x7 2V5 2.5V voltage reference typical value Others Reserved Reserved Note: 1. 2.0V to 2.5V can be used when the supply voltage(VDDANA) is higher than 2.7V Bit 7 – ONDEMAND On Demand Control The On Demand operation mode allows to enable or disable the voltage reference depending on peripheral requests. Value Description 0 The voltage reference is always on, if enabled. 1 The voltage reference is enabled when a peripheral is requesting it. The voltage reference is disabled if no peripheral is requesting it. Bit 6 – RUNSTDBY Run In Standby The bit controls how the voltage reference behaves during standby sleep mode. Value Description 0 The voltage reference is halted during standby sleep mode. SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 267

1 The voltage reference is not stopped in standby sleep mode. If VREF.ONDEMAND=1, the voltage reference will be running when a peripheral is requesting it. If VREF.ONDEMAND=0, the voltage reference will always be running in standby sleep mode. Bit 2 – VREFOE Voltage Reference Output Enable Value Description 0 The Voltage Reference output is not available as an ADC input channel. 1 The Voltage Reference output is routed to an ADC input channel. SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 268

22.8.8 Battery Backup Power Switch (BBPS) Control

Name: BBPS Offset: 0x20 Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PSOKEN WAKEEN CONF[1:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 3 – PSOKEN Power Supply OK Enable Value Description 0 The PSOK pin is not used. 1 The PSOK pin is used to determine the status of the Main Power Supply. Bit 2 – WAKEEN Wake Enable Value Description 0 The device is not woken up when switched from battery backup power to Main Power. 1 The device is woken up when switched from battery backup power to Main Power. Bits 1:0 – CONF[1:0] Battery Backup Power Switch Configuration Value Name Description 0x0 NONE The backup domain is always supplied by Main Power. 0x1 APWS The power switch is handled by the Automatic Power Switch. 0x2 FORCED The backup domain is always supplied by Battery Backup Power. 0x3 BOD33 The power switch is handled by the BOD33. SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 269

22.8.9 Backup Output (BKOUT) Control

Name: BKOUT Offset: 0x24 Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 RTCTGL[1:0] Access R/W R/W Reset 0 0 Bit 23 22 21 20 19 18 17 16 SET[1:0] Access W W Reset 0 0 Bit 15 14 13 12 11 10 9 8 CLR[1:0] Access W W Reset 0 0 Bit 7 6 5 4 3 2 1 0 EN[1:0] Access R/W R/W Reset 0 0 Bits 25:24 – RTCTGL[1:0] RTC Toggle Output Value Description 0 The output will not toggle on RTC event. 1 The output will toggle on RTC event. Bits 17:16 – SET[1:0] Set Output Writing a '0' to a bit has no effect. Writing a '1' to a bit will set the corresponding output. Reading this bit returns '0'. Bits 9:8 – CLR[1:0] Clear Output Writing a '0' to a bit has no effect. Writing a '1' to a bit will clear the corresponding output. Reading this bit returns '0'. Bits 1:0 – EN[1:0] Enable Output Value Description 0 The output is not enabled. 1 The output is enabled and driven by the SUPC. SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 270

22.8.10 Backup Input (BKIN) Value

Name: BKIN Offset: 0x28 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 BKIN[2:0] Access R R R Reset 0 0 0 Bits 2:0 – BKIN[2:0] Backup I/O Data Input Value These bits are cleared when the corresponding backup I/O pin detects a logical low level on the input pin or when the backup I/O is not enabled. These bits are set when the corresponding backup I/O pin detects a logical high level on the input pin when the backup I/O is enabled. BKIN[2:0] PAD Description BKIN[0] PSOK If BBPS.PSOKEN=1, BKIN[0] will give the input value of the PSOK pin BKIN[1] OUT[0] If BKOUT.EN[0]=1, BKIN[1] will give the input value of the OUT[0] pin BKIN[2] OUT[1] If BKOUT.EN[1]=1, BKIN[2] will give the input value of the OUT[1] pin SAM L22 Family SUPC – Supply Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 271

WDT – Watchdog Timer

23.1 Overview

The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover from error situations such as runaway or deadlocked code. The WDT is configured to a predefined time-out period, and is constantly running when enabled. If the WDT is not cleared within the time-out period, it will issue a system reset. An early-warning interrupt is available to indicate an upcoming watchdog time-out condition. The window mode makes it possible to define a time slot (or window) inside the total time-out period during which the WDT must be cleared. If the WDT is cleared outside this window, either too early or too late, a system reset will be issued. Compared to the normal mode, this can also catch situations where a code error causes the WDT to be cleared frequently. When enabled, the WDT will run in active mode and all sleep modes. It is asynchronous and runs from a CPU- independent clock source. The WDT will continue operation and issue a system reset or interrupt even if the main clocks fail.

23.2 Features

Issues a system reset if the Watchdog Timer is not cleared before its time-out period
Early Warning interrupt generation
Asynchronous operation from dedicated oscillator
Two types of operation – Normal – Window mode
Selectable time-out periods – From 8 cycles to 16,384 cycles in Normal mode – From 16 cycles to 32,768 cycles in Window mode
Always-On capability

23.3 Block Diagram

Figure 23-1. WDT Block Diagram 0xA5 CLEAR COUNT CLK_WDT_OSC OSC32KCTRL PER/WINDOWS/EWOFFSET Early Warning Interrupt Reset SAM L22 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 272

23.4 Signal Description

Not applicable.

23.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

23.5.1 I/O Lines

Not applicable.

23.5.2 Power Management

The WDT can continue to operate in any sleep mode where the selected source clock is running. The WDT interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes. References: PM - Power Manager

23.5.3 Clocks

The WDT bus clock (CLK_WDT_APB) can be enabled and disabled (masked) in the Main Clock module (MCLK). A 1KHz oscillator clock (CLK_WDT_OSC) is required to clock the WDT internal counter. This clock must be configured and enabled in the 32KHz Oscillator Controller (OSC32KCTRL) before using the WDT. CLK_WDT_OSC is normally sourced from the clock of the internal ultra-low-power oscillator, OSCULP32K. Due to the ultra-low-power design, the oscillator is not very accurate, and so the exact time-out period may vary from device to device. This variation must be kept in mind when designing software that uses the WDT to ensure that the time-out periods used are valid for all devices. The counter clock CLK_WDT_OSC is asynchronous to the bus clock (CLK_WDT_APB). Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains. Refer to Synchronization for further details. References: Peripheral Clock Masking OSC32KCTRL- 32.768 kHz Oscillators Controller

23.5.4 DMA

Not applicable.

23.5.5 Interrupts

The interrupt request line is connected to the interrupt controller. Using the WDT interrupt(s) requires the interrupt controller to be configured first. References: Nested Vector Interrupt Controller

23.5.6 Events

Not applicable.

23.5.7 Debug Operation

When the CPU is halted in debug mode the WDT will halt normal operation. SAM L22 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 273

23.5.8 Register Access Protection

All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Interrupt Flag Status and Clear (INTFLAG) register Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger.

23.5.9 Analog Connections

Not applicable.

23.6 Functional Description

23.6.1 Principle of Operation

The Watchdog Timer (WDT) is a system for monitoring correct program operation, making it possible to recover from error situations such as runaway code, by issuing a Reset. When enabled, the WDT is a constantly running timer that is configured to a predefined time-out period. Before the end of the time-out period, the WDT should be set back, or else, a system Reset is issued. The WDT has two modes of operation, Normal mode and Window mode. Both modes offer the option of Early Warning interrupt generation. The description for each of the basic modes is given below. The settings in the Control A register (CTRLA) and the Interrupt Enable register (handled by INTENCLR/INTENSET) determine the mode of operation: Table 23-1. WDT Operating Modes CTRLA.ENABLE CTRLA.WEN Interrupt Enable Mode 0 x x Stopped 1 0 0 Normal mode 1 0 1 Normal mode with Early Warning interrupt 1 1 0 Window mode 1 1 1 Window mode with Early Warning interrupt

23.6.2 Basic Operation

23.6.2.1 Initialization

The following bits are enable-protected, meaning that they can only be written when the WDT is disabled (CTRLA.ENABLE=0):

Control A register (CTRLA), except the Enable bit (CTRLA.ENABLE)
Configuration register (CONFIG)
Early Warning Interrupt Control register (EWCTRL) Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1', but not at the same time as CTRLA.ENABLE is written to '0'. The WDT can be configured only while the WDT is disabled. The WDT is configured by defining the required Time-Out Period bits in the Configuration register (CONFIG.PER). If Window mode operation is desired, the Window Enable bit in the Control A register must be set (CTRLA.WEN=1) and the Window Period bits in the Configuration register (CONFIG.WINDOW) must be defined. Enable-protection is denoted by the "Enable-Protected" property in the register description.

23.6.2.2 Configurable Reset Values

After a Power-on Reset, some registers will be loaded with initial values from the NVM User Row. SAM L22 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 274

This includes the following bits and bit groups:

Enable bit in the Control A register, CTRLA.ENABLE
Always-On bit in the Control A register, CTRLA.ALWAYSON
Watchdog Timer Windows Mode Enable bit in the Control A register, CTRLA.WEN
Watchdog Timer Windows Mode Time-Out Period bits in the Configuration register, CONFIG.WINDOW
Time-Out Period bits in the Configuration register, CONFIG.PER
Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register, EWCTRL.EWOFFSET References: NVM User Row Mapping

23.6.2.3 Enabling, Disabling, and Resetting

The WDT is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The WDT is disabled by writing a '0' to CTRLA.ENABLE. The WDT can be disabled only if the Always-On bit in the Control A register (CTRLA.ALWAYSON) is '0'.

23.6.2.4 Normal Mode

In Normal mode operation, the length of a time-out period is configured in CONFIG.PER. The WDT is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). Once enabled, the WDT will issue a system reset if a time-out occurs. This can be prevented by clearing the WDT at any time during the time-out period. The WDT is cleared and a new WDT time-out period is started by writing 0xA5 to the Clear register (CLEAR). Writing any other value than 0xA5 to CLEAR will issue an immediate system reset. There are 12 possible WDT time-out (TOWDT) periods, selectable from 8ms to 16s. By default, the early warning interrupt is disabled. If it is desired, the Early Warning Interrupt Enable bit in the Interrupt Enable register (INTENSET.EW) must be written to '1'. The Early Warning Interrupt is disabled again by writing a '1' to the Early Warning Interrupt bit in the Interrupt Enable Clear register (INTENCLR.EW). If the Early Warning Interrupt is enabled, an interrupt is generated prior to a WDT time-out condition. In Normal mode, the Early Warning Offset bits in the Early Warning Interrupt Control register, EWCTRL.EWOFFSET, define the time when the early warning interrupt occurs. The Normal mode operation is illustrated in the figure Normal-Mode Operation. Figure 23-2. Normal-Mode Operation 5 10 15 20 25 30 35 WDT Timeout Early Warning Interrupt Timely WDT Clear t[ms] TOWDT System Reset WDT Count PER[3:0] = 1 EWOFFSET[3:0] = 0

23.6.2.5 Window Mode

In Window mode operation, the WDT uses two different time specifications: the WDT can only be cleared by writing 0xA5 to the CLEAR register after the closed window time-out period (TOWDTW), during the subsequent Normal time-out period (TOWDT). If the WDT is cleared before the time window opens (before TOWDTW is over), the WDT will issue a system reset. Both parameters TOWDTW and TOWDT are periods in a range from 8ms to 16s, so the total duration of the WDT time-out period is the sum of the two parameters. The closed window period is defined by the Window Period bits in the Configuration register (CONFIG.WINDOW), and the open window period is defined by the Period bits in the Configuration register (CONFIG.PER). SAM L22 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 275

By default, the Early Warning interrupt is disabled. If it is desired, the Early Warning Interrupt Enable bit in the Interrupt Enable register (INTENSET.EW) must be written to '1'. The Early Warning Interrupt is disabled again by writing a '1' to the Early Warning Interrupt bit in the Interrupt Enable Clear (INTENCLR.EW) register. If the Early Warning interrupt is enabled in Window mode, the interrupt is generated at the start of the open window period, i.e. after TOWDTW. The Window mode operation is illustrated in figure Window-Mode Operation. Figure 23-3. Window-Mode Operation 5 10 15 20 25 30 35 WDT Timeout Early Warning Interrupt Timely WDT Clear t[ms] TOWDT System Reset WDT Count PER[3:0] = 0 WINDOW[3:0] = 0 TOWDTW Early WDT Clear Closed Open

23.6.3 DMA Operation

Not applicable.

23.6.4 Interrupts

The WDT has the following interrupt source:

Early Warning (EW): Indicates that the counter is approaching the time-out condition. – This interrupt is an asynchronous wake-up source. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the WDT is reset. See the 23.8.6. INTFLAG register description for details on how to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. The user must read the INTFLAG register to determine which interrupt condition is present. Note: Interrupts must be globally enabled for interrupt requests to be generated. References: Sleep Mode Controller Interrupt Line Mapping PM - Power Manager

23.6.5 Events

Not applicable.

23.6.6 Sleep Mode Operation

The WDT will continue to operate in any sleep mode where the source clock is active except backup mode. The WDT interrupts can be used to wake up the device from a sleep mode. An interrupt request will be generated after the wake-up if the Interrupt Controller is configured accordingly. Otherwise the CPU will wake up directly, without triggering an interrupt. In this case, the CPU will continue executing from the instruction following the entry into sleep. References: SAM L22 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 276

23.6.7 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following registers are synchronized when written:

Enable bit in Control A register (CTRLA.ENABLE)
Window Enable bit in Control A register (CTRLA.WEN)
Always-On bit in control Control A (CTRLA.ALWAYSON) The following registers are synchronized when read:
Watchdog Clear register (CLEAR) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Required read-synchronization is denoted by the "Read-Synchronized" property in the register description.

23.6.8 Additional Features

23.6.8.1 Always-On Mode

The Always-On mode is enabled by setting the Always-On bit in the Control A register (CTRLA.ALWAYSON=1). When the Always-On mode is enabled, the WDT runs continuously, regardless of the state of CTRLA.ENABLE. Once written, the Always-On bit can only be cleared by a power-on reset. The Configuration (CONFIG) and Early Warning Control (EWCTRL) registers are read-only registers while the CTRLA.ALWAYSON bit is set. Thus, the time period configuration bits (CONFIG.PER, CONFIG.WINDOW, EWCTRL.EWOFFSET) of the WDT cannot be changed. Enabling or disabling Window mode operation by writing the Window Enable bit (CTRLA.WEN) is allowed while in Always-On mode, but note that CONFIG.PER cannot be changed. The Interrupt Clear and Interrupt Set registers are accessible in the Always-On mode. The Early Warning interrupt can still be enabled or disabled while in the Always-On mode, but note that EWCTRL.EWOFFSET cannot be changed. Table WDT Operating Modes With Always-On shows the operation of the WDT for CTRLA.ALWAYSON=1. Table 23-2. WDT Operating Modes With Always-On WEN Interrupt Enable Mode 0 0 Always-on and normal mode 0 1 Always-on and normal mode with Early Warning interrupt 1 0 Always-on and window mode 1 1 Always-on and window mode with Early Warning interrupt

23.6.8.2 Early Warning

The Early Warning interrupt notifies that the WDT is approaching its time-out condition. The Early Warning interrupt behaves differently in Normal mode and in Window mode. In Normal mode, the Early Warning interrupt generation is defined by the Early Warning Offset in the Early Warning Control register (EWCTRL.EWOFFSET). The Early Warning Offset bits define the number of CLK_WDT_OSC clocks before the interrupt is generated, relative to the start of the watchdog time-out period. The user must take caution when programming the Early Warning Offset bits. If these bits define an Early Warning interrupt generation time greater than the watchdog time-out period, the watchdog time-out system reset is generated prior to the Early Warning interrupt. Consequently, the Early Warning interrupt will never be generated. In window mode, the Early Warning interrupt is generated at the start of the open window period. In a typical application where the system is in sleep mode, the Early Warning interrupt can be used to wake up and clear the Watchdog Timer, after which the system can perform other tasks or return to sleep mode. SAM L22 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 277

If the WDT is operating in Normal mode with CONFIG.PER = 0x2 and EWCTRL.EWOFFSET = 0x1, the Early Warning interrupt is generated 16 CLK_WDT_OSC clock cycles after the start of the time-out period. The time-out system reset is generated 32 CLK_WDT_OSC clock cycles after the start of the watchdog time-out period. SAM L22 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 278

23.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 ALWAYSON WEN ENABLE 0x01 CONFIG 7:0 WINDOW[3:0] PER[3:0] 0x02 EWCTRL 7:0 EWOFFSET[3:0] 0x03 Reserved 0x04 INTENCLR 7:0 EW 0x05 INTENSET 7:0 EW 0x06 INTFLAG 7:0 EW 0x07 Reserved 0x08 SYNCBUSY 7:0 CLEAR ALWAYSON WEN ENABLE 15:8 23:16 31:24 0x0C CLEAR 7:0 CLEAR[7:0]

23.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write- protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 23.5.8. Register Access Protection. Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write- Synchronized" or the "Read-Synchronized" property in each individual register description. For details refer to 23.6.7. Synchronization. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. SAM L22 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 279

23.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: x initially determined from NVM User Row after reset Property: PAC Write-Protection, Write-Synchronized Bit 7 6 5 4 3 2 1 0 ALWAYSON WEN ENABLE Access R/W R/W R/W Reset x x x Bit 7 – ALWAYSON Always-On This bit allows the WDT to run continuously. After being set, this bit cannot be written to '0', and the WDT will remain enabled until a power-on Reset is received. When this bit is '1', the Control A register (CTRLA), the Configuration register (CONFIG) and the Early Warning Control register (EWCTRL) will be read-only, and any writes to these registers are not allowed. Writing a '0' to this bit has no effect. This bit is not Enable-Protected. This bit is loaded from NVM User Row at start-up. Refer to NVM User Row Mapping. Value Description 0 The WDT is enabled and disabled through the ENABLE bit. 1 The WDT is enabled and can only be disabled by a power-on reset (POR). Bit 2 – WEN Watchdog Timer Window Mode Enable This bit enables Window mode. It can only be written if the peripheral is disabled unless CTRLA.ALWAYSON = 1. The initial value of this bit is loaded from Flash Calibration. This bit is loaded from NVM User Row at startup. Refer to NVM User Row Mapping. Value Description 0 Window mode is disabled (normal operation). 1 Window mode is enabled. Bit 1 – ENABLE Enable This bit enables or disables the WDT. It can only be written if CTRLA.ALWAYSON = 0. Due to synchronization, there is delay between writing CTRLA.ENABLE until the peripheral is enabled or disabled. The value written to CTRLA.ENABLE will read back immediately, and the Enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not Enable-Protected. This bit is loaded from NVM User Row at startup. Refer to NVM User Row Mapping. Value Description 0 The WDT is disabled. 1 The WDT is enabled. SAM L22 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 280

23.8.2 Configuration

Name: CONFIG Offset: 0x01 Reset: x initially determined from NVM User Row after reset Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 WINDOW[3:0] PER[3:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Bits 7:4 – WINDOW[3:0] Window Mode Time-Out Period In Window mode, these bits determine the watchdog closed window period as a number of cycles of the 1.024 kHz CLK_WDT_OSC clock. These bits are loaded from NVM User Row at start-up. Refer to NVM User Row Mapping. Value Name Description 0x0 CYC8 8 clock cycles 0x1 CYC16 16 clock cycles 0x2 CYC32 32 clock cycles 0x3 CYC64 64 clock cycles 0x4 CYC128 128 clock cycles 0x5 CYC256 256 clock cycles 0x6 CYC512 512 clock cycles 0x7 CYC1024 1024 clock cycles 0x8 CYC2048 2048 clock cycles 0x9 CYC4096 4096 clock cycles 0xA CYC8192 8192 clock cycles 0xB CYC16384 16384 clock cycles 0xC - 0xF - Reserved Bits 3:0 – PER[3:0] Time-Out Period These bits determine the watchdog time-out period as a number of 1.024 kHz CLK_WDTOSC clock cycles. In Window mode operation, these bits define the open window period. These bits are loaded from NVM User Row at startup. Refer to NVM User Row Mapping. Value Name Description 0x0 CYC8 8 clock cycles 0x1 CYC16 16 clock cycles 0x2 CYC32 32 clock cycles 0x3 CYC64 64 clock cycles 0x4 CYC128 128 clock cycles 0x5 CYC256 256 clock cycles 0x6 CYC512 512 clock cycles 0x7 CYC1024 1024 clock cycles 0x8 CYC2048 2048 clock cycles 0x9 CYC4096 4096 clock cycles 0xA CYC8192 8192 clock cycles 0xB CYC16384 16384 clock cycles 0xC - 0xF - Reserved SAM L22 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 281

23.8.3 Early Warning Control

Name: EWCTRL Offset: 0x02 Reset: x initially determined from NVM User Row after reset Property: PAC Write-Protection The Register reset value is loaded from the NVM User Row at start-up. Bit 7 6 5 4 3 2 1 0 EWOFFSET[3:0] Access R/W R/W R/W R/W Reset x x x x Bits 3:0 – EWOFFSET[3:0] Early Warning Interrupt Time Offset These bits determine the number of GCLK_WDT clock cycles between the start of the watchdog time-out period and the generation of the Early Warning interrupt. These bits are loaded from NVM User Row at start-up. Refer to NVM User Row Mapping. Value Name Description 0x0 CYC8 8 clock cycles 0x1 CYC16 16 clock cycles 0x2 CYC32 32 clock cycles 0x3 CYC64 64 clock cycles 0x4 CYC128 128 clock cycles 0x5 CYC256 256 clock cycles 0x6 CYC512 512 clock cycles 0x7 CYC1024 1024 clock cycles 0x8 CYC2048 2048 clock cycles 0x9 CYC4096 4096 clock cycles 0xA CYC8192 8192 clock cycles 0xB CYC16384 16384 clock cycles 0xC - 0xF - Reserved SAM L22 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 282

23.8.4 Interrupt Enable Clear

Name: INTENCLR Offset: 0x04 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 7 6 5 4 3 2 1 0 EW Access R/W Reset 0 Bit 0 – EW Early Warning Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Early Warning Interrupt Enable bit, which disables the Early Warning interrupt. Value Description 0 The Early Warning interrupt is disabled. 1 The Early Warning interrupt is enabled. SAM L22 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 283

23.8.5 Interrupt Enable Set

Name: INTENSET Offset: 0x05 Reset: 0x00 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 7 6 5 4 3 2 1 0 EW Access R/W Reset 0 Bit 0 – EW Early Warning Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit sets the Early Warning Interrupt Enable bit, which enables the Early Warning interrupt. Value Description 0 The Early Warning interrupt is disabled. 1 The Early Warning interrupt is enabled. SAM L22 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 284

23.8.6 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x06 Reset: 0x00 Property: N/A Bit 7 6 5 4 3 2 1 0 EW Access R/W Reset 0 Bit 0 – EW Early Warning This flag is cleared by writing a '1' to it. This flag is set when an Early Warning interrupt occurs, as defined by the EWOFFSET bit group in EWCTRL. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Early Warning interrupt flag. SAM L22 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 285

23.8.7 Synchronization Busy

Name: SYNCBUSY Offset: 0x08 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CLEAR ALWAYSON WEN ENABLE Access R R R R Reset 0 0 0 0 Bit 4 – CLEAR Clear Synchronization Busy Value Description 0 Write synchronization of the CLEAR register is complete. 1 Write synchronization of the CLEAR register is ongoing. Bit 3 – ALWAYSON Always-On Synchronization Busy Value Description 0 Write synchronization of the CTRLA.ALWAYSON bit is complete. 1 Write synchronization of the CTRLA.ALWAYSON bit is ongoing. Bit 2 – WEN Window Enable Synchronization Busy Value Description 0 Write synchronization of the CTRLA.WEN bit is complete. 1 Write synchronization of the CTRLA.WEN bit is ongoing. Bit 1 – ENABLE Enable Synchronization Busy Value Description 0 Write synchronization of the CTRLA.ENABLE bit is complete. 1 Write synchronization of the CTRLA.ENABLE bit is ongoing. SAM L22 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 286

23.8.8 Clear

Name: CLEAR Offset: 0x0C Reset: 0x00 Property: Write-Synchronized Bit 7 6 5 4 3 2 1 0 CLEAR[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – CLEAR[7:0] Watchdog Clear In Normal mode, writing 0xA5 to this register during the watchdog time-out period will clear the Watchdog Timer and the watchdog time-out period is restarted. In Window mode, any writing attempt to this register before the time-out period started (i.e., during TOWDTW) will issue an immediate system Reset. Writing 0xA5 during the time-out period TOWDT will clear the Watchdog Timer and the complete time-out sequence (first TOWDTW then TOWDT) is restarted. In both modes, writing any other value than 0xA5 will issue an immediate system Reset. SAM L22 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 287

RTC – Real-Time Counter

24.1 Overview

The Real-Time Counter (RTC) is a 32-bit counter with a 10-bit programmable prescaler that typically runs continuously to keep track of time. The RTC can wake up the device from sleep modes using the alarm/compare wake up, periodic wake up, or overflow wake up mechanisms, or from the wake up inputs. The RTC can generate periodic peripheral events from outputs of the prescaler, as well as alarm/compare interrupts and peripheral events, which can trigger at any counter value. Additionally, the timer can trigger an overflow interrupt and peripheral event, and can be reset on the occurrence of an alarm/compare match. This allows periodic interrupts and peripheral events at very long and accurate intervals. The 10-bit programmable prescaler can scale down the clock source. By this, a wide range of resolutions and time-out periods can be configured. With a 32.768 kHz clock source, the minimum counter tick interval is 30.5 µs, and time-out periods can range up to 36 hours. For a counter tick interval of 1s, the maximum time-out period is more than 136 years.

24.2 Features

The following are key features of the RTC module:

32-bit counter with 10-bit prescaler
Multiple clock sources
32-bit or 16-bit counter mode
One 32-bit or two 16-bit compare values
Clock/Calendar mode – Time in seconds, minutes, and hours (12/24) – Date in day of month, month, and year – Leap year correction
Digital prescaler correction/tuning for increased accuracy
Overflow, alarm/compare match and prescaler interrupts and events – Optional clear on alarm/compare match
8 backup registers with retention capability
Tamper Detection – Timestamp on event or up to 5 inputs with debouncing – Active layer protection

24.3 Block Diagram

Figure 24-1. RTC Block Diagram (Mode 0 — 32-Bit Counter) OVF MATCHCLR CMPn OSC32KCTRL CLK_RTC_OSC PRESCALER CLK_RTC_CNT Periodic Events COUNT COMPn 0x00000000 SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 288

Figure 24-2. RTC Block Diagram (Mode 1 — 16-Bit Counter) CLK_RTC_OSC CLK_RTC_CNT OSC32KCTRL PRESCALER COMPn PER COUNT 0x0000 Periodic Events = CMPn OVF Figure 24-3. RTC Block Diagram (Mode 2 — Clock/Calendar) CLK_RTC_CNTCLK_RTC_OSC OSC32KCTRL PRESCALER Periodic Events MASKn CLOCK ALARMn 0x00000000 OVF MATCHCLR ALARMn Figure 24-4. RTC Block Diagram (Tamper Detection) PRESCALER DEBOUNCE DEBOUNCE DEBOUNCE TIMESTAMP CAPTURE INn IN1 IN0 OUT Tamper Input [0..n] PCB Active Layer Protection TAMPEVT TAMPER ALARM FREQCORR CLOCK

24.4 Signal Description

Table 24-1. Signal Description Signal Description Type INn [n=0..4] Tamper / Wake / Active layer input Digital input OUT Active layer protection output Digital output SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 289

One signal can be mapped to one of several pins.

24.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

24.5.1 I/O Lines

Not applicable.

24.5.2 Power Management

The RTC will continue to operate in any sleep mode where the selected source clock is running. The RTC interrupts can be used to wake up the device from sleep modes. Events connected to the event system can trigger other operations in the system without exiting sleep modes. Refer to the Power Manager for details on the different sleep modes. The RTC will be reset only at power-on (POR) or by setting the Software Reset bit in the Control A register (CTRLA.SWRST=1). References: PM - Power Manager

24.5.3 Clocks

The RTC bus clock (CLK_RTC_APB) can be enabled and disabled in the Main Clock module MCLK, and the default state of CLK_RTC_APB can be found in Peripheral Clock Masking section. A 32KHz or 1KHz oscillator clock (CLK_RTC_OSC) is required to clock the RTC. This clock must be configured and enabled in the 32KHz oscillator controller (OSC32KCTRL) before using the RTC. This oscillator clock is asynchronous to the bus clock (CLK_RTC_APB). Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains. Refer to Synchronization for further details. References: Peripheral Clock Masking OSC32KCTRL

24.5.4 DMA

The DMA request lines (or line if only one request) are connected to the DMA Controller (DMAC). Using the RTC DMA requests requires the DMA Controller to be configured first. References: DMAC - Direct Memory Access Controller

24.5.5 Interrupts

The interrupt request line is connected to the Interrupt Controller. Using the RTC interrupt requires the Interrupt Controller to be configured first. References: Nested Vector Interrupt Controller

24.5.6 Events

The events are connected to the Event System. References: EVSYS - Event System SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 290

24.5.7 Debug Operation

When the CPU is halted in debug mode the RTC will halt normal operation. The RTC can be forced to continue

24.5.8 Register Access Protection

All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the following registers:

Interrupt Flag Status and Clear (INTFLAG) register
General Purpose (GPx) registers Write-protection is denoted by the "PAC Write-Protection" property in the register description. Write-protection does not apply to accesses through an external debugger. Refer to the PAC - Peripheral Access Controller for details.

24.5.9 Analog Connections

A 32.768kHz crystal can be connected to the XIN32 and XOUT32 pins, along with any required load capacitors. See Electrical Characteristics for details on recommended crystal characteristics and load capacitors. References:

24.6 Functional Description

24.6.1 Principle of Operation

The RTC keeps track of time in the system and enables periodic events, as well as interrupts and events at a specified time. The RTC consists of a 10-bit prescaler that feeds a 32-bit counter. The actual format of the 32-bit counter depends on the RTC operating mode. The RTC can function in one of these modes:

Mode 0 - COUNT32: RTC serves as 32-bit counter
Mode 1 - COUNT16: RTC serves as 16-bit counter
Mode 2 - CLOCK: RTC serves as clock/calendar with alarm functionality

24.6.2 Basic Operation

24.6.2.1 Initialization

The following bits are enable-protected, meaning that they can only be written when the RTC is disabled (CTRLA.ENABLE=0):

Operating Mode bits in the Control A register (CTRLA.MODE)
Prescaler bits in the Control A register (CTRLA.PRESCALER)
Clear on Match bit in the Control A register (CTRLA.MATCHCLR)
Clock Representation bit in the Control A register (CTRLA.CLKREP) The following registers are enable-protected:
Event Control register (EVCTRL)
Tamper Control register (TAMPCTRL)
Control B register (CTRLB) Enable-protected bits and registers can be changed only when the RTC is disabled (CTRLA.ENABLE=0). If the RTC is enabled (CTRLA.ENABLE=1), these operations are necessary: first write CTRLA.ENABLE=0 and check whether the write synchronization has finished, then change the desired bit field value. Enable-protected bits in can be written at the same time as CTRLA.ENABLE is written to '1', but not at the same time as CTRLA.ENABLE is written to '0'. Enable-protection is denoted by the "Enable-Protected" property in the register description. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 291

The RTC prescaler divides the source clock for the RTC counter. Note: In Clock/Calendar mode, the prescaler must be configured to provide a 1Hz clock to the counter for correct operation. The frequency of the RTC clock (CLK_RTC_CNT) is given by the following formula: f CLK_RTC_CNT = f CLK_RTC_OSC 2PRESCALER The frequency of the oscillator clock, CLK_RTC_OSC, is given by fCLK_RTC_OSC, and fCLK_RTC_CNT is the frequency of the internal prescaled RTC clock, CLK_RTC_CNT.

24.6.2.2 Enabling, Disabling, and Resetting

The RTC is enabled by setting the Enable bit in the Control A register (CTRLA.ENABLE=1). The RTC is disabled by writing CTRLA.ENABLE=0. The RTC is reset by setting the Software Reset bit in the Control A register (CTRLA.SWRST=1). All registers in the RTC, except DEBUG, will be reset to their initial state, and the RTC will be disabled. The RTC must be disabled before resetting it. 24.6.2.3 32-Bit Counter (Mode 0) When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x0, the counter operates in 32-bit Counter mode. The block diagram of this mode is shown in RTC Block Diagram (Mode 0 - 32-Bit Counter). When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The counter will increment until it reaches the top value of 0xFFFFFFFF, and then wrap to 0x00000000. This sets the Overflow Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF). The RTC counter value can be read from or written to the Counter Value register (COUNT) in 32-bit format. The counter value is continuously compared with the 32-bit Compare register (COMP). When a compare match occurs, the Compare0 Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMP0) is set on the next 0-to-1 transition of CLK_RTC_CNT. If the Clear on Match bit in the Control A register (CTRLA.MATCHCLR) is '1', the counter is cleared on the next counter cycle when a compare match with COMP occurs. This allows the RTC to generate periodic interrupts or events with longer periods than the prescaler events. Note that when CTRLA.MATCHCLR is '1', INTFLAG.CMP0 and INTFLAG.OVF will both be set simultaneously on a compare match with COMP. 24.6.2.4 16-Bit Counter (Mode 1) When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x1, the counter operates in 16-bit Counter mode as shown in RTC Block Diagram (Mode 1 - 16-Bit Counter). When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. In 16-bit Counter mode, the 16-bit Period register (PER) holds the maximum value of the counter. The counter will increment until it reaches the PER value, and then wrap to 0x0000. This sets the Overflow Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF). The RTC counter value can be read from or written to the Counter Value register (COUNT) in 16-bit format. The counter value is continuously compared with the 16-bit Compare registers (COMPn, n=0..1). When a compare match occurs, the Compare n Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn, n=0..1) is set on the next 0-to-1 transition of CLK_RTC_CNT.

24.6.2.5 Clock/Calendar (Mode 2)

When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x2, the counter operates in Clock/Calendar mode, as shown in RTC Block Diagram (Mode 2 - Clock/Calendar). When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The selected clock source and RTC prescaler must be configured to provide a 1Hz clock to the counter for correct operation in this mode. The time and date can be read from or written to the Clock Value register (CLOCK) in a 32-bit time/date format. Time is represented as:

Seconds
Minutes
Hours SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 292

Hours can be represented in either 12- or 24-hour format, selected by the Clock Representation bit in the Control A register (CTRLA.CLKREP). This bit can be changed only while the RTC is disabled. The date is represented in this form:

Day as the numeric day of the month (starting at 1)
Month as the numeric month of the year (1 = January, 2 = February, etc.)
Year as a value from 0x00 to 0x3F. This value must be added to a user-defined reference year. The reference year must be a leap year (2016, 2020 etc). Example: the year value 0x2D, added to a reference year 2016, represents the year 2061. The RTC will increment until it reaches the top value of 23:59:59 December 31 of year value 0x3F, and then wrap to 00:00:00 January 1 of year value 0x00. This will set the Overflow Interrupt flag in the Interrupt Flag Status and Clear registers (INTFLAG.OVF). The clock value is continuously compared with the 32-bit Alarm register (ALARM). When an alarm match occurs, the Alarm 0 Interrupt flag in the Interrupt Flag Status and Clear registers (INTFLAG.ALARM0) is set on the next 0-to-1 transition of CLK_RTC_CNT. E.g. For a 1Hz clock counter, it means the Alarm 0 Interrupt flag is set with a delay of 1s after the occurrence of alarm match. A valid alarm match depends on the setting of the Alarm Mask Selection bits in the Alarm Mask register (MASK.SEL). These bits determine which time/date fields of the clock and alarm values are valid for comparison and which are ignored. If the Clear on Match bit in the Control A register (CTRLA.MATCHCLR) is set, the counter is cleared on the next counter cycle when an alarm match with ALARM 0 occurs. This allows the RTC to generate periodic interrupts or Note: When CTRLA.MATCHCLR is 1, INTFLAG.ALARM0 and INTFLAG.OVF will both be set simultaneously on an alarm match with ALARM0.

24.6.3 DMA Operation

The RTC generates the following DMA request:

Tamper (TAMPER): The request is set on capture of the timestamp. The request is cleared when the Timestamp register is read. If the CPU accesses the registers which are the source for the DMA request set/clear condition, the DMA request can be lost or the DMA transfer can be corrupted, if enabled.

24.6.4 Interrupts

The RTC has the following interrupt sources:

Overflow (OVF): Indicates that the counter has reached its top value and wrapped to zero.
Compare (CMPn): Indicates a match between the counter value and the compare register.
Alarm (ALARM0): Indicates a match between the clock value and the alarm register.
Period n (PERn): The corresponding bit in the prescaler has toggled. Refer to Periodic Intervals for details.
Tamper (TAMPER): Indicates detection of a valid signal on a tamper input pin, or tamper event input. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by setting the corresponding bit in the Interrupt Enable Set register (INTENSET = 1), and disabled by setting the corresponding bit in the Interrupt Enable Clear register (INTENCLR = 1). An interrupt request is generated when the interrupt flag is raised and the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled or the RTC is reset. See the description of the INTFLAG registers for details on how to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. Refer to the Nested Vector Interrupt Controller for additional information. The user must read the INTFLAG register to determine which interrupt condition is present. Note: Interrupts must be globally enabled for interrupt requests to be generated. Refer to the Nested Vector Interrupt Controller for details. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 293

24.6.5 Events

The RTC can generate the following output events:

Overflow (OVF): Generated when the counter has reached its top value and wrapped to zero.
Compare (CMPn): Indicates a match between the counter value and the compare register.
Alarm (ALARM0): Indicates a match between the clock value and the alarm register.
Period n (PERn): The corresponding bit in the prescaler has toggled. Refer to Periodic Intervals for details.
Tamper (TAMPER): Generated on detection of a valid signal on a tamper input pin, or tamper event input. Setting the Event Output bit in the Event Control Register (EVCTRL.xxxEO = 1) enables the corresponding output event. Writing a zero to this bit disables the corresponding output event. Refer to the EVSYS - Event System for details on configuring the event system. The RTC can take the following actions on an input event: Writing a one to an Event Input bit into the Event Control register (EVCTRL.xxxEI) enables the corresponding action on input event. Writing a zero to this bit disables the corresponding action on input event. References: 29. EVSYS – Event System

24.6.6 Sleep Mode Operation

The RTC will continue to operate in any sleep mode where the source clock is active. The RTC interrupts can be used to wake up the device from a sleep mode. RTC events can trigger other operations in the system without exiting the sleep mode. An interrupt request will be generated after the wake-up if the Interrupt Controller is configured accordingly. Otherwise the CPU will wake up, without triggering any interrupt. In this case, the CPU will continue executing right from the first instruction that followed the entry into sleep. The periodic events also may wake-up the CPU through the interrupt function of the Event System. In this case, the event must be enabled and connected to an event channel with its interrupt enabled. Refer to the EVSYS - Event System for more information

24.6.7 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written:

Software Reset bit in Control A register, CTRLA.SWRST
Enable bit in Control A register, CTRLA.ENABLE
Count Read Synchronization bit in Control A register (CTRLA.COUNTSYNC) The following registers are synchronized when written:
Counter Value register, COUNT
Clock Value register, CLOCK
Counter Period register, PER
Compare n Value registers, COMPn
Alarm 0 Value register, ALARM
Frequency Correction register, FREQCORR
Alarm 0 Mask register, MASK
The General Purpose n registers (GPn) The following registers are synchronized when read:
The Counter Value register, COUNT, if the Counter Read Sync Enable bit in CTRLA (CTRLA.COUNTSYNC) is '1'
The Clock Value register, CLOCK, if the Clock Read Sync Enable bit in CTRLA (CTRLA.CLOCKSYNC) is '1' SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 294

The Timestamp Value register (TIMESTAMP) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Required read-synchronization is denoted by the "Read-Synchronized" property in the register description. References: 14.3. Register Synchronization

24.6.8 Additional Features

24.6.8.1 Periodic Intervals

The RTC prescaler can generate interrupts and events at periodic intervals, allowing flexible system tick creation. Any of the upper eight bits of the prescaler (bits 2 to 9) can be the source of an interrupt/event. When one of the eight Periodic Event Output bits in the Event Control register (EVCTRL.PEREO[n=0..7]) is '1', an event is generated on the 0-to-1 transition of the related bit in the prescaler, resulting in a periodic event frequency of: f PERIODIC(n) = f CLK_RTC_OSC 2n+3 fCLK_RTC_OSC is the frequency of the internal prescaler clock CLK_RTC_OSC, and n is the position of the EVCTRL.PEREOn bit. For example, PER0 will generate an event every eight CLK_RTC_OSC cycles, PER1 every 16 cycles, etc. This is shown in the figure below. Periodic events are independent of the prescaler setting used by the RTC counter, except if CTRLA.PRESCALER is zero. Then, no periodic events will be generated. Figure 24-5. Example Periodic Events CLK_RTC_OSC PER0 PER1 PER2 PER3

24.6.8.2 Frequency Correction

The RTC Frequency Correction module employs periodic counter corrections to compensate for a too-slow or too-fast oscillator. Frequency correction requires that CTRLA.PRESCALER is greater than 1. The digital correction circuit adds or subtracts cycles from the RTC prescaler to adjust the frequency in approximately 1ppm steps. Digital correction is achieved by adding or skipping a single count in the prescaler once every 8192 CLK_RTC_OSC cycles. The Value bit group in the Frequency Correction register (FREQCORR.VALUE) determines the number of times the adjustment is applied over 128 of these periods. The resulting correction is as follows: Correction in ppm = FREQCORR.VALUE 8192 ⋅ 128 ⋅ 106ppm This results in a resolution of 0.95367 ppm. The Sign bit in the Frequency Correction register (FREQCORR.SIGN) determines the direction of the correction. A positive value will add counts and increase the period (reducing the frequency), and a negative value will reduce counts per period (speeding up the frequency). Digital correction also affects the generation of the periodic events from the prescaler. When the correction is applied at the end of the correction cycle period, the interval between the previous periodic event and the next occurrence may also be shortened or lengthened depending on the correction value.

24.6.8.3 Backup Registers

The RTC includes eight Backup registers (BKUPn). These registers maintain their content in Backup sleep mode. They can be used to store user-defined values. If more user-defined data must be stored than the eight Backup registers can hold, the General Purpose registers (GPn) can be used. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 295

24.6.8.4 General Purpose Registers

The RTC includes two General Purpose registers (GPn). These registers are reset only when the RTC is reset or when tamper detection occurs while CTRLA.GPTRST=1, and remain powered while the RTC is powered. They can be used to store user-defined values while other parts of the system are powered off. It is recommended to use the eight Backup registers (BKUPn) first to store user-defined values, and use the GPn only when the user-defined values exceed the capacity of the provided BKUPn. An example procedure to write the general purpose registers GP0 and GP1 is: 1. Wait for any ongoing write to COMP0 to complete (SYNCBUSY.COMP0 = 0). If the RTC is operating in Mode 1, wait for any ongoing write to COMP1 to complete as well (SYNCBUSY.COMP1 = 0). 2. Write CTRLB.GP0EN = 1 if GP0 is needed. 3. Write GP0 if needed. 4. Wait for any ongoing write to GP0 to complete (SYNCBUSY.GP0 = 0). Note that GP1 will also show as busy when GP0 is busy. 5. Write GP1 if needed. Table 24-2. General Purpose Registers vs Compare/Alarm Registers Register Mode 0 Mode 1 Mode 2 Write Before GP0 COMP0 COMP0 / COMP1 ALARM0 GP1 GP1 COMP0 COMP0 / COMP1 ALARM0 - The GPn registers share internal resources with the compare/alarm features. Each pair of 32-bit GPn are associated with one 32-bit compare/alarm or a pair of 16-bit compare registers as shown in the table above. Before using an even GPn, the associated compare/alarm feature must be disabled by writing a '1' to the General Purpose Enable bit in the Control B register (CTRLB.GPnEN). To re-enable the compare/alarm, CTRLB.GPnEN must be written to zero and the associated COMPn/ALARM0 must be written with the correct value. Each even GPn must also be written prior to writing the odd GPn if both will be used. Odd GPn can be used without affecting the compare/alarm functions; however, any writes to the associated COMPn/ALARM0 register must be completed before writing the odd GPn.

24.6.8.5 Tamper Detection

The RTC provides up to five selectable polarity external inputs (INn) that can be used for tamper detection. The RTC also supports an input event (TAMPEVT) for generating a tamper condition from within the Event System. A single interrupt request (TAMPER) is available for all tamper sources. The polarity for each input is selected with the Tamper Level bits in the Tamper Control register (TAMPCTRL.TAMPLVLn). The tamper input event is enabled by the Tamper Input Event Enable in the Event Control register (EVCTRL.TAMPEVIE). The action of each input pin is configured using the Input n Action bits in the Tamper Control register (TAMPCTRL.INnACT). Tamper inputs support the following actions:

Off: Detection for INn is disabled.
Wake: A transition on INn matching TAMPCTRL.TAMPLVLn will be detected and the tamper interrupt flag (INTFLAG.TAMPER) will be set. The RTC value will not be captured in the TIMESTAMP register
Capture: A transition on INn matching TAMPCTRL.TAMPLVLn will be detected and the tamper interrupt flag (INTFLAG.TAMPER) will be set. The RTC value will be captured in the TIMESTAMP register.
Active Layer Protection: A mismatch between INn and OUT will be detected and the tamper interrupt flag (INTFLAG.TAMPER) will be set. The RTC value will be captured in the TIMESTAMP register. In order to determine which tamper source caused a tamper event, the Tamper ID register (TAMPID) provides the detection status of each input pin and the input event. These bits remain active until cleared by software. Separate debouncers are embedded for each external input. The debouncer for each input is enabled/disabled with the Debounce Enable bits in the Tamper Control register (TAMPCTRL.DEBNCn). The debouncer configuration is fixed for all inputs as set by the Control B register (CTRLB). The debouncing period duration is configurable using the Debounce Frequency field in the Control B register (CTRLB.DEBF). The period is set for all debouncers (i.e., the duration cannot be adjusted separately for each debouncer). When TAMPCTRL.DEBNCn = 0, INn is detected asynchronously. See Figure 24-6 for an example. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 296

When TAMPCTRL.DEBNCn = 1, the detection time depends on whether the debouncer operates synchronously or asynchronously, and whether majority detection is enabled or not. Refer to the table below for more details. Synchronous versus asynchronous stability debouncing is configured by the Debounce Asynchronous Enable bit in the Control B register (CTRLB.DEBASYNC):

Synchronous (CTRLB.DEBASYNC = 0): INn is synchronized in two CLK_RTC periods and then must remain stable for four CLK_RTC_DEB periods before a valid detection occurs. See Figure 24-7 for an example.
Asynchronous (CTRLB.DEBASYNC = 1): The first edge on INn is detected. Further detection is blanked until INn remains stable for four CLK_RTC_DEB periods. See Figure 24-8 for an example. Majority debouncing is configured by the Debounce Majority Enable bit in the Control B register (CTRLB.DEBMAJ). INn must be valid for two out of three CLK_RTC_DEB periods. See Figure 24-9 for an example. Table 24-3. Debouncer Configuration TAMPCTRL. DEBNCn CTRLB. DEBMAJ CTRLB. DEBASYNC

Description

0 X X Detect edge on INn with no debouncing. Every edge detected is immediately triggered. 1 0 0 Detect edge on INn with synchronous stability debouncing. Edge detected is only triggered when INn is stable for 4 consecutive CLK_RTC_DEB periods. 1 0 1 Detect edge on INn with asynchronous stability debouncing. First detected edge is triggered immediately. All subsequent detected edges are ignored until INn is stable for 4 consecutive CLK_RTC_DEB periods. 1 1 X Detect edge on INn with majority debouncing. Pin INn is sampled for 3 consecutive CLK_RTC_DEB periods. Signal level is determined by majority-rule (LLL, LLH, LHL, HLL = '0' and LHH, HLH, HHL, HHH = '1'). Figure 24-6. Edge Detection with Debouncer Disabled CLK_RTC CLK_RTC_DEB IN OUT NENE PE TAMLVL=0 CLK_RTC CLK_RTC_DEB IN OUT NENE PE TAMLVL=1 PE NE PE PE NE PE SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 297

Figure 24-9. Edge Detection with Majority Debouncing CLK_RTC CLK_RTC_DEB IN IN shift 0 IN shift 1 IN shift 2 MAJORITY3 OUT CLK_RTC CLK_RTC_DEB IN IN shift 0 IN shift 1 IN shift 2 MAJORITY3 OUT 1 1 1 0 0 0 TAMLVL=1 TAMLVL=0 0-to-1 transition 1-to-0 transition NENE PE PENE PE 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 NENE PE PENE PE 0 0 0 1 1 1 1 1 1

24.6.8.6 Active Layer Protection

The RTC provides a means of detecting broken traces on the PCB, also known as Active Layer Protection. In this mode an RTC output signal is routed over critical components on the board and fed back to one of the RTC inputs. The input and output signals are compared and a tamper condition is detected when they do not match. Enabling active layer protection requires the following steps:

Enable the RTC prescaler output by writing a one to the RTC Out bit in the Control B register (CTRLB.RTCOUT). The I/O pins must also be configured to correctly route the signal to the external pins.
Select the frequency of the output signal by configuring the RTC Active Layer Frequency field in the Control B register (CTRLB.ACTF). GCLK_RTC_OUT = CLK_RTC 2CTRLB.ACTF +1
Enable one of the tamper inputs (INn) in active layer mode by writing 3 to the corresponding Input Action field in the Tamper Control register (TAMPCTRL.INnACT). When active layer protection is enabled, the value of INn is sampled on the falling edge of CLK_RTC and compared to the expected value of OUT. Therefore up to one half of a CLK_RTC period is available for propagation delay through the trace. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 299

24.7 Register Summary - COUNT32

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 MATCHCLR MODE[1:0] ENABLE SWRST 15:8 COUNTSYNC GPTRST BKTRST PRESCALER[3:0] 0x02 CTRLB 7:0 DMAEN RTCOUT DEBASYNC DEBMAJ GP0EN 15:8 ACTF[2:0] DEBF[2:0] 0x04 EVCTRL 7:0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 15:8 OVFEO TAMPEREO CMPEO0 23:16 TAMPEVEI 31:24 0x08 INTENCLR 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF TAMPER CMP0 0x0A INTENSET 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF TAMPER CMP0 0x0C INTFLAG 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF TAMPER CMP0 0x0E DBGCTRL 7:0 DBGRUN 0x0F Reserved 0x10 SYNCBUSY 7:0 COMP0 COUNT FREQCORR ENABLE SWRST 15:8 COUNTSYNC 23:16 GP1 GP0 31:24 0x14 FREQCORR 7:0 SIGN VALUE[6:0] 0x15 ... 0x17 Reserved 0x18 COUNT 7:0 COUNT[7:0] 15:8 COUNT[15:8] 23:16 COUNT[23:16] 31:24 COUNT[31:24] 0x1C ... 0x1F Reserved 0x20 COMP0 7:0 COMP[7:0] 15:8 COMP[15:8] 23:16 COMP[23:16] 31:24 COMP[31:24] 0x24 ... 0x3F Reserved 0x40 GP0 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 0x44 GP1 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 0x48 ... 0x5F Reserved 0x60 TAMPCTRL 7:0 IN3ACT[1:0] IN2ACT[1:0] IN1ACT[1:0] IN0ACT[1:0] 15:8 IN4ACT[1:0] 23:16 TAMLVL4 TAMLVL3 TAMLVL2 TAMLVL1 TAMLVL0 31:24 DEBNC4 DEBNC3 DEBNC2 DEBNC1 DEBNC0 SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 300

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x64 TIMESTAMP 7:0 COUNT[7:0] 15:8 COUNT[15:8] 23:16 COUNT[23:16] 31:24 COUNT[31:24] 0x68 TAMPID 7:0 TAMPID4 TAMPID3 TAMPID2 TAMPID1 TAMPID0 15:8 23:16 31:24 TAMPEVT 0x6C ... 0x7F Reserved 0x80 BKUP0 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x84 BKUP1 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x88 BKUP2 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x8C BKUP3 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x90 BKUP4 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x94 BKUP5 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x98 BKUP6 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x9C BKUP7 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24]

24.8 Register Description - COUNT32

This Register Description section is valid if the RTC is in COUNT32 mode (CTRLA.MODE=0). Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read- Synchronized" and/or "Write-Synchronized" property in each individual register description. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 301

24.8.1 Control A in COUNT32 mode (CTRLA.MODE=0) Name: CTRLA Offset: 0x00 Reset: 0x0000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 COUNTSYNC GPTRST BKTRST PRESCALER[3:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MATCHCLR MODE[1:0] ENABLE SWRST Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 15 – COUNTSYNC COUNT Read Synchronization Enable The COUNT register requires synchronization when reading. Disabling the synchronization will prevent reading valid values from the COUNT register. This bit is not enable-protected. Value Description

0 COUNT read synchronization is disabled

1 COUNT read synchronization is enabled

Bit 14 – GPTRST GP Registers Reset On Tamper Enable Only GP registers enabled by the CTRLB.GPnEN bits are affected. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Bit 13 – BKTRST GP Registers Reset On Tamper Enable All BKUPn registers are affected. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Value Description 0 BKUPn registers will not reset when a tamper condition occurs. 1 BKUPn registers will reset when a tamper condition occurs. Bits 11:8 – PRESCALER[3:0] Prescaler These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not synchronized. Value Name Description 0x0 OFF CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x2 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x3 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x4 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x5 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x6 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x7 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x8 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x9 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0xA DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xB DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xC-0xF - Reserved SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 302

Bit 7 – MATCHCLR Clear on Match This bit defines if the counter is cleared or not on a match. This bit is not synchronized. Value Description

0 The counter is not cleared on a Compare/Alarm 0 match

1 The counter is cleared on a Compare/Alarm 0 match

Bits 3:2 – MODE[1:0] Operating Mode This bit group defines the operating mode of the RTC. This bit is not synchronized. Value Name Description 0x0 COUNT32 Mode 0: 32-bit counter 0x1 COUNT16 Mode 1: 16-bit counter 0x2 CLOCK Mode 2: Clock/calendar 0x3 - Reserved Bit 1 – ENABLE Enable Due to synchronization there is a delay between writing CTRLA.ENABLE and until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. Value Description

0 The peripheral is disabled

1 The peripheral is enabled

Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the RTC (except DBGCTRL) to their initial state, and the RTC will be disabled. Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization there is a delay between writing CTRLA.SWRST and until the reset is complete. CTRLA.SWRST will be cleared when the reset is complete. Value Description

0 There is not reset operation ongoing

1 The reset operation is ongoing

24.8.2 Control B in COUNT32 mode (CTRLA.MODE=0) Name: CTRLB Offset: 0x02 Reset: 0x0000 Property: PAC Write-Protection, Enable-Protected Bit 15 14 13 12 11 10 9 8 ACTF[2:0] DEBF[2:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DMAEN RTCOUT DEBASYNC DEBMAJ GP0EN Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bits 14:12 – ACTF[2:0] Active Layer Frequency These bits define the prescaling factor for the RTC clock output (OUT) used during active layer protection in terms of the CLK_RTC. Value Name Description 0x0 DIV2 CLK_RTC_OUT = CLK_RTC / 2 0x1 DIV4 CLK_RTC_OUT = CLK_RTC / 4 0x2 DIV8 CLK_RTC_OUT = CLK_RTC / 8 0x3 DIV16 CLK_RTC_OUT = CLK_RTC / 16 0x4 DIV32 CLK_RTC_OUT = CLK_RTC / 32 0x5 DIV64 CLK_RTC_OUT = CLK_RTC / 64 0x6 DIV128 CLK_RTC_OUT = CLK_RTC / 128 0x7 DIV256 CLK_RTC_OUT = CLK_RTC / 256 Bits 10:8 – DEBF[2:0] Debounce Frequency These bits define the prescaling factor for the input debouncers in terms of the CLK_RTC. Value Name Description 0x0 DIV2 CLK_RTC_DEB = CLK_RTC / 2 0x1 DIV4 CLK_RTC_DEB = CLK_RTC / 4 0x2 DIV8 CLK_RTC_DEB = CLK_RTC / 8 0x3 DIV16 CLK_RTC_DEB = CLK_RTC / 16 0x4 DIV32 CLK_RTC_DEB = CLK_RTC / 32 0x5 DIV64 CLK_RTC_DEB = CLK_RTC / 64 0x6 DIV128 CLK_RTC_DEB = CLK_RTC / 128 0x7 DIV256 CLK_RTC_DEB = CLK_RTC / 256 Bit 7 – DMAEN DMA Enable The RTC can trigger a DMA request when the timestamp is ready in the TIMESTAMP register. Value Description 0 Tamper DMA request is disabled. Reading TIMESTAMP has no effect on INTFLAG.TAMPER. 1 Tamper DMA request is enabled. Reading TIMESTAMP will clear INTFLAG.TAMPER. Bit 6 – RTCOUT RTC Output Enable Value Description 0 The RTC active layer output is disabled. 1 The RTC active layer output is enabled. Bit 5 – DEBASYNC Debouncer Asynchronous Enable SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 304

0 The tamper input debouncers operate synchronously. 1 The tamper input debouncers operate asynchronously. Bit 4 – DEBMAJ Debouncer Majority Enable Value Description 0 The tamper input debouncers match three equal values. 1 The tamper input debouncers match majority two of three values. Bit 0 – GP0EN General Purpose 0 Enable Value Description 0 COMP0 compare function enabled. GP0/GP1 disabled. 1 COMP0 compare function disabled. GP0/GP1 enabled. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 305

24.8.3 Event Control in COUNT32 mode (CTRLA.MODE=0) Name: EVCTRL Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 TAMPEVEI Access R/W Reset 0 Bit 15 14 13 12 11 10 9 8 OVFEO TAMPEREO CMPEO0 Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 16 – TAMPEVEI Tamper Event Input Enable Value Description 0 Tamper event input is disabled and incoming events will be ignored. 1 Tamper event input is enabled and incoming events will capture the COUNT value. Bit 15 – OVFEO Overflow Event Output Enable Value Description 0 Overflow event is disabled and will not be generated. 1 Overflow event is enabled and will be generated for every overflow. Bit 14 – TAMPEREO Tamper Event Output Enable Value Description 0 Tamper event output is disabled and will not be generated. 1 Tamper event output is enabled and will be generated for every tamper input. Bit 8 – CMPEO0 Compare 0 Event Output Enable Value Description 0 Compare 0 event is disabled and will not be generated. 1 Compare 0 event is enabled and will be generated for every compare match. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PEREOn Periodic Interval n Event Output Enable [n = 0..7] Value Description 0 Periodic Interval n event is disabled and will not be generated. 1 Periodic Interval n event is enabled and will be generated. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 306

24.8.4 Interrupt Enable Clear in COUNT32 mode (CTRLA.MODE=0) Name: INTENCLR Offset: 0x08 Reset: 0x0000 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 15 14 13 12 11 10 9 8 OVF TAMPER CMP0 Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. Bit 14 – TAMPER Tamper Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this but will clear the Tamper Interrupt Enable bit, which disables the Tamper interrupt. Value Description 0 The Tamper interrupt is disabled. 1 The Tamper interrupt is enabled. Bit 8 – CMP0 Compare 0 Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Compare 0 Interrupt Enable bit, which disables the Compare 0 interrupt. Value Description 0 The Compare 0 interrupt is disabled. 1 The Compare 0 interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 0..7] Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Periodic Interval n Interrupt Enable bit, which disables the Periodic Interval n interrupt. Value Description 0 Periodic Interval n interrupt is disabled. 1 Periodic Interval n interrupt is enabled. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 307

24.8.5 Interrupt Enable Set in COUNT32 mode (CTRLA.MODE=0) Name: INTENSET Offset: 0x0A Reset: 0x0000 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 15 14 13 12 11 10 9 8 OVF TAMPER CMP0 Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. Bit 14 – TAMPER Tamper Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Tamper Interrupt Enable bit, which enables the Tamper interrupt. Value Description 0 The Tamper interrupt is disabled. 1 The Tamper interrupt is enabled. Bit 8 – CMP0 Compare 0 Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Compare 0 Interrupt Enable bit, which enables the Compare 0 interrupt. Value Description 0 The Compare 0 interrupt is disabled. 1 The Compare 0 interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 0..7] Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Periodic Interval n Interrupt Enable bit, which enables the Periodic Interval n interrupt. Value Description 0 Periodic Interval n interrupt is disabled. 1 Periodic Interval n interrupt is enabled. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 308

24.8.6 Interrupt Flag Status and Clear in COUNT32 mode (CTRLA.MODE=0) Name: INTFLAG Offset: 0x0C Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 OVF TAMPER CMP0 Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Overflow interrupt flag. Bit 14 – TAMPER Tamper event This flag is set after a damper condition occurs, and an interrupt request will be generated if INTENCLR.TAMPER/ INTENSET.TAMPER is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Tamper interrupt flag. Bit 8 – CMP0 Compare 0 This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request will be generated if INTENCLR/SET.COMP0 is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Compare 0 interrupt flag. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n [n = 0..7] This flag is cleared by writing a '1' to the flag. This flag is set on the 0-to-1 transition of prescaler bit [n+2], and an interrupt request will be generated if INTENCLR/ SET.PERn is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Periodic Interval n interrupt flag. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 309

24.8.7 Debug Control

Name: DBGCTRL Offset: 0x0E Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Debug Run This bit is not reset by a software reset. This bit controls the functionality when the CPU is halted by an external debugger. Value Description 0 The RTC is halted when the CPU is halted by an external debugger. 1 The RTC continues normal operation when the CPU is halted by an external debugger. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 310

24.8.8 Synchronization Busy in COUNT32 mode (CTRLA.MODE=0) Name: SYNCBUSY Offset: 0x10 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 GP1 GP0 Access R R Reset 0 0 Bit 15 14 13 12 11 10 9 8 COUNTSYNC Access R Reset 0 Bit 7 6 5 4 3 2 1 0 COMP0 COUNT FREQCORR ENABLE SWRST Access R R R R R Reset 0 0 0 0 0 Bits 16, 17 – GPn General Purpose n Synchronization Busy Status Value Description 0 Write synchronization for GPn register is complete. 1 Write synchronization for GPn register is ongoing. Bit 15 – COUNTSYNC Count Read Sync Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.COUNTSYNC bit is complete. 1 Write synchronization for CTRLA.COUNTSYNC bit is ongoing. Bit 5 – COMP0 Compare 0 Synchronization Busy Status Value Description 0 Write synchronization for COMP0 register is complete. 1 Write synchronization for COMP0 register is ongoing. Bit 3 – COUNT Count Value Synchronization Busy Status Value Description 0 Read/write synchronization for COUNT register is complete. 1 Read/write synchronization for COUNT register is ongoing. Bit 2 – FREQCORR Frequency Correction Synchronization Busy Status Value Description 0 Read/write synchronization for FREQCORR register is complete. 1 Read/write synchronization for FREQCORR register is ongoing. Bit 1 – ENABLE Enable Synchronization Busy Status Value Description 0 Read/write synchronization for CTRLA.ENABLE bit is complete. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 311

1 Read/write synchronization for CTRLA.ENABLE bit is ongoing. Bit 0 – SWRST Software Reset Synchronization Busy Status Value Description 0 Read/write synchronization for CTRLA.SWRST bit is complete. 1 Read/write synchronization for CTRLA.SWRST bit is ongoing. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 312

24.8.9 Frequency Correlation

Name: FREQCORR Offset: 0x14 Reset: 0x00 Property: PAC Write-Protection, Write-Synchronized Bit 7 6 5 4 3 2 1 0 SIGN VALUE[6:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 – SIGN Correction Sign Value Description 0 The correction value is positive, i.e., frequency will be decreased. 1 The correction value is negative, i.e., frequency will be increased. Bits 6:0 – VALUE[6:0] Correction Value These bits define the amount of correction applied to the RTC prescaler. Value Description 0 Correction is disabled and the RTC frequency is unchanged. 1 - 127 The RTC frequency is adjusted according to the value. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 313

24.8.10 Counter Value in COUNT32 mode (CTRLA.MODE=0) Name: COUNT Offset: 0x18 Reset: 0x00000000 Property: PAC Write-Protection, Write-Synchronized Notes: 1. This register is read-synchronized when CTRLA.COUNTSYNC = 1: SYNCBUSY.COUNT must be checked to ensure the COUNT register synchronization is complete. 2. This register is write-synchronized: SYNCBUSY.COUNT must be checked to ensure the COUNT register synchronization is complete. 3. Prior to read access, this register must be synchronized by the user by writing CTRLA.COUNTSYNC = 1. Bit 31 30 29 28 27 26 25 24 COUNT[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 COUNT[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COUNT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – COUNT[31:0] Counter Value These bits define the value of the 32-bit RTC counter in mode 0. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 314

24.8.11 Compare 0 Value in COUNT32 mode (CTRLA.MODE=0) Name: COMP0 Offset: 0x20 Reset: 0x00000000 Property: PAC Write-Protection, Write-Synchronized Bit 31 30 29 28 27 26 25 24 COMP[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 COMP[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COMP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COMP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – COMP[31:0] Compare Value The 32-bit value of COMP0 is continuously compared with the 32-bit COUNT value. When a match occurs, the Compare 0 interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMP0) is set on the next counter cycle, and the counter value is cleared if CTRLA.MATCHCLR is '1'. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 315

24.8.12 General Purpose n

Name: GPn Offset: 0x40 + n*0x04 [n=0..1] Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 GP[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 GP[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 GP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – GP[31:0] General Purpose SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 316

24.8.13 Tamper Control

0 Debouncing is disabled for Tamper input INn

1 Debouncing is enabled for Tamper input INn

Bits 16, 17, 18, 19, 20 – TAMLVLn Tamper Level Select of Tamper Input INn [n=0..4] Note: Tamper Level Select feature does not apply to the Active Layer Protection mode (TAMPCTRL.INACT = ACTL). Value Description 0 A falling edge condition will be detected on Tamper input INn. 1 A rising edge condition will be detected on Tamper input INn. Bits 0:1, 2:3, 4:5, 6:7, 8:9 – INnACT Tamper Input n Action [n=0...4] These bits determine the action taken by Tamper Input INn. Value Name Description 0x0 OFF Off (Disabled) 0x1 WAKE Wake and set Tamper flag 0x2 CAPTURE Capture timestamp and set Tamper flag 0x3 ACTL Compare RTC signal routed between INn and OUT pins. When a mismatch occurs, capture timestamp and set Tamper flag SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 317

24.8.14 Timestamp

Name: TIMESTAMP Offset: 0x64 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 COUNT[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 COUNT[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COUNT[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – COUNT[31:0] Count Timestamp Value The 32-bit value of COUNT is captured by the TIMESTAMP when a tamper condition occurs SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 318

24.8.15 Tamper ID

Name: TAMPID Offset: 0x68 Reset: 0x00000000 Bit 31 30 29 28 27 26 25 24 TAMPEVT Access R/W Reset 0 Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 TAMPID4 TAMPID3 TAMPID2 TAMPID1 TAMPID0 Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 31 – TAMPEVT Tamper Event Detected Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value Description

0 A tamper input event has not been detected

1 A tamper input event has been detected

Bits 0, 1, 2, 3, 4 – TAMPIDn Tamper on Channel n Detected [n=0..4] Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value Description

0 A tamper condition has not been detected on Channel n

1 A tamper condition has been detected on Channel n

24.8.16 Backup n

Name: BKUPn Offset: 0x80 + n*0x04 [n=0..7] Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 BKUP[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 BKUP[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 BKUP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BKUP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – BKUP[31:0] Backup These bits are user-defined for general purpose use in the Backup domain. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 320

24.9 Register Summary - COUNT16

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 MODE[1:0] ENABLE SWRST 15:8 COUNTSYNC GPTRST BKTRST PRESCALER[3:0] 0x02 CTRLB 7:0 DMAEN RTCOUT DEBASYNC DEBMAJ GP0EN 15:8 ACTF[2:0] DEBF[2:0] 0x04 EVCTRL 7:0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 15:8 OVFEO TAMPEREO CMPEO1 CMPEO0 23:16 TAMPEVEI 31:24 0x08 INTENCLR 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF TAMPER CMP1 CMP0 0x0A INTENSET 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF TAMPER CMP1 CMP0 0x0C INTFLAG 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF TAMPER CMP1 CMP0 0x0E DBGCTRL 7:0 DBGRUN 0x0F Reserved 0x10 SYNCBUSY 7:0 COMP1 COMP0 PER COUNT FREQCORR ENABLE SWRST 15:8 COUNTSYNC 23:16 GP1 GP0 31:24 0x14 FREQCORR 7:0 SIGN VALUE[6:0] 0x15 ... 0x17 Reserved 0x18 COUNT 7:0 COUNT[7:0] 15:8 COUNT[15:8] 0x1A ... 0x1B Reserved 0x1C PER 7:0 PER[7:0] 15:8 PER[15:8] 0x1E ... 0x1F Reserved 0x20 COMP0 7:0 COMP[7:0] 15:8 COMP[15:8] 0x22 COMP1 7:0 COMP[7:0] 15:8 COMP[15:8] 0x24 ... 0x3F Reserved 0x40 GP0 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 0x44 GP1 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 0x48 ... 0x5F Reserved 0x60 TAMPCTRL 7:0 IN3ACT[1:0] IN2ACT[1:0] IN1ACT[1:0] IN0ACT[1:0] 15:8 IN4ACT[1:0] 23:16 TAMLVL4 TAMLVL3 TAMLVL2 TAMLVL1 TAMLVL0 31:24 DEBNC4 DEBNC3 DEBNC2 DEBNC1 DEBNC0 SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 321

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x64 TIMESTAMP 7:0 COUNT[7:0] 15:8 COUNT[15:8] 23:16 31:24 0x68 TAMPID 7:0 TAMPID4 TAMPID3 TAMPID2 TAMPID1 TAMPID0 15:8 23:16 31:24 TAMPEVT 0x6C ... 0x7F Reserved 0x80 BKUP0 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x84 BKUP1 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x88 BKUP2 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x8C BKUP3 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x90 BKUP4 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x94 BKUP5 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x98 BKUP6 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x9C BKUP7 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24]

24.10 Register Description - COUNT16

This Register Description section is valid if the RTC is in COUNT16 mode (CTRLA.MODE=1). Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read- Synchronized" and/or "Write-Synchronized" property in each individual register description. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 322

24.10.1 Control A in COUNT16 mode (CTRLA.MODE=1) Name: CTRLA Offset: 0x00 Reset: 0x0000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 COUNTSYNC GPTRST BKTRST PRESCALER[3:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MODE[1:0] ENABLE SWRST Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 – COUNTSYNC COUNT Read Synchronization Enable The COUNT register requires synchronization when reading. Disabling the synchronization will prevent reading valid values from the COUNT register. This bit is not enable-protected. Value Description Bit 14 – GPTRST GP Registers Reset On Tamper Enable Only GP registers enabled by the CTRLB.GPnEN bits are affected. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Value Description 0 GPn registers will not reset when a tamper condition occurs. 1 GPn registers will reset when a tamper condition occurs. Bit 13 – BKTRST BKUP Registers Reset On Tamper Enable All BKUPn registers are affected. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Value Description 0 BKUPn registers will not reset when a tamper condition occurs. 1 BKUPn registers will reset when a tamper condition occurs. Bits 11:8 – PRESCALER[3:0] Prescaler These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not synchronized. Value Name Description 0x0 OFF CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x2 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x3 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x4 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x5 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x6 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x7 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x8 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x9 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0xA DIV512 CLK_RTC_CNT = GCLK_RTC/512 SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 323

0xB DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xC-0xF - Reserved Bits 3:2 – MODE[1:0] Operating Mode This field defines the operating mode of the RTC. This bit is not synchronized. Value Name Description 0x0 COUNT32 Mode 0: 32-bit counter 0x1 COUNT16 Mode 1: 16-bit counter 0x2 CLOCK Mode 2: Clock/calendar 0x3 - Reserved Bit 1 – ENABLE Enable Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. Value Description Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the RTC (except DBGCTRL) to their initial state, and the RTC will be disabled. Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST will be cleared when the reset is complete. Value Description RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 324

24.10.2 Control B in COUNT16 mode (CTRLA.MODE=0) Name: CTRLB Offset: 0x02 Reset: 0x0000 Property: PAC Write-Protection, Enable-Protected Bit 15 14 13 12 11 10 9 8 ACTF[2:0] DEBF[2:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DMAEN RTCOUT DEBASYNC DEBMAJ GP0EN Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bits 14:12 – ACTF[2:0] Active Layer Frequency These bits define the prescaling factor for the RTC clock output (OUT) used during active layer protection in terms of the CLK_RTC. Value Name Description 0x0 DIV2 CLK_RTC_OUT = CLK_RTC / 2 0x1 DIV4 CLK_RTC_OUT = CLK_RTC / 4 0x2 DIV8 CLK_RTC_OUT = CLK_RTC / 8 0x3 DIV16 CLK_RTC_OUT = CLK_RTC / 16 0x4 DIV32 CLK_RTC_OUT = CLK_RTC / 32 0x5 DIV64 CLK_RTC_OUT = CLK_RTC / 64 0x6 DIV128 CLK_RTC_OUT = CLK_RTC / 128 0x7 DIV256 CLK_RTC_OUT = CLK_RTC / 256 Bits 10:8 – DEBF[2:0] Debounce Frequency These bits define the prescaling factor for the input debouncers in terms of the CLK_RTC. Value Name Description 0x0 DIV2 CLK_RTC_DEB = CLK_RTC / 2 0x1 DIV4 CLK_RTC_DEB = CLK_RTC / 4 0x2 DIV8 CLK_RTC_DEB = CLK_RTC / 8 0x3 DIV16 CLK_RTC_DEB = CLK_RTC / 16 0x4 DIV32 CLK_RTC_DEB = CLK_RTC / 32 0x5 DIV64 CLK_RTC_DEB = CLK_RTC / 64 0x6 DIV128 CLK_RTC_DEB = CLK_RTC / 128 0x7 DIV256 CLK_RTC_DEB = CLK_RTC / 256 Bit 7 – DMAEN DMA Enable The RTC can trigger a DMA request when the timestamp is ready in the TIMESTAMP register. Value Description 0 Tamper DMA request is disabled. Reading TIMESTAMP has no effect on INTFLAG.TAMPER. 1 Tamper DMA request is enabled. Reading TIMESTAMP will clear INTFLAG.TAMPER. Bit 6 – RTCOUT RTC Output Enable Value Description 0 The RTC active layer output is disabled. 1 The RTC active layer output is enabled. Bit 5 – DEBASYNC Debouncer Asynchronous Enable SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 325

24.10.3 Event Control in COUNT16 mode (CTRLA.MODE=1) Name: EVCTRL Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 TAMPEVEI Access R/W Reset 0 Bit 15 14 13 12 11 10 9 8 OVFEO TAMPEREO CMPEO1 CMPEO0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 16 – TAMPEVEI Tamper Event Input Enable Value Description

0 Tamper event input is disabled, and incoming events will be ignored

1 Tamper event input is enabled, and incoming events will capture the CLOCK value

Bit 15 – OVFEO Overflow Event Output Enable Value Description 0 Overflow event is disabled and will not be generated. 1 Overflow event is enabled and will be generated for every overflow. Bit 14 – TAMPEREO Tamper Event Output Enable Value Description 0 Tamper event output is disabled, and will not be generated. 1 Tamper event output is enabled, and will be generated for every tamper input. Bits 8, 9 – CMPEOn Compare n Event Output Enable [n = 0..1] Value Description 0 Compare n event is disabled and will not be generated. 1 Compare n event is enabled and will be generated for every compare match. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PEREOn Periodic Interval n Event Output Enable [n = 0..7] Value Description 0 Periodic Interval n event is disabled and will not be generated. [n = 0..7] 1 Periodic Interval n event is enabled and will be generated. [n = 0..7] SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 327

24.10.4 Interrupt Enable Clear in COUNT16 mode (CTRLA.MODE=1) Name: INTENCLR Offset: 0x08 Reset: 0x0000 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 15 14 13 12 11 10 9 8 OVF TAMPER CMP1 CMP0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. Bit 14 – TAMPER Tamper Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Tamper Interrupt Enable bit, which disables the Tamper interrupt. Value Description 0 The Tamper interrupt is disabled. 1 The Tamper interrupt is enabled. Bits 8, 9 – CMPn Compare n Interrupt Enable [n = 0..1] Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Compare n Interrupt Enable bit, which disables the Compare n interrupt. Value Description 0 The Compare n interrupt is disabled. 1 The Compare n interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 0..7] Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Periodic Interval n Interrupt Enable bit, which disables the Periodic Interval n interrupt. Value Description 0 Periodic Interval n interrupt is disabled. 1 Periodic Interval n interrupt is enabled. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 328

24.10.5 Interrupt Enable Set in COUNT16 mode (CTRLA.MODE=1) Name: INTENSET Offset: 0x0A Reset: 0x0000 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 15 14 13 12 11 10 9 8 OVF TAMPER CMP1 CMP0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. Bit 14 – TAMPER Tamper Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Tamper Interrupt Enable bit, which enables the Tamper interrupt. Value Description 0 The Tamper interrupt is disabled. 1 The Tamper interrupt is enabled. Bits 8, 9 – CMPn Compare n Interrupt Enable [n = 0..1] Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Compare n Interrupt Enable bit, which and enables the Compare n interrupt. Value Description 0 The Compare n interrupt is disabled. 1 The Compare n interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 0..7] Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Periodic Interval n Interrupt Enable bit, which enables the Periodic Interval n interrupt. Value Description 0 Periodic Interval n interrupt is disabled. 1 Periodic Interval n interrupt is enabled. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 329

24.10.6 Interrupt Flag Status and Clear in COUNT16 mode (CTRLA.MODE=1) Name: INTFLAG Offset: 0x0C Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 OVF TAMPER CMP1 CMP0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Overflow interrupt flag. Bit 14 – TAMPER Tamper This flag is set after a tamper condition occurs, and an interrupt request will be generated if INTENCLR.TAMPER/ INTENSET.TAMPER is one. Writing a '0' to this bit has no effect. Writing a one to this bit clears the Tamper interrupt flag. Bits 8, 9 – CMPn Compare n [n = 0..1] This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request will be generated if INTENCLR/SET.COMPn is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Compare n interrupt flag. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n [n = 0..7] This flag is cleared by writing a '1' to the flag. This flag is set on the 0-to-1 transition of prescaler bit [n+2], and an interrupt request will be generated if INTENCLR/ SET.PERx is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Periodic Interval n interrupt flag. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 330

24.10.7 Debug Control

24.10.8 Synchronization Busy in COUNT16 mode (CTRLA.MODE=1) Name: SYNCBUSY Offset: 0x10 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 GP1 GP0 Access R R Reset 0 0 Bit 15 14 13 12 11 10 9 8 COUNTSYNC Access R Reset 0 Bit 7 6 5 4 3 2 1 0 COMP1 COMP0 PER COUNT FREQCORR ENABLE SWRST Access R/W R/W R R R R R Reset 0 0 0 0 0 0 0 Bits 16, 17 – GPn General Purpose n Synchronization Busy Status Value Description 0 Write synchronization for GPn register is complete. 1 Write synchronization for GPn register is ongoing. Bit 15 – COUNTSYNC Count Read Sync Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.COUNTSYNC bit is complete. 1 Write synchronization for CTRLA.COUNTSYNC bit is ongoing. Bits 5, 6 – COMPn Compare n Synchronization Busy Status [n = 1..0] Value Description 0 Write synchronization for COMPn register is complete. 1 Write synchronization for COMPn register is ongoing. Bit 4 – PER Period Synchronization Busy Status Value Description 0 Write synchronization for PER register is complete. 1 Write synchronization for PER register is ongoing. Bit 3 – COUNT Count Value Synchronization Busy Status Value Description 0 Read/write synchronization for COUNT register is complete. 1 Read/write synchronization for COUNT register is ongoing. Bit 2 – FREQCORR Frequency Correction Synchronization Busy Status Value Description 0 Write synchronization for FREQCORR register is complete. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 332

1 Write synchronization for FREQCORR register is ongoing. Bit 1 – ENABLE Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.ENABLE bit is complete. 1 Write synchronization for CTRLA.ENABLE bit is ongoing. Bit 0 – SWRST Software Reset Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.SWRST bit is complete. 1 Write synchronization for CTRLA.SWRST bit is ongoing. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 333

24.10.9 Frequency Correlation

24.10.10 Counter Value in COUNT16 mode (CTRLA.MODE=1) Name: COUNT Offset: 0x18 Reset: 0x0000 Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized Notes: 1. This register is read-synchronized when CTRLA.COUNTSYNC = 1: SYNCBUSY.COUNT must be checked to ensure the COUNT register synchronization is complete. 2. This register is write-synchronized: SYNCBUSY.COUNT must be checked to ensure the COUNT register synchronization is complete. 3. Prior to read access, this register must be synchronized by the user by writing CTRLA.COUNTSYNC = 1. Bit 15 14 13 12 11 10 9 8 COUNT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – COUNT[15:0] Counter Value These bits define the value of the 16-bit RTC counter in COUNT16 mode (CTRLA.MODE=1). SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 335

24.10.11 Counter Period in COUNT16 mode (CTRLA.MODE=1) Name: PER Offset: 0x1C Reset: 0x0000 Property: PAC Write-Protection, Write-Synchronized Bit 15 14 13 12 11 10 9 8 PER[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PER[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – PER[15:0] Counter Period These bits define the value of the 16-bit RTC period in COUNT16 mode (CTRLA.MODE=1). SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 336

24.10.12 Compare n Value in COUNT16 mode (CTRLA.MODE=1) Name: COMPn Offset: 0x20 + n*0x02 [n=0..1] Reset: 0x0000 Property: PAC Write-Protection, Write-Synchronized Bit 15 14 13 12 11 10 9 8 COMP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COMP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – COMP[15:0] Compare Value The 16-bit value of COMPn is continuously compared with the 16-bit COUNT value. When a match occurs, the Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next counter cycle. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 337

24.10.13 General Purpose n

24.10.14 Tamper Control

Name: TAMPCTRL Offset: 0x60 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 DEBNC4 DEBNC3 DEBNC2 DEBNC1 DEBNC0 Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 TAMLVL4 TAMLVL3 TAMLVL2 TAMLVL1 TAMLVL0 Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 IN4ACT[1:0] Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 IN3ACT[1:0] IN2ACT[1:0] IN1ACT[1:0] IN0ACT[1:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 24, 25, 26, 27, 28 – DEBNCn Debounce Enable of Tamper Input INn [n=0..3] Note: Debounce feature does not apply to the Active Layer Protection mode (TAMPCTRL.INACT = ACTL). Value Description Bits 16, 17, 18, 19, 20 – TAMLVLn Tamper Level Select of Tamper Input INn [n=0..3] Note: Tamper Level feature does not apply to the Active Layer Protection mode (TAMPCTRL.INACT = ACTL). Value Description 0 A falling edge condition will be detected on Tamper input INn. 1 A rising edge condition will be detected on Tamper input INn. Bits 0:1, 2:3, 4:5, 6:7, 8:9 – INnACT Tamper Channel n Action [n=0..4] These bits determine the action taken by Tamper Channel n. Value Name Description 0x0 OFF Off (Disabled) 0x1 WAKE Wake and set Tamper flag 0x2 CAPTURE Capture timestamp and set Tamper flag 0x3 ACTL Compare RTC signal routed between INn and OUT pins . When a mismatch occurs, capture timestamp and set Tamper flag SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 339

24.10.15 Timestamp

Name: TIMESTAMP Offset: 0x64 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 COUNT[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15:0 – COUNT[15:0] Count Timestamp Value The 16-bit value of COUNT is captured by the TIMESTAMP when a tamper condition occurs. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 340

24.10.16 Tamper ID

Name: TAMPID Offset: 0x68 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 TAMPEVT Access R/W Reset 0 Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 TAMPID4 TAMPID3 TAMPID2 TAMPID1 TAMPID0 Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 31 – TAMPEVT Tamper Event Detected Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value Description Bits 0, 1, 2, 3, 4 – TAMPIDn Tamper on Channel n Detected [n=0..3] Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value Description RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 341

24.10.17 Backup n

24.11 Register Summary - CLOCK

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 MATCHCLR CLKREP MODE[1:0] ENABLE SWRST 15:8 CLOCKSYNC GPTRST BKTRST PRESCALER[3:0] 0x02 CTRLB 7:0 DMAEN RTCOUT DEBASYNC DEBMAJ GP0EN 15:8 ACTF[2:0] DEBF[2:0] 0x04 EVCTRL 7:0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 15:8 OVFEO TAMPEREO ALARMEO0 23:16 TAMPEVEI 31:24 0x08 INTENCLR 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF TAMPER ALARM0 0x0A INTENSET 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF TAMPER ALARM0 0x0C INTFLAG 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF TAMPER ALARM0 0x0E DBGCTRL 7:0 DBGRUN 0x0F Reserved 0x10 SYNCBUSY 7:0 ALARM0 CLOCK FREQCORR ENABLE SWRST 15:8 CLOCKSYNC MASK0 23:16 GP1 GP0 31:24 0x14 FREQCORR 7:0 SIGN VALUE[6:0] 0x15 ... 0x17 Reserved 0x18 CLOCK 7:0 MINUTE[1:0] SECOND[5:0] 15:8 HOUR[3:0] MINUTE[5:2] 23:16 MONTH[1:0] DAY[4:0] HOUR[4] 31:24 YEAR[5:0] MONTH[3:2] 0x1C ... 0x1F Reserved 0x20 ALARM 7:0 MINUTE[1:0] SECOND[5:0] 15:8 HOUR[3:0] MINUTE[5:2] 23:16 MONTH[1:0] DAY[4:0] HOUR[4] 31:24 YEAR[5:0] MONTH[3:2] 0x24 MASK 7:0 SEL[2:0] 0x25 ... 0x3F Reserved 0x40 GP0 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 0x44 GP1 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 0x48 ... 0x5F Reserved 0x60 TAMPCTRL 7:0 IN3ACT[1:0] IN2ACT[1:0] IN1ACT[1:0] IN0ACT[1:0] 15:8 IN4ACT[1:0] 23:16 TAMLVL4 TAMLVL3 TAMLVL2 TAMLVL1 TAMLVL0 31:24 DEBNC4 DEBNC3 DEBNC2 DEBNC1 DEBNC0 SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 343

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x64 TIMESTAMP 7:0 MINUTE[1:0] SECOND[5:0] 15:8 HOUR[3:0] MINUTE[5:2] 23:16 MONTH[1:0] DAY[4:0] HOUR[4] 31:24 YEAR[5:0] MONTH[3:2] 0x68 TAMPID 7:0 TAMPID4 TAMPID3 TAMPID2 TAMPID1 TAMPID0 15:8 23:16 31:24 TAMPEVT 0x6C ... 0x7F Reserved 0x80 BKUP0 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x84 BKUP1 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x88 BKUP2 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x8C BKUP3 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x90 BKUP4 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x94 BKUP5 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x98 BKUP6 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24] 0x9C BKUP7 7:0 BKUP[7:0] 15:8 BKUP[15:8] 23:16 BKUP[23:16] 31:24 BKUP[31:24]

24.12 Register Description - CLOCK

This Register Description section is valid if the RTC is in Clock/Calendar mode (CTRLA.MODE=2). Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read- Synchronized" and/or "Write-Synchronized" property in each individual register description. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 344

24.12.1 Control A in Clock/Calendar mode (CTRLA.MODE=2) Name: CTRLA Offset: 0x00 Reset: 0x0000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 CLOCKSYNC GPTRST BKTRST PRESCALER[3:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MATCHCLR CLKREP MODE[1:0] ENABLE SWRST Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 15 – CLOCKSYNC CLOCK Read Synchronization Enable The CLOCK register requires synchronization when reading. Disabling the synchronization will prevent reading valid values from the CLOCK register. This bit is not enable-protected. Value Description

0 CLOCK read synchronization is disabled

1 CLOCK read synchronization is enabled

Bit 14 – GPTRST GP Registers Reset On Tamper Enable Only GP registers enabled by the CTRLB.GPnEN bits are affected. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Bit 13 – BKTRST BKUP Registers Reset On Tamper Enable All BKUPn registers are affected. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Value Description 0 BKUPn registers will not reset when a tamper condition occurs. 1 BKUPn registers will reset when a tamper condition occurs. Bits 11:8 – PRESCALER[3:0] Prescaler These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not synchronized. Value Name Description 0x0 OFF CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x2 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x3 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x4 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x5 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x6 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x7 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x8 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x9 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0xA DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xB DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xC-0xF - Reserved SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 345

Bit 7 – MATCHCLR Clear on Match This bit is valid only in Mode 0 (COUNT32) and Mode 2 (CLOCK). This bit can be written only when the peripheral is disabled. This bit is not synchronized. Value Description Bit 6 – CLKREP Clock Representation This bit is valid only in Mode 2 and determines how the hours are represented in the Clock Value (CLOCK) register. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Value Description 0 24 Hour 1 12 Hour (AM/PM) Bits 3:2 – MODE[1:0] Operating Mode This field defines the operating mode of the RTC. This bit is not synchronized. Value Name Description 0x0 COUNT32 Mode 0: 32-bit counter 0x1 COUNT16 Mode 1: 16-bit counter 0x2 CLOCK Mode 2: Clock/calendar 0x3 - Reserved Bit 1 – ENABLE Enable Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. Value Description Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be disabled. Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST will be cleared when the reset is complete. Value Description RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 346

24.12.2 Control B in Clock/Calendar mode (CTRLA.MODE=2) Name: CTRLB Offset: 0x2 Reset: 0x0000 Property: PAC Write-Protection, Enable-Protected Bit 15 14 13 12 11 10 9 8 ACTF[2:0] DEBF[2:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DMAEN RTCOUT DEBASYNC DEBMAJ GP0EN Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bits 14:12 – ACTF[2:0] Active Layer Frequency These bits define the prescaling factor for the RTC clock output (OUT) used during active layer protection in terms of the CLK_RTC. Value Name Description 0x0 DIV2 CLK_RTC_OUT = CLK_RTC / 2 0x1 DIV4 CLK_RTC_OUT = CLK_RTC / 4 0x2 DIV8 CLK_RTC_OUT = CLK_RTC / 8 0x3 DIV16 CLK_RTC_OUT = CLK_RTC / 16 0x4 DIV32 CLK_RTC_OUT = CLK_RTC / 32 0x5 DIV64 CLK_RTC_OUT = CLK_RTC / 64 0x6 DIV128 CLK_RTC_OUT = CLK_RTC / 128 0x7 DIV256 CLK_RTC_OUT = CLK_RTC / 256 Bits 10:8 – DEBF[2:0] Debounce Frequency These bits define the prescaling factor for the input debouncers in terms of the CLK_RTC. Value Name Description 0x0 DIV2 CLK_RTC_DEB = CLK_RTC / 2 0x1 DIV4 CLK_RTC_DEB = CLK_RTC / 4 0x2 DIV8 CLK_RTC_DEB = CLK_RTC / 8 0x3 DIV16 CLK_RTC_DEB = CLK_RTC / 16 0x4 DIV32 CLK_RTC_DEB = CLK_RTC / 32 0x5 DIV64 CLK_RTC_DEB = CLK_RTC / 64 0x6 DIV128 CLK_RTC_DEB = CLK_RTC / 128 0x7 DIV256 CLK_RTC_DEB = CLK_RTC / 256 Bit 7 – DMAEN DMA Enable The RTC can trigger a DMA request when the timestamp is ready in the TIMESTAMP register. Value Description 0 Tamper DMA request is disabled. Reading TIMESTAMP has no effect on INTFLAG.TAMPER. 1 Tamper DMA request is enabled. Reading TIMESTAMP will clear INTFLAG.TAMPER. Bit 6 – RTCOUT RTC Out Enable Value Description 0 The RTC active layer output is disabled. 1 The RTC active layer output is enabled. Bit 5 – DEBASYNC Debouncer Asynchronous Enable SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 347

0 The tamper input debouncers operate synchronously. 1 The tamper input debouncers operate asynchronously. Bit 4 – DEBMAJ Debouncer Majority Enable Value Description 0 The tamper input debouncers match three equal values. 1 The tamper input debouncers match majority two of three values. Bit 0 – GP0EN General Purpose 0 Enable Value Description 0 COMP0 compare function enabled. GP0 disabled. 1 COMP0 compare function disabled. GP0 enabled. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 348

24.12.3 Event Control in Clock/Calendar mode (CTRLA.MODE=2) Name: EVCTRL Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 TAMPEVEI Access R/W Reset 0 Bit 15 14 13 12 11 10 9 8 OVFEO TAMPEREO ALARMEO0 Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 16 – TAMPEVEI Tamper Event Input Enable Value Description 0 Tamper event input is disabled, and incoming events will be ignored. 1 Tamper event input is enabled, and all incoming events will capture the CLOCK value. Bit 15 – OVFEO Overflow Event Output Enable Value Description 0 Overflow event is disabled and will not be generated. 1 Overflow event is enabled and will be generated for every overflow. Bit 14 – TAMPEREO Tamper Event Output Enable Value Description

0 Tamper event output is disabled, and will not be generated

1 Tamper event output is enabled, and will be generated for every tamper input. Bit 8 – ALARMEO0 Alarm 0 Event Output Enable Value Description 0 Alarm 0 event is disabled and will not be generated. 1 Alarm 0 event is enabled and will be generated for every compare match. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PEREOn Periodic Interval n Event Output Enable [n = 0..7] Value Description 0 Periodic Interval n event is disabled and will not be generated. 1 Periodic Interval n event is enabled and will be generated. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 349

24.12.4 Interrupt Enable Clear in Clock/Calendar mode (CTRLA.MODE=2) Name: INTENCLR Offset: 0x08 Reset: 0x0000 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 15 14 13 12 11 10 9 8 OVF TAMPER ALARM0 Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. Bit 14 – TAMPER Tamper Interrupt Enable Bit 8 – ALARM0 Alarm 0 Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Alarm 0 Interrupt Enable bit, which disables the Alarm interrupt. Value Description 0 The Alarm 0 interrupt is disabled. 1 The Alarm 0 interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 0..7] Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Periodic Interval n Interrupt Enable bit, which disables the Periodic Interval n interrupt. Value Description 0 Periodic Interval n interrupt is disabled. 1 Periodic Interval n interrupt is enabled. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 350

24.12.5 Interrupt Enable Set in Clock/Calendar mode (CTRLA.MODE=2) Name: INTENSET Offset: 0x0A Reset: 0x0000 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 15 14 13 12 11 10 9 8 OVF TAMPER ALARM0 Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. Bit 14 – TAMPER Tamper Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Tamper Interrupt Enable bit, which enables the Tamper interrupt. Value Description 0 The Tamper interrupt it disabled. 1 The Tamper interrupt is enabled. Bit 8 – ALARM0 Alarm 0 Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Alarm 0 Interrupt Enable bit, which enables the Alarm 0 interrupt. Value Description 0 The Alarm 0 interrupt is disabled. 1 The Alarm 0 interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 0..7] Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Periodic Interval n Interrupt Enable bit, which enables the Periodic Interval n interrupt. Value Description 0 Periodic Interval n interrupt is disabled. 1 Periodic Interval n interrupt is enabled. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 351

24.12.6 Interrupt Flag Status and Clear in Clock/Calendar mode (CTRLA.MODE=2) Name: INTFLAG Offset: 0x0C Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 OVF TAMPER ALARM0 Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Overflow interrupt flag. Bit 14 – TAMPER Tamper This flag is set after a tamper condition occurs, and an interrupt request will be generated if INTENCLR.TAMPER/ INTENSET.TAMPER is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Tamper interrupt flag. Bit 8 – ALARM0 Alarm 0 This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request will be generated if INTENCLR/SET.ALARM0 is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Alarm 0 interrupt flag. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n [n = 0..7] This flag is cleared by writing a '1' to the flag. This flag is set on the 0-to-1 transition of prescaler bit [n+2], and an interrupt request will be generated if INTENCLR/ SET.PERx is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Periodic Interval n interrupt flag. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 352

24.12.7 Debug Control

24.12.8 Synchronization Busy in Clock/Calendar mode (CTRLA.MODE=2) Name: SYNCBUSY Offset: 0x10 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 GP1 GP0 Access R R Reset 0 0 Bit 15 14 13 12 11 10 9 8 CLOCKSYNC MASK0 Access R R Reset 0 0 Bit 7 6 5 4 3 2 1 0 ALARM0 CLOCK FREQCORR ENABLE SWRST Access R R R R R Reset 0 0 0 0 0 Bits 16, 17 – GPn General Purpose n Synchronization Busy Status Value Description 0 Write synchronization for GPn register is complete. 1 Write synchronization for GPn register is ongoing. Bit 15 – CLOCKSYNC Clock Read Sync Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.CLOCKSYNC bit is complete. 1 Write synchronization for CTRLA.CLOCKSYNC bit is ongoing. Bit 11 – MASK0 Mask 0 Synchronization Busy Status Value Description 0 Write synchronization for MASK0 register is complete. 1 Write synchronization for MASK0 register is ongoing. Bit 5 – ALARM0 Alarm 0 Synchronization Busy Status Value Description 0 Write synchronization for ALARM0 register is complete. 1 Write synchronization for ALARM0 register is ongoing. Bit 3 – CLOCK Clock Register Synchronization Busy Status Value Description 0 Read/write synchronization for CLOCK register is complete. 1 Read/write synchronization for CLOCK register is ongoing. Bit 2 – FREQCORR Frequency Correction Synchronization Busy Status Value Description 0 Write synchronization for FREQCORR register is complete. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 354

24.12.9 Frequency Correlation

24.12.10 Clock Value in Clock/Calendar mode (CTRLA.MODE=2) Name: CLOCK Offset: 0x18 Reset: 0x00000000 Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized Bit 31 30 29 28 27 26 25 24 YEAR[5:0] MONTH[3:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 MONTH[1:0] DAY[4:0] HOUR[4] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 HOUR[3:0] MINUTE[5:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MINUTE[1:0] SECOND[5:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:26 – YEAR[5:0] Year The year offset with respect to the reference year (defined in software). The year is considered a leap year if YEAR[1:0] is zero. Bits 25:22 – MONTH[3:0] Month 1 – January 2 – February ... 12 – December Bits 21:17 – DAY[4:0] Day Day starts at 1 and ends at 28, 29, 30, or 31, depending on the month and year. Bits 16:12 – HOUR[4:0] Hour When CTRLA.CLKREP=0, the Hour bit group is in 24-hour format, with values 0-23. When CTRLA.CLKREP=1, HOUR[3:0] has values 1-12, and HOUR[4] represents AM (0) or PM (1). Bits 11:6 – MINUTE[5:0] Minute 0 – 59 Bits 5:0 – SECOND[5:0] Second 0 – 59 SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 357

24.12.11 Alarm Value in Clock/Calendar mode (CTRLA.MODE=2) Name: ALARM Offset: 0x20 Reset: 0x00000000 Property: PAC Write-Protection, Write-Synchronized The 32-bit value of ALARM is continuously compared with the 32-bit CLOCK value, based on the masking set by MASK.SEL. When a match occurs, the Alarm n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.ALARM) is set on the next counter cycle, and the counter is cleared if CTRLA.MATCHCLR is '1'. Bit 31 30 29 28 27 26 25 24 YEAR[5:0] MONTH[3:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 MONTH[1:0] DAY[4:0] HOUR[4] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 HOUR[3:0] MINUTE[5:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MINUTE[1:0] SECOND[5:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:26 – YEAR[5:0] Year The alarm year. Years are only matched if MASK.SEL is 6 Bits 25:22 – MONTH[3:0] Month The alarm month. Months are matched only if MASK.SEL is greater than 4. Bits 21:17 – DAY[4:0] Day The alarm day. Days are matched only if MASK.SEL is greater than 3. Bits 16:12 – HOUR[4:0] Hour The alarm hour. Hours are matched only if MASK.SEL is greater than 2. Bits 11:6 – MINUTE[5:0] Minute The alarm minute. Minutes are matched only if MASK.SEL is greater than 1. Bits 5:0 – SECOND[5:0] Second The alarm second. Seconds are matched only if MASK.SEL is greater than 0. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 358

24.12.12 Alarm Mask in Clock/Calendar mode (CTRLA.MODE=2) Name: MASK Offset: 0x24 Reset: 0x00 Property: PAC Write-Protection, Write-Synchronized Bit 7 6 5 4 3 2 1 0 SEL[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 2:0 – SEL[2:0] Alarm Mask Selection These bits define which bit groups of ALARM are valid. Value Name Description 0x0 OFF Alarm Disabled 0x1 SS Match seconds only 0x2 MMSS Match seconds and minutes only 0x3 HHMMSS Match seconds, minutes, and hours only 0x4 DDHHMMSS Match seconds, minutes, hours, and days only 0x5 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x6 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x7 - Reserved SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 359

24.12.13 General Purpose n

Name: GPn Offset: 0x40 + n*0x04 [n=0..1] Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 GP[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 GP[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 GP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – GP[31:0] General Purpose These bits are for user-defined general purpose use, see General Purpose Registers. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 360

24.12.14 Tamper Control

Name: TAMPCTRL Offset: 0x60 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 DEBNC4 DEBNC3 DEBNC2 DEBNC1 DEBNC0 Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 TAMLVL4 TAMLVL3 TAMLVL2 TAMLVL1 TAMLVL0 Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 IN4ACT[1:0] Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 IN3ACT[1:0] IN2ACT[1:0] IN1ACT[1:0] IN0ACT[1:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 24, 25, 26, 27, 28 – DEBNCn Debounce Enable of Tamper Input INn [n=0..4] Note: Debounce feature does not apply to the Active Layer Protection mode (TAMPCTRL.INACT = ACTL). Value Description Bits 16, 17, 18, 19, 20 – TAMLVLn Tamper Level Select of Tamper Input INn [n=0..4] Note: Tamper Level Select feature does not apply to the Active Layer Protection mode (TAMPCTRL.INACT = ACTL). Value Description 0 A falling edge condition will be detected on Tamper input INn. 1 A rising edge condition will be detected on Tamper input INn. Bits 0:1, 2:3, 4:5, 6:7, 8:9 – INnACT Tamper Input n Action [n=0...4] These bits determine the action taken by Tamper Input INn. Value Name Description 0x0 OFF Off (Disabled) 0x1 WAKE Wake and set Tamper flag 0x2 CAPTURE Capture timestamp and set Tamper flag 0x3 ACTL Compare RTC signal routed between INn and OUT pins. When a mismatch occurs, capture timestamp and set Tamper flag SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 361

24.12.15 Timestamp Value

Name: TIMESTAMP Offset: 0x64 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 YEAR[5:0] MONTH[3:2] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 MONTH[1:0] DAY[4:0] HOUR[4] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 HOUR[3:0] MINUTE[5:2] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MINUTE[1:0] SECOND[5:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:26 – YEAR[5:0] Year The year value is captured by the TIMESTAMP when a tamper condition occurs. Bits 25:22 – MONTH[3:0] Month The month value is captured by the TIMESTAMP when a tamper condition occurs. Bits 21:17 – DAY[4:0] Day The day value is captured by the TIMESTAMP when a tamper condition occurs. Bits 16:12 – HOUR[4:0] Hour The hour value is captured by the TIMESTAMP when a tamper condition occurs. Bits 11:6 – MINUTE[5:0] Minute The minute value is captured by the TIMESTAMP when a tamper condition occurs. Bits 5:0 – SECOND[5:0] Second The second value is captured by the TIMESTAMP when a tamper condition occurs. SAM L22 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 362

24.12.16 Tamper ID

Name: TAMPID Offset: 0x68 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 TAMPEVT Access R/W Reset 0 Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 TAMPID4 TAMPID3 TAMPID2 TAMPID1 TAMPID0 Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 31 – TAMPEVT Tamper Event Detected Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value Description Bits 0, 1, 2, 3, 4 – TAMPIDn Tamper on Channel n Detected [n=0..4] Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value Description RTC – Real-Time Counter © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 363

24.12.17 Backup n

DMAC – Direct Memory Access Controller

25.1 Overview

The Direct Memory Access Controller (DMAC) contains both a Direct Memory Access (DMA) engine and a Cyclic Redundancy Check (CRC) engine. The DMAC can transfer data between memories and peripherals and therefore, off-load these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time. With access to all peripherals, the DMAC can handle automatic transfer of data between communication modules. The DMA part of the DMAC has several DMA channels, which can receive different types of transfer triggers and generate transfer requests from the DMA channels to the arbiter, refer to the block diagram. The arbiter will grant one DMA channel at a time to act as the active channel. When an active channel has been granted, the fetch engine of the DMAC will fetch a transfer descriptor from the SRAM and store it in the internal memory of the active channel, which will then execute the data transmission. An ongoing data transfer of an active channel can be interrupted by a higher prioritized DMA channel. The DMAC will write back the updated transfer descriptor from the internal memory of the active channel to SRAM, and grant the higher prioritized channel a start transfer as the new active channel. Once a DMA channel is done with its transfer, interrupts and events can be generated optionally. The DMAC has four bus interfaces:

The data transfer bus is used for performing the actual DMA transfer.
The AHB/APB Bridge bus is used when writing and reading the I/O registers of the DMAC.
The descriptor fetch bus is used by the fetch engine to fetch transfer descriptors before data transfer can be started or continued.
The write-back bus is used to write the transfer descriptor back to SRAM. All buses are AHB host interfaces except the AHB/APB Bridge bus, which is an APB client interface. The CRC engine can be used by software to detect an accidental error in the transferred data and to take corrective action, such as requesting the data to be sent again or simply not using the incorrect data.

25.2 Features

Data Transfer From: – Peripheral-to-peripheral – Peripheral-to-memory – Memory-to-peripheral – Memory-to-memory
Transfer Trigger Sources: – Software – Events from Event System – Dedicated requests from peripherals
SRAM-based Transfer Descriptors: – Single transfer using one descriptor – Multi-buffer or Circular Buffer modes by linking multiple descriptors
Up to 16 Channels: – Enable 16 independent transfers – Automatic descriptor fetch for each channel – Suspend/resume operation support for each channel
Flexible Arbitration Scheme: – 4 configurable priority levels for each channel SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 365

– Fixed or round-robin priority scheme within each priority level

From 1 to 256KB Data Transfer in a Single Block Transfer
Multiple Addressing Modes: – Static – Configurable increment scheme
Optional Interrupt Generation: – On block transfer complete – On error detection – On channel suspend
4 Event Inputs: – One event input for each of the 4 least significant DMA channels – Can be selected to trigger normal transfers, periodic transfers or conditional transfers – Can be selected to suspend or resume channel operation
4 Event Outputs: – One output event for each of the 4 least significant DMA channels – Selectable generation on AHB, block, or transaction transfer complete
Error Management Supported by Write-back Function: – Dedicated write-back memory section for each channel to store ongoing descriptor transfer
CRC Polynomial Software Selectable to: – CRC-16 (CRC-CCITT) – CRC-32 (IEEE ® 802.3)

25.3 Block Diagram

Figure 25-1. DMAC Block Diagram HIGH SPEED BUS MATRIX AHB/APB Bridge CPU SRAM S S M M Events Channel 0 Channel 1 Channel n Arbiter DMA Channels HOST Active Channel CRC Engine Fetch Engine Interrupt / Events DMAC Interrupts Transfer Triggers n Data Transfer Write-back Descriptor Fetch SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 366

25.4 Signal Description

Not applicable.

25.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

25.5.1 I/O Lines

Not applicable.

25.5.2 Power Management

The DMAC will continue to operate in any sleep mode where the selected source clock is running. The DMAC’s interrupts can be used to wake-up the device from Sleep modes. Events connected to the event system can trigger other operations in the system without exiting Sleep modes. On hardware or software Reset, all registers are set to their Reset value.

25.5.3 Clocks

The DMAC bus clock (CLK_DMAC_APB) must be configured and enabled in the Main Clock module before using the DMAC. This bus clock (CLK_DMAC_APB) is always synchronous to the module clock (CLK_DMAC_AHB), but can be divided by a prescaler and may run even when the module clock is turned off.

25.5.4 DMA

Not applicable.

25.5.5 Interrupts

The interrupt request line is connected to the interrupt controller. Using the DMAC interrupt requires the interrupt controller to be configured first. References: Nested Vector Interrupt Controller

25.5.6 Events

Not applicable.

25.5.7 Debug Operation

When the CPU is halted in Debug mode the DMAC will halt normal operation. The DMAC can be forced to continue

25.5.8 Register Access Protection

All registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Interrupt Pending register (INTPEND)
Channel ID register (CHID)
Channel Interrupt Flag Status and Clear register (CHINTFLAG) Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. PAC write protection does not apply to accesses through an external debugger.

25.5.9 Analog Connections

25.6 Functional Description

25.6.1 Principle of Operation

The DMAC consists of a DMA module and a CRC module.

25.6.1.1 DMA

The DMAC can transfer data between memories and peripherals without interaction from the CPU. The data transferred by the DMAC are called transactions, and these transactions can be split into smaller data transfers. The following figure shows the relationship between the different transfer sizes: Figure 25-2. DMA Transfer Sizes DMA transaction Block transfer Link Enabled Burst transfer Link EnabledLink Enabled Beat transfer

Beat transfer: The size of one data transfer bus access, and the size is selected by writing the Beat Size bit group in the Block Transfer Control register (BTCTRL.BEATSIZE)
Block transfer: The amount of data one transfer descriptor can transfer, and the amount can range from 1 to 64k beats. A block transfer can be interrupted.
Burst transfer: Back-to-back beat transfers without CPU interference.
Transaction: The DMAC can link several transfer descriptors by having the first descriptor pointing to the second and so forth, as shown in the figure above. A DMA transaction is the complete transfer of all blocks within a linked list. A transfer descriptor describes how a block transfer should be carried out by the DMAC, and it must remain in SRAM. The previous figure shows several block transfers linked together, which are called linked descriptors. For further A DMA transfer is initiated by an incoming transfer trigger on one of the DMA channels. This trigger can be configured to be either a software trigger, an event trigger, or one of the dedicated peripheral triggers. The transfer trigger will result in a DMA transfer request from the specific channel to the arbiter. If there are several DMA channels with pending transfer requests, the arbiter chooses which channel is granted access to become the active channel. The DMA channel granted access as the active channel will carry out the transaction as configured in the transfer descriptor. A current transaction can be interrupted by a higher prioritized channel, but will resume the block transfer when the according DMA channel is granted access as the active channel again. For each beat transfer, an optional output event can be generated. For each block transfer, optional interrupts and an optional output event can be generated. When a transaction is completed, dependent on the configuration, the DMA channel will either be suspended or disabled.

25.6.1.2 CRC

The internal CRC engine supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and CRC-32 (IEEE details.

25.6.2 Basic Operation

25.6.2.1 Initialization

The following DMAC registers are enable-protected, meaning that they can only be written when the DMAC is disabled (CTRL.DMAENABLE=0): SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 368

Descriptor Base Memory Address register (BASEADDR)
Write-Back Memory Base Address register (WRBADDR) The following DMAC bit is enable-protected, meaning that it can only be written when both the DMAC and CRC are disabled (CTRL.DMAENABLE=0 and CTRL.CRCENABLE=0):
Software Reset bit in Control register (CTRL.SWRST) The following DMA channel register is enable-protected, meaning that it can only be written when the corresponding DMA channel is disabled (CHCTRLA.ENABLE=0):
Channel Control B (CHCTRLB) register, except the Command bit (CHCTRLB.CMD) and the Channel Arbitration Level bit (CHCTRLB.LVL) The following DMA channel bit is enable-protected, meaning that it can only be written when the corresponding DMA channel is disabled:
Channel Software Reset bit in Channel Control A register (CHCTRLA.SWRST) The following CRC registers are enable-protected, meaning that they can only be written when the CRC is disabled (CTRL.CRCENABLE=0):
CRC Control register (CRCCTRL)
CRC Checksum register (CRCCHKSUM) Enable-protection is denoted by the "Enable-Protected" property in the register description. Before the DMAC is enabled it must be configured, as outlined by the following steps:
The SRAM address of where the descriptor memory section is located must be written to the Description Base Address (BASEADDR) register
The SRAM address of where the write-back section should be located must be written to the Write-Back Memory Base Address (WRBADDR) register
Priority level x of the arbiter can be enabled by setting the Priority Level x Enable bit in the Control register (CTRL.LVLENx=1) Before a DMA channel is enabled, the DMA channel and the corresponding first transfer descriptor must be configured, as outlined by the following steps:
DMA channel configurations – The channel number of the DMA channel to configure must be written to the Channel ID (CHID) register – Trigger action must be selected by writing the Trigger Action bit group in the Channel Control B register (CHCTRLB.TRIGACT) – Trigger source must be selected by writing the Trigger Source bit group in the Channel Control B register (CHCTRLB.TRIGSRC)
Transfer Descriptor – The size of each access of the data transfer bus must be selected by writing the Beat Size bit group in the Block Transfer Control register (BTCTRL.BEATSIZE) – The transfer descriptor must be made valid by writing a one to the Valid bit in the Block Transfer Control register (BTCTRL.VALID) – Number of beats in the block transfer must be selected by writing the Block Transfer Count (BTCNT) register – Source address for the block transfer must be selected by writing the Block Transfer Source Address (SRCADDR) register – Destination address for the block transfer must be selected by writing the Block Transfer Destination Address (DSTADDR) register If CRC calculation is needed, the CRC engine must be configured before it is enabled, as outlined by the following steps:
The CRC input source must selected by writing the CRC Input Source bit group in the CRC Control register (CRCCTRL.CRCSRC) SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 369

The type of CRC calculation must be selected by writing the CRC Polynomial Type bit group in the CRC Control register (CRCCTRL.CRCPOLY)
If I/O is selected as input source, the beat size must be selected by writing the CRC Beat Size bit group in the CRC Control register (CRCCTRL.CRCBEATSIZE)

25.6.2.2 Enabling, Disabling, and Resetting

The DMAC is enabled by writing the DMA Enable bit in the Control register (CTRL.DMAENABLE) to '1'. The DMAC is disabled by writing a '0' to the CTRL.DMAENABLE bit. A DMA channel is enabled by writing the Enable bit in the Channel Control A register (CHCTRLA.ENABLE) to '1', after the corresponding channel ID to the channel is configured. A DMA channel is disabled by writing a '0' to CHCTRLAn.ENABLE. The CRC is enabled by writing a ‘1’ to the CRC Enable bit in the Control register (CTRL.CRCENABLE). The CRC is disabled by writing a '0' to CTRL.CRCENABLE. The DMAC is reset by writing a '1' to the Software Reset bit in the Control register (CTRL.SWRST) while the DMAC and CRC are disabled. All registers in the DMAC except DBGCTRL will be reset to their initial state. A DMA channel is reset by writing a '1' to the Software Reset bit in the Channel Control A register (CHCTRLAn.SWRST), after writing the corresponding channel ID to the Channel ID bit group in the Channel ID register (CHID.ID). The channel registers will be reset to their initial state. The corresponding DMA channel must be disabled in order for the Reset to take effect.

25.6.2.3 Transfer Descriptors

The transfer descriptors, together with the channel configurations, decide how a block transfer should be executed. Before a DMA channel is enabled (CHCTRLA.ENABLE is written to one) and receives a transfer trigger, its first transfer descriptor must be initialized and valid (BTCTRL.VALID). The first transfer descriptor describes the first block transfer of a transaction. All transfer descriptors must reside in SRAM. The addresses stored in the Descriptor Memory Section Base Address (BASEADDR) and Write-Back Memory Section Base Address (WRBADDR) registers tell the DMAC where to find the descriptor memory section and the write-back memory section. The descriptor memory section is where the DMAC expects to find the first transfer descriptors for all DMA channels. As BASEADDR points only to the first transfer descriptor of channel 0 (see figure below). All first transfer descriptors must be stored in a contiguous memory section, where the transfer descriptors must be ordered according to their The write-back memory section is where the DMAC stores the transfer descriptors for the ongoing block transfers. WRBADDR points to the ongoing transfer descriptor of channel 0. All ongoing transfer descriptors are stored in a contiguous memory section where the transfer descriptors are ordered according to their channel number. The following figure shows an example of linked descriptors on DMA channel 0. For additional information on linked SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 370

Figure 25-3. Memory Sections Channel 0 – Descriptor n-1 Channel 0 – Last Descriptor DESCADDR DESCADDR Device Memory Space BASEADDR Channel 0 – First Descriptor Channel 1 – First Descriptor Channel 2 – First Descriptor Channel n – First Descriptor Descriptor Section WRBADDR Channel 0 Ongoing Descriptor Channel 1 Ongoing Descriptor Channel 2 Ongoing Descriptor Channel n Ongoing Descriptor Write-Back Section Undefined Undefined Undefined Undefined Undefined SRCADDR DSTADDR BTCTRL DESCADDR BTCNT SRCADDR DSTADDR BTCTRL DESCADDR BTCNT SRCADDR DSTADDR BTCTRL 0x00000000 BTCNT The size of the descriptor and write-back memory sections are dependent on the number of the most significant enabled DMA channel m, as shown below: Si z e = 128bits ⋅ m + 1 For memory optimization, it is recommended to use the less significant DMA channels, if not all channels are required. The descriptor and write-back memory sections can either be two separate memory sections, or they can share a memory section (BASEADDR=WRBADDR). The benefit of having them in two separate sections, is that the same transaction for a channel can be repeated without having to modify the first transfer descriptor. The benefit of having descriptor memory and write-back memory in the same section is that it requires less SRAM.

25.6.2.4 Arbitration

If a DMA channel is enabled and not suspended when it receives a transfer trigger, it will send a transfer request to the arbiter. When the arbiter receives the transfer request it will include the DMA channel in the queue of channels having pending transfers, and the corresponding Pending Channel x bit in the Pending Channels registers (PENDCH.PENDCHx) will be set. Depending on the arbitration scheme, the arbiter will choose which DMA channel will be the next active channel. The active channel is the DMA channel being granted access to SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 371

perform its next transfer. When the arbiter has granted a DMA channel access to the DMAC, the corresponding bit PENDCH.PENDCHx will be cleared. See also the following figure. If the upcoming transfer is the first for the transfer request, the corresponding Busy Channel x bit in the Busy Channels register will be set (BUSYCH.BUSYCHx=1), and it will remain '1' for the subsequent granted transfers. When the channel has performed its granted transfer(s) it will be either fed into the queue of channels with pending transfers, set to be waiting for a new transfer trigger, suspended, or disabled. This depends on the channel and block transfer configuration. If the DMA channel is fed into the queue of channels with pending transfers, the corresponding BUSYCH.BUSYCHx will remain '1'. If the DMA channel is set to wait for a new transfer trigger, suspended, or disabled, the corresponding BUSYCH.BUSYCHx will be cleared. If a DMA channel is suspended while it has a pending transfer, it will be removed from the queue of pending channels, but the corresponding PENDCH.PENDCHx will remain set. When the same DMA channel is resumed, it will be added to the queue of pending channels again. If a DMA channel gets disabled (CHCTRLA.ENABLE=0) while it has a pending transfer, it will be removed from the queue of pending channels, and the corresponding PENDCH.PENDCHx will be cleared. Figure 25-4. Arbiter Overview Channel 0 Channel N Active Channel Priority decoder Active.LVLEXx PRICTRLx.LVLPRI Arbiter CTRL.LVLENx Burst Done Transfer Request Channel Number Level Enable Channel Burst Done Channel Priority Level Channel Pending Channel Suspend Channel Burst Done Channel Priority Level Channel Pending Channel Suspend Priority Levels When a channel level is pending or the channel is transferring data, the corresponding Level Executing bit is set in the Active Channel and Levels register (ACTIVE.LVLEXx). Each DMA channel supports a 4-level priority scheme. The priority level for a channel is configured by writing to the Channel Arbitration Level bit group in the Channel Control B register (CHCTRLB.LVL). As long as all priority levels are enabled, a channel with a higher priority level number will have priority over a channel with a lower priority level number. Each priority level x is enabled by setting the corresponding Priority Level x Enable bit in the Control register (CTRL.LVLENx=1). Within each priority level the DMAC's arbiter can be configured to prioritize statically or dynamically: Static Arbitration within a priority level is selected by writing a '0' to the Level x Round-Robin Scheduling Enable bit in the Priority Control 0 register (PRICTRL0.RRLVLENx). When static arbitration is selected, the arbiter will prioritize a low channel number over a high channel number as shown in the figure below. When using the static arbitration there is a risk of high channel numbers never being granted access as the active channel. This can be avoided using a dynamic arbitration scheme. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 372

Figure 25-5. Static Priority Scheduling Highest Channel Lowest Channel Highest Priority Lowest PriorityChannel N Channel 0 Channel x+1 Channel x Dynamic Arbitration within a priority level is selected by writing a '1' to PRICTRL0.RRLVLENx. The dynamic arbitration scheme in the DMAC is round-robin. With the round-robin scheme, the channel number of the last channel being granted access will have the lowest priority the next time the arbiter has to grant access to a channel within the same priority level, as shown in Figure 25-6. The channel number of the last channel being granted access as the active channel is stored in the Level x Channel Priority Number bit group in the Priority Control 0 register (PRICTRL0.LVLPRIx) for the corresponding priority level. Figure 25-6. Dynamic (Round-Robin) Priority Scheduling Channel N Channel N Channel 0 Channel x Channel x+1 Channel x last acknowledge request Channel (x+1) last acknowledge request Channel 0 Channel x Channel x+1 Channel x+2 Lowest Priority Highest Priority Highest Priority Lowest Priority

25.6.2.5 Data Transmission

Before the DMAC can perform a data transmission, a DMA channel has to be configured and enabled, its corresponding transfer descriptor has to be initialized, and the arbiter has to grant the DMA channel access as the active channel. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 373

Once the arbiter has granted a DMA channel access as the active channel (refer to DMA Block Diagram section) the transfer descriptor for the DMA channel will be fetched from SRAM using the fetch bus, and stored in the internal memory for the active channel. For a new block transfer, the transfer descriptor will be fetched from the descriptor memory section (BASEADDR); For an ongoing block transfer, the descriptor will be fetched from the write-back memory section (WRBADDR). By using the data transfer bus, the DMAC will read the data from the current source address and write it to the current destination address. For further details on how the current source and destination addresses are calculated, refer to the section on Addressing. The arbitration procedure is performed after each transfer. If the current DMA channel is granted access again, the block transfer counter (BTCNT) of the internal transfer descriptor will be decremented by the number of beats in a transfer, the optional output event Beat will be generated if configured and enabled, and the active channel will perform a new transfer. If a different DMA channel than the current active channel is granted access, the block transfer counter value will be written to the write-back section before the transfer descriptor of the newly granted DMA channel is fetched into the internal memory of the active channel. When a block transfer has come to its end (BTCNT is zero), the Valid bit in the Block Transfer Control register will be cleared (BTCTRL.VALID=0) before the entire transfer descriptor is written to the write-back memory. The optional interrupts, Channel Transfer Complete and Channel Suspend, and the optional output event Block, will be generated if configured and enabled. After the last block transfer in a transaction, the Next Descriptor Address register (DESCADDR) will hold the value 0x00000000, and the DMA channel will either be suspended or disabled, depending on the configuration in the Block Action bit group in the Block Transfer Control register (BTCTRL.BLOCKACT). If the transaction has further block transfers pending, DESCADDR will hold the SRAM address to the next transfer descriptor to be fetched. The DMAC will fetch the next descriptor into the internal memory of the active channel and write its content to the write-back section for the channel, before the arbiter gets to choose the next active channel.

25.6.2.6 Transfer Triggers and Actions

A DMA transfer through a DMA channel can be started only when a DMA transfer request is detected, and the DMA channel has been granted access to the DMA. A transfer request can be triggered from software, from a peripheral, or from an event. There are dedicated Trigger Source selections for each DMA Channel Control B (CHCTRLB.TRIGSRC). The trigger actions are available in the Trigger Action bit group in the Channel Control B register (CHCTRLB.TRIGACT). By default, a trigger generates a request for a block transfer operation. If a single descriptor is defined for a channel, the channel is automatically disabled when a block transfer has been completed. If a list of linked descriptors is defined for a channel, the channel is automatically disabled when the last descriptor in the list is executed. If the list still has descriptors to execute, the channel will be waiting for the next block transfer trigger. When enabled again, the channel will wait for the next block transfer trigger. The trigger actions can also be configured to generate a request for a beat transfer (CHCTRLB.TRIGACT=0x2) or transaction transfer (CHCTRLB.TRIGACT=0x3) instead of a block transfer (CHCTRLB.TRIGACT=0x0). Figure 25-7 shows an example where triggers are used with two linked block descriptors. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 374

Figure 25-7. Trigger Action and Transfers CHENn Trigger PENDCHn BUSYCHn Data Transfer CHENn Trigger PENDCHn BUSYCHn Data Transfer CHENn Trigger PENDCHn BUSYCHn Data Transfer Block Transfer Block TransferBlock Transfer Block TransferBlock Transfer Block Transfer Trigger Lost Trigger Lost Trigger Lost Transaction Trigger Action Block Trigger Action Beat Trigger Action BEATBEAT BEAT BEAT BEATBEAT BEATBEAT BEAT BEAT BEATBEAT BEATBEAT BEAT BEAT BEATBEAT If the trigger source generates a transfer request for a channel during an ongoing transfer, the new transfer request will be kept pending (CHSTATUS.PEND=1), and the new transfer can start after the ongoing one is done. Only one pending transfer can be kept per channel. If the trigger source generates more transfer requests while one is already pending, the additional ones will be lost. All channels pending status flags are also available in the Pending Channels register (PENDCH). When the transfer starts, the corresponding Channel Busy status flag is set in Channel Status register (CHSTATUS.BUSY). When the trigger action is complete, the Channel Busy status flag is cleared. All Channel Busy status flags are also available in the Busy Channels register (BUSYCH) in DMAC.

25.6.2.7 Addressing

Each block transfer needs to have both a source address and a destination address defined. The source address is set by writing the Transfer Source Address (SRCADDR)) register, the destination address is set by writing the Transfer Destination Address (DSTADDR) register. The addressing of this DMAC module can be static or incremental, for either source or destination of a block transfer, or both. Incrementation for the source address of a block transfer is enabled by writing the Source Address Incrementation Enable bit in the Block Transfer Control register (BTCTRL.SRCINC=1). The step size of the incrementation is configurable and can be chosen by writing the Step Selection bit in the Block Transfer Control register (BTCTRL.STEPSEL=1) and writing the desired step size in the Address Increment Step Size bit group in the Block Transfer Control register (BTCTRL.STEPSIZE). If BTCTRL.STEPSEL=0, the step size for the source incrementation will be the size of one beat. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 375

When source address incrementation is configured (BTCTRL.SRCINC=1), SRCADDR is calculated as follows: If BTCTRL.STEPSEL= 1: SRCADDR = SRCADDR ST A RT + BTC NT ⋅ B E A TSI ZE + 1 ⋅ 2STEPSIZE If BTCTRL.STEPSEL=0: SRCADDR = SRCADDR ST A RT + BTC NT ⋅ BE A TSI ZE + 1

SRCADDR START is the source address of the first beat transfer in the block transfer
BTCNT is the initial number of beats remaining in the block transfer
BEATSIZE is the configured number of bytes in a beat
STEPSIZE is the configured number of beats for each incrementation The following figure shows an example where DMA channel 0 is configured to increment the source address by one beat after each beat transfer (BTCTRL.SRCINC=1), and DMA channel 1 is configured to increment the source address by two beats (BTCTRL.SRCINC=1, BTCTRL.STEPSEL=1, and BTCTRL.STEPSIZE=0x1). As the destination address for both channels are peripherals, destination incrementation is disabled (BTCTRL.DSTINC=0). Figure 25-8. Source Address Increment SRC Data Buffer a b c d e f Incrementation for the destination address of a block transfer is enabled by setting the Destination Address Incrementation Enable bit in the Block Transfer Control register (BTCTRL.DSTINC=1). The step size of the incrementation is configurable by clearing BTCTRL.STEPSEL=0 and writing BTCTRL.STEPSIZE to the desired step size. If BTCTRL.STEPSEL=1, the step size for the destination incrementation will be the size of one beat. When the destination address incrementation is configured (BTCTRL.DSTINC=1), DSTADDR must be set and calculated as follows: DS T A DDR = D ST A DDR S T AR T + B TC NT • BE A TSI ZE + 1 • 2 STE PSI ZE where BTCTRL.STEPSEL is zero DS T A DDR = D ST A DDR S T AR T + B TC NT • BE AT SI ZE + 1 where BTCTRL.STEPSEL is one
DSTADDR START is the destination address of the first beat transfer in the block transfer
BTCNT is the initial number of beats remaining in the block transfer
BEATSIZE is the configured number of bytes in a beat
STEPSIZE is the configured number of beats for each incrementation The following figure shows an example where DMA channel 0 is configured to increment destination address by one beat (BTCTRL.DSTINC=1) and DMA channel 1 is configured to increment destination address by two beats (BTCTRL.DSTINC=1, BTCTRL.STEPSEL=0, and BTCTRL.STEPSIZE=0x1). As the source address for both channels are peripherals, source incrementation is disabled (BTCTRL.SRCINC=0). SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 376

Figure 25-9. Destination Address Increment DST Data Buffer a b c d

25.6.2.8 Error Handling

If a bus error is received from an AHB client during a DMA data transfer, the corresponding active channel is disabled and the corresponding Channel Transfer Error Interrupt flag in the Channel Interrupt Status and Clear register (CHINTFLAG.TERR) is set. If enabled, the optional transfer error interrupt is generated. The transfer counter will not be decremented and its current value is written-back in the write-back memory section before the channel is disabled. When the DMAC fetches an invalid descriptor (BTCTRL.VALID=0) or when the channel is resumed and the DMA fetches the next descriptor with null address (DESCADDR=0x00000000), the corresponding channel operation is suspended, the Channel Suspend Interrupt Flag in the Channel Interrupt Flag Status and Clear register (CHINTFLAG.SUSP) is set, and the Channel Fetch Error bit in the Channel Status register (CHSTATUS.FERR) is set. If enabled, the optional suspend interrupt is generated.

25.6.3 Additional Features

25.6.3.1 Linked Descriptors

A transaction can consist of either a single block transfer or of several block transfers. When a transaction consists of several block transfers it is done with the help of linked descriptors. Figure 25-3 illustrates how linked descriptors work. When the first block transfer is completed on DMA channel 0, the DMAC fetches the next transfer descriptor, which is pointed to by the value stored in the Next Descriptor Address (DESCADDR) register of the first transfer descriptor. Fetching the next transfer descriptor (DESCADDR) is continued until the last transfer descriptor. When the block transfer for the last transfer descriptor is executed and DESCADDR=0x00000000, the transaction is terminated. For further details on how the next descriptor is fetched

25.6.3.1.1 Adding Descriptor to the End of a List

To add a new descriptor at the end of the descriptor list, create the descriptor in SRAM, with DESCADDR=0x00000000 indicating that it is the new last descriptor in the list, and modify the DESCADDR value of the current last descriptor to the address of the newly created descriptor.

25.6.3.1.2 Modifying a Descriptor in a List

In order to add descriptors to a linked list, the following actions must be performed: 1. Enable the Suspend interrupt for the DMA channel. 2. Enable the DMA channel. 3. Reserve memory space in SRAM to configure a new descriptor. 4. Configure the new descriptor: – Set the next descriptor address ( DESCADDR) – Set the destination address ( 25.10.4. DSTADDR) – Set the source address ( 25.10.3. SRCADDR) – Configure the block transfer control ( BTCTRL) including

Optionally enable the suspend block action SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 377

Set the descriptor VALID bit 5. Clear the VALID bit for the existing list and for the descriptor which has to be updated. 6. Read DESCADDR from the write-back memory. – If the DMA has not already fetched the descriptor that requires changes (i.e., DESCADDR is wrong):
Update the DESCADDR location of the descriptor from the list
Optionally clear the suspend block action
Set the descriptor VALID bit to ' 1'
Optionally enable the Resume Software command – If the DMA is executing the same descriptor as the one that requires changes:
Set the Channel Suspend Software command and wait for the suspend interrupt
Update the next descriptor address ( DESCRADDR) in the write-back memory
Clear the interrupt sources and set the Resume Software command
Update the DESCADDR location of the descriptor from the list
Optionally clear the suspend block action
Set the descriptor VALID bit to ' 1' 7. Go to step 4 if needed.

25.6.3.1.3 Adding a Descriptor Between Existing Descriptors

To insert a new descriptor 'C' between two existing descriptors ('A' and 'B'), the descriptor currently executed by the DMA must be identified. 1. If DMA is executing descriptor B, descriptor C cannot be inserted. 2. If DMA has not started to execute descriptor A, follow the steps: a. Set the descriptor A VALID bit to ' 0'. b. Set the DESCADDR value of descriptor A to point to descriptor C instead of descriptor B. c. Set the DESCADDR value of descriptor C to point to descriptor B. d. Set the descriptor A VALID bit to ' 1'. 3. If DMA is executing descriptor A: a. Apply the software suspend command to the channel and b. Perform steps 2.1 through 2.4. c. Apply the software resume command to the channel.

25.6.3.2 Channel Suspend

The channel operation can be suspended at any time by software by writing a '1' to the Suspend command in the Command bit field of Channel Control B register (CHCTRLB.CMD). After the ongoing burst transfer is completed, the channel operation is suspended and the suspend command is automatically cleared. When suspended, the Channel Suspend Interrupt flag in the Channel Interrupt Status and Clear register is set (CHINTFLAG.SUSP=1) and the optional suspend interrupt is generated. By configuring the block action to suspend by writing Block Action bit group in the Block Transfer Control register (BTCTRL.BLOCKACT is 0x2 or 0x3), the DMA channel will be suspended after it has completed a block transfer. The DMA channel will be kept enabled and will be able to receive transfer triggers, but it will be removed from the arbitration scheme. If an invalid transfer descriptor (BTCTRL.VALID=0) is fetched from SRAM, the DMA channel will be suspended, and the Channel Fetch Error bit in the Channel Status register(CHASTATUS.FERR) will be set. Note: Only enabled DMA channels can be suspended. If a channel is disabled when it is attempted to be suspended, the internal suspend command will be ignored.

25.6.3.3 Channel Resume and Next Suspend Skip

A channel operation can be resumed by software by setting the Resume command in the Command bit field of the Channel Control B register (CHCTRLB.CMD). If the channel is already suspended, the channel operation resumes from where it previously stopped when the Resume command is detected. When the Resume command is SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 378

issued before the channel is suspended, the next suspend action is skipped and the channel continues the normal operation. Figure 25-10. Channel Suspend/Resume Operation CHENn Memory Descriptor Transfer Resume Command Descriptor 0 (suspend disabled) Fetch Block Transfer 0 Descriptor 1 (suspend enabled) Block Transfer 1 Suspend skipped Descriptor 2 (suspend enabled) Block Transfer 2 Channel suspended Descriptor 3 (last) Block Transfer 3

25.6.3.4 Event Input Actions

The event input actions are available only on the least significant DMA channels. For details on channels with event input support, refer to the in the Event system documentation. Before using event input actions, the event controller must be configured first according to the following table, and the Channel Event Input Enable bit in the Channel Control B register (CHCTRLB.EVIE) must be written to '1'. Refer also to 25.6.6. Events. Table 25-1. Event Input Action Action CHCTRLB.EVACT CHCTRLB.TRGSRC None NOACT - Normal Transfer TRIG DISABLE Conditional Transfer on Strobe TRIG any peripheral Conditional Transfer CTRIG Conditional Block Transfer CBLOCK Channel Suspend SUSPEND Channel Resume RESUME Skip Next Block Suspend SSKIP Normal Transfer The event input is used to trigger a beat or burst transfer on peripherals. The event is acknowledged as soon as the event is received. When received, both the Channel Pending Status bit in the Channel Status register (CHSTATUS.PEND) and the corresponding Channel n bit in the Pending Channels trigger is lost. The figure below shows an example where beat transfers are enabled by internal events. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 379

Figure 25-13. Conditional Event with Beat Peripheral Triggers Event Peripheral Trigger PENDCHn Data Transfer Block Transfer BEAT BEAT Conditional Block Transfer The event input is used to trigger a conditional block transfer on peripherals. Before starting transfers within a block, an event must be received. When received, the event is acknowledged when the block transfer is completed. A software trigger will trigger a transfer. The figure below shows an example where conditional event block transfer is started with peripheral beat trigger requests. Figure 25-14. Conditional Block Transfer with Beat Peripheral Triggers BEAT BEAT Block Transfer BEAT BEAT Block Transfer Data Transfer Peripheral Trigger Event PENDCHn Channel Suspend The event input is used to suspend an ongoing channel operation. The event is acknowledged when the current AHB Channel Resume The event input is used to resume a suspended channel operation. The event is acknowledged as soon as the event is received and the Channel Suspend Interrupt Flag (CHINTFLAG.SUSP) is cleared. For further details refer to Skip Next Block Suspend This event can be used to skip the next block suspend action. If the channel is suspended before the event rises, the channel operation is resumed and the event is acknowledged. If the event rises before a suspend block action is detected, the event is kept until the next block suspend detection. When the block transfer is completed, the channel continues the operation (not suspended) and the event is acknowledged.

25.6.3.5 Event Output Selection

Event output selection is available only for the Least Significant DMA channels. The pulse width of an event output from a channel is one AHB clock cycle. The output of channel events is enabled by writing a '1' to the Channel Event Output Enable bit in the Control B register (CHCTRLB.EVOE). The event output cause is selected by writing to the Event Output Selection bits in SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 381

the Block Transfer Control register (BTCTRL.EVOSEL). It is possible to generate events after each block transfer (BTCTRL.EVOSEL=0x1) or beat transfer (BTCTRL.EVOSEL=0x3). To enable an event being generated when a transaction is complete, the block event selection must be set in the last transfer descriptor only. Figure 25-15 shows an example where the event output generation is enabled in the first block transfer, and disabled in the second block. Figure 25-15. Event Output Generation Beat Event Output Data Transfer Event Output Data Transfer Event Output Block Transfer BEAT Block Event Output Block Transfer Block TransferBlock Transfer BEAT BEATBEAT BEAT BEAT BEAT BEAT

25.6.3.6 Aborting Transfers

Transfers on any channel can be aborted gracefully by software by disabling the corresponding DMA channel. It is also possible to abort all ongoing or pending transfers by disabling the DMAC. When a DMA channel disable request or DMAC disable request is detected:

Ongoing transfers of the active channel will be disabled when the ongoing beat transfer is completed and the write-back memory section is updated. This prevents transfer corruption before the channel is disabled.
All other enabled channels will be disabled in the next clock cycle. The corresponding Channel Enable bit in the Channel Control A register is cleared (CHCTRLA.ENABLE=0) when the channel is disabled. The corresponding DMAC Enable bit in the Control register is cleared (CTRL.DMAENABLE=0) when the entire DMAC module is disabled.

25.6.3.7 CRC Operation

A Cyclic Redundancy Check (CRC) is an error detection technique used to find errors in data. It is commonly used to determine whether the data during a transmission, or data present in data and program memories has been corrupted or not. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be appended to the data and used as a checksum. When the data is received, the device or application repeats the calculation using the DSU's CRC engine. If the new CRC result does not match the one calculated earlier, the block contains a data error. The application will then detect this and may take a corrective action, such as requesting the data to be sent again or simply not using the incorrect data. The CRC engine in DMAC supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3). Typically, applying CRC-n (CRC-16 or CRC-32) to a data block of arbitrary length will detect any single alteration that is ≤n bits in length, and will detect the fraction 1-2-n of all longer error bursts. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 382

CRC-16: – Polynomial: x 16+ x12+ x5+ 1 – Hex value: 0x1021
CRC-32: – Polynomial: x 32+x26+ x23+ x22+x16+ x12+ x11+ x10+ x8+ x7+ x5+ x4+ x2+ x + 1 – Hex value: 0x04C11DB7 The data source for the CRC engine can either be one of the DMA channels or the APB bus interface, and must be selected by writing to the CRC Input Source bits in the CRC Control register (CRCCTRL.CRCSRC). The CRC engine then takes data input from the selected source and generates a checksum based on these data. The checksum is available in the CRC Checksum register (CRCCHKSUM). When CRC-32 polynomial is used, the final checksum read is bit reversed and complemented, as shown in CRC Generator Block Diagram. The CRC polynomial is selected by writing to the CRC Polynomial Type bit in the CRC Control register (CRCCTRL.CRCPOLY), the default is CRC-16. The CRC engine operates on byte only. When the DMA is used as data source for the CRC engine, the DMA channel beat size setting will be used. When used with APB bus interface, the application must select the CRC Beat Size bit field of CRC Control register (CRCCTRL.CRCBEATSIZE). 8-, 16-, or 32-bit bus transfer access type is supported. The corresponding number of bytes will be written in the CRCDATAIN register and the CRC engine will operate on the input data in a byte by byte manner. Figure 25-16. CRC Generator Block Diagram 168 8 32 Checksum read crc32 CRCCTRL CHECKSUM bit-reverse + complement CRC-16 CRC-32 DMAC Channels CRCDATAIN CRC on DMA data CRC-16 or CRC-32 calculations can be performed on data passing through any DMA channel. Once a DMA channel is selected as the source, the CRC engine will continuously generate the CRC on the data passing through the DMA channel. The checksum is available for readout once the DMA transaction is completed or aborted. A CRC can also be generated on SRAM, Flash, or I/O memory by passing these SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 383

data through a DMA channel. If the latter is done, the destination register for the DMA data can be the data input (CRCDATAIN) register in the CRC engine. CRC using the I/O interface Before using the CRC engine with the I/O interface, the application must set the CRC Beat Size bits in the CRC Control register (CRCCTRL.CRCBEATSIZE). 8/16/32-bit bus transfer type can be selected. CRC can be performed on any data by loading them into the CRC engine using the CPU and writing the data to the CRCDATAIN register. Using this method, an arbitrary number of bytes can be written to the register by the CPU, and CRC is done continuously for each byte. This means if a 32-bit data is written to the CRCDATAIN register the CRC engine takes four cycles to calculate the CRC. The CRC complete is signaled by a set CRCBUSY bit in the CRCSTATUS register. New data can be written only when CRCBUSY flag is not set.

25.6.4 DMA Operation

Not applicable.

25.6.5 Interrupts

The DMAC channels have the following interrupt sources:

Transfer Complete (TCMPL): Indicates that a block transfer is completed on the corresponding channel. Refer to
Transfer Error (TERR): Indicates that a bus error has occurred during a burst transfer, or that an invalid
Channel Suspend (SUSP): Indicates that the corresponding channel has been suspended. Refer to Each interrupt source has an Interrupt flag associated with it. The Interrupt flag in the Channel Interrupt Flag Status and Clear (CHINTFLAG) register is set when the Interrupt condition occurs. Each interrupt can be individually enabled by setting the corresponding bit in the Channel Interrupt Enable Set register (CHINTENSET=1), and disabled by setting the corresponding bit in the Channel Interrupt Enable Clear register (CHINTENCLR=1). The status of enabled interrupts can be read from either INTENSET or INTENCLR. An interrupt request is generated when the Interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the Interrupt flag is cleared, the interrupt is disabled, the DMAC is reset or the corresponding DMA channel is reset. See CHINTFLAG for details on how to clear Interrupt flags. All interrupt requests are ORed together on system level to generate one combined interrupt request to the NVIC. The user must read the Channel Interrupt Status (INTSTATUS) register to identify the channels with pending interrupts and must read the Channel Interrupt Flag Status and Clear (CHINTFLAG) register to determine which Interrupt condition is present for the corresponding channel. It is also possible to read the Interrupt Pending register (INTPEND), which provides the lowest channel number with pending interrupt and the respective Interrupt flags. Note: Interrupts must be globally enabled for interrupt requests to be generated. References: Nested Vector Interrupt Controller

25.6.6 Events

The DMAC can generate the following output events:

Channel (CH): Generated when a block transfer for a given channel has been completed, or when a beat transfer within a block transfer for a given channel has been completed. Refer to Event Output Selection for details. Setting the Channel Control B Event Output Enable bit (CHCTRLB.EVOE=1) enables the corresponding output event configured in the Event Output Selection bit group in the Block Transfer Control register (BTCTRL.EVOSEL). Clearing CHCTRLB.EVOE=0 disables the corresponding output event. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 384

The DMAC can take the following actions on an input event:

Transfer and Periodic Transfer Trigger (TRIG): normal transfer or periodic transfers on peripherals are enabled
Conditional Transfer Trigger (CTRIG): conditional transfers on peripherals are enabled
Conditional Block Transfer Trigger (CBLOCK): conditional block transfers on peripherals are enabled
Channel Suspend Operation (SUSPEND): suspend a channel operation
Channel Resume Operation (RESUME): resume a suspended channel operation
Skip Next Block Suspend Action (SSKIP): skip the next block suspend transfer condition
Increase Priority (INCPRI): increase channel priority Setting the Channel Control B Event Input Enable bit (CHCTRLB.EVIE=1) enables the corresponding action on input event. Clearing this bit disables the corresponding action on input event. Note that several actions can be enabled for incoming events. If several events are connected to the peripheral, any enabled action will be taken for any of the incoming events. For further details on event input actions, refer to Event Input Actions. Note: Event input and outputs are not available for every channel. Refer to the Features section for more information.

25.6.7 Sleep Mode Operation

Each DMA channel can be configured to operate in any sleep mode. To be able to run in standby, the RUNSTDBY bit in Channel Control A register (CHCTRLA.RUNSTDBY) must be written to '1'. The DMAC can wake up the device using interrupts from any sleep mode or perform actions through the Event System. For channels with CHCTRLA.RUNSTDBY = 0, it is up to software to stop DMA transfers on these channels and wait for completion before going to standby mode using the following sequence: 1. Suspend the DMAC channels for which CHCTRLA.RUNSTDBY = 0. 2. Check the SYNCBUSY bits of registers accessed by the DMAC channels being suspended. 3. Go to sleep. 4. When the device wakes up, resume the suspended channels. Note: In Stand-by Sleep mode, the DMAC can only access RAM when it is not back biased (PM.STDBYCFG.BBIASxx = 0x0) Note: In Stand-by Sleep mode, the DMAC can access the SRAM only when the power domain PD1 is not in retention and PM.STDBYCFG.BBIASLP=0x0. The DMAC can access the SRAM in Stand-by Sleep mode only when the power domain PD2 is not in retention and PM.STDBYCFG.BBIASHS = 0x0.

25.6.8 Synchronization

25.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRL 7:0 CRCENABLE DMAENABLE SWRST 15:8 LVLEN3 LVLEN2 LVLEN1 LVLEN0 0x02 CRCCTRL 7:0 CRCPOLY[1:0] CRCBEATSIZE[1:0] 15:8 CRCSRC[5:0] 0x04 CRCDATAIN 7:0 CRCDATAIN[7:0] 15:8 CRCDATAIN[15:8] 23:16 CRCDATAIN[23:16] 31:24 CRCDATAIN[31:24] 0x08 CRCCHKSUM 7:0 CRCCHKSUM[7:0] 15:8 CRCCHKSUM[15:8] 23:16 CRCCHKSUM[23:16] 31:24 CRCCHKSUM[31:24] 0x0C CRCSTATUS 7:0 CRCZERO CRCBUSY 0x0D DBGCTRL 7:0 DBGRUN 0x0E QOSCTRL 7:0 DQOS[1:0] FQOS[1:0] WRBQOS[1:0] 0x0F Reserved 0x10 SWTRIGCTRL 7:0 SWTRIG7 SWTRIG6 SWTRIG5 SWTRIG4 SWTRIG3 SWTRIG2 SWTRIG1 SWTRIG0 15:8 SWTRIG15 SWTRIG14 SWTRIG13 SWTRIG12 SWTRIG11 SWTRIG10 SWTRIG9 SWTRIG8 23:16 31:24 0x14 PRICTRL0 7:0 RRLVLEN0 LVLPRI0[3:0] 15:8 RRLVLEN1 LVLPRI1[3:0] 23:16 RRLVLEN2 LVLPRI2[3:0] 31:24 RRLVLEN3 LVLPRI3[3:0] 0x18 ... 0x1F Reserved 0x20 INTPEND 7:0 ID[3:0] 15:8 PEND BUSY FERR SUSP TCMPL TERR 0x22 ... 0x23 Reserved 0x24 INTSTATUS 7:0 CHINT7 CHINT6 CHINT5 CHINT4 CHINT3 CHINT2 CHINT1 CHINT0 15:8 CHINT15 CHINT14 CHINT13 CHINT12 CHINT11 CHINT10 CHINT9 CHINT8 23:16 31:24 0x28 BUSYCH 7:0 BUSYCH7 BUSYCH6 BUSYCH5 BUSYCH4 BUSYCH3 BUSYCH2 BUSYCH1 BUSYCH0 15:8 BUSYCH15 BUSYCH14 BUSYCH13 BUSYCH12 BUSYCH11 BUSYCH10 BUSYCH9 BUSYCH8 23:16 31:24 0x2C PENDCH 7:0 PENDCH7 PENDCH6 PENDCH5 PENDCH4 PENDCH3 PENDCH2 PENDCH1 PENDCH0 15:8 PENDCH15 PENDCH14 PENDCH13 PENDCH12 PENDCH11 PENDCH10 PENDCH9 PENDCH8 23:16 31:24 0x30 ACTIVE 7:0 LVLEX3 LVLEX2 LVLEX1 LVLEX0 15:8 ABUSY ID[4:0] 23:16 BTCNT[7:0] 31:24 BTCNT[15:8] 0x34 BASEADDR 7:0 BASEADDR[7:0] 15:8 BASEADDR[15:8] 23:16 BASEADDR[23:16] 31:24 BASEADDR[31:24] 0x38 WRBADDR 7:0 WRBADDR[7:0] 15:8 WRBADDR[15:8] 23:16 WRBADDR[23:16] 31:24 WRBADDR[31:24] SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 386

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x3C ... 0x3E Reserved 0x3F CHID 7:0 ID[3:0] 0x40 CHCTRLA 7:0 RUNSTDBY ENABLE SWRST 0x41 ... 0x43 Reserved 0x44 CHCTRLB 7:0 LVL[1:0] EVOE EVIE EVACT[2:0] 15:8 TRIGSRC[5:0] 23:16 TRIGACT[1:0] 31:24 CMD[1:0] 0x48 ... 0x4B Reserved 0x4C CHINTENCLR 7:0 SUSP TCMPL TERR 0x4D CHINTENSET 7:0 SUSP TCMPL TERR 0x4E CHINTFLAG 7:0 SUSP TCMPL TERR 0x4F CHSTATUS 7:0 FERR BUSY PEND

25.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 25.5.8. Register Access Protection. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 387

25.8.1 Control

Name: CTRL Offset: 0x00 Reset: 0x00X0 Property: PAC Write-Protection, Enable-Protected Bit 15 14 13 12 11 10 9 8 LVLEN3 LVLEN2 LVLEN1 LVLEN0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCENABLE DMAENABLE SWRST Access R/W R/W R/W Reset 0 0 0 Bits 8, 9, 10, 11 – LVLENx Priority Level x Enable [x=0..3] When this bit is set, all requests with the corresponding level will be fed into the arbiter block. When cleared, all requests with the corresponding level will be ignored. For details on arbitration schemes, refer to the Arbitration section. These bits are not enable-protected. Value Description

0 Transfer requests for Priority level x will not be handled

1 Transfer requests for Priority level x will be handled

Bit 2 – CRCENABLE CRC Enable Writing a '0' to this bit will disable the CRC calculation when the CRC Status Busy flag is cleared (CRCSTATUS. CRCBUSY). The bit is zero when the CRC is disabled. Writing a '1' to this bit will enable the CRC calculation. This bit is not enable-protected. Value Description

0 The CRC calculation is disabled

1 The CRC calculation is enabled

Bit 1 – DMAENABLE DMA Enable Setting this bit will enable the DMA module. Writing a '0' to this bit will disable the DMA module. When writing a '0' during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst transfer is completed. This bit is not enable-protected. Value Description Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit when both the DMAC and the CRC module are disabled (DMAENABLE and CRCENABLE are '0') resets all registers in the DMAC (except DBGCTRL) to their initial state. If either the DMAC or CRC module is enabled, the Reset request will be ignored and the DMAC will return an access error. Value Description

0 There is no Reset operation ongoing

1 A Reset operation is ongoing

25.8.2 CRC Control

Name: CRCCTRL Offset: 0x02 Reset: 0x0000 Property: PAC Write-Protection, Enable-Protected Bit 15 14 13 12 11 10 9 8 CRCSRC[5:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCPOLY[1:0] CRCBEATSIZE[1:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 13:8 – CRCSRC[5:0] CRC Input Source These bits select the input source for generating the CRC, as shown in the table below. The selected source is locked until either the CRC generation is completed or the CRC module is disabled. This means the CRCSRC cannot be modified when the CRC operation is ongoing. The lock is signaled by the CRCBUSY Status bit. CRC generation complete is generated and signaled from the selected source when used with the DMA channel. Value Name Description 0x00 NOACT No action 0x01 IO I/O interface 0x02-0x1 F - Reserved 0x20 CH0 DMA channel 0 0x21 CH1 DMA channel 1 0x22 CH2 DMA channel 2 0x23 CH3 DMA channel 3 0x24 CH4 DMA channel 4 0x25 CH5 DMA channel 5 0x26 CH6 DMA channel 6 0x27 CH7 DMA channel 7 0x28 CH8 DMA channel 8 0x29 CH9 DMA channel 9 0x2A CH10 DMA channel 10 0x2B CH11 DMA channel 11 Bits 3:2 – CRCPOLY[1:0] CRC Polynomial Type These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface, as shown in the table below. Value Name Description 0x0 CRC16 CRC-16 (CRC-CCITT) 0x1 CRC32 CRC32 (IEEE 802.3) 0x2-0x3 Reserved Bits 1:0 – CRCBEATSIZE[1:0] CRC Beat Size These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface. Value Name Description 0x0 BYTE 8-bit bus transfer 0x1 HWORD 16-bit bus transfer 0x2 WORD 32-bit bus transfer 0x3 Reserved SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 389

25.8.3 CRC Data Input

Name: CRCDATAIN Offset: 0x04 Reset: 0x00000000 Property: PAC Write Protection Bit 31 30 29 28 27 26 25 24 CRCDATAIN[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CRCDATAIN[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CRCDATAIN[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCDATAIN[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – CRCDATAIN[31:0] CRC Data Input These bits store the data for which the CRC checksum is computed. A new CRC checksum is ready (CRCBEAT+ 1) clock cycles after the CRCDATAIN register is written. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 390

25.8.4 CRC Checksum

Name: CRCCHKSUM Offset: 0x08 Reset: 0x00000000 Property: PAC Write Protection, Enable-Protected The CRCCHKSUM represents the 16- or 32-bit checksum value and the generated CRC. The register is reset to zero by default, but it is possible to reset all bits to one by writing the CRCCHKSUM register directly. It is possible to write this register only when the CRC module is disabled. If CRC-32 is selected and the CRC Status Busy flag is cleared (i.e., CRC generation is completed or aborted), the bit reversed (bit 31 is swapped with bit 0, bit 30 with bit 1, etc.) and complemented result will be read from CRCCHKSUM. If CRC-16 is selected or the CRC Status Busy flag is set (i.e., CRC generation is ongoing), CRCCHKSUM will contain the actual content. Bit 31 30 29 28 27 26 25 24 CRCCHKSUM[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CRCCHKSUM[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CRCCHKSUM[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCCHKSUM[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – CRCCHKSUM[31:0] CRC Checksum These bits store the generated CRC result. The 16 MSB bits are always read zero when CRC-16 is enabled. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 391

25.8.5 CRC Status

Name: CRCSTATUS Offset: 0x0C Reset: 0x00 Property: PAC Write Protection Bit 7 6 5 4 3 2 1 0 CRCZERO CRCBUSY Access R R/W Reset 0 0 Bit 1 – CRCZERO CRC Zero This bit is cleared when a new CRC source is selected. This bit is set when the CRC generation is complete and the CRC checksum is zero. When running CRC-32 and appending the checksum at the end of the packet (as little endian), the final checksum should be 0x2144df1c, and not zero. However, if the checksum is complemented before it is appended (as little endian) to the data, the final result in the checksum register will be zero. See the description of CRCCHKSUM to read out different versions of the checksum. Bit 0 – CRCBUSY CRC Module Busy This flag is cleared by writing a one to it when used with I/O interface. When used with a DMA channel, the bit is set when the corresponding DMA channel is enabled, and cleared when the corresponding DMA channel is disabled. This register bit cannot be cleared by the application when the CRC is used with a DMA channel. This bit is set when a source configuration is selected and as long as the source is using the CRC module. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 392

25.8.6 Debug Control

Name: DBGCTRL Offset: 0x0D Reset: 0x00 Property: PAC Write Protection Bit 7 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Debug Run This bit is not reset by a Software Reset. This bit controls the functionality when the CPU is halted by an external debugger. Value Description 0 The DMAC is halted when the CPU is halted by an external debugger. 1 The DMAC continues normal operation when the CPU is halted by an external debugger. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 393

25.8.7 Quality of Service Control

Name: QOSCTRL Offset: 0x0E Reset: 0x2A Property: PAC Write Protection Bit 7 6 5 4 3 2 1 0 DQOS[1:0] FQOS[1:0] WRBQOS[1:0] Access R/W R/W R/W R/W R/W R/W Reset 1 0 1 0 1 0 Bits 5:4 – DQOS[1:0] Data Transfer Quality of Service These bits define the memory priority access during the data transfer operation. DQOS[1:0] Name Description 0x0 DISABLE Background (no sensitive operation) 0x1 LOW Sensitive Bandwidth 0x2 MEDIUM Sensitive Latency 0x3 HIGH Critical Latency Bits 3:2 – FQOS[1:0] Fetch Quality of Service These bits define the memory priority access during the fetch operation. FQOS[1:0] Name Description 0x0 DISABLE Background (no sensitive operation) 0x1 LOW Sensitive Bandwidth 0x2 MEDIUM Sensitive Latency 0x3 HIGH Critical Latency Bits 1:0 – WRBQOS[1:0] Write-Back Quality of Service These bits define the memory priority access during the write-back operation. WRBQOS[1:0] Name Description 0x0 DISABLE Background (no sensitive operation) 0x1 LOW Sensitive Bandwidth 0x2 MEDIUM Sensitive Latency 0x3 HIGH Critical Latency SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 394

25.8.8 Software Trigger Control

Name: SWTRIGCTRL Offset: 0x10 Reset: 0x00000000 Property: PAC Write Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 SWTRIG15 SWTRIG14 SWTRIG13 SWTRIG12 SWTRIG11 SWTRIG10 SWTRIG9 SWTRIG8 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SWTRIG7 SWTRIG6 SWTRIG5 SWTRIG4 SWTRIG3 SWTRIG2 SWTRIG1 SWTRIG0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – SWTRIGn Channel n Software Trigger [n = 0..15] This bit is cleared when the Channel Pending bit in the Channel Status register (CHSTATUS.PEND) for the corresponding channel is either set, or by writing a '1' to it. This bit is set if CHSTATUS.PEND is already '1' when writing a '1' to that bit. Writing a '0' to this bit will clear the bit. Writing a '1' to this bit will generate a DMA software trigger on channel x, if CHSTATUS.PEND=0 for channel x. CHSTATUS.PEND will be set and SWTRIGn will remain cleared. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 395

25.8.9 Priority Control 0

Name: PRICTRL0 Offset: 0x14 Reset: 0x00000000 Property: PAC Write Protection Bit 31 30 29 28 27 26 25 24 RRLVLEN3 LVLPRI3[3:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 RRLVLEN2 LVLPRI2[3:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 RRLVLEN1 LVLPRI1[3:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RRLVLEN0 LVLPRI0[3:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 31 – RRLVLEN3 Level 3 Round-Robin Arbitration Enable This bit controls which arbitration scheme is selected for DMA channels with priority level 3. For details on arbitration Value Description

0 Static arbitration scheme for channels with level 3 priority

1 Round-robin arbitration scheme for channels with level 3 priority

Bits 27:24 – LVLPRI3[3:0] Level 3 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN3=1) for priority level 3, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 3. When static arbitration is enabled (PRICTRL0.RRLVLEN3=0) for priority level 3, and the value of this bit group is non-zero, it will not affect the static priority scheme. This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN3 written to '0'). Bit 23 – RRLVLEN2 Level 2 Round-Robin Arbitration Enable This bit controls which arbitration scheme is selected for DMA channels with priority level 2. For details on arbitration Value Description

0 Static arbitration scheme for channels with level 2 priority

1 Round-robin arbitration scheme for channels with level 2 priority

Bits 19:16 – LVLPRI2[3:0] Level 2 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN2=1) for priority level 2, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 2. When static arbitration is enabled (PRICTRL0.RRLVLEN2=0) for priority level 2, and the value of this bit group is non-zero, it will not affect the static priority scheme. This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN2 written to '0'). SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 396

Bit 15 – RRLVLEN1 Level 1 Round-Robin Scheduling Enable Value Description

0 Static arbitration scheme for channels with level 1 priority

1 Round-robin arbitration scheme for channels with level 1 priority

Bits 11:8 – LVLPRI1[3:0] Level 1 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN1=1) for priority level 1, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 1. When static arbitration is enabled (PRICTRL0.RRLVLEN1=0) for priority level 1, and the value of this bit group is non-zero, it will not affect the static priority scheme. This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN1 written to '0'). Bit 7 – RRLVLEN0 Level 0 Round-Robin Scheduling Enable Value Description

0 Static arbitration scheme for channels with level 0 priority

1 Round-robin arbitration scheme for channels with level 0 priority

Bits 3:0 – LVLPRI0[3:0] Level 0 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN0=1) for priority level 0, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 0. When static arbitration is enabled (PRICTRL0.RRLVLEN0=0) for priority level 0, and the value of this bit group is non-zero, it will not affect the static priority scheme. This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN0 written to '0'). SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 397

25.8.10 Interrupt Pending

Name: INTPEND Offset: 0x20 Reset: 0x0000 Property: - This register allows the user to identify the lowest DMA channel with pending interrupt. Bit 15 14 13 12 11 10 9 8 PEND BUSY FERR SUSP TCMPL TERR Access R R R R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ID[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 – PEND Pending This bit will read '1' when the channel selected by Channel ID field (ID) is pending. Bit 14 – BUSY Busy This bit will read '1' when the channel selected by Channel ID field (ID) is busy. Bit 13 – FERR Fetch Error This bit will read '1' when the channel selected by Channel ID field (ID) fetched an invalid descriptor. Bit 10 – SUSP Channel Suspend This bit will read '1' when the channel selected by Channel ID field (ID) has pending Suspend interrupt. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel ID (ID) Suspend Interrupt flag. Bit 9 – TCMPL Transfer Complete This bit will read '1' when the channel selected by Channel ID field (ID) has pending Transfer Complete interrupt. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel ID (ID) Transfer Complete Interrupt flag. Bit 8 – TERR Transfer Error This bit is read one when the channel selected by Channel ID field (ID) has pending Transfer Error interrupt. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel ID (ID) Transfer Error Interrupt flag. Bits 3:0 – ID[3:0] Channel ID These bits store the lowest channel number with pending interrupts. The number is valid if Suspend (SUSP), Transfer Complete (TCMPL) or Transfer Error (TERR) bits are set. The Channel ID field is refreshed when a new channel (with channel number less than the current one) with pending interrupts is detected, or when the application clears the corresponding channel interrupt sources. When no pending channels interrupts are available, these bits will always return zero value when read. When the bits are written, indirect access to the corresponding Channel Interrupt Flag register is enabled. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 398

25.8.11 Interrupt Status

Name: INTSTATUS Offset: 0x24 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 CHINT15 CHINT14 CHINT13 CHINT12 CHINT11 CHINT10 CHINT9 CHINT8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CHINT7 CHINT6 CHINT5 CHINT4 CHINT3 CHINT2 CHINT1 CHINT0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – CHINTn Channel n Pending Interrupt [n=0..15] This bit is set when Channel n has a pending interrupt/the interrupt request is received. This bit is cleared when the corresponding Channel n interrupts are disabled or the interrupts sources are cleared. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 399

25.8.12 Busy Channels

Name: BUSYCH Offset: 0x28 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 BUSYCH15 BUSYCH14 BUSYCH13 BUSYCH12 BUSYCH11 BUSYCH10 BUSYCH9 BUSYCH8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BUSYCH7 BUSYCH6 BUSYCH5 BUSYCH4 BUSYCH3 BUSYCH2 BUSYCH1 BUSYCH0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – BUSYCHn Busy Channel n [x=0..15] This bit is cleared when the channel trigger action for DMA channel n is complete, when a bus error for DMA channel n is detected, or when DMA channel n is disabled. This bit is set when DMA channel n starts a DMA transfer. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 400

25.8.13 Pending Channels

Name: PENDCH Offset: 0x2C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 PENDCH15 PENDCH14 PENDCH13 PENDCH12 PENDCH11 PENDCH10 PENDCH9 PENDCH8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PENDCH7 PENDCH6 PENDCH5 PENDCH4 PENDCH3 PENDCH2 PENDCH1 PENDCH0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – PENDCHn Pending Channel n [n=0..15] This bit is cleared when trigger execution defined by channel trigger action settings for DMA channel n is started, when a bus error for DMA channel n is detected or when DMA channel n is disabled. For details on trigger action settings, refer to CHCTRLB.TRIGACT. This bit is set when a transfer is pending on DMA channel n. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 401

25.8.14 Active Channel and Levels

Name: ACTIVE Offset: 0x30 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 BTCNT[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 BTCNT[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ABUSY ID[4:0] Access R R R R R R Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LVLEX3 LVLEX2 LVLEX1 LVLEX0 Access R R R R Reset 0 0 0 0 Bits 31:16 – BTCNT[15:0] Active Channel Block Transfer Count These bits hold the 16-bit block transfer count of the ongoing transfer. This value is stored in the active channel and written back in the corresponding Write-Back channel memory location when the arbiter grants a new channel access. The value is valid only when the active channel Active Busy flag (ABUSY) is set. Bit 15 – ABUSY Active Channel Busy This bit is cleared when the active transfer count is written back in the write-back memory section. This bit is set when the next descriptor transfer count is read from the write-back memory section. Bits 12:8 – ID[4:0] Active Channel ID These bits hold the channel index currently stored in the active channel registers. The value is updated each time the arbiter grants a new channel transfer access request. Bits 0, 1, 2, 3 – LVLEXx Level x Channel Trigger Request Executing [x=0..3] This bit is set when a level-x channel trigger request is executing or pending. This bit is cleared when no request is pending or being executed. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 402

25.8.15 Descriptor Memory Section Base Address

Name: BASEADDR Offset: 0x34 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 BASEADDR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 BASEADDR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 BASEADDR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BASEADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – BASEADDR[31:0] Descriptor Memory Base Address These bits store the Descriptor memory section base address. The value must be 64-bit aligned. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 403

25.8.16 Write-Back Memory Section Base Address

Name: WRBADDR Offset: 0x38 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 WRBADDR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 WRBADDR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 WRBADDR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WRBADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – WRBADDR[31:0] Write-Back Memory Base Address These bits store the Write-Back memory base address. The value must be 64-bit aligned. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 404

25.8.17 Channel ID

Name: CHID Offset: 0x3F Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 ID[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 3:0 – ID[3:0] Channel ID These bits define the channel number that will be affected by the channel registers (CH*). Before reading or writing a channel register, the channel ID bit group must be written first. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 405

25.8.18 Channel Control A

Name: CHCTRLA Offset: 0x40 Reset: 0x00 Property: PAC Write Protection, Enable-Protected This register affects the DMA channel that is selected in the Channel ID register (CHID.ID). Bit 7 6 5 4 3 2 1 0 RUNSTDBY ENABLE SWRST Access R R/W R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 6 – RUNSTDBY Channel run in standby This bit is used to keep the DMAC channel running in Standby mode. This bit is not enable-protected. Value Description 0 The DMAC channel is halted in standby. 1 The DMAC channel continues to run in standby. Bit 1 – ENABLE Channel Enable Writing a '0' to this bit during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst transfer is completed. Writing a '1' to this bit will enable the DMA channel. This bit is not enable-protected. Value Description

0 DMA channel is disabled

1 DMA channel is enabled

Bit 0 – SWRST Channel Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets the Channel registers to their initial state. The bit can be set when the channel is disabled (ENABLE=0). Writing a '1' to this bit will be ignored as long as ENABLE=1. This bit is automatically cleared when the Reset is completed. Value Description DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 406

25.8.19 Channel Control B

Name: CHCTRLB Offset: 0x44 Reset: 0x00000000 Property: PAC Write Protection, Enable-Protected This register affects the DMA channel that is selected in the Channel ID register (CHID.ID). Bit 31 30 29 28 27 26 25 24 CMD[1:0] Access R/W R/W Reset 0 0 Bit 23 22 21 20 19 18 17 16 TRIGACT[1:0] Access R/W R/W Reset 0 0 Bit 15 14 13 12 11 10 9 8 TRIGSRC[5:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LVL[1:0] EVOE EVIE EVACT[2:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bits 25:24 – CMD[1:0] Software Command Next Suspend Skip. These bits are not enable-protected. CMD[1:0] Name Description 0x0 NOACT No action 0x1 SUSPEND Channel suspend operation 0x2 RESUME Channel resume operation 0x3 - Reserved Bits 23:22 – TRIGACT[1:0] Trigger Action These bits define the trigger action used for a transfer. TRIGACT[1:0] Name Description 0x0 BLOCK One trigger required for each block transfer 0x1 - Reserved 0x2 BEAT One trigger required for each beat transfer 0x3 TRANSACTION One trigger required for each transaction Bits 13:8 – TRIGSRC[5:0] Trigger Source These bits define the peripheral trigger which is source of the transfer. For details on trigger selection and trigger modes, refer to Transfer Triggers and Actions and CHCTRLB.TRIGACT. Value Name Description 0x00 DISABLE Only software/event triggers 0x01 RTC TIMESTAMP RTC Timestamp Trigger 0x02 SERCOM0 RX SERCOM0 RX Trigger 0x03 SERCOM0 TX SERCOM0 TX Trigger SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 407

0x04 SERCOM1 RX SERCOM1 RX Trigger 0x05 SERCOM1 TX SERCOM1 TX Trigger 0x06 SERCOM2 RX SERCOM2 RX Trigger 0x07 SERCOM2 TX SERCOM2 TX Trigger 0x08 SERCOM3 RX SERCOM3 RX Trigger 0x09 SERCOM3 TX SERCOM3 TX Trigger 0x0A SERCOM4 RX SERCOM4 RX Trigger 0x0B SERCOM4 TX SERCOM4 TX Trigger 0c0C SERCOM5 RX SERCOM5 RX Trigger 0x0D SERCOM5 TX SERCOM5 TX Trigger 0x0E TCC0 OVF TCC0 Overflow Trigger 0x0F TCC0 MC0 TCC0 Match/Compare 0 Trigger 0x10 TCC0 MC1 TCC0 Match/Compare 1 Trigger 0x11 TCC0 MC2 TCC0 Match/Compare 2 Trigger 0x12 TCC0 MC3 TCC0 Match/Compare 3 Trigger 0x13 TC0 OVF TC0 Overflow Trigger 0x14 TC0 MC0 TC0 Match/Compare 0 Trigger 0x15 TC0 MC1 TC0 Match/Compare 1 Trigger 0x16 TC1 OVF TC1 Overflow Trigger 0x17 TC1 MC0 TC1 Match/Compare 0 Trigger 0x18 TC1 MC1 TC1 Match/Compare 1 Trigger 0x19 TC2 OVF TC2 Overflow Trigger 0x1A TC2 MC0 TC2 Match/Compare 0 Trigger 0x1B TC2 MC1 TC2 Match/Compare 1 Trigger 0x1C TC3 OVF TC3 Overflow Trigger 0x1D TC3 MC0 TC3 Match/Compare 0 Trigger 0x1E TC3 MC1 TC3 Match/Compare 1 Trigger 0x1F ADC RESRDY ADC Result Ready Trigger 0x20 SLCD DMU SLCD Display Memory Update Trigger 0x21 SLCD ACMDRDY SLCD Automated Character Mapping Data Ready Trigger 0x22 SLCD ABMDRDY SLCD Automated Bit Mapping Data Ready Trigger 0x23 AES WR AES Write Trigger 0x24 AES RD AES Read Trigger 0x25 PTC EOC PTC End of Conversion Trigger 0x26 PTC SEQ PTC Sequence Trigger 0x27 PTC WCOMP PTC Window Comparator Trigger Bits 6:5 – LVL[1:0] Channel Arbitration Level These bits define the arbitration level used for the DMA channel, where a high level has priority over a low level. For These bits are not enable-protected. TRIGACT[1:0] Name Description 0x0 LVL0 Channel Priority Level 0 0x1 LVL1 Channel Priority Level 1 0x2 LVL2 Channel Priority Level 2 0x3 LVL3 Channel Priority Level 3 Bit 4 – EVOE Channel Event Output Enable This bit indicates if the Channel event generation is enabled. The event will be generated for every condition defined in the descriptor Event Output Selection (BTCTRL.EVOSEL). This bit is available only for the Least Significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details. Value Description

0 Channel event generation is disabled

1 Channel event generation is enabled

Bit 3 – EVIE Channel Event Input Enable This bit is available only for the Least Significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details. Value Description

0 Channel event action will not be executed on any incoming event

1 Channel event action will be executed on any incoming event

Bits 2:0 – EVACT[2:0] Event Input Action These bits define the event input action, as shown below. The action is executed only if the corresponding EVIE bit in CHCTRLB register of the channel is set. These bits are available only for the Least Significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details. EVACT[2:0] Name Description 0x0 NOACT No action 0x1 TRIG Normal Transfer and Conditional Transfer on Strobe trigger 0x2 CTRIG Conditional transfer trigger 0x3 CBLOCK Conditional block transfer 0x4 SUSPEND Channel suspend operation 0x5 RESUME Channel resume operation 0x6 SSKIP Skip next block suspend action 0x7 - Reserved SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 409

25.8.20 Channel Interrupt Enable Clear

Name: CHINTENCLR Offset: 0x4C Reset: 0x00 Property: PAC Write Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Channel Interrupt Enable Set (CHINTENSET) register. This register affects the DMA channel that is selected in the Channel ID register (CHID.ID). Bit 7 6 5 4 3 2 1 0 SUSP TCMPL TERR Access R/W R/W R/W Reset 0 0 0 Bit 2 – SUSP Channel Suspend Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel Suspend Interrupt Enable bit, which disables the Channel Suspend interrupt. Value Description

0 The Channel Suspend interrupt is disabled

1 The Channel Suspend interrupt is enabled

Bit 1 – TCMPL Channel Transfer Complete Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel Transfer Complete Interrupt Enable bit, which disables the Channel Transfer Complete interrupt. Value Description 0 The Channel Transfer Complete interrupt is disabled. When block action is set to none, the TCMPL flag will not be set when a block transfer is completed.

1 The Channel Transfer Complete interrupt is enabled

Bit 0 – TERR Channel Transfer Error Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel Transfer Error Interrupt Enable bit, which disables the Channel Transfer Error interrupt. Value Description

0 The Channel Transfer Error interrupt is disabled

1 The Channel Transfer Error interrupt is enabled

25.8.21 Channel Interrupt Enable Set

Name: CHINTENSET Offset: 0x4D Reset: 0x00 Property: PAC Write Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Channel Interrupt Enable Clear (CHINTENCLR) register. This register affects the DMA channel that is selected in the Channel ID register (CHID.ID). Bit 7 6 5 4 3 2 1 0 SUSP TCMPL TERR Access R/W R/W R/W Reset 0 0 0 Bit 2 – SUSP Channel Suspend Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Channel Suspend Interrupt Enable bit, which enables the Channel Suspend interrupt. Value Description Bit 1 – TCMPL Channel Transfer Complete Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Channel Transfer Complete Interrupt Enable bit, which enables the Channel Transfer Complete interrupt. Value Description

0 The Channel Transfer Complete interrupt is disabled

Bit 0 – TERR Channel Transfer Error Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Channel Transfer Error Interrupt Enable bit, which enables the Channel Transfer Error interrupt. Value Description DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 411

25.8.22 Channel Interrupt Flag Status and Clear

Name: CHINTFLAG Offset: 0x4E Reset: 0x00 Property: - This register affects the DMA channel that is selected in the Channel ID register (CHID.ID). Bit 7 6 5 4 3 2 1 0 SUSP TCMPL TERR Access R/W R/W R/W Reset 0 0 0 Bit 2 – SUSP Channel Suspend This flag is cleared by writing a '1' to it. This flag is set when a block transfer with suspend block action is completed, when a software suspend command is executed, when a suspend event is received or when an invalid descriptor is fetched by the DMA. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel Suspend Interrupt flag for the corresponding channel. For details on available software commands, refer to CHCTRLB.CMD. For details on available event input actions, refer to CHCTRLB.EVACT. For details on available block actions, refer to BTCTRL.BLOCKACT. Bit 1 – TCMPL Channel Transfer Complete This flag is cleared by writing a '1' to it. This flag is set when a block transfer is completed and the corresponding interrupt block action is enabled. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Transfer Complete Interrupt flag for the corresponding channel. Bit 0 – TERR Channel Transfer Error This flag is cleared by writing a '1' to it. This flag is set when a bus error is detected during a beat transfer or when the DMAC fetches an invalid descriptor. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Transfer Error Interrupt flag for the corresponding channel. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 412

25.8.23 Channel Status

Name: CHSTATUS Offset: 0x4F Reset: 0x00 Property: - This register affects the DMA channel that is selected in the Channel ID register (CHID.ID). Bit 7 6 5 4 3 2 1 0 FERR BUSY PEND Access R R R Reset 0 0 0 Bit 2 – FERR Channel Fetch Error This bit is cleared when a Software Resume command is executed. This bit is set when an invalid descriptor is fetched. Bit 1 – BUSY Channel Busy This bit is cleared when the channel trigger action is completed, when a bus error is detected or when the channel is disabled. This bit is set when the DMA channel starts a DMA transfer. Bit 0 – PEND Channel Pending This bit is cleared when the channel trigger action is started, when a bus error is detected or when the channel is disabled. For details on trigger action settings, refer to CHCTRLB.TRIGACT. This bit is set when a transfer is pending on the DMA channel, as soon as the transfer request is received. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 413

25.9 Register Summary - SRAM

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 BTCTRL 7:0 BLOCKACT[1:0] EVOSEL[1:0] VALID 15:8 STEPSIZE[2:0] STEPSEL DSTINC SRCINC BEATSIZE[1:0] 0x02 BTCNT 7:0 BTCNT[7:0] 15:8 BTCNT[15:8] 0x04 SRCADDR 7:0 SRCADDR[7:0] 15:8 SRCADDR[15:8] 23:16 SRCADDR[23:16] 31:24 SRCADDR[31:24] 0x08 DSTADDR 7:0 DSTADDR[7:0] 15:8 DSTADDR[15:8] 23:16 DSTADDR[23:16] 31:24 DSTADDR[31:24] 0x0C DESCADDR 7:0 DESCADDR[7:0] 15:8 DESCADDR[15:8] 23:16 DESCADDR[23:16] 31:24 DESCADDR[31:24]

25.10 Register Description - SRAM

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 25.5.8. Register Access Protection. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 414

25.10.1 Block Transfer Control

Name: BTCTRL Offset: 0x00 Reset: 0x0000 Property: - The BTCTRL register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 15 14 13 12 11 10 9 8 STEPSIZE[2:0] STEPSEL DSTINC SRCINC BEATSIZE[1:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BLOCKACT[1:0] EVOSEL[1:0] VALID Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bits 15:13 – STEPSIZE[2:0] Address Increment Step Size These bits select the address increment step size. The setting apply to source or destination address, depending on STEPSEL setting. Value Name Description 0x0 X1 Next ADDR = ADDR + (Beat size in byte) * 1 0x1 X2 Next ADDR = ADDR + (Beat size in byte) * 2 0x2 X4 Next ADDR = ADDR + (Beat size in byte) * 4 0x3 X8 Next ADDR = ADDR + (Beat size in byte) * 8 0x4 X16 Next ADDR = ADDR + (Beat size in byte) * 16 0x5 X32 Next ADDR = ADDR + (Beat size in byte) * 32 0x6 X64 Next ADDR = ADDR + (Beat size in byte) * 64 0x7 X128 Next ADDR = ADDR + (Beat size in byte) * 128 Bit 12 – STEPSEL Step Selection This bit selects if source or destination addresses are using the step size settings. Value Name Description 0x0 DST Step size settings apply to the destination address 0x1 SRC Step size settings apply to the source address Bit 11 – DSTINC Destination Address Increment Enable Writing a '0' to this bit will disable the destination address incrementation. The address will be kept fixed during the data transfer. Writing a '1' to this bit will enable the destination address incrementation. By default, the destination address is incremented by 1. If the STEPSEL bit is cleared, flexible step-size settings are available in the STEPSIZE register. Value Description

0 The Destination Address Increment is disabled

1 The Destination Address Increment is enabled

Bit 10 – SRCINC Source Address Increment Enable Writing a '0' to this bit will disable the source address incrementation. The address will be kept fixed during the data transfer. Writing a '1' to this bit will enable the source address incrementation. By default, the source address is incremented by 1. If the STEPSEL bit is set, flexible step-size settings are available in the STEPSIZE register. Value Description

0 The Source Address Increment is disabled

1 The Source Address Increment is enabled

Bits 9:8 – BEATSIZE[1:0] Beat Size These bits define the size of one beat. A beat is the size of one data transfer bus access, and the setting apply to both read and write accesses. Value Name Description 0x0 BYTE 8-bit bus transfer 0x1 HWORD 16-bit bus transfer 0x2 WORD 32-bit bus transfer other Reserved Bits 4:3 – BLOCKACT[1:0] Block Action These bits define what actions the DMAC should take after a block transfer has completed. BLOCKACT[1:0] Name Description 0x0 NOACT Channel will be disabled if it is the last block transfer in the transaction 0x1 INT Channel will be disabled if it is the last block transfer in the transaction and block interrupt 0x2 SUSPEND Channel suspend operation is completed 0x3 BOTH Both channel suspend operation and block interrupt Bits 2:1 – EVOSEL[1:0] Event Output Selection These bits define the event output selection. EVOSEL[1:0] Name Description 0x0 DISABLE Event generation disabled 0x1 BLOCK Event strobe when block transfer complete 0x2 Reserved 0x3 BEAT Event strobe when beat transfer complete Bit 0 – VALID Descriptor Valid Writing a '0' to this bit in the Descriptor or Write-Back memory will suspend the DMA channel operation when fetching the corresponding descriptor. The bit is automatically cleared in the Write-Back memory section when channel is aborted, when an error is detected during the block transfer, or when the block transfer is completed. Value Description

0 The descriptor is not valid

1 The descriptor is valid

25.10.2 Block Transfer Count

Name: BTCNT Offset: 0x02 Property: - The BTCNT register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 15 14 13 12 11 10 9 8 BTCNT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BTCNT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – BTCNT[15:0] Block Transfer Count This bit group holds the 16-bit block transfer count. During a transfer, the internal counter value is decremented by one after each beat transfer. The internal counter is written to the corresponding write-back memory section for the DMA channel when the DMA channel loses priority, is suspended or gets disabled. The DMA channel can be disabled by a complete transfer, a transfer error or by software. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 417

25.10.3 Block Transfer Source Address

Name: SRCADDR Offset: 0x04 Property: - The SRCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 31 30 29 28 27 26 25 24 SRCADDR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SRCADDR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SRCADDR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SRCADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – SRCADDR[31:0] Transfer Source Address This bit field holds the block transfer source address. When source address incrementation is disabled (BTCTRL.SRCINC = 0), SRCADDR corresponds to the last beat transfer address in the block transfer. When source address incrementation is enabled (BTCTRL.SRCINC = 1), SRCADDR is calculated as follows: If BTCTRL.STEPSEL = 1: SRCADDR = SRCADDR ST A RT + BTC NT ⋅ B E A TSI ZE + 1 ⋅ 2STEPSIZE If BTCTRL.STEPSEL= 0: SRCADDR = SRCADDR ST A RT + BTC NT ⋅ BE A TSI ZE + 1

SRCADDR START is the source address of the first beat transfer in the block transfer.
BTCNT is the initial number of beats remaining in the block transfer.
BEATSIZE is the configured number of bytes in a beat.
STEPSIZE is the configured number of beats for each incrementation. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 418

25.10.4 Block Transfer Destination Address

Name: DSTADDR Offset: 0x08 Reset: 0x00000000 Property: - The DSTADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 31 30 29 28 27 26 25 24 DSTADDR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DSTADDR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DSTADDR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DSTADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DSTADDR[31:0] Transfer Destination Address This bit field holds the block transfer destination address. When destination address incrementation is disabled (BTCTRL.DSTINC = 0), DSTADDR corresponds to the last beat transfer address in the block transfer. When destination address incrementation is enabled (BTCTRL.DSTINC = 1), DSTADDR is calculated as follows: If BTCTRL.STEPSEL = 1: DS T A DDR = D ST A DDR S T AR T + B TC NT • BE AT SI ZE + 1 If BTCTRL.STEPSEL = 0: DS T A DDR = D ST A DDR S T AR T + B TC NT • BE A TSI ZE + 1 • 2 STE PSI ZE

DSTADDR START is the destination address of the first beat transfer in the block transfer.
BTCNT is the initial number of beats remaining in the block transfer.
BEATSIZE is the configured number of bytes in a beat.
STEPSIZE is the configured number of beats for each incrementation. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 419

25.10.5 Next Descriptor Address

Name: DESCADDR Offset: 0x0C Reset: 0x00000000 Property: - The DESCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 31 30 29 28 27 26 25 24 DESCADDR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DESCADDR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DESCADDR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DESCADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DESCADDR[31:0] Next Descriptor Address This bit group holds the SRAM address of the next descriptor. The value must be 64-bit aligned. If the value of this SRAM register is 0x00000000, the transaction will be terminated when the DMAC tries to load the next transfer descriptor. SAM L22 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 420

EIC – External Interrupt Controller

26.1 Overview

The External Interrupt Controller (EIC) allows external pins to be configured as interrupt lines. Each interrupt line can be individually masked and can generate an interrupt on rising, falling, or both edges, or on high or low levels. Each external pin has a configurable filter to remove spikes. Each external pin can also be configured to be asynchronous in order to wake up the device from sleep modes where all clocks have been disabled. External pins can also generate an event. A separate non-maskable interrupt (NMI) is also supported. It has properties similar to the other external interrupts, but is connected to the NMI request of the CPU, enabling it to interrupt any other interrupt mode.

26.2 Features

Up to 16 external pins, plus one non-maskable pin
Dedicated, individually maskable interrupt for each pin
Interrupt on rising, falling, or both edges
Synchronous or asynchronous edge detection mode
Interrupt on high or low levels
Asynchronous interrupts for sleep modes without clock
Filtering of external pins
Event generation

26.3 Block Diagram

Figure 26-1. EIC Block Diagram Filter Edge/Level Detection Interrupt Wake Event FILTENx EXTINTx intreq_extint inwake_extint evt_extint Filter Edge/Level Detection Interrupt Wake NMIFILTEN NMISENSE[2:0] NMI intreq_nmi inwake_nmi SENSEx[2:0]

26.4 Signal Description

Signal Name Type Description EXTINT[15..0] Digital Input External interrupt pin SAM L22 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 421

Signal Name Type Description NMI Digital Input Non-maskable interrupt pin One signal can be mapped on several pins. References: I/O Multiplexing and Considerations

26.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

26.5.1 I/O Lines

Using the EIC’s I/O lines requires the I/O pins to be configured. References: 28. PORT - I/O Pin Controller

26.5.2 Power Management

All interrupts are available in all sleep modes, but the EIC can be configured to automatically mask some interrupts in order to prevent device wake-up. The EIC will continue to operate in any sleep mode where the selected source clock is running. The EIC’s interrupts can be used to wake up the device from sleep modes. Events connected to the Event System can trigger other operations in the system without exiting sleep modes. References: PM - Power Manager

26.5.3 Clocks

The EIC bus clock (CLK_EIC_APB) can be enabled and disabled by the Main Clock Controller, the default state of CLK_EIC_APB can be found in the Peripheral Clock Masking section. Some optional functions need a peripheral clock, which can either be a generic clock (GCLK_EIC, for wider frequency selection) or a Ultra Low Power 32.768 kHz clock (CLK_ULP32K, for highest power efficiency). One of the clock sources must be configured and enabled before using the peripheral: GCLK_EIC is configured and enabled in the Generic Clock Controller. CLK_ULP32K is provided by the internal ultra-low-power (OSCULP32K) oscillator in the OSC32KCTRL module. Both GCLK_EIC and CLK_ULP32K are asynchronous to the user interface clock (CLK_EIC_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to Synchronization for further details. References: 16. MCLK – Main Clock 16.6.2.6. Peripheral Clock Masking 15. GCLK - Generic Clock Controller 21. OSC32KCTRL – 32.768 kHz Oscillators Controller

26.5.4 DMA

26.5.5 Interrupts

There are two interrupt request lines, one for the external interrupts (EXTINT) and one for non-maskable interrupt (NMI). The EXTINT interrupt request line is connected to the interrupt controller. Using the EIC interrupt requires the interrupt controller to be configured first. The NMI interrupt request line is also connected to the interrupt controller, but does not require the interrupt to be configured. References: Nested Vector Interrupt Controller

26.5.6 Events

The events are connected to the Event System. Using the events requires the Event System to be configured first. References: 29. EVSYS – Event System

26.5.7 Debug Operation

When the CPU is halted in debug mode, the EIC continues normal operation. If the EIC is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging.

26.5.8 Register Access Protection

All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Interrupt Flag Status and Clear register (INTFLAG)
Non-Maskable Interrupt Flag Status and Clear register (NMIFLAG) Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger. References: PAC

26.5.9 Analog Connections

Not applicable.

26.6 Functional Description

26.6.1 Principle of Operation

The EIC detects edge or level condition to generate interrupts to the CPU interrupt controller or events to the Event System. Each external interrupt pin (EXTINT) can be filtered using majority vote filtering, clocked by GCLK_EIC or by CLK_ULP32K.

26.6.2 Basic Operation

26.6.2.1 Initialization

The EIC must be initialized in the following order: 1. Enable CLK_EIC_APB 2. If required, configure the NMI by writing the Non-Maskable Interrupt Control register ( NMICTRL) 3. When the NMI is used or synchronous edge detection or filtering are required, enable GCLK_EIC or CLK_ULP32K. SAM L22 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 423

GCLK_EIC is used when a frequency higher than 32.768 kHz is required for filtering, CLK_ULP32K is recommended when power consumption is the priority. For CLK_ULP32K write a '1' to the Clock Selection bit in the Control A register (CTRLA.CKSEL). Optionally, enable the asynchronous mode. 4. Configure the EIC input sense and filtering by writing the Configuration n register ( CONFIGn). 5. Enable the EIC. The following bits are enable-protected, meaning that it can only be written when the EIC is disabled (CTRLA.ENABLE=0):

Clock Selection bit in Control A register ( CTRLA.CKSEL) The following registers are enable-protected:
Event Control register ( EVCTRL)
Configuration n register ( CONFIGn)
External Interrupt Asynchronous Mode register ( ASYNCH) Enable-protected bits in the CTRLA register can be written at the same time when setting CTRLA.ENABLE to '1', but not at the same time as CTRLA.ENABLE is being cleared. Enable-protection is denoted by the "Enable-Protected" property in the register description.

26.6.2.2 Enabling, Disabling, and Resetting

The EIC is enabled by writing a '1' the Enable bit in the Control A register (CTRLA.ENABLE). The EIC is disabled by writing CTRLA.ENABLE to '0'. The EIC is reset by setting the Software Reset bit in the Control register (CTRLA.SWRST). All registers in the EIC will be reset to their initial state, and the EIC will be disabled. Refer to the CTRLA register description for details.

26.6.3 External Pin Processing

Each external pin can be configured to generate an interrupt/event on edge detection (rising, falling or both edges) or level detection (high or low). The sense of external interrupt pins is configured by writing the Input Sense x bits in the Config n register (CONFIGn.SENSEx). The corresponding interrupt flag (INTFLAG.EXTINT[x]) in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition is met. When the interrupt flag has been cleared in edge-sensitive mode, INTFLAG.EXTINT[x] will only be set if a new interrupt condition is met. In level-sensitive mode, when interrupt has been cleared, INTFLAG.EXTINT[x] will be set immediately if the EXTINTx pin still matches the interrupt condition. Each external pin can be filtered by a majority vote filtering, clocked by GCLK_EIC or CLK_ULP32K. Filtering is enabled if bit Filter Enable x in the Configuration n register (CONFIGn.FILTENx) is written to '1'. The majority vote filter samples the external pin three times with GCLK_EIC or CLK_ULP32K and outputs the value when two or more samples are equal. Table 26-1. Majority Vote Filter Samples [0, 1, 2] Filter Output [0,0,0] 0 [0,0,1] 0 [0,1,0] 0 [0,1,1] 1 [1,0,0] 0 [1,0,1] 1 [1,1,0] 1 [1,1,1] 1 SAM L22 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 424

When an external interrupt is configured for level detection and when filtering is disabled, detection is done asynchronously. Asynchronuous detection does not require GCLK_EIC or CLK_ULP32K, but interrupt and events can still be generated. If filtering or edge detection is enabled, the EIC automatically requests GCLK_EIC or CLK_ULP32K to operate. The selection between these two clocks is done by writing the Clock Selection bits in the Control A register (CTRLA.CKSEL). GCLK_EIC must be enabled in the GCLK module. Figure 26-2. Interrupt Detections intreq_extint[x] (edge detection / filter) intreq_extint[x] (edge detection / no filter) intreq_extint[x] (level detection / filter) intreq_extint[x] (level detection / no filter) EXTINTx CLK_EIC_APB GCLK_EIC clear INTFLAG.EXTINT[x] No interrupt No interrupt The detection delay depends on the detection mode. Table 26-2. Interrupt Latency Detection mode Latency (worst case) Level without filter Five CLK_EIC_APB periods Level with filter Four GCLK_EIC/CLK_ULP32K periods + five CLK_EIC_APB periods Edge without filter Four GCLK_EIC/CLK_ULP32K periods + five CLK_EIC_APB periods Edge with filter Six GCLK_EIC/CLK_ULP32K periods + five CLK_EIC_APB periods References: GCLK

26.6.4 Additional Features

26.6.4.1 Non-Maskable Interrupt (NMI)

The non-maskable interrupt pin can also generate an interrupt on edge or level detection, but it is configured with the dedicated NMI Control register (NMICTRL). To select the sense for NMI, write to the NMISENSE bit group in the NMI Control register (NMICTRL.NMISENSE). NMI filtering is enabled by writing a '1' to the NMI Filter Enable bit (NMICTRL.NMIFILTEN). If edge detection or filtering is required, enable GCLK_EIC or CLK_ULP32K. NMI detection is enabled only by the NMICTRL.NMISENSE value, and the EIC is not required to be enabled. After reset, NMI is configured to no detection mode. When an NMI is detected, the non-maskable interrupt flag in the NMI Flag Status and Clear register is set (NMIFLAG.NMI). NMI interrupt generation is always enabled, and NMIFLAG.NMI generates an interrupt request when set.

26.6.4.2 Asynchronous Edge Detection Mode (No Debouncing)

The EXTINT edge detection can be operated synchronously or asynchronously, selected by the Asynchronous Control Mode bit for external pin x in the External Interrupt Asynchronous Mode register (ASYNCH.ASYNCH[x]). The EIC edge detection is operated synchronously when the Asynchronous Control Mode bit (ASYNCH.ASYNCH[x]) is '0' (default value). It is operated asynchronously when ASYNCH.ASYNCH[x] is written to '1'. SAM L22 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 425

In Synchronous Edge Detection Mode, the external interrupt (EXTINT) or the non-maskable interrupt (NMI) pins are sampled using the EIC clock as defined by the Clock Selection bit in the Control A register (CTRLA.CKSEL). The External Interrupt flag (INTFLAG.EXTINT[x]) or Non-Maskable Interrupt flag (NMIFLAG.NMI) is set when the last sampled state of the pin differs from the previously sampled state. In this mode, the EIC clock is required. The Synchronous Edge Detection Mode can be used in Idle sleep mode. In Asynchronous Edge Detection Mode, the external interrupt (EXTINT) pins or the non-maskable interrupt (NMI) pins set the External Interrupt flag or Non-Maskable Interrupt flag (INTFLAG.EXTINT[x] or NMIFLAG) directly. In this mode, the EIC clock is not requested. The asynchronous edge detection mode can be used in all sleep modes.

26.6.5 DMA Operation

Not applicable.

26.6.6 Interrupts

The EIC has the following interrupt sources: Each interrupt source has an associated interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when an interrupt condition occurs (NMIFLAG for NMI). Each interrupt, except NMI, can be individually enabled by setting the corresponding bit in the Interrupt Enable Set register (INTENSET=1), and disabled by setting the corresponding bit in the Interrupt Enable Clear register (INTENCLR=1). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the EIC is reset. See the INTFLAG register for details on how to clear interrupt flags. The EIC has one common interrupt request line for all the interrupt sources, and one interrupt request line for the NMI. The user must read the INTFLAG (or NMIFLAG) register to determine which interrupt condition is present. Note: Interrupts must be globally enabled for interrupt requests to be generated. Note: If an external interrupts (EXTINT) is common on two or more I/O pins, only one will be active (the first one programmed). References: I/O Multiplexing and Considerations

26.6.7 Events

The EIC can generate the following output events:

External event from pin (EXTINTx). Setting an Event Output Control register (EVCTRL.EXTINTEO) enables the corresponding output event. Clearing this bit disables the corresponding output event. Refer to Event System for details on configuring the Event System. When the condition on pin EXTINTx matches the configuration in the CONFIGn register, the corresponding event is generated, if enabled. References: 29. EVSYS – Event System

26.6.8 Sleep Mode Operation

In sleep modes, an EXTINTx pin can wake up the device if the corresponding condition matches the configuration in CONFIGn register, and the corresponding bit in the Interrupt Enable Set register (INTENSET) is written to '1'. SAM L22 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 426

Figure 26-3. Wake-up Operation Example (High-Level Detection, No Filter, Interrupt Enable Set) CLK_EIC_APB EXTINTx intwake_extint[x] intreq_extint[x] clear INTFLAG.EXTINT[x]wake from sleep mode

26.6.9 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written:

Software Reset bit in control register ( CTRLA.SWRST)
Enable bit in control register ( CTRLA.ENABLE) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. SAM L22 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 427

26.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 CKSEL ENABLE SWRST 0x01 NMICTRL 7:0 NMIASYNCH NMIFILTEN NMISENSE[2:0] 0x02 NMIFLAG 7:0 NMI 15:8 0x04 SYNCBUSY 7:0 ENABLE SWRST 15:8 23:16 31:24 0x08 EVCTRL 7:0 EXTINTEO[7:0] 15:8 EXTINTEO[15:8] 23:16 31:24 0x0C INTENCLR 7:0 EXTINT[7:0] 15:8 EXTINT[15:8] 23:16 31:24 0x10 INTENSET 7:0 EXTINT[7:0] 15:8 EXTINT[15:8] 23:16 31:24 0x14 INTFLAG 7:0 EXTINT[7:0] 15:8 EXTINT[15:8] 23:16 31:24 0x18 ASYNCH 7:0 ASYNCH[7:0] 15:8 ASYNCH[15:8] 23:16 31:24 0x1C CONFIG0 7:0 FILTEN1 SENSE1[2:0] FILTEN0 SENSE0[2:0] 15:8 FILTEN3 SENSE3[2:0] FILTEN2 SENSE2[2:0] 23:16 FILTEN5 SENSE5[2:0] FILTEN4 SENSE4[2:0] 31:24 FILTEN7 SENSE7[2:0] FILTEN6 SENSE6[2:0] 0x20 CONFIG1 7:0 FILTEN1 SENSE1[2:0] FILTEN0 SENSE0[2:0] 15:8 FILTEN3 SENSE3[2:0] FILTEN2 SENSE2[2:0] 23:16 FILTEN5 SENSE5[2:0] FILTEN4 SENSE4[2:0] 31:24 FILTEN7 SENSE7[2:0] FILTEN6 SENSE6[2:0]

26.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read- Synchronized" and/or "Write-Synchronized" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. SAM L22 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 428

26.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CKSEL ENABLE SWRST Access R/W R/W W Reset 0 0 0 Bit 4 – CKSEL Clock Selection The EIC can be clocked either by GCLK_EIC (when a frequency higher than 32KHz is required for filtering) or by CLK_ULP32K (when power consumption is the priority). This bit is not Write-Synchronized. Value Description 0 The EIC is clocked by GCLK_EIC. 1 The EIC is clocked by CLK_ULP32K. Bit 1 – ENABLE Enable Due to synchronization there is a delay between writing to CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register will be set (SYNCBUSY.ENABLE=1). SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not Enable-Protected. Value Description 0 The EIC is disabled. 1 The EIC is enabled. Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the EIC to their initial state, and the EIC will be disabled. Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the Reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the Reset is complete. This bit is not Enable-Protected. Value Description 0 There is no ongoing reset operation. 1 The reset operation is ongoing. SAM L22 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 429

26.8.2 Non-Maskable Interrupt Control

Name: NMICTRL Offset: 0x01 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 NMIASYNCH NMIFILTEN NMISENSE[2:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 4 – NMIASYNCH Asynchronous Edge Detection Mode The NMI edge detection can be operated synchronously or asynchronously to the EIC clock. Value Description 0 The NMI edge detection is synchronously operated. 1 The NMI edge detection is asynchronously operated. Bit 3 – NMIFILTEN Non-Maskable Interrupt Filter Enable Value Description 0 NMI filter is disabled. 1 NMI filter is enabled. Bits 2:0 – NMISENSE[2:0] Non-Maskable Interrupt Sense Configuration These bits define on which edge or level the NMI triggers. Value Name Description 0x0 NONE No detection 0x1 RISE Rising-edge detection 0x2 FALL Falling-edge detection 0x3 BOTH Both-edge detection 0x4 HIGH High-level detection 0x5 LOW Low-level detection 0x6 - 0x7 - Reserved SAM L22 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 430

26.8.3 Non-Maskable Interrupt Flag Status and Clear

Name: NMIFLAG Offset: 0x02 Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 NMI Access R/W Reset 0 Bit 0 – NMI Non-Maskable Interrupt This flag is cleared by writing a '1' to it. This flag is set when the NMI pin matches the NMI sense configuration, and will generate an interrupt request. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the non-maskable interrupt flag. SAM L22 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 431

26.8.4 Synchronization Busy

Name: SYNCBUSY Offset: 0x04 Reset: 0x00000000 Property: – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ENABLE SWRST Access R R Reset 0 0 Bit 1 – ENABLE Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.ENABLE bit is complete. 1 Write synchronization for CTRLA.ENABLE bit is ongoing. Bit 0 – SWRST Software Reset Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.SWRST bit is complete. 1 Write synchronization for CTRLA.SWRST bit is ongoing. SAM L22 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 432

26.8.5 Event Control

Name: EVCTRL Offset: 0x08 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 EXTINTEO[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EXTINTEO[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – EXTINTEO[15:0] External Interrupt Event Output Enable The bit x of EXTINTEO enables the event associated with the EXTINTx pin. Value Description 0 Event from pin EXTINTx is disabled.

1 Event from pin EXTINTx is enabled and will be generated when EXTINTx pin matches the external

26.8.6 Interrupt Enable Clear

Name: INTENCLR Offset: 0x0C Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 EXTINT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EXTINT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – EXTINT[15:0] External Interrupt Enable The bit x of EXTINT enables the interrupt associated with the EXTINTx pin. Writing a '0' to bit x has no effect. Writing a '1' to bit x will clear the External Interrupt x Enable bit, which disables the external interrupt EXTINTx. Value Description 0 The external interrupt x is disabled. 1 The external interrupt x is enabled. SAM L22 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 434

26.8.7 Interrupt Enable Set

Name: INTENSET Offset: 0x10 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 EXTINT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EXTINT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – EXTINT[15:0] External Interrupt Enable The bit x of EXTINT enables the interrupt associated with the EXTINTx pin. Writing a '0' to bit x has no effect. Writing a '1' to bit x will set the External Interrupt x Enable bit, which enables the external interrupt EXTINTx. Value Description 0 The external interrupt x is disabled. 1 The external interrupt x is enabled. SAM L22 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 435

26.8.8 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x14 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 EXTINT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EXTINT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – EXTINT[15:0] External Interrupt The flag bit x is cleared by writing a '1' to it. This flag is set when EXTINTx pin matches the external interrupt sense configuration and will generate an interrupt request if INTENCLR/SET.EXTINT[x] is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the External Interrupt x flag. SAM L22 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 436

26.8.9 External Interrupt Asynchronous Mode

Name: ASYNCH Offset: 0x18 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 ASYNCH[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ASYNCH[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – ASYNCH[15:0] Asynchronous Edge Detection Mode The bit x of ASYNCH set the Asynchronous Edge Detection Mode for the interrupt associated with the EXTINTx pin. Value Description 0 The EXTINT x edge detection is synchronously operated. 1 The EXTINT x edge detection is asynchronously operated. SAM L22 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 437

26.8.10 External Interrupt Sense Configuration n

Name: CONFIGn Offset: 0x1C + n*0x04 [n=0..1] Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 FILTEN7 SENSE7[2:0] FILTEN6 SENSE6[2:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 FILTEN5 SENSE5[2:0] FILTEN4 SENSE4[2:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 FILTEN3 SENSE3[2:0] FILTEN2 SENSE2[2:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FILTEN1 SENSE1[2:0] FILTEN0 SENSE0[2:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 3, 7, 11, 15, 19, 23, 27, 31 – FILTENx Filter Enable x [x = 0..7] Note: The filter must be disabled if the asynchronous detection is enabled. Value Description 0 Filter is disabled for EXTINT[n*8+x] input. 1 Filter is enabled for EXTINT[n*8+x] input. Bits 0:2, 4:6, 8:10, 12:14, 16:18, 20:22, 24:26, 28:30 – SENSEx Input Sense Configuration x [x = 0..7] These bits define on which edge or level the interrupt or event for EXTINT[n*8+x] will be generated. Value Name Description 0x0 NONE No detection 0x1 RISE Rising-edge detection 0x2 FALL Falling-edge detection 0x3 BOTH Both-edge detection 0x4 HIGH High-level detection 0x5 LOW Low-level detection 0x6 - 0x7 - Reserved SAM L22 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 438

NVMCTRL – Non-Volatile Memory Controller

27.1 Overview

Non-Volatile Memory (NVM) is a reprogrammable Flash memory that retains program and data storage even with power off. It embeds a main array and a separate smaller array intended for EEPROM emulation (RWWEE, standing for Read (the main array) While Write (the EEPROM)) that can be programmed while reading the main array. The NVM Controller (NVMCTRL) connects to the AHB and APB bus interfaces for system access to the NVM block. The AHB interface is used for reads and writes to the NVM block, while the APB interface is used for commands and configuration.

27.2 Features

32-bit AHB interface for reads and writes
Read While Write EEPROM emulation area
All NVM sections are memory mapped to the AHB, including calibration and system configuration
32-bit APB interface for commands and control
Programmable wait states for read optimization
16 regions can be individually protected or unprotected
Additional protection for boot loader
Supports device protection through a security bit
Interface to Power Manager for power-down of Flash blocks in sleep modes
Can optionally wake up on exit from sleep or on first access
Direct-mapped cache Note: A register with property "Enable-Protected" may contain bits that are not enable-protected.

27.3 Block Diagram

Figure 27-1. NVMCTRL Block Diagram NVMCTRL Cache Command and Control NVM Interface RWWEE array NVM Block Main array Calibration and Auxiliary Space AHB APB DD-M2 SAM L22 Family NVMCTRL – Non-Volatile Memory Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 439

27.4 Signal Description

Not applicable.

27.5 Product Dependencies

In order to use this module, other parts of the system must be configured correctly, as described below.

27.5.1 Power Management

The NVMCTRL will continue to operate in any Sleep mode where the selected source clock is running. The NVMCTRL interrupts can be used to wake up the device from sleep modes. The Power Manager will automatically put the NVM block into a low-power state when entering Sleep mode. This is based on the Control B register (CTRLB) SLEEPPRM bit setting. Refer to the CTRLB.SLEEPPRM register description for more details. References: PM-Power Manager

27.5.2 Clocks

Two synchronous clocks are used by the NVMCTRL. One is provided by the AHB bus (CLK_NVMCTRL_AHB) and the other is provided by the APB bus (CLK_NVMCTRL_APB). For higher system frequencies, a programmable number of wait states can be used to optimize performance. When changing the AHB bus frequency, the user must ensure that the NVM Controller is configured with the proper number of wait states. Refer to the Electrical Characteristics for the exact number of wait states to be used for a particular frequency range. References:

27.5.3 Interrupts

The NVM Controller interrupt request line is connected to the interrupt controller. Using the NVMCTRL interrupt requires the interrupt controller to be programmed first.

27.5.4 Debug Operation

When an external debugger forces the CPU into debug mode, the peripheral continues normal operation. Access to the NVM block can be protected by the security bit. In this case, the NVM block will not be accessible. See the section on the NVMCTRL 27.6.6. Security Bit for details.

27.5.5 Register Access Protection

All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the following registers:

Interrupt Flag Status and Clear register (INTFLAG)
Status register (STATUS) Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description. PAC Write-Protection does not apply to accesses through an external debugger. Refer to the PAC - Peripheral Access Controller References: PAC-Peripheral Access Controller

27.5.6 Analog Connections

27.6 Functional Description

27.6.1 Principle of Operation

The NVM Controller is a client on the AHB and APB buses. It responds to commands, read requests and write requests, based on user configuration.

27.6.1.1 Initialization

After power up, the NVM Controller goes through a power-up sequence. During this time, access to the NVM Controller from the AHB bus is halted. Upon power-up completion, the NVM Controller is operational without any need for user configuration.

27.6.2 Memory Organization

Refer to the Physical Memory Map for memory sizes and addresses for each device. The NVM is organized into rows, where each row contains four pages, as shown in the NVM Row Organization figure. The NVM has a row-erase granularity, while the write granularity is by page. In other words, a single row erase will erase all four pages in the row, while four write operations are used to write the complete row. Figure 27-2. NVM Row Organization Page (n*4) + 3 Page (n*4) + 2 Page (n*4) + 1 Page (n*4) + 0 Row n The NVM block contains a calibration and auxiliary space , a RWWEE section, and main array that are memory mapped. Refer to the NVM Organization figure below for details. The calibration and auxiliary space contains factory calibration and system configuration information. These spaces can be read from the AHB bus in the same way as the main NVM main address space. In addition, a boot loader section can be allocated at the beginning of the main array, and an EEPROM Emulation section can be allocated at the end of the NVM main address space. Figure 27-3. NVM Memory Organization Calibration and Auxiliary Space RWWEE Address Space NVM Main Address Space NVM Base Address + 0x00800000 NVM Base Address + 0x00400000 NVM Base Address + NVM Size NVM Base Address SAM L22 Family NVMCTRL – Non-Volatile Memory Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 441

The lower rows in the NVM main address space can be allocated as a boot loader section by using the NVM User Row BOOTPROT fuses, and the upper rows can be allocated to EEPROM Emulation section by using the NVM User Row EEPROM fuses, as shown in the following figure. The boot loader section is protected by the Lock bit(s) corresponding to this address space and by the BOOTPROT[2:0] fuse. The EEPROM Emulation rows can be written regardless of the region lock status. The number of rows protected by BOOTPROT is given in Boot Loader Size, the number of rows allocated to the EEPROM Emulation area are given in EEPROM Size. Figure 27-4. EEPROM and Boot Loader Allocation References: Physical Memory Map

27.6.3 Region Lock Bits

The NVM block is grouped into 16 equally sized regions. The region size is dependent on the Flash memory size, and is given in the table below. Each region has a dedicated lock bit preventing writing and erasing pages in the region. After production, all regions will be unlocked. Table 27-1. Region Size Memory Size [KB] Region Size [KB] 256 16 128 8 64 4 32 2 To lock or unlock a region, the Lock Region and Unlock Region commands are provided. Writing one of these commands will temporarily lock/unlock the region containing the address loaded in the ADDR register. ADDR can be written by software, or the automatically loaded value from a write operation can be used. The new setting will stay in effect until the next Reset, or until the setting is changed again using the Lock and Unlock commands. The current status of the lock can be determined by reading the LOCK register. SAM L22 Family NVMCTRL – Non-Volatile Memory Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 442

To change the default lock/unlock setting for a region, the user configuration section of the auxiliary space must be written using the Write Auxiliary Page command. Writing to the auxiliary space will take effect after the next Reset. Therefore, a boot of the device is needed for changes in the lock/unlock setting to take effect. Refer to the Physical Memory Map for calibration and auxiliary space address mapping. References: Physical Memory Map

27.6.4 Command and Data Interface

The NVM Controller is addressable from the APB bus, while the NVM main address space is addressable from the AHB bus. Read and automatic page write operations are performed by addressing the NVM main address space or the RWWEE address space directly, while other operations such as manual page writes and row erases must be performed by issuing commands through the NVM Controller. To issue a command, the CTRLA.CMD bits must be written along with the CTRLA.CMDEX value. When a command is issued, INTFLAG.READY will be cleared until the command has completed. Any commands written while INTFLAG.READY is low will be ignored. Read the CTRLA register description for more details. The CTRLB register must be used to control the power reduction mode, read wait states, and the write mode.

27.6.4.1 NVM Read

Reading from the NVM main address space is performed via the AHB bus by addressing the NVM main address space or auxiliary address space directly. Read data is available after the configured number of read wait states (CTRLB.RWS) set in the NVM Controller. The number of cycles data are delayed to the AHB bus is determined by the read wait states. Examples of using zero and one wait states are shown in the following figure. Reading the NVM main address space while a programming or erase operation is ongoing on the NVM main array results in an AHB bus stall until the end of the operation. Reading the NVM main array does not stall the bus when the RWWEE array is being programmed or erased. Figure 27-5. Read Wait State Examples

0 Wait States

1 Wait States

27.6.4.2 RWWEE Read

Reading from the RWWEE address space is performed via the AHB bus by addressing the RWWEE address space Read timings are similar to regular NVM read timings when access size is Byte or half-Word. The AHB data phase is twice as long in case of full-Word-size access. SAM L22 Family NVMCTRL – Non-Volatile Memory Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 443

It is not possible to read the RWWEE area while the NVM main array is being written or erased, whereas the RWWEE area can be written or erased while the main array is being read. The RWWEE address space is not cached, therefore it is recommended to limit access to this area for performance and power consumption considerations.

27.6.4.3 NVM Write

The NVM Controller requires that an erase must be done before programming. The entire NVM main address space and the RWWEE address space can be erased by a debugger Chip Erase command. Alternatively, rows can be individually erased by the Erase Row command or the RWWEE Erase Row command to erase the NVM main address space or the RWWEE address space, respectively. After programming the NVM main array, the region that the page resides in can be locked to prevent spurious write or erase sequences. Locking is performed on a per-region basis, and so, locking a region will lock all pages inside the region. Data to be written to the NVM block are first written to and stored in an internal buffer called the page buffer. The page buffer contains the same number of bytes as an NVM page. Writes to the page buffer must be 16 or 32 bits. 8-bit writes to the page buffer are not allowed and will cause a system exception. Both the NVM main array and the RWWEE array share the same page buffer. Writing to the NVM block via the AHB bus is performed by a load operation to the page buffer. For each AHB bus write, the address is stored in the ADDR register. After the page buffer has been loaded with the required number of bytes, the page can be written to the NVM main array or the RWWEE array by setting CTRLA.CMD to 'Write Page' or 'RWWEE Write Page', respectively, and setting the key value to CMDEX. The LOAD bit in the STATUS register indicates whether the page buffer has been loaded or not. Before writing the page to memory, the accessed row must be erased. Automatic page writes are enabled by writing the manual write bit to zero (CTRLB.MANW=0). This will trigger a write operation to the page addressed by ADDR when the last location of the page is written. Because the address is automatically stored in ADDR during the I/O bus write operation, the last given address will be present in the ADDR register. There is no need to load the ADDR register manually, unless a different page in memory is to be written. The row to be written to must be erased before the write command is given.

Write to the page buffer by addressing the NVM main address space directly
Write the page buffer to memory: CTRL.CMD='Write Page' and CMDEX
The READY bit in the INTFLAG register will be low while programming is in progress, and access through the AHB will be stalled The row to be written to must be erased before the last write to the page buffer is performed. Note that partially written pages must be written with a manual write.
Write to the page buffer by addressing the NVM main address space directly. When the last location in the page buffer is written, the page is automatically written to NVM main address space.
INTFLAG.READY will be zero while programming is in progress and access through the AHB will be stalled.

27.6.4.4 Page Buffer Clear

The page buffer is automatically set to all '1' after a page write is performed. If a partial page has been written and it is desired to clear the contents of the page buffer, the Page Buffer Clear command can be used.

27.6.4.5 Erase Row

Before a page can be written, the row containing that page must be erased. The Erase Row command can be used to erase the desired row in the NVM main address space. The RWWEE Erase Row can be used to erase the desired row in the RWWEE array. Erasing the row sets all bits to '1'. If the row resides in a region that is locked, the erase will not be performed and the Lock Error bit in the Status register (STATUS.LOCKE) will be set. SAM L22 Family NVMCTRL – Non-Volatile Memory Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 444

Write the address of the row to erase to ADDR. Any address within the row can be used.
Issue an Erase Row command. Note: The NVM Address bit field in the Address register (ADDR.ADDR) uses 16-bit addressing.

27.6.4.6 Lock and Unlock Region

These commands are used to lock and unlock regions as detailed in section 27.6.3. Region Lock Bits.

27.6.4.7 Set and Clear Power Reduction Mode

The NVM Controller and block can be taken in and out of power reduction mode through the Set and Clear Power Reduction Mode commands. When the NVM Controller and block are in power reduction mode, the Power Reduction Mode bit in the Status register (STATUS.PRM) is set.

27.6.5 NVM User Configuration

The NVM user configuration resides in the auxiliary space. Refer to the Physical Memory Map of the device for calibration and auxiliary space address mapping. See NVM User Row Mapping for more information. The bootloader resides in the main array starting at offset zero. The allocated boot loader section is write-protected. Table 27-2. Boot Loader Size BOOTPROT [2:0] Rows Protected by BOOTPROT Boot Loader Size in Bytes 0x7(1) None 0 0x6 2 512 0x5 4 1024 0x4 8 2048 0x3 16 4096 0x2 32 8192 0x1 64 16384 0x0 128 32768 Note: 1. Default value is 0x7. The EEPROM[2:0] bits indicate the EEPROM size, see the table below. The EEPROM resides in the upper rows of the NVM main address space and is writable, regardless of the region lock status. Table 27-3. EEPROM Emulation Size EEPROM[2:0] Rows Allocated to EEPROM EEPROM Size in Bytes

7 None 0

References: Physical Memory Map

27.6.6 Security Bit

The security bit allows the entire chip to be locked from external access for code security. The security bit can be written by a dedicated command, Set Security Bit (SSB). Once set, the only way to clear the security bit is through a debugger Chip Erase command. After issuing the SSB command, the PROGE error bit can be checked. In order to increase the security level it is recommended to enable the internal BOD33 when the security bit is set. References: DSU

27.6.7 Cache

The NVM Controller cache reduces the device power consumption and improves system performance when wait states are required. Only the NVM main array address space is cached. It is a direct-mapped cache that implements 8 lines of 64 bits (i.e., 64 Bytes). NVM Controller cache can be enabled by writing a '0' to the Cache Disable bit in the Control B register (CTRLB.CACHEDIS). The cache can be configured to three different modes using the Read Mode bit group in the Control B register (CTRLB.READMODE). The INVALL command can be issued using the Command bits in the Control A register to invalidate all cache lines (CTRLA.CMD=INVALL). Commands affecting NVM content automatically invalidate cache lines. SAM L22 Family NVMCTRL – Non-Volatile Memory Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 446

27.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 CMD[6:0] 15:8 CMDEX[7:0] 0x02 ... 0x03 Reserved 0x04 CTRLB 7:0 MANW RWS[3:0] 15:8 FWUP SLEEPPRM[1:0] 23:16 CACHEDIS READMODE[1:0] 31:24 0x08 PARAM 7:0 NVMP[7:0] 15:8 NVMP[15:8] 23:16 RWWEEP[3:0] PSZ[2:0] 31:24 RWWEEP[11:4] 0x0C INTENCLR 7:0 ERROR READY 0x0D ... 0x0F Reserved 0x10 INTENSET 7:0 ERROR READY 0x11 ... 0x13 Reserved 0x14 INTFLAG 7:0 ERROR READY 0x15 ... 0x17 Reserved 0x18 STATUS 7:0 NVME LOCKE PROGE LOAD PRM 15:8 SB 0x1A ... 0x1B Reserved 0x1C ADDR 7:0 ADDR[7:0] 15:8 ADDR[15:8] 23:16 ADDR[21:16] 31:24 0x20 LOCK 7:0 LOCK[7:0] 15:8 LOCK[15:8]

27.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read- Synchronized" and/or "Write-Synchronized" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. SAM L22 Family NVMCTRL – Non-Volatile Memory Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 447

27.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x0000 Property: PAC Write-Protection Bit 15 14 13 12 11 10 9 8 CMDEX[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CMD[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bits 15:8 – CMDEX[7:0] Command Execution When this bit group is written to the key value 0xA5, the command written to CMD will be executed. If a value different from the key value is tried, the write will not be performed and the Programming Error bit in the Status register (STATUS.PROGE) will be set. PROGE is also set if a previously written command is not completed yet. The key value must be written at the same time as CMD. If a command is issued through the APB bus on the same cycle as an AHB bus access, the AHB bus access will be given priority. The command will then be executed when the NVM block and the AHB bus are idle. INTFLAG.READY must be '1' when the command is issued. Bit 0 of the CMDEX bit group will read back as '1' until the command is issued. Note: The NVM Address bit field in the Address register (ADDR.ADDR) uses 16-bit addressing. Bits 6:0 – CMD[6:0] Command These bits define the command to be executed when the CMDEX key is written. CMD[6:0] Group Configuration 0x02 ER Erase Row - Erases the row addressed by the ADDR register in the NVM main array. 0x03 - Reserved 0x04 WP Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. 0x05 EAR Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the User Configuration Row. 0x06 WAP Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the User Configuration Row. 0x07-0x0E - Reserved 0x1A-0x19 - Reserved 0x1A RWWEEER RWWEE Erase Row - Erases the row addressed by the ADDR register in the RWWEE array. 0x1B - Reserved 0x1C RWWEEWP RWWEE Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register in the RWWEE array. 0x1D-0x3F - Reserved 0x40 LR Lock Region - Locks the region containing the address location in the ADDR register. SAM L22 Family NVMCTRL – Non-Volatile Memory Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 448

CMD[6:0] Group Configuration 0x41 UR Unlock Region - Unlocks the region containing the address location in the ADDR register. 0x42 SPRM Sets the Power Reduction Mode. 0x43 CPRM Clears the Power Reduction Mode. 0x44 PBC Page Buffer Clear - Clears the page buffer. 0x45 SSB Set Security Bit - Locks device from external access for code security. 0x46 INVALL Invalidates all cache lines. SAM L22 Family NVMCTRL – Non-Volatile Memory Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 449

27.8.2 Control B

Name: CTRLB Offset: 0x04 Reset: 0x00000080 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 CACHEDIS READMODE[1:0] Access R/W R/W R/W Reset 0 0 0 Bit 15 14 13 12 11 10 9 8 FWUP SLEEPPRM[1:0] Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 MANW RWS[3:0] Access R/W R/W R/W R/W R/W Reset 1 0 0 0 0 Bit 18 – CACHEDIS Cache Disable These bits are used to enable/disable the cache. Value Description

0 The cache is enabled

1 The cache is disabled

Bits 17:16 – READMODE[1:0] NVMCTRL Read Mode Value Name Description 0x0 NO_MISS_PENALTY The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. 0x1 LOW_POWER Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increased run time. 0x2 DETERMINISTIC The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed Flash wait states. This mode can be used for real-time applications that require deterministic execution timings. 0x3 Reserved Bit 11 – FWUP Fast Wake-Up Value Description

0 Fast wake-up is turned off

1 Fast wake-up is turned on

Bits 9:8 – SLEEPPRM[1:0] Power Reduction Mode during Sleep Indicates the Power Reduction Mode during sleep. SAM L22 Family NVMCTRL – Non-Volatile Memory Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 450

0x0 WAKEONACCESS NVM block enters low-power mode when entering sleep. NVM block exits low-power mode upon first access. 0x1 WAKEUPINSTANT NVM block enters low-power mode when entering sleep. NVM block exits low-power mode when exiting sleep. 0x2 Reserved 0x3 DISABLED Auto power reduction disabled. Bit 7 – MANW Manual Write Note that reset value of this bit is '1'. Value Description 0 Writing to the last word in the page buffer will initiate a write operation to the page addressed by the last write operation. This includes writes to memory and auxiliary rows. 1 Write commands must be issued through the CTRLA.CMD register. Bits 4:1 – RWS[3:0] NVM Read Wait States These bits control the number of wait states for a read operation. '0' indicates zero wait states, '1' indicates one wait state and so on, up to 15 wait states. This register is initialized to 0 wait states. Software can change this value based on the NVM access time and system frequency. SAM L22 Family NVMCTRL – Non-Volatile Memory Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 451

27.8.3 NVM Parameter

Name: PARAM Offset: 0x08 Reset: 0x000XXXXX - x initially determined from NVM User Row after Reset Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 RWWEEP[11:4] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 RWWEEP[3:0] PSZ[2:0] Access R R R R R R R Reset 0 0 0 0 x x x Bit 15 14 13 12 11 10 9 8 NVMP[15:8] Access R R R R R R R R Reset x x x x x x x x Bit 7 6 5 4 3 2 1 0 NVMP[7:0] Access R R R R R R R R Reset x x x x x x x x Bits 31:20 – RWWEEP[11:0] RWWEE Pages Indicates the number of pages in the RWWEE address space. Bits 18:16 – PSZ[2:0] Page Size Indicates the page size. Not all devices of the device families will provide all the page sizes indicated in the table. Value Name Description 0x0 8 8 bytes 0x1 16 16 bytes 0x2 32 32 bytes 0x3 64 64 bytes 0x4 128 128 bytes 0x5 256 256 bytes 0x6 512 512 bytes 0x7 1024 1024 bytes Bits 15:0 – NVMP[15:0] NVM Pages Indicates the number of pages in the NVM main address space. SAM L22 Family NVMCTRL – Non-Volatile Memory Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 452

27.8.4 Interrupt Enable Clear

Name: INTENCLR Offset: 0x0C Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 5 4 3 2 1 0 ERROR READY Access R/W R/W Reset 0 0 Bit 1 – ERROR Error Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the ERROR interrupt enable. This bit will read as the current value of the ERROR interrupt enable. Bit 0 – READY NVM Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the READY interrupt enable. This bit will read as the current value of the READY interrupt enable. SAM L22 Family NVMCTRL – Non-Volatile Memory Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 453

27.8.5 Interrupt Enable Set

Name: INTENSET Offset: 0x10 Reset: 0x00 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 5 4 3 2 1 0 ERROR READY Access R/W R/W Reset 0 0 Bit 1 – ERROR Error Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit sets the ERROR interrupt enable. This bit will read as the current value of the ERROR interrupt enable. Bit 0 – READY NVM Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit sets the READY interrupt enable. This bit will read as the current value of the READY interrupt enable. SAM L22 Family NVMCTRL – Non-Volatile Memory Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 454

27.8.6 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x14 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 ERROR READY Access R/W R Reset 0 0 Bit 1 – ERROR Error This flag is set on the occurrence of an NVME, LOCKE or PROGE error. This bit can be cleared by writing a '1' to its bit location. Value Description 0 No errors have been received since the last clear. 1 At least one error has occurred since the last clear. Bit 0 – READY NVM Ready Value Description 0 The NVM controller is busy programming or erasing. 1 The NVM controller is ready to accept a new command. SAM L22 Family NVMCTRL – Non-Volatile Memory Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 455

27.8.7 Status

Name: STATUS Offset: 0x18 Reset: 0x0X00 - X initially determined from NVM User Row after Reset Property: – Bit 15 14 13 12 11 10 9 8 SB Access R Reset x Bit 7 6 5 4 3 2 1 0 NVME LOCKE PROGE LOAD PRM Access R/W R/W R/W R/W R Reset 0 0 0 0 0 Bit 8 – SB Security Bit Status Value Description 0 The Security bit is inactive. 1 The Security bit is active. Bit 4 – NVME NVM Error This bit can be cleared by writing a '1' to its bit location. Value Description

0 No programming or erase errors have been received from the NVM controller since this bit was last

cleared. 1 At least one error has been registered from the NVM Controller since this bit was last cleared. Bit 3 – LOCKE Lock Error Status This bit can be cleared by writing a '1' to its bit location. Value Description 0 No programming of any locked lock region has happened since this bit was last cleared. 1 Programming of at least one locked lock region has happened since this bit was last cleared. Bit 2 – PROGE Programming Error Status This bit can be cleared by writing a '1' to its bit location. Value Description

0 No invalid commands or bad keywords were written in the NVM Command register since this bit was

last cleared.

1 An invalid command and/or a bad keyword was/were written in the NVM Command register since this

bit was last cleared. Bit 1 – LOAD NVM Page Buffer Active Loading This bit indicates that the NVM page buffer has been loaded with one or more words. Immediately after an NVM load has been performed, this flag is set. It remains set until a page write or a page buffer clear (PBCLR) command is given. This bit can be cleared by writing a '1' to its bit location. Bit 0 – PRM Power Reduction Mode This bit indicates the current NVM power reduction state. The NVM block can be set in power reduction mode in two ways: through the command interface or automatically when entering sleep with SLEEPPRM set accordingly. PRM can be cleared in three ways: through AHB access to the NVM block, through the command interface (SPRM and CPRM) or when exiting sleep with SLEEPPRM set accordingly. Value Description 0 NVM is not in power reduction mode. SAM L22 Family NVMCTRL – Non-Volatile Memory Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 456

27.8.8 Address

Name: ADDR Offset: 0x1C Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 ADDR[21:16] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ADDR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 21:0 – ADDR[21:0] NVM Address ADDR drives the hardware half-word offset from the start address of the corresponding NVM section when a command is executed using CMDEX. The effective address for the operation is start address of the SECTION_ADDRESS + 2*ADDR. This register is also automatically updated when writing to the page buffer. Example: For erasing the 3rd row in the Flash memory - spanning from 0x00000200 to 0x000002FF - ADDR must be written with the half-word offset address of any half-word within this range, that is any value between 0x100 and 0x17F Refer to the Physical Memory Map for more information. SAM L22 Family NVMCTRL – Non-Volatile Memory Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 458

27.8.9 Lock Section

Name: LOCK Offset: 0x20 Reset: 0xXXXX - X determined at start-up from NVM User Row Property: – Bit 15 14 13 12 11 10 9 8 LOCK[15:8] Access R R R R R R R R Reset x x x x x x x x Bit 7 6 5 4 3 2 1 0 LOCK[7:0] Access R R R R R R R R Reset x x x x x x x x Bits 15:0 – LOCK[15:0] Region Lock Bits In order to set or clear these bits, the CMD register must be used. Default state after erase will be unlocked (0xFFFF). Value Description 0 The corresponding lock region is locked. 1 The corresponding lock region is not locked. SAM L22 Family NVMCTRL – Non-Volatile Memory Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 459

PORT - I/O Pin Controller

28.1 Overview

The IO Pin Controller (PORT) controls the I/O pins of the device. The I/O pins are organized in a series of groups, collectively referred to as a PORT group. Each PORT group can have up to 32 pins that can be configured and controlled individually or as a group. The number of PORT groups on a device may depend on the package/number of pins. Each pin may either be used for general-purpose I/O under direct application control or be assigned to an embedded device peripheral. When used for general-purpose I/O, each pin can be configured as input or output, with highly configurable driver and pull settings. All I/O pins have true read-modify-write functionality when used for general-purpose I/O; the direction or the output value of one or more pins may be changed (set, reset or toggled) explicitly without unintentionally changing the state of any other pins in the same port group by a single, atomic 8-, 16- or 32-bit write. The PORT is connected to the high-speed bus matrix through an AHB/APB bridge. The Pin Direction, Data Output Value and Data Input Value registers may also be accessed using the low-latency CPU local bus (IOBUS; ARM® single-cycle I/O port).

28.2 Features

Selectable input and output configuration for each individual pin
Software-controlled multiplexing of peripheral functions on I/O pins
Flexible pin configuration through a dedicated Pin Configuration register
Configurable output driver and pull settings: – Totem-pole (push-pull) – Pull configuration – Driver strength
Configurable input buffer and pull settings: – Internal pull-up or pull-down – Input sampling criteria – Input buffer can be disabled if not needed for lower power consumption
Input event: – Up to four input event pins for each PORT group – SET/CLEAR/TOGGLE event actions for each event input on output value of a pin – Can be output to pin
Power saving using STANDBY mode – No access to configuration registers – Possible access to data registers (DIR, OUT or IN) SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 460

28.3 Block Diagram

Figure 28-1. PORT Block Diagram ANALOG BLOCKS PERIPHERALS Digital Controls of Analog Blocks Analog Pad Connections I/O PADS Port Line Bundles IP Line Bundles Peripheral Mux Select PORT Control and Status Pad Line Bundles PORTMUX

28.4 Signal Description

Table 28-1. Signal description for PORT Signal name Type Description Pxy Digital I/O General-purpose I/O pin y in group x Refer to the I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be mapped on several pins. References: I/O Multiplexing and Considerations

28.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly as following.

28.5.1 I/O Lines

The I/O lines of the PORT are mapped to pins of the physical device. The following naming scheme is used: Each line bundle with up to 32 lines is assigned an identifier 'xy', with letter x=A, B, C… and two-digit number y=00, 01, …31. Examples: A24, C03. PORT pins are labeled 'Pxy' accordingly, for example PA24, PC03. This identifies each pin in the device uniquely. Each pin may be controlled by one or more peripheral multiplexer settings, which allow the pad to be routed internally to a dedicated peripheral function. When the setting is enabled, the selected peripheral has control over the output state of the pad, as well as the ability to read the current physical pad state. Refer to I/O Multiplexing and Considerations for details. Each pin may be secured or non-secured, with secured pins only accessible by secure accesses. Device-specific configurations may cause some lines (and the corresponding Pxy pin) not to be implemented. SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 461

References: I/O Multiplexing and Considerations

28.5.2 Power Management

During Reset, all PORT lines are configured as inputs with input buffers, output buffers and pull disabled. When the device is set to the BACKUP sleep mode, even if the PORT configuration registers and input synchronizers will lose their contents (these will not be restored when PORT is powered up again), the latches in the pads will keep their current configuration, such as the output value and pull settings. Refer to the Power Manager documentation for more features related to the I/O lines configuration in and out of BACKUP mode. The PORT peripheral will continue operating in any sleep mode where its source clock is running.

28.5.3 Clocks

The PORT bus clock (CLK_PORT_APB) can be enabled and disabled in the Main Clock module, and the default state of CLK_PORT_APB can be found in the Peripheral Clock Masking section in the MCLK - Main Clock. The PORT is fed by two different clocks: a CPU main clock, which allows the CPU to access the PORT through the low latency CPU local bus (IOBUS); an APB clock, which is a divided clock of the CPU main clock and allows the CPU to access the registers of PORT through the high-speed matrix and the AHB/APB bridge. The priority of IOBUS accesses is higher than event accesses and APB accesses. The EVSYS and APB will insert wait states in the event of concurrent PORT accesses. The PORT input synchronizers use the CPU main clock so that the resynchronization delay is minimized with respect to the APB clock. References: Peripheral Clock Masking MCLK - Main Clock

28.5.4 DMA

Not applicable.

28.5.5 Interrupts

Not applicable.

28.5.6 Events

The events of this peripheral are connected to the Event System. References: 29. EVSYS – Event System

28.5.7 Debug Operation

When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result during debugging. This peripheral can be forced to halt operation during debugging - refer to the Debug Control (DBGCTRL) register for details.

28.5.8 Register Access Protection

28.5.9 Analog Connections

Analog functions are connected directly between the analog blocks and the I/O pads using analog buses. However, selecting an analog peripheral function for a given pin will disable the corresponding digital features of the pad.

28.6 Functional Description

Figure 28-2. Overview of the PORT PULLENx OUTx DIRx INENx PORT PAD VDD INEN OE OUT PULLEN PAD Pull Resistor PG NG Input to Other Modules Analog Input/Output ININx APB Bus Synchronizer Q D RR D Q DRIVEx DRIVE VDDIO Note: The ESD diode connected to VDDIO is not plugged for the Back-up I/Os. For these specific pins, only the ESD diode connected to ground is implemented.

28.6.1 Principle of Operation

Each PORT group of up to 32 pins is controlled by the registers in PORT, as described in the figure. These registers in PORT are duplicated for each PORT group, with increasing base addresses. The number of PORT groups may depend on the package/number of pins. Figure 28-3. Overview of the peripheral functions multiplexing Port y PINCFG Port y Periph Signal 0 PORT bit y PMUXEN Data+Config Periph Signal 1 Periph Signal 15 Port y PMUX[3:0] Port y PMUX Select Port y Line Bundle PAD y Pad y Peripheral Signals to be muxed to Pad y Port y Peripheral Mux Enable Line Bundle PORTMUX SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 463

The I/O pins of the device are controlled by PORT peripheral registers. Each port pin has a corresponding bit in the Data Direction (DIR) and Data Output Value (OUT) registers to enable that pin as an output and to define the output state. The direction of each pin in a PORT group is configured by the DIR register. If a bit in DIR is set to '1', the corresponding pin is configured as an output pin. If a bit in DIR is set to '0', the corresponding pin is configured as an input pin. When the direction is set as output, the corresponding bit in the OUT register will set the level of the pin. If bit y in OUT is written to '1', pin y is driven HIGH. If bit y in OUT is written to '0', pin y is driven LOW. Pin configuration can be set by Pin Configuration (PINCFGy) registers, with y=00, 01, ..31 representing the bit position. The Data Input Value (IN) is set as the input value of a port pin with resynchronization to the PORT clock. To reduce power consumption, these input synchronizers are clocked only when system requires reading the input value. The value of the pin can always be read, whether the pin is configured as input or output. If the Input Enable bit in the Pin Configuration registers (PINCFGy.INEN) is '0', the input value will not be sampled. In PORT, the Peripheral Multiplexer Enable bit in the PINCFGy register (PINCFGy.PMUXEN) can be written to '1' to enable the connection between peripheral functions and individual I/O pins. The Peripheral Multiplexing n (PMUXn) registers select the peripheral function for the corresponding pin. This will override the connection between the PORT and that I/O pin, and connect the selected peripheral signal to the particular I/O pin instead of the PORT line bundle.

28.6.2 Basic Operation

28.6.2.1 Initialization

After reset, all standard function device I/O pads are connected to the PORT with outputs tri-stated and input buffers disabled, even if there is no clock running. However, specific pins, such as those used for connection to a debugger, may be configured differently, as required by their special function.

28.6.2.2 Operation

Each I/O pin y can be controlled by the registers in PORT. Each PORT group has its own set of PORT registers, the base address of the register set for pin y is at byte address PORT + ([y] * 0x4). The index within that register set is [y]. To use pin number y as an output, write bit y of the DIR register to '1'. This can also be done by writing bit y in the DIRSET register to '1' - this will avoid disturbing the configuration of other pins in that group. The y bit in the OUT register must be written to the desired output value. Similarly, writing an OUTSET bit to '1' will set the corresponding bit in the OUT register to '1'. Writing a bit in OUTCLR to '1' will set that bit in OUT to zero. Writing a bit in OUTTGL to '1' will toggle that bit in OUT. To use pin y as an input, bit y in the DIR register must be written to '0'. This can also be done by writing bit y in the DIRCLR register to '1' - this will avoid disturbing the configuration of other pins in that group. The input value can be read from bit y in register IN as soon as the INEN bit in the Pin Configuration register (PINCFGy.INEN) is written to '1'. Refer to I/O Multiplexing and Considerations for details on pin configuration and PORT groups. By default, the input synchronizer is clocked only when an input read is requested. This will delay the read operation by two CLK_PORT cycles. To remove the delay, the input synchronizers for each PORT group of eight pins can be configured to be always active, but this will increase power consumption. This is enabled by writing '1' to the corresponding SAMPLINGn bit field of the CTRL register, see CTRL.SAMPLING for details. To use pin y as one of the available peripheral functions, the corresponding PMUXEN bit of the PINCFGy register must be '1'. The PINCFGy register for pin y is at byte offset (PINCFG0 + [y]). The peripheral function can be selected by setting the PMUXO or PMUXE in the PMUXn register. The PMUXO/ PMUXE is at byte offset PMUX0 + (y/2). The chosen peripheral must also be configured and enabled. References: I/O Multiplexing and Considerations SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 464

28.6.3 I/O Pin Configuration

The Pin Configuration register (PINCFGy) is used for additional I/O pin configuration. A pin can be set in a totem- pole, or pull configuration. As pull configuration is done through the Pin Configuration register, all intermediate PORT states during switching of pin direction and pin values are avoided. The I/O pin configurations are described further in this chapter, and summarized in Table 28-2.

28.6.3.1 Pin Configurations Summary

Table 28-2. Pin Configurations Summary DIR INEN PULLEN OUT Configuration 0 0 0 X Reset or analog I/O: all digital disabled 0 0 1 0 Pull-down; input disabled 0 0 1 1 Pull-up; input disabled 0 1 0 X Input 0 1 1 0 Input with pull-down 0 1 1 1 Input with pull-up 1 0 X X Output; input disabled 1 1 X X Output; input enabled

28.6.3.2 Input Configuration

Figure 28-4. I/O configuration - Standard Input PULLEN DIR OUT IN INEN PULLEN INEN DIR 0 1 0 Figure 28-5. I/O Configuration - Input with Pull PULLEN DIR OUT IN INEN PULLEN INEN DIR 1 1 0 Note: When pull is enabled, the pull value is defined by the OUT value.

28.6.3.3 Totem-Pole Output

When configured for totem-pole (push-pull) output, the pin is driven low or high according to the corresponding bit setting in the OUT register. In this configuration there is no current limitation for sink or source other than what the pin is capable of. If the pin is configured for input, the pin will float if no external pull is connected. Note: Enabling the output driver will automatically disable pull. SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 465

Figure 28-6. I/O Configuration - Totem-Pole Output with Disabled Input PULLEN DIR OUT IN INEN PULLEN INEN DIR 0 0 1 Figure 28-7. I/O Configuration - Totem-Pole Output with Enabled Input PULLEN DIR OUT IN INEN PULLEN INEN DIR 0 1 1 Figure 28-8. I/O Configuration - Output with Pull PULLEN DIR OUT IN INEN PULLEN INEN DIR 1 0 0

28.6.3.4 Digital Functionality Disabled

Neither Input nor Output functionality are enabled. Figure 28-9. I/O Configuration - Reset or Analog I/O: Digital Output, Input and Pull Disabled PULLEN DIR OUT IN INEN PULLEN INEN DIR 0 0 0

28.6.4 Events

The PORT allows input events to control individual I/O pins. These input events are generated by the EVSYS module and can originate from a different clock domain than the PORT module. The PORT can perform the following actions:

Output (OUT): I/O pin will be set when the incoming event has a high level ('1') and cleared when the incoming event has a low-level ('0'). SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 466

Set (SET): I/O pin will be set when an incoming event is detected.
Clear (CLR): I/O pin will be cleared when an incoming event is detected.
Toggle (TGL): I/O pin will toggle when an incoming event is detected. The event is output to pin without any internal latency. For SET, CLEAR and TOGGLE event actions, the action will be executed up to three clock cycles after a rising edge. Note: In Standby mode, only the OUT operation is possible and SET, CLEAR and TOGGLE operations are not possible. The event actions can be configured with the Event Action m bit group in the Event Input Control register( EVCTRL.EVACTm). Writing a '1' to a PORT Event Enable Input m of the Event Control register (EVCTRL.PORTEIm) enables the corresponding action on input event. Writing '0' to this bit disables the corresponding action on input event. Note that several actions can be enabled for incoming events. If several events are connected to the peripheral, any enabled action will be taken for any of the incoming events. Refer to EVSYS. for details on configuring the Event System. Each event input can address one and only one I/O pin at a time. The selection of the pin is indicated by the PORT Event Pin Identifier of the Event Input Control register (EVCTR.PIDn). On the other hand, one I/O pin can be addressed by up to four different input events. To avoid action conflict on the output value of the register (OUT) of this particular I/O pin, only one action is performed according to the table below. Note that this truth table can be applied to any SET/CLR/TGL configuration from two to four active input events. Table 28-3. Priority on Simultaneous SET/CLR/TGL Event Actions EVACT0 EVACT1 EVACT2 EVACT3 Executed Event Action SET SET SET SET SET CLR CLR CLR CLR CLR All Other Combinations TGL Be careful when the event is output to pin. Due to the fact the events are received asynchronously, the I/O pin may have unpredictable levels, depending on the timing of when the events are received. When several events are output to the same pin, the lowest event line will get the access. All other events will be ignored. References: EVSYS

28.6.5 PORT Access Priority

The PORT is accessed by different systems:

The ARM ® CPU through the ARM® single-cycle I/O port (IOBUS)
The ARM ® CPU through the high-speed matrix and the AHB/APB bridge (APB)
EVSYS through four asynchronous input events The following priority is adopted: 1. ARM ® CPU IOBUS (No wait tolerated) 2. APB 3. EVSYS input events For input events that require different actions on the same I/O pin, refer to 28.6.4. Events. SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 467

28.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 DIR 7:0 DIR[7:0] 15:8 DIR[15:8] 23:16 DIR[23:16] 31:24 DIR[31:24] 0x04 DIRCLR 7:0 DIRCLR[7:0] 15:8 DIRCLR[15:8] 23:16 DIRCLR[23:16] 31:24 DIRCLR[31:24] 0x08 DIRSET 7:0 DIRSET[7:0] 15:8 DIRSET[15:8] 23:16 DIRSET[23:16] 31:24 DIRSET[31:24] 0x0C DIRTGL 7:0 DIRTGL[7:0] 15:8 DIRTGL[15:8] 23:16 DIRTGL[23:16] 31:24 DIRTGL[31:24] 0x10 OUT 7:0 OUT[7:0] 15:8 OUT[15:8] 23:16 OUT[23:16] 31:24 OUT[31:24] 0x14 OUTCLR 7:0 OUTCLR[7:0] 15:8 OUTCLR[15:8] 23:16 OUTCLR[23:16] 31:24 OUTCLR[31:24] 0x18 OUTSET 7:0 OUTSET[7:0] 15:8 OUTSET[15:8] 23:16 OUTSET[23:16] 31:24 OUTSET[31:24] 0x1C OUTTGL 7:0 OUTTGL[7:0] 15:8 OUTTGL[15:8] 23:16 OUTTGL[23:16] 31:24 OUTTGL[31:24] 0x20 IN 7:0 IN[7:0] 15:8 IN[15:8] 23:16 IN[23:16] 31:24 IN[31:24] 0x24 CTRL 7:0 SAMPLING[7:0] 15:8 SAMPLING[15:8] 23:16 SAMPLING[23:16] 31:24 SAMPLING[31:24] 0x28 WRCONFIG 7:0 PINMASK[7:0] 15:8 PINMASK[15:8] 23:16 DRVSTR PULLEN INEN PMUXEN 31:24 HWSEL WRPINCFG WRPMUX PMUX[3:0] 0x2C EVCTRL 7:0 PORTEI0 EVACT0[1:0] PID0[4:0] 15:8 PORTEI1 EVACT1[1:0] PID1[4:0] 23:16 PORTEI2 EVACT2[1:0] PID2[4:0] 31:24 PORTEI3 EVACT3[1:0] PID3[4:0] 0x30 PMUX0 7:0 PMUXO[3:0] PMUXE[3:0] ... 0x3F PMUX15 7:0 PMUXO[3:0] PMUXE[3:0] 0x40 PINCFG0 7:0 DRVSTR PULLEN INEN PMUXEN ... 0x5F PINCFG31 7:0 DRVSTR PULLEN INEN PMUXEN SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 468

28.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write- protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 28.5.8. Register Access Protection. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 469

28.8.1 Data Direction

Name: DIR Offset: 0x00 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to configure one or more I/O pins as an input or output. This register can be manipulated without doing a read-modify-write operation by using the Data Direction Toggle (DIRTGL), Data Direction Clear (DIRCLR) and Data Direction Set (DIRSET) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, and so on. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 DIR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DIR[31:0] Port Data Direction These bits set the data direction for the individual I/O pins in the PORT group. Value Description 0 The corresponding I/O pin in the PORT group is configured as an input. 1 The corresponding I/O pin in the PORT group is configured as an output. SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 470

28.8.2 Data Direction Clear

Name: DIRCLR Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to set one or more I/O pins as an input, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data Direction Set (DIRSET) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, and so on. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 DIRCLR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIRCLR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIRCLR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIRCLR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DIRCLR[31:0] Port Data Direction Clear Writing a '0' to a bit has no effect. Writing a '1' to a bit will clear the corresponding bit in the DIR register, which configures the I/O pin as an input. Value Description 0 The corresponding I/O pin in the PORT group will keep its configuration. 1 The corresponding I/O pin in the PORT group is configured as input. SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 471

28.8.3 Data Direction Set

Name: DIRSET Offset: 0x08 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to set one or more I/O pins as an output, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data Direction Clear (DIRCLR) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, and so on. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 DIRSET[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIRSET[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIRSET[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIRSET[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DIRSET[31:0] Port Data Direction Set Writing '0' to a bit has no effect. Writing '1' to a bit will set the corresponding bit in the DIR register, which configures the I/O pin as an output. Value Description 0 The corresponding I/O pin in the PORT group will keep its configuration. 1 The corresponding I/O pin in the PORT group is configured as an output. SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 472

28.8.4 Data Direction Toggle

Name: DIRTGL Offset: 0x0C Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to toggle the direction of one or more I/O pins, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Set (DIRSET) and Data Direction Clear (DIRCLR) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, and so on. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 DIRTGL[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIRTGL[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIRTGL[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIRTGL[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DIRTGL[31:0] Port Data Direction Toggle Writing '0' to a bit has no effect. Writing '1' to a bit will toggle the corresponding bit in the DIR register, which reverses the direction of the I/O pin. Value Description 0 The corresponding I/O pin in the PORT group will keep its configuration. 1 The direction of the corresponding I/O pin is toggled. SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 473

28.8.5 Data Output Value

Name: OUT Offset: 0x10 Reset: 0x00000000 Property: PAC Write-Protection This register sets the data output drive value for the individual I/O pins in the PORT. This register can be manipulated without doing a read-modify-write operation by using the Data Output Value Clear (OUTCLR), Data Output Value Set (OUTSET), and Data Output Value Toggle (OUTTGL) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, and so on. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 OUT[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OUT[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 OUT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OUT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – OUT[31:0] PORT Data Output Value For pins configured as outputs via the Data Direction register (DIR), these bits set the logical output drive level. For pins configured as inputs via the Data Direction register (DIR) and with pull enabled via the Pull Enable bit in the Pin Configuration register (PINCFG.PULLEN), these bits will set the input pull direction. Value Description 0 The I/O pin output is driven low, or the input is connected to an internal pull-down. 1 The I/O pin output is driven high, or the input is connected to an internal pull-up. SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 474

28.8.6 Data Output Value Clear

Name: OUTCLR Offset: 0x14 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to set one or more output I/O pin drive levels low, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle (OUTTGL) and Data Output Value Set (OUTSET) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, and so on. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 OUTCLR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OUTCLR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 OUTCLR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OUTCLR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – OUTCLR[31:0] PORT Data Output Value Clear Writing '0' to a bit has no effect. Writing '1' to a bit will clear the corresponding bit in the OUT register. Pins configured as outputs through the Data Direction register (DIR) will be set to low-output drive level. Pins configured as inputs through DIR and with pull enabled through the Pull Enable bit in the Pin Configuration register (PINCFG.PULLEN) will set the input pull direction to an internal pull-down. Value Description 0 The corresponding I/O pin in the PORT group will keep its configuration. 1 The corresponding I/O pin output is driven low, or the input is connected to an internal pull-down. SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 475

28.8.7 Data Output Value Set

Name: OUTSET Offset: 0x18 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to set one or more output I/O pin drive levels high, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle (OUTTGL) and Data Output Value Clear (OUTCLR) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, and so on. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 OUTSET[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OUTSET[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 OUTSET[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OUTSET[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – OUTSET[31:0] PORT Data Output Value Set Writing '0' to a bit has no effect. Writing '1' to a bit will set the corresponding bit in the OUT register, which sets the output drive level high for I/O pins configured as outputs via the Data Direction register (DIR). For pins configured as inputs via Data Direction register (DIR) with pull enabled via the Pull Enable register (PULLEN), these bits will set the input pull direction to an internal pull-up. Value Description 0 The corresponding I/O pin in the group will keep its configuration. 1 The corresponding I/O pin output is driven high, or the input is connected to an internal pull-up. SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 476

28.8.8 Data Output Value Toggle

Name: OUTTGL Offset: 0x1C Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to toggle the drive level of one or more output I/O pins, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Set (OUTSET) and Data Output Value Clear (OUTCLR) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, and so on. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 OUTTGL[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OUTTGL[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 OUTTGL[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OUTTGL[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – OUTTGL[31:0] PORT Data Output Value Toggle Writing '0' to a bit has no effect. Writing '1' to a bit will toggle the corresponding bit in the OUT register, which inverts the output drive level for I/O pins configured as outputs through the Data Direction register (DIR). For pins configured as inputs through Data Direction register (DIR) with pull enabled through the Pull Enable register (PULLEN), these bits will toggle the input pull direction. Value Description 0 The corresponding I/O pin in the PORT group will keep its configuration. 1 The corresponding OUT bit value is toggled. SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 477

28.8.9 Data Input Value

Name: IN Offset: 0x20 Reset: 0x00000000 Property: - Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, and so on. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 IN[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 IN[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 IN[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 IN[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – IN[31:0] PORT Data Input Value These bits are cleared when the corresponding I/O pin input sampler detects a logical low level on the input pin. These bits are set when the corresponding I/O pin input sampler detects a logical high level on the input pin. SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 478

28.8.10 Control

Name: CTRL Offset: 0x24 Reset: 0x00000000 Property: PAC Write-Protection Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, and so on. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 SAMPLING[31:24] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SAMPLING[23:16] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SAMPLING[15:8] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SAMPLING[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – SAMPLING[31:0] Input Sampling Mode Configures the input sampling functionality of the I/O pin input samplers, for pins configured as inputs through the Data Direction register (DIR). The input samplers are enabled and disabled in sub-groups of eight. Thus if any pins within a byte request continuous sampling, all pins in that eight pin sub-group will be continuously sampled. Value Description 0 The I/O pin input synchronizer is disabled. 1 The I/O pin input synchronizer is enabled. SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 479

28.8.11 Write Configuration

Name: WRCONFIG Offset: 0x28 Reset: 0x00000000 Property: PAC Write-Protection This write-only register is used to configure several pins simultaneously with the same configuration and peripheral multiplexing. To avoid side effect of non-atomic access, 8-bit or 16-bit writes to this register will have no effect. Reading this register always returns zero. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, and so on. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 HWSEL WRPINCFG WRPMUX PMUX[3:0] Access W W W W W W W Reset 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DRVSTR PULLEN INEN PMUXEN Access W W W W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 PINMASK[15:8] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PINMASK[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 31 – HWSEL Half-Word Select This bit selects the half-word field of a 32-PORT group to be reconfigured in the atomic write operation. This bit will always read as zero. Value Description 0 The lower 16 pins of the PORT group will be configured. 1 The upper 16 pins of the PORT group will be configured. Bit 30 – WRPINCFG Write PINCFG This bit determines whether the atomic write operation will update the Pin Configuration register (PINCFGy) or not for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits. Writing '0' to this bit has no effect. Writing '1' to this bit updates the configuration of the selected pins with the written WRCONFIG.DRVSTR, This bit will always read as zero. Value Description 0 The PINCFGy registers of the selected pins will not be updated. SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 480

1 The PINCFGy registers of the selected pins will be updated. Bit 28 – WRPMUX Write PMUX This bit determines whether the atomic write operation will update the Peripheral Multiplexing register (PMUXn) or not for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits. Writing '0' to this bit has no effect. Writing '1' to this bit updates the pin multiplexer configuration of the selected pins with the written WRCONFIG. PMUX value. This bit will always read as zero. Value Description 0 The PMUXn registers of the selected pins will not be updated. 1 The PMUXn registers of the selected pins will be updated. Bits 27:24 – PMUX[3:0] Peripheral Multiplexing These bits determine the new value written to the Peripheral Multiplexing register (PMUXn) for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPMUX bit is set. These bits will always read as zero. Bit 22 – DRVSTR Output Driver Strength Selection This bit determines the new value written to PINCFGy.DRVSTR for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set. This bit will always read as zero. Bit 18 – PULLEN Pull Enable This bit determines the new value written to PINCFGy.PULLEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set. This bit will always read as zero. Bit 17 – INEN Input Enable This bit determines the new value written to PINCFGy.INEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set. This bit will always read as zero. Bit 16 – PMUXEN Peripheral Multiplexer Enable This bit determines the new value written to PINCFGy.PMUXEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set. This bit will always read as zero. Bits 15:0 – PINMASK[15:0] Pin Mask for Multiple Pin Configuration These bits select the pins to be configured within the half-word group selected by the WRCONFIG.HWSEL bit. These bits will always read as zero. Value Description 0 The configuration of the corresponding I/O pin in the half-word group will be left unchanged. 1 The configuration of the corresponding I/O pin in the half-word PORT group will be updated. SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 481

28.8.12 Event Input Control

Name: EVCTRL Offset: 0x2C Reset: 0x00000000 Property: PAC Write-Protection, Secure Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, and so on. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. There are up to four input event pins for each PORT group. Each byte of this register addresses one Event input pin. Bit 31 30 29 28 27 26 25 24 PORTEI3 EVACT3[1:0] PID3[4:0] Access RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 PORTEI2 EVACT2[1:0] PID2[4:0] Access RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 PORTEI1 EVACT1[1:0] PID1[4:0] Access RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PORTEI0 EVACT0[1:0] PID0[4:0] Access RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW Reset 0 0 0 0 0 0 0 0 Bits 7, 15, 23, 31 – PORTEIx PORT Event Input Enable x [x = 3..0] Value Description 0 The event action x (EVACTx) will not be triggered on any incoming event. 1 The event action x (EVACTx) will be triggered on any incoming event. Bits 5:6, 13:14, 21:22, 29:30 – EVACTx PORT Event Action x [x = 3..0] These bits define the event action the PORT will perform on event input x. Refer to the PORT Event x Action ( x = [3..0] ) table in the PIDx bit field. Bits 0:4, 8:12, 16:20, 24:28 – PIDx PORT Event Pin Identifier x [x = 3..0] These bits define the I/O pin on which the event action will be performed, according to the following table. Table 28-4. PORT Event x Action ( x = [3..0] ) Value Name Description 0x0 OUT Output register of pin will be set to level of event. 0x1 SET Set output register of pin on event. 0x2 CLR Clear output register of pin on event. SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 482

0x3 TGL Toggle output register of pin on event. Table 28-5. PORT Event x Pin Identifier ( x = [3..0] ) Value Name Description 0x0 PIN0 Event action to be executed on PIN 0x1 PIN1 Event action to be executed on PIN 0x31 PIN31 Event action to be executed on PIN 31. SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 483

28.8.13 Peripheral Multiplexing n

Name: PMUXn Offset: 0x30 + n*0x01 [n=0..15] Reset: 0x00 Property: PAC Write-Protection Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, and so on Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. There are up to 16 Peripheral Multiplexing registers in each group, one for every set of two subsequent I/O lines. The ‘n’ denotes the number of the set of I/O lines. Bit 7 6 5 4 3 2 1 0 PMUXO[3:0] PMUXE[3:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 7:4 – PMUXO[3:0] Peripheral Multiplexing for Odd-Numbered Pin These bits select the peripheral function for odd-numbered pins (2*n + 1) of a PORT group, if the corresponding PINCFGy.PMUXEN bit is '1'. Not all possible values for this selection may be valid. For additional information, refer to I/O Multiplexing and Considerations. PMUXO[3:0] Name Description 0x0 A Peripheral function A selected 0x1 B Peripheral function B selected 0x2 C Peripheral function C selected 0x3 D Peripheral function D selected 0x4 E Peripheral function E selected 0x5 F Peripheral function F selected 0x6 G Peripheral function G selected 0x7 H Peripheral function H selected 0x8 I Peripheral function I selected 0x9-0xF - Reserved Bits 3:0 – PMUXE[3:0] Peripheral Multiplexing for Even-Numbered Pin These bits select the peripheral function for even-numbered pins (2*n) of a PORT group, if the corresponding PINCFGy.PMUXEN bit is '1'. Not all possible values for this selection may be valid. For additional information, refer to the I/O Multiplexing and Considerations. PMUXE[3:0] Name Description 0x0 A Peripheral function A selected 0x1 B Peripheral function B selected 0x2 C Peripheral function C selected 0x3 D Peripheral function D selected 0x4 E Peripheral function E selected 0x5 F Peripheral function F selected 0x6 G Peripheral function G selected 0x7 H Peripheral function H selected 0x8 I Peripheral function I selected SAM L22 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 484

28.8.14 Pin Configuration n

Name: PINCFGn Offset: 0x40 + n*0x01 [n=0..31] Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DRVSTR PULLEN INEN PMUXEN Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 6 – DRVSTR Output Driver Strength Selection This bit controls the output driver strength of an I/O pin configured as an output. Value Description 0 Pin drive strength is set to normal drive strength. 1 Pin drive strength is set to stronger drive strength. Bit 2 – PULLEN Pull Enable This bit enables the internal pull-up or pull-down resistor of an I/O pin configured as an input. Value Description 0 Internal pull resistor is disabled, and the input is in a high-impedance configuration.

1 Internal pull resistor is enabled, and the input is driven to a defined logic level in the absence of

external input. Bit 1 – INEN Input Enable This bit controls the input buffer of an I/O pin configured as either an input or output. Writing a zero to this bit disables the input buffer completely, preventing read-back of the physical pin state when the pin is configured as either an input or output. Value Description 0 Input buffer for the I/O pin is disabled, and the input value will not be sampled. 1 Input buffer for the I/O pin is enabled, and the input value will be sampled when required. Bit 0 – PMUXEN Peripheral Multiplexer Enable This bit enables or disables the peripheral multiplexer selection set in the Peripheral Multiplexing register (PMUXn) to enable or disable alternative peripheral control over an I/O pin direction and output drive value. Writing a zero to this bit allows the PORT to control the pad direction via the Data Direction register (DIR) and output drive value via the Data Output Value register (OUT). The peripheral multiplexer value in PMUXn is ignored. Writing '1' to this bit enables the peripheral selection in PMUXn to control the pad. In this configuration, the physical pin state may still be read from the Data Input Value register (IN) if PINCFGn.INEN is set. Value Description

0 The peripheral multiplexer selection is disabled, and the PORT registers control the direction and

output drive value.

1 The peripheral multiplexer selection is enabled, and the selected peripheral function controls the

EVSYS – Event System

29.1 Overview

The Event System (EVSYS) allows autonomous, low-latency and configurable communication between peripherals. Several peripherals can be configured to generate and/or respond to signals known as events. The exact condition to generate an event, or the action taken upon receiving an event, is specific to each peripheral. Peripherals that respond to events are called event users. Peripherals that generate events are called event generators. A peripheral can have one or more event generators and can have one or more event users. Communication is made without CPU intervention and without consuming system resources such as bus or RAM bandwidth. This reduces the load on the CPU and other system resources, compared to a traditional interrupt-based system.

29.2 Features

8 configurable event channels, where each channel can: – Be connected to any event generator. – Provide a pure asynchronous, resynchronized or synchronous path
69 event generators.
31 event users.
Configurable edge detector.
Peripherals can be event generators, event users, or both.
SleepWalking and interrupt for operation in sleep modes.
Software event generation.
Each event user can choose which channel to respond to.

29.3 Block Diagram

Figure 29-1. Event System Block Diagram USER x+1Event Channel mEvent Channel 1 Event Channel 0 USER x D Q R Synchronized Path Asynchronous Path Edge Detector CHANNEL0.EDGSEL CHANNEL0.PATH EVT DQ R DQ R DQ R Resynchronized Path D Q R D Q R D Q R SWEVT.CHANNEL0 PERIPHERAL n PERIPHERAL0 CHANNEL0.EVGEN USER.CHANNELx Channel_EVT_0 EVT ACK Channel_EVT_m Clock Request [m:0] To Peripheral x Peripheral x GCLK_EVSYS_0 SleepWalking Detector Event Acknowledge

29.4 Signal Description

29.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

29.5.1 I/O Lines

Not applicable.

29.5.2 Power Management

The EVSYS can be used to wake up the CPU from all sleep modes, even if the clock used by the EVSYS channel and the EVSYS bus clock are disabled. Refer to the PM - Power Manager for details on the different sleep modes. In all sleep modes, although the clock for the EVSYS is stopped, the device still can wake up the EVSYS clock. Some event generators can generate an event when their clocks are stopped. The generic clock for the channel (GCLK_EVSYS_CHANNEL_n) will be restarted if that channel uses a synchronized path or a resynchronized path. It does not need to wake the system from sleep. References: PM - Power Manager

29.5.3 Clocks

The EVSYS bus clock (CLK_EVSYS_APB) can be enabled and disabled in the Main Clock module, and the default state of CLK_EVSYS_APB can be found in Peripheral Clock Masking. Each EVSYS channel has a dedicated generic clock (GCLK_EVSYS_CHANNEL_n). These are used for event detection and propagation for each channel. These clocks must be configured and enabled in the generic clock controller before using the EVSYS. Refer to GCLK for details. References: Peripheral Clock Masking GCLK

29.5.4 DMA

Not applicable.

29.5.5 Interrupts

The interrupt request line is connected to the Interrupt Controller. Using the EVSYS interrupts requires the interrupt controller to be configured first. Refer to Nested Vector Interrupt Controller for details.

29.5.6 Events

Not applicable.

29.5.7 Debug Operation

29.5.8 Register Access Protection

Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following:

Channel Status (CHSTATUS)
Interrupt Flag Status and Clear register (INTFLAG) Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. SAM L22 Family EVSYS – Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 488

When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection does not apply for accesses through an external debugger.

29.5.9 Analog Connections

Not applicable.

29.6 Functional Description

29.6.1 Principle of Operation

The Event System consists of several channels which route the internal events from peripherals (generators) to other internal peripherals or IO pins (users). Each event generator can be selected as source for multiple channels, but a channel cannot be set to use multiple event generators at the same time. A channel path can be configured in asynchronous, synchronous or re-synchronized mode of operation. The mode of operation must be selected based on the requirements of the application. When using synchronous or resynchronized path, the Event System includes options to transfer events to users when rising, falling or both edges are detected on event generators. For further details, refer to Channel Path section of this chapter.

29.6.2 Basic Operation

29.6.2.1 Initialization

Before enabling event routing within the system, the Event Users Multiplexer and Event Channels must be selected in the Event System (EVSYS), and the two peripherals that generate and use the event have to be configured. The recommended sequence is: 1. In the event generator peripheral, enable output of event by writing a '1' to the respective Event Output Enable RTC.EVCTRL.OVFEO). 2. Configure the EVSYS: a. Configure the Event User multiplexer by writing the respective EVSYS.USERm register, see also b. Configure the Event Channel by writing the respective EVSYS.CHANNELn register, see also 3. Configure the action to be executed by the event user peripheral by writing to the Event Action bits (EVACT) in Note: Not all peripherals require this step. 4. In the event user peripheral, enable event input by writing a '1' to the respective Event Input Enable bit ("EI") in

29.6.2.2 Enabling, Disabling, and Resetting

The EVSYS is always enabled. The EVSYS is reset by writing a ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the EVSYS will be reset to their initial state and all ongoing events will be canceled. Refer to the CTRLA.SWRST register for details.

29.6.2.3 User Multiplexer Setup

The user multiplexer defines the channel to be connected to which event user. Each user multiplexer is dedicated to one event user. A user multiplexer receives all event channels output and must be configured to select one of these channels, as shown in Block Diagram section. The channel is selected with the Channel bit group in the User register (USERm.CHANNEL). The user multiplexer must always be configured before the channel. A list of all user multiplexers is found in the User (USERm) register description. References: SAM L22 Family EVSYS – Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 489

29.6.2.4 Event System Channel

An event channel can select one event from a list of event generators. Depending on configuration, the selected event could be synchronized, resynchronized or asynchronously sent to the users. When synchronization or resynchronization is required, the channel includes an internal edge detector, allowing the Event System to generate internal events when rising, falling or both edges are detected on the selected event generator. An event channel is able to generate internal events for the specific software commands. A channel block diagram is shown in Block Diagram section.

29.6.2.5 Event Generators

Each event channel can receive the events form all event generators. All event generators are listed in the Event Generator bit field in the Channel n register (CHANNELn.EVGEN). For details on event generation, refer to the corresponding module chapter. The channel event generator is selected by the Event Generator bit group in the Channel register (CHANNELn.EVGEN). By default, the channels are not connected to any event generators (ie, CHANNELn.EVGEN = 0)

29.6.2.6 Channel Path

There are three different ways to propagate the event from an event generator:

Asynchronous path
Synchronous path
Resynchronized path The path is decided by writing to the Path Selection bit group of the Channel register (CHANNELn.PATH). Asynchronous Path When using the asynchronous path, the events are propagated from the event generator to the event user without intervention from the Event System. The GCLK for this channel (GCLK_EVSYS_CHANNEL_n) is not mandatory, meaning that an event will be propagated to the user without any clock latency. When the asynchronous path is selected, the channel cannot generate any interrupts, and the Channel Status register (CHSTATUS) is always zero. The edge detection is not required and must be disabled by software. Each peripheral event user has to select which event edge must trigger internal actions. For further details, refer to each peripheral chapter description. Synchronous Path The synchronous path should be used when the event generator and the event channel share the same generator for the generic clock. If they do not share the same clock, a logic change from the event generator to the event channel might not be detected in the channel, which means that the event will not be propagated to the event user. For details on generic clock generators, refer to GCLK - Generic Clock Controller. When using the synchronous path, the channel is able to generate interrupts. The channel busy n bit in the Channel Status register (CHSTATUS.CHBUSYn) are also updated and available for use. Resynchronized Path The resynchronized path are used when the event generator and the event channel do not share the same generator for the generic clock. When the resynchronized path is used, resynchronization of the event from the event generator is done in the channel. For details on generic clock generators, refer to GCLK - Generic Clock Controller. When the resynchronized path is used, the channel is able to generate interrupts. The channel busy n bits in the Channel Status register (CHSTATUS.CHBUSYn) are also updated and available for use.

29.6.2.7 Edge Detection

When synchronous or resynchronized paths are used, edge detection must be enabled. The event system can execute edge detection in three different ways:

Generate an event only on the rising edge
Generate an event only on the falling edge
Generate an event on rising and falling edges. Edge detection is selected by writing to the Edge Selection bit group of the Channel register (CHANNELn.EDGSEL). SAM L22 Family EVSYS – Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 490

29.6.2.8 Event Latency

An event from an event generator is propagated to an event user with different latency, depending on event channel configuration.

Asynchronous Path: The maximum routing latency of an external event is related to the internal signal routing and it is device dependent.
Synchronous Path: The maximum routing latency of an external event is one GCLK_EVSYS_CHANNEL_n clock cycle.
Resynchronized Path: The maximum routing latency of an external event is three GCLK_EVSYS_CHANNEL_n clock cycles. The maximum propagation latency of a user event to the peripheral clock core domain is three peripheral clock cycles. The event generators, event channel and event user clocks ratio must be selected in relation with the internal event latency constraints. Events propagation or event actions in peripherals may be lost if the clock setup violates the internal latencies.

29.6.2.9 The Overrun Channel n Interrupt

The Overrun Channel n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVRn) will be set, and the optional interrupt will be generated in the following cases:

One or more event users on channel n is not ready when there is a new event.
An event occurs when the previous event on channel m has not been handled by all event users connected to that channel. The flag will only be set when using synchronous or resynchronized paths. In the case of asynchronous path, the INTFLAG.OVRn is always read as zero.

29.6.2.10 The Event Detected Channel n Interrupt

The Event Detected Channel n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.EVDn) is set when an event coming from the event generator configured on channel n is detected. The flag will only be set when using a synchronous or resynchronized path. In the case of asynchronous path, the INTFLAG.EVDn is always zero.

29.6.2.11 Channel Status

The Channel Status register (CHSTATUS) shows the status of the channels when using a synchronous or resynchronized path. There are two different status bits in CHSTATUS for each of the available channels:

The CHSTATUS.CHBUSYn bit will be set when an event on the corresponding channel n has not been handled by all event users connected to that channel.
The CHSTATUS.USRRDYn bit will be set when all event users connected to the corresponding channel are ready to handle incoming events on that channel.

29.6.2.12 Software Event

A software event can be initiated on a channel by setting the Channel n bit in the Software Event register (SWEVT.CHANNELn) to ‘1’. Then the software event can be serviced as any event generator; i.e., when the bit is set to ‘1’, an event will be generated on the respective channel.

29.6.3 Interrupts

The EVSYS has the following interrupt sources:

Event Detected Channel n interrupt (EVDn): for details, refer to 29.6.2.10. The Event Detected Channel n Interrupt. source has an interrupt flag which is in the Interrupt Flag Status and Clear (INTFLAG) register. The flag is set when the interrupt is issued. Each interrupt event can be individually enabled by setting a ‘1’ to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by setting a ‘1’ to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt event is generated when the interrupt flag is set and SAM L22 Family EVSYS – Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 491

the corresponding interrupt is enabled. The interrupt event works until the interrupt flag is cleared, the interrupt is disabled, or the Event System is reset. See INTFLAG for details on how to clear interrupt flags. All interrupt events from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. Refer to the Nested Vector Interrupt Controller for details. The event user must read the INTFLAG register to determine what the interrupt condition is. Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector Interrupt Controller for details.

29.6.4 Sleep Mode Operation

The EVSYS can generate interrupts to wake up the device from any sleep mode. To be able to run in standby, the Run in Standby bit in the Channel register (CHANNELn.RUNSTDBY) must be set to ‘1’. When the Generic Clock On Demand bit in Channel register (CHANNELn.ONDEMAND) is set to ‘1’ and the event generator is detected, the event channel will request its clock (GCLK_EVSYS_CHANNEL_n). The event latency for a resynchronized channel path will increase by two GCLK_EVSYS_CHANNEL_n clock (i.e., up to five GCLK_EVSYS_CHANNEL_n clock cycles). A channel will behave differently in different sleep modes regarding to CHANNELn.RUNSTDBY and CHANNELn.ONDEMAND, as shown in the table below: Table 29-1. Event Channel Sleep Behavior CHANNELn.PATH CHANNELn.ONDEM AND CHANNELn.RUNST DBY Sleep Behavior ASYNC 0 0 Only run in IDLE sleep modes if an event must be propagated. Disabled in STANDBY sleep mode. SYNC/RESYNC 0 0 N/A. Works only in Active mode. SYNC/RESYNC 0 1 Always run in IDLE and STANDBY sleep modes. SYNC/RESYNC 1 0 Only run in IDLE sleep modes if an event must be propagated. Disabled in STANDBY sleep mode. Two GCLK_EVSYS_n latency added in RESYNC path before the event is propagated internally. SYNC/RESYNC 1 1 Always run in IDLE and STANDBY sleep modes. Two GCLK_EVSYS_n latency added in RESYNC path before the event is propagated internally. Note: The ONDEMAND and RUNSTDBY bits have no effect for channels when the asynchronous path is selected. SAM L22 Family EVSYS – Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 492

29.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 SWRST 0x01 ... 0x0B Reserved 0x0C CHSTATUS 7:0 USRRDY7 USRRDY6 USRRDY5 USRRDY4 USRRDY3 USRRDY2 USRRDY1 USRRDY0 15:8 23:16 CHBUSY7 CHBUSY6 CHBUSY5 CHBUSY4 CHBUSY3 CHBUSY2 CHBUSY1 CHBUSY0 31:24 0x10 INTENCLR 7:0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 15:8 23:16 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 31:24 0x14 INTENSET 7:0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 15:8 23:16 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 31:24 0x18 INTFLAG 7:0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 15:8 23:16 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 31:24 0x1C SWEVT 7:0 CHANNEL7 CHANNEL6 CHANNEL5 CHANNEL4 CHANNEL3 CHANNEL2 CHANNEL1 CHANNEL0 15:8 23:16 31:24 0x20 CHANNEL0 7:0 EVGEN[6:0] 15:8 ONDEMAND RUNSTDBY EDGSEL[1:0] PATH[1:0] 23:16 31:24 0x24 CHANNEL1 7:0 EVGEN[6:0] 15:8 ONDEMAND RUNSTDBY EDGSEL[1:0] PATH[1:0] 23:16 31:24 0x28 CHANNEL2 7:0 EVGEN[6:0] 15:8 ONDEMAND RUNSTDBY EDGSEL[1:0] PATH[1:0] 23:16 31:24 0x2C CHANNEL3 7:0 EVGEN[6:0] 15:8 ONDEMAND RUNSTDBY EDGSEL[1:0] PATH[1:0] 23:16 31:24 0x30 CHANNEL4 7:0 EVGEN[6:0] 15:8 ONDEMAND RUNSTDBY EDGSEL[1:0] PATH[1:0] 23:16 31:24 0x34 CHANNEL5 7:0 EVGEN[6:0] 15:8 ONDEMAND RUNSTDBY EDGSEL[1:0] PATH[1:0] 23:16 31:24 0x38 CHANNEL6 7:0 EVGEN[6:0] 15:8 ONDEMAND RUNSTDBY EDGSEL[1:0] PATH[1:0] 23:16 31:24 0x3C CHANNEL7 7:0 EVGEN[6:0] 15:8 ONDEMAND RUNSTDBY EDGSEL[1:0] PATH[1:0] 23:16 31:24 SAM L22 Family EVSYS – Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 493

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x40 ... 0x7F Reserved 0x80 USER0 7:0 CHANNEL[3:0] 15:8 23:16 31:24 ... 0xF8 USER30 7:0 CHANNEL[3:0] 15:8 23:16 31:24

29.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. Refer to Register Access Protection and PAC - Peripheral Access Controller. SAM L22 Family EVSYS – Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 494

29.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 SWRST Access W Reset 0 Bit 0 – SWRST Software Reset Writing '0' to this bit has no effect. Writing '1' to this bit resets all registers in the EVSYS to their initial state. Note: Before applying a Software Reset it is recommended to disable the event generators. SAM L22 Family EVSYS – Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 495

29.8.2 Channel Status

Name: CHSTATUS Offset: 0x0C Reset: 0x00000000 Property: – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 CHBUSY7 CHBUSY6 CHBUSY5 CHBUSY4 CHBUSY3 CHBUSY2 CHBUSY1 CHBUSY0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 USRRDY7 USRRDY6 USRRDY5 USRRDY4 USRRDY3 USRRDY2 USRRDY1 USRRDY0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 1 Bits 16, 17, 18, 19, 20, 21, 22, 23 – CHBUSYn Channel Busy n [n = 0..7] This bit is cleared when channel n is idle. This bit is set if an event on channel n has not been handled by all event users connected to channel n. Bits 0, 1, 2, 3, 4, 5, 6, 7 – USRRDYn User Ready for Channel n [n = 0..7] This bit is cleared when at least one of the event users connected to the channel is not ready. This bit is set when all event users connected to channel n are ready to handle incoming events on channel n. SAM L22 Family EVSYS – Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 496

29.8.3 Interrupt Enable Clear

Name: INTENCLR Offset: 0x10 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 16, 17, 18, 19, 20, 21, 22, 23 – EVDn Event Detected Channel n Interrupt Enable [n = 0..7] Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Event Detected Channel n Interrupt Enable bit, which disables the Event Detected Channel n interrupt. Value Description 0 The Event Detected Channel n interrupt is disabled. 1 The Event Detected Channel n interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – OVRn Overrun Channel n Interrupt Enable[n = 0..7] Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Overrun Channel n Interrupt Enable bit, which disables the Overrun Channel n interrupt. Value Description 0 The Overrun Channel n interrupt is disabled. 1 The Overrun Channel n interrupt is enabled. SAM L22 Family EVSYS – Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 497

29.8.4 Interrupt Enable Set

Name: INTENSET Offset: 0x14 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 16, 17, 18, 19, 20, 21, 22, 23 – EVDn Event Detected Channel n Interrupt Enable [n = 0..7] Writing '0' to this bit has no effect. Writing '1' to this bit will set the Event Detected Channel n Interrupt Enable bit, which enables the Event Detected Channel n interrupt. Value Description 0 The Event Detected Channel n interrupt is disabled. 1 The Event Detected Channel n interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – OVRn Overrun Channel n Interrupt Enable [n = 0..7] Writing '0' to this bit has no effect. Writing '1' to this bit will set the Overrun Channel n Interrupt Enable bit, which disables the Overrun Channel n interrupt. Value Description 0 The Overrun Channel n interrupt is disabled. 1 The Overrun Channel n interrupt is enabled. SAM L22 Family EVSYS – Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 498

29.8.5 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x18 Reset: 0x00000000 Property: – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 16, 17, 18, 19, 20, 21, 22, 23 – EVDn Event Detected Channel n [n=0..7] This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and an interrupt request will be generated if INTENCLR/SET.EVDn is '1'. When the event channel path is asynchronous, the EVDn interrupt flag will not be set. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Event Detected Channel n interrupt flag. Bits 0, 1, 2, 3, 4, 5, 6, 7 – OVRn Overrun Channel n [n=0..7] This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and an interrupt request will be generated if INTENCLR/SET.OVRn is '1'. There are two possible overrun channel conditions:

One or more of the event users on channel n are not ready when a new event occurs.
An event happens when the previous event on channel n has not yet been handled by all event users. When the event channel path is asynchronous, the OVRn interrupt flag will not be set. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Overrun Detected Channel n interrupt flag. SAM L22 Family EVSYS – Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 499

29.8.6 Software Event

Name: SWEVT Offset: 0x1C Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CHANNEL7 CHANNEL6 CHANNEL5 CHANNEL4 CHANNEL3 CHANNEL2 CHANNEL1 CHANNEL0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 – CHANNELn Channel n Software [n=0..7] Selection Writing '0' to this bit has no effect. Writing '1' to this bit will trigger a software event for the channel n. These bits will always return zero when read. SAM L22 Family EVSYS – Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 500

29.8.7 Channel n

Name: CHANNELn Offset: 0x20 + n*0x04 [n=0..7] Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to configure channel n. To write to this register, do a single, 32-bit write of all the configuration data. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 ONDEMAND RUNSTDBY EDGSEL[1:0] PATH[1:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EVGEN[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 15 – ONDEMAND Generic Clock On Demand Value Description

0 Generic clock for a channel is always on, if the channel is configured and generic clock source is

enabled.

1 Generic clock is requested on demand while an event is handled

Bit 14 – RUNSTDBY Run in Standby This bit is used to define the behavior during standby sleep mode. Value Description 0 The channel is disabled in standby sleep mode. 1 The channel is not stopped in standby sleep mode and depends on the CHANNEL.ONDEMAND Bits 11:10 – EDGSEL[1:0] Edge Detection Selection These bits set the type of edge detection to be used on the channel. These bits must be written to zero when using the asynchronous path. Value Name Description 0x0 NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x1 RISING_EDGE Event detection only on the rising edge of the signal from the event generator 0x2 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator 0x3 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator Bits 9:8 – PATH[1:0] Path Selection These bits are used to choose which path will be used by the selected channel. The path choice can be limited by the channel source, see the table in 29.8.8. USERm. Value Name Description 0x0 SYNCHRONOUS Synchronous path 0x1 RESYNCHRONIZED Resynchronized path SAM L22 Family EVSYS – Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 501

0x2 ASYNCHRONOUS Asynchronous path 0x3 - Reserved Bits 6:0 – EVGEN[6:0] Event Generator These bits are used to choose the event generator to connect to the selected channel. Value Event Generator Description 0x00 NONE No event generator selected 0x01 OSCCTRL_CFD Clock Failure Detection 0x02 OSC32KCTRL_CFD Clock Failure Detection 0x03 RTC CMP0 Compare 0 (mode 0 and 1) or Alarm 0 (mode 2) 0x04 RTC CMP1 Compare 1 0x05 RTC_TAMPER Tamper Detection 0x06 RTC OVF Overflow 0x07 RTC PER0 Period 0 0x08 RTC PER1 Period 1 0x09 RTC PER2 Period 2 0x0A RTC PER3 Period 3 0x0B RTC PER4 Period 4 0x0C RTC PER5 Period 5 0x0D RTC PER6 Period 6 0x0E RTC PER7 Period 7 0x0F EIC EXTINT0 External Interrupt 0 0x10 EIC EXTINT1 External Interrupt 1 0x11 EIC EXTINT2 External Interrupt 2 0x12 EIC EXTINT3 External Interrupt 3 0x13 EIC EXTINT4 External Interrupt 4 0x14 EIC EXTINT5 External Interrupt 5 0x15 EIC EXTINT6 External Interrupt 6 0x16 EIC EXTINT7 External Interrupt 7 0x17 EIC EXTINT8 External Interrupt 8 0x18 EIC EXTINT9 External Interrupt 9 0x19 EIC EXTINT10 External Interrupt 10 0x1A EIC EXTINT11 External Interrupt 11 0x1B EIC EXTINT12 External Interrupt 12 0x1C EIC EXTINT13 External Interrupt 13 0x1D EIC EXTINT14 External Interrupt 14 0x1E EIC EXTINT15 External Interrupt 15 0x1F DMAC CH0 Channel 0 0x20 DMAC CH1 Channel 1 0x21 DMAC CH2 Channel 2 0x22 DMAC CH3 Channel 3 0x23 TCC0_OVF Overflow 0x24 TCC0_TRG Trig 0x25 TCC0_CNT Counter 0x26 TCC0_MC0 Match/Capture 0 0x27 TCC0_MC0 Match/Capture 1 0x28 TCC0_MC0 Match/Capture 2 0x29 TCC0_MC0 Match/Capture 3 0x2A TC0 OVF Overflow/Underflow 0x2B TC0 MC0 Match/Capture 0 0x2C TC0 MC0 Match/Capture 1 0x2D TC1 OVF Overflow/Underflow 0x2E TC1 MC0 Match/Capture 0 SAM L22 Family EVSYS – Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 502

Value Event Generator Description 0x2F TC1 MC0 Match/Capture 1 0x30 TC2 OVF Overflow/Underflow 0x31 TC2 MC0 Match/Capture 0 0x32 TC2 MC0 Match/Capture 1 0x33 TC3 OVF Overflow/Underflow 0x34 TC3 MC0 Match/Capture 0 0x35 TC3 MC0 Match/Capture 1 0x36 ADC RESRDY Result Ready 0x37 ADC WINMON Window Monitor 0x38 AC COMP0 Comparator 0 0x39 AC COMP1 Comparator 1 0x3A AC WIN0 Window 0 0x3B PTC EOC End of Conversion 0x3C PTC WCOMP Window Comparator 0x3D SLCD_FC0 Frame Counter 0 overflow 0x3E SCLD_FC1 Frame Counter 1 overflow 0x3F SLCD_FC2 Frame Counter 2 overflow 0x41 TRNG READY Data Ready 0x42 CCL LUTOUT0 CCL output 0x43 CCL LUTOUT1 CCL output 0x44 CCL LUTOUT2 CCL output 0x45 CCL LUTOUT3 CCL output 0x46 PAC ACCERR Access Error 0x47-0x7F Reserved SAM L22 Family EVSYS – Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 503

29.8.8 Event User m

Name: USERm Offset: 0x80 + m*0x04 [m=0..30] Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CHANNEL[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 3:0 – CHANNEL[3:0] Channel Event Selection These bits are used to select the channel to connect to the event user. Note that to select channel m, the value (m+1) must be written to the USER.CHANNEL bit group. Value Channel Number 0x00 No channel output selected 0x01 0 0x02 1 0x03 2 0x04 3 0x05 4 0x06 5 0x07 6 0x08 7 0x09-0xFF Reserved Table 29-2. User Multiplexer Number USERm User Multiplexer Description Path Type m = 0 RTC TAMPEVT Tamper Event Asynchronous, synchronous, and resynchronized paths m = 1 PORT EV0 Event 0 Asynchronous, synchronous, and resynchronized paths m = 2 PORT EV1 Event 1 Asynchronous, synchronous, and resynchronized paths SAM L22 Family EVSYS – Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 504

USERm User Multiplexer Description Path Type m = 3 PORT EV2 Event 2 Asynchronous, synchronous, and resynchronized paths m = 4 PORT EV3 Event 3 Asynchronous, synchronous, and resynchronized paths m = 5 DMAC CH0 Channel 0 Synchronous, and resynchronized paths m = 6 DMAC CH1 Channel 1 Synchronous, and resynchronized paths m = 7 DMAC CH2 Channel 2 Synchronous, and resynchronized paths m = 8 DMAC CH3 Channel 3 Synchronous, and resynchronized paths m = 9 TCC0 EV0 - Asynchronous, synchronous, and resynchronized paths m = 10 TCC0 EV1 - Asynchronous, synchronous, and resynchronized paths m = 11 TCC0 MC0 Match/Capture 0 Asynchronous, synchronous, and resynchronized paths m = 12 TCC0 MC1 Match/Capture 1 Asynchronous, synchronous, and resynchronized paths m = 13 TCC0 MC2 Match/Capture 2 Asynchronous, synchronous, and resynchronized paths m = 14 TCC0 MC3 Match/Capture 3 Asynchronous, synchronous, and resynchronized paths m = 15 TC0 - Asynchronous, synchronous, and resynchronized paths m = 16 TC1 - Asynchronous, synchronous, and resynchronized paths m = 17 TC2 - Asynchronous, synchronous, and resynchronized paths m = 18 TC3 - Asynchronous, synchronous, and resynchronized paths m = 19 ADC START ADC start conversion Asynchronous, synchronous, and resynchronized paths m = 20 ADC SYNC Flush ADC Asynchronous, synchronous, and resynchronized paths m = 21 AC COMP0 Start comparator 0 Asynchronous, synchronous, and resynchronized paths SAM L22 Family EVSYS – Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 505

USERm User Multiplexer Description Path Type m = 22 AC COMP1 Start comparator 1 Asynchronous, synchronous, and resynchronized paths m = 23 PTC STCONV PTC start conversion Asynchronous, synchronous, and resynchronized paths m = 24 CCL LUTIN 0 CCL input Asynchronous, synchronous, and resynchronized paths m = 25 CCL LUTIN 1 CCL input Asynchronous, synchronous, and resynchronized paths m = 26 CCL LUTIN 2 CCL input Asynchronous, synchronous, and resynchronized paths m = 27 CCL LUTIN 3 CCL input Asynchronous, synchronous, and resynchronized paths m = 29 MTB START Tracing start Asynchronous, synchronous, and resynchronized paths m = 30 MTB STOP Tracing stop Asynchronous, synchronous, and resynchronized paths SAM L22 Family EVSYS – Event System © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 506

SERCOM – Serial Communication Interface

30.1 Overview

There are up to six instances of the Serial Communication interface (SERCOM) peripheral. A SERCOM can be configured to support a number of modes: I2C, SPI, and USART. When an instance of SERCOM is configured and enabled, all of the resources of that SERCOM instance will be dedicated to the selected mode. The SERCOM serial engine consists of a transmitter and receiver, baud-rate generator and address matching functionality. It can use the internal generic clock or an external clock. Using an external clock allows the SERCOM to be operated in all Sleep modes.

30.2 Features

Interface for Configuring into one of the following (selected by CTRLA.MODE[2:0]): – Inter-Integrated Circuit (I 2C) two-wire serial interface – System Management Bus (SMBus ™) compatible – Serial Peripheral Interface (SPI) – Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
Single Transmit Buffer and Double Receive Buffer
Baud-rate Generator
Address Match/mask Logic
Operational in all Sleep modes with an External Clock Source
Can be used with DMA See the Related Links for full feature lists of the interface configurations.

30.3 Block Diagram

Figure 30-1. SERCOM Block Diagram TX/RX DATACONTROL/STATUS Mode n SERCOM BAUD/ADDR Transmitter Register Interface Serial Engine Receiver Mode 0 Mode 1 Baud Rate Generator Address Match Mode Specific PAD[3:0]

30.4 Signal Description

See the respective SERCOM mode chapters for details. SAM L22 Family SERCOM – Serial Communication Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 507

30.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

30.5.1 I/O Lines

Using the SERCOM I/O lines requires the I/O pins to be configured using port configuration (PORT). The PORT Control bit (PINCFGn.DRVSTR) is still effective for the SERCOM output pins. The PORT Control bit (PINCFGn.PULLEN) is still effective on the SERCOM input pins, but is limited to the enabling or disabling of a pull down only (it is not possible to enable or disable a pull up) The SERCOM has four internal pads, PAD[3:0], and the signals from I2C, SPI, and USART are routed through these SERCOM pads, through a multiplexer. The configuration of the multiplexer is available from the different SERCOM modes. Refer to the mode-specific chapters for additional information.

30.5.2 Power Management

The SERCOM can operate in any Sleep mode provided the selected clock source is running. SERCOM interrupts can be configured to wake the device from sleep modes.

30.5.3 Clocks

The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Main Clock Controller. Refer to Peripheral Clock Masking for details and default status of this clock. The SERCOM uses two generic clocks: GCLK_SERCOMx_CORE and GCLK_SERCOMx_SLOW. The core clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while working as a host. The slow clock (GCLK_SERCOMx_SLOW) is only required for certain functions. See specific mode chapters for details. These clocks must be configured and enabled in the Generic Clock Controller (GCLK) before using the SERCOM. The generic clocks are asynchronous to the user interface clock (CLK_SERCOMx_APB). Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains. Refer to 30.6.8. Synchronization for details.

30.5.4 DMA

The DMA request lines are connected to the DMA Controller (DMAC). The DMAC must be configured before the SERCOM DMA requests are used.

30.5.5 Interrupts

The interrupt request line is connected to the Interrupt Controller (NVIC). The NVIC must be configured before the SERCOM interrupts are used.

30.5.6 Events

Not applicable.

30.5.7 Debug Operation

When the CPU is halted in Debug mode, this peripheral will continue normal operation. If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result during debugging. This peripheral can be forced to halt operation during debugging - refer to the Debug Control (DBGCTRL) register for details.

30.5.8 Register Access Protection

Registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC). Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. PAC write protection does not apply to accesses through an external debugger. SAM L22 Family SERCOM – Serial Communication Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 508

30.5.9 Analog Connections

Not applicable.

30.6 Functional Description

30.6.1 Principle of Operation

The basic structure of the SERCOM serial engine is shown in SERCOM Serial Engine. Labels in capital letters are synchronous to the system clock and accessible by the CPU; labels in lowercase letters can be configured to run on the GCLK_SERCOMx_CORE clock or an external clock. Figure 30-2. SERCOM Serial Engine Transmitter Baud Rate Generator Equal Selectable Internal Clk (GCLK) Ext Clk Receiver Address Match Baud Rate Generator TX Shift Register RX Shift Register RX BufferStatus BAUD TX DATA ADDR/ADDRMASK RX DATASTATUS 1/- /2- /16 The transmitter consists of a single write buffer and a Shift register. The receiver consists of a one-level (I2C), or two-level (USART, SPI) receive buffer and a Shift register. The baud-rate generator is capable of running on the GCLK_SERCOMx_CORE clock or an external clock. Address matching logic is included for SPI and I2C operation.

30.6.2 Basic Operation

30.6.2.1 Initialization

The SERCOM must be configured to the desired mode by writing the Operating Mode bits in the Control A register (CTRLA.MODE) as shown in the table below. Table 30-1. SERCOM Modes CTRLA.MODE Description 0x0 USART with external clock 0x1 USART with internal clock 0x2 SPI in client operation 0x3 SPI in host operation 0x4 I2C client operation SAM L22 Family SERCOM – Serial Communication Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 509

CTRLA.MODE Description 0x5 I2C host operation 0x6-0x7 Reserved For further initialization information, see the respective SERCOM mode chapters:

30.6.2.2 Enabling, Disabling, and Resetting

This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and disabled by writing '0' to it. Writing ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of this peripheral to their initial states, except the DBGCTRL register, and the peripheral is disabled. Refer to the CTRLA register description for details.

30.6.2.3 Clock Generation – Baud-Rate Generator

The baud-rate generator, as shown in the following figure, generates internal clocks for asynchronous and synchronous communication. The output frequency (fBAUD) is determined by the Baud register (BAUD) setting and the baud reference frequency (fref). The baud reference clock is the serial engine clock, and it can be internal or external. For asynchronous communication, the /16 (divide-by-16) output is used when transmitting, whereas the /1 (divide- by-1) output is used while receiving. For synchronous communication, the /2 (divide-by-2) output is used. This functionality is automatically configured, depending on the selected operating mode. Figure 30-3. Baud Rate Generator Base Period Selectable Internal Clk (GCLK) Ext Clk CTRLA.MODE[0] fref Clock Recovery Tx Clk Rx Clk CTRLA.MODE /2 /8 /1 /2 /16 Baud Rate Generator The following table contains equations for the baud rate (in bits per second) and the BAUD register value for each operating mode. For asynchronous operation, there are two modes:

Arithmetic mode: the BAUD register value is 16 bits (0 to 65,535)
Fractional mode: the BAUD register value is 13 bits, while the fractional adjustment is 3 bits. In this mode the BAUD setting must be greater than or equal to 1. For synchronous operation, the BAUD register value is 8 bits (0 to 255). SAM L22 Family SERCOM – Serial Communication Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 510

Table 30-2. Baud Rate Equations Operating Mode Condition Baud Rate (Bits Per Second) BAUD Register Value Calculation Asynchronous Arithmetic f B AU D ≤ f r e f 16 f B AU D = f r e f 16 1 − B AU D

65536 B AU D = 65536 ⋅ 1 − S ⋅ f B AU D

Fractional f B AU D ≤ f r e f S f B AU D = f r e f S ⋅ B AU D + FP B A U D = f r e f S ⋅ f B AU D − F P Synchronous f B AU D ≤ f r e f 2 f B AU D = f re f 2 ⋅ B AU D + 1 B AU D = f r e f 2 ⋅ f B AU D − 1 S - Number of samples per bit, which can be 16, 8, or 3. The Asynchronous Fractional option is used for auto-baud detection. The baud rate error is represented by the following formula: Error = 1 − ExpectedBaudRate ActualBaudRate

30.6.2.3.1 Asynchronous Arithmetic Mode BAUD Value Selection

The formula given for fBAUD calculates the average frequency over 65536 fref cycles. Although the BAUD register can be set to any value between 0 and 65536, the actual average frequency of fBAUD over a single frame is more granular. The BAUD register values that will affect the average frequency over a single frame lead to an integer increase in the cycles per frame (CPF) C PF = f r e f f B AU D D + S where

D represent the data bits per frame
S represent the sum of start and first stop bits, if present. The following table shows the BAUD register value versus baud frequency fBAUD at a serial engine frequency of 48 MHz. This assumes a D value of 8 bits and an S value of 2 bits (10 bits, including start and stop bits). Table 30-3. BAUD Register Value vs. Baud Frequency BAUD Register Value Serial Engine CPF fBAUD at 100MHz Serial Engine Frequency (fREF) 0 – 406 161 6.211 MHz 407 – 808 162 6.211 MHz 809 – 1205 163 6.173 MHz 65206 31775 31.47 kHz 65207 31872 31.38 kHz 65208 31969 31.28 kHz

30.6.3 Additional Features

30.6.3.1 Address Match and Mask

The SERCOM address match and mask feature is capable of matching either one address, two unique addresses, or a range of addresses with a mask, based on the mode selected. The match uses seven or eight bits, depending on the mode. SAM L22 Family SERCOM – Serial Communication Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 511

30.6.3.1.1 Address With Mask

An address written to the Address bits in the Address register (ADDR.ADDR), and a mask written to the Address Mask bits in the Address register (ADDR.ADDRMASK) will yield an address match. All bits that are masked are not included in the match. Note that writing the ADDR.ADDRMASK to 'all zeros' will match a single unique address, while writing ADDR.ADDRMASK to 'all ones' will result in all addresses being accepted. Figure 30-4. Address With Mask rx shift register ADDRMASK ADDR == Match

30.6.3.1.2 Two Unique Addresses

The two addresses written to ADDR and ADDRMASK will cause a match. Figure 30-5. Two Unique Addresses ADDRMASK rx shift register ADDR Match

30.6.3.1.3 Address Range

The range of addresses between and including ADDR.ADDR and ADDR.ADDRMASK will cause a match. ADDR.ADDR and ADDR.ADDRMASK can be set to any two addresses, with ADDR.ADDR acting as the upper limit and ADDR.ADDRMASK acting as the lower limit. Figure 30-6. Address Range ADDRMASK rx shift register ADDR == Match

30.6.4 DMA Operation

The available DMA interrupts and their depend on the operation mode of the SERCOM peripheral. Refer to the Functional Description sections of the respective SERCOM mode.

30.6.5 Interrupts

Interrupt sources are mode specific. See the respective SERCOM mode chapters for details. Each interrupt source has its own Interrupt flag. The Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the Interrupt condition is met. Each interrupt can be individually enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the Interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until either the Interrupt flag is cleared, the interrupt is disabled, or the SERCOM is reset. For details on clearing Interrupt flags, refer to the INTFLAG register description. SAM L22 Family SERCOM – Serial Communication Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 512

The value of INTFLAG indicates which Interrupt condition occurred. The user must read the INTFLAG register to determine which Interrupt condition is present. Note: Interrupts must be globally enabled for interrupt requests to be generated.

30.6.6 Events

Not applicable.

30.6.7 Sleep Mode Operation

The peripheral can operate in any Sleep mode where the selected serial clock is running. This clock can be external or generated by the internal baud-rate generator. The SERCOM interrupts can be used to wake-up the device from Sleep modes. Refer to the different SERCOM mode chapters for details.

30.6.8 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. Required write synchronization is denoted by the "Write-Synchronized" property in the register description. Required read synchronization is denoted by the "Read-Synchronized" property in the register description. SAM L22 Family SERCOM – Serial Communication Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 513

SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter

31.1 Overview

The Universal Synchronous and Asynchronous Receiver and Transmitter (USART) is one of the available modes in the Serial Communication Interface (SERCOM). The USART uses the SERCOM transmitter and receiver, see 31.3. Block Diagram. Labels in uppercase letters are synchronous to CLK_SERCOMx_APB and accessible for CPU. Labels in lowercase letters can be programmed to run on the internal generic clock or an external clock. The transmitter consists of a single write buffer, a shift register, and control logic for different frame formats. The write buffer support data transmission without any delay between frames. The receiver consists of a two-level receive buffer and a shift register. Status information of the received data is available for error checking. Data and clock recovery units ensure robust synchronization and noise filtering during asynchronous data reception. References: SERCOM - Serial Communication Interface SERCOM USART and I2C Configurations

31.2 USART Features

Full-duplex operation
Asynchronous (with clock reconstruction) or synchronous operation
Internal or external clock source for asynchronous and synchronous operation
Baud-rate generator
Supports serial frames with 5, 6, 7, 8 or 9 data bits and 1 or 2 stop bits
Odd or even parity generation and parity check
Selectable LSB- or MSB-first data transfer
Buffer overflow and frame error detection
Noise filtering, including false start-bit detection and digital low-pass filter
Collision detection
Can operate in all sleep modes
Operation at speeds up to half the system clock for internally generated clocks
Operation at speeds up to the system clock for externally generated clocks
RTS and CTS flow control
IrDA modulation and demodulation up to 115.2kbps
Start-of-frame detection
Can work with DMA References:

31.3 Block Diagram

Figure 31-1. USART Block Diagram GCLK (internal) XCK BAUD baud rate generator /1 - /2 - /16 TX DATA tx shift register rx shift register STATUS status RX DATA rx buffer TxD RxD

31.4 Signal Description

Table 31-1. SERCOM USART Signals Signal Name Type Description PAD[3:0] Digital I/O General SERCOM pins One signal can be mapped to one of several pins. References: I/O Multiplexing and Considerations

31.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

31.5.1 I/O Lines

Using the USART’s I/O lines requires the I/O pins to be configured using the I/O Pin Controller (PORT). When the SERCOM is used in USART mode, the SERCOM controls the direction and value of the I/O pins according to the table below. PORT Control bit PINCFGn.DRVSTR is still effective for the SERCOM output pins. PORT Control bit PINCFGn.PULLEN is still effective on the SERCOM input pins, but is limited to the enabling/disabling of a pull down only (it is not possible to enable/disable a pull up). If the receiver or transmitter is disabled, these pins can be used for other purposes. Table 31-2. USART Pin Configuration Pin Pin Configuration TxD Output RxD Input XCK Output or input The combined configuration of PORT and the Transmit Data Pinout and Receive Data Pinout bit fields in the Control A register (CTRLA.TXPO and CTRLA.RXPO, respectively) will define the physical position of the USART signals in the previous table USART Pin Configuration. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 515

References: 28. PORT - I/O Pin Controller

31.5.2 Power Management

This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake up the device from sleep modes. References: PM - Power Manager

31.5.3 Clocks

The SERCOM bus clock (CLK_SERCOMx_APB) is enabled by default, and can be disabled and enabled in the Main Clock Controller. Refer to Peripheral Clock Masking for details. A generic clock (GCLK_SERCOMx_CORE) is required to clock the SERCOMx_CORE. This clock must be configured and enabled in the Generic Clock Controller before using the SERCOMx_CORE. Refer to 15. GCLK - Generic Clock Controller for details. This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Therefore, writing to certain registers

31.5.4 DMA

The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with this peripheral the DMAC must be configured first. Refer to the DMAC - Direct Memory Access Controller for details.

31.5.5 Interrupts

The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral, the Interrupt Controller (NVIC) must be configured first. Refer to the Nested Vector Interrupt Controller for details.

31.5.6 Events

Not applicable.

31.5.7 Debug Operation

31.5.8 Register Access Protection

Registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC). PAC Write-Protection is not available for the following registers:

Interrupt Flag Clear and Status register (INTFLAG)
Status register (STATUS)
Data register (DATA) Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger. References: PAC

31.5.9 Analog Connections

31.6 Functional Description

31.6.1 Principle of Operation

The USART uses the following lines for data transfer:

RxD for receiving
TxD for transmitting
XCK for the transmission clock in synchronous operation USART data transfer is frame based. A serial frame consists of:
1 start bit
From 5 to 9 data bits (MSB or LSB first)
No, even or odd parity bit
1 or 2 stop bits A frame starts with the start bit followed by one character of data bits. If enabled, the parity bit is inserted after the data bits and before the first stop bit. After the stop bit(s) of a frame, either the next frame can follow immediately, or the communication line can return to the idle (high) state. The figure below illustrates the possible frame formats. Brackets denote optional bits. Figure 31-2. Frame Formats Frame (IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] [St/IDL] St Start bit. Signal is always low. n, [n] Data bits. 0 to [5..9] [P] Parity bit. Either odd or even. Sp, [Sp] Stop bit. Signal is always high. IDLE No frame is transferred on the communication line. Signal is always high in this state.

31.6.2 Basic Operation

31.6.2.1 Initialization

The following registers are enable-protected, meaning they can only be written when the USART is disabled (CTRL.ENABLE=0):

Control A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits.
Control B register (CTRLB), except the Receiver Enable (RXEN) and Transmitter Enable (TXEN) bits.
Baud register (BAUD) When the USART is enabled or is being enabled (CTRLA.ENABLE=1), any writing attempt to these registers will be discarded. If the peripheral is being disabled, writing to these registers will be executed after disabling is completed. Enable-protection is denoted by the "Enable-Protection" property in the register description. Before the USART is enabled, it must be configured by these steps: 1. Select either external (0x0) or internal clock (0x1) by writing the Operating Mode value in the CTRLA register (CTRLA.MODE). 2. Select either asynchronous (0) or or synchronous (1) communication mode by writing the Communication Mode bit in the CTRLA register (CTRLA.CMODE). SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 517

Select pin for receive data by writing the Receive Data Pinout value in the CTRLA register (CTRLA.RXPO). 4. Select pads for the transmitter and external clock by writing the Transmit Data Pinout bit in the CTRLA register (CTRLA.TXPO). 5. Configure the Character Size field in the CTRLB register (CTRLB.CHSIZE) for character size. 6. Set the Data Order bit in the CTRLA register (CTRLA.DORD) to determine MSB- or LSB-first data transmission. 7. To use parity mode: a. Enable parity mode by writing 0x1 to the Frame Format field in the CTRLA register (CTRLA.FORM). b. Configure the Parity Mode bit in the CTRLB register (CTRLB.PMODE) for even or odd parity. 8. Configure the number of stop bits in the Stop Bit Mode bit in the CTRLB register (CTRLB.SBMODE). 9. When using an internal clock, write the Baud register (BAUD) to generate the desired baud rate. 10. Enable the transmitter and receiver by writing '1' to the Receiver Enable and Transmitter Enable bits in the CTRLB register (CTRLB.RXEN and CTRLB.TXEN).

31.6.2.2 Enabling, Disabling, and Resetting

31.6.2.3 Clock Generation and Selection

For both synchronous and asynchronous modes, the clock used for shifting and sampling data can be generated internally by the SERCOM baud-rate generator or supplied externally through the XCK line. The synchronous mode is selected by writing a '1' to the Communication Mode bit in the Control A register (CTRLA.CMODE), the asynchronous mode is selected by writing a zero to CTRLA.CMODE. The internal clock source is selected by writing 0x1 to the Operation Mode bit field in the Control A register (CTRLA.MODE), the external clock source is selected by writing 0x0 to CTRLA.MODE. The SERCOM baud-rate generator is configured as shown in the following figure. In asynchronous mode (CTRLA.CMODE=0), the 16-bit Baud register value is used. In synchronous mode (CTRLA.CMODE=1), the eight LSBs of the Baud register are used. Refer to Clock Generation - Baud Rate Generator for details on configuring the baud rate. Figure 31-3. Clock Generation XCK CTRLA.MODE[0] XCKInternal Clk (GCLK) Baud Rate Generator Base Period /2 /8 /2 /8/1 Tx Clk Rx Clk CTRLA.CMODE References: Clock Generation - Baud Rate Generator Asynchronous Arithmetic Mode BAUD Value Selection SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 518

Synchronous Clock Operation In synchronous mode, the CTRLA.MODE bit field determines whether the transmission clock line (XCK) serves either as input or output. The dependency between clock edges, data sampling, and data change is the same for internal and external clocks. Data input on the RxD pin is sampled at the opposite XCK clock edge when data is driven on the TxD pin. The Clock Polarity bit in the Control A register (CTRLA.CPOL) selects which XCK clock edge is used for RxD sampling, and which is used for TxD change: When CTRLA.CPOL is '0', the data will be changed on the rising edge of XCK, and sampled on the falling edge of XCK. When CTRLA.CPOL is '1', the data will be changed on the falling edge of XCK, and sampled on the rising edge of XCK. Figure 31-4. Synchronous Mode XCK Timing XCK RxD / TxD CTRLA.CPOL=1 Change Sample XCK RxD / TxD CTRLA.CPOL=0 Change Sample When the clock is provided through XCK (CTRLA.MODE=0x0), the shift registers operate directly on the XCK clock. This means that XCK is not synchronized with the system clock and, therefore, can operate at frequencies up to the system frequency.

31.6.2.4 Data Register

The USART Transmit Data register (TxDATA) and USART Receive Data register (RxDATA) share the same I/O address, referred to as the Data register (DATA). Writing the DATA register will update the TxDATA register. Reading the DATA register will return the contents of the RxDATA register.

31.6.2.5 Data Transmission

Data transmission is initiated by writing the data to be sent into the DATA register. Then, the data in TxDATA will be moved to the shift register when the shift register is empty and ready to send a new frame. After the shift register is loaded with data, the data frame will be transmitted. When the entire data frame including stop bit(s) has been transmitted and no new data was written to DATA, the Transmit Complete interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set, and the optional interrupt will be generated. The Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) indicates that the register is empty and ready for new data. The DATA register should only be written to when INTFLAG.DRE is set. Disabling the Transmitter The transmitter is disabled by writing '0' to the Transmitter Enable bit in the CTRLB register (CTRLB.TXEN). Disabling the transmitter will complete only after any ongoing and pending transmissions are completed, i.e., there is no data in the transmit shift register and TxDATA to transmit.

31.6.2.6 Data Reception

The receiver accepts data when a valid start bit is detected. Each bit following the start bit will be sampled according to the baud rate or XCK clock, and shifted into the receive shift register until the first stop bit of a frame is received. The second stop bit will be ignored by the receiver. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 519

When the first stop bit is received and a complete serial frame is present in the receive shift register, the contents of the shift register will be moved into the two-level receive buffer. Then, the Receive Complete interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set, and the optional interrupt will be generated. The received data can be read from the DATA register when the Receive Complete interrupt flag is set. Disabling the Receiver Writing '0' to the Receiver Enable bit in the CTRLB register (CTRLB.RXEN) will disable the receiver, flush the two-level receive buffer, and data from ongoing receptions will be lost. Error Bits The USART receiver has three error bits in the Status (STATUS) register: Frame Error (FERR), Buffer Overflow (BUFOVF), and Parity Error (PERR). Once an error happens, the corresponding error bit will be set until it is cleared by writing ‘1’ to it. These bits are also cleared automatically when the receiver is disabled. There are two methods for buffer overflow notification, selected by the Immediate Buffer Overflow Notification bit in the Control A register (CTRLA.IBON): When CTRLA.IBON=1, STATUS.BUFOVF is raised immediately upon buffer overflow. Software can then empty the receive FIFO by reading RxDATA, until the receiver complete interrupt flag (INTFLAG.RXC) is cleared. When CTRLA.IBON=0, the buffer overflow condition is attending data through the receive FIFO. After the received data is read, STATUS.BUFOVF will be set along with INTFLAG.RXC. Asynchronous Data Reception The USART includes a clock recovery and data recovery unit for handling asynchronous data reception. The clock recovery logic can synchronize the incoming asynchronous serial frames at the RxD pin to the internally generated baud-rate clock. The data recovery logic samples and applies a low-pass filter to each incoming bit, thereby improving the noise immunity of the receiver. Asynchronous Operational Range The operational range of the asynchronous reception depends on the accuracy of the internal baud-rate clock, the rate of the incoming frames, and the frame size (in number of bits). In addition, the operational range of the receiver is depending on the difference between the received bit rate and the internally generated baud rate. If the baud rate of an external transmitter is too high or too low compared to the internally generated baud rate, the receiver will not be able to synchronize the frames to the start bit. There are two possible sources for a mismatch in baud rate: First, the reference clock will always have some minor instability. Second, the baud-rate generator cannot always do an exact division of the reference clock frequency to get the baud rate desired. In this case, the BAUD register value should be set to give the lowest possible error. Refer to Clock Generation - Baud-Rate Generator for details. Recommended maximum receiver baud-rate errors for various character sizes are shown in the table below. Table 31-3. Asynchronous Receiver Error for 16-fold Oversampling D (Data bits+Parity) RSLOW [%] RFAST [%] Max. total error [%] Recommended max. Rx error [%] SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 520

The following equations calculate the ratio of the incoming data rate and internal receiver baud rate: R SLOW = D + 1 S S − 1 + D ⋅ S + S F , R FAST = D + 2 S D + 1 S + S M

RSLOW is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate
RFAST is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate
D is the sum of character size and parity size (D = 5 to 10 bits)
S is the number of samples per bit (S = 16, 8 or 3)
SF is the first sample number used for majority voting (SF = 7, 3, or 2) when CTRLA.SAMPA=0.
SM is the middle sample number used for majority voting (SM = 8, 4, or 2) when CTRLA.SAMPA=0. The recommended maximum Rx Error assumes that the receiver and transmitter equally divide the maximum total error. Its connection to the SERCOM Receiver error acceptance is depicted in this figure: Figure 31-5. USART Rx Error Calculation + + Error Max (%) Error Min (%) Baud Rate SERCOM Receiver error acceptance from RSLOW and RFAST formulas Baud Generator offset error depends on BAUD register value Clock source error Recommended max. Rx Error (%) The recommendation values in the table above accommodate errors of the clock source and the baud generator. The following figure gives an example for a baud rate of 3Mbps: Figure 31-6. USART Rx Error Calculation Example + + Error Max 3.3% Error Min -4.35% Baud Rate 3Mbps SERCOM Receiver error acceptance sampling = x16 data bits = 10 parity = 0 start bit = stop bit = 1 No baud generator offset error Fbaud(3Mbps) = 48MHz *1(BAUD=0) /16 DFLL source at 3MHz +/-0.3% Recommended max. Rx Error +/-1.5% (example) Error Max 3.3% Error Min -4.35% Error Max 3.0% Error Min -4.05% Transmitter Error* Accepted Receiver Error security margin *Transmitter Error depends on the external transmitter used in the application. It is advised that it is within the Recommended max. Rx Error (+/-1.5% in this example). Larger Transmitter Errors are acceptable but must lie within the Accepted Receiver Error. References: Clock Generation - Baud-Rate Generator Asynchronous Arithmetic Mode BAUD Value Selection

31.6.3 Additional Features

31.6.3.1 Parity

Even or odd parity can be selected for error checking by writing 0x1 to the Frame Format bit field in the Control A register (CTRLA.FORM). If even parity is selected (CTRLB.PMODE=0), the parity bit of an outgoing frame is '1' if the data contains an odd number of bits that are '1', making the total number of '1' even. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 521

If odd parity is selected (CTRLB.PMODE=1), the parity bit of an outgoing frame is '1' if the data contains an even number of bits that are '0', making the total number of '1' odd. When parity checking is enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit of the corresponding frame. If a parity error is detected, the Parity Error bit in the Status register (STATUS.PERR) is set.

31.6.3.2 Hardware Handshaking

The USART features an out-of-band hardware handshaking flow control mechanism, implemented by connecting the RTS and CTS pins with the remote device, as shown in the figure below. Figure 31-7. Connection with a Remote Device for Hardware Handshaking RXD CTS RTS USART TXD RTS CTS Remote Device TXD RXD Hardware handshaking is only available in the following configuration:

USART with internal clock (CTRLA.MODE=1),
Asynchronous mode (CTRLA.CMODE=0),
and Flow control pinout (CTRLA.TXPO=2). When the receiver is disabled or the receive FIFO is full, the receiver will drive the RTS pin high. This notifies the remote device to stop transfer after the ongoing transmission. Enabling and disabling the receiver by writing to CTRLB.RXEN will set/clear the RTS pin after a synchronization delay. When the receive FIFO goes full, RTS will be set immediately and the frame being received will be stored in the shift register until the receive FIFO is no longer full. Figure 31-8. Receiver Behavior when Operating with Hardware Handshaking RTS Rx FIFO Full RXD RXEN The current CTS Status is in the STATUS register (STATUS.CTS). Character transmission will start only if STATUS.CTS=0. When CTS is set, the transmitter will complete the ongoing transmission and stop transmitting. Figure 31-9. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD

31.6.3.3 IrDA Modulation and Demodulation

Transmission and reception can be encoded IrDA compliant up to 115.2 kb/s. IrDA modulation and demodulation work in the following configuration:

IrDA encoding enabled (CTRLB.ENC=1),
Asynchronous mode (CTRLA.CMODE=0),
and 16x sample rate (CTRLA.SAMPR[0]=0). During transmission, each low bit is transmitted as a high pulse. The pulse width is 3/16 of the baud rate period, as illustrated in the figure below. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 522

Figure 31-10. IrDA Transmit Encoding IrDA encoded TXD TXD 1 baud clock 3/16 baud clock The reception decoder has two main functions. The first is to synchronize the incoming data to the IrDA baud rate counter. Synchronization is performed at the start of each zero pulse. The second main function is to decode incoming Rx data. If a pulse width meets the minimum length set by configuration (RXPL.RXPL), it is accepted. When the baud rate counter reaches its middle value (1/2 bit length), it is transferred to the receiver. Note: Note that the polarity of the transmitter and receiver are opposite: During transmission, a '0' bit is transmitted as a '1' pulse. During reception, an accepted '0' pulse is received as a '0' bit. Example: The figure below illustrates reception where RXPL.RXPL is set to 19. This indicates that the pulse width should be at least 20 SE clock cycles. When using BAUD=0xE666 or 160 SE cycles per bit, this corresponds to 2/16 baud clock as minimum pulse width required. In this case the first bit is accepted as a '0', the second bit is a '1', and the third bit is also a '1'. A low pulse is rejected since it does not meet the minimum requirement of 2/16 baud clock. Figure 31-11. IrDA Receive Decoding IrDA encoded RXD RXD Baud clock

20 SE clock cycles

0 0.5 1 1.5 2 2.5

31.6.3.4 Break Character Detection and Auto-Baud

Break character detection and auto-baud are available in this configuration:

Auto-baud frame format (CTRLA.FORM = 0x04 or 0x05),
Asynchronous mode (CTRLA.CMODE = 0),
and 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1). The auto-baud follows the LIN format. All LIN Frames start with a Break Field followed by a Sync Field. The USART uses a break detection threshold of greater than 11 nominal bit times at the configured baud rate. At any time, if more than 11 consecutive dominant bits are detected on the bus, the USART detects a Break Field. When a Break Field has been detected, the Receive Break interrupt flag (INTFLAG.RXBRK) is set and the USART expects the Sync Field character to be 0x55. This field is used to update the actual baud rate in order to stay synchronized. If the received Sync character is not 0x55, then the Inconsistent Sync Field error flag (STATUS.ISF) is set along with the Error interrupt flag (INTFLAG.ERROR), and the baud rate is unchanged. Figure 31-12. LIN Break and Sync Fields Break Field Sync Field 8 bit times After a break field is detected and the start bit of the Sync Field is detected, a counter is started. The counter is then incremented for the next 8 bit times of the Sync Field. At the end of these 8 bit times, the counter is stopped. At this moment, the 13 most significant bits of the counter (value divided by 8) give the new clock divider (BAUD.BAUD), and the 3 least significant bits of this value (the remainder) give the new Fractional Part (BAUD.FP). When the Sync Field has been received, the clock divider (BAUD.BAUD) and the Fractional Part (BAUD.FP) are updated after a synchronization delay. After the Break and Sync Fields are received, multiple characters of data can be received. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 523

31.6.3.5 RS485

RS485 is available with the following configuration:

USART frame format (CTRLA.FORM = 0x00 or 0x01)
RS485 pinout (CTRLA.TXPO=0x3). The RS485 feature enables control of an external line driver as shown in the figure below. While operating in RS485 mode, the transmit enable pin (TE) is driven high when the transmitter is active. Figure 31-13. RS485 Bus Connection TXD TE USART RXD Differential Bus The TE pin will remain high for the complete frame including stop bit(s). If a Guard Time is programmed in the Control C register (CTRLC.GTIME), the line will remain driven after the last character completion. The following figure shows a transfer with one stop bit and CTRLC.GTIME=3. Figure 31-14. Example of TE Drive with Guard Time TXD Start Stop Data GTIME=3 TE The Transmit Complete interrupt flag (INTFLAG.TXC) will be raised after the guard time is complete and TE goes low.

31.6.3.6 ISO 7816 for Smart Card Interfacing

The SERCOM USART features an ISO/IEC 7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO 7816 link. Both T=0 and T=1 protocols defined by the ISO 7816 specification are supported. ISO 7816 is available with the following configuration:

ISO 7816 format (CTRLA.FORM = 0x07)
Inverse transmission and reception (CTRLA.RXINV=1 and CTRLA.TXINV=1)
Single bidirectional data line (CTRLA.TXPO and CTRLA.RXPO configured to use the same data pin)
Even parity (CTRLB.PMODE=0)
8-bit character size (CTRLB.CHSIZE=0)
T=0 (CTRLA.CMODE=1) or T=1 (CTRLA.CMODE=0) ISO 7816 is a half duplex communication on a single bidirectional line. The USART connects to a smart card as shown below. The output is only driven when the USART is transmitting. The USART is considered as the host of the communication as it generates the clock. Figure 31-15. Connection of a Smart Card to the SERCOM USART TXD/RXD SERCOM USART SCK I/O Smart Card CLK ISO 7816 characters are specified as 8 bits with even parity. The USART must be configured accordingly. The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO 7816 mode may lead to unpredictable results. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 524

programmed in the CTRLC.MAXITER field. As soon as the maximum is reached, the character is considered as correct, an acknowledge is sent on the line, the STATUS.ITER bit is set and the internal iteration counter is reset. Protocol T=1 When operating in ISO7816 protocol T=1, the transmission is asynchronous (CTRL1.CMODE=0) with one or two stop bits. After the stop bits are sent, the transmitter does not drive the I/O line. Parity is generated when transmitting and checked when receiving. Parity error detection sets the STATUS.PERR bit, and the erroneous character is written to the receive FIFO. When using T=1 protocol, the receiver does not signal errors on the I/O line and the transmitter does not retransmit.

31.6.3.7 Collision Detection

When the receiver and transmitter are connected either through pin configuration or externally, transmit collision can be detected after selecting the Collision Detection Enable bit in the CTRLB register (CTRLB.COLDEN=1). To detect collision, the receiver and transmitter must be enabled (CTRLB.RXEN=1 and CTRLB.TXEN=1). Collision detection is performed for each bit transmitted by comparing the received value with the transmit value, as shown in the figure below. While the transmitter is idle (no transmission in progress), characters can be received on RxD without triggering a collision. Figure 31-18. Collision Checking 8-bit character, single stop bit Collision checked TXD RXD The next figure shows the conditions for a collision detection. In this case, the start bit and the first data bit are received with the same value as transmitted. The second received data bit is found to be different than the transmitted bit at the detection point, which indicates a collision. Figure 31-19. Collision Detected Collision checked and ok TXD RXD Collision detected Tri-state TXEN When a collision is detected, the USART follows this sequence: 1. Abort the current transfer. 2. Flush the transmit buffer. 3. Disable transmitter (CTRLB.TXEN=0) – This is done after a synchronization delay. The CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB) will be set until this is complete. – After disabling, the TxD pin will be tri-stated. 4. Set the Collision Detected bit (STATUS.COLL) along with the Error interrupt flag (INTFLAG.ERROR). 5. Set the Transmit Complete interrupt flag (INTFLAG.TXC), since the transmit buffer no longer contains data. After a collision, software must manually enable the transmitter again before continuing, after assuring that the CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB) is not set.

31.6.3.8 Loop-Back Mode

For loop-back mode, configure the Receive Data Pinout (CTRLA.RXPO) and Transmit Data Pinout (CTRLA.TXPO) to use the same data pins for transmit and receive. The loop-back is through the pad, so the signal is also available externally. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 526

31.6.3.9 Start-of-Frame Detection

The USART start-of-frame detector can wake up the CPU when it detects a start bit. In standby sleep mode, the internal fast startup oscillator must be selected as the GCLK_SERCOMx_CORE source. When a 1-to-0 transition is detected on RxD, the 8MHz Internal Oscillator is powered up and the USART clock is enabled. After startup, the rest of the data frame can be received, provided that the baud rate is slow enough in relation to the fast startup internal oscillator start-up time. Refer to the Electrical Characteristics for details. The start-up time of this oscillator varies with supply voltage and temperature. The USART start-of-frame detection works both in asynchronous and synchronous modes. It is enabled by writing ‘1’ to the Start of Frame Detection Enable bit in the Control B register (CTRLB.SFDE). If the Receive Start Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.RXS) is set, the Receive Start interrupt is generated immediately when a start is detected. When using start-of-frame detection without the Receive Start interrupt, start detection will force the 8MHz Internal Oscillator and USART clock active while the frame is being received. In this case, the CPU will not wake up until the Receive Complete interrupt is generated.

31.6.3.10 Sample Adjustment

In asynchronous mode (CTRLA.CMODE=0), three samples in the middle are used to determine the value based on majority voting. The three samples used for voting can be selected using the Sample Adjustment bit field in Control A register (CTRLA.SAMPA). When CTRLA.SAMPA=0, samples 7-8-9 are used for 16x oversampling, and samples 3-4-5 are used for 8x oversampling.

31.6.4 DMA, Interrupts and Events

Table 31-4. Module Request for SERCOM USART Condition Request DMA Interrupt Event Data Register Empty (DRE) Yes (request cleared when data is written) Yes NA Receive Complete (RXC) Yes (request cleared when data is read) Yes Transmit Complete (TXC) NA Yes Receive Start (RXS) NA Yes Clear to Send Input Change (CTSIC) NA Yes Receive Break (RXBRK) NA Yes Error (ERROR) NA Yes

31.6.4.1 DMA Operation

The USART generates the following DMA requests:

Data received (RX): The request is set when data is available in the receive FIFO. The request is cleared when DATA is read.
Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is cleared when DATA is written.

31.6.4.2 Interrupts

The USART has the following interrupt sources. These are asynchronous interrupts, and can wake up the device from any sleep mode:

Data Register Empty (DRE)
Receive Complete (RXC)
Transmit Complete (TXC) SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 527

Receive Start (RXS)
Clear to Send Input Change (CTSIC)
Received Break (RXBRK)
Error (ERROR) Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the interrupt condition is met. Each interrupt can be individually enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and if the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the USART is reset. For details on clearing interrupt flags, refer to the INTFLAG register description. The USART has one common interrupt request line for all the interrupt sources. The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for interrupt requests. Refer to the Nested Vector Interrupt Controller for details.

31.6.4.3 Events

Not applicable.

31.6.5 Sleep Mode Operation

The behavior in sleep mode is depending on the clock source and the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY):

Internal clocking, CTRLA.RUNSTDBY=1: GCLK_SERCOMx_CORE can be enabled in all sleep modes. Any interrupt can wake up the device.
External clocking, CTRLA.RUNSTDBY=1: The Receive Start and the Receive Complete interrupt(s) can wake up the device.
Internal clocking, CTRLA.RUNSTDBY=0: Internal clock will be disabled, after any ongoing transfer was completed. The Receive Start and the Receive Complete interrupt(s) can wake up the device.
External clocking, CTRLA.RUNSTDBY=0: External clock will be disconnected, after any ongoing transfer was completed. All reception will be dropped.

31.6.6 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written:

Software Reset bit in the CTRLA register (CTRLA.SWRST)
Enable bit in the CTRLA register (CTRLA.ENABLE)
Receiver Enable bit in the CTRLB register (CTRLB.RXEN)
Transmitter Enable bit in the Control B register (CTRLB.TXEN) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 528

31.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 RUNSTDBY MODE[2:0] ENABLE SWRST 15:8 SAMPR[2:0] RXINV TXINV IBON 23:16 SAMPA[1:0] RXPO[1:0] TXPO[1:0] 31:24 DORD CPOL CMODE FORM[3:0] 0x04 CTRLB 7:0 SBMODE CHSIZE[2:0] 15:8 PMODE ENC SFDE COLDEN 23:16 RXEN TXEN 31:24 0x08 CTRLC 7:0 GTIME[2:0] 15:8 23:16 MAXITER[2:0] DSNACK INACK 31:24 0x0C BAUD 7:0 BAUD[7:0] 15:8 BAUD[15:8] 0x0E RXPL 7:0 RXPL[7:0] 0x0F ... 0x13 Reserved 0x14 INTENCLR 7:0 ERROR RXBRK CTSIC RXS RXC TXC DRE 0x15 Reserved 0x16 INTENSET 7:0 ERROR RXBRK CTSIC RXS RXC TXC DRE 0x17 Reserved 0x18 INTFLAG 7:0 ERROR RXBRK CTSIC RXS RXC TXC DRE 0x19 Reserved 0x1A STATUS 7:0 ITER COLL ISF CTS BUFOVF FERR PERR 15:8 0x1C SYNCBUSY 7:0 RXERRCNT CTRLB ENABLE SWRST 15:8 23:16 31:24 0x20 RXERRCNT 7:0 RXERRCNT[7:0] 0x21 ... 0x27 Reserved 0x28 DATA 7:0 DATA[7:0] 15:8 DATA[8] 0x2A ... 0x2F Reserved 0x30 DBGCTRL 7:0 DBGSTOP

31.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read- Synchronized" and/or "Write-Synchronized" property in each individual register description. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 529

31.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 DORD CPOL CMODE FORM[3:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SAMPA[1:0] RXPO[1:0] TXPO[1:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SAMPR[2:0] RXINV TXINV IBON Access R/W R/W R/W R/W R/W R Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RUNSTDBY MODE[2:0] ENABLE SWRST Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 30 – DORD Data Order This bit selects the data order when a character is shifted out from the Data register. This bit is not synchronized. Value Description 0 MSB is transmitted first. 1 LSB is transmitted first. Bit 29 – CPOL Clock Polarity This bit selects the relationship between data output change and data input sampling in synchronous mode. This bit is not synchronized. CPOL TxD Change RxD Sample 0x0 Rising XCK edge Falling XCK edge 0x1 Falling XCK edge Rising XCK edge Bit 28 – CMODE Communication Mode This bit selects asynchronous or synchronous communication. This bit is not synchronized. Value Description 0 Asynchronous communication. 1 Synchronous communication. Bits 27:24 – FORM[3:0] Frame Format These bits define the frame format. These bits are not synchronized. FORM[3:0] Description 0x0 USART frame 0x1 USART frame with parity SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 530

FORM[3:0] Description 0x4 Auto-baud - break detection and auto-baud 0x5 Auto-baud - break detection and auto-baud with parity 0x6-0xF Reserved Bits 23:22 – SAMPA[1:0] Sample Adjustment These bits define the sample adjustment. These bits are not synchronized. SAMPA[1:0] 16x Over-sampling (CTRLA.SAMPR=0 or 1) 8x Over-sampling (CTRLA.SAMPR=2 or 3) 0x0 7-8-9 3-4-5 0x1 9-10-11 4-5-6 0x2 11-12-13 5-6-7 0x3 13-14-15 6-7-8 Bits 21:20 – RXPO[1:0] Receive Data Pinout These bits define the receive data (RxD) pin configuration. These bits are not synchronized. RXPO[1:0] Name Description 0x0 PAD[0] SERCOM PAD[0] is used for data reception 0x1 PAD[1] SERCOM PAD[1] is used for data reception 0x2 PAD[2] SERCOM PAD[2] is used for data reception 0x3 PAD[3] SERCOM PAD[3] is used for data reception Bits 17:16 – TXPO[1:0] Transmit Data Pinout These bits define the transmit data (TxD) and XCK pin configurations. This bit is not synchronized. TXPO TxD Pin Location XCK Pin Location (When Applicable) RTS CTS 0x0 SERCOM PAD[0] SERCOM PAD[1] N/A N/A 0x1 SERCOM PAD[2] SERCOM PAD[3] N/A N/A 0x2 SERCOM PAD[0] N/A SERCOM PAD[2] SERCOM PAD[3] 0x3 SERCOM_PAD[0] SERCOM_PAD[1] SERCOM_PAD[2] N/A Bits 15:13 – SAMPR[2:0] Sample Rate These bits select the sample rate. These bits are not synchronized. SAMPR[2:0] Description 0x0 16x over-sampling using arithmetic baud rate generation. 0x1 16x over-sampling using fractional baud rate generation. 0x2 8x over-sampling using arithmetic baud rate generation. 0x3 8x over-sampling using fractional baud rate generation. 0x4 3x over-sampling using arithmetic baud rate generation. 0x5-0x7 Reserved Bit 10 – RXINV Receive Data Invert This bit controls whether the receive data (RxD) is inverted or not. Note: Start, parity and stop bit(s) are unchanged. When enabled, parity is calculated on the inverted data. Value Description 0 RxD is not inverted. 1 RxD is inverted. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 531

Bit 9 – TXINV Transmit Data Invert This bit controls whether the transmit data (TxD) is inverted or not. Note: Start, parity and stop bit(s) are unchanged. When enabled, parity is calculated on the inverted data. Value Description 0 TxD is not inverted. 1 TxD is inverted. Bit 8 – IBON Immediate Buffer Overflow Notification This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is asserted when a buffer overflow occurs. Value Description 0 STATUS.BUFOVF is asserted when it occurs in the data stream. 1 STATUS.BUFOVF is asserted immediately upon buffer overflow. Bit 7 – RUNSTDBY Run In Standby This bit defines the functionality in standby sleep mode. This bit is not synchronized. RUNSTDBY External Clock Internal Clock 0x0 External clock is disconnected when ongoing transfer is finished. All reception is dropped. Generic clock is disabled when ongoing transfer is finished. The device can wake up on Transfer Complete interrupt. 0x1 Wake on Receive Complete interrupt. Generic clock is enabled in all sleep modes. Any interrupt can wake up the device. Bits 4:2 – MODE[2:0] Operating Mode These bits select the USART serial communication interface of the SERCOM. These bits are not synchronized. Value Description 0x0 USART with external clock 0x1 USART with internal clock Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the operation is complete. This bit is not enable-protected. Value Description 0 The peripheral is disabled or being disabled. 1 The peripheral is enabled or being enabled. Bit 0 – SWRST Software Reset Writing '0' to this bit has no effect. Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Value Description 0 There is no reset operation ongoing. 1 The reset operation is ongoing. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 532

31.8.2 Control B

Name: CTRLB Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 RXEN TXEN Access R/W R/W Reset 0 0 Bit 15 14 13 12 11 10 9 8 PMODE ENC SFDE COLDEN Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SBMODE CHSIZE[2:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 17 – RXEN Receiver Enable Writing '0' to this bit will disable the USART receiver. Disabling the receiver will flush the receive buffer and clear the FERR, PERR and BUFOVF bits in the STATUS register. Writing '1' to CTRLB.RXEN when the USART is disabled will set CTRLB.RXEN immediately. When the USART is enabled, CTRLB.RXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until the receiver is enabled. When the receiver is enabled, CTRLB.RXEN will read back as '1'. Writing '1' to CTRLB.RXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain set until the receiver is enabled, and CTRLB.RXEN will read back as '1'. This bit is not enable-protected. Value Description 0 The receiver is disabled or being enabled. 1 The receiver is enabled or will be enabled when the USART is enabled. Bit 16 – TXEN Transmitter Enable Writing '0' to this bit will disable the USART transmitter. Disabling the transmitter will not become effective until ongoing and pending transmissions are completed. Writing '1' to CTRLB.TXEN when the USART is disabled will set CTRLB.TXEN immediately. When the USART is enabled, CTRLB.TXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until the transmitter is enabled. When the transmitter is enabled, CTRLB.TXEN will read back as '1'. Writing '1' to CTRLB.TXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain set until the receiver is enabled, and CTRLB.TXEN will read back as '1'. This bit is not enable-protected. Value Description 0 The transmitter is disabled or being enabled. 1 The transmitter is enabled or will be enabled when the USART is enabled. Bit 13 – PMODE Parity Mode This bit selects the type of parity used when parity is enabled (CTRLA.FORM is '1'). The transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 533

for the incoming data and parity bit, compare it to the parity mode and, if a mismatch is detected, STATUS.PERR will be set. This bit is not synchronized. Value Description 0 Even parity. 1 Odd parity. Bit 10 – ENC Encoding Format This bit selects the data encoding format. This bit is not synchronized. Value Description 0 Data is not encoded. 1 Data is IrDA encoded. Bit 9 – SFDE Start of Frame Detection Enable This bit controls whether the start-of-frame detector will wake up the device when a start bit is detected on the RxD line. This bit is not synchronized. SFDE INTENSET.RXS INTENSET.RXC Description 0 X X Start-of-frame detection disabled. 1 0 0 Reserved 1 0 1 Start-of-frame detection enabled. RXC wakes up the device from all sleep modes. 1 1 0 Start-of-frame detection enabled. RXS wakes up the device from all sleep modes. 1 1 1 Start-of-frame detection enabled. Both RXC and RXS wake up the device from all sleep modes. Bit 8 – COLDEN Collision Detection Enable This bit enables collision detection. This bit is not synchronized. Value Description 0 Collision detection is not enabled. 1 Collision detection is enabled. Bit 6 – SBMODE Stop Bit Mode This bit selects the number of stop bits transmitted. This bit is not synchronized. Value Description 0 One stop bit. 1 Two stop bits. Bits 2:0 – CHSIZE[2:0] Character Size These bits select the number of bits in a character. These bits are not synchronized. CHSIZE[2:0] Description 0x0 8 bits 0x1 9 bits 0x2-0x4 Reserved 0x5 5 bits 0x6 6 bits 0x7 7 bits SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 534

31.8.3 Control C

Name: CTRLC Offset: 0x08 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 MAXITER[2:0] DSNACK INACK Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 GTIME[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 22:20 – MAXITER[2:0] Maximum Iterations These bits define the maximum number of retransmit iterations. These bits also define the successive NACKs sent to the remote transmitter when CTRLC.DSNACK is set. This field is only valid when using ISO7816 T=0 mode (CTRLA.MODE=0x7 ). Bit 17 – DSNACK Disable Successive Not Acknowledge This bit controls how many times NACK will be sent on parity error reception. This bit is only valid in ISO7816 T=0 mode and when CTRLC.INACK=0. Value Description 0 NACK is sent on the ISO line for every parity error received. 1 Successive parity errors are counted up to the value specified in CTRLC.MAXITER. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. Bit 16 – INACK Inhibit Not Acknowledge This bit controls whether a NACK is transmitted when a parity error is received. This bit is only valid in ISO7816 T=0 mode. Value Description 0 NACK is transmitted when a parity error is received. 1 NACK is not transmitted when a parity error is received. Bits 2:0 – GTIME[2:0] Guard Time These bits define the guard time when using RS485 mode (CTRLA.FORM=0x0 or CTRLA.FORM=0x1, and CTRLA.TXPO=0x3) or ISO7816 mode (CTRLA.FORM=0x7). For RS485 mode, the guard time is programmable from 0-7 bit times and defines the time that the transmit enable pin (TE) remains high after the last stop bit is transmitted and there is no remaining data to be transmitted. For ISO7816 T=0 mode, the guard time is programmable from 2-9 bit times and defines the guard time between each transmitted byte. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 535

31.8.4 Baud

Name: BAUD Offset: 0x0C Reset: 0x0000 Property: Enable-Protected, PAC Write-Protection Bit 15 14 13 12 11 10 9 8 BAUD[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BAUD[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – BAUD[15:0] Baud Value Arithmetic Baud Rate Generation (CTRLA.SAMPR[0]=0): These bits control the clock generation, as described in the SERCOM Baud Rate section. If Fractional Baud Rate Generation (CTRLA.SAMPR[0]=1) bit positions 15 to 13 are replaced by FP[2:0] Fractional Part: For more information on an Arithmetic Baud Rate Generation, refer to Asynchronous Arithmetic Mode BAUD Value Selection.

Bits 15:13 - FP[2:0]: Fractional Part These bits control the clock generation, as described in the Clock Generation - Baud-Rate Generator section.
Bits 12:0 - BAUD[21:0]: Baud Value These bits control the clock generation, as described in the Clock Generation - Baud-Rate Generator section. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 536

31.8.5 Receive Pulse Length Register

Name: RXPL Offset: 0x0E Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 RXPL[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – RXPL[7:0] Receive Pulse Length When the encoding format is set to IrDA (CTRLB.ENC=1), these bits control the minimum pulse length that is required for a pulse to be accepted by the IrDA receiver with regards to the serial engine clock period SE p er . PU L SE ≥ RXPL + 2 ⋅ S E p er SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 537

31.8.6 Interrupt Enable Clear

Name: INTENCLR Offset: 0x14 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 5 4 3 2 1 0 ERROR RXBRK CTSIC RXS RXC TXC DRE Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 7 – ERROR Error Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. Value Description 0 Error interrupt is disabled. 1 Error interrupt is enabled. Bit 5 – RXBRK Receive Break Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Receive Break Interrupt Enable bit, which disables the Receive Break interrupt. Value Description 0 Receive Break interrupt is disabled. 1 Receive Break interrupt is enabled. Bit 4 – CTSIC Clear to Send Input Change Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Clear To Send Input Change Interrupt Enable bit, which disables the Clear To Send Input Change interrupt. Value Description 0 Clear To Send Input Change interrupt is disabled. 1 Clear To Send Input Change interrupt is enabled. Bit 3 – RXS Receive Start Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Receive Start Interrupt Enable bit, which disables the Receive Start interrupt. Value Description 0 Receive Start interrupt is disabled. 1 Receive Start interrupt is enabled. Bit 2 – RXC Receive Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete interrupt. Value Description 0 Receive Complete interrupt is disabled. 1 Receive Complete interrupt is enabled. Bit 1 – TXC Transmit Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Transmit Complete Interrupt Enable bit, which disables the Receive Complete interrupt. Value Description 0 Transmit Complete interrupt is disabled. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 538

1 Transmit Complete interrupt is enabled. Bit 0 – DRE Data Register Empty Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register Empty interrupt. Value Description 0 Data Register Empty interrupt is disabled. 1 Data Register Empty interrupt is enabled. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 539

31.8.7 Interrupt Enable Set

Name: INTENSET Offset: 0x16 Reset: 0x00 Property: PAC Write-Protection This register allows the user to enable an interrupt without read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR) . This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 5 4 3 2 1 0 ERROR RXBRK CTSIC RXS RXC TXC DRE Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 7 – ERROR Error Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. Value Description 0 Error interrupt is disabled. 1 Error interrupt is enabled. Bit 5 – RXBRK Receive Break Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Receive Break Interrupt Enable bit, which enables the Receive Break interrupt. Value Description 0 Receive Break interrupt is disabled. 1 Receive Break interrupt is enabled. Bit 4 – CTSIC Clear to Send Input Change Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Clear To Send Input Change Interrupt Enable bit, which enables the Clear To Send Input Change interrupt. Value Description 0 Clear To Send Input Change interrupt is disabled. 1 Clear To Send Input Change interrupt is enabled. Bit 3 – RXS Receive Start Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Receive Start Interrupt Enable bit, which enables the Receive Start interrupt. Value Description 0 Receive Start interrupt is disabled. 1 Receive Start interrupt is enabled. Bit 2 – RXC Receive Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive Complete interrupt. Value Description 0 Receive Complete interrupt is disabled. 1 Receive Complete interrupt is enabled. Bit 1 – TXC Transmit Complete Interrupt Enable Writing '0' to this bit has no effect. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 540

Writing '1' to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete interrupt. Value Description 0 Transmit Complete interrupt is disabled. 1 Transmit Complete interrupt is enabled. Bit 0 – DRE Data Register Empty Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register Empty interrupt. Value Description 0 Data Register Empty interrupt is disabled. 1 Data Register Empty interrupt is enabled. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 541

31.8.8 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x18 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 ERROR RXBRK CTSIC RXS RXC TXC DRE Access R/W R/W R/W R/W R R/W R Reset 0 0 0 0 0 0 0 Bit 7 – ERROR Error This flag is cleared by writing '1' to it. This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS register. Errors that will set this flag are COLL, ISF, BUFOVF, FERR, and PERR.Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 5 – RXBRK Receive Break This flag is cleared by writing '1' to it. This flag is set when auto-baud is enabled (CTRLA.FORM) and a break character is received. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 4 – CTSIC Clear to Send Input Change This flag is cleared by writing a '1' to it. This flag is set when a change is detected on the CTS pin. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 3 – RXS Receive Start This flag is cleared by writing '1' to it. This flag is set when a start condition is detected on the RxD line and start-of-frame detection is enabled (CTRLB.SFDE is '1'). Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Receive Start interrupt flag. Bit 2 – RXC Receive Complete This flag is cleared by reading the Data register (DATA) or by disabling the receiver. This flag is set when there are unread data in DATA. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. Bit 1 – TXC Transmit Complete This flag is cleared by writing '1' to it or by writing new data to DATA. This flag is set when the entire frame in the transmit shift register has been shifted out and there are no new data in DATA. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 0 – DRE Data Register Empty This flag is cleared by writing new data to DATA. This flag is set when DATA is empty and ready to be written. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 542

31.8.9 Status

Name: STATUS Offset: 0x1A Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ITER COLL ISF CTS BUFOVF FERR PERR Access R/W R/W R/W R R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 7 – ITER Maximum Number of Repetitions Reached This bit is set when the maximum number of NACK repetitions or retransmissions is met in ISO7816 T=0 mode. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Bit 5 – COLL Collision Detected This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set when collision detection is enabled (CTRLB.COLDEN) and a collision is detected. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Bit 4 – ISF Inconsistent Sync Field This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set when the frame format is set to auto-baud (CTRLA.FORM) and a sync field not equal to 0x55 is received. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Bit 3 – CTS Clear to Send This bit indicates the current level of the CTS pin when flow control is enabled (CTRLA.TXPO). Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. Bit 2 – BUFOVF Buffer Overflow Reading this bit before reading the Data register will indicate the error status of the next character to be read. This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set when a buffer overflow condition is detected. A buffer overflow occurs when the receive buffer is full, there is a new character waiting in the receive shift register and a new start bit is detected. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Bit 1 – FERR Frame Error Reading this bit before reading the Data register will indicate the error status of the next character to be read. This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set if the received character had a frame error, i.e., when the first stop bit is zero. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 543

Bit 0 – PERR Parity Error Reading this bit before reading the Data register will indicate the error status of the next character to be read. This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set if parity checking is enabled (CTRLA.FORM is 0x1, 0x5, or 0x7) and a parity error is detected. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 544

31.8.10 Synchronization Busy

Name: SYNCBUSY Offset: 0x1C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 RXERRCNT CTRLB ENABLE SWRST Access R R R R Reset 0 0 0 0 Bit 3 – RXERRCNT Receive Error Count Synchronization Busy The RXERRCNT register is automatically synchronized to the APB domain upon error. When returning from sleep, this bit will be raised until the new value is available to be read. Value Description 0 RXERRCNT synchronization is not busy. 1 RXERRCNT synchronization is busy. Bit 2 – CTRLB CTRLB Synchronization Busy Writing to the CTRLB register when the SERCOM is enabled requires synchronization. When writing to CTRLB the SYNCBUSY.CTRLB bit will be set until synchronization is complete. If CTRLB is written while SYNCBUSY.CTRLB is asserted, an APB error will be generated. Value Description 0 CTRLB synchronization is not busy. 1 CTRLB synchronization is busy. Bit 1 – ENABLE SERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNCBUSY.ENABLE bit will be set until synchronization is complete. Value Description 0 Enable synchronization is not busy. 1 Enable synchronization is busy. Bit 0 – SWRST Software Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will be set until synchronization is complete. Value Description 0 SWRST synchronization is not busy. 1 SWRST synchronization is busy. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 545

31.8.11 Receive Error Count

Name: RXERRCNT Offset: 0x20 Reset: 0x00 Property: Read-Synchronized Bit 7 6 5 4 3 2 1 0 RXERRCNT[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:0 – RXERRCNT[7:0] Receive Error Count This register records the total number of parity errors and NACK errors combined in ISO7816 mode (CTRLA.FORM=0x7). This register is automatically cleared on read. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 546

31.8.12 Data

Name: DATA Offset: 0x28 Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 DATA[8] Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 8:0 – DATA[8:0] Data Reading these bits will return the contents of the Receive Data register. The register should be read only when the Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set. The status bits in STATUS should be read before reading the DATA value in order to get any corresponding error. Writing these bits will write the Transmit Data register. This register should be written only when the Data Register Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 547

31.8.13 Debug Control

Name: DBGCTRL Offset: 0x30 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DBGSTOP Access R/W Reset 0 Bit 0 – DBGSTOP Debug Stop Mode This bit controls the baud-rate generator functionality when the CPU is halted by an external debugger. Value Description 0 The baud-rate generator continues normal operation when the CPU is halted by an external debugger. 1 The baud-rate generator is halted when the CPU is halted by an external debugger. SAM L22 Family SERCOM USART – SERCOM Universal Synchronous and As... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 548

SERCOM SPI – SERCOM Serial Peripheral Interface

32.1 Overview

The serial peripheral interface (SPI) is one of the available modes in the Serial Communication Interface (SERCOM). The SPI uses the SERCOM transmitter and receiver configured as shown in 32.3. Block Diagram. Each side, Host and Client, depicts a separate SPI containing a shift register, a transmit buffer and two receive buffers. In addition, the SPI Host uses the SERCOM baud-rate generator, while the SPI Client can use the SERCOM address match logic. Labels in capital letters are synchronous to CLK_SERCOMx_APB and accessible by the CPU, while labels in lowercase letters are synchronous to the SCK clock.

32.2 Features

SERCOM SPI includes the following features:

Full-duplex, four-wire interface (MISO, MOSI, SCK, SS)
Single-buffered transmitter, double-buffered receiver
Supports all four SPI modes of operation
Single data direction operation allows alternate function on MISO or MOSI pin
Selectable LSB- or MSB-first data transfer
Can be used with DMA
Host operation: – Serial clock speed, f SCK=1/tSCK(1) – 8-bit clock generator – Hardware controlled SS
Client operation: – Serial clock speed, f SCK=1/tSSCK(1) – Optional 8-bit address match operation – Operation in all sleep modes – Wake on SS transition 1. For t SCK and tSSCK values, refer to SPI Timing Characteristics. References: SERCOM SERCOM - Features

32.3 Block Diagram

Figure 32-1. Full-Duplex SPI Host Client Interconnection BAUD baud rate generator Tx DATA shift register rx buffer Rx DATA Host Client Tx DATA shift register rx buffer Rx DATA SCK _SS MISO MOSI ADDR/ADDRMASK Address Match SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 549

32.4 Signal Description

Table 32-1. SERCOM SPI Signals Signal Name Type Description PAD[3:0] Digital I/O General SERCOM pins One signal can be mapped to one of several pins. References: I/O Multiplexing and Considerations

32.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

32.5.1 I/O Lines

In order to use the SERCOM’s I/O lines, the I/O pins must be configured using the 28. PORT - I/O Pin Controller. When the SERCOM is configured for SPI operation, the SERCOM controls the direction and value of the I/O pins according to the table below. PORT Control bit PINCFGn.DRVSTR is still effective for the SERCOM output pins. PORT Control bit PINCFGn.PULLEN is still effective on the SERCOM input pins, but is limited to the enabling/ disabling of a pull down only (it is not possible to enable/disable a pull up). If the receiver is disabled, the data input pin can be used for other purposes. In Host mode, the SPI select line (SS) is hardware controlled when the Host SPI Select Enable bit in the Control B register (CTRLB.MSSEN) is '1'. Table 32-2. SPI Pin Configuration Pin Host SPI Client SPI MOSI Output Input MISO Input Output SCK Output Input SS Output (CTRLB.MSSEN=1) Input The combined configuration of PORT, the Data In Pinout and the Data Out Pinout bit groups in the Control A register (CTRLA.DIPO and CTRLA.DOPO) define the physical position of the SPI signals in the table above.

32.5.2 Power Management

This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake up the device from sleep modes. References: PM - Power Manager

32.5.3 Clocks

The SERCOM bus clock (CLK_SERCOMx_APB) is enabled by default, and can be enabled and disabled in the Main Clock. A generic clock (GCLK_SERCOMx_CORE) is required to clock the SPI. This clock must be configured and enabled in the Generic Clock Controller before using the SPI. This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Therefore, writes to certain registers will require synchronization to the clock domains. References: 15. GCLK - Generic Clock Controller SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 550

16.6.2.6. Peripheral Clock Masking SERCOM - Synchronization

32.5.4 DMA

32.5.5 Interrupts

32.5.6 Events

Not applicable.

32.5.7 Debug Operation

32.5.8 Register Access Protection

Registers with write-access can be write-protected optionally by the 11. PAC - Peripheral Access Controller. PAC Write-Protection is not available for the following registers:

Interrupt Flag Clear and Status register (INTFLAG)
Status register (STATUS)
Data register (DATA) Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger.

32.5.9 Analog Connections

Not applicable.

32.6 Functional Description

32.6.1 Principle of Operation

The SPI is a high-speed synchronous data transfer interface It allows high-speed communication between the device and peripheral devices. The SPI can operate as Host or Client. As Host, the SPI initiates and controls all data transactions. The SPI is single buffered for transmitting and double buffered for receiving. When transmitting data, the Data register can be loaded with the next character to be transmitted during the current transmission. When receiving, the data is transferred to the two-level receive buffer, and the receiver is ready for a new character. The SPI transaction format is shown in SPI Transaction Format. Each transaction can contain one or more characters. The character size is configurable, and can be either 8 or 9 bits. SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 551

Figure 32-2. SPI Transaction Format Character Transaction MOSI/MISO _SS Character 0 Character 1 Character 2 The SPI Host must pull the Client select line (SS) of the desired Client low to initiate a transaction. The Host and Client prepare data to send via their respective shift registers, and the Host generates the serial clock on the SCK line. Data are always shifted from Host to Client on the Host Output Client Input line (MOSI); data is shifted from Client to Host on the Host Input Client Output line (MISO). Each time character is shifted out from the Host, a character will be shifted out from the Client simultaneously. To signal the end of a transaction, the Host will pull the SS line high

32.6.2 Basic Operation

32.6.2.1 Initialization

The following registers are enable-protected, meaning that they can only be written when the SPI is disabled (CTRL.ENABLE=0):

Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST)
Control B register (CTRLB), except Receiver Enable (CTRLB.RXEN)
Baud register (BAUD)
Address register (ADDR) When the SPI is enabled or is being enabled (CTRLA.ENABLE=1), any writing to these registers will be discarded. when the SPI is being disabled, writing to these registers will be completed after the disabling. Enable-protection is denoted by the Enable-Protection property in the register description. Initialize the SPI by following these steps: 1. Select SPI mode in Host / Client operation in the Operating Mode bit group in the CTRLA register (CTRLA.MODE= 0x2 or 0x3 ). 2. Select transfer mode for the Clock Polarity bit and the Clock Phase bit in the CTRLA register (CTRLA.CPOL and CTRLA.CPHA) if desired. 3. Select the Frame Format value in the CTRLA register (CTRLA.FORM). 4. Configure the Data In Pinout field in the Control A register (CTRLA.DIPO) for SERCOM pads of the receiver. 5. Configure the Data Out Pinout bit group in the Control A register (CTRLA.DOPO) for SERCOM pads of the transmitter. 6. Select the Character Size value in the CTRLB register (CTRLB.CHSIZE). 7. Write the Data Order bit in the CTRLA register (CTRLA.DORD) for data direction. 8. If the SPI is used in Host mode: a. Select the desired baud rate by writing to the Baud register (BAUD). b. If Hardware SS control is required, write '1' to the Host Client Select Enable bit in CTRLB register (CTRLB.MSSEN). 9. Enable the receiver by writing the Receiver Enable bit in the CTRLB register (CTRLB.RXEN=1).

32.6.2.2 Enabling, Disabling, and Resetting

32.6.2.3 Clock Generation

In SPI Host operation (CTRLA.MODE=0x3), the serial clock (SCK) is generated internally by the SERCOM baud-rate generator. In SPI mode, the baud-rate generator is set to synchronous mode. The 8-bit Baud register (BAUD) value is used for generating SCK and clocking the shift register. Refer to Clock Generation - Baud-Rate Generator for more details. In SPI Client operation (CTRLA.MODE is 0x2), the clock is provided by an external Host on the SCK pin. This clock is used to directly clock the SPI shift register. References: Clock Generation - Baud-Rate Generator Asynchronous Arithmetic Mode BAUD Value Selection

32.6.2.4 Data Register

The SPI Transmit Data register (TxDATA) and SPI Receive Data register (RxDATA) share the same I/O address, referred to as the SPI Data register (DATA). Writing DATA register will update the Transmit Data register. Reading the DATA register will return the contents of the Receive Data register.

32.6.2.5 SPI Transfer Modes

There are four combinations of SCK phase and polarity to transfer serial data. The SPI data transfer modes are shown in SPI Transfer Modes (Table) and SPI Transfer Modes (Figure). SCK phase is configured by the Clock Phase bit in the CTRLA register (CTRLA.CPHA). SCK polarity is programmed by the Clock Polarity bit in the CTRLA register (CTRLA.CPOL). Data bits are shifted out and latched in on opposite edges of the SCK signal. This ensures sufficient time for the data signals to stabilize. Table 32-3. SPI Transfer Modes Mode CPOL CPHA Leading Edge Trailing Edge 0 0 0 Rising, sample Falling, setup 1 0 1 Rising, setup Falling, sample 2 1 0 Falling, sample Rising, setup 3 1 1 Falling, setup Rising, sample Note: Leading edge is the first clock edge in a clock cycle. Trailing edge is the second clock edge in a clock cycle. SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 553

Figure 32-3. SPI Transfer Modes Bit 1 Bit 6 LSB MSB Mode 0 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN Mode 2 SS MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 MSB first (DORD = 0) LSB first (DORD = 1) Mode 1 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN Mode 3 SS MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB MSB first (DORD = 0) LSB first (DORD = 1)

32.6.2.6 Transferring Data

In Host mode (CTRLA.MODE=0x3), when Host Client Enable Select (CTRLB.MSSEN) is ‘1’, hardware will control the SS line. When Host Client Select Enable (CTRLB.MSSEN) is '0', the SS line must be configured as an output. SS can be assigned to any general purpose I/O pin. When the SPI is ready for a data transaction, software must pull the SS line low. When writing a character to the Data register (DATA), the character will be transferred to the shift register. Once the content of TxDATA has been transferred to the shift register, the Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) will be set. And a new character can be written to DATA. Each time one character is shifted out from the Host, another character will be shifted in from the Client simultaneously. If the receiver is enabled (CTRLA.RXEN=1), the contents of the shift register will be transferred to the two-level receive buffer. The transfer takes place in the same clock cycle as the last data bit is shifted in. And the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set. The received data can be retrieved by reading DATA. SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 554

When the last character has been transmitted and there is no valid data in DATA, the Transmit Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set. When the transaction is finished, the Host must pull the SS line high to notify the Client. If Host Client Select Enable (CTRLB.MSSEN) is set to '0', the software must pull the SS line high. Client In Client mode (CTRLA.MODE=0x2), the SPI interface will remain inactive with the MISO line tri-stated as long as the SS pin is pulled high. Software may update the contents of DATA at any time as long as the Data Register Empty flag in the Interrupt Status and Clear register (INTFLAG.DRE) is set. When SS is pulled low and SCK is running, the Client will sample and shift out data according to the transaction mode set. When the content of TxDATA has been loaded into the shift register, INTFLAG.DRE will be set, and new data can be written to DATA. Similar to the Host, the Client will receive one character for each character transmitted. A character will be transferred into the two-level receive buffer within the same clock cycle its last data bit is received. The received character can be retrieved from DATA when the Receive Complete interrupt flag (INTFLAG.RXC) is set. When the Host pulls the SS line high, the transaction is done and the Transmit Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set. After DATA is written it takes up to three SCK clock cycles until the content of DATA is ready to be loaded into the shift register on the next character boundary. As a consequence, the first character transferred in a SPI transaction the Client Shift Register. When transmitting several characters in one SPI transaction, the data has to be written into DATA register with at least three SCK clock cycles left in the current character transmission. If this criteria is not met, the previously received character will be transmitted. Once the DATA register is empty, it takes three CLK_SERCOM_APB cycles for INTFLAG.DRE to be set.

32.6.2.7 Receiver Error Bit

The SPI receiver has one error bit: the Buffer Overflow bit (BUFOVF), which can be read from the Status register (STATUS). Once an error happens, the bit will stay set until it is cleared by writing '1' to it. The bit is also automatically cleared when the receiver is disabled. There are two methods for buffer overflow notification, selected by the immediate buffer overflow notification bit in the Control A register (CTRLA.IBON): If CTRLA.IBON=1, STATUS.BUFOVF is raised immediately upon buffer overflow. Software can then empty the receive FIFO by reading RxDATA until the receiver complete interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) goes low. If CTRLA.IBON=0, the buffer overflow condition travels with data through the receive FIFO. After the received data is read, STATUS.BUFOVF and INTFLAG.ERROR will be set along with INTFLAG.RXC, and RxDATA will be zero.

32.6.3 Additional Features

32.6.3.1 Address Recognition

When the SPI is configured for Client operation (CTRLA.MODE=0x2) with address recognition (CTRLA.FORM is 0x2), the SERCOM address recognition logic is enabled: the first character in a transaction is checked for an address match. If there is a match, the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set, the MISO output is enabled, and the transaction is processed. If the device is in sleep mode, an address match can wake up the device in order to process the transaction. If there is no match, the complete transaction is ignored. If a 9-bit frame format is selected, only the lower 8 bits of the shift register are checked against the Address register (ADDR). Preload must be disabled (CTRLB.PLOADEN=0) in order to use this mode. References: SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 555

32.6.3.2 Preloading of the Client Shift Register

When starting a transaction, the Client will first transmit the contents of the shift register before loading new data from DATA. The first character sent can be either the reset value of the shift register (if this is the first transmission since the last reset) or the last character in the previous transmission. Preloading can be used to preload data into the shift register while SS is high: this eliminates sending a dummy character when starting a transaction. If the shift register is not preloaded, the current contents of the shift register will be shifted out. Only one data character will be preloaded into the shift register while the synchronized SS signal is high. If the next character is written to DATA before SS is pulled low, the second character will be stored in DATA until transfer begins. For proper preloading, sufficient time must elapse between SS going low and the first SCK sampling edge, as in Timing Using Preloading. See the Electrical Characteristics for timing details. Preloading is enabled by writing '1' to the Client Data Preload Enable bit in the CTRLB register (CTRLB.PLOADEN). Figure 32-4. Timing Using Preloading SS SS synchronized to system domain SCK Synchronization to system domain MISO to SCK setup time Required SS-to-SCK time using PRELOADEN

32.6.3.3 Host with Several Clients

Host with multiple Clients in parallel is only available when Host Client Select Enable (CTRLB.MSSEN) is set to zero and hardware SS control is disabled. If the bus consists of several SPI Clients, an SPI Host can use general purpose I/O pins to control the SS line to each of the Clients on the bus, as shown in Multiple Clients in Parallel. In this configuration, the single selected SPI Client will drive the tri-state MISO line. Figure 32-5. Multiple Clients in Parallel MOSI MISO SCK SS MOSI MISO SCK SS[0] MOSI MISO SCK SS SS[n-1] shift register shift register shift register SPI Host SPI Client 0 SPI Client n-1 Another configuration is multiple Clients in series, as in Multiple Clients in Series. In this configuration, all n attached Clients are connected in series. A common SS line is provided to all Clients, enabling them simultaneously. The Host must shift n characters for a complete transaction. Depending on the Host Client Select Enable bit (CTRLB.MSSEN), the SS line can be controlled either by hardware or user software and normal GPIO. SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 556

Figure 32-6. Multiple Clients in Series MOSI MISO SCK SS MOSI MISO SCK SS MOSI MISO SCK SS shift register shift register shift register SPI Host SPI Client 0 SPI Client n-1

32.6.3.4 Loop-Back Mode

For loop-back mode, configure the Data In Pinout (CTRLA.DIPO) and Data Out Pinout (CTRLA.DOPO) to use the same data pins for transmit and receive. The loop-back is through the pad, so the signal is also available externally.

32.6.3.5 Hardware Controlled SS

In Host mode, a single SS chip select can be controlled by hardware by writing the Host Client Select Enable (CTRLB.MSSEN) bit to '1'. In this mode, the SS pin is driven low for a minimum of one baud cycle before transmission begins, and stays low for a minimum of one baud cycle after transmission completes. If back-to-back frames are transmitted, the SS pin will always be driven high for a minimum of one baud cycle between frames. In Hardware Controlled SS, the time T is between one and two baud cycles depending on the SPI transfer mode. Figure 32-7. Hardware Controlled SS SS SCK T T = 1 to 2 baud cycles T T TT When CTRLB.MSSEN=0, the SS pin(s) is/are controlled by user software and normal GPIO.

32.6.3.6 Client Select Low Detection

In Client mode, the SPI can wake the CPU when the Client select (SS) goes low. When the Client Select Low Detect is enabled (CTRLB.SSDE=1), a high-to-low transition will set the Client Select Low interrupt flag (INTFLAG.SSL) and the device will wake up if applicable. SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 557

32.6.4 DMA, Interrupts, and Events

Table 32-4. Module Request for SERCOM SPI Condition Request DMA Interrupt Event Data Register Empty (DRE) Yes (request cleared when data is written) Yes NA Receive Complete (RXC) Yes (request cleared when data is read) Yes Transmit Complete (TXC) NA Yes Client Select low (SSL) NA Yes Error (ERROR) NA Yes

32.6.4.1 DMA Operation

The SPI generates the following DMA requests:

Data received (RX): The request is set when data is available in the receive FIFO. The request is cleared when DATA is read.
Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is cleared when DATA is written.

32.6.4.2 Interrupts

The SPI has the following interrupt sources. These are asynchronous interrupts, and can wake up the device from any sleep mode:

Data Register Empty (DRE)
Receive Complete (RXC)
Transmit Complete (TXC)
Client Select Low (SSL)
Error (ERROR) Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the interrupt condition is met. Each interrupt can be individually enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and if the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the SPI is reset. For details on clearing interrupt flags, refer to the INTFLAG register description. The SPI has one common interrupt request line for all the interrupt sources. The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for interrupt requests. Refer to the Nested Vector Interrupt Controller for details.

32.6.4.3 Events

Not applicable.

32.6.5 Sleep Mode Operation

The behavior in sleep mode is depending on the Host/Client configuration and the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY):

Host operation, CTRLA.RUNSTDBY=1: The peripheral clock GCLK_SERCOM_CORE will continue to run in idle sleep mode and in standby sleep mode. Any interrupt can wake up the device.
Host operation, CTRLA.RUNSTDBY=0: GLK_SERCOMx_CORE will be disabled after the ongoing transaction is finished. Any interrupt can wake up the device. SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 558

Client operation, CTRLA.RUNSTDBY=1: The Receive Complete interrupt can wake up the device.
Client operation, CTRLA.RUNSTDBY=0: All reception will be dropped, including the ongoing transaction.

32.6.6 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written:

Software Reset bit in the CTRLA register (CTRLA.SWRST)
Enable bit in the CTRLA register (CTRLA.ENABLE)
Receiver Enable bit in the CTRLB register (CTRLB.RXEN) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 559

32.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 RUNSTDBY MODE[2:0] ENABLE SWRST 15:8 IBON 23:16 DIPO[1:0] DOPO[1:0] 31:24 DORD CPOL CPHA FORM[3:0] 0x04 CTRLB 7:0 PLOADEN CHSIZE[2:0] 15:8 AMODE[1:0] MSSEN SSDE 23:16 RXEN 31:24 0x08 ... 0x0B Reserved 0x0C BAUD 7:0 BAUD[7:0] 0x0D ... 0x13 Reserved 0x14 INTENCLR 7:0 ERROR SSL RXC TXC DRE 0x15 Reserved 0x16 INTENSET 7:0 ERROR SSL RXC TXC DRE 0x17 Reserved 0x18 INTFLAG 7:0 ERROR SSL RXC TXC DRE 0x19 Reserved 0x1A STATUS 7:0 BUFOVF 15:8 0x1C SYNCBUSY 7:0 CTRLB ENABLE SWRST 15:8 23:16 31:24 0x20 ... 0x23 Reserved 0x24 ADDR 7:0 ADDR[7:0] 15:8 23:16 ADDRMASK[7:0] 31:24 0x28 DATA 7:0 DATA[7:0] 15:8 DATA[8] 0x2A ... 0x2F Reserved 0x30 DBGCTRL 7:0 DBGSTOP

32.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-Synchronized" and/or "Write-Synchronized" property in each individual register description. Refer to 32.6.6. Synchronization. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 560

32.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 DORD CPOL CPHA FORM[3:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIPO[1:0] DOPO[1:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 IBON Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 RUNSTDBY MODE[2:0] ENABLE SWRST Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 30 – DORD Data Order This bit selects the data order when a character is shifted out from the shift register. This bit is not synchronized. Value Description 0 MSB is transferred first. 1 LSB is transferred first. Bit 29 – CPOL Clock Polarity In combination with the Clock Phase bit (CPHA), this bit determines the SPI transfer mode. This bit is not synchronized. Value Description 0 SCK is low when idle. The leading edge of a clock cycle is a rising edge, while the trailing edge is a falling edge. 1 SCK is high when idle. The leading edge of a clock cycle is a falling edge, while the trailing edge is a rising edge. Bit 28 – CPHA Clock Phase In combination with the Clock Polarity bit (CPOL), this bit determines the SPI transfer mode. This bit is not synchronized. Mode CPOL CPHA Leading Edge Trailing Edge 0x0 0 0 Rising, sample Falling, change 0x1 0 1 Rising, change Falling, sample 0x2 1 0 Falling, sample Rising, change 0x3 1 1 Falling, change Rising, sample Value Description 0 The data is sampled on a leading SCK edge and changed on a trailing SCK edge. 1 The data is sampled on a trailing SCK edge and changed on a leading SCK edge. SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 561

Bits 27:24 – FORM[3:0] Frame Format This bit field selects the various frame formats supported by the SPI in Client mode. When the 'SPI frame with address' format is selected, the first byte received is checked against the ADDR register. FORM[3:0] Name Description 0x0 SPI SPI frame 0x1 - Reserved 0x2 SPI_ADDR SPI frame with address 0x3-0xF - Reserved Bits 21:20 – DIPO[1:0] Data In Pinout These bits define the data in (DI) pad configurations. In Host operation, DI is MISO. In Client operation, DI is MOSI. These bits are not synchronized. DIPO[1:0] Name Description 0x0 PAD[0] SERCOM PAD[0] is used as data input 0x1 PAD[1] SERCOM PAD[1] is used as data input 0x2 PAD[2] SERCOM PAD[2] is used as data input 0x3 PAD[3] SERCOM PAD[3] is used as data input Bits 17:16 – DOPO[1:0] Data Out Pinout This bit defines the available pad configurations for data out (DO) and the serial clock (SCK). In Client operation, the Client select line (SS) is controlled by DOPO, while in Host operation the SS line is controlled by the port configuration. In Host operation, DO is MOSI. In Client operation, DO is MISO. These bits are not synchronized. DOPO DO SCK Client SS Host SS 0x0 PAD[0] PAD[1] PAD[2] System configuration 0x1 PAD[2] PAD[3] PAD[1] System configuration 0x2 PAD[3] PAD[1] PAD[2] System configuration 0x3 PAD[0] PAD[3] PAD[1] System configuration Bit 8 – IBON Immediate Buffer Overflow Notification This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is set when a buffer overflow occurs. This bit is not synchronized. Value Description 0 STATUS.BUFOVF is set when it occurs in the data stream. 1 STATUS.BUFOVF is set immediately upon buffer overflow. Bit 7 – RUNSTDBY Run In Standby This bit defines the functionality in standby sleep mode. These bits are not synchronized. RUNSTDBY Client Host 0x0 Disabled. All reception is dropped, including the ongoing transaction. Generic clock is disabled when ongoing transaction is finished. All interrupts can wake up the device. 0x1 Ongoing transaction continues, wake on Receive Complete interrupt. Generic clock is enabled while in sleep modes. All interrupts can wake up the device. Bits 4:2 – MODE[2:0] Operating Mode These bits must be written to 0x2 or 0x3 to select the SPI serial communication interface of the SERCOM. 0x2: SPI Client operation 0x3: SPI Host operation SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 562

These bits are not synchronized. Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the Synchronization Enable Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the operation is complete. This bit is not enable-protected. Value Description 0 The peripheral is disabled or being disabled. 1 The peripheral is enabled or being enabled. Bit 0 – SWRST Software Reset Writing '0' to this bit has no effect. Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing ''1' to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY. SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Value Description 0 There is no reset operation ongoing. 1 The reset operation is ongoing. SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 563

32.8.2 Control B

Name: CTRLB Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 RXEN Access R/W Reset 0 Bit 15 14 13 12 11 10 9 8 AMODE[1:0] MSSEN SSDE Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PLOADEN CHSIZE[2:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 17 – RXEN Receiver Enable Writing '0' to this bit will disable the SPI receiver immediately. The receive buffer will be flushed, data from ongoing receptions will be lost and STATUS.BUFOVF will be cleared. Writing '1' to CTRLB.RXEN when the SPI is disabled will set CTRLB.RXEN immediately. When the SPI is enabled, CTRLB.RXEN will be cleared, SYNCBUSY.CTRLB will be set and remain set until the receiver is enabled. When the receiver is enabled CTRLB.RXEN will read back as '1'. Writing '1' to CTRLB.RXEN when the SPI is enabled will set SYNCBUSY.CTRLB, which will remain set until the receiver is enabled, and CTRLB.RXEN will read back as '1'. This bit is not enable-protected. Value Description 0 The receiver is disabled or being enabled. 1 The receiver is enabled or it will be enabled when SPI is enabled. Bits 15:14 – AMODE[1:0] Address Mode These bits set the Client addressing mode when the frame format (CTRLA.FORM) with address is used. They are unused in Host mode. AMODE[1:0] Name Description 0x0 MASK ADDRMASK is used as a mask to the ADDR register 0x1 2_ADDRS The Client responds to the two unique addresses in ADDR and ADDRMASK 0x2 RANGE The Client responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit 0x3 - Reserved Bit 13 – MSSEN Host Client Select Enable This bit enables hardware Client select (SS) control. Value Description 0 Hardware SS control is disabled. 1 Hardware SS control is enabled. SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 564

Bit 9 – SSDE Client Select Low Detect Enable This bit enables wake up when the Client select (SS) pin transitions from high to low. Value Description 0 SS low detector is disabled. 1 SS low detector is enabled. Bit 6 – PLOADEN Client Data Preload Enable Setting this bit will enable preloading of the Client shift register when there is no transfer in progress. If the SS line is high when DATA is written, it will be transferred immediately to the shift register. Bits 2:0 – CHSIZE[2:0] Character Size CHSIZE[2:0] Name Description 0x0 8BIT 8 bits 0x1 9BIT 9 bits 0x2-0x7 - Reserved SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 565

32.8.3 Baud Rate

Name: BAUD Offset: 0x0C Reset: 0x00 Property: PAC Write-Protection, Enable-Protected Bit 7 6 5 4 3 2 1 0 BAUD[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – BAUD[7:0] Baud Register These bits control the clock generation, as described in the Clock Generation - Baud-Rate Generator. For further information, refer to Asynchronous Arithmetic Mode BAUD Value Selection. SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 566

32.8.4 Interrupt Enable Clear

Name: INTENCLR Offset: 0x14 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 5 4 3 2 1 0 ERROR SSL RXC TXC DRE Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 – ERROR Error Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. Value Description 0 Error interrupt is disabled. 1 Error interrupt is enabled. Bit 3 – SSL Client Select Low Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Client Select Low Interrupt Enable bit, which disables the Client Select Low interrupt. Value Description 0 Client Select Low interrupt is disabled. 1 Client Select Low interrupt is enabled. Bit 2 – RXC Receive Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete interrupt. Value Description 0 Receive Complete interrupt is disabled. 1 Receive Complete interrupt is enabled. Bit 1 – TXC Transmit Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Transmit Complete Interrupt Enable bit, which disable the Transmit Complete interrupt. Value Description 0 Transmit Complete interrupt is disabled. 1 Transmit Complete interrupt is enabled. Bit 0 – DRE Data Register Empty Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register Empty interrupt. Value Description 0 Data Register Empty interrupt is disabled. 1 Data Register Empty interrupt is enabled. SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 567

32.8.5 Interrupt Enable Set

Name: INTENSET Offset: 0x16 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 5 4 3 2 1 0 ERROR SSL RXC TXC DRE Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 – ERROR Error Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. Value Description 0 Error interrupt is disabled. 1 Error interrupt is enabled. Bit 3 – SSL Client Select Low Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Client Select Low Interrupt Enable bit, which enables the Client Select Low interrupt. Value Description 0 Client Select Low interrupt is disabled. 1 Client Select Low interrupt is enabled. Bit 2 – RXC Receive Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive Complete interrupt. Value Description 0 Receive Complete interrupt is disabled. 1 Receive Complete interrupt is enabled. Bit 1 – TXC Transmit Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete interrupt. Value Description 0 Transmit Complete interrupt is disabled. 1 Transmit Complete interrupt is enabled. Bit 0 – DRE Data Register Empty Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register Empty interrupt. Value Description 0 Data Register Empty interrupt is disabled. 1 Data Register Empty interrupt is enabled. SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 568

32.8.6 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x18 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 ERROR SSL RXC TXC DRE Access R/W R/W R R/W R Reset 0 0 0 0 0 Bit 7 – ERROR Error This flag is cleared by writing '1' to it. This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS register. The BUFOVF error will set this interrupt flag. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 3 – SSL Client Select Low This flag is cleared by writing '1' to it. This bit is set when a high to low transition is detected on the _SS pin in Client mode and Client Select Low Detect (CTRLB.SSDE) is enabled. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 2 – RXC Receive Complete This flag is cleared by reading the Data (DATA) register or by disabling the receiver. This flag is set when there are unread data in the receive buffer. If address matching is enabled, the first data received in a transaction will be an address. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. Bit 1 – TXC Transmit Complete This flag is cleared by writing '1' to it or by writing new data to DATA. In Host mode, this flag is set when the data have been shifted out and there are no new data in DATA. In Client mode, this flag is set when the _SS pin is pulled high. If address matching is enabled, this flag is only set if the transaction was initiated with an address match. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 0 – DRE Data Register Empty This flag is cleared by writing new data to DATA. This flag is set when DATA is empty and ready for new data to transmit. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 569

32.8.7 Status

Name: STATUS Offset: 0x1A Reset: 0x0000 Property: – Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 BUFOVF Access R/W Reset 0 Bit 2 – BUFOVF Buffer Overflow Reading this bit before reading DATA will indicate the error status of the next character to be read. This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set when a buffer overflow condition is detected. See also CTRLA.IBON for overflow handling. When set, the corresponding RxDATA will be zero. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Value Description 0 No Buffer Overflow has occurred. 1 A Buffer Overflow has occurred. SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 570

32.8.8 Synchronization Busy

Name: SYNCBUSY Offset: 0x1C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CTRLB ENABLE SWRST Access R R R Reset 0 0 0 Bit 2 – CTRLB CTRLB Synchronization Busy Writing to the CTRLB when the SERCOM is enabled requires synchronization. Ongoing synchronization is indicated by SYNCBUSY.CTRLB=1 until synchronization is complete. If CTRLB is written while SYNCBUSY.CTRLB=1, an APB error will be generated. Value Description 0 CTRLB synchronization is not busy. 1 CTRLB synchronization is busy. Bit 1 – ENABLE SERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. Ongoing synchronization is indicated by SYNCBUSY.ENABLE=1 until synchronization is complete. Writes to any register (except for CTRLA.SWRST) while enable synchronization is on-going will be discarded and an APB error will be generated. Value Description 0 Enable synchronization is not busy. 1 Enable synchronization is busy. Bit 0 – SWRST Software Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. Ongoing synchronization is indicated by SYNCBUSY.SWRST=1 until synchronization is complete. Writes to any register while synchronization is on-going will be discarded and an APB error will be generated. Value Description 0 SWRST synchronization is not busy. 1 SWRST synchronization is busy. SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 571

32.8.9 Address

Name: ADDR Offset: 0x24 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 ADDRMASK[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 23:16 – ADDRMASK[7:0] Address Mask These bits hold the address mask when the transaction format with address is used (CTRLA.FORM, CTRLB.AMODE). Bits 7:0 – ADDR[7:0] Address These bits hold the address when the transaction format with address is used (CTRLA.FORM, CTRLB.AMODE). SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 572

32.8.10 Data

Name: DATA Offset: 0x28 Reset: 0x0000 Property: – Bit 15 14 13 12 11 10 9 8 DATA[8] Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 8:0 – DATA[8:0] Data Reading these bits will return the contents of the receive data buffer. The register should be read only when the Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set. Writing these bits will write the transmit data buffer. This register should be written only when the Data Register Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set. SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 573

32.8.11 Debug Control

Name: DBGCTRL Offset: 0x30 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DBGSTOP Access R/W Reset 0 Bit 0 – DBGSTOP Debug Stop Mode This bit controls the functionality when the CPU is halted by an external debugger. Value Description 0 The baud-rate generator continues normal operation when the CPU is halted by an external debugger. 1 The baud-rate generator is halted when the CPU is halted by an external debugger. SAM L22 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 574

SERCOM I2C – SERCOM Inter-Integrated Circuit

33.1 Overview

The inter-integrated circuit ( I2C) interface is one of the available modes in the SERCOM - Serial Communication Interface. The I2C interface uses the SERCOM transmitter and receiver configured as shown in Figure 33-1. Labels in capital letters are registers accessible by the CPU, while lowercase labels are internal to the SERCOM. Each Host and Client have a separate I2C interface containing a shift register, a transmit buffer and a receive buffer. In addition, the I2C Host uses the SERCOM baud-rate generator, while the I2C Client uses the SERCOM address match logic.

33.2 Features

SERCOM I2C includes the following features:

Host or Client operation
Can be used with DMA
Philips I 2C compatible
SMBus ™ compatible
PMBus compatible
Support of 100kHz and 400kHz, 1MHz and 3.4MHz I 2C mode low system clock frequencies
Physical interface includes: – Slew-rate limited outputs – Filtered inputs
Client operation: – Operation in all sleep modes – Wake-up on address match – 7-bit and 10-bit Address match in hardware for:
Unique address and/or 7-bit general call address
Address range
Two unique addresses can be used with DMA References:

33.3 Block Diagram

Figure 33-1. I2C Single-Host Single-Client Interconnection BAUD TxDATA RxDATA baud rate generator SCL hold low shift register TxDATA RxDATA shift register 0 0 0 0 SCL hold low ADDR/ADDRMASK SDA SCL Host Client

33.4 Signal Description

Signal Name Type Description PAD[0] Digital I/O SDA PAD[1] Digital I/O SCL PAD[2] Digital I/O SDA_OUT (4-wire) PAD[3] Digital I/O SDC_OUT (4-wire) One signal can be mapped on several pins. Not all the pins are I2C pins. Refer to SERCOM USART and I²C Configurations for additional information References: I/O Multiplexing and Considerations

33.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

33.5.1 I/O Lines

In order to use the I/O lines of this peripheral, the I/O pins must be configured using the I/O Pin Controller (PORT). When the SERCOM is used in I2C mode, the SERCOM controls the direction and value of the I/O pins. PORT Control bit PINCFGn.DRVSTR is still effective for the SERCOM output pins. PORT Control bit PINCFGn.PULLEN is still effective on the SERCOM input pins, but is limited to the enabling/disabling of a pull down only (it is not possible to enable/disable a pull up). If the receiver or transmitter is disabled, these pins can be used for other purposes.

33.5.2 Power Management

This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake up the device from sleep modes. References: PM - Power Manager SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 576

33.5.3 Clocks

The SERCOM bus clock (CLK_SERCOMx_APB) is enabled by default, and can be enabled and disabled in the Main Clock Controller and the Power Manager. Two generic clocks ared used by SERCOM, GCLK_SERCOMx_CORE and GCLK_SERCOM_SLOW. The core clock (GCLK_SERCOMx_CORE) can clock the I2C when working as a Host. The slow clock (GCLK_SERCOM_SLOW) is required only for certain functions, e.g. SMBus timing. These clocks must be configured and enabled in the Generic Clock Controller (GCLK) before using the I2C. These generic clocks are asynchronous to the bus clock (CLK_SERCOMx_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to 33.6.6. Synchronization for further details. References: GCLK - Generic Clock Controller Peripheral Clock Masking PM - Power Manager

33.5.4 DMA

33.5.5 Interrupts

33.5.6 Events

Not applicable.

33.5.7 Debug Operation

33.5.8 Register Access Protection

Registers with write-access can be write-protected optionally by the 11. PAC - Peripheral Access Controller. PAC Write-Protection is not available for the following registers:

Interrupt Flag Clear and Status register (INTFLAG)
Status register (STATUS)
Data register (DATA)
Address register (ADDR) Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger.

33.5.9 Analog Connections

33.6 Functional Description

33.6.1 Principle of Operation

The I2C interface uses two physical lines for communication:

Serial Data Line (SDA) for packet transfer
Serial Clock Line (SCL) for the bus clock A transaction starts with the I2C Host sending the start condition, followed by a 7-bit address and a direction bit (read or write to/from the Client). The addressed I2C Client will then acknowledge (ACK) the address, and data packet transactions can begin. Every 9-bit data packet consists of 8 data bits followed by a one-bit reply indicating whether the data was acknowledged or not. If a data packet is not acknowledged (NACK), whether by the I2C Client or Host, the I2C Host takes action by either terminating the transaction by sending the stop condition, or by sending a repeated start to transfer more data. The following figure illustrates the possible transaction formats and Transaction Diagram Symbols explains the transaction symbols. These symbols will be used in the following descriptions. Figure 33-2. Basic I2C Transaction Diagram SDA SCL S ADDRESS R/W ACK DATA ACK DATA ACK/NACK P S ADDRESS R/W A DATA PA DATA A/A Direction Address Packet Data Packet #0 Data Packet #1 Transaction SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 578

Transaction Diagram Symbols S Sr A A R W P START condition repeated START condition STOP condition Host driving bus Client driving bus Either Host or Client driving bus Acknowledge (ACK) Not Acknowledge (NACK) Host Read Host Write Bus Driver Special Bus Conditions Data Package Direction Acknowledge '1' '0' '0' '1'

33.6.2 Basic Operation

33.6.2.1 Initialization

The following registers are enable-protected, meaning they can be written only when the I2C interface is disabled (CTRLA.ENABLE is ‘0’):

Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST) bits
Control B register (CTRLB), except Acknowledge Action (CTRLB.ACKACT) and Command (CTRLB.CMD) bits
Baud register (BAUD)
Address register (ADDR) in Client operation. When the I2C is enabled or is being enabled (CTRLA.ENABLE=1), writing to these registers will be discarded. If the I2C is being disabled, writing to these registers will be completed after the disabling. Enable-protection is denoted by the "Enable-Protection" property in the register description. Before the I2C is enabled it must be configured as outlined by the following steps: 1. Select I 2C Host or Client mode by writing 0x4 or 0x5 to the Operating Mode bits in the CTRLA register (CTRLA.MODE). 2. If desired, select the SDA Hold Time value in the CTRLA register (CTRLA.SDAHOLD). 3. If desired, enable smart operation by setting the Smart Mode Enable bit in the CTRLB register (CTRLB.SMEN). 4. If desired, enable SCL low time-out by setting the SCL Low Time-Out bit in the Control A register (CTRLA.LOWTOUT). 5. In Host mode: a. Select the inactive bus time-out in the Inactive Time-Out bit group in the CTRLA register (CTRLA.INACTOUT). b. Write the Baud Rate register (BAUD) to generate the desired baud rate. In Client mode: a. Configure the address match configuration by writing the Address Mode value in the CTRLB register (CTRLB.AMODE). b. Set the Address and Address Mask value in the Address register (ADDR.ADDR and ADDR.ADDRMASK) according to the address configuration. SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 579

33.6.2.2 Enabling, Disabling, and Resetting

This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and disabled by writing '0' to it. Refer to 33.10.1. CTRLA for details.

33.6.2.3 I2C Bus State Logic

The bus state logic includes several logic blocks that continuously monitor the activity on the I2C bus lines in all sleep modes. The start and stop detectors and the bit counter are all essential in the process of determining the current bus state. The bus state is determined according to Bus State Diagram. Software can get the current bus state by reading the Host Bus State bits in the Status register (STATUS.BUSSTATE). The value of STATUS.BUSSTATE in the figure is shown in binary. Figure 33-3. Bus State Diagram RESET Write ADDR to g enerate Start Condition IDLE (0b01) Start Condition BUSY (0b11)Timeout or Stop Condition UNKNOWN (0b00) OWNER (0b10) Lost A rbitration Repeated Start Condition Write ADDR to g enerate Repeated Start Condition Stop Condition Timeout or Stop Condition The bus state machine is active when the I2C Host is enabled. After the I2C Host has been enabled, the bus state is UNKNOWN (0b00). From the UNKNOWN state, the bus will transition to IDLE (0b01) by either:

Forcing by by writing 0b01 to STATUS.BUSSTATE
A stop condition is detected on the bus
If the inactive bus time-out is configured for SMBus compatibility (CTRLA.INACTOUT) and a time-out occurs. Note: Once a known bus state is established, the bus state logic will not re-enter the UNKNOWN state. When the bus is IDLE it is ready for a new transaction. If a start condition is issued on the bus by another I2C Host in a multi-Host setup, the bus becomes BUSY (0b11). The bus will re-enter IDLE either when a stop condition is detected, or when a time-out occurs (inactive bus time-out needs to be configured). If a start condition is generated internally by writing the Address bit group in the Address register (ADDR.ADDR) while IDLE, the OWNER state (0b10) is entered. If the complete transaction was performed without interference, i.e., arbitration was not lost, the I2C Host can issue a stop condition, which will change the bus state back to IDLE. However, if a packet collision is detected while in OWNER state, the arbitration is assumed lost and the bus state becomes BUSY until a stop condition is detected. A repeated start condition will change the bus state only if arbitration is lost while issuing a repeated start. SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 580

Regardless of winning or losing arbitration, the entire address will be sent. If arbitration is lost, only 'ones' are transmitted from the point of losing arbitration and the rest of the address length. Note: Violating the protocol may cause the I2C to hang. If this happens it is possible to recover from this state by a software reset (CTRLA.SWRST='1'). References: Host CTRLA Register

33.6.2.4 I2C Host Operation

The I2C Host is byte-oriented and interrupt based. The number of interrupts generated is kept at a minimum by automatic handling of most events. The software driver complexity and code size are reduced by auto-triggering of operations, and a special smart mode, which can be enabled by the Smart Mode Enable bit in the Control A register (CTRLA.SMEN). The I2C Host has two interrupt strategies. When SCL Stretch Mode (CTRLA.SCLSM) is '0', SCL is stretched before or after the acknowledge bit . In this mode the I2C Host operates according to Host Behavioral Diagram (SCLSM=0). The circles labelled "Mn" (M1, M2..) indicate the nodes the bus logic can jump to, based on software or hardware interaction. This diagram is used as reference for the description of the I2C Host operation throughout the document. Figure 33-4. I2C Host Behavioral Diagram (SCLSM=0) IDLE S BUSYBUSY P Sr P R DATA Wait for IDLE ADDRESS W A/ADATA APPLICATION SW SW Sr P BUSY M4ASW A/A A/A A/A A IDLE IDLE SB INTERRUPT + SCL HOLD MB INTERRUPT + SCL HOLD SW SW SW BUSYR/W SW Software interaction A A R/W BUSY M4 The host provides data on the bus Addressed client provides data on the bus In the second strategy (CTRLA.SCLSM=1), interrupts only occur after the ACK bit, as in Host Behavioral Diagram (SCLSM=1). This strategy can be used when it is not necessary to check DATA before acknowledging. Note: I2C High-speed (Hs) mode requires CTRLA.SCLSM=1. SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 581

Figure 33-5. I2C Host Behavioral Diagram (SCLSM=1) IDLE S BUSYBUSY P Sr P R DATA W A/ADATA APPLICATION SW SW Sr P BUSY M4SW A/A A IDLE IDLE MB INTERRUPT + SCL HOLD SW SW SW BUSYR/W A A R/W BUSY M4 SW Software interaction The host provides data on the bus Addressed client provides data on the bus SB INTERRUPT + SCL HOLD Wait for IDLE ADDRESS Host Clock Generation The SERCOM peripheral supports several I2C bi-directional modes:

Standard mode ( Sm) up to 100kHz
Fast mode ( Fm) up to 400kHz
Fast mode Plus ( Fm+) up to 1MHz
High-speed mode ( Hs) up to 3.4MHz The Host clock configuration for Sm, Fm, and Fm+ are described in Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus) . For Hs, refer to Host Clock Generation (High-Speed Mode) . Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus) In I2C Sm, Fm, and Fm+ mode, the Host clock (SCL) frequency is determined as described in this section: The low (TLOW) and high (THIGH) times are determined by the Baud Rate register (BAUD), while the rise (TRISE) and fall (TFALL) times are determined by the bus topology. Because of the wired-AND logic of the bus, TFALL will be considered as part of TLOW. Likewise, TRISE will be in a state between TLOW and THIGH until a high state has been detected. SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 582

Figure 33-6. SCL Timing TSU;STO THD;STA TBUF TFALL TLOW TLOW THIGH SCL SDA P S TSU;STA Sr The following parameters are timed using the SCL low time period TLOW. This comes from the Host Baud Rate Low bit group in the Baud Rate register (BAUD.BAUDLOW). When BAUD.BAUDLOW=0, or the Host Baud Rate bit group in the Baud Rate register (BAUD.BAUD) determines it.

T LOW – Low period of SCL clock
T SU;STO – Set-up time for stop condition
T BUF – Bus free time between stop and start conditions
T HD;STA – Hold time (repeated) start condition
T SU;STA – Set-up time for repeated start condition
T HIGH is timed using the SCL high time count from BAUD.BAUD
T RISE is determined by the bus impedance; for internal pull-ups. Refer to the Electrical Characteristics.
T FALL is determined by the open-drain current limit and bus impedance; can typically be regarded as zero. Refer to the Electrical Characteristics for details. The SCL frequency is given by: f SCL = 1 T LOW + T HIGH + T RISE When BAUD.BAUDLOW is zero, the BAUD.BAUD value is used to time both SCL high and SCL low. In this case the following formula will give the SCL frequency: f SCL = f GCLK 10 + 2 B A U D + f GCLK ⋅ T RISE When BAUD.BAUDLOW is non-zero, the following formula determines the SCL frequency: f SCL = f GCLK 10 + B AU D + B A U DL OW + f GCLK ⋅ T RISE The following formulas can determine the SCL TLOW and THIGH times: T LOW = B AU D LO W + 5 f GCLK T HIGH = B AU D + 5 f GCLK Note: The I2C standard Fm+ (Fast-mode plus) requires a nominal high to low SCL ratio of 1:2, and BAUD should be set accordingly. At a minimum, BAUD.BAUD and/or BAUD.BAUDLOW must be non-zero. Startup Timing The minimum time between SDA transition and SCL rising edge is 6 APB cycles when the DATA register is written in smart mode. If a greater startup time is required due to long rise times, the time between DATA write and IF clear must be controlled by software. Note: When timing is controlled by user, the Smart Mode cannot be enabled. References: SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 583

Host Clock Generation (High-Speed Mode) For I2C Hs transfers, there is no SCL synchronization. Instead, the SCL frequency is determined by the GCLK_SERCOMx_CORE frequency (fGCLK) and the High-Speed Baud setting in the Baud register (BAUD.HSBAUD). When BAUD.HSBAUDLOW=0, the HSBAUD value will determine both SCL high and SCL low. In this case the following formula determines the SCL frequency. f SCL = f GCLK 2 + 2 ⋅ HS B AU D When HSBAUDLOW is non-zero, the following formula determines the SCL frequency. f SCL = f GCLK 2 + HS B AU D + HS B A U DL OW Note: The I2C standard Hs (High-speed) requires a nominal high to low SCL ratio of 1:2, and HSBAUD should be set accordingly. At a minimum, BAUD.HSBAUD and/or BAUD.HSBAUDLOW must be non-zero. Transmitting Address Packets The I2C Host starts a bus transaction by writing the I2C Client address to ADDR.ADDR and the direction bit, as described in 33.6.1. Principle of Operation. If the bus is busy, the I2C Host will wait until the bus becomes idle before continuing the operation. When the bus is idle, the I2C Host will issue a start condition on the bus. The I2C Host will then transmit an address packet using the address written to ADDR.ADDR. After the address packet has been transmitted by the I2C Host, one of four cases will arise according to arbitration and transfer direction. Case 1: Arbitration lost or bus error during address packet transmission If arbitration was lost during transmission of the address packet, the Host on Bus bit in the Interrupt Flag Status and Clear register (INTFLAG.MB) and the Arbitration Lost bit in the Status register (STATUS.ARBLOST) are both set. Serial data output to SDA is disabled, and the SCL is released, which disables clock stretching. In effect the I2C Host is no longer allowed to execute any operation on the bus until the bus is idle again. A bus error will behave similarly to the arbitration lost condition. In this case, the MB interrupt flag and Host Bus Error bit in the Status register (STATUS.BUSERR) are both set in addition to STATUS.ARBLOST. The Host Received Not Acknowledge bit in the Status register (STATUS.RXNACK) will always contain the last successfully received acknowledge or not acknowledge indication. In this case, software will typically inform the application code of the condition and then clear the interrupt flag before exiting the interrupt routine. No other flags have to be cleared at this moment, because all flags will be cleared automatically the next time the ADDR.ADDR register is written. Case 2: Address packet transmit complete – No ACK received If there is no I2C Client device responding to the address packet, then the INTFLAG.MB interrupt flag and STATUS.RXNACK will be set. The clock hold is active at this point, preventing further activity on the bus. The missing ACK response can indicate that the I2C Client is busy with other tasks or sleeping. Therefore, it is not able to respond. In this event, the next step can be either issuing a stop condition (recommended) or resending the address packet by a repeated start condition. When using SMBus logic, the Client must ACK the address. If there is no response, it means that the Client is not available on the bus. Case 3: Address packet transmit complete – Write packet, Host on Bus set If the I2C Host receives an acknowledge response from the I2C Client, INTFLAG.MB will be set and STATUS.RXNACK will be cleared. The clock hold is active at this point, preventing further activity on the bus. In this case, the software implementation becomes highly protocol dependent. Three possible actions can enable the I2C operation to continue:

Initiate a data transmit operation by writing the data byte to be transmitted into DATA.DATA.
Transmit a new address packet by writing ADDR.ADDR. A repeated start condition will automatically be inserted before the address packet.
Issue a stop condition, consequently terminating the transaction. Case 4: Address packet transmit complete – Read packet, Client on Bus set SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 584

If the I2C Host receives an ACK from the I2C Client, the I2C Host proceeds to receive the next byte of data from the I2C Client. When the first data byte is received, the Client on Bus bit in the Interrupt Flag register (INTFLAG.SB) will be set and STATUS.RXNACK will be cleared. The clock hold is active at this point, preventing further activity on the bus. In this case, the software implementation becomes highly protocol dependent. Three possible actions can enable the I2C operation to continue:

Let the I 2C Host continue to read data by acknowledging the data received. ACK can be sent by software, or automatically in smart mode.
Transmit a new address packet.
Terminate the transaction by issuing a stop condition. Note: An ACK or NACK will be automatically transmitted if smart mode is enabled. The Acknowledge Action bit in the Control B register (CTRLB.ACKACT) determines whether ACK or NACK should be sent. Transmitting Data Packets When an address packet with direction Host Write (see Figure 33-2) was transmitted successfully , INTFLAG.MB will be set. The I2C Host will start transmitting data via the I2C bus by writing to DATA.DATA, and monitor continuously for packet collisions. I If a collision is detected, the I2C Host will lose arbitration and STATUS.ARBLOST will be set. If the transmit was successful, the I2C Host will receive an ACK bit from the I2C Client, and STATUS.RXNACK will be cleared. INTFLAG.MB will be set in both cases, regardless of arbitration outcome. It is recommended to read STATUS.ARBLOST and handle the arbitration lost condition in the beginning of the I2C Host on Bus interrupt. This can be done as there is no difference between handling address and data packet arbitration. STATUS.RXNACK must be checked for each data packet transmitted before the next data packet transmission can commence. The I2C Host is not allowed to continue transmitting data packets if a NACK is received from the I2C Client. Receiving Data Packets (SCLSM=0) When INTFLAG.SB is set, the I2C Host will already have received one data packet. The I2C Host must respond by sending either an ACK or NACK. Sending a NACK may be unsuccessful when arbitration is lost during the transmission. In this case, a lost arbitration will prevent setting INTFLAG.SB. Instead, INTFLAG.MB will indicate a change in arbitration. Handling of lost arbitration is the same as for data bit transmission. Receiving Data Packets (SCLSM=1) When INTFLAG.SB is set, the I2C Host will already have received one data packet and transmitted an ACK or NACK, depending on CTRLB.ACKACT. At this point, CTRLB.ACKACT must be set to the correct value for the next ACK bit, and the transaction can continue by reading DATA and issuing a command if not in the smart mode. High-Speed Mode High-speed transfers are a multi-step process, see the following figure. First, a Host code (0b00001nnn, where 'nnn' is a unique Host code) is transmitted in Full-speed mode, followed by a NACK since no Client should acknowledge. Arbitration is performed only during the Full-speed Host Code phase. The Host code is transmitted by writing the Host code to the address register (ADDR.ADDR) and writing the high-speed bit (ADDR.HS) to '0'. After the Host code and NACK have been transmitted, the Host write interrupt will be asserted. In the meanwhile, the Client address can be written to the ADDR.ADDR register together with ADDR.HS=1. Now in High-speed mode, the Host will generate a repeated start, followed by the Client address with RW-direction. The bus will remain in High-speed mode until a stop is generated. If a repeated start is desired, the ADDR.HS bit must again be written to '1', along with the new address ADDR.ADDR to be transmitted. SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 585

Figure 33-7. High Speed Transfer S A A/ASr PA DATA N Data Packets Host Code R/WADDRESS Sr ADDRESS Hs-mode continues F/S-modeHs-modeF/S-mode Transmitting in High-speed mode requires the I2C Host to be configured in High-speed mode (CTRLA.SPEED=0x2) and the SCL clock stretch mode (CTRLA.SCLSM) bit set to '1'. 10-Bit Addressing When 10-bit addressing is enabled by the Ten Bit Addressing Enable bit in the Address register (ADDR.TENBITEN=1) and the Address bit field ADDR.ADDR is written, the two address bytes will be transmitted, see the following figure. The addressed Client acknowledges the two address bytes, and the transaction continues. Regardless of whether the transaction is a read or write, the Host must start by sending the 10-bit address with the direction bit (ADDR.ADDR[0]) being zero. If the Host receives a NACK after the first byte, the write interrupt flag will be raised and the STATUS.RXNACK bit will be set. If the first byte is acknowledged by one or more Clients, then the Host will proceed to transmit the second address byte and the Host will first see the write interrupt flag after the second byte is transmitted. If the transaction direction is read-from-Client, the 10-bit address transmission must be followed by a repeated start and the first 7 bits of the address with the read/write bit equal to '1'. Figure 33-8. 10-bit Address Transmission for a Read Transaction S AW addr[7:0] A11110 addr[9:8] Sr AR S W 11110 addr[9:8] MB INTERRUPT This implies the following procedure for a 10-bit read operation: 1. Write the 10-bit address to ADDR.ADDR[10:1]. ADDR.TENBITEN must be '1', the direction bit (ADDR.ADDR[0]) must be '0' (can be written simultaneously with ADDR). 2. Once the Host on Bus interrupt is asserted, Write ADDR[7:0] register to '11110 address[9:8] 1'. ADDR.TENBITEN must be cleared (can be written simultaneously with ADDR). 3. Proceed to transmit data.

33.6.2.5 I2C Client Operation

The I2C Client is byte-oriented and interrupt-based. The number of interrupts generated is kept at a minimum by automatic handling of most events. The software driver complexity and code size are reduced by auto-triggering of operations, and a special smart mode, which can be enabled by the Smart Mode Enable bit in the Control A register (CTRLA.SMEN). The I2C Client has two interrupt strategies. When SCL Stretch Mode bit (CTRLA.SCLSM) is '0', SCL is stretched before or after the acknowledge bit. In this mode, the I2C Client operates according to the following figure. The circles labelled "Sn" (S1, S2..) indicate the nodes the bus logic can jump to, based on software or hardware interaction. This diagram is used as reference for the description of the I2C Client operation throughout the document. SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 586

Receiving Address Packets (SCLSM=0) When CTRLA.SCLSM=0, the I2C Client stretches the SCL line according to I2C Client Behavioral Diagram (SCLSM=0). When the I2C Client is properly configured, it will wait for a start condition. When a start condition is detected, the successive address packet will be received and checked by the address match logic. If the received address is not a match, the packet will be rejected, and the I2C Client will wait for a new start condition. If the received address is a match, the Address Match bit in the Interrupt Flag register (INTFLAG.AMATCH) will be set. SCL will be stretched until the I2C Client clears INTFLAG.AMATCH. As the I2C Client holds the clock by forcing SCL low, the software has unlimited time to respond. The direction of a transaction is determined by reading the Read / Write Direction bit in the Status register (STATUS.DIR). This bit will be updated only when a valid address packet is received. If the Transmit Collision bit in the Status register (STATUS.COLL) is set, this indicates that the last packet addressed to the I2C Client had a packet collision. A collision causes the SDA and SCL lines to be released without any notification to software. Therefore, the next AMATCH interrupt is the first indication of the previous packet’s collision. Collisions are intended to follow the SMBus Address Resolution Protocol (ARP). After the address packet has been received from the I2C Host, one of two cases will arise based on transfer direction. Case 1: Address packet accepted – Read flag set The STATUS.DIR bit is ‘1’, indicating an I2C Host read operation. The SCL line is forced low, stretching the bus clock. If an ACK is sent, I2C Client hardware will set the Data Ready bit in the Interrupt Flag register (INTFLAG.DRDY), indicating data are needed for transmit. If a NACK is sent, the I2C Client will wait for a new start condition and address match. Typically, software will immediately acknowledge the address packet by sending an ACK/NACK bit. The I2C Client Command bit field in the Control B register (CTRLB.CMD) can be written to '0x3' for both read and write operations as the command execution is dependent on the STATUS.DIR bit. Writing ‘1’ to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit. Case 2: Address packet accepted – Write flag set The STATUS.DIR bit is cleared, indicating an I2C Host write operation. The SCL line is forced low, stretching the bus clock. If an ACK is sent, the I2C Client will wait for data to be received. Data, repeated start or stop can be received. If a NACK is sent, the I2C Client will wait for a new start condition and address match. Typically, software will immediately acknowledge the address packet by sending an ACK/NACK. The I2C Client command CTRLB.CMD = 3 can be used for both read and write operation as the command execution is dependent on STATUS.DIR. Writing ‘1’ to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit. Receiving Address Packets (SCLSM=1) When SCLSM=1, the I2C Client will stretch the SCL line only after an ACK, see Client Behavioral Diagram (SCLSM=1). When the I2C Client is properly configured, it will wait for a start condition to be detected. When a start condition is detected, the successive address packet will be received and checked by the address match logic. If the received address is not a match, the packet will be rejected and the I2C Client will wait for a new start condition. If the address matches, the acknowledge action as configured by the Acknowledge Action bit Control B register (CTRLB.ACKACT) will be sent and the Address Match bit in the Interrupt Flag register (INTFLAG.AMATCH) is set. SCL will be stretched until the I2C Client clears INTFLAG.AMATCH. As the I2C Client holds the clock by forcing SCL low, the software is given unlimited time to respond to the address. The direction of a transaction is determined by reading the Read/Write Direction bit in the Status register (STATUS.DIR). This bit will be updated only when a valid address packet is received. If the Transmit Collision bit in the Status register (STATUS.COLL) is set, the last packet addressed to the I2C Client had a packet collision. A collision causes the SDA and SCL lines to be released without any notification to software. The next AMATCH interrupt is, therefore, the first indication of the previous packet’s collision. Collisions are intended to follow the SMBus Address Resolution Protocol (ARP). SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 588

After the address packet has been received from the I2C Host, INTFLAG.AMATCH be set to ‘1’ to clear it. Receiving and Transmitting Data Packets After the I2C Client has received an address packet, it will respond according to the direction either by waiting for the data packet to be received or by starting to send a data packet by writing to DATA.DATA. When a data packet is received or sent, INTFLAG.DRDY will be set. After receiving data, the I2C Client will send an acknowledge according to CTRLB.ACKACT. Case 1: Data received INTFLAG.DRDY is set, and SCL is held low, pending for SW interaction. Case 2: Data sent When a byte transmission is successfully completed, the INTFLAG.DRDY interrupt flag is set. If NACK is received, indicated by STATUS.RXNACK=1, the I2C Client must expect a stop or a repeated start to be received. The I2C Client must release the data line to allow the I2C Host to generate a stop or repeated start. Upon detecting a stop condition, the Stop Received bit in the Interrupt Flag register (INTFLAG.PREC) will be set and the I2C Client will return to IDLE state. High-Speed Mode When the I2C Client is configured in High-speed mode (Hs, CTRLA.SPEED=0x2) and CTRLA.SCLSM=1, switching between Full-speed and High-speed modes is automatic. When the Client recognizes a START followed by a Host code transmission and a NACK, it automatically switches to High-speed mode and sets the High-speed status bit (STATUS.HS). The Client will then remain in High-speed mode until a STOP is received. 10-Bit Addressing When 10-bit addressing is enabled (ADDR.TENBITEN=1), the two address bytes following a START will be checked against the 10-bit Client address recognition. The first byte of the address will always be acknowledged, and the second byte will raise the address interrupt flag, see the following figure. If the transaction is a write, then the 10-bit address will be followed by N data bytes. If the operation is a read, the 10-bit address will be followed by a repeated START and reception of '11110 ADDR[9:8] 1', and the second address interrupt will be received with the DIR bit set. The Client matches on the second address as it it was addressed by the previous 10-bit address. Figure 33-11. 10-bit Addressing S AW addr[7:0] A11110 addr[9:8] Sr RS W S W11110 addr[9:8] AMATCH INTERRUPT AMATCH INTERRUPT PMBus Group Command When the PMBus Group Command bit in the CTRLB register is set (CTRLB.GCMD=1) and 7-bit addressing is used, INTFLAG.PREC will be set when a STOP condition is detected on the bus. When CTRLB.GCMD=0, a STOP condition without address match will not be set INTFLAG.PREC. The group command protocol is used to send commands to more than one device. The commands are sent in one continuous transmission with a single STOP condition at the end. When the STOP condition is detected by the Clients addressed during the group command, they all begin executing the command they received. The following figure shows an example where this Client, bearing ADDRESS 1, is addressed after a repeated START condition. There can be multiple Clients addressed before and after this Client. Eventually, at the end of the group command, a single STOP is generated by the Host. At this point a STOP interrupt is asserted. SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 589

Figure 33-12. PMBus Group Command Example AS A n BytesWADDRESS 0 Command/Data ASr A n BytesWADDRESS 1 (this client) Command/Data S W S W ASr A n BytesWADDRESS 2 Command/Data P S W AMATCH INTERRUPT DRDY INTERRUPT PREC INTERRUPT

33.6.3 Additional Features

33.6.3.1 SMBus

The I2C includes three hardware SCL low time-outs which allow a time-out to occur for SMBus SCL low time-out, Host extend time-out, and Client extend time-out. This allows for SMBus functionality These time-outs are driven by the GCLK_SERCOM_SLOW clock. The GCLK_SERCOM_SLOW clock is used to accurately time the time-out and must be configured to use a 32.768 kHz oscillator. The I2C interface also allows for a SMBus compatible SDA hold time.

T TIMEOUT: SCL low time of 25..35ms – Measured for a single SCL low period. It is enabled by CTRLA.LOWTOUTEN.
T LOW:SEXT: Cumulative clock low extend time of 25 ms – Measured as the cumulative SCL low extend time by a Client device in a single message from the initial START to the STOP. It is enabled by CTRLA.SEXTTOEN.
T LOW:MEXT: Cumulative clock low extend time of 10 ms – Measured as the cumulative SCL low extend time by the Host device within a single byte from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. It is enabled by CTRLA.MEXTTOEN.

33.6.3.2 Smart Mode

The I2C interface has a smart mode that simplifies application code and minimizes the user interaction needed to adhere to the I2C protocol. The smart mode accomplishes this by automatically issuing an ACK or NACK (based on the content of CTRLB.ACKACT) as soon as DATA.DATA is read. 33.6.3.3 4-Wire Mode Writing a '1' to the Pin Usage bit in the Control A register (CTRLA.PINOUT) will enable 4-wire mode operation. In this mode, the internal I2C tri-state drivers are bypassed, and an external I2C compliant tri-state driver is needed when connecting to an I2C bus. SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 590

Figure 33-13. I2C Pad Interface SCL/SDA pad I2C Driver SCL_OUT/ SDA_OUT padPINOUT PINOUT SCL_IN/ SDA_IN SCL_OUT/ SDA_OUT

33.6.3.4 Quick Command

Setting the Quick Command Enable bit in the Control B register (CTRLB.QCEN) enables quick command. When quick command is enabled, the corresponding interrupt flag (INTFLAG.SB or INTFLAG.MB) is set immediately after the client acknowledges the address. At this point, the software can either issue a stop command or a repeated start by writing CTRLB.CMD or ADDR.ADDR.

33.6.4 DMA, Interrupts and Events

Table 33-1. Module Request for SERCOM I2C Client Condition Request DMA Interrupt Event Data needed for transmit (TX) (Client transmit mode) Yes (request cleared when data is written) NA Data received (RX) (Client receive mode) Yes (request cleared when data is read) Data Ready (DRDY) Yes Address Match (AMATCH) Yes Stop received (PREC) Yes Error (ERROR) Yes Table 33-2. Module Request for SERCOM I2C Host Condition Request DMA Interrupt Event Data needed for transmit (TX) (Host transmit mode) Yes (request cleared when data is written) NA Data needed for transmit (RX) (Host transmit mode) Yes (request cleared when data is read) Host on Bus (MB) Yes Stop received (SB) Yes Error (ERROR) Yes SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 591

33.6.4.1 DMA Operation

Smart mode must be enabled for DMA operation in the Control B register by writing CTRLB.SMEN=1. Client DMA When using the I2C Client with DMA, an address match will cause the address interrupt flag (INTFLAG.ADDRMATCH) to be raised. After the interrupt has been serviced, data transfer will be performed through DMA. The I2C Client generates the following requests:

Write data received (RX): The request is set when Host write data is received. The request is cleared when DATA is read.
Read data needed for transmit (TX): The request is set when data is needed for a Host read operation. The request is cleared when DATA is written. Host DMA When using the I2C Host with DMA, the ADDR register must be written with the desired address (ADDR.ADDR), transaction length (ADDR.LEN), and transaction length enable (ADDR.LENEN). When ADDR.LENEN is written to 1 along with ADDR.ADDR, ADDR.LEN determines the number of data bytes in the transaction from 0 to 255. DMA is then used to transfer ADDR.LEN bytes followed by an automatically generated NACK (for Host reads) and a STOP. If a NACK is received by the Client for a Host write transaction before ADDR.LEN bytes, a STOP will be automatically generated and the length error (STATUS.LENERR) will be raised along with the INTFLAG.ERROR interrupt. The I2C Host generates the following requests:
Read data received (RX): The request is set when Host read data is received. The request is cleared when DATA is read.
Write data needed for transmit (TX): The request is set when data is needed for a Host write operation. The request is cleared when DATA is written.

33.6.4.2 Interrupts

The I2C Client has the following interrupt sources. These are asynchronous interrupts. They can wake-up the device from any sleep mode:

Error (ERROR)
Data Ready (DRDY)
Address Match (AMATCH)
Stop Received (PREC) The I2C Host has the following interrupt sources. These are asynchronous interrupts. They can wake-up the device from any sleep mode:
Error (ERROR)
Client on Bus (SB)
Host on Bus (MB) Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the interrupt condition is meet. Each interrupt can be individually enabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request active until the interrupt flag is cleared, the interrupt is disabled or the I2C is reset. See 33.10.6. INTFLAG register for details on how to clear interrupt flags. The I2C has one common interrupt request line for all the interrupt sources. The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for interrupt requests. Refer to the Nested Vector Interrupt Controller for details.

33.6.4.3 Events

33.6.5 Sleep Mode Operation

The generic clock (GCLK_SERCOMx_CORE) will continue to run in idle sleep mode. If the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY) is '1', the GLK_SERCOMx_CORE will also run in standby sleep mode. Any interrupt can wake up the device. If CTRLA.RUNSTDBY=0, the GLK_SERCOMx_CORE will be disabled after any ongoing transaction is finished. Any interrupt can wake up the device. I2C Client Operation Writing CTRLA.RUNSTDBY=1 will allow the Address Match interrupt to wake up the device. When CTRLA.RUNSTDBY=0, all receptions will be dropped.

33.6.6 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written:

Software Reset bit in the CTRLA register (CTRLA.SWRST)
Enable bit in the CTRLA register (CTRLA.ENABLE)
Write to Bus State bits in the Status register (STATUS.BUSSTATE)
Address bits in the Address register (ADDR.ADDR) when in Host operation. The following registers are synchronized when written:
Data (DATA) when in Host operation Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 593

33.7 Register Summary - I2C Client

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 RUNSTDBY MODE[2:0] ENABLE SWRST 15:8 23:16 SEXTTOEN SDAHOLD[1:0] PINOUT 31:24 LOWTOUT SCLSM SPEED[1:0] 0x04 CTRLB 7:0 15:8 QCEN SMEN 23:16 ACKACT CMD[1:0] 31:24 0x08 ... 0x13 Reserved 0x14 INTENCLR 7:0 ERROR DRDY AMATCH PREC 0x15 Reserved 0x16 INTENSET 7:0 ERROR DRDY AMATCH PREC 0x17 Reserved 0x18 INTFLAG 7:0 ERROR DRDY AMATCH PREC 0x19 Reserved 0x1A STATUS 7:0 CLKHOLD LOWTOUT SR DIR RXNACK COLL BUSERR 15:8 HS SEXTTOUT 0x1C SYNCBUSY 7:0 ENABLE SWRST 15:8 23:16 31:24 0x20 ... 0x23 Reserved 0x24 ADDR 7:0 ADDR[6:0] GENCEN 15:8 TENBITEN ADDR[9:7] 23:16 ADDRMASK[6:0] 31:24 ADDRMASK[9:7] 0x28 DATA 7:0 DATA[7:0] 15:8

33.8 Register Description - I2C Client

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write- protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 33.5.8. Register Access Protection. Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write- Synchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to 33.6.6. Synchronization. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 594

33.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 LOWTOUT SCLSM SPEED[1:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SEXTTOEN SDAHOLD[1:0] PINOUT Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 RUNSTDBY MODE[2:0] ENABLE SWRST Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 30 – LOWTOUT SCL Low Time-Out This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the Client will release its clock hold, if enabled, and reset the internal state machine. Any interrupt flags set at the time of time-out will remain set. Value Description 0 Time-out disabled. 1 Time-out enabled. Bit 27 – SCLSM SCL Clock Stretch Mode This bit controls when SCL will be stretched for software interaction. This bit is not synchronized. Value Description

0 SCL stretch according to Figure 33-9

1 SCL stretch only after ACK bit according to Figure 33-10

Bits 25:24 – SPEED[1:0] Transfer Speed These bits define bus speed. These bits are not synchronized. Value Description 0x0 Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz 0x1 Fast-mode Plus (Fm+) up to 1 MHz 0x2 High-speed mode (Hs-mode) up to 3.4 MHz 0x3 Reserved Bit 23 – SEXTTOEN Client SCL Low Extend Time-Out This bit enables the Client SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the Client will release its clock hold if enabled and reset the internal state machine. Any interrupt flags set at the time of time-out will remain set. If the address was recognized, PREC will be set when a STOP is received. This bit is not synchronized. SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 595

0 Time-out disabled

1 Time-out enabled

Bits 21:20 – SDAHOLD[1:0] SDA Hold Time These bits define the SDA hold time with respect to the negative edge of SCL. These bits are not synchronized. Value Name Description 0x0 DIS Disabled 0x1 75 50-100ns hold time 0x2 450 300-600ns hold time 0x3 600 400-800ns hold time Bit 16 – PINOUT Pin Usage This bit sets the pin usage to either two- or four-wire operation: This bit is not synchronized. Value Description 0 4-wire operation disabled 1 4-wire operation enabled Bit 7 – RUNSTDBY Run in Standby This bit defines the functionality in standby sleep mode. This bit is not synchronized. Value Description 0 Disabled – All reception is dropped. 1 Wake on address match, if enabled. Bits 4:2 – MODE[2:0] Operating Mode These bits must be written to 0x04 to select the I2C Client serial communication interface of the SERCOM. These bits are not synchronized. Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not enable-protected. Value Description 0 The peripheral is disabled or being disabled. 1 The peripheral is enabled. Bit 0 – SWRST Software Reset Writing '0' to this bit has no effect. Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Value Description 0 There is no reset operation ongoing. 1 The reset operation is ongoing. SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 596

33.8.2 Control B

Name: CTRLB Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 ACKACT CMD[1:0] Access R/W W W Reset 0 0 0 Bit 15 14 13 12 11 10 9 8 QCEN SMEN Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 Access Reset Bit 18 – ACKACT Acknowledge Action This bit defines the Client's acknowledge behavior after an address or data byte is received from the Host. The acknowledge action is executed when a command is written to the CMD bits. If smart mode is enabled (CTRLB.SMEN=1), the acknowledge action is performed when the DATA register is read. This bit is not enable-protected. Value Description

0 Send ACK

1 Send NACK

Bits 17:16 – CMD[1:0] Command This bit field triggers the Client operation as the below. The CMD bits are strobe bits, and always read as zero. The operation is dependent on the Client interrupt flags, INTFLAG.DRDY and INTFLAG.AMATCH, in addition to STATUS.DIR. All interrupt flags (INTFLAG.DRDY, INTFLAG.AMATCH and INTFLAG.PREC) are automatically cleared when a command is given. This bit is not enable-protected. Table 33-3. Command Description CMD[1:0] DIR Action 0x0 X (No action) 0x1 X (Reserved) 0x2 Used to complete a transaction in response to a data interrupt (DRDY) 0 (Host write) Execute acknowledge action succeeded by waiting for any start (S/Sr) condition 1 (Host read) Wait for any start (S/Sr) condition SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 597

CMD[1:0] DIR Action 0x3 Used in response to an address interrupt (AMATCH) 0 (Host write) Execute acknowledge action succeeded by reception of next byte 1 (Host read) Execute acknowledge action succeeded by Client data interrupt Used in response to a data interrupt (DRDY) 0 (Host write) Execute acknowledge action succeeded by reception of next byte 1 (Host read) Execute a byte read operation followed by ACK/NACK reception Bit 9 – QCEN Quick Command Enable This bit is not write-synchronized. Value Description 0 Quick Command is disabled. 1 Quick Command is enabled. Bit 8 – SMEN Smart Mode Enable When smart mode is enabled, data is acknowledged automatically when DATA.DATA is read. This bit is not write-synchronized. Value Description 0 Smart mode is disabled. 1 Smart mode is enabled. SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 598

33.8.3 Interrupt Enable Clear

Name: INTENCLR Offset: 0x14 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 5 4 3 2 1 0 ERROR DRDY AMATCH PREC Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 – ERROR Error Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. Value Description 0 Error interrupt is disabled. 1 Error interrupt is enabled. Bit 2 – DRDY Data Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Data Ready bit, which disables the Data Ready interrupt. Value Description 0 The Data Ready interrupt is disabled. 1 The Data Ready interrupt is enabled. Bit 1 – AMATCH Address Match Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Address Match Interrupt Enable bit, which disables the Address Match interrupt. Value Description 0 The Address Match interrupt is disabled. 1 The Address Match interrupt is enabled. Bit 0 – PREC Stop Received Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Stop Received Interrupt Enable bit, which disables the Stop Received interrupt. Value Description 0 The Stop Received interrupt is disabled. 1 The Stop Received interrupt is enabled. SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 599

33.8.4 Interrupt Enable Set

Name: INTENSET Offset: 0x16 Reset: 0x00 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 5 4 3 2 1 0 ERROR DRDY AMATCH PREC Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 – ERROR Error Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. Value Description 0 Error interrupt is disabled. 1 Error interrupt is enabled. Bit 2 – DRDY Data Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Data Ready bit, which enables the Data Ready interrupt. Value Description 0 The Data Ready interrupt is disabled. 1 The Data Ready interrupt is enabled. Bit 1 – AMATCH Address Match Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Address Match Interrupt Enable bit, which enables the Address Match interrupt. Value Description 0 The Address Match interrupt is disabled. 1 The Address Match interrupt is enabled. Bit 0 – PREC Stop Received Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Stop Received Interrupt Enable bit, which enables the Stop Received interrupt. Value Description 0 The Stop Received interrupt is disabled. 1 The Stop Received interrupt is enabled. SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 600

33.8.5 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x18 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 ERROR DRDY AMATCH PREC Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 – ERROR Error This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS register. The corresponding bits in STATUS are LENERR, SEXTTOUT, LOWTOUT, COLL, and BUSERR. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 2 – DRDY Data Ready This flag is set when a I2C Client byte transmission or reception is successfully completed. The flag is cleared by hardware when either:

Writing to the DATA register.
Reading the DATA register with smart mode enabled.
Writing a valid command to the CMD register. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Data Ready interrupt flag. Bit 1 – AMATCH Address Match This flag is set when the I2C Client address match logic detects that a valid address has been received. The flag is cleared by hardware when CTRL.CMD is written. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Address Match interrupt flag. When cleared, an ACK/NACK will be sent according to CTRLB.ACKACT. Bit 0 – PREC Stop Received This flag is set when a stop condition is detected for a transaction being processed. A stop condition detected between a bus Host and another Client will not set this flag, unless the PMBus Group Command is enabled in the Control B register (CTRLB.GCMD=1). This flag is cleared by hardware after a command is issued on the next address match. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Stop Received interrupt flag. SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 601

33.8.6 Status

Name: STATUS Offset: 0x1A Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 HS SEXTTOUT Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 CLKHOLD LOWTOUT SR DIR RXNACK COLL BUSERR Access R R/W R R R R/W R/W Reset 0 0 0 0 0 0 0 Bit 10 – HS High-speed This bit is set if the Client detects a START followed by a Host Code transmission. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the status. However, this flag is automatically cleared when a STOP is received. Bit 9 – SEXTTOUT Client SCL Low Extend Time-Out This bit is set if a Client SCL low extend time-out occurs. This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD) or when INTFLAG.AMATCH is cleared. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the status. Value Description 0 No SCL low extend time-out has occurred. 1 SCL low extend time-out has occurred. Bit 7 – CLKHOLD Clock Hold The Client Clock Hold bit (STATUS.CLKHOLD) is set when the Client is holding the SCL line low, stretching the I2C clock. Software should consider this bit a read-only status flag that is set when INTFLAG.DRDY or INTFLAG.AMATCH is set. This bit is automatically cleared when the corresponding interrupt is also cleared. Bit 6 – LOWTOUT SCL Low Time-out This bit is set if an SCL low time-out occurs. This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD) or when INTFLAG.AMATCH is cleared. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the status. Value Description 0 No SCL low time-out has occurred. 1 SCL low time-out has occurred. Bit 4 – SR Repeated Start When INTFLAG.AMATCH is raised due to an address match, SR indicates a repeated start or start condition. This flag is only valid while the INTFLAG.AMATCH flag is one. Value Description

0 Start condition on last address match

1 Repeated start condition on last address match

Bit 3 – DIR Read / Write Direction The Read/Write Direction (STATUS.DIR) bit stores the direction of the last address packet received from a Host. Value Description 0 Host write operation is in progress. 1 Host read operation is in progress. Bit 2 – RXNACK Received Not Acknowledge This bit indicates whether the last data packet sent was acknowledged or not. Value Description 0 Host responded with ACK. 1 Host responded with NACK. Bit 1 – COLL Transmit Collision If set, the I2C Client was not able to transmit a high data or NACK bit, the I2C Client will immediately release the SDA and SCL lines and wait for the next packet addressed to it. This flag is intended for the SMBus address resolution protocol (ARP). A detected collision in non-ARP situations indicates that there has been a protocol violation, and should be treated as a bus error. Note that this status will not trigger any interrupt, and should be checked by software to verify that the data were sent correctly. This bit is cleared automatically if responding to an address match with an ACK or a NACK (writing 0x3 to CTRLB.CMD), or INTFLAG.AMATCH is cleared. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the status. Value Description 0 No collision detected on last data byte sent. 1 Collision detected on last data byte sent. Bit 0 – BUSERR Bus Error The Bus Error bit (STATUS.BUSERR) indicates that an illegal bus condition has occurred on the bus, regardless of bus ownership. An illegal bus condition is detected if a protocol violating start, repeated start or stop is detected on the I2C bus lines. A start condition directly followed by a stop condition is one example of a protocol violation. If a time-out occurs during a frame, this is also considered a protocol violation, and will set STATUS.BUSERR. This bit is cleared automatically if responding to an address match with an ACK or a NACK (writing 0x3 to CTRLB.CMD) or INTFLAG.AMATCH is cleared. Writing a '1' to this bit will clear the status. Writing a '0' to this bit has no effect. Value Description 0 No bus error detected. 1 Bus error detected. SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 603

33.8.7 Synchronization Busy

Name: SYNCBUSY Offset: 0x1C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ENABLE SWRST Access R R Reset 0 0 Bit 1 – ENABLE SERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNCBUSY.ENABLE bit will be set until synchronization is complete. Writes to any register (except for CTRLA.SWRST) while enable synchronization is on-going will be discarded and an APB error will be generated. Value Description 0 Enable synchronization is not busy. 1 Enable synchronization is busy. Bit 0 – SWRST Software Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will be set until synchronization is complete. Writes to any register while synchronization is on-going will be discarded and an APB error will be generated. Value Description 0 SWRST synchronization is not busy. 1 SWRST synchronization is busy. SAM L22 Family SERCOM I2C – SERCOM Inter-Integrated Circ... © 2021 Microchip Technology Inc. and its subsidiaries Complete Datasheet DS60001465B-page 604

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Product Information

SAM-L22 specifications and overview.

Summary

32-bit ARM Cortex-M0+ Ultra-Low-Power MCU family with Peripheral Touch Controller (PTC), Segment LCD Controller, Advanced Analog, USB and AES Rev A - 08/2015

Description

32-bit ARM Cortex-M0+ Ultra-Low-Power MCU family with Peripheral Touch Controller (PTC), Segment LCD Controller, Advanced Analog, USB and AES Rev A - 08/2015

Source title SAM-L22 Datasheet(PDF) - Microchip Technology

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