Microcontroller

SAM-D21

Microchip Technology

Low-Power, 32-bit Cortex-M0+ MCU with Advanced Analog and PWM 2021

Manufacturer: Microchip Technology

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Technical content

Features

Processor – Arm Cortex -M0+ CPU running at up to 48 MHz
Single-cycle hardware multiplier
Micro Trace Buffer (MTB)
Memories – 4/2/1/0.5 KB Read-While-Write (RWWEE) Flash section (not available on 256 KB devices) – 256/128/64/32/16 KB in-system self-programmable Flash – 32/16/8/4 KB SRAM Memory
System – Power-on Reset (POR) and Brown-out Detection (BOD) – Internal and external clock options with 48 MHz Digital Frequency-Locked Loop (DFLL48M) and 48 MHz to

96 MHz Fractional Digital Phase-Locked Loop (FDPLL96M)

– External Interrupt Controller (EIC) – 16 external interrupts – One Non-maskable Interrupt (NMI) – Two-pin Serial Wire Debug (SWD) programming, test and debugging interface

Low Power – Idle and Standby Sleep modes – SleepWalking peripherals
Peripherals – 12-channel Direct Memory Access Controller (DMAC) – 12-channel Event System – Up to five 16-bit Timer/Counters (TC), configurable as either:
One 16-bit TC with two compare/capture channels
One 8-bit TC with two compare/capture channels
One 32-bit TC with two compare/capture channels, by using two TCs – Up to four 24-bit Timer/Counters for Control (TCC), with extended functions:
Up to four compare channels with optional complementary output
Generation of synchronized pulse width modulation (PWM) pattern across port pins
Deterministic fault protection, fast decay and configurable dead-time between complementary output
Dithering that increase resolution with up to 5 bit and reduce quantization error – PWM Channels using TC and TCC peripherals:
Up to eight PWM channels on each 24-bit TCC
Up to two PWM channels on each 16-bit TCC
Up to two PWM channels on each 16-bit TC – 32-bit Real Time Counter (RTC) with clock/calendar function – Watchdog Timer (WDT) – CRC-32 generator © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 1

– One full-speed (12 Mbps) Universal Serial Bus (USB) 2.0 interface

Embedded host and device function
Eight endpoints – Up to six Serial Communication Interfaces (SERCOM), each configurable to operate as either:
USART with full-duplex and single-wire half-duplex configuration
I 2C up to 3.4 MHz
SPI
LIN client – One two-channel Inter-IC Sound (I 2S) interface – One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to 20 channels
Differential and single-ended input
1/2x to 16x programmable gain stage
Automatic offset and gain error compensation
Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution – 10-bit, 350 ksps Digital-to-Analog Converter (DAC) – Up to four Analog Comparators (AC) with Window Compare function – Peripheral Touch Controller (PTC)
Up to 256-Channel capacitive touch and proximity sensing
I/O – Up to 52 programmable I/O pins
Qualification – SAM D21 AEC-Q100 Grade 1 (-40°C to 125°C) – SAM DA1 AEC-Q100 Grade 2 (-40C to 105C)
Drop-in compatible with SAM D20
Packages – 64-pin TQFP, QFN, UFBGA – 48-pin TQFP, QFN – 45-pin WLCSP – 35-pin WLCSP – 32-pin TQFP, QFN
Operating Voltage – SAM D21: 1.62V – 3.63V – SAM DA1: 2.7V - 3.63V SAM D21/DA1 Family © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 2

Description The SAM D21/DA1 is a series of low-power microcontrollers using the 32-bit ARM® Cortex®-M0+ processor, and ranging from 32-pins to 64-pins with up to 256 KB Flash and 32 KB of SRAM. The SAM D21/DA1 operates at a maximum frequency of 48 MHz and reach 2.46 CoreMark/MHz. They are designed for simple and intuitive migration with identical peripheral modules, hex compatible code, identical linear address map, and pin compatible migration paths between all devices in the product series. All devices include intelligent and flexible peripherals, Event System for inter-peripheral signaling, and support for capacitive touch button, slider, and wheel user interfaces. The SAM D21/DA1 provides the following features: In-system programmable Flash, 12-channel Direct Memory Access Controller (DMAC), 12-channel Event System, programmable Interrupt Controller, up to 52 programmable I/O pins, 32-bit Real-Time Clock and Calendar (RTC), up to five 16-bit Timer/Counters (TC) and up to four 24-bit Timer/Counters for Control (TCC), where each TC can be configured to perform frequency and waveform generation, accurate program execution timing or input capture with time and frequency measurement of digital signals. The TCs can operate in 8- or 16-bit mode, selected TCs can be cascaded to form a 32-bit TC, and three timer/counters have extended functions optimized for motor, lighting, and other control applications. The series provide one full-speed USB 2.0 embedded host and device interface; up to six Serial Communication Modules (SERCOM) that each can be configured to act as an USART, UART, SPI, I2C up to 3.4MHz, SMBus, PMBus, and LIN client; two-channel I2S interface; up to twenty-channel 350 ksps 12-bit ADC with programmable gain and optional oversampling and decimation supporting up to 16-bit resolution, one 10-bit 350 ksps DAC, up to four analog comparators with Window mode, Peripheral Touch Controller (PTG) supporting up to 256 buttons, sliders, wheels, and proximity sensing; programmable Watchdog Timer (WDT), brown-out detector and power-on Reset and two-pin Serial Wire Debug (SWD) program and debug interface. All devices have accurate and low-power external and internal oscillators. All oscillators can be used as a source for the system clock. Different clock domains can be independently configured to run at different frequencies, enabling power saving by running each peripheral at its optimal clock frequency, and thus maintaining a high CPU frequency while reducing power consumption. The SAM D21/DA1 have two software-selectable sleep modes, Idle and Stand-by. In Idle mode, the CPU is stopped while all other functions can be kept running. In Stand-by mode, all clocks and functions are stopped, expect those selected to continue running. The device supports SleepWalking. This feature allows the peripheral to wake up from sleep based on predefined conditions, and thus allows the CPU to wake up only when needed, e.g., when a threshold is crossed or a result is ready. The Event System supports synchronous and asynchronous events, allowing peripherals to receive, react to and send events even in Stand-by mode. The Flash program memory can be reprogrammed in-system through the SWD interface. The same interface can be used for non-intrusive on-chip debug of application code. A boot loader running in the device can use any communication interface to download and upgrade the application program in the Flash memory. The SAM D21/DA1 microcontrollers are supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits. SAM D21/DA1 Family

Description

Configuration Summary Table 2-1. SAM D21 E/G/J and SAM D21 EL/GL Product Family Features Device Program Memory (KB) Data Memory (KB) Pins Packages Oscillators Peripherals Analog Internal External USB SERCOM TC-Waveform /PWM Output/Capture Input Channels per TCx Instance TCC Waveform /PWM Output Channels per TCCx Instance I2S DMA Channels RTC WDT Event System (Channels) External Interrupt Lines I/O Pins ADC Channels Analog Comparator DAC PTC (Mutual/Self-capacitance Channels)" ATSAMD21E15A 32 4 TQFP, QFN OSC32K, OSCULP32K, OSC8M, DFLL48M, FDPLL96M XOSC32K, XOSC, Y 3-2 8/4/2 Y 12 Y Y 12 16 26 10 Y ATSAMD21E16A 64 8 ATSAMD21E17A 128 16 ATSAMD21E18A 256 32 ATSAMD21E15B 32 4 ATSAMD21E16B 64 8 ATSAMD21E15C 32 4

35 WLCSP

OSC32K, OSCULP32K, OSC8M, DFLL48M, FDPLL96M 3 12 Y ATSAMD21G15A 32 4 TQFP, QFN 6 8/4/2 38 14 120/10 ATSAMD21G16A 64 8 ATSAMD21G17A (1) 128 16 ATSAMD21G18A ( 1) 256 32 ATSAMD21G15B 32 4 ATSAMD21G16B 64 8 ATSAMD21J15A 32 4 TQFP, QFN OSC32K, OSCULP32K, OSC8M, DFLL48M, FDPLL96M 5-2

12 Y Y 12 16

ATSAMD21J15B 32 4 TQFP, QFN, UFBGAATSAMD21J16B 64 8 ATSAMD21E15L 32 4 32 TQFP, QFN XOSC N 4 3-2 6/4/2 N 26 14

4 NATSAMD21E16L 64 8 32

ATSAMD21G16L 64 8 48 QFN 6 5-2 8/4/2 38 18 ATSAMD21E17D 128 16 TQFP, QFN WLCSP OSC32K, OSCULP32K, OSC8M, DFLL48M, XOSC32K, XOSC Y 4 3-2 4 6/4/2/6 Y 26 10 2 30/6 ATSAMD21G17D 128 16

48 QFN,

OSC32K, OSCULP32K, OSC8M, DFLL48M, FDPLL96M XOSC32K, XOSC, Y 6 3-2 4 8/4/2/8 Y 12 Y Y 12 16 38 14 2 Y 120/10 SAM D21/DA1 Family Configuration Summary © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 14

Program Memory (KB) Data Memory (KB) Pins Packages Oscillators Peripherals Analog Internal External USB SERCOM TC-Waveform /PWM Output/Capture Input Channels per TCx Instance TCC Waveform /PWM Output Channels per TCCx Instance I2S DMA Channels RTC WDT Event System (Channels) External Interrupt Lines I/O Pins ADC Channels Analog Comparator DAC PTC (Mutual/Self-capacitance Channels)" ATSAMD21J17D 128 16 QFN, TQFP UFBGA OSC32K, OSCULP32K, OSC8M, DFLL48M, FDPLL96M XOSC32K, XOSC, Y 6 5-2 4 8/4/2/8 Y 12 Y Y 12 16 52 20 2 Y 256/16 ATSAMD21E17L 128 16

32 QFN,

OSC32K, OSCULP32K, OSC8M, DFLL48M, FDPLL96M XOSC N 4 3-2 4 6/4/2/6 N 12 Y Y 12 16 26 14 4 Y N ATSAMD21G17L 128 16

48 QFN

OSC32K, OSCULP32K, OSC8M, DFLL48M, FDPLL96M XOSC N 6 5-2 4 8/4/2/8 N 12 Y Y 12 16 38 18 4 Y N Note: 1. This part number is also available in a 45-Ball WLCSP package with a total of five TC instances and 15 ADC Channels. Table 2-2. SAM DA1 E/G/J Product Family Features Device Program Memory (KB) Data Memory (KB) Pins Packages Internal External USB SERCOM TC-Waveform/PWM Output/Capture Input Channels per TCx Instance TCC Waveform/PWM Output Channels per TCCx Instance I2S DMA Channels RTC WDT Event System (Channels) External Interrupt Lines I/O Pins ADC Channels Analog Comparator DAC PTC (Mutual/Self- capacitance Channels) ATSAMDA1E14B 16 TQFP, QFN OSC32K, OSCULP32K, OSC8M, DFLL48M, FDPLL96M XOSC32K, XOSC 1 3-2 6/4/2 1 12 Y Y 12 16 26 10 2 1 60/6ATSAMDA1E15B 32 ATSAMDA1E16B 64 8 ATSAMDA1G14B 16 6 8/4/2 38 14 120/10ATSAMDA1G15B 32 ATSAMDA1G16B 64 8 ATSAMDA1J14B 16

64 TQFP 5-2 52 20 256/16ATSAMDA1J15B 32

SAM D21 Ordering Information(1) ATSAMD 21 E 15 A - M U T Product Family SAMD = General Purpose Microcontroller 21 = Cortex M0 + CPU, Basic Feature Set E = 32 Pins (35 Pins for WLCSP) G = 48 Pins (45 Pins for WLCSP) J = 64 Pins No character = Tray (Default) T = Tape and Reel U = -40 - 85°C Matte Sn Plating N = -40 - 105°C Matte Sn Plating F = -40 - 125°C Matte Sn Plating Z = -40 - 125°C Matte Sn Plating (AEC-Q100 Qualified) A = TQFP(4) M = QFN(4) U = WLCSP (2,3) C = UFBGA + DMA + USB Product Series Flash Memory Density Device Variant A = Default Variant B = Added RWWEE support for 32 KB and 64 KB memory options C = Silicon revision F for WLCSP45 package option L = Pinout optimized for Analog and PWM D = Silicon Revision G with RWWEE Support in 128KB memory options Pin Count Package Carrier Package Grade 18 = 256 KB 17 = 128 KB 16 = 64 KB 15 = 32 KB Package Type Notes: 1. Not all combinations are valid. The available ordering numbers are listed in the Configuration Summary. 2. WLCSP package is available in -40C to 85C operating temperature range. 3. WLCSP parts are programmed with a specific SPI/I 2C bootloader. Refer to "Application Note AT09002" for additional information. Contact Microchip sales office for additional information on availability. 4. The AEC-Q100 grade 1 qualified version is only offered in the TQFP and QFN packages. The QFN will have wettable flanks, and both packages will be assembled with gold bond wires. SAM D21/DA1 Family © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 16

3.1 SAM DA1 Ordering Information

Figure 3-1. SAM DA1 Ordering Information SAM D A1 E 14 A - A B T Product Family SAM D = Baseline Cortex-M0+ MCU A1 = Automotive basic feature set + DMA, E = 32 Pins G = 48 Pins J = 64 Pins T = Tape and Reel B = -40OC - 105OC Matte Sn Plating (only DA1) A = TQFP M = QFN Wettable Flanks Adv Timers, USB, I2S, PTC Product Series Flash Memory Density Device Variant A = Silicon revision E (Initial revision) B = Silicon revision F Pin Count Package Carrier Package Grade 16 = 64KB 15 = 32KB 14 = 16KB Package Type Note: 1. Not all combinations are valid. The available ordering numbers are listed in the Configuration Summary. SAM D21/DA1 Family © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 17

Block Diagram 6 x SERCOM 8 x Timer Counter REAL TIME COUNTER AHB-APB BRIDGE C M MHIGH-SPEED BUS MATRIX PORT PORT WATCHDOG TIMER SERIAL WIRESWDIO S CORTEX-M0+ PROCESSOR Fmax 48 MHz SWCLK DEVICE SERVICE UNIT AHB-APB BRIDGE A 20-CHANNEL 12-bit ADC 350KSPS AIN[19..0] VREFA AIN[3..0] S SRAM CONTROLLER 32/16/8/4KB RAM M RESET CONTROLLER SLEEP CONTROLLER CLOCK CONTROLLER POWER MANAGER RESET 5 x TIMER / COUNTER EVENT SYSTEM S 6 x SERCOM Up to 4 ANALOG COMPARATORS SYSTEM CONTROLLER XOUT XIN XOUT32 XIN32 OSCULP32K OSC32K OSC8M DFLL48M BOD33 XOSC32K XOSC VREF X[15..0] Y[15..0] PERIPHERAL TOUCH CONTROLLER PERIPHERAL ACCESS CONTROLLER AHB-APB BRIDGE B VREFA VOUT 10-bit DAC EXTERNAL INTERRUPT CONTROLLER PERIPHERAL ACCESS CONTROLLER PERIPHERAL ACCESS CONTROLLER EXTINT[15..0] NMI GCLK_IO[7..0] S PAD0 WO1 PAD1 PAD2 PAD3 WO0 VREFB 256/128/64/32KB NVM NVM CONTROLLER Cache S DMA USB FS DEVICE MINI-HOST DP DM 4x TIMER / COUNTER FOR CONTROL WOn IOBUS FDPLL96M DMA DMA DMA DMA DMA MCK[1..0] SCK[1..0]INTER-IC SOUND CONTROLLER SD[1..0] FS[1..0] DMA MICRO TRACE BUFFER SOF 1KHZ WO0 WO1 (2) GENERIC CLOCK CONTROLLER CMP[1..0] 1. Some products have different number of SERCOM instances, Timer/Counter instances, PTC signals and ADC signals. Refer to the Configuration Summary for details. 2. The TCC instances have different configurations, including the number of Waveform Output (WO) lines. Refer to the TCC Configuration for details. Related Links 2. Configuration Summary

7.2.5 TCC Configurations

Pinout

5.1 SAM D21J and SAM DA1J

5.1.1 QFN64 / TQFP64

5.1.2 UFBGA64

5.2 SAM D21GxxA/B/D and SAM DA1GxxA/B

5.2.1 QFN48 / TQFP48

5.3 SAM D21GxxA

5.3.1 WLCSP45

5.4 SAM D21GxxL

5.4.1 QFN48

5.5 SAM D21ExxA/B/D and SAM DA1ExxA/B

5.5.1 QFN32 / TQFP32

5.6 SAM D21ExxB/C/D

5.6.1 WLCSP35

5.7 SAM D21ExxL

5.7.1 QFN32 / TQFP32

25 RESET

Signal Descriptions List The following table gives details on signal names classified by peripheral. Signal Name Function Type Active Level Analog Comparators - AC AIN[3:0] AC Analog Inputs Analog CMP[:0] AC Comparator Outputs Digital Analog Digital Converter - ADC AIN[19:0] ADC Analog Inputs Analog VREFA ADC Voltage External Reference A Analog VREFB ADC Voltage External Reference B Analog Digital Analog Converter - DAC VOUT DAC Voltage output Analog VREFA DAC Voltage External Reference Analog External Interrupt Controller EXTINT[15:0] External Interrupts Input NMI External Non-Maskable Interrupt Input Generic Clock Generator - GCLK GCLK_IO[7:0] Generic Clock (source clock or generic clock generator output) I/O Inter-IC Sound Controller - I2S MCK[1:0] Host Clock I/O SCK[1:0] Serial Clock I/O FS[1:0] I2S Word Select or TDM Frame Sync I/O SD[1:0] Serial Data Input or Output I/O Power Manager - PM RESET Reset Input Low Serial Communication Interface - SERCOMx PAD[3:0] SERCOM I/O Pads I/O System Control - SYSCTRL XIN Crystal Input Analog/ Digital XIN32 32kHz Crystal Input Analog/ Digital XOUT Crystal Output Analog XOUT32 32kHz Crystal Output Analog Timer Counter - TCx WO[1:0] Waveform/PWM Outputs/ Capture Inputs Output Timer Counter - TCCx WO[7:0] Waveform/PWM Outputs Output SAM D21/DA1 Family Signal Descriptions List © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 27

Signal Name Function Type Active Level Peripheral Touch Controller - PTC X[15:0] PTC Input Analog Y[15:0] PTC Input Analog General Purpose I/O - PORT PA25 - PA00 Parallel I/O Controller I/O Port A I/O PA28 - PA27 Parallel I/O Controller I/O Port A I/O PA31 - PA30 Parallel I/O Controller I/O Port A I/O PB17 - PB00 Parallel I/O Controller I/O Port B I/O PB23 - PB22 Parallel I/O Controller I/O Port B I/O PB31 - PB30 Parallel I/O Controller I/O Port B I/O Universal Serial Bus - USB DP DP for USB I/O DM DM for USB I/O SOF 1kHz USB Start of Frame I/O SAM D21/DA1 Family Signal Descriptions List © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 28

I/O Multiplexing and Considerations

7.1 Multiplexed Signals

Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one. The selection of peripheral function A to H is done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT. This table describes the peripheral signals multiplexed to the PORT I/O pins. Table 7-1. PORT Function Multiplexing for SAM D21 A/B/C/D Variant Devices and SAM DA1 A/B Variant Devices Pin(1) I/O Pin Supply A B(2)(3) C D E F G H SAMD2xE SAMD2xG SAMD2xJ EIC REF ADC AC PTC DAC SERCOM(2)(3) SERCOM-ALT TC(4) /TCC TCC COM AC/ GCLK 1 1 1 PA00 VDDANA EXTINT[0] SERCOM1/ PAD[0] TCC2/WO[0] 2 2 2 PA01 VDDANA EXTINT[1] SERCOM1/ PAD[1] TCC2/WO[1] 3 3 3 PA02 VDDANA EXTINT[2] AIN[0] Y[0] VOUT TCC3/ WO[0] 4 4 4 PA03 VDDANA EXTINT[3] ADC/VREFA DAC/VREFA AIN[1] Y[1] TCC3/ WO[1]

5 PB04 VDDANA EXTINT[4] AIN[12] Y[10]

6 PB05 VDDANA EXTINT[5] AIN[13] Y[11]

9 PB06 VDDANA EXTINT[6] AIN[14] Y[12]

10 PB07 VDDANA EXTINT[7] AIN[15] Y[13]

7 11 PB08 VDDANA EXTINT[8] AIN[2] Y[14] SERCOM4/ PAD[0] TC4/WO[0] TCC3/ WO[6] 8 12 PB09 VDDANA EXTINT[9] AIN[3] Y[15] SERCOM4/ PAD[1] TC4/WO[1] TCC3/ WO[7] 5 9 13 PA04 VDDANA EXTINT[4] ADC/VREFB AIN[4] AIN[0] Y[2] SERCOM0/ PAD[0] TCC0/WO[0] TCC3/ WO[2] 6 10 14 PA05 VDDANA EXTINT[5] AIN[5] AIN[1] Y[3] SERCOM0/ PAD[1] TCC0/WO[1] TCC3/ WO[3] 7 11 15 PA06 VDDANA EXTINT[6] AIN[6] AIN[2] Y[4] SERCOM0/ PAD[2] TCC1/WO[0] TCC3/ WO[4] 8 12 16 PA07 VDDANA EXTINT[7] AIN[7] AIN[3] Y[5] SERCOM0/ PAD[3] TCC1/WO[1] TCC3/ WO[5] I2S/SD[0] 11 13 17 PA08 VDDIO NMI AIN[16] X[0] SERCOM0/ PAD[0] SERCOM2/ PAD[0] TCC0/WO[0] TCC1/ WO[2] I2S/SD[1] 12 14 18 PA09 VDDIO EXTINT[9] AIN[17] X[1] SERCOM0/ PAD[1] SERCOM2/ PAD[1] TCC0/WO[1] TCC1/ WO[3] I2S/ MCK[0] 13 15 19 PA10 VDDIO EXTINT[10] AIN[18] X[2] SERCOM0/ PAD[2] SERCOM2/ PAD[2] TCC1/WO[0] TCC0/ WO[2] I2S/ SCK[0] GCLK_IO[4] 14 16 20 PA11 VDDIO EXTINT[11] AIN[19] X[3] SERCOM0/ PAD[3] SERCOM2/ PAD[3] TCC1/WO[1] TCC0/ WO[3] I2S/FS[0] GCLK_IO[5] 19 23 PB10 VDDIO EXTINT[10] SERCOM4/ PAD[2] TC5/WO[0] TCC0/ WO[4] I2S/ MCK[1] GCLK_IO[4] 20 24 PB11 VDDIO EXTINT[11] SERCOM4/ PAD[3] TC5/WO[1] TCC0/ WO[5] I2S/ SCK[1] GCLK_IO[5]

25 PB12 VDDIO EXTINT[12] X[12] SERCOM4/

PAD[0] TC4/WO[0] TCC0/ WO[6] I2S/FS[1] GCLK_IO[6]

26 PB13 VDDIO EXTINT[13] X[13] SERCOM4/

PAD[1] TC4/WO[1] TCC0/ WO[7] GCLK_IO[7]

27 PB14 VDDIO EXTINT[14] X[14] SERCOM4/

Pin(1) I/O Pin Supply A B(2)(3) C D E F G H SAMD2xE SAMD2xG SAMD2xJ EIC REF ADC AC PTC DAC SERCOM(2)(3) SERCOM-ALT TC(4) /TCC TCC COM AC/ GCLK

28 PB15 VDDIO EXTINT[15] X[15] SERCOM4/

PAD[3] TC5/WO[1] GCLK_IO[1] 21 29 PA12 VDDIO EXTINT[12] SERCOM2/ PAD[0] SERCOM4/ PAD[0] TCC2/WO[0] TCC0/ WO[6] AC/CMP[0] 22 30 PA13 VDDIO EXTINT[13] SERCOM2/ PAD[1] SERCOM4/ PAD[1] TCC2/WO[1] TCC0/ WO[7] AC/CMP[1] 15 23 31 PA14 VDDIO EXTINT[14] SERCOM2/ PAD[2] SERCOM4/ PAD[2] TC3/WO[0] TCC0/ WO[4] GCLK_IO[0] 16 24 32 PA15 VDDIO EXTINT[15] SERCOM2/ PAD[3] SERCOM4/ PAD[3] TC3/WO[1] TCC0/ WO[5] GCLK_IO[1] 17 25 35 PA16 VDDIO EXTINT[0] X[4] SERCOM1/ PAD[0] SERCOM3/ PAD[0] TCC2/WO[0] TCC0/WO[6] GCLK_IO[2] 18 26 36 PA17 VDDIO EXTINT[1] X[5] SERCOM1/ PAD[1] SERCOM3/ PAD[1] TCC2/WO[1] TCC0/WO[7] GCLK_IO[3] 19 27 37 PA18 VDDIO EXTINT[2] X[6] SERCOM1/ PAD[2] SERCOM3/ PAD[2] TC3/WO[0] TCC0/ WO[2] AC/CMP[0] 20 28 38 PA19 VDDIO EXTINT[3] X[7] SERCOM1/ PAD[3] SERCOM3/ PAD[3] TC3/WO[1] TCC0/ WO[3] I2S/SD[0] AC/CMP[1]

39 PB16 VDDIO EXTINT[0] SERCOM5/

PAD[0] TC6/WO[0] TCC0/ WO[4] I2S/SD[1] GCLK_IO[2]

40 PB17 VDDIO EXTINT[1] SERCOM5/

PAD[1] TC6/WO[1] TCC0/ WO[5] I2S/ MCK[0] GCLK_IO[3] 29 41 PA20 VDDIO EXTINT[4] X[8] SERCOM5/ PAD[2] SERCOM3/ PAD[2] TC7/WO[0] TCC0/ WO[6] I2S/ SCK[0] GCLK_IO[4] 30 42 PA21 VDDIO EXTINT[5] X[9] SERCOM5/ PAD[3] SERCOM3/ PAD[3] TC7/WO[1] TCC0/ WO[7] I2S/FS[0] GCLK_IO[5] 21 31 43 PA22 VDDIO EXTINT[6] X[10] SERCOM3/ PAD[0] SERCOM5/ PAD[0] TC4/WO[0] TCC0/ WO[4] GCLK_IO[6] 22 32 44 PA23 VDDIO EXTINT[7] X[11] SERCOM3/ PAD[1] SERCOM5/ PAD[1] TC4/WO[1] TCC0/ WO[5] USB/SOF 1kHz GCLK_IO[7] 23 33 45 PA24(6) VDDIO EXTINT[12] SERCOM3/ PAD[2] SERCOM5/ PAD[2] TC5/WO[0] TCC1/ WO[2] USB/DM 24 34 46 PA25(6) VDDIO EXTINT[13] SERCOM3/ PAD[3] SERCOM5/ PAD[3] TC5/WO[1] TCC1/ WO[3] USB/DP 37 49 PB22 VDDIO EXTINT[6] SERCOM5/ PAD[2] TC7/WO[0] TCC3/ WO[0] GCLK_IO[0] 38 50 PB23 VDDIO EXTINT[7] SERCOM5/ PAD[3] TC7/WO[1] TCC3/ WO[1] GCLK_IO[1] 25 39 51 PA27 VDDIO EXTINT[15] TCC3/ WO[6] GCLK_IO[0] 27 41 53 PA28 VDDIO EXTINT[8] TCC3/ WO[7] GCLK_IO[0] 31 45 57 PA30 VDDIO EXTINT[10] SERCOM1/ PAD[2] TCC1/WO[0] TCC3/ WO[4] SWCLK GCLK_IO[0] 32 46 58 PA31 VDDIO EXTINT[11] SERCOM1/ PAD[3] TCC1/WO[1] TCC3/ WO[5] SWDIO(5)

59 PB30 VDDIO EXTINT[14] SERCOM5/

PAD[0] TCC0/WO[0] TCC1/ WO[2]

60 PB31 VDDIO EXTINT[15] SERCOM5/

PAD[1] TCC0/WO[1] TCC1/ WO[3]

61 PB00 VDDANA EXTINT[0] AIN[8] Y[6] SERCOM5/

PAD[2] TC7/WO[0]

62 PB01 VDDANA EXTINT[1] AIN[9] Y[7] SERCOM5/

PAD[3] TC7/WO[1] 47 63 PB02 VDDANA EXTINT[2] AIN[10] Y[8] SERCOM5/ PAD[0] TC6/WO[0] TCC3/ WO[2] 48 64 PB03 VDDANA EXTINT[3] AIN[11] Y[9] SERCOM5/ PAD[1] TC6/WO[1] TCC3/ WO[3] SAM D21/DA1 Family I/O Multiplexing and Considerations © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 30

Use the SAMD21J pinout muxing for WLCSP45 package. 2. All analog pin functions are on peripheral function B. Peripheral function B must be selected to disable the digital control of the pin. 4. TC6 and TC7 are not supported on the SAM D21E. Refer to 2. Configuration Summary for details. 5. This function is only activated in the presence of a debugger. 6. If the PA24 and PA25 pins are not connected, it is recommended to enable a pull-up on PA24 and PA25 through input GPIO mode. The aim is to avoid an eventually extract power consumption (<1mA) due to a not stable level on pad. The port PA24 and PA25 doesn't have Drive Strength option. 7. SERCOM4 and SERCOM5 are not supported in SAMD21ExxA, SAMD21E15(B/BU/CU/L), SAMD21E16(B/BU/CU/L) and SAMD21E17(D/DU/L). Refer to the 2. Configuration Summary for details. 8. TCC3 is only supported in SAMD21x17D. Refer to the 2. Configuration Summary for details. Table 7-2. PORT Function Multiplexing for L Variant Devices Pin I/O Pin Supply A B(1)(2) C D E F G H SAMD21ExL SAMD21GxL EIC REF ADC AC AC1 DAC SERCOM(1)(2) SERCOM-ALT(7) TC(3) /TCC TCC COM AC/ GCLK 1 1 PA02 VDDANA EXTINT[2] AIN[0] VOUT TCC3/ WO[0] 2 2 PA03 VDDANA EXTINT[3] DAC/VREFA AIN[1] TCC3/ WO[1] 3 3 PB04 VDDANA EXTINT[4] AIN[12] AIN[0] 4 4 PB05 VDDANA EXTINT[5] AIN[13] AIN[1]

7 PB08 VDDANA EXTINT[8] AIN[2] SERCOM4/

PAD[0] TC4/WO[0] TCC3/ WO[6]

8 PB09 VDDANA EXTINT[9] AIN[3] SERCOM4/

PAD[1] TC4/WO[1] TCC3/ WO[7] 5 9 PA04 VDDANA EXTINT[4] ADC/VREFB AIN[4] AIN[0] SERCOM0/ PAD[0] TCC0/WO[0] TCC3/ WO[2] 6 10 PA05 VDDANA EXTINT[5] AIN[5] AIN[1] SERCOM0/ PAD[1] TCC0/WO[1] TCC3/ WO[3] 7 11 PA06 VDDANA EXTINT[6] AIN[6] AIN[2] SERCOM0/ PAD[2] TCC1/WO[0] TCC3/ WO[4] 8 12 PA07 VDDANA EXTINT[7] AIN[7] AIN[3] SERCOM0/ PAD[3] TCC1/WO[1] TCC3/ WO[5] 11 13 PA08 VDDIO NMI AIN[16] SERCOM0/ PAD[0] SERCOM2/ PAD[0] TCC0/WO[0] TCC1/ WO[2] 12 14 PA09 VDDIO EXTINT[9] AIN[17] SERCOM0/ PAD[1] SERCOM2/ PAD[1] TCC0/WO[1] TCC1/ WO[3] 13 15 PA10 VDDIO EXTINT[10] AIN[18] SERCOM0/ PAD[2] SERCOM2/ PAD[2] TCC1/WO[0] TCC0/ WO[2] GCLK_IO[4] 14 16 PA11 VDDIO EXTINT[11] AIN[19] SERCOM0/ PAD[3] SERCOM2/ PAD[3] TCC1/WO[1] TCC0/ WO[3] GCLK_IO[5]

19 PB10 VDDIO EXTINT[10] SERCOM4/

PAD[2] TC5/WO[0] TCC0/ WO[4] GCLK_IO[4]

20 PB11 VDDIO EXTINT[11] SERCOM4/

PAD[3] TC5/WO[1] TCC0/ WO[5] GCLK_IO[5]

21 PA12 VDDIO EXTINT[12] SERCOM2/

PAD[0] SERCOM4/ PAD[0] TCC2/WO[0] TCC0/ WO[6] AC/CMP[0]

22 PA13 VDDIO EXTINT[13] SERCOM2/

PAD[1] SERCOM4/ PAD[1] TCC2/WO[1] TCC0/ WO[7] AC/CMP[1] 15 23 PA14 VDDIO EXTINT[14] SERCOM2/ PAD[2] SERCOM4/ PAD[2] TC3/WO[0] TCC0/ WO[4] GCLK_IO[0] 16 24 PA15 VDDIO EXTINT[15] SERCOM2/ PAD[3] SERCOM4/ PAD[3] TC3/WO[1] TCC0/ WO[5] GCLK_IO[1] 17 25 PA16 VDDIO EXTINT[0] SERCOM1/ PAD[0] SERCOM3/ PAD[0] TCC2/WO[0] TCC0/WO[6] GCLK_IO[2] 18 26 PA17 VDDIO EXTINT[1] SERCOM1/ PAD[1] SERCOM3/ PAD[1] TCC2/WO[1] TCC0/WO[7] GCLK_IO[3] SAM D21/DA1 Family I/O Multiplexing and Considerations © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 31

Pin I/O Pin Supply A B(1)(2) C D E F G H SAMD21ExL SAMD21GxL EIC REF ADC AC AC1 DAC SERCOM(1)(2) SERCOM-ALT(7) TC(3) /TCC TCC COM AC/ GCLK 19 27 PA18 VDDIO EXTINT[2] SERCOM1/ PAD[2] SERCOM3/ PAD[2] TC3/WO[0] TCC0/ WO[2] AC/CMP[0] 20 28 PA19 VDDIO EXTINT[3] SERCOM1/ PAD[3] SERCOM3/ PAD[3] TC3/WO[1] TCC0/ WO[3] AC/CMP[1]

29 PA20 VDDIO EXTINT[4] SERCOM5/

PAD[2] SERCOM3/ PAD[2] TC7/WO[0] TCC0/ WO[6] GCLK_IO[4]

30 PA21 VDDIO EXTINT[5] SERCOM5/

PAD[3] SERCOM3/ PAD[3] TC7/WO[1] TCC0/ WO[7] GCLK_IO[5] 21 31 PA22 VDDIO EXTINT[6] SERCOM3/ PAD[0] SERCOM5/ PAD[0] TC4/WO[0] TCC0/ WO[4] GCLK_IO[6] 22 32 PA23 VDDIO EXTINT[7] SERCOM3/ PAD[1] SERCOM5/ PAD[1] TC4/WO[1] TCC0/ WO[5] GCLK_IO[7] 23 33 PA24(5) VDDIO EXTINT[12] SERCOM3/ PAD[2] SERCOM5/ PAD[2] TC5/WO[0] TCC1/ WO[2] AC1/CMP[0] 24 34 PA25(5) VDDIO EXTINT[13] SERCOM3/ PAD[3] SERCOM5/ PAD[3] TC5/WO[1] TCC1/ WO[3] AC1/CMP[1]

37 PA27 VDDIO EXTINT[15] TCC3/

WO[6] GCLK_IO[0]

39 PA28 VDDIO EXTINT[8] TCC3/

WO[7] GCLK_IO[0] 29 43 PA30 VDDIO EXTINT[10] SERCOM1/ PAD[2] TCC1/WO[0] TCC3/ WO[4] SWCLK GCLK_IO[0] 30 44 PA31 VDDIO EXTINT[11] SERCOM1/ PAD[3] TCC1/WO[1] TCC3/ WO[5] SWDIO(5)

45 PB00 AIN[8]

46 PB01 AIN[9]

31 47 PB02 VDDANA EXTINT[2] AIN[10] AIN[2] SERCOM5/ PAD[0] TC6/WO0 TCC3/ WO[2] 32 48 PB03 VDDANA EXTINT[3] AIN[11] AIN[3] SERCOM5/ PAD[1] TC6/WO1 TCC3/ WO[3] 1. All analog pin functions are on peripheral function B. Peripheral function B must be selected to disable the digital control of the pin. 2. Only some pins can be used in SERCOM I 2C mode. 3. TC6 and TC7 are not supported on the SAM D21ExL and SAM D21GxL devices. Refer to 2. Configuration Summary for details. 4. This function is only activated in the presence of a debugger. 5. If the PA24 and PA25 pins are not connected, it is recommended to enable a pull-up on PA24 and PA25 through input GPIO mode. The aim is to avoid an eventually extract power consumption (<1mA) due to a not stable level on pad. The port PA24 and PA25 doesn't have Drive Strength option. 6. TC6 is only available on the SAM D21GxL and not the SAM D21ExL. 7. SERCOM4 and SERCOM5 are not supported on the SAM D21E devices. Refer to 2. Configuration Summary for details. 8. TCC3 is only supported in SAMD21x17L devices. Refer to the 2. Configuration Summary for details. Related Links 37. Electrical Characteristics at 85℃

7.2 Other Functions

7.2.1 Oscillator Pinout

The oscillators are not mapped to the normal port functions and their multiplexing are controlled by registers in the System Controller (SYSCTRL). SAM D21/DA1 Family I/O Multiplexing and Considerations © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 32

Table 7-3. Oscillator Pinout Oscillator Supply Signal I/O Pin XOSC VDDIO XIN PA14 XOUT PA15 XOSC32K VDDANA XIN32 PA00 XOUT32 PA01

7.2.2 Serial Wire Debug Interface Pinout

Only the SWCLK pin is mapped to the normal port functions. A debugger cold-plugging or hot-plugging detection will automatically switch the SWDIO port to the SWDIO function. Table 7-4. Serial Wire Debug Interface Pinout Signal Supply I/O Pin SWCLK VDDIO PA30 SWDIO VDDIO PA31

7.2.3 SERCOM I2C Pins

Table 7-5. SERCOM Pins Supporting I2C Device Pins Supporting I2C mode 32 pins PA08, PA09, PA16, PA17, PA22, PA23 48 pins PA08, PA09, PA12, PA13, PA16, PA17, PA22, PA23 64 pins PA08, PA09, PA12, PA13, PA16, PA17, PA22, PA23, PB12, PB13, PB16, PB17, PB30, PB31

7.2.4 GPIO Clusters

Table 7-6. GPIO Clusters PACKAGE CLUSTER GPIO SUPPLIES PINS CONNECTED TO THE CLUSTER 64pins 1 PB31 PB30 PA31 PA30 VDDIN pin56/GND pin54

2 PA28 PA27 PB23 PB22 VDDIN pin56/GND pin54 and VDDIO

3 PA25 PA24 PA23 PA22 PA21 PA20 PB17 PB16 PA19 PA18 PA17 PA16 VDDIO pin 48/GND pin47 and VDDIO

4 PA15 PA14 PA13 PA12 PB15 PB14 PB13 PB12 PB11 PB10 VDDIO pin 34/GND pin33 and VDDIO

5 PA11 PA10 PA09 PA08 VDDIO pin21/GND pin22

6 PA07 PA06 PA05 PA04 PB09 PB08 PB07 PB06 VDDANA pin 8/GNDANA pin7

7 PB05 PB04 PA03 PA02 PA01 PA00 PB03 PB02 PB01 PB00 VDDANA pin 8/GNDANA pin7

PACKAGE CLUSTER GPIO SUPPLIES PINS CONNECTED TO THE CLUSTER 48pins 1 PA31 PA30 VDDIN pin44/GND pin42

2 PA28 PA27 PB23 PB22 VDDIN pin44/GND pin42 and VDDIO

3 PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 PA12 PB11 PB10 VDDIO pin36/GND pin35 and VDDIO pin17/GND pin18

4 PA11 PA10 PA09 PA08 VDDIO pin17/GND pin18

5 PA07 PA06 PA05 PA04 PB09 PB08 VDDANA pin6/GNDANA pin5

6 PA03 PA02 PA01 PA00 PB03 PB02 PB05 PB04 PB01 PB00 VDDANA pin6/GNDANA pin5

32pins 1 PA31 PA30 VDDIN pin30/GND pin 28 2 PA28 PA27 PA25 PA24 PA23 PA22 PA19 PA18 PA17 PA16 PA15 PA14 PA11 PA10 PA09 PA08 VDDIN pin30/GND pin 28 and VDDANA pin9/GND pin10

3 PA07 PA06 PA05 PA04 PA03 PA02 PA01 PA00 PB05 PB04 PB03 PB02 VDDANA pin9/GND pin10

The SAM D21/DA1 has up to four instances of the Timer/Counter for Control applications (TCC) peripheral , TCC[3:0]. The following table lists the features for each TCC instance. Table 7-7. TCC Configuration Summary TCC# Channels (CC_NUM) Waveform Output (WO_NUM) Counter Size Fault Dithering Output Matrix Dead Time Insertion (DTI) SWAP Pattern Generation 0 4 8 24-bit Yes Yes Yes Yes Yes Yes 1 2 4 24-bit Yes Yes Yes 2 2 2 16-bit Yes 3 4 8 24-bit Yes Yes Yes Yes Yes Yes Note: The number of CC registers (CC_NUM) for each TCC corresponds to the number of compare/capture channels, so that a TCC can have more Waveform Outputs (WO_NUM) than CC registers. SAM D21/DA1 Family I/O Multiplexing and Considerations © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 34

Power Supply and Start-Up Considerations

8.1 Power Domain Overview

PA[7:2] PB[9:0] PA[1:0] Digital Logic (CPU, peripherals) DFLL48M VDDIO OSC8M XOSC OSCULP32K PA[31:16] PB[31:10] PA[15:14] BOD33 POR PA[13:8]BOD12 FDPLL96M ADC AC AC1

8.2 Power Supply Considerations

8.2.1 Power Supplies

The device has several different power supply pins:

VDDIO: Powers I/O lines, OSC8M and XOSC. Voltage is 1.62V to 3.63V.
VDDIN: Powers I/O lines and the internal regulator. Voltage is 1.62V to 3.63V.
VDDANA: Powers I/O lines and the ADC, AC, DAC, PTC, OSCULP32K, OSC32K, XOSC32K. Voltage is 1.62V to 3.63V.
VDDCORE: Internal regulated voltage output. Powers the core, memories, peripherals, FDPLL96M, and DFLL48M. Voltage is 1.2V. The same voltage must be applied to both VDDIN, VDDIO and VDDANA. This common voltage is referred to as VDD in the datasheet. The ground pins, GND, are common to VDDCORE, VDDIO and VDDIN. The ground pin for VDDANA is GNDANA. For decoupling recommendations for the different power supplies. Refer to Schematic Checklist for details. Related Links 45. Schematic Checklist SAM D21/DA1 Family Power Supply and Start-Up Considerations © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 35

8.2.2 Voltage Regulator

The voltage regulator has two different modes:

Normal mode: To be used when the CPU and peripherals are running
Low Power (LP) mode: To be used when the regulator draws small static current. It can be used in standby mode

8.2.3 Typical Powering Schematics

The device uses a single main supply with a range of 1.62V - 3.63V. The following figure shows the recommended power supply connection. Figure 8-1. Power Supply Connection (1.62V — 3.63V) Main Supply VDDIO VDDANA VDDIN VDDCORE GND GNDANA DEVICE

8.2.4 Power-Up Sequence

8.2.4.1 Minimum Rise Rate

The integrated Power-on Reset (POR) circuitry monitoring the VDDANA power supply requires a minimum rise rate. Refer to the Electrical Characteristics for details. Related Links 37. Electrical Characteristics at 85℃

8.2.4.2 Maximum Rise Rate

The rise rate of the power supply must not exceed the values described in Electrical Characteristics. Refer to the Electrical Characteristics for details. Related Links 37. Electrical Characteristics at 85℃ SAM D21/DA1 Family Power Supply and Start-Up Considerations © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 36

8.3 Power-Up

This section summarizes the power-up sequence of the device. The behavior after power-up is controlled by the Power Manager. Refer to PM – Power Manager for details. Related Links 16. PM – Power Manager

8.3.1 Starting of Clocks

After power-up, the device is set to its initial state and kept in reset, until the power has stabilized throughout the device. Once the power has stabilized, the device will use a 1MHz clock. This clock is derived from the 8MHz Internal Oscillator (OSC8M), which is divided by eight and used as a clock source for generic clock generator 0. Generic clock generator 0 is the main clock for the Power Manager (PM). Some synchronous system clocks are active, allowing software execution. Refer to the “Clock Mask Register” section in PM – Power Manager for the list of default peripheral clocks running. Synchronous system clocks that are running are by default not divided and receive a 1MHz clock through generic clock generator 0. Other generic clocks are disabled except GCLK_WDT, which is used by the Watchdog Timer (WDT). Related Links 16. PM – Power Manager

8.3.2 I/O Pins

After power-up, the I/O pins are tri-stated.

8.3.3 Fetching of Initial Instructions

After reset has been released, the CPU starts fetching PC and SP values from the reset address, which is 0x00000000. This address points to the first executable address in the internal Flash. The code read from the Internal Flash is free to configure the clock system and clock sources. Refer to PM – Power Manager, GCLK – Generic Clock Controller and SYSCTRL – System Controller for details. Refer to the ARM Architecture Reference Manual for more information on CPU startup (http://www.arm.com). Related Links 16. PM – Power Manager 17. SYSCTRL – System Controller 14. Clock System

8.4 Power-On Reset and Brown-Out Detector

The SAM D21 embeds three features to monitor, warn and/or reset the device:

POR: Power-On Reset on VDDANA
BOD33: Brown-Out Detector on VDDANA
BOD12: Voltage Regulator Internal Brown-Out Detector on VDDCORE. The Voltage Regulator Internal BOD is calibrated in production and its calibration configuration is stored in the NVM User Row. This configuration should not be changed if the user row is written to assure the correct behavior of the BOD12.

8.4.1 Power-On Reset on VDDANA

POR monitors VDDANA. It is always activated and monitors voltage at startup and also during all the sleep modes. If VDDANA goes below the threshold voltage, the entire chip is reset.

8.4.2 Brown-Out Detector on VDDANA

BOD33 monitors VDDANA. Refer to SYSCTRL – System Controller for details. Related Links 17. SYSCTRL – System Controller SAM D21/DA1 Family Power Supply and Start-Up Considerations © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 37

8.4.3 Brown-Out Detector on VDDCORE

Product Mapping Figure 9-1. SAM D21 Product Mapping Code SRAM Undefined Peripherals Reserved Global Memory Space 0x00000000 0x20000000 0x20008000 0x40000000 0x43000000 0x60000000 Internal SRAM AHB-APB Bridge A AHB-APB Bridge B AHB-APB Bridge C AHB-APB Internal Flash Reserved Code 0x00000000 0x00040000 0x1FFFFFFF 0x20000000 0x20007FFF 0x40000000 0x41000000 0x42000000 0x42FFFFFF Reserved PAC0 PM SYSCTRL GCLK WDT RTC EIC AHB-APB Bridge A 0x40000000 0x40000400 0x40000800 0x40000C00 0x40001000 0x40001400 0x40001800 0x40FFFFFF 0x40001C00 AHB-APB Bridge B PAC1 DSU NVMCTRL PORT 0x41000000 0x41002000 0x41004000 0x41004400 0x41FFFFFF 0x41007000 SERCOM5 PAC2 EVSYS SERCOM0 SERCOM1 SERCOM2 SERCOM3 SERCOM4 AHB-APB Bridge C TC7 TCC0 TCC1 TCC2 TC3 TC4 TC5 TC6 ADC AC 0x42000000 0x42000400 0x42000800 0x42000C00 0x42001000 0x42001400 0x42001800 0x42002000 0x42001C00 0x42003000 0x42003400 0x42003800 0x42003C00 0x42004000 0x42004400 0x42004800 Reserved 0x60000200 0xFFFFFFFF Reserved System 0xE0000000 DAC 0x42004C00 0x42002400 0x42002800 0x42002C00 PTC 0x42005400 0x42005000 I2S DMAC USB MTB 0x41004800 0x41005000 0x41006000 0xE0000000 0xE000E000 0xE000F000 0xE00FF000 0xE0100000 0xFFFFFFFF System Reserved SCS Reserved ROMTable Reserved Internal Flash Device Variant A Device Variant B/C/D/L AC1 SRAM Reserved 0x42006000 IOBUS TCC3 Reserved 0x420058000x42005800 0x42005800 0x42006090 0x4200FFFF 0x1FFFFFFF Reserved 0x00000000 0x00040000 0x00400000 RWWEE Section Internal RWWEE Section SAM D21/DA1 Family Product Mapping © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 39

This figure represents the full configuration of the SAM D21 with maximum Flash and SRAM capabilities and a full set of peripherals. Refer to the 2. Configuration Summary for details. SAM D21/DA1 Family Product Mapping © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 40

Memories

10.1 Embedded Memories

Internal high-speed Flash
Read-While-Write EEPROM Emulation (RWWEE, standing for Read (the main array) while Write (the EEPROM Emulation)) (Only available on device variant B, C, D, and L)
Internal high-speed RAM, single-cycle access at full speed

10.2 Physical Memory Map

The High-Speed bus is implemented as a bus matrix. All High-Speed bus addresses are fixed, and they are never remapped in any way, even during boot. The 32-bit physical address space is mapped as follow: Table 10-1. SAM D21 Physical Memory Map(1)(1) Memory Start address Size SAMD21x18 SAMD21x17 SAMD21x16 SAMD21x15 SAMD21x16L SAMD21x15L Internal Flash 0x00000000 256 Kbytes 128 Kbytes 64 Kbytes 32 Kbytes 64 Kbytes 32 Kbytes Internal RWWEE Emulation section(2) 0x00400000 - 4 Kbytes 2 Kbytes 1 Kbytes 2 Kbytes 1 Kbytes Internal SRAM 0x20000000 32 Kbytes 16 Kbytes 8 Kbytes 4 Kbytes 8 Kbytes 4 Kbytes Peripheral Bridge A 0x40000000 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes Peripheral Bridge B 0x41000000 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes Peripheral Bridge C 0x42000000 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes Table 10-2. SAM DA1 Physical memory map(1) Memory Start Address Size SAMDA1x16 SAMDA1x15 SAMDA1x14 Internal Flash 0x00000000 64Kbytes 32Kbytes 16Kbytes Internal RWWEE Emulation section 0x00400000 2Kbytes 1Kbytes 512bytes Internal SRAM 0x20000000 8Kbytes 4Kbytes 4Kbytes Peripheral Bridge A 0x40000000 64Kbytes 64Kbytes 64Kbytes Peripheral Bridge B 0x41000000 64Kbytes 64Kbytes 64Kbytes Peripheral Bridge C 0x42000000 64Kbytes 64Kbytes 64Kbytes Notes: 1. x = G, J, or E. 2. Only applicable for device variants B, C, D, and L. SAM D21/DA1 Family Memories © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 41

Table 10-3. SAM D21 Flash Memory Parameters(1,2)(1) Device Flash size Number of pages Page size SAMD21x18 256 Kbytes 4096 64 bytes SAMD21x17 128 Kbytes 2048 64 bytes SAMD21x16 64 Kbytes 1024 64 bytes SAMD21x15 32 Kbytes 512 64 bytes Table 10-4. SAM DA1 Flash memory parameters(1) Device Flash Size Number of Pages Page Size SAMDA1x16 64Kbytes 1024 64 bytes SAMDA1x15 32Kbytes 512 64 bytes SAMDA1x14 16Kbytes 256 64 bytes Notes: 1. x = G, J, or E. 2. The number of pages (NVMP) and page size (PSZ) can be read from the NVM Pages and Page Size bits in the NVM Parameter register in the NVMCTRL (PARAM.NVMP and PARAM.PSZ, respectively). Refer to NVM Parameter (PARAM) register for details. Table 10-5. SAM D21 RWWEE Emulation Section Parameters (Device Variants B, C, D,and L) Device(1) Flash size Number of pages Page size SAMD21x17 4 Kbytes 64 64 bytes SAMD21x16 2 Kbytes 32 64 bytes SAMD21x15 1 Kbytes 16 64 bytes Table 10-6. SAM DA1 RWWEE Emulation Section Parameters Device Flash Size Number of Pages Page Size SAMDA1x16 2Kbytes 32 64 bytes SAMDA1x15 1Kbytes 16 64 bytes SAMDA1x14 512 bytes 8 64 bytes Note: 1. x = G, J, or E. Related Links

22.8.3 PARAM

SAM D21 Ordering Information(1)

10.3 NVM Calibration and Auxiliary Space

The device calibration data are stored in different sections of the NVM calibration and auxiliary space presented in the following figure. SAM D21/DA1 Family Memories © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 42

Figure 10-1. Calibration and Auxiliary Space 0x00800000 AUX0 offset address Automatic calibration row Calibration and auxiliary space address offset AUX0 – NVM User Row AUX1 0x00804000 0x00806000 AUX1 offset address 0x00806000 Area 3 offset address Area 1: Reserved (64 bits) Area 2: Device configuration area (64 bits) Area 1 address offset Area 2 offset address Area 3: Reserved (128bits) Area 4: Software calibration area (256bits) 0x00806008 0x00806010 0x00806020 Area 4 offset address AUX10x00806040 0x00000000 NVM base address + NVM size NVM main address space NVM Base Address Calibration and auxiliary space0x00800000 NVM base address + 0x00800000 The values from the automatic calibration row are loaded into their respective registers at startup.

10.3.1 NVM User Row Mapping

The first two 32-bit words of the NVM User Row contain calibration data that are automatically read at device power on. The NVM User Row can be read at address 0x804000. To write the NVM User Row refer to NVMCTRL – Non-Volatile Memory Controller. When writing to the user row the values do not get loaded by the other modules on the device until a device reset occurs. Table 10-7. NVM User Row Mapping Bit Position Name Usage 2:0 BOOTPROT Used to select one of eight different bootloader sizes. Refer to “NVMCTRL – Non-Volatile Memory Controller”. Default value = 7 except for WLCSP (Default value = 3).

3 Reserved

6:4 EEPROM Used to select one of eight different EEPROM Emulation sizes. Refer to “NVMCTRL – Non-Volatile Memory Controller”. Default value = 7.

7 Reserved

13:8 BOD33 Level BOD33 Threshold Level at power on. Refer to the SYSCTRL BOD33 register. Default value = 0x7 (non-AECQ100) Default value = 0x22 (AECQ100) 14 BOD33 Enable BOD33 enable at power on. Refer to the SYSCTRL BOD33 register. Default value = 1. SAM D21/DA1 Family Memories © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 43

16:15 BOD33 Action BOD33 Action at power on. Refer to the SYSCTRL BOD33 register. Default value = 1. 24:17 Reserved Voltage Regulator Internal BOD (BOD12) configuration. These bits are written in production and must not be changed. Default value = 0x70. 25 WDT Enable WDT Enable at power on. Refer to the WDT CTRL register. Default value = 0. 26 WDT Always-On WDT Always-On at power on. Refer to the WDT CTRL register. Default value = 0. 30:27 WDT Period WDT Period at power on. Refer to the WDT CONFIG register. Default value = 0x0B. 34:31 WDT Window WDT Window mode time-out at power on. Refer to the WDT CONFIG register. Default value = 0x05. 38:35 WDT EWOFFSET WDT Early Warning Interrupt Time Offset at power on. Refer to the WDT EWCTRL register. Default value = 0x0B. 39 WDT WEN WDT Timer Window Mode Enable at power on. Refer to the WDT CTRL register. Default value = 0. 40 BOD33 Hysteresis BOD33 Hysteresis configuration at power on. Refer to the SYSCTRL BOD33 register. Default value = 0. 41 Reserved Voltage Regulator Internal BOD(BOD12) configuration. This bit is written in production and must not be changed. Default value = 0. 47:42 Reserved 63:48 LOCK NVM Region Lock Bits. Refer to “NVMCTRL – Non-Volatile Memory Controller”. Default value = 0xFFFF. Related Links 22. Nonvolatile Memory Controller (NVMCTRL)

17.8.14 BOD33

18.8.1 CTRL

10.3.2 NVM Software Calibration Area Mapping

The NVM Software Calibration Area contains calibration data that are measured and written during production test. These calibration values should be read by the application software and written back to the corresponding register. The NVM Software Calibration Area can be read at address 0x806020. The NVM Software Calibration Area can not be written. Table 10-8. NVM Software Calibration Area Mapping Bit Position Name Description 2:0 Reserved 14:3 Reserved 26:15 Reserved 34:27 ADC LINEARITY ADC Linearity Calibration. Should be written to ADC CALIB register. 37:35 ADC BIASCAL ADC Bias Calibration. Should be written to ADC CALIB register. SAM D21/DA1 Family Memories © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 44

Bit Position Name Description 44:38 OSC32K CAL OSC32KCalibration. Should be written to SYSCTRL OSC32K register. 49:45 USB TRANSN USB TRANSN calibration value. Should be written to USB PADCAL register. 54:50 USB TRANSP USB TRANSP calibration value. Should be written to USB PADCAL register. 57:55 USB TRIM USB TRIM calibration value. Should be written to the USB PADCAL register. 63:58 DFLL48M COARSE CAL DFLL48M Coarse calibration value. Should be written to SYSCTRL DFLLVAL register. 73:64 Reserved 127:74 Reserved

10.3.3 Serial Number

Each device has a unique 128-bit serial number which is a concatenation of four 32-bit words contained at the following addresses: Word 0: 0x0080A00C Word 1: 0x0080A040 Word 2: 0x0080A044 Word 3: 0x0080A048 The uniqueness of the serial number is guaranteed only when using all 128 bits. SAM D21/DA1 Family Memories © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 45

Processor And Architecture

11.1 Cortex M0+ Processor

The SAM D21 implements the ARM® Cortex®-M0+ processor, based on the ARMv6 Architecture and Thumb®-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0 core, and upward compatible to Cortex-M3 and M4 cores. The ARM Cortex-M0+ implemented is revision r0p1. For more information refer to www.arm.com.

11.1.1 Cortex M0+ Configuration

Table 11-1. Cortex M0+ Configuration Features Configurable option Device configuration Interrupts External interrupts 0-32 28 Data endianness Little-endian or big-endian Little-endian SysTick timer Present or absent Present Number of watchpoint comparators 0, 1, 2 2 Number of breakpoint comparators 0, 1, 2, 3, 4 4 Halting debug support Present or absent Present Multiplier Fast or small Fast (single cycle) Single-cycle I/O port Present or absent Present Wake-up interrupt controller Supported or not supported Not supported Vector Table Offset Register Present or absent Present Unprivileged/Privileged support Present or absent Absent(1) Memory Protection Unit Not present or 8-region Not present Reset all registers Present or absent Absent Instruction fetch width 16-bit only or mostly 32-bit 32-bit Note: 1. All software run in Privileged mode only. The ARM Cortex-M0+ core has the following two bus interfaces:

Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all system memory, which includes Flash and RAM.
Single 32-bit I/O port bus interfacing to the PORT with 1-cycle loads and stores.

11.1.2 Cortex-M0+ Peripherals

System Control Space (SCS) – The processor provides debug through registers in the SCS. Refer to the Cortex-M0+ Technical Reference Manual for details (www.arm.com).
System Timer (SysTick) – The System Timer is a 24-bit timer clocked by CLK_CPU that extends the functionality of both the processor and the NVIC. Refer to the Cortex-M0+ Technical Reference Manual for details (www.arm.com).
Nested Vectored Interrupt Controller (NVIC) – External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software can set the priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely coupled, providing low SAM D21/DA1 Family Processor And Architecture © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 46

latency interrupt processing and efficient processing of late arriving interrupts. Refer to 11.2 Nested Vector Interrupt Controller and the Cortex-M0+ Technical Reference Manual for details (www.arm.com).

System Control Block (SCB) – The System Control Block provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions. Refer to the Cortex-M0+ Devices Generic User Guide for details (www.arm.com).
Micro Trace Buffer (MTB) – The CoreSight MTB-M0+ (MTB) provides a simple execution trace capability to the Cortex-M0+ processor. Refer to section 11.3 Micro Trace Buffer and the CoreSight MTB-M0+ Technical Reference Manual for details (www.arm.com).

11.1.3 Cortex-M0+ Address Map

Table 11-2. Cortex-M0+ Address Map Address Peripheral 0xE000E000 System Control Space (SCS) 0xE000E010 System Timer (SysTick) 0xE000E100 Nested Vectored Interrupt Controller (NVIC) 0xE000ED00 System Control Block (SCB) 0x41006000 (see also Product Mapping) Micro Trace Buffer (MTB)

11.1.4 I/O Interface

11.1.4.1 Overview

Because accesses to the AMBA® AHB-Lite™ and the single cycle I/O interface can be made concurrently, the Cortex-M0+ processor can fetch the next instructions while accessing the I/Os. This enables single cycle I/O accesses to be sustained for as long as needed. Refer to CPU Local Bus for more information. Related Links

23.5.10 CPU Local Bus

11.1.4.2 Description

Direct access to PORT registers.

11.2 Nested Vector Interrupt Controller

11.2.1 Overview

The Nested Vectored Interrupt Controller (NVIC) in the SAM D21 supports 32 interrupt lines with four different priority levels. For more details, refer to the Cortex-M0+ Technical Reference Manual (www.arm.com).

11.2.2 Interrupt Line Mapping

Each of the 29 interrupt lines is connected to one peripheral instance, as shown in the table below. Each peripheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register. The Interrupt flag is set when the Interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by writing a one to the corresponding bit in the peripheral’s Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the corresponding bit in the peripheral’s Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated from the peripheral when the Interrupt flag is set and the corresponding interrupt is enabled. The interrupt requests for one peripheral are ORed together on system level, generating one interrupt request for each peripheral. An interrupt request will set the corresponding Interrupt Pending bit in the NVIC Interrupt Pending registers (SETPEND/CLRPEND bits in ISPR/ICPR). For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC Interrupt Priority registers IPR0-IPR7 provide a priority field for each interrupt. SAM D21/DA1 Family Processor And Architecture © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 47

Table 11-3. Interrupt Line Mapping Peripheral Source NVIC Line EIC NMI – External Interrupt Controller NMI PM – Power Manager 0 SYSCTRL – System Control 1 WDT – Watchdog Timer 2 RTC – Real-Time Counter 3 EIC – External Interrupt Controller 4 NVMCTRL – Nonvolatile Memory Controller 5 DMAC - Direct Memory Access Controller 6 USB - Universal Serial Bus 7 EVSYS – Event System 8 SERCOM0 – Serial Communication Interface 0 9 SERCOM1 – Serial Communication Interface 1 10 SERCOM2 – Serial Communication Interface 2 11 SERCOM3 – Serial Communication Interface 3 12 SERCOM4 – Serial Communication Interface 4 13 SERCOM5 – Serial Communication Interface 5 14 TCC0 – Timer Counter for Control 0 15 TCC1 – Timer Counter for Control 1 16 TCC2 – Timer Counter for Control 2 17 TC3 – Timer Counter 3 18 TC4 – Timer Counter 4 19 TC5 – Timer Counter 5 20 TC6 – Timer Counter 6 21 TC7 – Timer Counter 7 22 ADC – Analog-to-Digital Converter 23 AC – Analog Comparator 24 DAC – Digital-to-Analog Converter 25 PTC – Peripheral Touch Controller 26 I2S - Inter IC Sound 27 AC1 - Analog Comparator 1 28 TCC3 - Timer Counter for Control 3 29 SAM D21/DA1 Family Processor And Architecture © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 48

11.3 Micro Trace Buffer

11.3.1 Features

Program flow tracing for the Cortex-M0+ processor
MTB SRAM can be used for both trace and general purpose storage by the processor
The position and size of the trace buffer in SRAM is configurable by software
CoreSight compliant

11.3.2 Overview

When enabled, the MTB records changes in program flow, reported by the Cortex-M0+ processor over the execution trace interface shared between the Cortex-M0+ processor and the CoreSight MTB-M0+. This information is stored as trace packets in the SRAM by the MTB. An off-chip debugger can extract the trace information using the Debug Access Port to read the trace information from the SRAM. The debugger can then reconstruct the program flow from this information. The MTB simultaneously stores trace information into the SRAM, and gives the processor access to the SRAM. The MTB ensures that trace write accesses have priority over processor accesses. The execution trace packet consists of a pair of 32-bit words that the MTB generates when it detects the processor PC value changes non-sequentially. A non-sequential PC change can occur during branch instructions or during exception entry. See the CoreSight MTB-M0+ Technical Reference Manual for more details on the MTB execution trace packet format. Tracing is enabled when the MASTER.EN bit in the Master Trace Control register is 1. There are various ways to set the bit to 1 to start tracing, or to 0 to stop tracing. See the CoreSight Cortex-M0+ Technical Reference Manual for more details on the trace start and stop and for a detailed description of the MTB’s MASTER register. The MTB can be programmed to stop tracing automatically when the memory fills to a specified watermark level or to start or stop tracing by writing directly to the MASTER.EN bit. If the watermark mechanism is not being used and the trace buffer overflows, then the buffer wraps around overwriting previous trace packets. The base address of the MTB registers is 0x41006000; this address is also written in the CoreSight ROM Table. The offset of each register from the base address is fixed and as defined by the CoreSight MTB-M0+ Technical Reference Manual. The MTB has four programmable registers to control the behavior of the trace features:

POSITION: Contains the trace Write Pointer and the wrap bit,
MASTER: Contains the main trace enable bit and other trace control fields,
FLOW: Contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits,
BASE: Indicates where the SRAM is located in the processor memory map. This register is provided to enable auto-discovery of the MTB SRAM location, by a debug agent. See the CoreSight MTB-M0+ Technical Reference Manual for a detailed description of these registers.

11.4 High-Speed Bus System

11.4.1 Features

High-Speed Bus Matrix has the following features:

Symmetric crossbar bus switch implementation
Allows concurrent accesses from different hosts to different clients
32-bit data bus
Operation at a one-to-one clock frequency with the bus hosts SAM D21/DA1 Family Processor And Architecture © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 49

11.4.2 Configuration

Table 11-4. Bus Matrix Hosts Bus Matrix Hosts Host ID CM0+ - Cortex M0+ Processor 0 DSU - Device Service Unit 1 DMAC - Direct Memory Access Controller - Data Access 2 Table 11-5. Bus Matrix Clients Bus Matrix Clients Client ID Internal Flash Memory 0 AHB-APB Bridge A 1 AHB-APB Bridge B 2 AHB-APB Bridge C 3 SRAM Port 4 - CM0+ Access 4 SRAM Port 5 - DMAC Data Access 5 SRAM Port 6 - DSU Access 6 SAM D21/DA1 Family Processor And Architecture © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 50

Table 11-6. SRAM Port Connection SRAM Port Connection Port ID Connection Type MTB - Micro Trace Buffer 0 Direct USB - Universal Serial Bus 1 Direct DMAC - Direct Memory Access Controller - Write-Back Access 2 Direct DMAC - Direct Memory Access Controller - Fetch Access 3 Direct CM0+ - Cortex M0+ Processor 4 Bus Matrix DMAC - Direct Memory Access Controller - Data Access 5 Bus Matrix DSU - Device Service Unit 6 Bus Matrix

11.4.3 SRAM Quality of Service

To ensure that hosts with latency requirements get sufficient priority when accessing RAM, the different hosts can be configured to have a given priority for different type of access. The Quality of Service (QoS) level is independently selected for each host accessing the RAM. For any access to the RAM the RAM also receives the QoS level. The QoS levels and their corresponding bit values for the QoS level configuration is shown in the following table. Table 11-7. Quality of Service Value Name Description

00 DISABLE Background (no sensitive operation)

01 LOW Sensitive Bandwidth

10 MEDIUM Sensitive Latency

11 HIGH Critical Latency

If a host is configured with QoS level 0x00 or 0x01 there will be minimum one cycle latency for the RAM access. The priority order for concurrent accesses are decided by two factors. First the QoS level for the host and then a static priority given by table nn-mm (table: SRAM port connection) where the lowest port ID has the highest static priority. The MTB has fixed QoS level 3 and the DSU has fixed QoS level 1. The CPU QoS level can be written/read at address 0x41007120, bits [1:0]. Its reset value is 0x2. Refer to different host QOSCTRL registers for configuring QoS for the other hosts (USB, DMAC).

11.5 AHB-APB Bridge

The AHB-APB bridge is an AHB client, providing an interface between the high-speed AHB domain and the low- power APB domain. It is used to provide access to the Programmable Control registers of peripherals. AHB-APB bridge is based on AMBA APB Protocol Specification V2.0 (ref. as APB4) including:

Wait state support
Error reporting
Transaction protection
Sparse data transfer (byte, half-word and word) Additional enhancements:
Address and data cycles merged into a single cycle
Sparse data transfer also apply to read access SAM D21/DA1 Family Processor And Architecture © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 51

To operate the AHB-APB bridge, the clock (CLK_HPBx_AHB) must be enabled. See PM – Power Manager for details. Figure 11-1. APB Write Access T0 T1 T2 T3 Addr 1 Data 1 PADDR PWRITE PCLK PSEL PENABLE PWDATA PREADY T0 T1 T2 T3 Addr 1 Data 1 PADDR PWRITE PCLK PSEL PENABLE PWDATA PREADY T4 T5 Wait statesNo wait states Figure 11-2. APB Read Access T0 T1 T2 T3 Addr 1 Data 1 PADDR PWRITE PCLK PSEL PENABLE PRDATA PREADY T0 T1 T2 T3 Addr 1 Data 1 PADDR PWRITE PCLK PSEL PENABLE PRDATA PREADY T4 T5 Wait statesNo wait states Related Links 16. PM – Power Manager 9. Product Mapping

11.6 Peripheral Access Controller (PAC)

11.6.1 Overview

One PAC is associated with each AHB-APB bridge and the PAC can provide write protection for registers of each peripheral connected on the same bridge. The PAC peripheral bus clock (CLK_PACx_APB) can be enabled and disabled in the Power Manager. CLK_PAC0_APB and CLK_PAC1_APB are enabled are reset. CLK_PAC2_APB is disabled at reset. Refer to PM – Power Manager for details. The PAC will continue to operate in any Sleep mode where the selected clock source is running. Write-protection does not apply for debugger access. When the debugger makes an access to a peripheral, write-protection is ignored so that the debugger can update the register. SAM D21/DA1 Family Processor And Architecture © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 52

Write-protect registers allow the user to disable a selected peripheral’s write-protection without doing a read-modify- write operation. These registers are mapped into two I/O memory locations, one for clearing and one for setting the register bits. Writing a one to a bit in the Write Protect Clear register (WPCLR) will clear the corresponding bit in both registers (WPCLR and WPSET) and disable the write-protection for the corresponding peripheral, while writing a one to a bit in the Write Protect Set (WPSET) register will set the corresponding bit in both registers (WPCLR and WPSET) and enable the write-protection for the corresponding peripheral. Both registers (WPCLR and WPSET) will return the same value when read. If a peripheral is write-protected, and if a write access is performed, data will not be written, and the peripheral will return an access error (CPU exception). The PAC also offers a safety feature for correct program execution, with a CPU exception generated on double write-protection or double unprotection of a peripheral. If a peripheral n is write-protected and a write to one in WPSET[n] is detected, the PAC returns an error. This can be used to ensure that the application follows the intended program flow by always following a write-protect with an unprotect, and vice versa. However, in applications where a write-protected peripheral is used in several contexts, for example, interrupts, care should be taken so that either the interrupt can not happen while the main application or other interrupt levels manipulate the write-protection status, or when the interrupt handler needs to unprotect the peripheral, based on the current protection status, by reading WPSET. Related Links 16. PM – Power Manager

11.6.2 Register Description

Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Refer to the Product Mapping for PAC locations.

11.6.2.1 PAC0 Register Description

11.6.2.1.1 Write Protect Clear

Name: WPCLR Offset: 0x00 Reset: 0x000000 Property: – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 EIC RTC WDT GCLK SYSCTRL PM Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 6 – EIC Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals. Value Description 0 Write-protection is disabled. 1 Write-protection is enabled. Bit 5 – RTC Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals. Value Description 0 Write-protection is disabled. 1 Write-protection is enabled. Bit 4 – WDT Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals. Value Description 0 Write-protection is disabled. 1 Write-protection is enabled. Bit 3 – GCLK Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals. Value Description 0 Write-protection is disabled. 1 Write-protection is enabled. SAM D21/DA1 Family Processor And Architecture © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 54

Bit 2 – SYSCTRL Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals. Value Description 0 Write-protection is disabled. 1 Write-protection is enabled. Bit 1 – PM Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals. Value Description 0 Write-protection is disabled. 1 Write-protection is enabled. SAM D21/DA1 Family Processor And Architecture © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 55

11.6.2.1.2 Write-Protect Set

Name: WPSET Offset: 0x04 Reset: 0x000000 Property: – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 EIC RTC WDT GCLK SYSCTRL PM Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 6 – EIC Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description

0 Write protection is disabled

1 Write protection is enabled

Bit 5 – RTC Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description Bit 4 – WDT Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description Bit 3 – GCLK Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description Processor And Architecture © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 56

Bit 2 – SYSCTRL Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description Bit 1 – PM Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description

11.6.2.2 PAC1 Register Description

11.6.2.2.1 Write Protect Clear

Name: WPCLR Offset: 0x00 Reset: 0x000002 Property: – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 MTB USB DMAC PORT NVMCTRL DSU Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 1 Bit 6 – MTB Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals. Value Description 0 Write-protection is disabled. 1 Write-protection is enabled. Bit 5 – USB Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals. Value Description 0 Write-protection is disabled. 1 Write-protection is enabled. Bit 4 – DMAC Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals. Value Description 0 Write-protection is disabled. 1 Write-protection is enabled. Bit 3 – PORT Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals. Value Description 0 Write-protection is disabled. 1 Write-protection is enabled. SAM D21/DA1 Family Processor And Architecture © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 58

Bit 2 – NVMCTRL Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals. Value Description 0 Write-protection is disabled. 1 Write-protection is enabled. Bit 1 – DSU Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals. Value Description 0 Write-protection is disabled. 1 Write-protection is enabled. SAM D21/DA1 Family Processor And Architecture © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 59

11.6.2.2.2 Write-Protect Set

Name: WPSET Offset: 0x04 Reset: 0x000002 Property: – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 MTB USB DMAC PORT NVMCTRL DSU Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 1 Bit 6 – MTB Writing a zero to these bits has no effect. Writing a one to these bits will Set the Write-Protect bit for the corresponding peripherals. Value Description Bit 5 – USB Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description Bit 4 – DMAC Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description Bit 3 – PORT Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description Processor And Architecture © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 60

Bit 2 – NVMCTRL Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description Bit 1 – DSU Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description

11.6.2.3 PAC2 Register Description

11.6.2.3.1 Write-Protect Clear

Name: WPCLR Offset: 0x00 Reset: 0x00800000 Property: – Bit 31 30 29 28 27 26 25 24 TCC3 Access R/W Reset 0 Bit 23 22 21 20 19 18 17 16 AC1 I2S PTC DAC AC ADC Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 TC7 TC6 TC5 TC4 TC3 TCC2 TCC1 TCC0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SERCOM[5:0] EVSYS Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 24 – TCC3 Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals. Value Description Bit 21 – AC1 Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals. Value Description Bit 20 – I2S Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals. Value Description Bit 19 – PTC Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals. Value Description Processor And Architecture © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 62

Bit 18 – DAC Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals. Value Description Bit 17 – AC Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals. Value Description Bit 16 – ADC Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals. Value Description Bits 11, 12, 13, 14, 15 – TC Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals. Value Description Bits 8, 9, 10 – TCC Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals. Value Description Bits 7:2 – SERCOM[5:0] Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals. Value Description Bit 1 – EVSYS Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals. Value Description Processor And Architecture © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 63

11.6.2.3.2 Write-Protect Set

Name: WPSET Offset: 0x04 Reset: 0x00800000 Property: – Bit 31 30 29 28 27 26 25 24 TCC3 Access R/W Reset 0 Bit 23 22 21 20 19 18 17 16 AC1 I2S PTC DAC AC ADC Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 TC7 TC6 TC5 TC4 TC3 TCC2 TCC1 TCC0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 24 – TCC3 Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description Bit 21 – AC1 Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description Bit 20 – I2S Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description Bit 19 – PTC Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description Processor And Architecture © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 64

Bit 18 – DAC Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description Bit 17 – AC Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description Bit 16 – ADC Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description Bits 11, 12, 13, 14, 15 – TC Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description Bits 8, 9, 10 – TCC Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description Bits 2, 3, 4, 5, 6, 7 – SERCOM Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description Bit 1 – EVSYS Writing a zero to these bits has no effect. Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals. Value Description

11.7 Register Access and Behavior

Write protected registers, enable protected registers, and registers in sync process should not be accessed. These accesses are illegal, and an attempt to access these registers will result generation of hard fault exception. SAM D21/DA1 Family Processor And Architecture © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 65

Peripherals Configuration Summary Table 12-1. Peripherals Configuration Summary Periph. Name Base Address IRQ Line AHB Clock APB Clock Generic Clock PAC Events DMA Index Enabled at Reset Index Enabled at Reset Index Index Prot. at Reset User Generator Index Sleep Walking AHB-APB Bridge A 0x40000000 0 Y PAC0 0x40000000 0 Y PM 0x40000400 0 1 Y 1 N Y SYSCTRL 0x40000800 1 2 Y 0: DFLL48M reference 1: FDPLL96M clk source 2: FDPLL96M 32kHz

2 N Y

WDT 0x40001000 2 4 Y 3 4 N RTC 0x40001400 3 5 Y 4 5 N 1: CMP0/ALARM0 2: CMP1 3: OVF 4-11: PER0-7 Y EIC 0x40001800 NMI,

6 Y 5 6 N 12-27: EXTINT0-15 Y

DSU 0x41002000 3 Y 1 Y 1 Y NVMCTRL 0x41004000 5 4 Y 2 Y 2 N PORT 0x41004400 3 Y 3 N DMAC 0x41004800 6 5 Y 4 Y 4 N 0-3: CH0-3 30-33: CH0-3 USB 0x41005000 7 6 Y 5 Y 6 5 N Y MTB 0x41006000 6 N AHB-APB Bridge C 0x42000000 2 Y PAC2 0x42000000 0 N EVSYS 0x42000400 8 1 N 7-18: one per CHANNEL 1 N Y SERCOM0 0x42000800 9 2 N 20: CORE 19: SLOW

2 N 1: RX

2: TX Y SERCOM1 0x42000C00 10 3 N 21: CORE 19: SLOW

3 N 3: RX

4: TX Y SERCOM2 0x42001000 11 4 N 22: CORE 19: SLOW

4 N 5: RX

6: TX Y SERCOM3 0x42001400 12 5 N 23: CORE 19: SLOW

5 N 7: RX

8: TX Y SERCOM4 0x42001800 13 6 N 24: CORE 19: SLOW

6 N 9: RX

10: TX Y SERCOM5 0x42001C00 14 7 N 25: CORE 19: SLOW

7 N 11: RX

12: TX Y TCC0 0x42002000 15 8 N 26 8 N 4-5: EV0-1 6-9: MC0-3 34: OVF 35: TRG 36: CNT 37-40: MC0-3 13: OVF 14-17: MC0-3 Y TCC1 0x42002400 16 9 N 26 9 N 10-11: EV0-1 12-13: MC0-1 41: OVF 42: TRG 43: CNT 44-45: MC0-1 18: OVF 19-20: MC0-1 Y TCC2 0x42002800 17 10 N 27 10 N 14-15: EV0-1 16-17: MC0-1 46: OVF 47: TRG 48: CNT 49-50: MC0-1 21: OVF 22-23: MC0-1 Y TC3 0x42002C00 18 11 N 27 11 N 18: EV 51: OVF 52-53: MC0-1 24: OVF 25-26: MC0-1 Y TC4 0x42003000 19 12 N 28 12 N 19: EV 54: OVF 55-56: MCX0-1 27: OVF 28-29: MC0-1 Y SAM D21/DA1 Family Peripherals Configuration Summary © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 66

Periph. Name Base Address IRQ Line AHB Clock APB Clock Generic Clock PAC Events DMA Index Enabled at Reset Index Enabled at Reset Index Index Prot. at Reset User Generator Index Sleep Walking TC5 0x42003400 20 13 N 28 13 N 20: EV 57: OVF 58-59: MC0-1 30: OVF 31-32: MC0-1 Y TC6 0x42003800 21 14 N 29 14 N 21: EV 60: OVF 61-62: MC0-1 33: OVF 34-35: MC0-1 Y TC7 0x42003C00 22 15 N 29 15 N 22: EV 63: OVF 64-65: MC0-1 36: OVF 37-38: MC0-1 Y ADC 0x42004000 23 16 Y 30 16 N 23: START 24: SYNC 66: RESRDY 67: WINMON 39: RESRDY Y AC 0x42004400 24 17 N 31: DIG 32: ANA

17 N 25-26: SOC0-1 68-69: COMP0-1

70: WIN0 Y DAC 0x42004800 25 18 N 33 18 N 27: START 71: EMPTY 40: EMPTY Y PTC 0x42004C00 26 19 N 34 19 N 28: STCONV 72: EOC 73: WCOMP I2S 0x42005000 27 20 N 35-36 20 N 41:42: RX 43:44: TX Y AC1 0x42005400 28 21 N 31: DIG 32: ANA

21 N 25-26: SOC0-1 68-69: COMP0-1

70: WIN0 Y TCC3 0x42006000 29 22 N 37 24 N 31-32: EV0-1, 33-36: MC0-3 77: OVF, 78: TRG, 79 CNT, 80-83 MC 0x2D:OVF 0x2E: MC0 0x2F: MC1 0x30: MC2 0x31: MC3 Y SAM D21/DA1 Family Peripherals Configuration Summary © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 67

DSU - Device Service Unit

13.1 Overview

The Device Service Unit (DSU) provides a means of detecting debugger probes. It enables the ARM Debug Access Port (DAP) to have control over multiplexed debug pads and CPU reset. The DSU also provides system-level services to debug adapters in an ARM debug system. It implements a CoreSight Debug ROM that provides device identification as well as identification of other debug components within the system. Hence, it complies with the ARM Peripheral Identification specification. The DSU also provides system services to applications that need memory testing, as required for IEC60730 Class B compliance, for example. The DSU can be accessed simultaneously by a debugger and the CPU, as it is connected on the High-Speed Bus Matrix. For security reasons, some of the DSU features will be limited or unavailable when the device is protected by the NVMCTRL security bit. Related Links

13.11.6 System Services Availability when Accessed Externally and Device is Protected

Nonvolatile Memory Controller (NVMCTRL)

22.6.6 Security Bit

13.2 Features

CPU reset extension
Debugger probe detection (Cold- and Hot-Plugging)
Chip-Erase command and status
32-bit cyclic redundancy check (CRC32) of any memory accessible through the bus matrix
ARM ® CoreSight™ compliant device identification
Two debug communications channels
Debug access port security filter
Onboard memory built-in self-test (MBIST)

13.3 Block Diagram

Figure 13-1. DSU Block Diagram DSU SWCLK CORESIGHT ROM DAP SECURITY FILTER CRC-32 MBIST CHIP ERASE RESET cpu_reset_extension CPUDAP SWDIO NVMCTRL DBG M HIGH-SPEED BUS MATRIXM S debugger_present DEBUGGER PROBE INTERFACE AHB-AP PORT SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 68

13.4 Signal Description

The DSU uses three signals to function. Signal Name Type Description RESET Digital Input External reset SWCLK Digital Input SW clock SWDIO Digital I/O SW bidirectional data pin Related Links 7. I/O Multiplexing and Considerations

13.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

13.5.1 I/O Lines

The SWCLK pin is by default assigned to the DSU module to allow debugger probe detection and to stretch the CPU reset phase. For more information, refer to 13.6.3 Debugger Probe Detection. The Hot-Plugging feature depends on the PORT configuration. If the SWCLK pin function is changed in the PORT or if the PORT_MUX is disabled, the Hot-Plugging feature is disabled until a power-reset or an external reset is performed.

13.5.2 Power Management

The DSU will continue to operate in Idle mode. Related Links 16. PM – Power Manager

13.5.3 Clocks

The DSU bus clocks (CLK_DSU_APB and CLK_DSU_AHB) can be enabled and disabled by the Power Manager. Refer to PM – Power Manager Related Links 16. PM – Power Manager

13.5.4 DMA

Not applicable.

13.5.5 Interrupts

Not applicable.

13.5.6 Events

Not applicable.

13.5.7 Register Access Protection

Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following:

Debug Communication Channel 0 register (DCC0)
Debug Communication Channel 1 register (DCC1) Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. Write-protection does not apply for accesses through an external debugger. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 69

13.5.8 Analog Connections

Not applicable.

13.6 Debug Operation

13.6.1 Principle of Operation

The DSU provides basic services to allow on-chip debug using the ARM Debug Access Port and the ARM processor debug resources:

CPU reset extension
Debugger probe detection For more details on the ARM debug components, refer to the ARM Debug Interface v5 Architecture Specification.

13.6.2 CPU Reset Extension

“CPU reset extension” refers to the extension of the reset phase of the CPU core after the external reset is released. This ensures that the CPU is not executing code at startup while a debugger is connects to the system. The debugger is detected on a RESET release event when SWCLK is low. At startup, SWCLK is internally pulled up to avoid false detection of a debugger if the SWCLK pin is left unconnected. When the CPU is held in the reset extension phase, the CPU Reset Extension bit of the Status A register (STATUSA.CRSTEXT) is set. To release the CPU, write a '1' to STATUSA.CRSTEXT. STATUSA.CRSTEXT will then be set to '0'. Writing a '0' to STATUSA.CRSTEXT has no effect. For security reasons, it is not possible to release the CPU reset extension when the device is protected by the NVMCTRL security bit. Trying to do so sets the Protection Error bit (PERR) of the Status A register (STATUSA.PERR). Figure 13-2. Typical CPU Reset Extension Set and Clear Timing Diagram DSU CRSTEXT Clear SWCLK CPU reset extension CPU_STATE reset running RESET pin Related Links 22. Nonvolatile Memory Controller (NVMCTRL)

13.6.3 Debugger Probe Detection

13.6.3.1 Cold Plugging

Cold-Plugging is the detection of a debugger when the system is in reset. Cold-Plugging is detected when the CPU reset extension is requested, as described above. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 70

13.6.3.2 Hot Plugging

Hot-Plugging is the detection of a debugger probe when the system is not in reset. Hot-Plugging is not possible under reset because the detector is reset when POR or RESET are asserted. Hot-Plugging is active when a SWCLK falling edge is detected. The SWCLK pad is multiplexed with other functions and the user must ensure that its default function is assigned to the debug system. If the SWCLK function is changed, the Hot-Plugging feature is disabled until a power-reset or external reset occurs. Availability of the Hot-Plugging feature can be read from the Hot-Plugging Enable bit of the Status B register (STATUSB.HPE). Figure 13-3. Hot-Plugging Detection Timing Diagram SWCLK Hot-Plugging CPU_STATE reset running RESET pin The presence of a debugger probe is detected when either Hot-Plugging or Cold-Plugging is detected. Once detected, the Debugger Present bit of the Status B register (STATUSB.DBGPRES) is set. For security reasons, Hot-Plugging is not available when the device is protected by the NVMCTRL security bit. This detection requires that pads are correctly powered. Thus, at cold startup, this detection cannot be done until POR is released. If the device is protected, Cold-Plugging is the only way to detect a debugger probe, and so the external reset timing must be longer than the POR timing. If external reset is deasserted before POR release, the user must retry the procedure above until it gets connected to the device. Related Links 22. Nonvolatile Memory Controller (NVMCTRL)

13.7 Chip Erase

Chip-Erase consists of removing all sensitive information stored in the chip and clearing the NVMCTRL security bit. Therefore, all volatile memories, the Flash memory (including the EEPROM Emulation area) and the RWWEE Emulation section will be erased. The Flash auxiliary rows, including the user row, will not be erased. When the device is protected, the debugger must first reset the device in order to be detected. This ensures that internal registers are reset after the protected state is removed. The Chip-Erase operation is triggered by writing a '1' to the Chip-Erase bit in the Control register (CTRL.CE). This command will be discarded if the DSU is protected by the Peripheral Access Controller (PAC). Once issued, the module clears volatile memories prior to erasing the Flash array. To ensure that the Chip-Erase operation is completed, check the Done bit of the Status A register (STATUSA.DONE). The Chip-Erase operation depends on clocks and power management features that can be altered by the CPU. For that reason, it is recommended to issue a Chip-Erase after a Cold-Plugging procedure to ensure that the device is in a known and safe state. The recommended sequence is as follows: 1. Issue the Cold-Plugging procedure (refer to 13.6.3.1 Cold Plugging), and the device performs these actions: 1.1. Detects the debugger probe. 1.2. Holds the CPU in reset. 2. Issue the Chip-Erase command by writing a '1' to CTRL.CE. The device then: 2.1. Clears the system volatile memories. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 71

2.2. Erases the whole Flash array (including the EEPROM Emulation area, not including auxiliary rows) and the RWWEE Emulation section. 2.3. Erases the lock row, removing the NVMCTRL security bit protection. 3. Check for completion by polling STATUSA.DONE (read as '1' when completed). 4. Reset the device to let the NVMCTRL update the fuses.

13.8 Programming

Programming the Flash or RAM memories is only possible when the device is not protected by the NVMCTRL security bit. The programming procedure is as follows: 1. At power up, RESET is driven low by a debugger. The on-chip regulator holds the system in a POR state until the input supply is above the POR threshold (refer to Powe-On Reset (POR) characteristics). The system continues to be held in this static state until the internally regulated supplies have reached a safe operating state. 2. The PM starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash Clock and any Bus Clocks that do not have clock gate control). Internal resets are maintained due to the external reset. 3. The debugger maintains a low level on SWCLK. RESET is released, resulting in a debugger Cold-Plugging procedure. 4. The debugger generates a clock signal on the SWCLK pin, the Debug Access Port (DAP) receives a clock. 5. The CPU remains in Reset due to the Cold-Plugging procedure; meanwhile, the rest of the system is released. 6. A Chip-Erase is issued to ensure that the Flash is fully erased prior to programming. 7. Programming is available through the AHB-AP. 8. After the operation is completed, the chip can be restarted either by asserting RESET or toggling power. Make sure that the SWCLK pin is high when releasing RESET to prevent extending the CPU reset. Related Links 37. Electrical Characteristics at 85℃ 22. Nonvolatile Memory Controller (NVMCTRL)

13.9 Intellectual Property Protection

Intellectual property protection consists of restricting access to internal memories from external tools when the device is protected, and this is accomplished by setting the NVMCTRL security bit. This protected state can be removed by issuing a Chip-Erase (refer to 13.7 Chip Erase). When the device is protected, read/write accesses using the AHB-AP are limited to the DSU address range and DSU commands are restricted. When issuing a Chip-Erase, sensitive information is erased from volatile memory and Flash. The DSU implements a security filter that monitors the AHB transactions inside the DAP. If the device is protected, then AHB-AP read/write accesses outside the DSU external address range are discarded, causing an error response that sets the ARM AHB-AP sticky error bits (refer to the ARM Debug Interface v5 Architecture Specification on www.arm.com). The DSU is intended to be accessed either:

Internally from the CPU, without any limitation, even when the device is protected
Externally from a debug adapter, with some restrictions when the device is protected For security reasons, DSU features have limitations when used from a debug adapter. To differentiate external accesses from internal ones, the first 0x100 bytes of the DSU register map has been mirrored at offset 0x100:
The first 0x100 bytes form the internal address range
The next 0x100 bytes form the external address range When the device is protected, the DAP can only issue MEM-AP accesses in the DSU range 0x0100-0x2000. The DSU operating registers are located in the 0x0000-0x00FF area and remapped in 0x0100-0x01FF to differentiate accesses coming from a debugger and the CPU. If the device is protected and an access is issued in the region 0x0100-0x01FF, it is subject to security restrictions. For more information, refer to the Table 13-1. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 72

Figure 13-4. APB Memory Mapping 0x0000 0x00FF 0x0100 0x01FF 0x1000 0x1FFF DSU operating registers Mirrored DSU operating registers DSU CoreSight ROM Empty Internal address range (cannot be accessed from debug tools when the device is protected by the NVMCTRL security bit) External address range (can be accessed from debug tools with some restrictions) Some features not activated by APB transactions are not available when the device is protected: Table 13-1. Feature Availability Under Protection Features Availability when the device is protected CPU Reset Extension Yes Clear CPU Reset Extension No Debugger Cold-Plugging Yes Debugger Hot-Plugging No Related Links 22. Nonvolatile Memory Controller (NVMCTRL)

13.10 Device Identification

Device identification relies on the ARM CoreSight component identification scheme, which allows the chip to be identified as a SAM device implementing a DSU. The DSU contains identification registers to differentiate the device.

13.10.1 CoreSight Identification

A system-level ARM® CoreSight™ ROM table is present in the device to identify the vendor and the chip identification method. Its address is provided in the MEM-AP BASE register inside the ARM Debug Access Port. The CoreSight ROM implements a 64-bit conceptual ID composed as follows from the PID0 to PID7 CoreSight ROM Table registers: SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 73

Figure 13-5. Conceptual 64-bit Peripheral ID Table 13-2. Conceptual 64-Bit Peripheral ID Bit Descriptions Field Size Description Location JEP-106 CC code 4 Continuation code: 0x0 PID4 JEP-106 ID code 7 Device ID: 0x1F PID1+PID2 4KB count 4 Indicates that the CoreSight component is a ROM: 0x0 PID4 RevAnd 4 Not used; read as 0 PID3 CUSMOD 4 Not used; read as 0 PID3 PARTNUM 12 Contains 0xCD0 to indicate that DSU is present PID0+PID1 REVISION 4 DSU revision (starts at 0x0 and increments by 1 at both major and minor revisions). Identifies DSU identification method variants. If 0x0, this indicates that device identification can be completed by reading the Device Identification register (DID) PID2 For more information, refer to the ARM Debug Interface Version 5 Architecture Specification.

13.10.2 Chip Identification Method

The DSU DID register identifies the device by implementing the following information:

Processor identification
Product family identification
Product series identification
Device select

13.11 Functional Description

13.11.1 Principle of Operation

The DSU provides memory services, such as CRC32 or MBIST that require almost the same interface. Hence, the Address, Length and Data registers (ADDR, LENGTH, DATA) are shared. These shared registers must be configured first; then a command can be issued by writing the Control register. When a command is ongoing, other commands are discarded until the current operation is completed. Hence, the user must wait for the STATUSA.DONE bit to be set prior to issuing another one.

13.11.2 Basic Operation

13.11.2.1 Initialization

The module is enabled by enabling its clocks. For more details, refer to 13.5.3 Clocks. The DSU registers can be PAC write-protected. Related Links © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 74

13.11.2.2 Operation From a Debug Adapter

Debug adapters should access the DSU registers in the external address range 0x100 – 0x2000. If the device is protected by the NVMCTRL security bit, accessing the first 0x100 bytes causes the system to return an error. Refer to 13.9 Intellectual Property Protection. Related Links 22. Nonvolatile Memory Controller (NVMCTRL)

13.11.2.3 Operation From the CPU

There are no restrictions when accessing DSU registers from the CPU. However, the user should access DSU registers in the internal address range (0x0 – 0x100) to avoid external security restrictions. Refer to 13.9 Intellectual Property Protection. 13.11.3 32-bit Cyclic Redundancy Check CRC32 The DSU unit provides support for calculating a cyclic redundancy check (CRC32) value for a memory area (including Flash and AHB RAM). When the CRC32 command is issued from:

The internal range, the CRC32 can be operated at any memory location
The external range, the CRC32 operation is restricted; DATA, ADDR, and LENGTH values are forced (see below) Table 13-3. AMOD Bit Descriptions when Operating CRC32 AMOD[1:0] Short name External range restrictions

0 ARRAY CRC32 is restricted to the full Flash array area (EEPROM Emulation area not included)

DATA forced to 0xFFFFFFFF before calculation (no seed)

1 EEPROM CRC32 of the whole EEPROM Emulation area DATA forced to 0xFFFFFFFF before

calculation (no seed) 2-3 Reserved - The algorithm employed is the industry standard CRC32 algorithm using the generator polynomial 0xEDB88320 (reversed representation).

13.11.3.1 Starting CRC32 Calculation

CRC32 calculation for a memory range is started after writing the start address into the Address register (ADDR) and the size of the memory range into the Length register (LENGTH). Both must be word-aligned. The initial value used for the CRC32 calculation must be written to the Data register (DATA). This value will usually be 0xFFFFFFFF, but can be, for example, the result of a previous CRC32 calculation if generating a common CRC32 of separate memory blocks. Once completed, the calculated CRC32 value can be read out of the Data register. The read value must be complemented to match standard CRC32 implementations or kept non-inverted if used as starting point for subsequent CRC32 calculations. The actual test is started by writing a '1' in the 32-bit Cyclic Redundancy Check bit of the Control register (CTRL.CRC). A running CRC32 operation can be canceled by resetting the module (writing '1' to CTRL.SWRST). Related Links 22. Nonvolatile Memory Controller (NVMCTRL)

13.11.3.2 Interpreting the Results

The user should monitor the Status A register. When the operation is completed, STATUSA.DONE is set. Then the Bus Error bit of the Status A register (STATUSA.BERR) must be read to ensure that no bus error occurred. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 75

13.11.4 Debug Communication Channels

The Debug Communication Channels (DCCO and DCC1) consist of a pair of registers with associated handshake logic, accessible by both CPU and debugger even if the device is protected by the NVMCTRL security bit. The registers can be used to exchange data between the CPU and the debugger, during run time as well as in debug mode. This enables the user to build a custom debug protocol using only these registers. The DCC0 and DCC1 registers are accessible when the protected state is active. When the device is protected, however, it is not possible to connect a debugger while the CPU is running (STATUSA.CRSTEXT is not writable and the CPU is held under Reset). Two Debug Communication Channel status bits in the Status B registers (STATUS.DCCDx) indicate whether a new value has been written in DCC0 or DCC1. These bits, DCC0D and DCC1D, are located in the STATUSB registers. They are automatically set on write and cleared on read. Note: The DCC0 and DCC1 registers are shared with the on-board memory testing logic (MBIST). Accordingly, DCC0 and DCC1 must not be used while performing MBIST operations. Related Links 22. Nonvolatile Memory Controller (NVMCTRL)

13.11.5 Testing of On-Board Memories MBIST

The DSU implements a feature for automatic testing of memory, also known as MBIST (memory built-in self test). This is primarily intended for production test of on-board memories. MBIST cannot be operated from the external address range when the device is protected by the NVMCTRL security bit. If an MBIST command is issued when the device is protected, a protection error is reported in the Protection Error bit in the Status A register (STATUSA.PERR). 1. Algorithm The algorithm used for testing is a type of March algorithm called "March LR". This algorithm is able to detect a wide range of memory defects, while still keeping a linear run time. The algorithm is: 1.1. Write entire memory to '0', in any order. 1.2. Bit by bit read '0', write '1', in descending order. 1.3. Bit by bit read '1', write '0', read '0', write '1', in ascending order. 1.4. Bit by bit read '1', write '0', in ascending order. 1.5. Bit by bit read '0', write '1', read '1', write '0', in ascending order. 1.6. Read '0' from entire memory, in ascending order. The specific implementation used as a run time which depends on the CPU clock frequency and the number of bytes tested in the RAM. The detected faults are: – Address decoder faults – Stuck-at faults – Transition faults – Coupling faults – Linked Coupling faults 2. Starting MBIST To test a memory, you need to write the start address of the memory to the ADDR.ADDR bit field, and the size of the memory into the Length register. For best test coverage, an entire physical memory block should be tested at once. It is possible to test only a subset of a memory, but the test coverage will then be somewhat lower. The actual test is started by writing a '1' to CTRL.MBIST. A running MBIST operation can be canceled by writing a '1' to CTRL.SWRST. 3. Interpreting the Results The tester should monitor the STATUSA register. When the operation is completed, STATUSA.DONE is set. There are two different modes: – ADDR.AMOD=0: exit-on-error (default) SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 76

In this mode, the algorithm terminates either when a fault is detected or on successful completion. In both cases, STATUSA.DONE is set. If an error was detected, STATUSA.FAIL will be set. User then can read the DATA and ADDR registers to locate the fault. – ADDR.AMOD=1: pause-on-error In this mode, the MBIST algorithm is paused when an error is detected. In such a situation, only STATUSA.FAIL is asserted. The state machine waits for user to clear STATUSA.FAIL by writing a '1' in STATUSA.FAIL to resume. Prior to resuming, user can read the DATA and ADDR registers to locate the fault. 4. Locating Faults If the test stops with STATUSA.FAIL set, one or more bits failed the test. The test stops at the first detected error. The position of the failing bit can be found by reading the following registers: – ADDR: Address of the word containing the failing bit – DATA: contains data to identify which bit failed, and during which phase of the test it failed. The DATA register will in this case contains the following bit groups: Figure 13-6. DATA bits Description When MBIST Operation Returns an Error Bit Bit Bit Bit phase bit_index 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

bit_index: contains the bit number of the failing bit
phase: indicates which phase of the test failed and the cause of the error, as listed in the following table. Table 13-4. MBIST Operation Phases Phase Test actions 0 Write all bits to zero. This phase cannot fail.

1 Read '0', write '1', increment address

2 Read '1', write '0'

3 Read '0', write '1', decrement address

4 Read '1', write '0', decrement address

5 Read '0', write '1'

6 Read '1', write '0', decrement address

7 Read all zeros. bit_index is not used Table 13-5. AMOD Bit Descriptions for MBIST AMOD[1:0] Description 0x0 Exit on Error 0x1 Pause on Error SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 77

AMOD[1:0] Description 0x2, 0x3 Reserved Related Links 22. Nonvolatile Memory Controller (NVMCTRL)

Product Mapping

External access: Access performed in the DSU address offset 0x200-0x1FFF range. Internal access: Access performed in the DSU address offset 0x000-0x100 range. Table 13-6. Available Features when Operated From The External Address Range and Device is Protected Features Availability From The External Address Range and Device is Protected Chip-Erase command and status Yes CRC32 Yes, only full array or full RWWEE Emulation CoreSight Compliant Device identification Yes Debug communication channels Yes Testing of onboard memories (MBIST) No STATUSA.CRSTEXT clearing No (STATUSA.PERR is set when attempting to do so) SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 78

13.12 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRL 7:0 CE MBIST CRC SWRST 0x01 STATUSA 7:0 PERR FAIL BERR CRSTEXT DONE 0x02 STATUSB 7:0 HPE DCCD1 DCCD0 DBGPRES PROT 0x03 Reserved 0x04 ADDR 7:0 ADDR[5:0] AMOD[1:0] 15:8 ADDR[13:6] 23:16 ADDR[21:14] 31:24 ADDR[29:22] 0x08 LENGTH 7:0 LENGTH[5:0] 15:8 LENGTH[13:6] 23:16 LENGTH[21:14] 31:24 LENGTH[29:22] 0x0C DATA 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] 0x10 DCC0 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] 0x14 DCC1 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] 0x18 DID 7:0 DEVSEL[7:0] 15:8 DIE[3:0] REVISION[3:0] 23:16 FAMILY[0] SERIES[5:0] 31:24 PROCESSOR[3:0] FAMILY[4:1] 0x1C ... 0x0FFF Reserved 0x1000 ENTRY0 7:0 FMT EPRES 15:8 ADDOFF[3:0] 23:16 ADDOFF[11:4] 31:24 ADDOFF[19:12] 0x1004 ENTRY1 7:0 FMT EPRES 15:8 ADDOFF[3:0] 23:16 ADDOFF[11:4] 31:24 ADDOFF[19:12] 0x1008 END 7:0 END[7:0] 15:8 END[15:8] 23:16 END[23:16] 31:24 END[31:24] 0x100C ... 0x1FCB Reserved 0x1FCC MEMTYPE 7:0 SMEMP 15:8 23:16 31:24 0x1FD0 PID4 7:0 FKBC[3:0] JEPCC[3:0] 15:8 23:16 31:24 SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 79

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x1FD4 ... 0x1FDF Reserved 0x1FE0 PID0 7:0 PARTNBL[7:0] 15:8 23:16 31:24 0x1FE4 PID1 7:0 JEPIDCL[3:0] PARTNBH[3:0] 15:8 23:16 31:24 0x1FE8 PID2 7:0 REVISION[3:0] JEPU JEPIDCH[2:0] 15:8 23:16 31:24 0x1FEC PID3 7:0 REVAND[3:0] CUSMOD[3:0] 15:8 23:16 31:24 0x1FF0 CID0 7:0 PREAMBLEB0[7:0] 15:8 23:16 31:24 0x1FF4 CID1 7:0 CCLASS[3:0] PREAMBLE[3:0] 15:8 23:16 31:24 0x1FF8 CID2 7:0 PREAMBLEB2[7:0] 15:8 23:16 31:24 0x1FFC CID3 7:0 PREAMBLEB3[7:0] 15:8 23:16 31:24

13.13 Register Description

13.13.1 Control

Name: CTRL Offset: 0x0000 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CE MBIST CRC SWRST Access W W W W Reset 0 0 0 0 Bit 4 – CE Chip-Erase Writing a '0' to this bit has no effect. Writing a '1' to this bit starts the Chip-Erase operation. Bit 3 – MBIST Memory Built-In Self-Test Writing a '0' to this bit has no effect. Writing a '1' to this bit starts the memory BIST algorithm. Bit 2 – CRC 32-bit Cyclic Redundancy Check Writing a '0' to this bit has no effect. Writing a '1' to this bit starts the cyclic redundancy check algorithm. Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets the module. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 81

13.13.2 Status A

Name: STATUSA Offset: 0x0001 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 PERR FAIL BERR CRSTEXT DONE Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 4 – PERR Protection Error Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Protection Error bit. This bit is set when a command that is not allowed in protected state is issued. Bit 3 – FAIL Failure Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Failure bit. This bit is set when a DSU operation failure is detected. Bit 2 – BERR Bus Error Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Bus Error bit. This bit is set when a bus error is detected. Bit 1 – CRSTEXT CPU Reset Phase Extension Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the CPU Reset Phase Extension bit. This bit is set when a debug adapter Cold-Plugging is detected, which extends the CPU reset phase. Bit 0 – DONE Done Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Done bit. This bit is set when a DSU operation is completed. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 82

13.13.3 Status B

Name: STATUSB Offset: 0x0002 Reset: 0x1X Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 HPE DCCD1 DCCD0 DBGPRES PROT Access R R R R R Reset 1 0 0 0 0 Bit 4 – HPE Hot-Plugging Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit has no effect. This bit is set when Hot-Plugging is enabled. This bit is cleared when Hot-Plugging is disabled. This is the case when the SWCLK function is changed. Only a power-reset or a external reset can set it again. Bits 2, 3 – DCCDx Debug Communication Channel x Dirty [x=1..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit has no effect. This bit is set when DCCx is written. This bit is cleared when DCCx is read. Bit 1 – DBGPRES Debugger Present Writing a '0' to this bit has no effect. Writing a '1' to this bit has no effect. This bit is set when a debugger probe is detected. This bit is never cleared. Bit 0 – PROT Protected Writing a '0' to this bit has no effect. Writing a '1' to this bit has no effect. This bit is set at power-up when the device is protected. This bit is never cleared. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 83

13.13.4 Address

Name: ADDR Offset: 0x0004 Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 ADDR[29:22] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 ADDR[21:14] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ADDR[13:6] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[5:0] AMOD[1:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:2 – ADDR[29:0] Address Initial word start address needed for memory operations. Bits 1:0 – AMOD[1:0] Access Mode The functionality of these bits is dependent on the operation mode. Bit description when operating CRC32: refer to 13.11.3 32-bit Cyclic Redundancy Check CRC32 Bit description when testing onboard memories (MBIST): refer to 13.11.5 Testing of On-Board Memories MBIST SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 84

13.13.5 Length

Name: LENGTH Offset: 0x0008 Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 LENGTH[29:22] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 LENGTH[21:14] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 LENGTH[13:6] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LENGTH[5:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bits 31:2 – LENGTH[29:0] Length Length in words needed for memory operations. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 85

13.13.6 Data

Name: DATA Offset: 0x000C Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 DATA[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DATA[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DATA[31:0] Data Memory operation initial value or result value. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 86

13.13.7 Debug Communication Channel 0

Name: DCC0 Offset: 0x0010 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 DATA[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DATA[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DATA[31:0] Data Data register. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 87

13.13.8 Debug Communication Channel 1

Name: DCC1 Offset: 0x0014 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 DATA[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DATA[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DATA[31:0] Data Data register. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 88

13.13.9 Device Identification

Name: DID Offset: 0x0018 Property: PAC Write Protection The information in this register is related to the Ordering Information. Bit 31 30 29 28 27 26 25 24 PROCESSOR[3:0] FAMILY[4:1] Access R R R R R R R R Reset p p p p f f f f Bit 23 22 21 20 19 18 17 16 FAMILY[0] SERIES[5:0] Access R R R R R R R Reset f s s s s s s Bit 15 14 13 12 11 10 9 8 DIE[3:0] REVISION[3:0] Access R R R R R R R R Reset d d d d r r r r Bit 7 6 5 4 3 2 1 0 DEVSEL[7:0] Access R R R R R R R R Reset x x x x x x x x Bits 31:28 – PROCESSOR[3:0] Processor The value of this field defines the processor used on the device. For this device, the value of this field is 0x1, corresponding to the ARM Cortex-M0+ processor. Bits 27:23 – FAMILY[4:0] Product Family The value of this field corresponds to the product family part of the ordering code. For this device, the value of this field is 0x0, corresponding to the SAM D family of base line microcontrollers. Bits 21:16 – SERIES[5:0] Product Series The value of this field corresponds to the product series part of the ordering code. For this device, the value of this field is 0x01, corresponding to a product with the Cortex-M0+ processor with DMA and USB features. Bits 15:12 – DIE[3:0] Die Number Identifies the die family. Bits 11:8 – REVISION[3:0] Revision Number Identifies the die revision number. Refer the product family silicon errata and data sheet clarification document for further information. Note: The device variant (last letter of the ordering number) is independent of the die revision (DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks evolution of the die. Bits 7:0 – DEVSEL[7:0] Device Selection This bit field identifies a device within a product family and product series. The value corresponds to the Flash memory density, pin count and device variant parts of the ordering code. The Family Silicon Device Identification table in the “SAM D21/DA1 Family Silicon Errata” document provides the link between DEVSEL and part number. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 89

13.13.10 CoreSight ROM Table Entry 0

Name: ENTRY0 Offset: 0x1000 Reset: 0xXXXXX00X Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 ADDOFF[19:12] Access R R R R R R R R Reset x x x x x x x x Bit 23 22 21 20 19 18 17 16 ADDOFF[11:4] Access R R R R R R R R Reset x x x x x x x x Bit 15 14 13 12 11 10 9 8 ADDOFF[3:0] Access R R R R Reset x x x x Bit 7 6 5 4 3 2 1 0 FMT EPRES Access R R Reset 1 x Bits 31:12 – ADDOFF[19:0] Address Offset The base address of the component, relative to the base address of this ROM table. Bit 1 – FMT Format Always reads as '1', indicating a 32-bit ROM table. Bit 0 – EPRES Entry Present This bit indicates whether an entry is present at this location in the ROM table. This bit is set at power-up if the device is not protected indicating that the entry is not present. This bit is cleared at power-up if the device is not protected indicating that the entry is present. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 90

13.13.11 CoreSight ROM Table Entry 1

Name: ENTRY1 Offset: 0x1004 Reset: 0xXXXXX00X Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 ADDOFF[19:12] Access R R R R R R R R Reset x x x x x x x x Bit 23 22 21 20 19 18 17 16 ADDOFF[11:4] Access R R R R R R R R Reset x x x x x x x x Bit 15 14 13 12 11 10 9 8 ADDOFF[3:0] Access R R R R Reset x x x x Bit 7 6 5 4 3 2 1 0 FMT EPRES Access R R Reset 1 x Bits 31:12 – ADDOFF[19:0] Address Offset The base address of the component, relative to the base address of this ROM table. Bit 1 – FMT Format Always read as '1', indicating a 32-bit ROM table. Bit 0 – EPRES Entry Present This bit indicates whether an entry is present at this location in the ROM table. This bit is set at power-up if the device is not protected indicating that the entry is not present. This bit is cleared at power-up if the device is not protected indicating that the entry is present. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 91

13.13.12 CoreSight ROM Table End

Name: END Offset: 0x1008 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 END[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 END[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 END[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 END[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – END[31:0] End Marker Indicates the end of the CoreSight ROM table entries. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 92

13.13.13 CoreSight ROM Table Memory Type

Name: MEMTYPE Offset: 0x1FCC Reset: 0x0000000x Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 SMEMP Access R Reset x Bit 0 – SMEMP System Memory Present This bit indicates whether system memory is present on the bus that connects to the ROM table. This bit is set at power-up if the device is not protected, indicating that the system memory is accessible from a debug adapter. This bit is cleared at power-up if the device is protected, indicating that the system memory is not accessible from a debug adapter. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 93

13.13.14 Peripheral Identification 4

Name: PID4 Offset: 0x1FD0 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 FKBC[3:0] JEPCC[3:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:4 – FKBC[3:0] 4KB Count These bits will always return zero when read, indicating that this debug component occupies one 4KB block. Bits 3:0 – JEPCC[3:0] JEP-106 Continuation Code These bits will always return zero when read. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 94

13.13.15 Peripheral Identification 0

Name: PID0 Offset: 0x1FE0 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PARTNBL[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:0 – PARTNBL[7:0] Part Number Low These bits will always return 0xD0 when read, indicating that this device implements a DSU module instance. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 95

13.13.16 Peripheral Identification 1

Name: PID1 Offset: 0x1FE4 Reset: 0x000000FC Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 JEPIDCL[3:0] PARTNBH[3:0] Access R R R R R R R R Reset 1 1 1 1 1 1 0 0 Bits 7:4 – JEPIDCL[3:0] Low part of the JEP-106 Identity Code These bits will always return 0xF when read (JEP-106 identity code is 0x1F). Bits 3:0 – PARTNBH[3:0] Part Number High These bits will always return 0xC when read, indicating that this device implements a DSU module instance. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 96

13.13.17 Peripheral Identification 2

Name: PID2 Offset: 0x1FE8 Reset: 0x00000009 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 REVISION[3:0] JEPU JEPIDCH[2:0] Access R R R R R R R R Reset 0 0 0 0 1 0 0 1 Bits 7:4 – REVISION[3:0] Revision Number Revision of the peripheral. Starts at 0x0 and increments by one at both major and minor revisions. Bit 3 – JEPU JEP-106 Identity Code is used This bit will always return one when read, indicating that JEP-106 code is used. Bits 2:0 – JEPIDCH[2:0] JEP-106 Identity Code High These bits will always return 0x1 when read, (JEP-106 identity code is 0x1F). SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 97

13.13.18 Peripheral Identification 3

Name: PID3 Offset: 0x1FEC Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 REVAND[3:0] CUSMOD[3:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:4 – REVAND[3:0] Revision Number These bits will always return 0x0 when read. Bits 3:0 – CUSMOD[3:0] ARM CUSMOD These bits will always return 0x0 when read. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 98

13.13.19 Component Identification 0

Name: CID0 Offset: 0x1FF0 Reset: 0x0000000D Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PREAMBLEB0[7:0] Access R R R R R R R R Reset 0 0 0 0 1 1 0 1 Bits 7:0 – PREAMBLEB0[7:0] Preamble Byte 0 These bits will always return 0x0000000D when read. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 99

13.13.20 Component Identification 1

Name: CID1 Offset: 0x1FF4 Reset: 0x00000010 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CCLASS[3:0] PREAMBLE[3:0] Access R R R R R R R R Reset 0 0 0 1 0 0 0 0 Bits 7:4 – CCLASS[3:0] Component Class These bits will always return 0x1 when read indicating that this ARM CoreSight component is ROM table (refer to the ARM Debug Interface v5 Architecture Specification at http://www.arm.com). Bits 3:0 – PREAMBLE[3:0] Preamble These bits will always return 0x00 when read. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 100

13.13.21 Component Identification 2

Name: CID2 Offset: 0x1FF8 Reset: 0x00000005 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PREAMBLEB2[7:0] Access R R R R R R R R Reset 0 0 0 0 0 1 0 1 Bits 7:0 – PREAMBLEB2[7:0] Preamble Byte 2 These bits will always return 0x00000005 when read. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 101

13.13.22 Component Identification 3

Name: CID3 Offset: 0x1FFC Reset: 0x000000B1 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PREAMBLEB3[7:0] Access R R R R R R R R Reset 1 0 1 1 0 0 0 1 Bits 7:0 – PREAMBLEB3[7:0] Preamble Byte 3 These bits will always return 0x000000B1 when read. SAM D21/DA1 Family DSU - Device Service Unit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 102

Clock System This chapter summarizes the clock distribution and terminology in the SAM D21 device. It will not explain every detail of its configuration. For in-depth documentation, see the respective peripherals descriptions and the Generic Clock documentation. Related Links 15. GCLK - Generic Clock Controller

14.1 Clock Distribution

Figure 14-1. Clock distribution GCLK Generator 0 SYSCTRL GCLK GCLK Generator 1 GCLK Generator x GCLK Multiplexer 0 (DFLL48M Reference) GCLK Multiplexer 1 GCLK Multiplexer y Peripheral z Peripheral 0 Synchronous Clock Controller PM AHB/APB System Clocks GCLK_MAIN OSC8M OSC32K OSCULP32K XOSC32K DFLL48M XOSC Generic Clocks FDPLL96M The clock system on the SAM D21 consists of:

Clock sources, controlled by SYSCTRL – A clock source provides a time base that is used by other components, such as Generic Clock Generators. Example clock sources are the internal 8MHz oscillator (OSC8M), External crystal oscillator (XOSC) and the Digital frequency locked loop (DFLL48M).
Generic Clock Controller (GCLK) which controls the clock distribution system, made up of:
Generic Clock Generators: These are programmable prescalers that can use any of the system clock sources as a time base. The Generic Clock Generator 0 generates the clock signal GCLK_MAIN, which is used by the Power Manager, which in turn generates synchronous clocks.
Generic Clocks: These are clock signals generated by Generic Clock Generators and output by the Generic Clock Multiplexer, and serve as clocks for the peripherals of the system. Multiple instances of a peripheral will typically have a separate Generic Clock for each instance. Generic Clock 0 serves as the clock source for the DFLL48M clock input (when multiplying another clock source).
Power Manager (PM)
The PM generates and controls the synchronous clocks on the system. This includes the CPU, bus clocks (APB, AHB) as well as the synchronous (to the CPU) user interfaces of the peripherals. It contains clock masks that can turn on/off the user interface of a peripheral as well as prescalers for the CPU and bus clocks. The next figure shows an example where SERCOM0 is clocked by the DFLL48M in open loop mode. The DFLL48M is enabled, the Generic Clock Generator 1 uses the DFLL48M as its clock source and feeds into Peripheral Channel 20. The Generic Clock 20, also called GCLK_SERCOM0_CORE, is connected to SERCOM0. The SERCOM0 interface, clocked by CLK_SERCOM0_APB, has been unmasked in the APBC Mask register in the PM. SAM D21/DA1 Family Clock System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 103

Figure 14-2. Example of SERCOM clock SYSCTRL DFLL48M Generic Clock Generator 1 Generic Clock Multiplexer 20 SERCOM 0 Synchronous Clock Controller PM CLK_SERCOM0_APB GCLK_SERCOM0_CORE GCLK

14.2 Synchronous and Asynchronous Clocks

As the CPU and the peripherals can be in different clock domains, i.e. they are clocked from different clock sources and/or with different clock speeds, some peripheral accesses by the CPU need to be synchronized. In this case the peripheral includes a SYNCBUSY status register that can be used to check if a sync operation is in progress. For a general description, see 14.3 Register Synchronization. Some peripherals have specific properties described in their individual sub-chapter “Synchronization”. In the datasheet, references to Synchronous Clocks are referring to the CPU and bus clocks, while asynchronous clocks are generated by the Generic Clock Controller (GCLK).

14.3 Register Synchronization

There are two different register synchronization schemes implemented on this device: common synchronizer register synchronization and distributed synchronizer register synchronization. The modules using a common synchronizer register synchronization are: GCLK, WDT, RTC, EIC, TC, ADC, AC and DAC. The modules adopting a distributed synchronizer register synchronization are: SERCOM USART, SERCOM SPI, SERCOM I2C, I2S, TCC, USB.

14.3.1 Common Synchronizer Register Synchronization

14.3.1.1 Overview

All peripherals are composed of one digital bus interface connected to the APB or AHB bus and running from a corresponding clock in the Main Clock domain, and one peripheral core running from the peripheral Generic Clock (GCLK). Communication between these clock domains must be synchronized. This mechanism is implemented in hardware, so the synchronization process takes place even if the peripheral generic clock is running from the same clock source and on the same frequency as the bus interface. All registers in the bus interface are accessible without synchronization. All registers in the peripheral core are synchronized when written. Some registers in the peripheral core are synchronized when read. Each individual register description will have the properties "Read-Synchronized" and/or "Write-Synchronized" if a register is synchronized. As shown in the figure below, the common synchronizer is used for all registers in one peripheral. Therefore, status register (STATUS) of each peripheral can be synchronized at a time. SAM D21/DA1 Family Clock System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 104

Figure 14-3. Synchronization Non Synced reg INTFLAG STATUS READREQ Write-Synced reg Write-Synced reg R/W-Synced reg Synchronizer Sync SYNCBUSY Synchronous Domain (CLK_APB) Asynchronous Domain (generic clock) Peripheral bus

14.3.1.2 Write-Synchronization

Write-Synchronization is triggered by writing to a register in the peripheral clock domain. The Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set when the write-synchronization starts and cleared when the write-synchronization is complete. Refer to 14.3.1.8 Synchronization Delay for details on the synchronization delay. When the write-synchronization is ongoing (STATUS.SYNCBUSY is one), any of the following actions will cause the peripheral bus to stall until the synchronization is complete:

Writing a generic clock peripheral core register
Reading a read-synchronized peripheral core register
Reading the register that is being written (and thus triggered the synchronization) Peripheral core registers without read-synchronization will remain static once they have been written and synchronized, and can be read while the synchronization is ongoing without causing the peripheral bus to stall. APB registers can also be read while the synchronization is ongoing without causing the peripheral bus to stall. SAM D21/DA1 Family Clock System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 105

14.3.1.3 Read-Synchronization

Reading a read-synchronized peripheral core register will cause the peripheral bus to stall immediately until the for details on the synchronization delay. Note that reading a read-synchronized peripheral core register while STATUS.SYNCBUSY is one will cause the peripheral bus to stall twice; first because of the ongoing synchronization, and then again because reading a read-synchronized core register will cause the peripheral bus to stall immediately.

14.3.1.4 Completion of synchronization

The user can either poll STATUS.SYNCBUSY or use the Synchronisation Ready interrupt (if available) to check when the synchronization is complete. It is also possible to perform the next read/write operation and wait, as this next operation will be started once the previous write/read operation is synchronized and/or complete.

14.3.1.5 Read Request

The read request functionality is only available to peripherals that have the Read Request register (READREQ) implemented. Refer to the register description of individual peripheral chapters for details. To avoid forcing the peripheral bus to stall when reading read-synchronized Peripheral Core registers, the read request mechanism can be used. Basic Read Request Writing a '1' to the Read Request bit in the Read Request register (READREQ.RREQ) will request read synchronization of the register specified in the Address bits in READREQ (READREQ.ADDR) and set STATUS.SYNCBUSY. When read synchronization is complete, STATUS.SYNCBUSY is cleared. The read- synchronized value is then available for reading without delay until READREQ.RREQ is written to '1' again. The address to use is the offset to the peripheral's base address of the register that should be synchronized. Continuous Read Request Writing a '1' to the Read Continuously bit in READREQ (READREQ.RCONT) will force continuous read synchronization of the register specified in READREQ.ADDR. The latest value is always available for reading without stalling the bus, as the synchronization mechanism is continuously synchronizing the given value. READREQ.RCONT prevents READREQ.RREQ from clearing automatically. For the continuous read mode, RREQ bit is required to be set once the RCONT bit is set. SYNCBUSY is set for the first synchronization, but not for the subsequent synchronizations. If another synchronization is attempted, that is by executing a write-operation of a Write-synchronized register), the read request will be stopped, and will have to be manually restarted. Note: The continuous read synchronization is paused in sleep modes where the generic clock is not running. This means that a new read request is required if the value is needed immediately after exiting sleep.

14.3.1.6 Enable Write-Synchronization

Writing to the Enable bit in the Control register (CTRL.ENABLE) will also trigger write-synchronization and set STATUS.SYNCBUSY. CTRL.ENABLE will read its new value immediately after being written. The Synchronisation Ready interrupt (if available) cannot be used for Enable write-synchronization. When the enable write-synchronization is ongoing (STATUS.SYNCBUSY is one), attempt to do any of the following will cause the peripheral bus to stall until the enable synchronization is complete:

Writing a peripheral core register
Writing an APB register
Reading a read-synchronized peripheral core register APB registers can be read while the enable write-synchronization is ongoing without causing the peripheral bus to stall.

14.3.1.7 Software Reset Write-Synchronization

Writing a '1' to the Software Reset bit in CTRL (CTRL.SWRST) will also trigger write-synchronization and set and STATUS.SYNCBUSY will be cleared by hardware when the peripheral has been reset. Writing a zero to the SAM D21/DA1 Family Clock System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 106

CTRL.SWRST bit has no effect. The Synchronisation Ready interrupt (if available) cannot be used for Software Reset write-synchronization. When the software reset is in progress (STATUS.SYNCBUSY and CTRL.SWRST are '1'), attempt to do any of the following will cause the peripheral bus to stall until the Software Reset synchronization and the reset is complete:

Writing a peripheral core register
Writing an APB register
Reading a read-synchronized register APB registers can be read while the software reset is being write-synchronized without causing the peripheral bus to stall.

14.3.1.8 Synchronization Delay

The synchronization will delay write and read accesses by a certain amount. This delay D is within the range of: 5 × P GCLK + 2 × P APB < D < 6 × P GCLK + 3 × P APB Where P GCLK is the period of the generic clock and P APB is the period of the peripheral bus clock. A normal peripheral bus register access duration is 2 × P APB .

14.3.2 Distributed Synchronizer Register Synchronization

14.3.2.1 Overview

All peripherals are composed of one digital bus interface connected to the APB or AHB bus and running from a corresponding clock in the Main Clock domain, and one peripheral core running from the peripheral Generic Clock (GCLK). Communication between these clock domains must be synchronized. This mechanism is implemented in hardware, so the synchronization process takes place even if the peripheral generic clock is running from the same clock source and on the same frequency as the bus interface. All registers in the bus interface are accessible without synchronization. All registers in the peripheral core are synchronized when written. Some registers in the peripheral core are synchronized when read. Registers that need synchronization has this denoted in each individual register description.

14.3.2.2 General Write synchronization

Write-Synchronization is triggered by writing to a register in the peripheral clock domain. The respective bit in the Synchronization Busy register (SYNCBUSY) will be set when the write-synchronization starts and cleared when the When write-synchronization is ongoing for a register, any subsequent write attempts to this register will be discarded, and an error will be reported. Example: REGA, REGB are 8-bit peripheral core registers. REGC is 16-bit peripheral core register. Offset Register 0x00 REGA 0x01 REGB 0x02 REGC 0x03 Synchronization is per register, so multiple registers can be synchronized in parallel. Consequently, after REGA (8-bit access) was written, REGB (8-bit access) can be written immediately without error. REGC (16-bit access) can be written without affecting REGA or REGB. If REGC is written to in two consecutive 8-bit accesses without waiting for synchronization, the second write attempt will be discarded and an error is generated. A 32-bit access to offset 0x00 will write all three registers. Note that REGA, REGB and REGC can be updated at different times because of independent write synchronization. SAM D21/DA1 Family Clock System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 107

14.3.2.3 General read synchronization

Read-synchronized registers are synchronized when the register value is updated. During synchronization the corresponding bit in SYNCBUSY will be set. Reading a read-synchronized register will return its value immediately and the corresponding bit in SYNCBUSY will not be set.

14.3.2.4 Completion of synchronization

In order to check if synchronization is complete, the user can either poll the relevant bits in SYNCBUSY or use the Synchronisation Ready interrupt (if available). The Synchronization Ready interrupt flag will be set when all ongoing synchronizations are complete, i.e. when all bits in SYNCBUSY are '0'.

14.3.2.5 Enable Write-Synchronization

Setting the Enable bit in a module's Control register (CTRL.ENABLE) will also trigger write-synchronization and set will be cleared by hardware when the operation is complete. The Synchronisation Ready interrupt (if available) cannot be used for Enable write-synchronization.

14.3.2.6 Software Reset Write-Synchronization

Setting the Software Reset bit in CTRLA (CTRLA.SWRST=1) will trigger write-synchronization and set and SYNCBUSY.SWRST will be cleared by hardware when the peripheral has been reset. Writing a '0' to the CTRL.SWRST bit has no effect. The Ready interrupt (if available) cannot be used for Software Reset write- synchronization.

14.3.2.7 Synchronization Delay

14.4 Enabling a Peripheral

In order to enable a peripheral that is clocked by a Generic Clock, the following parts of the system needs to be configured:

A running Clock Source.
A clock from the Generic Clock Generator must be configured to use one of the running Clock Sources, and the Generator must be enabled.
The Generic Clock Multiplexer that provides the Generic Clock signal to the peripheral must be configured to use a running Generic Clock Generator, and the Generic Clock must be enabled.
The user interface of the peripheral needs to be unmasked in the PM. If this is not done the peripheral registers will read all 0’s and any writing attempts to the peripheral will be discarded.

14.5 Disabling a Peripheral

When disabling a peripheral and if a pin change interrupt is enabled on pins driven by the respective peripheral, a wake condition may be generated. If this happen the interrupt flag will not be set. As a consequence the system will not be able to identify the wake source. To avoid this, the interrupt enable register of the peripheral must be cleared (or the Nested Vectored Interrupt Controller (NVIC) Enable for the peripheral must be cleared) before disabling the peripheral. SAM D21/DA1 Family Clock System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 108

14.6 On-demand, Clock Requests

Figure 14-4. Clock request routing DFLL48M Generic Clock Generator Clock request Generic Clock Multiplexer Clock request Peripheral Clock request ENABLE RUNSTDBY ONDEMAND CLKEN RUNSTDBY ENABLE RUNSTDBY GENEN All clock sources in the system can be run in an on-demand mode: the clock source is in a stopped state unless a peripheral is requesting the clock source. Clock requests propagate from the peripheral, via the GCLK, to the clock source. If one or more peripheral is using a clock source, the clock source will be started/kept running. As soon as the clock source is no longer needed and no peripheral has an active request, the clock source will be stopped until requested again. The clock request can reach the clock source only if the peripheral, the generic clock and the clock from the Generic Clock Generator in-between are enabled. The time taken from a clock request being asserted to the clock source being ready is dependent on the clock source startup time, clock source frequency as well as the divider used in the Generic Clock Generator. The total startup time Tstart from a clock request until the clock is available for the peripheral is between: Tstart_max = Clock source startup time + 2 × clock source periods + 2 × divided clock source periods Tstart_min = Clock source startup time + 1 × clock source period + 1 × divided clock source period The time between the last active clock request stopped and the clock is shut down, Tstop, is between: Tstop_min = 1 × divided clock source period + 1 × clock source period Tstop_max = 2 × divided clock source periods + 2 × clock source periods The On-Demand function can be disabled individually for each clock source by clearing the ONDEMAND bit located in each clock source controller. Consequently, the clock will always run whatever the clock request status is. This has the effect of removing the clock source startup time at the cost of power consumption. The clock request mechanism can be configured to work in standby mode by setting the RUNSDTBY bits of the modules, see Figure 14-4. 14.7 Power Consumption vs. Speed When targeting for either a low-power or a fast acting system, some considerations have to be taken into account due to the nature of the asynchronous clocking of the peripherals: If clocking a peripheral with a very low clock, the active power consumption of the peripheral will be lower. At the same time the synchronization to the synchronous (CPU) clock domain is dependent on the peripheral clock speed, and will take longer with a slower peripheral clock. This will cause worse response times and longer synchronization delays.

14.8 Clocks after Reset

On any reset the synchronous clocks start to their initial state:

OSC8M is enabled and divided by 8
Generic Generator 0 uses OSC8M as source and generates GCLK_MAIN
CPU and BUS clocks are undivided On a Power Reset, the GCLK module starts to its initial state:
All Generic Clock Generators are disabled except SAM D21/DA1 Family Clock System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 109

– Generator 0 is using OSC8M as source without division and generates GCLK_MAIN – Generator 2 uses OSCULP32K as source without division

All Generic Clocks are disabled except: – WDT Generic Clock uses the Generator 2 as source On a User Reset the GCLK module starts to its initial state, except for:
Generic Clocks that are write-locked , i.e., the according WRTLOCK is set to 1 prior to Reset or WDT Generic Clock if the WDT Always-On at power on bit set in the NVM User Row
Generic Clock is dedicated to the RTC if the RTC Generic Clock is enabled On any reset the clock sources are reset to their initial state except the 32KHz clock sources which are reset only by a power reset. SAM D21/DA1 Family Clock System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 110

GCLK - Generic Clock Controller

15.1 Overview

Depending on the application, peripherals may require specific clock frequencies to operate correctly. The Generic Clock controller GCLK provides nine Generic Clock Generators that can provide a wide range of clock frequencies. Generators can be set to use different external and internal oscillators as source. The clock of each Generator can be divided. The outputs from the Generators are used as sources for the Generic Clock Multiplexers, which provide the Generic Clock (GCLK_PERIPHERAL) to the peripheral modules, as shown in Generic Clock Controller Block Diagram. The number of Peripheral Clocks depends on how many peripherals the device has. Note: The Generator 0 is always the direct source of the GCLK_MAIN signal.

15.2 Features

Provides Generic Clocks
Wide frequency range
Clock source for the generator can be changed on the fly

15.3 Block Diagram

The generation of Peripheral Clock signals (GCLK_PERIPHERAL) and the Main Clock (GCLK_MAIN) can be seen in the figure below. Figure 15-1. Device Clocking Diagram Generic Clock Generator OSC8M OSC32K OSCULP32K XOSC32K SYSCTRL Clock Divider & Masker Clock Gate Generic Clock Multiplexer GCLK_PERIPHERAL PERIPHERALS GENERIC CLOCK CONTROLLER PMGCLK_MAIN DFLL48M XOSC GCLK_IO The GCLK block diagram is shown in the next figure. SAM D21/DA1 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 111

Figure 15-2. Generic Clock Controller Block Diagram(1) Generic Clock Generator 0 GCLK_IO[0] (I/O input) Clock Divider & Masker Clock Sources GCLKGEN[0] GCLK_IO[1] (I/O input) GCLKGEN[1] GCLK_IO[n] (I/O input) GCLKGEN[n] Clock Gate Generic Clock Multiplexer 0 GCLK_PERIPHERAL[0] Clock Gate Generic Clock Multiplexer 1 Clock Gate Generic Clock Multiplexer m GCLKGEN[n:0] GCLK_MAIN GCLK_IO[1] (I/O output) GCLK_IO[0] (I/O output) GCLK_IO[n] (I/O output) Generic Clock Generator 1 Clock Divider & Masker Generic Clock Generator n Clock Divider & Masker GCLK_PERIPHERAL[1] GCLK_PERIPHERAL[m] Note: 1. If GENCTRL.SRC=0x01(GCLKIN), the GCLK_IO is set as an input.

15.4 Signal Description

Table 15-1. Signal Description Signal Name Type Description GCLK_IO[7:0] Digital I/O Clock source for Generators when input Generic Clock signal when output Refer to PORT Function Multiplexing table in I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. Note: One signal can be mapped on several pins. Related Links 7. I/O Multiplexing and Considerations

15.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

15.5.1 I/O Lines

Using the GCLK I/O lines requires the I/O pins to be configured. Related Links 23. PORT - I/O Pin Controller

15.5.2 Power Management

The GCLK can operate in sleep modes, if required. Refer to the sleep mode description in the Power Manager (PM) section. SAM D21/DA1 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 112

PM – Power Manager

15.5.3 Clocks

The GCLK bus clock (CLK_GCLK_APB) can be enabled and disabled in the Power Manager, and the default state of CLK_GCLK_APB can be found in the Peripheral Clock Masking section of PM – Power Manager. Related Links 16. PM – Power Manager

15.5.4 DMA

Not applicable.

15.5.5 Interrupts

Not applicable.

15.5.6 Events

Not applicable.

15.5.7 Debug Operation

Not applicable.

15.5.8 Register Access Protection

All registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC). Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. Write-protection does not apply for accesses through an external debugger. Related Links

15.5.9 Analog Connections

Not applicable.

15.6 Functional Description

15.6.1 Principle of Operation

The GCLK module is comprised of eight Generic Clock Generators (Generators) sourcing m Generic Clock Multiplexers. A clock source selected as input to a Generator can either be used directly, or it can be prescaled in the Generator. A generator output is used as input to one or more the Generic Clock Multiplexers to provide a peripheral (GCLK_PERIPHERAL). A generic clock can act as the clock to one or several of peripherals.

15.6.2 Basic Operation

15.6.2.1 Initialization

Before a Generator is enabled, the corresponding clock source should be enabled. The Peripheral clock must be configured as outlined by the following steps: 1. The Generic Clock Generator division factor must be set by performing a single 32-bit write to the Generic Clock Generator Division register (GENDIV): – The Generic Clock Generator that will be selected as the source of the generic clock by setting the ID bit group (GENDIV.ID). SAM D21/DA1 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 113

– The division factor must be selected by the DIV bit group (GENDIV.DIV) Note: Refer to Generic Clock Generator Division register (GENDIV) for details. 2. The generic clock generator must be enabled by performing a single 32-bit write to the Generic Clock Generator Control register (GENCTRL): – The Generic Clock Generator will be selected as the source of the generic clock by the ID bit group (GENCTRL.ID) – The Generic Clock generator must be enabled (GENCTRL.GENEN=1) Note: Refer to Generic Clock Generator Control register (GENCTRL) for details. 3. The generic clock must be configured by performing a single 16-bit write to the Generic Clock Control register (CLKCTRL): – The Generic Clock that will be configured via the ID bit group (CLKCTRL.ID) – The Generic Clock Generator used as the source of the generic clock by writing the GEN bit group (CLKCTRL.GEN) Note: Refer to Generic Clock Control register (CLKCTRL) for details. Related Links

15.8.5 GENDIV

15.8.4 GENCTRL

15.8.3 CLKCTRL

15.6.2.2 Enabling, Disabling and Resetting

The GCLK module has no enable/disable bit to enable or disable the whole module. The GCLK is reset by setting the Software Reset bit in the Control register (CTRL.SWRST) to 1. All registers in the GCLK will be reset to their initial state, except for Generic Clocks Multiplexer and associated Generators that have

15.6.2.3 Generic Clock Generator

Each Generator (GCLK_GEN) can be set to run from one of eight different clock sources except GCLKGEN[1], which can be set to run from one of seven sources. GCLKGEN[1] is the only Generator that can be selected as source to other Generators but can not act as source to itself. Each generator GCLKGEN[x] can be connected to one specific pin GCLK_IO[x]. The GCLK_IO[x] can be set to act as source to GCLKGEN[x] or GCLK_IO[x] can be set up to output the clock generated by GCLKGEN[x]. The selected source can be divided. Each Generator can be enabled or disabled independently. Each GCLKGEN clock signal can then be used as clock source for Generic Clock Multiplexers. Each Generator output is allocated to one or several Peripherals. GCLKGEN[0], is used as GCLK_MAIN for the synchronous clock controller inside the Power Manager. Refer to PM-Power Manager for details on the synchronous clock generation. Figure 15-3. Generic Clock Generator Clock Sources GENCTRL.DIVSEL GENCTRL.GENEN GENDIV.DIVGENCTRL.SRC GCLKGENSRC GCLK_IO[x] GCLKGENSRC DIVIDER Clock Gate GCLKGEN[x] Related Links 16. PM – Power Manager SAM D21/DA1 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 114

15.6.2.4 Enabling a Generic Clock Generator

A Generator is enabled by setting the Generic Clock Generator Enable bit in the Generic Clock Generator Control register (GENCTRL.GENEN=1).

15.6.2.5 Disabling a Generic Clock Generator

A Generator is disabled by clearing GENCTRL.GENEN. When GENCTRL.GENEN=0, the GCLKGEN clock is disabled and clock gated.

15.6.2.6 Selecting a Clock Source for the Generic Clock Generator

Each Generator can individually select a clock source by setting the Source Select bit group in GENCTRL (GENCTRL.SRC). Changing from one clock source, for example A, to another clock source, B, can be done on the fly: If clock source B is not ready, the Generator will continue running with clock source A. As soon as clock source B is ready, however, the generic clock generator will switch to it. During the switching operation, the Generator holds clock requests to clock sources A and B and then releases the clock source A request when the switch is done. The available clock sources are device dependent (usually the crystal oscillators, RC oscillators, PLL and DFLL). Only GCLKGEN[1] can be used as a common source for all other generators except Generator 1. Note: Before switching the Generic Clock Generator 0 (GCLKGEN0) from a clock source A to another clock source B, enable the "ONDEMAND" feature of the clock source A to ensure a proper transition from clock source A to clock source B.

15.6.2.7 Changing Clock Frequency

The selected source (GENCLKSRC) for a Generator can be divided by writing a division value in the Division Factor bit group in the Generic Clock Generator Division register (GENDIV.DIV). How the actual division factor is calculated is depending on the Divide Selection bit in GENCTRL (GENCTRL.DIVSEL), it can be interpreted in two ways by the integer divider. Note: The number of DIV bits for each Generator is device dependent.

15.6.2.8 Duty Cycle

When dividing a clock with an odd division factor, the duty-cycle will not be 50/50. Writing the Improve Duty Cycle bit in GENCTRL (GENCTRL.IDC=1) will result in a 50/50 duty cycle.

15.6.2.9 Generic Clock Output on I/O Pins

Each Generator's output can be directed to a GCLK_IO pin. If the Output Enable bit in GENCTRL is '1' (GENCTRL.OE=1) and the Generator is enabled (GENCTRL.GENEN=1), the Generator requests its clock source and the GCLKGEN clock is output to a GCLK_IO pin. If GENCTRL.OE=0, GCLK_IO is set according to the Output Off Value bit. If the Output Off Value bit in GENCTRL (GENCTRL.OOV) is zero, the output clock will be low when generic clock generator is turned off. If GENCTRL.OOV=1, the output clock will be high when Generator is turned off. In standby mode, if the clock is output (GENCTRL.OE=1), the clock on the GCLK_IO pin is frozen to the OOV value if the Run In Standby bit in GENCTRL (GENCTRL.RUNSTDBY) is zero. If GENCTRL.RUNSTDBY=1, the GCLKGEN clock is kept running and output to GCLK_IO. SAM D21/DA1 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 115

15.6.3 Generic Clock

Figure 15-4. Generic Clock Multiplexer Clock Gate GCLK_PERIPHERAL CLKCTRL.GEN CLKCTRL.CLKEN GCLKGEN[0] GCLKGEN[1] GCLKGEN[2] GCLKGEN[n]

15.6.3.1 Enabling a Generic Clock

Before a generic clock is enabled, one of the Generators must be selected as the source for the generic clock by writing to CLKCTRL.GEN. The clock source selection is individually set for each generic clock. When a Generator has been selected, the generic clock is enabled by setting the Clock Enable bit in CLKCTRL (CLKCTRL.CLKEN=1). The CLKCTRL.CLKEN bit must be synchronized to the generic clock domain. CLKCTRL.CLKEN will continue to read as its previous state until the synchronization is complete.

15.6.3.2 Disabling a Generic Clock

A generic clock is disabled by writing CLKCTRL.CLKEN=0. The SYNCBUSY bit will be cleared when this write- synchronization is complete. CLKCTRL.CLKEN will stay in its previous state until the synchronization is complete. The generic clock is gated when disabled.

15.6.3.3 Selecting a Clock Source for the Generic Clock

When changing a generic clock source by writing to CLKCTRL.GEN, the generic clock must be disabled before being re-enabled with the new clock source setting. This prevents glitches during the transition: 1. Write CLKCTRL.CLKEN=0 2. Assert that CLKCTRL.CLKEN reads '0' 3. Change the source of the generic clock by writing CLKCTRL.GEN 4. Re-enable the generic clock by writing CLKCTRL.CLKEN=1

15.6.3.4 Configuration Lock

The generic clock configuration can be locked for further write accesses by setting the Write Lock bit in the CLKCTRL register (CLKCTRL.WRTLOCK). All writes to the CLKCTRL register will be ignored. It can only be unlocked by a Power Reset. The Generator source of a locked generic clock are also locked, too: The corresponding GENCTRL and GENDIV are locked, and can be unlocked only by a Power Reset. There is one exception concerning the GCLKGEN[0]. As it is used as GCLK_MAIN, it can not be locked. It is reset by any Reset and will start up in a known configuration. The software reset (CTRL.SWRST) can not unlock the registers.

15.6.4 Additional Features

15.6.4.1 Indirect Access

The Generic Clock Generator Control and Division registers (GENCTRL and GENDIV) and the Generic Clock Control register (CLKCTRL) are indirectly addressed as shown in the next figure. SAM D21/DA1 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 116

Figure 15-5. GCLK Indirect Access GENCTRL GENDIV CLKCTRL GENCTRL.ID=i GENDIV.ID=i CLKCTRL.ID=j User Interface GENCTRL GENDIV Generic Clock Generator [i] CLKCTRL Generic Clock[j] Writing these registers is done by setting the corresponding ID bit group. To read a register, the user must write the ID of the channel, i, in the corresponding register. The value of the register for the corresponding ID is available in the user interface by a read access. For example, the sequence to read the GENCTRL register of generic clock generator i is: 1. Do an 8-bit write of the i value to GENCTRL.ID 2. Read the value of GENCTRL

15.6.4.2 Generic Clock Enable after Reset

The Generic Clock Controller must be able to provide a generic clock to some specific peripherals after a reset. That means that the configuration of the Generators and generic clocks after Reset is device-dependent. Refer to GENCTRL.ID for details on GENCTRL reset. Refer to GENDIV.ID for details on GENDIV reset. Refer to CLKCTRL.ID for details on CLKCTRL reset. Related Links

15.6.5 Sleep Mode Operation

15.6.5.1 Sleep Walking

The GCLK module supports the Sleep Walking feature. If the system is in a sleep mode where the Generic Clocks are stopped, a peripheral that needs its clock in order to execute a process must request it from the Generic Clock Controller. The Generic Clock Controller receives this request, determines which Generic Clock Generator is involved and which clock source needs to be awakened. It then wakes up the respective clock source, enables the Generator and generic clock stages successively, and delivers the clock to the peripheral.

15.6.5.2 Run in Standby Mode

In standby mode, the GCLK can continuously output the generator output to GCLK_IO. When set, the GCLK can continuously output the generator output to GCLK_IO. Refer to 15.6.2.9 Generic Clock Output on I/O Pins for details.

15.6.6 Synchronization

If an operation that requires synchronization is executed while STATUS.SYNCBUSY=1, the bus will be stalled. All operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is stalled. The following registers are synchronized when written:

Generic Clock Generator Control register (GENCTRL)
Generic Clock Generator Division register (GENDIV)
Control register (CTRL) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Related Links

15.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRL 7:0 SWRST 0x01 STATUS 7:0 SYNCBUSY 0x02 CLKCTRL 7:0 ID[5:0] 15:8 WRTLOCK CLKEN GEN[3:0] 0x04 GENCTRL 7:0 ID[3:0] 15:8 SRC[4:0] 23:16 RUNSTDBY DIVSEL OE OOV IDC GENEN 31:24 0x08 GENDIV 7:0 ID[3:0] 15:8 DIV[7:0] 23:16 DIV[15:8] 31:24

15.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read- Synchronized" and/or "Write-Synchronized" property in each individual register description. Refer to 15.5.8 Register Access Protection for details. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. Refer to 15.6.6 Synchronization for details. SAM D21/DA1 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 119

15.8.1 Control

Name: CTRL Offset: 0x0 Reset: 0x00 Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 3 2 1 0 SWRST Access R/W Reset 0 Bit 0 – SWRST Software Reset Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the GCLK to their initial state after a power reset, except for generic clocks and associated generators that have their WRTLOCK bit in CLKCTRL read as one. Refer to GENCTRL.ID for details on GENCTRL reset. Refer to GENDIV.ID for details on GENDIV reset. Refer to CLKCTRL.ID for details on CLKCTRL reset. Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete. Value Description 0 There is no reset operation ongoing. 1 There is a reset operation ongoing. SAM D21/DA1 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 120

15.8.2 Status

Name: STATUS Offset: 0x1 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 SYNCBUSY Access R Reset 0 Bit 7 – SYNCBUSY Synchronization Busy Status This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. SAM D21/DA1 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 121

15.8.3 Generic Clock Control

Name: CLKCTRL Offset: 0x2 Reset: 0x0000 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 WRTLOCK CLKEN GEN[3:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ID[5:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 15 – WRTLOCK Write Lock When this bit is written, it will lock from further writes the generic clock pointed to by CLKCTRL.ID, the generic clock generator pointed to in CLKCTRL.GEN and the division factor used in the generic clock generator. It can only be unlocked by a Power Reset. One exception to this is generic clock generator 0, which cannot be locked. Value Description

0 The generic clock and the associated generic clock generator and division factor are not locked

1 The generic clock and the associated generic clock generator and division factor are locked

Bit 14 – CLKEN Clock Enable This bit is used to enable and disable a generic clock. Value Description

0 The generic clock is disabled

1 The generic clock is enabled

Bits 11:8 – GEN[3:0] Generic Clock Generator These bits define the Generic Clock Generator which will be associated with the peripheral GCLK clock defined in the CLKCTRL.ID. Table 15-2. Generic Clock Generator GEN[3:0] Name Description 0x0 GCLKGEN0 Generic clock generator 0 0x1 GCLKGEN1 Generic clock generator 1 0x2 GCLKGEN2 Generic clock generator 2 0x3 GCLKGEN3 Generic clock generator 3 0x4 GCLKGEN4 Generic clock generator 4 0x5 GCLKGEN5 Generic clock generator 5 0x6 GCLKGEN6 Generic clock generator 6 0x7 GCLKGEN7 Generic clock generator 7 0x8 GCLKGEN8 Generic clock generator 8 0x9-0xF - Reserved Bits 5:0 – ID[5:0] Generic Clock Selection ID These bits select the peripheral GCLK clock which will be associated with the Generic Clock Generator defined in the CLKCTRL.GEN. The third table below provides the ID number for each possible peripheral GCLK clock.. A Power Reset will reset the CLKCTRL register for all IDs, including the RTC. If the WRTLOCK bit of the corresponding ID is zero and the ID is not the RTC, a user Reset will reset the CLKCTRL register for this ID. After a Power Reset, the Reset value of the CLKCTRL register versus module instance is as shown in the next table. SAM D21/DA1 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 122

Table 15-3. CLKCTRL Value after Power Reset for each Peripheral GCLK clock ID Module Instance Reset Value after Power Reset CLKCTRL.GEN CLKCTRL.CLKEN CLKCTRL.WRTLOCK RTC (ID = 0x04) 0x00 0x00 0x00 WDT (ID = 0x03) 0x02 0x01 if WDT Enable bit in NVM User Row written to one 0x00 if WDT Enable bit in NVM User Row written to zero 0x01 if WDT Always-On bit in NVM User Row written to one 0x00 if WDT Always-On bit in NVM User Row written to zero Others 0x00 0x00 0x00 After a user Reset, the Reset value of the CLKCTRL register versus module instance is as shown in the table below. Table 15-4. CLKCTRL Value after User Reset for each Peripheral GCLK clock ID Module Instance Reset Value after a User Reset CLKCTRL.GEN CLCTRL.CLKEN CLKCTRL.WRTLOCK RTC (ID = 0x04) 0x00 if WRTLOCK=0 and CLKEN=0 No change if WRTLOCK=1 or CLKEN=1 0x00 if WRTLOCK=0 and CLKEN=0 No change if WRTLOCK=1 or CLKEN=1 No change WDT (ID = 0x03) 0x02 if WRTLOCK=0 No change if WRTLOCK=1 If WRTLOCK=0 0x01 if WDT Enable bit in NVM User Row written to one 0x00 if WDT Enable bit in NVM User Row written to zero If WRTLOCK=1 no change No change Others 0x00 if WRTLOCK=0 No change if WRTLOCK=1 0x00 if WRTLOCK=0 No change if WRTLOCK=1 No change Value Name Description 0x00 GCLK_DFLL48M_REF DFLL48M Reference 0x01 GCLK_DPLL FDPLL96M input clock source for reference 0x02 GCLK_DPLL_32K FDPLL96M 32 kHz clock for FDPLL96M internal lock timer 0x03 GCLK_WDT WDT 0x04 GCLK_RTC RTC 0x05 GCLK_EIC EIC 0x06 GCLK_USB USB 0x07 GCLK_EVSYS_CHANNEL_0 EVSYS_CHANNEL_0 0x08 GCLK_EVSYS_CHANNEL_1 EVSYS_CHANNEL_1 0x09 GCLK_EVSYS_CHANNEL_2 EVSYS_CHANNEL_2 0x0A GCLK_EVSYS_CHANNEL_3 EVSYS_CHANNEL_3 0x0B GCLK_EVSYS_CHANNEL_4 EVSYS_CHANNEL_4 0x0C GCLK_EVSYS_CHANNEL_5 EVSYS_CHANNEL_5 0x0D GCLK_EVSYS_CHANNEL_6 EVSYS_CHANNEL_6 0x0E GCLK_EVSYS_CHANNEL_7 EVSYS_CHANNEL_7 0x0F GCLK_EVSYS_CHANNEL_8 EVSYS_CHANNEL_8 0x10 GCLK_EVSYS_CHANNEL_9 EVSYS_CHANNEL_9 0x11 GCLK_EVSYS_CHANNEL_10 EVSYS_CHANNEL_10 0x12 GCLK_EVSYS_CHANNEL_11 EVSYS_CHANNEL_11 0x13 GCLK_SERCOMx_SLOW SERCOMx_SLOW 0x14 GCLK_SERCOM0_CORE SERCOM0_CORE 0x15 GCLK_SERCOM1_CORE SERCOM1_CORE 0x16 GCLK_SERCOM2_CORE SERCOM2_CORE 0x17 GCLK_SERCOM3_CORE SERCOM3_CORE 0x18 GCLK_SERCOM4_CORE SERCOM4_CORE SAM D21/DA1 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 123

0x19 GCLK_SERCOM5_CORE SERCOM5_CORE 0x1A GCLK_TCC0, GCLK_TCC1 TCC0,TCC1 0x1B GCLK_TCC2, GCLK_TC3 TCC2,TC3 0x1C GCLK_TC4, GCLK_TC5 TC4,TC5 0x1D GCLK_TC6, GCLK_TC7 TC6,TC7 0x1E GCLK_ADC ADC 0x1F GCLK_AC_DIG, GCLK_AC1_DIG AC_DIG, AC1_DIG 0x20 GCLK_AC_ANA, GCLK_AC1_ANA AC_ANA, AC1_ANA 0x21 GCLK_DAC DAC 0x22 GCLK_PTC PTC 0x23 GCLK_I2S_0 I2S_0 0x24 GCLK_I2S_1 I2S_1 0x25 GCLK_TCC3 TCC3 0x26-0x3 F - Reserved SAM D21/DA1 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 124

15.8.4 Generic Clock Generator Control

Name: GENCTRL Offset: 0x4 Reset: 0x00000000 Property: Write-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 RUNSTDBY DIVSEL OE OOV IDC GENEN Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SRC[4:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ID[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 21 – RUNSTDBY Run in Standby This bit is used to keep the generic clock generator running when it is configured to be output to its dedicated GCLK_IO pin. If GENCTRL.OE is zero, this bit has no effect and the generic clock generator will only be running if a peripheral requires the clock. Value Description

0 The generic clock generator is stopped in standby and the GCLK_IO pin state (one or zero) will be

dependent on the setting in GENCTRL.OOV.

1 The generic clock generator is kept running and output to its dedicated GCLK_IO pin during standby

mode. Bit 20 – DIVSEL Divide Selection This bit is used to decide how the clock source used by the generic clock generator will be divided. If the clock source should not be divided, the DIVSEL bit must be zero and the GENDIV.DIV value for the corresponding generic clock generator must be zero or one. Value Description 0 The generic clock generator equals the clock source divided by GENDIV.DIV. 1 The generic clock generator equals the clock source divided by 2^(GENDIV.DIV+1). Bit 19 – OE Output Enable This bit is used to enable output of the generated clock to GCLK_IO when GCLK_IO is not selected as a source in the GENCLK.SRC bit group. Value Description 0 The generic clock generator is not output.

1 The generic clock generator is output to the corresponding GCLK_IO, unless the corresponding

GCLK_IO is selected as a source in the GENCLK.SRC bit group. Bit 18 – OOV Output Off Value This bit is used to control the value of GCLK_IO when GCLK_IO is not selected as a source in the GENCLK.SRC bit group. SAM D21/DA1 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 125

0 The GCLK_IO will be zero when the generic clock generator is turned off or when the OE bit is zero. 1 The GCLK_IO will be one when the generic clock generator is turned off or when the OE bit is zero. Bit 17 – IDC Improve Duty Cycle This bit is used to improve the duty cycle of the generic clock generator when odd division factors are used. Value Description 0 The generic clock generator duty cycle is not 50/50 for odd division factors. 1 The generic clock generator duty cycle is 50/50. Bit 16 – GENEN Generic Clock Generator Enable This bit is used to enable and disable the generic clock generator. Value Description 0 The generic clock generator is disabled. 1 The generic clock generator is enabled. Bits 12:8 – SRC[4:0] Source Select These bits define the clock source to be used as the source for the generic clock generator, as shown in the table below. Value Name Description 0x00 XOSC XOSC oscillator output 0x01 GCLKIN Generator input pad 0x02 GCLKGEN1 Generic clock generator 1 output 0x03 OSCULP32K OSCULP32K oscillator output 0x04 OSC32K OSC32K oscillator output 0x05 XOSC32K XOSC32K oscillator output 0x06 OSC8M OSC8M oscillator output 0x07 DFLL48M DFLL48M output 0x08 FDPLL96M FDPLL96M output 0x09-0x1 F Reserved Reserved for future use Bits 3:0 – ID[3:0] Generic Clock Generator Selection These bits select the generic clock generator that will be configured or read. The value of the ID bit group versus which generic clock generator is configured is shown in the next table. A power reset will reset the GENCTRL register for all IDs, including the generic clock generator used by the RTC. If a generic clock generator ID other than generic clock generator 0 is not a source of a “locked” generic clock or a source of the RTC generic clock, a user reset will reset the GENCTRL for this ID. After a power reset, the reset value of the GENCTRL register is as shown in the next table. GCLK Generator ID Reset Value after a Power Reset 0x00 0x00010600 0x01 0x00000001 0x02 0x00010302 0x03 0x00000003 0x04 0x00000004 0x05 0x00000005 0x06 0x00000006 0x07 0x00000007 0x08 0x00000008 After a user reset, the reset value of the GENCTRL register is as shown in the table below. GCLK Generator ID Reset Value after a User Reset 0x00 0x00010600 SAM D21/DA1 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 126

Reset Value after a User Reset 0x01 0x00000001 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x02 0x00010302 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x03 0x00000003 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x04 0x00000004 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x05 0x00000005 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x06 0x00000006 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x07 0x00000007 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x08 0x00000008 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one Value Name Description 0x0 GCLKGEN0 Generic clock generator 0 0x1 GCLKGEN1 Generic clock generator 1 0x2 GCLKGEN2 Generic clock generator 2 0x3 GCLKGEN3 Generic clock generator 3 0x4 GCLKGEN4 Generic clock generator 4 0x5 GCLKGEN5 Generic clock generator 5 0x6 GCLKGEN6 Generic clock generator 6 0x7 GCLKGEN7 Generic clock generator 7 0x8 GCLKGEN8 Generic clock generator 8 0x9-0xF Reserved SAM D21/DA1 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 127

15.8.5 Generic Clock Generator Division

Name: GENDIV Offset: 0x8 Reset: 0x00000000 Property: Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 DIV[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIV[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ID[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 23:8 – DIV[15:0] Division Factor These bits apply a division on each selected generic clock generator. The number of DIV bits each generator has can be seen in the next table. Writes to bits above the specified number will be ignored. Generator Division Factor Bits Maximum Division Factor Generic clock generator 0 8 division factor bits - DIV[7:0] 512 Generic clock generator 1 16 division factor bits - DIV[15:0] 131072 Generic clock generators 2 5 division factor bits - DIV[4:0] 64 Generic clock generators 3 - 8 8 division factor bits - DIV[7:0] 512 Bits 3:0 – ID[3:0] Generic Clock Generator Selection These bits select the generic clock generator on which the division factor will be applied, as shown in the table below. Values Description 0x0 Generic clock generator 0 0x1 Generic clock generator 1 0x2 Generic clock generator 2 0x3 Generic clock generator 3 0x4 Generic clock generator 4 0x5 Generic clock generator 5 0x6 Generic clock generator 6 0x7 Generic clock generator 7 0x8 Generic clock generator 8 0x9-0xF Reserved A Power Reset will reset the GENDIV register for all IDs, including the generic clock generator used by the RTC. If a generic clock generator ID other than generic clock generator 0 is not a source of a “locked” generic clock or a source of the RTC generic clock, a user Reset will reset the GENDIV register for this ID. After a Power Reset, the Reset value of the GENDIV register is as shown in the table below. SAM D21/DA1 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 128

GCLK Generator ID Reset Value after a Power Reset 0x00 0x00000000 0x01 0x00000001 0x02 0x00000002 0x03 0x00000003 0x04 0x00000004 0x05 0x00000005 0x06 0x00000006 0x07 0x00000007 0x08 0x00000008 After a user Reset, the Reset value of the GENDIV register is as shown in next table. GCLK Generator ID Reset Value after a User Reset 0x00 0x00000000 0x01 0x00000001 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x02 0x00000002 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x03 0x00000003 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x04 0x00000004 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x05 0x00000005 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x06 0x00000006 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x07 0x00000007 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x08 0x00000008 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one SAM D21/DA1 Family GCLK - Generic Clock Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 129

PM – Power Manager

16.1 Overview

The Power Manager (PM) controls the reset, clock generation and sleep modes of the device. Utilizing a main clock chosen from a large number of clock sources from the GCLK, the clock controller provides synchronous system clocks to the CPU and the modules connected to the AHB and the APBx bus. The synchronous system clocks are divided into a number of clock domains; one for the CPU and AHB and one for each APBx. Any synchronous system clock can be changed at run-time during normal operation. The clock domains can run at different speeds, enabling the user to save power by running peripherals at a relatively low clock frequency, while maintaining high CPU performance. In addition, the clock can be masked for individual modules, enabling the user to minimize power consumption. Before entering the Stand-by Sleep mode the user must make sure that a significant amount of clocks and peripherals are disabled, so that the voltage regulator is not overloaded. This is because during Stand-by Sleep mode the internal voltage regulator will be in Low-Power mode. Various sleep modes are provided in order to fit power consumption requirements. This enables the PM to stop unused modules in order to save power. In active mode, the CPU is executing application code. When the device enters a Sleep mode, program execution is stopped and some modules and clock domains are automatically switched off by the PM according to the Sleep mode. The application code decides which Sleep mode to enter and when. Interrupts from enabled peripherals and all enabled reset sources can restore the device from a Sleep mode to Active mode. The PM also contains a reset controller to collect all possible reset sources. It issues a device reset and sets the device to its initial state, and allows the reset source to be identified by software.

16.2 Features

Reset control – Reset the microcontroller and set it to an initial state according to the reset source – Multiple reset sources
Power reset sources: POR, BOD12, BOD33
User reset sources: External reset ( RESET), Watchdog Timer reset, software reset – Reset status register for reading the reset source from the application code
Clock control – Controls CPU, AHB and APB system clocks
Multiple clock sources and division factor from GCLK
Clock prescaler with 1x to 128x division – Safe run-time clock switching from GCLK – Module-level clock gating through maskable peripheral clocks
Power management control – Sleep modes: IDLE, STANDBY – SleepWalking support on GCLK clocks SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 130

16.3 Block Diagram

Figure 16-1. PM Block Diagram SYNCHRONOUS CLOCK CONTROLLER SLEEP MODE CONTROLLER RESET CONTROLLER CPU BOD12 BOD33 POR WDT GCLK RESET SOURCES PERIPHERALS RESET CLK_APB CLK_AHB CLK_CPU USER RESET POWER RESET POWER MANAGER CPU

16.4 Signal Description

Signal Name Type Description RESET Digital input External reset Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be mapped on several pins. Related Links 7. I/O Multiplexing and Considerations

16.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

16.5.1 I/O Lines

Not applicable.

16.5.2 Power Management

16.5.3 Clocks

The PM bus clock (CLK_PM_APB) can be enabled and disabled in the Power Manager, and the default state of CLK_PM_APB can be found in Peripheral Clock Default State table in the Peripheral Clock Masking section. If this clock is disabled in the Power Manager, it can only be re-enabled by a reset. A generic clock (GCLK_MAIN) is required to generate the main clock. The clock source for GCLK_MAIN is configured by default in the Generic Clock Controller, and can be reconfigured by the user if needed. Refer to GCLK – Generic Clock Controller for details. Related Links

16.6.2.6 Peripheral Clock Masking

GCLK - Generic Clock Controller

16.5.3.1 Main Clock

The main clock (CLK_MAIN) is the common source for the synchronous clocks. This is fed into the common 8-bit prescaler that is used to generate synchronous clocks to the CPU, AHB and APBx modules.

16.5.3.2 CPU Clock

The CPU clock (CLK_CPU) is routed to the CPU. Halting the CPU clock inhibits the CPU from executing instructions.

16.5.3.3 AHB Clock

The AHB clock (CLK_AHB) is the root clock source used by peripherals requiring an AHB clock. The AHB clock is always synchronous to the CPU clock and has the same frequency, but may run even when the CPU clock is turned off. A clock gate is inserted from the common AHB clock to any AHB clock of a peripheral.

16.5.3.4 APBx Clocks

The APBx clock (CLK_APBX) is the root clock source used by modules requiring a clock on the APBx bus. The APBx clock is always synchronous to the CPU clock, but can be divided by a prescaler, and will run even when the CPU clock is turned off. A clock gater is inserted from the common APB clock to any APBx clock of a module on APBx bus.

16.5.4 DMA

Not applicable.

16.5.5 Interrupts

The interrupt request line is connected to the Interrupt Controller. Using the PM interrupt requires the Interrupt Controller to be configured first. Refer to Nested Vector Interrupt Controller for details. Related Links

16.5.6 Events

Not applicable.

16.5.7 Debug Operation

When the CPU is halted in debug mode, the PM continues normal operation. In sleep mode, the clocks generated from the PM are kept running to allow the debugger accessing any modules. As a consequence, power measurements are not possible in debug mode.

16.5.8 Register Access Protection

Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following:

Interrupt Flag register (INTFLAG).
Reset Cause register (RCAUSE). Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. Write-protection does not apply for accesses through an external debugger. Refer to PAC – Peripheral Access Controller for details. SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 132

16.5.9 Analog Connections

Not applicable.

16.6 Functional Description

16.6.1 Principle of Operation

16.6.1.1 Synchronous Clocks

The GCLK_MAIN clock from GCLK module provides the source for the main clock, which is the common root for the synchronous clocks for the CPU and APBx modules. The main clock is divided by an 8-bit prescaler, and each of the derived clocks can run from any tapping off this prescaler or the undivided main clock, as long as fCPU ≥ fAPBx. The synchronous clock source can be changed on the fly to respond to varying load in the application. The clocks for each module in each synchronous clock domain can be individually masked to avoid power consumption in inactive modules. Depending on the sleep mode, some clock domains can be turned off (see Table 16-4).

16.6.1.2 Reset Controller

The Reset Controller collects the various reset sources and generates reset for the device. The device contains a Power-on-Reset (POR) detector, which keeps the system reset until power is stable. This eliminates the need for external reset circuitry to guarantee stable operation when powering up the device.

16.6.1.3 Sleep Mode Controller

In Active mode, all clock domains are active, allowing software execution and peripheral operation. The PM Sleep Mode Controller allows the user to choose between different sleep modes depending on application requirements, to save power (see Table 16-4).

16.6.2 Basic Operation

16.6.2.1 Initialization

After a Power-on Reset (POR), the PM is enabled and the Reset Cause register indicates the POR source (RCAUSE.POR). The default clock source of the GCLK_MAIN clock is started and calibrated before the CPU starts running. The GCLK_MAIN clock is selected as the main clock without any division on the prescaler. The device is in the Active mode. By default, only the necessary clocks are enabled (see Table 16-1).

16.6.2.2 Enabling, Disabling and Resetting

The PM module is always enabled and can not be reset.

16.6.2.3 Selecting the Main Clock Source

Refer to GCLK – Generic Clock Controller for details on how to configure the main clock source. Related Links 15. GCLK - Generic Clock Controller

16.6.2.4 Selecting the Synchronous Clock Division Ratio

The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By default, the synchronous clocks run on the undivided main clock. The user can select a prescaler division for the CPU clock by writing the CPU Prescaler Selection bits in the CPU Select register (CPUSEL.CPUDIV), resulting in a CPU clock frequency determined by this equation: f CPU = f main

2 CPUDIV

Similarly, the clock for the APBx can be divided by writing their respective registers (APBxSEL.APBxDIV). To ensure correct operation, frequencies must be selected so that fCPU ≥ fAPBx. Also, frequencies must never exceed the specified maximum frequency for each clock domain. SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 133

Note: The AHB clock is always equal to the CPU clock. CPUSEL and APBxSEL can be written without halting or disabling peripheral modules. Writing CPUSEL and APBxSEL allows a new clock setting to be written to all synchronous clocks at the same time. It is possible to keep one or more clocks unchanged. This way, it is possible to, for example, scale the CPU speed according to the required performance, while keeping the APBx frequency constant. Figure 16-2. Synchronous Clock Selection and Prescaler Clock gateClock gate Prescaler Sleep Controller Sleep mode CLK_AHB Clock gateClock gateCLK_APBA Clock gateClock gateCLK_APBC Clock gateClock gateCLK_APBB APBCDIV APBBDIV APBADIV CLK_PERIPHERAL_AHB_0 CLK_PERIPHERAL_AHB_1 CLK_PERIPHERAL_AHB_n CLK_PERIPHERAL_APBA_0 CLK_PERIPHERAL_APBA_1 CLK_PERIPHERAL_APBA_n CLK_PERIPHERAL_APBB_0 CLK_PERIPHERAL_APBB_1 CLK_PERIPHERAL_APBB_n CLK_PERIPHERAL_APBC_0 CLK_PERIPHERAL_APBC_1 CLK_PERIPHERAL_APBC_n APBCMASK APBBMASK APBAMASK CPUDIV AHBMASK CLK_CPU GCLK GCLK_MAIN Clock gate Clock gate Clock gate Clock gate Clock gate Clock gate Clock gate Clock gate Clock gate CLK_MAIN

16.6.2.5 Clock Ready Flag

There is a slight delay from when CPUSEL and APBxSEL are written until the new clock setting becomes effective. During this interval, the Clock Ready flag in the Interrupt Flag Status and Clear register (INTFLAG.CKRDY) will read as zero. If CKRDY in the INTENSET register is written to one, the Power Manager interrupt can be triggered when the new clock setting is effective. CPUSEL must not be re-written while CKRDY is zero, or the system may become unstable or hang. It is possible to disable or enable the clock for a peripheral in the AHB or APBx clock domain by writing the corresponding bit in the Clock Mask register (APBxMASK) to zero or one. Refer to the table below for the default state of each of the peripheral clocks. Table 16-1. Peripheral Clock Default State Peripheral Clock Default State CLK_PAC0_APB Enabled CLK_PM_APB Enabled CLK_SYSCTRL_APB Enabled CLK_GCLK_APB Enabled CLK_WDT_APB Enabled SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 134

Peripheral Clock Default State CLK_RTC_APB Enabled CLK_EIC_APB Enabled CLK_PAC1_APB Enabled CLK_DSU_APB Enabled CLK_NVMCTRL_APB Enabled CLK_PORT_APB Enabled CLK_HMATRIX_APB Enabled CLK_PAC2_APB Disabled CLK_SERCOMx_APB Disabled CLK_TCx_APB Disabled CLK_ADC_APB Enabled CLK_ACx_APB Disabled CLK_DAC_APB Disabled CLK_PTC_APB Disabled CLK_USB_APB Enabled CLK_DMAC_APB Enabled CLK_TCCx_APB Disabled CLK_I2S_APB Disabled When the APB clock for a module is not provided its registers cannot be read or written. The module can be re-enabled later by writing the corresponding mask bit to one. A module may be connected to several clock domains (for instance, AHB and APB), in which case it will have several mask bits. Note: Clocks should only be switched off if it is certain that the module will not be used. Switching off the clock for the NVM Controller (NVMCTRL) will cause a problem if the CPU needs to read from the flash memory. Switching off the clock to the Power Manager (PM), which contains the mask registers, or the corresponding APBx bridge, will make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset.

16.6.2.7 Reset Controller

The latest reset cause is available in RCAUSE, and can be read during the application boot sequence in order to determine proper action. There are two groups of reset sources:

Power Reset: Resets caused by an electrical issue.
User Reset: Resets caused by the application. The table below lists the parts of the device that are reset, depending on the reset type. SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 135

Table 16-2. Effects of the Different Reset Events Power Reset User Reset POR, BOD12, BOD33 External Reset WDT Reset, SysResetReq RTC All the 32kHz sources WDT with ALWAYSON feature Generic Clock with WRTLOCK feature Y N N Debug logic Y Y N Others Y Y Y The external reset is generated when pulling the RESET pin low. This pin has an internal pull-up, and does not need to be driven externally during normal operation. The POR, BOD12 and BOD33 reset sources are generated by their corresponding module in the System Controller Interface (SYSCTRL). The WDT reset is generated by the Watchdog Timer. The System Reset Request (SysResetReq) is a software reset generated by the CPU when asserting the SYSRESETREQ bit located in the Reset Control register of the CPU (See the ARM® Cortex® Technical Reference Manual on http://www.arm.com). Figure 16-3. Reset Controller RESET CONTROLLER BOD12 BOD33 POR WDT RESET RESET SOURCES RTC 32kHz clock sources WDT with ALWAYSON Generic Clock with WRTLOCK Debug Logic Others CPU RCAUSE

16.6.2.8 Sleep Mode Controller

Sleep mode is activated by the Wait For Interrupt instruction (WFI). The Idle bits in the Sleep Mode register (SLEEP.IDLE) and the SLEEPDEEP bit of the System Control register of the CPU should be used as argument to select the level of the sleep mode. There are two main types of sleep mode:

IDLE mode: The CPU is stopped. Optionally, some synchronous clock domains are stopped, depending on the IDLE argument. Regulator operates in normal mode. SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 136

STANDBY mode: All clock sources are stopped, except those where the RUNSTDBY bit is set. Regulator operates in low-power mode. Before entering standby mode the user must make sure that a significant amount of clocks and peripherals are disabled, so that the voltage regulator is not overloaded. Table 16-3. Sleep Mode Entry and Exit Table Mode Level Mode Entry Wake-Up Sources IDLE 0 SCR.SLEEPDEEP = 0 SLEEP.IDLE=Level WFI Synchronous(2) (APB, AHB), asynchronous(1)

1 Synchronous (APB), asynchronous

2 Asynchronous

STANDBY SCR.SLEEPDEEP = 1 WFI Asynchronous Notes: 1. Asynchronous: interrupt generated on generic clock or external clock or external event. 2. Synchronous: interrupt generated on the APB clock. Table 16-4. Sleep Mode Overview Sleep Mode CPU Clock AHB Clock APB Clock Oscillators Main Clock Regulator Mode RAM Mode ONDEMAND = 0 ONDEMAND = 1 RUNSTDBY=0 RUNSTDBY=1 RUNSTDBY=0 RUNSTDBY=1 Idle 0 Stop Run Run Run Run Run if requested Run if requested Run Normal Normal Idle 1 Stop Stop Run Run Run Run if requested Run if requested Run Normal Normal Idle 2 Stop Stop Stop Run Run Run if requested Run if requested Run Normal Normal Standby Stop Stop Stop Stop Run Stop Run if requested Stop Low power Low power

16.6.2.8.1 IDLE Mode

The IDLE modes allow power optimization with the fastest wake-up time. The CPU is stopped. To further reduce power consumption, the user can disable the clocking of modules and clock sources by configuring the SLEEP.IDLE bit group. The module will be halted regardless of the bit settings of the mask registers in the Power Manager (PM.AHBMASK, PM.APBxMASK). Regulator operates in normal mode.

Entering IDLE mode: The IDLE mode is entered by executing the WFI instruction. Additionally, if the SLEEPONEXIT bit in the ARM Cortex System Control register (SCR) is set, the IDLE mode will also be entered when the CPU exits the lowest priority ISR. This mechanism can be useful for applications that only require the processor to run when an interrupt occurs. Before entering the IDLE mode, the user must configure the IDLE mode configuration bit group and must write a zero to the SCR.SLEEPDEEP bit.
Exiting IDLE mode: The processor wakes the system up when it detects the occurrence of any interrupt that is not masked in the NVIC Controller with sufficient priority to cause exception entry. The system goes back to the ACTIVE mode. The CPU and affected modules are restarted.

16.6.2.8.2 STANDBY Mode

The STANDBY mode allows achieving very low-power consumption. In this mode, all clocks are stopped except those which are kept running if requested by a running module or have the ONDEMAND bit set to zero. For example, the RTC can operate in STANDBY mode. In this case, its generic clock clock source will also be enabled. The regulator and the RAM operate in Low-Power mode and the RAM content is retained. A SLEEPONEXIT feature is also available.

Entering STANDBY mode: This mode is entered by executing the WFI instruction with the SCR.SLEEPDEEP bit of the CPU is written to 1. SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 137

Exiting STANDBY mode: Any peripheral able to generate an asynchronous interrupt can wake-up the system. For example, a module running on a generic clock can trigger an interrupt. When the enabled asynchronous wake-up event occurs and the system is woken up, the device will either execute the Interrupt Service Routine or continue the normal program execution according to the Priority Mask Register (PRIMASK) configuration of the CPU.

16.6.3 SleepWalking

SleepWalking is the capability for a device to temporarily wake-up clocks for the peripheral to perform a task without waking-up the CPU in STANDBY sleep mode. At the end of the sleepwalking task, the device can either be awakened by an interrupt (from a peripheral involved in SleepWalking) or enter into STANDBY sleep mode again. In this device, SleepWalking is supported only on GCLK clocks by using the on-demand clock principle of the clock sources. Refer to On-demand, Clock Requests for more details. Related Links

16.6.4 DMA Operation

Not applicable.

16.6.5 Interrupts

The peripheral has the following interrupt sources:

Clock Ready flag Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the peripheral is reset. An interrupt flag is cleared by writing a one to the corresponding bit in the INTFLAG register. Each peripheral can have one interrupt request line per interrupt source or one common interrupt request line for all the interrupt sources. Refer to Nested Vector Interrupt Controller for details. If the peripheral has one common interrupt request line for all the interrupt sources, the user must read the INTFLAG register to determine which interrupt condition is present. Related Links

16.6.6 Events

Not applicable.

16.6.7 Sleep Mode Operation

In all IDLE sleep modes, the power manager is still running on the selected main clock. In STANDDBY sleep mode, the power manager is frozen and is able to go back to ACTIVE mode upon any asynchronous interrupt. SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 138

16.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRL 7:0 0x01 SLEEP 7:0 IDLE[1:0] 0x02 ... 0x07 Reserved 0x08 CPUSEL 7:0 CPUDIV[2:0] 0x09 APBASEL 7:0 APBADIV[2:0] 0x0A APBBSEL 7:0 APBBDIV[2:0] 0x0B APBCSEL 7:0 APBCDIV[2:0] 0x0C ... 0x13 Reserved 0x14 AHBMASK 7:0 USB DMAC NVMCTRL DSU HPB2 HPB1 HPB0 15:8 23:16 31:24 0x18 APBAMASK 7:0 EIC RTC WDT GCLK SYSCTRL PM PAC0 15:8 23:16 31:24 0x1C APBBMASK 7:0 USB DMAC PORT NVMCTRL DSU PAC1 15:8 23:16 31:24 0x20 APBCMASK 7:0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS PAC2 15:8 TC7 TC6 TC5 TC4 TC3 TCC2 TCC1 TCC0 23:16 AC1 I2S PTC DAC AC ADC 31:24 TCC3 0x24 ... 0x33 Reserved 0x34 INTENCLR 7:0 CKRDY 0x35 INTENSET 7:0 CKRDY 0x36 INTFLAG 7:0 CKRDY 0x37 Reserved 0x38 RCAUSE 7:0 SYST WDT EXT BOD33 BOD12 POR

16.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Exception for APBASEL, APBBSEL and APBCSEL: These registers must only be accessed with 8-bit access. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description. SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 139

16.8.1 Control

Name: CTRL Offset: 0x00 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 Access Reset SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 140

16.8.2 Sleep Mode

Name: SLEEP Offset: 0x01 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 IDLE[1:0] Access R/W R/W Reset 0 0 Bits 1:0 – IDLE[1:0] Idle Mode Configuration These bits select the Idle mode configuration after a WFI instruction. IDLE[1:0] Name Description 0x0 CPU The CPU clock domain is stopped 0x1 AHB The CPU and AHB clock domains are stopped 0x2 APB The CPU, AHB and APB clock domains are stopped 0x3 Reserved SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 141

16.8.3 CPU Clock Select

Name: CPUSEL Offset: 0x08 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 CPUDIV[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 2:0 – CPUDIV[2:0] CPU Prescaler Selection These bits define the division ratio of the main clock prescaler (2n). CPUDIV[2:0] Name Description 0x0 DIV1 Divide by 1 0x1 DIV2 Divide by 2 0x2 DIV4 Divide by 4 0x3 DIV8 Divide by 8 0x4 DIV16 Divide by 16 0x5 DIV32 Divide by 32 0x6 DIV64 Divide by 64 0x7 DIV128 Divide by 128 SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 142

16.8.4 APBA Clock Select

Name: APBASEL Offset: 0x09 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 APBADIV[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 2:0 – APBADIV[2:0] APBA Prescaler Selection These bits define the division ratio of the APBA clock prescaler (2n). APBADIV[2:0] Name Description 0x0 DIV1 Divide by 1 0x1 DIV2 Divide by 2 0x2 DIV4 Divide by 4 0x3 DIV8 Divide by 8 0x4 DIV16 Divide by 16 0x5 DIV32 Divide by 32 0x6 DIV64 Divide by 64 0x7 DIV128 Divide by 128 SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 143

16.8.5 APBB Clock Select

Name: APBBSEL Offset: 0x0A Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 APBBDIV[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 2:0 – APBBDIV[2:0] APBB Prescaler Selection These bits define the division ratio of the APBB clock prescaler (2n). APBBDIV[2:0] Name Description 0x0 DIV1 Divide by 1 0x1 DIV2 Divide by 2 0x2 DIV4 Divide by 4 0x3 DIV8 Divide by 8 0x4 DIV16 Divide by 16 0x5 DIV32 Divide by 32 0x6 DIV64 Divide by 64 0x7 DIV128 Divide by 128 SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 144

16.8.6 APBC Clock Select

Name: APBCSEL Offset: 0x0B Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 APBCDIV[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 2:0 – APBCDIV[2:0] APBC Prescaler Selection These bits define the division ratio of the APBC clock prescaler (2n). APBCDIV[2:0] Name Description 0x0 DIV1 Divide by 1 0x1 DIV2 Divide by 2 0x2 DIV4 Divide by 4 0x3 DIV8 Divide by 8 0x4 DIV16 Divide by 16 0x5 DIV32 Divide by 32 0x6 DIV64 Divide by 64 0x7 DIV128 Divide by 128 SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 145

16.8.7 AHB Mask

Name: AHBMASK Offset: 0x14 Reset: 0x0000007F Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 USB DMAC NVMCTRL DSU HPB2 HPB1 HPB0 Access R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 Bit 6 – USB USB AHB Clock Mask Value Description 0 The AHB clock for the USB is stopped. 1 The AHB clock for the USB is enabled. Bit 5 – DMAC DMAC AHB Clock Mask Value Description 0 The AHB clock for the DMAC is stopped. 1 The AHB clock for the DMAC is enabled. Bit 4 – NVMCTRL NVMCTRL AHB Clock Mask Value Description 0 The AHB clock for the NVMCTRL is stopped. 1 The AHB clock for the NVMCTRL is enabled. Bit 3 – DSU DSU AHB Clock Mask Value Description 0 The AHB clock for the DSU is stopped. 1 The AHB clock for the DSU is enabled. Bit 2 – HPB2 HPB2 AHB Clock Mask Value Description 0 The AHB clock for the HPB2 is stopped. 1 The AHB clock for the HPB2 is enabled. Bit 1 – HPB1 HPB1 AHB Clock Mask Value Description 0 The AHB clock for the HPB1 is stopped. 1 The AHB clock for the HPB1 is enabled. SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 146

Bit 0 – HPB0 HPB0 AHB Clock Mask Value Description 0 The AHB clock for the HPB0 is stopped. 1 The AHB clock for the HPB0 is enabled. SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 147

16.8.8 APBA Mask

Name: APBAMASK Offset: 0x18 Reset: 0x0000007F Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 EIC RTC WDT GCLK SYSCTRL PM PAC0 Access R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 Bit 6 – EIC EIC APB Clock Enable Value Description 0 The APBA clock for the EIC is stopped. 1 The APBA clock for the EIC is enabled. Bit 5 – RTC RTC APB Clock Enable Value Description 0 The APBA clock for the RTC is stopped. 1 The APBA clock for the RTC is enabled. Bit 4 – WDT WDT APB Clock Enable Value Description 0 The APBA clock for the WDT is stopped. 1 The APBA clock for the WDT is enabled. Bit 3 – GCLK GCLK APB Clock Enable Value Description 0 The APBA clock for the GCLK is stopped. 1 The APBA clock for the GCLK is enabled. Bit 2 – SYSCTRL SYSCTRL APB Clock Enable Value Description 0 The APBA clock for the SYSCTRL is stopped. 1 The APBA clock for the SYSCTRL is enabled. Bit 1 – PM PM APB Clock Enable Value Description 0 The APBA clock for the PM is stopped. 1 The APBA clock for the PM is enabled. SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 148

Bit 0 – PAC0 PAC0 APB Clock Enable Value Description 0 The APBA clock for the PAC0 is stopped. 1 The APBA clock for the PAC0 is enabled. SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 149

16.8.9 APBB Mask

Name: APBBMASK Offset: 0x1C Reset: 0x0000007F Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 USB DMAC PORT NVMCTRL DSU PAC1 Access R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 Bit 5 – USB USB APB Clock Enable Value Description 0 The APBB clock for the USB is stopped. 1 The APBB clock for the USB is enabled. Bit 4 – DMAC DMAC APB Clock Enable Value Description 0 The APBB clock for the DMAC is stopped. 1 The APBB clock for the DMAC is enabled. Bit 3 – PORT PORT APB Clock Enable Value Description 0 The APBB clock for the PORT is stopped. 1 The APBB clock for the PORT is enabled. Bit 2 – NVMCTRL NVMCTRL APB Clock Enable Value Description 0 The APBB clock for the NVMCTRL is stopped. 1 The APBB clock for the NVMCTRL is enabled. Bit 1 – DSU DSU APB Clock Enable Value Description 0 The APBB clock for the DSU is stopped. 1 The APBB clock for the DSU is enabled. Bit 0 – PAC1 PAC1 APB Clock Enable Value Description 0 The APBB clock for the PAC1 is stopped. 1 The APBB clock for the PAC1 is enabled. SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 150

16.8.10 APBC Mask

Name: APBCMASK Offset: 0x20 Reset: 0x00010000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 TCC3 Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 AC1 I2S PTC DAC AC ADC Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 1 Bit 15 14 13 12 11 10 9 8 TC7 TC6 TC5 TC4 TC3 TCC2 TCC1 TCC0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS PAC2 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 24 – TCC3 TCC2 APB Clock Enable Value Description

0 The APBC clock for the TCC3 is stopped

1 The APBC clock for the TCC3 is enabled

Bit 21 – AC1 AC1 APB Clock Enable Value Description

0 The APBC clock for the AC1 is stopped

1 The APBC clock for the AC1 is enabled

Bit 20 – I2S I2S APB Clock Enable Value Description

0 The APBC clock for the I2S is stopped

1 The APBC clock for the I2S is enabled

Bit 19 – PTC PTC APB Clock Enable Value Description

0 The APBC clock for the PTC is stopped

1 The APBC clock for the PTC is enabled

Bit 18 – DAC DAC APB Clock Enable Value Description

0 The APBC clock for the DAC is stopped

1 The APBC clock for the DAC is enabled

Bit 17 – AC AC APB Clock Enable Value Description

0 The APBC clock for the AC is stopped

1 The APBC clock for the AC is enabled

Bit 16 – ADC ADC APB Clock Enable Value Description

0 The APBC clock for the ADC is stopped

1 The APBC clock for the ADC is enabled

Bit 15 – TC7 TC7 APB Clock Enable Value Description

0 The APBC clock for the TC7 is stopped

1 The APBC clock for the TC7 is enabled

Bit 14 – TC6 TC6 APB Clock Enable Value Description

0 The APBC clock for the TC6 is stopped

1 The APBC clock for the TC6 is enabled

Bit 13 – TC5 TC5 APB Clock Enable Value Description

0 The APBC clock for the TC5 is stopped

1 The APBC clock for the TC5 is enabled

Bit 12 – TC4 TC4 APB Clock Enable Value Description

0 The APBC clock for the TC4 is stopped

1 The APBC clock for the TC4 is enabled

Bit 11 – TC3 TC3 APB Clock Enable Value Description

0 The APBC clock for the TC3 is stopped

1 The APBC clock for the TC3 is enabled

Bit 10 – TCC2 TCC2 APB Clock Enable Value Description

0 The APBC clock for the TCC2 is stopped

1 The APBC clock for the TCC2 is enabled

Bit 9 – TCC1 TCC1 APB Clock Enable Value Description

0 The APBC clock for the TCC1 is stopped

1 The APBC clock for the TCC1 is enabled

Bit 8 – TCC0 TCC0 APB Clock Enable Value Description

0 The APBC clock for the TCC0 is stopped

1 The APBC clock for the TCC0 is enabled

Bit 7 – SERCOM5 SERCOM5 APB Clock Enable Value Description

0 The APBC clock for the SERCOM5 is stopped

1 The APBC clock for the SERCOM5 is enabled

Bit 6 – SERCOM4 SERCOM4 APB Clock Enable Value Description

0 The APBC clock for the SERCOM4 is stopped

1 The APBC clock for the SERCOM4 is enabled

Bit 5 – SERCOM3 SERCOM3 APB Clock Enable Value Description

0 The APBC clock for the SERCOM3 is stopped

1 The APBC clock for the SERCOM3 is enabled

Bit 4 – SERCOM2 SERCOM2 APB Clock Enable Value Description

0 The APBC clock for the SERCOM2 is stopped

1 The APBC clock for the SERCOM2 is enabled

Bit 3 – SERCOM1 SERCOM1 APB Clock Enable Value Description

0 The APBC clock for the SERCOM1 is stopped

1 The APBC clock for the SERCOM1 is enabled

Bit 2 – SERCOM0 SERCOM0 APB Clock Enable Value Description

0 The APBC clock for the SERCOM0 is stopped

1 The APBC clock for the SERCOM0 is enabled

Bit 1 – EVSYS EVSYS APB Clock Enable Value Description

0 The APBC clock for the EVSYS is stopped

1 The APBC clock for the EVSYS is enabled

Bit 0 – PAC2 PAC2 APB Clock Enable Value Description

0 The APBC clock for the PAC2 is stopped

1 The APBC clock for the PAC2 is enabled

16.8.11 Interrupt Enable Clear

Name: INTENCLR Offset: 0x34 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 CKRDY Access R/W Reset 0 Bit 0 – CKRDY Clock Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the Clock Ready Interrupt Enable bit and the corresponding interrupt request. Value Description 0 The Clock Ready interrupt is disabled.

1 The Clock Ready interrupt is enabled and will generate an interrupt request when the Clock Ready

16.8.12 Interrupt Enable Set

Name: INTENSET Offset: 0x35 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 CKRDY Access R/W Reset 0 Bit 0 – CKRDY Clock Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the Clock Ready Interrupt Enable bit and enable the Clock Ready interrupt. Value Description 0 The Clock Ready interrupt is disabled. 1 The Clock Ready interrupt is enabled. SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 155

16.8.13 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x36 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 CKRDY Access R/W Reset 0 Bit 0 – CKRDY Clock Ready This flag is cleared by writing a one to the flag. This flag is set when the synchronous CPU and APBx clocks have frequencies as indicated in the CPUSEL and APBxSEL registers, and will generate an interrupt if INTENCLR/SET.CKRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Clock Ready Interrupt flag. SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 156

16.8.14 Reset Cause

Name: RCAUSE Offset: 0x38 Reset: 0x01 Property: - Bit 7 6 5 4 3 2 1 0 SYST WDT EXT BOD33 BOD12 POR Access R R R R R R Reset 0 0 0 0 0 1 Bit 6 – SYST System Reset Request This bit is set if a system reset request has been performed. Refer to the Cortex processor documentation for more details. Bit 5 – WDT Watchdog Reset This flag is set if a Watchdog Timer reset occurs. Bit 4 – EXT External Reset This flag is set if an external reset occurs. Bit 2 – BOD33 Brown Out 33 Detector Reset This flag is set if a BOD33 reset occurs. Bit 1 – BOD12 Brown Out 12 Detector Reset This flag is set if a BOD12 reset occurs. Bit 0 – POR Power On Reset This flag is set if a POR occurs. SAM D21/DA1 Family PM – Power Manager © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 157

SYSCTRL – System Controller

17.1 Overview

The System Controller (SYSCTRL) provides a user interface to the clock sources, brown out detectors, on-chip voltage regulator and voltage reference of the device. Through the interface registers, it is possible to enable, disable, calibrate and monitor the SYSCTRL sub-peripherals. All sub-peripheral statuses are collected in the Power and Clocks Status register (PCLKSR). They can additionally trigger interrupts upon status changes through the INTENSET (INTENSET), INTENCLR (INTENCLR) and INTFLAG (INTFLAG) registers. Additionally, BOD33 interrupts can be used to wake up the device from Stand-by mode upon a programmed brown- out detection.

17.2 Features

0.4-32 MHz Crystal Oscillator (XOSC) – Tunable gain control – Programmable start-up time – Crystal or external input clock on XIN I/O
32.768 kHz Crystal Oscillator (XOSC32K) – Automatic or manual gain control – Programmable start-up time – Crystal or external input clock on XIN32 I/O
32.768 kHz High Accuracy Internal Oscillator (OSC32K) – Frequency fine tuning – Programmable start-up time
32.768 kHz Ultra Low-Power Internal Oscillator (OSCULP32K) – Ultra low-power, always-on oscillator – Frequency fine tuning – Calibration value loaded from Flash Factory Calibration at Reset
8 MHz Internal Oscillator (OSC8M) – Fast start-up – Output frequency fine tuning – 4/2/1 MHz divided output frequencies available – Calibration value loaded from Flash Factory Calibration at Reset
Digital Frequency Locked Loop (DFLL48M) – Internal oscillator with no external components – 48 MHz output frequency – Operates standalone as a high-frequency programmable oscillator in Open-Loop mode – Operates as an accurate frequency multiplier against a known frequency in Closed-Loop mode
Fractional Digital Phase-Locked Loop (FDPLL96M) – 48 MHz to 96 MHz output clock frequency – 32 kHz to 2 MHz input reference clock frequency range – Three possible sources for the reference clock – Adjustable proportional integral controller – Fractional part used to achieve 1/16th of reference clock step
3.3V Brown-Out Detector (BOD33) – Programmable threshold SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 158

– Threshold value loaded from Flash User Calibration at start-up – Triggers Resets or interrupts – Hysteresis

Internal Voltage Regulator system (VREG) – Operating modes:
Normal mode
Low-power mode – With an internal non-configurable Brown-out Detector (BOD12)
Voltage Reference System (VREF) – Bandgap voltage generator with programmable calibration value – Temperature sensor – Bandgap calibration value loaded from Flash Factory Calibration at start-up

17.3 Block Diagram

Figure 17-1. SYSCTRL Block Diagram XOSC XOSC32K OSC32K OSCULP32K OSC8M DFLL48M VOLTAGE REFERENCE SYSTEM OSCILLATORS CONTROL POWER MONITOR CONTROL VOLTAGE REFERENCE CONTROL STATUS (PCLKSR register) INTERRUPTS GENERATOR BOD33 Interrupts SYSCTRL FDPLL96M

17.4 Signal Description

Signal Name Types Description XIN Analog Input Multipurpose Crystal Oscillator or external clock generator input XOUT Analog Output External Multipurpose Crystal Oscillator output XIN32 Analog Input 32kHz Crystal Oscillator or external clock generator input SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 159

Signal Name Types Description XOUT32 Analog Output 32kHz Crystal Oscillator output The I/O lines are automatically selected when XOSC or XOSC32K are enabled. Refer to Oscillator Pinout. Related Links 7. I/O Multiplexing and Considerations

17.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

17.5.1 I/O Lines

I/O lines are configured by SYSCTRL when either XOSC or XOSC32K are enabled, and need no user configuration.

17.5.2 Power Management

The SYSCTRL can continue to operate in any sleep mode where the selected source clock is running. The SYSCTRL interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes. Refer to PM – Power Manager on the different sleep modes. Related Links 16. PM – Power Manager

17.5.3 Clocks

The SYSCTRL gathers controls for all device oscillators and provides clock sources to the Generic Clock Controller (GCLK). The available clock sources are: XOSC, XOSC32K, OSC32K, OSCULP32K, OSC8M, DFLL48M and FDPLL96M. The SYSCTRL bus clock (CLK_SYSCTRL_APB) can be enabled and disabled in the Power Manager, and the default state of CLK_SYSCTRL_APB can be found in the Peripheral Clock Masking section in the PM – Power Manager. The clock used by BOD33 in Sampled mode is asynchronous to the user interface clock (CLK_SYSCTRL_APB). Likewise, the DFLL48M control logic uses the DFLL oscillator output, which is also asynchronous to the user interface clock (CLK_SYSCTRL_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to 17.6.14 Synchronization for further details. Related Links

17.5.4 Interrupts

The interrupt request line is connected to the Interrupt Controller. Using the SYSCTRL interrupts requires the Interrupt Controller to be configured first. Refer to Nested Vector Interrupt Controller for details. Related Links

17.5.5 Debug Operation

When the CPU is halted in debug mode, the SYSCTRL continues normal operation. If the SYSCTRL is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. If debugger cold-plugging is detected by the system, BOD33 reset will be masked. The BOD resets keep running under hot-plugging. This allows to correct a BOD33 user level too high for the available supply.

17.5.6 Register Access Protection

Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following: SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 160

Interrupt Flag Status and Clear register (INTFLAG) Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. Write-protection does not apply for accesses through an external debugger.

17.5.7 Analog Connections

When used, the 32.768kHz crystal must be connected between the XIN32 and XOUT32 pins, and the 0.4-32MHz crystal must be connected between the XIN and XOUT pins, along with any required load capacitors. For details on recommended oscillator characteristics and capacitor load, refer to the Electrical Characteristics for details. Related Links 37. Electrical Characteristics at 85℃

17.6 Functional Description

17.6.1 Principle of Operation

XOSC, XOSC32K, OSC32K, OSCULP32K, OSC8M, DFLL48M, FDPLL96M, BOD33, and VREF are configured through SYSCTRL control registers. Through this interface, the sub-peripherals are enabled, disabled or have their calibration values updated. The Power and Clocks Status register gathers different status signals coming from the sub-peripherals controlled by the SYSCTRL. The status signals can be used to generate system interrupts, and in some cases wake up the system from Standby mode, provided the corresponding interrupt is enabled. The oscillator must be enabled to run. The oscillator is enabled by writing a one to the ENABLE bit in the respective oscillator control register, and disabled by writing a zero to the oscillator control register. In Idle mode, the default operation of the oscillator is to run only when requested by a peripheral. In Standby mode, the default operation of the oscillator is to stop. This behavior can be changed by the user, see below for details. The behavior of the oscillators in the different sleep modes is shown in the table below. Table 17-1. Behavior of the Oscillators Oscillator Idle 0, 1, 2 Standby XOSC Run on request Stop XOSC32K Run on request Stop OSC32K Run on request Stop OSCULP32K Run Run OSC8M Run on request Stop DFLL48M Run on request Stop FDPLL96M Run on request Stop To force an oscillator to always run in Idle mode, and not only when requested by a peripheral, the oscillator ONDEMAND bit must be written to zero. The default value of this bit is one, and thus the default operation in Idle mode is to run only when requested by a peripheral. To force the oscillator to run in Standby mode, the RUNSTDBY bit must be written to one. The oscillator will then run in Standby mode when requested by a peripheral (ONDEMAND is one). To force an oscillator to always run in Standby mode, and not only when requested by a peripheral, the ONDEMAND bit must be written to zero and RUNSTDBY must be written to one. The next table shows the behavior in the different sleep modes, depending on the settings of ONDEMAND and RUNSTDBY. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 161

Table 17-2. Behavior in the different sleep modes Sleep mode ONDEMAND RUNSTDBY Behavior Idle 0, 1, 2 0 X Run Idle 0, 1, 2 1 X Run when requested by a peripheral Standby 0 0 Stop Standby 0 1 Run Standby 1 0 Stop Standby 1 1 Run when requested by a peripheral Note: This does not apply to the OSCULP32K oscillator, which is always running and cannot be disabled.

17.6.2 External Multipurpose Crystal Oscillator (XOSC) Operation

The XOSC can operate in two different modes:

External clock, with an external clock signal connected to the XIN pin
Crystal oscillator, with an external 0.4-32MHz crystal The XOSC can be used as a clock source for generic clock generators, as described in the GCLK – Generic Clock Controller. At reset, the XOSC is disabled, and the XIN/XOUT pins can be used as General Purpose I/O (GPIO) pins or by other peripherals in the system. When XOSC is enabled, the operating mode determines the GPIO usage. When in crystal oscillator mode, the XIN and XOUT pins are controlled by the SYSCTRL, and GPIO functions are overridden on both pins. When in external clock mode, only the XIN pin will be overridden and controlled by the SYSCTRL, while the XOUT pin can still be used as a GPIO pin. The XOSC is enabled by writing a one to the Enable bit in the External Multipurpose Crystal Oscillator Control register (XOSC.ENABLE). To enable the XOSC as a crystal oscillator, a one must be written to the XTAL Enable bit (XOSC.XTALEN). If XOSC.XTALEN is zero, external clock input will be enabled. When in crystal oscillator mode (XOSC.XTALEN is one), the External Multipurpose Crystal Oscillator Gain (XOSC.GAIN) must be set to match the external crystal oscillator frequency. If the External Multipurpose Crystal Oscillator Automatic Amplitude Gain Control (XOSC.AMPGC) is one, the oscillator amplitude will be automatically adjusted, and in most cases result in a lower power consumption. The XOSC will behave differently in different sleep modes based on the settings of XOSC.RUNSTDBY, XOSC.ONDEMAND and XOSC.ENABLE: XOSC.RUNSTDBY XOSC.ONDEMAND XOSC.ENABLE Sleep Behavior - - 0 Disabled 0 0 1 Always run in IDLE sleep modes. Disabled in STANDBY sleep mode. 0 1 1 Only run in IDLE sleep modes if requested by a peripheral. Disabled in STANDBY sleep mode. 1 0 1 Always run in IDLE and STANDBY sleep modes. 1 1 1 Only run in IDLE or STANDBY sleep modes if requested by a peripheral. After a hard reset, or when waking up from a sleep mode where the XOSC was disabled, the XOSC will need a certain amount of time to stabilize on the correct frequency. This start-up time can be configured by changing the Oscillator Start-Up Time bit group (XOSC.STARTUP) in the External Multipurpose Crystal Oscillator Control register. During the start-up time, the oscillator output is masked to ensure that no unstable clock propagates to the digital logic. The External Multipurpose Crystal Oscillator Ready bit in the Power and Clock Status register (PCLKSR.XOSCRDY) is set when the user-selected start-up time is over. An interrupt is generated on a zero-to-one SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 162

transition on PCLKSR.XOSCRDY if the External Multipurpose Crystal Oscillator Ready bit in the Interrupt Enable Set register (INTENSET.XOSCRDY) is set. Note: Do not enter standby mode when an oscillator is in start-up: Wait for the OSCxRDY bit in SYSCTRL.PCLKSR register to be set before going into standby mode. Related Links 15. GCLK - Generic Clock Controller 17.6.3 32kHz External Crystal Oscillator (XOSC32K) Operation The XOSC32K can operate in two different modes:

External clock, with an external clock signal connected to XIN32
Crystal oscillator, with an external 32.768kHz crystal connected between XIN32 and XOUT32 The XOSC32K can be used as a source for generic clock generators, as described in the GCLK – Generic Clock Controller. At Power-on Reset (POR) the XOSC32K is disabled, and the XIN32/XOUT32 pins can be used as General Purpose I/O (GPIO) pins or by other peripherals in the system. When XOSC32K is enabled, the operating mode determines the GPIO usage. When in crystal oscillator mode, XIN32 and XOUT32 are controlled by the SYSCTRL, and GPIO functions are overridden on both pins. When in external clock mode, only the XIN32 pin will be overridden and controlled by the SYSCTRL, while the XOUT32 pin can still be used as a GPIO pin. The external clock or crystal oscillator is enabled by writing a one to the Enable bit (XOSC32K.ENABLE) in the 32kHz External Crystal Oscillator Control register. To enable the XOSC32K as a crystal oscillator, a one must be written to the XTAL Enable bit (XOSC32K.XTALEN). If XOSC32K.XTALEN is zero, external clock input will be enabled. The oscillator is disabled by writing a zero to the Enable bit (XOSC32K.ENABLE) in the 32kHz External Crystal Oscillator Control register while keeping the other bits unchanged. Writing to the XOSC32K.ENABLE bit while writing to other bits may result in unpredictable behavior. The oscillator remains enabled in all sleep modes if it has been enabled beforehand. The start-up time of the 32kHz External Crystal Oscillator is selected by writing to the Oscillator Start-Up Time bit group (XOSC32K.STARTUP) in the in the 32kHz External Crystal Oscillator Control register. The SYSCTRL masks the oscillator output during the start-up time to ensure that no unstable clock propagates to the digital logic. The 32kHz External Crystal Oscillator Ready bit (PCLKSR.XOSC32KRDY) in the Power and Clock Status register is set when the user-selected startup time is over. An interrupt is generated on a zero-to-one transition of PCLKSR.XOSC32KRDY if the 32kHz External Crystal Oscillator Ready bit (INTENSET.XOSC32KRDY) in the Interrupt Enable Set Register is set. As a crystal oscillator usually requires a very long start-up time (up to one second), the 32kHz External Crystal Oscillator will keep running across resets, except for power-on reset (POR). XOSC32K can provide two clock outputs when connected to a crystal. The XOSC32K has a 32.768kHz output enabled by writing a one to the 32kHz External Crystal Oscillator 32kHz Output Enable bit (XOSC32K.EN32K) in the 32kHz External Crystal Oscillator Control register. XOSC32K.EN32K is only usable when XIN32 is connected to a crystal, and not when an external digital clock is applied on XIN32. Note: Do not enter Standby mode when an oscillator is in start-up: Wait for the OSCxRDY bit in SYSCTRL.PCLKSR register to be set before going into Standby mode. Related Links 15. GCLK - Generic Clock Controller 17.6.4 32 kHz Internal Oscillator (OSC32K) Operation The OSC32K provides a tunable, low-speed and low-power clock source. The OSC32K can be used as a source for the generic clock generators, as described in the GCLK – Generic Clock Controller. The OSC32K is disabled by default. The OSC32K is enabled by writing a one to the 32 kHz Internal Oscillator Enable bit (OSC32K.ENABLE) in the 32 kHz Internal Oscillator Control register. It is disabled by writing a zero to OSC32K.ENABLE. The OSC32K has a 32.768 kHz output enabled by writing a one to the 32 kHz Internal Oscillator 32 kHz Output Enable bit (OSC32K.EN32K). Both of the OSC32K.ENABLE and OSC32K.EN32K bits must be set for SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 163

the clock to start. When the clock is stable, the PCLKSR.OSC32KRDY bit will go high and the clock will propagate in the design. The frequency of the OSC32K oscillator is controlled by the value in the 32 kHz Internal Oscillator Calibration bits (OSC32K.CALIB) in the 32 kHz Internal Oscillator Control register. The OSC32K.CALIB value must be written by the user. Flash Factory Calibration values are stored in the NVM Software Calibration Area (refer to NVM Software Calibration Area Mapping). When writing to the Calibration bits, the user must wait for the PCLKSR.OSC32KRDY bit to go high before the value is committed to the oscillator. Related Links 15. GCLK - Generic Clock Controller 17.6.5 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Operation The OSCULP32K provides a tunable, low-speed and ultra-low-power clock source. The OSCULP32K is factory- calibrated under typical voltage and temperature conditions. The OSCULP32K should be preferred to the OSC32K whenever the power requirements are prevalent over frequency stability and accuracy. The OSCULP32K can be used as a source for the generic clock generators, as described in the GCLK – Generic Clock Controller. The OSCULP32K is enabled by default after a power-on reset (POR) and will always run except during POR. The OSCULP32K has a 32.768kHz output and a 1.024kHz output that are always running. The frequency of the OSCULP32K oscillator is controlled by the value in the 32kHz Ultra Low Power Internal Oscillator Calibration bits (OSCULP32K.CALIB) in the 32kHz Ultra Low Power Internal Oscillator Control register. OSCULP32K.CALIB is automatically loaded from Flash Factory Calibration during startup, and is used to compensate for process variation, as described in the Electrical Characteristics. The calibration value can be overridden by the user by writing to OSCULP32K.CALIB. Related Links 37. Electrical Characteristics at 85℃ 15. GCLK - Generic Clock Controller 17.6.6 8MHz Internal Oscillator (OSC8M) Operation OSC8M is an internal oscillator operating in open-loop mode and generating an 8MHz frequency. The OSC8M is factory-calibrated under typical voltage and temperature conditions. OSC8M is the default clock source that is used after a power-on reset (POR). The OSC8M can be used as a source for the generic clock generators, as described in the GCLK – Generic Clock Controller. In order to enable OSC8M, the Oscillator Enable bit in the OSC8M Control register (OSC8M.ENABLE) must be written to one. OSC8M will not be enabled until OSC8M.ENABLE is set. In order to disable OSC8M, OSC8M.ENABLE must be written to zero. OSC8M will not be disabled until OSC8M is cleared. The frequency of the OSC8M oscillator is controlled by the value in the calibration bits (OSC8M.CALIB) in the OSC8M Control register. CALIB is automatically loaded from Flash Factory Calibration during start-up, and is used to compensate for process variation, as described in the Electrical Characteristics. The user can control the oscillation frequency by writing to the Frequency Range (FRANGE) and Calibration (CALIB) bit groups in the 8MHz RC Oscillator Control register (OSC8M). It is not recommended to update the FRANGE and CALIB bits when the OSC8M is enabled. As this is in open-loop mode, the frequency will be voltage, temperature and process dependent. Refer to the Electrical Characteristics for details. OSC8M is automatically switched off in certain sleep modes to reduce power consumption, as described in the PM – Power Manager. Related Links 16. PM – Power Manager 37. Electrical Characteristics at 85℃ 15. GCLK - Generic Clock Controller SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 164

17.6.7 Digital Frequency Locked Loop (DFLL48M) Operation

The DFLL48M can operate in both open-loop mode and closed-loop mode. In closed-loop mode, a low-frequency clock with high accuracy can be used as the reference clock to get high accuracy on the output clock (CLK_DFLL48M). The DFLL48M can be used as a source for the generic clock generators, as described in the GCLK – Generic Clock Controller. Related Links 15. GCLK - Generic Clock Controller

17.6.7.1 Basic Operation

17.6.7.1.1 Open-Loop Operation

After any reset, the open-loop mode is selected. When operating in open-loop mode, the output frequency of the DFLL48M will be determined by the values written to the DFLL Coarse Value bit group and the DFLL Fine Value bit group (DFLLVAL.COARSE and DFLLVAL.FINE) in the DFLL Value register. Using "DFLL48M COARSE CAL" value from NVM Software Calibration Area Mapping in DFLL.COARSE helps to output a frequency close to 48 MHz. It is possible to change the values of DFLLVAL.COARSE and DFLLVAL.FINE and thereby the output frequency of the DFLL48M output clock, CLK_DFLL48M, while the DFLL48M is enabled and in use. CLK_DFLL48M is ready to be used when PCLKSR.DFLLRDY is set after enabling the DFLL48M. Related Links

17.6.7.1.2 Closed-Loop Operation

In closed-loop operation, the output frequency is continuously regulated against a reference clock. Once the multiplication factor is set, the oscillator fine tuning is automatically adjusted. The DFLL48M must be correctly configured before closed-loop operation can be enabled. After enabling the DFLL48M, it must be configured in the following way: 1. Enable and select a reference clock (CLK_DFLL48M_REF). CLK_DFLL48M_REF is Generic Clock Channel 0 (GCLK_DFLL48M_REF). Refer to GCLK – Generic Clock Controller for details. 2. Select the maximum step size allowed in finding the Coarse and Fine values by writing the appropriate values to the DFLL Coarse Maximum Step and DFLL Fine Maximum Step bit groups (DFLLMUL.CSTEP and DFLLMUL.FSTEP) in the DFLL Multiplier register. A small step size will ensure low overshoot on the output frequency, but will typically result in longer lock times. A high value might give a large overshoot, but will typically provide faster locking. DFLLMUL.CSTEP and DFLLMUL.FSTEP should not be higher than 50% of the maximum value of DFLLVAL.COARSE and DFLLVAL.FINE, respectively. 3. Select the multiplication factor in the DFLL Multiply Factor bit group (DFLLMUL.MUL) in the DFLL Multiplier register. Care must be taken when choosing DFLLMUL.MUL so that the output frequency does not exceed the maximum frequency of the DFLL. 4. Start the closed loop mode by writing a one to the DFLL Mode Selection bit (DFLLCTRL.MODE) in the DFLL Control register. The frequency of CLK_DFLL48M (Fclkdfll48m) is given by: F clkdfll 48 m = DFLLMUL ⋅ MUL × F clkdfll 48 mref where Fclkdfll48mref is the frequency of the reference clock (CLK_DFLL48M_REF). DFLLVAL.COARSE and DFLLVAL.FINE are read-only in closed-loop mode, and are controlled by the frequency tuner to meet user specified frequency. In closed-loop mode, the value in DFLLVAL.COARSE is used by the frequency tuner as a starting point for Coarse. Writing DFLLVAL.COARSE to a value close to the final value before entering closed-loop mode will reduce the time needed to get a lock on Coarse. Using "DFLL48M COARSE CAL" from NVM Software Calibration Area Mapping for DFLL.COARSE will start DFLL with a frequency close to 48 MHz. Following Software sequence should be followed while using the same. 1. load "DFLL48M COARSE CAL" from NVM User Row Mapping in DFLL.COARSE register 2. Set DFLLCTRL.BPLCKC bit SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 165

Start DFLL close loop This procedure will reduce DFLL Lock time to DFLL Fine lock time. Related Links 15. GCLK - Generic Clock Controller

17.6.7.1.3 Frequency Locking

The locking of the frequency in closed-loop mode is divided into two stages. In the first, coarse stage, the control logic quickly finds the correct value for DFLLVAL.COARSE and sets the output frequency to a value close to the correct frequency. On coarse lock, the DFLL Locked on Coarse Value bit (PCLKSR.DFLLLOCKC) in the Power and Clocks Status register will be set. In the second, fine stage, the control logic tunes the value in DFLLVAL.FINE so that the output frequency is very close to the desired frequency. On fine lock, the DFLL Locked on Fine Value bit (PCLKSR.DFLLLOCKF) in the Power and Clocks Status register will be set. Interrupts are generated by both PCLKSR.DFLLLOCKC and PCLKSR.DFLLLOCKF if INTENSET.DFLLOCKC or INTENSET.DFLLOCKF are written to one. CLK_DFLL48M is ready to be used when the DFLL Ready bit (PCLKSR.DFLLRDY) in the Power and Clocks Status register is set, but the accuracy of the output frequency depends on which locks are set. For lock times, refer to the Electrical Characteristics. Related Links 37. Electrical Characteristics at 85℃

17.6.7.1.4 Frequency Error Measurement

The ratio between CLK_DFLL48M_REF and CLK48M_DFLL is measured automatically when the DFLL48M is in closed-loop mode. The difference between this ratio and the value in DFLLMUL.MUL is stored in the DFLL Multiplication Ratio Difference bit group(DFLLVAL.DIFF) in the DFLL Value register. The relative error on CLK_DFLL48M compared to the target frequency is calculated as follows: ERROR = DIFF MUL

17.6.7.1.5 Drift Compensation

If the Stable DFLL Frequency bit (DFLLCTRL.STABLE) in the DFLL Control register is zero, the frequency tuner will automatically compensate for drift in the CLK_DFLL48M without losing either of the locks. This means that DFLLVAL.FINE can change after every measurement of CLK_DFLL48M. The DFLLVAL.FINE value overflows or underflows can occur in close loop mode when the clock source reference drifts or is unstable. This will set the DFLL Out Of Bounds bit (PCLKSR.DFLLOOB) in the Power and Clocks Status register. To avoid this error, the reference clock in close loop mode must be stable, an external oscillator is recommended and internal oscillator forbidden. The better choice is to use an XOSC32K.

17.6.7.1.6 Reference Clock Stop Detection

If CLK_DFLL48M_REF stops or is running at a very low frequency (slower than CLK_DFLL48M/(2 * MULMAX)), the DFLL Reference Clock Stopped bit (PCLKSR.DFLLRCS) in the Power and Clocks Status register will be set. Detecting a stopped reference clock can take a long time, on the order of 217 CLK_DFLL48M cycles. When the reference clock is stopped, the DFLL48M will operate as if in open-loop mode. Closed-loop mode operation will automatically resume if the CLK_DFLL48M_REF is restarted. An interrupt is generated on a zero-to-one transition on PCLKSR.DFLLRCS if the DFLL Reference Clock Stopped bit (INTENSET.DFLLRCS) in the Interrupt Enable Set register is set.

17.6.7.2 Additional Features

17.6.7.2.1 Dealing with Delay in the DFLL in Closed-Loop Mode

The time from selecting a new CLK_DFLL48M frequency until this frequency is output by the DFLL48M can be up to several microseconds. If the value in DFLLMUL.MUL is small, this can lead to instability in the DFLL48M locking mechanism, which can prevent the DFLL48M from achieving locks. To avoid this, a chill cycle, during which the SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 166

CLK_DFLL48M frequency is not measured, can be enabled. The chill cycle is enabled by default, but can be disabled by writing a one to the DFLL Chill Cycle Disable bit (DFLLCTRL.CCDIS) in the DFLL Control register. Enabling chill cycles might double the lock time. Another solution to this problem consists of using less strict lock requirements. This is called Quick Lock (QL), which is also enabled by default, but it can be disabled by writing a one to the Quick Lock Disable bit (DFLLCTRL.QLDIS) in the DFLL Control register. The Quick Lock might lead to a larger spread in the output frequency than chill cycles, but the average output frequency is the same.

17.6.7.2.2 USB Clock Recovery Mode

USB Clock Recovery mode can be used to create the 48MHz USB clock from the USB Start Of Frame (SOF). This mode is enabled by writing a '1' to both the USB Clock Recovery Mode bit and the Mode bit in DFLL Control register (DFLLCTRL.USBCRM and DFLLCTRL.MODE). Note: In USB Clock Recovery mode, the status bits of the DFLL in OSCCTRL.STATUS are determined by the USB bus activity, and have no valid meaning. The SOF signal from USB device will be used as reference clock (CLK_DFLL_REF), ignoring the selected generic clock reference. When the USB device is connected, a SOF will be sent every 1ms, thus DFLLVAL.MUX bits should be written to 0xBB80 to obtain a 48MHz clock. In USB clock recovery mode, the DFLLCTRL.BPLCKC bit state is ignored, and the value stored in the DFLLVAL.COARSE will be used as final Coarse Value. The COARSE calibration value can be loaded from NVM OTP row by software. The locking procedure will also go instantaneously to the fine lock search. The DFLLCTRL.QLDIS bit must be cleared and DFLLCTRL.CCDIS should be set to speed up the lock phase. The DFLLCTRL.STABLE bit state is ignored, an auto jitter reduction mechanism is used instead.

17.6.7.2.3 Wake from Sleep Modes

DFLL48M can optionally reset its lock bits when it is disabled. This is configured by the Lose Lock After Wake bit (DFLLCTRL.LLAW) in the DFLL Control register. If DFLLCTRL.LLAW is zero, the DFLL48M will be re-enabled and start running with the same configuration as before being disabled, even if the reference clock is not available. The locks will not be lost. When the reference clock has restarted, the Fine tracking will quickly compensate for any frequency drift during sleep if DFLLCTRL.STABLE is zero. If DFLLCTRL.LLAW is one when the DFLL is turned off, the DFLL48M will lose all its locks, and needs to regain these through the full lock sequence.

17.6.7.2.4 Accuracy

There are three main factors that determine the accuracy of Fclkdfll48m. These can be tuned to obtain maximum accuracy when fine lock is achieved.

Fine resolution: The frequency step between two Fine values. This is relatively smaller for high output frequencies.
Resolution of the measurement: If the resolution of the measured F clkdfll48m is low, i.e., the ratio between the CLK_DFLL48M frequency and the CLK_DFLL48M_REF frequency is small, then the DFLL48M might lock at a frequency that is lower than the targeted frequency. It is recommended to use a reference clock frequency of 32kHz or lower to avoid this issue for low target frequencies.
The accuracy of the reference clock.

17.6.8 Fractional Digital Phase-Locked Loop Controller (FDPLL96M) Operation

17.6.8.1 Overview

The FDPLL96M controller allows flexible interface to the core digital function of the Digital Phase Locked Loop (DPLL). The FDPLL96M integrates a digital filter with a proportional integral controller, a Time-to-Digital Converter (TDC), a test mode controller, a Digitally Controlled Oscillator (DCO) and a PLL controller. It also provides a fractional multiplier of frequency N between the input and output frequency. The CLK_FDPLL96M_REF is the DPLL input clock reference. The selectable sources for the reference clock are XOSC32K, XOSC and GCLK_DPLL. The path between XOSC and input multiplexer integrates a clock divider. The selected clock must be configured and enabled before using the FDPLL96M. If the GCLK is selected as reference clock, it must be configured and enabled in the Generic Clock Controller before using the FDPLL96M. Refer to GCLK – Generic Clock Controller for details. If the GCLK_DPLL is selected as the source for the CLK_FDPLL96M_REF, care must be taken to make sure the source for this GCLK is within the valid frequency range for the FDPLL96M. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 167

The XOSC source can be divided inside the FDPLL96M. The user must make sure that the programmable clock divider and XOSC frequency provides a valid CLK_FDPLL96M_REF clock frequency that meets the FDPLL96M input frequency range. The output clock of the FDPLL96M is CLK_FDPLL96M. The state of the CLK_FDPLL96M clock only depends on the FDPLL96M internal control of the final clock gater CG. The FDPLL96M requires a 32kHz clock from the GCLK when the FDPLL96M internal lock timer is used. This clock must be configured and enabled in the Generic Clock Controller before using the FDPLL96M. Refer to GCLK – Generic Clock Controller for details. Table 17-3. Generic Clock Input for FDPLL96M Generic Clock FDPLL96M FDPLL96M 32kHz clock GCLK_DPLL_32K for internal lock timer FDPLL96M GCLK_DPLL for CLK_FDPLL96M_REF Related Links 15. GCLK - Generic Clock Controller

17.6.8.2 Block Diagram

Figure 17-2. FDPLL96M Block Diagram TDC Digital Filter DCO XOSC32K XOSC CK GCLK_DPLL CLK_FDPLL96M User Interface CLK_FDPLL96M_REF GCLK_DPLL_32K Divider CG

17.6.8.3 Principle of Operation

The task of the FDPLL96M is to maintain coherence between the input reference clock signal (CLK_FDPLL96M_REF) and the respective output frequency CK via phase comparison. The FDPLL96M supports three independent sources of clocks; XOSC32K, XOSC and GCLK_DPLL. When the FDPLL96M is enabled, the relationship between the reference clock (CLK_FDPLL96M_REF) frequency and the output clock (CLK_FDPLL96M) frequency is defined below. f c l k _ f d pl l 96 m = f c lk _ f d pl l 96 m _ r e f × L DR + 1 + L DR FR AC Where LDR is the loop divider ratio integer part, LDRFRAC is the loop divider ratio fractional part, fckrx is the frequency of the selected reference clock and fck is the frequency of the FDPLL96M output clock. As previously stated a clock divider exist between XOSC and CLK_FDPLL96M_REF. The frequency between the two clocks is defined below. f c l k _ f d pl l 96 m _ re f = f xo s c × 1 2 × DI V + 1 When the FDPLL96M is disabled, the output clock is reset. If the loop divider ratio fractional part (DPLLRATIO.LDRFRAC) field is reset, the FDPLL96M works in integer mode, otherwise the fractional mode is activated. It shall be noted that fractional part has a negative impact on the jitter of the FDPLL96M. Example (integer mode only): assuming fckr = 32kHz and fck = 48MHz, the multiplication ratio is 1500. It means that LDR shall be set to 1499. Example (fractional mode): assuming fckr = 32kHz and fck = 48.006MHz, the multiplication ratio is 1500.1875 (1500 + 3/16). Thus LDR is set to 1499 and LDRFRAC to 3. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 168

17.6.8.4 Initialization, Enabling, Disabling and Resetting

The FDPLL96M is enabled by writing a one to the Enable bit in the DPLL Control A register (DPLLCTRLA.ENABLE). The FDPLL96M is disabled by writing a zero to DPLLCTRLA.ENABLE. The frequency of the FDPLL96M output clock CK is stable when the module is enabled and when the DPLL Lock Status bit in the DPLL Status register (DPLLSTATUS.LOCK) bit is set. When DPLLCTRLB.LTIME is different from 0, a user defined lock time is used to validate the lock operation. In this case the lock time is constant. If DPLLCTRLB.LTIME is reset, the lock signal is linked with the status bit of the DPLL, the lock time vary depending on the filter selection and final target frequency. When DPLLCTRLB.WUF is set, the wake up fast mode is activated. In that mode, the clock gating cell is enabled at the end of the startup time. At that time, the final frequency is not stable as it is still in the acquisition period, but it allows saving several milliseconds. After first acquisition, DPLLCTRLB.LBYPASS indicates if the Lock signal is discarded from the control of the clock gater generating the output clock CLK_FDPLL96M. Table 17-4. CLK_FDPLL96M Behavior from Start-up to First Edge Detection. WUF LTIME CLK_FDPLL96M Behavior 0 0 Normal Mode: First Edge when lock is asserted 0 Not Equal To Zero Lock Timer Timeout mode: First Edge when the timer downcounts to 0.

1 X Wake Up Fast Mode: First Edge when CK is active (start-up time)

Table 17-5. CLK_FDPLL96M behavior after First Edge detection. LBYPASS CLK_FDPLL96M Behavior 0 Normal Mode: the CLK_FDPLL96M is turned off when lock signal is low. 1 Lock Bypass Mode: the CLK_FDPLL96M is always running, lock is irrelevant. Figure 17-3. CK and CLK_FDPLL96M Off Mode to Running Mode CKRx ENABLE CK LOCK CLK_FDPLL96M SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 169

Figure 17-4. CK and CLK_FDPLL96M Off Mode to Running Mode when Wake-Up Fast is Activated CKRx ENABLE CK LOCK CLK_FDPLL96M Figure 17-5. CK and CLK_FDPLL96M Running Mode to Off Mode CKRx ENABLE CK LOCK CLK_FDPLL96M

17.6.8.5 Reference Clock Switching

When a software operation requires reference clock switching, the normal operation is to disable the FDPLL96M, modify the DPLLCTRLB.REFCLK to select the desired reference source and activate the FDPLL96M again.

17.6.8.6 Loop Divider Ratio updates

The FDPLL96M supports on-the-fly update of the DPLLRATIO register, so it is allowed to modify the loop divider ratio and the loop divider ratio fractional part when the FDPLL96M is enabled. At that time, the DPLLSTATUS.LOCK bit is cleared and set again by hardware when the output frequency reached a stable state. The DPLL Lock Fail bit in the Interrupt Flag Status and Clear register (INTFLAG.DPLLLCK) is set when a falling edge has been detected. The flag is cleared when the software write a one to the interrupt flag bit location. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 170

Figure 17-6. RATIOCTRL Register Update Operation CKRx LDR LDRFRAC CK CLK_FDPLL96M mult0 mult1 LOCK LOCKL

17.6.8.7 Digital Filter Selection

The PLL digital filter (PI controller) is automatically adjusted in order to provide a good compromise between stability and jitter. Nevertheless a software operation can override the filter setting using the DPLLCTRLB.FILTER field. The DPLLCTRLB.LPEN field can be use to bypass the TDC module. 17.6.9 3.3V Brown-Out Detector Operation The 3.3V BOD monitors the 3.3V VDDANA supply (BOD33). It supports continuous or sampling modes. The threshold value action (reset the device or generate an interrupt), the Hysteresis configuration, as well as the enable/disable settings are loaded from Flash User Calibration at startup, and can be overridden by writing to the corresponding BOD33 register bit groups. 17.6.9.1 3.3V Brown-Out Detector (BOD33) The 3.3V Brown-Out Detector (BOD33) monitors the VDDANA supply and compares the voltage with the brown-out threshold level set in the BOD33 Level bit group (BOD33.LEVEL) in the BOD33 register. The BOD33 can generate either an interrupt or a reset when VDDANA crosses below the brown-out threshold level. The BOD33 detection status can be read from the BOD33 Detection bit (PCLKSR.BOD33DET) in the Power and Clocks Status register. At start-up or at power-on reset (POR), the BOD33 register values are loaded from the Flash User Row. Refer to NVM User Row Mapping for more details. Related Links

17.6.9.2 Continuous Mode

When the BOD33 Mode bit (BOD33.MODE) in the BOD33 register is written to zero and the BOD33 is enabled, the BOD33 operates in continuous mode. In this mode, the BOD33 is continuously monitoring the VDDANA supply voltage. Continuous mode is the default mode for BOD33.

17.6.9.3 Sampling Mode

The Sampling mode is a low-power mode where the BOD33 is being repeatedly enabled on a sampling clock’s ticks. The BOD33 will monitor the supply voltage for a short period of time and then go to a low-power disabled state until the next sampling clock tick. Sampling mode is enabled by writing one to BOD33.MODE. The frequency of the clock ticks (Fclksampling) is controlled by the BOD33 Prescaler Select bit group (BOD33.PSEL) in the BOD33 register. F clksampling = F clkprescaler

2 PSEL+1

The prescaler signal (Fclkprescaler) is a 1 kHz clock, output from the32 kHz Ultra Low-Power Oscillator, OSCULP32K. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 171

As the Sampling mode clock is different from the APB clock domain, synchronization among the clocks is necessary. The next figure shows a block diagram of the Sampling mode. The BOD33Synchronization Ready bit (PCLKSR.B33SRDY) in the Power and Clocks Status register show the synchronization ready status of the synchronizer. Writing attempts to the BOD33 register are ignored while PCLKSR.B33SRDY is zero. Figure 17-7. Sampling Mode Block Diagram US ER INTERFA CE R E G IS TER S (APB clock domain ) P RE SC ALE R (clk_prescale r domain ) S YN C HR O NIZER P S EL C EN MO DE ENABL E C LK_APB C LK_PRE SC ALER C LK _ SAMPLIN G The BOD33 Clock Enable bit (BOD33.CEN) in the BOD33 register should always be disabled before changing the prescaler value. To change the prescaler value for the BOD33 during Sampling mode, the following steps need to be taken: 1. Wait until the PCLKSR.B33SRDY bit is set. 2. Write the selected value to the BOD33.PSEL bit group.

17.6.9.4 Hysteresis

The hysteresis functionality can be used in both continuous and sampling mode. Writing a one to the BOD33 Hysteresis bit (BOD33.HYST) in the BOD33 register will add hysteresis to the BOD33 threshold level.

17.6.10 Voltage Reference System Operation

The Voltage Reference System (VREF) consists of a Bandgap Reference Voltage Generator and a temperature sensor. The Bandgap Reference Voltage Generator is factory-calibrated under typical voltage and temperature conditions. At reset, the VREF.CAL register value is loaded from Flash Factory Calibration. The temperature sensor can be used to get an absolute temperature in the temperature range of CMIN to CMAX degrees Celsius. The sensor will output a linear voltage proportional to the temperature. The output voltage and temperature range are located in the Electrical Characteristics. To calculate the temperature from a measured voltage, the following formula can be used: C MIN + Vmes + − Vou t MAX ∆ temperature ∆ voltage Related Links 37. Electrical Characteristics at 85℃

17.6.10.1 User Control of the Voltage Reference System

To enable the temperature sensor, write a one to the Temperature Sensor Enable bit (VREF.TSEN) in the VREF register. The temperature sensor is not available on the DA1 devices. The temperature sensor can be redirected to the ADC for conversion. The Bandgap Reference Voltage Generator output can also be routed to the ADC if the Bandgap Output Enable bit (VREF.BGOUTEN) in the VREF register is set. The Bandgap Reference Voltage Generator output level is determined by the CALIB bit group (VREF.CALIB) value in the VREF register. The default calibration value can be overridden by writing to the CALIB bit group. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 172

17.6.11 Voltage Regulator System Operation

The embedded Voltage Regulator (VREG) is an internal voltage regulator that provides the core logic supply (VDDCORE).

17.6.12 DMA Operation

Not applicable.

17.6.13 Interrupts

The SYSCTRL has the following interrupt sources:

XOSCRDY - Multipurpose Crystal Oscillator Ready: A “0-to-1” transition on the PCLKSR.XOSCRDY bit is detected
XOSC32KRDY - 32kHz Crystal Oscillator Ready: A “0-to-1” transition on the PCLKSR.XOSC32KRDY bit is detected
OSC32KRDY - 32kHz Internal Oscillator Ready: A “0-to-1” transition on the PCLKSR.OSC32KRDY bit is detected
OSC8MRDY - 8MHz Internal Oscillator Ready: A “0-to-1” transition on the PCLKSR.OSC8MRDY bit is detected
DFLLRDY - DFLL48M Ready: A “0-to-1” transition on the PCLKSR.DFLLRDY bit is detected
DFLLOOB - DFLL48M Out Of Boundaries: A “0-to-1” transition on the PCLKSR.DFLLOOB bit is detected
DFLLLOCKF - DFLL48M Fine Lock: A “0-to-1” transition on the PCLKSR.DFLLLOCKF bit is detected
DFLLLOCKC - DFLL48M Coarse Lock: A “0-to-1” transition on the PCLKSR.DFLLLOCKC bit is detected
DFLLRCS - DFLL48M Reference Clock has Stopped: A “0-to-1” transition on the PCLKSR.DFLLRCS bit is detected
BOD33RDY - BOD33 Ready: A “0-to-1” transition on the PCLKSR.BOD33RDY bit is detected
BOD33DET - BOD33 Detection: A “0-to-1” transition on the PCLKSR.BOD33DET bit is detected. This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
B33SRDY - BOD33 Synchronization Ready: A “0-to-1” transition on the PCLKSR.B33SRDY bit is detected
PLL Lock (LOCK): Indicates that the DPLL Lock bit is asserted.
PLL Lock Lost (LOCKL): Indicates that a falling edge has been detected on the Lock bit during normal operation mode.
PLL Lock Timer Timeout (LTTO): This interrupt flag indicates that the software defined time DPLLCTRLB.LTIME has elapsed since the start of the FDPLL96M. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the SYSCTRL is reset. See Interrupt Flag Status and Clear (INTFLAG) register for details on how to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. Refer to Nested Vector Interrupt Controller for details. The user must read the INTFLAG register to determine which interrupt condition is present. Note: Interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector Interrupt Controller for details. Related Links

17.6.14 Synchronization

Due to the multiple clock domains, values in the DFLL48M Control registers need to be synchronized to other clock domains. The status of this synchronization can be read from the Power and Clocks Status register (PCLKSR). Before writing to any of the DFLL48M Control registers, the user must check that the DFLL Ready bit (PCLKSR.DFLLRDY) in PCLKSR is set to one. When this bit is set, the DFLL48M can be configured and CLK_DFLL48M is ready to be used. Any write to any of the DFLL48M Control registers while DFLLRDY is SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 173

zero will be ignored. An interrupt is generated on a zero-to-one transition of DFLLRDY if the DFLLRDY bit (INTENSET.DFLLDY) in the Interrupt Enable Set register is set. In order to read from any of the DFLL48M Configuration registers, the user must request a read synchronization by writing a one to DFLLSYNC.READREQ. The registers can be read only when PCLKSR.DFLLRDY is set. If DFLLSYNC.READREQ is not written before a read, a synchronization will be started, and the bus will be halted until the synchronization is complete. Reading the DFLL48M registers when the DFLL48M is disabled will not halt the bus. The prescaler counter used to trigger one-shot brown-out detections also operates asynchronously from the peripheral bus. As a consequence, the Prescaler registers require synchronization when written or read. The synchronization results in a delay from when the initialization of the write or read operation begins until the operation is complete. The write synchronization is triggered by a write to the BOD33 Control register. The Synchronization Ready bit (PCLKSR.B33SRDY) in the PCLKSR register will be cleared when the write synchronization starts and set when the write synchronization is complete. When the write synchronization is ongoing (PCLKSR.B33SRDYis zero), an attempt to do any of the following will cause the peripheral bus to stall until the synchronization is complete:

Writing to the BOD33Control register
Reading the BOD33 Control register that was written The user can poll PCLKSR.B33SRDY or use the INTENSET.B33SRDY interrupt to check when the synchronization is complete. It is also possible to perform the next read/write operation and wait, as this next operation will be completed after the ongoing read/write operation is synchronized. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 174

17.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 INTENCLR 7:0 DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRD Y XOSCRDY 15:8 DPLLLCKR B33SRDY BOD33DET BOD33RDY DFLLRCS 23:16 DPLLLTO DPLLLCKF 31:24 0x04 INTENSET 7:0 DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRD Y XOSCRDY 15:8 DPLLLCKR B33SRDY BOD33DET BOD33RDY DFLLRCS 23:16 DPLLLTO DPLLLCKF 31:24 0x08 INTFLAG 7:0 DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRD Y XOSCRDY 15:8 DPLLLCKR B33SRDY BOD33DET BOD33RDY DFLLRCS 23:16 DPLLLTO DPLLLCKF 31:24 0x0C PCLKSR 7:0 DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRD Y XOSCRDY 15:8 DPLLLCKR B33SRDY BOD33DET BOD33RDY DFLLRCS 23:16 DPLLLTO DPLLLCKF 31:24 0x10 XOSC 7:0 ONDEMAND RUNSTDBY XTALEN ENABLE 15:8 STARTUP[3:0] AMPGC GAIN[2:0] 0x12 ... 0x13 Reserved 0x14 XOSC32K 7:0 ONDEMAND RUNSTDBY AAMPEN EN32K XTALEN ENABLE 15:8 WRTLOCK STARTUP[2:0] 0x16 ... 0x17 Reserved 0x18 OSC32K 7:0 ONDEMAND RUNSTDBY EN32K ENABLE 15:8 WRTLOCK STARTUP[2:0] 23:16 CALIB[6:0] 31:24 0x1C OSCULP32K 7:0 WRTLOCK CALIB[4:0] 0x1D ... 0x1F Reserved 0x20 OSC8M 7:0 ONDEMAND RUNSTDBY ENABLE 15:8 PRESC[1:0] 23:16 CALIB[7:0] 31:24 FRANGE[1:0] CALIB[11:8] 0x24 DFLLCTRL 7:0 ONDEMAND USBCRM LLAW STABLE MODE ENABLE 15:8 WAITLOCK BPLCKC QLDIS CCDIS 0x26 ... 0x27 Reserved 0x28 DFLLVAL 7:0 FINE[7:0] 15:8 COARSE[5:0] FINE[9:8] 23:16 DIFF[7:0] 31:24 DIFF[15:8] 0x2C DFLLMUL 7:0 MUL[7:0] 15:8 MUL[15:8] 23:16 FSTEP[7:0] 31:24 CSTEP[5:0] FSTEP[9:8] 0x30 DFLLSYNC 7:0 READREQ SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 175

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x31 ... 0x33 Reserved 0x34 BOD33 7:0 RUNSTDBY ACTION[1:0] HYST ENABLE 15:8 PSEL[3:0] CEN MODE 23:16 LEVEL[5:0] 31:24 0x38 ... 0x3B Reserved 0x3C VREG 7:0 RUNSTDBY ENABLE 15:8 FORCELDO 0x3E ... 0x3F Reserved 0x40 VREF 7:0 BGOUTEN TSEN 15:8 23:16 CALIB[7:0] 31:24 CALIB[10:8] 0x44 DPLLCTRLA 7:0 ONDEMAND RUNSTDBY ENABLE 0x45 ... 0x47 Reserved 0x48 DPLLRATIO 7:0 LDR[7:0] 15:8 LDR[11:8] 23:16 LDRFRAC[3:0] 31:24 0x4C DPLLCTRLB 7:0 REFCLK[1:0] WUF LPEN FILTER[1:0] 15:8 LBYPASS LTIME[2:0] 23:16 DIV[7:0] 31:24 DIV[10:8] 0x50 DPLLSTATUS 7:0 DIV ENABLE CLKRDY LOCK

17.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read- Synchronized" and/or "Write-Synchronized" property in each individual register description. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 176

17.8.1 Interrupt Enable Clear

Name: INTENCLR Offset: 0x00 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DPLLLTO DPLLLCKF Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DPLLLCKR B33SRDY BOD33DET BOD33RDY DFLLRCS Access R/W R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 17 – DPLLLTO DPLL Lock Timeout Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the DPLL Lock Timeout Interrupt Enable bit, which disables the DPLL Lock Timeout interrupt. Value Description 0 The DPLL Lock Timeout interrupt is disabled.

1 The DPLL Lock Timeout interrupt is enabled, and an interrupt request will be generated when the DPLL

Lock Timeout Interrupt flag is set. Bit 16 – DPLLLCKF DPLL Lock Fall Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the DPLL Lock Fall Interrupt Enable bit, which disables the DPLL Lock Fall interrupt. Value Description 0 The DPLL Lock Fall interrupt is disabled.

1 The DPLL Lock Fall interrupt is enabled, and an interrupt request will be generated when the DPLL

Lock Fall Interrupt flag is set. Bit 15 – DPLLLCKR DPLL Lock Rise Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the DPLL Lock Rise Interrupt Enable bit, which disables the DPLL Lock Rise interrupt. Value Description 0 The DPLL Lock Rise interrupt is disabled.

1 The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL

Lock Rise Interrupt flag is set. Bit 11 – B33SRDY BOD33 Synchronization Ready Interrupt Enable Writing a zero to this bit has no effect. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 177

Writing a one to this bit will clear the BOD33 Synchronization Ready Interrupt Enable bit, which disables the BOD33 Synchronization Ready interrupt. Value Description 0 The BOD33 Synchronization Ready interrupt is disabled.

1 The BOD33 Synchronization Ready interrupt is enabled, and an interrupt request will be generated

when the BOD33 Synchronization Ready Interrupt flag is set. Bit 10 – BOD33DET BOD33 Detection Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the BOD33 Detection Interrupt Enable bit, which disables the BOD33 Detection interrupt. Value Description 0 The BOD33 Detection interrupt is disabled.

1 The BOD33 Detection interrupt is enabled, and an interrupt request will be generated when the BOD33

Detection Interrupt flag is set. Bit 9 – BOD33RDY BOD33 Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the BOD33 Ready Interrupt Enable bit, which disables the BOD33 Ready interrupt. Value Description 0 The BOD33 Ready interrupt is disabled.

1 The BOD33 Ready interrupt is enabled, and an interrupt request will be generated when the BOD33

Ready Interrupt flag is set. Bit 8 – DFLLRCS DFLL Reference Clock Stopped Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the DFLL Reference Clock Stopped Interrupt Enable bit, which disables the DFLL Reference Clock Stopped interrupt. Value Description 0 The DFLL Reference Clock Stopped interrupt is disabled.

1 The DFLL Reference Clock Stopped interrupt is enabled, and an interrupt request will be generated

when the DFLL Reference Clock Stopped Interrupt flag is set. Bit 7 – DFLLLCKC DFLL Lock Coarse Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the DFLL Lock Coarse Interrupt Enable bit, which disables the DFLL Lock Coarse interrupt. Value Description 0 The DFLL Lock Coarse interrupt is disabled.

1 The DFLL Lock Coarse interrupt is enabled, and an interrupt request will be generated when the DFLL

Lock Coarse Interrupt flag is set. Bit 6 – DFLLLCKF DFLL Lock Fine Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the DFLL Lock Fine Interrupt Enable bit, which disables the DFLL Lock Fine interrupt. Value Description 0 The DFLL Lock Fine interrupt is disabled.

1 The DFLL Lock Fine interrupt is enabled, and an interrupt request will be generated when the DFLL

Lock Fine Interrupt flag is set. Bit 5 – DFLLOOB DFLL Out Of Bounds Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the DFLL Out Of Bounds Interrupt Enable bit, which disables the DFLL Out Of Bounds interrupt. Value Description 0 The DFLL Out Of Bounds interrupt is disabled. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 178

1 The DFLL Out Of Bounds interrupt is enabled, and an interrupt request will be generated when the

DFLL Out Of Bounds Interrupt flag is set. Bit 4 – DFLLRDY DFLL Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the DFLL Ready Interrupt Enable bit, which disables the DFLL Ready interrupt. Value Description 0 The DFLL Ready interrupt is disabled.

1 The DFLL Ready interrupt is enabled, and an interrupt request will be generated when the DFLL Ready

Interrupt flag is set. Bit 3 – OSC8MRDY OSC8M Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the OSC8M Ready Interrupt Enable bit, which disables the OSC8M Ready interrupt. Value Description 0 The OSC8M Ready interrupt is disabled.

1 The OSC8M Ready interrupt is enabled, and an interrupt request will be generated when the OSC8M

Ready Interrupt flag is set. Bit 2 – OSC32KRDY OSC32K Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the OSC32K Ready Interrupt Enable bit, which disables the OSC32K Ready interrupt. Value Description 0 The OSC32K Ready interrupt is disabled.

1 The OSC32K Ready interrupt is enabled, and an interrupt request will be generated when the OSC32K

Ready Interrupt flag is set. Bit 1 – XOSC32KRDY XOSC32K Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the XOSC32K Ready Interrupt Enable bit, which disables the XOSC32K Ready interrupt. Value Description 0 The XOSC32K Ready interrupt is disabled.

1 The XOSC32K Ready interrupt is enabled, and an interrupt request will be generated when the

XOSC32K Ready Interrupt flag is set. Bit 0 – XOSCRDY XOSC Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the XOSC Ready Interrupt Enable bit, which disables the XOSC Ready interrupt. Value Description 0 The XOSC Ready interrupt is disabled.

1 The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC

17.8.2 Interrupt Enable Set

Name: INTENSET Offset: 0x04 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DPLLLTO DPLLLCKF Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DPLLLCKR B33SRDY BOD33DET BOD33RDY DFLLRCS Access R/W R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 17 – DPLLLTO DPLL Lock Timeout Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the DPLL Lock Timeout Interrupt Enable bit, which enables the DPLL Lock Timeout interrupt. Value Description 0 The DPLL Lock Timeout interrupt is disabled. Lock Timeout Interrupt flag is set. Bit 16 – DPLLLCKF DPLL Lock Fall Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the DPLL Lock Fall Interrupt Enable bit, which enables the DPLL Lock Fall interrupt. Value Description 0 The DPLL Lock Fall interrupt is disabled. Lock Fall Interrupt flag is set. Bit 15 – DPLLLCKR DPLL Lock Rise Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the DPLL Lock Rise Interrupt Enable bit, which enables the DPLL Lock Rise interrupt. Value Description 0 The DPLL Lock Rise interrupt is disabled. Lock Rise Interrupt flag is set. Bit 11 – B33SRDY BOD33 Synchronization Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the BOD33 Synchronization Ready Interrupt Enable bit, which enables the BOD33 Synchronization Ready interrupt. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 180

0 The BOD33 Synchronization Ready interrupt is disabled. when the BOD33 Synchronization Ready Interrupt flag is set. Bit 10 – BOD33DET BOD33 Detection Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the BOD33 Detection Interrupt Enable bit, which enables the BOD33 Detection interrupt. Value Description 0 The BOD33 Detection interrupt is disabled. Detection Interrupt flag is set. Bit 9 – BOD33RDY BOD33 Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the BOD33 Ready Interrupt Enable bit, which enables the BOD33 Ready interrupt. Value Description 0 The BOD33 Ready interrupt is disabled. Ready Interrupt flag is set. Bit 8 – DFLLRCS DFLL Reference Clock Stopped Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the DFLL Reference Clock Stopped Interrupt Enable bit, which enables the DFLL Reference Clock Stopped interrupt. Value Description 0 The DFLL Reference Clock Stopped interrupt is disabled. when the DFLL Reference Clock Stopped Interrupt flag is set. Bit 7 – DFLLLCKC DFLL Lock Coarse Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the DFLL Lock Coarse Interrupt Enable bit, which enables the DFLL Lock Coarse interrupt. Value Description 0 The DFLL Lock Coarse interrupt is disabled. Lock Coarse Interrupt flag is set. Bit 6 – DFLLLCKF DFLL Lock Fine Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the DFLL Lock Fine Interrupt Disable/Enable bit, disable the DFLL Lock Fine interrupt and set the corresponding interrupt request. Value Description 0 The DFLL Lock Fine interrupt is disabled. Lock Fine Interrupt flag is set. Bit 5 – DFLLOOB DFLL Out Of Bounds Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the DFLL Out Of Bounds Interrupt Enable bit, which enables the DFLL Out Of Bounds interrupt. Value Description 0 The DFLL Out Of Bounds interrupt is disabled. DFLL Out Of Bounds Interrupt flag is set. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 181

Bit 4 – DFLLRDY DFLL Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the DFLL Ready Interrupt Enable bit, which enables the DFLL Ready interrupt and set the corresponding interrupt request. Value Description 0 The DFLL Ready interrupt is disabled. Interrupt flag is set. Bit 3 – OSC8MRDY OSC8M Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the OSC8M Ready Interrupt Enable bit, which enables the OSC8M Ready interrupt. Value Description 0 The OSC8M Ready interrupt is disabled. Ready Interrupt flag is set. Bit 2 – OSC32KRDY OSC32K Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the OSC32K Ready Interrupt Enable bit, which enables the OSC32K Ready interrupt. Value Description 0 The OSC32K Ready interrupt is disabled. Ready Interrupt flag is set. Bit 1 – XOSC32KRDY XOSC32K Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the XOSC32K Ready Interrupt Enable bit, which enables the XOSC32K Ready interrupt. Value Description 0 The XOSC32K Ready interrupt is disabled. XOSC32K Ready Interrupt flag is set. Bit 0 – XOSCRDY XOSC Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the XOSC Ready Interrupt Enable bit, which enables the XOSC Ready interrupt. Value Description 0 The XOSC Ready interrupt is disabled. Ready Interrupt flag is set. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 182

17.8.3 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x08 Reset: 0x00000000 Property: - Note: Depending on the fuse settings, various bits of the INTFLAG register can be set to one at startup. Therefore the user should clear those bits before using the corresponding interrupts. Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DPLLLTO DPLLLCKF Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DPLLLCKR B33SRDY BOD33DET BOD33RDY DFLLRCS Access R/W R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 17 – DPLLLTO DPLL Lock Timeout This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the DPLL Lock Timeout bit in the Status register (PCLKSR.DPLLLTO) and will generate an interrupt request if INTENSET.DPLLLTO is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the DPLL Lock Timeout interrupt flag. Bit 16 – DPLLLCKF DPLL Lock Fall This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the DPLL Lock Fall bit in the Status register (PCLKSR.DPLLLCKF) and will generate an interrupt request if INTENSET.DPLLLCKF is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the DPLL Lock Fall interrupt flag. Bit 15 – DPLLLCKR DPLL Lock Rise This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the DPLL Lock Rise bit in the Status register (PCLKSR.DPLLLCKR) and will generate an interrupt request if INTENSET.DPLLLCKR is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the DPLL Lock Rise interrupt flag. Bit 11 – B33SRDY BOD33 Synchronization Ready This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the BOD33 Synchronization Ready bit in the Status register (PCLKSR.B33SRDY) and will generate an interrupt request if INTENSET.B33SRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the BOD33 Synchronization Ready interrupt flag SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 183

Bit 10 – BOD33DET BOD33 Detection This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the BOD33 Detection bit in the Status register (PCLKSR.BOD33DET) and will generate an interrupt request if INTENSET.BOD33DET is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the BOD33 Detection interrupt flag. Bit 9 – BOD33RDY BOD33 Ready This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the BOD33 Ready bit in the Status register (PCLKSR.BOD33RDY) and will generate an interrupt request if INTENSET.BOD33RDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the BOD33 Ready interrupt flag. Bit 8 – DFLLRCS DFLL Reference Clock Stopped This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the DFLL Reference Clock Stopped bit in the Status register (PCLKSR.DFLLRCS) and will generate an interrupt request if INTENSET.DFLLRCS is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the DFLL Reference Clock Stopped interrupt flag. Bit 7 – DFLLLCKC DFLL Lock Coarse This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the DFLL Lock Coarse bit in the Status register (PCLKSR.DFLLLCKC) and will generate an interrupt request if INTENSET.DFLLLCKC is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the DFLL Lock Coarse interrupt flag. Bit 6 – DFLLLCKF DFLL Lock Fine This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the DFLL Lock Fine bit in the Status register (PCLKSR.DFLLLCKF) and will generate an interrupt request if INTENSET.DFLLLCKF is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the DFLL Lock Fine interrupt flag. Bit 5 – DFLLOOB DFLL Out Of Bounds This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the DFLL Out Of Bounds bit in the Status register (PCLKSR.DFLLOOB) and will generate an interrupt request if INTENSET.DFLLOOB is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the DFLL Out Of Bounds interrupt flag. Bit 4 – DFLLRDY DFLL Ready This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the DFLL Ready bit in the Status register (PCLKSR.DFLLRDY) and will generate an interrupt request if INTENSET.DFLLRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the DFLL Ready interrupt flag. Bit 3 – OSC8MRDY OSC8M Ready This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the OSC8M Ready bit in the Status register (PCLKSR.OSC8MRDY) and will generate an interrupt request if INTENSET.OSC8MRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the OSC8M Ready interrupt flag. Bit 2 – OSC32KRDY OSC32K Ready This flag is cleared by writing a one to it. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 184

This flag is set on a zero-to-one transition of the OSC32K Ready bit in the Status register (PCLKSR.OSC32KRDY) and will generate an interrupt request if INTENSET.OSC32KRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the OSC32K Ready interrupt flag. Bit 1 – XOSC32KRDY XOSC32K Ready This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the XOSC32K Ready bit in the Status register (PCLKSR.XOSC32KRDY) and will generate an interrupt request if INTENSET.XOSC32KRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the XOSC32K Ready interrupt flag. Bit 0 – XOSCRDY XOSC Ready This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the XOSC Ready bit in the Status register (PCLKSR.XOSCRDY) and will generate an interrupt request if INTENSET.XOSCRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the XOSC Ready interrupt flag. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 185

17.8.4 Power and Clocks Status

Name: PCLKSR Offset: 0x0C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DPLLLTO DPLLLCKF Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DPLLLCKR B33SRDY BOD33DET BOD33RDY DFLLRCS Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 17 – DPLLLTO DPLL Lock Timeout Value Description 0 DPLL Lock time-out not detected. 1 DPLL Lock time-out detected. Bit 16 – DPLLLCKF DPLL Lock Fall Value Description 0 DPLL Lock fall edge not detected. 1 DPLL Lock fall edge detected. Bit 15 – DPLLLCKR DPLL Lock Rise Value Description 0 DPLL Lock rise edge not detected. 1 DPLL Lock fall edge detected. Bit 11 – B33SRDY BOD33 Synchronization Ready Value Description 0 BOD33 synchronization is complete. 1 BOD33 synchronization is ongoing. Bit 10 – BOD33DET BOD33 Detection Value Description 0 No BOD33 detection. 1 BOD33 has detected that the I/O power supply is going below the BOD33 reference value. Bit 9 – BOD33RDY BOD33 Ready Value Description 0 BOD33 is not ready. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 186

1 BOD33 is ready. Bit 8 – DFLLRCS DFLL Reference Clock Stopped Value Description 0 DFLL reference clock is running. 1 DFLL reference clock has stopped. Bit 7 – DFLLLCKC DFLL Lock Coarse Value Description 0 No DFLL coarse lock detected. 1 DFLL coarse lock detected. Bit 6 – DFLLLCKF DFLL Lock Fine Value Description 0 No DFLL fine lock detected. 1 DFLL fine lock detected. Bit 5 – DFLLOOB DFLL Out Of Bounds Value Description 0 No DFLL Out Of Bounds detected. 1 DFLL Out Of Bounds detected. Bit 4 – DFLLRDY DFLL Ready This bit is cleared when the synchronization of registers between clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. Value Description 0 The Synchronization is ongoing. 1 The Synchronization is complete. Bit 3 – OSC8MRDY OSC8M Ready Value Description 0 OSC8M is not ready. 1 OSC8M is stable and ready to be used as a clock source. Bit 2 – OSC32KRDY OSC32K Ready Value Description 0 OSC32K is not ready. 1 OSC32K is stable and ready to be used as a clock source. Bit 1 – XOSC32KRDY XOSC32K Ready Value Description 0 XOSC32K is not ready. 1 XOSC32K is stable and ready to be used as a clock source. Bit 0 – XOSCRDY XOSC Ready Value Description 0 XOSC is not ready. 1 XOSC is stable and ready to be used as a clock source. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 187

17.8.5 External Multipurpose Crystal Oscillator (XOSC) Control

Name: XOSC Offset: 0x10 Reset: 0x0080 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 STARTUP[3:0] AMPGC GAIN[2:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY XTALEN ENABLE Access R/W R/W R/W R/W Reset 1 0 0 0 Bits 15:12 – STARTUP[3:0] Start-Up Time These bits select start-up time for the oscillator according to the table below. The OSCULP32K oscillator is used to clock the start-up counter. STARTUP[3:0] Number of OSCULP32K Clock Cycles Number of XOSC Clock Cycles Approximate Equivalent Time(1)(2)(3) 0x0 1 3 31 μs 0x1 2 3 61 μs 0x2 4 3 122 μs 0x3 8 3 244 μs 0x4 16 3 488 μs 0x5 32 3 977 μs 0x6 64 3 1953 μs 0x7 128 3 3906 μs 0x8 256 3 7813 μs 0x9 512 3 15625 μs 0xA 1024 3 31250 μs 0xB 2048 3 62500 μs 0xC 4096 3 125000 μs 0xD 8192 3 250000 μs 0xE 16384 3 500000 μs 0xF 32768 3 1000000 μs Notes: 1. Number of cycles for the start-up counter 2. Number of cycles for the synchronization delay, before PCLKSR.XOSCRDY is set. 3. Actual start-up time is n OSCULP32K cycles + 3 XOSC cycles, but given the time neglects the three XOSC cycles. Bit 11 – AMPGC Automatic Amplitude Gain Control Note: The configuration of the oscillator gain is mandatory even if AMPGC feature is enabled at startup. Value Description

0 The automatic amplitude gain control is disabled

1 The automatic amplitude gain control is enabled. Amplitude gain will be automatically adjusted during Crystal Oscillator operation. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 188

Bits 10:8 – GAIN[2:0] Oscillator Gain These bits select the gain for the oscillator. The listed maximum frequencies are recommendations, and might vary based on capacitive load and crystal characteristics. These bits must be properly configured even when the Automatic Amplitude Gain Control is active. GAIN[2:0] Recommended Max Frequency 0x0 2 MHz 0x1 4 MHz 0x2 8 MHz 0x3 16 MHz 0x4 30 MHz 0x5-0x7 Reserved Bit 7 – ONDEMAND On Demand Control The On Demand operation mode allows an oscillator to be enabled or disabled, depending on peripheral clock requests. In On Demand operation mode (i.e., if the XOSC.ONDEMAND bit has been previously written to one), the oscillator will be running only when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source, the oscillator will be in a disabled state. If On Demand is disabled, the oscillator will always be running when enabled. In Standby Sleep mode, the On Demand operation is still active if the XOSC.RUNSTDBY bit is one. If XOSC.RUNSTDBY is zero, the oscillator is disabled. Value Description

0 The oscillator is always on, if enabled

1 The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is disabled if no peripheral is requesting the clock source. Bit 6 – RUNSTDBY Run in Standby This bit controls how the XOSC behaves during Standby Sleep mode: Value Description 0 The oscillator is disabled in Standby Sleep mode. 1 The oscillator is not stopped in Standby Sleep mode. If XOSC.ONDEMAND is one, the clock source will be running when a peripheral is requesting the clock. If XOSC.ONDEMAND is zero, the clock source will always be running in Standby Sleep mode. Bit 2 – XTALEN Crystal Oscillator Enable This bit controls the connections between the I/O pads and the external clock or crystal oscillator: Value Description 0 External clock connected on XIN. XOUT can be used as general purpose I/O.

1 Crystal connected to XIN/XOUT

Bit 1 – ENABLE Oscillator Enable Value Description

0 The oscillator is disabled

1 The oscillator is enabled

17.8.6 32kHz External Crystal Oscillator (XOSC32K) Control Name: XOSC32K Offset: 0x14 Reset: 0x0080 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 WRTLOCK STARTUP[2:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY AAMPEN EN32K XTALEN ENABLE Access R/W R/W R/W R/W R/W R/W Reset 1 0 0 0 0 0 Bit 12 – WRTLOCK Write Lock This bit locks the XOSC32K register for future writes to fix the XOSC32K configuration. Value Description 0 The XOSC32K configuration is not locked. 1 The XOSC32K configuration is locked. Bits 10:8 – STARTUP[2:0] Oscillator Start-Up Time These bits select the start-up time for the oscillator. The OSCULP32K oscillator is used to clock the start-up counter. Table 17-6. Start-Up Time for 32kHz External Crystal Oscillator STARTUP[2:0] Number of OSCULP32K Clock Cycles Number of XOSC32K Clock Cycles Approximate Equivalent Time (OSCULP = 32kHz)(1)(2)(3) 0x0 1 3 122μs 0x1 32 3 1068μs 0x2 2048 3 62592μs 0x3 4096 3 125092μs 0x4 16384 3 500092μs 0x5 32768 3 1000092μs 0x6 65536 3 2000092μs 0x7 131072 3 4000092μs Notes: 1. Number of cycles for the start-up counter. 2. Number of cycles for the synchronization delay, before PCLKSR.XOSC32KRDY is set. 3. Start-up time is n OSCULP32K cycles + 3 XOSC32K cycles. Bit 7 – ONDEMAND On Demand Control The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock requests. In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the oscillator will only be running when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source, the oscillator will be in a disabled state. If On Demand is disabled the oscillator will always be running when enabled. In standby sleep mode, the On Demand operation is still active if the XOSC32K.RUNSTDBY bit is one. If XOSC32K.RUNSTDBY is zero, the oscillator is disabled. Value Description 0 The oscillator is always on, if enabled. 1 The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is disabled if no peripheral is requesting the clock source. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 190

Bit 6 – RUNSTDBY Run in Standby This bit controls how the XOSC32K behaves during standby sleep mode: Value Description 0 The oscillator is disabled in standby sleep mode. 1 The oscillator is not stopped in standby sleep mode. If XOSC32K.ONDEMAND is one, the clock source will be running when a peripheral is requesting the clock. If XOSC32K.ONDEMAND is zero, the clock source will always be running in standby sleep mode. Bit 5 – AAMPEN Automatic Amplitude Control Enable Value Description 0 The automatic amplitude control for the crystal oscillator is disabled. 1 The automatic amplitude control for the crystal oscillator is enabled. Bit 3 – EN32K 32kHz Output Enable Value Description 0 The 32kHz output is disabled. 1 The 32kHz output is enabled. Bit 2 – XTALEN Crystal Oscillator Enable This bit controls the connections between the I/O pads and the external clock or crystal oscillator: Value Description 0 External clock connected on XIN32. XOUT32 can be used as general-purpose I/O. 1 Crystal connected to XIN32/XOUT32. Bit 1 – ENABLE Oscillator Enable Value Description 0 The oscillator is disabled. 1 The oscillator is enabled. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 191

17.8.7 32kHz Internal Oscillator (OSC32K) Control Name: OSC32K Offset: 0x18 Reset: 0x003F0080 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 CALIB[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 WRTLOCK STARTUP[2:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY EN32K ENABLE Access R/W R/W R/W R/W Reset 1 0 0 0 Bits 22:16 – CALIB[6:0] Oscillator Calibration These bits control the oscillator calibration. This value must be written by the user. Factory calibration values can be loaded from the non-volatile memory. Bit 12 – WRTLOCK Write Lock This bit locks the OSC32K register for future writes to fix the OSC32K configuration. Value Description 0 The OSC32K configuration is not locked. 1 The OSC32K configuration is locked. Bits 10:8 – STARTUP[2:0] Oscillator Start-Up Time These bits select start-up time for the oscillator. The OSCULP32K oscillator is used as input clock to the startup counter. Table 17-7. Start-Up Time for 32kHz Internal Oscillator STARTUP[2:0] Number of OSC32K clock cycles Approximate Equivalent Time (OSCULP= 32 kHz)(1)(2)(3) 0x0 3 92μs 0x1 4 122μs 0x2 6 183μs 0x3 10 305μs 0x4 18 549μs 0x5 34 1038μs 0x6 66 2014μs 0x7 130 3967μs Notes: 1. Number of cycles for the start-up counter. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 192

Number of cycles for the synchronization delay, before PCLKSR.OSC32KRDY is set. 3. Start-up time is n OSC32K cycles + 2 OSC32K cycles. Bit 7 – ONDEMAND On Demand Control The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock requests. In On Demand operation mode, that is, if the ONDEMAND bit has been previously written to one, the oscillator will only be running when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source, the oscillator will be in a disabled state. If On Demand is disabled the oscillator will always be running when enabled. In standby sleep mode, the On Demand operation is still active if the OSC32K.RUNSTDBY bit is one. If OSC32K.RUNSTDBY is zero, the oscillator is disabled. Value Description 0 The oscillator is always on, if enabled. 1 The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is disabled if no peripheral is requesting the clock source. Bit 6 – RUNSTDBY Run in Standby This bit controls how the OSC32K behaves during Standby Sleep mode: Value Description 0 The oscillator is disabled in standby sleep mode. 1 The oscillator is not stopped in standby sleep mode. If OSC32K.ONDEMAND is one, the clock source will be running when a peripheral is requesting the clock. If OSC32K.ONDEMAND is zero, the clock source will always be running in standby sleep mode. Bit 2 – EN32K 32 kHz Output Enable Value Description 0 The 32 kHz output is disabled. 1 The 32 kHz output is enabled. Bit 1 – ENABLE Oscillator Enable Value Description 0 The oscillator is disabled. 1 The oscillator is enabled. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 193

17.8.8 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control Name: OSCULP32K Offset: 0x1C Reset: 0xXX Property: Write-Protected Bit 7 6 5 4 3 2 1 0 WRTLOCK CALIB[4:0] Access R/W R/W R/W R/W R/W R/W Reset 0 x x x x x Bit 7 – WRTLOCK Write Lock This bit locks the OSCULP32K register for future writes to fix the OSCULP32K configuration. Value Description 0 The OSCULP32K configuration is not locked. 1 The OSCULP32K configuration is locked. Bits 4:0 – CALIB[4:0] Oscillator Calibration These bits control the oscillator calibration. These bits are loaded from Flash Calibration at startup. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 194

17.8.9 8MHz Internal Oscillator (OSC8M) Control Name: OSC8M Offset: 0x20 Reset: 0xXXXX0382 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 FRANGE[1:0] CALIB[11:8] Access R/W R/W R/W R/W R/W R/W Reset x x 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CALIB[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 x Bit 15 14 13 12 11 10 9 8 PRESC[1:0] Access R/W R/W Reset 1 1 Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY ENABLE Access R/W R/W R/W Reset 1 0 1 Bits 31:30 – FRANGE[1:0] Oscillator Frequency Range These bits control the oscillator frequency range according to the table below. These bits are loaded from Flash Calibration at startup. FRANGE[1:0] Description 0x0 4 to 6MHz 0x1 6 to 8MHz 0x2 8 to 11MHz 0x3 11 to 15MHz Bits 27:16 – CALIB[11:0] Oscillator Calibration These bits control the oscillator calibration. The calibration field is split in two: CALIB[11:6] is for temperature calibration CALIB[5:0] is for overall process calibration These bits are loaded from Flash Calibration at startup. Bits 9:8 – PRESC[1:0] Oscillator Prescaler These bits select the oscillator prescaler factor setting according to the table below. PRESC[1:0] Description 0x0 1 0x1 2 0x2 4 0x3 8 Bit 7 – ONDEMAND On Demand Control The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock requests. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 195

In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the oscillator will only be running when requested by a peripheral. If there is no peripheral requesting the oscillator's clock source, the oscillator will be in a disabled state. If On Demand is disabled the oscillator will always be running when enabled. In standby sleep mode, the On Demand operation is still active if the OSC8M.RUNSTDBY bit is one. If OSC8M.RUNSTDBY is zero, the oscillator is disabled. Value Description 0 The oscillator is always on, if enabled. 1 The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is disabled if no peripheral is requesting the clock source. Bit 6 – RUNSTDBY Run in Standby This bit controls how the OSC8M behaves during standby sleep mode: Value Description 0 The oscillator is disabled in standby sleep mode. 1 The oscillator is not stopped in standby sleep mode. If OSC8M.ONDEMAND is one, the clock source will be running when a peripheral is requesting the clock. If OSC8M.ONDEMAND is zero, the clock source will always be running in standby sleep mode. Bit 1 – ENABLE Oscillator Enable The user must ensure that the OSC8M is fully disabled before enabling it, and that the OSC8M is fully enabled before disabling it by reading OSC8M.ENABLE. Value Description 0 The oscillator is disabled or being enabled. 1 The oscillator is enabled or being disabled. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 196

17.8.10 DFLL48M Control

Name: DFLLCTRL Offset: 0x24 Reset: 0x0080 Property: Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 WAITLOCK BPLCKC QLDIS CCDIS Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ONDEMAND USBCRM LLAW STABLE MODE ENABLE Access R/W R/W R/W R/W R/W R/W Reset 1 0 0 0 0 0 Bit 11 – WAITLOCK Wait Lock This bit controls the DFLL output clock, depending on lock status: Value Description

0 Output clock before the DFLL is locked

1 Output clock when DFLL is locked

Bit 10 – BPLCKC Bypass Coarse Lock This bit controls the coarse lock procedure: Value Description

0 Bypass coarse lock is disabled

1 Bypass coarse lock is enabled

Bit 9 – QLDIS Quick Lock Disable Value Description

0 Quick Lock is enabled

1 Quick Lock is disabled

Bit 8 – CCDIS Chill Cycle Disable Value Description

0 Chill Cycle is enabled

1 Chill Cycle is disabled

Bit 7 – ONDEMAND On Demand Control The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock requests. In On Demand operation mode (i.e., if the ONDEMAND bit has been previously written to one), the oscillator will only be running when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source, the oscillator will be in a disabled state. If On Demand is disabled the oscillator will always be running when enabled. In Standby Sleep mode, the On Demand operation is still active if the DFLLCTRL.RUNSTDBY bit is one. If DFLLCTRL.RUNSTDBY is zero, the oscillator is disabled. Value Description 1 The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is disabled if no peripheral is requesting the clock source. Bit 5 – USBCRM USB Clock Recovery Mode Value Description

0 USB Clock Recovery mode is disabled

1 USB Clock Recovery mode is enabled

Bit 4 – LLAW Lose Lock After Wake Value Description

0 Locks will not be lost after waking up from Sleep modes if the DFLL clock has been stopped

1 Locks will be lost after waking up from Sleep modes if the DFLL clock has been stopped

Bit 3 – STABLE Stable DFLL Frequency Value Description

0 FINE calibration tracks changes in output frequency

1 FINE calibration register value will be fixed after a fine lock

Bit 2 – MODE Operating Mode Selection Value Description

0 The DFLL operates in open-loop operation

1 The DFLL operates in closed-loop operation

Bit 1 – ENABLE DFLL Enable Due to synchronization, there is a delay from updating the register until the peripheral is enabled/disabled. The value written to DFLLCTRL.ENABLE will read back immediately after written. Value Description

0 The DFLL oscillator is disabled

1 The DFLL oscillator is enabled

17.8.11 DFLL48M Value

Name: DFLLVAL Offset: 0x28 Reset: 0x00000000 Property: Read-Synchronized, Write-Protected Bit 31 30 29 28 27 26 25 24 DIFF[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIFF[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COARSE[5:0] FINE[9:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FINE[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:16 – DIFF[15:0] Multiplication Ratio Difference In closed-loop mode (DFLLCTRL.MODE is written to one), this bit group indicates the difference between the ideal number of DFLL cycles and the counted number of cycles. This value is not updated in open-loop mode, and should be considered invalid in that case. Bits 15:10 – COARSE[5:0] Coarse Value Set the value of the Coarse Calibration register. In closed-loop mode, this field is read-only. Bits 9:0 – FINE[9:0] Fine Value Set the value of the Fine Calibration register. In closed-loop mode, this field is read-only. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 199

17.8.12 DFLL48M Multiplier

Name: DFLLMUL Offset: 0x2C Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 CSTEP[5:0] FSTEP[9:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 FSTEP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 MUL[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MUL[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:26 – CSTEP[5:0] Coarse Maximum Step This bit group indicates the maximum step size allowed during coarse adjustment in closed-loop mode. When adjusting to a new frequency, the expected output frequency overshoot depends on this step size. Bits 25:16 – FSTEP[9:0] Fine Maximum Step This bit group indicates the maximum step size allowed during fine adjustment in closed-loop mode. When adjusting to a new frequency, the expected output frequency overshoot depends on this step size. Bits 15:0 – MUL[15:0] DFLL Multiply Factor This field determines the ratio of the CLK_DFLL output frequency to the CLK_DFLL_REF input frequency. Writing to the MUL bits will cause locks to be lost and the fine calibration value to be reset to its midpoint. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 200

17.8.13 DFLL48M Synchronization

Name: DFLLSYNC Offset: 0x30 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 READREQ Access W Reset 0 Bit 7 – READREQ Read Request To be able to read the current value of DFLLVAL in closed-loop mode, this bit should be written to one. The updated value is available in DFLLVAL when PCLKSR.DFLLRDY is set. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 201

17.8.14 3.3V Brown-Out Detector (BOD33) Control Name: BOD33 Offset: 0x34 Reset: 0x00XX00XX Property: Write-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 LEVEL[5:0] Access R/W R/W R/W R/W R/W R/W Reset x x x x x x Bit 15 14 13 12 11 10 9 8 PSEL[3:0] CEN MODE Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RUNSTDBY ACTION[1:0] HYST ENABLE Access R/W R/W R/W R/W R/W Reset 0 x x x x Bits 21:16 – LEVEL[5:0] BOD33 Threshold Level This field sets the triggering voltage threshold for the BOD33. See the Electrical Characteristics for actual voltage levels. Note that any change to the LEVEL field of the BOD33 register should be done when the BOD33 is disabled in order to avoid spurious resets or interrupts. These bits are loaded from Flash User Row at start-up. Refer to NVM User Row Mapping for more details. Bits 15:12 – PSEL[3:0] Prescaler Select Selects the prescaler divide-by output for the BOD33 sampling mode according to the table below. The input clock comes from the OSCULP32K 1kHz output. PSEL[3:0] Name Description 0x0 DIV2 Divide clock by 2 0x1 DIV4 Divide clock by 4 0x2 DIV8 Divide clock by 8 0x3 DIV16 Divide clock by 16 0x4 DIV32 Divide clock by 32 0x5 DIV64 Divide clock by 64 0x6 DIV128 Divide clock by 128 0x7 DIV256 Divide clock by 256 0x8 DIV512 Divide clock by 512 0x9 DIV1K Divide clock by 1024 0xA DIV2K Divide clock by 2048 0xB DIV4K Divide clock by 4096 0xC DIV8K Divide clock by 8192 0xD DIV16K Divide clock by 16384 0xE DIV32K Divide clock by 32768 0xF DIV64K Divide clock by 65536 SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 202

Bit 9 – CEN Clock Enable Writing a zero to this bit will stop the BOD33 sampling clock. Writing a one to this bit will start the BOD33 sampling clock. Value Description 0 The BOD33 sampling clock is either disabled and stopped, or enabled but not yet stable. 1 The BOD33 sampling clock is either enabled and stable, or disabled but not yet stopped. Bit 8 – MODE Operation Mode Value Description 0 The BOD33 operates in continuous mode. 1 The BOD33 operates in sampling mode. Bit 6 – RUNSTDBY Run in Standby Value Description 0 The BOD33 is disabled in standby sleep mode. 1 The BOD33 is enabled in standby sleep mode. Bits 4:3 – ACTION[1:0] BOD33 Action These bits are used to select the BOD33 action when the supply voltage crosses below the BOD33 threshold. These bits are loaded from Flash User Row at start-up. ACTION[1:0] Name Description 0x0 NONE No action 0x1 RESET The BOD33 generates a reset 0x2 INTERRUPT The BOD33 generates an interrupt 0x3 Reserved Bit 2 – HYST Hysteresis This bit indicates whether hysteresis is enabled for the BOD33 threshold voltage: This bit is loaded from Flash User Row at start-up. Refer to NVM User Row Mapping for more details. Value Description 0 No hysteresis. 1 Hysteresis enabled. Bit 1 – ENABLE Enable This bit is loaded from Flash User Row at startup. Refer to NVM User Row Mapping for more details. Value Description 0 BOD33 is disabled. 1 BOD33 is enabled. Related Links 37. Electrical Characteristics at 85℃ SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 203

17.8.15 Voltage Regulator System (VREG) Control

Name: VREG Offset: 0x3C Reset: 0x0X02 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 FORCELDO Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 RUNSTDBY ENABLE Access R/W R/W Reset 0 1 Bit 13 – FORCELDO Force LDO Voltage Regulator Value Description

0 The voltage regulator is in low-power and low-drive configuration in Standby Sleep mode

1 The voltage regulator is in low-power and high-drive configuration in Standby Sleep mode

Bit 6 – RUNSTDBY Run in Standby Value Description

0 The voltage regulator is in low-power configuration in Standby Sleep mode

1 The voltage regulator is in normal configuration in Standby Sleep mode

17.8.16 Voltage References System (VREF) Control

Name: VREF Offset: 0x40 Reset: 0x0XXX0000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 CALIB[10:8] Access R/W R/W R/W Reset x x x Bit 23 22 21 20 19 18 17 16 CALIB[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 BGOUTEN TSEN Access R/W R/W Reset 0 0 Bits 26:16 – CALIB[10:0] Bandgap Voltage Generator Calibration These bits are used to calibrate the output level of the bandgap voltage reference. These bits are loaded from Flash Calibration Row at start-up. Bit 2 – BGOUTEN Bandgap Output Enable Value Description

0 The bandgap output is not available as an ADC input channel

1 The bandgap output is routed to an ADC input channel

Bit 1 – TSEN Temperature Sensor Enable(1) Value Description

0 Temperature sensor is disabled

1 Temperature sensor is enabled and routed to an ADC input channel

17.8.17 DPLL Control A

Name: DPLLCTRLA Offset: 0x44 Reset: 0x80 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY ENABLE Access R/W R/W R/W Reset 1 0 0 Bit 7 – ONDEMAND On Demand Clock Activation Value Description 0 The DPLL is always on when enabled. 1 The DPLL is activated only when a peripheral request the DPLL as a source clock. The DPLLCTRLA.ENABLE bit must be one to validate that operation, otherwise the peripheral request has no effect. Bit 6 – RUNSTDBY Run in Standby Value Description 0 The DPLL is disabled in standby sleep mode. 1 The DPLL is not stopped in standby sleep mode. Bit 1 – ENABLE DPLL Enable The software operation of enabling or disabling the DPLL takes a few clock cycles, so check the DPLLSTATUS.ENABLE status bit to identify when the DPLL is successfully activated or disabled. Value Description 0 The DPLL is disabled. 1 The DPLL is enabled. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 206

17.8.18 DPLL Ratio Control

Name: DPLLRATIO Offset: 0x48 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 LDRFRAC[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 LDR[11:8] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 19:16 – LDRFRAC[3:0] Loop Divider Ratio Fractional Part Write this field with the fractional part of the frequency multiplier. Bits 11:0 – LDR[11:0] Loop Divider Ratio Write this field with the integer part of the frequency multiplier. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 207

17.8.19 DPLL Control B

Name: DPLLCTRLB Offset: 0x4C Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 DIV[10:8] Access R/W R/W R/W Reset 0 0 0 Bit 23 22 21 20 19 18 17 16 DIV[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 LBYPASS LTIME[2:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 REFCLK[1:0] WUF LPEN FILTER[1:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bits 26:16 – DIV[10:0] Clock Divider Bit 12 – LBYPASS Lock Bypass Value Description 0 Normal Mode: the CLK_FDPLL96M is turned off when lock signal is low. 1 Lock Bypass Mode: the CLK_FDPLL96M is always running, lock is irrelevant. Bits 10:8 – LTIME[2:0] Lock Time These bits select Lock Timeout. LTIME[2:0] Name Description 0x0 DEFAULT No time-out 0x1-0x3 Reserved 0x4 8MS Time-out if no lock within 8 ms 0x5 9MS Time-out if no lock within 9 ms 0x6 10MS Time-out if no lock within 10 ms 0x7 11MS Time-out if no lock within 11 ms Bits 5:4 – REFCLK[1:0] Reference Clock Selection These bits select the CLK_FDPLL96M_REF source. REFCLK[1:0] Name Description 0x0 XOSC32 XOSC32 clock reference 0x1 XOSC XOSC clock reference 0x2 GCLK_DPLL GCLK_DPLL clock reference 0x3 Reserved SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 208

Bit 3 – WUF Wake Up Fast Value Description 0 DPLL CK output is gated until complete startup time and lock time. 1 DPLL CK output is gated until startup time only. Bit 2 – LPEN Low-Power Enable Value Description 0 The time to digital converter is selected.

1 The time to digital converter is not selected, this will improve power consumption but increase the

output jitter. Bits 1:0 – FILTER[1:0] Proportional Integral Filter Selection These bits select the DPLL filter type. FILTER[1:0] Name Description 0x0 DEFAULT Default filter mode 0x1 LBFILT Low bandwidth filter 0x2 HBFILT High bandwidth filter 0x3 HDFILT High damping filter SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 209

17.8.20 DPLL Status

Name: DPLLSTATUS Offset: 0x50 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 DIV ENABLE CLKRDY LOCK Access R R R R Reset 0 0 0 0 Bit 3 – DIV Divider Enable Value Description 0 The reference clock divider is disabled. 1 The reference clock divider is enabled. Bit 2 – ENABLE DPLL Enable Value Description 0 The DPLL is disabled. 1 The DPLL is enabled. Bit 1 – CLKRDY Output Clock Ready Value Description

0 The DPLL output clock is off

1 The DPLL output clock in on. Bit 0 – LOCK DPLL Lock Status Value Description 0 The DPLL Lock signal is cleared. 1 The DPLL Lock signal is asserted. SAM D21/DA1 Family SYSCTRL – System Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 210

WDT – Watchdog Timer

18.1 Overview

The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover from error situations such as runaway or deadlocked code. The WDT is configured to a predefined time-out period, and is constantly running when enabled. If the WDT is not cleared within the time-out period, it will issue a system reset. An early-warning interrupt is available to indicate an upcoming watchdog time-out condition. The window mode makes it possible to define a time slot (or window) inside the total time-out period during which the WDT must be cleared. If the WDT is cleared outside this window, either too early or too late, a system reset will be issued. Compared to the normal mode, this can also catch situations where a code error causes the WDT to be cleared frequently. When enabled, the WDT will run in active mode and all sleep modes. It is asynchronous and runs from a CPU- independent clock source. The WDT will continue operation and issue a system reset or interrupt even if the main clocks fail.

18.2 Features

Issues a system reset if the Watchdog Timer is not cleared before its time-out period
Early Warning interrupt generation
Asynchronous operation from dedicated oscillator
Two types of operation: – Normal mode – Window mode
Selectable time-out periods – From 8 cycles to 16,000 cycles in normal mode – From 16 cycles to 32,000 cycles in window mode
Always-on capability

18.3 Block Diagram

Figure 18-1. WDT Block Diagram GCLK_WDT COUNT Reset PER/WINDOW/EWOFFSET CLEAR 0xA5 Early Warning Interrupt SAM D21/DA1 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 211

18.4 Signal Description

Not applicable.

18.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

18.5.1 I/O Lines

Not applicable.

18.5.2 Power Management

The WDT can continue to operate in any sleep mode where the selected source clock is running. The WDT interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes. Related Links 16. PM – Power Manager

18.5.3 Clocks

The WDT bus clock (CLK_WDT_APB) is enabled by default, and can be enabled and disabled in the Power Manager. Refer to PM – Power Manager for details. A generic clock (GCLK_WDT) is required to clock the WDT. This clock must be configured and enabled in the Generic Clock Controller before using the WDT. Refer to GCLK – Generic Clock Controller for details. This generic clock is asynchronous to the user interface clock (CLK_WDT_APB). Due to this asynchronicity, accessing certain registers will require synchronization between the clock domains. Refer to Synchronization for further details. GCLK_WDT is intended to be sourced from the clock of the internal ultra-low-power (ULP) oscillator. Due to the ultralow- power design, the oscillator is not very accurate, and so the exact time-out period may vary from device to device. This variation must be kept in mind when designing software that uses the WDT to ensure that the time-out periods used are valid for all devices. For more information on ULP oscillator accuracy, consult the Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics. GCLK_WDT can also be clocked from other sources if a more accurate clock is needed, but at the cost of higher power consumption. Related Links 16. PM – Power Manager 15. GCLK - Generic Clock Controller 17.6.5 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Operation

18.6.5 Synchronization

18.5.4 DMA

Not applicable.

18.5.5 Interrupts

The interrupt request line is connected to the interrupt controller. Using the WDT interrupt(s) requires the interrupt controller to be configured first. Related Links

18.5.6 Events

18.5.7 Debug Operation

When the CPU is halted in debug mode the WDT will halt normal operation.

18.5.8 Register Access Protection

Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following:

Interrupt Flag Status and Clear register (INTFLAG) Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. Related Links

18.5.9 Analog Connections

Not applicable.

18.6 Functional Description

18.6.1 Principle of Operation

The Watchdog Timer (WDT) is a system for monitoring correct program operation, making it possible to recover from error situations such as runaway code, by issuing a Reset. When enabled, the WDT is a constantly running timer that is configured to a predefined time-out period. Before the end of the time-out period, the WDT should be set back, or else, a system Reset is issued. The WDT has two modes of operation, Normal mode and Window mode. Both modes offer the option of Early Warning interrupt generation. The description for each of the basic modes is given below. The settings in the Control register (CTRL) and the Interrupt Enable register (handled by INTENCLR/SET) determine the mode of operation: Table 18-1. WDT Operating Modes CTRL.ENABLE CTRL.WEN INTENSET.EW Mode 0 x x Stopped 1 0 0 Normal 1 0 1 Normal with Early Warning interrupt 1 1 0 Window 1 1 1 Window with Early Warning interrupt

18.6.2 Basic Operation

18.6.2.1 Initialization

The following bits are enable-protected:

Window Mode Enable in the Control register (CTRL.WEN)
Always-On in the Control register (CTRL-ALWAYSON) The following registers are enable-protected:
Configuration register (CONFIG)
Early Warning Interrupt Control register (EWCTRL) Any writes to these bits or registers when the WDT is enabled or is being enabled (CTRL.ENABLE=1) will be discarded. Writes to these registers while the WDT is being disabled will be completed after the disabling is complete. Enable-protection is denoted by the Enable-Protected property in the register description. Initialization of the WDT can be done only while the WDT is disabled. The WDT is configured by defining the required Time-Out Period bits in the Configuration register (CONFIG.PER). If window-mode operation is required, the SAM D21/DA1 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 213

Window Enable bit in the Control register (CTRL.WEN) must be written to one and the Window Period bits in the Configuration register (CONFIG.WINDOW) must be defined. Normal Mode

Defining the required Time-Out Period bits in the Configuration register (CONFIG.PER). Normal Mode with Early Warning interrupt
Defining the required Time-Out Period bits in the Configuration register (CONFIG.PER).
Defining Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register (EWCTRL. EWOFFSET).
Setting Early Warning Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.EW). Window Mode
Defining Time-Out Period bits in the Configuration register (CONFIG.PER).
Defining Window Mode Time-Out Period bits in the Configuration register (CONFIG.WINDOW).
Setting Window Enable bit in the Control register (CTRL.WEN). Window Mode with Early Warning interrupt
Defining Time-Out Period bits in the Configuration register (CONFIG.PER).
Defining Window Mode Time-Out Period bits in the Configuration register (CONFIG.WINDOW).
Setting Window Enable bit in the Control register (CTRL.WEN).
Defining Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register (EWCTRL. EWOFFSET).
Setting Early Warning Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.EW).

18.6.2.2 Configurable Reset Values

After a Power-on Reset, some registers will be loaded with initial values from the NVM User Row. Refer to NVM User Row Mapping for more details. This encompasses the following bits and bit groups:

Enable bit in the Control register, CTRL.ENABLE
Always-On bit in the Control register, CTRL.ALWAYSON
Watchdog Timer Windows Mode Enable bit in the Control register, CTRL.WEN
Watchdog Timer Windows Mode Time-Out Period bits in the Configuration register, CONFIG.WINDOW
Time-Out Period in the Configuration register, CONFIG.PER
Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register, EWCTRL.EWOFFSET For more information about fuse locations, see NVM User Row Mapping. Related Links

18.6.2.3 Enabling and Disabling

The WDT is enabled by writing a '1' to the Enable bit in the Control register (CTRL.ENABLE). The WDT is disabled by writing a '0' to CTRL.ENABLE. The WDT can be disabled only if the Always-On bit in the Control register (CTRL.ALWAYSON) is '0'.

18.6.2.4 Normal Mode

In Normal mode operation, the length of a time-out period is configured in CONFIG.PER. The WDT is enabled by writing a '1' to the Enable bit in the Control register (CTRL.ENABLE). Once enabled, the WDT will issue a system reset if a time-out occurs. This can be prevented by clearing the WDT at any time during the time-out period. The WDT is cleared and a new WDT time-out period is started by writing 0xA5 to the Clear register (CLEAR). Writing any other value than 0xA5 to CLEAR will issue an immediate system reset. There are 12 possible WDT time-out (TOWDT) periods, selectable from 8ms to 16s. SAM D21/DA1 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 214

By default, the early warning interrupt is disabled. If it is desired, the Early Warning Interrupt Enable bit in the Interrupt Enable register (INTENSET.EW) must be written to '1'. The Early Warning Interrupt is disabled again by writing a '1' to the Early Warning Interrupt bit in the Interrupt Enable Clear register (INTENCLR.EW). If the Early Warning Interrupt is enabled, an interrupt is generated prior to a WDT time-out condition. In Normal mode, the Early Warning Offset bits in the Early Warning Interrupt Control register, EWCTRL.EWOFFSET, define the time when the early warning interrupt occurs. The Normal mode operation is illustrated in the figure Normal-Mode Operation. Figure 18-2. Normal-Mode Operation 5 10 15 20 25 30 35 WDT Timeout Early Warning Interrupt Timely WDT Clear t[ms] TOWDT System Reset WDT Count PER[3:0] = 1 EWOFFSET[3:0] = 0

18.6.2.5 Window Mode

In Window mode operation, the WDT uses two different time specifications: the WDT can only be cleared by writing 0xA5 to the CLEAR register after the closed window time-out period (TOWDTW), during the subsequent Normal time-out period (TOWDTW). If the WDT is cleared before the time window opens (before TOWDTW is over), the WDT will issue a system reset. Both parameters TOWDTW and TOWDT are periods in a range from 8ms to 16s, so the total duration of the WDT time-out period is the sum of the two parameters. The closed window period is defined by the Window Period bits in the Configuration register (CONFIG.WINDOW), and the open window period is defined by the Period bits in the Configuration register (CONFIG.PER). By default, the Early Warning interrupt is disabled. If it is desired, the Early Warning Interrupt Enable bit in the Interrupt Enable register (INTENSET.EW) must be written to '1'. The Early Warning Interrupt is disabled again by writing a '1' to the Early Warning Interrupt bit in the Interrupt Enable Clear (INTENCLR.EW) register. If the Early Warning interrupt is enabled in Window mode, the interrupt is generated at the start of the open window period, i.e. after TOWDTW. The Window mode operation is illustrated in figure Window-Mode Operation. Figure 18-3. Window-Mode Operation 5 10 15 20 25 30 35 WDT Timeout Early Warning Interrupt Timely WDT Clear t[ms] TOWDT System Reset WDT Count PER[3:0] = 0 WINDOW[3:0] = 0 TOWDTW Early WDT Clear Closed Open

18.6.3 Additional Features

18.6.3.1 Always-On Mode

The Always-On mode is enabled by setting the Always-On bit in the Control register (CTRLA.ALWAYSON=1). When the Always-On mode is enabled, the WDT runs continuously, regardless of the state of CTRL.ENABLE. Once written, the Always-On bit can only be cleared by a power-on reset. The Configuration (CONFIG) and Early Warning Control (EWCTRL) registers are read-only registers while the CTRL.ALWAYSON bit is set. Thus, the time period configuration bits (CONFIG.PER, CONFIG.WINDOW, EWCTRL.EWOFFSET) of the WDT cannot be changed. Enabling or disabling Window mode operation by writing the Window Enable bit (CTRLA.WEN) is allowed while in Always-On mode, but note that CONFIG.PER cannot be changed. SAM D21/DA1 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 215

The CTRL.ALWAYSON bit must never be set to one by software if any of the following conditions is true: 1. The GCLK_WDT is disabled 2. The clock generator for the GCLK_WDT is disabled 3. The source clock of the clock generator for the GCLK_WDT is disabled or off The Interrupt Clear and Interrupt Set registers are accessible in the Always-On mode. The Early Warning interrupt can still be enabled or disabled while in the Always-On mode, but note that EWCTRL.EWOFFSET cannot be changed. Table 18-2. WDT Operating Modes With Always-On WEN Interrupt enable Mode 0 0 Always-on and normal mode 0 1 Always-on and normal mode with Early Warning interrupt 1 0 Always-on and window mode 1 1 Always-on and window mode with Early Warning interrupt

18.6.4 Interrupts

The WDT has the following interrupt source:

Early Warning (EW) Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the WDT is reset. See the INTFLAG register description for details on how to clear interrupt flags. The WDT has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register to determine which interrupt condition is present. Note: Interrupts must be globally enabled for interrupt requests to be generated. The Early Warning interrupt behaves differently in normal mode and in window mode. In normal mode, the Early Warning interrupt generation is defined by the Early Warning Offset in the Early Warning Control register (EWCTRL.EWOFFSET). The Early Warning Offset bits define the number of GCLK_WDT clocks before the interrupt is generated, relative to the start of the watchdog time-out period. For example, if the WDT is operating in normal mode with CONFIG.PER = 0x2 and EWCTRL.EWOFFSET = 0x1, the Early Warning interrupt is generated 16 GCLK_WDT clock cycles from the start of the watchdog time-out period, and the watchdog time-out system reset is generated 32 GCLK_WDT clock cycles from the start of the watchdog time-out period. The user must take caution when programming the Early Warning Offset bits. If these bits define an Early Warning interrupt generation time greater than the watchdog time-out period, the watchdog time-out system reset is generated prior to the Early Warning interrupt. Thus, the Early Warning interrupt will never be generated. In window mode, the Early Warning interrupt is generated at the start of the open window period. In a typical application where the system is in sleep mode, it can use this interrupt to wake up and clear the Watchdog Timer, after which the system can perform other tasks or return to sleep mode.

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. If an operation that requires synchronization is executed while STATUS.SYNCBUSY='1', the bus will be stalled. All operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is stalled. SAM D21/DA1 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 216

The following registers are synchronized when written:

Control register (CTRL)
Clear register (CLEAR) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Related Links

18.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRL 7:0 ALWAYSON WEN ENABLE 0x01 CONFIG 7:0 WINDOW[3:0] PER[3:0] 0x02 EWCTRL 7:0 EWOFFSET[3:0] 0x03 Reserved 0x04 INTENCLR 7:0 EW 0x05 INTENSET 7:0 EW 0x06 INTFLAG 7:0 EW 0x07 STATUS 7:0 SYNCBUSY 0x08 CLEAR 7:0 CLEAR[7:0]

18.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read- Synchronized" and/or "Write-Synchronized" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description. SAM D21/DA1 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 218

18.8.1 Control

Name: CTRL Offset: 0x0 Reset: N/A - Loaded from NVM User Row at start-up Property: Write-Protected, Enable-Protected, Write-Synchronized Bit 7 6 5 4 3 2 1 0 ALWAYSON WEN ENABLE Access R/W R/W R/W Reset x x x Bit 7 – ALWAYSON Always-On This bit allows the WDT to run continuously. After being written to one, this bit cannot be written to zero, and the WDT will remain enabled until a power-on reset is received. When this bit is one, the Control register (CTRL), the Configuration register (CONFIG) and the Early Warning Control register (EWCTRL) will be read-only, and any writes to these registers are not allowed. Writing a zero to this bit has no effect. This bit is not enable-protected. These bits are loaded from NVM User Row at start-up. Refer to NVM User Row Mapping for more details. Value Description 0 The WDT is enabled and disabled through the ENABLE bit. 1 The WDT is enabled and can only be disabled by a power-on reset (POR). Bit 2 – WEN Watchdog Timer Window Mode Enable The initial value of this bit is loaded from Flash Calibration. This bit is loaded from NVM User Row at start-up. Refer to NVM User Row Mapping for more details. Value Description 0 Window mode is disabled (normal operation). 1 Window mode is enabled. Bit 1 – ENABLE Enable This bit enables or disables the WDT. Can only be written while CTRL.ALWAYSON is zero. Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete. This bit is not enable-protected. This bit is loaded from NVM User Row at start-up. Refer to NVM User Row Mapping for more details. Value Description 0 The WDT is disabled. 1 The WDT is enabled. Related Links WDT – Watchdog Timer © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 219

18.8.2 Configuration

Name: CONFIG Offset: 0x1 Reset: N/A - Loaded from NVM User Row at startup Property: Write-Protected, Enable-Protected, Write-Synchronized Bit 7 6 5 4 3 2 1 0 WINDOW[3:0] PER[3:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Bits 7:4 – WINDOW[3:0] Window Mode Time-Out Period In window mode, these bits determine the watchdog closed window period as a number of oscillator cycles. These bits are loaded from NVM User Row at start-up. Refer to NVM User Row Mapping for more details. Value Description 0x0 8 clock cycles 0x1 16 clock cycles 0x2 32 clock cycles 0x3 64 clock cycles 0x4 128 clock cycles 0x5 256 clocks cycles 0x6 512 clocks cycles 0x7 1024 clock cycles 0x8 2048 clock cycles 0x9 4096 clock cycles 0xA 8192 clock cycles 0xB 16384 clock cycles 0xC-0xF Reserved Bits 3:0 – PER[3:0] Time-Out Period These bits determine the watchdog time-out period as a number of GCLK_WDT clock cycles. In window mode operation, these bits define the open window period. These bits are loaded from NVM User Row at start-up. Refer to NVM User Row Mapping for more details. Value Description 0x0 8 clock cycles 0x1 16 clock cycles 0x2 32 clock cycles 0x3 64 clock cycles 0x4 128 clock cycles 0x5 256 clocks cycles 0x6 512 clocks cycles 0x7 1024 clock cycles 0x8 2048 clock cycles 0x9 4096 clock cycles 0xA 8192 clock cycles 0xB 16384 clock cycles 0xC-0xF Reserved Related Links WDT – Watchdog Timer © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 220

18.8.3 Early Warning Interrupt Control

Name: EWCTRL Offset: 0x2 Reset: N/A - Loaded from NVM User Row at start-up Property: Write-Protected, Enable-Protected Bit 7 6 5 4 3 2 1 0 EWOFFSET[3:0] Access R/W R/W R/W R/W Reset x x x x Bits 3:0 – EWOFFSET[3:0] Early Warning Interrupt Time Offset These bits determine the number of GCLK_WDT clocks in the offset from the start of the watchdog time-out period to when the Early Warning interrupt is generated. These bits are loaded from NVM User Row at start-up. Refer to NVM User Row Mapping for more details. Value Description 0x0 8 clock cycles 0x1 16 clock cycles 0x2 32 clock cycles 0x3 64 clock cycles 0x4 128 clock cycles 0x5 256 clocks cycles 0x6 512 clocks cycles 0x7 1024 clock cycles 0x8 2048 clock cycles 0x9 4096 clock cycles 0xA 8192 clock cycles 0xB 16384 clock cycles 0xC-0xF Reserved Related Links WDT – Watchdog Timer © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 221

18.8.4 Interrupt Enable Clear

Name: INTENCLR Offset: 0x4 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 EW Access R/W Reset 0 Bit 0 – EW Early Warning Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit disables the Early Warning interrupt. Value Description 0 The Early Warning interrupt is disabled. 1 The Early Warning interrupt is enabled. SAM D21/DA1 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 222

18.8.5 Interrupt Enable Set

Name: INTENSET Offset: 0x5 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 EW Access R/W Reset 0 Bit 0 – EW Early Warning Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit enables the Early Warning interrupt. Value Description 0 The Early Warning interrupt is disabled. 1 The Early Warning interrupt is enabled. SAM D21/DA1 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 223

18.8.6 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x6 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 EW Access R/W Reset 0 Bit 0 – EW Early Warning This flag is set when an Early Warning interrupt occurs, as defined by the EWOFFSET bit group in EWCTRL. Writing a zero to this bit has no effect. Writing a one to this bit clears the Early Warning interrupt flag. SAM D21/DA1 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 224

18.8.7 Status

Name: STATUS Offset: 0x7 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 SYNCBUSY Access R Reset 0 Bit 7 – SYNCBUSY Synchronization Busy This bit is cleared when the synchronization of registers between clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. SAM D21/DA1 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 225

18.8.8 Clear

Name: CLEAR Offset: 0x8 Reset: 0x00 Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 3 2 1 0 CLEAR[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – CLEAR[7:0] Watchdog Clear Writing 0xA5 to this register will clear the Watchdog Timer and the watchdog time-out period is restarted. Writing any other value will issue an immediate system reset. SAM D21/DA1 Family WDT – Watchdog Timer © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 226

RTC – Real-Time Counter

19.1 Overview

The Real-Time Counter (RTC) is a 32-bit counter with a 10-bit programmable prescaler that typically runs continuously to keep track of time. The RTC can wake-up the device from Sleep modes using the alarm/compare wake-up, periodic wake-up, or overflow wake-up mechanisms The RTC can be clocked from several clock sources selectable through the Generic Clock module (GCLK). This GCLK_RTC clock can then be divided with CTRLA.PRESCALER to achieve the required resolution. The RTC can generate periodic peripheral events from outputs of the prescaler, as well as alarm/compare interrupts and peripheral events, which can trigger at any counter value. Additionally, the timer can trigger an overflow interrupt and peripheral event, and can be Reset on the occurrence of an alarm/compare match. This allows periodic interrupts and peripheral events at very long and accurate intervals. The 10-bit programmable prescaler can scale down the clock source. By this, a wide range of resolutions and time-out periods can be configured. With a 32.768 kHz clock source, the minimum counter tick interval is 30.5 µs, and time-out periods can range up to 36 hours. For a counter tick interval of 1s, the maximum time-out period is more than 136 years.

19.2 Features

32-bit counter with 10-bit prescaler
Multiple clock sources
32-bit or 16-bit Counter mode – One 32-bit or two 16-bit compare values
Clock/Calendar mode – Time in seconds, minutes and hours (12/24) – Date in day of month, month and year – Leap year correction
Digital prescaler correction/tuning for increased accuracy
Overflow, alarm/compare match and prescaler interrupts and events – Optional clear on alarm/compare match

19.3 Block Diagram

Figure 19-1. RTC Block Diagram (Mode 0 — 32-Bit Counter) COUNT COMPn = Compare n Overflow MATCHCLR 10-bit Prescaler GCLK_RTC CLK_RTC_CNT Periodic Events SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 227

Figure 19-2. RTC Block Diagram (Mode 1 — 16-Bit Counter) 10-bit Prescaler GCLK_RTC COUNT PER Overflow COMPn Compare n CLK_RTC_CNT Periodic Events Figure 19-3. RTC Block Diagram (Mode 2 — Clock/Calendar) CLOCK ALARMn = Alarm n Overflow MATCHCLR 10-bit Prescaler GCLK_RTC CLK_RTC_CNT Periodic Events MASKn Y/M/D H:M:S Y/M/D H:M:S

19.4 Signal Description

Not applicable.

19.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

19.5.1 I/O Lines

Not applicable.

19.5.2 Power Management

The RTC will continue to operate in any sleep mode where the selected source clock is running. The RTC interrupts can be used to wake up the device from sleep modes. Events connected to the event system can trigger other operations in the system without exiting sleep modes. Refer to the Power Manager for details on the different sleep modes. The RTC will be reset only at power-on (POR) or by setting the Software Reset bit in the Control register (CTRL.SWRST=1). Related Links 16. PM – Power Manager

19.5.3 Clocks

The RTC bus clock (CLK_RTC_APB) can be enabled and disabled in the Power Manager, and the default state of CLK_RTC_APB can be found in the Peripheral Clock Masking section. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 228

A generic clock (GCLK_RTC) is required to clock the RTC. This clock must be configured and enabled in the Generic Clock Controller before using the RTC. Refer to GCLK – Generic Clock Controller for details. This generic clock is asynchronous to the user interface clock (CLK_RTC_APB). Due to this asynchronicity, accessing certain registers will require synchronization between the clock domains. Refer to 19.6.8 Synchronization for further details. The RTC should not work with the Generic Clock Generator 0. Related Links

GCLK - Generic Clock Controller

19.5.4 DMA

Not applicable.

19.5.5 Interrupts

The interrupt request line is connected to the Interrupt Controller. Using the RTC interrupts requires the Interrupt Controller to be configured first. Refer to Nested Vector Interrupt Controller for details. Related Links

19.5.6 Events

The events are connected to the Event System. Related Links 24. EVSYS – Event System

19.5.7 Debug Operation

When the CPU is halted in debug mode the RTC will halt normal operation. The RTC can be forced to continue operation during debugging. Refer to the Debug Control (DBGCTRL) register for details.

19.5.8 Register Access Protection

Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following:

Interrupt Flag Status and Clear register (INTFLAG)
Read Request register (READREQ)
Status register (STATUS)
Debug register (DBGCTRL) Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. Write-protection does not apply for accesses through an external debugger.

19.5.9 Analog Connections

A 32.768kHz crystal can be connected to the XIN32 and XOUT32 pins, along with any required load capacitors. For details on recommended crystal characteristics and load capacitors, refer to Electrical Characteristics for details. Related Links 37. Electrical Characteristics at 85℃ SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 229

19.6 Functional Description

19.6.1 Principle of Operation

The RTC keeps track of time in the system and enables periodic events, as well as interrupts and events at a specified time. The RTC consists of a 10-bit prescaler that feeds a 32-bit counter. The actual format of the 32-bit counter depends on the RTC operating mode. The RTC can function in one of these modes:

Mode 0 - COUNT32: RTC serves as 32-bit counter
Mode 1 - COUNT16: RTC serves as 16-bit counter
Mode 2 - CLOCK: RTC serves as clock/calendar with alarm functionality

19.6.2 Basic Operation

19.6.2.1 Initialization

The following bits are enable-protected, meaning that they can only be written when the RTC is disabled (CTRL.ENABLE=0):

Operating Mode bits in the Control register (CTRL.MODE)
Prescaler bits in the Control register (CTRL.PRESCALER)
Clear on Match bit in the Control register (CTRL.MATCHCLR)
Clock Representation bit in the Control register (CTRL.CLKREP) The following register is enable-protected:
Event Control register (EVCTRL) Any writes to these bits or registers when the RTC is enabled or being enabled (CTRL.ENABLE=1) will be discarded. Writes to these bits or registers while the RTC is being disabled will be completed after the disabling is complete. Enable-protection is denoted by the "Enable-Protected" property in the register description. Before the RTC is enabled, it must be configured, as outlined by the following steps: 1. RTC operation mode must be selected by writing the Operating Mode bit group in the Control register (CTRL.MODE) 2. Clock representation must be selected by writing the Clock Representation bit in the Control register (CTRL.CLKREP) 3. Prescaler value must be selected by writing the Prescaler bit group in the Control register (CTRL.PRESCALER) The RTC prescaler divides the source clock for the RTC counter. Note: In Clock/Calendar mode, the prescaler must be configured to provide a 1Hz clock to the counter for correct operation. The frequency of the RTC clock (CLK_RTC_CNT) is given by the following formula: f CLK_RTC_CNT = f GCLK_RTC

2 PRESCALER

The frequency of the generic clock, GCLK_RTC, is given by fGCLK_RTC, and fCLK_RTC_CNT is the frequency of the internal prescaled RTC clock, CLK_RTC_CNT.

19.6.2.2 Enabling, Disabling and Resetting

The RTC is enabled by setting the Enable bit in the Control register (CTRL.ENABLE=1). The RTC is disabled by writing CTRL.ENABLE=0. The RTC is reset by setting the Software Reset bit in the Control register (CTRL.SWRST=1). All registers in the RTC, except DEBUG, will be reset to their initial state, and the RTC will be disabled. The RTC must be disabled before resetting it. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 230

19.6.3 Operating Modes

The RTC counter supports three RTC operating modes: 32-bit Counter, 16-bit Counter and Clock/Calendar. The operating mode is selected by writing to the Operating Mode bit group in the Control register (CTRL.MODE). 19.6.3.1 32-Bit Counter (Mode 0) When the RTC Operating Mode bits in the Control register are zero (CTRL.MODE=00), the counter operates in 32-bit Counter mode. The block diagram of this mode is shown in Figure 19-1. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The counter will increment until it reaches the top value of 0xFFFFFFFF, and then wrap to 0x00000000. This sets the Overflow Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF). The RTC counter value can be read from or written to the Counter Value register (COUNT) in 32-bit format. The counter value is continuously compared with the 32-bit Compare register (COMP0). When a compare match occurs, the Compare 0interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMP0) is set on the next 0-to-1 transition of CLK_RTC_CNT. If the Clear on Match bit in the Control register (CTRL.MATCHCLR) is '1', the counter is cleared on the next counter cycle when a compare match with COMP0 occurs. This allows the RTC to generate periodic interrupts or events with longer periods than are possible with the prescaler events. Note that when CTRL.MATCHCLR is '1', INTFLAG.CMP0 and INTFLAG.OVF will both be set simultaneously on a compare match with COMP0. 19.6.3.2 16-Bit Counter (Mode 1) When the RTC Operating Mode bits in the Control register (CTRL.MODE) are 1, the counter operates in 16-bit Counter mode as shown in Figure 19-2. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. In 16-bit Counter mode, the 16-bit Period register (PER) holds the maximum value of the counter. The counter will increment until it reaches the PER value, and then wrap to 0x0000. This sets the Overflow interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF). The RTC counter value can be read from or written to the Counter Value register (COUNT) in 16-bit format. The counter value is continuously compared with the 16-bit Compare registers (COMPn, n=0–1). When a compare match occurs, the Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn, n=0–1) is set on the next 0-to-1 transition of CLK_RTC_CNT.

19.6.3.3 Clock/Calendar (Mode 2)

When CTRL.MODE is two, the counter operates in Clock/Calendar mode, as shown in Figure 19-3. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The selected clock source and RTC prescaler must be configured to provide a 1Hz clock to the counter for correct operation in this mode. The time and date can be read from or written to the Clock Value register (CLOCK) in a 32-bit time/date format. Time is represented as:

Seconds
Minutes
Hours Hours can be represented in either 12- or 24-hour format, selected by the Clock Representation bit in the Control register (CTRL.CLKREP). This bit can be changed only while the RTC is disabled. Date is represented as:
Day as the numeric day of the month (starting at 1)
Month as the numeric month of the year (1 = January, 2 = February, etc.)
Year as a value counting the offset from a reference value that must be defined in software The date is automatically adjusted for leap years, assuming every year divisible by 4 is a leap year. Therefore, the reference value must be a leap year, e.g. 2000. The RTC will increment until it reaches the top value of 23:59:59 December 31st of year 63, and then wrap to 00:00:00 January 1st of year 0. This will set the Overflow interrupt flag in the Interrupt Flag Status and Clear registers (INTFLAG.OVF). The clock value is continuously compared with the 32-bit Alarm register (ALARM0). When an alarm match occurs, the Alarm 0 Interrupt flag in the Interrupt Flag Status and Clear registers (INTFLAG.ALARMn0) is set on the next 0-to-1 transition of CLK_RTC_CNT. E.g. For a 1Hz clock counter, it means the Alarm 0 Interrupt flag is set with a SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 231

delay of 1s after the occurrence of alarm match. A valid alarm match depends on the setting of the Alarm Mask Selection bits in the Alarm A valid alarm match depends on the setting of the Alarm Mask Selection bits in the Alarm 0 Mask register (MASK0.SEL). These bits determine which time/date fields of the clock and alarm values are valid for comparison and which are ignored. If the Clear on Match bit in the Control register (CTRL.MATCHCLR) is one, the counter is cleared on the next counter cycle when an alarm match with ALARM0 occurs. This allows the RTC to generate periodic interrupts or events with longer periods than are possible with the prescaler events (see 19.6.9.1 Periodic Events). Note that when CTRL.MATCHCLR is '1', INTFLAG.ALARM0 and INTFLAG.OVF will both be set simultaneously on an alarm match with ALARM0.

19.6.4 DMA Operation

Not applicable.

19.6.5 Interrupts

The RTC has the following interrupt sources which are asynchronous interrupts and can wake-up the device from any sleep mode.:

Overflow (INTFLAG.OVF): Indicates that the counter has reached its top value and wrapped to zero.
Compare n (INTFLAG.CMPn): Indicates a match between the counter value and the compare register.
Alarm n (INTFLAG.ALARMn): Indicates a match between the clock value and the alarm register.
Synchronization Ready (INTFLAG.SYNCRDY): Indicates an operation requires synchronization. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by setting the corresponding bit in the Interrupt Enable Set register (INTENSET=1), and disabled by setting the corresponding bit in the Interrupt Enable Clear register (INTENCLR=1). An interrupt request is generated when the interrupt flag is raised and the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled or the RTC is reset. See the description of the INTFLAG registers for details on how to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. Refer to the Nested Vector Interrupt Controller for details. The user must read the INTFLAG register to determine which interrupt condition is present. Note: Interrupts must be globally enabled for interrupt requests to be generated. Refer to the Nested Vector Interrupt Controller for details. Related Links

19.6.6 Events

The RTC can generate the following output events, which are generated in the same way as the corresponding interrupts:

Overflow (OVF): Indicates that the counter has reached its top value and wrapped to zero.
Period n (PERn): The corresponding bit in the prescaler has toggled. Refer to 19.6.9.1 Periodic Events for details.
Compare n (CMPn): Indicates a match between the counter value and the compare register.
Alarm n (ALARMn): Indicates a match between the clock value and the alarm register. Setting the Event Output bit in the Event Control Register (EVCTRL.xxxEO=1) enables the corresponding output event. Writing a zero to this bit disables the corresponding output event. Refer to the EVSYS - Event System for details on configuring the event system. Related Links 24. EVSYS – Event System SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 232

19.6.7 Sleep Mode Operation

The RTC will continue to operate in any sleep mode where the source clock is active. The RTC interrupts can be used to wake up the device from a sleep mode. RTC events can trigger other operations in the system without exiting the sleep mode. An interrupt request will be generated after the wake-up if the Interrupt Controller is configured accordingly. Otherwise the CPU will wake up directly, without triggering any interrupt. In this case, the CPU will continue executing right from the first instruction that followed the entry into sleep. The periodic events can also wake up the CPU through the interrupt function of the Event System. In this case, the event must be enabled and connected to an event channel with its interrupt enabled. See Event System for more information. Related Links 24. EVSYS – Event System

19.6.8 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization Ready interrupt can be used to signal when synchronization is complete. This can be accessed via the Synchronization Ready Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.SYNCRDY). If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is stalled. The following bits are synchronized when written:

Software Reset bit in the Control register (CTRL.SWRST)
Enable bit in the Control register (CTRL.ENABLE) The following registers are synchronized when written:
Counter Value register (COUNT)
Clock Value register (CLOCK)
Counter Period register (PER)
Compare n Value registers (COMPn)
Alarm n Value registers (ALARMn)
Frequency Correction register (FREQCORR)
Alarm n Mask register (MASKn) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. The following registers are synchronized when read:
The Counter Value register (COUNT)
The Clock Value register (CLOCK) Required read-synchronization is denoted by the "Read-Synchronized" property in the register description. Related Links

19.6.9 Additional Features

19.6.9.1 Periodic Events

The RTC prescaler can generate events at periodic intervals, allowing flexible system tick creation. Any of the upper eight bits of the prescaler (bits 2 to 9) can be the source of an event. When one of the eight Periodic Event Output bits in the Event Control register (EVCTRL.PEREO[n=0..7]) is '1', an event is generated on the 0-to-1 transition of the related bit in the prescaler, resulting in a periodic event frequency of: SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 233

f PE RI OD I C = f GCLK_RTC 2 n + 3 fGCLK_RTC is the frequency of the internal prescaler clock, GCLK_RTC, and n is the position of the EVCTRL.PEREOn bit. For example, PER0 will generate an event every eight CLK_RTC_OSC cycles, PER1 every 16 cycles, etc. This is shown in the figure below. Periodic events are independent of the prescaler setting used by the RTC counter, except if CTRL.PRESCALER is zero. Then, no periodic events will be generated. Figure 19-4. Example Periodic Events PEREO0 PEREO1 PEREO2 PEREO3 PEREO4 GCLK_RTC

19.6.9.2 Frequency Correction

The RTC Frequency Correction module employs periodic counter corrections to compensate for a too-slow or too-fast oscillator. Frequency correction requires that CTRL.PRESCALER is greater than 1. The digital correction circuit adds or subtracts cycles from the RTC prescaler to adjust the frequency in approximately 1 ppm steps. Digital correction is achieved by adding or skipping a single count in the prescaler once every 4096 GCLK_RTC_OSC cycles. The Value bit group in the Frequency Correction register (FREQCORR.VALUE) determines the number of times the adjustment is applied over 240 of these periods. The resulting correction is as follows: Correction in ppm = (FREQCORR.VALUE / 4096 * 240) * 106ppm This results in a resolution of 1.017 PPM. The Sign bit in the Frequency Correction register (FREQCORR.SIGN) determines the direction of the correction. A positive value will add counts and increase the period (reducing the frequency), and a negative value will reduce counts per period (speeding up the frequency). Digital correction also affects the generation of the periodic events from the prescaler. When the correction is applied at the end of the correction cycle period, the interval between the previous periodic event and the next occurrence may also be shortened or lengthened depending on the correction value.

19.7 Register Summary

The register mapping depends on the Operating Mode bits in the Control register (CTRL.MODE). The register summary is presented for each of the three modes. Table 19-1. MODE0 - Mode Register Summary Offset Name Bit Pos. 0x00 CTRL 7:0 MATCHCLR MODE[1:0] ENABLE SWRST 0x01 15:8 PRESCALER[3:0] 0x02 READREQ 7:0 ADDR[5:0] 0x03 15:8 RREQ RCONT 0x04 EVCTRL 7:0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 0x05 15:8 OVFEO CMPEO0 0x06 INTENCLR 7:0 OVF SYNCRDY CMP0 0x07 INTENSET 7:0 OVF SYNCRDY CMP0 0x08 INTFLAG 7:0 OVF SYNCRDY CMP0 SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 234

Pos. 0x09 Reserved 0x0A STATUS 7:0 SYNCBUSY 0x0B DBGCTRL 7:0 DBGRUN 0x0C FREQCORR 7:0 SIGN VALUE[6:0] 0x0D ... 0x0F Reserved 0x10 COUNT 7:0 COUNT[7:0] 0x11 15:8 COUNT[15:8] 0x12 23:16 COUNT[23:16] 0x13 31:24 COUNT[31:24] 0x14 ... 0x17 Reserved 0x18 COMP0 7:0 COMP[7:0] 0x19 15:8 COMP[15:8] 0x1A 23:16 COMP[23:16] 0x1B 31:24 COMP[31:24] Table 19-2. MODE1 - Mode Register Summary Offset Name Bit Pos. 0x00 CTRL 7:0 MODE[1:0] ENABLE SWRST 0x01 15:8 PRESCALER[3:0] 0x02 READREQ 7:0 ADDR[5:0] 0x03 15:8 RREQ RCONT 0x04 EVCTRL 7:0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 0x05 15:8 OVFEO CMPEO1 CMPEO0 0x06 INTENCLR 7:0 OVF SYNCRDY CMP1 CMP0 0x07 INTENSET 7:0 OVF SYNCRDY CMP1 CMP0 0x08 INTFLAG 7:0 OVF SYNCRDY CMP1 CMP0 0x09 Reserved 0x0A STATUS 7:0 SYNCBUSY 0x0B DBGCTRL 7:0 DBGRUN 0x0C FREQCORR 7:0 SIGN VALUE[6:0] 0x0D ... 0x0F Reserved 0x10 COUNT 7:0 COUNT[7:0] 0x11 15:8 COUNT[15:8] 0x12 Reserved 0x13 Reserved 0x14 PER 7:0 PER[7:0] 0x15 15:8 PER[15:8] 0x16 Reserved 0x17 Reserved 0x18 COMP0 7:0 COMP[7:0] 0x19 15:8 COMP[15:8] 0x1A COMP1 7:0 COMP[7:0] 0x1B 15:8 COMP[15:8] SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 235

Table 19-3. MODE2 - Mode Register Summary Offset Name Bit Pos. 0x00 CTRL 7:0 MATCHCLR CLKREP MODE[1:0] ENABLE SWRST 0x01 15:8 PRESCALER[3:0] 0x02 READREQ 7:0 ADDR[5:0] 0x03 15:8 RREQ RCONT 0x04 EVCTRL 7:0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 0x05 15:8 OVFEO ALARMEO0 0x06 INTENCLR 7:0 OVF SYNCRDY ALARM0 0x07 INTENSET 7:0 OVF SYNCRDY ALARM0 0x08 INTFLAG 7:0 OVF SYNCRDY ALARM0 0x09 Reserved 0x0A STATUS 7:0 SYNCBUSY 0x0B DBGCTRL 7:0 DBGRUN 0x0C FREQCORR 7:0 SIGN VALUE[6:0] 0x0D ... 0x0F Reserved 0x10 CLOCK 7:0 MINUTE[1:0] SECOND[5:0] 0x11 15:8 HOUR[3:0] MINUTE[5:2] 0x12 23:16 MONTH[1:0] DAY[4:0] HOUR[4] 0x13 31:24 YEAR[5:0] MONTH[3:2] 0x14 ... 0x17 Reserved 0x18 ALARM0 7:0 MINUTE[1:0] SECOND[5:0] 0x19 15:8 HOUR[3:0] MINUTE[5:2] 0x1A 23:16 MONTH[1:0] DAY[4:0] HOUR[4] 0x1B 31:24 YEAR[5:0] MONTH[3:2] 0x1C MASK 7:0 SEL[2:0]

19.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read- Synchronized" and/or "Write-Synchronized" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 236

19.8.1 Control - MODE0

Name: CTRL Offset: 0x00 Reset: 0x0000 Property: Enable-Protected, Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 PRESCALER[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MATCHCLR MODE[1:0] ENABLE SWRST Access R/W R/W R/W R/W W Reset 0 0 0 0 0 Bits 11:8 – PRESCALER[3:0] Prescaler These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT). These bits are not synchronized. PRESCALER[3:0] Name Description 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xB-0xF Reserved Bit 7 – MATCHCLR Clear on Match This bit is valid only in Mode 0 and Mode 2. This bit is not synchronized. Value Description 0 The counter is not cleared on a Compare/Alarm 0 match. 1 The counter is cleared on a Compare/Alarm 0 match. Bits 3:2 – MODE[1:0] Operating Mode These bits define the operating mode of the RTC. These bits are not synchronized. MODE[1:0] Name Description 0x0 COUNT32 Mode 0: 32-bit Counter 0x1 COUNT16 Mode 1: 16-bit Counter 0x2 CLOCK Mode 2: Clock/Calendar 0x3 Reserved SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 237

Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete. This bit is not enable-protected. Value Description 0 The peripheral is disabled or being disabled. 1 The peripheral is enabled or being enabled. Bit 0 – SWRST Software Reset Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be disabled. Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete. This bit is not enable-protected. Value Description 0 There is no reset operation ongoing. 1 The reset operation is ongoing. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 238

19.8.2 Control - MODE1

Name: CTRL Offset: 0x00 Reset: 0x0000 Property: Enable-Protected, Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 PRESCALER[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MODE[1:0] ENABLE SWRST Access R/W R/W R/W W Reset 0 0 0 0 Bits 11:8 – PRESCALER[3:0] Prescaler These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT). These bits are not synchronized. PRESCALER[3:0] Name Description 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xB-0xF Reserved Bits 3:2 – MODE[1:0] Operating Mode These bits define the operating mode of the RTC. These bits are not synchronized. MODE[1:0] Name Description 0x0 COUNT32 Mode 0: 32-bit Counter 0x1 COUNT16 Mode 1: 16-bit Counter 0x2 CLOCK Mode 2: Clock/Calendar 0x3 Reserved Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete. This bit is not enable-protected. Value Description 0 The peripheral is disabled or being disabled. 1 The peripheral is enabled or being enabled. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 239

Bit 0 – SWRST Software Reset Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be disabled. Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete. This bit is not enable-protected. Value Description 0 There is no reset operation ongoing. 1 The reset operation is ongoing. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 240

19.8.3 Control - MODE2

Name: CTRL Offset: 0x00 Reset: 0x0000 Property: Enable-Protected, Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 PRESCALER[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MATCHCLR CLKREP MODE[1:0] ENABLE SWRST Access R/W R/W R/W R/W R/W W Reset 0 0 0 0 0 0 Bits 11:8 – PRESCALER[3:0] Prescaler These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT). These bits are not synchronized. PRESCALER[3:0] Name Description 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xB-0xF Reserved Bit 7 – MATCHCLR Clear on Match This bit is valid only in Mode 0 and Mode 2. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Value Description 0 The counter is not cleared on a Compare/Alarm 0 match. 1 The counter is cleared on a Compare/Alarm 0 match. Bit 6 – CLKREP Clock Representation This bit is valid only in Mode 2 and determines how the hours are represented in the Clock Value (CLOCK) register. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Value Description 0 24 Hour 1 12 Hour (AM/PM) Bits 3:2 – MODE[1:0] Operating Mode These bits define the operating mode of the RTC. These bits are not synchronized. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 241

MODE[1:0] Name Description 0x0 COUNT32 Mode 0: 32-bit Counter 0x1 COUNT16 Mode 1: 16-bit Counter 0x2 CLOCK Mode 2: Clock/Calendar 0x3 Reserved Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete. This bit is not enable-protected. Value Description 0 The peripheral is disabled or being disabled. 1 The peripheral is enabled or being enabled. Bit 0 – SWRST Software Reset Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be disabled. Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete. This bit is not enable-protected. Value Description 0 There is no reset operation ongoing. 1 The reset operation is ongoing. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 242

19.8.4 Read Request

Name: READREQ Offset: 0x02 Reset: 0x0010 Property: - Bit 15 14 13 12 11 10 9 8 RREQ RCONT Access W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[5:0] Access R R R R R R Reset 0 1 0 0 0 0 Bit 15 – RREQ Read Request Writing a zero to this bit has no effect. Writing a one to this bit requests synchronization of the register pointed to by the Address bit group (READREQ.ADDR) and sets the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY). Bit 14 – RCONT Read Continuously Writing a zero to this bit disables continuous synchronization. Writing a one to this bit enables continuous synchronization of the register pointed to by READREQ.ADDR. The register value will be synchronized automatically every time the register is updated. READREQ.RCONT prevents READREQ.RREQ from clearing automatically. For the continuous read mode, RREQ bit is required to be set once the RCONT bit is set. This bit is cleared when an RTC register is written. Note: Once the continuous synchronization is enabled, the first write in the COUNT/CLOCK register will be stalled for a maximum of 6 APB + 6 RTC clock cycles (the time for the on-going read synchronization to complete). Bits 5:0 – ADDR[5:0] Address These bits select the offset of the register that needs read synchronization. In the RTC only COUNT and CLOCK, which share the same address, are available for read synchronization. Therefore, ADDR is a read-only constant of 0x10. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 243

19.8.5 Event Control - MODE0

Name: EVCTRL Offset: 0x04 Reset: 0x0000 Property: Enable-Protected, Write-Protected Bit 15 14 13 12 11 10 9 8 OVFEO CMPEO0 Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 PEREOx PEREOx PEREOx PEREOx PEREOx PEREOx PEREOx PEREOx Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVFEO Overflow Event Output Enable Value Description 0 Overflow event is disabled and will not be generated. 1 Overflow event is enabled and will be generated for every overflow. Bit 8 – CMPEO0 Compare 0 Event Output Enable Value Description 0 Compare 0 event is disabled and will not be generated. 1 Compare 0 event is enabled and will be generated for every compare match. Bits 7,6,5,4,3,2,1,0 – PEREOx Periodic Interval x Event Output Enable [x=7:0] Value Description 0 Periodic Interval x event is disabled and will not be generated. 1 Periodic Interval x event is enabled and will be generated. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 244

19.8.6 Event Control - MODE1

Name: EVCTRL Offset: 0x04 Reset: 0x0000 Property: Enable-Protected, Write-Protected Bit 15 14 13 12 11 10 9 8 OVFEO CMPEOx CMPEOx Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 PEREOx PEREOx PEREOx PEREOx PEREOx PEREOx PEREOx PEREOx Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVFEO Overflow Event Output Enable Value Description 0 Overflow event is disabled and will not be generated. 1 Overflow event is enabled and will be generated for every overflow. Bits 9,8 – CMPEOx Compare x Event Output Enable [x=1:0] Value Description 0 Compare x event is disabled and will not be generated. 1 Compare x event is enabled and will be generated for every compare match. Bits 7,6,5,4,3,2,1,0 – PEREOx Periodic Interval x Event Output Enable [x=7:0] Value Description 0 Periodic Interval x event is disabled and will not be generated. 1 Periodic Interval x event is enabled and will be generated. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 245

19.8.7 Event Control - MODE2

Name: EVCTRL Offset: 0x04 Reset: 0x0000 Property: Enable-Protected, Write-Protected Bit 15 14 13 12 11 10 9 8 OVFEO ALARMEO0 Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 PEREOx PEREOx PEREOx PEREOx PEREOx PEREOx PEREOx PEREOx Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVFEO Overflow Event Output Enable Value Description 0 Overflow event is disabled and will not be generated. 1 Overflow event is enabled and will be generated for every overflow. Bit 8 – ALARMEO0 Alarm 0 Event Output Enable Value Description 0 Alarm 0 event is disabled and will not be generated. 1 Alarm 0 event is enabled and will be generated for every alarm. Bits 7,6,5,4,3,2,1,0 – PEREOx Periodic Interval x Event Output Enable [x=7:0] Value Description 0 Periodic Interval x event is disabled and will not be generated. 1 Periodic Interval x event is enabled and will be generated. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 246

19.8.8 Interrupt Enable Clear - MODE0

Name: INTENCLR Offset: 0x06 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 OVF SYNCRDY CMP0 Access R/W R/W R/W Reset 0 0 0 Bit 7 – OVF Overflow Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt. Value Description 0 The Overflow interrupt is disabled.

1 The Overflow interrupt is enabled, and an interrupt request will be generated when the Overflow

interrupt flag is set. Bit 6 – SYNCRDY Synchronization Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and disable the corresponding interrupt. Value Description 0 The Synchronization Ready interrupt is disabled.

1 The Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the

Synchronization Ready interrupt flag is set. Bit 0 – CMP0 Compare 0 Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the Compare 0 Interrupt Enable bit and disable the corresponding interrupt. Value Description 0 The Compare 0 interrupt is disabled.

1 The Compare 0 interrupt is enabled, and an interrupt request will be generated when the Compare x

19.8.9 Interrupt Enable Clear - MODE1

Name: INTENCLR Offset: 0x06 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 OVF SYNCRDY CMPx CMPx Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 – OVF Overflow Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt. Value Description 0 The Overflow interrupt is disabled. interrupt flag is set. Bit 6 – SYNCRDY Synchronization Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and disable the corresponding interrupt. Value Description 0 The Synchronization Ready interrupt is disabled. Synchronization Ready interrupt flag is set. Bits 1,0 – CMPx Compare x Interrupt Enable [x=1:0] Writing a zero to this bit has no effect. Writing a one to this bit will clear the Compare x Interrupt Enable bit and disable the corresponding interrupt. Value Description 0 The Compare x interrupt is disabled.

1 The Compare x interrupt is enabled, and an interrupt request will be generated when the Compare x

19.8.10 Interrupt Enable Clear - MODE2

Name: INTENCLR Offset: 0x06 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 OVF SYNCRDY ALARM0 Access R/W R/W R/W Reset 0 0 0 Bit 7 – OVF Overflow Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt. Value Description 0 The Overflow interrupt is disabled. interrupt flag is set. Bit 6 – SYNCRDY Synchronization Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and disable the corresponding interrupt. Value Description 0 The synchronization ready interrupt is disabled. Synchronization Ready interrupt flag is set. Bit 0 – ALARM0 Alarm 0 Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit disables the Alarm 0 interrupt. Value Description 0 The Alarm 0 interrupt is disabled. 1 The Alarm 0 interrupt is enabled, and an interrupt request will be generated when the Alarm 0 interrupt flag is set. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 249

19.8.11 Interrupt Enable Set - MODE0

Name: INTENSET Offset: 0x07 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 OVF SYNCRDY CMP0 Access R/W R/W R/W Reset 0 0 0 Bit 7 – OVF Overflow Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the Overflow Interrupt Enable bit and enable the Overflow interrupt. Value Description 0 The overflow interrupt is disabled. 1 The overflow interrupt is enabled. Bit 6 – SYNCRDY Synchronization Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit and enable the Synchronization Ready interrupt. Value Description 0 The synchronization ready interrupt is disabled. 1 The synchronization ready interrupt is enabled. Bit 0 – CMP0 Compare 0 Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the Compare 0 Interrupt Enable bit and enable the Compare 0 interrupt. Value Description 0 The compare 0 interrupt is disabled. 1 The compare 0 interrupt is enabled. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 250

19.8.12 Interrupt Enable Set - MODE1

Name: INTENSET Offset: 0x07 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 OVF SYNCRDY CMPx CMPx Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 – OVF Overflow Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the Overflow interrupt bit and enable the Overflow interrupt. Value Description 0 The overflow interrupt is disabled. 1 The overflow interrupt is enabled. Bit 6 – SYNCRDY Synchronization Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit and enable the Synchronization Ready interrupt. Value Description 0 The synchronization ready interrupt is disabled. 1 The synchronization ready interrupt is enabled. Bits 1,0 – CMPx Compare x Interrupt Enable [x=1:0] Writing a zero to this bit has no effect. Writing a one to this bit will set the Compare x Interrupt Enable bit and enable the Compare x interrupt. Value Description 0 The compare x interrupt is disabled. 1 The compare x interrupt is enabled. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 251

19.8.13 Interrupt Enable Set - MODE2

Name: INTENSET Offset: 0x07 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 OVF SYNCRDY ALARM0 Access R/W R/W R/W Reset 0 0 0 Bit 7 – OVF Overflow Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the Overflow Interrupt Enable bit and enable the Overflow interrupt. Value Description 0 The overflow interrupt is disabled. 1 The overflow interrupt is enabled. Bit 6 – SYNCRDY Synchronization Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the Synchronization Ready Interrupt bit and enable the Synchronization Ready interrupt. Value Description 0 The synchronization ready interrupt is disabled. 1 The synchronization ready interrupt is enabled. Bit 0 – ALARM0 Alarm 0 Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the Alarm 0 Interrupt Enable bit and enable the Alarm 0 interrupt. Value Description 0 The alarm 0 interrupt is disabled. 1 The alarm 0 interrupt is enabled. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 252

19.8.14 Interrupt Flag Status and Clear - MODE0

Name: INTFLAG Offset: 0x08 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 OVF SYNCRDY CMP0 Access R/W R/W R/W Reset 0 0 0 Bit 7 – OVF Overflow This flag is cleared by writing a one to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Overflow interrupt flag. Bit 6 – SYNCRDY Synchronization Ready This flag is cleared by writing a one to the flag. This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY), except when caused by enable or software reset, and an interrupt request will be generated if INTENCLR/ SET.SYNCRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Synchronization Ready interrupt flag. Bit 0 – CMP0 Compare 0 This flag is cleared by writing a one to the flag. This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request will be generated if INTENCLR/SET.CMP0 is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Compare 0 interrupt flag. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 253

19.8.15 Interrupt Flag Status and Clear - MODE1

Name: INTFLAG Offset: 0x08 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 OVF SYNCRDY CMPx CMPx Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 – OVF Overflow This flag is cleared by writing a one to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Overflow interrupt flag. Bit 6 – SYNCRDY Synchronization Ready This flag is cleared by writing a one to the flag. This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY), except when caused by enable or software reset, and an interrupt request will be generated if INTENCLR/ SET.SYNCRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Synchronization Ready interrupt flag. Bits 1,0 – CMPx Compare x [x=1:0] This flag is cleared by writing a one to the flag. This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition and an interrupt request will be generated if INTENCLR/SET.CMPx is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Compare x interrupt flag. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 254

19.8.16 Interrupt Flag Status and Clear - MODE2

Name: INTFLAG Offset: 0x08 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 OVF SYNCRDY ALARM0 Access R/W R/W R/W Reset 0 0 0 Bit 7 – OVF Overflow This flag is cleared by writing a one to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Overflow interrupt flag. Bit 6 – SYNCRDY Synchronization Ready This flag is cleared by writing a one to the flag. This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY), except when caused by enable or software reset, and an interrupt request will be generated if INTENCLR/ SET.SYNCRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Synchronization Ready interrupt flag. Bit 0 – ALARM0 Alarm 0 This flag is cleared by writing a one to the flag. This flag is set on the next CLK_RTC_CNT cycle after a match with ALARM0 condition occurs, and an interrupt request will be generated if INTENCLR/SET.ALARM0 is also one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Alarm 0 interrupt flag. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 255

19.8.17 Status

Name: STATUS Offset: 0x0A Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 SYNCBUSY Access R Reset 0 Bit 7 – SYNCBUSY Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 256

19.8.18 Debug Control

Name: DBGCTRL Offset: 0x0B Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Run During Debug This bit is not reset by a software reset. Writing a zero to this bit causes the RTC to halt during debug mode. Writing a one to this bit allows the RTC to continue normal operation during debug mode. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 257

19.8.19 Frequency Correction

Name: FREQCORR Offset: 0x0C Reset: 0x00 Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 3 2 1 0 SIGN VALUE[6:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 – SIGN Correction Sign Value Description 0 The correction value is positive, i.e., frequency will be decreased. 1 The correction value is negative, i.e., frequency will be increased. Bits 6:0 – VALUE[6:0] Correction Value These bits define the amount of correction applied to the RTC prescaler. 1–127: The RTC frequency is adjusted according to the value. Value Description 0 Correction is disabled and the RTC frequency is unchanged. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 258

19.8.20 Counter Value - MODE0

Name: COUNT Offset: 0x10 Reset: 0x00000000 Property: Read-Synchronized, Write-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 COUNT[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 COUNT[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COUNT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – COUNT[31:0] Counter Value These bits define the value of the 32-bit RTC counter. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 259

19.8.21 Counter Value - MODE1

Name: COUNT Offset: 0x10 Reset: 0x0000 Property: Read-Synchronized, Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 COUNT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – COUNT[15:0] Counter Value These bits define the value of the 16-bit RTC counter. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 260

19.8.22 Clock Value - MODE2

Name: CLOCK Offset: 0x10 Reset: 0x00000000 Property: Read-Synchronized, Write-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 YEAR[5:0] MONTH[3:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 MONTH[1:0] DAY[4:0] HOUR[4] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 HOUR[3:0] MINUTE[5:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MINUTE[1:0] SECOND[5:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:26 – YEAR[5:0] Year The year offset with respect to the reference year (defined in software). The year is considered a leap year if YEAR[1:0] is zero. Bits 25:22 – MONTH[3:0] Month 1 – January 2 – February ... 12 – December Bits 21:17 – DAY[4:0] Day Day starts at 1 and ends at 28, 29, 30 or 31, depending on the month and year. Bits 16:12 – HOUR[4:0] Hour When CTRL.CLKREP is zero, the Hour bit group is in 24-hour format, with values 0-23. When CTRL.CLKREP is one, HOUR[3:0] has values 1-12 and HOUR[4] represents AM (0) or PM (1). Table 19-4. Hour HOUR[4:0] CLOCK.HOUR[4] CLOCK.HOUR[3:0] Description 0 0x00 - 0x17 Hour (0 - 23) 0x18 - 0x1F Reserved 1 0 0x0 Reserved 0x1 - 0xC AM Hour (1 - 12) 0xD - 0xF Reserved 1 0x0 Reserved 0x1 - 0xC PM Hour (1 - 12) 0xF - 0xF Reserved SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 261

19.8.23 Counter Period - MODE1

Name: PER Offset: 0x14 Reset: 0x0000 Property: Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 PER[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PER[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – PER[15:0] Counter Period These bits define the value of the 16-bit RTC period. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 263

19.8.24 Compare n Value - MODE0

Name: COMP Offset: 0x18 Reset: 0x00000000 Property: Write-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 COMP[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 COMP[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COMP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COMP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – COMP[31:0] Compare Value The 32-bit value of COMPn is continuously compared with the 32-bit COUNT value. When a match occurs, the Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next counter cycle, and the counter value is cleared if CTRL.MATCHCLR is one. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 264

19.8.25 Compare n Value - MODE1

Name: COMPn Offset: 0x18+n*0x2 [n=0..1] Reset: 0x0000 Property: Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 COMP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COMP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – COMP[15:0] Compare Value The 16-bit value of COMPn is continuously compared with the 16-bit COUNT value. When a match occurs, the Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next counter cycle. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 265

19.8.26 Alarm 0 Value - MODE2

Name: ALARM0 Offset: 0x18 Reset: 0x00000000 Property: Write-Protected, Write-Synchronized The 32-bit value of ALARM0 is continuously compared with the 32-bit CLOCK value, based on the masking set by MASKn.SEL. When a match occurs, the Alarm 0 interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.ALARMn) is set on the next counter cycle, and the counter is cleared if CTRL.MATCHCLR is one. Bit 31 30 29 28 27 26 25 24 YEAR[5:0] MONTH[3:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 MONTH[1:0] DAY[4:0] HOUR[4] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 HOUR[3:0] MINUTE[5:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MINUTE[1:0] SECOND[5:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:26 – YEAR[5:0] Year The alarm year. Years are only matched if MASKn.SEL is 6. Bits 25:22 – MONTH[3:0] Month The alarm month. Months are matched only if MASKn.SEL is greater than 4. Bits 21:17 – DAY[4:0] Day The alarm day. Days are matched only if MASKn.SEL is greater than 3. Bits 16:12 – HOUR[4:0] Hour The alarm hour. Hours are matched only if MASKn.SEL is greater than 2. Bits 11:6 – MINUTE[5:0] Minute The alarm minute. Minutes are matched only if MASKn.SEL is greater than 1. Bits 5:0 – SECOND[5:0] Second The alarm second. Seconds are matched only if MASKn.SEL is greater than 0. SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 266

19.8.27 Alarm n Mask - MODE2

Name: MASK Offset: 0x1C Reset: 0x00 Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 3 2 1 0 SEL[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 2:0 – SEL[2:0] Alarm Mask Selection These bits define which bit groups of Alarm n are valid. SEL[2:0] Name Description 0x0 OFF Alarm Disabled 0x1 SS Match seconds only 0x2 MMSS Match seconds and minutes only 0x3 HHMMSS Match seconds, minutes, and hours only 0x4 DDHHMMSS Match seconds, minutes, hours, and days only 0x5 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x6 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x7 Reserved SAM D21/DA1 Family RTC – Real-Time Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 267

DMAC – Direct Memory Access Controller

20.1 Overview

The Direct Memory Access Controller (DMAC) contains both a Direct Memory Access (DMA) engine and a Cyclic Redundancy Check (CRC) engine. The DMAC can transfer data between memories and peripherals and therefore, off-load these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time. With access to all peripherals, the DMAC can handle automatic transfer of data between communication modules. The DMA part of the DMAC has several DMA channels, which can receive different types of transfer triggers and generate transfer requests from the DMA channels to the arbiter (Refer to the Block Diagram). The arbiter will select one DMA channel at a time to act as the active channel. When an active channel has been selected, the fetch engine of the DMAC will fetch a transfer descriptor from the SRAM and store it in the internal memory of the active channel, which will then execute the data transmission. An ongoing data transfer of an active channel can be interrupted by a higher prioritized DMA channel. The DMAC will write back the updated transfer descriptor from the internal memory of the active channel to SRAM, and grant the higher prioritized channel a start transfer as the new active channel. Once a DMA channel is done with its transfer, interrupts and events can be generated optionally. The DMAC has four bus interfaces:

The data transfer bus is used for performing the actual DMA transfer.
The AHB/APB Bridge bus is used when writing and reading the I/O registers of the DMAC.
The descriptor fetch bus is used by the fetch engine to fetch transfer descriptors before data transfer can be started or continued.
The write-back bus is used to write the transfer descriptor back to SRAM. All buses are AHB host interfaces except the AHB/APB Bridge bus, which is an APB client interface. The CRC engine can be used by software to detect an accidental error in the transferred data and to take corrective action, such as requesting the data to be sent again or simply not using the incorrect data.

20.2 Features

Data Transfer From: – Peripheral-to-peripheral – Peripheral-to-memory – Memory-to-peripheral – Memory-to-memory
Transfer Trigger Sources: – Software – Events from Event System – Dedicated requests from peripherals
SRAM-based Transfer Descriptors: – Single transfer using one descriptor – Multi-buffer or Circular Buffer modes by linking multiple descriptors
Up to 12 Channels: – Enable 12 independent transfers – Automatic descriptor fetch for each channel – Suspend/resume operation support for each channel
Flexible Arbitration Scheme: – 4 configurable priority levels for each channel SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 268

– Fixed or round-robin priority scheme within each priority level

From 1 to 256KB Data Transfer in a Single Block Transfer
Multiple Addressing Modes: – Static – Configurable increment scheme
Optional Interrupt Generation: – On block transfer complete – On error detection – On channel suspend
4 Event Inputs: – One event input for each of the 4 least significant DMA channels – Can be selected to trigger normal transfers, periodic transfers or conditional transfers – Can be selected to suspend or resume channel operation
4 Event Outputs: – One output event for each of the 4 least significant DMA channels – Selectable generation on AHB, block, or transaction transfer complete
Error Management Supported by Write-back Function: – Dedicated write-back memory section for each channel to store ongoing descriptor transfer
CRC Polynomial Software Selectable to: – CRC-16 (CRC-CCITT) – CRC-32 (IEEE ® 802.3)

20.3 Block Diagram

Figure 20-1. DMAC Block Diagram HIGH SPEED BUS MATRIX AHB/APB Bridge CPU SRAM S S M M Events Channel 0 Channel 1 Channel n Arbiter DMA Channels HOST Active Channel CRC Engine Fetch Engine Interrupt / Events DMAC Interrupts Transfer Triggers n Data Transfer Write-back Descriptor Fetch SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 269

20.4 Signal Description

Not applicable.

20.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

20.5.1 I/O Lines

Not applicable.

20.5.2 Power Management

The DMAC will continue to operate in IDLE 0 mode where the selected source clock is running. The DMAC’s interrupts can be used to wake-up the device from Sleep modes. Events connected to the event system can trigger other operations in the system without exiting Sleep modes. On hardware or software Reset, all registers are set to their Reset value. Related Links 16. PM – Power Manager

20.5.3 Clocks

The DMAC bus clock (CLK_DMAC_APB) must be configured and enabled in the Power Manager before using the DMAC. An AHB clock (CLK_DMAC_AHB) is required to clock the DMAC. This clock must be configured and enabled in the power manager before using the DMAC, and the default state of CLK_DMAC_AHB can be found in Peripheral Clock Masking. This bus clock (CLK_DMAC_APB) is always synchronous to the module clock (CLK_DMAC_AHB), but can be divided by a prescaler and may run even when the module clock is turned off. Related Links

20.5.4 DMA

Not applicable.

20.5.5 Interrupts

The interrupt request line is connected to the interrupt controller. Using the DMAC interrupt requires the interrupt controller to be configured first. Related Links

20.5.6 Events

Not applicable. Related Links 24. EVSYS – Event System

20.5.7 Debug Operation

When the CPU is halted in debug mode the DMAC will halt normal operation. The DMAC can be forced to continue operation during debugging. Refer to 20.8.6 DBGCTRL for details.

20.5.8 Register Access Protection

All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers: SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 270

Interrupt Pending register (INTPEND)
Channel ID register (CHID)
Channel Interrupt Flag Status and Clear register (CHINTFLAG) Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger. Related Links

20.5.9 Analog Connections

Not applicable.

20.6 Functional Description

20.6.1 Principle of Operation

The DMAC consists of a DMA module and a CRC module.

20.6.1.1 DMA

The DMAC can transfer data between memories and peripherals without interaction from the CPU. The data transferred by the DMAC are called transactions, and these transactions can be split into smaller data transfers. The following figure shows the relationship between the different transfer sizes: Figure 20-2. DMA Transfer Sizes DMA transaction Block transfer Link Enabled Burst transfer Link EnabledLink Enabled Beat transfer

Beat transfer: The size of one data transfer bus access, and the size is selected by writing the Beat Size bit group in the Block Transfer Control register (BTCTRL.BEATSIZE)
Burst transfer: Defined as n beat transfers, where n will differ from one device family to another. A burst transfer is atomic, cannot be interrupted and the length of the burst is selected by writing the Burst Length bit group in each Channel n Control A register (CHCTRLA.BURSTLEN).
Block transfer: The amount of data one transfer descriptor can transfer, and the amount can range from 1 to 64k beats. A block transfer can be interrupted, in contrast to the burst transfer.
Transaction: The DMAC can link several transfer descriptors by having the first descriptor pointing to the second and so forth, as shown in the figure above. A DMA transaction is the complete transfer of all blocks within a linked list. A transfer descriptor describes how a block transfer should be carried out by the DMAC, and it must remain in SRAM. For further details on the transfer descriptor refer to 20.6.2.3 Transfer Descriptors. The figure above shows several block transfers linked together, which are called linked descriptors. For further information about linked descriptors, refer to 20.6.3.1 Linked Descriptors. A DMA transfer is initiated by an incoming transfer trigger on one of the DMA channels. This trigger can be configured to be either a software trigger, an event trigger, or one of the dedicated peripheral triggers. The transfer trigger will result in a DMA transfer request from the specific channel to the arbiter. If there are several DMA channels with pending transfer requests, the arbiter chooses which channel is granted access to become the active channel. The DMA channel granted access as the active channel will carry out the transaction as configured in the transfer SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 271

descriptor. A current transaction can be interrupted by a higher prioritized channel after each burst transfer, but will resume the block transfer when the according DMA channel is granted access as the active channel again. For each beat transfer, an optional output event can be generated. For each block transfer, optional interrupts and an optional output event can be generated. When a transaction is completed, dependent of the configuration, the DMA channel will either be suspended or disabled.

20.6.1.2 CRC

The internal CRC engine supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and CRC-32 (IEEE details.

20.6.2 Basic Operation

20.6.2.1 Initialization

The following DMAC registers are enable-protected, meaning that they can only be written when the DMAC is disabled (CTRL.DMAENABLE=0):

Descriptor Base Memory Address register (BASEADDR)
Write-Back Memory Base Address register (WRBADDR) The following DMAC bit is enable-protected, meaning that it can only be written when both the DMAC and CRC are disabled (CTRL.DMAENABLE=0 and CTRL.CRCENABLE=0):
Software Reset bit in Control register (CTRL.SWRST) The following DMA channel register is enable-protected, meaning that it can only be written when the corresponding DMA channel is disabled (CHCTRLA.ENABLE=0):
Channel Control B (CHCTRLB) register, except the Command bit (CHCTRLB.CMD) and the Channel Arbitration Level bit (CHCTRLB.LVL) The following DMA channel bit is enable-protected, meaning that it can only be written when the corresponding DMA channel is disabled:
Channel Software Reset bit in Channel Control A register (CHCTRLA.SWRST) The following CRC registers are enable-protected, meaning that they can only be written when the CRC is disabled (CTRL.CRCENABLE=0):
CRC Control register (CRCCTRL)
CRC Checksum register (CRCCHKSUM) Enable-protection is denoted by the "Enable-Protected" property in the register description. Before the DMAC is enabled it must be configured, as outlined by the following steps:
The SRAM address of where the descriptor memory section is located must be written to the Description Base Address (BASEADDR) register
The SRAM address of where the write-back section should be located must be written to the Write-Back Memory Base Address (WRBADDR) register
Priority level x of the arbiter can be enabled by setting the Priority Level x Enable bit in the Control register (CTRL.LVLENx=1) Before a DMA channel is enabled, the DMA channel and the corresponding first transfer descriptor must be configured, as outlined by the following steps:
DMA channel configurations – The channel number of the DMA channel to configure must be written to the Channel ID (CHID) register – Trigger action must be selected by writing the Trigger Action bit group in the Channel Control B register (CHCTRLB.TRIGACT) – Trigger source must be selected by writing the Trigger Source bit group in the Channel Control B register (CHCTRLB.TRIGSRC)
Transfer Descriptor SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 272

– The size of each access of the data transfer bus must be selected by writing the Beat Size bit group in the Block Transfer Control register (BTCTRL.BEATSIZE) – The transfer descriptor must be made valid by writing a one to the Valid bit in the Block Transfer Control register (BTCTRL.VALID) – Number of beats in the block transfer must be selected by writing the Block Transfer Count (BTCNT) register – Source address for the block transfer must be selected by writing the Block Transfer Source Address (SRCADDR) register – Destination address for the block transfer must be selected by writing the Block Transfer Destination Address (DSTADDR) register If CRC calculation is needed, the CRC engine must be configured before it is enabled, as outlined by the following steps:

The CRC input source must selected by writing the CRC Input Source bit group in the CRC Control register (CRCCTRL.CRCSRC)
The type of CRC calculation must be selected by writing the CRC Polynomial Type bit group in the CRC Control register (CRCCTRL.CRCPOLY)
If I/O is selected as input source, the beat size must be selected by writing the CRC Beat Size bit group in the CRC Control register (CRCCTRL.CRCBEATSIZE)

20.6.2.2 Enabling, Disabling, and Resetting

The DMAC is enabled by writing the DMA Enable bit in the Control register (CTRL.DMAENABLE) to '1'. The DMAC is disabled by writing a '0' to CTRL.DMAENABLE. A DMA channel is enabled by writing the Enable bit in the Channel Control A register (CHCTRLA.ENABLE) to '1', after writing the corresponding channel id to the Channel ID bit group in the Channel ID register (CHID.ID). A DMA channel is disabled by writing a '0' to CHCTRLA.ENABLE. The CRC is enabled by writing a '1' to the CRC Enable bit in the Control register (CTRL.CRCENABLE). The CRC is disabled by writing a '0' to CTRL.CRCENABLE. The DMAC is reset by writing a '1' to the Software Reset bit in the Control register (CTRL.SWRST) while the DMAC and CRC are disabled. All registers in the DMAC except DBGCTRL will be reset to their initial state. A DMA channel is reset by writing a '1' to the Software Reset bit in the Channel Control A register (CHCTRLA.SWRST), after writing the corresponding channel id to the Channel ID bit group in the Channel ID register (CHID.ID). The channel registers will be reset to their initial state. The corresponding DMA channel must be disabled in order for the reset to take effect.

20.6.2.3 Transfer Descriptors

Together with the channel configurations the transfer descriptors decides how a block transfer should be executed. Before a DMA channel is enabled (CHCTRLA.ENABLE is written to one), and receives a transfer trigger, its first transfer descriptor has to be initialized and valid (BTCTRL.VALID). The first transfer descriptor describes the first block transfer of a transaction. All transfer descriptors must reside in SRAM. The addresses stored in the Descriptor Memory Section Base Address (BASEADDR) and Write-Back Memory Section Base Address (WRBADDR) registers tell the DMAC where to find the descriptor memory section and the write-back memory section. The descriptor memory section is where the DMAC expects to find the first transfer descriptors for all DMA channels. As BASEADDR points only to the first transfer descriptor of channel 0 (see figure below), all first transfer descriptors must be stored in a contiguous memory section, where the transfer descriptors must be ordered according to their The write-back memory section is the section where the DMAC stores the transfer descriptors for the ongoing block transfers. WRBADDR points to the ongoing transfer descriptor of channel 0. All ongoing transfer descriptors will be stored in a contiguous memory section where the transfer descriptors are ordered according to their channel number. The figure below shows an example of linked descriptors on DMA channel 0. For further details on linked descriptors, refer to 20.6.3.1 Linked Descriptors. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 273

Figure 20-3. Memory Sections Channel 0 – Descriptor n-1 Channel 0 – Last Descriptor DESCADDR DESCADDR Device Memory Space BASEADDR Channel 0 – First Descriptor Channel 1 – First Descriptor Channel 2 – First Descriptor Channel n – First Descriptor Descriptor Section WRBADDR Channel 0 Ongoing Descriptor Channel 1 Ongoing Descriptor Channel 2 Ongoing Descriptor Channel n Ongoing Descriptor Write-Back Section Undefined Undefined Undefined Undefined Undefined SRCADDR DSTADDR BTCTRL DESCADDR BTCNT SRCADDR DSTADDR BTCTRL DESCADDR BTCNT SRCADDR DSTADDR BTCTRL 0x00000000 BTCNT The size of the descriptor and write-back memory sections is dependent on the number of the most significant enabled DMA channel m, as shown below: Si z e = 128 bits ⋅ m + 1 For memory optimization, it is recommended to always use the less significant DMA channels if not all channels are required. The descriptor and write-back memory sections can either be two separate memory sections, or they can share memory section (BASEADDR=WRBADDR). The benefit of having them in two separate sections, is that the same transaction for a channel can be repeated without having to modify the first transfer descriptor. The benefit of having descriptor memory and write-back memory in the same section is that it requires less SRAM. In addition, the latency from fetching the first descriptor of a transaction to the first burst transfer is executed, is reduced.

20.6.2.4 Arbitration

If a DMA channel is enabled and not suspended when it receives a transfer trigger, it will send a transfer request to the arbiter. When the arbiter receives the transfer request it will include the DMA channel in the queue of channels having pending transfers, and the corresponding Pending Channel x bit in the Pending Channels registers (PENDCH.PENDCHx) will be set. Depending on the arbitration scheme, the arbiter will choose which DMA channel will be the next active channel. The active channel is the DMA channel being granted access to perform its next burst transfer. When the arbiter has granted a DMA channel access to the DMAC, the corresponding bit PENDCH.PENDCHx will be cleared. See also the following figure. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 274

If the upcoming burst transfer is the first for the transfer request, the corresponding Busy Channel x bit in the Busy Channels register will be set (BUSYCH.BUSYCHx=1), and it will remain '1' for the subsequent granted burst transfers. When the channel has performed its granted burst transfer(s) it will be either fed into the queue of channels with pending transfers, set to be waiting for a new transfer trigger, suspended, or disabled. This depends on the channel and block transfer configuration. If the DMA channel is fed into the queue of channels with pending transfers, the corresponding BUSYCH.BUSYCHx will remain '1'. If the DMA channel is set to wait for a new transfer trigger, suspended, or disabled, the corresponding BUSYCH.BUSYCHx will be cleared. If a DMA channel is suspended while it has a pending transfer, it will be removed from the queue of pending channels, but the corresponding PENDCH.PENDCHx will remain set. When the same DMA channel is resumed, it will be added to the queue of pending channels again. If a DMA channel gets disabled (CHCTRLA.ENABLE=0) while it has a pending transfer, it will be removed from the queue of pending channels, and the corresponding PENDCH.PENDCHx will be cleared. Figure 20-4. Arbiter Overview Channel 0 Channel N Active Channel Priority decoder Active.LVLEXx PRICTRLx.LVLPRI Arbiter CTRL.LVLENx Burst Done Transfer Request Channel Number Level Enable Channel Burst Done Channel Priority Level Channel Pending Channel Suspend Channel Burst Done Channel Priority Level Channel Pending Channel Suspend Priority Levels When a channel level is pending or the channel is transferring data, the corresponding Level Executing bit is set in the Active Channel and Levels register (ACTIVE.LVLEXx). Each DMA channel supports a 4-level priority scheme. The priority level for a channel is configured by writing to the Channel Arbitration Level bit group in the Channel Control B register (CHCTRLB.LVL). As long as all priority levels are enabled, a channel with a higher priority level number will have priority over a channel with a lower priority level number. Each priority level x is enabled by setting the corresponding Priority Level x Enable bit in the Control register (CTRL.LVLENx=1). Within each priority level the DMAC's arbiter can be configured to prioritize statically or dynamically: Static Arbitration within a priority level is selected by writing a '0' to the Level x Round-Robin Scheduling Enable bit in the Priority Control 0 register (PRICTRL0.RRLVLENx). When static arbitration is selected, the arbiter will prioritize a low channel number over a high channel number as shown in the figure below. When using the static arbitration there is a risk of high channel numbers never being granted access as the active channel. This can be avoided using a dynamic arbitration scheme. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 275

Figure 20-5. Static Priority Scheduling Highest Channel Lowest Channel Highest Priority Lowest PriorityChannel N Channel 0 Channel x+1 Channel x Dynamic Arbitration within a priority level is selected by writing a '1' to PRICTRL0.RRLVLENx. The dynamic arbitration scheme in the DMAC is round-robin. With the round-robin scheme, the channel number of the last channel being granted access will have the lowest priority the next time the arbiter has to grant access to a channel within the same priority level, as shown in Figure 20-6. The channel number of the last channel being granted access as the active channel is stored in the Level x Channel Priority Number bit group in the Priority Control 0 register (PRICTRL0.LVLPRIx) for the corresponding priority level. Figure 20-6. Dynamic (Round-Robin) Priority Scheduling Channel N Channel N Channel 0 Channel x Channel x+1 Channel x last acknowledge request Channel (x+1) last acknowledge request Channel 0 Channel x Channel x+1 Channel x+2 Lowest Priority Highest Priority Highest Priority Lowest Priority

20.6.2.5 Data Transmission

Before the DMAC can perform a data transmission, a DMA channel has to be configured and enabled, its corresponding transfer descriptor has to be initialized, and the arbiter has to grant the DMA channel access as the active channel. Once the arbiter has granted a DMA channel access as the active channel (refer to DMA Block Diagram section) the transfer descriptor for the DMA channel will be fetched from SRAM using the fetch bus, and stored in the internal memory for the active channel. For a new block transfer, the transfer descriptor will be fetched from the descriptor memory section (BASEADDR); For an ongoing block transfer, the descriptor will be fetched from the write-back SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 276

memory section (WRBADDR). By using the data transfer bus, the DMAC will read the data from the current source address and write it to the current destination address. For further details on how the current source and destination addresses are calculated, refer to the section on Addressing. The arbitration procedure is performed after each burst transfer. If the current DMA channel is granted access again, the block transfer counter (BTCNT) of the internal transfer descriptor will be decremented by the number of beats in a burst transfer, the optional output event Beat will be generated if configured and enabled, and the active channel will perform a new burst transfer. If a different DMA channel than the current active channel is granted access, the block transfer counter value will be written to the write-back section before the transfer descriptor of the newly granted DMA channel is fetched into the internal memory of the active channel. When a block transfer has come to its end (BTCNT is zero), the Valid bit in the Block Transfer Control register will be cleared (BTCTRL.VALID=0) before the entire transfer descriptor is written to the write-back memory. The optional interrupts, Channel Transfer Complete and Channel Suspend, and the optional output event Block, will be generated if configured and enabled. After the last block transfer in a transaction, the Next Descriptor Address register (DESCADDR) will hold the value 0x00000000, and the DMA channel will either be suspended or disabled, depending on the configuration in the Block Action bit group in the Block Transfer Control register (BTCTRL.BLOCKACT). If the transaction has further block transfers pending, DESCADDR will hold the SRAM address to the next transfer descriptor to be fetched. The DMAC will fetch the next descriptor into the internal memory of the active channel and write its content to the write-back section for the channel, before the arbiter gets to choose the next active channel.

20.6.2.6 Transfer Triggers and Actions

A DMA transfer through a DMA channel can be started only when a DMA transfer request is detected, and the DMA channel has been granted access to the DMA. A transfer request can be triggered from software, from a peripheral, or from an event. There are dedicated Trigger Source selections for each DMA Channel Control B (CHCTRLB.TRIGSRC). The trigger actions are available in the Trigger Action bit group in the Channel Control B register (CHCTRLB.TRIGACT). By default, a trigger generates a request for a block transfer operation. If a single descriptor is defined for a channel, the channel is automatically disabled when a block transfer has been completed. If a list of linked descriptors is defined for a channel, the channel is automatically disabled when the last descriptor in the list is executed. If the list still has descriptors to execute, the channel will be waiting for the next block transfer trigger. When enabled again, the channel will wait for the next block transfer trigger. The trigger actions can also be configured to generate a request for a beat transfer (CHCTRLB.TRIGACT=0x2) or transaction transfer (CHCTRLB.TRIGACT=0x3) instead of a block transfer (CHCTRLB.TRIGACT=0x0). Figure 20-7 shows an example where triggers are used with two linked block descriptors. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 277

Figure 20-7. Trigger Action and Transfers CHENn Trigger PENDCHn BUSYCHn Data Transfer CHENn Trigger PENDCHn BUSYCHn Data Transfer CHENn Trigger PENDCHn BUSYCHn Data Transfer Block Transfer Block TransferBlock Transfer Block TransferBlock Transfer Block Transfer Trigger Lost Trigger Lost Trigger Lost Transaction Trigger Action Block Trigger Action Beat Trigger Action BEATBEAT BEAT BEAT BEATBEAT BEATBEAT BEAT BEAT BEATBEAT BEATBEAT BEAT BEAT BEATBEAT If the trigger source generates a transfer request for a channel during an ongoing transfer, the new transfer request will be kept pending (CHSTATUS.PEND=1), and the new transfer can start after the ongoing one is done. Only one pending transfer can be kept per channel. If the trigger source generates more transfer requests while one is already pending, the additional ones will be lost. All channels pending status flags are also available in the Pending Channels register (PENDCH). When the transfer starts, the corresponding Channel Busy status flag is set in Channel Status register (CHSTATUS.BUSY). When the trigger action is complete, the Channel Busy status flag is cleared. All channel busy status flags are also available in the Busy Channels register (BUSYCH) in DMAC.

20.6.2.7 Addressing

Each block transfer needs to have both a source address and a destination address defined. The source address is set by writing the Transfer Source Address (SRCADDR) register, the destination address is set by writing the Transfer Destination Address (SRCADDR) register. The addressing of this DMAC module can be static or incremental, for either source or destination of a block transfer, or both. Incrementation for the source address of a block transfer is enabled by writing the Source Address Incrementation Enable bit in the Block Transfer Control register (BTCTRL.SRCINC=1). The step size of the incrementation is configurable and can be chosen by writing the Step Selection bit in the Block Transfer Control register (BTCTRL.STEPSEL=1) and writing the desired step size in the Address Increment Step Size bit group in the Block Transfer Control register (BTCTRL.STEPSIZE). If BTCTRL.STEPSEL=0, the step size for the source incrementation will be the size of one beat. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 278

When source address incrementation is configured (BTCTRL.SRCINC=1), SRCADDR is calculated as follows: If BTCTRL.STEPSEL=1: SRCADDR = SRCADDR ST A RT + BTC NT ⋅ B E A TSI ZE + 1 ⋅ 2 STEPSIZE If BTCTRL.STEPSEL=0: SRCADDR = SRCADDR ST A RT + BTC NT ⋅ BE A TSI ZE + 1

SRCADDR START is the source address of the first beat transfer in the block transfer
BTCNT is the initial number of beats remaining in the block transfer
BEATSIZE is the configured number of bytes in a beat
STEPSIZE is the configured number of beats for each incrementation The following figure shows an example where DMA channel 0 is configured to increment the source address by one beat after each beat transfer (BTCTRL.SRCINC=1), and DMA channel 1 is configured to increment the source address by two beats (BTCTRL.SRCINC=1, BTCTRL.STEPSEL=1, and BTCTRL.STEPSIZE=0x1). As the destination address for both channels are peripherals, destination incrementation is disabled (BTCTRL.DSTINC=0). Figure 20-8. Source Address Increment SRC Data Buffer a b c d e f Incrementation for the destination address of a block transfer is enabled by setting the Destination Address Incrementation Enable bit in the Block Transfer Control register (BTCTRL.DSTINC=1). The step size of the incrementation is configurable by clearing BTCTRL.STEPSEL=0 and writing BTCTRL.STEPSIZE to the desired step size. If BTCTRL.STEPSEL=1, the step size for the destination incrementation will be the size of one beat. When the destination address incrementation is configured (BTCTRL.DSTINC=1), DSTADDR must be set and calculated as follows: DS T A DDR = D ST A DDR S T AR T + B TC NT • BE A TSI ZE + 1 • 2 STE PSI ZE where BTCTRL.STEPSEL is zero DS T A DDR = D ST A DDR S T AR T + B TC NT • BE AT SI ZE + 1 where BTCTRL.STEPSEL is one
DSTADDR START is the destination address of the first beat transfer in the block transfer
BTCNT is the initial number of beats remaining in the block transfer
BEATSIZE is the configured number of bytes in a beat
STEPSIZE is the configured number of beats for each incrementation The followiong figure shows an example where DMA channel 0 is configured to increment destination address by one beat (BTCTRL.DSTINC=1) and DMA channel 1 is configured to increment destination address by two beats (BTCTRL.DSTINC=1, BTCTRL.STEPSEL=0, and BTCTRL.STEPSIZE=0x1). As the source address for both channels are peripherals, source incrementation is disabled (BTCTRL.SRCINC=0). SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 279

Figure 20-9. Destination Address Increment DST Data Buffer a b c d

20.6.2.8 Error Handling

If a bus error is received from an AHB client during a DMA data transfer, the corresponding active channel is disabled and the corresponding Channel Transfer Error Interrupt flag in the Channel Interrupt Status and Clear register (CHINTFLAG.TERR) is set. If enabled, the optional transfer error interrupt is generated. The transfer counter will not be decremented and its current value is written-back in the write-back memory section before the channel is disabled. When the DMAC fetches an invalid descriptor (BTCTRL.VALID=0) or when the channel is resumed and the DMA fetches the next descriptor with null address (DESCADDR=0x00000000), the corresponding channel operation is suspended, the Channel Suspend Interrupt Flag in the Channel Interrupt Flag Status and Clear register (CHINTFLAG.SUSP) is set, and the Channel Fetch Error bit in the Channel Status register (CHSTATUS.FERR) is set. If enabled, the optional suspend interrupt is generated.

20.6.3 Additional Features

20.6.3.1 Linked Descriptors

A transaction can consist of either a single block transfer or of several block transfers. When a transaction consists of several block transfers it is done with the help of linked descriptors. Figure 20-3 illustrates how linked descriptors work. When the first block transfer is completed on DMA channel 0, the DMAC fetches the next transfer descriptor, which is pointed to by the value stored in the Next Descriptor Address (DESCADDR) register of the first transfer descriptor. Fetching the next transfer descriptor (DESCADDR) is continued until the last transfer descriptor. When the block transfer for the last transfer descriptor is executed and DESCADDR=0x00000000, the transaction is terminated. For further details on how the next descriptor is fetched from SRAM, refer to section 20.6.2.5 Data Transmission.

20.6.3.1.1 Adding Descriptor to the End of a List

To add a new descriptor at the end of the descriptor list, create the descriptor in SRAM, with DESCADDR=0x00000000 indicating that it is the new last descriptor in the list, and modify the DESCADDR value of the current last descriptor to the address of the newly created descriptor.

20.6.3.1.2 Modifying a Descriptor in a List

In order to add descriptors to a linked list, the following actions must be performed: 1. Enable the Suspend interrupt for the DMA channel. 2. Enable the DMA channel. 3. Reserve memory space in SRAM to configure a new descriptor. 4. Configure the new descriptor: – Set the next descriptor address ( DESCADDR) – Set the destination address ( DSTADDR) – Set the source address ( SRCADDR) – Configure the block transfer control ( BTCTRL) including

Optionally enable the Suspend block action SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 280

Set the descriptor VALID bit 5. Clear the VALID bit for the existing list and for the descriptor which has to be updated. 6. Read DESCADDR from the Write-Back memory. – If the DMA has not already fetched the descriptor which requires changes (i.e., DESCADDR is wrong):
Update the DESCADDR location of the descriptor from the List
Optionally clear the Suspend block action
Set the descriptor VALID bit to '1'
Optionally enable the Resume software command – If the DMA is executing the same descriptor as the one which requires changes:
Set the Channel Suspend software command and wait for the Suspend interrupt
Update the next descriptor address ( DESCRADDR) in the write-back memory
Clear the interrupt sources and set the Resume software command
Update the DESCADDR location of the descriptor from the List
Optionally clear the Suspend block action
Set the descriptor VALID bit to '1' 7. Go to step 4 if needed.

20.6.3.1.3 Adding a Descriptor Between Existing Descriptors

To insert a new descriptor 'C' between two existing descriptors ('A' and 'B'), the descriptor currently executed by the DMA must be identified. 1. If DMA is executing descriptor B, descriptor C cannot be inserted. 2. If DMA has not started to execute descriptor A, follow the steps: 2.1. Set the descriptor A VALID bit to '0'. 2.2. Set the DESCADDR value of descriptor A to point to descriptor C instead of descriptor B. 2.3. Set the DESCADDR value of descriptor C to point to descriptor B. 2.4. Set the descriptor A VALID bit to '1'. 3. If DMA is executing descriptor A: 3.1. Apply the software suspend command to the channel and 3.3. Apply the software resume command to the channel.

20.6.3.2 Channel Suspend

The channel operation can be suspended at any time by software by writing a '1' to the Suspend command in the Command bit field of Channel Control B register (CHCTRLB.CMD). After the ongoing burst transfer is completed, the channel operation is suspended and the suspend command is automatically cleared. When suspended, the Channel Suspend Interrupt flag in the Channel Interrupt Status and Clear register is set (CHINTFLAG.SUSP=1) and the optional suspend interrupt is generated. By configuring the block action to suspend by writing Block Action bit group in the Block Transfer Control register (BTCTRL.BLOCKACT is 0x2 or 0x3), the DMA channel will be suspended after it has completed a block transfer. The DMA channel will be kept enabled and will be able to receive transfer triggers, but it will be removed from the arbitration scheme. If an invalid transfer descriptor (BTCTRL.VALID=0) is fetched from SRAM, the DMA channel will be suspended, and the Channel Fetch Error bit in the Channel Status register(CHASTATUS.FERR) will be set. Note: Only enabled DMA channels can be suspended. If a channel is disabled when it is attempted to be suspended, the internal suspend command will be ignored. For more details on transfer descriptors, refer to section 20.6.2.3 Transfer Descriptors.

20.6.3.3 Channel Resume and Next Suspend Skip

A channel operation can be resumed by software by setting the Resume command in the Command bit field of the Channel Control B register (CHCTRLB.CMD). If the channel is already suspended, the channel operation resumes from where it previously stopped when the Resume command is detected. When the Resume command is SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 281

issued before the channel is suspended, the next suspend action is skipped and the channel continues the normal operation. Figure 20-10. Channel Suspend/Resume Operation CHENn Memory Descriptor Transfer Resume Command Descriptor 0 (suspend disabled) Fetch Block Transfer 0 Descriptor 1 (suspend enabled) Block Transfer 1 Suspend skipped Descriptor 2 (suspend enabled) Block Transfer 2 Channel suspended Descriptor 3 (last) Block Transfer 3

20.6.3.4 Event Input Actions

The event input actions are available only on the least significant DMA channels. For details on channels with event input support, refer to the in the Event system documentation. Before using event input actions, the event controller must be configured first according to the following table, and the Channel Event Input Enable bit in the Channel Control B register (CHCTRLB.EVIE) must be written to '1'. Refer also to 20.6.6 Events. Table 20-1. Event Input Action Action CHCTRLB.EVACT CHCTRLB.TRGSRC None NOACT - Normal Transfer TRIG DISABLE Conditional Transfer on Strobe TRIG any peripheral Conditional Transfer CTRIG Conditional Block Transfer CBLOCK Channel Suspend SUSPEND Channel Resume RESUME Skip Next Block Suspend SSKIP Normal Transfer The event input is used to trigger a beat or burst transfer on peripherals. The event is acknowledged as soon as the event is received. When received, both the Channel Pending status bit in the Channel Status register (CHSTATUS.PEND) and the corresponding Channel n bit in the Pending Channels register (20.8.13 PENDCH.PENDCHn) are set. If the event is received while the channel is pending, the event trigger is lost. The figure below shows an example where beat transfers are enabled by internal events. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 282

Figure 20-13. Conditional Event with Beat Peripheral Triggers Event Peripheral Trigger PENDCHn Data Transfer Block Transfer BEAT BEAT Conditional Block Transfer The event input is used to trigger a conditional block transfer on peripherals. Before starting transfers within a block, an event must be received. When received, the event is acknowledged when the block transfer is completed. A software trigger will trigger a transfer. The figure below shows an example where conditional event block transfer is started with peripheral beat trigger requests. Figure 20-14. Conditional Block Transfer with Beat Peripheral Triggers BEAT BEAT Block Transfer BEAT BEAT Block Transfer Data Transfer Peripheral Trigger Event PENDCHn Channel Suspend The event input is used to suspend an ongoing channel operation. The event is acknowledged when the current AHB Channel Resume The event input is used to resume a suspended channel operation. The event is acknowledged as soon as the event is received and the Channel Suspend Interrupt Flag (CHINTFLAG.SUSP) is cleared. For further details refer to 20.6.3.2 Channel Suspend. Skip Next Block Suspend This event can be used to skip the next block suspend action. If the channel is suspended before the event rises, the channel operation is resumed and the event is acknowledged. If the event rises before a suspend block action is detected, the event is kept until the next block suspend detection. When the block transfer is completed, the channel continues the operation (not suspended) and the event is acknowledged. Related Links

24.8.3 USER

20.6.3.5 Event Output Selection

Event output selection is available only for the least significant DMA channels. The pulse width of an event output from a channel is one AHB clock cycle. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 284

The output of channel events is enabled by writing a '1' to the Channel Event Output Enable bit in the Control B register (CHCTRLB.EVOE). The event output cause is selected by writing to the Event Output Selection bits in the Block Transfer Control register (BTCTRL.EVOSEL). It is possible to generate events after each block transfer (BTCTRL.EVOSEL=0x1) or beat transfer (BTCTRL.EVOSEL=0x3). To enable an event being generated when a transaction is complete, the block event selection must be set in the last transfer descriptor only. Figure 20-15 shows an example where the event output generation is enabled in the first block transfer, and disabled in the second block. Figure 20-15. Event Output Generation Beat Event Output Data Transfer Event Output Data Transfer Event Output Block Transfer BEAT Block Event Output Block Transfer Block TransferBlock Transfer BEAT BEATBEAT BEAT BEAT BEAT BEAT

20.6.3.6 Aborting Transfers

Transfers on any channel can be aborted gracefully by software by disabling the corresponding DMA channel. It is also possible to abort all ongoing or pending transfers by disabling the DMAC. When a DMA channel disable request or DMAC disable request is detected:

Ongoing transfers of the active channel will be disabled when the ongoing beat transfer is completed and the write-back memory section is updated. This prevents transfer corruption before the channel is disabled.
All other enabled channels will be disabled in the next clock cycle. The corresponding Channel Enable bit in the Channel Control A register is cleared (CHCTRLA.ENABLE=0) when the channel is disabled. The corresponding DMAC Enable bit in the Control register is cleared (CTRL.DMAENABLE=0) when the entire DMAC module is disabled.

20.6.3.7 CRC Operation

A cyclic redundancy check (CRC) is an error detection technique used to find errors in data. It is commonly used to determine whether the data during a transmission, or data present in data and program memories has been corrupted or not. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be appended to the data and used as a checksum. When the data is received, the device or application repeats the calculation: If the new CRC result does not match the one calculated earlier, the block contains a data error. The application will then detect this and may take a corrective action, such as requesting the data to be sent again or simply not using the incorrect data. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 285

The CRC engine in DMAC supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3). Typically, applying CRC-n (CRC-16 or CRC-32) to a data block of arbitrary length will detect any single alteration that is ≤n bits in length, and will detect the fraction 1-2-n of all longer error bursts.

CRC-16: – Polynomial: x 16+ x12+ x5+ 1 – Hex value: 0x1021
CRC-32: – Polynomial: x 32+x26+ x23+ x22+x16+ x12+ x11+ x10+ x8+ x7+ x5+ x4+ x2+ x + 1 – Hex value: 0x04C11DB7 The data source for the CRC engine can either be one of the DMA channels or the APB bus interface, and must be selected by writing to the CRC Input Source bits in the CRC Control register (CRCCTRL.CRCSRC). The CRC engine then takes data input from the selected source and generates a checksum based on these data. The checksum is available in the CRC Checksum register (CRCCHKSUM). When CRC-32 polynomial is used, the final checksum read is bit reversed and complemented, as shown in Figure 20-16. The CRC polynomial is selected by writing to the CRC Polynomial Type bit in the CRC Control register (CRCCTRL.CRCPOLY), the default is CRC-16. The CRC engine operates on byte only. When the DMA is used as data source for the CRC engine, the DMA channel beat size setting will be used. When used with APB bus interface, the application must select the CRC Beat Size bit field of CRC Control register (CRCCTRL.CRCBEATSIZE). 8-, 16-, or 32-bit bus transfer access type is supported. The corresponding number of bytes will be written in the CRCDATAIN register and the CRC engine will operate on the input data in a byte by byte manner. Figure 20-16. CRC Generator Block Diagram 168 8 32 Checksum read crc32 CRCCTRL CHECKSUM bit-reverse + complement CRC-16 CRC-32 DMAC Channels CRCDATAIN SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 286

CRC-16 or CRC-32 calculations can be performed on data passing through any DMA channel. Once a DMA channel is selected as the source, the CRC engine will continuously generate the CRC on the data passing through the DMA channel. The checksum is available for readout once the DMA transaction is completed or aborted. A CRC can also be generated on SRAM, Flash, or I/O memory by passing these data through a DMA channel. If the latter is done, the destination register for the DMA data can be the data input (CRCDATAIN) register in the CRC engine. CRC using the I/O interface Before using the CRC engine with the I/O interface, the application must set the CRC Beat Size bits in the CRC Control register (CRCCTRL.CRCBEATSIZE). 8/16/32-bit bus transfer type can be selected. CRC can be performed on any data by loading them into the CRC engine using the CPU and writing the data to the CRCDATAIN register. Using this method, an arbitrary number of bytes can be written to the register by the CPU, and CRC is done continuously for each byte. This means if a 32-bit data is written to the CRCDATAIN register the CRC engine takes four cycles to calculate the CRC. The CRC complete is signaled by a set CRCBUSY bit in the CRCSTATUS register. New data can be written only when CRCBUSY flag is not set.

20.6.4 DMA Operation

Not applicable.

20.6.5 Interrupts

The DMAC channels have the following interrupt sources:

Transfer Complete (TCMPL): Indicates that a block transfer is completed on the corresponding channel. Refer to 20.6.2.5 Data Transmission for details.
Transfer Error (TERR): Indicates that a bus error has occurred during a burst transfer, or that an invalid
Channel Suspend (SUSP): Indicates that the corresponding channel has been suspended. Refer to Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Channel Interrupt Flag Status and Clear (CHINTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by setting the corresponding bit in the Channel Interrupt Enable Set register (CHINTENSET=1), and disabled by setting the corresponding bit in the Channel Interrupt Enable Clear register (CHINTENCLR=1). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, the DMAC is reset or the corresponding DMA channel is reset. See CHINTFLAG for details on how to clear interrupt flags. All interrupt requests are ORed together on system level to generate one combined interrupt request to the NVIC. The user must read the Channel Interrupt Status (INTSTATUS) register to identify the channels with pending interrupts and must read the Channel Interrupt Flag Status and Clear (CHINTFLAG) register to determine which interrupt condition is present for the corresponding channel. It is also possible to read the Interrupt Pending register (INTPEND), which provides the lowest channel number with pending interrupt and the respective interrupt flags. Note: Interrupts must be globally enabled for interrupt requests to be generated. Related Links

20.6.6 Events

The DMAC can generate the following output events:

Channel (CH): Generated when a block transfer for a given channel has been completed, or when a beat transfer within a block transfer for a given channel has been completed. Refer to Event Output Selection for details. Setting the Channel Event Output Enable bit (CHEVCTRLx.EVOE = 1) enables the corresponding output event configured in the Event Output Selection bit group in the Block Transfer Control register (BTCTRL.EVOSEL). Clearing CHEVCTRLx.EVOE = 0 disables the corresponding output event. The DMAC can take the following actions on an input event: SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 287

Transfer and Periodic Transfer Trigger (TRIG): normal transfer or periodic transfers on peripherals are enabled
Conditional Transfer Trigger (CTRIG): conditional transfers on peripherals are enabled
Conditional Block Transfer Trigger (CBLOCK): conditional block transfers on peripherals are enabled
Channel Suspend Operation (SUSPEND): suspend a channel operation
Channel Resume Operation (RESUME): resume a suspended channel operation
Skip Next Block Suspend Action (SSKIP): skip the next block suspend transfer condition
Increase Priority (INCPRI): increase channel priority Setting the Channel Event Input Enable bit (CHEVCTRLx.EVIE = 1) enables the corresponding action on input event. Clearing this bit disables the corresponding action on input event. Note that several actions can be enabled for incoming events. If several events are connected to the peripheral, any enabled action will be taken for any of the incoming events. For further details on event input actions, refer to Event Input Actions. Note: Event input and outputs are not available for every channel. Refer to the Features section for more information. Related Links 24. EVSYS – Event System

20.6.7 Sleep Mode Operation

The DMAC will continue to operate in IDLE 0 sleep mode. It does not perform transfers in IDLE 1 and IDLE 2 sleep modes, since the AHB clocks are stopped. In Standby Sleep mode, the DMAC will be internally disabled, but maintains its current configuration.

20.6.8 Synchronization

20.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRL 7:0 CRCENABLE DMAENABLE SWRST 15:8 LVLENx3 LVLENx2 LVLENx1 LVLENx0 0x02 CRCCTRL 7:0 CRCPOLY[1:0] CRCBEATSIZE[1:0] 15:8 CRCSRC[5:0] 0x04 CRCDATAIN 7:0 CRCDATAIN[7:0] 15:8 CRCDATAIN[15:8] 23:16 CRCDATAIN[23:16] 31:24 CRCDATAIN[31:24] 0x08 CRCCHKSUM 7:0 CRCCHKSUM[7:0] 15:8 CRCCHKSUM[15:8] 23:16 CRCCHKSUM[23:16] 31:24 CRCCHKSUM[31:24] 0x0C CRCSTATUS 7:0 CRCZERO CRCBUSY 0x0D DBGCTRL 7:0 DBGRUN 0x0E QOSCTRL 7:0 DQOS[1:0] FQOS[1:0] WRBQOS[1:0] 0x0F Reserved 0x10 SWTRIGCTRL 7:0 SWTRIGn[7:0] 15:8 SWTRIGn[11:8] 23:16 31:24 0x14 PRICTRL0 7:0 RRLVLEN0 LVLPRI0[3:0] 15:8 RRLVLEN1 LVLPRI1[3:0] 23:16 RRLVLEN2 LVLPRI2[3:0] 31:24 RRLVLEN3 LVLPRI3[3:0] 0x18 ... 0x1F Reserved 0x20 INTPEND 7:0 ID[3:0] 15:8 PEND BUSY FERR SUSP TCMPL TERR 0x22 ... 0x23 Reserved 0x24 INTSTATUS 7:0 CHINTn[7:0] 15:8 CHINTn[11:8] 23:16 31:24 0x28 BUSYCH 7:0 BUSYCHn[7:0] 15:8 BUSYCHn[11:8] 23:16 31:24 0x2C PENDCH 7:0 PENDCH7 PENDCH6 PENDCH5 PENDCH4 PENDCH3 PENDCH2 PENDCH1 PENDCH0 15:8 PENDCH11 PENDCH10 PENDCH9 PENDCH8 23:16 31:24 0x30 ACTIVE 7:0 LVLEXx LVLEXx LVLEXx LVLEXx 15:8 ABUSY ID[4:0] 23:16 BTCNT[7:0] 31:24 BTCNT[15:8] 0x34 BASEADDR 7:0 BASEADDR[7:0] 15:8 BASEADDR[15:8] 23:16 BASEADDR[23:16] 31:24 BASEADDR[31:24] 0x38 WRBADDR 7:0 WRBADDR[7:0] 15:8 WRBADDR[15:8] 23:16 WRBADDR[23:16] 31:24 WRBADDR[31:24] SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 289

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x3C ... 0x3E Reserved 0x3F CHID 7:0 ID[3:0] 0x40 CHCTRLA 7:0 ENABLE SWRST 0x41 ... 0x43 Reserved 0x44 CHCTRLB 7:0 LVL[1:0] EVOE EVIE EVACT[2:0] 15:8 TRIGSRC[5:0] 23:16 TRIGACT[1:0] 31:24 CMD[1:0] 0x48 ... 0x4B Reserved 0x4C CHINTENCLR 7:0 SUSP TCMPL TERR 0x4D CHINTENSET 7:0 SUSP TCMPL TERR 0x4E CHINTFLAG 7:0 SUSP TCMPL TERR 0x4F CHSTATUS 7:0 FERR BUSY PEND

20.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write- protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 20.5.8 Register Access Protection. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 290

20.8.1 Control

Name: CTRL Offset: 0x00 Reset: 0x00X0 Property: PAC Write-Protection, Enable-Protected Bit 15 14 13 12 11 10 9 8 LVLENx3 LVLENx2 LVLENx1 LVLENx0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCENABLE DMAENABLE SWRST Access R/W R/W R/W Reset 0 0 0 Bits 8, 9, 10, 11 – LVLENx Priority Level x Enable When this bit is set, all requests with the corresponding level will be fed into the arbiter block. When cleared, all requests with the corresponding level will be ignored. For details on arbitration schemes, refer to the Arbitration section. These bits are not enable-protected. Value Description 0 Transfer requests for Priority level x will not be handled. 1 Transfer requests for Priority level x will be handled. Bit 2 – CRCENABLE CRC Enable Writing a '0' to this bit will disable the CRC calculation when the CRC Status Busy flag is cleared (CRCSTATUS. CRCBUSY). The bit is zero when the CRC is disabled. Writing a '1' to this bit will enable the CRC calculation. Value Description 0 The CRC calculation is disabled. 1 The CRC calculation is enabled. Bit 1 – DMAENABLE DMA Enable Setting this bit will enable the DMA module. Writing a '0' to this bit will disable the DMA module. When writing a '0' during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst transfer is completed. This bit is not enable-protected. Value Description 0 The peripheral is disabled. 1 The peripheral is enabled. Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit when both the DMAC and the CRC module are disabled (DMAENABLE and CRCENABLE are '0') resets all registers in the DMAC (except DBGCTRL) to their initial state. If either the DMAC or CRC module is enabled, the Reset request will be ignored and the DMAC will return an access error. Value Description 0 There is no Reset operation ongoing. 1 A Reset operation is ongoing. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 291

20.8.2 CRC Control

Name: CRCCTRL Offset: 0x02 Reset: 0x0000 Property: PAC Write-Protection, Enable-Protected Bit 15 14 13 12 11 10 9 8 CRCSRC[5:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCPOLY[1:0] CRCBEATSIZE[1:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 13:8 – CRCSRC[5:0] CRC Input Source These bits select the input source for generating the CRC, as shown in the table below. The selected source is locked until either the CRC generation is completed or the CRC module is disabled. This means the CRCSRC cannot be modified when the CRC operation is ongoing. The lock is signaled by the CRCBUSY Status bit. CRC generation complete is generated and signaled from the selected source when used with the DMA channel. Value Name Description 0x00 NOACT No action 0x01 IO I/O interface 0x02-0x1 F - Reserved 0x20 CHN DMA channel 0 0x21 CHN DMA channel 1 0x22 CHN DMA channel 2 0x23 CHN DMA channel 3 0x24 CHN DMA channel 4 0x25 CHN DMA channel 5 0x26 CHN DMA channel 6 0x27 CHN DMA channel 7 0x28 CHN DMA channel 8 0x29 CHN DMA channel 9 0x2A CHN DMA channel 10 0x2B CHN DMA channel 11 Bits 3:2 – CRCPOLY[1:0] CRC Polynomial Type These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface, as shown in the table below. Value Name Description 0x0 CRC16 CRC-16 (CRC-CCITT) 0x1 CRC32 CRC32 (IEEE 802.3) 0x2-0x3 Reserved Bits 1:0 – CRCBEATSIZE[1:0] CRC Beat Size These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface. Value Name Description 0x0 BYTE 8-bit bus transfer 0x1 HWORD 16-bit bus transfer 0x2 WORD 32-bit bus transfer 0x3 Reserved SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 292

20.8.3 CRC Data Input

Name: CRCDATAIN Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 CRCDATAIN[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CRCDATAIN[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CRCDATAIN[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCDATAIN[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – CRCDATAIN[31:0] CRC Data Input These bits store the data for which the CRC checksum is computed. A new CRC Checksum is ready (CRCBEAT+ 1) clock cycles after the CRCDATAIN register is written. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 293

20.8.4 CRC Checksum

Name: CRCCHKSUM Offset: 0x08 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected The CRCCHKSUM represents the 16- or 32-bit checksum value and the generated CRC. The register is reset to zero by default, but it is possible to reset all bits to one by writing the CRCCHKSUM register directly. It is possible to write this register only when the CRC module is disabled. If CRC-32 is selected and the CRC Status Busy flag is cleared (i.e., CRC generation is completed or aborted), the bit reversed (bit 31 is swapped with bit 0, bit 30 with bit 1, etc.) and complemented result will be read from CRCCHKSUM. If CRC-16 is selected or the CRC Status Busy flag is set (i.e., CRC generation is ongoing), CRCCHKSUM will contain the actual content. Bit 31 30 29 28 27 26 25 24 CRCCHKSUM[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CRCCHKSUM[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CRCCHKSUM[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCCHKSUM[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – CRCCHKSUM[31:0] CRC Checksum These bits store the generated CRC result. The 16 MSB bits are always read zero when CRC-16 is enabled. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 294

20.8.5 CRC Status

Name: CRCSTATUS Offset: 0x0C Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CRCZERO CRCBUSY Access R R/W Reset 0 0 Bit 1 – CRCZERO CRC Zero This bit is cleared when a new CRC source is selected. This bit is set when the CRC generation is complete and the CRC Checksum is zero. When running CRC-32 and appending the checksum at the end of the packet (as little endian), the final checksum should be 0x2144df1c, and not zero. However, if the checksum is complemented before it is appended (as little endian) to the data, the final result in the checksum register will be zero. See the description of CRCCHKSUM to read out different versions of the checksum. Bit 0 – CRCBUSY CRC Module Busy This flag is cleared by writing a one to it when used with I/O interface. When used with a DMA channel, the bit is set when the corresponding DMA channel is enabled, and cleared when the corresponding DMA channel is disabled. This register bit cannot be cleared by the application when the CRC is used with a DMA channel. This bit is set when a source configuration is selected and as long as the source is using the CRC module. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 295

20.8.6 Debug Control

Name: DBGCTRL Offset: 0x0D Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Debug Run This bit is not reset by a software reset. This bit controls the functionality when the CPU is halted by an external debugger. Value Description 0 The DMAC is halted when the CPU is halted by an external debugger. 1 The DMAC continues normal operation when the CPU is halted by an external debugger. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 296

20.8.7 Quality of Service Control

Name: QOSCTRL Offset: 0x0E Reset: 0x15 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DQOS[1:0] FQOS[1:0] WRBQOS[1:0] Access R/W R/W R/W R/W R/W R/W Reset 1 0 1 0 1 0 Bits 5:4 – DQOS[1:0] Data Transfer Quality of Service These bits define the memory priority access during the data transfer operation. DQOS[1:0] Name Description 0x0 DISABLE Background (no sensitive operation) 0x1 LOW Sensitive Bandwidth 0x2 MEDIUM Sensitive Latency 0x3 HIGH Critical Latency Bits 3:2 – FQOS[1:0] Fetch Quality of Service These bits define the memory priority access during the fetch operation. FQOS[1:0] Name Description 0x0 DISABLE Background (no sensitive operation) 0x1 LOW Sensitive Bandwidth 0x2 MEDIUM Sensitive Latency 0x3 HIGH Critical Latency Bits 1:0 – WRBQOS[1:0] Write-Back Quality of Service These bits define the memory priority access during the write-back operation. WRBQOS[1:0] Name Description 0x0 DISABLE Background (no sensitive operation) 0x1 LOW Sensitive Bandwidth 0x2 MEDIUM Sensitive Latency 0x3 HIGH Critical Latency Related Links DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 297

20.8.8 Software Trigger Control

Name: SWTRIGCTRL Offset: 0x10 Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 SWTRIGn[11:8] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SWTRIGn[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 11:0 – SWTRIGn[11:0] Channel n Software Trigger [n = 11..0] This bit is cleared when the Channel Pending bit in the Channel Status register (CHSTATUS.PEND) for the corresponding channel is either set, or by writing a '1' to it. This bit is set if CHSTATUS.PEND is already '1' when writing a '1' to that bit. Writing a '0' to this bit will clear the bit. Writing a '1' to this bit will generate a DMA software trigger on channel x, if CHSTATUS.PEND=0 for channel x. CHSTATUS.PEND will be set and SWTRIGn will remain cleared. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 298

20.8.9 Priority Control 0

Name: PRICTRL0 Offset: 0x14 Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 RRLVLEN3 LVLPRI3[3:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 RRLVLEN2 LVLPRI2[3:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 RRLVLEN1 LVLPRI1[3:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RRLVLEN0 LVLPRI0[3:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 31 – RRLVLEN3 Level 3 Round-Robin Arbitration Enable This bit controls which arbitration scheme is selected for DMA channels with priority level 3. For details on arbitration schemes, refer to 20.6.2.4 Arbitration. Value Description 0 Static arbitration scheme for channels with level 3 priority. 1 Round-robin arbitration scheme for channels with level 3 priority. Bits 27:24 – LVLPRI3[3:0] Level 3 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN3=1) for priority level 3, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 3. When static arbitration is enabled (PRICTRL0.RRLVLEN3=0) for priority level 3, and the value of this bit group is non-zero, it will not affect the static priority scheme. This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN3 written to '0'). Bit 23 – RRLVLEN2 Level 2 Round-Robin Arbitration Enable This bit controls which arbitration scheme is selected for DMA channels with priority level 2. For details on arbitration schemes, refer to 20.6.2.4 Arbitration. Value Description 0 Static arbitration scheme for channels with level 2 priority. 1 Round-robin arbitration scheme for channels with level 2 priority. Bits 19:16 – LVLPRI2[3:0] Level 2 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN2=1) for priority level 2, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 2. When static arbitration is enabled (PRICTRL0.RRLVLEN2=0) for priority level 2, and the value of this bit group is non-zero, it will not affect the static priority scheme. This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN2 written to '0'). SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 299

Bit 15 – RRLVLEN1 Level 1 Round-Robin Scheduling Enable For details on arbitration schemes, refer to 20.6.2.4 Arbitration. Value Description 0 Static arbitration scheme for channels with level 1 priority. 1 Round-robin arbitration scheme for channels with level 1 priority. Bits 11:8 – LVLPRI1[3:0] Level 1 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN1=1) for priority level 1, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 1. When static arbitration is enabled (PRICTRL0.RRLVLEN1=0) for priority level 1, and the value of this bit group is non-zero, it will not affect the static priority scheme. This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN1 written to '0'). Bit 7 – RRLVLEN0 Level 0 Round-Robin Scheduling Enable For details on arbitration schemes, refer to 20.6.2.4 Arbitration. Value Description 0 Static arbitration scheme for channels with level 0 priority. 1 Round-robin arbitration scheme for channels with level 0 priority. Bits 3:0 – LVLPRI0[3:0] Level 0 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN0=1) for priority level 0, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 0. When static arbitration is enabled (PRICTRL0.RRLVLEN0=0) for priority level 0, and the value of this bit group is non-zero, it will not affect the static priority scheme. This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN0 written to '0'). SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 300

20.8.10 Interrupt Pending

Name: INTPEND Offset: 0x20 Reset: 0x0000 Property: - This register allows the user to identify the lowest DMA channel with pending interrupt. Bit 15 14 13 12 11 10 9 8 PEND BUSY FERR SUSP TCMPL TERR Access R R R R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ID[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 – PEND Pending This bit will read '1' when the channel selected by Channel ID field (ID) is pending. Bit 14 – BUSY Busy This bit will read '1' when the channel selected by Channel ID field (ID) is busy. Bit 13 – FERR Fetch Error This bit will read '1' when the channel selected by Channel ID field (ID) fetched an invalid descriptor. Bit 10 – SUSP Channel Suspend This bit will read '1' when the channel selected by Channel ID field (ID) has pending Suspend interrupt. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel ID (ID) Suspend interrupt flag. Bit 9 – TCMPL Transfer Complete This bit will read '1' when the channel selected by Channel ID field (ID) has pending Transfer Complete interrupt. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel ID (ID) Transfer Complete interrupt flag. Bit 8 – TERR Transfer Error This bit is read one when the channel selected by Channel ID field (ID) has pending Transfer Error interrupt. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel ID (ID) Transfer Error interrupt flag. Bits 3:0 – ID[3:0] Channel ID These bits store the lowest channel number with pending interrupts. The number is valid if Suspend (SUSP), Transfer Complete (TCMPL) or Transfer Error (TERR) bits are set. The Channel ID field is refreshed when a new channel (with channel number less than the current one) with pending interrupts is detected, or when the application clears the corresponding channel interrupt sources. When no pending channels interrupts are available, these bits will always return zero value when read. When the bits are written, indirect access to the corresponding Channel Interrupt Flag register is enabled. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 301

20.8.11 Interrupt Status

Name: INTSTATUS Offset: 0x24 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 CHINTn[11:8] Access R R R R Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CHINTn[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 11:0 – CHINTn[11:0] Channel n Pending Interrupt [n=11..0] This bit is set when Channel n has a pending interrupt/the interrupt request is received. This bit is cleared when the corresponding Channel n interrupts are disabled or the interrupts sources are cleared. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 302

20.8.12 Busy Channels

Name: BUSYCH Offset: 0x28 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 BUSYCHn[11:8] Access R R R R Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BUSYCHn[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 11:0 – BUSYCHn[11:0] Busy Channel n [x=11..0] This bit is cleared when the channel trigger action for DMA channel n is complete, when a bus error for DMA channel n is detected, or when DMA channel n is disabled. This bit is set when DMA channel n starts a DMA transfer. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 303

20.8.13 Pending Channels

Name: PENDCH Offset: 0x2C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 PENDCH11 PENDCH10 PENDCH9 PENDCH8 Access R R R R Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PENDCH7 PENDCH6 PENDCH5 PENDCH4 PENDCH3 PENDCH2 PENDCH1 PENDCH0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – PENDCH Pending Channel n [n=11..0] This bit is cleared when trigger execution defined by channel trigger action settings for DMA channel n is started, when a bus error for DMA channel n is detected or when DMA channel n is disabled. For details on trigger action settings, refer to CHCTRLB.TRIGACT. This bit is set when a transfer is pending on DMA channel n. Related Links

20.8.19 CHCTRLB

20.8.14 Active Channel and Levels

Name: ACTIVE Offset: 0x30 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 BTCNT[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 BTCNT[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ABUSY ID[4:0] Access R R R R R R Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LVLEXx LVLEXx LVLEXx LVLEXx Access R R R R Reset 0 0 0 0 Bits 31:16 – BTCNT[15:0] Active Channel Block Transfer Count These bits hold the 16-bit block transfer count of the ongoing transfer. This value is stored in the active channel and written back in the corresponding Write-Back channel memory location when the arbiter grants a new channel access. The value is valid only when the active channel active busy flag (ABUSY) is set. Bit 15 – ABUSY Active Channel Busy This bit is cleared when the active transfer count is written back in the write-back memory section. This bit is set when the next descriptor transfer count is read from the write-back memory section. Bits 12:8 – ID[4:0] Active Channel ID These bits hold the channel index currently stored in the active channel registers. The value is updated each time the arbiter grants a new channel transfer access request. Bits 3,2,1,0 – LVLEXx Level x Channel Trigger Request Executing [x=3..0] This bit is set when a level-x channel trigger request is executing or pending. This bit is cleared when no request is pending or being executed. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 305

20.8.15 Descriptor Memory Section Base Address

Name: BASEADDR Offset: 0x34 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 BASEADDR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 BASEADDR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 BASEADDR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BASEADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – BASEADDR[31:0] Descriptor Memory Base Address These bits store the Descriptor memory section base address. The value must be 64-bit aligned. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 306

20.8.16 Write-Back Memory Section Base Address

Name: WRBADDR Offset: 0x38 Reset: 0x00000000 Property: PAC Write Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 WRBADDR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 WRBADDR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 WRBADDR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WRBADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – WRBADDR[31:0] Write-Back Memory Base Address These bits store the Write-Back memory base address. The value must be 64-bit aligned. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 307

20.8.17 Channel ID

Name: CHID Offset: 0x3F Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 ID[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 3:0 – ID[3:0] Channel ID These bits define the channel number that will be affected by the channel registers (CH*). Before reading or writing a channel register, the channel ID bit group must be written first. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 308

20.8.18 Channel Control A

Name: CHCTRLA Offset: 0x40 Reset: 0x00 Property: PAC Write-Protection, Enable-Protected This register affects the DMA channel that is selected in the Channel ID register (CHID.ID). Bit 7 6 5 4 3 2 1 0 ENABLE SWRST Access R R R R R R/W R/W Reset 0 0 0 0 0 0 0 Bit 1 – ENABLE Channel Enable Writing a '0' to this bit during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst transfer is completed. Writing a '1' to this bit will enable the DMA channel. This bit is not enable-protected. Value Description 0 DMA channel is disabled. 1 DMA channel is enabled. Bit 0 – SWRST Channel Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets the channel registers to their initial state. The bit can be set when the channel is disabled (ENABLE=0). Writing a '1' to this bit will be ignored as long as ENABLE=1. This bit is automatically cleared when the reset is completed. Value Description 0 There is no reset operation ongoing. 1 The reset operation is ongoing. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 309

20.8.19 Channel Control B

Name: CHCTRLB Offset: 0x44 Reset: 0x00000000 Property: PAC Write Protection, Enable-Protected This register affects the DMA channel that is selected in the Channel ID register (CHID.ID). Bit 31 30 29 28 27 26 25 24 CMD[1:0] Access R/W R/W Reset 0 0 Bit 23 22 21 20 19 18 17 16 TRIGACT[1:0] Access R/W R/W Reset 0 0 Bit 15 14 13 12 11 10 9 8 TRIGSRC[5:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LVL[1:0] EVOE EVIE EVACT[2:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bits 25:24 – CMD[1:0] Software Command Next Suspend Skip. These bits are not enable-protected. CMD[1:0] Name Description 0x0 NOACT No action 0x1 SUSPEND Channel suspend operation 0x2 RESUME Channel resume operation 0x3 - Reserved Bits 23:22 – TRIGACT[1:0] Trigger Action These bits define the trigger action used for a transfer. TRIGACT[1:0] Name Description 0x0 BLOCK One trigger required for each block transfer 0x1 - Reserved 0x2 BEAT One trigger required for each beat transfer 0x3 TRANSACTION One trigger required for each transaction Bits 13:8 – TRIGSRC[5:0] Trigger Source These bits define the peripheral trigger which is source of the transfer. For details on trigger selection and trigger modes, refer to Transfer Triggers and Actions and CHCTRLB.TRIGACT. Value Name Description 0x00 DISABLE Only software/event triggers 0x01 SERCOM0 RX SERCOM0 RX Trigger 0x02 SERCOM0 TX SERCOM0 TX Trigger 0x03 SERCOM1 RX SERCOM1 RX Trigger SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 310

0x04 SERCOM1 TX SERCOM1 TX Trigger 0x05 SERCOM2 RX SERCOM2 RX Trigger 0x06 SERCOM2 TX SERCOM2 TX Trigger 0x07 SERCOM3 RX SERCOM3 RX Trigger 0x08 SERCOM3 TX SERCOM3 TX Trigger 0x09 SERCOM4 RX SERCOM4 RX Trigger 0x0A SERCOM4 TX SERCOM4 TX Trigger 0x0B SERCOM5 RX SERCOM5 RX Trigger 0x0C SERCOM5 TX SERCOM5 TX Trigger 0x0D TCC0 OVF TCC0 Overflow Trigger 0x0E TCC0 MC0 TCC0 Match/Compare 0 Trigger 0x0F TCC0 MC1 TCC0 Match/Compare 1 Trigger 0x10 TCC0 MC2 TCC0 Match/Compare 2 Trigger 0x11 TCC0 MC3 TCC0 Match/Compare 3 Trigger 0x12 TCC1 OVF TCC1 Overflow Trigger 0x13 TCC1 MC0 TCC1 Match/Compare 0 Trigger 0x14 TCC1 MC1 TCC1 Match/Compare 1 Trigger 0x15 TCC2 OVF TCC2 Overflow Trigger 0x16 TCC2 MC0 TCC2 Match/Compare 0 Trigger 0x17 TCC2 MC1 TCC2 Match/Compare 1 Trigger 0x18 TC3 OVF TC3 Overflow Trigger 0x19 TC3 MC0 TC3 Match/Compare 0 Trigger 0x1A TC3 MC1 TC3 Match/Compare 1 Trigger 0x1B TC4 OVF TC4 Overflow Trigger 0x1C TC4 MC0 TC4 Match/Compare 0 Trigger 0x1D TC4 MC1 TC4 Match/Compare 1 Trigger 0x1E TC5 OVF TC5 Overflow Trigger 0x1F TC5 MC0 TC5 Match/Compare 0 Trigger 0x20 TC5 MC1 TC5 Match/Compare 1 Trigger 0x21 TC6 OVF TC6 Overflow Trigger 0x22 TC6 MC0 TC6 Match/Compare 0 Trigger 0x23 TC6 MC1 TC6 Match/Compare 1 Trigger 0x24 TC7 OVF TC7 Overflow Trigger 0x25 TC7 MC0 TC7 Match/Compare 0 Trigger 0x26 TC7 MC1 TC7 Match/Compare 1 Trigger 0x27 ADC RESRDY ADC Result Ready Trigger 0x28 DAC EMPTY DAC Empty Trigger 0x29 I2S RX 0 I2S RX 0 Trigger 0x2A I2S RX 1 I2S RX 1 Trigger 0x2B I2S TX 0 I2S TX 0 Trigger 0x2C I2S TX 0 I2S TX 1 Trigger 0x2D OVF TCC3 Overflow Trigger 0x2E TCC3 MC0 TCC3 Match/Compare 0 Trigger 0x2F TCC3 MC1 TCC3 Match/Compare 1 Trigger 0x30 TCC3 MC2 Match/Compare 2 Trigger 0x31 TCC3 MC3 Match/Compare 3 Trigger Bits 6:5 – LVL[1:0] Channel Arbitration Level These bits define the arbitration level used for the DMA channel, where a high level has priority over a low level. For further details on arbitration schemes, refer to 20.6.2.4 Arbitration. These bits are not enable-protected. TRIGACT[1:0] Name Description 0x0 LVL0 Channel Priority Level 0 0x1 LVL1 Channel Priority Level 1 SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 311

TRIGACT[1:0] Name Description 0x2 LVL2 Channel Priority Level 2 0x3 LVL3 Channel Priority Level 3 Bit 4 – EVOE Channel Event Output Enable This bit indicates if the Channel event generation is enabled. The event will be generated for every condition defined in the descriptor Event Output Selection (BTCTRL.EVOSEL). This bit is available only for the Least Significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details. Value Description

0 Channel event generation is disabled

1 Channel event generation is enabled

Bit 3 – EVIE Channel Event Input Enable This bit is available only for the Least Significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details. Value Description

0 Channel event action will not be executed on any incoming event

1 Channel event action will be executed on any incoming event

Bits 2:0 – EVACT[2:0] Event Input Action These bits define the event input action, as shown below. The action is executed only if the corresponding EVIE bit in CHCTRLB register of the channel is set. These bits are available only for the Least Significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details. EVACT[2:0] Name Description 0x0 NOACT No action 0x1 TRIG Normal Transfer and Conditional Transfer on Strobe trigger 0x2 CTRIG Conditional transfer trigger 0x3 CBLOCK Conditional block transfer 0x4 SUSPEND Channel suspend operation 0x5 RESUME Channel resume operation 0x6 SSKIP Skip next block suspend action 0x7 - Reserved Related Links

24.8.2 CHANNEL

20.8.20 Channel Interrupt Enable Clear

Name: CHINTENCLR Offset: 0x4C Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Channel Interrupt Enable Set (CHINTENSET) register. This register affects the DMA channel that is selected in the Channel ID register (CHID.ID). Bit 7 6 5 4 3 2 1 0 SUSP TCMPL TERR Access R/W R/W R/W Reset 0 0 0 Bit 2 – SUSP Channel Suspend Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel Suspend Interrupt Enable bit, which disables the Channel Suspend interrupt. Value Description 0 The Channel Suspend interrupt is disabled. 1 The Channel Suspend interrupt is enabled. Bit 1 – TCMPL Channel Transfer Complete Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel Transfer Complete Interrupt Enable bit, which disables the Channel Transfer Complete interrupt. Value Description 0 The Channel Transfer Complete interrupt is disabled. When block action is set to none, the TCMPL flag will not be set when a block transfer is completed. 1 The Channel Transfer Complete interrupt is enabled. Bit 0 – TERR Channel Transfer Error Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel Transfer Error Interrupt Enable bit, which disables the Channel Transfer Error interrupt. Value Description 0 The Channel Transfer Error interrupt is disabled. 1 The Channel Transfer Error interrupt is enabled. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 313

20.8.21 Channel Interrupt Enable Set

Name: CHINTENSET Offset: 0x4D Reset: 0x00 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Channel Interrupt Enable Clear (CHINTENCLR) register. This register affects the DMA channel that is selected in the Channel ID register (CHID.ID). Bit 7 6 5 4 3 2 1 0 SUSP TCMPL TERR Access R/W R/W R/W Reset 0 0 0 Bit 2 – SUSP Channel Suspend Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Channel Suspend Interrupt Enable bit, which enables the Channel Suspend interrupt. Value Description 0 The Channel Suspend interrupt is disabled. 1 The Channel Suspend interrupt is enabled. Bit 1 – TCMPL Channel Transfer Complete Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Channel Transfer Complete Interrupt Enable bit, which enables the Channel Transfer Complete interrupt. Value Description 0 The Channel Transfer Complete interrupt is disabled. 1 The Channel Transfer Complete interrupt is enabled. Bit 0 – TERR Channel Transfer Error Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Channel Transfer Error Interrupt Enable bit, which enables the Channel Transfer Error interrupt. Value Description 0 The Channel Transfer Error interrupt is disabled. 1 The Channel Transfer Error interrupt is enabled. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 314

20.8.22 Channel Interrupt Flag Status and Clear

Name: CHINTFLAG Offset: 0x4E Reset: 0x00 Property: - This register affects the DMA channel that is selected in the Channel ID register (CHID.ID). Bit 7 6 5 4 3 2 1 0 SUSP TCMPL TERR Access R/W R/W R/W Reset 0 0 0 Bit 2 – SUSP Channel Suspend This flag is cleared by writing a '1' to it. This flag is set when a block transfer with suspend block action is completed, when a software suspend command is executed, when a suspend event is received or when an invalid descriptor is fetched by the DMA. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel Suspend interrupt flag for the corresponding channel. For details on available software commands, refer to CHCTRLB.CMD. For details on available event input actions, refer to CHCTRLB.EVACT. For details on available block actions, refer to BTCTRL.BLOCKACT. Bit 1 – TCMPL Channel Transfer Complete This flag is cleared by writing a '1' to it. This flag is set when a block transfer is completed and the corresponding interrupt block action is enabled. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Transfer Complete interrupt flag for the corresponding channel. Bit 0 – TERR Channel Transfer Error This flag is cleared by writing a '1' to it. This flag is set when a bus error is detected during a beat transfer or when the DMAC fetches an invalid descriptor. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Transfer Error interrupt flag for the corresponding channel. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 315

20.8.23 Channel Status

Name: CHSTATUS Offset: 0x4F Reset: 0x00 Property: - This register affects the DMA channel that is selected in the Channel ID register (CHID.ID). Bit 7 6 5 4 3 2 1 0 FERR BUSY PEND Access R R R Reset 0 0 0 Bit 2 – FERR Channel Fetch Error This bit is cleared when a software resume command is executed. This bit is set when an invalid descriptor is fetched. Bit 1 – BUSY Channel Busy This bit is cleared when the channel trigger action is completed, when a bus error is detected or when the channel is disabled. This bit is set when the DMA channel starts a DMA transfer. Bit 0 – PEND Channel Pending This bit is cleared when the channel trigger action is started, when a bus error is detected or when the channel is disabled. For details on trigger action settings, refer to CHCTRLB.TRIGACT. This bit is set when a transfer is pending on the DMA channel, as soon as the transfer request is received. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 316

20.9 Register Summary - SRAM

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 BTCTRL 7:0 BLOCKACT[1:0] EVOSEL[1:0] VALID 15:8 STEPSIZE[2:0] STEPSEL DSTINC SRCINC BEATSIZE[1:0] 0x02 BTCNT 7:0 BTCNT[7:0] 15:8 BTCNT[15:8] 0x04 SRCADDR 7:0 SRCADDR[7:0] 15:8 SRCADDR[15:8] 23:16 SRCADDR[23:16] 31:24 SRCADDR[31:24] 0x08 DSTADDR 7:0 DSTADDR[7:0] 15:8 DSTADDR[15:8] 23:16 DSTADDR[23:16] 31:24 DSTADDR[31:24] 0x0C DESCADDR 7:0 DESCADDR[7:0] 15:8 DESCADDR[15:8] 23:16 DESCADDR[23:16] 31:24 DESCADDR[31:24]

20.10 Register Description - SRAM

20.10.1 Block Transfer Control

Name: BTCTRL Offset: 0x00 Property: - The BTCTRL register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 15 14 13 12 11 10 9 8 STEPSIZE[2:0] STEPSEL DSTINC SRCINC BEATSIZE[1:0] Access Reset Bit 7 6 5 4 3 2 1 0 BLOCKACT[1:0] EVOSEL[1:0] VALID Access Reset Bits 15:13 – STEPSIZE[2:0] Address Increment Step Size These bits select the address increment step size. The setting apply to source or destination address, depending on STEPSEL setting. Value Name Description 0x0 X1 Next ADDR = ADDR + (Beat size in byte) * 1 0x1 X2 Next ADDR = ADDR + (Beat size in byte) * 2 0x2 X4 Next ADDR = ADDR + (Beat size in byte) * 4 0x3 X8 Next ADDR = ADDR + (Beat size in byte) * 8 0x4 X16 Next ADDR = ADDR + (Beat size in byte) * 16 0x5 X32 Next ADDR = ADDR + (Beat size in byte) * 32 0x6 X64 Next ADDR = ADDR + (Beat size in byte) * 64 0x7 X128 Next ADDR = ADDR + (Beat size in byte) * 128 Bit 12 – STEPSEL Step Selection This bit selects if source or destination addresses are using the step size settings. Value Name Description 0x0 DST Step size settings apply to the destination address 0x1 SRC Step size settings apply to the source address Bit 11 – DSTINC Destination Address Increment Enable Writing a '0' to this bit will disable the destination address incrementation. The address will be kept fixed during the data transfer. Writing a '1' to this bit will enable the destination address incrementation. By default, the destination address is incremented by 1. If the STEPSEL bit is cleared, flexible step-size settings are available in the STEPSIZE register. Value Description 0 The Destination Address Increment is disabled. 1 The Destination Address Increment is enabled. Bit 10 – SRCINC Source Address Increment Enable Writing a '0' to this bit will disable the source address incrementation. The address will be kept fixed during the data transfer. Writing a '1' to this bit will enable the source address incrementation. By default, the source address is incremented by 1. If the STEPSEL bit is set, flexible step-size settings are available in the STEPSIZE register. Value Description 0 The Source Address Increment is disabled. 1 The Source Address Increment is enabled. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 318

Bits 9:8 – BEATSIZE[1:0] Beat Size These bits define the size of one beat. A beat is the size of one data transfer bus access, and the setting apply to both read and write accesses. Value Name Description 0x0 BYTE 8-bit bus transfer 0x1 HWORD 16-bit bus transfer 0x2 WORD 32-bit bus transfer other Reserved Bits 4:3 – BLOCKACT[1:0] Block Action These bits define what actions the DMAC should take after a block transfer has completed. BLOCKACT[1:0] Name Description 0x0 NOACT Channel will be disabled if it is the last block transfer in the transaction 0x1 INT Channel will be disabled if it is the last block transfer in the transaction and block interrupt 0x2 SUSPEND Channel suspend operation is completed 0x3 BOTH Both channel suspend operation and block interrupt Bits 2:1 – EVOSEL[1:0] Event Output Selection These bits define the event output selection. EVOSEL[1:0] Name Description 0x0 DISABLE Event generation disabled 0x1 BLOCK Event strobe when block transfer complete 0x2 Reserved 0x3 BEAT Event strobe when beat transfer complete Bit 0 – VALID Descriptor Valid Writing a '0' to this bit in the Descriptor or Write-Back memory will suspend the DMA channel operation when fetching the corresponding descriptor. The bit is automatically cleared in the Write-Back memory section when channel is aborted, when an error is detected during the block transfer, or when the block transfer is completed. Value Description 0 The descriptor is not valid. 1 The descriptor is valid. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 319

20.10.2 Block Transfer Count

Name: BTCNT Offset: 0x02 Property: - The BTCNT register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 15 14 13 12 11 10 9 8 BTCNT[15:8] Access Reset Bit 7 6 5 4 3 2 1 0 BTCNT[7:0] Access Reset Bits 15:0 – BTCNT[15:0] Block Transfer Count This bit group holds the 16-bit block transfer count. During a transfer, the internal counter value is decremented by one after each beat transfer. The internal counter is written to the corresponding write-back memory section for the DMA channel when the DMA channel loses priority, is suspended or gets disabled. The DMA channel can be disabled by a complete transfer, a transfer error or by software. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 320

20.10.3 Block Transfer Source Address

Name: SRCADDR Offset: 0x04 Property: - The SRCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 31 30 29 28 27 26 25 24 SRCADDR[31:24] Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SRCADDR[23:16] Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SRCADDR[15:8] Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SRCADDR[7:0] Access Reset 0 0 0 0 0 0 0 0 Bits 31:0 – SRCADDR[31:0] Transfer Source Address This bit field holds the block transfer source address. When source address incrementation is disabled (BTCTRL.SRCINC=0), SRCADDR corresponds to the last beat transfer address in the block transfer. When source address incrementation is enabled (BTCTRL.SRCINC=1), SRCADDR is calculated as follows: If BTCTRL.STEPSEL = 1: SRCADDR = SRCADDR ST A RT + BTC NT ⋅ B E A TSI ZE + 1 ⋅ 2 STEPSIZE If BTCTRL.STEPSEL= 0: SRCADDR = SRCADDR ST A RT + BTC NT ⋅ BE A TSI ZE + 1

SRCADDR START is the source address of the first beat transfer in the block transfer
BTCNT is the initial number of beats remaining in the block transfer
BEATSIZE is the configured number of bytes in a beat
STEPSIZE is the configured number of beats for each incrementation SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 321

20.10.4 Block Transfer Destination Address

Name: DSTADDR Offset: 0x08 Property: - The DSTADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 31 30 29 28 27 26 25 24 DSTADDR[31:24] Access Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DSTADDR[23:16] Access Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DSTADDR[15:8] Access Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DSTADDR[7:0] Access Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DSTADDR[31:0] Transfer Destination Address This bit field holds the block transfer destination address. When destination address incrementation is disabled (BTCTRL.DSTINC = 0), DSTADDR corresponds to the last beat transfer address in the block transfer. When destination address incrementation is enabled (BTCTRL.DSTINC = 1), DSTADDR is calculated as follows: If BTCTRL.STEPSEL = 1: DS T A DDR = D ST A DDR S T AR T + B TC NT • BE AT SI ZE + 1 If BTCTRL.STEPSEL = 0: DS T A DDR = D ST A DDR S T AR T + B TC NT • BE A TSI ZE + 1 • 2 STE PSI ZE

DSTADDR START is the destination address of the first beat transfer in the block transfer
BTCNT is the initial number of beats remaining in the block transfer
BEATSIZE is the configured number of bytes in a beat
STEPSIZE is the configured number of beats for each incrementation SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 322

20.10.5 Next Descriptor Address

Name: DESCADDR Offset: 0x0C Property: - The DESCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 31 30 29 28 27 26 25 24 DESCADDR[31:24] Access Reset Bit 23 22 21 20 19 18 17 16 DESCADDR[23:16] Access Reset Bit 15 14 13 12 11 10 9 8 DESCADDR[15:8] Access Reset Bit 7 6 5 4 3 2 1 0 DESCADDR[7:0] Access Reset Bits 31:0 – DESCADDR[31:0] Next Descriptor Address This bit group holds the SRAM address of the next descriptor. The value must be 64-bit aligned. If the value of this SRAM register is 0x00000000, the transaction will be terminated when the DMAC tries to load the next transfer descriptor. SAM D21/DA1 Family DMAC – Direct Memory Access Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 323

EIC – External Interrupt Controller

21.1 Overview

The External Interrupt Controller (EIC) allows external pins to be configured as interrupt lines. Each interrupt line can be individually masked and can generate an interrupt on rising, falling, or both edges, or on high or low levels. Each external pin has a configurable filter to remove spikes. Each external pin can also be configured to be asynchronous in order to wake up the device from sleep modes where all clocks have been disabled. External pins can also generate an event. A separate non-maskable interrupt (NMI) is also supported. It has properties similar to the other external interrupts, but is connected to the NMI request of the CPU, enabling it to interrupt any other interrupt mode.

21.2 Features

Up to 16 external pins (EXTINTx), plus one non-maskable pin (NMI)
Dedicated, individually maskable interrupt for each pin
Interrupt on rising, falling, or both edges
Interrupt on high or low levels
Asynchronous interrupts for sleep modes without clock
Filtering of external pins
Event generation from EXTINTx

21.3 Block Diagram

Figure 21-1. EIC Block Diagram Filter Edge/Level Detection Interrupt Wake Event FILTENx EXTINTx intreq_extint inwake_extint evt_extint Filter Edge/Level Detection Interrupt Wake NMIFILTEN NMISENSE[2:0] NMI intreq_nmi inwake_nmi SENSEx[2:0]

21.4 Signal Description

Signal Name Type Description EXTINT[15..0] Digital Input External interrupt pin NMI Digital Input Non-maskable interrupt pin One signal may be available on several pins. SAM D21/DA1 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 324

I/O Multiplexing and Considerations

21.5 Product Dependencies

In order to use this EIC, other parts of the system must be configured correctly, as described below.

21.5.1 I/O Lines

Using the EIC’s I/O lines requires the I/O pins to be configured. Related Links 23. PORT - I/O Pin Controller

21.5.2 Power Management

All interrupts are available down to STANDBY sleep mode, but the EIC can be configured to automatically mask some interrupts in order to prevent device wake-up. The EIC will continue to operate in any sleep mode where the selected source clock is running. The EIC’s interrupts can be used to wake up the device from sleep modes. Events connected to the Event System can trigger other operations in the system without exiting sleep modes. Related Links 16. PM – Power Manager

21.5.3 Clocks

The EIC bus clock (CLK_EIC_APB) can be enabled and disabled in the Power Manager, and the default state of CLK_EIC_APB can be found in the Peripheral Clock Masking section in PM – Power Manager. A generic clock (GCLK_EIC) is required to clock the peripheral. This clock must be configured and enabled in the Generic Clock Controller before using the peripheral. Refer to GCLK – Generic Clock Controller. This generic clock is asynchronous to the user interface clock (CLK_EIC_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to 21.6.9 Synchronization for further details. Related Links

GCLK - Generic Clock Controller

21.5.4 DMA

Not applicable.

21.5.5 Interrupts

There are several interrupt request lines, at least one for the external interrupts (EXTINT) and one for non-maskable interrupt (NMI). The EXTINT interrupt request line is connected to the interrupt controller. Using the EIC interrupt requires the interrupt controller to be configured first. The NMI interrupt request line is also connected to the interrupt controller, but does not require the interrupt to be configured. Related Links

21.5.6 Events

The events are connected to the Event System. Using the events requires the Event System to be configured first. Related Links 24. EVSYS – Event System SAM D21/DA1 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 325

21.5.7 Debug Operation

When the CPU is halted in debug mode, the EIC continues normal operation. If the EIC is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging.

21.5.8 Register Access Protection

All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Interrupt Flag Status and Clear register (INTFLAG)
Non-Maskable Interrupt Flag Status and Clear register (NMIFLAG) Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger. Related Links

21.5.9 Analog Connections

Not applicable.

21.6 Functional Description

21.6.1 Principle of Operation

The EIC detects edge or level condition to generate interrupts to the CPU interrupt controller or events to the Event System. Each external interrupt pin (EXTINT) can be filtered using majority vote filtering, clocked by GCLK_EIC

21.6.2 Basic Operation

21.6.2.1 Initialization

The EIC must be initialized in the following order: 1. Enable CLK_EIC_APB 2. If edge detection or filtering is required, GCLK_EIC must be enabled 3. Write the EIC configuration registers (EVCTRL, WAKEUP, CONFIGy) 4. Enable the EIC To use NMI, GCLK_EIC must be enabled after EIC configuration (NMICTRL).

21.6.2.2 Enabling, Disabling and Resetting

The EIC is enabled by writing a '1' the Enable bit in the Control register (CTRL.ENABLE). The EIC is disabled by writing CTRL.ENABLE to '0'. The EIC is reset by setting the Software Reset bit in the Control register (CTRL.SWRST). All registers in the EIC will be reset to their initial state, and the EIC will be disabled. Refer to the CTRL register description for details.

21.6.3 External Pin Processing

Each external pin can be configured to generate an interrupt/event on edge detection (rising, falling or both edges) or level detection (high or low). The sense of external interrupt pins is configured by writing the Input Sense x bits in the Config n register (CONFIGn.SENSEx). The corresponding interrupt flag (INTFLAG.EXTINT[x]) in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition is met. When the interrupt flag has been cleared in edge-sensitive mode, INTFLAG.EXTINT[x] will only be set if a new interrupt condition is met. In level-sensitive mode, when interrupt has been cleared, INTFLAG.EXTINT[x] will be set immediately if the EXTINTx pin still matches the interrupt condition. SAM D21/DA1 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 326

Each external pin can be filtered by a majority vote filtering, clocked by GCLK_EIC. Filtering is enabled if bit Filter Enable x in the Configuration n register (CONFIGn.FILTENx) is written to '1'. The majority vote filter samples the external pin three times with GCLK_EIC and outputs the value when two or more samples are equal. Table 21-1. Majority Vote Filter Samples [0, 1, 2] Filter Output [0,0,0] 0 [0,0,1] 0 [0,1,0] 0 [0,1,1] 1 [1,0,0] 0 [1,0,1] 1 [1,1,0] 1 [1,1,1] 1 When an external interrupt is configured for level detection, or if filtering is disabled, detection is made asynchronously, and GCLK_EIC is not required. If filtering or edge detection is enabled, the EIC automatically requests the GCLK_EIC to operate (GCLK_EIC must be enabled in the GCLK module, see GCLK – Generic Clock Controller for details). If level detection is enabled, GCLK_EIC is not required, but interrupt and events can still be generated. When an external interrupt is configured for level detection and when filtering is disabled, detection is done asynchronously. Asynchronuous detection does not require GCLK_EIC, but interrupt and events can still be generated. If filtering or edge detection is enabled, the EIC automatically requests GCLK_EIC to operate. GCLK_EIC must be enabled in the GCLK module. Figure 21-2. Interrupt Detections intreq_extint[x] (edge detection / filter) intreq_extint[x] (edge detection / no filter) intreq_extint[x] (level detection / filter) intreq_extint[x] (level detection / no filter) EXTINTx CLK_EIC_APB GCLK_EIC clear INTFLAG.EXTINT[x] No interrupt No interrupt The detection delay depends on the detection mode. Table 21-2. Interrupt Latency Detection mode Latency (worst case) Level without filter Three CLK_EIC_APB periods Level with filter Four GCLK_EIC periods + Three CLK_EIC_APB periods Edge without filter Four GCLK_EIC periods + Three CLK_EIC_APB periods Edge with filter Six GCLK_EIC periods + Three CLK_EIC_APB periods SAM D21/DA1 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 327

GCLK - Generic Clock Controller

21.6.4 Additional Features

21.6.4.1 Non-Maskable Interrupt (NMI)

The non-maskable interrupt pin can also generate an interrupt on edge or level detection, but it is configured with the dedicated NMI Control register (NMICTRL). To select the sense for NMI, write to the NMISENSE bit group in the NMI Control register (NMICTRL.NMISENSE). NMI filtering is enabled by writing a '1' to the NMI Filter Enable bit (NMICTRL.NMIFILTEN). If edge detection or filtering is required, enable GCLK_EIC or CLK_ULP32K. NMI detection is enabled only by the NMICTRL.NMISENSE value, and the EIC is not required to be enabled. When an NMI is detected, the non-maskable interrupt flag in the NMI Flag Status and Clear register is set (NMIFLAG.NMI). NMI interrupt generation is always enabled, and NMIFLAG.NMI generates an interrupt request when set.

21.6.5 DMA Operation

Not applicable.

21.6.6 Interrupts

The EIC has the following interrupt sources:

External interrupt pins (EXTINTx). See 21.6.2 Basic Operation.
Non-maskable interrupt pin (NMI). See 21.6.4 Additional Features. Each interrupt source has an associated interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when an interrupt condition occurs (NMIFLAG for NMI). Each interrupt, except NMI, can be individually enabled by setting the corresponding bit in the Interrupt Enable Set register (INTENSET=1), and disabled by setting the corresponding bit in the Interrupt Enable Clear register (INTENCLR=1). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the EIC is reset. See the INTFLAG register for details on how to clear interrupt flags. The EIC has one interrupt request line for each external interrupt (EXTINTx) and one line for NMI. The user must read the INTFLAG (or NMIFLAG) register to determine which interrupt condition is present. Notes: 1. Interrupts must be globally enabled for interrupt requests to be generated. 2. If an external interrupts (EXTINT) is common on two or more I/O pins, only one will be active (the first one programmed). Related Links

Processor And Architecture

21.6.7 Events

The EIC can generate the following output events:

External event from pin (EXTINTx). Setting an Event Output Control register (EVCTRL.EXTINTEO) enables the corresponding output event. Clearing this bit disables the corresponding output event. Refer to Event System for details on configuring the Event System. When the condition on pin EXTINTx matches the configuration in the CONFIGn register, the corresponding event is generated, if enabled. Related Links 24. EVSYS – Event System SAM D21/DA1 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 328

21.6.8 Sleep Mode Operation

In sleep modes, an EXTINTx pin can wake up the device if the corresponding condition matches the configuration in CONFIGy register. Writing a one to a Wake-Up Enable bit (WAKEUP.WAKEUPEN[x]) enables the wake-up from pin EXTINTx. Writing a zero to a Wake-Up Enable bit (WAKEUP.WAKEUPEN[x]) disables the wake-up from pin EXTINTx. Using WAKEUPEN[x]=1 with INTENSET=0 is not recommended. In sleep modes, an EXTINTx pin can wake up the device if the corresponding condition matches the configuration in CONFIGn register, and the corresponding bit in the Interrupt Enable Set register (INTENSET) is written to '1'. WAKEUP.WAKEUPEN[x]=1 can enable the wake-up from pin EXTINTx. Figure 21-3. Wake-Up Operation Example (High-Level Detection, No Filter, WAKEUPEN[x]=1) CLK_EIC_APB EXTINTx intwake_extint[x] intreq_extint[x] clear INTFLAG.EXTINT[x]wake from sleep mode

21.6.9 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All operations will complete successfully, but the CPU will be stalled, and interrupts will be pending as long as the bus is stalled. The following bits are synchronized when written:

Software Reset bit in the Control register (CTRL.SWRST)
Enable bit in the Control register (CTRL.ENABLE) Related Links

21.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRL 7:0 ENABLE SWRST 0x01 STATUS 7:0 SYNCBUSY 0x02 NMICTRL 7:0 NMIFILTEN NMISENSE[2:0] 0x03 NMIFLAG 7:0 NMI 0x04 EVCTRL 7:0 EXTINTEO7 EXTINTEO6 EXTINTEO5 EXTINTEO4 EXTINTEO3 EXTINTEO2 EXTINTEO1 EXTINTEO0 15:8 EXTINTEO15 EXTINTEO14 EXTINTEO13 EXTINTEO12 EXTINTEO11 EXTINTEO10 EXTINTEO9 EXTINTEO8 23:16 31:24 0x08 INTENCLR 7:0 EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 EXTINT1 EXTINT0 15:8 EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10 EXTINT9 EXTINT8 23:16 31:24 0x0C INTENSET 7:0 EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 EXTINT1 EXTINT0 15:8 EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10 EXTINT9 EXTINT8 23:16 31:24 0x10 INTFLAG 7:0 EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 EXTINT1 EXTINT0 15:8 EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10 EXTINT9 EXTINT8 23:16 31:24 0x14 WAKEUP 7:0 WAKEUPEN7 WAKEUPEN6 WAKEUPEN5 WAKEUPEN4 WAKEUPEN3 WAKEUPEN2 WAKEUPEN1 WAKEUPEN0 15:8 WAKEUPEN1 WAKEUPEN1 WAKEUPEN1 WAKEUPEN1 WAKEUPEN1 WAKEUPEN1

0 WAKEUPEN9 WAKEUPEN8

23:16 31:24 0x18 CONFIG0 7:0 FILTEN1 SENSE1[2:0] FILTEN0 SENSE0[2:0] 15:8 FILTEN3 SENSE3[2:0] FILTEN2 SENSE2[2:0] 23:16 FILTEN5 SENSE5[2:0] FILTEN4 SENSE4[2:0] 31:24 FILTEN7 SENSE7[2:0] FILTEN6 SENSE6[2:0] 0x1C CONFIG1 7:0 FILTEN1 SENSE1[2:0] FILTEN0 SENSE0[2:0] 15:8 FILTEN3 SENSE3[2:0] FILTEN2 SENSE2[2:0] 23:16 FILTEN5 SENSE5[2:0] FILTEN4 SENSE4[2:0] 31:24 FILTEN7 SENSE7[2:0] FILTEN6 SENSE6[2:0]

21.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read- Synchronized" and/or "Write-Synchronized" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. SAM D21/DA1 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 330

21.8.1 Control

Name: CTRL Offset: 0x00 Reset: 0x00 Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 3 2 1 0 ENABLE SWRST Access R/W R/W Reset 0 0 Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete. Value Description 0 The EIC is disabled. 1 The EIC is enabled. Bit 0 – SWRST Software Reset Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the EIC to their initial state, and the EIC will be disabled. Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write operation will be discarded. Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete. Value Description 0 There is no ongoing reset operation. 1 The reset operation is ongoing. SAM D21/DA1 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 331

21.8.2 Status

Name: STATUS Offset: 0x01 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 SYNCBUSY Access R Reset 0 Bit 7 – SYNCBUSY Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. SAM D21/DA1 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 332

21.8.3 Non-Maskable Interrupt Control

Name: NMICTRL Offset: 0x02 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 NMIFILTEN NMISENSE[2:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 3 – NMIFILTEN Non-Maskable Interrupt Filter Enable Value Description 0 NMI filter is disabled. 1 NMI filter is enabled. Bits 2:0 – NMISENSE[2:0] Non-Maskable Interrupt Sense These bits define on which edge or level the NMI triggers. NMISENSE[2:0] Name Description 0x0 NONE No detection 0x1 RISE Rising-edge detection 0x2 FALL Falling-edge detection 0x3 BOTH Both-edges detection 0x4 HIGH High-level detection 0x5 LOW Low-level detection 0x6-0x7 Reserved SAM D21/DA1 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 333

21.8.4 Non-Maskable Interrupt Flag Status and Clear

Name: NMIFLAG Offset: 0x03 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 NMI Access R/W Reset 0 Bit 0 – NMI Non-Maskable Interrupt This flag is cleared by writing a one to it. This flag is set when the NMI pin matches the NMI sense configuration, and will generate an interrupt request. Writing a zero to this bit has no effect. Writing a one to this bit clears the non-maskable interrupt flag. SAM D21/DA1 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 334

21.8.5 Event Control

Name: EVCTRL Offset: 0x04 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 EXTINTEO15 EXTINTEO14 EXTINTEO13 EXTINTEO12 EXTINTEO11 EXTINTEO10 EXTINTEO9 EXTINTEO8 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EXTINTEO7 EXTINTEO6 EXTINTEO5 EXTINTEO4 EXTINTEO3 EXTINTEO2 EXTINTEO1 EXTINTEO0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EXTINTEOx External Interrupt x Event Output Enable [x=15..0] These bits indicate whether the event associated with the EXTINTx pin is enabled or not to generated for every detection. Value Description 0 Event from pin EXTINTx is disabled. 1 Event from pin EXTINTx is enabled. SAM D21/DA1 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 335

21.8.6 Interrupt Enable Clear

Name: INTENCLR Offset: 0x08 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10 EXTINT9 EXTINT8 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 EXTINT1 EXTINT0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EXTINTx External Interrupt x Enable [x=15..0] Writing a zero to this bit has no effect. Writing a one to this bit will clear the External Interrupt x Enable bit, which disables the external interrupt. Value Description 0 The external interrupt x is disabled. 1 The external interrupt x is enabled. SAM D21/DA1 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 336

21.8.7 Interrupt Enable Set

Name: INTENSET Offset: 0x0C Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10 EXTINT9 EXTINT8 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 EXTINT1 EXTINT0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EXTINTx External Interrupt x Enable [x=15..0] Writing a zero to this bit has no effect. Writing a one to this bit will set the External Interrupt x Enable bit, which enables the external interrupt. Value Description 0 The external interrupt x is disabled. 1 The external interrupt x is enabled. SAM D21/DA1 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 337

21.8.8 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x10 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10 EXTINT9 EXTINT8 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 EXTINT1 EXTINT0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EXTINTx External Interrupt x [x=15..0] This flag is cleared by writing a one to it. This flag is set when EXTINTx pin matches the external interrupt sense configuration and will generate an interrupt request if INTENCLR/SET.EXTINT[x] is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the External Interrupt x flag. SAM D21/DA1 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 338

21.8.9 Wake-Up Enable

Name: WAKEUP Offset: 0x14 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 WAKEUPEN15 WAKEUPEN14 WAKEUPEN13 WAKEUPEN12 WAKEUPEN11 WAKEUPEN10 WAKEUPEN9 WAKEUPEN8 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WAKEUPEN7 WAKEUPEN6 WAKEUPEN5 WAKEUPEN4 WAKEUPEN3 WAKEUPEN2 WAKEUPEN1 WAKEUPEN0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – WAKEUPENx External Interrupt x Wake-up Enable [x=15..0] This bit enables or disables wake-up from Sleep modes when the EXTINTx pin matches the external interrupt sense configuration. Value Description 0 Wake-up from the EXTINTx pin is disabled. 1 Wake-up from the EXTINTx pin is enabled. SAM D21/DA1 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 339

21.8.10 Configuration n

Name: CONFIGn Offset: 0x18 + n*0x04 [n=0..1] Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 FILTEN7 SENSE7[2:0] FILTEN6 SENSE6[2:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 FILTEN5 SENSE5[2:0] FILTEN4 SENSE4[2:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 FILTEN3 SENSE3[2:0] FILTEN2 SENSE2[2:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FILTEN1 SENSE1[2:0] FILTEN0 SENSE0[2:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 3, 7, 11, 15, 19, 23, 27, 31 – FILTENx Filter x Enable [x=7..0] 0: Filter is disabled for EXTINT[n*8+x] input. 1: Filter is enabled for EXTINT[n*8+x] input. Bits 0:2, 4:6, 8:10, 12:14, 16:18, 20:22, 24:26, 28:30 – SENSEx Input Sense x Configuration [x=7..0] SENSEx[2:0] Name Description 0x0 NONE No detection 0x1 RISE Rising-edge detection 0x2 FALL Falling-edge detection 0x3 BOTH Both-edges detection 0x4 HIGH High-level detection 0x5 LOW Low-level detection 0x6-0x7 Reserved Notes: 1. FILTEN7-FILTEN0 bits and SENSE7[2:0]-SENSE0[2:0] bitfields in CONFIG0 register belong to External Interrupt 7 to 0. 2. FILTEN7-FILTEN0 bits and SENSE7[2:0]-SENSE0[2:0] bitfields in CONFIG1 register belong to External Interrupt 15 to 8. SAM D21/DA1 Family EIC – External Interrupt Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 340

Nonvolatile Memory Controller (NVMCTRL)

22.1 Overview

Non-volatile Memory (NVM) is a reprogrammable Flash memory that retains program and data storage even with power off. It embeds a main array and a separate smaller Read While Write EEPROM Emulation array (RWWEE Emulation) that can be programmed while reading the main array (RWWEE stands for Read (the main array) while Write (the EEPROM Emulation)). The NVM Controller (NVMCTRL) connects to the AHB and APB bus interfaces for system access to the NVM block. The AHB interface is used for reads and writes to the NVM block, while the APB interface is used for commands and configuration.

22.2 Features

32-bit AHB interface for reads and writes
Read-While-Write DATA Flash
All NVM sections are memory mapped to the AHB, including calibration and system configuration
32-bit APB interface for commands and control
Programmable wait states for read optimization
16 regions can be individually protected or unprotected
Additional protection for bootloader
Supports device protection through a security bit
Interface to Power Manager for power-down of Flash blocks in sleep modes
Can optionally wake up on exit from sleep or on first access
Direct-mapped cache Note: A register with property "Enable-Protected" may contain bits that are not enable-protected.

22.3 Block Diagram

Figure 22-1. Block Diagram Command and Control NVM Interface Cache NVM BlockNVMCTRL AHB APB main array RWWEE array SAM D21/DA1 Family Nonvolatile Memory Controller (NVMCTRL) © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 341

22.4 Signal Description

Not applicable.

22.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described in the following sections.

22.5.1 Power Management

The NVMCTRL will continue to operate in any sleep mode where the selected source clock is running. The NVMCTRL interrupts can be used to wake up the device from sleep modes. The Power Manager will automatically put the NVM block into a low-power state when entering sleep mode. This is based on the Control B register (CTRLB) SLEEPPRM bit setting. Refer to the 22.8.2 CTRLB. SLEEPPRM register description for more details. The NVM block goes into low-power mode automatically when the device enters STANDBY mode regardless of SLEEPPRM. The NVM Page Buffer is lost when the NVM goes into low power mode therefore a write command must be issued prior entering the NVM low power mode. NVMCTRL SLEEPPRM can be disabled to avoid such loss when the CPU goes into sleep except if the device goes into STANDBY mode for which there is no way to retain the Page Buffer. Related Links 16. PM – Power Manager

22.5.2 Clocks

Two synchronous clocks are used by the NVMCTRL. One is provided by the AHB bus (CLK_NVMCTRL_AHB) and the other is provided by the APB bus (CLK_NVMCTRL_APB). For higher system frequencies, a programmable number of wait states can be used to optimize performance. When changing the AHB bus frequency, the user must ensure that the NVM Controller is configured with the proper number of wait states. Refer to the Electrical Characteristics for the exact number of wait states to be used for a particular frequency range. Related Links 37. Electrical Characteristics at 85℃

22.5.3 Interrupts

The NVM Controller interrupt request line is connected to the interrupt controller. Using the NVMCTRL interrupt requires the interrupt controller to be programmed first.

22.5.4 Debug Operation

When an external debugger forces the CPU into debug mode, the peripheral continues normal operation. Access to the NVM block can be protected by the security bit. In this case, the NVM block will not be accessible. See the section on the NVMCTRL 22.6.6 Security Bit for details.

22.5.5 Register Access Protection

All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the following registers:

Interrupt Flag Status and Clear register (INTFLAG)
Status register (STATUS) Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description. Related Links

22.5.6 Analog Connections

Not applicable.

22.6 Functional Description

22.6.1 Principle of Operation

The NVM Controller is a client on the AHB and APB buses. It responds to commands, read requests and write requests, based on user configuration.

22.6.1.1 Initialization

After power up, the NVM Controller goes through a power-up sequence. During this time, access to the NVM Controller from the AHB bus is halted. Upon power-up completion, the NVM Controller is operational without any need for user configuration.

22.6.2 Memory Organization

Refer to the Physical Memory Map for memory sizes and addresses for each device. The NVM is organized into rows, where each row contains four pages, as shown in the NVM Row Organization figure. The NVM has a row-erase granularity, while the write granularity is by page. In other words, a single row erase will erase all four pages in the row, while four write operations are used to write the complete row. Figure 22-2. NVM Row Organization Page (n*4) + 3 Page (n*4) + 2 Page (n*4) + 1 Page (n*4) + 0 Row n The NVM block contains a calibration and auxiliary space plus a dedicated RWWEE Emulation address space that are memory mapped. Refer to the NVM Organization figure below for details. The calibration and auxiliary space contains factory calibration and system configuration information. These spaces can be read from the AHB bus in the same way as the main NVM main address space. In addition, a boot loader section can be allocated at the beginning of the main array, and an EEPROM Emulation section can be allocated at the end of the NVM main address space. SAM D21/DA1 Family Nonvolatile Memory Controller (NVMCTRL) © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 343

Figure 22-3. NVM Memory Organization Calibration and Auxillary Space RWWEE Address Space NVM Main Address Space NVM Base Address + 0x00800000 NVM Base Address + 0x00400000 NVM Base Address + NVM Size NVM Base Address The lower rows in the NVM main address space can be allocated as a boot loader section by using the BOOTPROT fuses, and the upper rows can be allocated to EEPROM Emulation, as shown in the figure below. The boot loader section is protected by the lock bit(s) corresponding to this address space and by the BOOTPROT[2:0] fuse. The EEPROM Emulation rows can be written regardless of the region lock status. The number of rows protected by BOOTPROT is given in Boot Loader Size, the number of rows allocated to the EEPROM Emulation are given in EEPROM Size. SAM D21/DA1 Family Nonvolatile Memory Controller (NVMCTRL) © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 344

Figure 22-4. EEPROM Emulation and Boot Loader Allocation Related Links

22.6.3 Region Lock Bits

The NVM block is grouped into 16 equally sized regions. The region size is dependent on the Flash memory size, and is given in the table below. Each region has a dedicated lock bit preventing writing and erasing pages in the region. After production, all regions will be unlocked. Table 22-1. Region Size Memory Size [KB] Region Size [KB] 256 16 128 8 64 4 32 2 To lock or unlock a region, the Lock Region and Unlock Region commands are provided. Writing one of these commands will temporarily lock/unlock the region containing the address loaded in the ADDR register. ADDR can be written by software, or the automatically loaded value from a write operation can be used. The new setting will stay in effect until the next Reset, or until the setting is changed again using the Lock and Unlock commands. The current status of the lock can be determined by reading the LOCK register. SAM D21/DA1 Family Nonvolatile Memory Controller (NVMCTRL) © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 345

To change the default lock/unlock setting for a region, the user configuration section of the auxiliary space must be written using the Write Auxiliary Page command. Writing to the auxiliary space will take effect after the next Reset. Therefore, a boot of the device is needed for changes in the lock/unlock setting to take effect. Refer to the Physical Memory Map for calibration and auxiliary space address mapping. Related Links

22.6.4 Command and Data Interface

The NVM Controller is addressable from the APB bus, while the NVM main address space is addressable from the AHB bus. Read and automatic page write operations are performed by addressing the NVM main address space or the RWWEE address space directly, while other operations such as manual page writes and row erases must be performed by issuing commands through the NVM Controller. To issue a command, the CTRLA.CMD bits must be written along with the CTRLA.CMDEX value. When a command is issued, INTFLAG.READY will be cleared until the command has completed. Any commands written while INTFLAG.READY is low will be ignored. The CTRLB register must be used to control the power reduction mode, read wait states, and the write mode.

22.6.4.1 NVM Read

Reading from the NVM main address space is performed via the AHB bus by addressing the NVM main address space or auxiliary address space directly. Read data is available after the configured number of read wait states (CTRLB.RWS) set in the NVM Controller. The number of cycles data are delayed to the AHB bus is determined by the read wait states. Examples of using zero and one wait states are shown in the following figure. Reading the NVM main address space while a programming or erase operation is ongoing on the NVM main array results in an AHB bus stall until the end of the operation. Reading the NVM main array does not stall the bus when the RWWEE array is being programmed or erased. Figure 22-5. Read Wait State Examples

0 Wait States

1 Wait States

22.6.4.2 RWWEE Read

Reading from the RWW EEPROM address space is performed via the AHB bus by addressing the RWWEE address space directly. Read timings are similar to regular NVM read timings when access size is Byte or half-Word. The AHB data phase is twice as long in case of full-Word-size access. SAM D21/DA1 Family Nonvolatile Memory Controller (NVMCTRL) © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 346

It is not possible to read the RWWEE area while the NVM main array is being written or erased, whereas the RWWEE area can be written or erased while the main array is being read. The RWWEE address space is not cached, therefore it is recommended to limit access to this area for performance and power consumption considerations.

22.6.4.3 NVM Write

The NVM Controller requires that an erase must be done before programming. The entire NVM main address space and the RWWEE address space can be erased by a debugger Chip Erase command. Alternatively, rows can be individually erased by the Erase Row command or the RWWEE Erase Row command to erase the NVM main address space or the RWWEE address space, respectively. After programming the NVM main array, the region that the page resides in can be locked to prevent spurious write or erase sequences. Locking is performed on a per-region basis, and so, locking a region will lock all pages inside the region. Data to be written to the NVM block are first written to and stored in an internal buffer called the page buffer. The page buffer contains the same number of bytes as an NVM page. Writes to the page buffer must be 16 or 32 bits. 8-bit writes to the page buffer are not allowed and will cause a system exception. Both the NVM main array and the RWWEE array share the same page buffer. Writing to the NVM block via the AHB bus is performed by a load operation to the page buffer. For each AHB bus write, the address is stored in the ADDR register. After the page buffer has been loaded with the required number of bytes, the page can be written to the NVM main array or the RWWEE array by setting CTRLA.CMD to 'Write Page' or 'RWWEE Write Page', respectively, and setting the key value to CMDEX. The LOAD bit in the STATUS register indicates whether the page buffer has been loaded or not. Before writing the page to memory, the accessed row must be erased. Automatic page writes are enabled by writing the manual write bit to zero (CTRLB.MANW=0). This will trigger a write operation to the page addressed by ADDR when the last location of the page is written. Because the address is automatically stored in ADDR during the I/O bus write operation, the last given address will be present in the ADDR register. There is no need to load the ADDR register manually, unless a different page in memory is to be written. The row to be written to must be erased before the write command is given.

Write to the page buffer by addressing the NVM main address space directly
Write the page buffer to memory: CTRL.CMD='Write Page' and CMDEX
The READY bit in the INTFLAG register will be low while programming is in progress, and access through the AHB will be stalled The row to be written to must be erased before the last write to the page buffer is performed. Note that partially written pages must be written with a manual write.
Write to the page buffer by addressing the NVM main address space directly. When the last location in the page buffer is written, the page is automatically written to NVM main address space.
INTFLAG.READY will be zero while programming is in progress and access through the AHB will be stalled.

22.6.4.4 Page Buffer Clear

The page buffer is automatically set to all '1' after a page write is performed. If a partial page has been written and it is desired to clear the contents of the page buffer, the Page Buffer Clear command can be used.

22.6.4.5 Erase Row

Before a page can be written, the row containing that page must be erased. The Erase Row command can be used to erase the desired row in the NVM main address space. The RWWEE Erase Row can be used to erase the desired row in the RWWEE array. Erasing the row sets all bits to '1'. If the row resides in a region that is locked, the erase will not be performed and the Lock Error bit in the Status register (STATUS.LOCKE) will be set.

22.6.4.5.1 Procedure for Erase Row

Write the address of the row to erase to ADDR. Any address within the row can be used. SAM D21/DA1 Family Nonvolatile Memory Controller (NVMCTRL) © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 347

Issue an Erase Row command. Note: The NVM Address bit field in the Address register (ADDR.ADDR) uses 16-bit addressing.

22.6.4.6 Lock and Unlock Region

These commands are used to lock and unlock regions as detailed in section 22.6.3 Region Lock Bits.

22.6.4.7 Set and Clear Power Reduction Mode

The NVM Controller and block can be taken in and out of power reduction mode through the Set and Clear Power Reduction Mode commands. When the NVM Controller and block are in power reduction mode, the Power Reduction Mode bit in the Status register (STATUS.PRM) is set.

22.6.5 NVM User Configuration

The NVM user configuration resides in the auxiliary space. Refer to the Physical Memory Map of the device for calibration and auxiliary space address mapping. The bootloader resides in the main array starting at offset zero. The allocated boot loader section is write-protected. Table 22-2. Boot Loader Size BOOTPROT [2:0] Rows Protected by BOOTPROT Boot Loader Size in Bytes 0x7(1) None 0 0x6 2 512 0x5 4 1024 0x4 8 2048 0x3 16 4096 0x2 32 8192 0x1 64 16384 0x0 128 32768 Note: 1. Default value is 0x7. The EEPROM[2:0] bits indicate the EEPROM Emulation size, see the table below. The EEPROM Emulation resides in the upper rows of the NVM main address space and is writable, regardless of the region lock status. Note that it is different from the RWWEE Emulation section residing outside of the main Flash. Table 22-3. EEPROM Emulation Size EEPROM[2:0] Rows Allocated to EEPROM Emulation EEPROM Emulation Size in Bytes

7 None 0

The security bit allows the entire chip to be locked from external access for code security. The security bit can be written by a dedicated command, Set Security Bit (SSB). Once set, the only way to clear the security bit is through a debugger Chip Erase command. After issuing the SSB command, the PROGE error bit can be checked. In order to increase the security level it is recommended to enable the internal BOD33 when the security bit is set. Related Links 13. DSU - Device Service Unit

22.6.7 Cache

The NVM Controller cache reduces the device power consumption and improves system performance when wait states are required. Only the NVM main array address space is cached. It is a direct-mapped cache that implements 8 lines of 64 bits (i.e., 64 Bytes). NVM Controller cache can be enabled by writing a '0' to the Cache Disable bit in the Control B register (CTRLB.CACHEDIS). The cache can be configured to three different modes using the Read Mode bit group in the Control B register (CTRLB.READMODE). The INVALL command can be issued using the Command bits in the Control A register to invalidate all cache lines (CTRLA.CMD=INVALL). Commands affecting NVM content automatically invalidate cache lines. SAM D21/DA1 Family Nonvolatile Memory Controller (NVMCTRL) © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 349

22.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 CMD[6:0] 15:8 CMDEX[7:0] 0x02 ... 0x03 Reserved 0x04 CTRLB 7:0 MANW RWS[3:0] 15:8 SLEEPPRM[1:0] 23:16 CACHEDIS READMODE[1:0] 31:24 0x08 PARAM 7:0 NVMP[7:0] 15:8 NVMP[15:8] 23:16 RWWEEP[3:0] PSZ[2:0] 31:24 RWWEEP[11:4] 0x0C INTENCLR 7:0 ERROR READY 0x0D ... 0x0F Reserved 0x10 INTENSET 7:0 ERROR READY 0x11 ... 0x13 Reserved 0x14 INTFLAG 7:0 ERROR READY 0x15 ... 0x17 Reserved 0x18 STATUS 7:0 NVME LOCKE PROGE LOAD PRM 15:8 SB 0x1A ... 0x1B Reserved 0x1C ADDR 7:0 ADDR[7:0] 15:8 ADDR[15:8] 23:16 ADDR[21:16] 31:24 0x20 LOCK 7:0 LOCK[7:0] 15:8 LOCK[15:8]

22.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read- Synchronized" and/or "Write-Synchronized" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. SAM D21/DA1 Family Nonvolatile Memory Controller (NVMCTRL) © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 350

22.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x0000 Property: PAC Write-Protection Bit 15 14 13 12 11 10 9 8 CMDEX[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CMD[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bits 15:8 – CMDEX[7:0] Command Execution When this bit group is written to the key value 0xA5, the command written to CMD will be executed. If a value different from the key value is tried, the write will not be performed and the Programming Error bit in the Status register (STATUS.PROGE) will be set. PROGE is also set if a previously written command is not completed yet. The key value must be written at the same time as CMD. If a command is issued through the APB bus on the same cycle as an AHB bus access, the AHB bus access will be given priority. The command will then be executed when the NVM block and the AHB bus are idle. INTFLAG.READY must be '1' when the command is issued. Bit 0 of the CMDEX bit group will read back as '1' until the command is issued. Note: The NVM Address bit field in the Address register (ADDR.ADDR) uses 16-bit addressing. Bits 6:0 – CMD[6:0] Command These bits define the command to be executed when the CMDEX key is written. CMD[6:0] Group Configuration 0x02 ER Erase Row - Erases the row addressed by the ADDR register in the NVM main array. 0x03 - Reserved 0x04 WP Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. 0x05 EAR Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the Security bit is not set and only to the User Configuration Row. 0x06 WAP Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the Security bit is not set and only to the User Configuration Row. 0x07-0x0E - Reserved 0x0F - Reserved 0x1A-0x19 - Reserved 0x1A RWWEEER RWWEE Erase Row - Erases the row addressed by the ADDR register in the RWWEE array. 0x1B - Reserved 0x1C RWWEEWP RWWEE Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register in the RWWEE array. 0x1D-0x3F - Reserved 0x40 LR Lock Region - Locks the region containing the address location in the ADDR register. SAM D21/DA1 Family Nonvolatile Memory Controller (NVMCTRL) © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 351

CMD[6:0] Group Configuration 0x41 UR Unlock Region - Unlocks the region containing the address location in the ADDR register. 0x42 SPRM Sets the Power Reduction mode. 0x43 CPRM Clears the Power Reduction mode. 0x44 PBC Page Buffer Clear - Clears the page buffer. 0x45 SSB Set Security Bit - Sets the Security bit by writing 0x00 to the first byte in the lockbit row. 0x46 INVALL Invalidates all cache lines. 0x47 LDR Lock Data Region - Locks the data region containing the address location in the ADDR register. When the security extension is enabled, only secure access can lock secure regions. 0x48 UDR Unlock Data Region - Unlocks the data region containing the address location in the ADDR register. When the security extension is enabled, only secure access can unlock secure regions. 0x47-0x7F - Reserved SAM D21/DA1 Family Nonvolatile Memory Controller (NVMCTRL) © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 352

22.8.2 Control B

Name: CTRLB Offset: 0x04 Reset: 0x00000080 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 CACHEDIS READMODE[1:0] Access R/W R/W R/W Reset 0 0 0 Bit 15 14 13 12 11 10 9 8 SLEEPPRM[1:0] Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 MANW RWS[3:0] Access R/W R/W R/W R/W R/W Reset 1 0 0 0 0 Bit 18 – CACHEDIS Cache Disable This bit is used to disable the cache. Value Description

0 The cache is enabled

1 The cache is disabled

Bits 17:16 – READMODE[1:0] NVMCTRL Read Mode Value Name Description 0x0 NO_MISS_PENALTY The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. 0x1 LOW_POWER Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increased run time. 0x2 DETERMINISTIC The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed Flash wait states. This mode can be used for real-time applications that require deterministic execution timings. 0x3 Reserved Bits 9:8 – SLEEPPRM[1:0] Power Reduction Mode during Sleep Indicates the Power Reduction Mode during sleep. Value Name Description 0x0 WAKEUPACCESS NVM block enters low-power mode when entering sleep. NVM block exits low-power mode upon first access. 0x1 WAKEUPINSTANT NVM block enters low-power mode when entering sleep. NVM block exits low-power mode when exiting sleep. 0x2 Reserved 0x3 DISABLED Auto power reduction disabled. SAM D21/DA1 Family Nonvolatile Memory Controller (NVMCTRL) © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 353

Bit 7 – MANW Manual Write Note that reset value of this bit is '1'. Value Description 0 Writing to the last word in the page buffer will initiate a write operation to the page addressed by the last write operation. This includes writes to memory and auxiliary rows. 1 Write commands must be issued through the CTRLA.CMD register. Bits 4:1 – RWS[3:0] NVM Read Wait States These bits control the number of wait states for a read operation. '0' indicates zero wait states, '1' indicates one wait state, etc., up to 15 wait states. This register is initialized to 0 wait states. Software can change this value based on the NVM access time and system frequency. SAM D21/DA1 Family Nonvolatile Memory Controller (NVMCTRL) © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 354

22.8.3 NVM Parameter

Name: PARAM Offset: 0x08 Reset: 0x000XXXXX Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 RWWEEP[11:4] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 RWWEEP[3:0] PSZ[2:0] Access R R R R R R R Reset 0 0 0 0 x x x Bit 15 14 13 12 11 10 9 8 NVMP[15:8] Access R R R R R R R R Reset x x x x x x x x Bit 7 6 5 4 3 2 1 0 NVMP[7:0] Access R R R R R R R R Reset x x x x x x x x Bits 31:20 – RWWEEP[11:0] Read While Write EEPROM Emulation area Pages Indicates the number of pages in the RWW EEPROM Emulation address space. Bits 18:16 – PSZ[2:0] Page Size Indicates the page size. Not all devices of the device families will provide all the page sizes indicated in the table. Value Name Description 0x0 8 8 bytes 0x1 16 16 bytes 0x2 32 32 bytes 0x3 64 64 bytes 0x4 128 128 bytes 0x5 256 256 bytes 0x6 512 512 bytes 0x7 1024 1024 bytes Bits 15:0 – NVMP[15:0] NVM Pages Indicates the number of pages in the NVM main address space. SAM D21/DA1 Family Nonvolatile Memory Controller (NVMCTRL) © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 355

22.8.4 Interrupt Enable Clear

22.8.5 Interrupt Enable Set

Name: INTENSET Offset: 0x10 Reset: 0x00 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 5 4 3 2 1 0 ERROR READY Access R/W R/W Reset 0 0 Bit 1 – ERROR Error Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit sets the ERROR interrupt enable. This bit will read as the current value of the ERROR interrupt enable. Bit 0 – READY NVM Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit sets the READY interrupt enable. This bit will read as the current value of the READY interrupt enable. SAM D21/DA1 Family Nonvolatile Memory Controller (NVMCTRL) © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 357

22.8.6 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x14 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 ERROR READY Access R/W R Reset 0 0 Bit 1 – ERROR Error This flag is set on the occurrence of an NVME, LOCKE or PROGE error. This bit can be cleared by writing a '1' to its bit location. Value Description 0 No errors have been received since the last clear. 1 At least one error has occurred since the last clear. Bit 0 – READY NVM Ready Value Description 0 The NVM controller is busy programming or erasing. 1 The NVM controller is ready to accept a new command. SAM D21/DA1 Family Nonvolatile Memory Controller (NVMCTRL) © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 358

22.8.7 Status

Name: STATUS Offset: 0x18 Reset: 0x0X00 Property: – Bit 15 14 13 12 11 10 9 8 SB Access R Reset x Bit 7 6 5 4 3 2 1 0 NVME LOCKE PROGE LOAD PRM Access R/W R/W R/W R/W R Reset 0 0 0 0 0 Bit 8 – SB Security Bit Status Value Description 0 The Security bit is inactive. 1 The Security bit is active. Bit 4 – NVME NVM Error This bit can be cleared by writing a '1' to its bit location. Value Description

0 No programming or erase errors have been received from the NVM controller since this bit was last

cleared. 1 At least one error has been registered from the NVM Controller since this bit was last cleared. Bit 3 – LOCKE Lock Error Status This bit can be cleared by writing a '1' to its bit location. Value Description 0 No programming of any locked lock region has happened since this bit was last cleared. 1 Programming of at least one locked lock region has happened since this bit was last cleared. Bit 2 – PROGE Programming Error Status This bit can be cleared by writing a '1' to its bit location. Value Description

0 No invalid commands or bad keywords were written in the NVM Command register since this bit was

last cleared.

1 An invalid command and/or a bad keyword was/were written in the NVM Command register since this

bit was last cleared. Bit 1 – LOAD NVM Page Buffer Active Loading This bit indicates that the NVM page buffer has been loaded with one or more words. Immediately after an NVM load has been performed, this flag is set. It remains set until a page write or a page buffer clear (PBCLR) command is given. This bit can be cleared by writing a '1' to its bit location. Bit 0 – PRM Power Reduction Mode This bit indicates the current NVM power reduction state. The NVM block can be set in power reduction mode in two ways: through the command interface or automatically when entering sleep with SLEEPPRM set accordingly. PRM can be cleared in three ways: through AHB access to the NVM block, through the command interface (SPRM and CPRM) or when exiting sleep with SLEEPPRM set accordingly. Value Description 0 NVM is not in power reduction mode. SAM D21/DA1 Family Nonvolatile Memory Controller (NVMCTRL) © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 359

22.8.8 Address

Name: ADDR Offset: 0x1C Reset: 0x00000000 Property: PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 ADDR[21:16] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ADDR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 21:0 – ADDR[21:0] NVM Address ADDR drives the hardware half-word offset from the start address of the corresponding NVM section when a command is executed using CMDEX. This register is also automatically updated when writing to the page buffer. The effective address for the operation is Start address of the section + 2*ADDR. Example: For erasing the 3rd row in the Flash memory, spanning from 0x00000200 to 0x000002FF, ADDR must be written with the half-word offset address of any half-word within this range, that is any value between 0x100 and 0x17F. For erasing the 5th row in the RWWEE memory, spanning from 0x00400400 to 0x004004FF, ADDR should be written with the half-word offset address of any half-word within this range, that is any value between 0x200 and 0x27F. SAM D21/DA1 Family Nonvolatile Memory Controller (NVMCTRL) © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 361

22.8.9 Lock Section

Name: LOCK Offset: 0x20 Reset: 0xXXXX Property: – Bit 15 14 13 12 11 10 9 8 LOCK[15:8] Access R R R R R R R R Reset x x x x x x x x Bit 7 6 5 4 3 2 1 0 LOCK[7:0] Access R R R R R R R R Reset x x x x x x x x Bits 15:0 – LOCK[15:0] Region Lock Bits To set or clear these bits, the CMD register must be used. Default state after erase will be unlocked (0xFFFF). Default state after reset will be loaded from the NVM User Row. Value Description 0 The corresponding lock region is locked. 1 The corresponding lock region is not locked. SAM D21/DA1 Family Nonvolatile Memory Controller (NVMCTRL) © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 362

PORT - I/O Pin Controller

23.1 Overview

The IO Pin Controller (PORT) controls the I/O pins of the device. The I/O pins are organized in a series of groups, collectively referred to as a PORT group. Each PORT group can have up to 32 pins that can be configured and controlled individually or as a group. The number of PORT groups on a device may depend on the package/number of pins. Each pin may either be used for general-purpose I/O under direct application control or be assigned to an embedded device peripheral. When used for general-purpose I/O, each pin can be configured as input or output, with highly configurable driver and pull settings. All I/O pins have true read-modify-write functionality when used for general-purpose I/O; the direction or the output value of one or more pins may be changed (set, reset or toggled) explicitly without unintentionally changing the state of any other pins in the same port group by a single, atomic 8-, 16- or 32-bit write. The PORT is connected to the high-speed bus matrix through an AHB/APB bridge. The Pin Direction, Data Output Value and Data Input Value registers may also be accessed using the low-latency CPU local bus (IOBUS; ARM® single-cycle I/O port) .

23.2 Features

Selectable input and output configuration for each individual pin
Software-controlled multiplexing of peripheral functions on I/O pins
Flexible pin configuration through a dedicated Pin Configuration register
Configurable output driver and pull settings: – Totem-pole (push-pull) – Pull configuration – Driver strength
Configurable input buffer and pull settings: – Internal pull-up or pull-down – Input sampling criteria – Input buffer can be disabled if not needed for lower power consumption – Read-Modify-Write support for output value (OUTCLR/OUTSET/OUTGL) and pin direction (DIRCLR/ DIRSET/DIRTGL) SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 363

23.3 Block Diagram

Figure 23-1. PORT Block Diagram ANALOG BLOCKS PERIPHERALS Digital Controls of Analog Blocks Analog Pad Connections I/O PADS Port Line Bundles IP Line Bundles Peripheral Mux Select PORT Control and Status Pad Line Bundles PORTMUX

23.4 Signal Description

Table 23-1. Signal description for PORT Signal name Type Description Pxy Digital I/O General-purpose I/O pin y in group x Refer to the I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be mapped on several pins. Related Links 7. I/O Multiplexing and Considerations

23.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly as follows.

23.5.1 I/O Lines

The I/O lines of the PORT are mapped to pins of the physical device. The following naming scheme is used: Each line bundle with up to 32 lines is assigned an identifier 'xy', with letter x=A, B, C… and two-digit number y=00, 01, …31. Examples: A24, C03. PORT pins are labeled 'Pxy' accordingly, for example PA24, PC03. This identifies each pin in the device uniquely. Each pin may be controlled by one or more peripheral multiplexer settings, which allow the pad to be routed internally to a dedicated peripheral function. When the setting is enabled, the selected peripheral has control over the output state of the pad, as well as the ability to read the current physical pad state. Refer to I/O Multiplexing and Considerations for details. Device-specific configurations may cause some lines (and the corresponding Pxy pin) not to be implemented. SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 364

I/O Multiplexing and Considerations

23.5.2 Power Management

During Reset, all PORT lines are configured as inputs with input buffers, output buffers and pull disabled. The PORT peripheral will continue operating in any sleep mode where its source clock is running.

23.5.3 Clocks

The PORT bus clock (CLK_PORT_APB) can be enabled and disabled in the Power Manager, and the default state of CLK_PORT_APB can be found in the Peripheral Clock Masking section in PM – Power Manager. The PORT requires an APB clock, which may be divided from the CPU main clock and allows the CPU to access the registers of PORT through the high-speed matrix and the AHB/APB bridge. The PORT also requires an AHB clock for CPU IOBUS accesses to the PORT. That AHB clock is the internal PORT clock. The priority of IOBUS accesses is higher than APB accesses. One clock cycle latency can be observed on the APB access in case of concurrent PORT accesses. Related Links

23.5.4 DMA

Not applicable.

23.5.5 Interrupts

Not applicable.

23.5.6 Events

Not applicable.

23.5.7 Debug Operation

When the CPU is halted in debug mode, this peripheral will continue normal operation.

23.5.8 Register Access Protection

23.5.9 Analog Connections

Analog functions are connected directly between the analog blocks and the I/O pads using analog buses. However, selecting an analog peripheral function for a given pin will disable the corresponding digital features of the pad. The CPU local bus (IOBUS) is an interface that connects the CPU directly to the PORT. It is a single-cycle bus interface, which does not support wait states. It supports 8-bit, 16-bit and 32-bit sizes. This bus is generally used for low latency operation. The Data Direction (DIR) and Data Output Value (OUT) registers can be read, written, set, cleared or be toggled using this bus, and the Data Input Value (IN) registers can be read. Since the IOBUS cannot wait for IN register resynchronization, the Control register (CTRL) must be configured to continuous sampling of all pins that need to be read via the IOBUS in order to prevent stale data from being read. Note: Refer to the Product Mapping chapter for the IOBUS address. SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 365

23.6 Functional Description

Figure 23-2. Overview of the PORT PULLENx OUTx DIRx INENx PORT PAD VDD INEN OE OUT PULLEN PAD Pull Resistor PG NG Input to Other Modules Analog Input/Output ININx APB Bus Synchronizer Q D RR D Q DRIVEx DRIVE VDDIO

23.6.1 Principle of Operation

Each PORT group of up to 32 pins is controlled by the registers in PORT, as described in the figure. These registers in PORT are duplicated for each PORT group, with increasing base addresses. The number of PORT groups may depend on the package/number of pins. Figure 23-3. Overview of the peripheral functions multiplexing Port y PINCFG Port y Periph Signal 0 PORT bit y PMUXEN Data+Config Periph Signal 1 Periph Signal 15 Port y PMUX[3:0] Port y PMUX Select Port y Line Bundle PAD y Pad y Peripheral Signals to be muxed to Pad y Port y Peripheral Mux Enable Line Bundle PORTMUX The I/O pins of the device are controlled by PORT peripheral registers. Each port pin has a corresponding bit in the Data Direction (DIR) and Data Output Value (OUT) registers to enable that pin as an output and to define the Output state. The direction of each pin in a PORT group is configured by the DIR register. If a bit in DIR is set to '1', the corresponding pin is configured as an output pin. If a bit in DIR is set to '0', the corresponding pin is configured as an input pin. SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 366

When the direction is set as output, the corresponding bit in the OUT register will set the level of the pin. If bit y in OUT is written to '1', pin y is driven HIGH. If bit y in OUT is written to '0', pin y is driven LOW. Pin configuration can be set by Pin Configuration (PINCFGy) registers, with y=00, 01, ..31 representing the pin number within the group. The Data Input Value (IN) is set as the input value of a port pin with resynchronization to the PORT clock. To reduce power consumption, these input synchronizers can be clocked only when system requires reading the input value, as specified in the SAMPLING field of the Control register (CTRL). The value of the pin can always be read, whether the pin is configured as input or output. If the Input Enable bit in the Pin Configuration registers (PINCFGy.INEN) is '0', the input value will not be sampled. In PORT, the Peripheral Multiplexer Enable bit in the PINCFGy register (PINCFGy.PMUXEN) can be written to '1' to enable the connection between peripheral functions and individual I/O pins. The Peripheral Multiplexing n (PMUXn) registers select the peripheral function for the corresponding pin. This will override the connection between the PORT and that I/O pin, and connect the selected peripheral signal to the particular I/O pin instead of the PORT line bundle.

23.6.2 Basic Operation

23.6.2.1 Initialization

After reset, all standard function device I/O pads are connected to the PORT with outputs tri-stated and input buffers disabled, even if there is no clock running. However, specific pins, such as those used for connection to a debugger, may be configured differently, as required by their special function.

23.6.2.2 Operation

Each I/O pin Pxy can be controlled by the registers in PORT. Each PORT group x has its own set of PORT registers, with a base address at byte address (PORT + 0x80 * group index) (A corresponds to group index 0, B to 1, etc...). Within that set of registers, the pin index is y, from 0 to 31. Refer to I/O Multiplexing and Considerations for details on available pin configuration and PORT groups. Configuring Pins as Output To use pin Pxy as an output, write bit y of the DIR register to '1'. This can also be done by writing bit y in the DIRSET register to '1' - this will avoid disturbing the configuration of other pins in that group. The y bit in the OUT register must be written to the desired output value. Similarly, writing an OUTSET bit to '1' will set the corresponding bit in the OUT register to '1'. Writing a bit in OUTCLR to '1' will set that bit in OUT to zero. Writing a bit in OUTTGL to '1' will toggle that bit in OUT. Configuring Pins as Input To use pin Pxy as an input, bit y in the DIR register must be written to '0'. This can also be done by writing bit y in the DIRCLR register to '1' - this will avoid disturbing the configuration of other pins in that group. The input value can be read from bit y in register IN as soon as the INEN bit in the Pin Configuration register (PINCFGy.INEN) is written to '1' to enable the pin's input buffer. By default, the input synchronizer is clocked only when an input read is requested. This will delay the read operation by two cycles of the PORT clock. To remove the delay, the input synchronizers for each PORT group of eight pins can be configured to be always active, but this will increase power consumption. This is enabled by writing '1' to the corresponding SAMPLINGn bit field of the CTRL register, see CTRL.SAMPLING for details. Using Alternative Peripheral Functions To use pin Pxy as one of the available peripheral functions, the corresponding PMUXEN bit of the PINCFGy register must be '1'. The PINCFGy register for pin Pxy is at byte offset (PINCFG0 + y). The peripheral function can be selected by setting the PMUXO or PMUXE in the PMUXn register. The PMUXO/ PMUXE is at byte offset PMUX0 + (y/2). The chosen peripheral must also be configured and enabled. Related Links 7. I/O Multiplexing and Considerations SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 367

23.6.3 I/O Pin Configuration

The Pin Configuration register (PINCFGy) is used for additional I/O pin configuration. A pin can be set in a totem-pole or pull configuration. As pull configuration is done through the Pin Configuration register, all intermediate PORT states during switching of pin direction and pin values are avoided. The I/O pin configurations are described further in this chapter, and summarized in Table 23-2.

23.6.3.1 Pin Configurations Summary

Table 23-2. Pin Configurations Summary DIR INEN PULLEN OUT Configuration 0 0 0 X Reset or analog I/O: all digital disabled 0 0 1 0 Pull-down; input buffer disabled 0 0 1 1 Pull-up; input buffer disabled 0 1 0 X Input 0 1 1 0 Input with pull-down 0 1 1 1 Input with pull-up 1 0 X X Output; input buffer disabled 1 1 X X Output; input buffer enabled

23.6.3.2 Input Configuration

Figure 23-4. I/O configuration - Standard Input PULLEN DIR OUT IN INEN PULLEN INEN DIR 0 1 0 Figure 23-5. I/O Configuration - Input with Pull PULLEN DIR OUT IN INEN PULLEN INEN DIR 1 1 0 Note: When pull is enabled, the pull value is defined by the OUT value.

23.6.3.3 Totem-Pole Output

When configured for totem-pole (push-pull) output, the pin is driven low or high according to the corresponding bit setting in the OUT register. In this configuration there is no current limitation for sink or source other than what the pin is capable of. If the pin is configured for input, the pin will float if no external pull is connected. Note: Enabling the output driver will automatically disable pull. SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 368

Figure 23-6. I/O Configuration - Totem-Pole Output with Disabled Input PULLEN DIR OUT IN INEN PULLEN INEN DIR 0 0 1 Figure 23-7. I/O Configuration - Totem-Pole Output with Enabled Input PULLEN DIR OUT IN INEN PULLEN INEN DIR 0 1 1 Figure 23-8. I/O Configuration - Output with Pull PULLEN DIR OUT IN INEN PULLEN INEN DIR 1 0 0

23.6.3.4 Digital Functionality Disabled

Neither Input nor Output functionality are enabled. Figure 23-9. I/O Configuration - Reset or Analog I/O: Digital Output, Input and Pull Disabled PULLEN DIR OUT IN INEN PULLEN INEN DIR 0 0 0

23.6.4 PORT Access Priority

The PORT is accessed by different systems:

The ARM ® CPU through the ARM® single-cycle I/O port (IOBUS)
The ARM ® CPU through the high-speed matrix and the AHB/APB bridge (APB) The following priority is adopted: SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 369

ARM ® CPU IOBUS (No wait tolerated) 2. APB SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 370

23.7 Register Summary

The I/O pins are assembled in pin groups with up to 32 pins. Group 0 consists of the PA pins, and group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 DIR 7:0 DIR[7:0] 15:8 DIR[15:8] 23:16 DIR[23:16] 31:24 DIR[31:24] 0x04 DIRCLR 7:0 DIRCLR[7:0] 15:8 DIRCLR[15:8] 23:16 DIRCLR[23:16] 31:24 DIRCLR[31:24] 0x08 DIRSET 7:0 DIRSET[7:0] 15:8 DIRSET[15:8] 23:16 DIRSET[23:16] 31:24 DIRSET[31:24] 0x0C DIRTGL 7:0 DIRTGL[7:0] 15:8 DIRTGL[15:8] 23:16 DIRTGL[23:16] 31:24 DIRTGL[31:24] 0x10 OUT 7:0 OUT[7:0] 15:8 OUT[15:8] 23:16 OUT[23:16] 31:24 OUT[31:24] 0x14 OUTCLR 7:0 OUTCLR[7:0] 15:8 OUTCLR[15:8] 23:16 OUTCLR[23:16] 31:24 OUTCLR[31:24] 0x18 OUTSET 7:0 OUTSET[7:0] 15:8 OUTSET[15:8] 23:16 OUTSET[23:16] 31:24 OUTSET[31:24] 0x1C OUTTGL 7:0 OUTTGL[7:0] 15:8 OUTTGL[15:8] 23:16 OUTTGL[23:16] 31:24 OUTTGL[31:24] 0x20 IN 7:0 IN[7:0] 15:8 IN[15:8] 23:16 IN[23:16] 31:24 IN[31:24] 0x24 CTRL 7:0 SAMPLING[7:0] 15:8 SAMPLING[15:8] 23:16 SAMPLING[23:16] 31:24 SAMPLING[31:24] 0x28 WRCONFIG 7:0 PINMASK[7:0] 15:8 PINMASK[15:8] 23:16 DRVSTR PULLEN INEN PMUXEN 31:24 HWSEL WRPINCFG WRPMUX PMUX[3:0] 0x2C ... 0x2F Reserved 0x30 PMUX0 7:0 PMUXO[3:0] PMUXE[3:0] ... 0x3F PMUX15 7:0 PMUXO[3:0] PMUXE[3:0] 0x40 PINCFG0 7:0 DRVSTR PULLEN INEN PMUXEN ... SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 371

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x5F PINCFG31 7:0 DRVSTR PULLEN INEN PMUXEN

23.8 Register Description

23.8.1 Data Direction

Name: DIR Offset: 0x00 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to configure one or more I/O pins as an input or output. This register can be manipulated without doing a read-modify-write operation by using the Data Direction Toggle (DIRTGL), Data Direction Clear (DIRCLR) and Data Direction Set (DIRSET) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 DIR[31:24] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIR[23:16] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIR[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIR[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DIR[31:0] Port Data Direction These bits set the data direction for the individual I/O pins in the PORT group. Value Description 0 The corresponding I/O pin in the PORT group is configured as an input. 1 The corresponding I/O pin in the PORT group is configured as an output. SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 373

23.8.2 Data Direction Clear

Name: DIRCLR Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to set one or more I/O pins as an input, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data Direction Set (DIRSET) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 DIRCLR[31:24] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIRCLR[23:16] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIRCLR[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIRCLR[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DIRCLR[31:0] Port Data Direction Clear Writing a '0' to a bit has no effect. Writing a '1' to a bit will clear the corresponding bit in the DIR register, which configures the I/O pin as an input. Value Description 0 The corresponding I/O pin in the PORT group will keep its configuration. 1 The corresponding I/O pin in the PORT group is configured as input. SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 374

23.8.3 Data Direction Set

Name: DIRSET Offset: 0x08 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to set one or more I/O pins as an output, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data Direction Clear (DIRCLR) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 DIRSET[31:24] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIRSET[23:16] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIRSET[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIRSET[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DIRSET[31:0] Port Data Direction Set Writing '0' to a bit has no effect. Writing '1' to a bit will set the corresponding bit in the DIR register, which configures the I/O pin as an output. Value Description 0 The corresponding I/O pin in the PORT group will keep its configuration. 1 The corresponding I/O pin in the PORT group is configured as an output. SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 375

23.8.4 Data Direction Toggle

Name: DIRTGL Offset: 0x0C Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to toggle the direction of one or more I/O pins, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Set (DIRSET) and Data Direction Clear (DIRCLR) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 DIRTGL[31:24] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIRTGL[23:16] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIRTGL[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIRTGL[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DIRTGL[31:0] Port Data Direction Toggle Writing '0' to a bit has no effect. Writing '1' to a bit will toggle the corresponding bit in the DIR register, which reverses the direction of the I/O pin. Value Description 0 The corresponding I/O pin in the PORT group will keep its configuration. 1 The direction of the corresponding I/O pin is toggled. SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 376

23.8.5 Data Output Value

Name: OUT Offset: 0x10 Reset: 0x00000000 Property: PAC Write-Protection This register sets the data output drive value for the individual I/O pins in the PORT. This register can be manipulated without doing a read-modify-write operation by using the Data Output Value Clear (OUTCLR), Data Output Value Set (OUTSET), and Data Output Value Toggle (OUTTGL) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 OUT[31:24] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OUT[23:16] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 OUT[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OUT[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31:0 – OUT[31:0] PORT Data Output Value For pins configured as outputs via the Data Direction register (DIR), these bits set the logical output drive level. For pins configured as inputs via the Data Direction register (DIR) and with pull enabled via the Pull Enable bit in the Pin Configuration register (PINCFG.PULLEN), these bits will set the input pull direction. Value Description 0 The I/O pin output is driven low, or the input is connected to an internal pull-down. 1 The I/O pin output is driven high, or the input is connected to an internal pull-up. SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 377

23.8.6 Data Output Value Clear

Name: OUTCLR Offset: 0x14 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to set one or more output I/O pin drive levels low, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle (OUTTGL) and Data Output Value Set (OUTSET) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 OUTCLR[31:24] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OUTCLR[23:16] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 OUTCLR[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OUTCLR[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31:0 – OUTCLR[31:0] PORT Data Output Value Clear Writing '0' to a bit has no effect. Writing '1' to a bit will clear the corresponding bit in the OUT register. Pins configured as outputs via the Data Direction register (DIR) will be set to low output drive level. Pins configured as inputs via DIR and with pull enabled via the Pull Enable bit in the Pin Configuration register (PINCFG.PULLEN) will set the input pull direction to an internal pull-down. Value Description 0 The corresponding I/O pin in the PORT group will keep its configuration. 1 The corresponding I/O pin output is driven low, or the input is connected to an internal pull-down. SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 378

23.8.7 Data Output Value Set

Name: OUTSET Offset: 0x18 Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to set one or more output I/O pin drive levels high, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle (OUTTGL) and Data Output Value Clear (OUTCLR) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 OUTSET[31:24] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OUTSET[23:16] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 OUTSET[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OUTSET[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31:0 – OUTSET[31:0] PORT Data Output Value Set Writing '0' to a bit has no effect. Writing '1' to a bit will set the corresponding bit in the OUT register, which sets the output drive level high for I/O pins configured as outputs via the Data Direction register (DIR). For pins configured as inputs via Data Direction register (DIR) with pull enabled via the Pull Enable register (PULLEN), these bits will set the input pull direction to an internal pull-up. Value Description 0 The corresponding I/O pin in the group will keep its configuration. 1 The corresponding I/O pin output is driven high, or the input is connected to an internal pull-up. SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 379

23.8.8 Data Output Value Toggle

Name: OUTTGL Offset: 0x1C Reset: 0x00000000 Property: PAC Write-Protection This register allows the user to toggle the drive level of one or more output I/O pins, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Set (OUTSET) and Data Output Value Clear (OUTCLR) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 OUTTGL[31:24] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OUTTGL[23:16] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 OUTTGL[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OUTTGL[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31:0 – OUTTGL[31:0] PORT Data Output Value Toggle Writing '0' to a bit has no effect. Writing '1' to a bit will toggle the corresponding bit in the OUT register, which inverts the output drive level for I/O pins configured as outputs via the Data Direction register (DIR). For pins configured as inputs via Data Direction register (DIR) with pull enabled via the Pull Enable register (PULLEN), these bits will toggle the input pull direction. Value Description 0 The corresponding I/O pin in the PORT group will keep its configuration. 1 The corresponding OUT bit value is toggled. SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 380

23.8.9 Data Input Value

Name: IN Offset: 0x20 Reset: 0x00000000 Property: - Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 IN[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 IN[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 IN[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 IN[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – IN[31:0] PORT Data Input Value These bits are cleared when the corresponding I/O pin input sampler detects a logical low level on the input pin. These bits are set when the corresponding I/O pin input sampler detects a logical high level on the input pin. SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 381

23.8.10 Control

Name: CTRL Offset: 0x24 Reset: 0x00000000 Property: PAC Write-Protection Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit 31 30 29 28 27 26 25 24 SAMPLING[31:24] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SAMPLING[23:16] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SAMPLING[15:8] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SAMPLING[7:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31:0 – SAMPLING[31:0] Input Sampling Mode Configures the input sampling functionality of the I/O pin input samplers, for pins configured as inputs via the Data Direction register (DIR). The input samplers are enabled and disabled in sub-groups of eight. Thus if any pins within a byte request continuous sampling, all pins in that eight pin sub-group will be continuously sampled. Value Description 0 On demand sampling of I/O pin is enabled. 1 Continuous sampling of I/O pin is enabled. SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 382

23.8.11 Write Configuration

Name: WRCONFIG Offset: 0x28 Reset: 0x00000000 Property: PAC Write-Protection, Write-Only Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. This Write-only register is used to configure several pins simultaneously with the same configuration and peripheral multiplexing. To avoid side effect of non-atomic access, 8-bit or 16-bit writes to this register will have no effect. Reading this register always returns zero. Bit 31 30 29 28 27 26 25 24 HWSEL WRPINCFG WRPMUX PMUX[3:0] Access W W W W W W W Reset 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DRVSTR PULLEN INEN PMUXEN Access W W W W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 PINMASK[15:8] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PINMASK[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 31 – HWSEL Half-Word Select This bit selects the half-word field of a 32-PORT group to be reconfigured in the atomic write operation. This bit will always read as zero. Value Description 0 The lower 16 pins of the PORT group will be configured. 1 The upper 16 pins of the PORT group will be configured. Bit 30 – WRPINCFG Write PINCFG This bit determines whether the atomic write operation will update the Pin Configuration register (PINCFGy) or not for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits. Writing '0' to this bit has no effect. Writing '1' to this bit updates the configuration of the selected pins with the written WRCONFIG.DRVSTR, This bit will always read as zero. Value Description 0 The PINCFGy registers of the selected pins will not be updated. 1 The PINCFGy registers of the selected pins will be updated. SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 383

Bit 28 – WRPMUX Write PMUX This bit determines whether the atomic write operation will update the Peripheral Multiplexing register (PMUXn) or not for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits. Writing '0' to this bit has no effect. Writing '1' to this bit updates the pin multiplexer configuration of the selected pins with the written WRCONFIG. PMUX value. This bit will always read as zero. Value Description 0 The PMUXn registers of the selected pins will not be updated. 1 The PMUXn registers of the selected pins will be updated. Bits 27:24 – PMUX[3:0] Peripheral Multiplexing These bits determine the new value written to the Peripheral Multiplexing register (PMUXn) for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPMUX bit is set. These bits will always read as zero. Bit 22 – DRVSTR Output Driver Strength Selection This bit determines the new value written to PINCFGy.DRVSTR for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set. This bit will always read as zero. Bit 18 – PULLEN Pull Enable This bit determines the new value written to PINCFGy.PULLEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set. This bit will always read as zero. Bit 17 – INEN Input Enable This bit determines the new value written to PINCFGy.INEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set. This bit will always read as zero. Bit 16 – PMUXEN Peripheral Multiplexer Enable This bit determines the new value written to PINCFGy.PMUXEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set. This bit will always read as zero. Bits 15:0 – PINMASK[15:0] Pin Mask for Multiple Pin Configuration These bits select the pins to be configured within the half-word group selected by the WRCONFIG.HWSEL bit. These bits will always read as zero. Value Description 0 The configuration of the corresponding I/O pin in the half-word group will be left unchanged. 1 The configuration of the corresponding I/O pin in the half-word PORT group will be updated. SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 384

23.8.12 Peripheral Multiplexing n

Name: PMUX Offset: 0x30 + n*0x01 [n=0..15] Reset: 0x00 Property: PAC Write-Protection Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. There are up to 16 Peripheral Multiplexing registers in each group, one for every set of two subsequent I/O lines. The n denotes the number of the set of I/O lines. Bit 7 6 5 4 3 2 1 0 PMUXO[3:0] PMUXE[3:0] Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 7:4 – PMUXO[3:0] Peripheral Multiplexing for Odd-Numbered Pin These bits select the peripheral function for odd-numbered pins (2*n + 1) of a PORT group, if the corresponding PINCFGy.PMUXEN bit is '1'. Not all possible values for this selection may be valid. For more details, refer to the I/O Multiplexing and Considerations. PMUXO[3:0] Name Description 0x0 A Peripheral function A selected 0x1 B Peripheral function B selected 0x2 C Peripheral function C selected 0x3 D Peripheral function D selected 0x4 E Peripheral function E selected 0x5 F Peripheral function F selected 0x6 G Peripheral function G selected 0x7 H Peripheral function H selected 0x8 I Peripheral function I selected 0x9-0xF - Reserved Bits 3:0 – PMUXE[3:0] Peripheral Multiplexing for Even-Numbered Pin These bits select the peripheral function for even-numbered pins (2*n) of a PORT group, if the corresponding PINCFGy.PMUXEN bit is '1'. Not all possible values for this selection may be valid. For more details, refer to the I/O Multiplexing and Considerations. PMUXE[3:0] Name Description 0x0 A Peripheral function A selected 0x1 B Peripheral function B selected 0x2 C Peripheral function C selected 0x3 D Peripheral function D selected 0x4 E Peripheral function E selected 0x5 F Peripheral function F selected 0x6 G Peripheral function G selected 0x7 H Peripheral function H selected 0x8 I Peripheral function I selected SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 385

PMUXE[3:0] Name Description 0x9-0xF - Reserved Related Links 7. I/O Multiplexing and Considerations SAM D21/DA1 Family PORT - I/O Pin Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 386

23.8.13 Pin Configuration

Name: PINCFG Offset: 0x40 + n*0x01 [n=0..31] Reset: 0x00 Property: PAC Write-Protection Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. There are up to 32 Pin Configuration registers in each PORT group, one for each I/O line. Bit 7 6 5 4 3 2 1 0 DRVSTR PULLEN INEN PMUXEN Access RW RW RW RW Reset 0 0 0 0 Bit 6 – DRVSTR Output Driver Strength Selection This bit controls the output driver strength of an I/O pin configured as an output. Value Description 0 Pin drive strength is set to normal drive strength. 1 Pin drive strength is set to stronger drive strength. Bit 2 – PULLEN Pull Enable This bit enables the internal pull-up or pull-down resistor of an I/O pin configured as an input. Value Description 0 Internal pull resistor is disabled, and the input is in a high-impedance configuration.

1 Internal pull resistor is enabled, and the input is driven to a defined logic level in the absence of

external input. Bit 1 – INEN Input Enable This bit controls the input buffer of an I/O pin configured as either an input or output. Writing a zero to this bit disables the input buffer completely, preventing read-back of the Physical Pin state when the pin is configured as either an input or output. Value Description 0 Input buffer for the I/O pin is disabled, and the input value will not be sampled. 1 Input buffer for the I/O pin is enabled, and the input value will be sampled when required. Bit 0 – PMUXEN Peripheral Multiplexer Enable This bit enables or disables the peripheral multiplexer selection set in the Peripheral Multiplexing register (PMUXn) to enable or disable alternative peripheral control over an I/O pin direction and output drive value. Writing a zero to this bit allows the PORT to control the pad direction via the Data Direction register (DIR) and output drive value via the Data Output Value register (OUT). The peripheral multiplexer value in PMUXn is ignored. Writing '1' to this bit enables the peripheral selection in PMUXn to control the pad. In this configuration, the Physical Pin state may still be read from the Data Input Value register (IN) if PINCFGn.INEN is set. Value Description

0 The peripheral multiplexer selection is disabled, and the PORT registers control the direction and

output drive value.

1 The peripheral multiplexer selection is enabled, and the selected peripheral function controls the

EVSYS – Event System

24.1 Overview

The Event System (EVSYS) allows autonomous, low-latency and configurable communication between peripherals. Several peripherals can be configured to generate and/or respond to signals known as events. The exact condition to generate an event, or the action taken upon receiving an event, is specific to each peripheral. Peripherals that respond to events are called event users. Peripherals that generate events are called event generators. A peripheral can have one or more event generators and can have one or more event users. Communication is made without CPU intervention and without consuming system resources such as bus or RAM bandwidth. This reduces the load on the CPU and other system resources, compared to a traditional interrupt-based system.

24.2 Features

12 configurable event channels: – Can be connected to any event generator – Can provide a pure asynchronous, resynchronized, or synchronous path
74 Event Generators
29 Event Users
Configurable Edge Detector
Peripherals can be Event Generators, Event Users, or both
SleepWalking and interrupt for operation in sleep modes
Software Event Generation
Each Event User can choose which channel to respond to, and several Event Users can share the same channel and therefore answer to the same event

24.3 Block Diagram

Figure 24-1. Event System Block Diagram PERIPHERALS EVSYS USER MUX PERIPHERALS GCLK GENERATOR EVENTS CLOCK REQUESTS USERS EVENTS EVENT CHANNELS

24.4 Signal Description

24.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

24.5.1 I/O Lines

Not applicable.

24.5.2 Power Management

The EVSYS can be used to wake up the CPU from all sleep modes, even if the clock used by the EVSYS channel and the EVSYS bus clock are disabled. Refer to the PM – Power Manager for details on the different sleep modes. In all sleep modes, although the clock for the EVSYS is stopped, the device still can wake up the EVSYS clock. Some event generators can generate an event when their clocks are stopped. Related Links 16. PM – Power Manager

24.5.3 Clocks

The EVSYS bus clock (CLK_EVSYS_APB) can be enabled and disabled in the Main Clock module, and the default state of CLK_EVSYS_APB can be found in Peripheral Clock Masking. Each EVSYS channel has a dedicated generic clock (GCLK_EVSYS_CHANNEL_n). These are used for event detection and propagation for each channel. These clocks must be configured and enabled in the generic clock controller before using the EVSYS. Refer to GCLK - Generic Clock Controller for details. Related Links

GCLK - Generic Clock Controller

24.5.4 DMA

Not applicable.

24.5.5 Interrupts

The interrupt request line is connected to the Interrupt Controller. Using the EVSYS interrupts requires the interrupt controller to be configured first. Refer to Nested Vector Interrupt Controller for details. Related Links

24.5.6 Events

Not applicable.

24.5.7 Debug Operation

When the CPU is halted in Debug mode, this peripheral will continue normal operation. If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result during debugging. This peripheral can be forced to halt operation during debugging.

24.5.8 Register Access Protection

Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following:

Interrupt Flag Status and Clear register (INTFLAG) Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. Write-protection does not apply for accesses through an external debugger.

24.5.9 Analog Connections

24.6 Functional Description

24.6.1 Principle of Operation

The Event System consists of several channels which route the internal events from peripherals (generators) to other internal peripherals or IO pins (users). Each event generator can be selected as source for multiple channels, but a channel cannot be set to use multiple event generators at the same time.

24.6.2 Basic Operation

24.6.2.1 Initialization

Before enabling events routing within the system, the User Multiplexer (USER) and Channel (CHANNEL) register must be configured. The User Multiplexer (USER) must be configured first. Configure the User Multiplexer (USER) register: 1. The channel to be connected to a user is written to the Channel bit group (USER.CHANNEL) 2. The user to connect the channel is written to the User bit group (USER.USER) Configure the Channel (CHANNEL) register: 1. The channel to be configured is written to the Channel Selection bit group (CHANNEL.CHANNEL) 2. The path to be used is written to the Path Selection bit group (CHANNEL.PATH) 3. The type of edge detection to use on the channel is written to the Edge Selection bit group (CHANNEL.EDGSEL) 4. The event generator to be used is written to the Event Generator bit group (CHANNEL.EVGEN)

24.6.2.2 Enabling, Disabling and Resetting

The EVSYS is always enabled. The EVSYS is reset by writing a ‘1’ to the Software Reset bit in the Control register (CTRL.SWRST). All registers in the EVSYS will be reset to their initial state and all ongoing events will be canceled. Refer to CTRL.SWRST register for details.

24.6.2.3 User Multiplexer Setup

The user multiplexer defines the channel to be connected to which event user. Each user multiplexer is dedicated to one event user. A user multiplexer receives all event channels output and must be configured to select one of these channels, as shown in the next figure. The channel is selected with the Channel bit group in the USER register (USER.CHANNEL). The user multiplexer must always be configured before the channel. A full list of selectable users can be found in the User Multiplexer register (USER) description. Refer to UserList for details. To configure a user multiplexer, the USER register must be written in a single 16-bit write. It is possible to read out the configuration of a user by first selecting the user by writing to USER.USER using an 8-bit write and then performing a read of the 16-bit USER register. SAM D21/DA1 Family EVSYS – Event System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 390

Figure 24-2. User MUX USER MUX PERIPHERAL A PERIPHERAL B USER.CHANNEL USER_EVT_x USER_EVT_y USER_EVT_z CHANNEL_EVT_0 CHANNEL_EVT_1 CHANNEL_EVT_m

24.6.2.4 Channel Setup

An event channel can select one event from a list of event generators. Depending on configuration, the selected event could be synchronized, resynchronized or asynchronously sent to the users. When synchronization or resynchronization is required, the channel includes an internal edge detector, allowing the Event System to generate internal events when rising, falling or both edges are detected on the selected event generator. An event channel is able to generate internal events for the specific software commands. All these configurations are available in the Channel register (CHANNEL). To configure a channel, the Channel register must be written in a single 32-bit write. It is possible to read out the configuration of a channel by first selecting the channel by writing to CHANNEL.CHANNEL using a, 8-bit write, and then performing a read of the CHANNEL register.

24.6.2.5 Channel Path

There are three different ways to propagate the event provided by an event generator:

Asynchronous path
Synchronous path
Resynchronized path SAM D21/DA1 Family EVSYS – Event System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 391

Figure 24-3. Channel The path is selected by writing to the Path Selection bit group in the Channel register (CHANNEL.PATH).

24.6.2.5.1 Asynchronous Path

When using the asynchronous path, the events are propagated from the event generator to the event user without intervention from the Event System. The GCLK for this channel (GCLK_EVSYS_CHANNEL_n) is not mandatory, meaning that an event will be propagated to the user without any clock latency. When the asynchronous path is selected, the channel cannot generate any interrupts, and the Channel Status register (CHSTATUS) is always zero. No edge detection is available; this must be handled in the event user. When the event generator and the event user share the same generic clock, using the asynchronous path will propagate the event with the least amount of latency.

24.6.2.5.2 Synchronous Path

The synchronous path should be used when the event generator and the event channel share the same generator for the generic clock and also if event user supports synchronous path. If event user doesn't support synchronous path, asynchronous path has to be selected. If they do not share the same clock, a logic change from the event generator to the event channel might not be detected in the channel, which means that the event will not be propagated to the event user. For details on generic clock generators, refer to GCLK - Generic Clock Controller. When using the synchronous path, the channel is able to generate interrupts. The channel status bits in the Channel Status register (CHSTATUS) are also updated and available for use. If the Generic Clocks Request bit in the Control register (CTRL.GCLKREQ) is zero, the channel operates in SleepWalking mode and request the configured generic clock only when an event is to be propagated through the channel. If CTRL.GCLKREQ is one, the generic clock will always be on for the configured channel. Related Links 15. GCLK - Generic Clock Controller

24.6.2.5.3 Resynchronized Path

The resynchronized path should be used when the event generator and the event channel do not share the same generic clock generator. When the resynchronized path is used, resynchronization of the event from the event generator is done in the channel. For details on generic clock generators, refer to GCLK - Generic Clock Controller. When the resynchronized path is used, the channel is able to generate interrupts. The channel status bits in the Channel Status register (CHSTATUS) are also updated and available for use. SAM D21/DA1 Family EVSYS – Event System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 392

If the Generic Clocks Request bit in the Control register is zero (CTRL.GCLKREQ=0), the channel operates in SleepWalking mode and requests the configured generic clock only when an event is to be propagated through the channel. If CTRL.GCLKREQ=1 , the generic clock will always be on for the configured channel. Related Links 15. GCLK - Generic Clock Controller

24.6.2.6 Edge Detection

When synchronous or resynchronized paths are used, edge detection must be used. The event system can perform edge detection in three different ways:

Generate an event only on the rising edge
Generate an event only on the falling edge
Generate an event on rising and falling edges Edge detection is selected by writing to the Edge Selection bit group in the Channel register (CHANNEL.EDGSEL). If the generator event is a pulse, both edges cannot be selected. Use the rising edge or falling edge detection methods, depending on the generator event default level.

24.6.2.7 Event Generators

Each event channel can receive the events form all event generators. All event generators are listed in the statement of CHANNEL.EVGEN. For details on event generation, refer to the corresponding module chapter. The channel event generator is selected by the Event Generator bit group in the Channel register (CHANNEL.EVGEN). By default, the channels are not connected to any event generators (ie, CHANNEL.EVGEN = 0)

24.6.2.8 Channel Status

The Channel Status register (CHSTATUS) shows the status of the channels when using a synchronous or resynchronized path. There are two different status bits in CHSTATUS for each of the available channels:

The CHSTATUS.CHBUSYn bit will be set when an event on the corresponding channel n has not been handled by all event users connected to that channel.
The CHSTATUS.USRRDYn bit will be set when all event users connected to the corresponding channel are ready to handle incoming events on that channel.

24.6.2.9 Software Event

A software event can be initiated on a channel by setting the Software Event bit in the Channel register (CHANNEL.SWEVT) to ‘1’ at the same time as writing the Channel bits (CHANNEL.CHANNEL). This will generate a software event on the selected channel. The software event can be used for application debugging, and functions like any event generator. To use the software event, the event path must be configured to either a synchronous path or resynchronized path (CHANNEL.PATH = 0x0 or 0x1), edge detection must be configured to rising-edge detection (CHANNEL.EDGSEL= 0x1) and the Generic Clock Request bit must be set to '1' (CTRL.GCLKREQ=0x1).

24.6.3 Interrupts

The EVSYS has the following interrupt sources:

Overrun Channel n (OVRn): for details, refer to The Overrun Channel n Interrupt section.
Event Detected Channel n (EVDn): for details, refer to The Event Detected Channel n Interrupt section. These interrupts events are asynchronous wake-up sources. See Sleep Mode Controller. Each interrupt source has an interrupt flag which is in the Interrupt Flag Status and Clear (INTFLAG) register. The flag is set when the interrupt is issued. Each interrupt event can be individually enabled by setting a ‘1’ to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by setting a ‘1’ to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt event is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt event works until the interrupt flag is cleared, the interrupt is disabled, or the Event System is reset. See INTFLAG for details on how to clear interrupt flags. All interrupt events from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. Refer to the Nested Vector Interrupt Controller for details. The event user must read the INTFLAG register to determine what the interrupt condition is. SAM D21/DA1 Family EVSYS – Event System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 393

Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector Interrupt Controller for details. Related Links

24.6.3.1 The Overrun Channel n Interrupt

The Overrun Channel n interrupt flag in the Interrupt Flag Status and Clear register (CHINTFLAGn.OVR) will be set, and the optional interrupt will be generated in the following cases:

One or more event users on channel n is not ready when there is a new event.
An event occurs when the previous event on channel m has not been handled by all event users connected to that channel. The flag will only be set when using resynchronized paths. In the case of asynchronous path, the CHINTFLAGn.OVR is always read as zero. Related Links

24.6.3.2 The Event Detected Channel n Interrupt

The Event Detected Channel n interrupt flag in the Interrupt Flag Status and Clear register (CHINTFLAGn.EVD) is set when an event coming from the event generator configured on channel n is detected. The flag will only be set when using a resynchronized path. In the case of asynchronous path, the CHINTFLAGn.EVD is always zero. Related Links

24.6.4 Sleep Mode Operation

The EVSYS can generate interrupts to wake up the device from any sleep mode. Some event generators can generate an event when the system clock is stopped. The generic clock (GCLK_EVSYS_CHANNELx) for this channel will be restarted if the channel uses a synchronized path or a resynchronized path, without waking the system from sleep. The clock remains active only as long as necessary to handle the event. After the event has been handled, the clock will be turned off and the system will remain in the original sleep mode. This is known as SleepWalking. When an asynchronous path is used, there is no need for the clock to be activated for the event to be propagated to the user. On a software reset, all registers are set to their reset values and any ongoing events are canceled.

24.7 Register Summary

Table 24-1. Event System Register Summary Offset Name Bit Pos. 0x00 CTRL 7:0 GCLKREQ SWRST 0x01 ... 0x03 Reserved 0x04 CHANNEL 7:0 CHANNEL[3:0] 0x05 15:8 SWEVT 0x06 23:16 EVGEN[6:0] 0x07 31:24 EDGSEL[1:0] PATH[1:0] 0x08 USER 7:0 USER[4:0] 0x09 15:8 CHANNEL[4:0] 0x0A Reserved SAM D21/DA1 Family EVSYS – Event System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 394

Pos. 0x0B Reserved 0x0C CHSTATUS 7:0 USRRDY7 USRRDY6 USRRDY5 USRRDY4 USRRDY3 USRRDY2 USRRDY1 USRRDY0 0x0D 15:8 CHBUSY7 CHBUSY6 CHBUSY5 CHBUSY4 CHBUSY3 CHBUSY2 CHBUSY1 CHBUSY0 0x0E 23:16 USRRDY11 USRRDY10 USRRDY9 USRRDY8 0x0F 31:24 CHBUSY11 CHBUSY10 CHBUSY9 CHBUSY8 0x10 INTENCLR 7:0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 0x11 15:8 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 0x12 23:16 OVR11 OVR10 OVR9 OVR8 0x13 31:24 EVD11 EVD10 EVD9 EVD8 0x14 INTENSET 7:0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 0x15 15:8 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 0x16 23:16 OVR11 OVR10 OVR9 OVR8 0x17 31:24 EVD11 EVD10 EVD9 EVD8 0x18 INTFLAG 7:0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 0x19 15:8 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 0x1A 23:16 OVR11 OVR10 OVR9 OVR8 0x1B 31:24 EVD11 EVD10 EVD9 EVD8

24.8 Register Description

24.8.1 Control

Name: CTRL Offset: 0x00 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 GCLKREQ SWRST Access R/W W Reset 0 0 Bit 4 – GCLKREQ Generic Clock Requests This bit is used to determine whether the generic clocks used for the different channels should be on all the time or only when an event needs the generic clock. Events propagated through asynchronous paths will not need a generic clock. Value Description 0 Generic clock is requested and turned on only if an event is detected. 1 Generic clock for a channel is always on. Bit 0 – SWRST Software Reset Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the EVSYS to their initial state. Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Note: Before applying a Software Reset it is recommended to disable the event generators. SAM D21/DA1 Family EVSYS – Event System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 396

Name: CHANNEL Offset: 0x04 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 EDGSEL[1:0] PATH[1:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 23 22 21 20 19 18 17 16 EVGEN[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SWEVT Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 CHANNEL[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 27:26 – EDGSEL[1:0] Edge Detection Selection These bits set the type of edge detection to be used on the channel. These bits must be written to zero when using the asynchronous path. EDGSEL[1:0] Name Description 0x0 NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x1 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x3 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path Bits 25:24 – PATH[1:0] Path Selection These bits are used to choose the path to be used by the selected channel. The path choice can be limited by the channel source. PATH[1:0] Name Description 0x0 SYNCHRONOUS Synchronous path 0x1 RESYNCHRONIZED Resynchronized path 0x2 ASYNCHRONOUS Asynchronous path 0x3 Reserved Bits 22:16 – EVGEN[6:0] Event Generator Selection These bits are used to choose which event generator to connect to the selected channel. Value Event Generator Description 0x00 NONE No event generator selected 0x01 RTC CMP0 Compare 0 (mode 0 and 1) or Alarm 0 (mode 2) SAM D21/DA1 Family EVSYS – Event System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 397

Value Event Generator Description 0x02 RTC CMP1 Compare 1 0x03 RTC OVF Overflow 0x04 RTC PER0 Period 0 0x05 RTC PER1 Period 1 0x06 RTC PER2 Period 2 0x07 RTC PER3 Period 3 0x08 RTC PER4 Period 4 0x09 RTC PER5 Period 5 0x0A RTC PER6 Period 6 0x0B RTC PER7 Period 7 0x0C EIC EXTINT0 External Interrupt 0 0x0D EIC EXTINT1 External Interrupt 1 0x0E EIC EXTINT2 External Interrupt 2 0x0F EIC EXTINT3 External Interrupt 3 0x10 EIC EXTINT4 External Interrupt 4 0x11 EIC EXTINT5 External Interrupt 5 0x12 EIC EXTINT6 External Interrupt 6 0x13 EIC EXTINT7 External Interrupt 7 0x14 EIC EXTINT8 External Interrupt 8 0x15 EIC EXTINT9 External Interrupt 9 0x16 EIC EXTINT10 External Interrupt 10 0x17 EIC EXTINT11 External Interrupt 11 0x18 EIC EXTINT12 External Interrupt 12 0x19 EIC EXTINT13 External Interrupt 13 0x1A EIC EXTINT14 External Interrupt 14 0x1B EIC EXTINT15 External Interrupt 15 0x1C Reserved 0x1D Reserved 0x1E DMAC CH0 Channel 0 0x1F DMAC CH1 Channel 1 0x20 DMAC CH2 Channel 2 0x21 DMAC CH3 Channel 3 0x22 TCC0 OVF Overflow 0x23 TCC0 TRG Trig 0x24 TCC0 CNT Counter 0x25 TCC0_MCX0 Match/Capture 0 0x26 TCC0_MCX1 Match/Capture 1 0x27 TCC0_MCX2 Match/Capture 2 0x28 TCC0_MCX3 Match/Capture 3 0x29 TCC1 OVF Overflow 0x2A TCC1 TRG Trig 0x2B TCC1 CNT Counter 0x2C TCC1_MCX0 Match/Capture 0 0x2D TCC1_MCX1 Match/Capture 1 0x2E TCC2 OVF Overflow 0x2F TCC2 TRG Trig 0x30 TCC2 CNT Counter 0x31 TCC2_MCX0 Match/Capture 0 0x32 TCC2_MCX1 Match/Capture 1 0x33 TC3 OVF Overflow/Underflow 0x34 TC3 MC0 Match/Capture 0 0x35 TC3 MC1 Match/Capture 1 0x36 TC4 OVF Overflow/Underflow SAM D21/DA1 Family EVSYS – Event System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 398

Value Event Generator Description 0x37 TC4 MC0 Match/Capture 0 0x38 TC4 MC1 Match/Capture 1 0x39 TC5 OVF Overflow/Underflow 0x3A TC5 MC0 Match/Capture 0 0x3B TC5 MC1 Match/Capture 1 0x3C TC6 OVF Overflow/Underflow 0x3D TC6 MC0 Match/Capture 0 0x3E TC6 MC1 Match/Capture 1 0x3F TC7 OVF Overflow/Underflow 0x40 TC7 MC0 Match/Capture 0 0x41 TC7 MC1 Match/Capture 1 0x42 ADC RESRDY Result Ready 0x43 ADC WINMON Window Monitor 0x44 AC COMP0 Comparator 0 0x45 AC COMP1 Comparator 1 0x46 AC WIN0 Window 0 0x47 DAC EMPTY Data Buffer Empty 0x48 PTC EOC End of Conversion 0x49 PTC WCOMP Window Comparator 0x4A AC COMP2 Comparator 2 0x4B AC COMP3 Comparator 3 0x4C AC WIN1 Window 1 0x4D TCC3 OVF Overflow 0x4E TCC3 TRG Trigger 0x4F TCC3 CNT Counter 0x50 TCC3_MCX0 Match/Capture 0 0x51 TCC3_MCX1 Match/Capture 1 0x52 TCC3_MCX2 Match/Capture 2 0x53 TCC3_MCX3 Match/Capture 3 0x54-0x7F Reserved Reserved Bit 8 – SWEVT Software Event This bit is used to insert a software event on the channel selected by the CHANNEL.CHANNEL bit group. This bit has the same behavior similar to an event. This bit must be written together with CHANNEL.CHANNEL using a 16-bit write. Writing a zero to this bit has no effect. Writing a one to this bit will trigger a software event for the corresponding channel. This bit will always return zero when read. Bits 3:0 – CHANNEL[3:0] Channel Selection These bits are used to select the channel to be set up or read from. SAM D21/DA1 Family EVSYS – Event System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 399

24.8.3 User Multiplexer

Name: USER Offset: 0x08 Reset: 0x0000 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 CHANNEL[4:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 USER[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 12:8 – CHANNEL[4:0] Channel Event Selection These bits are used to select the channel to connect to the event user. Note that to select channel n, the value (n+1) must be written to the USER.CHANNEL bit group. CHANNEL[4:0] Channel Number 0x0 No Channel Output Selected 0x1-0xC Channel n-1 selected 0xD-0xFF Reserved Bits 7:0 – USER[7:0] User Multiplexer Selection These bits select the event user to be configured with a channel, or the event user to read the channel value from. Table 24-2. User Multiplexer Selection USER[7:0] User Multiplexer Description Path Type 0x00 DMAC CH0 Channel 0 Resynchronized path only 0x01 DMAC CH1 Channel 1 Resynchronized path only 0x02 DMAC CH2 Channel 2 Resynchronized path only 0x03 DMAC CH3 Channel 3 Resynchronized path only 0x04 TCC0 EV0 Asynchronous, synchronous and resynchronized paths 0x05 TCC0 EV1 Asynchronous, synchronous and resynchronized paths 0x06 TCC0 MC0 Match/Capture 0 Asynchronous, synchronous and resynchronized paths 0x07 TCC0 MC1 Match/Capture 1 Asynchronous, synchronous and resynchronized paths 0x08 TCC0 MC2 Match/Capture 2 Asynchronous, synchronous and resynchronized paths 0x09 TCC0 MC3 Match/Capture 3 Asynchronous, synchronous and resynchronized paths 0x0A TCC1 EV0 Asynchronous, synchronous and resynchronized paths 0x0B TCC1 EV1 Asynchronous, synchronous and resynchronized paths 0x0C TCC1 MC0 Match/Capture 0 Asynchronous, synchronous and resynchronized paths 0x0D TCC1 MC1 Match/Capture 1 Asynchronous, synchronous and resynchronized paths 0x0E TCC2 EV0 Asynchronous, synchronous and resynchronized paths 0x0F TCC2 EV1 Asynchronous, synchronous and resynchronized paths 0x10 TCC2 MC0 Match/Capture 0 Asynchronous, synchronous and resynchronized paths 0x11 TCC2 MC1 Match/Capture 1 Asynchronous, synchronous and resynchronized paths 0x12 TC3 Asynchronous, synchronous and resynchronized paths 0x13 TC4 Asynchronous, synchronous and resynchronized paths 0x14 TC5 Asynchronous, synchronous and resynchronized paths 0x15 TC6 Asynchronous, synchronous and resynchronized paths 0x16 TC7 Asynchronous, synchronous and resynchronized paths 0x17 ADC START ADC start conversion Asynchronous path only SAM D21/DA1 Family EVSYS – Event System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 400

USER[7:0] User Multiplexer Description Path Type 0x18 ADC SYNC Flush ADC Asynchronous path only 0x19 AC COMP0 Start comparator 0 Asynchronous path only 0x1A AC COMP1 Start comparator 1 Asynchronous path only 0x1B DAC START DAC start conversion Asynchronous path only 0x1C PTC STCONV PTC start conversion Asynchronous path only 0x1D AC COMP2 Start Comparator 2 Asynchronous path only 0x1E AC COMP3 Start Comparator 3 Asynchronous path only 0x1F TCC3 EV0 Match/Capture 1 Asynchronous, synchronous and resynchronized paths 0x20 TCC3 EV1 Match/Capture 2 Asynchronous, synchronous and resynchronized paths 0x21 TCC3 MC0 Match/Capture 0 Asynchronous, synchronous and resynchronized paths 0x22 TCC3 MC1 Match/Capture 1 Asynchronous, synchronous and resynchronized paths 0x23 TCC3 MC2 Match/Capture 2 Asynchronous, synchronous and resynchronized paths 0x24 TCC3 MC3 Match/Capture 3 Asynchronous, synchronous and resynchronized paths 0x25- 0x3F Reserved Reserved SAM D21/DA1 Family EVSYS – Event System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 401

24.8.4 Channel Status

Name: CHSTATUS Offset: 0x0C Reset: 0x000F00FF Property: - Bit 31 30 29 28 27 26 25 24 CHBUSY11 CHBUSY10 CHBUSY9 CHBUSY8 Access R R R R Reset 0 0 0 0 Bit 23 22 21 20 19 18 17 16 USRRDY11 USRRDY10 USRRDY9 USRRDY8 Access R R R R Reset 1 1 1 1 Bit 15 14 13 12 11 10 9 8 CHBUSY7 CHBUSY6 CHBUSY5 CHBUSY4 CHBUSY3 CHBUSY2 CHBUSY1 CHBUSY0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 USRRDY7 USRRDY6 USRRDY5 USRRDY4 USRRDY3 USRRDY2 USRRDY1 USRRDY0 Access R R R R R R R R Reset 1 1 1 1 1 1 1 1 Bits 24, 25, 26, 27 – CHBUSYn Channel n Busy This bit is cleared when channel n is idle This bit is set if an event on channel n has not been handled by all event users connected to channel n. Bits 16, 17, 18, 19 – USRRDYn Channel n User Ready This bit is cleared when at least one of the event users connected to the channel is not ready. This bit is set when all event users connected to channel n are ready to handle incoming events on channel n. Bits 8, 9, 10, 11, 12, 13, 14, 15 – CHBUSYn Channel n Busy This bit is cleared when channel n is idle This bit is set if an event on channel n has not been handled by all event users connected to channel n. Bits 0, 1, 2, 3, 4, 5, 6, 7 – USRRDYn Channel n User Ready This bit is cleared when at least one of the event users connected to the channel is not ready. This bit is set when all event users connected to channel n are ready to handle incoming events on channel n. SAM D21/DA1 Family EVSYS – Event System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 402

24.8.5 Interrupt Enable Clear

Name: INTENCLR Offset: 0x10 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 EVD11 EVD10 EVD9 EVD8 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OVR11 OVR10 OVR9 OVR8 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 24, 25, 26, 27 – EVDn Channel n Event Detection Interrupt Enable [n=11..8] Writing a zero to this bit has no effect. Writing a one to this bit will clear the Event Detected Channel n Interrupt Enable bit, which disables the Event Detected Channel n interrupt. Value Description 0 The Event Detected Channel n interrupt is disabled. 1 The Event Detected Channel n interrupt is enabled. Bits 16, 17, 18, 19 – OVRn Channel n Overrun Interrupt Enable [n=11..8] Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overrun Channel n Interrupt Enable bit, which disables the Overrun Channel n interrupt. Value Description 0 The Overrun Channel n interrupt is disabled. 1 The Overrun Channel n interrupt is enabled. Bits 8, 9, 10, 11, 12, 13, 14, 15 – EVDn Channel n Event Detection Interrupt Enable [n=7..0] Writing a zero to this bit has no effect. Writing a one to this bit will clear the Event Detected Channel n Interrupt Enable bit, which disables the Event Detected Channel n interrupt. Value Description 0 The Event Detected Channel n interrupt is disabled. 1 The Event Detected Channel n interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – OVRn Channel n Overrun Interrupt Enable [n=7..0] Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overrun Channel n Interrupt Enable bit, which disables the Overrun Channel n interrupt. SAM D21/DA1 Family EVSYS – Event System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 403

0 The Overrun Channel n interrupt is disabled. 1 The Overrun Channel n interrupt is enabled. SAM D21/DA1 Family EVSYS – Event System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 404

24.8.6 Interrupt Enable Set

Name: INTENSET Offset: 0x14 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 EVD11 EVD10 EVD9 EVD8 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OVR11 OVR10 OVR9 OVR8 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 24, 25, 26, 27 – EVDn Channel n Event Detection Interrupt Enable [n=11..8] Writing a zero to this bit has no effect. Writing a one to this bit will set the Event Detected Channel n Interrupt Enable bit, which enables the Event Detected Channel n interrupt. Value Description 0 The Event Detected Channel n interrupt is disabled. 1 The Event Detected Channel n interrupt is enabled. Bits 16, 17, 18, 19 – OVRn Channel n Overrun Interrupt Enable [n=11..8] Writing a zero to this bit has no effect. Writing a one to this bit will set the Overrun Channel n Interrupt Enable bit, which enables the Overrun Channel n interrupt. Value Description 0 The Overrun Channel n interrupt is disabled. 1 The Overrun Channel n interrupt is enabled. Bits 8, 9, 10, 11, 12, 13, 14, 15 – EVDn Channel n Event Detection Interrupt Enable [n=7..0] Writing a zero to this bit has no effect. Writing a one to this bit will set the Event Detected Channel n Interrupt Enable bit, which enables the Event Detected Channel n interrupt. Value Description 0 The Event Detected Channel n interrupt is disabled. 1 The Event Detected Channel n interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – OVRn Channel n Overrun Interrupt Enable [n=7..0] Writing a zero to this bit has no effect. Writing a one to this bit will set the Overrun Channel n Interrupt Enable bit, which enables the Overrun Channel n interrupt. SAM D21/DA1 Family EVSYS – Event System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 405

24.8.7 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x18 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 EVD11 EVD10 EVD9 EVD8 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OVR11 OVR10 OVR9 OVR8 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 24, 25, 26, 27 – EVDn Channel n Event Detection [n=11..8] This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and an interrupt request will be generated if INTENCLR/SET.EVDn is one. When the event channel path is asynchronous, the EVDn Interrupt flag will not be set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Event Detected Channel n interrupt flag. Bits 16, 17, 18, 19 – OVRn Channel n Overrun [n=11..8] This flag is set on the next CLK_EVSYS cycle after an Overrun Channel condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVRn is one. When the event channel path is asynchronous, the OVRn Interrupt flag will not be set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overrun Channel n Interrupt flag. Bits 8, 9, 10, 11, 12, 13, 14, 15 – EVDn Channel n Event Detection [n=7..0] This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and an interrupt request will be generated if INTENCLR/SET.EVDn is one. When the event channel path is asynchronous, the EVDn Interrupt flag will not be set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Event Detected Channel n interrupt flag. Bits 0, 1, 2, 3, 4, 5, 6, 7 – OVRn Channel n Overrun [n=7..0] This flag is set on the next CLK_EVSYS cycle after an Overrun Channel condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVRn is one. When the event channel path is asynchronous, the OVRn Interrupt flag will not be set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overrun Channel n Interrupt flag. SAM D21/DA1 Family EVSYS – Event System © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 407

SERCOM – Serial Communication Interface

25.1 Overview

There are up to six instances of the serial communication interface (SERCOM) peripheral. A SERCOM can be configured to support a number of modes: I2C, SPI, and USART. When an instance of SERCOM is configured and enabled, all of the resources of that SERCOM instance will be dedicated to the selected mode. The SERCOM serial engine consists of a transmitter and receiver, baud-rate generator and address matching functionality. It can use the internal generic clock or an external clock. Using an external clock allows the SERCOM to be operated in all Sleep modes. Related Links 26. SERCOM USART 27. SERCOM SPI – SERCOM Serial Peripheral Interface 28. SERCOM I2C – Inter-Integrated Circuit

25.2 Features

Interface for Configuring into one of the following (selected by CTRLA.MODE[2:0]): – Inter-Integrated Circuit (I 2C) two-wire serial interface – System Management Bus (SMBus ™) compatible – Serial Peripheral Interface (SPI) – Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
Single Transmit Buffer and Double Receive Buffer
Baud-rate Generator
Address Match/mask Logic
Operational in all Sleep modes with an External Clock Source
Can be used with DMA See the Related Links for full feature lists of the interface configurations. Related Links 26. SERCOM USART 27. SERCOM SPI – SERCOM Serial Peripheral Interface 28. SERCOM I2C – Inter-Integrated Circuit SAM D21/DA1 Family SERCOM – Serial Communication Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 408

25.3 Block Diagram

Figure 25-1. SERCOM Block Diagram TX/RX DATACONTROL/STATUS Mode n SERCOM BAUD/ADDR Transmitter Register Interface Serial Engine Receiver Mode 0 Mode 1 Baud Rate Generator Address Match Mode Specific PAD[3:0]

25.4 Signal Description

See the respective SERCOM mode chapters for details. Related Links 26. SERCOM USART 27. SERCOM SPI – SERCOM Serial Peripheral Interface 28. SERCOM I2C – Inter-Integrated Circuit

25.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

25.5.1 I/O Lines

Using the SERCOM I/O lines requires the I/O pins to be configured using port configuration (PORT). The SERCOM has four internal pads, PAD[3:0], and the signals from I2C, SPI and USART are routed through these SERCOM pads via a multiplexer. The configuration of the multiplexer is available from the different SERCOM modes. Refer to the mode specific chapters for details. Related Links 26. SERCOM USART 27. SERCOM SPI – SERCOM Serial Peripheral Interface 28. SERCOM I2C – Inter-Integrated Circuit 23. PORT - I/O Pin Controller

26.3 Block Diagram

25.5.2 Power Management

The SERCOM can operate in any Sleep mode provided the selected clock source is running. SERCOM interrupts can be configured to wake the device from Sleep modes. Related Links 16. PM – Power Manager SAM D21/DA1 Family SERCOM – Serial Communication Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 409

25.5.3 Clocks

The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Power Manager. Refer to Peripheral Clock Masking for details and default status of this clock. The SERCOM uses two generic clocks: GCLK_SERCOMx_CORE and GCLK_SERCOMx_SLOW. The core clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while working as a host. The slow clock (GCLK_SERCOMx_SLOW) is only required for certain functions. See specific mode chapters for details. These clocks must be configured and enabled in the Generic Clock Controller (GCLK) before using the SERCOM. The generic clocks are asynchronous to the user interface clock (CLK_SERCOMx_APB). Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains. Refer to 25.6.8 Synchronization for details. Related Links 15. GCLK - Generic Clock Controller

25.5.4 DMA

The DMA request lines are connected to the DMA Controller (DMAC). The DMAC must be configured before the SERCOM DMA requests are used. Related Links 20. DMAC – Direct Memory Access Controller

25.5.5 Interrupts

The interrupt request line is connected to the Interrupt Controller (NVIC). The NVIC must be configured before the SERCOM interrupts are used. Related Links

25.5.6 Events

Not applicable.

25.5.7 Debug Operation

When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result during debugging. This peripheral can be forced to halt operation during debugging - refer to the Debug Control (DBGCTRL) register for details.

25.5.8 Register Access Protection

All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Interrupt Flag Clear and Status register (INTFLAG)
Status register (STATUS)
Data register (DATA)
Address register (ADDR) Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger. Related Links

25.5.9 Analog Connections

25.6 Functional Description

25.6.1 Principle of Operation

The basic structure of the SERCOM serial engine is shown in Figure 25-2. Labels in capital letters are synchronous to the system clock and accessible by the CPU; labels in lowercase letters can be configured to run on the GCLK_SERCOMx_CORE clock or an external clock. Figure 25-2. SERCOM Serial Engine Transmitter Baud Rate Generator Equal Selectable Internal Clk (GCLK) Ext Clk Receiver Address Match Baud Rate Generator TX Shift Register RX Shift Register RX BufferStatus BAUD TX DATA ADDR/ADDRMASK RX DATASTATUS 1/- /2- /16 The transmitter consists of a single write buffer and a shift register. The receiver consists of a one-level (I2C), two-level (USART, SPI) receive buffer and a shift register. The baud-rate generator is capable of running on the GCLK_SERCOMx_CORE clock or an external clock. Address matching logic is included for SPI and I2C operation.

25.6.2 Basic Operation

25.6.2.1 Initialization

The SERCOM must be configured to the desired mode by writing the Operating Mode bits in the Control A register (CTRLA.MODE) as shown in the table below. Table 25-1. SERCOM Modes CTRLA.MODE Description 0x0 USART with external clock 0x1 USART with internal clock 0x2 SPI in client operation 0x3 SPI in host operation 0x4 I2C client operation 0x5 I2C host operation 0x6-0x7 Reserved For further initialization information, see the respective SERCOM mode chapters: SAM D21/DA1 Family SERCOM – Serial Communication Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 411

SERCOM USART 27. SERCOM SPI – SERCOM Serial Peripheral Interface 28. SERCOM I2C – Inter-Integrated Circuit

25.6.2.2 Enabling, Disabling, and Resetting

This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and disabled by writing '0' to it. Writing ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of this peripheral to their initial states, except the DBGCTRL register, and the peripheral is disabled. Refer to the CTRLA register description for details.

25.6.2.3 Clock Generation – Baud-Rate Generator

The baud-rate generator, as shown in Figure 25-3, generates internal clocks for asynchronous and synchronous communication. The output frequency (fBAUD) is determined by the Baud register (BAUD) setting and the baud reference frequency (fref). The baud reference clock is the serial engine clock, and it can be internal or external. For asynchronous communication, the /16 (divide-by-16) output is used when transmitting, whereas the /1 (divide- by-1) output is used while receiving. For synchronous communication, the /2 (divide-by-2) output is used. This functionality is automatically configured, depending on the selected operating mode. Figure 25-3. Baud Rate Generator Base Period Selectable Internal Clk (GCLK) Ext Clk CTRLA.MODE[0] fref Clock Recovery Tx Clk Rx Clk CTRLA.MODE /2 /8 /1 /2 /16 Baud Rate Generator Table 25-2 contains equations for the baud rate (in bits per second) and the BAUD register value for each operating mode. For asynchronous operation, there is one mode: arithmetic mode, the BAUD register value is 16 bits (0 to 65,535). For synchronous operation, the BAUD register value is 8 bits (0 to 255). Table 25-2. Baud Rate Equations Operating Mode Condition Baud Rate (Bits Per Second) BAUD Register Value Calculation Asynchronous Arithmetic f B AU D ≤ f r e f 16 f B AU D = f r e f 16 1 − B AU D

65536 B AU D = 65536 ⋅ 1 − S ⋅ f B AU D

Fractional f B AU D ≤ f r e f S f B AU D = f r e f S ⋅ B AU D + FP B A U D = f r e f S ⋅ f B AU D − F P SAM D21/DA1 Family SERCOM – Serial Communication Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 412

Operating Mode Condition Baud Rate (Bits Per Second) BAUD Register Value Calculation Synchronous f B AU D ≤ f r e f 2 f B AU D = f re f 2 ⋅ B AU D + 1 B AU D = f r e f 2 ⋅ f B AU D − 1 S - Number of samples per bit, which can be 16, 8, or 3. The Asynchronous Fractional option is used for auto-baud detection. The baud rate error is represented by the following formula: Err or = 1 − Exp e ct ed B audRat e Act u alB audRat e

25.6.2.3.1 Asynchronous Arithmetic Mode BAUD Value Selection

The formula given for fBAUD calculates the average frequency over 65536 fref cycles. Although the BAUD register can be set to any value between 0 and 65536, the actual average frequency of fBAUD over a single frame is more granular. The BAUD register values that will affect the average frequency over a single frame lead to an integer increase in the cycles per frame (CPF) C PF = f r e f f B AU D D + S where

D represent the data bits per frame
S represent the sum of start and first stop bits, if present. Table 25-3 shows the BAUD register value versus baud frequency fBAUD at a serial engine frequency of 48MHz. This assumes a D value of 8 bits and an S value of 2 bits (10 bits, including start and stop bits). Table 25-3. BAUD Register Value vs. Baud Frequency BAUD Register Value Serial Engine CPF fBAUD at 48MHz Serial Engine Frequency (fREF) 0 – 406 160 3MHz 407 – 808 161 2.981MHz 809 – 1205 162 2.963MHz 65206 31775 15.11kHz 65207 31871 15.06kHz 65208 31969 15.01kHz

25.6.3 Additional Features

25.6.3.1 Address Match and Mask

The SERCOM address match and mask feature is capable of matching either one address, two unique addresses, or a range of addresses with a mask, based on the mode selected. The match uses seven or eight bits, depending on the mode.

25.6.3.1.1 Address With Mask

An address written to the Address bits in the Address register (ADDR.ADDR), and a mask written to the Address Mask bits in the Address register (ADDR.ADDRMASK) will yield an address match. All bits that are masked are not included in the match. Note that writing the ADDR.ADDRMASK to 'all zeros' will match a single unique address, while writing ADDR.ADDRMASK to 'all ones' will result in all addresses being accepted. SAM D21/DA1 Family SERCOM – Serial Communication Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 413

Figure 25-4. Address With Mask rx shift register ADDRMASK ADDR == Match

25.6.3.1.2 Two Unique Addresses

The two addresses written to ADDR and ADDRMASK will cause a match. Figure 25-5. Two Unique Addresses ADDRMASK rx shift register ADDR Match

25.6.3.1.3 Address Range

The range of addresses between and including ADDR.ADDR and ADDR.ADDRMASK will cause a match. ADDR.ADDR and ADDR.ADDRMASK can be set to any two addresses, with ADDR.ADDR acting as the upper limit and ADDR.ADDRMASK acting as the lower limit. Figure 25-6. Address Range ADDRMASK rx shift register ADDR == Match

25.6.4 DMA Operation

The available DMA interrupts and their depend on the operation mode of the SERCOM peripheral. Refer to the Functional Description sections of the respective SERCOM mode. Related Links 26. SERCOM USART 27. SERCOM SPI – SERCOM Serial Peripheral Interface 28. SERCOM I2C – Inter-Integrated Circuit

25.6.5 Interrupts

Interrupt sources are mode-specific. See the respective SERCOM mode chapters for details. Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the interrupt condition is met. Each interrupt can be individually enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the SERCOM is reset. For details on clearing interrupt flags, refer to the INTFLAG register description. SAM D21/DA1 Family SERCOM – Serial Communication Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 414

The value of INTFLAG indicates which interrupt condition occurred. The user must read the INTFLAG register to determine which interrupt condition is present. Note: Interrupts must be globally enabled for interrupt requests. Related Links

25.6.6 Events

Not applicable.

25.6.7 Sleep Mode Operation

The peripheral can operate in any sleep mode where the selected serial clock is running. This clock can be external or generated by the internal baud-rate generator. The SERCOM interrupts can be used to wake up the device from sleep modes. Refer to the different SERCOM mode chapters for details.

25.6.8 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Required read-synchronization is denoted by the "Read-Synchronized" property in the register description. Related Links SERCOM – Serial Communication Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 415

SERCOM USART

26.1 Overview

The Universal Synchronous and Asynchronous Receiver and Transmitter (USART) is one of the available modes in the Serial Communication Interface (SERCOM). The USART uses the SERCOM transmitter and receiver, see 26.3 Block Diagram. Labels in uppercase letters are synchronous to CLK_SERCOMx_APB and accessible for CPU. Labels in lowercase letters can be programmed to run on the internal generic clock or an external clock. The transmitter consists of a single write buffer, a shift register, and control logic for different frame formats. The write buffer support data transmission without any delay between frames. The receiver consists of a two-level receive buffer and a shift register. Status information of the received data is available for error checking. Data and clock recovery units ensure robust synchronization and noise filtering during asynchronous data reception. Related Links 25. SERCOM – Serial Communication Interface

26.2 USART Features

Full-duplex Operation
Asynchronous (with Clock Reconstruction) or Synchronous Operation
Internal or External Clock source for Asynchronous and Synchronous Operation
Baud-rate Generator
Supports Serial Frames with 5, 6, 7, 8 or 9 Data bits and 1 or 2 Stop bits
Odd or Even Parity Generation and Parity Check
Selectable LSB- or MSB-first Data Transfer
Buffer Overflow and Frame Error Detection
Noise Filtering, Including False Start bit Detection and Digital Low-pass Filter
Collision Detection
Can Operate in all Sleep modes
Operation at Speeds up to Half the System Clock for Internally Generated Clocks
Operation at Speeds up to the System Clock for Externally Generated Clocks
RTS and CTS Flow Control
IrDA Modulation and Demodulation up to 115.2kbps
Start-of-frame detection
Can work with DMA Related Links

Figure 26-1. USART Block Diagram GCLK (internal) XCK BAUD Baud Rate Generator TX DATA TX Shift Register RX Shift Register STATUS Status RX DATA RX Buffer TxD RxD CTRLA.MODE /1 - /2 - /16 CTRLA.MODE

26.4 Signal Description

Table 26-1. SERCOM USART Signals Signal Name Type Description PAD[3:0] Digital I/O General SERCOM pins One signal can be mapped to one of several pins. Related Links 7. I/O Multiplexing and Considerations

26.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

26.5.1 I/O Lines

Using the USART’s I/O lines requires the I/O pins to be configured using the I/O Pin Controller (PORT). When the SERCOM is used in USART mode, the SERCOM controls the direction and value of the I/O pins according to the table below. PORT Control bit PINCFGn.DRVSTR is still effective for the SERCOM output pins. PORT Control bit PINCFGn.PULLEN is still effective on the SERCOM input pins, but is limited to the enabling/disabling of a pull down only (it is not possible to enable/disable a pull up). If the receiver or transmitter is disabled, these pins can be used for other purposes. The combined configuration of PORT and the Transmit Data Pinout and Receive Data Pinout bit fields in the CTRLA register (CTRLA.TXPO and CTRLA.RXPO, respectively) will define the physical position of the USART signals in the following table. Table 26-2. USART Pin Configuration Pin Pin Configuration TxD Output RxD Input SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 417

PORT - I/O Pin Controller

26.5.2 Power Management

This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake up the device from sleep modes. Related Links 16. PM – Power Manager

26.5.3 Clocks

The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Power Manager. Refer to Peripheral Clock Masking for details and default status of this clock. A generic clock (GCLK_SERCOMx_CORE) is required to clock the SERCOMx_CORE. This clock must be configured and enabled in the Generic Clock Controller before using the SERCOMx_CORE. Refer to GCLK - Generic Clock Controller for details. This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Therefore, writing to certain registers will require synchronization to the clock domains. Refer to Synchronization for further details. Related Links

26.6.6 Synchronization

GCLK - Generic Clock Controller

26.5.4 DMA

The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with this peripheral the DMAC must be configured first. Refer to DMAC – Direct Memory Access Controller for details. Related Links 20. DMAC – Direct Memory Access Controller

26.5.5 Interrupts

The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral, the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt Controller for details. Related Links

26.5.6 Events

Not applicable.

26.5.7 Debug Operation

26.8.11 DBGCTRL

26.5.8 Register Access Protection

Registers with write-access can be write-protected optionally by the peripheral access controller (PAC). SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 418

PAC Write-Protection is not available for the following registers:

Interrupt Flag Clear and Status register (INTFLAG)
Status register (STATUS)
Data register (DATA) Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger. Related Links

26.5.9 Analog Connections

Not applicable.

26.6 Functional Description

26.6.1 Principle of Operation

The USART uses the following lines for data transfer:

RxD for receiving
TxD for transmitting
XCK for the transmission clock in synchronous operation USART data transfer is frame based. A serial frame consists of:
1 start bit
From 5 to 9 data bits (MSB or LSB first)
No, even or odd parity bit
1 or 2 stop bits A frame starts with the start bit followed by one character of data bits. If enabled, the parity bit is inserted after the data bits and before the first stop bit. After the stop bit(s) of a frame, either the next frame can follow immediately, or the communication line can return to the idle (high) state. The figure below illustrates the possible frame formats. Brackets denote optional bits. Figure 26-2. Frame Formats Frame (IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] [St/IDL] St Start bit. Signal is always low. n, [n] Data bits. 0 to [5..9] [P] Parity bit. Either odd or even. Sp, [Sp] Stop bit. Signal is always high. IDLE No frame is transferred on the communication line. Signal is always high in this state. SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 419

26.6.2 Basic Operation

26.6.2.1 Initialization

The following registers are enable-protected, meaning they can only be written when the USART is disabled (CTRL.ENABLE=0):

Control A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits.
Control B register (CTRLB), except the Receiver Enable (RXEN) and Transmitter Enable (TXEN) bits.
Baud register (BAUD) When the USART is enabled or is being enabled (CTRLA.ENABLE=1), any writing attempt to these registers will be discarded. If the peripheral is being disabled, writing to these registers will be executed after disabling is completed. Enable-protection is denoted by the "Enable-Protection" property in the register description. Before the USART is enabled, it must be configured by these steps: 1. Select either external (0x0) or internal clock (0x1) by writing the Operating Mode value in the CTRLA register (CTRLA.MODE). 2. Select either asynchronous (0) or or synchronous (1) communication mode by writing the Communication Mode bit in the CTRLA register (CTRLA.CMODE). 3. Select pin for receive data by writing the Receive Data Pinout value in the CTRLA register (CTRLA.RXPO). 4. Select pads for the transmitter and external clock by writing the Transmit Data Pinout bit in the CTRLA register (CTRLA.TXPO). 5. Configure the Character Size field in the CTRLB register (CTRLB.CHSIZE) for character size. 6. Set the Data Order bit in the CTRLA register (CTRLA.DORD) to determine MSB- or LSB-first data transmission. 7. To use parity mode: 7.1. Enable parity mode by writing 0x1 to the Frame Format field in the CTRLA register (CTRLA.FORM). 7.2. Configure the Parity Mode bit in the CTRLB register (CTRLB.PMODE) for even or odd parity. 8. Configure the number of stop bits in the Stop Bit Mode bit in the CTRLB register (CTRLB.SBMODE). 9. When using an internal clock, write the Baud register (BAUD) to generate the desired baud rate. 10. Enable the transmitter and receiver by writing '1' to the Receiver Enable and Transmitter Enable bits in the CTRLB register (CTRLB.RXEN and CTRLB.TXEN).

26.6.2.2 Enabling, Disabling, and Resetting

26.6.2.3 Clock Generation and Selection

For both synchronous and asynchronous modes, the clock used for shifting and sampling data can be generated internally by the SERCOM baud-rate generator or supplied externally through the XCK line. The synchronous mode is selected by writing a '1' to the Communication Mode bit in the Control A register (CTRLA.CMODE), the asynchronous mode is selected by writing a zero to CTRLA.CMODE. The internal clock source is selected by writing 0x1 to the Operation Mode bit field in the Control A register (CTRLA.MODE), the external clock source is selected by writing 0x0 to CTRLA.MODE. The SERCOM baud-rate generator is configured as in the figure below. In asynchronous mode (CTRLA.CMODE=0), the 16-bit Baud register value is used. In synchronous mode (CTRLA.CMODE=1), the eight LSBs of the Baud register are used. Refer to Clock Generation – Baud-Rate Generator for details on configuring the baud rate. SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 420

Figure 26-3. Clock Generation XCK CTRLA.MODE[0] XCKInternal Clk (GCLK) Baud Rate Generator Base Period /2 /8 /2 /8/1 Tx Clk Rx Clk CTRLA.CMODE Related Links

26.6.2.3.1 Synchronous Clock Operation

In synchronous mode, the CTRLA.MODE bit field determines whether the transmission clock line (XCK) serves either as input or output. The dependency between clock edges, data sampling, and data change is the same for internal and external clocks. Data input on the RxD pin is sampled at the opposite XCK clock edge when data is driven on the TxD pin. The Clock Polarity bit in the Control A register (CTRLA.CPOL) selects which XCK clock edge is used for RxD sampling, and which is used for TxD change: When CTRLA.CPOL is '0', the data will be changed on the rising edge of XCK, and sampled on the falling edge of XCK. When CTRLA.CPOL is '1', the data will be changed on the falling edge of XCK, and sampled on the rising edge of XCK. Figure 26-4. Synchronous Mode XCK Timing XCK RxD / TxD CTRLA.CPOL=1 Change Sample XCK RxD / TxD CTRLA.CPOL=0 Change Sample When the clock is provided through XCK (CTRLA.MODE=0x0), the shift registers operate directly on the XCK clock. This means that XCK is not synchronized with the system clock and, therefore, can operate at frequencies up to the system frequency.

26.6.2.4 Data Register

The USART Transmit Data register (TxDATA) and USART Receive Data register (RxDATA) share the same I/O address, referred to as the Data register (DATA). Writing the DATA register will update the TxDATA register. Reading the DATA register will return the contents of the RxDATA register. SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 421

26.6.2.5 Data Transmission

Data transmission is initiated by writing the data to be sent into the DATA register. Then, the data in TxDATA will be moved to the shift register when the shift register is empty and ready to send a new frame. After the shift register is loaded with data, the data frame will be transmitted. When the entire data frame including stop bit(s) has been transmitted and no new data was written to DATA, the Transmit Complete interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set, and the optional interrupt will be generated. The Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) indicates that the register is empty and ready for new data. The DATA register should only be written to when INTFLAG.DRE is set.

26.6.2.5.1 Disabling the Transmitter

The transmitter is disabled by writing '0' to the Transmitter Enable bit in the CTRLB register (CTRLB.TXEN). Disabling the transmitter will complete only after any ongoing and pending transmissions are completed, i.e., there is no data in the transmit shift register and TxDATA to transmit.

26.6.2.6 Data Reception

The receiver accepts data when a valid Start bit is detected. Each bit following the Start bit will be sampled according to the baud rate or XCK clock, and shifted into the receive Shift register until the first Stop bit of a frame is received. The second Stop bit will be ignored by the receiver. When the first Stop bit is received and a complete serial frame is present in the Receive Shift register, the contents of the Shift register will be moved into the two-level receive buffer. Then, the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set, and the optional interrupt can be generated. The received data can be read from the DATA register when the Receive Complete Interrupt flag is set.

26.6.2.6.1 Disabling the Receiver

Writing '0' to the Receiver Enable bit in the CTRLB register (CTRLB.RXEN) will disable the receiver, flush the two-level receive buffer, and data from ongoing receptions will be lost.

26.6.2.6.2 Error Bits

The USART receiver has three error bits in the Status (STATUS) register: Frame Error (FERR), Buffer Overflow (BUFOVF), and Parity Error (PERR). Once an error happens, the corresponding error bit will be set until it is cleared by writing ‘1’ to it. These bits are also cleared automatically when the receiver is disabled. There are two methods for buffer overflow notification, selected by the Immediate Buffer Overflow Notification bit in the Control A register (CTRLA.IBON): When CTRLA.IBON=1, STATUS.BUFOVF is raised immediately upon buffer overflow. Software can then empty the receive FIFO by reading RxDATA, until the Receiver Complete Interrupt flag (INTFLAG.RXC) is cleared. When CTRLA.IBON=0, the Buffer Overflow condition travels with data through the receive FIFO. After the received data is read, STATUS.BUFOVF and INTFLAG.ERROR will be set along with INTFLAG.RXC.

26.6.2.6.3 Asynchronous Data Reception

The USART includes a clock recovery and data recovery unit for handling asynchronous data reception. The clock recovery logic can synchronize the incoming asynchronous serial frames at the RxD pin to the internally generated baud-rate clock. The data recovery logic samples and applies a low-pass filter to each incoming bit, thereby improving the noise immunity of the receiver.

26.6.2.6.4 Asynchronous Operational Range

The operational range of the asynchronous reception depends on the accuracy of the internal baud-rate clock, the rate of the incoming frames, and the frame size (in number of bits). In addition, the operational range of the receiver is depending on the difference between the received bit rate and the internally generated baud rate. If the baud rate of an external transmitter is too high or too low compared to the internally generated baud rate, the receiver will not be able to synchronize the frames to the start bit. There are two possible sources for a mismatch in baud rate: First, the reference clock will always have some minor instability. Second, the baud-rate generator cannot always do an exact division of the reference clock frequency to SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 422

get the baud rate desired. In this case, the BAUD register value should be set to give the lowest possible error. Refer to Clock Generation – Baud-Rate Generator for details. Recommended maximum receiver baud-rate errors for various character sizes are shown in the table below. Table 26-3. Asynchronous Receiver Error for 16-fold Oversampling D (Data bits+Parity) RSLOW [%] RFAST [%] Max. total error [%] Recommended max. Rx error [%] The following equations calculate the ratio of the incoming data rate and internal receiver baud rate: R SLOW = D + 1 S S − 1 + D ⋅ S + S F , R FAST = D + 2 S D + 1 S + S M

RSLOW is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate
RFAST is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate
D is the sum of character size and parity size (D = 5 to 10 bits)
S is the number of samples per bit (S = 16, 8 or 3)
SF is the first sample number used for majority voting (SF = 7, 3, or 2) when CTRLA.SAMPA=0.
SM is the middle sample number used for majority voting (SM = 8, 4, or 2) when CTRLA.SAMPA=0. The recommended maximum Rx Error assumes that the receiver and transmitter equally divide the maximum total error. Its connection to the SERCOM Receiver error acceptance is depicted in this figure: Figure 26-5. USART Rx Error Calculation + + Error Max (%) Error Min (%) Baud Rate SERCOM Receiver error acceptance from RSLOW and RFAST formulas Baud Generator offset error depends on BAUD register value Clock source error Recommended max. Rx Error (%) The recommendation values in the table above accommodate errors of the clock source and the baud generator. The following figure gives an example for a baud rate of 3Mbps: SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 423

Figure 26-6. USART Rx Error Calculation Example + + Error Max 3.3% Error Min -4.35% Baud Rate 3Mbps SERCOM Receiver error acceptance sampling = x16 data bits = 10 parity = 0 start bit = stop bit = 1 No baud generator offset error Fbaud(3Mbps) = 48MHz *1(BAUD=0) /16 DFLL source at 3MHz +/-0.3% Recommended max. Rx Error +/-1.5% (example) Error Max 3.3% Error Min -4.35% Error Max 3.0% Error Min -4.05% Transmitter Error* Accepted Receiver Error security margin *Transmitter Error depends on the external transmitter used in the application. It is advised that it is within the Recommended max. Rx Error (+/-1.5% in this example). Larger Transmitter Errors are acceptable but must lie within the Accepted Receiver Error. Related Links

26.6.3 Additional Features

26.6.3.1 Parity

Even or odd parity can be selected for error checking by writing 0x1 to the Frame Format bit field in the Control A register (CTRLA.FORM). If even parity is selected (CTRLB.PMODE=0), the parity bit of an outgoing frame is '1' if the data contains an odd number of bits that are '1', making the total number of '1' even. If odd parity is selected (CTRLB.PMODE=1), the parity bit of an outgoing frame is '1' if the data contains an even number of bits that are '0', making the total number of '1' odd. When parity checking is enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit of the corresponding frame. If a parity error is detected, the Parity Error bit in the Status register (STATUS.PERR) is set.

26.6.3.2 Hardware Handshaking

The USART features an out-of-band hardware handshaking flow control mechanism, implemented by connecting the RTS and CTS pins with the remote device, as shown in the figure below. Figure 26-7. Connection with a Remote Device for Hardware Handshaking RXD CTS RTS USART TXD RTS CTS Remote Device TXD RXD Hardware handshaking is only available in the following configuration:

USART with internal clock (CTRLA.MODE=1),
Asynchronous mode (CTRLA.CMODE=0),
and Flow control pinout (CTRLA.TXPO=2). When the receiver is disabled or the receive FIFO is full, the receiver will drive the RTS pin high. This notifies the remote device to stop transfer after the ongoing transmission. Enabling and disabling the receiver by writing to CTRLB.RXEN will set/clear the RTS pin after a synchronization delay. When the receive FIFO goes full, RTS will be set immediately and the frame being received will be stored in the shift register until the receive FIFO is no longer full. SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 424

Figure 26-8. Receiver Behavior when Operating with Hardware Handshaking RTS Rx FIFO Full RXD RXEN The current CTS Status is in the STATUS register (STATUS.CTS). Character transmission will start only if STATUS.CTS=0. When CTS is set, the transmitter will complete the ongoing transmission and stop transmitting. Figure 26-9. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD

26.6.3.3 IrDA Modulation and Demodulation

Transmission and reception can be encoded IrDA compliant up to 115.2 kb/s. IrDA modulation and demodulation work in the following configuration:

IrDA encoding enabled (CTRLB.ENC=1),
Asynchronous mode (CTRLA.CMODE=0),
and 16x sample rate (CTRLA.SAMPR[0]=0). During transmission, each low bit is transmitted as a high pulse. The pulse width is 3/16 of the baud rate period, as illustrated in the figure below. Figure 26-10. IrDA Transmit Encoding IrDA encoded TXD TXD 1 baud clock 3/16 baud clock The reception decoder has two main functions. The first is to synchronize the incoming data to the IrDA baud rate counter. Synchronization is performed at the start of each zero pulse. The second main function is to decode incoming Rx data. If a pulse width meets the minimum length set by configuration (RXPL.RXPL), it is accepted. When the baud rate counter reaches its middle value (1/2 bit length), it is transferred to the receiver. Note: Note that the polarity of the transmitter and receiver are opposite: During transmission, a '0' bit is transmitted as a '1' pulse. During reception, an accepted '0' pulse is received as a '0' bit. Example: The figure below illustrates reception where RXPL.RXPL is set to 19. This indicates that the pulse width should be at least 20 SE clock cycles. When using BAUD=0xE666 or 160 SE cycles per bit, this corresponds to 2/16 baud clock as minimum pulse width required. In this case the first bit is accepted as a '0', the second bit is a '1', and the third bit is also a '1'. A low pulse is rejected since it does not meet the minimum requirement of 2/16 baud clock. Figure 26-11. IrDA Receive Decoding IrDA encoded RXD RXD Baud clock

20 SE clock cycles

26.6.3.4 Break Character Detection and Auto-Baud

Break character detection and auto-baud are available in this configuration:

Auto-baud frame format (CTRLA.FORM = 0x04 or 0x05),
Asynchronous mode (CTRLA.CMODE = 0),
and 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1). The USART uses a break detection threshold of greater than 11 nominal bit times at the configured baud rate. At any time, if more than 11 consecutive dominant bits are detected on the bus, the USART detects a Break Field. When a Break Field has been detected, the Receive Break interrupt flag (INTFLAG.RXBRK) is set and the USART expects the Sync Field character to be 0x55. This field is used to update the actual baud rate in order to stay synchronized. If the received Sync character is not 0x55, then the Inconsistent Sync Field error flag (STATUS.ISF) is set along with the Error interrupt flag (INTFLAG.ERROR), and the baud rate is unchanged. After a break field is detected and the start bit of the Sync Field is detected, a counter is started. The counter is then incremented for the next 8 bit times of the Sync Field. At the end of these 8 bit times, the counter is stopped. At this moment, the 13 most significant bits of the counter (value divided by 8) give the new clock divider (BAUD.BAUD), and the 3 least significant bits of this value (the remainder) give the new Fractional Part (BAUD.FP). When the Sync Field has been received, the clock divider (BAUD.BAUD) and the Fractional Part (BAUD.FP) are updated after a synchronization delay. After the Break and Sync Fields are received, multiple characters of data can be received.

26.6.3.5 Collision Detection

When the receiver and transmitter are connected either through pin configuration or externally, transmit collision can be detected after selecting the Collision Detection Enable bit in the CTRLB register (CTRLB.COLDEN=1). To detect collision, the receiver and transmitter must be enabled (CTRLB.RXEN=1 and CTRLB.TXEN=1). Collision detection is performed for each bit transmitted by comparing the received value with the transmit value, as shown in the figure below. While the transmitter is idle (no transmission in progress), characters can be received on RxD without triggering a collision. Figure 26-12. Collision Checking 8-bit character, single stop bit Collision checked TXD RXD The next figure shows the conditions for a collision detection. In this case, the start bit and the first data bit are received with the same value as transmitted. The second received data bit is found to be different than the transmitted bit at the detection point, which indicates a collision. Figure 26-13. Collision Detected Collision checked and ok TXD RXD Collision detected Tri-state TXEN When a collision is detected, the USART follows this sequence: 1. Abort the current transfer. 2. Flush the transmit buffer. 3. Disable transmitter (CTRLB.TXEN=0) – This is done after a synchronization delay. The CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB) will be set until this is complete. SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 426

– After disabling, the TxD pin will be tri-stated. 4. Set the Collision Detected bit (STATUS.COLL) along with the Error interrupt flag (INTFLAG.ERROR). 5. Set the Transmit Complete interrupt flag (INTFLAG.TXC), since the transmit buffer no longer contains data. After a collision, software must manually enable the transmitter again before continuing, after assuring that the CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB) is not set.

26.6.3.6 Loop-Back Mode

For loop-back mode, configure the Receive Data Pinout (CTRLA.RXPO) and Transmit Data Pinout (CTRLA.TXPO) to use the same data pins for transmit and receive. The loop-back is through the pad, so the signal is also available externally.

26.6.3.7 Start-of-Frame Detection

The USART start-of-frame detector can wake up the CPU when it detects a start bit. In standby sleep mode, the internal fast startup oscillator must be selected as the GCLK_SERCOMx_CORE source. When a 1-to-0 transition is detected on RxD, the 8MHz Internal Oscillator is powered up and the USART clock is enabled. After startup, the rest of the data frame can be received, provided that the baud rate is slow enough in relation to the fast startup internal oscillator start-up time. Refer to Electrical Characteristics for details. The start-up time of this oscillator varies with supply voltage and temperature. The USART start-of-frame detection works both in asynchronous and synchronous modes. It is enabled by writing ‘1’ to the Start of Frame Detection Enable bit in the Control B register (CTRLB.SFDE). If the Receive Start Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.RXS) is set, the Receive Start interrupt is generated immediately when a start is detected. When using start-of-frame detection without the Receive Start interrupt, start detection will force the 8MHz Internal Oscillator and USART clock active while the frame is being received. In this case, the CPU will not wake up until the Receive Complete interrupt is generated. Related Links 37. Electrical Characteristics at 85℃

26.6.3.8 Sample Adjustment

In asynchronous mode (CTRLA.CMODE=0), three samples in the middle are used to determine the value based on majority voting. The three samples used for voting can be selected using the Sample Adjustment bit field in Control A register (CTRLA.SAMPA). When CTRLA.SAMPA=0, samples 7-8-9 are used for 16x oversampling, and samples 3-4-5 are used for 8x oversampling.

26.6.4 DMA, Interrupts and Events

Table 26-4. Module Request for SERCOM USART Condition Request DMA Interrupt Event Data Register Empty (DRE) Yes (request cleared when data is written) Yes NA Receive Complete (RXC) Yes (request cleared when data is read) Yes Transmit Complete (TXC) NA Yes Receive Start (RXS) NA Yes Clear to Send Input Change (CTSIC) NA Yes Receive Break (RXBRK) NA Yes Error (ERROR) NA Yes SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 427

26.6.4.1 DMA Operation

The USART generates the following DMA requests:

Data received (RX): The request is set when data is available in the receive FIFO. The request is cleared when DATA is read.
Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is cleared when DATA is written.

26.6.4.2 Interrupts

The USART has the following interrupt sources. These are asynchronous interrupts, and can wake up the device from any sleep mode:

Data Register Empty (DRE)
Receive Complete (RXC)
Transmit Complete (TXC)
Receive Start (RXS)
Clear to Send Input Change (CTSIC)
Received Break (RXBRK)
Error (ERROR) Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the interrupt condition is met. Each interrupt can be individually enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and if the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the USART is reset. For details on clearing interrupt flags, refer to the INTFLAG register description. The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for interrupt requests. Refer to Nested Vector Interrupt Controller for details. Related Links

26.6.4.3 Events

Not applicable.

26.6.5 Sleep Mode Operation

The behavior in sleep mode is depending on the clock source and the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY):

Internal clocking, CTRLA.RUNSTDBY=1: GCLK_SERCOMx_CORE can be enabled in all sleep modes. Any interrupt can wake up the device.
External clocking, CTRLA.RUNSTDBY=1: The Receive Start and the Receive Complete interrupt(s) can wake up the device.
Internal clocking, CTRLA.RUNSTDBY=0: Internal clock will be disabled, after any ongoing transfer was completed. The Receive Start and the Receive Complete interrupt(s) can wake up the device.
External clocking, CTRLA.RUNSTDBY=0: External clock will be disconnected, after any ongoing transfer was completed. All reception will be dropped.

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written:

Software Reset bit in the CTRLA register (CTRLA.SWRST)
Enable bit in the CTRLA register (CTRLA.ENABLE)
Receiver Enable bit in the CTRLB register (CTRLB.RXEN) SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 428

Transmitter Enable bit in the Control B register (CTRLB.TXEN) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Related Links

26.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 RUNSTDBY MODE[2:0] ENABLE SWRST 15:8 SAMPR[2:0] IBON 23:16 SAMPA[1:0] RXPO[1:0] TXPO[1:0] 31:24 DORD CPOL CMODE FORM[3:0] 0x04 CTRLB 7:0 SBMODE CHSIZE[2:0] 15:8 PMODE ENC SFDE COLDEN 23:16 RXEN TXEN 31:24 0x08 ... 0x0B Reserved 0x0C BAUD 7:0 BAUD[7:0] 15:8 BAUD[15:8] 0x0E RXPL 7:0 RXPL[7:0] 0x0F ... 0x13 Reserved 0x14 INTENCLR 7:0 ERROR RXBRK CTSIC RXS RXC TXC DRE 0x15 Reserved 0x16 INTENSET 7:0 ERROR RXBRK CTSIC RXS RXC TXC DRE 0x17 Reserved 0x18 INTFLAG 7:0 ERROR RXBRK CTSIC RXS RXC TXC DRE 0x19 Reserved 0x1A STATUS 7:0 TXE COLL ISF CTS BUFOVF FERR PERR 15:8 0x1C SYNCBUSY 7:0 CTRLB ENABLE SWRST 15:8 23:16 31:24 0x20 ... 0x27 Reserved 0x28 DATA 7:0 DATA[7:0] 15:8 DATA[8] 0x2A ... 0x2F Reserved 0x30 DBGCTRL 7:0 DBGSTOP

26.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read- Synchronized" and/or "Write-Synchronized" property in each individual register description. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 430

26.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 DORD CPOL CMODE FORM[3:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SAMPA[1:0] RXPO[1:0] TXPO[1:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SAMPR[2:0] IBON Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RUNSTDBY MODE[2:0] ENABLE SWRST Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 30 – DORD Data Order This bit selects the data order when a character is shifted out from the Data register. This bit is not synchronized. Value Description 0 MSB is transmitted first. 1 LSB is transmitted first. Bit 29 – CPOL Clock Polarity This bit selects the relationship between data output change and data input sampling in synchronous mode. This bit is not synchronized. CPOL TxD Change RxD Sample 0x0 Rising XCK edge Falling XCK edge 0x1 Falling XCK edge Rising XCK edge Bit 28 – CMODE Communication Mode This bit selects asynchronous or synchronous communication. This bit is not synchronized. Value Description 0 Asynchronous communication. 1 Synchronous communication. Bits 27:24 – FORM[3:0] Frame Format These bits define the frame format. These bits are not synchronized. FORM[3:0] Description 0x0 USART frame 0x1 USART frame with parity SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 431

FORM[3:0] Description 0x2-0x3 Reserved 0x4 Auto-baud - break detection and auto-baud. 0x5 Auto-baud - break detection and auto-baud with parity 0x6-0xF Reserved Bits 23:22 – SAMPA[1:0] Sample Adjustment These bits define the sample adjustment. These bits are not synchronized. SAMPA[1:0] 16x Over-sampling (CTRLA.SAMPR=0 or 1) 8x Over-sampling (CTRLA.SAMPR=2 or 3) 0x0 7-8-9 3-4-5 0x1 9-10-11 4-5-6 0x2 11-12-13 5-6-7 0x3 13-14-15 6-7-8 Bits 21:20 – RXPO[1:0] Receive Data Pinout These bits define the receive data (RxD) pin configuration. These bits are not synchronized. RXPO[1:0] Name Description 0x0 PAD[0] SERCOM PAD[0] is used for data reception 0x1 PAD[1] SERCOM PAD[1] is used for data reception 0x2 PAD[2] SERCOM PAD[2] is used for data reception 0x3 PAD[3] SERCOM PAD[3] is used for data reception Bits 17:16 – TXPO[1:0] Transmit Data Pinout These bits define the transmit data (TxD) and XCK pin configurations. This bit is not synchronized. TXPO TxD Pin Location XCK Pin Location (When Applicable) RTS CTS 0x0 SERCOM PAD[0] SERCOM PAD[1] N/A N/A 0x1 SERCOM PAD[2] SERCOM PAD[3] N/A N/A 0x2 SERCOM PAD[0] N/A SERCOM PAD[2] SERCOM PAD[3] 0x3 Reserved Bits 15:13 – SAMPR[2:0] Sample Rate These bits select the sample rate. These bits are not synchronized. SAMPR[2:0] Description 0x0 16x over-sampling using arithmetic baud rate generation. 0x1 16x over-sampling using fractional baud rate generation. 0x2 8x over-sampling using arithmetic baud rate generation. 0x3 8x over-sampling using fractional baud rate generation. 0x4 3x over-sampling using arithmetic baud rate generation. 0x5-0x7 Reserved Bit 8 – IBON Immediate Buffer Overflow Notification This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is asserted when a buffer overflow occurs. Value Description 0 STATUS.BUFOVF is asserted when it occurs in the data stream. 1 STATUS.BUFOVF is asserted immediately upon buffer overflow. SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 432

Bit 7 – RUNSTDBY Run In Standby This bit defines the functionality in standby sleep mode. This bit is not synchronized. RUNSTDBY External Clock Internal Clock 0x0 External clock is disconnected when ongoing transfer is finished. All reception is dropped. Generic clock is disabled when ongoing transfer is finished. The device will not wake up on either Receive Start or Transfer Complete interrupt unless the appropriate ONDEMAND bits are set in the clocking chain. 0x1 Wake on Receive Start or Receive Complete interrupt. Generic clock is enabled in all sleep modes. Any interrupt can wake up the device. Bits 4:2 – MODE[2:0] Operating Mode These bits select the USART serial communication interface of the SERCOM. These bits are not synchronized. Value Description 0x0 USART with external clock 0x1 USART with internal clock Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the operation is complete. This bit is not enable-protected. Value Description 0 The peripheral is disabled or being disabled. 1 The peripheral is enabled or being enabled. Bit 0 – SWRST Software Reset Writing '0' to this bit has no effect. Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Value Description 0 There is no reset operation ongoing. 1 The reset operation is ongoing. SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 433

26.8.2 Control B

Name: CTRLB Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 RXEN TXEN Access R/W R/W Reset 0 0 Bit 15 14 13 12 11 10 9 8 PMODE ENC SFDE COLDEN Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SBMODE CHSIZE[2:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 17 – RXEN Receiver Enable Writing '0' to this bit will disable the USART receiver. Disabling the receiver will flush the receive buffer and clear the FERR, PERR and BUFOVF bits in the STATUS register. Writing '1' to CTRLB.RXEN when the USART is disabled will set CTRLB.RXEN immediately. When the USART is enabled, CTRLB.RXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until the receiver is enabled. When the receiver is enabled, CTRLB.RXEN will read back as '1'. Writing '1' to CTRLB.RXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain set until the receiver is enabled, and CTRLB.RXEN will read back as '1'. This bit is not enable-protected. Value Description 0 The receiver is disabled or being enabled. 1 The receiver is enabled or will be enabled when the USART is enabled. Bit 16 – TXEN Transmitter Enable Writing '0' to this bit will disable the USART transmitter. Disabling the transmitter will not become effective until ongoing and pending transmissions are completed. Writing '1' to CTRLB.TXEN when the USART is disabled will set CTRLB.TXEN immediately. When the USART is enabled, CTRLB.TXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until the transmitter is enabled. When the transmitter is enabled, CTRLB.TXEN will read back as '1'. Writing '1' to CTRLB.TXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain set until the transmitter is enabled, and CTRLB.TXEN will read back as '1'. This bit is not enable-protected. Value Description 0 The transmitter is disabled or being enabled. 1 The transmitter is enabled or will be enabled when the USART is enabled. Bit 13 – PMODE Parity Mode This bit selects the type of parity used when parity is enabled (CTRLA.FORM is '1'). The transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 434

for the incoming data and parity bit, compare it to the parity mode and, if a mismatch is detected, STATUS.PERR will be set. This bit is not synchronized. Value Description 0 Even parity. 1 Odd parity. Bit 10 – ENC Encoding Format This bit selects the data encoding format. This bit is not synchronized. Value Description 0 Data is not encoded. 1 Data is IrDA encoded. Bit 9 – SFDE Start of Frame Detection Enable This bit controls whether the start-of-frame detector will wake up the device when a start bit is detected on the RxD line. This bit is not synchronized. SFDE INTENSET.RXS INTENSET.RXC Description 0 X X Start-of-frame detection disabled. 1 0 0 Reserved 1 0 1 Start-of-frame detection enabled. RXC wakes up the device from all sleep modes. 1 1 0 Start-of-frame detection enabled. RXS wakes up the device from all sleep modes. 1 1 1 Start-of-frame detection enabled. Both RXC and RXS wake up the device from all sleep modes. Bit 8 – COLDEN Collision Detection Enable This bit enables collision detection. This bit is not synchronized. Value Description 0 Collision detection is not enabled. 1 Collision detection is enabled. Bit 6 – SBMODE Stop Bit Mode This bit selects the number of stop bits transmitted. This bit is not synchronized. Value Description 0 One stop bit. 1 Two stop bits. Bits 2:0 – CHSIZE[2:0] Character Size These bits select the number of bits in a character. These bits are not synchronized. CHSIZE[2:0] Description 0x0 8 bits 0x1 9 bits 0x2-0x4 Reserved 0x5 5 bits 0x6 6 bits 0x7 7 bits SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 435

26.8.3 Baud

Name: BAUD Offset: 0x0C Reset: 0x0000 Property: Enable-Protected, PAC Write-Protection Bit 15 14 13 12 11 10 9 8 BAUD[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BAUD[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – BAUD[15:0] Baud Value Arithmetic Baud Rate Generation (CTRLA.SAMPR[0]=0): These bits control the clock generation, as described in the SERCOM Baud Rate section. If Fractional Baud Rate Generation (CTRLA.SAMPR[0]=1) bit positions 15 to 13 are replaced by FP[2:0] Fractional Part:

Bits 15:13 - FP[2:0]: Fractional Part These bits control the clock generation, as described in the SERCOM Clock Generation – Baud-Rate Generator section.
Bits 12:0 - BAUD[12:0]: Baud Value These bits control the clock generation, as described in the SERCOM Clock Generation – Baud-Rate Generator section. Related Links

26.8.4 Receive Pulse Length Register

Name: RXPL Offset: 0x0E Reset: 0x00 Property: Enable-Protected, PAC Write-Protection Bit 7 6 5 4 3 2 1 0 RXPL[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – RXPL[7:0] Receive Pulse Length When the encoding format is set to IrDA (CTRLB.ENC=1), these bits control the minimum pulse length that is required for a pulse to be accepted by the IrDA receiver with regards to the serial engine clock period SE p er . PU L SE ≥ R XPL + 2 ⋅ S E p er SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 437

26.8.5 Interrupt Enable Clear

Name: INTENCLR Offset: 0x14 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 5 4 3 2 1 0 ERROR RXBRK CTSIC RXS RXC TXC DRE Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 7 – ERROR Error Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. Value Description 0 Error interrupt is disabled. 1 Error interrupt is enabled. Bit 5 – RXBRK Receive Break Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Receive Break Interrupt Enable bit, which disables the Receive Break interrupt. Value Description 0 Receive Break interrupt is disabled. 1 Receive Break interrupt is enabled. Bit 4 – CTSIC Clear to Send Input Change Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Clear To Send Input Change Interrupt Enable bit, which disables the Clear To Send Input Change interrupt. Value Description 0 Clear To Send Input Change interrupt is disabled. 1 Clear To Send Input Change interrupt is enabled. Bit 3 – RXS Receive Start Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Receive Start Interrupt Enable bit, which disables the Receive Start interrupt. Value Description 0 Receive Start interrupt is disabled. 1 Receive Start interrupt is enabled. Bit 2 – RXC Receive Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete interrupt. Value Description 0 Receive Complete interrupt is disabled. 1 Receive Complete interrupt is enabled. Bit 1 – TXC Transmit Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Transmit Complete Interrupt Enable bit, which disables the Receive Complete interrupt. SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 438

0 Transmit Complete interrupt is disabled. 1 Transmit Complete interrupt is enabled. Bit 0 – DRE Data Register Empty Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register Empty interrupt. Value Description 0 Data Register Empty interrupt is disabled. 1 Data Register Empty interrupt is enabled. SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 439

26.8.6 Interrupt Enable Set

Name: INTENSET Offset: 0x16 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 5 4 3 2 1 0 ERROR RXBRK CTSIC RXS RXC TXC DRE Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 7 – ERROR Error Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. Value Description 0 Error interrupt is disabled. 1 Error interrupt is enabled. Bit 5 – RXBRK Receive Break Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Receive Break Interrupt Enable bit, which enables the Receive Break interrupt. Value Description 0 Receive Break interrupt is disabled. 1 Receive Break interrupt is enabled. Bit 4 – CTSIC Clear to Send Input Change Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Clear To Send Input Change Interrupt Enable bit, which enables the Clear To Send Input Change interrupt. Value Description 0 Clear To Send Input Change interrupt is disabled. 1 Clear To Send Input Change interrupt is enabled. Bit 3 – RXS Receive Start Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Receive Start Interrupt Enable bit, which enables the Receive Start interrupt. Value Description 0 Receive Start interrupt is disabled. 1 Receive Start interrupt is enabled. Bit 2 – RXC Receive Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive Complete interrupt. Value Description 0 Receive Complete interrupt is disabled. 1 Receive Complete interrupt is enabled. Bit 1 – TXC Transmit Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete interrupt. SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 440

0 Transmit Complete interrupt is disabled. 1 Transmit Complete interrupt is enabled. Bit 0 – DRE Data Register Empty Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register Empty interrupt. Value Description 0 Data Register Empty interrupt is disabled. 1 Data Register Empty interrupt is enabled. SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 441

26.8.7 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x18 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 ERROR RXBRK CTSIC RXS RXC TXC DRE Access R/W R/W R/W R/W R R/W R Reset 0 0 0 0 0 0 0 Bit 7 – ERROR Error This flag is cleared by writing '1' to it. This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS register. Errors that will set this flag are COLL, ISF, BUFOVF, FERR, and PERR.Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 5 – RXBRK Receive Break This flag is cleared by writing '1' to it. This flag is set when auto-baud is enabled (CTRLA.FORM) and a break character is received. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 4 – CTSIC Clear to Send Input Change This flag is cleared by writing a '1' to it. This flag is set when a change is detected on the CTS pin. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 3 – RXS Receive Start This flag is cleared by writing '1' to it. This flag is set when a start condition is detected on the RxD line and start-of-frame detection is enabled (CTRLB.SFDE is '1'). Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Receive Start interrupt flag. Bit 2 – RXC Receive Complete This flag is cleared by reading the Data register (DATA) or by disabling the receiver. This flag is set when there are unread data in DATA. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. Bit 1 – TXC Transmit Complete This flag is cleared by writing '1' to it or by writing new data to DATA. This flag is set when the entire frame in the transmit shift register has been shifted out and there are no new data in DATA. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 0 – DRE Data Register Empty This flag is cleared by writing new data to DATA. This flag is set when DATA is empty and ready to be written. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 442

26.8.8 Status

Name: STATUS Offset: 0x1A Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 TXE COLL ISF CTS BUFOVF FERR PERR Access R/W R/W R/W R R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 6 – TXE Transmitter Empty This bit will always read back as zero. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Bit 5 – COLL Collision Detected This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set when collision detection is enabled (CTRLB.COLDEN) and a collision is detected. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Bit 4 – ISF Inconsistent Sync Field This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set when the frame format is set to auto-baud (CTRLA.FORM) and a sync field not equal to 0x55 is received. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Bit 3 – CTS Clear to Send This bit indicates the current level of the CTS pin when flow control is enabled (CTRLA.TXPO). Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. Bit 2 – BUFOVF Buffer Overflow Reading this bit before reading the Data register will indicate the error status of the next character to be read. This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set when a buffer overflow condition is detected. A buffer overflow occurs when the receive buffer is full, there is a new character waiting in the receive shift register and a new start bit is detected. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Bit 1 – FERR Frame Error Reading this bit before reading the Data register will indicate the error status of the next character to be read. This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set if the received character had a frame error, i.e., when the first stop bit is zero. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 443

Bit 0 – PERR Parity Error Reading this bit before reading the Data register will indicate the error status of the next character to be read. This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set if parity checking is enabled (CTRLA.FORM is 0x1, 0x5) and a parity error is detected. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 444

26.8.9 Synchronization Busy

Name: SYNCBUSY Offset: 0x1C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CTRLB ENABLE SWRST Access R R R Reset 0 0 0 Bit 2 – CTRLB CTRLB Synchronization Busy Writing to the CTRLB register when the SERCOM is enabled requires synchronization. When writing to CTRLB the SYNCBUSY.CTRLB bit will be set until synchronization is complete. If CTRLB is written while SYNCBUSY.CTRLB is asserted, an APB error will be generated. Value Description 0 CTRLB synchronization is not busy. 1 CTRLB synchronization is busy. Bit 1 – ENABLE SERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNCBUSY.ENABLE bit will be set until synchronization is complete. Value Description 0 Enable synchronization is not busy. 1 Enable synchronization is busy. Bit 0 – SWRST Software Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will be set until synchronization is complete. Value Description 0 SWRST synchronization is not busy. 1 SWRST synchronization is busy. SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 445

26.8.10 Data

Name: DATA Offset: 0x28 Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 DATA[8] Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 8:0 – DATA[8:0] Data Reading these bits will return the contents of the Receive Data register. The register should be read only when the Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set. The status bits in STATUS should be read before reading the DATA value in order to get any corresponding error. Writing these bits will write the Transmit Data register. This register should be written only when the Data Register Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set. SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 446

26.8.11 Debug Control

Name: DBGCTRL Offset: 0x30 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DBGSTOP Access R/W Reset 0 Bit 0 – DBGSTOP Debug Stop Mode This bit controls the baud-rate generator functionality when the CPU is halted by an external debugger. Value Description 0 The baud-rate generator continues normal operation when the CPU is halted by an external debugger. 1 The baud-rate generator is halted when the CPU is halted by an external debugger. SAM D21/DA1 Family SERCOM USART © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 447

SERCOM SPI – SERCOM Serial Peripheral Interface

27.1 Overview

The Serial Peripheral Interface (SPI) is one of the available modes in the Serial Communication Interface (SERCOM). The SPI uses the SERCOM transmitter and receiver configured as shown in 27.3 Block Diagram. Each side, host and client, depicts a separate SPI containing a Shift register, a transmit buffer and a two-level receive buffer. In addition, the SPI host uses the SERCOM baud-rate generator, while the SPI client can use the SERCOM address match logic. Labels in capital letters are synchronous to CLK_SERCOMx_APB and accessible by the CPU, while labels in lowercase letters are synchronous to the SCK clock. Related Links 25. SERCOM – Serial Communication Interface

27.2 Features

SERCOM SPI includes the following features:

Full-duplex, four-wire interface (MISO, MOSI, SCK, SS)
One-level transmit buffer, two-level receive buffer
Supports all four SPI modes of operation
Single data direction operation allows alternate function on MISO or MOSI pin
Selectable LSB- or MSB-first data transfer
Can be used with DMA
Host operation: – Serial clock speed, f SCK=1/tSCK(1) – 8-bit clock generator – Hardware controlled SS
Client Operation: – Serial clock speed, f SCK=1/tSSCK(1) – Optional 8-bit address match operation – Operation in all sleep modes – Wake on SS transition 1. For t SCK and tSSCK values, refer to SPI Timing Characteristics. Related Links

37.16.2 SERCOM in SPI Mode Timing

SERCOM – Serial Communication Interface

27.3 Block Diagram

Figure 27-1. Full-Duplex SPI Host Client Interconnection BAUD baud rate generator Tx DATA shift register rx buffer Rx DATA Host Client Tx DATA shift register rx buffer Rx DATA SCK SS MISO MOSI ADDR/ADDRMASK Address Match

27.4 Signal Description

Table 27-1. SERCOM SPI Signals Signal Name Type Description PAD[3:0] Digital I/O General SERCOM pins One signal can be mapped to one of several pins. Related Links 7. I/O Multiplexing and Considerations

27.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

27.5.1 I/O Lines

In order to use the SERCOM’s I/O lines, the I/O pins must be configured using the IO Pin Controller (PORT). When the SERCOM is configured for SPI operation, the SERCOM controls the direction and value of the I/O pins according to the table below. PORT Control bit PINCFGn.DRVSTR is still effective for the SERCOM output pins. PORT Control bit PINCFGn.PULLEN is still effective on the SERCOM input pins, but is limited to the enabling/ disabling of a pull down only (it is not possible to enable/disable a pull up). If the receiver is disabled, the data input pin can be used for other purposes. In Host mode, the SPI Select line (SS) is hardware controlled when the Host SPI Select Enable bit in the Control B register (CTRLB.MSSEN) is '1'. Table 27-2. SPI Pin Configuration Pin Host SPI Client SPI MOSI Output Input MISO Input Output SCK Output Input SS Output (CTRLB.MSSEN=1) Input The combined configuration of PORT, the Data In Pinout and the Data Out Pinout bit groups in the Control A register (CTRLA.DIPO and CTRLA.DOPO) define the physical position of the SPI signals in the table above. Related Links 23. PORT - I/O Pin Controller SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 449

27.5.2 Power Management

This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake up the device from sleep modes. Related Links 16. PM – Power Manager

27.5.3 Clocks

The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Power Manager. Refer to Peripheral Clock Masking for details and default status of this clock. A generic clock (GCLK_SERCOMx_CORE) is required to clock the SPI. This clock must be configured and enabled in the Generic Clock Controller before using the SPI. This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Therefore, writes to certain registers will require synchronization to the clock domains. Related Links 15. GCLK - Generic Clock Controller

27.6.6 Synchronization

27.5.4 DMA

27.5.5 Interrupts

27.5.6 Events

Not applicable.

27.5.7 Debug Operation

27.5.8 Register Access Protection

Registers with write-access can be write-protected optionally by the peripheral access controller (PAC). PAC Write-Protection is not available for the following registers:

Interrupt Flag Clear and Status register (INTFLAG)
Status register (STATUS)
Data register (DATA) Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger. Related Links

27.5.9 Analog Connections

Not applicable.

27.6 Functional Description

27.6.1 Principle of Operation

The SPI is a high-speed synchronous data transfer interface. It allows high-speed communication between the device and peripheral devices. The SPI can operate as host or client. As host, the SPI initiates and controls all data transactions. The SPI is single buffered for transmitting and double buffered for receiving. When transmitting data, the Data register can be loaded with the next character to be transmitted during the current transmission. When receiving, the data is transferred to the two-level receive buffer, and the receiver is ready for a new character. The SPI transaction format is shown in SPI Transaction Format. Each transaction can contain one or more characters. The character size is configurable, and can be either 8 or 9 bits. Figure 27-2. SPI Transaction Format Character Transaction MOSI/MISO Character 0 Character 1 Character 2 SS The SPI host must pull the SPI select line (SS) of the desired client low to initiate a transaction if multiple clients are connected to the bus. The SPI select line can be wired low if there is only one SPI client on the bus. The host and client prepare data to send via their respective Shift registers, and the host generates the serial clock on the SCK line. Data is always shifted from host to client on the Host Output Client Input line (MOSI); data is shifted from client to host on the Host Input Client Output line (MISO). Each time character is shifted out from the host, a character will be shifted out from the client simultaneously. To signal the end of a transaction, the host will pull the SS line high.

27.6.2 Basic Operation

27.6.2.1 Initialization

The following registers are enable-protected, meaning that they can only be written when the SPI is disabled (CTRL.ENABLE=0):

Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST)
Control B register (CTRLB), except Receiver Enable (CTRLB.RXEN)
Baud register (BAUD)
Address register (ADDR) When the SPI is enabled or is being enabled (CTRLA.ENABLE=1), any writing to these registers will be discarded. When the SPI is being disabled, writing to these registers will be completed after the disabling. Enable-protection is denoted by the Enable-Protection property in the register description. Initialize the SPI by following these steps: 1. Select SPI mode in host/client operation in the Operating Mode bit group in the CTRLA register (CTRLA.MODE= 0x2 or 0x3 ). 2. Select Transfer mode for the Clock Polarity bit and the Clock Phase bit in the CTRLA register (CTRLA.CPOL and CTRLA.CPHA) if desired. SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 451

Select the Frame Format value in the CTRLA register (CTRLA.FORM). 4. Configure the Data In Pinout field in the Control A register (CTRLA.DIPO) for SERCOM pads of the receiver. 5. Configure the Data Out Pinout bit group in the Control A register (CTRLA.DOPO) for SERCOM pads of the transmitter. 6. Select the Character Size value in the CTRLB register (CTRLB.CHSIZE). 7. Write the Data Order bit in the CTRLA register (CTRLA.DORD) for data direction. 8. If the SPI is used in Host mode: 8.1. Select the desired baud rate by writing to the Baud register (BAUD). 8.2. If Hardware SS control is required, write '1' to the Host SPI Select Enable bit in CTRLB register (CTRLB.MSSEN). 9. Enable the receiver by writing the Receiver Enable bit in the CTRLB register (CTRLB.RXEN=1).

27.6.2.2 Enabling, Disabling, and Resetting

27.6.2.3 Clock Generation

In the SPI host operation (CTRLA.MODE=0x3), the serial clock (SCK) is generated internally by the SERCOM Baud Rate Generator (BRG). In SPI mode, the BRG is set to Synchronous mode. The 8-bit Baud register (BAUD) value is used for generating SCK and clocking the Shift register. Refer to Clock Generation – Baud-Rate Generator for more details. In SPI client operation (CTRLA.MODE is 0x2), the clock is provided by an external host on the SCK pin. This clock is used to clock the SPI Shift register. Related Links

27.6.2.4 Data Register

The SPI Transmit Data register (TxDATA) and SPI Receive Data register (RxDATA) share the same I/O address, referred to as the SPI Data register (DATA). Writing DATA register will update the Transmit Data register. Reading the DATA register will return the contents of the Receive Data register.

27.6.2.5 SPI Transfer Modes

There are four combinations of SCK phase and polarity to transfer serial data. The SPI data transfer modes are shown in SPI Transfer Modes (Table) and SPI Transfer Modes (Figure). SCK phase is configured by the Clock Phase bit in the CTRLA register (CTRLA.CPHA). SCK polarity is programmed by the Clock Polarity bit in the CTRLA register (CTRLA.CPOL). Data bits are shifted out and latched in on opposite edges of the SCK signal. This ensures sufficient time for the data signals to stabilize. Table 27-3. SPI Transfer Modes Mode CPOL CPHA Leading Edge Trailing Edge 0 0 0 Rising, sample Falling, setup 1 0 1 Rising, setup Falling, sample 2 1 0 Falling, sample Rising, setup 3 1 1 Falling, setup Rising, sample Note: Leading edge is the first clock edge in a clock cycle. Trailing edge is the second clock edge in a clock cycle. SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 452

Figure 27-3. SPI Transfer Modes Bit 1 Bit 6 LSB MSB Mode 0 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN Mode 2 SS MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 MSB first (DORD = 0) LSB first (DORD = 1) Mode 1 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN Mode 3 SS MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB MSB first (DORD = 0) LSB first (DORD = 1)

27.6.2.6 Transferring Data

27.6.2.6.1 Host

In host mode (CTRLA.MODE=0x3), when Host SPI Enable Select (CTRLB.MSSEN) is ‘1’, hardware will control the SS line. When Host SPI Select Enable (CTRLB.MSSEN) is '0', the SS line must be configured as an output. SS can be assigned to any general purpose I/O pin. When the SPI is ready for a data transaction, software must pull the SS line low. When writing a character to the Data register (DATA), the character will be transferred to the shift register. Once the content of TxDATA has been transferred to the shift register, the Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) will be set. And a new character can be written to DATA. Each time one character is shifted out from the host, another character will be shifted in from the client simultaneously. If the receiver is enabled (CTRLA.RXEN=1), the contents of the shift register will be transferred to the two-level receive buffer. The transfer takes place in the same clock cycle as the last data bit is shifted in. And the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set. The received data can be retrieved by reading DATA. SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 453

When the last character has been transmitted and there is no valid data in DATA, the Transmit Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set. When the transaction is finished, the host must pull the SS line high to notify the client. If Host SPI Select Enable (CTRLB.MSSEN) is set to '0', the software must pull the SS line high.

27.6.2.6.2 Client

In Client mode (CTRLA.MODE=0x2), the SPI interface will remain inactive with the MISO line tri-stated as long as the SS pin is pulled high. Software may update the contents of DATA at any time as long as the Data Register Empty flag in the Interrupt Status and Clear register (INTFLAG.DRE) is set. When SS is pulled low and SCK is running, the client will sample and shift out data according to the Transaction mode set. When the content of TxDATA has been loaded into the Shift register, INTFLAG.DRE will be set, and new data can be written to DATA. Similar to the host, the client will receive one character for each character transmitted. A character will be transferred into the two-level receive buffer within the same clock cycle its last data bit is received. The received character can be retrieved from DATA when the Receive Complete interrupt flag (INTFLAG.RXC) is set. When the host pulls the SS line high, the transaction is done and the Transmit Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set. After DATA is written it takes up to three SCK clock cycles until the content of DATA is ready to be loaded into the Shift register on the next character boundary. As a consequence, the first character transferred in a SPI transaction the Client Shift Register. When transmitting several characters in one SPI transaction, the data has to be written into DATA register with at least three SCK clock cycles left in the current character transmission. If this criteria is not met, the previously received character will be transmitted. Once the DATA register is empty, it takes three CLK_SERCOM_APB cycles for INTFLAG.DRE to be set.

27.6.2.7 Receiver Error Bit

The SPI receiver has one error bit: the Buffer Overflow bit (BUFOVF), which can be read from the Status register (STATUS). Once an error happens, the bit will stay set until it is cleared by writing '1' to it. The bit is also automatically cleared when the receiver is disabled. There are two methods for buffer overflow notification, selected by the immediate buffer overflow notification bit in the Control A register (CTRLA.IBON): If CTRLA.IBON=1, STATUS.BUFOVF is raised immediately upon buffer overflow. Software can then empty the receive FIFO by reading RxDATA until the receiver complete interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) goes low. If CTRLA.IBON=0, the buffer overflow condition travels with data through the receive FIFO. After the received data is read, STATUS.BUFOVF and INTFLAG.ERROR will be set along with INTFLAG.RXC, and RxDATA will be zero.

27.6.3 Additional Features

27.6.3.1 Address Recognition

When the SPI is configured for client operation (CTRLA.MODE=0x2) with address recognition (CTRLA.FORM is 0x2), the SERCOM address recognition logic is enabled: the first character in a transaction is checked for an address match. If there is a match, the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set, the MISO output is enabled, and the transaction is processed. If the device is in Sleep mode, an address match can wake-up the device in order to process the transaction. If there is no match, the complete transaction is ignored. If a 9-bit frame format is selected, only the lower 8 bits of the Shift register are checked against the Address register (ADDR). Preload must be disabled (CTRLB.PLOADEN=0) in order to use this mode. SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 454

27.6.3.2 Preloading of the Client Shift Register

When starting a transaction, the client will first transmit the contents of the shift register before loading new data from DATA. The first character sent can be either the reset value of the shift register (if this is the first transmission since the last reset) or the last character in the previous transmission. Preloading can be used to preload data into the shift register while SS is high: this eliminates sending a dummy character when starting a transaction. If the shift register is not preloaded, the current contents of the shift register will be shifted out. Only one data character will be preloaded into the shift register while the synchronized SS signal is high. If the next character is written to DATA before SS is pulled low, the second character will be stored in DATA until transfer begins. For proper preloading, sufficient time must elapse between SS going low and the first SCK sampling edge, as in Timing Using Preloading. See also the Electrical Characteristics chapters for timing details. Preloading is enabled by writing '1' to the Client Data Preload Enable bit in the CTRLB register (CTRLB.PLOADEN). Figure 27-4. Timing Using Preloading SS SS synchronized to system domain SCK Synchronization to system domain MISO to SCK setup time Required SS-to-SCK time using PRELOADEN Related Links 37. Electrical Characteristics at 85℃

27.6.3.3 Host with Several Clients

Host with multiple clients in parallel is only available when Host SPI Select Enable (CTRLB.MSSEN) is set to zero and hardware SS control is disabled. If the bus consists of several SPI clients, a SPI host can use general purpose I/O pins to control the SS line to each of the clients on the bus, as shown in the following figure. In this configuration, the single selected SPI client will drive the tri-state MISO line. Figure 27-5. Multiple Clients in Parallel MOSI MISO SCK SS MOSI MISO SCK SS[0] MOSI MISO SCK SS SS[n-1] shift register shift register shift register SPI Host SPI Client 0 SPI Client n-1 Another configuration is multiple clients in series, as shown in the following figure. In this configuration, all n attached clients are connected in series. A common SS line is provided to all clients, enabling them simultaneously. The host SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 455

must shift n characters for a complete transaction. Depending on the Host SPI Select Enable bit (CTRLB.MSSEN), the SS line can be controlled either by hardware or user software and normal GPIO. Figure 27-6. Multiple Clients in Series MOSI MISO SCK SS MOSI MISO SCK SS MOSI MISO SCK SS shift register shift register shift register SPI Host SPI Client 0 SPI Client n-1

27.6.3.4 Loop-Back Mode

For loop-back mode, configure the Data In Pinout (CTRLA.DIPO) and Data Out Pinout (CTRLA.DOPO) to use the same data pins for transmit and receive. The loop-back is through the pad, so the signal is also available externally.

27.6.3.5 Hardware Controlled SS

In Host mode, a single SS chip select can be controlled by hardware by writing the Host SPI Select Enable (CTRLB.MSSEN) bit to '1'. In this mode, the SS pin is driven low for a minimum of one baud cycle before transmission begins, and stays low for a minimum of one baud cycle after transmission completes. If back-to-back frames are transmitted, the SS pin will always be driven high for a minimum of one baud cycle between frames. In Hardware Controlled SS, the time T is between one and two baud cycles depending on the SPI Transfer mode. Figure 27-7. Hardware Controlled SS SS SCK T T = 1 to 2 baud cycles T T TT When CTRLB.MSSEN=0, the SS pin(s) is/are controlled by user software and normal GPIO.

27.6.3.6 SPI Select Low Detection

In Client mode, the SPI can wake the CPU when the SPI Select (SS) goes low. When the SPI Select Low Detect is enabled (CTRLB.SSDE=1), a high-to-low transition will set the SPI Select Low Interrupt flag (INTFLAG.SSL) and the device will wake-up if applicable. SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 456

27.6.4 DMA, Interrupts, and Events

Table 27-4. Module Request for SERCOM SPI Condition Request DMA Interrupt Event Data Register Empty (DRE) Yes (request cleared when data is written) Yes NA Receive Complete (RXC) Yes (request cleared when data is read) Yes Transmit Complete (TXC) NA Yes SPI Select low (SSL) NA Yes Error (ERROR) NA Yes

27.6.4.1 DMA Operation

The SPI generates the following DMA requests:

Data received (RX): The request is set when data is available in the receive FIFO. The request is cleared when DATA is read.
Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is cleared when DATA is written.

27.6.4.2 Interrupts

The SPI has the following interrupt sources. These are asynchronous interrupts, and can wake-up the device from any Sleep mode:

Data Register Empty (DRE)
Receive Complete (RXC)
Transmit Complete (TXC)
SPI Select Low (SSL)
Error (ERROR) Each interrupt source has its own Interrupt flag. The Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the Interrupt condition is met. Each interrupt can be individually enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). The current state of enabled interrupts can be read from INTENSET or INTENCLR. An interrupt request is generated when the Interrupt flag is set and if the corresponding interrupt is enabled. The interrupt request remains active until either the Interrupt flag is cleared, the interrupt is disabled, or the SPI is reset. For details on clearing Interrupt flags, refer to the INTFLAG register description. The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for interrupt requests. Refer to Nested Vector Interrupt Controller for details. Related Links

27.6.4.3 Events

Not applicable.

27.6.5 Sleep Mode Operation

The behavior in Sleep mode is depending on the host/client configuration and the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY):

Host operation, CTRLA.RUNSTDBY=1: The peripheral clock GCLK_SERCOMx_CORE will continue to run in Idle Sleep mode and in Standby Sleep mode. Any interrupt can wake-up the device. SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 457

Host operation, CTRLA.RUNSTDBY=0: GLK_SERCOMx_CORE will be disabled after the ongoing transaction is finished. Any interrupt can wake up the device.
Client operation, CTRLA.RUNSTDBY=1: The Receive Complete interrupt can wake-up the device.
Client operation, CTRLA.RUNSTDBY=0: All reception will be dropped, including the ongoing transaction.

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written:

Software Reset bit in the CTRLA register (CTRLA.SWRST)
Enable bit in the CTRLA register (CTRLA.ENABLE)
Receiver Enable bit in the CTRLB register (CTRLB.RXEN) Note: CTRLB.RXEN is write-synchronized somewhat differently. See also CTRLB register for details. Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Related Links

27.7 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 RUNSTDBY MODE[2:0] ENABLE SWRST 15:8 IBON 23:16 DIPO[1:0] DOPO[1:0] 31:24 DORD CPOL CPHA FORM[3:0] 0x04 CTRLB 7:0 PLOADEN CHSIZE[2:0] 15:8 AMODE[1:0] MSSEN SSDE 23:16 RXEN 31:24 0x08 ... 0x0B Reserved 0x0C BAUD 7:0 BAUD[7:0] 0x0D ... 0x13 Reserved 0x14 INTENCLR 7:0 ERROR SSL RXC TXC DRE 0x15 Reserved 0x16 INTENSET 7:0 ERROR SSL RXC TXC DRE 0x17 Reserved 0x18 INTFLAG 7:0 ERROR SSL RXC TXC DRE 0x19 Reserved 0x1A STATUS 7:0 BUFOVF 15:8 0x1C SYNCBUSY 7:0 CTRLB ENABLE SWRST 15:8 23:16 31:24 0x20 ... 0x23 Reserved 0x24 ADDR 7:0 ADDR[7:0] 15:8 23:16 ADDRMASK[7:0] 31:24 0x28 DATA 7:0 DATA[7:0] 15:8 DATA[8] 0x2A ... 0x2F Reserved 0x30 DBGCTRL 7:0 DBGSTOP

27.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read- Synchronized" and/or "Write-Synchronized" property in each individual register description. Refer to 27.6.6 Synchronization Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description. SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 459

27.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 DORD CPOL CPHA FORM[3:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIPO[1:0] DOPO[1:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 IBON Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 RUNSTDBY MODE[2:0] ENABLE SWRST Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 30 – DORD Data Order This bit selects the data order when a character is shifted out from the shift register. This bit is not synchronized. Value Description 0 MSB is transferred first. 1 LSB is transferred first. Bit 29 – CPOL Clock Polarity In combination with the Clock Phase bit (CPHA), this bit determines the SPI transfer mode. This bit is not synchronized. Value Description 0 SCK is low when idle. The leading edge of a clock cycle is a rising edge, while the trailing edge is a falling edge. 1 SCK is high when idle. The leading edge of a clock cycle is a falling edge, while the trailing edge is a rising edge. Bit 28 – CPHA Clock Phase In combination with the Clock Polarity bit (CPOL), this bit determines the SPI transfer mode. This bit is not synchronized. Mode CPOL CPHA Leading Edge Trailing Edge 0x0 0 0 Rising, sample Falling, change 0x1 0 1 Rising, change Falling, sample 0x2 1 0 Falling, sample Rising, change 0x3 1 1 Falling, change Rising, sample Value Description 0 The data is sampled on a leading SCK edge and changed on a trailing SCK edge. 1 The data is sampled on a trailing SCK edge and changed on a leading SCK edge. SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 461

Bits 27:24 – FORM[3:0] Frame Format This bit field selects the various frame formats supported by the SPI in client mode. When the 'SPI frame with address' format is selected, the first byte received is checked against the ADDR register. FORM[3:0] Name Description 0x0 SPI SPI frame 0x1 - Reserved 0x2 SPI_ADDR SPI frame with address 0x3-0xF - Reserved Bits 21:20 – DIPO[1:0] Data In Pinout These bits define the data in (DI) pad configurations. In host operation, DI is MISO. In client operation, DI is MOSI. These bits are not synchronized. DIPO[1:0] Name Description 0x0 PAD[0] SERCOM PAD[0] is used as data input 0x1 PAD[1] SERCOM PAD[1] is used as data input 0x2 PAD[2] SERCOM PAD[2] is used as data input 0x3 PAD[3] SERCOM PAD[3] is used as data input Bits 17:16 – DOPO[1:0] Data Out Pinout This bit defines the available pad configurations for data out (DO), the serial clock (SCK) and the SPI select (SS). In Client operation, the SPI Select line (SS) is controlled by DOPO. In host operation, the SPI Select line (SS) is either controlled by DOPO when CTRLB.MSSEN = 1, or by a GPIO driven by the application when CTRLB.MSSEN = 0. In host operation, DO is MOSI. In client operation, DO is MISO. These bits are not synchronized. DOPO DO SCK Client SS Host SS (MSSEN = 1) Host SS (MSSEN = 0) 0x0 PAD[0] PAD[1] PAD[2] PAD[2] Any GPIO configured by the application 0x1 PAD[2] PAD[3] PAD[1] PAD[1] Any GPIO configured by the application 0x2 PAD[3] PAD[1] PAD[2] PAD[2] Any GPIO configured by the application 0x3 PAD[0] PAD[3] PAD[1] PAD[1] Any GPIO configured by the application Bit 8 – IBON Immediate Buffer Overflow Notification This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is set when a buffer overflow occurs. This bit is not synchronized. Value Description 0 STATUS.BUFOVF is set when it occurs in the data stream. 1 STATUS.BUFOVF is set immediately upon buffer overflow. Bit 7 – RUNSTDBY Run In Standby This bit defines the functionality in standby sleep mode. These bits are not synchronized. RUNSTDBY Client Host 0x0 Disabled. All reception is dropped, including the ongoing transaction. Generic clock is disabled when ongoing transaction is finished. All interrupts can wake up the device. 0x1 Ongoing transaction continues, wake on Receive Complete interrupt. Generic clock is enabled while in sleep modes. All interrupts can wake up the device. Bits 4:2 – MODE[2:0] Operating Mode These bits must be written to 0x2 or 0x3 to select the SPI serial communication interface of the SERCOM. 0x2: SPI client operation 0x3: SPI host operation SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 462

These bits are not synchronized. Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the Synchronization Enable Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the operation is complete. This bit is not enable-protected. Value Description 0 The peripheral is disabled or being disabled. 1 The peripheral is enabled or being enabled. Bit 0 – SWRST Software Reset Writing '0' to this bit has no effect. Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing ''1' to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY. SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Value Description 0 There is no reset operation ongoing. 1 The reset operation is ongoing. SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 463

27.8.2 Control B

Name: CTRLB Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 RXEN Access R/W Reset 0 Bit 15 14 13 12 11 10 9 8 AMODE[1:0] MSSEN SSDE Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PLOADEN CHSIZE[2:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 17 – RXEN Receiver Enable Writing '0' to this bit will disable the SPI receiver immediately. The receive buffer will be flushed, data from ongoing receptions will be lost and STATUS.BUFOVF will be cleared. Writing '1' to CTRLB.RXEN when the SPI is disabled will set CTRLB.RXEN immediately. When the SPI is enabled, CTRLB.RXEN will be cleared, SYNCBUSY.CTRLB will be set and remain set until the receiver is enabled. When the receiver is enabled CTRLB.RXEN will read back as '1'. Writing '1' to CTRLB.RXEN when the SPI is enabled will set SYNCBUSY.CTRLB, which will remain set until the receiver is enabled, and CTRLB.RXEN will read back as '1'. This bit is not enable-protected. Value Description 0 The receiver is disabled or being enabled. 1 The receiver is enabled or it will be enabled when SPI is enabled. Bits 15:14 – AMODE[1:0] Address Mode These bits set the Client Addressing mode when the frame format (CTRLA.FORM) with address is used. They are unused in Host mode. These bits are not synchronized. AMODE[1:0] Name Description 0x0 MASK ADDRMASK is used as a mask to the ADDR register 0x1 2_ADDRS The client responds to the two unique addresses in ADDR and ADDRMASK 0x2 RANGE The client responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit 0x3 - Reserved Bit 13 – MSSEN Host SPI Select Enable This bit enables hardware SPI Select (SS) control. This bit is not synchronized. SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 464

0 Hardware SS control is disabled. 1 Hardware SS control is enabled. Bit 9 – SSDE SPI Select Low Detect Enable This bit enables wake-up when the SPI Select (SS) pin transitions from high to low. This bit is not synchronized. Value Description 0 SS low detector is disabled. 1 SS low detector is enabled. Bit 6 – PLOADEN Client Data Preload Enable Setting this bit will enable preloading of the Client Shift register when there is no transfer in progress. If the SS line is high when DATA is written, it will be transferred immediately to the Shift register. This bit is not synchronized. Bits 2:0 – CHSIZE[2:0] Character Size These bits are not synchronized. CHSIZE[2:0] Name Description 0x0 8BIT 8 bits 0x1 9BIT 9 bits 0x2-0x7 - Reserved SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 465

27.8.3 Baud Rate

Name: BAUD Offset: 0x0C Reset: 0x00 Property: PAC Write-Protection, Enable-Protected Bit 7 6 5 4 3 2 1 0 BAUD[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – BAUD[7:0] Baud Register These bits control the clock generation, as described in the SERCOM Clock Generation – Baud-Rate Generator. Related Links SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 466

27.8.4 Interrupt Enable Clear

Name: INTENCLR Offset: 0x14 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 5 4 3 2 1 0 ERROR SSL RXC TXC DRE Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 – ERROR Error Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. Value Description 0 Error interrupt is disabled. 1 Error interrupt is enabled. Bit 3 – SSL SPI Select Low Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the SPI Select Low Interrupt Enable bit, which disables the SPI Select Low interrupt. Value Description 0 SPI Select Low interrupt is disabled. 1 SPI Select Low interrupt is enabled. Bit 2 – RXC Receive Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete interrupt. Value Description 0 Receive Complete interrupt is disabled. 1 Receive Complete interrupt is enabled. Bit 1 – TXC Transmit Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Transmit Complete Interrupt Enable bit, which disable the Transmit Complete interrupt. Value Description 0 Transmit Complete interrupt is disabled. 1 Transmit Complete interrupt is enabled. Bit 0 – DRE Data Register Empty Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register Empty interrupt. Value Description 0 Data Register Empty interrupt is disabled. 1 Data Register Empty interrupt is enabled. SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 467

27.8.5 Interrupt Enable Set

Name: INTENSET Offset: 0x16 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 5 4 3 2 1 0 ERROR SSL RXC TXC DRE Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 – ERROR Error Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. Value Description 0 Error interrupt is disabled. 1 Error interrupt is enabled. Bit 3 – SSL SPI Select Low Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the SPI Select Low Interrupt Enable bit, which enables the SPI Select Low interrupt. Value Description 0 SPI Select Low interrupt is disabled. 1 SPI Select Low interrupt is enabled. Bit 2 – RXC Receive Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive Complete interrupt. Value Description 0 Receive Complete interrupt is disabled. 1 Receive Complete interrupt is enabled. Bit 1 – TXC Transmit Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete interrupt. Value Description 0 Transmit Complete interrupt is disabled. 1 Transmit Complete interrupt is enabled. Bit 0 – DRE Data Register Empty Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register Empty interrupt. Value Description 0 Data Register Empty interrupt is disabled. 1 Data Register Empty interrupt is enabled. SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 468

27.8.6 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x18 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 ERROR SSL RXC TXC DRE Access R/W R/W R R/W R Reset 0 0 0 0 0 Bit 7 – ERROR Error This flag is cleared by writing '1' to it. This bit is set when any error is detected. Errors that will set this flag have corresponding Status flags in the STATUS register. The BUFOVF error will set this Interrupt flag. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 3 – SSL SPI Select Low This flag is cleared by writing '1' to it. This bit is set when a high to low transition is detected on the SS pin in Client mode and SPI Select Low Detect (CTRLB.SSDE) is enabled. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 2 – RXC Receive Complete This flag is cleared by reading the Data (DATA) register or by disabling the receiver. This flag is set when there are unread data in the receive buffer. If address matching is enabled, the first data received in a transaction will be an address. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. Bit 1 – TXC Transmit Complete This flag is cleared by writing '1' to it or by writing new data to DATA. In Host mode, this flag is set when the data have been shifted out and there are no new data in DATA. In Client mode, this flag is set when the SS pin is pulled high. If address matching is enabled, this flag is only set if the transaction was initiated with an address match. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 0 – DRE Data Register Empty This flag is cleared by writing new data to DATA. This flag is set when DATA is empty and ready for new data to transmit. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 469

27.8.7 Status

Name: STATUS Offset: 0x1A Reset: 0x0000 Property: – Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 BUFOVF Access R/W Reset 0 Bit 2 – BUFOVF Buffer Overflow Reading this bit before reading DATA will indicate the error status of the next character to be read. This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set when a buffer overflow condition is detected. See also CTRLA.IBON for overflow handling. When set, the corresponding RxDATA will be zero. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Value Description 0 No Buffer Overflow has occurred. 1 A Buffer Overflow has occurred. SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 470

27.8.8 Synchronization Busy

Name: SYNCBUSY Offset: 0x1C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CTRLB ENABLE SWRST Access R R R Reset 0 0 0 Bit 2 – CTRLB CTRLB Synchronization Busy Writing to the CTRLB when the SERCOM is enabled requires synchronization. Ongoing synchronization is indicated by SYNCBUSY.CTRLB=1 until synchronization is complete. If CTRLB is written while SYNCBUSY.CTRLB=1, an APB error will be generated. Value Description 0 CTRLB synchronization is not busy. 1 CTRLB synchronization is busy. Bit 1 – ENABLE SERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. Ongoing synchronization is indicated by SYNCBUSY.ENABLE=1 until synchronization is complete. Value Description 0 Enable synchronization is not busy. 1 Enable synchronization is busy. Bit 0 – SWRST Software Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. Ongoing synchronization is indicated by SYNCBUSY.SWRST=1 until synchronization is complete. Value Description 0 SWRST synchronization is not busy. 1 SWRST synchronization is busy. SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 471

27.8.9 Address

Name: ADDR Offset: 0x24 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 ADDRMASK[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 23:16 – ADDRMASK[7:0] Address Mask These bits hold the address mask when the transaction format with address is used (CTRLA.FORM, CTRLB.AMODE). Bits 7:0 – ADDR[7:0] Address These bits hold the address when the transaction format with address is used (CTRLA.FORM, CTRLB.AMODE). SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 472

27.8.10 Data

Name: DATA Offset: 0x28 Reset: 0x0000 Property: – Bit 15 14 13 12 11 10 9 8 DATA[8] Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 8:0 – DATA[8:0] Data Reading these bits will return the contents of the receive data buffer. The register should be read only when the Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set. Writing these bits will write the transmit data buffer. This register should be written only when the Data Register Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set. SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 473

27.8.11 Debug Control

Name: DBGCTRL Offset: 0x30 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DBGSTOP Access R/W Reset 0 Bit 0 – DBGSTOP Debug Stop Mode This bit controls the functionality when the CPU is halted by an external debugger. Value Description 0 The baud-rate generator continues normal operation when the CPU is halted by an external debugger. 1 The baud-rate generator is halted when the CPU is halted by an external debugger. SAM D21/DA1 Family SERCOM SPI – SERCOM Serial Peripheral Interface © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 474

SERCOM I2C – Inter-Integrated Circuit

28.1 Overview

The inter-integrated circuit ( I2C) interface is one of the available modes in the serial communication interface (SERCOM). The I2C interface uses the SERCOM transmitter and receiver configured as shown in Figure 28-1. Labels in capital letters are registers accessible by the CPU, while lowercase labels are internal to the SERCOM. A SERCOM instance can be configured to be either an I2C host or an I2C client. Both host and client have an interface containing a shift register, a transmit buffer and a receive buffer. In addition, the I2C host uses the SERCOM baud-rate generator, while the I2C client uses the SERCOM address match logic. Related Links 25. SERCOM – Serial Communication Interface

28.2 Features

SERCOM I2C includes the following features:

Host or Client Operation
Can be used with DMA
Philips I 2C Compatible
SMBus Compatible
PMBus ™ Compatible
Support of 100 kHz and 400 kHz, 1 MHz and 3.4 MHz I 2C mode
4-Wire Operation Supported
Physical interface includes: – Slew-rate limited outputs – Filtered inputs
Client Operation: – Operation in all Sleep modes – Wake-up on address match – 7-bit and 10-bit Address match in hardware for: – • Unique address and/or 7-bit general call address
Address range
Two unique addresses can be used with DMA Related Links

28.3 Block Diagram

Figure 28-1. I2C Single-Host Single-Client Interconnection BAUD TxDATA RxDATA baud rate generator SCL hold low shift register TxDATA RxDATA shift register 0 0 0 0 SCL hold low ADDR/ADDRMASK SDA SCL Host Client

28.4 Signal Description

Signal Name Type Description PAD[0] Digital I/O SDA PAD[1] Digital I/O SCL PAD[2] Digital I/O SDA_OUT (4-wire operation) PAD[3] Digital I/O SCL_OUT (4-wire operation) One signal can be mapped on several pins. Not all the pins are I2C pins. Refer to Table 7-5. SERCOM Pins Supporting I2C for additional information . Related Links 7. I/O Multiplexing and Considerations 28.6.3.3 4-Wire Mode

28.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

28.5.1 I/O Lines

In order to use the I/O lines of this peripheral, the I/O pins must be configured using the I/O Pin Controller (PORT). When the SERCOM is used in I2C mode, the SERCOM controls the direction and value of the I/O pins. If the receiver or transmitter is disabled, these pins can be used for other purposes. Related Links 23. PORT - I/O Pin Controller

28.5.2 Power Management

This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake up the device from sleep modes. Related Links 16. PM – Power Manager SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 476

28.5.3 Clocks

The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Power Manager. Refer to Peripheral Clock Masking for details and default status of this clock. Two generic clocks are used by SERCOM: GCLK_SERCOMx_CORE and GCLK_SERCOM_SLOW. The core clock (GCLK_SERCOMx_CORE) can clock the I2C when working as a host. The slow clock (GCLK_SERCOM_SLOW) is required only for certain functions, e.g. SMBus timing. These two clocks must be configured and enabled in the Generic Clock Controller (GCLK) before using the I2C. These generic clocks are asynchronous to the bus clock (CLK_SERCOMx_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to 28.6.6 Synchronization for further details. Related Links 15. GCLK - Generic Clock Controller 16. PM – Power Manager

28.5.4 DMA

28.5.5 Interrupts

28.5.6 Events

Not applicable.

28.5.7 Debug Operation

28.5.8 Register Access Protection

Registers with write-access can be write-protected optionally by the peripheral access controller (PAC). PAC Write-Protection is not available for the following registers:

Interrupt Flag Clear and Status register (INTFLAG)
Status register (STATUS)
Data register (DATA)
Address register (ADDR) Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger. Related Links

28.5.9 Analog Connections

Not applicable.

28.6 Functional Description

28.6.1 Principle of Operation

The I2C interface uses two physical lines for communication:

Serial Data Line (SDA) for data transfer
Serial Clock Line (SCL) for the bus clock A transaction starts with the I2C host sending the Start condition, followed by a 7-bit address and a direction bit (read or write to/from the client). The addressed I2C client will then Acknowledge (ACK) the address, and data packet transactions can begin. Every 9-bit data packet consists of 8 data bits followed by a one-bit reply indicating whether the data was acknowledged or not. If a data packet is Not Acknowledged (NACK), whether by the I2C client or host, the I2C host takes action by either terminating the transaction by sending the Stop condition, or by sending a repeated start to transfer more data. The figure below illustrates the possible transaction formats and Transaction Diagram Symbols explains the transaction symbols. These symbols will be used in the following descriptions. Figure 28-2. Transaction Diagram Symbols S Sr A A R W P START condition repeated START condition STOP condition Host driving bus Client driving bus Either Host or Client driving bus Acknowledge (ACK) Not Acknowledge (NACK) Host Read Host Write Bus Driver Special Bus Conditions Data Package Direction Acknowledge '1' '0' '0' '1' SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 478

Figure 28-3. Basic I2C Transaction Diagram SDA SCL S ADDRESS R/W ACK DATA ACK DATA ACK/NACK P S ADDRESS R/W A DATA PA DATA A/A Direction Address Packet Data Packet #0 Data Packet #1 Transaction

28.6.2 Basic Operation

28.6.2.1 Initialization

The following registers are enable-protected, meaning they can be written only when the I2C interface is disabled (CTRLA.ENABLE is ‘0’):

Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST) bits
Control B register (CTRLB), except Acknowledge Action (CTRLB.ACKACT) and Command (CTRLB.CMD) bits
Baud register (BAUD)
Address register (ADDR) in client operation. When the I2C is enabled or is being enabled (CTRLA.ENABLE=1), writing to these registers will be discarded. If the I2C is being disabled, writing to these registers will be completed after the disabling. Enable-protection is denoted by the "Enable-Protection" property in the register description. Before the I2C is enabled it must be configured as outlined by the following steps: 1. Select I 2C Host or Client mode by writing 0x4 (Client mode) or 0x5 (Host mode) to the Operating Mode bits in the CTRLA register (CTRLA.MODE). 2. If desired, select the SDA Hold Time value in the CTRLA register (CTRLA.SDAHOLD). 3. If desired, enable smart operation by setting the Smart Mode Enable bit in the CTRLB register (CTRLB.SMEN). 4. If desired, enable SCL low time-out by setting the SCL Low Time-Out bit in the Control A register (CTRLA.LOWTOUTEN). 5. In Host mode: 5.1. Select the inactive bus time-out in the Inactive Time-Out bit group in the CTRLA register (CTRLA.INACTOUT). 5.2. Write the Baud Rate register (BAUD) to generate the desired baud rate. In Client mode: 5.1. Configure the address match configuration by writing the Address Mode value in the CTRLB register (CTRLB.AMODE). 5.2. Set the Address and Address Mask value in the Address register (ADDR.ADDR and ADDR.ADDRMASK) according to the address configuration.

28.6.2.2 Enabling, Disabling, and Resetting

This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and disabled by writing '0' to it. Writing ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of this peripheral to their initial states, except the DBGCTRL register, and the peripheral is disabled. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 479

28.6.2.3 I2C Bus State Logic

The Bus state logic includes several logic blocks that continuously monitor the activity on the I2C bus lines in all Sleep modes with running GCLK_SERCOM_x clocks. The start and stop detectors and the bit counter are all essential in the process of determining the current Bus state. The Bus state is determined according to Bus State Diagram. Software can get the current Bus state by reading the Host Bus State bits in the Status register (STATUS.BUSSTATE). The value of STATUS.BUSSTATE in the figure is shown in binary. Figure 28-4. Bus State Diagram RESET Write ADDR to g enerate Start Condition IDLE (0b01) Start Condition BUSY (0b11)Timeout or Stop Condition UNKNOWN (0b00) OWNER (0b10) Lost A rbitration Repeated Start Condition Write ADDR to g enerate Repeated Start Condition Stop Condition Timeout or Stop Condition The Bus state machine is active when the I2C host is enabled. After the I2C host has been enabled, the Bus state is UNKNOWN (0b00). From the UNKNOWN state, the bus will transition to IDLE (0b01) by either:

Forcing by writing 0b01 to STATUS.BUSSTATE
A Stop condition is detected on the bus
If the inactive bus time-out is configured for SMBus compatibility (CTRLA.INACTOUT) and a time-out occurs. Note: Once a known Bus state is established, the Bus state logic will not re-enter the UNKNOWN state. When the bus is IDLE it is ready for a new transaction. If a Start condition is issued on the bus by another I2C host in a multi-host setup, the bus becomes BUSY (0b11). The bus will re-enter IDLE either when a Stop condition is detected, or when a time-out occurs (inactive bus time-out needs to be configured). If a Start condition is generated internally by writing the Address bit group in the Address register (ADDR.ADDR) while IDLE, the OWNER state (0b10) is entered. If the complete transaction was performed without interference, i.e., arbitration was not lost, the I2C host can issue a Stop condition, which will change the Bus state back to IDLE. However, if a packet collision is detected while in OWNER state, the arbitration is assumed lost and the Bus state becomes BUSY until a Stop condition is detected. A repeated Start condition will change the Bus state only if arbitration is lost while issuing a repeated start. Note: Violating the protocol may cause the I2C to hang. If this happens it is possible to recover from this state by a software Reset (CTRLA.SWRST='1'). Related Links

28.10.1 CTRLA

28.6.2.4 I2C Host Operation

The I2C host is byte-oriented and interrupt based. The number of interrupts generated is kept at a minimum by automatic handling of most incidents. The software driver complexity and code size are reduced by auto-triggering of operations, and a Special Smart mode, which can be enabled by the Smart Mode Enable bit in the Control B register (CTRLB.SMEN). The I2C host has two interrupt strategies. When SCL Clock Stretch Mode (CTRLA.SCLSM) is '0', SCL is stretched before or after the Acknowledge bit . In this mode the I2C host operates according to the following figure. The circles labeled "Mn" (M1, M2..) indicate the nodes the bus logic can jump to, based on software or hardware interaction. This diagram is used as reference for the description of the I2C host operation throughout the document. Figure 28-5. I2C Host Behavioral Diagram (SCLSM=0) IDLE S BUSYBUSY P Sr P R DATA Wait for IDLE ADDRESS W A/ADATA APPLICATION SW SW Sr P BUSY M4ASW A/A A/A A/A A IDLE IDLE CLIENT BUS INTERRUPT + SCL HOLD HOST BUS INTERRUPT + SCL HOLD SW SW SW BUSYR/W SW Software interaction A A R/W BUSY M4 The host provides data on the bus Addressed client provides data on the bus In the second strategy (CTRLA.SCLSM=1), interrupts only occur after the ACK bit, as shown in the following figure. This strategy can be used when it is not necessary to check DATA before acknowledging. Note: I2C High-speed (Hs) mode requires CTRLA.SCLSM=1. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 481

Figure 28-6. I2C Host Behavioral Diagram (SCLSM=1) IDLE S BUSYBUSY P Sr P R DATA W A/ADATA APPLICATION SW SW Sr P BUSY M4SW A/A A IDLE IDLE Host Bus INTERRUPT + SCL HOLD SW SW SW BUSYR/W A A R/W BUSY M4 SW Software interaction The host provides data on the bus Addressed client provides data on the bus Client Bus INTERRUPT + SCL HOLD Wait for IDLE ADDRESS

28.6.2.4.1 Host Clock Generation

The SERCOM peripheral supports several I2C bidirectional modes:

Standard mode ( Sm) up to 100 kHz
Fast mode ( Fm) up to 400 kHz
Fast mode Plus ( Fm+) up to 1 MHz
High-speed mode ( Hs) up to 3.4 MHz The Host clock configuration for Sm, Fm, and Fm+ are described in Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus). For Hs, refer to Host Clock Generation (High-Speed Mode). Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus) In I2C Sm, Fm, and Fm+ mode, the Host clock (SCL) frequency is determined as described in this section: The low (TLOW) and high (THIGH) times are determined by the Baud Rate register (BAUD), while the rise (TRISE) and fall (TFALL) times are determined by the bus topology. Because of the wired-AND logic of the bus, TFALL will be considered as part of TLOW. Likewise, TRISE will be in a state between TLOW and THIGH until a high state has been detected. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 482

Figure 28-7. SCL Timing TSU;STO THD;STA TBUF TFALL TLOW TRISE THIGH SCL SDA P S TSU;STA Sr The following parameters are timed using the SCL low time period TLOW. This comes from the Host Baud Rate Low bit group in the Baud Rate register (BAUD.BAUDLOW). When BAUD.BAUDLOW=0, or the Host Baud Rate bit group in the Baud Rate register (BAUD.BAUD) determines it.

T LOW – Low period of SCL clock
T SU;STO – Set-up time for stop condition
T BUF – Bus free time between stop and start conditions
T HD;STA – Hold time (repeated) start condition
T SU;STA – Set-up time for repeated start condition
T HIGH is timed using the SCL high time count from BAUD.BAUD
T RISE is determined by the bus impedance; for internal pull-ups.
T FALL is determined by the open-drain current limit and bus impedance; can typically be regarded as zero. The SCL frequency is given by: f SCL = 1 T LOW + T HIGH + T RISE When BAUD.BAUDLOW is zero, the BAUD.BAUD value is used to time both SCL high and SCL low. In this case the following formula will give the SCL frequency: f SCL = f GCLK 10 + 2 B A U D + f GCLK ⋅ T RISE When BAUD.BAUDLOW is non-zero, the following formula determines the SCL frequency: f SCL = f GCLK 10 + B AU D + B A U DL OW + f GCLK ⋅ T RISE The following formulas can determine the SCL TLOW and THIGH times: T LOW = B AU D LO W + 5 f GCLK T HIGH = B AU D + 5 f GCLK Note: The I2C standard Fm+ (Fast-mode plus) requires a nominal high to low SCL ratio of 1:2, and BAUD should be set accordingly. At a minimum, BAUD.BAUD and/or BAUD.BAUDLOW must be non-zero. Startup Timing The minimum time between SDA transition and SCL rising edge is 6 APB cycles when the DATA register is written in smart mode. If a greater startup time is required due to long rise times, the time between DATA write and IF clear must be controlled by software. Note: When timing is controlled by user, the Smart Mode cannot be enabled. Related Links 37. Electrical Characteristics at 85℃ SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 483

Host Clock Generation (High-Speed Mode) For I2C Hs transfers, there is no SCL synchronization. Instead, the SCL frequency is determined by the GCLK_SERCOMx_CORE frequency (fGCLK) and the High-Speed Baud setting in the Baud register (BAUD.HSBAUD). When BAUD.HSBAUDLOW=0, the HSBAUD value will determine both SCL high and SCL low. In this case the following formula determines the SCL frequency. f SCL = f GCLK 2 + 2 ⋅ HS B AU D When HSBAUDLOW is non-zero, the following formula determines the SCL frequency. f SCL = f GCLK 2 + HS B AU D + HS B A U DL OW Note: The I2C standard Hs (High-speed) requires a nominal high to low SCL ratio of 1:2, and HSBAUD should be set accordingly. At a minimum, BAUD.HSBAUD and/or BAUD.HSBAUDLOW must be non-zero.

28.6.2.4.2 Transmitting Address Packets

The I2C host starts a bus transaction by writing the I2C client address to ADDR.ADDR and the direction bit, as described in 28.6.1 Principle of Operation. If the bus is busy, the I2C host will wait until the bus becomes idle before continuing the operation. When the bus is idle, the I2C host will issue a start condition on the bus. The I2C host will then transmit an address packet using the address written to ADDR.ADDR. After the address packet has been transmitted by the I2C host, one of four cases will arise according to arbitration and transfer direction. Case 1: Arbitration lost or bus error during address packet transmission If arbitration was lost during transmission of the address packet, the Host on Bus bit in the Interrupt Flag Status and Clear register (INTFLAG.MB) and the Arbitration Lost bit in the Status register (STATUS.ARBLOST) are both set. Serial data output to SDA is disabled, and the SCL is released, which disables clock stretching. In effect the I2C host is no longer allowed to execute any operation on the bus until the bus is idle again. A bus error will behave similarly to the Arbitration Lost condition. In this case, the MB Interrupt flag and Host Bus Error bit in the Status register (STATUS.BUSERR) are both set in addition to STATUS.ARBLOST. The Host Received Not Acknowledge bit in the Status register (STATUS.RXNACK) will always contain the last successfully received acknowledge or not acknowledge indication. In this case, software will typically inform the application code of the condition and then clear the Interrupt flag before exiting the interrupt routine. No other flags have to be cleared at this moment, because all flags will be cleared automatically the next time the ADDR.ADDR register is written. Case 2: Address packet transmit complete – No ACK received If there is no I2C client device responding to the address packet, then the INTFLAG.MB Interrupt flag and STATUS.RXNACK will be set. The clock hold is active at this point, preventing further activity on the bus. The missing ACK response can indicate that the I2C client is busy with other tasks or sleeping. Therefore, it is not able to respond. In this event, the next step can be either issuing a Stop condition (recommended) or resending the address packet by a repeated Start condition. When using SMBus logic, the client must ACK the address. If there is no response, it means that the client is not available on the bus. Case 3: Address packet transmit complete – Write packet, Host on Bus set If the I2C host receives an acknowledge response from the I2C client, INTFLAG.MB will be set and STATUS.RXNACK will be cleared. The clock hold is active at this point, preventing further activity on the bus. In this case, the software implementation becomes highly protocol dependent. Three possible actions can enable the I2C operation to continue:

Initiate a data transmit operation by writing the data byte to be transmitted into DATA.DATA.
Transmit a new address packet by writing ADDR.ADDR. A repeated Start condition will automatically be inserted before the address packet.
Issue a Stop condition, consequently terminating the transaction. Case 4: Address packet transmit complete – Read packet, Client on Bus set SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 484

If the I2C host receives an ACK from the I2C client, the I2C host proceeds to receive the next byte of data from the I2C client. When the first data byte is received, the Client on Bus bit in the Interrupt Flag register (INTFLAG.SB) will be set and STATUS.RXNACK will be cleared. The clock hold is active at this point, preventing further activity on the bus. In this case, the software implementation becomes highly protocol dependent. Three possible actions can enable the I2C operation to continue:

Let the I 2C host continue to read data by acknowledging the data received. ACK can be sent by software, or automatically in Smart mode.
Transmit a new address packet.
Terminate the transaction by issuing a Stop condition. Note: An ACK or NACK will be automatically transmitted if Smart mode is enabled. The Acknowledge Action bit in the Control B register (CTRLB.ACKACT) determines whether ACK or NACK should be sent.

28.6.2.4.3 Transmitting Data Packets

When an address packet with direction Host Write (see Figure 28-3) was transmitted successfully , INTFLAG.MB will be set. The I2C host will start transmitting data via the I2C bus by writing to DATA.DATA, and monitor continuously for packet collisions. If a collision is detected, the I2C host will lose arbitration and STATUS.ARBLOST will be set. If the transmit was successful, the I2C host will receive an ACK bit from the I2C client, and STATUS.RXNACK will be cleared. INTFLAG.MB will be set in both cases, regardless of arbitration outcome. It is recommended to read STATUS.ARBLOST and handle the arbitration lost condition in the beginning of the I2C Host on Bus interrupt. This can be done as there is no difference between handling address and data packet arbitration. STATUS.RXNACK must be checked for each data packet transmitted before the next data packet transmission can commence. The I2C host is not allowed to continue transmitting data packets if a NACK is received from the I2C client.

28.6.2.4.4 Receiving Data Packets (SCLSM=0)

When INTFLAG.SB is set, the I2C host will already have received one data packet. The I2C host must respond by sending either an ACK or NACK. Sending a NACK may be unsuccessful when arbitration is lost during the transmission. In this case, a lost arbitration will prevent setting INTFLAG.SB. Instead, INTFLAG.MB will indicate a change in arbitration. Handling of lost arbitration is the same as for data bit transmission.

28.6.2.4.5 Receiving Data Packets (SCLSM=1)

When INTFLAG.SB is set, the I2C host will already have received one data packet and transmitted an ACK or NACK, depending on CTRLB.ACKACT. At this point, CTRLB.ACKACT must be set to the correct value for the next ACK bit, and the transaction can continue by reading DATA and issuing a command if not in the Smart mode.

28.6.2.4.6 High-Speed Mode

High-speed transfers are a multi-step process, see High Speed Transfer. First, a host code (0b00001nnn, where 'nnn' is a unique host code) is transmitted in Full-speed mode, followed by a NACK since no client should acknowledge. Arbitration is performed only during the Full-speed Host Code phase. The host code is transmitted by writing the host code to the Address register (ADDR.ADDR) and writing the High-speed bit (ADDR.HS) to '0'. After the host code and NACK have been transmitted, the host write interrupt will be asserted. In the meanwhile, the client address can be written to the ADDR.ADDR register together with ADDR.HS=1. Now in High-speed mode, the host will generate a repeated start, followed by the client address with RW-direction. The bus will remain in High-speed mode until a stop is generated. If a repeated start is desired, the ADDR.HS bit must again be written to '1', along with the new address ADDR.ADDR to be transmitted. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 485

Figure 28-8. High Speed Transfer S A A/ASr PA DATA N Data Packets Host Code R/WADDRESS Sr ADDRESS Hs-mode continues F/S-modeHs-modeF/S-mode Transmitting in High-speed mode requires the I2C host to be configured in High-speed mode (CTRLA.SPEED=0x2) and the SCL Clock Stretch mode (CTRLA.SCLSM) bit set to '1'. 28.6.2.4.7 10-Bit Addressing When 10-bit addressing is enabled by the Ten Bit Addressing Enable bit in the Address register (ADDR.TENBITEN=1) and the Address bit field ADDR.ADDR is written, the two address bytes will be transmitted, see 10-bit Address Transmission for a Read Transaction. The addressed client acknowledges the two address bytes, and the transaction continues. Regardless of whether the transaction is a read or write, the host must start by sending the 10-bit address with the direction bit (ADDR.ADDR[0]) being zero. If the host receives a NACK after the first byte, the Write Interrupt flag will be raised and the STATUS.RXNACK bit will be set. If the first byte is acknowledged by one or more clients, then the host will proceed to transmit the second address byte and the host will first see the Write Interrupt flag after the second byte is transmitted. If the transaction direction is read-from-client, the 10-bit address transmission must be followed by a repeated start and the first 7 bits of the address with the read/write bit equal to '1'. Figure 28-9. 10-bit Address Transmission for a Read Transaction S AW addr[7:0] A11110 addr[9:8] Sr AR S W 11110 addr[9:8] MB INTERRUPT This implies the following procedure for a 10-bit read operation: 1. Write the 10-bit address to ADDR.ADDR[10:1]. ADDR.TENBITEN must be '1', the direction bit (ADDR.ADDR[0]) must be '0' (can be written simultaneously with ADDR). 2. Once the Host on Bus interrupt is asserted, Write ADDR[7:0] register to '11110 address[9:8] 1'. ADDR.TENBITEN must be cleared (can be written simultaneously with ADDR). 3. Proceed to transmit data.

28.6.2.5 I2C Client Operation

The I2C client is byte-oriented and interrupt-based. The number of interrupts generated is kept at a minimum by automatic handling of most events. The software driver complexity and code size are reduced by auto-triggering of operations, and a special smart mode, which can be enabled by the Smart Mode Enable bit in the Control B register (CTRLB.SMEN). The I2C client has two interrupt strategies. When SCL Stretch Mode bit (CTRLA.SCLSM) is '0', SCL is stretched before or after the acknowledge bit. In this mode, the I2C client operates according to the following figure. The circles labeled "Sn" (S1, S2..) indicate the nodes the bus logic can jump to, based on software or hardware interaction. This diagram is used as reference for the description of the I2C client operation throughout the document. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 486

28.6.2.5.1 Receiving Address Packets (SCLSM=0)

When CTRLA.SCLSM=0, the I2C client stretches the SCL line according to Figure 28-10. When the I2C client is properly configured, it will wait for a Start condition. When a Start condition is detected, the successive address packet will be received and checked by the address match logic. If the received address is not a match, the packet will be rejected, and the I2C client will wait for a new Start condition. If the received address is a match, the Address Match bit in the Interrupt Flag register (INTFLAG.AMATCH) will be set. SCL will be stretched until the I2C client clears INTFLAG.AMATCH. As the I2C client holds the clock by forcing SCL low, the software has unlimited time to respond. The direction of a transaction is determined by reading the Read/Write Direction bit in the Status register (STATUS.DIR). This bit will be updated only when a valid address packet is received. If the Transmit Collision bit in the Status register (STATUS.COLL) is set, this indicates that the last packet addressed to the I2C client had a packet collision. A collision causes the SDA and SCL lines to be released without any notification to software. Therefore, the next AMATCH interrupt is the first indication of the previous packet’s collision. Collisions are intended to follow the SMBus Address Resolution Protocol (ARP). After the address packet has been received from the I2C host, one of two cases will arise based on transfer direction. Case 1: Address packet accepted – Read flag set The STATUS.DIR bit is ‘1’, indicating an I2C host read operation. The SCL line is forced low, stretching the bus clock. If an ACK is sent, I2C client hardware will set the Data Ready bit in the Interrupt Flag register (INTFLAG.DRDY), indicating data are needed for transmit. If a NACK is sent, the I2C client will wait for a new Start condition and address match. Typically, software will immediately acknowledge the address packet by sending an ACK/NACK bit. The I2C client Command bit field in the Control B register (CTRLB.CMD) can be written to '0x3' for both read and write operations as the command execution is dependent on the STATUS.DIR bit. Writing ‘1’ to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit. Case 2: Address packet accepted – Write flag set The STATUS.DIR bit is cleared, indicating an I2C host write operation. The SCL line is forced low, stretching the bus clock. If an ACK is sent, the I2C client will wait for data to be received. Data, repeated start or stop can be received. If a NACK is sent, the I2C client will wait for a new Start condition and address match. Typically, software will immediately acknowledge the address packet by sending an ACK/NACK. The I2C client command CTRLB.CMD = 3 can be used for both read and write operation as the command execution is dependent on STATUS.DIR. Writing ‘1’ to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit.

28.6.2.5.2 Receiving Address Packets (SCLSM=1)

When SCLSM=1, the I2C client will stretch the SCL line only after an ACK, see Client Behavioral Diagram (SCLSM=1). When the I2C client is properly configured, it will wait for a Start condition to be detected. When a Start condition is detected, the successive address packet will be received and checked by the address match logic. If the received address is not a match, the packet will be rejected and the I2C client will wait for a new Start condition. If the address matches, the acknowledge action as configured by the Acknowledge Action bit Control B register (CTRLB.ACKACT) will be sent and the Address Match bit in the Interrupt Flag register (INTFLAG.AMATCH) is set. SCL will be stretched until the I2C client clears INTFLAG.AMATCH. As the I2C client holds the clock by forcing SCL low, the software is given unlimited time to respond to the address. The direction of a transaction is determined by reading the Read/Write Direction bit in the Status register (STATUS.DIR). This bit will be updated only when a valid address packet is received. If the Transmit Collision bit in the Status register (STATUS.COLL) is set, the last packet addressed to the I2C client had a packet collision. A collision causes the SDA and SCL lines to be released without any notification to software. The next AMATCH interrupt is, therefore, the first indication of the previous packet’s collision. Collisions are intended to follow the SMBus Address Resolution Protocol (ARP). After the address packet has been received from the I2C host, INTFLAG.AMATCH be set to ‘1’ to clear it. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 488

28.6.2.5.3 Receiving and Transmitting Data Packets

After the I2C client has received an address packet, it will respond according to the direction either by waiting for the data packet to be received or by starting to send a data packet by writing to DATA.DATA. When a data packet is received or sent, INTFLAG.DRDY will be set. After receiving data, the I2C client will send an acknowledge according to CTRLB.ACKACT. Case 1: Data received INTFLAG.DRDY is set, and SCL is held low, pending for SW interaction. Case 2: Data sent When a byte transmission is successfully completed, the INTFLAG.DRDY Interrupt flag is set. If NACK is received, indicated by STATUS.RXNACK=1, the I2C client must expect a stop or a repeated start to be received. The I2C client must release the data line to allow the I2C host to generate a stop or repeated start. Upon detecting a Stop condition, the Stop Received bit in the Interrupt Flag register (INTFLAG.PREC) will be set and the I2C client will return to IDLE state.

28.6.2.5.4 High-Speed Mode

When the I2C client is configured in High-speed mode (Hs, CTRLA.SPEED=0x2) and CTRLA.SCLSM=1, switching between Full-speed and High-speed modes is automatic. When the client recognizes a START followed by a host code transmission and a NACK, it automatically switches to High-speed mode and sets the High-speed status bit (STATUS.HS). The client will then remain in High-speed mode until a STOP is received. 28.6.2.5.5 10-Bit Addressing When 10-bit addressing is enabled (ADDR.TENBITEN=1), the two address bytes following a START will be checked against the 10-bit client address recognition. The first byte of the address will always be acknowledged, and the second byte will raise the address Interrupt flag, see 10-bit Addressing. If the transaction is a write, then the 10-bit address will be followed by N data bytes. If the operation is a read, the 10-bit address will be followed by a repeated START and reception of '11110 ADDR[9:8] 1', and the second address interrupt will be received with the DIR bit set. The client matches on the second address as it was addressed by the previous 10-bit address. Figure 28-12. 10-bit Addressing S AW addr[7:0] A11110 addr[9:8] Sr R S W S W 11110 addr[9:8] AMATCH INTERRUPT AMATCH INTERRUPT

28.6.2.5.6 PMBus Group Command

When the PMBus Group Command bit in the CTRLB register is set (CTRLB.GCMD=1) and 7-bit addressing is used, INTFLAG.PREC will be set if the client has been addressed since the last STOP condition. When CTRLB.GCMD=0, a STOP condition without address match will not be set INTFLAG.PREC. The group command protocol is used to send commands to more than one device. The commands are sent in one continuous transmission with a single STOP condition at the end. When the STOP condition is detected by the clients addressed during the group command, they all begin executing the command they received. The following figure shows an example where this client, bearing ADDRESS 1, is addressed after a repeated START condition. There can be multiple clients addressed before and after this client. Eventually, at the end of the group command, a single STOP is generated by the host. At this point a STOP interrupt is asserted. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 489

Figure 28-13. PMBus Group Command Example AS A n BytesWADDRESS 0 Command/Data ASr A n BytesW ADDRESS 1 (this client) Command/Data S W S W ASr A n BytesWADDRESS 2 Command/Data P S W AMATCH INTERRUPT DRDY INTERRUPT PREC INTERRUPT

28.6.3 Additional Features

28.6.3.1 SMBus

The I2C includes three hardware SCL low time-outs which allow a time-out to occur for SMBus SCL low time-out, host extend time-out, and client extend time-out. This allows for SMBus functionality These time-outs are driven by the GCLK_SERCOM_SLOW clock. The GCLK_SERCOM_SLOW clock is used to accurately time the time-out and must be configured to use a 32KHz oscillator. The I2C interface also allows for a SMBus compatible SDA hold time.

T TIMEOUT: SCL low time of 25..35ms – Measured for a single SCL low period. It is enabled by CTRLA.LOWTOUTEN.
T LOW:SEXT: Cumulative clock low extend time of 25 ms – Measured as the cumulative SCL low extend time by a client device in a single message from the initial START to the STOP. It is enabled by CTRLA.SEXTTOEN.
T LOW:MEXT: Cumulative clock low extend time of 10 ms – Measured as the cumulative SCL low extend time by the host device within a single byte from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. It is enabled by CTRLA.MEXTTOEN.

28.6.3.2 Smart Mode

The I2C interface has a smart mode that simplifies application code and minimizes the user interaction needed to adhere to the I2C protocol. The smart mode accomplishes this by automatically issuing an ACK or NACK (based on the content of CTRLB.ACKACT) as soon as DATA.DATA is read. 28.6.3.3 4-Wire Mode Writing a '1' to the Pin Usage bit in the Control A register (CTRLA.PINOUT) will enable 4-wire mode operation. In this mode, the internal I2C tri-state drivers are bypassed, and an external I2C compliant tri-state driver is needed when connecting to an I2C bus. Figure 28-14. I2C Pad Interface SCL/SDA pad I2C Driver SCL_OUT/ SDA_OUT padPINOUT PINOUT SCL_IN/ SDA_IN SCL_OUT/ SDA_OUT SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 490

28.6.3.4 Quick Command

Setting the Quick Command Enable bit in the Control B register (CTRLB.QCEN) enables quick command. When quick command is enabled, the corresponding Interrupt flag (INTFLAG.SB or INTFLAG.MB) is set immediately after the client acknowledges the address. At this point, the software can either issue a Stop command or a repeated start by writing CTRLB.CMD or ADDR.ADDR.

28.6.4 DMA, Interrupts and Events

Each interrupt source has its own Interrupt flag. The Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the Interrupt condition is meet. Each interrupt can be individually enabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the Interrupt flag is set and the corresponding interrupt is enabled. The interrupt request is active until the Interrupt flag is cleared, the interrupt is disabled or the I2C is reset. See the INTFLAG (Client) or INTFLAG (Host) register for details on how to clear Interrupt flags. Table 28-1. Module Request for SERCOM I2C Client Condition Request DMA Interrupt Event Data needed for transmit (TX) (Client Transmit mode) Yes (request cleared when data is written) NA Data received (RX) (Client Receive mode) Yes (request cleared when data is read) Data Ready (DRDY) Yes Address Match (AMATCH) Yes Stop received (PREC) Yes Error (ERROR) Yes Table 28-2. Module Request for SERCOM I2C Host Condition Request DMA Interrupt Event Data needed for transmit (TX) (Host Transmit mode) Yes (request cleared when data is written) NA Data needed for transmit (RX) (Host Transmit mode) Yes (request cleared when data is read) Host on Bus (MB) Yes Stop received (SB) Yes Error (ERROR) Yes

28.6.4.1 DMA Operation

Smart mode must be enabled for DMA operation in the Control B register by writing CTRLB.SMEN=1. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 491

28.6.4.1.1 Client DMA

When using the I2C client with DMA, an address match will cause the address Interrupt flag (INTFLAG.ADDRMATCH) to be raised. After the interrupt has been serviced, data transfer will be performed through DMA. The I2C client generates the following requests:

Write data received (RX): The request is set when host write data is received. The request is cleared when DATA is read.
Read data needed for transmit (TX): The request is set when data is needed for a host read operation. The request is cleared when DATA is written.

28.6.4.1.2 Host DMA

When using the I2C host with DMA, the ADDR register must be written with the desired address (ADDR.ADDR), transaction length (ADDR.LEN), and transaction length enable (ADDR.LENEN). When ADDR.LENEN is written to 1 along with ADDR.ADDR, ADDR.LEN determines the number of data bytes in the transaction from 0 to 255. DMA is then used to transfer ADDR.LEN bytes followed by an automatically generated NACK (for host reads) and a STOP. If a NACK is received by the client for a host write transaction before ADDR.LEN bytes, a STOP will be automatically generated and the length error (STATUS.LENERR) will be raised along with the INTFLAG.ERROR interrupt. The I2C host generates the following requests:

Read data received (RX): The request is set when host read data is received. The request is cleared when DATA is read.
Write data needed for transmit (TX): The request is set when data is needed for a host write operation. The request is cleared when DATA is written.

28.6.4.2 Interrupts

The I2C client has the following interrupt sources. These are asynchronous interrupts. They can wake-up the device from any Sleep mode:

Error (ERROR)
Data Ready (DRDY)
Address Match (AMATCH)
Stop Received (PREC) The I2C host has the following interrupt sources. These are asynchronous interrupts. They can wake-up the device from any Sleep mode:
Error (ERROR)
Client on Bus (SB)
Host on Bus (MB) Each interrupt source has its own Interrupt flag. The Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the Interrupt condition is meet. Each interrupt can be individually enabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). The status of enabled interrupts can be read from either INTENSET or INTENCLR. An interrupt request is generated when the Interrupt flag is set and the corresponding interrupt is enabled. The interrupt request active until the Interrupt flag is cleared, the interrupt is disabled or the I2C is reset. See the INTFLAG register for details on how to clear Interrupt flags. The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for interrupt requests. Refer to Nested Vector Interrupt Controller for details. Related Links

28.6.4.3 Events

28.6.5 Sleep Mode Operation

The generic clock (GCLK_SERCOMx_CORE) will continue to run in idle sleep mode. If the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY) is '1', the GLK_SERCOMx_CORE will also run in Standby Sleep mode. Any interrupt can wake-up the device. If CTRLA.RUNSTDBY=0, the GLK_SERCOMx_CORE will be disabled after any ongoing transaction is finished. Any interrupt can wake-up the device. I2C Client Operation Writing CTRLA.RUNSTDBY=1 will allow the Address Match interrupt to wake-up the device. When CTRLA.RUNSTDBY=0, all receptions will be dropped.

28.6.6 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written:

Software Reset bit in the CTRLA register (CTRLA.SWRST)
Enable bit in the CTRLA register (CTRLA.ENABLE)
Command bits in CTRLB register (CTRLB.CMD)
Write to Bus State bits in the Status register (STATUS.BUSSTATE)
Address bits in the Address register (ADDR.ADDR) when in host operation. The following registers are synchronized when written:
Data (DATA) when in host operation Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Related Links

28.7 Register Summary - I2C Client

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 RUNSTDBY MODE[2:0] ENABLE SWRST 15:8 23:16 SEXTTOEN SDAHOLD[1:0] PINOUT 31:24 LOWTOUTEN SCLSM SPEED[1:0] 0x04 CTRLB 7:0 15:8 AMODE[1:0] AACKEN GCMD SMEN 23:16 ACKACT CMD[1:0] 31:24 0x08 ... 0x13 Reserved 0x14 INTENCLR 7:0 ERROR DRDY AMATCH PREC 0x15 Reserved 0x16 INTENSET 7:0 ERROR DRDY AMATCH PREC 0x17 Reserved 0x18 INTFLAG 7:0 ERROR DRDY AMATCH PREC 0x19 Reserved 0x1A STATUS 7:0 CLKHOLD LOWTOUT SR DIR RXNACK COLL BUSERR 15:8 HS SEXTTOUT 0x1C SYNCBUSY 7:0 ENABLE SWRST 15:8 23:16 31:24 0x20 ... 0x23 Reserved 0x24 ADDR 7:0 ADDR[6:0] GENCEN 15:8 TENBITEN ADDR[9:7] 23:16 ADDRMASK[6:0] 31:24 ADDRMASK[9:7] 0x28 DATA 7:0 DATA[7:0] 15:8

28.8 Register Description - I2C Client

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write- protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to Register Access Protection. Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write- Synchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to 28.6.6 Synchronization. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 494

28.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 LOWTOUTEN SCLSM SPEED[1:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SEXTTOEN SDAHOLD[1:0] PINOUT Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 RUNSTDBY MODE[2:0] ENABLE SWRST Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 30 – LOWTOUTEN SCL Low Time-Out This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the client will release its clock hold, if enabled, and reset the internal state machine. Any interrupt flags set at the time of time-out will remain set. This bit is not synchronized. Value Description 0 Time-out disabled. 1 Time-out enabled. Bit 27 – SCLSM SCL Clock Stretch Mode This bit controls when SCL will be stretched for software interaction. This bit is not synchronized. Value Description

0 SCL stretch according to Figure 28-10

1 SCL stretch only after ACK bit according to Figure 28-11

This bit is not synchronized. Value Description

0 Time-out disabled

1 Time-out enabled

Bits 21:20 – SDAHOLD[1:0] SDA Hold Time These bits define the SDA hold time with respect to the negative edge of SCL. These bits are not synchronized. Value Name Description 0x0 DIS Disabled 0x1 75 50-100ns hold time 0x2 450 300-600ns hold time 0x3 600 400-800ns hold time Bit 16 – PINOUT Pin Usage This bit sets the pin usage to either two- or four-wire operation: This bit is not synchronized. Value Description 0 4-wire operation disabled 1 4-wire operation enabled Bit 7 – RUNSTDBY Run in Standby This bit defines the functionality in standby sleep mode. This bit is not synchronized. Value Description 0 Disabled – All reception is dropped. 1 Wake on address match, if enabled. Bits 4:2 – MODE[2:0] Operating Mode These bits must be written to 0x04 to select the I2C client serial communication interface of the SERCOM. These bits are not synchronized. Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not enable-protected. Value Description 0 The peripheral is disabled or being disabled. 1 The peripheral is enabled. Bit 0 – SWRST Software Reset Writing '0' to this bit has no effect. Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Value Description 0 There is no reset operation ongoing. 1 The reset operation is ongoing. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 496

28.8.2 Control B

Name: CTRLB Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 ACKACT CMD[1:0] Access R/W W W Reset 0 0 0 Bit 15 14 13 12 11 10 9 8 AMODE[1:0] AACKEN GCMD SMEN Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Access Reset Bit 18 – ACKACT Acknowledge Action This bit defines the client's acknowledge behavior after an address or data byte is received from the host. The acknowledge action is executed when a command is written to the CMD bits. If smart mode is enabled (CTRLB.SMEN=1), the acknowledge action is performed when the DATA register is read. ACKACT shall not be updated more than once between each peripheral interrupts request. This bit is not enable-protected. Value Description

0 Send ACK

1 Send NACK

Bits 17:16 – CMD[1:0] Command This bit field triggers the client operation as the below. The CMD bits are strobe bits, and always read as zero. The operation is dependent on the client interrupt flags, INTFLAG.DRDY and INTFLAG.AMATCH, in addition to STATUS.DIR. All interrupt flags (INTFLAG.DRDY, INTFLAG.AMATCH and INTFLAG.PREC) are automatically cleared when a command is given. This bit is not enable-protected. Table 28-3. Command Description CMD[1:0] DIR Action 0x0 X (No action) 0x1 X (Reserved) 0x2 Used to complete a transaction in response to a data interrupt (DRDY) 0 (Host write) Execute acknowledge action succeeded by waiting for any start (S/Sr) condition 1 (Host read) Wait for any start (S/Sr) condition SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 497

CMD[1:0] DIR Action 0x3 Used in response to an address interrupt (AMATCH) 0 (Host write) Execute acknowledge action succeeded by reception of next byte 1 (Host read) Execute acknowledge action succeeded by client data interrupt Used in response to a data interrupt (DRDY) 0 (Host write) Execute acknowledge action succeeded by reception of next byte 1 (Host read) Execute a byte read operation followed by ACK/NACK reception Bits 15:14 – AMODE[1:0] Address Mode These bits set the addressing mode. Value Name Description 0x0 MASK The client responds to the address written in ADDR.ADDR masked by the value in ADDR.ADDRMASK. See SERCOM – Serial Communication Interface for additional information. 0x1 2_ADDRS The client responds to the two unique addresses in ADDR.ADDR and ADDR.ADDRMASK. 0x2 RANGE The client responds to the range of addresses between and including ADDR.ADDR and ADDR.ADDRMASK. ADDR.ADDR is the upper limit. 0x3 - Reserved. Bit 10 – AACKEN Automatic Acknowledge Enable This bit enables the address to be automatically acknowledged if there is an address match. Value Description 0 Automatic acknowledge is disabled. 1 Automatic acknowledge is enabled. Bit 9 – GCMD PMBus Group Command This bit enables PMBus group command support. When enabled, the Stop Received interrupt flag (INTFLAG.PREC) will be set when a STOP condition is detected if the client has been addressed since the last STOP condition on the bus. Value Description 0 Group command is disabled. 1 Group command is enabled. Bit 8 – SMEN Smart Mode Enable When smart mode is enabled, data is acknowledged automatically when DATA.DATA is read. Value Description 0 Smart mode is disabled. 1 Smart mode is enabled. Related Links 25. SERCOM – Serial Communication Interface SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 498

28.8.3 Interrupt Enable Clear

Name: INTENCLR Offset: 0x14 Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 5 4 3 2 1 0 ERROR DRDY AMATCH PREC Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 – ERROR Error Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. Value Description 0 Error interrupt is disabled. 1 Error interrupt is enabled. Bit 2 – DRDY Data Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Data Ready bit, which disables the Data Ready interrupt. Value Description 0 The Data Ready interrupt is disabled. 1 The Data Ready interrupt is enabled. Bit 1 – AMATCH Address Match Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Address Match Interrupt Enable bit, which disables the Address Match interrupt. Value Description 0 The Address Match interrupt is disabled. 1 The Address Match interrupt is enabled. Bit 0 – PREC Stop Received Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Stop Received Interrupt Enable bit, which disables the Stop Received interrupt. Value Description 0 The Stop Received interrupt is disabled. 1 The Stop Received interrupt is enabled. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 499

28.8.4 Interrupt Enable Set

Name: INTENSET Offset: 0x16 Reset: 0x00 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 5 4 3 2 1 0 ERROR DRDY AMATCH PREC Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 – ERROR Error Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. Value Description 0 Error interrupt is disabled. 1 Error interrupt is enabled. Bit 2 – DRDY Data Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Data Ready bit, which enables the Data Ready interrupt. Value Description 0 The Data Ready interrupt is disabled. 1 The Data Ready interrupt is enabled. Bit 1 – AMATCH Address Match Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Address Match Interrupt Enable bit, which enables the Address Match interrupt. Value Description 0 The Address Match interrupt is disabled. 1 The Address Match interrupt is enabled. Bit 0 – PREC Stop Received Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Stop Received Interrupt Enable bit, which enables the Stop Received interrupt. Value Description 0 The Stop Received interrupt is disabled. 1 The Stop Received interrupt is enabled. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 500

28.8.5 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x18 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 ERROR DRDY AMATCH PREC Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 – ERROR Error This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS register. The corresponding bits in STATUS are SEXTTOUT, LOWTOUT, COLL, and BUSERR. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 2 – DRDY Data Ready This flag is set when a I2C client byte transmission or reception is successfully completed. The flag is cleared by hardware when either:

Writing to the DATA register.
Reading the DATA register with Smart mode enabled.
Writing a valid command to the CMD register. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Data Ready Interrupt flag. Bit 1 – AMATCH Address Match This flag is set when the I2C client address match logic detects that a valid address has been received. The flag is cleared by hardware when CTRL.CMD is written. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Address Match Interrupt flag. When cleared, an ACK/NACK will be sent according to CTRLB.ACKACT. Bit 0 – PREC Stop Received This flag is set when a Stop condition is detected for a transaction being processed. A Stop condition detected between a bus host and another client will not set this flag, unless the PMBus Group Command is enabled in the Control B register (CTRLB.GCMD=1). This flag is cleared by hardware after a command is issued on the next address match. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Stop Received Interrupt flag. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 501

28.8.6 Status

Name: STATUS Offset: 0x1A Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 HS SEXTTOUT Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 CLKHOLD LOWTOUT SR DIR RXNACK COLL BUSERR Access R R/W R R R R/W R/W Reset 0 0 0 0 0 0 0 Bit 10 – HS High-speed This bit is set if the client detects a START followed by a Host Code transmission. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the status. However, this flag is automatically cleared when a STOP is received. Bit 9 – SEXTTOUT Client SCL Low Extend Time-Out This bit is set if a client SCL low extend time-out occurs. This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD) or when INTFLAG.AMATCH is cleared. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the status. Value Description 0 No SCL low extend time-out has occurred. 1 SCL low extend time-out has occurred. Bit 7 – CLKHOLD Clock Hold The client Clock Hold bit (STATUS.CLKHOLD) is set when the client is holding the SCL line low, stretching the I2C clock. Software should consider this bit a read-only status flag that is set when INTFLAG.DRDY or INTFLAG.AMATCH is set. This bit is automatically cleared when the corresponding interrupt is also cleared. Bit 6 – LOWTOUT SCL Low Time-out This bit is set if an SCL low time-out occurs. This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD) or when INTFLAG.AMATCH is cleared. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the status. Value Description 0 No SCL low time-out has occurred. 1 SCL low time-out has occurred. Bit 4 – SR Repeated Start When INTFLAG.AMATCH is raised due to an address match, SR indicates a repeated start or start condition. This flag is only valid while the INTFLAG.AMATCH flag is one. Value Description

0 Start condition on last address match

1 Repeated start condition on last address match

Bit 3 – DIR Read / Write Direction The Read/Write Direction (STATUS.DIR) bit stores the direction of the last address packet received from a host. Value Description 0 Host write operation is in progress. 1 Host read operation is in progress. Bit 2 – RXNACK Received Not Acknowledge This bit indicates whether the last data packet sent was acknowledged or not. Value Description 0 Host responded with ACK. 1 Host responded with NACK. Bit 1 – COLL Transmit Collision If set, the I2C client was not able to transmit a high data or NACK bit, the I2C client will immediately release the SDA and SCL lines and wait for the next packet addressed to it. This flag is intended for the SMBus address resolution protocol (ARP). A detected collision in non-ARP situations indicates that there has been a protocol violation, and should be treated as a bus error. Note that this status will not trigger any interrupt, and should be checked by software to verify that the data were sent correctly. This bit is cleared automatically if responding to an address match with an ACK or a NACK (writing 0x3 to CTRLB.CMD), or INTFLAG.AMATCH is cleared. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the status. Value Description 0 No collision detected on last data byte sent. 1 Collision detected on last data byte sent. Bit 0 – BUSERR Bus Error The Bus Error bit (STATUS.BUSERR) indicates that an illegal bus condition has occurred on the bus, regardless of bus ownership. An illegal bus condition is detected if a protocol violating start, repeated start or stop is detected on the I2C bus lines. A start condition directly followed by a stop condition is one example of a protocol violation. If a time-out occurs during a frame, this is also considered a protocol violation, and will set STATUS.BUSERR. This bit is cleared automatically if responding to an address match with an ACK or a NACK (writing 0x3 to CTRLB.CMD) or INTFLAG.AMATCH is cleared. Writing a '1' to this bit will clear the status. Writing a '0' to this bit has no effect. Value Description 0 No bus error detected. 1 Bus error detected. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 503

28.8.7 Synchronization Busy

Name: SYNCBUSY Offset: 0x1C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ENABLE SWRST Access R R Reset 0 0 Bit 1 – ENABLE SERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNCBUSY.ENABLE bit will be set until synchronization is complete. Value Description 0 Enable synchronization is not busy. 1 Enable synchronization is busy. Bit 0 – SWRST Software Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will be set until synchronization is complete. Value Description 0 SWRST synchronization is not busy. 1 SWRST synchronization is busy. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 504

28.8.8 Address

Name: ADDR Offset: 0x24 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 ADDRMASK[9:7] Access R/W R/W R/W Reset 0 0 0 Bit 23 22 21 20 19 18 17 16 ADDRMASK[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 TENBITEN ADDR[9:7] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[6:0] GENCEN Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 26:17 – ADDRMASK[9:0] Address Mask These bits act as a second address match register, an address mask register or the lower limit of an address range, depending on the CTRLB.AMODE setting. Bit 15 – TENBITEN Ten Bit Addressing Enable Value Description 0 10-bit address recognition disabled. 1 10-bit address recognition enabled. Bits 10:1 – ADDR[9:0] Address These bits contain the I2C client address used by the client address match logic to determine if a host has addressed the client. When using 7-bit addressing, the client address is represented by ADDR[6:0]. When using 10-bit addressing (ADDR.TENBITEN=1), the client address is represented by ADDR[9:0] When the address match logic detects a match, INTFLAG.AMATCH is set and STATUS.DIR is updated to indicate whether it is a read or a write transaction. Bit 0 – GENCEN General Call Address Enable A general call address is an address consisting of all-zeroes, including the direction bit (host write). Value Description 0 General call address recognition disabled. 1 General call address recognition enabled. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 505

28.8.9 Data

Name: DATA Offset: 0x28 Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – DATA[7:0] Data The client data register I/O location (DATA.DATA) provides access to the host transmit and receive data buffers. Reading valid data or writing data to be transmitted can be successfully done only when SCL is held low by the client (STATUS.CLKHOLD is set). An exception occurs when reading the last data byte after the stop condition has been received. Accessing DATA.DATA auto-triggers I2C bus operations. The operation performed depends on the state of CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write). SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 506

28.9 Register Summary - I2C Host

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 RUNSTDBY MODE[2:0] ENABLE SWRST 15:8 23:16 SEXTTOEN MEXTTOEN SDAHOLD[1:0] PINOUT 31:24 LOWTOUTEN INACTOUT[1:0] SCLSM SPEED[1:0] 0x04 CTRLB 7:0 15:8 QCEN SMEN 23:16 ACKACT CMD[1:0] 31:24 0x08 ... 0x0B Reserved 0x0C BAUD 7:0 BAUD[7:0] 15:8 BAUDLOW[7:0] 23:16 HSBAUD[7:0] 31:24 HSBAUDLOW[7:0] 0x10 ... 0x13 Reserved 0x14 INTENCLR 7:0 ERROR SB MB 0x15 Reserved 0x16 INTENSET 7:0 ERROR SB MB 0x17 Reserved 0x18 INTFLAG 7:0 ERROR SB MB 0x19 Reserved 0x1A STATUS 7:0 CLKHOLD LOWTOUT BUSSTATE[1:0] RXNACK ARBLOST BUSERR 15:8 LENERR SEXTTOUT MEXTTOUT 0x1C SYNCBUSY 7:0 SYSOP ENABLE SWRST 15:8 23:16 31:24 0x20 ... 0x23 Reserved 0x24 ADDR 7:0 ADDR[7:0] 15:8 TENBITEN HS LENEN ADDR[10:8] 23:16 LEN[7:0] 31:24 0x28 DATA 7:0 DATA[7:0] 15:8 0x2A ... 0x2F Reserved 0x30 DBGCTRL 7:0 DBGSTOP

28.10 Register Description - I2C Host

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write- protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 28.5.8 Register Access Protection. Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write- Synchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to 28.6.6 Synchronization. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 507

Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 508

28.10.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 LOWTOUTEN INACTOUT[1:0] SCLSM SPEED[1:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SEXTTOEN MEXTTOEN SDAHOLD[1:0] PINOUT Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 RUNSTDBY MODE[2:0] ENABLE SWRST Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 30 – LOWTOUTEN SCL Low Time-Out This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the host will release its clock hold, if enabled, and complete the current transaction. A stop condition will automatically be transmitted. INTFLAG.SB or INTFLAG.MB will be set as normal, but the clock hold will be released. The STATUS.LOWTOUT and STATUS.BUSERR status bits will be set. This bit is not synchronized. Value Description 0 Time-out disabled. 1 Time-out enabled. Bits 29:28 – INACTOUT[1:0] Inactive Time-Out If the inactive bus time-out is enabled and the bus is inactive for longer than the time-out setting, the bus state logic will be set to idle. An inactive bus arise when either an I2C host or client is holding the SCL low. Enabling this option is necessary for SMBus compatibility, but can also be used in a non-SMBus set-up. Calculated time-out periods are based on a 100kHz baud rate. These bits are not synchronized. Value Name Description 0x0 DIS Disabled 0x1 55US 5-6 SCL cycle time-out (50-60µs) 0x2 105US 10-11 SCL cycle time-out (100-110µs) 0x3 205US 20-21 SCL cycle time-out (200-210µs) Bit 27 – SCLSM SCL Clock Stretch Mode This bit controls when SCL will be stretched for software interaction. This bit is not synchronized. Value Description 0 SCL stretch according to Figure 28-5. 1 SCL stretch only after ACK bit, Figure 28-6. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 509

Bits 25:24 – SPEED[1:0] Transfer Speed These bits define bus speed. These bits are not synchronized. Value Description 0x0 Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz 0x1 Fast-mode Plus (Fm+) up to 1 MHz 0x2 High-speed mode (Hs-mode) up to 3.4 MHz 0x3 Reserved Bit 23 – SEXTTOEN Client SCL Low Extend Time-Out This bit enables the client SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the host will release its clock hold if enabled, and complete the current transaction. A STOP will automatically be transmitted. SB or MB will be set as normal, but CLKHOLD will be release. The MEXTTOUT and BUSERR status bits will be set. This bit is not synchronized. Value Description Bit 22 – MEXTTOEN Host SCL Low Extend Time-Out This bit enables the host SCL low extend time-out. If SCL is cumulatively held low for greater than 10ms from START-to-ACK, ACK-to-ACK, or ACK-to-STOP the host will release its clock hold if enabled, and complete the current transaction. A STOP will automatically be transmitted. SB or MB will be set as normal, but CLKHOLD will be released. The MEXTTOUT and BUSERR status bits will be set. This bit is not synchronized. Value Description Bits 21:20 – SDAHOLD[1:0] SDA Hold Time These bits define the SDA hold time with respect to the negative edge of SCL. These bits are not synchronized. Value Name Description 0x0 DIS Disabled 0x1 75NS 50-100ns hold time 0x2 450NS 300-600ns hold time 0x3 600NS 400-800ns hold time Bit 16 – PINOUT Pin Usage This bit set the pin usage to either two- or four-wire operation: This bit is not synchronized. Value Description 0 4-wire operation disabled. 1 4-wire operation enabled. Bit 7 – RUNSTDBY Run in Standby This bit defines the functionality in standby sleep mode. This bit is not synchronized. Value Description 0 GCLK_SERCOMx_CORE is disabled and the I2C host will not operate in standby sleep mode. 1 GCLK_SERCOMx_CORE is enabled in all sleep modes. Bits 4:2 – MODE[2:0] Operating Mode These bits must be written to 0x5 to select the I2C host serial communication interface of the SERCOM. These bits are not synchronized. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 510

Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the Synchronization Enable Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not enable-protected. Value Description 0 The peripheral is disabled or being disabled. 1 The peripheral is enabled. Bit 0 – SWRST Software Reset Writing '0' to this bit has no effect. Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register. Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Value Description 0 There is no reset operation ongoing. 1 The reset operation is ongoing. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 511

28.10.2 Control B

Name: CTRLB Offset: 0x04 Reset: 0x00000000 Property: PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 ACKACT CMD[1:0] Access R/W W W Reset 0 0 0 Bit 15 14 13 12 11 10 9 8 QCEN SMEN Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 Access Reset Bit 18 – ACKACT Acknowledge Action This bit defines the I2C host's acknowledge behavior after a data byte is received from the I2C client. The acknowledge action is executed when a command is written to CTRLB.CMD, or if Smart mode is enabled (CTRLB.SMEN is written to one), when DATA.DATA is read. This bit is not enable-protected. This bit is not write-synchronized. Value Description 0 Send ACK. 1 Send NACK. Bits 17:16 – CMD[1:0] Command Writing these bits triggers a host operation as described below. The CMD bits are strobe bits, and always read as zero. The acknowledge action is only valid in Host Read mode. In Host Write mode, a command will only result in a repeated Start or Stop condition. The CTRLB.ACKACT bit and the CMD bits can be written at the same time, and then the acknowledge action will be updated before the command is triggered. Commands can only be issued when either the Client on Bus Interrupt flag (INTFLAG.SB) or Host on Bus Interrupt flag (INTFLAG.MB) is '1'. If CMD 0x1 is issued, a repeated start will be issued followed by the transmission of the current address in ADDR.ADDR. If another address is desired, ADDR.ADDR must be written instead of the CMD bits. This will trigger a repeated start followed by transmission of the new address. Issuing a command will set the System Operation bit in the Synchronization Busy register (SYNCBUSY.SYSOP). Table 28-4. Command Description CMD[1:0] Direction Action 0x0 X (No action) 0x1 X Execute acknowledge action succeeded by repeated Start 0x2 0 (Write) No operation 1 (Read) Execute acknowledge action succeeded by a byte read operation 0x3 X Execute acknowledge action succeeded by issuing a Stop condition SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 512

These bits are not enable-protected. Bit 9 – QCEN Quick Command Enable This bit is not write-synchronized. Value Description 0 Quick Command is disabled. 1 Quick Command is enabled. Bit 8 – SMEN Smart Mode Enable When Smart mode is enabled, acknowledge action is sent when DATA.DATA is read. This bit is not write-synchronized. Value Description 0 Smart mode is disabled. 1 Smart mode is enabled. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 513

28.10.3 Baud Rate

Name: BAUD Offset: 0x0C Reset: 0x0000 Property: PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 HSBAUDLOW[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 HSBAUD[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 BAUDLOW[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BAUD[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:24 – HSBAUDLOW[7:0] High Speed Host Baud Rate Low HSBAUDLOW non-zero: HSBAUDLOW indicates the SCL low time in High-speed mode according to HSBAUDLOW = f GCLK ⋅ T LOW − 1 HSBAUDLOW equal to zero: The HSBAUD register is used to time TLOW, THIGH, TSU;STO, THD;STA and TSU;STA.. TBUF is timed by the BAUD register. Bits 23:16 – HSBAUD[7:0] High Speed Host Baud Rate This bit field indicates the SCL high time in High-speed mode according to the following formula. When HSBAUDLOW is zero, TLOW, THIGH, TSU;STO, THD;STA and TSU;STA are derived using this formula. TBUF is timed by the BAUD register. HSBAUD = f GCLK ⋅ T HIGH − 1 Bits 15:8 – BAUDLOW[7:0] Host Baud Rate Low If this bit field is non-zero, the SCL low time will be described by the value written. For more information on how to calculate the frequency, see SERCOM 25.6.2.3 Clock Generation – Baud-Rate Generator. Bits 7:0 – BAUD[7:0] Host Baud Rate This bit field is used to derive the SCL high time if BAUD.BAUDLOW is non-zero. If BAUD.BAUDLOW is zero, BAUD will be used to generate both high and low periods of the SCL. For more information on how to calculate the frequency, see SERCOM 25.6.2.3 Clock Generation – Baud-Rate Generator. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 514

28.10.4 Interrupt Enable Clear

28.10.5 Interrupt Enable Set

Name: INTENSET Offset: 0x16 Reset: 0x00 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 5 4 3 2 1 0 ERROR SB MB Access R/W R/W R/W Reset 0 0 0 Bit 7 – ERROR Error Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. Value Description 0 Error interrupt is disabled. 1 Error interrupt is enabled. Bit 1 – SB Client on Bus Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Client on Bus Interrupt Enable bit, which enables the Client on Bus interrupt. Value Description 0 The Client on Bus interrupt is disabled. 1 The Client on Bus interrupt is enabled. Bit 0 – MB Host on Bus Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Host on Bus Interrupt Enable bit, which enables the Host on Bus interrupt. Value Description 0 The Host on Bus interrupt is disabled. 1 The Host on Bus interrupt is enabled. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 516

28.10.6 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x18 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 ERROR SB MB Access R/W R/W R/W Reset 0 0 0 Bit 7 – ERROR Error This flag is cleared by writing '1' to it. This bit is set when any error is detected. Errors that will set this flag have corresponding status bits in the STATUS register. These status bits are LENERR, SEXTTOUT, MEXTTOUT, LOWTOUT, ARBLOST, and BUSERR. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 1 – SB Client on Bus The Client on Bus flag (SB) is set when a byte is successfully received in Host Read mode, for example, no arbitration lost or bus error occurred during the operation. When this flag is set, the host forces the SCL line low, stretching the I2C clock period. The SCL line will be released and SB will be cleared on one of the following actions:

Writing to ADDR.ADDR
Writing to DATA.DATA
Reading DATA.DATA when Smart mode is enabled (CTRLB.SMEN)
Writing a valid command to CTRLB.CMD Writing '1' to this bit location will clear the SB flag. The transaction will not continue or be terminated until one of the above actions is performed. Writing '0' to this bit has no effect. Bit 0 – MB Host on Bus This flag is set when a byte is transmitted in Host Write mode. The flag is set regardless of the occurrence of a bus error or an Arbitration Lost condition. MB is also set when arbitration is lost during sending of NACK in Host Read mode, or when issuing a Start condition if the bus state is unknown. When this flag is set and arbitration is not lost, the host forces the SCL line low, stretching the I2C clock period. The SCL line will be released and MB will be cleared on one of the following actions:
Writing to ADDR.ADDR
Writing to DATA.DATA
Reading DATA.DATA when Smart mode is enabled (CTRLB.SMEN)
Writing a valid command to CTRLB.CMD Writing '1' to this bit location will clear the MB flag. The transaction will not continue or be terminated until one of the above actions is performed. Writing '0' to this bit has no effect. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 517

28.10.7 Status

Name: STATUS Offset: 0x1A Reset: 0x0000 Property: Write-Synchronized Bit 15 14 13 12 11 10 9 8 LENERR SEXTTOUT MEXTTOUT Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 CLKHOLD LOWTOUT BUSSTATE[1:0] RXNACK ARBLOST BUSERR Access R R/W R/W R/W R R/W R/W Reset 0 0 0 0 0 0 0 Bit 10 – LENERR Transaction Length Error This bit is set when automatic length is used for a DMA transaction and the client sends a NACK before ADDR.LEN bytes have been written by the host. Writing '1' to this bit location will clear STATUS.LENERR. This flag is automatically cleared when writing to the ADDR register. Writing '0' to this bit has no effect. This bit is not write-synchronized. Bit 9 – SEXTTOUT Client SCL Low Extend Time-Out This bit is set if a client SCL low extend time-out occurs. This bit is automatically cleared when writing to the ADDR register. Writing '1' to this bit location will clear SEXTTOUT. Normal use of the I2C interface does not require the SEXTTOUT flag to be cleared by this method. Writing '0' to this bit has no effect. This bit is not write-synchronized. Bit 8 – MEXTTOUT Host SCL Low Extend Time-Out This bit is set if a Host SCL low time-out occurs. Writing '1' to this bit location will clear STATUS.MEXTTOUT. This flag is automatically cleared when writing to the ADDR register. Writing '0' to this bit has no effect. This bit is not write-synchronized. Bit 7 – CLKHOLD Clock Hold This bit is set when the host is holding the SCL line low, stretching the I2C clock. Software should consider this bit when INTFLAG.SB or INTFLAG.MB is set. This bit is cleared when the corresponding Interrupt flag is cleared and the next operation is given. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. This bit is not write-synchronized. Bit 6 – LOWTOUT SCL Low Time-Out This bit is set if an SCL low time-out occurs. Writing '1' to this bit location will clear this bit. This flag is automatically cleared when writing to the ADDR register. Writing '0' to this bit has no effect. This bit is not write-synchronized. Bits 5:4 – BUSSTATE[1:0] Bus State These bits indicate the current I2C Bus state. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 518

When in UNKNOWN state, writing 0x1 to BUSSTATE forces the bus state into the IDLE state. The bus state cannot be forced into any other state. Writing BUSSTATE to idle will set SYNCBUSY.SYSOP. Value Name Description 0x0 UNKNOWN The Bus state is unknown to the I2C host and will wait for a Stop condition to be detected or wait to be forced into an Idle state by software 0x1 IDLE The Bus state is waiting for a transaction to be initialized 0x2 OWNER The I2C host is the current owner of the bus 0x3 BUSY Some other I2C host owns the bus Bit 2 – RXNACK Received Not Acknowledge This bit indicates whether the last address or data packet sent was acknowledged or not. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. This bit is not write-synchronized. Value Description 0 Client responded with ACK. 1 Client responded with NACK. Bit 1 – ARBLOST Arbitration Lost This bit is set if arbitration is lost while transmitting a high data bit or a NACK bit, or while issuing a Start or Repeated Start condition on the bus. The Host on Bus Interrupt flag (INTFLAG.MB) will be set when STATUS.ARBLOST is set. Writing the ADDR.ADDR register will automatically clear STATUS.ARBLOST. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. This bit is not write-synchronized. Bit 0 – BUSERR Bus Error This bit indicates that an illegal Bus condition has occurred on the bus, regardless of bus ownership. An illegal Bus condition is detected if a protocol violating start, repeated start or stop is detected on the I2C bus lines. A Start condition directly followed by a Stop condition is one example of a protocol violation. If a time-out occurs during a frame, this is also considered a protocol violation, and will set BUSERR. If the I2C host is the bus owner at the time a bus error occurs, STATUS.ARBLOST and INTFLAG.MB will be set in addition to BUSERR. Writing the ADDR.ADDR register will automatically clear the BUSERR flag. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. This bit is not write-synchronized. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 519

28.10.8 Synchronization Busy

Name: SYNCBUSY Offset: 0x1C Reset: 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 SYSOP ENABLE SWRST Access R R R Reset 0 0 0 Bit 2 – SYSOP System Operation Synchronization Busy Writing CTRLB.CMD, STATUS.BUSSTATE, ADDR, or DATA when the SERCOM is enabled requires synchronization. When written, the SYNCBUSY.SYSOP bit will be set until synchronization is complete. Value Description 0 System operation synchronization is not busy. 1 System operation synchronization is busy. Bit 1 – ENABLE SERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNCBUSY.ENABLE bit will be set until synchronization is complete. Value Description 0 Enable synchronization is not busy. 1 Enable synchronization is busy. Bit 0 – SWRST Software Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will be set until synchronization is complete. Value Description 0 SWRST synchronization is not busy. 1 SWRST synchronization is busy. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 520

28.10.9 Address

Name: ADDR Offset: 0x24 Reset: 0x0000 Property: Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 LEN[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 TENBITEN HS LENEN ADDR[10:8] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 23:16 – LEN[7:0] Transaction Length These bits define the transaction length of a DMA transaction from 0 to 255 bytes. The Transfer Length Enable (LENEN) bit must be written to '1' in order to use DMA. Bit 15 – TENBITEN Ten Bit Addressing Enable This bit enables 10-bit addressing. This bit can be written simultaneously with ADDR to indicate a 10-bit or 7-bit address transmission. Value Description 0 10-bit addressing disabled. 1 10-bit addressing enabled. Bit 14 – HS High Speed This bit enables High-speed mode for the current transfer from repeated START to STOP. This bit can be written simultaneously with ADDR for a high speed transfer. Value Description 0 High-speed transfer disabled. 1 High-speed transfer enabled. Bit 13 – LENEN Transfer Length Enable Value Description 0 Automatic transfer length disabled. 1 Automatic transfer length enabled. Bits 10:0 – ADDR[10:0] Address When ADDR is written, the consecutive operation will depend on the bus state: UNKNOWN: INTFLAG.MB and STATUS.BUSERR are set, and the operation is terminated. BUSY: The I2C host will await further operation until the bus becomes IDLE. IDLE: The I2C host will issue a start condition followed by the address written in ADDR. If the address is acknowledged, SCL is forced and held low, and STATUS.CLKHOLD and INTFLAG.MB are set. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 521

OWNER: A repeated start sequence will be performed. If the previous transaction was a read, the acknowledge action is sent before the repeated start bus condition is issued on the bus. Writing ADDR to issue a repeated start is performed while INTFLAG.MB or INTFLAG.SB is set. The ADDR register can be read at any time without interfering with ongoing bus activity, as a read access does not trigger the host logic to perform any bus protocol related operations. The I2C host control logic uses bit 0 of ADDR as the bus protocol’s read/write flag (R/W); 0 for write and 1 for read. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 522

28.10.10 Data

Name: DATA Offset: 0x28 Reset: 0x0000 Property: Write-Synchronized, Read-Synchronized (1) Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – DATA[7:0] Data The host data register I/O location (DATA) provides access to the host transmit and receive data buffers. Reading valid data or writing data to be transmitted can be successfully done only when SCL is held low by the host (STATUS.CLKHOLD is set). An exception is reading the last data byte after the stop condition has been sent. Accessing DATA.DATA auto-triggers I2C bus operations. The operation performed depends on the state of CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write). Note: 1. Writing DATA.DATA always requires synchronization. Reading DATA.DATA only requires synchronization when Smart mode is enabled. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 523

28.10.11 Debug Control

Name: DBGCTRL Offset: 0x30 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DBGSTOP Access R/W Reset 0 Bit 0 – DBGSTOP Debug Stop Mode This bit controls functionality when the CPU is halted by an external debugger. Value Description 0 The baud-rate generator continues normal operation when the CPU is halted by an external debugger. 1 The baud-rate generator is halted when the CPU is halted by an external debugger. SAM D21/DA1 Family SERCOM I2C – Inter-Integrated Circuit © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 524

I2S - Inter-IC Sound Controller

29.1 Overview

The Inter-IC Sound Controller (I2S) provides bidirectional, synchronous and digital audio link with external audio devices. This controller is compliant with the Inter-IC Sound (I2S) bus specification. It supports TDM interface with external multi-slot audio codecs. It also supports Pulse Density Modulation (PDM) interface with external MEMS microphones. The I2S consists of two Clock Units and two Serializers, that can be enabled separately, to provide Host, Client, or controller modes, and operate as Receiver or Transmitter. The pins associated with I2S peripheral are SDm, FSn, SCKn, and MCKn pins, where n=[0,1] denotes the Clock Unit and m=[0,1] is the Serializers instance. FSn is referred to as Word Select in standard I2S mode operation and as Frame Sync in TDM mode. Peripheral DMAC channels, separate for each Serializer, allow a continuous high bitrate data transfer without processor intervention to the following:

Audio codecs in Host, Client, or Controller mode
Stereo DAC or ADC through dedicated I 2S serial interface
Multi-slot or multiple stereo DACs or ADCs, using the TDM format
Mono or stereo MEMS microphones, using the PDM interface
1-channel burst transfer with non-periodic Frame Sync Each Serializer supports using either a single DMAC channel for all data channels, or two separate DMAC channels for different data channels. The I2S supports 8-bit and 16-bit compact stereo format. This helps in reducing the required DMA bandwidth by transferring the left and right samples within the same data word. Usually, an external audio codec or digital signal processor (DSP) requires a clock which is a multiple of the sampling frequency fs (for example, 384×fs). The I2S peripheral in Host Mode and Controller mode is capable of outputting an output clock ranging from 16×fs to 1024×fs on the Host Clock pin (MCKn).

29.2 Features

Compliant with Inter-IC Sound (I 2S) bus specification
2 independent Serializers configurable as receiver or as transmitter
Supported data formats: – 32-, 24-, 20-, 18-, 16-, and 8-bit mono or stereo format – 16- and 8-bit compact stereo format, with left and right samples packed in the same word to reduce data transfers
Supported data frame formats: – 2-channel I 2S with Word Select – 1- to 8-slot Time Division Multiplexed (TDM) with Frame Sync and individually enabled slots – 1- or 2-channel Pulse Density Modulation (PDM) reception for MEMS microphones – 1-channel burst transfer with non-periodic Frame Sync
2 independent Clock Units handling either the same clock or separate clocks for the Serializers: – Suitable for a wide range of sample frequencies fs, including 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, and 192kHz – 16× fs to 1024×fs Host Clock generated for external audio CODECs
Host, client, and controller modes: – Host: Data received/transmitted based on internally-generated clocks. Output Serial Clock on SCKn pin, Host Clock on MCKn pin, and Frame Sync Clock on FSn pin SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 525

– Client: Data received/transmitted based on external clocks on Serial Clock pin (SCKn) or Host Clock pin (MCKn) – Controller: Only output internally generated Host clock (MCKn), Serial Clock (SCKn), and Frame Sync Clock (FSn)

Individual enabling and disabling of Clock Units and Serializers
DMA interfaces for each Serializer receiver or transmitter to reduce processor overhead: – Either one DMA channel for all data slots or – One DMA channel per data channel in stereo
Smart Data Holding register management to avoid data slots mix after overrun or underrun

29.3 Block Diagram

Figure 29-1. I2S Block Diagram

29.4 Signal Description

Table 29-1. Host Mode Pin Name Pin Description Type MCKn Host Clock for Clock Unit n Input/Output SCKn Serial Clock for Clock Unit n Input/Output FSn I2S Word Select or TDM Frame Sync for Clock Unit n Input/Output SDm Serial Data Input or Output for Serializer m Input/Output SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 526

Table 29-2. Client Mode Pin Name Pin Description Type MCKn Host Clock Input SCKn Serial Clock for Clock Unit n Input FSn I2S Word Select or TDM Frame Sync Input SDm Serial Data Input or Output for Serializer m Input/Output Table 29-3. Controller Mode Pin Name Pin Description Type MCKn Host Clock for Clock Unit n Output SCKn Serial Clock for Clock Unit n Output FSn I2S Word Select or TDM Frame Sync Output SDm Not Applicable Not Applicable Note: One signal can be mapped on several pins. Related Links 7. I/O Multiplexing and Considerations

29.5 Product Dependencies

In order to use this module, other parts of the system must be configured correctly, as described below.

29.5.1 I/O Lines

Using the I2S I/O lines requires the I/O pins to be configured. The I2S pins may be multiplexed with I/O Controller lines. The user must first program the I/O Controller to assign the desired I2S pins to their peripheral function. If the I2S I/O lines are not used by the application, they can be used for other purposes by the I/O Controller. It is required to enable only the I2S inputs and outputs actually in use. Related Links 23. PORT - I/O Pin Controller

29.5.2 Power Management

The I2S will continue to operate in any sleep mode where the selected source clocks are running.

29.5.3 Clocks

The clock for the I2S bus interface (CLK_I2S_APB) is generated by the Power Manager. This clock is disabled at reset, and can be enabled in the Power Manager. It is recommended to disable the I2S before disabling the clock, to avoid freezing the I2S in an undefined state. There are two generic clocks, GCLK_I2S_0 and GCLK_I2S_1, connected to the I2S peripheral, one for each I2S clock unit. The generic clocks (GCLK_I2S_n, n=0..1) can be set to a wide range of frequencies and clock sources. The GCLK_I2S_n must be enabled and configured before use. The GCLK_I2S_n clocks must be enabled and configured before triggering Software Reset, so that the logic in all clock domains can be reset. The generic clocks are only used in Host mode and Controller mode. In Host mode, the clock from a single clock unit can be used for both Serializers to handle synchronous transfers, or a separate clock from different clock units can be used for each Serializer to handle transfers on non-related clocks. Related Links 15. GCLK - Generic Clock Controller SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 527

29.5.4 DMA

The DMA request lines are connected to the DMA Controller (DMAC). Using the I2S DMA requests requires the DMA Controller to be configured first. Related Links 20. DMAC – Direct Memory Access Controller

29.5.5 Interrupts

The interrupt request line is connected to the interrupt controller. Using I2S interrupts requires the interrupt controller to be configured first. Related Links

29.5.6 Events

Not applicable.

29.5.7 Debug Operation

29.5.8 Register Access Protection

Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following:

DATAm
INTFLAG
SYNCBUSY Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. Write-protection does not apply for accesses through an external debugger.

29.5.9 Analog Connections

Not applicable.

29.6 Functional Description

29.6.1 Principle of Operation

The I2S uses three or four communication lines for synchronous data transfer:

SDm for receiving or transmitting in Serializer m (m=0..1)
SCKn for the serial clock in Clock Unit n (n=0..1)
FSn for the frame synchronization or I 2S word select, identifying the beginning of each frame
Optionally, MCKn to output an oversampling clock to an external codec I2S data transfer is frame based, where a serial frame:
Starts with the frame synchronization active edge, and
Consists of 1 to 8 data slots, that are 8-, 16-, 24-, or 32-bit wide. Each data slot is used to transfer one data sample of 8, 16, 18, 20, 24 or 32 bits. Frame based data transfer is described in the following figure: SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 528

Figure 29-2. Data Format: Frames, Slot, Bits and Clocks I2S supports multiple data formats such as:

32-, 24-, 20-, 18-, 16-, and 8-bit mono or stereo format
16- and 8-bit compact stereo format, with left and right samples packed in the same word to reduce data transfers In mono format, Transmit mode, data written to the left channel is duplicated to the right output channel. In mono format, Receiver mode, data received from the right channel is ignored and data received from the left channel is duplicated in to the right channel. In mono format, TDM Transmit mode with more than two slots, data written to the even-numbered slots is duplicated in to the following odd-numbered slot. In mono format, TDM Receiver mode with more than two slots, data received from the even-numbered slots is duplicated in to the following odd-numbered slot. Mono format can be enabled by writing a '1' to the MONO bit in the Serializer m Control register (SERCTRLm.MONO). I2S support different data frame formats:
2-channel I 2S with Word Select
1- to 8-slot Time Division Multiplexed (TDM) with Frame Sync and individually enabled slots
1- or 2-channel Pulse Density Modulation (PDM) reception for MEMS microphones
1-channel burst transfer with non-periodic Frame Sync In 2 channel I2S mode, number of slots configured is one or two and successive data words corresponds to left and right channel. Left and right channel are identified by polarity of Word Select signal (FSn signal). Each frame consists of one or two data word(s). In the case of compact stereo format, the number of slots can be one. When 32-bit slot size is used, the number of slots can be two. In TDM format, number slots can be configured up to 8 slots. If 4 slots are configured, each frame consists of 4 data words. In PDM format, continuous 1-bit data samples are available on the SDI line for each SCKn rising and SCKn falling edge as in case of a MEMS microphone with PDM interface. SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 529

1-channel burst transfer with non-periodic Frame Sync mode is useful typically for passing control non-auto data as in case of DSP. In Burst mode, a single Data transfer starts at each Frame Sync pulse, and these pulses are 1-bit wide and occur only when a Data transfer is requested. Sections 29.6.4 I2S Format - Reception and Transmission Sequence with Word Select, 29.6.5 TDM Format - Reception and Transmission Sequence and 29.7 I2S Application Examples describe more about frame/data formats and register settings required for different I2S applications. Figure 29-3. I2S Functional Block Diagram

29.6.1.1 Initialization

The I2S features two Clock Units, and two Serializers configurable as Receiver or Transmitter. The two Serializers can either share the same Clock Unit or use separate Clock Units. Before enabling the I2S, the following registers must be configured:

Clock Control registers (CLKCTRLn)
Serializer Control registers (SERCTRLm) In Host mode, one of the generic clocks for the I2S must also be configured to operate at the required frequency, as described in 29.6.1 Principle of Operation.
fs is the sampling frequency that defines the frame period
CLKCTRLn.NBSLOTS defines the number of slots in each frame
CLKCTRLn.SLOTSIZE defines the number of bits in each slot
SCKn frequency must be fSCKn = fs × number_of_slots × number_of_bits_per_slot) Once the configuration has been written, the I2S Clock Units and Serializers can be enabled by writing a '1' to the CKENn and SERENm bits and to the ENABLE bit in the Control register (CTRLA). The Clock Unit n can be enabled alone, in Controller Mode, to output clocks to the MCKn, SCKn, and FSn pins. The Clock Units must be enabled if Serializers are enabled. The Clock Units and the Serializers can be disabled independently by writing a '0' to CTRLA.CKENn or CTRLA.SERENm, respectively. Once requested to stop, they will only stop when the pending transmit frames will be completed, if any. When requested to stop, the ongoing reception of the current slot will be completed and then the Serializer will be stopped. Example 29-1. Example Requirements: fs=48kHz, MCKn=384×fs If a 384×fs MCKn Host Clock is required (i.e. 18.432 MHz), the I2S generic clock could run at 18.432 MHz with a Host Clock Output Division Factor of 1 (selected by writing CLKCTRLn.MCKOUTDIV=0x0) in order to obtain the desired MCKn frequency. SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 530

When using 6 slots per frame (CLKCTRLn.NBSLOTS=0x5) and 32-bit slots (CLKCTRLn.SLOTSIZE=0x3), the desired SCKn frequency is fSCKn = 48 kHz × 6 × 32 = 9.216 MHz This frequency can be achieved by dividing the I2S generic clock output of 18.432 MHz by factor 2: Writing CLKCTRLn.MCKDIV=0x1 will select the correct division factor and output the desired SCKn frequency of 9.216 MHz to the SCKn pin. If MCKn is not required, the generic clock could be set to 9.216 MHz and CLKCTRLn.MCKDIV=0x0.

29.6.2 Basic Operation

The Receiver can be operated by reading the Data Holding register (DATAm), whenever the Receive Ready m bit in the Interrupt Flag Status and Clear register (INTFLAG.RXRDYm) is set. Successive values read from DATAm register will correspond to the samples from the left and right audio channels. In TDM mode, the successive values read from DATAm register correspond to the first slot to the last slot. For instance, if I2S is configured in TDM mode with 4 slots in a frame, then successive values written to DATAm register correspond to first, second, third, and fourth slot. The number of slots in TDM is configured in CLKCTRLn.NBSLOTS. The Transmitter can be operated by writing to the Data Holding register (DATAm), whenever the Transmit Ready m bit in the Interrupt Flag Status and Clear register (INTFLAG.TXRDYm) is set. Successive values written to DATAm register should correspond to the samples from the left and right audio channels. In TDM mode, the successive values written to DATAm register correspond to the first, second, third, slot to the last slot. The number of slots in TDM is configured in CLKCTRLn.NBSLOTS. The Receive Ready and Transmit Ready bits can be polled by reading the INTFLAG register. The processor load can be reduced by enabling interrupt-driven operation. The RXRDYm and/or TXRDYm interrupt requests can be enabled by writing a '1' to the corresponding bit in the Interrupt Enable register (INTENSET). The interrupt service routine associated to the I2S interrupt request will then be executed whenever Receive Ready or Transmit Ready status bits are set. The processor load can be reduced further by enabling DMA-driven operation. Then, the DMA channels support up to four trigger sources from the I2S peripheral. These four trigger sources in DMAC channel are

I2S RX 0,
I2S RX 1,
I2S TX 0, and
I2S TX 1. For further reference, these are called I2S_DMAC_ID_RX_m and I2S_DMAC_ID_TX_m triggers (m=0..1). By using these trigger sources, one DMA data transfer will be executed whenever the Receive Ready or Transmit Ready status bits are set.

29.6.2.1 Host Clock, Serial Clock, and Frame Sync Generation

Figure 29-4. I2S Clocks Generation

29.6.2.1.1 Client Mode

In Client mode, the Serial Clock and Frame Sync (Word Select in I2S mode and Frame Sync in TDM mode) are driven by an external host. SCKn and FSn pins are inputs and no generic clock is required by the I2S.

29.6.2.1.2 Host Mode and Controller Mode

In Host Mode, the Host Clock (MCKn), the Serial Clock (SCKn), and the Frame Sync Clock (FSn) are generated by the I2S controller. The user can configure the Host Clock, Serial Clock, and Word Select Frame Sync signal (Word Select in I2S mode and Frame Sync in TDM mode) using the Clock Unit n Control register (CLKCTRLn). MCKn, SCKn, and FSn pins are outputs and a generic clock is used to derive the I2S clocks. In some applications, audio CODECs connected to the I2S pins may require a Host Clock signal with a frequency multiple of the audio sample frequency fs, such as 256×fs. In Controller mode, only the Clock generation unit needs to be configured by writing to the CTRLA and CLKCTRLn registers, where parameters such as clock division factors, Number of slots, Slot size, Frame Sync signal, clock enable are selected. SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 532

29.6.2.1.3 MCKn Clock Frequency

When the I2S is in Host mode, writing a '1' to CLKCTRLn.MCKEN will output GCLK_I2S_n as Host Clock to the MCKn pin. The Host Clock to MCKn pin can be divided by writing to CLKCTRLn.MCKSEL and CLKCTRLn.MCKOUTDIV. The Host Clock (MCKn) frequency is GCLK_I2S_n frequency divided by (MCLKOUTDIV+1). f MCKn = f GCLK _ I 2 S _ n MCKOUTDIV + 1

29.6.2.1.4 SCKn Clock Frequency

When the Serial Clock (SCKn) is generated from GCLK_I2S_n and both CLKCTRLn.MCKSEL and CLKCTRLn.SCKSEL are zero, the Serial Clock (SCKn) frequency is GCLK_I2S_n frequency divided by (MCKDIV+1). i.e. f S CKn = f GCLK_ I 2 S _ n MCKDIV+ 1

29.6.2.1.5 Relation Between MCKn, SCKn, and Sampling Frequency fs

Based on sampling frequency fs, the SCKn frequency requirement can be calculated:

SCKn frequency: f SCKn = fs × total_number_of_bits_per_frame ,
Where total_number_of_bits_per_frame = number_of_slots × number_of_bits_per_slots .
The number of slots is selected by writing to the Number of Slots in Frame bit field in the Clock Unit n Control (CLKCTRLn) register: number_of_slots = NBSLOTS + 1 .
The number of bits per slot (8, 16, 24, or 32 bit) is selected by writing to the Slot Size bit field in CLKCTRLn: .
Consequently, f SCKn = 8 × f s × NBSLOTS + 1 × SLOTSIZE + 1 . The clock frequencies f SCKn and f MCKn are derived from the generic clock frequency f GCLK_I2S_n : f GCLK_I2S_n = f SCKn × CLKCTRLn.MCKDIV + 1 = 8 × f s × NBSLOTS + 1 × SLOTSIZE + 1 × MCKDIV + 1 , and
f GCLK_I2S_n = f MCKn × MCKOUTDIV + 1 . Substituting the right hand sides of the two last equations yields: f MCKn = f GCLK_I2S_n MCKOUTDIV + 1 f MCKn = 8 ⋅ SLOTSIZE + 1 ⋅ NBSLOTS + 1 ⋅ MCKDIV+ 1 MCKOUTDIV+ 1 If a Host Clock output is not required, the GCLK_I2S generic clock can be configured as SCKn by writing a '0'to CLKCTRLn.MCKDIV. Alternatively, if the frequency of the generic clock is a multiple of the required SCKn frequency, the MCKn-to-SCKn divider can be used with the ratio defined by writing the CLKCTRLn.MCKDIV field. The FSn pin is used as Word Select in I2S format and as Frame Synchronization in TDM format, as described in 29.6.4 I2S Format - Reception and Transmission Sequence with Word Select and 29.6.5 TDM Format - Reception and Transmission Sequence, respectively.

29.6.2.2 Data Holding Registers

For each Serializer m, the I2S user interface includes a Data m register (DATAm). They are used to access data samples for all data slots.

29.6.2.2.1 Data Reception Mode

In receiver mode, the DATAm registers store the received data. When a new data word is available in the DATAm register, the Receive Ready bit (RXRDYm) in the Interrupt Flag Status and Clear register (INTFLAG) is set. Reading the DATAm register will clear this bit. A receive overrun condition occurs if a new data word becomes available before the previous data word has been read from the DATAm register. Then, the Receive Overrun bit in INTFLAG will be set (INTFLAG.RXORm). This interrupt can be cleared by writing a '1' to it. SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 533

29.6.2.2.2 Data Transmission Mode

In Transmitter mode, the DATAm registers contain the data to be transmitted. when DATAm is empty, the Transmit Ready bit in the Interrupt Flag Status and Clear register is set (INTFLAG.TXRDYm). Writing to DATAm will clear this bit. A transmit underrun condition occurs if a new data word needs to be transmitted before it has been written to DATAm. Then, the Transmit Underrun bit in INTFLAG will be set (INTFLAG.TXURm). This interrupt can be cleared by writing a '1' to it. The Transmit Data when Underrun bit in the Serializer n Control register (SERCTRLm.TXSAME) configures whether a zero data word is transmitted in case of underrun (SERCTRLm.TXSAME=0), or the previous data word for the current transmit slot number is transmitted again (SERCTRLm.TXSAME=1).

29.6.3 Host, Controller, and Client Modes

In Host and Controller modes, the I2S provides the Serial Clock, a Word Select/Frame Sync signal and optionally a Host Clock. In Controller mode, the I2S Serializers are disabled. Only the clocks are enabled and output for external receivers and/or transmitters. In Client mode, the I2S receives the Serial Clock and the Word Select/Frame Sync Signal from an external host. SCKn and FSn pins are inputs.

29.6.4 I2S Format - Reception and Transmission Sequence with Word Select

As specified in the I2S protocol, data bits are left-adjusted in the Word Select slot, with the MSB transmitted first, starting one clock period after the transition on the Word Select line. Figure 29-5. I2S Reception and Transmission Sequence Data bits are sent on the falling edge of the Serial Clock and sampled on the rising edge of the Serial Clock. The Word Select line indicates the channel in transmission, a low level for the left channel and a high level for the right channel. In I2S format, typical configurations are described below. These configurations do not list all necessary settings, but only basic ones. Other configuration settings are to be done as per requirement such as clock and DMA configurations. Case 1: I2S 16-bit compact stereo

Slot size configured as 16 bits (CLKCTRL0.SLOTSIZE = 0x1)
Number of slots configured as 2 (CLKCTRL0.NBSLOTS = 0x1)
Data size configured as 16-bit compact stereo (SERCTRL0.DATASIZE = 0x05)
Data delay from Frame Sync configured as 1-bit delay (CLKCTRLn.BITDELAY = 0x01)
Frame Sync Width configured as HALF frame (CLKCTRLn.FSWIDTH = 0x01) Case 2: I2S 24-bit stereo Transmitterwith 24-bit slot
Slot size configured as 24 bits (CLKCTRL0.SLOTSIZE = 0x2)
Number of slots configured as 2 (CLKCTRL0.NBSLOTS = 0x1)
Data size configured as 24 bits (SERCTRL0.DATASIZE = 0x01)
Data delay from Frame Sync configured as 1-bit delay (CLKCTRLn.BITDELAY = 0x01) SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 534

Frame Sync Width configured as HALF frame (CLKCTRLn.FSWIDTH = 0x01) In both cases, it will ensure that Word select signal is 'low level' for the left channel and 'high level' for the right channel. The length of transmitted words can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing the Data Word Size bit group in the Serializer Control mregister (SERCTRLm.DATASIZE). If the slot allows for more data bits than the number of bits specified in the respective DATASIZE field, additional bits are appended to the transmitted or received data word as specified in the SERCTRLm.EXTEND field. If the slot allows less data bits than programmed, the extra bits are not transmitted, or received data word is extended based on the EXTEND field value.

29.6.5 TDM Format - Reception and Transmission Sequence

In Time Division Multiplexed (TDM) format, the number of data slots sent or received within each frame will be (CLKCTRLn.NBSLOTS + 1). By configuring the CLKCTRLn register (CLKCTRLn.FSWIDTH and CLKCTRLn.FSINV), the Frame Sync pulse width and polarity can be modified. By configuring SERCTRLm, data bits can be left-adjusted or right-adjusted in the slot. It can also configure the data transmission/reception with either the MSB or the LSB transmitted/received first and starting the transmission/ reception either at the transition of the FSn pin or one clock period after. Figure 29-6. TDM Format Reception and Transmission Sequence Data bits are sent on the falling edge of the Serial Clock and sampled on the rising edge of the Serial Clock. The FSn pin provides a frame synchronization signal, at the beginning of slot 0. The delay between the frame start and the first data bit is defined by writing the CLKCTRLn.BITDELAY field. The Frame Sync pulse can be either one SCKn period (BIT), one slot (SLOT), or one half frame (HALF). This selection is done by writing the CLKCTRLn.FSWIDTH field. The number of slots is selected by writing the CLKCTRLn.NBSLOTS field. The number of bits in each slot is selected by writing the CLKCTRLn.SLOTSIZE field. The length of transmitted words can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing the DATASIZE field in the Serializer Control register (SERCTRLm). If the slot allows more data bits than the number of bits specified in the SERCTRLmDATASIZE bit field, additional bits are appended to the transmitted or received data word as specified in the SERCTRLmEXTEND bit field. If the slot allows less data bits than programmed, the extra bits are not transmitted, or received data word is extended based on the EXTEND field value.

29.6.6 PDM Reception

In Pulse Density Modulation (PDM) reception mode, continuous 1-bit data samples are available on the SDI line on each SCKn rising edge, for example, by a MEMS microphone with PDM interface. When using two channel PDM microphones, the second one (right channel) is configured to output data on each SCKn falling edge. For one PDM microphone, the I2S controller must be configured in normal Receive mode with one slot and 16-bit or 32-bit data size, so that 16 or 32 samples of the microphone are stored into each data word. For two PDM microphones, the I2S controller must be configured in PDM2 mode with one slot and 32-bit data size. The Serializer will store 16 samples of each microphone in one half of the data word, with left microphone bits in lower half and right microphone bits in upper half, like in compact stereo format. Based on oversampling frequency requirement from PDM microphone, the SCKn frequency must be configured in the I2S controller. SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 535

A microphone that requires a sampling frequency of fs = 48 kHz and an oversampling frequency of fo=64 × fs would require an SCKn frequency of 3.072 MHz. After selecting a proper frequency for GCLK_I2S_n and according Host Clock Division Factor in the Clock Unit n Control register (CLKCTRLn.MCKDIV), SCKn must be selected as per required frequency. In PDM mode, only the clock and data line (SCKn and SDIn) pins are used. To configure PDM2 mode, set SLOTSIZE = 0x01 (16-bits), NBSLOTS = 0x01 (2 slots) and SERCTRL0.DATASIZE = 0x00 (32-bit).

29.6.7 Data Formatting Unit

To allow more flexibility, data words received by Serializer m will be formatted by the Receive Formatting Unit before being stored into the Data Holding register (RXDATA). The data words written into TXDATA register will be formatted by the Transmit Formatting Unit before transmission by Serializer m . The formatting options are defined in SERCTRLm:

SLOTADJ for left or right justification in the slot
BITREV for bit reversal
WORDADJ for left or right justification in the data word
EXTEND for extension to the word size

29.6.8 DMA, Interrupts and Events

Table 29-4. Module Request for I2S Condition DMA request DMA request is cleared Interrupt request Event input/ output Receive Ready YES When data is read YES Transmit Ready (Buffer empty) YES When data is written YES Receive Overrun YES Transmit Underrun YES

29.6.8.1 DMA Operation

Each Serializer can be connected either to one single DMAC channel or to one DMAC channel per data slot in stereo mode. This is selected by writing the SERCTRLm.DMA bit: Table 29-5. I2C DMA Request Generation SERCTRLm.DMA Mode Slot Parity DMA Request Trigger

0 Receiver all I2S_DMAC_ID_RX_m

Transmitter all I2S_DMAC_ID_TX_m

1 Receiver even I2S_DMAC_ID_RX_0

odd I2S_DMAC_ID_RX_1 Transmitter even I2S_DMAC_ID_TX_0 odd I2S_DMAC_ID_TX_1 The DMAC reads from the DATAm register and writes to the DATAm register for all data slots, successively. The DMAC transfers may use 32-, 16- or or 8-bit transactions according to the value of the SERCTRLm.DATASIZE field. 8-bit compact stereo uses 16-bit and 16-bit compact stereo uses 32-bit transactions.

29.6.8.2 Interrupts

Receive Ready (RXRDYm): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
Receive Overrun (RXORm): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
Transmit Ready (TXRDYm): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
Transmit Underrun (TXURm): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the I2S is reset. See INTFLAG register for details on how to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. Refer to Nested Vector Interrupt Controller for details. The user must read the INTFLAG register to determine which interrupt condition is present. Note: Interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector Interrupt Controller for details. Related Links

29.6.8.3 Events

Not applicable.

29.6.9 Sleep Mode Operation

The I2S continues to operate in all sleep modes that still provide its clocks.

29.6.10 Synchronization

Software Reset bit in the Control A register (CTRLA.SWRST). SYNCBUSY.SWRST is set to '1' while synchronization is in progress.
Enable bit in the Control A register (CTRLA.ENABLE). SYNCBUSY.ENABLE is set to '1' while synchronization is in progress.
Clock Unit x Enable bits in the Control A register (CTRLA.CKENx). SYNCBUSY.CKENx is set to '1' while synchronization is in progress.
Serializer x Enable bits in the Control A register (CTRLA.SERENx). SYNCBUSY.SERENx is set to '1' while synchronization is in progress. The following registers require synchronization when read or written:
Data n registers (DATAn), Read-Synchronized when Serializer n is in Rx mode or Write-Synchronized when in Tx mode. SYNCBUSY.DATAn is set to '1' while synchronization is in progress. Synchronization is denoted by the Read-Synchronized or Write-Synchronized property in the register description. Related Links

29.6.11 Loop-Back Mode

For debugging purposes, the I2S can be configured to loop back the Transmitter to the Receiver. Writing a '1' to the Loop-Back Test Mode bit in the Serializer m Control register (SERCTRLm.RXLOOP) configures SDm as input and the remaining SD as output. Both SD will be connected internally, so the transmitted data is also received. For instance, writing SERCTRL0.RXLOOP=1 will connect SD1 output to SD0 input, or writing SERCTRL1.RXLOOP=1 will connect SD0 output to SD1 input. RXLOOP=1 will connect the Transmitter output of the other Serializer to the Receiver input of the current Serializer. For the Loop-back Mode to work, the current Serializer must be configured as receiver and the other Serializer as transmitter. Writing SERCTRLm.RXLOOP=0 will restore normal behavior and connection between Serializer m and SDm pin input. As for other changes to the Serializer configuration, Serializer m must be disabled before writing the SERCTRLm register to update SERCTRLm.RXLOOP.

29.7 I2S Application Examples

The I2S can support several serial communication modes used in audio or high-speed serial links. Some standard applications are shown in the following figures. Note: The following examples are not a complete list of serial link applications supported by the I2S. Figure 29-7. Audio Application Block Diagram Serial Clock Word Select Serial Data Out MSB Left Channel LSB MSB Right Channel Serial Data Out Word Select Serial Clock I2S SCKn FSn SDOm EXTERNALI2SRECEIVER SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 538

Figure 29-10. PDM Microphones Application Block Diagram EXTERNAL PDM MICROPHONE for Left Channel EXTERNAL PDM MICROPHONE for Right Channel Serial Data In 64 fs Serial Clock Serial Clock Serial Data In I2S SCKn FSn SDI MCKn VDD GND L/RSEL L/RSEL Left Right Left Right Left Right Left RightRight SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 540

29.8 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 SEREN1 SEREN0 CKEN1 CKEN0 ENABLE SWRST 0x01 ... 0x03 Reserved 0x04 CLKCTRL0 7:0 BITDELAY FSWIDTH[1:0] NBSLOTS[2:0] SLOTSIZE[1:0] 15:8 SCKSEL FSINV FSSEL 23:16 MCKDIV[4:0] MCKEN MCKSEL 31:24 MCKOUTINV SCKOUTINV FSOUTINV MCKOUTDIV[4:0] 0x08 CLKCTRL1 7:0 BITDELAY FSWIDTH[1:0] NBSLOTS[2:0] SLOTSIZE[1:0] 15:8 SCKSEL FSINV FSSEL 23:16 MCKDIV[4:0] MCKEN MCKSEL 31:24 MCKOUTINV SCKOUTINV FSOUTINV MCKOUTDIV[4:0] 0x0C INTENCLR 7:0 RXOR1 RXOR0 RXRDY1 RXRDY0 15:8 TXUR1 TXUR0 TXRDY1 TXRDY0 0x0E ... 0x0F Reserved 0x10 INTENSET 7:0 RXOR1 RXOR0 RXRDY1 RXRDY0 15:8 TXUR1 TXUR0 TXRDY1 TXRDY0 0x12 ... 0x13 Reserved 0x14 INTFLAG 7:0 RXOR1 RXOR0 RXRDY1 RXRDY0 15:8 TXUR1 TXUR0 TXRDY1 TXRDY0 0x16 ... 0x17 Reserved 0x18 SYNCBUSY 7:0 SEREN1 SEREN0 CKEN1 CKEN0 ENABLE SWRST 15:8 DATA1 DATA0 0x1A ... 0x1F Reserved 0x20 SERCTRL0 7:0 SLOTADJ CLKSEL TXSAME TXDEFAULT[1:0] SERMODE[1:0] 15:8 BITREV EXTEND[1:0] WORDADJ DATASIZE[2:0] 23:16 SLOTDIS7 SLOTDIS6 SLOTDIS5 SLOTDIS4 SLOTDIS3 SLOTDIS2 SLOTDIS1 SLOTDIS0 31:24 RXLOOP DMA MONO 0x24 SERCTRL1 7:0 SLOTADJ CLKSEL TXSAME TXDEFAULT[1:0] SERMODE[1:0] 15:8 BITREV EXTEND[1:0] WORDADJ DATASIZE[2:0] 23:16 SLOTDIS7 SLOTDIS6 SLOTDIS5 SLOTDIS4 SLOTDIS3 SLOTDIS2 SLOTDIS1 SLOTDIS0 31:24 RXLOOP DMA MONO 0x28 ... 0x2F Reserved 0x30 DATA0 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] 0x34 DATA1 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] 0x34 RXDATA 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 541

29.9 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read- Synchronized" and/or "Write-Synchronized" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description. SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 542

29.9.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 SEREN1 SEREN0 CKEN1 CKEN0 ENABLE SWRST Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bits 4, 5 – SERENx Serializer x Enable [x=1..0] Writing a '0' to this bit will disable the Serializer x. Writing a '1' to this bit will enable the Serializer x. Value Description 0 The Serializer x is disabled. 1 The Serializer x is enabled. Bits 2, 3 – CKENx Clock Unit x Enable [x=1..0] Writing a '0' to this bit will disable the Clock Unit x. Writing a '1' to this bit will enable the Clock Unit x. Value Description 0 The Clock Unit x is disabled. 1 The Clock Unit x is enabled. Bit 1 – ENABLE Enable Writing a '0' to this bit will disable the module. Writing a '1' to this bit will enable the module. Value Description 0 The peripheral is disabled. 1 The peripheral is enabled. Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers to their initial state, and the peripheral will be disabled. Writing a '1' to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. The I2S generic clocks must be enabled before triggering Software Reset, hence the logic in all clock domains can be reset. Value Description 0 There is no reset operation ongoing. 1 The reset operation is ongoing. SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 543

29.9.2 Clock Unit n Control

Name: CLKCTRLn Offset: 0x04 + n*0x04 [n=0..1] Reset: 0x00000000 Property: Enable-Protected, PAC Write-Protection Bit 31 30 29 28 27 26 25 24 MCKOUTINV SCKOUTINV FSOUTINV MCKOUTDIV[4:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 MCKDIV[4:0] MCKEN MCKSEL Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SCKSEL FSINV FSSEL Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 BITDELAY FSWIDTH[1:0] NBSLOTS[2:0] SLOTSIZE[1:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 31 – MCKOUTINV Host Clock Output Invert Value Description 0 The Host Clock n is output without inversion. 1 The Host Clock n is inverted before being output. Bit 30 – SCKOUTINV Serial Clock Output Invert Value Description 0 The Serial Clock n is output without inversion. 1 The Serial Clock n is inverted before being output. Bit 29 – FSOUTINV Frame Sync Output Invert Value Description 0 The Frame Sync n is output without inversion. 1 The Frame Sync n is inverted before being output. Bits 28:24 – MCKOUTDIV[4:0] Host Clock Output Division Factor The generic clock selected by MCKSEL is divided by (MCKOUTDIV + 1) to obtain the Host Clock n output. Bits 23:19 – MCKDIV[4:0] Host Clock Division Factor The Host Clock n is divided by (MCKDIV + 1) to obtain the Serial Clock n. Bit 18 – MCKEN Host Clock Enable Value Description 0 The Host Clock n division and output is disabled. 1 The Host Clock n division and output is enabled. Bit 16 – MCKSEL Host Clock Select This field selects the source of the Host Clock n. SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 544

0x0 GCLK GCLK_I2S_n is used as Host Clock n source 0x1 MCKPIN MCKn input pin is used as Host Clock n source Bit 12 – SCKSEL Serial Clock Select This field selects the source of the Serial Clock n. SCKSEL Name Description 0x0 MCKDIV Divided Host Clock n is used as Serial Clock n source 0x1 SCKPIN SCKn input pin is used as Serial Clock n source Bit 11 – FSINV Frame Sync Invert Value Description 0 The Frame Sync n is used without inversion. 1 The Frame Sync n is inverted before being used. Bit 8 – FSSEL Frame Sync Select This field selects the source of the Frame Sync n. FSSEL Name Description 0x0 SCKDIV Divided Serial Clock n is used as Frame Sync n source 0x1 FSPIN FSn input pin is used as Frame Sync n source Bit 7 – BITDELAY Data Delay from Frame Sync BITDELAY Name Description 0x0 LJ Left Justified (0 Bit Delay) 0x1 I2S I2S (1 Bit Delay) Bits 6:5 – FSWIDTH[1:0] Frame Sync Width This field selects the duration of the Frame Sync output pulses. When not in Burst mode, the Clock unit n operates in continuous mode when enabled, with periodic Frame Sync pulses and Data samples. In Burst mode, a single Data transfer starts at each Frame Sync pulse; these pulses are 1-bit wide and occur only when a Data transfer is requested. Note that the compact stereo modes (16C and 8C) are not supported in the Burst mode. FSWIDTH[1:0] Name Description 0x0 SLOT Frame Sync Pulse is 1 Slot wide (default for I2S protocol) 0x1 HALF Frame Sync Pulse is half a Frame wide 0x2 BIT Frame Sync Pulse is 1 Bit wide 0x3 BURST Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested Bits 4:2 – NBSLOTS[2:0] Number of Slots in Frame Each Frame for Clock Unit n is composed of (NBSLOTS + 1) Slots. Bits 1:0 – SLOTSIZE[1:0] Slot Size Each Slot for Clock Unit n is composed of a number of bits specified by SLOTSIZE. SLOTSIZE[1:0] Name Description 0x0 8 8-bit Slot for Clock Unit n 0x1 16 16-bit Slot for Clock Unit n 0x2 24 24-bit Slot for Clock Unit n 0x3 32 32-bit Slot for Clock Unit n SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 545

29.9.3 Interrupt Enable Clear

Name: INTENCLR Offset: 0x0C Reset: 0x0000 Property: PAC Write-Protection Bit 15 14 13 12 11 10 9 8 TXUR1 TXUR0 TXRDY1 TXRDY0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RXOR1 RXOR0 RXRDY1 RXRDY0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 12, 13 – TXURx Transmit Underrun x Interrupt Enable [x=1..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Transmit Underrun x Interrupt Enable bit, which disables the Transmit Underrun x interrupt. Value Description 0 The Transmit Underrun x interrupt is disabled. 1 The Transmit Underrun x interrupt is enabled. Bits 8, 9 – TXRDYx Transmit Ready x Interrupt Enable [x=1..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Transmit Ready x Interrupt Enable bit, which disables the Transmit Ready x interrupt. Value Description 0 The Transmit Ready x interrupt is disabled. 1 The Transmit Ready x interrupt is enabled. Bits 4, 5 – RXORx Receive Overrun x Interrupt Enable [x=1..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Receive Overrun x Interrupt Enable bit, which disables the Receive Overrun x interrupt. Value Description 0 The Receive Overrun x interrupt is disabled. 1 The Receive Overrun x interrupt is enabled. Bits 0, 1 – RXRDYx Receive Ready x Interrupt Enable [x=1..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Receive Ready x Interrupt Enable bit, which disables the Receive Ready x interrupt. Value Description 0 The Receive Ready x interrupt is disabled. 1 The Receive Ready x interrupt is enabled. SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 546

29.9.4 Interrupt Enable Set

Name: INTENSET Offset: 0x10 Reset: 0x0000 Property: PAC Write-Protection Bit 15 14 13 12 11 10 9 8 TXUR1 TXUR0 TXRDY1 TXRDY0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RXOR1 RXOR0 RXRDY1 RXRDY0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 12, 13 – TXURx Transmit Underrun x Interrupt Enable [x=1..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Transmit Underrun Interrupt Enable bit, which enables the Transmit Underrun interrupt. Value Description 0 The Transmit Underrun interrupt is disabled. 1 The Transmit Underrun interrupt is enabled. Bits 8, 9 – TXRDYx Transmit Ready x Interrupt Enable [x=1..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Transmit Ready Interrupt Enable bit, which enables the Transmit Ready interrupt. Value Description 0 The Transmit Ready interrupt is disabled. 1 The Transmit Ready interrupt is enabled. Bits 4, 5 – RXORx Receive Overrun x Interrupt Enable [x=1..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Receive Overrun Interrupt Enable bit, which enables the Receive Overrun interrupt. Value Description 0 The Receive Overrun interrupt is disabled. 1 The Receive Overrun interrupt is enabled. Bits 0, 1 – RXRDYx Receive Ready x Interrupt Enable [x=1..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Receive Ready Interrupt Enable bit, which enables the Receive Ready interrupt. Value Description 0 The Receive Ready interrupt is disabled. 1 The Receive Ready interrupt is enabled. SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 547

29.9.5 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x14 Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 TXUR1 TXUR0 TXRDY1 TXRDY0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RXOR1 RXOR0 RXRDY1 RXRDY0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 12, 13 – TXURx Transmit Underrun x [x=1..0] This flag is cleared by writing a '1' to it. This flag is set when a Transmit Underrun condition occurs in Sequencer x, and will generate an interrupt request if INTENCLR/SET.TXURx is set to '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Transmit Underrun x interrupt flag. Bits 8, 9 – TXRDYx Transmit Ready x [x=1..0] This flag is cleared by writing to DATAx register or writing a '1' to it. This flag is set when Sequencer x is ready to accept a new data word to be transmitted, and will generate an interrupt request if INTENCLR/SET.TXRDYx is set to '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Transmit Ready x interrupt flag. Bits 4, 5 – RXORx Receive Overrun x [x=1..0] This flag is cleared by writing a '1' to it. This flag is set when a Receive Overrun condition occurs in Sequencer x, and will generate an interrupt request if INTENCLR/SET.RXORx is set to '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Receive Overrun x interrupt flag. Bits 0, 1 – RXRDYx Receive Ready x [x=1..0] This flag is cleared by reading from DATAx register or writing a '1' to it. This flag is set when a Sequencer x has received a new data word, and will generate an interrupt request if INTENCLR/SET.RXRDYx is set to '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Receive Ready x interrupt flag. SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 548

29.9.6 Synchronization Busy

Name: SYNCBUSY Offset: 0x18 Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 DATA1 DATA0 Access R R Reset 0 0 Bit 7 6 5 4 3 2 1 0 SEREN1 SEREN0 CKEN1 CKEN0 ENABLE SWRST Access R R R R R R Reset 0 0 0 0 0 0 Bits 8, 9 – DATAx Data x Synchronization Status [x=1..0] Bit DATAx is cleared when the synchronization of DATA Holding register (DATAx) between the clock domains is complete. Bit DATAx is set when the synchronization of DATA Holding register (DATAx) between the clock domains is started. Bits 4, 5 – SERENx Serializer x Enable Synchronization Status [x=1..0] Bit SERENx is cleared when the synchronization of the CTRLA.SERENx bit between the clock domains is complete. Bit SERENx is set when the synchronization of the CTRLA.SERENx bit between the clock domains is started. Bits 2, 3 – CKENx Clock Unit x Enable Synchronization Status [x=1..0] Bit CKENx is cleared when the synchronization of the CTRLA.CKENx bit between the clock domains is complete. Bit CKENx is set when the synchronization of the CTRLA.CKENx bit between the clock domains is started. Bit 1 – ENABLE Enable Synchronization Status This bit is cleared when the synchronization of the CTRLA.ENABLE bit between the clock domains is complete. This bit is set when the synchronization of the CTRLA.ENABLE bit between the clock domains is started. Bit 0 – SWRST Software Reset Synchronization Status This bit is cleared when the synchronization of the CTRLA.SWRST bit between the clock domains is complete. This bit is set when the synchronization of the CTRLA.SWRST bit between the clock domains is started. SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 549

29.9.7 Serializer n Control

Name: SERCTRLn Offset: 0x20 + n*0x04 [n=0..1] Reset: 0x00000000 Property: Enable-Protected, PAC Write-Protection Bit 31 30 29 28 27 26 25 24 RXLOOP DMA MONO Access R/W R/W R/W Reset 0 0 0 Bit 23 22 21 20 19 18 17 16 SLOTDIS7 SLOTDIS6 SLOTDIS5 SLOTDIS4 SLOTDIS3 SLOTDIS2 SLOTDIS1 SLOTDIS0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 BITREV EXTEND[1:0] WORDADJ DATASIZE[2:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SLOTADJ CLKSEL TXSAME TXDEFAULT[1:0] SERMODE[1:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 26 – RXLOOP Loop-back Test Mode This bit enables a loop-back test mode: Value Description 0 Each Receiver uses its SDn pin as input (default mode). 1 Receiver uses as input the transmitter output of the other Serializer in the pair: e.g. SD1 for SD0 or SD0 for SD1. Bit 25 – DMA Single or Multiple DMA Channels This bit selects whether even- and odd-numbered slots use separate DMA channels or the same DMA channel. DMA Name Description 0x0 SINGLE Single DMA channel 0x1 MULTIPLE One DMA channel per data channel Bit 24 – MONO Mono Mode. MONO Name Description 0x0 STEREO Normal mode 0x1 MONO Left channel data is duplicated to right channel Bits 16, 17, 18, 19, 20, 21, 22, 23 – SLOTDISx Slot x Disabled for this Serializer [x=7..0] This field allows disabling some slots in each transmit frame: Value Description 0 Slot x is used for data transfer. 1 Slot x is not used for data transfer and will be output as specified in the TXDEFAULT field. Bit 15 – BITREV Data Formatting Bit Reverse This bit allows changing the order of data bits in the word in the Formatting Unit. SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 550

0x0 MSBIT Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) 0x1 LSBIT Transfer Data Least Significant Bit (LSB) first Bits 14:13 – EXTEND[1:0] Data Formatting Bit Extension This field defines the bit value used to extend data samples in the Formatting Unit. EXTEND[1:0] Name Description 0x0 ZERO Extend with zeros 0x1 ONE Extend with ones 0x2 MSBIT Extend with Most Significant Bit 0x3 LSBIT Extend with Least Significant Bit Bit 12 – WORDADJ Data Word Formatting Adjust This field defines left or right adjustment of data samples in the word in the Formatting Unit. for details. WORDADJ Name Description 0x0 RIGHT Data is right adjusted in word 0x1 LEFT Data is left adjusted in word Bits 10:8 – DATASIZE[2:0] Data Word Size This field defines the number of bits in each data sample. For 8-bit compact stereo, two 8-bit data samples are packed in bits 15 to 0 of the DATAm register. For 16-bit compact stereo, two 16-bit data samples are packed in bits 31 to 0 of the DATAm register. DATASIZE[2:0] Name Description 0x0 32 32 bits 0x1 24 24 bits 0x2 20 20 bits 0x3 18 18 bits 0x4 16 16 bits 0x5 16C 16 bits compact stereo 0x6 8 8 bits 0x7 8C 8 bits compact stereo Bit 7 – SLOTADJ Data Slot Formatting Adjust This field defines left or right adjustment of data samples in the slot. SLOTADJ Name Description 0x0 RIGHT Data is right adjusted in slot 0x1 LEFT Data is left adjusted in slot Bit 5 – CLKSEL Clock Unit Selection. CLKSEL Name Description 0x0 CLK0 Use Clock Unit 0 0x1 CLK1 Use Clock Unit 1 Bit 4 – TXSAME Transmit Data when Underrun. TXSAME Name Description 0x0 ZERO Zero data transmitted in case of underrun 0x1 SAME Last data transmitted in case of underrun Bits 3:2 – TXDEFAULT[1:0] Line Default Line when Slot Disabled This field defines the default value driven on the SDn output pin during all disabled Slots. SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 551

TXDEFAULT[1:0] Name Description 0x0 ZERO Output Default Value is 0 0x1 ONE Output Default Value is 1 0x2 Reserved 0x3 HIZ Output Default Value is high impedance Bits 1:0 – SERMODE[1:0] Serializer Mode. SERMODE[1:0] Name Description 0x0 RX Receive 0x1 TX Transmit 0x2 PDM2 Receive one PDM data on each serial clock edge 0x3 Reserved SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 552

29.9.8 Data Holding m

Name: DATAm Offset: 0x30 + m*0x04 [m=0..1] Reset: 0x00000000 Property: Read-Synchronized, Write-Synchronized Bit 31 30 29 28 27 26 25 24 DATA[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DATA[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DATA[31:0] Sample Data This register is used to transfer data to or from Serializer n. Data samples written to DATAn register will be sent to Serializer n for transmission, through the Transmit Formatting Unit that will apply the formatting specified in the SERCTRLn register. Data samples received by Serializer n will be available for reading from DATAn register, through the Receive Formatting Unit, according to formatting information for Serializer n in the SERCTRLn register. SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 553

29.9.9 Rx Data

Name: RXDATA Offset: 0x34 Reset: 0x00000000 Property: Read-Synchronized Bit 31 30 29 28 27 26 25 24 DATA[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DATA[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DATA[31:0] Sample Data This register is used to transfer data from the Rx Serializer. Data samples received by Rx Serializer will be available for reading from RXDATA register, through the Receive Formatting Unit, according to formatting information for Rx Serializer in the RXCTRL register. SAM D21/DA1 Family I2S - Inter-IC Sound Controller © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 554

TC – Timer/Counter

30.1 Overview

The TC consists of a counter, a prescaler, compare/capture channels and control logic. The counter can be set to count events, or it can be configured to count clock pulses. The counter, together with the compare/capture channels, can be configured to timestamp input events, allowing capture of frequency and pulse width. It can also perform waveform generation, such as frequency generation and pulse-width modulation (PWM).

30.2 Features

Selectable configuration – Up to five 16-bit Timer/Counters (TC), each configurable as:
8-bit TC with two compare/capture channels
16-bit TC with two compare/capture channels
32-bit TC with two compare/capture channels, by using two TCs
Waveform generation – Frequency generation – Single-slope pulse-width modulation
Input capture – Event capture – Frequency capture – Pulse-width capture
One input event
Interrupts/output events on: – Counter overflow/underflow – Compare match or capture
Internal prescaler
Can be used with DMA and to trigger DMA transactions SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 555

30.3 Block Diagram

Figure 30-1. Timer/Counter Block Diagram PER PRESCALER CONTROL LOGIC WAVEFORM GENERATION COUNT CC0 BASE COUNTER COUNTER Compare / Capture Top Zero= 0 match Updateevent OVF/UNF (INT Req.) ERR (INT Req.) WOx Out MCx (INT Req.) count clear load direction CONTROL LOGIC

30.4 Signal Description

Signal Name Type Description WO[1:0] Digital output Waveform output Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be mapped on several pins. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 556

I/O Multiplexing and Considerations

30.5 Product Dependencies

In order to use this peripheral, other parts of the system must be configured correctly, as described below.

30.5.1 I/O Lines

In order to use the I/O lines of this peripheral, the I/O pins must be configured using the I/O Pin Controller (PORT). Related Links 23. PORT - I/O Pin Controller

30.5.2 Power Management

This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake up the device from sleep modes. Events connected to the event system can trigger other operations in the system without exiting sleep modes. Related Links 16. PM – Power Manager

30.5.3 Clocks

The TC bus clock (CLK_TCx_APB, where x represents the specific TC instance number) can be enabled and disabled in the Power Manager, and the default state of CLK_TCx_APB can be found in the Peripheral Clock Masking section in “PM – Power Manager”. The different TC instances are paired, even and odd, starting from TC3, and use the same generic clock, GCLK_TCx. This means that the TC instances in a TC pair cannot be set up to use different GCLK_TCx clocks. This generic clock is asynchronous to the user interface clock (CLK_TCx_APB). Due to this asynchronicity, accessing certain registers will require synchronization between the clock domains. Refer to 30.6.6 Synchronization for further details. Related Links

30.5.4 DMA

30.5.5 Interrupts

30.5.6 Events

The events of this peripheral are connected to the Event System. Related Links 24. EVSYS – Event System

30.5.7 Debug Operation

When the CPU is halted in debug mode, this peripheral will halt normal operation. This peripheral can be forced to continue operation during debugging - refer to the Debug Control (DBGCTRL) register for details. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 557

30.5.8 Register Access Protection

Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following:

Interrupt Flag register (INTFLAG)
Status register (STATUS)
Read Request register (READREQ)
Count register (COUNT)
Period register (PER)
Compare/Capture Value registers (CCx) Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. Write-protection does not apply for accesses through an external debugger.

30.5.9 Analog Connections

Not applicable.

30.6 Functional Description

30.6.1 Principle of Operation

The following definitions are used throughout the documentation: Table 30-1. Timer/Counter Definitions Name Description TOP The counter reaches TOP when it becomes equal to the highest value in the count sequence. The TOP value can be the same as Period (PER) or the Compare Channel 0 (CC0) register value depending on the waveform generator mode in Waveform Output Operations. ZERO The counter is ZERO when it contains all zeroes MAX The counter reaches MAX when it contains all ones UPDATE The timer/counter signals an update when it reaches ZERO or TOP, depending on the direction settings. Timer The timer/counter clock control is handled by an internal source Counter The clock control is handled externally (e.g. counting external events) CC For compare operations, the CC are referred to as “compare channels” For capture operations, the CC are referred to as “capture channels.” The counter in the TC can either count events from the Event System, or clock ticks of the GCLK_TCx clock, which may be divided by the prescaler. The counter value is passed to the CCx where it can be either compared to user-defined values or captured. The compare and capture registers (CCx) and counter register (COUNT) can be configured as 8-, 16- or 32-bit registers, with according MAX values. Mode settings determine the maximum range of the counter. In 8-bit mode, Period Value (PER) is also available. The counter range and the operating frequency determine the maximum time resolution achievable with the TC peripheral. The TC can be set to count up or down. Under normal operation, the counter value is continuously compared to the TOP or ZERO value to determine whether the counter has reached that value. On a comparison match the TC can request DMA transactions, or generate interrupts or events for the Event System. On a comparison match the TC can request DMA transactions, or generate interrupts or events for the Event System. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 558

In compare operation, the counter value is continuously compared to the values in the CCx registers. In case of a match the TC can request DMA transactions, or generate interrupts or events for the Event System. In waveform generator mode, these comparisons are used to set the waveform period or pulse width. Capture operation can be enabled to perform input signal period and pulse width measurements, or to capture selectable edges from an internal event from Event System.

30.6.2 Basic Operation

30.6.2.1 Initialization

The following registers are enable-protected, meaning that they can only be written when the TC is disabled (CTRLA.ENABLE =0):

Control A register (CTRLA), except the Run Standby (RUNSTDBY), Enable (ENABLE) and Software Reset (SWRST) bits Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1', but not at the same time as CTRLA.ENABLE is written to '0'. Enable-protection is denoted by the "Enable-Protected" property in the register description. The following bits are enable-protected:
Event Action bits in the Event Control register (EVCTRL.EVACT) Before enabling the TC, the peripheral must be configured by the following steps: 1. Enable the TC bus clock (CLK_TCx_APB). 2. Select 8-, 16- or 32-bit counter mode via the TC Mode bit group in the Control A register (CTRLA.MODE). The default mode is 16-bit. 3. Select one wave generation operation in the Waveform Generation Operation bit group in the Control A register (CTRLA.WAVEGEN). 4. If desired, the GCLK_TCx clock can be prescaled via the Prescaler bit group in the Control A register (CTRLA.PRESCALER). – If the prescaler is used, select a prescaler synchronization operation via the Prescaler and Counter Synchronization bit group in the Control A register (CTRLA.PRESYNC). 5. Select one-shot operation by writing a '1' to the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT). 6. If desired, configure the counting direction 'down' (starting from the TOP value) by writing a '1' to the Counter Direction bit in the Control B register (CTRLBSET.DIR). 7. For capture operation, enable the individual channels to capture in the Capture Channel x Enable bit group in the Control C register (CTRLC.CPTEN). 8. If desired, enable inversion of the waveform output or IO pin input signal for individual channels via the Waveform Output Invert Enable bit group in the Control C register (CTRLC.INVEN).

30.6.2.2 Enabling, Disabling and Resetting

The TC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The TC is disbled by writing a zero to CTRLA.ENABLE. The TC is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the TC, except DBGCTRL, will be reset to their initial state, and the TC will be disabled. Refer to the CTRLA register for details. The TC should be disabled before the TC is reset in order to avoid undefined behavior.

30.6.2.3 Prescaler Selection

The GCLK_TCx is fed into the internal prescaler. The prescaler consists of a counter that counts up to the selected prescaler value, whereupon the output of the prescaler toggles. If the prescaler value is higher than one, the counter update condition can be optionally executed on the next GCLK_TCx clock pulse or the next prescaled clock pulse. For further details, refer to Prescaler (CTRLA.PRESCALER) and Counter Synchronization (CTRLA.PRESYNC) description. Prescaler outputs from 1 to 1/1024 are available. For a complete list of available prescaler outputs, see the register description for the Prescaler bit group in the Control A register (CTRLA.PRESCALER). SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 559

Note: When counting events, the prescaler is bypassed. The joint stream of prescaler ticks and event action ticks is called CLK_TC_CNT. Figure 30-2. Prescaler PRESCALER GCLK_TC / GCLK_TC Prescaler COUNTCLK_TC_CNT EVACT EVENT

30.6.2.4 Counter Mode

The Counter mode is selected by the Mode bit group in the Control A register (CTRLA.MODE). By default, the counter is enabled in the 16-bit counter resolution. Three counter resolutions are available:

COUNT8: The 8-bit TC has its own Period register (PER). This register is used to store the period value that can be used as the top value for waveform generation.
COUNT16: 16-bit is the default Counter mode. There is no dedicated Period register in this mode.
COUNT32: This mode is achieved by pairing two 16-bit TC peripherals. TC4 is paired with TC5, and TC6 is paired with TC7. TC3 does not support 32-bit resolution. When paired, the TC peripherals are configured using the registers of the even-numbered TC (TC4 or TC6 respectively). The odd-numbered partner (TC5 or TC7 respectively) will act as client, and the Client bit in the Status register (STATUS.SLAVE) will be set. The register values of a client will not reflect the registers of the 32-bit counter. Writing to any of the Client registers will not affect the 32-bit counter. Normal access to the client COUNT and CCx registers is not allowed.

30.6.2.5 Counter Operations

The counter can be set to count up or down. When the counter is counting up and the top value is reached, the counter will wrap around to zero on the next clock cycle. When counting down, the counter will wrap around to the top value when zero is reached. In one-shot mode, the counter will stop counting after a wraparound occurs. The counting direction is set by the Direction bit in the Control B register (CTRLB.DIR). If this bit is zero the counter is counting up, and counting down if CTRLB.DIR=1. The counter will count up or down for each tick (clock or event) until it reaches TOP or ZERO. When it is counting up and TOP is reached, the counter will be set to zero at the next tick (overflow) and the Overflow Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF) will be set. It is also possible to generate an event on overflow or underflow when the Overflow/Underflow Event Output Enable bit in the Event Control register (EVCTRL.OVFEO) is one. It is possible to change the counter value (by writing directly in the COUNT register) even when the counter is running. When starting the TC, the COUNT value will be either ZERO or TOP (depending on the counting direction set by CTRLBSET.DIR or CTRLBCLR.DIR), unless a different value has been written to it, or the TC has been stopped at a value other than ZERO. The write access has higher priority than count, clear, or reload. The direction of the counter can also be changed during normal operation. See also the figure below. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 560

Figure 30-3. Counter Operation DIR COUNT MAX "reload" update TOP COUNT writtenDirection ChangePeriod (T) ZERO "clear" update

30.6.2.5.1 Stop Command and Event Action

A Stop command can be issued from software by using Command bits in the Control B Set register (CTRLBSET.CMD = 0x2, STOP). When a Stop is detected while the counter is running, the counter will retain its current value. All waveforms are cleared and the Stop bit in the Status register is set (STATUS.STOP).

30.6.2.5.2 Re-Trigger Command and Event Action

A re-trigger command can be issued from software by writing the Command bits in the Control B Set register (CTRLBSET.CMD = 0x1, RETRIGGER), or from event when a re-trigger event action is configured in the Event Control register (EVCTRL.EVACT = 0x1, RETRIGGER). When the command is detected during counting operation, the counter will be reloaded or cleared, depending on the counting direction (CTRLBSET.DIR or CTRLBCLR.DIR). When the re-trigger command is detected while the counter is stopped, the counter will resume counting from the current value in the COUNT register. Note: When a re-trigger event action is configured in the Event Action bits in the Event Control register (EVCTRL.EVACT=0x1, RETRIGGER), enabling the counter will not start the counter. The counter will start on the next incoming event and restart on corresponding following event.

30.6.2.5.3 Count Event Action

The TC can count events. When an event is received, the counter increases or decreases the value, depending on direction settings (CTRLBSET.DIR or CTRLBCLR.DIR). The count event action can be selected by the Event Action bit group in the Event Control register (EVCTRL.EVACT=0x2, COUNT).

30.6.2.5.4 Start Event Action

The TC can start counting operation on an event when previously stopped. In this configuration, the event has no effect if the counter is already counting. When the peripheral is enabled, the counter operation starts when the event is received or when a re-trigger software command is applied. The Start TC on Event action can be selected by the Event Action bit group in the Event Control register (EVCTRL.EVACT=0x3, START).

30.6.2.6 Compare Operations

By default, the Compare/Capture channel is configured for compare operations. When using the TC and the Compare/Capture Value registers (CCx) for compare operations, the counter value is continuously compared to the values in the CCx registers. This can be used for timer or for waveform operation.

30.6.2.6.1 Waveform Output Operations

The compare channels can be used for waveform generation on output port pins. To make the waveform available on the connected pin, the following requirements must be fulfilled: 1. Choose a waveform generation mode in the Waveform Generation Operation bit in Waveform register (CTRLA.WAVEGEN). 2. Optionally invert the waveform output by writing the corresponding Waveform Output Invert Enable bit in the Control C register (CTRLC.INVx). SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 561

Configure the pins with the I/O Pin Controller. Refer to PORT - I/O Pin Controller for details. The counter value is continuously compared with each CCx value. On a comparison match, the Match or Capture Channel x bit in the Interrupt Flag Status and Clear register (INTFLAG.MCx) will be set on the next zero-to-one transition of CLK_TC_CNT (see the next figure). An interrupt/and or event can be generated on comparison match when INTENSET.MCx=1 and/or EVCTRL.MCEOx=1. There are four waveform configurations for the Waveform Generation Operation bit group in the Control A register (CTRLA.WAVEGEN) . This will influence how the waveform is generated and impose restrictions on the top value. The configurations are:

Normal frequency (NFRQ)
Match frequency (MFRQ)
Normal pulse-width modulation (NPWM)
Match pulse-width modulation (MPWM) When using NPWM or NFRQ configuration, the TOP will be determined by the counter resolution. In 8-bit counter mode, the Period register (PER) is used as TOP, and the TOP can be changed by writing to the PER register. In 16- and 32-bit counter mode, TOP is fixed to the maximum (MAX) value of the counter. Related Links 23. PORT - I/O Pin Controller

30.6.2.6.2 Frequency Operation

Normal Frequency Generation (NFRQ) For Normal Frequency Generation, the period time (T) is controlled by the period register (PER) for 8-bit counter mode and MAX for 16- and 32-bit mode. The waveform generation output (WO[x]) is toggled on each compare match between COUNT and CCx, and the corresponding Match or Capture Channel x Interrupt Flag (INTFLAG.MCx) will be set. Figure 30-4. Normal Frequency Operation COUNT MAX TOP ZERO CCx WO[x] Direction ChangePeriod (T) COUNT Written "reload" update "clear" update "match" Match Frequency Generation (MFRQ) For Match Frequency Generation, the period time (T) is controlled by the CC0 register instead of PER or MAX. WO[0] toggles on each update condition. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 562

Figure 30-5. Match Frequency Operation COUNT MAX CC0 COUNT WrittenDirection ChangePeriod (T) ZERO WO[0] "reload" update "clear" update

30.6.2.6.3 PWM Operation

Normal Pulse-Width Modulation Operation (NPWM) NPWM uses single-slope PWM generation. For single-slope PWM generation, the period time (T) is controlled by the TOP value, and CCx controls the duty cycle of the generated waveform output. When up-counting, the WO[x] is set at start or compare match between the COUNT and TOP values, and cleared on compare match between COUNT and CCx register values. When down-counting, the WO[x] is cleared at start or compare match between the COUNT and ZERO values, and set on compare match between COUNT and CCx register values. The following equation calculates the exact resolution for a single-slope PWM (RPWM_SS) waveform: R PWM_SS = log(TOP+1) log(2) The PWM frequency (fPWM_SS) depends on TOP value and the peripheral clock frequency (fGCLK_TC), and can be calculated by the following equation: f PWM_SS = f GCLK_TC N(TOP+1) Where N represents the prescaler divider used (1, 2, 4, 8, 16, 64, 256, 1024). Match Pulse-Width Modulation Operation (MPWM) In MPWM, the output of WO[1] is depending on CC1 as shown in the figure below. On every overflow/underflow, a one-TC-clock-cycle negative pulse is put out on WO[0] (not shown in the figure). Figure 30-6. Match PWM Operation COUNT MAX CC0 Period (T) " match" ZERO CCx=Zero CC1 CCx=TOP "clear" update WO[1] The table below shows the update counter and overflow event/interrupt generation conditions in different operation modes. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 563

Table 30-2. Counter Update and Overflow Event/interrupt Conditions in TC Name Operation TOP Update Output Waveform OVFIF/Event On Match On Update Up Down NFRQ Normal Frequency PER TOP/ ZERO Toggle Stable TOP ZERO MFRQ Match Frequency CC0 TOP/ ZERO Toggle Stable TOP ZERO NPWM Single-slope PWM PER TOP/ ZERO See description above. TOP ZERO MPWM Single-slope PWM CC0 TOP/ ZERO Toggle Toggle TOP ZERO

30.6.2.6.4 Changing the Top Value

The counter period is changed by writing a new TOP value to the Period register (PER or CC0, depending on the waveform generation mode). If a new TOP value is written when the counter value is close to zero and counting down, the counter can be reloaded with the previous TOP value, due to synchronization delays. Then, the counter will count one extra cycle before the new TOP value is used. COUNT and TOP are continuously compared, so when a new TOP value that is lower than current COUNT is written to TOP, COUNT will wrap before a compare match. A counter wraparound can occur in any operation mode when up-counting without buffering, see the figure below. Figure 30-7. Changing the Top value with Up-Counting Operation COUNT MAX New TOP written to PER that is higher than current COUNT Counter Wraparound New TOP written to PER that is lower than current COUNT "clear" update "write" ZERO Figure 30-8. Changing the Top Value with Down-Counting Operation COUNT MAX New TOP written to PER that is higher than current COUNT New TOP written to PER that is lower than current COUNT "reload" update "write" ZERO SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 564

30.6.2.7 Capture Operations

To enable and use capture operations, the event line into the TC must be enabled using the TC Event Input bit in the Event Control register (EVCTRL.TCEI). The capture channels to be used must also be enabled in the Capture Channel x Enable bit group in the Control C register (CTRLC.CPTENx) before capture can be performed. To enable and use capture operations, the corresponding Capture Channel x Enable bit in the Control C register (CTRLC.CAPTENx) must be written to '1'. Note: The RETRIGGER, COUNT and START event actions are available only on an event from the Event System.

30.6.2.7.1 Event Capture Action

The compare/capture channels can be used as input capture channels to capture events from the Event System and give them a timestamp. The following figure shows four capture events for one capture channel. Figure 30-9. Input Capture Timing events COUNT TOP ZERO Capture 0 Capture 1 Capture 2 Capture 3 The TC can detect capture overflow of the input capture channels: When a new capture event is detected while the Capture Interrupt flag (INTFLAG.MCx) is still set, the new timestamp will not be stored and INTFLAG.ERR will be set.

30.6.2.7.2 Period and Pulse-Width (PPW) Capture Action

The TC can perform two input captures and restart the counter on one of the edges. This enables the TC to measure the pulse width and period and to characterize the frequency f and duty cycle of an input signal: f = 1 T dutyCycle = t p T Selecting PWP (pulse-width, period) in the Event Action bit group in the Event Control register (EVCTRL.EVACT) enables the TC to perform one capture action on the rising edge and the other one on the falling edge. The period T will be captured into CC1 and the pulse width tp in CC0. EVCTRL.EVACT=PPW (period and pulse-width)offers identical functionality, but will capture T into CC0 and tp into CC1. The TC Event Input Invert Enable bit in the Event Control register (EVCTRL.TCINV) is used to select whether the wraparound should occur on the rising edge or the falling edge. If EVCTRL.TCINV=1, the wraparound will happen on the falling edge. To fully characterize the frequency and duty cycle of the input signal, activate capture on CC0 and CC1 by writing 0x3 to the Capture Channel x Enable bit group in the Control C register (CTRLC.CPTEN). When only one of these measurements is required, the second channel can be used for other purposes. The TC can detect capture overflow of the input capture channels: When a new capture event is detected while the Capture Interrupt flag (INTFLAG.MCx) is still set, the new timestamp will not be stored and INTFLAG.ERR will be set. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 565

Figure 30-10. PWP Capture Period (T) external signal events COUNT MAX ZERO "capture" Pulsewitdh (t p) CC0 CC0 CC1CC1

30.6.3 Additional Features

30.6.3.1 One-Shot Operation

When one-shot is enabled, the counter automatically stops on the next counter overflow or underflow condition. When the counter is stopped, the Stop bit in the Status register (STATUS.STOP) is automatically set and the waveform outputs are set to zero. One-shot operation is enabled by writing a '1' to the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT), and disabled by writing a '1' to CTRLBCLR.ONESHOT. When enabled, the TC will count until an overflow or underflow occurs and stops counting operation. The one-shot operation can be restarted by a re-trigger software command, a re-trigger event, or a start event. When the counter restarts its operation, STATUS.STOP is automatically cleared.

30.6.4 DMA, Interrupts and Events

Table 30-3. Module Request for TC Condition Interrupt request Event output Event input DMA request DMA request is cleared Overflow / Underflow YES YES YES Cleared on next clock cycle Channel Compare Match or Capture YES YES YES1 For compare channel – Cleared on next clock cycle. For capture channel – cleared when CCx register is read Capture Overflow Error YES Synchronization Ready YES SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 566

Event output Event input DMA request DMA request is cleared Start Counter YES Retrigger Counter YES Increment / Decrement counter YES Simple Capture YES Period Capture YES Pulse Width Capture YES Note: 1. Two DMA requests lines are available, one for each compare/capture channel.

30.6.4.1 DMA Operation

The TC can generate the following DMA requests:

Overflow (OVF): the request is set when an update condition (overflow, underflow) is detected. The request is cleared on next clock cycle.
Channel Match or Capture (MCx): for a compare channel, the request is set on each compare match detection and cleared on next clock cycle. For a capture channel, the request is set when valid data is present in CCx register, and cleared when CCx register is read. When using the TC with the DMA OVF request, the new value will be transferred to the register after the update condition. This means that the value is updated after the DMA and synchronization delay, and if the COUNT value has reached the new value before PER or CCx is updated, a match will not happen. When using the TC with the DMA MCx request and updating CCx with a value that is lower than the current COUNT when down-counting, or higher than the current COUNT when up-counting, this value could cause a new compare match before the counter overflows. This will trigger the next DMA transfer, update CCx again, and the previous value is disregarded from the output signal WO[x].

30.6.4.2 Interrupts

The TC has the following interrupt sources:

Overflow/Underflow (OVF)
Match or Capture Channel x (MCx)
Capture Overflow Error (ERR)
Synchronization Ready (SYNCRDY) Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the TC is reset. on how to clear interrupt flags. The TC has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register to determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector Interrupt Controller for details. Related Links

30.6.4.3 Events

The TC can generate the following output events:

Overflow/Underflow (OVF)
Match or Capture (MC) Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.MCEOx) enables the corresponding output event. The output event is disabled by writing EVCTRL.MCEOx=0. One of the following event actions can be selected by the Event Action bit group in the Event Control register (EVCTRL.EVACT):
Start TC (START)
Re-trigger TC (RETRIGGER)
Increment or decrement counter (depends on counter direction)
Count on event (COUNT)
Capture Period (PPW and PWP) Writing a '1' to the TC Event Input bit in the Event Control register (EVCTRL.TCEI) enables input events to the TC. Writing a '0' to this bit disables input events to the TC. The TC requires only asynchronous event inputs. For further details on how configuring the asynchronous events, refer to EVSYS - Event System. Related Links 24. EVSYS – Event System

30.6.5 Sleep Mode Operation

The TC can be configured to operate in any sleep mode. To be able to run in standby, the RUNSTDBY bit in the Control A register (CTRLA.RUNSTDBY) must be written to one. The TC can wake up the device using interrupts from any sleep mode or perform actions through the Event System.

30.6.6 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written:

Software Reset bit in the Control A register (CTRLA.SWRST)
Enable bit in the Control A register (CTRLA.ENABLE) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. The following registers are synchronized when written:
Control B Clear register (CTRLBCLR)
Control B Set register (CTRLBSET)
Control C register (CTRLC)
Count Value register (COUNT)
Period Value register (PER)
Compare/Capture Value registers (CCx) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. The following registers are synchronized when read:
Control B Clear register (CTRLBCLR)
Control B Set register (CTRLBSET)
Control C register (CTRLC)
Count Value register (COUNT)
Period Value register (PER)
Compare/Capture Value registers (CCx) Required read-synchronization is denoted by the "Read-Synchronized" property in the register description. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 568

30.7 Register Summary for 8-bit Registers

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 WAVEGEN[1:0] MODE[1:0] ENABLE SWRST 15:8 PRESCSYNC[1:0] RUNSTDBY PRESCALER[2:0] 0x02 READREQ 7:0 ADDR[4:0] 15:8 RREQ RCONT 0x04 CTRLBCLR 7:0 CMD[1:0] ONESHOT DIR 0x05 CTRLBSET 7:0 CMD[1:0] ONESHOT DIR 0x06 CTRLC 7:0 CPTEN1 CPTEN0 INVEN1 INVEN0 0x07 Reserved 0x08 DBGCTRL 7:0 DBGRUN 0x09 Reserved 0x0A EVCTRL 7:0 TCEI TCINV EVACT[2:0] 15:8 MCEO1 MCEO0 OVFEO 0x0C INTENCLR 7:0 MC1 MC0 SYNCRDY ERR OVF 0x0D INTENSET 7:0 MC1 MC0 SYNCRDY ERR OVF 0x0E INTFLAG 7:0 MC1 MC0 SYNCRDY ERR OVF 0x0F STATUS 7:0 SYNCBUSY STOP 0x10 COUNT 7:0 COUNT[7:0] 0x11 ... 0x13 Reserved 0x14 PER 7:0 PER[7:0] 0x15 ... 0x17 Reserved 0x18 CC0 7:0 CC[7:0] 0x19 CC1 7:0 CC[7:0]

30.8 Register Description for 8-bit Registers

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write- protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 30.5.8 Register Access Protection Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write- Synchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to 30.6.6 Synchronization. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 570

30.8.1 Control A

Name: CTRLA Offset: 0x00 Reset: 0x00000000 Property: PAC Write-Protection, Write-Synchronized, Enable-Protected Bit 15 14 13 12 11 10 9 8 PRESCSYNC[1:0] RUNSTDBY PRESCALER[2:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WAVEGEN[1:0] MODE[1:0] ENABLE SWRST Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bits 13:12 – PRESCSYNC[1:0] Prescaler and Counter Synchronization These bits select whether the counter should wrap around on the next GCLK_TCx clock or the next prescaled GCLK_TCx clock. It also makes it possible to reset the prescaler. These bits are not synchronized. Value Name Description 0x0 GCLK Reload or reset the counter on next generic clock 0x1 PRESC Reload or reset the counter on next prescaler clock 0x2 RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter 0x3 - Reserved Bit 11 – RUNSTDBY Run in Standby This bit is used to keep the TC running in Standby mode. This bit is not synchronized. Value Description 0 The TC is halted in standby. 1 The TC continues to run in standby. Bits 10:8 – PRESCALER[2:0] Prescaler These bits select the counter prescaler factor. These bits are not synchronized. Value Name Description 0x0 DIV1 Prescaler: GCLK_TC 0x1 DIV2 Prescaler: GCLK_TC/2 0x2 DIV4 Prescaler: GCLK_TC/4 0x3 DIV8 Prescaler: GCLK_TC/8 0x4 DIV16 Prescaler: GCLK_TC/16 0x5 DIV64 Prescaler: GCLK_TC/64 0x6 DIV256 Prescaler: GCLK_TC/256 0x7 DIV1024 Prescaler: GCLK_TC/1024 Bits 6:5 – WAVEGEN[1:0] Waveform Generation Operation These bits select the waveform generation operation. They affect the top value, as shown in “Waveform Output Operations”. It also controls whether frequency or PWM waveform generation should be used. How these modes differ can also be seen from “Waveform Output Operations”. These bits are not synchronized. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 571

Table 30-4. Waveform Generation Operation Value Name Operation Top Value Waveform Output on Match Waveform Output on Wraparound 0x0 NFRQ Normal frequency PER(1)/Max Toggle No action 0x1 MFRQ Match frequency CC0 Toggle No action 0x2 NPWM Normal PWM PER(1)/Max Clear when counting up Set when counting down Set when counting up Clear when counting down 0x3 MPWM Match PWM CC0 Clear when counting up Set when counting down Set when counting up Clear when counting down Note: 1. This depends on the TC mode. In 8-bit mode, the top value is the Period Value register (PER). In 16- and 32-bit mode it is the maximum value. Bits 3:2 – MODE[1:0] Timer Counter Mode These bits select the Counter mode. These bits are not synchronized. Value Name Description 0x0 COUNT16 Counter in 16-bit mode 0x1 COUNT8 Counter in 8-bit mode 0x2 COUNT32 Counter in 32-bit mode 0x3 - Reserved Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately, and the ENABLE Synchronization Busy bit in the SYNCBUSY register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not enable protected. Value Description 0 The peripheral is disabled. 1 The peripheral is enabled. Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will be disabled. Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is not enable protected. Value Description 0 There is no reset operation ongoing. 1 The reset operation is ongoing. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 572

30.8.2 Read Request

Name: READREQ Offset: 0x02 Reset: 0x0000 Bit 15 14 13 12 11 10 9 8 RREQ RCONT Access W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[4:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 15 – RREQ Read Request Writing a zero to this bit has no effect. This bit will always read as zero. Writing a one to this bit requests synchronization of the register pointed to by the Address bit group (READREQ. ADDR) and sets the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY). Bit 14 – RCONT Read Continuously When continuous synchronization is enabled, the register pointed to by the Address bit group (READREQ.ADDR) will be synchronized automatically every time the register is updated. READREQ.RCONT prevents READREQ.RREQ from clearing automatically. For the continuous read mode, RREQ bit is required to be set once the RCONT bit is set. Note: Once the continuous synchronization is enabled, the first write in the COUNT/CLOCK register will be stalled for a maximum of 6 APB + 6 TC clock cycles (the time for the on-going read synchronization to complete). Value Description 0 Continuous synchronization is disabled. 1 Continuous synchronization is enabled. Bits 4:0 – ADDR[4:0] Address These bits select the offset of the register that needs read synchronization. In the TC, only COUNT and CCx are available for read synchronization. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 573

30.8.3 Control B Clear

Name: CTRLBCLR Offset: 0x04 Reset: 0x00 Property: PAC Write-Protection, Read-Synchronized, Write-Synchronized This register allows the user to clear bits in the CTRLB register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set register (CTRLBSET). Bit 7 6 5 4 3 2 1 0 CMD[1:0] ONESHOT DIR Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 7:6 – CMD[1:0] Command These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC clock cycle. When a command has been executed, the CMD bit group will be read back as zero. Writing 0x0 to these bits has no effect. Writing a '1' to any of these bits will clear the pending command. Table 30-5. Command Value Name Description 0x0 NONE No action 0x1 RETRIGGER Force a start, restart or retrigger 0x2 STOP Force a stop 0x3 - Reserved Bit 2 – ONESHOT One-Shot on Counter This bit controls one-shot operation of the TC. Writing a '0' to this bit has no effect Writing a '1' to this bit will disable one-shot operation. Value Description 0 The TC will wrap around and continue counting on an Overflow/Underflow condition. 1 The TC will wrap around and stop on the next Underflow/Overflow condition. Bit 0 – DIR Counter Direction This bit is used to change the direction of the counter. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the bit and make the counter count up. Value Description 0 The timer/counter is counting up (incrementing). 1 The timer/counter is counting down (decrementing). SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 574

30.8.4 Control B Set

Name: CTRLBSET Offset: 0x05 Reset: 0x00 Property: PAC Write-Protection, Read-synchronized, Write-Synchronized This register allows the user to set bits in the CTRLB register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Clear register (CTRLBCLR). Bit 7 6 5 4 3 2 1 0 CMD[1:0] ONESHOT DIR Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 7:6 – CMD[1:0] Command These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC clock cycle. When a command has been executed, the CMD bit group will be read back as zero. Writing 0x0 to these bits has no effect. Writing a '1' to one of these bits will set a command. Table 30-6. Command Value Name Description 0x0 NONE No action 0x1 RETRIGGER Force a start, restart or retrigger 0x2 STOP Force a stop 0x3 - Reserved Bit 2 – ONESHOT One-Shot on Counter This bit controls one-shot operation of the TC. Writing a '0' to this bit has no effect Writing a '1' to this bit will enable one-shot operation. Value Description 0 The TC will wrap around and continue counting on an Overflow/Underflow condition. 1 The TC will wrap around and stop on the next Underflow/Overflow condition. Bit 0 – DIR Counter Direction This bit is used to change the direction of the counter. Writing a '0' to this bit has no effect. Writing a '1' to this bit will make the counter count down. Value Description 0 The timer/counter is counting up (incrementing). 1 The timer/counter is counting down (decrementing). SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 575

30.8.5 Control C

Name: CTRLC Offset: 0x06 Reset: 0x00 Property: PAC Write-Protection, Read-synchronized, Write-Synchronized Bit 7 6 5 4 3 2 1 0 CPTEN1 CPTEN0 INVEN1 INVEN0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 4, 5 – CPTENx Capture Channel x Enable These bits are used to select the capture or compare operation on channel x. Writing a '1' to CPTENx enables capture on channel x. Writing a '0' to CPTENx disables capture on channel x. Bits 0, 1 – INVENx Waveform Output x Inversion Enable These bits are used to select inversion on the output of channel x. Writing a '1' to INVENx inverts output from WO[x]. Writing a '0' to INVENx disables inversion of output from WO[x]. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 576

30.8.6 Debug Control

Name: DBGCTRL Offset: 0x08 Reset: 0x00 Property: PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Debug Run Mode This bit is not affected by a software Reset, and should not be changed by software while the TC is enabled. Value Description 0 The TC is halted when the device is halted in Debug mode. 1 The TC continues normal operation when the device is halted in Debug mode. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 577

30.8.7 Event Control

Name: EVCTRL Offset: 0x0A Reset: 0x0000 Property: PAC Write-Protection, Enable-Protected Bit 15 14 13 12 11 10 9 8 MCEO1 MCEO0 OVFEO Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 TCEI TCINV EVACT[2:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bits 12, 13 – MCEOx Match or Capture Channel x Event Output Enable [x = 1..0] These bits enable the generation of an event for every match or capture on channel x. Value Description 0 Match/Capture event on channel x is disabled and will not be generated. 1 Match/Capture event on channel x is enabled and will be generated for every compare/capture. Bit 8 – OVFEO Overflow/Underflow Event Output Enable This bit enables the Overflow/Underflow event. When enabled, an event will be generated when the counter overflows/underflows. Value Description 0 Overflow/Underflow event is disabled and will not be generated. 1 Overflow/Underflow event is enabled and will be generated for every counter overflow/underflow. Bit 5 – TCEI TC Event Enable This bit is used to enable asynchronous input events to the TC. Value Description 0 Incoming events are disabled. 1 Incoming events are enabled. Bit 4 – TCINV TC Inverted Event Input Polarity This bit inverts the asynchronous input event source. Value Description 0 Input event source is not inverted. 1 Input event source is inverted. Bits 2:0 – EVACT[2:0] Event Action These bits define the event action the TC will perform on an event. Value Name Description 0x0 OFF Event action disabled 0x1 RETRIGGER Start, restart or retrigger TC on event 0x2 COUNT Count on event 0x3 START Start TC on event 0x4 - Reserved 0x5 PPW Period captured in CC0, pulse width in CC1 0x6 PWP Period captured in CC1, pulse width in CC0 0x7 - Reserved SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 578

30.8.8 Interrupt Enable Clear

Name: INTENCLR Offset: 0x0C Reset: 0x00 Property: PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 5 4 3 2 1 0 MC1 MC0 SYNCRDY ERR OVF Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bits 4, 5 – MCx Match or Capture Channel x Interrupt Enable [x = 1..0] Writing a '0' to these bits has no effect. Writing a '1' to MCx will clear the corresponding Match or Capture Channel x Interrupt Enable bit, which disables the Match or Capture Channel x interrupt. Value Description 0 The Match or Capture Channel x interrupt is disabled. 1 The Match or Capture Channel x interrupt is enabled. Bit 3 – SYNCRDY Synchronization Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a one to this bit will clear the Synchronization Ready Interrupt Disable/Enable bit, which disables the Synchronization Ready interrupt. Value Description 0 The Synchronization Ready interrupt is disabled. 1 The Synchronization Ready interrupt is enabled. Bit 1 – ERR Error Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. Value Description 0 The Error interrupt is disabled. 1 The Error interrupt is enabled. Bit 0 – OVF Overflow Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt request. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 579

30.8.9 Interrupt Enable Set

Name: INTENSET Offset: 0x0D Reset: 0x00 Property: PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 5 4 3 2 1 0 MC1 MC0 SYNCRDY ERR OVF Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bits 4, 5 – MCx Match or Capture Channel x Interrupt Enable [x = 1..0] Writing a '0' to these bits has no effect. Writing a '1' to MCx will set the corresponding Match or Capture Channel x Interrupt Enable bit, which enables the Match or Capture Channel x interrupt. Value Description 0 The Match or Capture Channel x interrupt is disabled. 1 The Match or Capture Channel x interrupt is enabled. Bit 3 – SYNCRDY Synchronization Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a one to this bit will clear the Synchronization Ready Interrupt Disable/Enable bit, which disables the Synchronization Ready interrupt. Value Description 0 The Synchronization Ready interrupt is disabled. 1 The Synchronization Ready interrupt is enabled. Bit 1 – ERR Error Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. Value Description 0 The Error interrupt is disabled. 1 The Error interrupt is enabled. Bit 0 – OVF Overflow Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt request. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 580

30.8.10 Interrupt Flag Status and Clear

Name: INTFLAG Offset: 0x0E Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 MC1 MC0 SYNCRDY ERR OVF Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bits 4, 5 – MCx Match or Capture Channel x [x = 1..0] This flag is set on a comparison match, or when the corresponding CCx register contains a valid capture value. This flag is set on the next CLK_TC_CNT cycle, and will generate an interrupt request if the corresponding Match or Capture Channel x Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.MCx) is '1'. Writing a '0' to one of these bits has no effect. Writing a '1' to one of these bits will clear the corresponding Match or Capture Channel x Interrupt flag In capture operation, this flag is automatically cleared when CCx register is read. Bit 3 – SYNCRDY Synchronization Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a one to this bit will clear the Synchronization Ready Interrupt Disable/Enable bit, which disables the Synchronization Ready interrupt. Value Description 0 The Synchronization Ready interrupt is disabled. 1 The Synchronization Ready interrupt is enabled. Bit 1 – ERR Error Interrupt Flag This flag is set when a new capture occurs on a channel while the corresponding Match or Capture Channel x Interrupt flag is set, in which case there is nowhere to store the new capture. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Error Interrupt flag. Bit 0 – OVF Overflow Interrupt Flag This flag is set on the next CLK_TC_CNT cycle after an Overflow condition occurs, and will generate an interrupt request if INTENCLR.OVF or INTENSET.OVF is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Overflow Interrupt flag. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 581

30.8.11 Status

Name: STATUS Offset: 0x0F Reset: 0x08 Property: - Bit 7 6 5 4 3 2 1 0 SYNCBUSY STOP Access R R Reset 0 1 Bit 7 – SYNCBUSY Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. Bit 3 – STOP Stop Status Flag This bit is set when the TC is disabled, on a Stop command, or on an overflow/underflow condition when the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is '1'. Value Description 0 Counter is running. 1 Counter is stopped. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 582

30.8.12 Counter Value, 8-bit Mode

Name: COUNT Offset: 0x10 Reset: 0x00 Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – COUNT[7:0] Counter Value These bits contain the current counter value. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 583

30.8.13 Period Value, 8-bit Mode

Name: PER Offset: 0x14 Reset: 0xFF Property: Write-Synchronized Bit 7 6 5 4 3 2 1 0 PER[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 1 Bits 7:0 – PER[7:0] Period Value These bits hold the value of the Period Buffer register PERBUF. The value is copied to PER register on UPDATE condition. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 584

30.8.14 Channel x Compare/Capture Value, 8-bit Mode

Name: CCx Offset: 0x18 + x*0x01 [x=0..1] Reset: 0x00 Property: Write-Synchronized Bit 7 6 5 4 3 2 1 0 CC[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – CC[7:0] Channel x Compare/Capture Value These bits contain the compare/capture value in 8-bit TC mode. In Match frequency (MFRQ) or Match PWM (MPWM) waveform operation (CTRLA.WAVEGEN), the CC0 register is used as a period register. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 585

30.9 Register Summary for 16-bit Registers

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 WAVEGEN[1:0] MODE[1:0] ENABLE SWRST 15:8 PRESCSYNC[1:0] RUNSTDBY PRESCALER[2:0] 0x02 READREQ 7:0 ADDR[4:0] 15:8 RREQ RCONT 0x04 CTRLBCLR 7:0 CMD[1:0] ONESHOT DIR 0x05 CTRLBSET 7:0 CMD[1:0] ONESHOT DIR 0x06 CTRLC 7:0 CPTEN1 CPTEN0 INVEN1 INVEN0 0x07 Reserved 0x08 DBGCTRL 7:0 DBGRUN 0x09 Reserved 0x0A EVCTRL 7:0 TCEI TCINV EVACT[2:0] 15:8 MCEO1 MCEO0 OVFEO 0x0C INTENCLR 7:0 MC1 MC0 SYNCRDY ERR OVF 0x0D INTENSET 7:0 MC1 MC0 SYNCRDY ERR OVF 0x0E INTFLAG 7:0 MC1 MC0 SYNCRDY ERR OVF 0x0F STATUS 7:0 SYNCBUSY STOP 0x10 COUNT 7:0 COUNT[7:0] 15:8 COUNT[15:8] 0x12 ... 0x17 Reserved 0x18 CC0 7:0 CC[7:0] 15:8 CC[15:8] 0x1A CC1 7:0 CC[7:0] 15:8 CC[15:8]

30.10 Register Description for 16-bit Registers

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write- protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 30.5.8 Register Access Protection Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write- Synchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to 30.6.6 Synchronization. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 586

30.10.1 Control A

Table 30-7. Waveform Generation Operation Value Name Operation Top Value Waveform Output on Match Waveform Output on Wraparound 0x0 NFRQ Normal frequency PER(1)/Max Toggle No action 0x1 MFRQ Match frequency CC0 Toggle No action 0x2 NPWM Normal PWM PER(1)/Max Clear when counting up Set when counting down Set when counting up Clear when counting down 0x3 MPWM Match PWM CC0 Clear when counting up Set when counting down Set when counting up Clear when counting down Note: 1. This depends on the TC mode. In 8-bit mode, the top value is the Period Value register (PER). In 16- and 32-bit mode it is the maximum value. Bits 3:2 – MODE[1:0] Timer Counter Mode These bits select the Counter mode. These bits are not synchronized. Value Name Description 0x0 COUNT16 Counter in 16-bit mode 0x1 COUNT8 Counter in 8-bit mode 0x2 COUNT32 Counter in 32-bit mode 0x3 - Reserved Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately, and the ENABLE Synchronization Busy bit in the SYNCBUSY register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not enable protected. Value Description 0 The peripheral is disabled. 1 The peripheral is enabled. Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will be disabled. Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is not enable protected. Value Description 0 There is no reset operation ongoing. 1 The reset operation is ongoing. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 588

30.10.2 Read Request

30.10.3 Control B Clear

Name: CTRLBCLR Offset: 0x04 Reset: 0x00 Property: PAC Write-Protection, Read-Synchronized, Write-Synchronized This register allows the user to clear bits in the CTRLB register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set register (CTRLBSET). Bit 7 6 5 4 3 2 1 0 CMD[1:0] ONESHOT DIR Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 7:6 – CMD[1:0] Command These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC clock cycle. When a command has been executed, the CMD bit group will be read back as zero. Writing 0x0 to these bits has no effect. Writing a '1' to any of these bits will clear the pending command. Table 30-8. Command Value Name Description 0x0 NONE No action 0x1 RETRIGGER Force a start, restart or retrigger 0x2 STOP Force a stop 0x3 - Reserved Bit 2 – ONESHOT One-Shot on Counter This bit controls one-shot operation of the TC. Writing a '0' to this bit has no effect Writing a '1' to this bit will disable one-shot operation. Value Description 0 The TC will wrap around and continue counting on an Overflow/Underflow condition. 1 The TC will wrap around and stop on the next Underflow/Overflow condition. Bit 0 – DIR Counter Direction This bit is used to change the direction of the counter. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the bit and make the counter count up. Value Description 0 The timer/counter is counting up (incrementing). 1 The timer/counter is counting down (decrementing). SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 590

30.10.4 Control B Set

Name: CTRLBSET Offset: 0x05 Reset: 0x00 Property: PAC Write-Protection, Read-synchronized, Write-Synchronized This register allows the user to set bits in the CTRLB register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Clear register (CTRLBCLR). Bit 7 6 5 4 3 2 1 0 CMD[1:0] ONESHOT DIR Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 7:6 – CMD[1:0] Command These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC clock cycle. When a command has been executed, the CMD bit group will be read back as zero. Writing 0x0 to these bits has no effect. Writing a '1' to one of these bits will set a command. Table 30-9. Command Value Name Description 0x0 NONE No action 0x1 RETRIGGER Force a start, restart or retrigger 0x2 STOP Force a stop 0x3 - Reserved Bit 2 – ONESHOT One-Shot on Counter This bit controls one-shot operation of the TC. Writing a '0' to this bit has no effect Writing a '1' to this bit will enable one-shot operation. Value Description 0 The TC will wrap around and continue counting on an Overflow/Underflow condition. 1 The TC will wrap around and stop on the next Underflow/Overflow condition. Bit 0 – DIR Counter Direction This bit is used to change the direction of the counter. Writing a '0' to this bit has no effect. Writing a '1' to this bit will make the counter count down. Value Description 0 The timer/counter is counting up (incrementing). 1 The timer/counter is counting down (decrementing). SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 591

30.10.5 Control C

30.10.6 Debug Control

30.10.7 Event Control

30.10.8 Interrupt Enable Clear

30.10.9 Interrupt Enable Set

30.10.10 Interrupt Flag Status and Clear

30.10.11 Status

30.10.12 Counter Value, 16-bit Mode

Name: COUNT Offset: 0x10 Reset: 0x00 Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized Bit 15 14 13 12 11 10 9 8 COUNT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – COUNT[15:0] Counter Value These bits contain the current counter value. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 599

30.10.13 Channel x Compare/Capture Value, 16-bit Mode

Name: CCx Offset: 0x18 + x*0x02 [x=0..1] Reset: 0x0000 Property: Write-Synchronized Bit 15 14 13 12 11 10 9 8 CC[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CC[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – CC[15:0] Channel x Compare/Capture Value These bits contain the compare/capture value in 16-bit TC mode. In Match frequency (MFRQ) or Match PWM (MPWM) waveform operation (CTRLA.WAVEGEN), the CC0 register is used as a period register. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 600

30.11 Register Summary for 32-bit Registers

Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 7:0 WAVEGEN[1:0] MODE[1:0] ENABLE SWRST 15:8 PRESCSYNC[1:0] RUNSTDBY PRESCALER[2:0] 0x02 READREQ 7:0 ADDR[4:0] 15:8 RREQ RCONT 0x04 CTRLBCLR 7:0 CMD[1:0] ONESHOT DIR 0x05 CTRLBSET 7:0 CMD[1:0] ONESHOT DIR 0x06 CTRLC 7:0 CPTEN1 CPTEN0 INVEN1 INVEN0 0x07 Reserved 0x08 DBGCTRL 7:0 DBGRUN 0x09 Reserved 0x0A EVCTRL 7:0 TCEI TCINV EVACT[2:0] 15:8 MCEO1 MCEO0 OVFEO 0x0C INTENCLR 7:0 MC1 MC0 SYNCRDY ERR OVF 0x0D INTENSET 7:0 MC1 MC0 SYNCRDY ERR OVF 0x0E INTFLAG 7:0 MC1 MC0 SYNCRDY ERR OVF 0x0F STATUS 7:0 SYNCBUSY SLAVE STOP 0x10 COUNT 7:0 COUNT[7:0] 15:8 COUNT[15:8] 23:16 COUNT[23:16] 31:24 COUNT[31:24] 0x14 ... 0x17 Reserved 0x18 CC0 7:0 CC[7:0] 15:8 CC[15:8] 23:16 CC[23:16] 31:24 CC[31:24] 0x1C CC1 7:0 CC[7:0] 15:8 CC[15:8] 23:16 CC[23:16] 31:24 CC[31:24]

30.12 Register Description for 32-bit Registers

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write- protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 30.5.8 Register Access Protection Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write- Synchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to 30.6.6 Synchronization. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable- protection is denoted by the "Enable-Protected" property in each individual register description. SAM D21/DA1 Family TC – Timer/Counter © 2021 Microchip Technology Inc. Complete Datasheet DS40001882G-page 601

30.12.1 Control A

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Product Information

SAM-D21 specifications and overview.

Summary

Low-Power, 32-bit Cortex-M0+ MCU with Advanced Analog and PWM 2021

Description

Low-Power, 32-bit Cortex-M0+ MCU with Advanced Analog and PWM 2021

Source title SAM-D21 Datasheet(PDF) - Microchip Technology

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