SAF1508BET

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Technical content

1. General description The SAF1508BET is a UTMI+ Low Pin Interface (ULPI) Universal Serial Bus (USB) transceiver that is fully compliant with Universal Serial Bus Specification Rev. 2.0, On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 and UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. The SAF1508BET can transmit and receive USB data at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer front-end attachment to the USB host, peripheral or On-The-Go (OTG) controller with Single Data Rate (SDR) or Dual Data Rate (DDR) ULPI interface. The SAF1508BET can transparently transmit and receive UART signaling. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs) or any system chip set to interface with the physical layer of the USB through an 8-pin (DDR) or 12-pin (SDR) synchronous digital interface. The SAF1508BET can interface to devices with digital I/O voltages in the range of 1.4 V to 1.95 V. The SAF1508BET is available in TFBGA36 package. 2. Features and benefits  Fully complies with:  USB: Universal Serial Bus Specification Rev. 2.0  OTG: On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3  ULPI: UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1  Interfaces to USB host, peripheral or OTG cores; optimized for system ASICs with built-in ULPI link  Complete Hi-Speed USB physical front-end solution that supports high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)  Integrated 45  high-speed termination resistors, 1.5 k full-speed device pull-up resistor, and 15 k host termination resistors  Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive  USB clock and data recovery to receive USB data up to 500 ppm  Insertion of stuff bits during transmit and discarding of stuff bits during receive  Non-Return-to-Zero Inverted (NRZI) encoding and decoding  Supports bus reset, suspend, resume and high-speed detection handshake (chirp) SAF1508BET ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver Rev. 2 — 23 July 2012 Product data sheet

Product data sheet Rev. 2 — 23 July 2012 2 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver  Complete USB OTG physical front-end that supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)  Supports external charge pump or external VBUS power switch  Complete control over USB termination resistors  Data line and VBUS pulsing session request methods  Integrated VBUS voltage comparators  Integrated cable (ID) detector  Flexible system integration and very low power consumption  3.0 V to 4.5 V power supply input range  Internal voltage regulator supplies 2.7 V or 3.3 V and 1.8 V  Supports interfacing I/O voltage of 1.4 V to 1.95 V; separate I/O voltage supply pins minimize crosstalk  Power-down internal regulators in power-down mode when VCC(I/O) is not present or the CHIP_SEL pin is not active  Typical operating current of 13 mA to 32 mA, depending on the USB speed and bus utilization  Typical V CC power consumption in suspend mode is 70 A and in power-down mode is 0.5 A  3-state ULPI interface by the CHIP_SEL pin, allowing bus reuse by other

applications

 Highly optimized ULPI-compliant interface  60 MHz, 8-pin or 12-pin interface between the core and the transceiver, including a 4-bit DDR bus or an 8-bit SDR bus  DDR or SDR interface selectable by pin  Supports 60 MHz output clock configuration  Integrated Phase-Locked Loop (PLL) supporting crystal or clock frequencies of 13 MHz, 19.2 MHz, 24 MHz or 26 MHz  Crystal or clock frequency selectable by pin  Fully programmable ULPI-compliant register set  3-pin or 6-pin full-speed or low-speed serial mode  Internal Power-On Reset (POR) circuit  UART interface:  Supports transparent UART signaling on pins DP and DM for the UART accessory application  2.7 V UART signaling on pins DP and DM  Entering UART mode by register setting  Exiting UART mode by asserting STP or by toggling the CHIP_SEL pin  Full industrial grade operating temperature range from 40 C to +85 C  ESD compliance:  JESD22-A114D, 2 kV contact Human Body Model (HBM)  JESD22-A115-A, 200 V Machine Model (MM)  JESD22-C101C, 500 V Charge Device Model (CDM)  Available in small TFBGA36 (3.5 mm  3.5 mm) Restriction of Hazardous Substances (RoHS) compliant, halogen-free and lead-free package

resulting from such inclusion or use. Table 1. Ordering information

Product data sheet Rev. 2 — 23 July 2012 4 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver 5. Block diagram Fig 1. Block diagram REGISTER MAP ULPI INTERFACE CONTROLLER USB DATA SERIALIZER USB DATA DESERIALIZER HI-SPEED USB ATX DM DP STP DIR NXT DATA [7:0] 001aai303 CLOCK TERMINATION RESISTORS PLL CRYSTAL OSCILLATOR VOLTAGE REGULATOR BAND GAP REFERENCE VOLTAGE RREF internal power VCC REG1V8 REG3V3 GLOBAL CLOCKS XTAL2 XTAL1 VCC(I/O) interface voltage VBUS SAF1508 ULPI INTERFACE VREF CHIP_SEL UART BUFFER DATA0 DDR OR SDR SELECTION CLOCK FREQUENCY SELECTION ID DETECTOR SRP CHARGE AND DISCHARGE RESISTORS OTG MODULE VBUS COMPARATORS PORT POWER CONTROL FAULT PSW_N CFG0 CFG1 CFG2 POWER-ON RESET POR GND ID C6, B6, A6, A5, A3, A2, A1, B1 B2, B5 C5, D2, E4 DATA1 TEST_N n.c.F1, F2

6.1 Pinning

6.2 Pin description

Table 2. Pin description

• USB mode: D input or output
• UART mode: TXD output RREF C2 AI/O resistor reference; connect through a 12 k  1 % resistor to GND CHIP_SEL C3 I • When this pin is not active, ULPI pins will be in 3-state and the SAF1508BET is in power-down mode.
• When this pin is active, ULPI pins will operate normally. active LOW chip select input; if this pin is not in use, connect it to GND plain input TEST_N C4 I directly connect to V CC(I/O) for normal operation plain input (active LOW) DATA7 C6 I/O ULPI data pin 7; when DDR mode is selected, this pin can be left open 3-state output; plain input DP D1 AI/O connect to the D+ pin of the USB connector
• USB mode: D+ input or output
• UART mode: RXD input ID D3 I IDentification (ID) pin of the micro-USB connector; if this pin is not in use, leave it open (an internal 400 k pull-up resistor is present on this pin) plain input; TTL PSW_N D4 OD active LOW external V BUS power switch or external charge pump enable open-drain output; 4 mA current sinking capability; 5 V tolerant NXT D5 O ULPI next signal 3-state output STP D6 I ULPI stop signal plain input CFG0 E1 I Select SDR or DDR ULPI interface
• SDR: connect this pin to GND
• DDR: connect this pin to REG3V3 plain input; TTL FAULT E2 I input for the V BUS digital overcurrent or fault detector signal; if this pin is not in use, connect it to GND plain input; 5 V tolerant REG3V3 E3 P 3.3 V regulator output for USB mode or 2.7 V regulator output for UART mode; requires parallel 0.1 F and 4.7 F capacitors; internally powers ATX and other analog circuits; must not be used to power external circuits GND C5, D2, E4 P ground supply DIR E5 O ULPI direction signal 3-state output REG1V8 E6 P 1.8 V regulator output; requires parallel 0.1 F and 4.7 F capacitors; internally powers the digital core; must not be used to power external circuits n.c. F1, F2 - not connected; leave this pin open V CC F3 P input supply voltage or battery source; 3.0 V to 4.5 V Remark: Below 3.0 V, USB full-speed and low-speed transactions are not guaranteed, though some devices may work with the SAF1508BET at these voltages.

Table 2. Pin description …continued

[1] Symbol names ending with underscore N (for example, NAME_N) indicate active LOW signals. [2] I = input; O = output; I/O = digital input/output; OD = open-drain output; AI/O = analog input/output; P = power or ground pin. [3] A detailed description of these pins can be found in Section 7.

1. Detailed description of pins

7.1 DATA[7:0] pins

of CLOCK, and DATA[7:4] can be left unconnected. These pins can also be 3-stated when pin CHIP_SEL is not active. synchronous mode. For details, see Section 9.2.

7.2 V CC(I/O) pin

• CFG1
• CFG2
• CHIP_SEL
• CLOCK
• DATA[7:0]
• DIR
• NXT
• STP
• TEST_N VBUS F4 AI/O connect to the V BUS pin of the USB connector; if this pin is not in use, leave it open (an internal 70 k pull-down resistor is present on this pin) XTAL1 F5 AI/O crystal oscillator or clock input; 1.8 V peak input allowed; frequency depends on status on the CFG1 and CFG2 pins XTAL2 F6 AI/O crystal oscillator output; when a clock is driven into the XTAL1 pin, leave this pin open

7.3 RREF pin

for analog circuits, thus the USB signal quality.

7.4 DP and DM pins

and the DM pin functions as the USB data minus line. RXD input pin, and the DM pin functions as the UART TXD output pin. The DP and DM pins must be connected to the D+ and D pins of the USB receptacle.

7.5 FAULT pin

be connected to ground to avoid floating input. sending RXCMDs on the ULPI bus. FAULT input will trigger RXCMD carrying the FAULT condition with A_VBUS_VLD.

7.6 PSW_N pin

resistor is required. This allows for per-port or ganged power control. DRV_VBUS_EXT bit in the OTG Control register to logic 1. Table 3 summarizes settings to drive 5 V on VBUS. Table 3. OTG Control register power control bits

7.7 ID pin

role. Roles can be swapped at a later time by using HNP. pull-up resistor is always enabled to avoid the possible floating condition on the ID pin. The ID pin can be left open when not in use.

7.8 V CC pin

7.9 V BUS pin

charge and discharge resistors. For details, see Figure 3. values for various applications. Table 4. Recommended V BUS capacitor value

7.10 REG3V3 and REG1V8 pins

internally to power digital and analog circuits. 0.1 F capacitor in parallel with a 4.7 F low ESR capacitor.

• CFG0
• DM
• DP
• FAULT
• ID
• PSW_N
• RREF

7.11 XTAL1 and XTAL2 pins

Table 5. Allowed crystal or clock frequency on the XTAL1 pin

XTAL2 must be left open when a clock is driven into XTAL1. [1] Specified by the crystal manufacturer. [1] Specified by the crystal manufacturer.

7.12 CHIP_SEL pin

addition the STP input is ignored; internal circuits are powered-down as well. When CHIP_SEL is active, the SAF1508BET will operate normally.

7.13 DIR pin

data bus to be an input. When DIR is LOW, the SAF1508BET listens for data from the link.

• To send the USB receive data, RXCMD status updates and register reads data to the link.
• To block the link from driving the data bus during power-up, reset and low power (suspend) mode. This pin can be 3-stated when the CHIP_SEL pin is not active. 012 6 MHz 102 4 MHz 111 3 MHz

Table 6. External capacitor values for 13 MHz or 19.2 MHz clock frequency Table 7. External capacitor values for 24 MHz or 26 MHz clock frequency Table 5. Allowed crystal or clock frequency on the XTAL1 pin …continued

Product data sheet Rev. 2 — 23 July 2012 12 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver

7.14 STP pin

ULPI stop input pin. Synchronous to the rising edge of CLOCK. The link must assert STP to signal the end of a USB transmit packet or a register write operation. When DIR is asserted, the link can optionally assert STP for one cycle to abort the SAF1508BET, causing it to deassert DIR in the next clock cycle.

7.15 NXT pin

ULPI next data output pin. Synchronous to the rising edge of CLOCK. The SAF1508BET holds NXT at LOW, by default. When DIR is LOW and the link is sending data to the SAF1508BET, NXT will be asserted to notify the link to provide the next data byte. When DIR is HIGH and the SAF1508BET is sending data to the link, NXT will be asserted to notify the link that another valid byte is on the bus. NXT is not used for register read data or the RXCMD status update. This pin can be 3-stated when the CHIP_SEL pin is not active.

7.16 CLOCK pin

A 60 MHz interface clock to synchronize the ULPI bus. In SDR mode, all ULPI pins are synchronous to the rising edge of CLOCK. In DDR mode, DATA[3:0] are the only interface pins that are synchronous to both the rising and falling edges of CLOCK. All other pins are synchronous to the rising edge of CLOCK only, including DIR, NXT and STP . The SAF1508BET outputs 60 MHz clock when:

• A crystal is attached between the XTAL1 and XTAL2 pins.
• A clock is driven into the XTAL1 pin, with the XTAL2 pin left unconnected.

7.17 GND pin

Global ground signal. To ensure the correct operation of the SAF1508BET, GND must be soldered to the cleanest available ground.

Product data sheet Rev. 2 — 23 July 2012 13 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver 8. Functional description

8.1 ULPI interface controller

The SAF1508BET provides an 8-pin or 12-pin interface that is compliant with UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. This interface must be connected to a USB link. The ULPI interface controller provides the following functions:

• ULPI-compliant interface and register set
• Allows full control over the USB peripheral, host or OTG functionality
• Parses the USB transmit and receive data
• Prioritizes the USB receive data, USB transmit data, interrupts and register operations
• Low-power mode
• Transparent UART mode
• 3-pin serial mode
• 6-pin serial mode
• Generates RXCMDs (status updates)
• Maskable interrupts For more information on the ULPI protocol, see Section 10.

8.2 USB serializer and deserializer

The USB data serializer prepares data to transmit on the USB bus. To transmit data, the USB link sends a transmit command and data on the ULPI bus. The serializer performs parallel-to-serial conversion, bit stuffing and NRZI encoding. For packets with a Package IDentifier (PID), the serializer adds a SYNC pattern to the start of the packet, and an EOP pattern to the end of the packet. When the serializer is busy and cannot accept any more data, the ULPI interface controller deasserts NXT. The USB data deserializer decodes data received from the USB bus. When data is received, the deserializer strips the SYNC and EOP patterns, and then performs serial-to-parallel conversion, NRZI decoding and discarding of stuff bits on the data payload. The ULPI interface controller sends data to the USB link by asserting DIR, and then asserting NXT whenever a byte is ready. The deserializer also detects various receive errors, including bit stuff errors, elasticity buffer underrun or overrun, and byte-alignment errors. 8.3 Hi-Speed USB (USB 2.0) ATX The Hi-Speed USB ATX block is an analog front-end containing the circuitry needed to transmit, receive and terminate the USB bus in high-speed, full-speed and low-speed, for USB peripheral, host or OTG implementations. The following circuitry is included:

• Differential drivers to transmit data at high-speed, full-speed and low-speed
• Differential and single-ended receivers to receive data at high-speed, full-speed and low-speed

Product data sheet Rev. 2 — 23 July 2012 14 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver

• Squelch circuit to detect high-speed bus activity
• High-speed disconnect detector
• 45  high-speed bus terminations on DP and DM
• 1.5 k pull-up resistor on DP
• 15 k bus terminations on DP and DM For details on controlling resistor settings, see Table 14.

8.4 Voltage regulator

The SAF1508BET contains a built-in voltage regulator that conditions the VCC supply for use inside the SAF1508BET. The voltage regulator:

• Supports input supply range 3.0 V < VCC <4 . 5V .
• Can be supplied from a battery with the preceding voltage range.
• Supplies internal digital circuitry with 1.8 V and analog circuitry with 3.3 V or 2.7 V.
• In USB mode, automatically bypasses the internal 3.3 V regulator when VCC <3 . 5V , the internal analog circuitry directly draws power from the VCC pin. In UART mode, the bypass switch will be disabled.
• Will be shut down when VCC(I/O) is not present or when the CHIP_SEL pin is not active.

8.5 Crystal oscillator and PLL

The SAF1508BET has a built-in crystal oscillator and a Phase-Locked Loop (PLL) for clock generation. When a crystal is in use, the built-in crystal oscillator generates a square wave clock for internal use. A square wave clock of the same frequency can also be driven directly into the XTAL1 pin. Using an existing square wave clock can save the cost of the crystal and also reduce the board space. The crystal or clock frequencies supported are 13 MHz, 19.2 MHz, 24 MHz and 26 MHz. The PLL takes the square wave clock from the crystal oscillator, and multiplies or divides it into various frequencies for internal use. The PLL produces the following frequencies, irrespective of the clock source:

• 1.5 MHz for low-speed USB data
• 12 MHz for full-speed USB data
• 60 MHz clock for the ULPI interface controller
• 480 MHz for high-speed USB data
• Other internal frequencies for data conversion and data recovery

8.6 UART buffer

The UART buffer includes circuits to support the transparent UART signaling between the DATA0 or DATA1 pin and the DM or DP pin. When the SAF1508BET is put into UART mode, it acts as a voltage level shifter between the following pins:

Product data sheet Rev. 2 — 23 July 2012 15 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver

• From DATA0 (VCC(I/O) level) to DM (2.7 V level) for the UART TXD signaling path.
• From DP (2.7 V level) to DATA1 (VCC(I/O) level) for the UART RXD signaling path.

8.7 OTG module

This module contains several sub-blocks that provide all the functionality required by the USB OTG specification. Specifically, it provides the following circuits:

• The ID detector to sense the ID pin of the micro-USB cable. The ID pin dictates which device is initially configured as a host and which as a peripheral.
• VBUS comparators to determine the VBUS voltage level. This is required for the VBUS detection, SRP and HNP.
• Resistors to temporarily charge and discharge VBUS. This is required for SRP.

8.7.1 ID detector

The ID detector detects which end of the micro-USB cable is plugged in. The ID detector must first be enabled by setting the ID_PULLUP register bit to logic 1. If the SAF1508BET senses a value on the ID pin that is different from the previously reported value, an RXCMD status update will be sent to the USB link, or an interrupt will be asserted.

• If the micro-B end of the cable is plugged in (or nothing is plugged in), the SAF1508BET will report that ID_GND is logic 1. The USB link must be in the B-device state.
• If the micro-A end of the cable is plugged in, the SAF1508BET will report that ID_GND is logic 0. The USB link must be in the A-device state. The ID pin has a weak pull-up resistor (RweakPU(ID)) permanently enabled to avoid the floating condition.

8.7.2 V BUS comparators

The SAF1508BET provides three comparators to detect the VBUS voltage level. The comparators are explained in the following subsections.

8.7.2.1 V BUS valid comparator

This comparator is used only by hosts and A-devices to determine whether the voltage on VBUS is at a valid level for operation. The SAF1508BET minimum threshold for the VBUS valid comparator is 4.4 V. Any voltage on VBUS below this threshold is considered invalid. During power-up, it is expected that the comparator output will be ignored.

8.7.2.2 Session valid comparator

The session valid comparator is a TTL-level input that determines when VBUS is high enough for a session to start. Peripherals, A-devices and B-devices use this comparator to detect when a session is started. The A-device also uses this comparator to determine when a session is completed. The session valid threshold of the SAF1508BET is between 0.8 V to 2.0 V.

8.7.2.3 Session end comparator

The session end comparator determines when V BUS is below the B-device session end threshold of 0.2 V to 0.8 V. The B-device uses this threshold to determine when a session has ended.

Product data sheet Rev. 2 — 23 July 2012 16 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver

8.7.3 SRP charge and discharge resistors

The SAF1508BET provides on-chip resistors for short-term charging and discharging of VBUS. These are used by the B-device to request a session, prompting the A-device to restore the VBUS power. First, the B-device makes sure that VBUS is fully discharged from the previous session by setting the DISCHRG_VBUS register bit to logic 1 and waiting for SESS_END to be logic 1. Then the B-device charges VBUS by setting the CHRG_VBUS register bit to logic 1. The A-device sees that VBUS is charged above the session valid threshold and starts a session by turning on the VBUS power.

8.8 Port power control

For an OTG or host application, the SAF1508BET uses the PSW_N pin to control the external power switch for the VBUS 5 V supply. The overcurrent detector output of the external power switch can be connected to the FAULT pin of the SAF1508BET to indicate to the ULPI link the V BUS overcurrent status. For the connection scheme, see Figure 4. When the FAULT pin is not used, connect it to GND.

8.9 Band gap reference voltage

The band gap circuit provides a stable internal voltage reference to bias the analog circuitry. This band gap circuit requires an accurate external reference resistor. Connect a 12 k 1 % resistor between the RREF pin and GND.

8.10 Power-On Reset (POR)

An internal POR is generated when REG1V8 rises above VPOR(trip). The internal POR pulse will be generated whenever REG1V8 drops below VPOR(trip) for more than tw(REG1V8_L). To give a better view of the functionality, Figure 5 shows a possible curve of REG1V8. The internal POR starts with logic 0 at t0. At t1, the detector will see the passing of the trip level so that POR pulse is generated to reset all internal circuits. If REG1V8 dips from t2 to t3 for greater than tw(REG1V8_L), another POR pulse is generated. If the dip from t4 to t5 is less than tw(REG1V8_L), the internal POR pulse will not be generated and will remain LOW. Fig 4. Digital overcurrent detection scheme 001aai306 SAF1508 PSW_N FAULT POWER SWITCH WITH FAULT INDICATOR +5 V VBUS VBUS

Product data sheet Rev. 2 — 23 July 2012 17 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver

8.11 Power-up, reset and bus idle sequence

Figure 6 shows a typical start-up sequence. On power-up, the SAF1508BET performs an internal power-on reset and asserts DIR to indicate to the link that the ULPI bus cannot be used. When the internal PLL is stable, the SAF1508BET deasserts DIR and drives 60 MHz clock out from the CLOCK pin. The power-up time depends on the V CC supply rise time, the crystal start-up time, and PLL start-up time tstartup(PLL). When DIR is deasserted, the link must drive the data bus to a valid level. By default, the link must drive data to LOW. Before beginning USB packets, the link must set the RESET bit in the Function Control register to reset the SAF1508BET. After the RESET bit is set, the SAF1508BET will assert DIR until the internal reset completes. The SAF1508BET will automatically deassert DIR and clear the RESET bit when the reset has completed. After every reset, an RXCMD is sent to the link to update USB status information. After this sequence, the ULPI bus is ready for use and the link can start USB operations. If V CC(I/O) is not present or the CHIP_SEL pin is non-active, the SAF1508BET will be kept in power-down mode. In power-down mode, all ULPI interface pins will be put in 3-state, the internal regulator will be shut down (see Table 8), and the total power current from VCC will be less than ICC in power-down mode. The link can do a hardware reset to the SAF1508BET by toggling the CHIP_SEL pin. The recommended sequence is: 1. Deactivate the CHIP_SEL pin. 2. Wait for at least t PWRDN. 3. Activate the CHIP_SEL pin. The recommended power-up sequence for the link is: 1. Apply the V CC and VCC(I/O) power. 2. Activate the CHIP_SEL pin. 3. The link waits for at least t PWRUP, ignoring all the ULPI pin status. 4. The link may start to detect the DIR status level. If DIR is detected LOW, the link may send a RESET command. The ULPI interface is ready for use. Fig 5. Internal power-on reset timing 004aab023 REG1V8 t0 t1 t2 t3 t4 t5 VPOR(trip) POR

Product data sheet Rev. 2 — 23 July 2012 18 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver t1 = VCC is applied to the SAF1508BET. t2 = VCC(I/O) is turned on. ULPI interface pins CLOCK, DATA[7:0], DIR and NXT are in 3-state as long as CHIP_SEL is non-active. t3 = CHIP_SEL turns from non-active to active. The SAF1508BET regulator starts to turn on. ULPI pads are not in 3-state and may drive to either LOW or HIGH. It is recommended that the link ignores ULPI pins status during tPWRUP. t4 = Power-on reset threshold is reached and the POR pulse is generated. After the POR pulse, ULPI pins are driven to a defined level. DIR is driven to HIGH and the other pins are driven to LOW. t5 = The PLL is stabilized after t d(det)clk(osc) +t startup(PLL). The CLOCK pin starts to output 60 MHz. The DIR pin will transition from HIGH to LOW. The link must drive DATA[7:0] and STP to LOW as the idle state. The link will then issue a reset command to initialize the SAF1508BET. t6 = The power-up sequence is completed and the ULPI bus interface is ready for use. Fig 6. Power-up and reset sequence required before the ULPI bus is ready for use CHIP_SEL CLOCK (output) TXCMD DIR DATA[7:0] STP NXT 004aaa870 RESET command internal clocks stable internal reset RXCMD update bus idle D VCC VCC(I/O) REG1V8 Internal POR XTAL1 t1 t2 t3 t4 t5 t6 tPWRUP td(det)clk(osc) + tstartup(PLL)

Product data sheet Rev. 2 — 23 July 2012 19 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver

8.11.1 Interface protection

By default, the SAF1508BET enables a weak pull-up resistor on STP . If the STP pin is unexpectedly HIGH at any time, the SAF1508BET will protect the ULPI interface by enabling weak pull-down resistors on DATA[7:0]. The interface protect feature prevents unwanted activity of the SAF1508BET whenever the ULPI interface is not correctly driven by the link. For example, when the link powers up more slowly than the SAF1508BET. The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1.

8.11.2 Interface behavior with respect to the CHIP_SEL pin

The use of the CHIP_SEL pin is optional. When not active, ULPI pins will be 3-stated and the internal circuitry is powered down. If the CHIP_SEL pin is not used, it must be connected to GND in the SAF1508BET. Figure 7 shows the ULPI interface behavior when the CHIP_SEL pin is asserted and subsequently deasserted. Fig 7. Interface behavior with respect to the CHIP_SEL pin CLOCK 004aaa910 STP CHIP_SEL DATA[7:0] DIR NXT Hi-Z (input) Hi-Z (input) Hi-Z (ignored) Hi-Z (ignored) Hi-Z (ignored) tPWRDN Hi-Z Hi-Z

9.1 Power modes

range will not damage the SAF1508BET chip. SAF1508BET will be fully functional as in normal mode.

9.1.1 Normal mode

SAF1508BET is fully functional.

9.1.2 Power-down mode

and/or VBUS pins. In this mode, the SAF1508BET pin states are given in Table 8. [1] These pins must not be externally driven to HIGH. Otherwise, the SAF1508BET behavior is undefined and leakage current will o ccur. Section 7.10) are not powered. Table 8. Pin states in power-down mode

detect the CHIP_SEL pin status.

9.2 ULPI modes

subsections. Setting more than one mode will lead to undefined behavior.

9.2.1 Synchronous mode

set-up time and the hold time as defined in Section 15.

• High-speed detection handshake (chirp)
• Transmit and receive USB packets
• Read and write to registers
• Receive USB status updates (RXCMDs) from the SAF1508BET For more information on various synchronous mode protocols, see Section 10.

Table 9. ULPI signal description the SAF1508BET will drive a 60 MHz output clock. During low-power, serial and UART modes, the clock is turned off to save power. initiates transfers by sending a nonzero data pattern called a TXCMD (transmit command). DATA[7:0] lines must be ignored for exactly one clock cycle whenever DIR changes value. This is called a turnaround cycle.

9.2.2 Low-power mode

sent if the interrupt condition is removed before exiting. The SAF1508BET will draw only suspend current from the VCC supply. See Table 52. again before asserting STP to exit low-power mode. Interface (ULPI) Specification Rev. 1.1. DIR O Direction: Controls the direction of data bus DATA[7:0]. NXT is LOW, the byte contains status information called an RXCMD (receive command). DIR is always asserted during low-power, serial and UART modes. SAF1508BET, causing the ULPI bus to return to synchronous mode. register read data is to be returned to the link in the current cycle. NXT is not used in low-power, serial and UART modes. Table 10. Signal mapping during low-power mode

register bit must be set to logic 1 before entering 6-pin serial mode. Pin Interface (ULPI) Specification Rev. 1.1. The 6-pin serial mode is not applicable if the SAF1508BET functions as a 4-bit DDR. register bit must be set to logic 1 before entering 3-pin serial mode. Pin Interface (ULPI) Specification Rev. 1.1. Table 10. Signal mapping during low-power mode …continued Table 11. Signal mapping for 6-pin serial mode

9.2.5 Transparent UART mode

• From pin DATA0 (VCC(I/O) level) to pin DM (2.7 V level).
• From pin DP (2.7 V level) to pin DATA1 (VCC(I/O) level). The USB transceiver is used to drive the UART transmitting signal on the DM line. The rise time and the fall time of the transmitting signal is determined by whether a full-speed or low-speed transceiver is in use. It is recommended to use a low-speed transceiver if the UART bit rate is below 921 kbit/s for better ElectroMagnetic Interference (EMI) performance. If the UART bit rate is equal to or above 921 kbit/s, a full-speed transceiver can be used. In transparent UART mode, data bus definitions change to that shown in Table 13 Transparent UART mode is entered by setting some register bits in ULPI registers. The recommended sequence is: 1. Set the XCVRSELECT[1:0] bits in the Functi on Control register to 10b (low-speed) or 01b (full-speed). This setting affects the rise time and the fall time of the UART transmitting signal on the DM line. 2. Set the DP_PULLDOWN and DM_PULLDOWN bits in the OTG Control register to logic 0. 3. Set the TERMSELECT bit in the Function Control register to logic 0 (power-on default value). Remark: Mandatory when a full-speed driver is used and optional for a low-speed driver.

Table 12. Signal mapping for 3-pin serial mode Table 13. UART signal mapping

Product data sheet Rev. 2 — 23 July 2012 25 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver 4. Set the TXD_EN and RXD_EN bits in the ca rkit Control register to logic 1. These two bits must be set together in one TXCMD. 5. Set the CARKIT_MODE bit in the Interface Control register to logic 1. Remark: The CARKIT_MODE, TXD_EN and RXD_EN bits must be set to logic 1. The sequence of setting these register bits is ignored. After the register configuration is complete: 1. A weak pull-up resistor will be enabled on the DP and DATA0 pins. This is to avoid the possible floating condition on these input pins when UART mode is enabled. 2. The 39  serial termination resistors on the DP and DM pins will be enabled. 3. One clock cycle after DIR goes from LOW to HIGH, the SAF1508BET will drive the data bus for five clock cycles. This is to charge the DATA0 pin to a HIGH level for a slow link. The link, however, can start driving DATA0 to HIGH immediately after the turnaround cycle. 4. UART buffers between DATA0 or DATA1 and DM or DP are enabled. Transparent UART mode is entered. Remark: The DP pin will be slowly charged up to HIGH by the weak pull-up resistor. The time needed depends on the capacitive loading on DP . By default, the clock is powered down when the SAF1508BET enters UART mode. If the link requires CLOCK to be running in UART mode, it can set the CLOCK_SUSPENDM bit in the Interface Control register to logic 1 before entering UART mode. Transparent UART mode is exited by asserting the STP pin to HIGH or by toggling the CHIP_SEL pin. The INT pin is asserted and latched whenever an unmasked interrupt event occurs. When the link detects INT as HIGH, it must wake-up the PHY from transparent UART mode by asserting STP . When the PHY is in synchronous mode, the link can read the USB Interrupt Latch register to determine the source of the interrupt. Note that the SAF1508BET does not implement the optional carkit interrupt registers. An alternative way to exit UART mode is to set the CHIP_SEL pin to non-active for more than tPWRDN and then set it to active. A power-on reset will be generated and the ULPI bus will be put in default synchronous mode.

Product data sheet Rev. 2 — 23 July 2012 26 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver (1) Clock remains powered when the CLOCK_SUSPENDM register bit is logic 1. (2) Clock is powered down when the CLOCK_ SUSPENDM register bit is logic 0 (default). Fig 8. Interface behavior when entering UART mode (1) Clock remains powered when the CLOCK_SUSPENDM register bit is logic 1. (2) Clock is powered down when the CLOCK_ SUSPENDM register bit is logic 0 (default). Fig 9. Interface behavior when exiting UART mode 004aaa865 CLOCK(2) DATA[7:0] TXCMD (REGW) DATA 0001 0001 DIR STP NXT UART mode turnaround UART mode signals CLOCK(1) 004aaa867 DIR STP NXT UART mode CLOCK(2) DATA[7:0] UART mode signals synchronous mode signals turnaround 0000 0000 CLOCK(1)

9.3 USB state transitions

DP_PULLDOWN and DM_PULLDOWN bits.

• RPU_DP_EN enables the 1.5 k pull-up resistor on DP
• RPD_DP_EN enables the 15 k pull-down resistor on DP
• RPD_DM_EN enables the 15 k pull-down resistor on DM
• HSTERM_EN enables the 45  termination resistors on DP and DM It is up to the link to set the desired register settings.

Table 14. Operating states and thei r corresponding resistor settings

10.1 ULPI references

10.2 TXCMD and RXCMD

10.2.1 TXCMD

those in Table 15 are illegal and will result in undefined behavior. Various TXCMD packet and register sequences are given in later sections.

10.2.2 RXCMD

Low Pin Interface (ULPI) Specification Rev. 1.1 and is given in Table 16. Table 15. TXCMD byte format link must drive NOOP by default. transmitting only after accepting the next data byte. XX XXXXb REGW Register write comma nd with 6-bit immediate address. XX XXXXb REGR Register read command with 6-bit immediate address.

diagrams, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.

10.2.2.1 Linestate encoding

depending on whether it is in peripheral or host mode. Table 16. RXCMD byte format 1t o0 L I N E S T A T E LINESTATE signals: For a definition of LINESTATE, see Section 10.2.2.1. 3t o2 V BUS state Encoded VBUS voltage state: For an explanation of the VBUS state, see Section 10.2.2.2. 5t o4 R x E v e n t Encoded USB event signals: For an explanation of RxEvent, see Section 10.2.2.4. 6 ID Reflects the value of the ID pin. Valid 50 ms after ID_PULLUP is set to logic 1. changes in BVALID will cause an RXCMD to be sent to the link with the ALT_INT bit asserted.

[1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output. [1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output.

10.2.2.2 V BUS state encoding

more VBUS voltage indicators, as shown in Figure 11. Table 17. LINESTATE[1:0] encoding for upstream facing ports: peripheral

11 SE1 invalid invalid

Table 18. LINESTATE[1:0] encoding fo r downstream facing ports: host

11 SE1 SE1 invalid invalid

Table 19. Encoded V BUS voltage state

00 V BUS <V B_SESS_END 100

01 V B_SESS_END  VBUS < VA_SESS_VLD 000

10 V A_SESS_VLD  VBUS < VA_VBUS_VLD X10

11 V BUS  VA_VBUS_VLD XX1

10.2.2.3 Using and selecting the V BUS state encoding

USB Interrupt Enable Falling registers. shows the recommended usage for typical applications.

1. Set the IND_COMPL bit in the Interface Control register to logic 0 or logic 1,

depending on the polarity of the external fault signal.

1. Set the USE_EXT_VBUS_IND bit in the OTG Control register to logic 1.
2. If it is not necessary to qualify the f ault indicator with the internal A_VBUS_VLD

comparator, set the IND_PASSTHRU bit in the Interface Control register to logic 1. thresholds is not needed for standard peripherals. Table 20. V BUS indicators in RXCMD required for typical applications

A-device is initiating VBUS pulsing SRP.

10.2.2.4 RxEvent encoding

methods. The first method is for the SAF1508BET to simultaneously assert DIR and NXT. methods. RxActive frames the receive packet from the first byte to the last byte. DIR is deasserted, whichever occurs first. packet is no longer valid and must be dropped by the link. HostDisconnect: HostDisconnect is encoded into the RxEvent field of the RXCMD. link with the updated value. Table 21. Encoded USB event signals

10 X X 1

Product data sheet Rev. 2 — 23 July 2012 34 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver

10.3 Register read and write operations

Figure 12 shows register read and write sequences. The SAF1508BET supports immediate addressing and extended addressing register operations. Extended register addressing is optional for links. Note that register operations will be aborted if the SAF1508BET asserts DIR during the operation. When a register operation is aborted, the link must retry until successful. For more information on register operations, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.

10.4 USB reset and high-speed detection handshake (chirp)

Figure 13 shows the sequence of events for USB reset and high-speed detection handshake (chirp). The sequence is shown for hosts and peripherals. Figure 13 does not show all RXCMD updates, and timing is not to scale. The sequence is as follows: 1. USB reset: The host detects a peripheral attachment as low-speed if DM is HIGH and as full-speed if DP is HIGH. If a host detects a low-speed peripheral, it does not follow the remainder of this protocol. If a host detects a full-speed peripheral, it resets the peripheral by writing to the Function Control register and setting XCVRSELECT[1:0] = 00b (high-speed) and TERMSELECT = 0b that drives SE0 on the bus (DP and DM connected to ground through 45 ). The host also sets OPMODE[1:0] = 10b for correct chirp transmit and receive. The start of SE0 is labeled T0. Remark: To receive chirp signaling, the host must also consider the high-speed differential receiver output. The host controller must interpret LINESTATE as shown in Table 18. 2. High-speed detection handshake (chirp) a. Peripheral chirp: After detecting SE0 for no less than 2.5 s, if the peripheral is capable of high-speed, it sets XCVRSELECT[1:0] to 00b (high-speed) and OPMODE[1:0] to 10b (chirp). The peripheral immediately follows this with a TXCMD (NOPID), transmitting a Chirp K for no less than 1 ms and ending no more AD indicates the address byte, and D indicates the data byte. Fig 12. Example of register write, register read, extended register write and extended register read CLOCK DIR DATA[7:0] NXT 004aaa710 D TXCMD (EXTW) AD D immediate register write TXCMD (REGW) TXCMD (REGR) D AD TXCMD (EXTW) D STP extended register write immediate register read extended register read

Product data sheet Rev. 2 — 23 July 2012 35 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver than 7 ms after reset time T0. If the peripheral is in low-power mode, it must wake up its clock within 5.6 ms, leaving 200 s for the link to start transmitting the Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 % slow clock). b. Host chirp: If the host does not detect the peripheral chirp, it must continue asserting SE0 until the end of reset. If the host detects the peripheral Chirp K for no less than 2.5 s, then no more than 100 s after the bus leaves the Chirp K state, the host sends a TXCMD (NOPID) with an alternating sequence of Chirp Ks and Js. Each Chirp K or Chirp J must last no less than 40 s and no longer than 60 s. c. High-speed idle: The peripheral must detect a minimum of Chirp K-J-K-J-K-J. Each Chirp K and Chirp J must be detected for at least 2.5 s. After seeing that minimum sequence, the peripheral sets TERMSELECT = 0b and OPMODE[1:0] = 00b. The peripheral is now in high-speed mode and sees !squelch (01b on LINESTATE). When the peripheral sees squelch (10b on LINESTATE), it knows that the host has completed chirp and waits for Hi-Speed USB traffic to begin. After transmitting the chirp sequence, the host changes OPMODE[1:0] to 00b and begins sending USB packets. For more information, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.

Product data sheet Rev. 2 — 23 July 2012 36 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver Timing is not to scale. Fig 13. USB reset and high-speed detection handshake (chirp) sequence 004aaa711 K DATA [7:0] K J TXCMD NOPID J ... TXCMD (REGW) TXCMD (REGW) SE0 K DIR STP NXT XCVR SELECT TERM SELECT 01 (FS) 00 (HS) OP MODE 00 (normal) 01 (chirp) 00 (normal) LINE STATE J (01b) SE0 (00b) peripheral chirp K (10b) squelch (00b)host chirp K (10b) or chirp J (01b) squelch (00b) ULPI host K DATA [7:0] K TXCMD NOPID K ...SE0 TXCMD (REGW) 00 K J K J K J TXCMD (REGW) 00 DIR STP NXT XCVR SELECT 01 (FS) 00 (HS) TERM SELECT OP MODE 00 (normal) 10 (chirp) 00 (normal) LINE STATE J (01b) SE0 (00b) peripheral chirp K (10b) !squelch (01b)host chirp K or J (10b or 01b) squelch (00b) squelch (00b) DP DM ULPI peripheralUSB signals USB reset high-speed detection handshake (chirp) peripheral chirp host chirp HS idleT0 RXCMDs

10.5 USB packet transmit and receive

packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.

10.5.1 USB packet timing

10.5.1.1 SAF1508BET pipeline delays

10.5.1.2 Allowed link decision time

Table 22. PHY pipeline delays

Table 23. Link decision times TXCMD for the second packet. TXCMD for the transmit packet. delays of 2 bit times to 6.5 bit times. subsequent transmission can occur after this time.

Product data sheet Rev. 2 — 23 July 2012 39 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver

10.6 Preamble

Preamble packets are headers to low-speed packets that must travel over a full-speed bus, between a host and a hub. To enter preamble mode, the link sets XCVRSELECT[1:0] = 11b in the Function Control register. When in preamble mode, the SAF1508BET operates just as in full-speed mode, and sends all data with the full-speed rise time and fall time. Whenever the link transmits a USB packet in preamble mode, the SAF1508BET will automatically send a preamble header at full-speed bit rate before sending the link packet at low-speed bit rate. The SAF1508BET will ensure a minimum gap of four full-speed bit times between the last bit of the full-speed PRE PID and the first bit of the low-speed packet SYNC. The SAF1508BET will drive a J for at least one full-speed bit time after sending the PRE PID, after which the pull-up resistor can hold the J state on the bus. An example transmit packet is shown in Figure 17 In preamble mode, the SAF1508BET can also receive low-speed packets from the full-speed bus. Fig 16. High-speed receive-to-transmit packet timing 004aaa713 DP or DM DATA EOP IDLE SYNC CLOCK DN−4 DN−3 DATA [7:0] D0TXCMD D1 DIR STP NXT RX end delay (three to eight clocks) link decision time (1 to 14 clocks) TX start delay (one to two clocks) USB interpacket delay (8 to 192 high-speed bit times) DN−2 DN−1 DN turnaround

Product data sheet Rev. 2 — 23 July 2012 40 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver

10.7 USB suspend and resume

10.7.1 Full-speed or low-speed host-initiated suspend and resume

Figure 18 illustrates how a host or a hub places a full-speed or low-speed peripheral into suspend and sometime later initiates resume signaling to wake-up the downstream peripheral. Note that Figure 18 timing is not to scale, and does not show all RXCMD LINESTATE updates. The sequence of events for a host and a peripheral, both with SAF1508BET, is as follows: 1. Idle: Initially, the host and the peripheral are idle. The host has its 15 k  pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b) and 45  terminations disabled (TERMSELECT is set to 1b). The peripheral has the 1.5 k pull-up resistor connected to DP for full-speed or DM for low-speed (TERMSELECT is set to 1b). 2. Suspend: When the peripheral sees no bus activity for 3 ms, it enters the suspend state. The peripheral link places the PHY into low-power mode by clearing the SUSPENDM bit in the Function Control register, causing the PHY to draw only suspend current. The host may or may not be powered down. 3. Resume K: When the host wants to wake up the peripheral, it sets OPMODE[1:0] to 10b and transmits a K for at least 20 ms. The peripheral link sees the resume K on LINESTATE, and asserts STP to wake up the PHY . 4. EOP: When STP is assert ed, the SAF1508BET on the host side automatically appends an EOP of two bits of SE0 at low-speed bit rate followed by one bit of J. The SAF1508BET on the host side knows to add the EOP because DP_PULLDOWN and DM_PULLDOWN are set to 1b for a host. After the EOP is completed, the host link sets OPMODE[1:0] to 00b for normal operation. The peripheral link sees the EOP and also resumes normal operation. DP and DM timing is not to scale. Fig 17. Preamble sequence CLOCK D0TXCMD (low-speed packet ID) D1DATA[7:0] DIR STP NXT 004aaa714 DP or DM FS SYNC FS PRE ID IDLE (min

4 FS bits) LS SYNC LS PID LS D0 LS D1

Product data sheet Rev. 2 — 23 July 2012 41 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver Timing is not to scale. Fig 18. Full-speed suspend and resume DATA [7:0] K TXCMD NOPID K ... TXCMD (REGW) DIR STP NXT OPMODE 00b 10b 00b K TXCMD LINE STATE J K SE0 J CLOCK DATA [7:0] TXCMD (REGW) LINESTATE J LINESTATE K SE0 J DIR STP NXT OPMODE 00b 10b 00b SUSPEND M LINE STATE J K SE0 J DP DM 004aaa715 FS or LS host (XCVRSELECT = 01b (FS) or 10b (LS), DP_PULLDOWN = 1b, DM_PULLDOWN = 1b, TERMSELECT = 1b) FS or LS peripheral (XCVRSELECT = 01b (FS) or 10b (LS), DP_PULLDOWN = 0b, TERMSELECT = 1b) USB signals (only FS is shown) idle suspend resume K EOP idle

Product data sheet Rev. 2 — 23 July 2012 42 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver

10.7.2 High-speed suspend and resume

Figure 19 illustrates how a host or a hub places a high-speed enabled peripheral into suspend and then initiates resume signaling. The high-speed peripheral will wake up and return to high-speed operations. Note that Figure 19 timing is not to scale, and does not show all RXCMD LINESTATE updates. The sequence of events related to a host and a peripheral, both with SAF1508BET, is as follows. 1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 k  pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b) and 45  terminations enabled (TERMSELECT is set to 0b). The peripheral has its 45  terminations enabled (TERMSELECT is set to 0b). 2. Full-speed suspend: When the peripheral sees no bus activity for 3 ms, it enters the suspend state. The peripheral link places the SAF1508BET into full-speed mode (XCVRSELECT is set to 01b), removes 45  terminations, and enables the 1.5 k pull-up resistor on DP (TERMSELECT is set to 1b). The peripheral link then places the SAF1508BET into low-power mode by setting SUSPENDM, causing the SAF1508BET to draw only suspend current. The host also changes the SAF1508BET to full-speed (XCVRSELECT is set to 01b), removes 45  terminations (TERMSELECT is set to 1b), and then may or may not be powered down. 3. Resume K: When the host wants to wake up the peripheral, it sets OPMODE to 10b and transmits a full-speed K for at least 20 ms. The peripheral link sees the resume K (10b) on LINESTATE, and asserts STP to wake up the SAF1508BET. 4. High-speed traffic: The host link sets high-speed (XCVRSELECT is set to 00b), and enables its 45  terminations (TERMSELECT is set to 0b). The peripheral link sees SE0 on LINESTATE and also sets high-speed (XCVRSELECT is set to 00b), and enables its 45  terminations (TERMSELECT is set to 0b). The host link sets OPMODE to 00b for normal high-speed operation.

Product data sheet Rev. 2 — 23 July 2012 43 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver Timing is not to scale. Fig 19. High-speed suspend and resume DATA [7:0] K TXCMD NOPID K ... TXCMD (REGW) DIR STP NXT OP MODE 00b 10b 00b K TXCMD (REGW) CLOCK DATA [7:0] TXCMD (REGW) LINESTATE J LINESTATE K SE0 TXCMD (REGW) DIR STP NXT OP MODE 00b 10b 00b SUSPEND M LINE STATE DP DM 004aaa717 ULPI HS host (DP_PULLDOWN = 1b, DM_PULLDOWN = 1b)ULPI HS peripheral (DP_PULLDOWN = 0b)USB signals HS idle FS suspend resume K TXCMD (REGW) HS idle XCVR SELECT 00b 01b 00b TERM SELECT LINE STATE !SQUELCH (01b) FS J (01b) !SQUELCH (01b)SQUELCH (00b)FS K (10b) XCVR SELECT 00b 01b 00b TERM SELECT !SQUELCH (01b) SQUELCH (00b) FS J (01b) !SQUELCH (01b)SQUELCH (00b)FS K (10b) SQUELCH (00b)

Product data sheet Rev. 2 — 23 July 2012 44 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver

10.7.3 Remote wake-up

The SAF1508BET supports peripherals that initiate remote wake-up resume. When placed into USB suspend, the peripheral link remembers at what speed it was originally operating. Depending on the original speed, the link follows one of the protocols detailed here. In Figure 20 , timing is not to scale, and not all RXCMD LINESTATE updates are shown. The sequence of events related to a host and a peripheral, both with SAF1508BET, is as follows: 1. Both the host and the peripheral are assumed to be in low-power mode. 2. The peripheral begins remote wake-up by re-enabling its clock and setting its SUSPENDM bit to 1b. 3. The peripheral begins driving K on the bus to signal resume. Note that the peripheral link must assume that LINESTATE is K (01b) while transmitting because it will not receive any RXCMDs. 4. The host recognizes the resume, re-enables its clock and sets its SUSPENDM bit. 5. The host takes over resume driving within 1 ms of detecting the remote wake-up. 6. The peripheral stops driving resume. 7. The peripheral sees the host continuing to drive the resume. 8. The host stops driving resume and the SAF1508BET automatically adds the EOP to the end of the resume. The peripheral recognizes the EOP as the end of resume. 9. Both the host and the peripheral revert to normal operation by writing 00b to OPMODE. If the host or the peripheral was previously in high-speed mode, it must revert to high-speed before the SE0 of the EOP is completed. This can be achieved by writing XCVRSELECT[1:0] = 00b and TERMSELECT = 0b after LINESTATE indicates SE0.

Product data sheet Rev. 2 — 23 July 2012 45 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver

10.8 No automatic SYNC and EOP generation (optional)

This setting allows the link to turn off the automatic SYNC and EOP generation, and must be used for high-speed packets only. It is provided for backward compatibility with legacy controllers that include SYNC and EOP bytes in the data payload when transmitting packets. The SAF1508BET will not automatically generate SYNC and EOP patterns when OPMODE[1:0] is set to 11b. The SAF1508BET will still NRZI encode data and perform bit stuffing. An example of a sequence is shown in Figure 21 . The link must always send packets using the TXCMD (NOPID) type. The SAF1508BET does not provide a mechanism to control bit stuffing in individual bytes, but will automatically turn off bit stuffing for EOP when STP is asserted with data set to FEh. If data is set to 00h when STP Timing is not to scale. Fig 20. Remote wake-up from low-power mode DATA [7:0] LINESTATE TXCMD REGW TXCMD REGW00h TXCMD NOPID DIR STP NXT XCVR SELECT 01b (FS), 10b (LS) 00b (HS only) TERM SELECT OP MODE 10b 00b DATA [7:0] LINESTATE TXCMD REGW RXCMD00h TXCMD NOPID RXCMD RXCMD TXCMD REGW DIR STP NXT XCVR SELECT 00b (HS), 01b (FS), 10b (LS) 00b (HS only) TERM SELECT OP MODE 10b 00b ULPI hostULPI peripheral 004aaa718 0b (HS only) 0b (HS only)

Product data sheet Rev. 2 — 23 July 2012 46 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver is asserted, the PHY will not transmit any EOP. The SAF1508BET will also detect if the PID byte is A5h, indicating an SOF packet, and automatically send a long EOP when STP is asserted. To transmit chirp and resume signaling, the link must set OPMODE to 10b.

10.9 On-The-Go operations

On-The-Go (OTG) is a supplement to Universal Serial Bus Specification Rev. 2.0 that allows a portable USB device to assume the role of a limited USB host by defining improvements, such as a small connector and low power. Non-portable devices, such as standard hosts and embedded hosts, can also benefit from OTG features. The SAF1508BET OTG PHY is designed to support all the tasks specified in the OTG supplement. The SAF1508BET provides the front end analog support for Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for dual-role devices. The supporting components include:

• Voltage comparators – A_VBUS_VLD – SESS_VLD (session valid, can be used for both A-session and B-session valid) – SESS_END (session end)
• Pull-up and pull-down resistors on DP and DM
• ID detector indicates if micro-A or micro-B plug is inserted
• Charge and discharge resistors on VBUS The following subsections describe how to use the SAF1508BET OTG components. Fig 21. Transmitting USB packets without automatic SYNC and EOP generation CLOCK DATA DN − 1 FEhDN DIR STP NXT ULPI signals TX VALID TX READY TXBIT STUFF ENABLE DP, DM IDLE SYNC PID IDLEEOPDATA PAYLOAD 004aaa719 UTMI+ equivalent signalsUSB bus

Product data sheet Rev. 2 — 23 July 2012 47 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver

10.9.1 OTG comparators

The SAF1508BET provides comparators that conform to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 requirements of VA_VBUS_VLD, VA_SESS_VLD, VB_SESS_VLD and VB_SESS_END. In this data sheet, VA_SESS_VLD and VB_SESS_VLD are combined into VA_SESS_VLD. Comparators are described in Section 8.7.2. Changes in comparator values are communicated to the link by RXCMDs as described in Section 10.2.2.2. Control over comparators is described in Section 11.5 to Section 11.8.

10.9.2 Pull-up and pull-down resistors

The USB resistors on DP and DM can be used to initiate data-line pulsing SRP. The link must set the required bus state using the mode settings in Table 14.

10.9.3 ID detection

The SAF1508BET provides an internal pull-up resistor to sense the value of the ID pin. The pull-up resistor must first be enabled by setting the ID_PULLUP register bit to logic 1. If the value on ID has changed, the SAF1508BET will send an RXCMD or interrupt to the link by time tID. If the link does not receive any RXCMD or interrupt by tID, then the ID value has not changed.

10.9.4 V BUS charge and discharge resistors

A pull-up resistor, RUP(VBUS), is provided to perform VBUS pulsing SRP. A B-device is allowed to charge VBUS above the session valid threshold to request the host to turn on the VBUS power. A pull-down resistor, RDN(VBUS), is provided for a B-device to discharge VBUS. This is done whenever the A-device turns off the VBUS power; the B-device can use the pull-down resistor to ensure VBUS is below VB_SESS_END before starting a session. For details, refer to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3.

10.10 Serial modes

The SAF1508BET supports both 6-pin serial mode and 3-pin serial mode, controlled by bits 6PIN_FSLS_SERIAL and 3PIN_FSLS_SERIAL of the Interface Control register. For details, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.10. Figure 22 and Figure 23 provide example of 6-pin serial mode and 3-pin serial mode, respectively.

Product data sheet Rev. 2 — 23 July 2012 48 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver Fig 22. Example of transmit follow ed by receive in 6-pin serial mode DATA0 (TX_ENABLE) DATA1 (TX_DAT) DATA2 (TX_SE0) DATA4 (RX_DP) DATA5 (RX_DM) DATA6 (RX_RCV) DP DM SYNC DATA EOP TRANSMIT RECEIVE SYNC DATA EOP 004aaa692 Fig 23. Example of transmit follow ed by receive in 3-pin serial mode DATA0 (TX_ENABLE) DATA1 (TX_DAT/ RX_RCV) DP DATA2 (TX_SE0/ RX_SE0) DM 004aaa693 SYNC DATA EOP TRANSMIT RECEIVE SYNC DATA EOP

Product data sheet Rev. 2 — 23 July 2012 49 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver

10.11 Aborting transfers

The SAF1508BET supports aborting transfers on the ULPI bus. For details, refer to

10.12 Avoiding contention on the ULPI data bus

Because the ULPI data bus is bidirectional, avoid situations in which both the link and the PHY simultaneously drive the data bus. The following points must be considered while implementing the data bus drive control on the link. After power-up and clock stabilization, default states are as follows:

• The SAF1508BET drives DIR to LOW.
• The data bus is input to the SAF1508BET.
• The ULPI link data bus is output, with all data bus lines driven to LOW. When the SAF1508BET wants to take control of the data bus to initiate a data transfer, it changes the DIR value from LOW to HIGH. At this point, the link must disable its output buffers. This must be as fast as possible so the link must use a combinational path from DIR. The SAF1508BET will not immediately enable its output buffers, but will delay the enabling of its buffers until the next clock edge, avoiding bus contention. When the data transfer is no longer required by the SAF1508BET, it changes DIR from HIGH to LOW and starts to immediately turn off its output drivers. The link senses the change of DIR from HIGH to LOW, but delays enabling its output buffers for one CLOCK cycle, avoiding data bus contention.

[1] Read (R): A register can be read. Read-only if this is the only mode given. [2] Write (W): The pattern on the data bus will be written over all bits of a register. [3] Set (S): The pattern on the data bus is OR-ed with and written to a register.

11.1 Vendor ID and Product ID registers

11.1.1 Vendor ID Low register

Table 25 shows the bit description of the register.

11.1.2 Vendor ID High register

Table 26 shows the bit description of the register. Table 24. Register map Table 25. Vendor ID Low register (address R = 00h) bit description Table 26. Vendor ID High register (address R = 01h) bit description

11.1.3 Product ID Low register

The bit description of the Product ID Low register is given in Table 27.

11.1.4 Product ID High register

The bit description of the register is given in Table 28.

11.2 Function Control register

Table 27. Product ID Low register (address R = 02h) bit description Table 28. Product ID High register (address R = 03h) bit description Table 29. Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit allocation Table 30. Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit description 6 SUSPENDM Suspend LOW: Active LOW PHY suspend. full-speed receiver, OTG comparators and ULPI interface pins. this bit when it exits low-power mode. 5 RESET Reset: Active HIGH transceiver reset. reset the ULPI interface or the ULPI register set. followed by an RXCMD update to the link.

11.3 Interface Control register

results in undefined behavior. Table 31 provides the bit allocation of the register. 4 to 3 OPMODE[1:0] Operation Mode: Selects the required bit-encoding style during transmit. Transceiver Select: Selects the required transceiver speed. Table 30. Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit description …continued Table 31. Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit allocation

Table 32. Interface Control register (address R = 07 h to 09h, W = 07h, S = 08h, C = 09h) bit description SAF1508BET will automatically detect when the link stops driving STP. resistors on DATA[7:0], protecting data inputs. DATA[7:0], and a weak pull-up resistor on STP.

6 IND_PASSTHRU Indicator Pass-through: Controls whether the complement output is qualified with the

internal A_VBUS_VLD comparator before being used in the VBUS state in RXCMD. 0b — The SAF1508BET will not invert the FAULT signal. 1b — The SAF1508BET will invert the FAULT signal. 3 CLOCK_SUSPENDM Clock Suspend LOW: Active LOW clock suspend. 6-pin serial mode or 3-pin serial mode. logic 1, otherwise this bit is ignored. 0b — Clock will not be powered in 3-pin or 6-pin serial mode, or UART mode. 1b — Clock will be powered in 3-pin and 6-pin serial mode, or UART mode. automatically clear this bit when carkit mode is exited. 0b — Full-speed or low-speed packets are sent using the parallel interface. 1b — Full-speed or low-speed packets are sent using the 3-pin serial interface. 0b — Full-speed or low-speed packets are sent using the parallel interface. 1b — Full-speed or low-speed packets are sent using the 6-pin serial interface.

11.4 OTG Control register

OTG Control register is given in Table 33. Table 33. OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit allocation Table 34. OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit description

7 USE_EXT_

Use External VBUS Indicator: Informs the PHY to use an external VBUS overcurrent indicator. 0b — Use the internal OTG comparator. 1b — Use the external VBUS valid indicator signal input from the FAULT pin. 6 DRV_VBUS_EXT Drive VBUS External: Controls the external charge pump or 5 V supply by the PSW_N pin. DM data lines have been LOW (SE0) for 2 ms. 2 DM_PULLDOWN DM Pull Down: Enables the 15 k pull-down resistor on DM. 0b — Pull-down resistor is not connected to DM. 1b — Pull-down resistor is connected to DM. 1 DP_PULLDOWN DP Pull Down: Enables the 15 k pull-down resistor on DP. 0b — Pull-down resistor is not connected to DP. 1b — Pull-down resistor is connected to DP. the ID line sampler will reduce the PHY power consumption. 0b — Disable sampling of the ID line. 1b — Enable sampling of the ID line.

11.5 USB Interrupt Enable Rising register

transitions are enabled. Table 35 shows the bit allocation of the register.

11.6 USB Interrupt Enab le Falling register

transitions are enabled. See Table 37. Table 35. USB Interrupt Enable Rising register (add ress R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit allocation Table 36. USB Interrupt Enable Rising register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit description 4 ID_GND_R ID Ground Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on ID_GND.

3 SESS_END_R Session End Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on

2 SESS_VALID_R Session Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on

1 VBUS_VALID_R VBUS Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on

Table 37. USB Interrupt Enable Falling register (add ress R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit allocation Table 38. USB Interrupt Enable Falling register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit description

4 ID_GND_F ID Ground Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on

3 SESS_END_F Session End Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on

11.7 USB Interrupt Status register

This register (see Table 39) indicates the current value of the interrupt source signal.

11.8 USB Interrupt Latch register

all signal information will automatically be sent to the link through the RXCMD byte. The bit allocation of this register is given in Table 41.

2 SESS_VALID_F Session Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on

1 VBUS_VALID_F VBUS Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on

Table 39. USB Interrupt Status register (address R = 13h) bit allocation Table 40. USB Interrupt Status register (address R = 13h) bit description 4I D _ G N D ID Ground: Reflects the current value of the ID detector circuit. 3 SESS_END Session End: Reflects the current value of the session end voltage comparator. 2 SESS_VALID Session Valid: Reflects the current value of the session valid voltage comparator. 1 VBUS_VALID VBUS Valid: Reflects the current value of the VBUS valid voltage comparator. 0 HOST_DISCON Host Disconnect: Reflects the current value of the host disconnect detector. Table 41. USB Interrupt Latch register (address R = 14h) bit allocation

11.9 Debug register

current value of signals useful for debugging.

11.10 Scratch register

This is a 1-byte empty register for testing purposes, see Table 45.

11.11 Carkit Control register

Table 42. USB Interrupt Latch register (address R = 14h) bit description 4 ID_GND_L ID Ground Latch: Automatically set when an unmasked event occurs on ID_GND. Cleared when this register is read. 3 SESS_END_L Session End Latch: Automatically set when an unmasked event occurs on SESS_END. Cleared when this register is read. 2 SESS_VALID_L Session Valid Latch: Automatically set when an unmasked event occurs on SESS_VLD. Cleared when this register is read. 1 VBUS_VALID_L VBUS Valid Latch: Automatically set when an unmasked event occurs on A_VBUS_VLD. Cleared when this register is read.

0 HOST_DISCON_L Host Disconnect Latch: Automatically set when an unmasked event occurs on

HOST_DISCON. Cleared when this register is read. Table 43. Debug register (address R = 15h) bit allocation Table 44. Debug register (address R = 15h) bit description 1L I N E S T A T E 1 Line State 1: Contains the current value of LINESTATE 1. 0L INESTATE0 Line State 0: Contains the current value of LINESTATE 0. Table 45. Scratch register (address R = 16h t o 18h, W = 16h, S = 17h, C = 18h) bit description

11.12 Power Control register

allocation of the register is given in Table 48. Table 46. Carkit Control register (address R = 19h to 1Bh, W = 19h, S = 1Ah, C = 1Bh) bit allocation Table 47. Carkit Control register (address R = 19h to 1Bh, W = 19h, S = 1Ah, C = 1Bh) bit description automatically be cleared when UART mode is exited. automatically be cleared when UART mode is exited. Table 48. Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation Table 49. Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit description

4 DP_WKPU_EN DP Weak Pull-Up Enable: Enable the weak pull-up resistor on the DP pin (R

0 — DP weak pull-up is disabled. 1 — DP weak pull-up is enabled when VBUS > VA_SESS_VLD. purposes. Disabled by default. purposes. Disabled by default.

be fully operational after the test completed. 5 seconds. Actual performance may vary depending on the resistor used and whether other components are connected to VBUS. customers perform their own ESD tests, depending on application requirements.

1. Recommended operating conditions

Table 50. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Table 51. Recommended operating conditions

Table 52. Static characte ristics: supply pins Typical case refers to VCC = 3.6 V; VCC(I/O) =1 . 8V ; Tamb = +25 C; unless otherwise specified. Table 53. Static characte ristics: digital pins Digital pins: CLOCK, DIR, STP, NXT, DATA[7:0], CHIP_SEL, CFG2, CFG1 and TEST_N. Typical case refers to VCC = 3.6 V; VCC(I/O) =1 . 8V ; Tamb = +25 C; unless otherwise specified.

[1] When V OH is less than REG3V3, ICC may increase because of the cross current. Table 53. Static characte ristics: digital pins …continued Digital pins: CLOCK, DIR, STP, NXT, DATA[7:0], CHIP_SEL, CFG2, CFG1 and TEST_N. Typical case refers to VCC = 3.6 V; VCC(I/O) =1 . 8V ; Tamb = +25 C; unless otherwise specified. Table 54. Static characteri stics: digital pin FAULT Table 55. Static characteri stics: digital pin PSW_N

Table 56. Static characteristi cs: analog pins (DP and DM) Typical case refers to VCC = 3.6 V; VCC(I/O) =1 . 8V ; Tamb = +25 C; unless otherwise specified.

Table 56. Static characteristi cs: analog pins (DP and DM) …continued Typical case refers to VCC = 3.6 V; VCC(I/O) =1 . 8V ; Tamb = +25 C; unless otherwise specified. Table 57. Static characte ristics: analog pin VBUS Typical case refers to VCC = 3.6 V; VCC(I/O) =1 . 8V ; Tamb = +25 C; unless otherwise specified.

Table 57. Static characte ristics: analog pin VBUS …continued Typical case refers to VCC = 3.6 V; VCC(I/O) =1 . 8V ; Tamb = +25 C; unless otherwise specified. Table 58. Static characterist ics: ID detection circuit Typical case refers to VCC = 3.6 V; VCC(I/O) =1 . 8V ; Tamb = +25 C; unless otherwise specified. Table 59. Static characterist ics: resistor reference Typical case refers to VCC = 3.6 V; VCC(I/O) =1 . 8V ; Tamb = +25 C; unless otherwise specified. Table 60. Static characteristics: regulator Typical case refers to VCC = 3.6 V; VCC(I/O) =1 . 8V ; Tamb = +25 C; unless otherwise specified.

1.8 V regulator

3.3 V regulator

Table 61. Static charac teristics: pin XTAL1

[1] The internal PLL is triggered only on the positive edge from the crystal oscillator. Therefore, the duty cycle is not critical. Table 62. Dynamic characteristics: reset and power Table 63. Dynamic characteristics: clock applied to XTAL1 Typical case refers to VCC = 3.6 V; VCC(I/O) = 1.8 V; Tamb = +25 C; unless otherwise specified. Table 64. Dynamic characteristics: CLOCK output Typical case refers to VCC = 3.6 V; VCC(I/O) = 1.8 V; Tamb = +25 C; unless otherwise specified.

[1] Load capacitance on each ULPI pin. [1] Note that the value exceeds that specified in UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. [2] Load capacitance on each ULPI pin. Table 65. Dynamic characteristics: digital I/O pins (SDR) Table 66. Dynamic characteristics: digital I/O pins (DDR) Table 67. Dynamic characteristics: anal og I/O pins (DP and DM) in USB mode

Table 67. Dynamic characteristics: anal og I/O pins (DP and DM) in USB mode …continued Table 68. Dynamic characteristi cs: analog I/O pins (DP and DM) in transparent UART mode

Table 69. Dynamic characteristics: analog I/O pins (DP and DM) in serial mode

Product data sheet Rev. 2 — 23 July 2012 69 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver Fig 24. Rise time and fall time Fig 25. Timing of TX_DAT and TX_SE0 to DP and DM Fig 26. Timing of TX_ENABLE to DP and DM Fig 27. Timing of DP and DM to RX_RCV, RX_DP and RX_DM 004aaa861 VOL tHSR, tFR, tLR tHSF, tFF, tLF VOH 90 % 10 % 10 % 90 % 004aaa573VOL VOH tPHL(drv)tPLH(drv) VCRS VCRS 0.9 V0.9 V 1.8 V 0 V logic input differential data lines 004aaa574VOL VOH tPZH tPZL tPHZ tPLZ VOH − 0.3 V VOL + 0.3 V VCRS 0.9 V0.9 V 1.8 V 0 V logic input differential data lines tPLH(se) tPHL(se) 004aaa575 VOL VOH tPHL(rcv)tPLH(rcv) VCRS VCRS 0.9 V0.9 V 2.0 V 0.8 V logic output differential data lines Fig 28. ULPI timing interface CLOCK Control IN (STP) DATA IN (8-bit) tsu th tsu th Control OUT (DIR, NXT) DATA OUT (8-bit) 004aaa993 td(o) td(o) td(o)

Product data sheet Rev. 2 — 23 July 2012 70 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver 16. Application information [1] For more information, contact Murata. Table 70. Recommended bill of materials 0.1 F  20 % - Cfilter highly recommended for all 4.7 F  20 % use ESR = 300  type capacitor for best performance Rpullup recommended; for applications with an external V BUS supply controlled by PSW_N 10 k - DESD recommended to prevent damages from ESD IP4359CX4/LF; Wafer-Level Chip-Scale Package (WLCSP); ESD IEC 61000-4-2 level 4; 15 kV contact; 15 kV air discharge compliant protection xtal mandatory in all applications 13 MHz 50 ppm; C L =1 0p F ; RS < 300 ; CXTAL =1 8p F

19.2 MHz 50 ppm; C L =1 0p F ; RS < 220 ; CXTAL =1 8p F

24 MHz 50 ppm; C L =1 0p F ; RS < 160 ; CXTAL =1 8p F

26 MHz 50 ppm; C L =1 0p F ; RS < 130 ; CXTAL =1 8p F

• CSTCE26M0XK2***-R0 [1]; CXTAL is not required

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 2 — 23 July 2012 71 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver (1) Connect to either GND or V CC(I/O), depending on the clock frequency used. See Table 5. Fig 29. SAF1508BET in peripheral only application SAF1508 DATA0VCC(I/O) RREF DM DP FAULT ID V CC PSW_N DATA1 DATA2 CHIP_SEL DATA3 CLOCK DATA4 DATA5 DATA6 DATA7 NXT B2 B1 001aai308 VBUS REG3V3 XTAL2F6 STP DIR REG1V8 TEST_NC4 USB PERIPHERAL CONTROLLER USB STANDARD-B RECEPTACLE SHIELD VBUS GND 4 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 CLOCK NXT STP DIR VCC(I/O) CHIP_SEL GND IP4359CX4/LF A1 A2 Cbypass RRREF CVBUS Cbypass Cfilter Cbypass Cfilter RS(VBUS) CFG1(1)B4 CFG0 E1 CFG2(1)B3 B5 VCC(I/O) VCC Cbypass C5, D2, E4 n.c.F2 n.c.F1 XTAL1 F5 SHIELD 6 Cbypass DESD

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 2 — 23 July 2012 72 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver (1) Connect to either GND or V CC(I/O), depending on the crystal frequency used. See Table 5. Fig 30. SAF1508BET in OTG application SAF1508 RREF DM DP FAULT ID PSW_ND4 001aai309 VBUS REG3V3 XTAL2F6 REG1V8 E6 USB MICRO-AB RECEPTACLE 5 +5 V IN FAULT ON OUT VBUS SWITCH RS(VBUS) RRREF IP4359CX4/LF A1 A2 DESD CVBUS Cbypass Cfilter Cbypass Cfilter CFG1(1)B4 CFG2(1)B3 DATA0 DATA1 DATA2 CHIP_SEL DATA3 CLOCK DATA4 DATA5 DATA6 DATA7 NXT STP DIR DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 CLOCK NXT STP DIR CHIP_SEL CFG0 E1 OTG CONTROLLER VCC(I/O) VCC TEST_NC4 VCC(I/O) Cbypass B5 VCC(I/O) VCC Cbypass GND C5, D2, E4 n.c.F2 F1 n.c. Rpu XTAL1F5 SHIELD VBUS ID GND SHIELD SHIELD SHIELD CXTAL CXTAL xtal Cbypass

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 2 — 23 July 2012 73 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver (1) Connect to either GND or V CC(I/O), depending on the crystal frequency used. See Table 5. Fig 31. SAF1508BET in host application SAF1508 RREF DM DP FAULT ID PSW_ND4 001aai310VBUS REG3V3 XTAL1 XTAL2F6 USB STANDARD-A RECEPTACLE VBUS GND 4 +5 V IN FAULT ON OUT VBUS SWITCH IP4359CX4/LF DESD RRREF Rpu CVBUS Cbypass Cfilter CXTAL CXTAL xtal CFG1(1)B4 CFG2(1)B3 REG1V8 E6 Cbypass Cfilter DATA0 DATA1 DATA2 CHIP_SEL DATA3 CLOCK DATA4 DATA5 DATA6 DATA7 NXT STP DIR DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 CLOCK NXT STP DIR CHIP_SEL CFG0 USB HOST CONTROLLER VCC(I/O) VCC TEST_NC4 VCC(I/O) Cbypass B5 VCC(I/O) VCC Cbypass GND C5, D2, E4 n.c.F2 F1 n.c. B1 B2 SHIELD 5 SHIELD 6 Cbypass

Product data sheet Rev. 2 — 23 July 2012 74 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver 17. Package outline Fig 32. Package outline SOT912-1 (TFBGA36) REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT912-1 SOT912-1 05-08-09 05-09-01 UNIT A max mm 1.15 0.25 0.15 0.90 0.75 0.35 0.25 3.6 3.4 3.6 3.4 A DIMENSIONS (mm are the original dimensions) TFBGA36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm 0 2.5 5 mm scale A2 b D E e2 2.5 e 0.5 2.5 0.1 v 0.15 w 0.05 y 0.08 - - - - - -- - - b e e 1/2 e 1/2 e A CBv M Cw M ball A1 index area A B C D E F 246135 ball A1 index area B A E D C yCy1 X detail X A

Product data sheet Rev. 2 — 23 July 2012 75 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”.

18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.

18.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering

18.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave
• Solder bath specifications, including temperature and impurities

18.4 Reflow soldering

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 33) than a SnPb process, thus reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 71 and 72 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 33.

Table 71. SnPb eutectic process (from J-STD-020C) Table 72. Lead-free process (from J-STD-020C)

“Surface mount reflow soldering description”. Table 73. Abbreviations

A-device — An OTG device with an attached micro-A plug. B-device — An OTG device with an attached micro-B plug. Link — ASIC, SOC or FPGA that contains the USB host or peripheral core. PHY — Physical layer containing the USB transceiver. Chirp — A signal with increasing or decreasing frequency. MP3 — Shorthand notation the audio encoding format MPEG-1 audio layer 3. On-chip pad — On-chip contact, which many times includes some circuitry as well. RX — A common abbreviation from telegraphy for receive. Squelch — Complete suppression of an unwanted signal. Transceiver — A device which can both transmit and receive data. Table 73. Abbreviations …continued

Table 74. Revision history

Product data sheet Rev. 2 — 23 July 2012 81 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver 23. Legal information

23.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

23.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

23.3 Disclaimers

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Product data sheet Rev. 2 — 23 July 2012 82 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

23.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 24. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Table 4. Recommended V Table 5. Allowed crystal or clock frequency on the Table 6. External capacitor values for 13 MHz or Table 7. External capacitor values for 24 MHz or Table 14. Operating states and their corresponding Table 17. LINESTATE[1:0] encoding for upstream facing Table 18. LINESTATE[1:0] encoding for downstream Table 19. Encoded V Table 20. V BUS indicators in RXCMD required for Table 25. Vendor ID Low register (address R = 00h) Table 26. Vendor ID High register (address R = 01h) Table 27. Product ID Low register (address R = 02h) Table 28. Product ID High register (address R = 03h) Table 29. Function Control register (address Table 30. Function Control register (address Table 31. Interface Control register (address Table 32. Interface Control register (address R = 07h to 09h, Table 33. OTG Control register (address R = 0Ah to 0Ch, Table 34. OTG Control register (address R = 0Ah to 0Ch, Table 35. USB Interrupt Enable Rising register (address Table 36. USB Interrupt Enable Rising register (address Table 37. USB Interrupt Enable Falling register (address Table 38. USB Interrupt Enable Falling register (address Table 39. USB Interrupt Status register (address R = 13h) Table 40. USB Interrupt Status register (address R = 13h) Table 41. USB Interrupt Latch register (address R = 14h) Table 42. USB Interrupt Latch register (address R = 14h) Table 43. Debug register (address R = 15h) Table 44. Debug register (address R = 15h) Table 45. Scratch register (address R = 16h to 18h, Table 46. Carkit Control register (address R = 19h to 1Bh, Table 47. Carkit Control register (address R = 19h to 1Bh, Table 48. Power Control register (address R = 3Dh to 3Fh, Table 49. Power Control register (address R = 3Dh to 3Fh, Table 56. Static characteristics: analog pins

Table 63. Dynamic characteristics: Table 65. Dynamic characteristics: digital I/O pins Table 66. Dynamic characteristics: digital I/O pins Table 67. Dynamic characteristics: analog I/O pins Table 68. Dynamic characteristics: analog I/O pins Table 69. Dynamic characteristics: analog I/O pins Table 71. SnPb eutectic process (from J-STD-020C) . . .76

Product data sheet Rev. 2 — 23 July 2012 85 of 87 NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver 26. Figures Fig 3. V BUS pin internal pull-up and pull-down scheme .10 Fig 6. Power-up and reset sequence required before Fig 7. Interface behavior with respect to the CHIP_SEL Fig 8. Interface behavior when entering UART mode . .26 Fig 9. Interface behavior when exiting UART mode . . .26 Fig 10. Single and back-to-back RXCMDs from the Fig 12. Example of register wr ite, register read, extended Fig 13. USB reset and high-speed detection handshake Fig 14. Example of using the SAF1508BET to transmit and Fig 15. High-speed transmit-to-transmit packet timing . .38 Fig 16. High-speed receive-to-transmit packet timing . . .39 Fig 21. Transmitting USB packets without automatic Fig 22. Example of transmit followed by receive in 6-pin Fig 23. Example of transmit followed by receive in 3-pin Fig 25. Timing of TX_DAT and TX_SE0 to DP and DM. .69 Fig 27. Timing of DP and DM to RX_RCV, RX_DP Fig 33. Temperature profiles for large and small

Product data sheet Rev. 2 — 23 July 2012 86 of 87 continued >> NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver 27. Contents 7.2 V 7.8 V 8.7.2 V

8.11.2 Interface behavior with respect to the

10.2.2.2 V

10.2.2.3 Using and selecting the V BUS state encoding 32

10.4 USB reset and high-speed detection

10.7.1 Full-speed or low-speed host-initiated

10.8 No automatic SYNC and EOP generation

10.9.4 V 10.12 Avoiding contention on the ULPI data bus. . . 49

NXP Semiconductors SAF1508BET ULPI HS USB OTG transceiver © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 23 July 2012 Document identifier: SAF1508 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.