SAE81C90

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Data Sheet 01.97 Preliminary Microcomputer Components SAE 81C90/91 Standalone Full-CAN Controller

Semiconductor Group 1 01.97

• Full CAN controller for data rate up to 1 Mbaud
• Complies with CAN specification V2.0 part A (part B passive)
• Up to 16 messages simultaneous (each with maximum data length)
• Message identifier reprogrammable “on the fly”
• Several transmit jobs can be sent with a single command
• Transmit check
• Basic CAN feature
• Time stamp for eight messages
• Two host interfaces (parallel and serial)
• User-configurable outputs for different bus concepts
• Programmable clock output
• Two 8 bit I/O-Port extension (P-LCC-44-1 package only) Stand Alone Full CAN Controller SAE 81C90/91 The device comes in two versions: SAE 81C90 in a P-LCC-44-1 package with two 8-bit l/O ports, and SAE 81C91 in a P-LCC-28-1 package without l/O ports. Controller Area Network (CAN): License of Robert Bosch GmbH SAE 81C90/91 Revision History: Version 01.97 Previous Releases: 06.95 05.94 (Copy version) Page Subjects 1056 Figure 1 corrected. 1057 Figure 2 corrected. 1059 Notes updated. 1065 - 1084 Register description and arrangement improved. 1066, 1069 New register maps. 1093 t AVLL ,tLLAX ,tDVWH changed to 10 ns. 1093 tWHDX changed to 5 ns. P-LCC-44-1 P-LCC-28-1

07Feb95@09:05h Intermediate Version Semiconductor Group 2 SAE 81C90/91 Introduction The Siemens Stand Alone Full CAN (SFCAN) circuit incorporates all the parts for completely autonomous transmission and reception of messages using the CAN protocol. The flexible, programmable interface allows hookup to different implementations of the physical layer. The link to a host controller can be made either by a multiplexed 8-bit address/data bus or by a high-speed, serial synchronous interface. Figure 1 Logic Symbol

Ordering Information

Type Ordering Code Package Function SAE 81C91 Q67121-F0001 P-LCC-28-1 Stand Alone Full CAN Controller Temperature range – 40 to + 110 ˚C SAE 81C90 Q67121-H9038 P-LCC-44-1 Stand Alone Full CAN Controller Temperature range – 40 to + 110 ˚C

07Feb95@09:05h Intermediate Version Semiconductor Group 3 SAE 81C90/91 Pin Configurations (top view) Figure 2

07Feb95@09:05h Intermediate Version Semiconductor Group 4 SAE 81C90/91 Pin Definitions and Functions Symbol Pin Number Input (I) Output (O) Function PLCC-48 PLCC-28 X1 1) 11 28 O Crystal oscillator output. Must be unconnected for external clock input. X2 1) 10 27 I Crystal oscillator input. Used for external clock input. CLKOUT 1) 14 3 O Clock output RES 19 4 I Reset. (Schmitt trigger characteristic) AD0/DI 42 19 I/O PI: Address / Data bus / SI: Data input AD1/DO 43 20 I/O PI: Address / Data bus / SI: Data output AD2/CLK 44 21 I/O PI: Address / Data bus / SI: Clock input AD3/ W 1 22 I/O PI: Address / Data bus / SI: Write select AD4/TIM 2 23 I/O PI: Address / Data bus / SI: TIM = 0: Timing A; TIM = 1: Timing B AD5 3 24 I/O PI: Address/Data bus AD6 4 25 I/O PI: Address/Data bus AD7 5 26 I/O PI: Address/Data bus RD 35 16 I PI: Read / SI: no Function WR 36 17 I PI: Write / SI: no Function ALE 34 15 I PI: Address Latch Enable / SI:no Function CS 27 12 I Chip Select INT 41 18 O Interrupt MS 26 11 I Mode Select (PI ↔ SI) P00 … P03, P04 … P07 28, 29, 30, 31, 37, 38, 39, 40 I/O I/O Port 0 These pins provide internal pullup resistors of about 10...200 kΩ . P10 … P13, P14 … P17 18, 17, 16, 15, 9, 8, 7, 6 I/O I/O Port 1 These pins provide internal pullup resistors of about 10...200 kΩ . TX0 25 10 O Transmitter output 0 TX1 24 9 O Transmitter output 1 RX0 23 8 I Comparator input 0 / Digital input RX1 22 7 I Comparator input 1 2) VDDA 20 5 I Analog power supply for comparator (may be unconnected using the digital mode)

07Feb95@09:05h Intermediate Version Semiconductor Group 5 SAE 81C90/91 1) For best results keep the crystal circuitry connections as short as possible and keep the CLKOUT line away from it. 2) If the bus lines work according to the ISO specification, additional circuitry is necessary for interconnection of the input comparator to the bus lines. The digital mode is enabled by setting bit DI in register BL2. When using the digital mode pin RX1 should be on V SS . 3) It is recommended to decouple these supply pins close to the device using a 10 pF capacitor in addition to the standard 100 nF capacitor. VSSA 21 6 I Analog power ground for comparator (must always be connected) VDD1 13 2 I Digital power supply 3) VDD2 32 13 I Digital power supply VSS1 12 1 I Digital power ground 3) VSS2 33 14 I Digital power ground Pin Definitions and Functions (cont’d) Symbol Pin Number Input (I) Output (O) Function PLCC-48 PLCC-28

07Feb95@09:05h Intermediate Version Semiconductor Group 6 SAE 81C90/91 Functional Description The Siemens stand-alone Full-CAN (SFCAN) circuit is a large-scale-integrated peripheral device that executes the entire protocol of an automobile or industrial network. Figure 3 Block Diagram

07Feb95@09:05h Intermediate Version Semiconductor Group 7 SAE 81C90/91 Bus communication is based on the controller-area-network (CAN) protocol. With features like short message length, guaranteed reaction time for messages of appropriate priority, which is defined by the message identifiers. Also included are powerful error detection and treatment capabilities plus ease of operation. The CAN protocol is especially designed for the requirements of automobile and industrial electronic networks. The SFCAN circuit incorporates all the parts for completely independent transmission and reception of messages using the CAN protocol. The flexible, programmable interface allows connection to different implementations of the physical layer. The link to a host controller can be made either by a multiplexed 8-bit address/data bus or by a high-speed, serial synchronous interface. Message Memory The SFCAN circuit filters incoming messages with an associative memory (CAM = content- addressable memory). For this the identifier and RTR bits of the required message must be written to the appropriate memory location. The identifier of each incoming message is compared with the identifiers stored in the CAM. Upon a match the received data bytes are written into the RAM buffer of the matching message. At the same time the corresponding receive-ready bit is set and a receive interrupt is generated, if it is enabled. If no match is detected, the received message is rejected. Identifiers can be reprogrammed at any time, although it is possible that data of the old or new identifier may be lost during reprogramming. An incoming transmit request will only be satisfied automatically by the hardware if the RTR bit of the particular identifier is set in CAM. To ensure data consistency when reading or writing several data bytes of a specific message the message objects are not accessed directly but via a 64-bit shadow register (see figure below). This shadow register stores the complete data field of a certain message object for both reading and writing. For read accesses the message’s data field is copied to the shadow register... H ... 87H for message 0), or This ensures that all bytes read via the shadow register belong to the same message, even though a new one might have been received in the meantime. For write accesses the shadow register is copied to the respective message data field... H for message 0). This ensures that only completely updated message are transmitted. It is therefore recommended to begin all read and write accesses with the most-significant data byte of a message and end with data byte 0. This ensures operations on consistent data and correct transfers between the shadow register and the message RAM. Note: For these reasons it is absolutely essential to ensure that the writing of data is not interrupted by a read operation and vice versa, a read operation should not be interrupted by a write.

07Feb95@09:05h Intermediate Version Semiconductor Group 8 SAE 81C90/91 Figure 4 CAM, Message Memory and Time-Stamp Registers

07Feb95@09:05h Intermediate Version Semiconductor Group 9 SAE 81C90/91 Bit Stream Processor (BSP) The bit-stream processor controls the entire protocol, differentiates between the frames types and detects frame errors. Error Management Logic (EML) The error-management logic receives error messages from the BSP and, in turn, sends back information about error state to the BSP and CIL. Bit Timing Logic (BTL) The bit-timing logic determines the timing of the bits and synchronizes with the edges of the bit stream on the CAN bus. Transceiver Control Logic (TCL) The transceiver-control logic consists of programmable output driver, input comparator and input multiplexer. Clock Generator (CG) The clock generator consists of an oscillator and a programmable divider. The oscillator can be fed from an external quartz crystal, ceramic resonator or an external timing source. The permissible crystal frequency is 1 to 20 MHz, and the external clock may be between 0 and 20 MHz. A programmable frequency, dependent on the crystal clock, is available with the CLKOUT pin, e.g. for the clocking of a host controller. CPU Interface Logic (ClL) The CPU interface logic controls the access of the host via the parallel or serial interface, interprets the commands and outputs status and interrupt information. Transmit Check The CAN protocol ensures a very high integrity for the data transferred over the bus. The on-chip path from the data stored in parallel to the serial bit stream is not protected by the protocol. To eliminate any possible uncertainties at this point too, the SFCAN circuit incorporates a transmit- check unit. This unit reads back a transmitted message via the normal receive path from the bus interface and compares the data with those written into the message memory by the host controller. If any inconsistency of the data is detected, the current message will be invalidated by an error frame. The transmit-check error counter TCEC is then incremented by 1. If this counter reaches 4 an error interrupt (bit TCI in the INT register) is generated, provided that this has not been masked (bit ETCI in the IMSK register). This count will also produce the Bus Off status. The TCEC is set to 0 after a reset and can be read and also written for test purposes at any time. Note: The transmit-check is an additional feature of the Siemens Full CAN Chip and is not part of the CAN protocol.

07Feb95@09:05h Intermediate Version Semiconductor Group 10 SAE 81C90/91 Time Stamp It is impossible to determine from the received data in the message memory when they were received. So the host controller is unable to derive any information about the actuality or the repetition rate of the data. To enable an indication of the time of reception for at least some of the messages, a 16-bit timer is implemented on the SAE 81C90/91. The content of this gets written into the time-stamp registers of the particular message when it is received (for the messages 0 through 7). There are two time- stamp bytes for each of the messages 0 through 7, and these hold the value of the 16-bit timer. The actuality of a message is determined by subtracting the old time-stamp of a message, stored in the host controller, from the new one, with respect to the timer overflow bit. Overflow of the timer can be detected by bit TSOV in the CTRL register. This bit does not trigger an interrupt and has to be reset by the host controller. Depending on the setting of bitfield TSP in register CTRL, the counter is fed with 1/32, 1/64, 1/128 or 1/256 of the bus clock. The momentary timer status can be read and set at any time. The timer starts at 0 after a reset and cannot be stopped. I/O-Ports There are two parallel I/O ports in the SAE 81C90, each with eight pins. These ports are configured pin by pin as input or output, depending on the contents of the port-direction register. The output data for the port pins can be written (latched) into the port-latch register. Reading this register reproduces the contents of the latch. The levels on the port pins can be read from the port- pin register. For the SAE 81C91 in its P-LCC-28-1 package, the pads of the I/O ports are not bonded and therefore unavailable to the user. Note: Registers PxPDR and PxPL may be used for general purpose storage if the ports are not used.

07Feb95@09:05h Intermediate Version Semiconductor Group 11 SAE 81C90/91 Device Control and Registers The operation of the SAE 81C90/91 is controlled via a number of registers. These registers allow initialization and function control, provide status information and configure the message objects. The upper part of the address space provides access to the data buffers of the message objects. The data buffers are ordered sequentially as shown in the table below. The register map on the next page summarizes the other registers (i.e. except the data registers) ordered by their address, while the following pages describe these registers in more detail from a functional point of view. Note: Locations marked “ Reserved” in the register map must not be written in initialization mode. This also applies to locations 60H through 7FH . Data Registers Address Function 80H Byte 0 Message 0 81H Byte 1 82H Byte 2 83H Byte 3 84H Byte 4 85H Byte 5 86H Byte 6 87H Byte 7 88H Byte 0 Message 1 89H Byte 1 :: : H Byte 6 Message 14 F7H Byte 7 F8H Byte 0 Message 15 F9H Byte 1 FA H Byte 2 FB H Byte 3 FC H Byte 4 FD H Byte 5 FE H Byte 6 FFH Byte 7

07Feb95@09:05h Intermediate Version Semiconductor Group 12 SAE 81C90/91 Register Map (ordered by address) Note: The locations marked “UUH ” are not changed upon a reset. After a power on reset they are undefined (XXH ), of course. 00H BL1 00 H 20H Reserved --- 40H DR0H UU H 01H BL2 00 H 21H Reserved --- 41H DR0L UU H 02H OC 00 H 22H Reserved --- 42H DR1H UU H 03H BRP 00 H 23H Reserved --- 43H DR1L UU H 04H RRR1 00 H 24H Reserved --- 44H DR2H UU H 05H RRR2 00 H 25H Reserved --- 45H DR2L UU H 06H RIMR1 00 H 26H Reserved --- 46H DR3H UU H 07H RIMR2 00 H 27H Reserved --- 47H DR3L UU H 08H TRS1 00 H 28H P0PDR 00 H 48H DR4H UU H 09H TRS2 00 H 29H P0PR XX H 49H DR4L UU H 0AH IMSK 00 H 2AH P0LR 00 H 4AH DR5H UU H 0BH Reserved --- 2BH Reserved --- 4BH DR5L UU H 0C H Reserved --- 2C H P1PDR 00 H 4C H DR6H UU H 0D H Reserved --- 2D H P1PR XX H 4D H DR6L UU H 0EH Reserved --- 2EH P1LR 00 H 4EH DR7H UU H 0FH Reserved --- 2FH Reserved --- 4FH DR7L UU H 10H MOD 00 H 30H TSR0H UU H 50H DR8H UU H 11H INT 00 H 31H TSR0L UU H 51H DR8L UU H 12H CTRL 00 H 32H TSR1H UU H 52H DR9H UU H 13H Reserved --- 33H TSR1L UU H 53H DR9L UU H 14H CC 01 H 34H TSR2H UU H 54H DR10H UU H 15H TCEC 00 H 35H TSR2L UU H 55H DR10L UU H 16H TCD XX H 36H TSR3H UU H 56H DR11H UU H 17H Reserved --- 37H TSR3L UU H 57H DR11L UU H 18H TRR1 00 H 38H TSR4H UU H 58H DR12H UU H 19H TRR2 00 H 39H TSR4L UU H 59H DR12L UU H 1AH RRP1 00 H 3AH TSR5H UU H 5AH DR13H UU H 1BH RRP2 00 H 3BH TSR5L UU H 5BH DR13L UU H 1C H TSCH 00 H 3C H TSR6H UU H 5C H DR14H UU H 1D H TSCL 00 H 3D H TSR6L UU H 5D H DR14L UU H 1EH Reserved --- 3EH TSR7H UU H 5EH DR15H UU H 1FH Reserved --- 3FH TSR7L UU H 5FH DR15L UU H

07Feb95@09:05h Intermediate Version Semiconductor Group 13 SAE 81C90/91 Descriptor Registers A descriptor register is available for each message object and contains the eleven bits of the message identifier (ID.0 through ID.10), the remote-transmission-request bit (RTR) and the data length code (DLC) of a message. n = 0...15 Bit RTR determines the function of the corresponding message object when it is transmitted, and its reaction on a received data frame or remote frame. The table below summarizes the message object’s behaviour in the different cases. Note: For the transmission of remote frames (RTR = 1) the data-length-code should be set to ‘0’. DRnH 76543210 Address: XX Reset Value: UUH rw rw rw rw rw rw rw rw DRnL 76543210 Address: XXH ID.2 ID.1 ID.0 RTR DLC Reset Value: UUH rw rw rw rw rw rw rw rw Bit(field) Function DLC Data Length Code Defines the number of data bytes of message n. RTR Remote Transmission Request Bit ‘0’: This message operates as a data frame. ‘1’: This message operates as a remote frame. Note: See description and table below. ID.10-0 Identifier Identifier associated with message n, controls the acceptance of received frames and is inserted into transmitted frames. RTR bit Object is transmitted Matching Data Frame received Matching Remote Frame received ’0’ (data frame) The message object is transmitted as a standard data frame. The data frame is stored in the message object. The remote frame is ignored. ’1’ (remote frame) The message object is transmitted as a remote frame (i.e. a request). The data frame is ignored and not stored. The message object is sent as a data frame.

07Feb95@09:05h Intermediate Version Semiconductor Group 14 SAE 81C90/91 Descriptor Register Arrangement Address Function 40H High Byte Descriptor Register for Message Object 0 41H Low Byte 42H High Byte Descriptor Register for Message Object 1 43H Low Byte ::: H High Byte Descriptor Register for Message Object 14 5D H Low Byte 5EH High Byte Descriptor Register for Message Object 15 5FH Low Byte

07Feb95@09:05h Intermediate Version Semiconductor Group 15 SAE 81C90/91 Control Register Summary Note: 1)ro: read only,r/w: read and write access,wo: write only,I: access only with bit IM set. Register Name Address Function Reset Value Read Write1) OC 02 H Output-control register 00 H r/w, I CC 14 H Clock-control register 01 H wo CTRL 12 H Control register 00 H r/w MOD 10 H Mode/status register 00 H r/w INT 11 H Interrupt register 00 H r/w IMSK 0A H Interrupt-mask register 00 H r/w BL1 00 H Bit-length register 1 00 H r/w, I BL2 01 H Bit-length register 2 00 H r/w, I BRP 03 H Baud-rate prescaler 00 H wo, I RRR1 04 H Receive-ready register 1 00 H r/w RRR2 05 H Receive-ready register 2 00 H r/w RIMR1 06 H Receive-interrupt-mask register 1 00 H r/w RIMR2 07 H Receive-interrupt-mask register 2 00 H r/w TRSR1 08 H Transmit-request-set register 1 00 H r/w TRSR2 09 H Transmit-request-set register 2 00 H r/w TRRR1 18 H Transmit-request-reset register 1 00 H wo TRRR2 19 H Transmit-request-reset register 2 00 H wo RRPR1 1A H Remote-request-pending register 1 00 H ro RRPR2 1B H Remote-request-pending register 2 00 H ro TSCH 1C H Time-Stamp counter high byte 00 H r/w TSCL 1D H Time-Stamp counter low byte 00 H r/w TCEC 15 H Transmit-check error counter 00 H r/w TCD 16 H Transmit-check data register XX ro P0PDR 28 H Port 0 port-direction register 00 H r/w P1PDR 2C H Port 1 port-direction register 00 H r/w P0LR 2A H Port 0 latch register 00 H r/w P1LR 2E H Port 1 latch register 00 H r/w P0PR 29 H Port 0 pin register XX H ro P1PR 2D H Port 1 pin register XX H ro

07Feb95@09:05h Intermediate Version Semiconductor Group 16 SAE 81C90/91 Output-Control Register The output drivers of the SAE 81C90/91’s transmit pins (TXn) can be individually configured. Thus they can be adapted to the requirements of the external bs system. n = 0, 1 Note: This register can only be written when bit IM (MOD.0) is set. Figure 5 Output Control Circuitry OC 76543210 Address: 02H OCTP1 OCTN1 OCP1 OCTP0 OCTN0 OCP0 OCM Reset Value: 00H rw rw rw rw rw rw rw rw Bit(field) Function OCM Output Mode ’0X’:Normal Mode : TX0 = Bit Sequence, TX1 = Bit Sequence. ’10’:Test Mode: TX0 = Bit Sequence, TX1 = RX0. ’11’:Clock Mode: TX0 = Bit Sequence, TX1 = Bit Clock. OCPn Output Polarity ’0’: Output is driven directly with CAN data. ’1’: Output is driven with inverted CAN data. OCTNn Negative Output Transistor Control ’0’: The low side output transistor TnN is disabled. ’1’: The low side output transistor TnN drives the pin according to data. OCTPn Positive Output Transistor Control ’0’: The high side output transistor TnP is disabled. ’1’: The high side output transistor TnP drives the pin according to data.

07Feb95@09:05h Intermediate Version Semiconductor Group 17 SAE 81C90/91 Output Programming TnP is the output transistor switching toVDD , TnN switches toVSS . TXn is the output level at the transmit pin. Clock Control Register The Clock Control Register determines the output frequency at pin CLKOUT which is derived from the oscillator frequency. The Clock Control Register requires a special protocol for writing in order to prevent the clock output from being changed inadvertently:

• Step 1: Write 80H to CC
• Step 2: Write desired value to CC (bits 7...4 must be ’0000’) Note: Not defined bit positions must be ’0’ for write accesses. OCTP.n OCTN.n OCP.n Data TnP TnN TXn-Level 0000 = dominant OFF OFF float 0001 = recessive OFF OFF float

0010 O F F O F F float

0011 O F F O F F float

0100 O F F O N L O W

0101 O F F O F F float

0110 O F F O F F float

0111 O F F O N L O W

1000 O F F O F F float

1001 O N O F F HIGH

1010 O N O F F HIGH

1011 O F F O F F float

1100 O F F O N L O W

1101 O N O F F HIGH

1110 O N O F F HIGH

1111 O F F O N L O W

Address: 14 H ---- C C Reset Value: 01H - - - - wwww Bit(field) Function CC Clock Output Control ’0000’: fCLKOUT = fOSC ’0001’: fCLKOUT = fOSC / 2 ’0010’: fCLKOUT = fOSC / 4 ’0011’: fCLKOUT = fOSC / 6 ’0100’: fCLKOUT = fOSC / 8 ’0101’: fCLKOUT = fOSC / 10 ’0110’: fCLKOUT = fOSC / 12 ’0111’: fCLKOUT = fOSC / 14 ’1XXX’: fCLKOUT = LOW (clock output is switched off)

07Feb95@09:05h Intermediate Version Semiconductor Group 18 SAE 81C90/91 Control Register CTRL 76543210 Address: 12H RX TST TSP TSOV SME TCE MM Reset Value: 00H rw rw rw rw rw rw rw rw Bit(field) Function MM Monitor Mode ’0’: Message object 0 operates like all other objects. ’1’: Message object 0 receives all identifiers that are not accepted by other objects (corresponds to a Basic CAN receive register). TCE Transmit Check Enable ’0’: If the transmit check detects an error, there is no intervention. ’1’: If the transmit check detects an error, the message is invalidated by an error frame and the error counter TCEC is incremented by 1. If the counter reaches 4, the Bus Off status is initiated and, if enabled, an interrupt (TCI) is generated. SME Sleep Mode Enable ’0’: Normal operation. ’1’: The sleep mode is enabled: the crystal oscillator is deactivated, all other activities are inhibited. The wake up is done by a reset signal or by an active signal at the CS pin or by an input edge going from recessive to dominant at pin Rx0 or Rx1. TSOV Time Stamp Overflow ’0’: There has been no overflow ’1’: There was at least one overflow of the time-stamp timer. TSP Time Stamp Prescaler (Defines the input clock of the time-stamp timer) ’00’: fBL / 32 ’01’:fBL / 64 ’10’:fBL / 128 ’11’:fBL / 256 (ForfBL see baud-rate prescaler BRP). TST Time Stamp Test ’0’: The prescaler is activated. ’1’: The time-stamp prescaler is deactivated. (Only for testing purposes, bit IM = MOD.0 must be set to ’1’). RX Input Monitor RX This bit monitors the actual state of the digital input pin RX0.

07Feb95@09:05h Intermediate Version Semiconductor Group 19 SAE 81C90/91 Mode/Status-Register MOD 76543210 Address: 10H ADE RS TC TWL RWL BS RES IM Reset Value: 00H r w rrrrr r w r w Bit(field) Function IM Init Mode ’0’: Normal mode. ’1’: Initialization mode: write access to the configuration registers BL1, BL2, OC, BRP is enabled. If the bit stays set, the chip enters the normal mode, with enabled access to the configuration registers. If this bit is set in conjunction with bit RES a hard software reset is activated. RES Reset Request ’0’: Normal mode. ’1’: The chip enters the reset state: – if bit IM = ’0’ a soft software reset takes place. – if bit IM = ’1’ a hard software reset takes place. Further details see below. BS Bus State (read only) ’0’: Normal mode. ’1’: Bus Off state, the IC does not participate in bus activities. RWL Receiver Warning Level (read only) ’0’: Receive-error counter below 96. ’1’: Receive-error counter equal or above 96. TWL Transmit Warning Level (read only) ’0’: Transmit-error counter below 96. ’1’: Transmit-error counter equal or above 96. TC Transmission Complete (read only) ’0’: The last transmission request is not yet executed successfully. ’1’: The last transmission request was executed successfully. RS Receive State (read only) ’0’: No reception active. ’1’: Currently the SAE 81C90/91 is in receive mode. ADE Auto Decrement Enable ’0’: No automatic address decrement. ’1’: With every read or write access using the serial synchronous interface SI the address is automatically decremented by one. So data can be accessed sequentially without the need of writing a new address.

07Feb95@09:05h Intermediate Version Semiconductor Group 20 SAE 81C90/91 Notes on Bit TC Scanning this bit is particularly useful if only one transmission is active. If there are several transmission jobs at the same time, it is better to scan the transmit-request register, because bit TC may possibly only be set very briefly between acknowledgment of the previous message and the start of the next one. Notes on Bit RES and IM and reset modes There are three different reset modes implemented in the SAE 81C90/91: hardware reset (activated by low level on pin RES) hard software reset (activated by setting both bits RES and IM to 1) soft software reset (activated by setting bit RES to 1 and bit IM to 0) The only difference between hardware and hard software reset affect bits RES and IM, that are not changed by software reset. With soft software reset the registers RRR1, RRR2, TRSR1, TRSR2, RRPR1 and RRPR2 are cleared, all bus activities are stopped, the error counters are not cleared, the Bus Off state is cancelled only after 128 idle phases (according to the CAN protocol 1 idle phase = 11 recessive bits in sequence). Simply spoken a soft software reset interrupts and cancels all bus activities and - if necessary - recovers from Bus Off state. Notes on Bit RS Bit RS directly reflects the internal status. RS is ’0’ during transmission or when the SAE 81C90/91 is idle. RS is ’1’ during reception or during the synchronization after a reset.

07Feb95@09:05h Intermediate Version Semiconductor Group 21 SAE 81C90/91 Interrupt Register Note: All bits of this register must be reset by software. This is done by writing ’0’ to the respective bit location, writing ’1’ has no effect. An interrupt is only generated if the respective IMSK bit is set. The bits in this register are set independent of register IMSK (see below). The interrupt output is active for at least one bit time. The interrupt output is deactivated when all enabled request bits are cleared. A request bit is enabled by setting its corresponding mask bit. Masked request bits do not activate the interrupt output. INT 76543210 Address: 11 H TCI EPI BOI WUPI RFI WLI TI RI Reset Value: 00H rw rw rw rw rw rw rw rw Bit(field) Function RI Receive Interrupt After a valid message has been received and filed, this bit is set and an interrupt generated. This bit will remain set until all bits of the registers RRR1 and RRR2 are reset. TI Transmit Interrupt This bit is set and an interrupt generated as soon as a transmit request has been processed. WLI Warning Level Interrupt If at least one of the two error counters is greater than or equals 96, this bit is set and an interrupt generated. RFI Remote Frame Interrupt This interrupt is generated after reception of a remote frame. WUPI Wake Up Interrupt After a wake-up this bit is set and an interrupt generated. BOI Bus Off Interrupt This bit is set and an interrupt generated when the Bus Off status is entered. EPI Error Passive Interrupt If at least one of the two error counters is greater than or equals 128, this bit is set and an interrupt generated. TCI Transmit Check Interrupt If the transmit-check error counter reaches 4, this bit is set and an interrupt generated.

07Feb95@09:05h Intermediate Version Semiconductor Group 22 SAE 81C90/91 Interrupt-Mask Register These mask bits determine if an event activates the INT pin. They do not influence the INT register. IMSK 76543210 Address: 0AH ETCI EEPI EBOI EWUPI ERFI EWLI ETI ERI Reset Value: 00H rw rw rw rw rw rw rw rw Bit(field) Function ERI Enable Receive Interrupt ’0’: No receive interrupt enabled. ’1’: Receive interrupts are enabled. ETI Enable Transmit Interrupt ’0’: No transmit interrupt enabled. ’1’: Completed transmit jobs generate interrupts. EWLI Enable Warning Level Interrupt ’0’: No warning level interrupt enabled. ’1’: There is an interrupt when the warning level is reached. ERFI Enable Remote Frame Interrupt ’0’: No remote frame interrupt enabled. ’1’: A receive interrupt is generated after receiving a remote frame EWUPI Enable Wake Up Interrupt ’0’: No wake up interrupt enabled. ’1’: Wake-up interrupt is enabled. EBOI Enable Bus Off Interrupt ’0’: No bus off interrupt enabled. ’1’: Bus off interrupt is enabled. EEPI Enable Error Passive Interrupt ’0’: No error passive interrupt enabled. ’1’: Error passive interrupt is enabled. ETCI Enable Transmit Check Error Interrupt ’0’: No transmit check interrupt enabled. ’1’: Transmit-check error interrupt is enabled.

07Feb95@09:05h Intermediate Version Semiconductor Group 23 SAE 81C90/91 Bit-Length Registers Note: Not defined bit positions must be ’0’ for write accesses. The Bit Length Registers BL1 and BL2 can only written while bit IM (MOD.0) is set. 1) If the bus lines work according to the ISO specification, additional circuitry is necessary for interconnection of the input comparator to the bus lines. BL1 76543210 Address: 00H SAM TS2 TS1 Reset Value: 00H rw rw rw rw rw rw rw rw Bit(field) Function TS1 Length of Timing Segment 1 (TSeg1). tTSeg1 = (TS1 + 1)× tSCL . FortSCL see baud-rate prescaler BRP. TS2 Length of Timing Segment 2 (TSeg2). tTSeg2 = (TS2 + 1)× tSCL . FortSCL see baud-rate prescaler BRP. SAM Sample Rate ’0’: Input signal is sampled once per bit. ’1’: Input signal is sampled three times per bit. Note: Bit SAM should only be set to ’1’ using very low baud rates. BL2 76543210 Address: 01 H IPOL DI – – – SM SJW Reset Value: 00H rw rw - - - rw rw rw Bit(field) Function SJW Maximum Synchronization Jump Width. tSJWidth = (SJW + 1)× tSCL . FortSCL see baud-rate prescaler BRP. SM Speed Mode (Defines edge used for synchronization) ’0’: Recessive to dominant is used. ’1’: Both edges are used. Note: According to the CAN specification this bit should not be set to ’1’. DI Digital Input ’0’: The input signal is applied to the input comparator. ’1’: The input signal on pin RX0 is evaluated digitally. The input comparator is inactive. Pin RX1 should be onVSS . IPOL Input Polarity ’0’: The input level remains unaltered. ’1’: The input level is inverted.

07Feb95@09:05h Intermediate Version Semiconductor Group 24 SAE 81C90/91 Baud Rate Prescaler Register The register is not readable and can only be written when bit IM (MOD.0) is set. Note: Not defined bit positions must be ’0’ for write accesses. The bit lengthtBL is computed as follows: tBL =tTSeg1 +tTSeg2 + 1tSCL The baudrate BR can be computed with the following formula: BR = fcrystal / (2 x (BRP + 1) x (TS1 + TS2 + 3) ) Note: BRP see Baud Rate Prescaler Register TS1 see Bit Length Register 1 TS2 see Bit Length Register 1 BRPR 76543210 Address: 03 H – – BRP Reset Value: 00H - - wwwwww Bit(field) Function BRP Baud Rate Prescaler This prescaler determines the period of the system clock: tSCL = (BRP + 1)× 2× tOSC , wheretOSC = 1 /fcrystal.

07Feb95@09:05h Intermediate Version Semiconductor Group 25 SAE 81C90/91 Receive-Ready Registers These register bits can be reset by writing ’0’ to the respective bit, writing ’1’ has no effect. Bit RRn is set when a message has arrived and been written into the memory location of message n. Setting this bit by hardware can generate a receive interrupt, which can be blocked by bit RIMn in the receive-interrupt-mask register. Bits RRn must be reset by software. Receive-Interrupt-Mask Registers Setting bit RIMn enables a receive interrupt to be generated if the receive-ready bit RRn has been set, i.e. a message has arrived and was written into the memory location of message n. Note: Bit ERI in the interrupt-mask register IM blocks all receive interrupts, even if bits RIMn are set. RRR2 76543210 Address: 05 H RR15 RR14 RR13 RR12 RR11 RR10 RR9 RR8 Reset Value: 00H rw rw rw rw rw rw rw rw RRR1 76543210 Address: 04H RR7 RR6 RR5 RR4 RR3 RR2 RR1 RR0 Reset Value: 00H rw rw rw rw rw rw rw rw Bit(field) Function RRn Receive Ready Bit ’0’: No new message received in object n. ’1’: A new message has been received and stored in object n. RIMR2 76543210 Address: 07 H RIM15 RIM14 RIM13 RIM12 RIM11 RIM10 RIM9 RIM8 Reset Value: 00H rw rw rw rw rw rw rw rw RIMR1 76543210 Address: 06H RIM7 RIM6 RIM5 RIM4 RIM3 RIM2 RIM1 RIM0 Reset Value: 00H rw rw rw rw rw rw rw rw Bit(field) Function RIMn Receive Interrupt Mask Bit ’0’: No interrupt upon reception of object n. ’1’: When a new message is stored in object n an interrupt is generated.

07Feb95@09:05h Intermediate Version Semiconductor Group 26 SAE 81C90/91 Transmit Request Registers The Transmit Request Set Registers provide a transmission request bit (TRSn) for each message object. Setting a transmission request bit causes the respective message x to be transmitted. The bit is cleared by hardware after transmission. Several bits can be set simultaneously. In this way all messages whose request bits are set are transmitted in turn, starting with the memory location with the highest number. Note: A transmission request bit is set by writing ’1’ to the respective bit location (TRSn). Writing ’0’ has no effect. n = 0...15 The Transmit Request Reset Registers provide a transmit request reset bit (TRRn) for each transmit request bit TRSn, i.e. for each message object. Writing ’1’ to a TRRn bit clears the corresponding transmission request bit TRSn. This causes a transmission request, initiated by the corresponding bit TRSn, to be cancelled, provided that it is not currently processed. This scheme avoids conflicts when writing to register bits while they are cleared by hardware because of a completed transmission. Note: Registers TRRRx cannot be read. TRSR2 76543210 Address: 09 H TRS15 TRS14 TRS13 TRS12 TRS11 TRS10 TRS9 TRS8 Reset Value: 00H rw rw rw rw rw rw rw rw TRSR1 76543210 Address: 08H TRS7 TRS6 TRS5 TRS4 TRS3 TRS2 TRS1 TRS0 Reset Value: 00H rw rw rw rw rw rw rw rw Bit(field) Function TRSn Transmit Request Set Bit ’0’: No change of the respective transmit request bit. ’1’: The respective transmit request bit is cleared.

07Feb95@09:05h Intermediate Version Semiconductor Group 27 SAE 81C90/91 Remote-Request-Pending Registers n = 0...15 TRRR2 76543210 Address: 19H TRR15 TRR14 TRR13 TRR12 TRR11 TRR10 TRR9 TRR8 Reset Value: 00H wwwwwwww TRRR1 76543210 Address: 18H TRR7 TRR6 TRR5 TRR4 TRR3 TRR2 TRR1 TRR0 Reset Value: 00H wwwwwwww Bit(field) Function TRRx Transmit Request Reset Bit ’0’: No change of the respective transmit request bit. ’1’: The respective transmit request bit is cleared. RRPR2 76543210 Address: 1B H RRP15 RRP14 RRP13 RRP12 RRP11 RRP10 RRP9 RRP8 Reset Value: 00H rrrrrrrr RRPR1 76543210 Address: 1AH RRP7 RRP6 RRP5 RRP4 RRP3 RRP2 RRP1 RRP0 Reset Value: 00H rrrrrrrr Bit(field) Function RRPn Remote Request Pending Bit ’0’: No remote request pending. ’1’: A remote request (remote frame) for message n was received but is not yet answered by the transmission of the corresponding data frame.

07Feb95@09:05h Intermediate Version Semiconductor Group 28 SAE 81C90/91 Message Time Stamp This mechanism stores the time at which a specific message was received, i.e. it assigns a time stamp to that message. For this purpose the contents of the free-running time stamp counter TSC is copied to the time stamp register TSRn of the respective message object upon reception of this message. The Time Stamp Counter Registers provide access to the free-running time stamp counter. The Time-Stamp Registers are available for each of message objects 0...7 (see table below) and contain the time-stamp of the corresponding message. These registers can only be read. n = 0...7 TSCH 76543210 Address: 1C Reset Value: 00H rw rw rw rw rw rw rw rw TSCL 76543210 Reset Value: 00H rw rw rw rw rw rw rw rw Bit(field) Function TSC Time Stamp Counter Current contents of the free running time stamp counter. TSRnH 76543210 Reset Value: UUH rrrrrrrr TSRnL 76543210 Reset Value: UUH rrrrrrrr Bit(field) Function TSn Time Stamp n A 16-bit timer value to identify the time of reception of message n.

07Feb95@09:05h Intermediate Version Semiconductor Group 29 SAE 81C90/91 Time Stamp Register Table Transmit Check Error Counter Note: Not defined bit positions must be ’0’ for write accesses. Transmit Check Data Register This register supports an error analysis when a transmit check error is encountered. Reading TCD provides the byte which was actually being sent when the error occurred. Address Function 30H High Byte Time-Stamp 0 31H Low Byte 32H High Byte Time-Stamp 1 33H Low Byte ::: H High Byte Time-Stamp 6 3D H Low Byte 3EH High Byte Time-Stamp 7 3FH Low Byte TCEC 76543210 Address: 15H ----- TCECV Reset Value: 00H ----- r w r w r w Bit(field) Function TCECV Transmit Check Error Counter Value Number of errors detected by the transmit check unit. When a count of 4 is reached an interrupt is generated if enabled. If bit TCE (CTRL.1) is set to ’1’ the Bus Off status is entered in this case. TCD 76543210 Address: 16 H Data Byte Reset Value: XXH rrrrrrrr Bit(field) Function Data Byte The data byte which was attempted to be sent while a transmit check error was encountered.

07Feb95@09:05h Intermediate Version Semiconductor Group 30 SAE 81C90/91 Port Control Registers These registers control the parallel ports P0 and P1 which are provided in the SAE 81C90. The Port Direction Registers PxPDR select each port pin separately for input (PxPDR.n=’0’) or output (PxPDR.n=’1’). After reset the ports are switched as inputs. The Port Latch Registers PxLR store the output data for those port pins that are switched to output. The Port Pin Registers PxPR provide the current level of the port pins. These registers can only be read. In parallel to the standard CMOS structure there are additional internal pullup devices of about 10...200 kΩ at each port pin. Note: Registers PxPDR and PxPL may be used for general purpose storage if the ports are not used. P1PDR 76543210 Reset Value: 00H rw rw rw rw rw rw rw rw P0PDR 76543210 Reset Value: 00H rw rw rw rw rw rw rw rw P1LR 76543210 Reset Value: 00H rw rw rw rw rw rw rw rw P0LR 76543210 Reset Value: 00H rw rw rw rw rw rw rw rw P1PR 76543210 Reset Value: 00H rrrrrrrr P0PR 76543210 Reset Value: 00H rrrrrrrr

07Feb95@09:05h Intermediate Version Semiconductor Group 31 SAE 81C90/91 Bit Timing A regular bit period is composed of the following three segments:

• synchronization segment
• timing segment 1
• timing segment 2. The sampling point is between timing segment 1 and timing segment 2. Figure 6 Bit Time Segments Synchronization The edge of the input signal is expected during the sync segment (duration = 1 system clock cycle = 1tSCL ). Timing Segment 1 (TSeg1) Timing segment 1 determines the sampling point within a bit period. This point is always at the end of segment 1. The segment is programmable from 1 to 16tSCL (see bit-length register BL1). Timing Segment 2 (TSeg2) Timing segment 2 provides extra time for internal processing after the sampling point. The segment is programmable from 1 to 8tSCL (see bit-length register BL1). Synchronization Jump Width (SJW) To compensate for phase shifts between the oscillator frequencies of the different bus stations, each CAN controller must be able to synchronize to the relevant signal edge of the incoming signal. The synchronization jump width (SJW) determines the maximum number of system clock pulses by which the bit period can be lengthened or shortened for resynchronization. The synchronization jump width is programmable from 1 to 4 tSCL (see bit-length register BL2).

07Feb95@09:05h Intermediate Version Semiconductor Group 33 SAE 81C90/91 Host Interfaces There are two different host interfaces implemented in the SAE 81C90/91. Data and addresses on a multiplexed 8-bit bus, compatible with Siemens microcontrollers (C5xx, C16x), can be transferred via the parallel interface (PI). Using the serial synchronous interface (Sl), any host controller with a serial three-lead interface can be connected with. The interface is selected by hardware through the wiring of the MS (Mode Select) pin. This pin may not be switched during operation. If there is a High level on the MS pin, the SI and thus pins DI, DO, CLK, W and TIM are activated, while pins AD5 through AD7,RD, WR and ALE are inactive. A Low level on the MS pin switches to the Pl and thus activates pins AD0 through AD7,RD, WR and ALE. Parallel Interface Pl The parallel interface uses a multiplexed 8-bit address/data bus. First the address of the required register is applied to the pins AD0 through AD7. A falling edge on pin ALE means that this address is transferred to an on-chip latch. After this, data can either be written into the selected register (pin WR = 0) or read from it (pinRD = 0) via the address/data bus. PinCS must be 0 for the entire duration of theRD/WR active time so that the circuit is activated. Serial Synchronous Interface Sl If the SI is used the unused pins of PI must be set to inactive levels (RD, WR to VDD and ALE, AD5, AD6, AD7 toVSS ). Communication on the SI is accomplished according to the following procedure: Each access to the stand-alone Full-CAN circuit has to be started by activating the device ( CS = 0). After the beginning of access, an address must be written first and then data can be read or written. The required function is determined by pin W (W = 1: read;W = 0: write). If the automatic decrementing of the address is activated (bit ADE in the MOD register), any number of data bytes can be accessed in succession. Finally the device has to be deactivated. Procedure:

• Activate device (CS = 0)
• Set pinW to 1 for read, to 0 for write
• Write in address of first data byte
• Read out/write in one or more data bytes
• Deactivate device (CS = 1) The most-significant bit is always output as the first bit of an address or a data byte. Data from pin DI are transferred into the internal shift register with therising edge of the clock. The active clock edge of pin DO is selectable via the pin TIM. If this pin is 0 the data are output from the shift register to pin DO with therising clock edge (Timing A). If the pin TIM is 1, the output of data is done with thefalling edge (Timing B). The timing for reading and writing of two data bytes with automatic decrementing activated is illustrated below.

07Feb95@09:05h Intermediate Version Semiconductor Group 34 SAE 81C90/91 Figure 9 Serial Interface Timing (for 2 Data Bytes)

07Feb95@09:05h Intermediate Version Semiconductor Group 35 SAE 81C90/91 Absolute Maximum Ratings Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions ( VIN > VCC orVIN < VSS ) the voltage on pins with respect to ground (VSS ) must not exceed the values defined by the Absolute Maximum Ratings. Parameter Interpretation The parameters listed in the following partly represent the characteristics of the SAE 81C90/91 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: DC (D eviceC haracteristics): The logic of the SAE 81C90/91 will provide signals with the respective timing characteristics. SR (System R equirement): The external system must provide signals with the respective timing characteristics to the SAE 81C90/91.

07Feb95@09:05h Intermediate Version Semiconductor Group 36 SAE 81C90/91 DC Characteristics VCC = 5 V± 10 %; VSS = 0 V TA = – 40 to + 110 ˚C Notes 1) If the bus lines work according to the ISO specification, additional circuitry is necessary for interconnection of the input comparator to the bus lines. 2) Not 100% tested, guaranteed by design characterization. 3) This value is a typical value! 5) In oscillator mode the size of the low-end capacitance must correspond to the specification of the crystal manufacturer. The optimum values depend on the selected crystal, the intended frequency and the actual application hardware (stray capacitances). 10 pF are recommended for C For best results keep the crystal circuitry connections as short as possible and keep the CLKOUT line away from it. If the CLKOUT signal is not required by the system it should be switched off. Parameter Symbol Limit Values Unit Test Condition min. max. Input low voltage (all except XTAL1 and XTAL2) VIL SR 0 0.3 VCC V– Input low voltage (XTAL1 and XTAL2) VILX SR 0 0.5 V – Input high voltage (all except XTAL1 and XTAL2) VIH SR 0.7 VCC VCC V– Input high voltage (XTAL1 and XTAL2) VIHX SR VCC – 1.0 VCC V– Comparator input voltage 1) VCI SR 0.5 VCC + 0.5 V – Common mode voltage 2) VICOM SR 1.5 VCC – 1.5 V – Hysteresis 2) VHYS DC – 100 3) mV – Offset voltage 2) VOFF DC – 100 3) mV – Output low voltage (all except CLKOUT, TX0, TX1) VOL DC – 0.2 VCC V IOL = 1.6 mA Output low voltage (CLKOUT) VOLC DC – 0.4 V IOL1 = 10 mA Output high voltage (all except CLKOUT, TX0, TX1) VOH DC 0.8 VCC VCC V IOH = – 1.6 mA Output high voltage (CLKOUT) VOHC DC VCC – 0.8 VCC V IOH = – 10 mA Input leakage current II DC – ±1 µA 0 V < VIN <VCC Source output current (TX0, TX1)ISRC D C 5–m A VO =VCC – 1 V Sink output current (TX0, TX1)ISNK D C 5–m A VO = 1 V Low end capacitance 5) C L DC 6.8 12 pF Pin capacitance 2) C I DC – 10 pF f = 1 MHz TA = 25 ˚C Power supply current ICC –3 0 m A

07Feb95@09:05h Intermediate Version Semiconductor Group 37 SAE 81C90/91 AC Characteristics(General Timing) VCC = 5 V± 10 %; VSS = 0 V TA = – 40 to + 110 ˚C 1) Not 100% tested, guaranteed by design characterization. AC Characteristics (SI Timing) VCC = 5 V± 10 %; VSS = 0 V TA = – 40 to + 110 ˚C;C L = 50 pF Parameter Symbol Limit Values Unit Test Conditions min. max. Oscillator period tOSC SR 50 - ns Clock input high time tH SR 23.5 – ns Clock input low time tL SR 23.5 – ns Reset pulse width tRES SR 2 – tOSC Output rise time 1) tQR DC – 40 ns C L = 70 pF Output fall time 1) tQF DC – 40 ns C L = 70 pF CLKOUT rise time 1) tQRC DC – 20 ns C L = 50 pF CLKOUT fall time 1) tQFC DC – 20 ns C L = 50 pF Parameter Symbol Limit Values Unit Test Conditions min. max. Chip Select Setup tCSS SR 10 ns Clock High Time tCH SR 1.5 tOSC + ns Clock Low Time tCL SR 1.5 tOSC + ns Clock Period tC SR 4 tOSC ns DI Setup tDIS SR 10 ns DI Hold tDIH SR 0 ns Address to Data Out tADO DC 3 tOSC ns Output Delay tOD DC 25 ns Data Float afterCS high tDF DC 25 ns Chip Select Hold tCSH SR 1 tOSC ns Write to Clock tWC 0n s W toCS high tWCS SR 0 ns Address to Data In tADI DC 0 ns

07Feb95@09:05h Intermediate Version Semiconductor Group 39 SAE 81C90/91 Figure 12 SI-Write-Timing AC Characteristics (PI Timing) VCC = 5 V± 10 %; VSS = 0 V TA = – 40 to + 110 ˚C;C L = 50 pF Parameter Symbol Limit Values Unit Test Condition min. max. Read-Cycle time tCYR DC 4 tOSC ns Write-Cycle time tCYW DC 4 tOSC ns ALE pulse width tLHLL DC 30 ns Address setup to ALE low tAVLL SR 10 ns Address hold after ALE low tLLAX SR 10 ns RD pulse width tRLRH SR 2 tOSC + 30 ns WR pulse width tWLWH SR 2 tOSC + 30 ns ALE low toWR active tLLWL SR 20 ns ALE low toRD active tLLRL SR 20 ns Data float afterRD high tRFDX DC 0 20 ns RD low to data valid tRLDV DC 2 tOSC + 20 ns Data setup beforeWR high tDVWH SR 10 ns Data hold afterWR high tWHDX SR 5 ns CS low toRD low tCLRL /SR 0 ns CS low toWR low tCLWL SR 0 ns WR high to next ALE low tWHLL SR 1.5 tOSC ns