Microcontroller

SAB9075H

NXP Semiconductors

Picture-in-Picture PIP controller for NTSC February 1995

Manufacturer: NXP Semiconductors

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Preliminary speciﬁcation File under Integrated Circuits, IC02 February 1995 INTEGRATED CIRCUITS Philips Semiconductors SAB9075H Picture-in-Picture (PIP) controller for NTSC

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H

FEATURES

One or two live pictures can be displayed simultaneously
Wide range of multi-Picture-In-Picture (PIP) modes available
Six 6-bit Analog-to-Digital Converters (ADC) with clamping circuit
Enhanced vertical resolution at most modes for live pictures
Two Phase-Locked-Loops (PLL) with Voltage Controlled Oscillator (VCO) to generate the line-locked clocks
Three 7-bit Digital-to-Analog Converters (DAC)
4:1:1 data format
Data reduction factors 1 to 4, 1 to 9 and 1 to 16. I 2C-bus programmable
Different single, double and multi-PIP modes can be set
Several aspect ratios can be handled
Reduction factors can be set automatically and manually
Selection of vertical filtering type
Freeze of live pictures
Single-PIP display position, four corners on-screen
Multi-PIP display position, left or right on-screen
Fine tuned display position, H (6-bit), V (6-bit)
Fine tuned acquisition area, H (4-bit), V (4-bit)
Channel-border and live PIP selectable
Eight main-border, sub-border, channel-border and background colours selectable
Border and background brightness adjustable, 30%, 50%, 70% and 100% IRE
Several types of decoder input signals can be set
6-bit HUE and SAT signals (0 to 5 V) adjustable by I2C-bus
Main and sub-audio mute controllable by I2C-bus. GENERAL DESCRIPTION The SAB9075H is a picture-in-picture controller for the NTSC environment in combination with the Integrated NTSC decoder and sync processor TDA8315. The device inserts one or two live video channels with reduced sizes into a live video signal. All video signals are expected to be analog baseband signals. The conversion into the digital environment and back to the analog environment is carried out on-chip. Internal clocks are generated by two PLLs. Due to the two PIP channels and a large external memory, a wide range of PIP modes are offered. The emphasis is put on double-PIP and multi-PIP modes. In combination with the different border colours and some external software the IC concept can be used as an excellent channel selection tool. Some of the I 2C-bus registers are for controlling the saturation and HUE of the colours. There are also outputs for the mute function of main and sub-channel.

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H

ORDERING INFORMATION

When using IR reflow soldering it is recommended that the Drypack instructions in the“Quality Reference Handbook” (order number 9398 510 63011) are followed. QUICK REFERENCE DATA Notes 1. Digital clocks are silent and analog bias current is zero. 2. The internal system frequencies are 1728 times the input frequency. For more detailed information about the clock generation see Section “PLLs and clock generation”. TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION SAB9075H QFP100 (1) plastic quad ﬂat package; 100 leads (lead length 1.95 mm); body 14× 20 × 2.8 mm SOT317-2 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDD supply voltage all positive supply pins 4.5 5.0 5.5 V Itot total supply current note 1 tbf 220 tbf mA fsys system frequency note 2 − 27 30 MHz floop loop bandwidth frequency 4 −− kHz tjitter short term stability time jitter during 1 line (64µs) −− 4n s ς damping factor − 0.7 −−

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... BLOCK DIAGRAM dbook, full pagewidth MBE084 D/A CONVERTER AND BUFFER 18 DY

14 DU16 DV

19 DAIbias13 DAV refTU15 DAV refTV17 DAV refTY

27 29,31,35,33 26,25,30,28 48 to 56 AD0 to 8DAI0 to 7DAO0 to 7 SC 47 45 44 32 36,39,40,38 41,46,37,34 DT WE CAS RAS 72 73 9 8 MV DDD MV SSD SV DDD SV SSD 82 81 89 90 SAV DDA SAV SSA SAV DDD SAV SSD 99 100 92 91 MAV DDA MAV SSA MAV DDD MAV SSD MEMORY CONTROL

24 DBF

93MAI bias 97MAV refT 95MAV refB MU 83SY 85SV 88SAI bias 86SAV refT 84SAV refB SU 69SAT 67MMUTE 68SMUTE HUE CLAMP AND A/D CONVERTER ACQUISITION MAIN CLAMP AND A/D CONVERTER ACQUISITION SUB HUE AND SAT D/A CONVERTERS VDD 22 42 43 DISPLAY DISPLAY TIMING CONTROL AND PLL BLOCK

65 SCL66 SDA

63 POR64 A0

SV sync SPV DDDV DDD V SSS 71 23 74 SPV SSA SPV DDA SH sync SPV SSD 76 80 SPIbias MH sync MPI bias MPV SSD MPV DDD 3457 MPV SSA MPV DDA I C-BUS2 I C2 Fig.1 Block diagram.

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H PINNING SYMBOL PIN I/O TYPE DESCRIPTION MPV DDA 1 I/O E030 analog positive power supply for PLL main-channel MPV SSA 2 I/O E009 analog negative power supply for PLL main-channel MH sync 3 I E027 horizontal synchronization for main-channel MPIbias 4 I E027 analog bias reference current for PLL main-channel MPV SSD 5 I/O E009 digital negative power supply for PLL main-channel MTCLK 6 I HPP01 test clock for main-channel MPV DDD 7 I/O E030 digital positive power supply for PLL main-channel MV DDD 8 I/O E030 digital positive power supply for main-channel core MV SSD 9 I/O E009 digital negative power supply for main-channel core DAV DDD 10 I/O E030 digital positive power supply for DACs DAV SSD 11 I/O E009 digital negative power supply for DACs n.c. 12 −− not connected DAV refTU 13 I/O E027 analog reference voltage for top U DAC DU 14 O E027 analog U output DAV refTV 15 I/O E027 analog reference voltage for top V DAC DV 16 O E027 analog V output DAV refTY 17 I/O E027 analog reference voltage for top Y DAC DY 18 O E027 analog Y output DAI bias 19 I E027 analog bias reference current for DACs DAV SSA 20 I/O E009 analog negative power supply for DACs DAV DDA 21 I/O E030 analog positive power supply for DACs I2CV DD 22 I/O E030 positive supply for HUE and SAT decoders MV sync 23 I HPP01 vertical synchronization for main-channel DBF 24 O SPF20 fast blanking control output signal DAI5 25 I HPP01 data bus input from memory; bit 5 DAI4 26 I HPP01 data bus input from memory; bit 4 SC 27 O OPF20 memory shift clock DAI7 28 I HPP01 data bus input from memory; bit 7 DAI0 29 I HPP01 data bus input from memory; bit 0 DAI6 30 I HPP01 data bus input from memory; bit 6 DAI1 31 I HPP01 data bus input from memory; bit 1 DT 32 O OPF20 memory data transfer; active LOW DAI3 33 I HPP01 data bus input from memory; bit 3 DAO7 34 O OPF20 data bus output to memory; bit 7 DAI2 35 I HPP01 data bus input from memory; bit 2 DAO0 36 O OPF20 data bus output to memory; bit 0 DAO6 37 O OPF20 data bus output to memory; bit 6 DAO3 38 O OPF20 data bus output to memory; bit 3 DAO1 39 O OPF20 data bus output to memory; bit 1 DAO2 40 O OPF20 data bus output to memory; bit 2

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H DAO4 41 O OPF20 data bus output to memory; bit 4 VDDD 42 I/O E030 digital positive power supply for peripherals VSSS 43 I/O E009 digital negative power supply for peripherals WE 44 O OPF20 memory write enable; active LOW CAS 45 O OPF20 memory column address strobe; active LOW DAO5 46 O OPF20 data bus output to memory; bit 5 RAS 47 O OPF20 memory row address strobe; active LOW AD0 48 O OPF20 memory address bus; bit 0 AD8 49 O OPF20 memory address bus; bit 8 AD1 50 O OPF20 memory address bus; bit 1 AD6 51 O OPF20 memory address bus; bit 6 AD2 52 O OPF20 memory address bus; bit 2 AD5 53 O OPF20 memory address bus; bit 5 AD3 54 O OPF20 memory address bus; bit 3 AD4 55 O OPF20 memory address bus; bit 4 AD7 56 O OPF20 memory address bus; bit 7 n.c. 57 −− not connected TC 58 I HPP01 test control TM0 59 I HPP01 test mode 0 TM1 60 I HPP01 test mode 1 TM2 61 I HPP01 test mode 2 n.c. 62 −− not connected POR 63 I HUP07 power-on reset A0 64 I HPF01 I 2C-bus address 0 selection pin SCL 65 I HPF01 shift clock for I 2C-bus SDA 66 I/O IOI41 shift I 2C-bus input data; acknowledge I2C-bus output data MMUTE 67 O SPF20 mute output for main-channel SMUTE 68 O SPF20 mute output for sub-channel SAT 69 O E027 analog output for SAT decoder HUE 70 O E027 analog output for HUE decoder SV sync 71 I HPP01 vertical synchronization for sub-channel SV SSD 72 I/O E009 digital negative power supply for sub-channel core SV DDD 73 I/O E030 digital positive power supply for sub-channel core SPV DDD 74 I/O E030 digital positive power supply for PLL sub-channel STCLK 75 I HPP01 test clock for sub-channel SPV SSD 76 I/O E009 digital negative power supply for PLL sub-channel SPIbias 77 I E027 analog bias reference current for PLL sub-channel SH sync 78 I E027 horizontal synchronization for sub-channel SPV SSA 79 I/O E009 analog negative power supply for PLL sub-channel SPV DDA 80 I/O E030 analog positive power supply for PLL sub-channel SAV DDD 81 I/O E030 digital positive power supply for ADC sub-channel SYMBOL PIN I/O TYPE DESCRIPTION

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Table 1 Pin type explanation SAV SSD 82 I/O E009 digital negative power supply for ADC sub-channel SU 83 I E027 analog U input for sub-channel SAV refB 84 I/O E027 analog reference voltage for bottom ADC sub-channel SV 85 I E027 analog V input for sub-channel SAV refT 86 I/O E027 analog reference voltage for top ADC sub-channel SY 87 I E027 analog Y input for sub-channel SAI bias 88 I E027 analog bias reference current for ADC sub-channel SAV SSA 89 I/O E009 analog negative power supply for ADC sub-channel SAV DDA 90 I/O E030 analog positive power supply for ADC sub-channel MAV DDA 91 I/O E030 analog positive power supply for ADC main-channel MAV SSA 92 I/O E009 analog negative power supply for ADC main-channel MAIbias 93 I E027 analog bias reference current for ADC main-channel MU 94 I E027 analog U input for main-channel MAV refB 95 I/O E027 analog reference voltage for bottom ADC main-channel MV 96 I E027 analog V input for main-channel MAV refT 97 I/O E027 analog reference voltage for top ADC main-channel MY 98 I E027 analog Y input for main-channel MAV SSD 99 I/O E009 digital negative power supply for ADC main-channel MAV DDD 100 I/O E030 digital positive power supply for ADC main-channel PIN TYPE DESCRIPTION E030 V DD pin; diode to VSS E009 V SS pin; diode to VDD E027 analog input pin; diode to VDD and VSS HPF01 digital input pin; CMOS levels, diode to VSS HPP01 digital input pin; CMOS levels, diode to VDD and VSS HUP07 digital input pin; CMOS levels with hysteresis, pull up resistor to VDD , diode to VDD and VSS IOI41 I 2C-bus pull-down output stage; CMOS input levels OPF20 digital output pin SPF20 digital output pin; slew rate controlled SYMBOL PIN I/O TYPE DESCRIPTION

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Fig.2 Pin configuration. 100 MAV SSD MAV DDD MY MAV refT MV MAV refB MU MAI bias MAV SSA MAV DDA SAV DDA SAV SSA SAI bias SY SAV refT SV SAV refB SU SAV SSD SAV DDD 80SPVDDA 79SPVSSA 78SHsync 77SPIbias 76SPVSSD

75 STCLK

67 MMUTE

66 SDA

63 POR

62n.c. 61TM2 60TM1 59TM0 58TC 57n.c. 56AD7 55AD4 54AD3 53AD5 52AD2 51AD6

50 AD1

V V DAO4 DAO2 DAO1 DAO3 DAO6 DAO0 DAI2 DAO7 DAI3 DT DAI1 SSS DDD SAB9075H MPVDDA MPVSSA MHsync MPIbias MPVSSD MTCLK MPVDDD MVDDD MVSSD DAVDDD DAVSSD DAVrefTU DU n.c. DAVrefTV DV DAVrefTY DY DAIbias DAVSSA DAVDDA I C VDD MVsync DBF DAI5 DAI4 SC DAI7 DAI0 DAI6 MBE083

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H FUNCTIONAL DESCRIPTION Acquisition area The acquisition area is in the centre of the visible screen area. Vertically 228 lines are sampled. Horizontally 672 Y-pixels are processed. The exact active processing area can be fine tuned in horizontal (2 pixels/steps, 16 steps) and vertical (1 line/step, 16 steps) direction for both main and sub-channel by the I 2C-bus (see Fig.3). The given numbers are pixel numbers at a 13.5 MHz data rate. The signals, which are dependent on the I 2C-bus registers, can also be related to the Hsync, in which event they are delayed by 68 pixels. Chrominance format The chrominance format is 4 : 1 : 1. The YUV signals are sampled at a rate of 27 MHz and then filtered and subsampled to a data rate of 13.5 MHz. It is expected that the input signals do not contain frequencies outside the video bandwidth (Y BW = 4.5 MHz; U BW and VBW = 1.125 MHz). Display area The display area is shown in Fig.4. The given numbers are pixels at a data rate of 13.5 MHz. The signals are related to the burstkey and the V sync. Dependent on the I2C-bus registers the signals can also be related to the Hsync. The internal 13.5 MHz data rate is upsampled to the double frequency (27 MHz) and then fed to the DACs. The display output can be fine positioned by the I2C-bus in 64 steps of 4 pixels in horizontal direction and 64 steps of 1 line/field in vertical direction. handbook, full pagewidth MBE085 228262.5 18 FT 18 FT 80 FT

104 FTV sync

1/1, 1/3 and 1/4 reduction 1/2 reduction 672 624 Fig.3 Acquisition area.

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Fig.4 Display area. handbook, full pagewidth MBE086 228262.5 11 FT 11 FT 36 FT V sync burstkey H sync 68 864 672

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H PIP modes The controller contains two independent acquisition-channels which provide the scaling factors to support the range of different modes. With the external memory of 2 Mbit it is possible to select between single, double and multi-PIP modes. Table 2 gives an overview of the different PIP modes. Table 2 PIP modes Notes 1. The given sub/main sizes are visible PIP sizes, a border is drawn around these PIPs and does not influence these sizes. The size of the border is 4 pixels wide and 2 lines/fields high. 2. The SAB9075H can be set in automatic mode in which the reduction factors are automatically set by the mode select and aspect ratio select bits of the I2C-bus. If the automatic mode is switched OFF the reduction factors can be set manually. This will give more flexibility to adjust the aspect ratios of incoming signals. PIP positions The positions are graphically depicted in Figs 5 to 17. MODE SUB MAIN SUB SIZE (1) MAIN SIZE(1) PIXELS REDUCTION (2) PIXELS REDUCTION (2) 4 : 3 main + 4 : 3 sub to 4 : 3 screen or 16 : 9 main + 16 : 9 sub to 16 : 9 screen

1.1 SPS 1⁄16 − 160P, 53L 1⁄4H, 1⁄4V −−

1.2 SPL 1⁄9 − 216P, 72L 1⁄3H, 1⁄3V −−

1.3 DP 1⁄4 1⁄4 304P, 108L 1⁄2H, 1⁄2V 304P, 108L 1⁄2H, 1⁄2V

1.4 MP3 3 × 1⁄16 − 160P, 53L 1⁄4H, 1⁄4V −−

1.5 MP4 3 × 1⁄16 1⁄4 160P, 53L 1⁄4H, 1⁄4V 304P, 108L 1⁄2H, 1⁄2V

1.6 MP7 7 × 1⁄16 − 160P, 53L 1⁄4H, 1⁄4V −−

1.7 MP8 7 × 1⁄16 1⁄4 160P, 53L 1⁄4H, 1⁄4V 304P, 108L 1⁄2H, 1⁄2V

1.8 MP9 8 × 1⁄9 1⁄9 216P, 72L 1⁄3H, 1⁄3V 216P, 72L 1⁄3H, 1⁄3V

16 : 9 sub + 4 : 3 main to 4 : 3 screen

2.1 SPS 1⁄16 − 216P, 53L 1⁄3H, 1⁄4V −−

2.2 SPL 1⁄9 − 304P, 72L 1⁄2H, 1⁄3V −−

4 : 3 sub + 16 : 9 main to 16 : 9 screen

3.1 SPS 1⁄16 − 160P, 72L 1⁄4H, 1⁄3V

3.2 DP 1⁄4 1⁄4 216P, 108L 1⁄3H, 1⁄2V 304P, 108L 1⁄2H, 1⁄2V

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Fig.5 Single-PIP, size1⁄16 (mode SPS). handbook, full pagewidth MBE087 228 11 FT

36 FTV sync

S 288 Fig.6 Single-PIP, size1⁄9 (mode SPL). handbook, full pagewidth MBE088 228 11 FT S 176

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Fig.7 Double-PIP, size1⁄16 (mode DP). handbook, full pagewidth MBE089 228 11 FT Fig.8 Multi PIP, 3× sub 1⁄16 (mode MP3). handbook, full pagewidth MBE090 228 11 FT

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Fig.9 Multi-PIP, 3× sub 1⁄16, 1× main 1⁄4 (mode MP4). handbook, full pagewidth MBE091 228 11 FT M 112 Fig.10 Multi-PIP, 3× sub 1⁄16, 1× main 1⁄4 (mode MP4, Right). handbook, full pagewidth MBE092 228 11 FT M

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Fig.11 Multi-PIP, 7× sub 1⁄16, main life (mode MP7). handbook, full pagewidth MBE093 228 11 FT

57 C3 C4 C5 C6

Fig.12 Multi-PIP, 7× sub 1⁄16, 1× main 1⁄4 (mode MP8). handbook, full pagewidth MBE094 228 11 FT

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Fig.13 Multi-PIP, 8× sub 1⁄9, 1× main 1⁄9 (mode MP9). handbook, full pagewidth MBE095 228 11 FT M 224 Fig.14 Single-PIP, 4 : 3 sub to 16 : 9 screen (mode SPS). handbook, full pagewidth MBE097 228 11 FT S 288

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Fig.15 Single-PIP, 16 : 9 sub to 4 : 3 screen (mode SPS). handbook, full pagewidth MBE096 228 11 FT S 176 Fig.16 Single-PIP, 16 : 9 sub to 4 : 3 screen (mode SPL). handbook, full pagewidth MBE098 228 11 FT S

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Fig.17 Factory mode. handbook, full pagewidth MBE099 238 11 FT

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H I2C-bus The I2C-bus provides bi-directional 2-line communication between different ICs. The SDA line is the Serial Data line and the SCL serves as Serial Clock Line. Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. The SAB9075H has the I 2C-bus addresses 2C and 2E, switchable by the pin A0. Valid subaddresses are 00H to 0FH. I 2C-bus control is in accordance with the I2C-bus protocol. First a start sequence must be put on the I2C-bus, then the I2C-bus address 2C or 2E, followed by a subaddress 00 to 0F. After this sequence, the data of the subaddress must be sent. An auto-increment function then gives the option ‘send data’ of the incremented subaddresses until a stop sequence has been given. Table 3 Overview of I 2C-bus addresses (note 1) Notes 1. Table 3 gives an overview of the I2C-bus addresses. They will be explained in more detail in the following pages. 2. Some address spaces are unused but already implemented for future functionality. Data Bytes SA BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

00 PIPON MANRED MASPECT SASPECT MODE3 MODE2 MODE1 MODE0

01 HPOS VPOS MFREEZE SFREEZE note 2 BCOLPOL MVFILT SVFILT

02 note 2 note 2 DHFP5 DHFP4 DHFP3 DHFP2 DHFP1 DHFP0 03 note 2 note 2 DVFP5 DVFP4 DVFP3 DVFP2 DVFP1 DVFP0

04 MREDH1 MREDH0 MREDV1 MREDV0 SREDH1 SREDH0 SREDV1 SREDV0

05 note 2 CBSEL2 CBSEL1 CBSEL0 note 2 SLSEL2 SLSEL1 SLSEL0 06 note 2 MBON MBBRT1 MBBRT0 note 2 MBCOL2 MBCOL1 MBCOL0 07 note 2 SBON SBBRT1 SBBRT0 note 2 SBCOL2 SBCOL1 SBCOL0 08 note 2 CBON CBBRT1 CBBRT0 note 2 CBCOL2 CBCOL1 CBCOL0

09 FACMODE BGON BGBRT1 BGBRT0 note 2 BGCOL2 BGCOL1 BGCOL0

0A MCOLPOL MVSPOL MHSYNC MFPOL SCOLPOL SVSPOL SHSYNC SFPOL 0B MAAHFP3 MAAHFP3 MAAHFP3 MAAHFP3 MAAVFP3 MAAVFP3 MAAVFP3 MAAVFP3 0C SAAHFP3 SAAHFP3 SAAHFP3 SAAHFP3 SAAVFP3 SAAVFP3 SAAVFP3 SAAVFP3 0D note 2 note 2 HUE5 HUE4 HUE3 HUE2 HUE1 HUE0 0E note 2 note 2 SAT5 SAT4 SAT3 SAT2 SAT1 SAT0 0F MMUTE SMUTE note 2 note 2 note 2 note 2 note 2 note 2

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Table 4 PIP mode control (note 1) Notes 1. Table 4 gives an overview of the possible PIP modes and how to set them via the I2C-bus. 2. The columns main and sub-reduction indicate how the PIP pictures appear on the screen. 3. The column mode corresponds to the lower 4 bits of I 2C-bus Register 0. 4. The main and sub-aspect ratios correspond to the bits 5 and 6 of I2C-bus Register 0. PIP MODE ASPECT RATIO MAIN-REDUCTION (2) SUB-REDUCTION (2) NAME MODE (3) MAIN (4) SUB (4) HOR VER HOR VER SPS 0000 0 0 −− 1⁄4 1⁄4 SPS 0000 0 1 −− 1⁄3 1⁄4 SPS 0000 1 0 −− 1⁄4 1⁄3 SPS 0000 1 1 −− 1⁄4 1⁄4 SPL 0001 0 0 −− 1⁄3 1⁄3 SPL 0001 0 1 −− 1⁄2 1⁄3 SPL 0001 1 X −− 1⁄3 1⁄3 DP 1010 0 X 1⁄2 1⁄2 1⁄2 1⁄2 DP 1010 1 0 1⁄2 1⁄2 1⁄3 1⁄2 DP 1010 1 1 1⁄2 1⁄2 1⁄2 1⁄2 MP3 0110 X X −− 1⁄4 1⁄4 MP4 1110 X X 1⁄2 1⁄2 1⁄4 1⁄4 MP7 0100 X X −− 1⁄4 1⁄4 MP8 1100 X X 1⁄2 1⁄2 1⁄4 1⁄4 MP9 1001 X X 1⁄3 1⁄3 1⁄3 1⁄3

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Table 5 Register 0; PIP mode control register Notes 1. With PIPON in OFF mode the fast blanking signal is made inactive. All other functions will operate as if the circuit were in operational mode. 2. With MANRED set to logic 0 the reduction factors will be set automatically, dependent on the PIP mode and the aspect ratio bits of main and sub (bits 5 and 4). Table 4 indicates which bits should be set to obtain a certain PIP mode. 3. With MANRED set to logic 1 the calculation of the reduction factors is not carried out and should be set by Register 4 (see Table 9). Only combinations with MANRED set to logic 0 are guaranteed. 4. MASPECT and SASPECT are used in automatic mode (MANRED) to indicate the type of input signals, together with MODE the PIP mode can be set (see Table 4). In manual mode these bits are ignored. 5. The MODE bits set the PIP mode. For the multi-PIP modes the frozen PIPs are set to the 30% grey colour. Once a PIP has been made live it will always display the last video data. Table 6 Register 1; general control register Notes 1. HPOS and VPOS determine the general location of the sub-PIP on the screen. HPOS only operates in modes SPS, SPL, DP, MP3 and MP4. VPOS only operates in modes SPS and SPL. The default location of the sub-pictures will be left top. 2. MFREEZE will freeze the main-picture, and SFREEZE will freeze the sub-picture selected by the live select bits as in Register 8 (see Table 13). 3. BCOLPOL can invert the border polarity of U and V. 4. MVFILT and SVFILT set the type of vertical filtering for the main and sub-channel. Mode 1 means that diagonal lines are linearized, in Mode 0 this option is switched OFF. This filtering mode only operates with vertical reduction factors 1⁄3 and1⁄4. BIT MODE RESULT

7 PIPON logic 0 = PIP function is OFF (1); logic 1 = PIP function is ON

6 MANRED logic 0 = automatic reduction factors (2); logic 1 = manual reduction factors(3)

5 MASPECT (4) main-aspect ratio; 0 = 4 : 3; 1 = 16 : 9

4 SASPECT (4) sub-aspect ratio; 0 = 4 : 3; 1 = 16 : 9

3 MODE(3) (5) PIP mode

2 MODE(2) (5) PIP mode

1 MODE(1) (5) PIP mode

0 MODE(0) (5) PIP mode

7 HPOS (1) logic 0 = left; logic 1 = right

6 VPOS (1) logic 0 = top; logic 1 = bottom

5 MFREEZE (2) logic 0 = main-freeze is OFF; logic 1 = main-freeze is ON

4 SFREEZE (2) logic 0 = sub-freeze is OFF; logic 1 = sub-freeze is ON

3 − not used

2 BCOLPOL (3) border UV polarity; logic 0 = +(B−Y), +(R−Y); logic 1 =−(B−Y),−(R−Y)

1 MVFILT (4) main-vertical ﬁlter mode; logic 0 = Mode 0; logic 1 = Mode 1

0 SVFILT (4) sub-vertical ﬁlter mode; logic 0 = Mode 0; logic 1 = Mode 1

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Table 7 Register 2; display horizontal ﬁne position register Note 1. The display position can be set in steps of 4 pixels/lines and 1 line/field. The offsets on the display position are depicted in Fig.4. Table 8 Register 3; display vertical ﬁne position register Note 1. The display position can be set in steps of 4 pixels/lines and 1 line/field. The offsets on the display position are depicted in Fig.4. Table 9 Register 4; reduction factor register Note BIT MODE DESCRIPTION (1) 7 − not used 6 − not used

5 DHFP(5) horizontal ﬁne position (64 steps)

4 DHFP(4) horizontal ﬁne position

3 DHFP(3) horizontal ﬁne position

2 DHFP(2) horizontal ﬁne position

1 DHFP(1) horizontal ﬁne position

0 DHFP(0) horizontal ﬁne position

(1) 7 − not used 6 − not used

5 DVFP(5) vertical ﬁne position (64 steps)

4 DVFP(4) vertical ﬁne position

3 DVFP(3) vertical ﬁne position

2 DVFP(2) vertical ﬁne position

1 DVFP(1) vertical ﬁne position

0 DVFP(0) vertical ﬁne position

(1)

7 MREDH(1) main-horizontal reduction factor

6 MREDH(0) main-horizontal reduction factor

5 MREDV(1) main-vertical reduction factor

4 MREDV(0) main-vertical reduction factor

3 SREDH(1) sub-horizontal reduction factor

2 SREDH(2) sub-horizontal reduction factor

1 SREDV(1) sub-vertical reduction factor

0 SREDV(0) sub-vertical reduction factor

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Table 10Register 5; channel select register Notes 1. With CBSEL one border of the displayed sub-borders can be selected independently of the SLSEL. This only operates when the channel select-border is ON as in Register 8 (see Table 13) and when the selected channel number is displayed. 2. With SLSEL the active sub-live picture can be selected. This only operates when the SFREEZE is OFF as in Register 1 (see Table 6) and when the selected channel is displayed. BIT MODE DESCRIPTION 7 − not used

6 CBSEL(2)

(1) channel-border select (maximum 8 channels)

5 CBSEL(1) (1) channel-border select

4 CBSEL(0) (1) channel-border select

3 − not used

2 SLSEL(2) (2) sub-live select (maximum 8 channels)

1 SLSEL(1) (2) sub-live select

0 SLSEL(0) (2) sub-live select

Background and main, sub and channel-border colour and brightness handling Registers 6 to 9 (see Tables 11 to 14) handle background and main, sub and channel-border colour and brightness. The borders and background can be set ON and OFF. Background, main and sub-borders are black when they are OFF. The channel-border gets the current sub-border colour when it is switched OFF. The brightness can be set in 4 steps (30%, 50%, 70% and 100%). Eight different colours can be set in accordance with Table 15. Table 11Register 6; main-border control register BIT MODE DESCRIPTION 7 − not used

6 MB0N logi c0=M Bi s OFF; logic 1 =MB is ON

5 MBBRT(1) main-border brightness (4 steps)

4 MBBRT(0) main-border brightness

3 − not used

2 MBCOL(2) main-border colour (8 colours)

1 MBCOL(1) main-border colour

0 MBCOL(0) main-border colour

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Table 12Register 7; sub-border control register Table 13Register 8; channel-border control register Table 14Register 9; background control register Note 1. The FACMODE bit controls the factory mode which shows an enlarged background colour as depicted in Fig.17 (BGON must be set). BIT MODE DESCRIPTION 7 − not used

6 SBON logi c0=S Bi sOFF; logic1=S Bi sO N

5 SBBRT(1) sub-border brightness (4 steps)

4 SBBRT(0) sub-border brightness

3 − not used

2 SBCOL(2) sub-border colour (8 colours)

1 SBCOL(1) sub-border colour

0 SBCOL(0) sub-border colour

7 − not used

6 CBON logi c0=C Bi sOFF; logic1=C Bi sO N

5 CBBRT(1) channel-border brightness (4 steps)

4 CBBRT(0) channel-border brightness

3 − not used

2 CBCOL(2) channel-border colour (8 colours)

1 CBCOL(1) channel-border colour

0 CBCOL(0) channel-border colour

7 FACMODE

(1) logic0=F Mi s OFF; logic1=F Mi sO N

6 BGON logi c0=B Gi s OFF; logic1=B Gi sO N

5 BGBRT(1) background brightness (4 steps)

4 BGBRT(0) background brightness

3 − not used

2 BGCOL(2) background colour (8 colours)

1 BGCOL(1) background colour

0 BGCOL(0) background colour

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Table 15Colour table Note 1. The values in are the I2C-bus register values for the Colour Control Registers 6 to 9 (see Tables 11 to 14). The values are hexadecimal values of which the left part indicates the brightness and the right part the colour value. Table 16 Border display Notes 1. The BGON I2C-bus bit controls the display area outside the PIP and border area, set to ON means that the background gets the BGCOL colour value. 2. The main and sub-border displays are dependent on the I2C-bus switches. 3. ‘Live BG’ means that the original picture is shown. COLOUR TYPE BRIGHTNESS (%) (1) 0 1 03 05 06 07 08 0 1 0 0 Black/white 40H 50H 60H 70H 47H 57H 67H 77H Blue −− 41H 51H − 61H − 71H Red −− 42H 52H − 62H − 72H Magenta −− 43H 53H − 63H − 73H Green −− 44H 54H − 64H − 74H Cyan −− 45H 55H − 65H − 75H Yellow −− 46H 56H − 66H − 76H PIP MODES MBON BGON (1) SBON CBON MAIN- BORDER DISPLAY (2) BACK- GROUND DISPLAY SUB- BORDER DISPLAY (2) CHANNEL BORDER DISPLAY MP4 MP8 MP9 FFS OFF OFF −− live BG (3) live BG(3) −− OFF ON −− BGCOL BGCOL −− ON OFF −− MBCOL live BG (3) −− ON ON −− MBCOL BGCOL −− SPS SPL DP OFF OFF OFF − live BG(3) live BG(3) live BG(3) − OFF ON OFF − BGCOL BGCOL BGCOL − ON OFF ON − MBCOL live BG (3) SBCOL − ON ON ON − MBCOL BGCOL SBCOL − MP3 MP4 MP7 MP8 MP9 − OFF OFF ON − live BG (3) live BG(3) CBCOL − ON OFF ON − BGCOL BGCOL CBCOL − OFF ON ON − live BG(3) SBCOL CBCOL − ON ON ON − BGCOL SBCOL CBCOL

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Table 17Register A; decoder format register Notes 1. MCOLPOL and SCOPOL invert the UV video data. 2. MVSPOL and SVSPOL determine the active edge of the V sync. If VSPOL is logic 0, the positive edge of the Vsync will be taken; if VSPOL is logic 1, the negative edge of the Vsync will be taken. 3. MHSYNC and SHSYNC determine whether the Hsync signal or the burstkey is used as internal horizontal synchronization. BIT MODE RESULT

7 MCOLPOL (1) main-UV polarity; logic 0 = original; logic 1 = inverted

6 MVSPOL (2) main-vertical sync polarity; logic 0 = positive pulse; logic 1 = negative pulse

5 MHSYNC (3) main-horizontal sync selection; logic 0 = burst edge; logic 1 = H− sync

4 MFPOL main-ﬁeld polarity; inverts ﬁeld identiﬁcation window

3 SCOLPOL

(1) sub-UV polarity; logic 0 = original; logic 1 = inverted

2 SVSPOL (2) sub-vertical sync polarity; logic 0 = positive pulse; logic 1 = negative pulse

1 SHSYNC (3) sub-horizontal sync selection; logic 0 = burst edge; logic 1 = H− sync

0 SFPOL sub-ﬁeld polarity, inverts ﬁeld identiﬁcation window

The exact timing of the Vsync in relation to the Hsync reference pulse is depicted in Fig.18. A field identification window determines whether a Vsync is being handled as a 1st field or a 2nd field. This field identification window can be inverted by the FPOL bit. If FPOL is logic 0 and an active edge of the V sync occurs when the F-ID signal is logic 0, it will be regarded as the 1st field. If FPOL is logic 0 and an active edge of the V sync occurs when the F-ID signal is logic 1, it will be regarded as the 2nd field. If FPOL is logic 1 the 1st and 2nd field IDs are changed over. Fig.18 Vsync timing and field identification. handbook, full pagewidth MBE100 43238943 1st field 2nd field field ID (internal) (number of pixels) H (external)sync V (external)sync V (external)sync

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Table 18Register B; main-acquisition area ﬁne position Notes 1. The acquisition area can be adjusted in 16 steps of 2 pixels horizontally and 1 line/field vertically. 2. With MAAVFP a complete field must have been processed before the next V sync occurs. This is relevant for non-standard signals. Table 19Register C; sub-acquisition area ﬁne position Notes 1. The acquisition area can be adjusted in 16 steps of 2 pixels horizontally and 1 line/field vertically. 2. With SAAVFP a complete field must have been processed before the next V sync occurs. This is relevant for non-standard signals. BIT MODE DESCRIPTION (1)

7 MAAHFP(3) main-acquisition area horizontal ﬁne position

6 MAAHFP(2) main-acquisition area horizontal ﬁne position

5 MAAHFP(1) main-acquisition area horizontal ﬁne position

4 MAAHFP(0) main-acquisition area horizontal ﬁne position

3 MAAVFP(3)

(2) main-acquisition area vertical ﬁne position

2 MAAVFP(2) (2) main-acquisition area vertical ﬁne position

1 MAAVFP(1) (2) main-acquisition area vertical ﬁne position

0 MAAVFP(0) (2) main-acquisition area vertical ﬁne position

BIT MODE DESCRIPTION (1)

7 SAAHFP(3) sub-acquisition area horizontal ﬁne position

6 SAAHFP(2) sub-acquisition area horizontal ﬁne position

5 SAAHFP(1) sub-acquisition area horizontal ﬁne position

4 SAAHFP(0) sub-acquisition area horizontal ﬁne position

3 SAAVFP(3)

(2) sub-acquisition area vertical ﬁne position

2 SAAVFP(2) (2) sub-acquisition area vertical ﬁne position

1 SAAVFP(1) (2) sub-acquisition area vertical ﬁne position

0 SAAVFP(0) (2) sub-acquisition area vertical ﬁne position

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Auxiliary registers The Auxiliary Registers D to F (see Tables 20 to 22) are implemented to generate I2C-bus controlled signals for circuits which do not have an on-board I2C-bus. Table 20Register D; Auxiliary Control Register 1 Table 21Register E; Auxiliary Control Register 2 Table 22Register F; Auxiliary Control Register 3 BIT MODE DESCRIPTION 7 − not used 6 − not used

5 HUE(5) hue control (output pin HUE)

4 HUE(4) hue control

3 HUE(3) hue control

2 HUE(2) hue control

1 HUE(1) hue control

0 HUE(0) hue control

7 − not used 6 − not used

5 SAT(5) saturation control (output pin SAT)

4 SAT(4) saturation control

3 SAT(3) saturation control

2 SAT(2) saturation control

1 SAT(1) saturation control

0 SAT(0) saturation control

7 MMUTE data bit directly to output pin MMUTE

6 SMUTE data bit directly to output pin SMUTE

5 − not used 4 − not used 3 − not used 2 − not used 1 − not used 0 − not used

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H External memory For the external memory two VDRAMS of type Mitsubishi M5442256 are used. They have a storage capacity of 262144 words of 4-bit each and will be used in parallel. An overview of the timing to the VDRAM is depicted in Fig.19. Three different timing modes are shown. If the SAB9075 is not in one of these three modes, it is in idle mode in which all the control signals are HIGH. An idle mode takes at least 4 clock periods. Switching from one mode to another is always carried out via this idle mode. The clock signal shown is an internal clock derived from the PLLs and is approximately 27 MHz. Main and sub-ADCs Both main and sub-channels convert the analog input signals to digital signals by three ADCs for each channel. The input levels of the ADCs are equal and can set by the MAV refT, SAVrefT, MAVrefB, and SAVrefBpins.The reference levels are made internally by a resistor network which divides the analog V DD to a default set of preferred signal levels of 1.5 V. If the application requires a different set of levels the internal resistors can be shunted. External capacitors are required to filter AC components on the reference levels. The resolution of the ADCs is 6-bit and the sampling is carried out at the system frequency of 27 MHz. The bias current I bias is made internally but can be increased or decreased. The inputs should be AC-coupled and an internal clamping circuit will clamp the input to MAVrefB and SAVrefB for the luminance channels and to for the chrominance channels. The clamping starts at the active edge of the burstkey. For more information see chapter “Test and application information”. MAV refT MAV refB+ SAV refT SAV refB+ Output DACs The digital processed signals are converted to analog signals by means of three DACs. The output voltages of these DACs are default set by the DAV refTU, DAVrefTV and DAV refTYpins for the TOP-levels. Default signal levels are 1.5 V. The output buffer after each DAC is a PMOS source follower. For more information see chapter “Test and application information”. HUE and SAT DACs The HUE and SAT DACs are resistor DACs based on a R2R network. They have a direct control from their I 2C-bus register and therefore their sample frequency is limited by the I 2C-bus frequency. The output voltage is linear with the I2CV DD . Therefore the VDD of this block is a separate pin. PLLs and clock generation The SAB9075H has two PLLs on-board, one for the sub- channel and one for the main-channel and the display part. The PLLs lock to the input signals MH sync and SHsync. The internal clock frequency is 1 728 times higher which is approximately 27 MHz in a standard NTSC system. The positive edges of the H sync signals are the driving timing points. For good short term stability they have to be noise/jitter free.

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Fig.19 VDRAM timing. handbook, full pagewidth MBE101 AD0 to AD8 ROW COLUMN COLUMN COLUMN COLUMN COLUMN write cycle (SUB or MAIN) WE DAI0 to DAI7 CAS RAS CLOCK AD0 to AD8 ROW COLUMN read cycle WE DT CAS RAS CLOCK CAS RAS CLOCK refresh cycle SC DAO0 to DAO7 SC cycles

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134) THERMAL CHARACTERISTICS QUALITY SPECIFICATION In accordance with SNW-FQ-611, Part E, dated 14 December 1992. SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage −0.5 +6.5 V ΔVDD supply voltage variation − 0.2 V Tstg storage temperature −25 +150 °C Tamb operating ambient temperature 0 70 °C Vesd electrostatic discharge handling −− V Ptot total power dissipation − 1.5 W SYMBOL PARAMETER VALUE UNIT R thj-a thermal resistance from junction to ambient in free air 38 K/W

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H CHARACTERISTICS VDD = 5.0 V; Tamb =2 5°C; unless otherwise speciﬁed. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD positive supply voltage 4.5 5.0 5.5 V VSS negative supply voltage − 0 − V ΔVDD maximum voltage difference between all positive supply pins − 0 100 mV ΔVSS maximum voltage difference between all negative supply pins − 0 100 mV IDDQ quiescent current digital positive supply pins note 1 − 2 tbf µA MPIV DDA supply current PLL main − 2.5 tbf mA SPIVDDA supply current PLL sub − 2.5 tbf mA MAIV DDA supply current 3 main-ADCs − 36 tbf mA SAIVDDA supply current 3 sub-ADCs − 36 tbf mA DIVDDA supply current 3 display DACs − 18 tbf mA I2CV DD supply current HUE and SAT DACs note 2 − 2.5 5 mA Itot total supply current tbf 220 tbf mA Converter and clamping AV refT top reference voltage note 3 1.0 1.9 2.0 V AV refB bottom reference voltage note 3 0 0.4 1.0 V Rinref input resistance VrefT to VrefB note 3; 1 ADC tbf 860 tbf Ω VI DC input voltage V refB − VrefT V Vi AC input voltage (peak-to-peak value) 1.0 1.5 − V R i input resistance clamping OFF 1 −− M Ω R iY input resistance for Y channel clamping ON − 200 −Ω R iV input resistance for V channel clamping ON − 800 −Ω R iU input resistance for U channel clamping ON − 800 −Ω C i input capacitance − 15 − pF Res resolution − 6 − bit fs sample frequency rate note 4 − 27 − MHz DNL differential non-linearity −1.0 − +1.0 LSB INL integral non-linearity −1.0 − +1.0 LSB Vos input offset voltage −1.0 − +1.0 LSB α cs channel separation within channel tbf 40 − dB to other channel tbf 40 − dB PSRR power supply rejection ratio tbf 40 − dB

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Notes 1. Digital clocks are silent and analog bias current is zero. 2. The HUE and SAT DACs are based on a R2R ladder network as describe in the section “HUE and SAT DACs”. The maximum output sample frequency is determined by the I 2C-bus. 3. The input configuration of the ADCs is depicted in Fig.20. The minimum difference AVrefT− AV refB should be larger than 1.0 V. The reference voltages can be calculated as follows: 4. The internal system frequencies are 1728 times the input frequency. For more detailed information about the clock generation see section “PLLs and clock generation”. TD clamp delay burstkey edge to clamping start − 0 −µ s Tclamp duration of clamping − 2.33 −µ s VclampY clamping voltage level Y AD out=0 H − Vs − V VclampU clamping voltage level U AD out= 20H − 0.5 VT+B − V VclampV clamping voltage level V AD out= 20H − 0.5 VT+B − V Digital-to-analog converter VrefT top reference voltage (Y, U and V) note 3 1.0 1.5 2.0 V Rinref input resistance VrefTto VrefB note 3; 1 DAC tbf 1.0 tbf k Ω Vo(max) maximum output voltage V refB − VrefT V R L(min) minimum load resistance 10 −− kΩ C L(max) maximum load capacitance − 50 − pF Res resolution − 7 − bit fs sample frequency rate note 4 − 27 − MHz DNL differential non-linearity −0.5 − +0.5 LSB INL integral non-linearity −1.0 − +1.0 LSB α cs channel separation tbf 40 − dB PSRR power supply rejection ratio tbf 40 − dB Digital-to-analog converter HUE/SAT Vo output voltage V SS − VDD V R L(min) minimum load resistance note 2 100 −− kΩ C L(max) maximum load capacitance − 50 − pF Res resolution − 6 − bit DNL differential non-linearity −1.0 − +1.0 LSB INL integral non-linearity −1.0 − +1.0 LSB PSRR power supply rejection ratio note 2 − 0 − dB PLL and clock generation;note 4 VTOP TOP-level input voltage 2.5 − PV DD V VLOW LOW-level input voltage −− 0.5 V Vslice slicing voltage level below TOP 0.45 1.0 2.0 V fPLL input frequency 14750 15734 17250 Hz SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V refT AV DD 1.9 × V= V refB AV DD 0.4 × V=

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H DC CHARACTERISTICS FOR DIGITAL PART All VDD pins = 4.5 to 5.5 V; Tamb = −20 to +75°C; unless otherwise speciﬁed. AC CHARACTERISTICS FOR DIGITAL PART VDD = 4.5 5.5 V; Tamb = −20 to +75°C; unless otherwise speciﬁed. Note 1. The internal system frequencies are 1728 times the input frequency. For more detailed information about the clock generation see section “PLLs and clock generation”. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VIH HIGH level input voltage HPF01 70 −− %V DD HPP01 70 −− %V DD HUP07 80 −− %V DD VIL LOW level input voltage IOI41 70 −− %V DD HPF01 −− 30 %V DD HPP01 −− 30 %V DD HUP07 −− 20 %V DD IOI41 −− 30 %V DD Vhys hysteresis voltage HUP07 − 33 − %V DD VOH HIGH level output voltage OPF20; IOL = −2 mA; VDD = 4.5 V 4.4 −− V SPF20; IOL = −2 mA; VDD = 4.5 V 4.4 −− V VOL LOW level output voltage IOI41; IOL = +2 mA; VDD = 4.5 V −− 0.15 V OPF20; IOL = +2 mA; VDD = 4.5 V −− 0.15 V SPF20; IOL = +2 mA; VDD = 4.5 V −− 0.15 V ILI input leakage current HPF01 − 0.1 1 µA HPP01 − 0.1 1 µA ILOZ three-state output leakage current IOI41; VDD = 5.5 V − 0.2 5.0 µA R pu internal pull up resistor HUP07 17 − 134 k Ω SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT fsys system frequency note 1 − 27 30 MHz tr rise time V DD = 4.5 V − 62 5 n s tf fall time V DD = 4.5 V − 62 5 n s

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H TEST AND APPLICATION INFORMATION Fig.20 shows how the ADCs and the DACs can be connected in the application. The generation of the reference voltages is carried out internally and they have to be externally decoupled for AC signals. For all ADCs and DACs the internal resistor division is such that a maximum signal voltage level of 1.5 V is obtained. For the ADCs there is a DC offset voltage of 0.4 V. A modification of these reference voltages can be achieved by external shunting. The ADC reference voltages are the same for all Y/U/V channels which means that their input levels need to be the same. The DAC voltage references can be set separately for Y/U/V channels. These reference voltages can be modified by shunting. The output buffers of the DACS are PMOS source followers with a minimum output load of 10 kΩ . Fig.20 Analog application diagram ADCs and DACs. handbook, full pagewidth VIDEO SIGNAL PROCESSING ADCMY MU MV SY SU SV ADC ADC DAC DY DU DV DAC DAC ADC ADC ADC MAV DDA SAV DDA MAV SSA SAV SSA MAV refT SAV refT R top MAV refB DAV SSA DAV DDA DAV refTY DAV refTU DAV refTV SAV refB R top 3R top R bottom R bottom MGC001

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H Fig.21 Application diagram. handbook, full pagewidth V DDDSAI bias SAV DDA I CV DD SAV SSA SAV refT SAV refB SV sync MH sync MV sync MAV refB MAV refT MAV SSA MAV DDA MAI bias SH SY SU MY MU MV SV Y U V HUE HUE SMUTE MMUTE SAT HOUT VOUT SAT Y U V HUE HOUT VOUT SAT sync V SSS SV DDD SV SSD MV DDD MV SSD AD0 to AD8 DAO4 to DAO7 DAO0 to DAO3 DAI4 to DAI7 DAI0 to DAI3 SC TC TM0 POR SCL SDA TM1 TM2 STCLK MTCLK CAS RAS WE DT DAIbias DAV DDA DAV SSA DAV refTY DAV refTU DAV DBF DY DU DV refTV DAV DDD DAV SSD MAV DDD MPI bias MPV DDA MPV SSA MPV DDD MPV SSD SPV DDA SPV SSA SPV DDD SPV SSD SPIbias SAV DDD SAV SSD MAV SSD main-channel mute output sub-channel mute output SAB9075H TDA8315T CVBS/Y CVBS/Y TDA8315T TMS44C250 TMS44C250 CVBS/Y sub-channel input CVBS/Y main-channel input fast blanking control output analog Y output analog U output analog V output SCL SDA

0 V or 5 V

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H PACKAGE OUTLINE UNIT A 1 A 2 A 3 bp cE (1) eH E LL p Zywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 0.25 0.05 2.90 2.65 0.25 0.40 0.25 0.25 0.14 14.1 13.9 0.65 18.2 17.6 1.0 0.6 o o0.15 0.10.21.95 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 SOT317-2 95-02-04 97-08-01 D (1) (1)(1) 20.1 19.9 H D 24.2 23.6 EZ 0.8 0.4 D e θ E A 1 A Lp detail X L (A )3 B c bp EH A 2 D Z D A Z E e v M A 100 80 51 pin 1 index X y bp DH v M B w M w M 0 5 10 mm scale QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mmSOT317-2 A max. 3.20

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H SOLDERING Plastic quad ﬂat-packs BYW A V E During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260°C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150°C within 6 s. Typical dwell time is 4 s at 250°C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. B Y SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250°C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45°C. R EPAIRING SOLDERED JOINTS (BY HAND -HELD SOLDERING IRON OR PULSE -HEATED SOLDER TOOL ) Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 °C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320°C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement. DEFINITIONS LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. Data sheet status Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development. Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later. Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

Philips Semiconductors Preliminary speciﬁcation Picture-in-Picture (PIP) controller for NTSC SAB9075H NOTES

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Product Information

SAB9075H specifications and overview.

Summary

Picture-in-Picture PIP controller for NTSC February 1995

Description

Picture-in-Picture PIP controller for NTSC February 1995

Source title SAB9075H Datasheet(PDF) - NXP Semiconductors

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