SAB3035 PHILIPS | Alldatasheet
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Features
© Combined analogue and digital circuitry minimizes the number of additional interfacing components required » Frequency measurement with resolution of 50 kHz » Selectable prescaler divisor of 64 or 256 » 32 V tuning voltage amplifier » 4high-current outputs for direct band selection ‘ ) 8 static digital to analogue converters (DACs) for control of analogue functions » Four general purpose input/output (1/O) ports ¢ » Tuning with control of speed and direction ° » Tuning with or without a.f.c. ' Single-pin, 4 MHz on-chip oscillator ' 1? bus slave transceiver WICK REFERENCE DATA upply voltages (pin 16) Vp4 typ. 12 V (pin 22) Vp2 typ. 13 V (pin 17) Vp3 typ. 32 V upply currents (no outputs loaded) ! (pin 16) Ipq typ. 32 mA (pin 22) Ip2 typ. 0,1 mA (pin 17) Ip3 typ. “0,6 mA Total power dissipation Prot typ. 400 mW Operating ambient temperature range Tamb ~—20 to +70 °C eee PACKAGE OUTLINE 28-lead DIL; plastic (SOT 117). | | October 1983 1347
[ I PRESCALER os] Ve1 GND O66 FDIV Ver | 4 23 22.17 oO POWER -DOWN REFERENCE DETECTOR OSCILLATOR | 20 PORT 1 SAB3035 CONTROL TUNER WRITE CIRCUIT son (a ran weet time (am 3 eiT REFERENCE GATE 15-BIT COUNTER FREQUENCY BUFFER Apc 15-BIT le | (P20) {F120} FREQUENCY COUNTER (| sian Is | (P21) (P21) ] Pi2z F227, pov FLOeR OF [ro | wee peed LEOV 5 ELOeK | ELI GED FIST TUNING CONTROL CIRCUIT CONTROL CIRCUIT DivisoR 3-BIT SELECTOR ac 15 | TUN TURN 12-BIT CHARGE PUMP TUNING TUNING COUNTER VOLTAGE cnt AMPLIFIER c+] AFC. ul c- AMPLIFIER AFCS Cos CORRECTION-| IN~ BAND CIRCUIT DACcO act Dace acs DAC4 DACs DAC oac7 25 26 27 28 1 2 3 4 3290132 Fig. 1 Block diagram.
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Computer interface for tuning and control (CITAC) SAB3035 PINNING
1 DAC4 |
2 DACS outputs of static DACs
3 DACE |
4 DAC7
oace [7] U paca 5 SDA serial data line | PC bus
6 SCL serial clock line
DACS A 7 p20 | PACE pact 8 P21 general purpose vac? [4 | Aco 9 p22 | input/output ports spa [5 | [24] osc 10 P23 set [6] FOlv wT AFC# | a.f.c. inputs 12 aFc- J P20 Vp2 . oo . SAB3035 13 «TI tuning voltage amplifier inverting input ear [a | j21] P13 14 GND ground p22 [9 | P12 15 TUN tuning voltage amplifier output P23 [io] [19] p11 16 Vp +12 V supply voltage arce [11] [18] P10 17 Vpg +32 V supply for tuning voltage V amplifier fo A °3 18 P10 | ; fi3] 7 . - "Us [8] ver 19 P11 High-current band-selection output np [14] [15] Tun 20 P12 | ports 7286564.1 21 P13
22 Vp2 positive supply for high-current band-
Fi . ; 23. ~FDIV input from prescaler ig. 2 Pinning diagram. 24 OSC crystal oscillator input
25 DACO
26 DAC1 . outputs of static DACs
27 DAC2
28 DAC3
[| oe] Purchase of Philips’ 1?C components conveys a license under the | 2 Philips’ 1?C patent to use the components in the |?C-system | Ee provided the system conforms to the |?C specifications defined . BUS by Philips. October 1983 1349
The SAB3035 is a monolithic computer interface which provides tuning and control functions and operates in conjunction with a microcomputer via an |? C bus, Tuning This is performed using frequency-locked loop digital control. Data corresponding to the required tuner frequency is stored in a 15-bit frequency buffer. The actual tuner frequency, divided by a factor of 256 (or by 64) by a prescaler, is applied via a gate to a 15-bit frequency counter. This input (FDIV) is measured over a period controlled by a time reference counter and is compared with the contents of the frequency buffer. The result of the comparison is used to control the tuning voltage so that the tuner frequency equals the contents of the frequency buffer multiplied by 50 kHz within a program- mable tuning window (TUW). The system cycles over a period of 6,4 ms (or 2,56 ms), controlled by the time reference counter which is clocked by an on-chip 4 MHz reference oscillator. Regulation of the tuning voltage is performed by a charge pump frequency-locked loop system. The charge IT flowing into the tuning voltage amplifier is controlled by the tuning counter, 3-bit DAC and the charge pump circuit. The charge IT is linear with the frequency deviation Af in steps of 50 kHz. For loop gain control, the relationship AIT/Af is orogrammable. In the normal mode (when control bits TUHNO and TUHN1 are both at logic 1, see OPERATION), the minimum charge IT at Af = 50 kHz equals 250 wA us (typical). By programming the tuning sensitivity bits (TUS), the charge IT can be doubled up to 6 times. If 2orrection-in-band (COIB) is programmed, the charge can be further doubled up to three times in ‘elation to the tuning voltage level. From this, the maximum charge IT at Af = 50 kHz equals 26 x 23 x 250 uA us (typical). The maximum tuning current | is 875 uA (typical). In the tuning-hold (TUHN) mode (TUHN is active -OW), the tuning current | is reduced and as a consequence the charge into the tuning amplifier is also educed. An in-lock situation can be detected by reading FLOCK. When the tuner oscillator frequency is within he programmable tuning window (TUW), FLOCK is set to logic 1. If the frequency is also within the »rogrammable a.f.c. hold range (AFCR), which always occurs if AFCR is wider than TUW, control bit \\FCT can be set to logic 1. When set, digital tuning will be switched off, a.f.c. will be switched on and *LOCK will stay at logic 1 as long as the oscillator frequency is within AFCR. If the frequency of the uning oscillator does not remain within AFCR, AFCT is cleared automatically and the system reverts o digital tuning. To be able to detect this situation, the occurrence of positive and negative transitions 1 the FLOCK signal can be read (FL/1N and FL/ON). AFCT can also be cleared by programming the \\FCT bit to logic 0. ‘he a.f.c. has programmable polarity and transconductance; the latter can be doubled up to 3 times, epending on the tuning voltage level if correction-in-band is used. ‘he direction of tuning is programmable by using control bits TDIRD (tuning direction down) and 'DIRU (tuning direction up). If a tuner enters a region in which oscillation stops, then, providing the prescaler remains stable, no FDIV signal is supplied to CITAC. In this situation the system will tune up, moving away from frequency lock-in. This situation is avoided by setting TDIRD which causes the system to tune down. In normal operation TDIRD must be cleared. If a tuner stops oscillating and the prescaler becomes unstable by going into self-oscillation at a very high frequency, the system will react by tuning down, moving away from frequency lock-in. To overcome this, the system can be forced to tune up at the lowest sensitivity (TUS) value, by setting TDIRU. Setting both TDIRD and TDIRU causes the digital tuning to be interrupted and a.f.c. to be switched on. The minimum tuning voltage which can be generated during digital tuning is programmable by VTMI to prevent the tuner being driven into an unspecified low tuning voltage region. 1350 October 1983 | .
Computer interface for tuning and control (CITAC) SAB3035 Control For tuner band selection there are four outputs P10 to P13 which are capable of sourcing up to 50 mA at a voltage drop of less than 600 mV with respect to the separate power supply input Vp2. For additional digital control, four open collector I/O ports P20 to P23 are provided. Ports P22 and P23 are capable of detecting positive and negative transitions in their input signals. With the aid of port P20, up to three independent module addresses can be programmed. Eight 6-bit digital-to-analogue converters DACO to DAC7 are provided for analogue control. Reset CITAC goes into the power-down-reset mode when Vp, is below 8,5 V (typical). In this mode all registers are set to a defined state. Reset can also be programmed. OPERATION Write CITAC is controlled via a bidirectional two-wire |? C bus; the |? C bus is specified in our data handbook “ICs for digital systems in radio, audio, and video equipment’. For programming, a module address, (/W bit (logic 0), an instruction byte and a data/control byte are written into CITAC in the format hown in Fig. 3. MODULE ADDRESS INSTRUCTION BYTE DATA/CONTROL BYTE BESOOCGGOHODOONCOC DDO ccccc to msb msb msb L R/W 7290129 Fig. 3 1?C bus write format. he module address bits MA1, MAO are used to give a 2-bit module address as a function of the voltage port P20 as shown in Table 1. cknowledge (A) is generated by CITAC only when a valid address is received and the device is not in e power-down-reset mode (Vp 1 > 8,5 V (typical)). able 1 Valid module addresses 0 (e) don’t care i?) 1 GND 1 0 YVp1 1 1 Vp4 October 1983 1351
OPERATION (continued) Tuning Tuning is controlled by the instruction and data/control bytes as shown in Fig. 4. INSTRUCTION BYTE DATA/CONTROL BYTE ly \\g Is \\g Ig Ip 4 lo Dy Og Ds gg D2 Dy D9 frea. 1 Fig FIZ, F121 FIO FD. F8 F7 F6 5 F4 F3 F2 FI FO TCDO oO oO 1 oO 1 oO oO 1 AFCT VTMIO AFCR1 AFCRO TUHN1 TUHNO TUWI1 TUWO TCOT oO ° 1 oO 1 tC) 1 Oo VTMI1 COIB1 COIBO AFCS1 AFCSO TUS2 TUS1 TUSO TCO2 0 Oo 1 oO 1 oO 1 1 0 oO oO oO AFCP FDIVM TDIRD TOIRU a . 7290125 Fig. 4 Tuning control format. Frequency Frequency is set when bit I7 of the instruction byte is set to logic 1; the remainder of this byte ogether with the data/control byte are loaded into the frequency buffer. The frequency to which the uner oscillator is regulated equals the decimal representation of the 15-bit word multiplied by 50 kHz. Ml frequency bits are set to logic 1 at reset. ‘uning hold ‘he TUHN bits are used to decrease the maximum tuning current and, as a consequence, the minimum harge IT (at Af = 50 kHz) into the tuning amplifier. ‘able 2 Tuning current control TUHN1 TUHNO typ. Imax typ. ITmin | tvP- AVTUNmin at CINT = 1 HF BA HA us uv 0 0 3,5* 1* 1* ie) 1 29 8 8 1 0 110 30 30 1 1 875 250 250 Values after reset. ‘uring tuning but before lock-in, the highest current value should be selected. ffter lock-in the current may be reduced to decrease the tuning voltage ripple. the lowest current value should not be used for tuning due to the input bias current of the tuning voltage amplifier (max. 5 nA). However it is good practice to program the lowest current value during tuner band switching. Tuning sensitivity To be able to program an optimum loop gain, the charge IT can be programmed by changing T using tuning sensitivity (TUS). Table 3 shows the minimum charge IT obtained by programming the TUS bits at Af = 50 kHz; TUHNO and TUHNT = logic 1.
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Computer interface for tuning and control (CITAC) SAB3035 Table 3 Minimum charge IT as a function of TUS Af = 50 kHz; TUHNO = logic 1; TUHN1 = logic 1 Tus2 Tus! TUSO typ. ITmin typ. AVTUNmin at CINT = THF mA us mV ie} 0 1 0,5 0,5 0 1 ie} 1 1 ie} 1 1 2 2 1 ie) ie) 4 4 1 ie} 1 8 8 1 1 0 16 16 * Values after reset. Correction-in-band This control is used to correct the loop gain of the tuning system to reduce in-band variations due to a non-linear voltage/frequency characteristic of the tuner. Correction-in-band (COIB) controls the time T of the charge equation IT and takes into account the tuning voltage VT yn to give charge multiplying factors as shown in Table 4. Table 4 Programming correction-in-band charge multiplying factors at typical values of VT Uy at: colBt Co1B0 <12V 12 to 18 V 18 to 24V >24Vv : 0 0 i* 1* 1* 1* 0 1 1 1 1 2 1 (e) 1 1 2 4 1 1 1 2 4 8 * Values after reset. The transconductance multiplying factor of the a.f.c. amplifier is similar when COIB is used, except for the lowest transconductance which is not affected. Tuning window Digital tuning is interrupted and FLOCK is set to logic 1 (in-lock) when the absolute deviation |Af| yetween the tuner oscillator frequency and the programmed frequency is smaller than the programmed [UW value (see Table 5). If |Af| is up to 50 KHz above the values listed in Table 5, it is possible for the Ystem to be locked depending on the phase relationship between FDIV and the reference counter. Table 5 Tuning window programming Tuw1 TUWO IAfl (kHz) tuning window (kHz) i) o* o ie} 50 100 1 150 300 * Values after reset. | October 1983 1353
OPERATION (continued) A.F.C. When AFCT is set to logic 1 it will not be cleared and the a.f.c. will remain on as. long as |Af| is less than on for values of up to 50 kHz more than the programmed value depending on the phase relationship between FDIV and the reference counter. Table 6 A.F.C. hold range programming AFCR1 AFCRO IAf| (kHz) a.f.c. hold range (kHz) o* o* 350 700 750 1500 * Values after reset. : Transconductance shown in Table 7. Table 7 Transconductance programming AFCS1 AFCSO typ. transconductance (uA/V) () 0 0,25"! ie} 1 25 1 0 50 1 1 100 Value after reset. F.C. polarity f a positive differential input voltage is applied to the (switched on) a.f.c. amplifier, the tuning voltage ‘TUN falls when the a.f.c. polarity bit AFCP is at logic 0 (value after reset). At AFCP = logic 1, ‘TUN rises. linimum tuning voltage oth minimum tuning voltage control bits, VTMI1 and VTMIO, are at logic O after reset. Further details “e given in CHARACTERISTICS. requency measuring window he frequency measuring window which is programmed must correspond with the division factor of the tescaler in use (see Table 8). Table 8 Frequency measuring window programming FDIVM prescaler division factor cycle period (ms) measuring window (ms) 0 256 6,4* 5,12* 1 64 2,56 1,28 * Values after reset. Tuning direction Both tuning direction bits, TDIRU (up) and TDIRD (down), are at logic O after reset.
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Computer interface for tuning and control (CITAC) SAB3035 Control The instruction bytes POD (port output data) and DACX (digital-to-analogue converter control) are shown in Fig. 5, together with the corresponding data/control bytes. Control is implemented as follows: P13, P12, P11, P10 Band select outputs. If a logic 1 is programmed on any of the POD bits D3 to Do, the relevant output goes HIGH. All outputs are LOW after reset. P23, P22, P21, P20 Open collector !/O ports. If a logic 0 is programmed on any of the POD bits D7 to Dg, the relevant output is forced LOW. All outputs are at logic 1 after reset (high impedance state). DACX Digital-to-analogue converters. The digital-to-analogue converter selected corresponds to the decimal equivalent of the DACX bits X2, X1, XO. The output voltage of the selected DAC is set by programming the bits AX5 to AXO; the lowest output voltage is programmed with all data AX5 to AXO at logic O, or after reset has been activated. INSTRUCTION BYTE DATA/CONTROL BYTE "7 1g '5 '4 '3 '2 4 'o 7 eS HZ QO POD 0 0 1 oO 1 Oo 0 i) P23 P22 Pai P20 P13 P12 Pq P10 DACX 0 0 1 i) Oo x2 xT xo oO 0 AXS AX4 = AX3 AX2 AX1 AXO 7290127 Fig. 5 Control programming. Read Information is read from CITAC when the R/W bit is set to logic 1. An acknowledge must be generated by the master after each data byte to allow transmission to continue. If no acknowledge is generated by the master the slave (CITAC) stops transmitting. The format of the information bytes is shown in Fig. 6. MODULE ADDRESS TUNING / RESET INFORMATION PORT INFORMATION 8) Bg Bs By Bz By By 8 ‘ MA™A SKDEDEYOCICi 11 DECI C3 SN OEDIED
7290130 R/W 4 i t MWN i i L from master
RESN | PI20 FOV Pi21 FL/ON Pi22 FL/IN PI23 FLOCK P22/0N P22/1N L. P23/0N P23/1N from CITAC from master Fig. 6 Information byte format. October 1983 1355
OPERATION (continued) Tuning/reset information bits FLOCK Set to logic 1 when the tuning oscillator frequency is within the programmed tuning window. FL/1N Set to logic O (active LOW) when FLOCK changes from 0 to 1 and is reset to logic 1 automatically after tuning information has been read. FL/ON As for FL/1N but is set to logic O when FLOCK changes from 1 to 0. FOV Indicates frequency overflow. When the tuner oscillator frequency is too high with respect to the programmed frequency, FOV is at logic 1, and when too low, FOV is at logic 0. FOV is not valid when TDIRU and/or TDIRD are set to logic 1. RESN Set to logic O (active LOW) by a programmed reset or a power-down-reset. It is reset > to logic 1 automatically after tuning/reset information has been read. MWN MWN (frequency measuring window, active LOW) is at logic 1 for a period of 1,28 ms, during which time the results of frequency measurement are processed. This time is independent of the cycle period. During the remaining time, MWN is at logic 0 and the received frequency is measured. When slightly different frequencies are programmed repeatedly and a.f.c. is switched on, the received frequency can be measured using FOV and FLOCK. To prevent the frequency counter and frequency buffer being loaded at the same time, frequency should be programmed only during the period of MWN = logic 0. °ort information bits ?23/1N, P22/1N Set to logic 0 {active LOW) at a LOW-to-HIGH transition in the input voltage on P23 and P22 respectively. Both are reset to logic 1 after the port information has been read. 23/0N,P22/ON As for P23/1N and P22/1N but are set to logic 0 at a HIGH-to- LOW transition. 123, P122,P121, Indicate input voltage levels at P23, P22, P21 and P20 respectively. A logic 1 120 indicates a HIGH input level. Reset “he programming to reset all registers is shown in Fig. 7. Reset is activated only at data byte HEX 06. \\cknowledge is generated at every byte, provided that CITAC is not in the power-down-reset mode. \\fter the general cal! address byte, transmission of more than one data byte is not allowed. GENERAL CALL ADDRESS HEXO6 BDOOOOOOSLOOCCCNIICILL 7280128 Fig. 7 Reset programming.
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Computer interface for tuning and control (CITAC) SAB3035 RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Supply voltage ranges: (pin 16) VP4 —0,3 to +18 V (pin 22) Vp2 —0,3 to +18 V (pin 17) Vp3 -0,3 to +36 V Input/output voltage ranges: (pin 5) VsDA —03 to +18 V (pin 6) Vsci -0,3 to +18 V (pins 7 to 10) Vp2x -0,3 to +18 V (pins 11 and 12) VAFC+,AFC——0,3 to Vpy* V (pin 13) VTi —0,3 to Vpy* V (pin 15) VTUN ~0,3 to Vp3* V (pins 18 to 21) Vpix -0,3 to Vpo**V (pin 23) VEDIV —0,3 to Vpi* V (pin 24) Vosc -03 to +5 V (pins 1 to 4 and 25 to 28) VDACX —0,3 to Vpy* V Total power dissipation Prot max. 1000 mW Storage temperature range Tstg —55 to +125 °C Operating ambient temperature range Tamb —20 to +70 °C * Pin voltage may exceed supply voltage if current is limited to 10 mA. ** Pin voltage must not exceed 18 V but may exceed Vp9 if current is limited to 200 mA. October 1983 1357
Tamb = 25 °C; Vpy, Vp2, Vp3 at typical voltages, unless otherwise specified Supply voltages Vpy 10,5 12 13,5 Vv Vp2 4,7 13 | 16 v Vp3 30 32 35 Vv Supply currents (no outputs loaded) Ip4 20 32 50 mA Ipo 0 - 0,1 mA 1p3 0,2 0,6 | 2 mA Additional supply currents (A) Ip2a | -2 - loHP1x} MA (note 1) IP3A 0,2 - 2 mA Total power dissipation Prot - 400 | - mW Operating ambient temperature Tamb —20 - +70 °C °C bus inputs/outputs SDA input (pin 5); ! | SCL input (pin 6) | Input voltage HIGH (note 2) | Vin 3 — | Vpqy-1} Vv Input voltage LOW | VIL —0,3 - 1,5 Vv Input current HIGH (note 2) ur) - - 10 uA Input current LOW (note 2) Nie - - 10 HA SDA output (pin 5, open collector) | | | Output voltage LOW at Io, = 3 mA Vor - - | 04 Vv | Maximum output sink current lot - 5 | = mA | Open collector !/O ports | | P20, P21, P22, P23 | | (pins 7 to 10, open collector) | Input voltage HIGH Vin 2 -— | 16 Vv : Input voltage LOW Vit -0,3 - | 08 Vv Input current HIGH NH - - 25 HA . Input current LOW le - - 25 BA Output voltage LOW at lol =2mA VoL - - 0,4 Vv Maximum output sink current lot - 4 - mA
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Computer interface for tuning and control (CITAC) SAB3035 A.F.C. amplifier Inputs AFC+, AFC— (pins 11, 12) Transconductance for input voltages up to 1 V differential: AFCS1 AFCS2 0 0 goo 100 250 800 nA/V 0 1 901 15 25 35 HA/V 1 () 310 30 50 70 HAV 1 1 911 60 100 140 A/V Tolerance of transconductance } multiplying factor (2, 4 or 8) | when correction-in-band is used AMg —20 - +20 | % Input offset voltage Vioff —75 |- +75 | mV Common mode input voltage V, 3 - Vp4-2,5 | Vv com Pi | Common mode rejection ratio CMRR - 50 - | dB Power supply (Vp7) rejection ratio PSRR - 50 - dB Input current yy - - 500 nA Tuning voltage amplifier | Input TI, output TUN (pins 13, 15) | Maximum output voltage at | load = £1,5 mA | VTUN — |Vp3—1,6)— Vp3—0,4} V Minimum output voltage at Noad = 1,5 mA | | VTMI1 — VTMIO | ie) ie) | Vtmoo 300 - 500 mV 1 0 | Vtm10 | 450 - | 650 mV 1 1 | VTM11 | 650 - 900 | mV Maximum output source current —ITUNH | 2,5 - | 8 mA | Maximum output sink current ITUNL - 40 | - mA Input bias current It —5 - | +5 nA Power supply (Vp3) rejection ratio PSRR - 60 | — dB i | October 1983 1359
CHARACTERISTICS (continued) Tuning voltage amplifier (continued) Minimum charge IT to tuning voltage amplifier TUHN1 TUHNO 0 0 CHoo 0,4 1 1,7 HA us 0 1 CHo4 4 8 14 HA us 1 ie) CH19 15 30 48 HA us 1 1 CHy4 130 250 370 BA Us Tolerance of charge (or AVTYN) multiplying factor when COIB and/or TUS are used ACH —20 = +20 % Maximum current | into tuning amplifier | TUHN1 TUHNO (e) 0 too 1,7 3,5 5,1 HA ie) 1 'T01 15 29 41 HA 1 0 IT10 65 110 160 | uA 1 1 "11 530 875 1220, | nA Correction-in-band | Tolerance of correction-in-band : levels 12 V, 18 V and 24 V AVciB -15 =- +15 % Band-select output ports P10, P11, P12, P13 (pins 18 to 21) Output voltage HIGH at | —IOH = 50 mA (note 3) VOH \\Vp2—0,6| — - Vv Output voltage LOW at Io, = 2mA | Vo - - 04 | Vv Maximum output source current (note 3) | —lOH ~ 130 200 mA Maximum output sink current for - 5 - mA FDIV input (pin 23) Input voltage (peak-to-peak value) (trisg and tfal} <40 ns) VEDIV(p-p} 01 - 2 v Duty cycle - 40 - 60 % Maximum input frequency fmax 14,5 - - MHz Input impedance Zj - 8 - kQ Input capacitance Gj - 5 - pF
1360 October 1983 |
Computer interface for tuning and control (CITAC) SAB3035 Came ot Yin Jon Pom Ta OSC input (pin 24) Crystal resistance at resonance (4 MHz) Rx - - 150 a DAC outputs 0 to 7 (pins 25 to 28 and 1 to 4) | Maximum output voltage (no load) at Vpq = 12 V (note 4) VDH 10 - 11,5 Vv Minimum output voltage (no load) at Vpq = 12 V (note 4) VoL 0,1 - 1 v Positive value of smallest step | (1 least-significant bit) AVD ) - 350 mV | Deviation from linearity = - - 0,5 Vv | Output impedance at Iigaq = +2MA Zo - - 70 2 | Maximum output source current -IDH - - 6 mA | Maximum output sink current IDL - 8 - | mA | | Power-down-reset | Maximum supply voltage Vpq at which | power-down-reset is active Vpp 7,5 - 9,5 | Vv Vp rise-time during power-up | (up to Vpp) tr 5 - | — | us Voltage level for valid module address | Voltage level at P20 (pin 7) for valid module address as a function of MA1, MAO | MA1 MAO | 0 0 Vvaoo | -03 |= 1 6] Vv 0) 1 Vyao1 | -0,3 |- og8 | Vv 1 ie} VvA10 2,5 - Vp1—-2 Vv 1 1 Vvait | Vp1—0,3)— vPq v "Notes to the characteristics 1, For each band-select output which is programmed at logic 1, sourcing a current !Q14p1 x, the addi- tional supply currents (A) shown must be added to lpg and Ipg respectively. 2. If Vpq <1 V, the input current is limited to 10 uA at input voltages up to 16 V. 3. At continuous operation the output current should not exceed 50 mA. When the output is short- circuited to ground for several seconds the device may be damaged. 4. Values are proportional to Vp1. October 1983 1361
(°C BUS TIMING (Fig. 8) !?C bus load conditions are as follows: 4kQ pull-up resistor to +5 V; 200 pF capacitor to GND. All values are referred to Vjyy=3 Vand Vjy = 1,5 V. [penne mint im | ve | moe | nt | Bus free before start tBUF 4 - us Start condition set-up time tsu,stTa | 4 - us Start condition hold time tHD,STA 4 - us SCL, SDA LOW period tLow 4 - us SCL HIGH period tHIGH 4 - US SCL, SDA rise time tr - 1 US SCL, SDA fall time tr - 0,3 US Data set-up time (write) tsu,DAT | 1 - BS Data hold time (write) tHD,DAT | 1 - us Acknowledge (from CITAC) set-up time tsu,cAc | — 2 us Acknowledge (from CITAC) hold time tup,cac | 9 - us Stop condition set-up time tsu,sto | 4 - MS Data set-up time (read) tsu,RDA | — 2 HS Data hold time (read) tHD,RDA| 0 - us Acknowledge (from master) set-up time tsu,MAC | 1 ~ US Acknowledge (from master) hold time tHD, MAC| 2 - us Note Timings tsy,DAT and typ, DAT deviate from the |?C bus specification . Mfter reset has been activated, transmission may only be started after a 50 us delay. SDA "BUF tho, DAT>| — t tsu, CAC tHD,cAC — tLow F tk | aye ae { | scL | | 'su,STA HD, STA tsu, STO SDA Fy MA | Le wle ot tsu, RDA HD, RDA SU, MAC THD, MAC 7290131 Fig. 8 1?C bus timing SAB3035.