SAA9060 PHILIPS | Alldatasheet
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® Single scan or double scan applications @ Parallel data input © 7-bit D/A conversion of the colour difference signals © 8-bit D/A conversion of the luminance signal QUICK REFERENCE DATA Supply voltage | Vpp 45 5.0 5.5 |v | Input current lbp - 170 250 | mA | Power dissipation | Prot - - 140+) Wo Back-bias voltage -3 - 0 | vo | Operating ambient temperature range Tamb 0 - +70 | OC | PACKAGE OUTLINE 28-lead DIL; plastic (SOT117). July 1989 1305
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1306 July 1989
Video processor with DACs SAA9060 PINNING Ysus L] U [28] at ne. 6 ne. Ds ctr [4 | [25] 04 ctato [5 | [24] p3 os[é] 02 Vssa oO Bias iG SAAS060 [a] bo -6-n [9] 120] Vsso Yo [11] [18] uv2 nc. [12] ui LL9/LLI.5 16] uvo Vpp [14] [15] 12 7281794.1 : Fig.2 Pinning diagram.
1 VsuB Substrate pin for external capacitor, smooths internally generated voltages
2,3 nc. Not connected
4 CTRL1 Control input for resolution enhancement filter
5 CTRLO Control input for resolution enhancement filter
6 os Data format switch-over (from serial to parallel)
7 Vssa Analogue ground
8 IBIAS Reference current for the DACs
9 —(B-Y) Chrominance analogue output; inverted colour difference signal B-Y 10 —(R-Y) Chrominance analogue output; inverted colour difference signal R-Y
11 Yo Luminance analogue output
12 nc. Not connected 13 LL3/ Clock input: single scan parallel mode, f = 13.5 MHz LL15 double scan parallel mode, f = 27 MHz July 1989 1307
PINNING (continued)
14 Vpop Supply voltage
15 LL2 (Clock input for data word DO...D6) for serial data format only*/ f = 20.25 MHz; low-level version Do not connect pin when selecting parallel data format
16 UvOo |
7 uv1 a . we 18 uv2 | Digital chrominance input; f = 13.5 MHz or 27 MHz
19 UV3
20 Vssp Digital ground (0 V)
24 D3 Digital 7-bit luminance input; f = 13.5 MHz or 27 MHz 25 D4 26 DS 27 D6
28 BL Format input; indicates the start of a transmission of a data line
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Video processor with DACs SAA9060 FUNCTIONAL DESCRIPTION (see Fig. 1) The VDA, DMSD/S-DMSD and a RGB controller form the video channel of a digital TV system. The VDA receives the luminance and chrominance data from the DMSD/S-DMSD and converts this data into an analogue output for a RGB controller, Chrominance data signal The chrominance data consist of alternating UV samples with a sample frequency of 3.375 MHz (single scan), the sample frequency is increased to 13.5 MHz by using two cascaded interpolation filters. The 7-bit chrominance data is then converted to an analogue signal (inverted colour difference signals B-Y and R-Y) for use in a RGB controller. Luminance data signal The luminance data frequency is clocked at 13.5 MHz or 27 MHz into the resolution enhancement filter (controlled by CTRLO and CTRL1), this improves the quantization noise behaviour in areas with small variation and produces an 8-bit data output. The 8-bit data is converted into an analogue signal for use in a RGB controller. BL signal (see Fig. 3) The BL signal is used to indicate the active video length within the line and synchronizes the demulti- plexing of the UV data. Operating modes There are two operating modes: » parallel data transmission (single scan); LL3/LL1.5 = 13.5 MHz » parallel data transmission (double scan), LL3/LL1.5 = 27 MHz. Dutput signals The output signals are AC-coupied to a RGB controller. During the horizontal synchronization gap he luminance and chrominance signals are blanked (black and no colour difference respectively) and he RGB controller clamps the input signals. ee July 1989 1309
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Video processor with DACs SAA9060 RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Supply voltage Vop -0.3 6.0 Vv Input voltage vy -0.5 6.0 Vv Back-bias voltage VBIAS —3 ie) Vv Storage temperature range Tstg —55 +125 | °C Operating ambient temperature range Tamb 0 +70 oC THERMAL RESISTANCE Junction to ambient Rthj-a 50 K/W BY July 1989 1311
Tamb = 25 °C; Vpp = 5 V; all values referred to Vgg; unless otherwise specified Supply Supply voltage Vop 4.5 5.0 5.5 Vv | Supply current lbp * 170 250 mA Voltage on pin 1 with clock VsuB —3.0 —2.5 —2.0 Vv Current on pin 1 without clock IsuB - 0.2 40 BA Voltage ripple on pin 1 Vripple - - 10 mV Inputs | LL3 input signal note 1; | see Fig. 4 | Input voltage HIGH ViH 2 - Vpp Vv Input voltage LOW VIL —0.5 - 0.8 Vv Input capacitance (pin 20) Vy=OV Cc, - - 10 pF LL3 time period fnom =
13.5 MHz tLL3 69 74 80 ns
Duty factor tpH/tLL3 43 50 57 % LL1.5 input signal note 2; see Fig. 5 Input voltage HIGH ViH 2 - Vpop Vv Input voltage LOW Vit —0.5 = 0.8 Vv } Input capacitance (pin 20) V,)=0V ; Cy - - 10 pF ' LL1.5 time period fnom=
27 MHz tLL15 35 37 40 ns
| Duty factor tPH/tLL1.5 43 50 57 % i * Value to be fixed.
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Video processor with DACs SAAS060 [ parameter contions | symbol | min’ [vp | mex | ni | BL input signal note 3; see Figs 6 and 7 Input voltage HIGH ViH 2 = Vopb Vv Input voltage LOW Vin -0.5 - 0.8 Vv Input capacitance (pin 20) Vj)=0V C - - 10 pF Input current HIGH UH - - 1 HA Input current LOW He - - 100 uA Pulse width HIGH tPH - 720 - * Pulse width LOW NTSC/PAL tPL - 138/144 - * LL3 set-up time tsu 12 - - ns DO-D6 and UVO to UV3 | note 2; see Fig. 8 input voltage HIGH ViH 2 - Vop Vv Input voltage LOW Vit -0.5 = 0.8 Vv Input capacitance . (pin 20) Vip=O0V Cc; - - 10 pF Input current HIGH Ny - - 1 BA Input current LOW hie - - 100 HA LL1.5 set-up time tsu 13 - = ns LL1.5 hold time tHD 3 - ~- ns CTRLO and CTRL1 input signals note 4 Input voltage HIGH note 5 ViH 2 - Vop Vv Input voltage LOW note 5 Vit Vss - 0.8 Vv Input capacitance** V)=0V Cc) - - 10 pF | IBIAS input signal Fig. 9 | Input current note 6 liBias - 100 - HA ' Bias resistance note 7 RiBIAS - 39 = kQ Input voltage note 7 VIBIAS - Vpp - Vv ' Potential difference across RiBi AS note 8 UpBias - 1.5 - Vv * Clock periods of LL3. ** Referred to pin 20. July 1989 1313
CHARACTERISTICS (continued) OUTPUTS Y signal output note 9 | Resolution | - 8 - | bits Nominal range max. 255 | 14 - 230 | Output current max. 2.55 | Ife) 0.14 - | 2.35 | mA Resolution per step NIBIAS = | | | 100 pA | Res - 10 ;- | pA | Load on pin 11 PRE _ 180 | _ | 2 | Coupling capacitance | | to RGB controller see Fig. 10 | Coc - 47 | - | nF | Total output capacitance | | {pin 11) note 10 | Co - 17 - | pF Conversion time | tDAC - - 30 | ons Time constant = RL | | (Cg+Cp+Ce) | tc - 50 \\ = ; as | Output voltage range | Vo Vpp-2 - ‘Vpp | V | Differential non-linearity | -0.5 - +0.5 | LSB | Equality of converter | | \\ output normalized | | to maximum level -1 - +1 | LSB | Temperature dependency | Aljpyas=0 -0.5 |= +05 | LSB Glitch | -0.5 - +0.5 | LSB —(B-Y) signal output note 10 | | | Resolution - 7 - | bits | Nominal range max. 127 13 > 114 Output current lo 0.26 - 2.28 mA Resolution per step liBiAS = 100 pA Res - 20 - BA Load on pin 9 Ru - 750 = 2 Coupling capacitance to RGB controller see Fig. 10 Coc - 10 - nF Total output capacitance including pin (pin 9) capacitance and wiring Co - 7 =- pF Conversion time tpAC - - 30 ns Time constant =R_ (Cg t+ Cp + Ce) tc - 50 - ns
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Video processor with DACs SAA9060 Output voltage range Vo Vpp-2 - Vop Vv Differential non-linearity -0.5 - +0.5 LSB Equality of converter output normalized to maximum level -1 - +1 LSB Temperature dependency | Aljpyas=0 —0.5 - +05 LSB Glitch -0.5 - +05 | LSB —(R-Y) signal output note 10 Resolution - 7 - | bits Nominal range max. 127 10 = 117 | Output current max. 2.55 0.2 - 2.34 mA Resolution per step liBIAS = | | 100 nA Res - 20 - | pA | Load on pin 10 RL - 560 | — | Q | Coupling capacitance | to RGB controller see Fig. 10 Coc - 10 [-~ nF Total output capacitance including pin | | : (pin 10) capacitance | | and wiring | Co - 7 - pF | Conversion time | tDAC i - 30 ns | Time constant = RL (Cs + j | ' Cp + Ce) | tc - 50 - ns Output voltage range | Vo | Vpp-2 - Vpb Vv Differential non-linearity | —0.5 - ; +05 | LSB Equality of converter | | | output normalized | | | to maximum level | -1 - +1 LSB | Temperature dependency | Aljpias | -0.5 - +0.5 LSB | Glitch —0.5 - +0.5 LSB i BS July 1989 1315
Notes to the characteristics 1. 25/30 Hz picture frequency with interlace. 2. 50/60 Hz picture frequency, parallel data transmission. 3. 25/30 Hz picture frequency, f = 20.25 MHz. 4. Static input signal; input HIGH by means of an internal pull-up resistor of 100 kQ. crit | cTRLO 0 (e) bypass (min.) 1 1 lowpass (max.) 6. When I1B) As = 100 BA the quantization steps of the Y output DAC is 10 uA and —(B-Y), —(R-Y) outputs are 20 zA, The maximum voltage at R__ is 2 V. If Rygias is used, the temperature coefficients of Igias and the DACs are compensated. 7. Effective voltage noise is < 1 mV. 8. UiBiAs = 1.2 V+ liBias x 3kQ. 9. Values measured from the Y output DAC. 10. Values measured from the —(B-Y) output DAC, - tpH | U3 ' rn i Vin input | signal _ 15 Veo min) —s Mie Fig. 4 LL3 timing waveform; 25/30 Hz picture frequency with interlace. ! ‘PH LL1.5 Vin input ——15v signal ——— Vit "Los 72817921 Fig. 5 LL1.5 timing waveform; 50/60 Hz picture frequency, parallel data transmission.
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Video processor with DACs SAAS9060 J uu 15V — Vit BL input signal 7281789.1 Fig. 6 BL timing waveform; 25/30 Hz picture frequency; f = 13.5 MHz. LL1S —>| ‘su BL input : signal 7281793 Fig. 7 BL timing waveform; 50/60 Hz picture frequency; f = 27 MHz. BL | Yo =| || 0-06 UV0-UV3 input | signals Lu1s . 7281791 Fig. 8 DO to D6 and UVO to UV3 timing waveform; 50/60 Hz picture frequency, f = 27 MHz. July 1989 1317
APPLICATION INFORMATION
SAA9060 i * Ripias IBIAS I * Rigas ~ 40 k® then lipiag = 100 HA. 7281787 Fig.9 IBIAS input circuit. Yoo SAA9060 | | RGB controller (Rigi | | | Co n-bits 'p py } Cs | Re Ce 7 a Vssa a 7 t 72817881 ) Rigias = Rx (Y output), Ry (B-Y output), Ry (R-Y output) : Fig. 10 Application of the DACs.