SAA9051

SAA9051 PHILIPS | Alldatasheet

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Philips Semiconductors Product specification a Digital multistandard TV decoder SAA9051 eT FEATURES GENERAL DESCRIPTION r= ¢ All operations based on a The SAA9051 digital multistandard sampling frequency of decoder (S-DMSD) performs

13.5 MHz, providing: demodulation and decoding of all

• full adaptability to all quadrature modulated colour TV transmission standards standards, as well as performing . luminance processing for all TV ~ capability for memory-based standards with CVBS or Y/C input features signals. * Separate chrominance and juminance input (Y/C) « CVBS input for standard

applications

• CVBS throughput capability for SECAM application * Luminance signal processing for all TV standards (PAL, NTSC, SECAM, B/W) « Horizontal and vertical synchronization detection for all standards * Chrominance signal processing for all quadrature amplitude modulated colour-carrier signals * Requires only one crystal © Controlled via the I?C-bus « User-programmablie aperture correction (horizontal peaking) * Compatible with memory-based features (line-locked clock) * Cross-colour reduction by chrominance comb-filter (NTSC) « Wide range hue control

ORDERING INFORMATION

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Philips Semiconductors Product specification Digital multistandard TV decoder SAA9051 SSS SeFFseeeees wll i PETE FF * 8 2 oT 5,8 fe 13 Joe 2B2)> 32) < > Sz] 82 ~ - 3 + 252 w ae g Ed g< 25 > i a E 72 iJ z , z c 8 3 3h 8 c = Tt gee 3 A "LZ te sg 3 * 3 ees 22 8 2 3 fNo8eh gz z 2 Fa e385 3 “_ 8 aE 8 19 3 3 ~ : &3 > . “6 we & 8 8 a3 = SEE oN Fe Lg 3| = 8 ge zi 8 > | 8 5 “Ss 5 ° 3 3 ° eal<fl E 8 ° é 5 A Be Se Pa Zoz ~ Qf ge 226 Es a 3 3a5 5 Fa

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Philips Semiconductors Product specification Digital multistandard TV decoder SAA9051 s 223 3 mis £8 5 “8 Poh ¥xo zx2 cues 3 g M rd Se Fa yoe & £ Ee a 5 | : gs 8 - | - 2 ttt tl tof § zo 8 58 5 OF 2 z z i | : 5 & gs] £2 e s | tt 3 $2 ie) 3g |s igi Lal © g a 2§ g 2 gs | z 4 & 8 z8 is 8 8 cB ie 22 ¢ 5 ba. 25 5 «f geet 5 29 6.5 & : ge ol ie pitepereperspeteré ff] ose 28 e a 4 alg fs ek 5 3 6 % 3 May 1991 3-577 Mi 7110826 0076463 OT] ‘www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification Digital multistandard TV decoder SAA9051 ——— esses PIN CONFIGURATION 2 2 sig 8 8 os eo 8sses 29k Bef ee BRB: ee WHUEEPEEHGEBEE REE 10a [710] [60] nc tos [1] [59 fone tos [72] [se] uve \\o7 ui cveso [14 _] (ss_| uve eves! [15] [ss] v3 cves2 [16 _} (sa7] ac cves3 1 Vss [_19_] {51_] Yss cvess [20 J [50] 02 cvess [22 ) [48 | oa eves? [23] Ds ss2 [24] [46 | 06 ss3 {25 J (45 | 07 we [26] (aay nc. 7z979481 Fig.3 Pinning configuration. May 1991 3-578 Mf 7110826 0076464 T38 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification Digital multistandard TV decoder SAA9051 PINNING symeo, =| PIN DESCRIPTION SC TEST test input (active HIGH), when HIGH enables scan-test mode, always connected to ground reset input (active LOW), results in the |?C-bus control registers 1 to 3 and internal stages being reset during the reset phase. The minimum LOW period of RES is 120 LL3 clock cycles [nc ‘(8 |rotcomeded SS SCSCS—~*d 100 (LSB) - 107 6-13 bidirectional data path; chrominance input for separate luminance and (MSB) chrominance input (Y/C) or CVBS output for SECAM decoder SAA9056. Two's complement format (/O0 is only used internally for CVBS throughput) CVBSO (LSB) - 14-17, 20-23 digitalized composite video blanking and synchronization signals; CVBS7 (MSB) containing luminance, chrominance and all synchronization information or luminance, blanking and synchronization signals in the event of separate luminance and chrominance (Y/C) input. Two's compiement format (CVBS0 is only used internally for CVBS throughput) positive supply votage 5 V) [Vs 9 | around 0 V4 $82 - S83 [24-25 __| source select output signals; |"C-bus controlled, TTL compatible switches HC programmable horizontal output pulse; when used in conjunction with input circuits (e.g. ADC} indicates the black-level position before analog-to-digital conversion. The start and stop times are programmable, between -9.4 1s and +9.5 ys in steps of 74 ns, via the |?C-bus a HSY programmable horizontal output pulse; when used in conjunction with input circuits (e.g. an ADC). It indicates the synchronization pulse position before analog-to-digital conversion The start and stop times are programmable, between -14.2 us and +4.7 ps in steps of 74 ns, via the P’C-bus vs vertical synchronization output; indicates the vertical position of the picture for 50/60 Hz field frequency May 1991 3-579 WE 7110826 O07b865 574 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification a Digital multistandard TV decoder SAA9051 a PINNING (continued) syMeo. =| PIN | DESCRIPTION HS horizontal synchronization pulse output (duration = 64 LL3 clock cycles). HS is programmable, between -32 is and +32 ps in steps of 300 ns, via the I?C-bus XCL2 32 clock output; half of the crystal clock frequency (12.288 MHz). In phase with crystal (pin 33) XTAL crystal oscillator inputinverting amplifier output; input to the internal clock generator from an external oscillator or output of the inverting amplifier to an external crystal (24.576 MHz) XTALI input to the inverting amplifier from an external crystal (24.576 MHz); connect to ground if an external oscillator is used Ine SSSSC*dRSCSC~C~*~*dit connate LFCO line frequency control; analog output representing a multiple of the line frequency (6.75 MHz) with 4-bit resolution, the phase of which is compared to the system clock by the CGC (SAA9057A) [ned [SoA [40 | Fou serie datainpoVoutpu [st [4 Feu seal lock input BL blanking signal output (active LOW); indicates the active video and line blanking periods. BL also synchronizes the data multiplexers/demultiplexers |2C-bus select address; input for selection of the appropriate I2C-bus slave address D7 (MSB) - luminance data output D1 (LSB) gear OV) postive supply vakage SV) [nc [ss _|noteomnectes SS SSOSCSC~—~SCSCS UV3 - UVO multiplexed PAL or NTSC colour difference signal output or SECAM CS input signal from the SECAM decoder. Output data format is two's complement. The multiplexer is synchronized to the rising-edge of BL Cn 0 FOE fast output enable signal (active LOW); sets D1 - D7 and UVO - UV3 outputs to the HIGH-impedance Z-state SS0-SS1 source select output signals, set via the I?C-bus; used to control the input switch (e.g. TDA8708) a A AFCC [68 —————_| additional output for circuit control; activated via the ?C-bus May 1991 3-680 ME 7110826 OO7b8bb S00 a _ www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification Digital multistandard TV decoder SAA9051 FUNCTIONAL DESCRIPTION (see CVBS processin weighting and adding stage, see Fig.) In the CVBS mode: Gaara 2 Tones Channel 1 and The S-DMSD performs the A . demodulation and decoding for all + The CVBS signal is separated uadrature modulated colour TV into its luminance (VBS) and COMBINING CHANNEL 1 AND CHANNEL 2 standards (PAL-B, G, H, |. M,N chrominance (CG) parts by the SIGNALS NTSC 4,43 MHz and NTSC-M), as chrommnarce Wap an bandhass The Channel 1 HF signal is well as performing luminance, and vith d by the standard weighted and added to the parts of the synchronization, switche a vy tne nda Channel 2 DCAsignal. The identification signals (CCFRO, . . processing for TV standards (PAL, CCFRI/YPN) according to the combined signals are matched to NTSC and SECAM). All of the detected colour-carri "9 the specified amplitude and the controllable functions, user as well tre sen 5 $8 Mion word size is reduced to 7 bits. The as factory adjustments, are 4 ns ined ° AVD signal is transmitted to the accessed via |?C-bus thereby ° ~ . variable delay compensation stage enhancing the adaptability of the * On reception of a SECAM signal where compensation for IF group digital TV concept. the signal is transmitted to the delays occurs, the amount of delay Operation is based on a line-locked SECAM decoder (SAA9056) we is programmable (from —4 to +3 LL3 pe ‘i ft 13.5 MH, the IO port (i00 - 107). Bit CT clock cycles, see note) via bits YDLO tacmuing ihe oretem fully enables the 3-state butter - YDL2. The Y signal is transmitted ageptabla ha allie trequencies between both parts. to the time multiplexed interface Only one crystal is required for all where the signal is output via D1 - WV Y orlanne eq Luminance path D7. A A The S-DMSD !s designed to operate hie Hot ‘ helo ance wee cans CHANNEL 3 SIGNAL eon re eee), ‘ separated into three Channels as The Channel 3 VB signal is the CG c is hot va iged the designer foliows: transmitted to the prefilter must ensure: 9 synchronization stage, see section ust ensure CHANNEL 1 SIGNAL “Synchronization path’ * areset pulse is appited to the The Channel 1 si ', . ignal is transmitted S-OMSD after a power failure to the programmable bandpass filter Note . where the high luminance Differences in the delay YIC processing frequencies are removed (centre compensation required for PAL and In the Y/C mode: frequency is programmable via bits NTSC are catered for by | BP1 and BP2). The BC signal is identification signal YPN which * The chrominance signal 's input transmitted to the coring (corner switches the chrominance trap to at the 10 port (100 - 107) and correction) stage where low the appropriate colour-carrier transmitted via the input amplitude noise is removed (amount —_ frequency 3.58 MHz or 4.43 MHz. switch/SECAM delay of low amplitude noise removal is compensation circurt programmable via bits COR1 and Chrominance path (see Fig.1) (multplexer) to the chrominance COR2). The HF signal is transmitted . an bandpass filter, ‘see section to the weighting and adding stage, The chrominance CG signal is Chrominance path’ see section ‘Combining Channel 1 fransmited from tre oon * The other components, Y signal and Channel 2 signals’. andpass Stage to the gain contro and synchronization pulse, are circuit (see note 1). The gain control input via inputs CVBSO - CVBS7 CHANNEL 2 SIGNAL stage ensures that the chrominance and transmitted via the input signal has constant burst amplitude. switch/SECAM delay The Channel 2 signal is transmitted The GQ signal is transmitted to the compensation circuit to the to the fixed delay compensation quadrature demodulator, where luminance prefilter. stage where delay compensation demodulation of the quadrature . and black-level adjustment occurs. modulated chrominance GQ signal The DCA signal is transmitted to the to colour difference signals occurs. May 1991 3-581 MH 7110826 OO?7b8b? 747 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification il tel el Digital multistandard TV decoder SAA9051 SSeS The QLU and QLV signals are COLOUA-CARRIER FREQUENCY PHASE DETECTORS tare 3 lowpass filter. The REGENERATION The phase detectors that receive the transmitted to te Teton and The regeneration of the SP signal, also part of the PLL, ra ‘better stage. The comb-filter colour-carrier frequency is control the generation of the swae soe te 2) e at " th performed by the phase-locked-loop _line-locked clock (PL). Loop fitter 2, 5 9 a vertical So ieelate - e (PLL) which comprises a quadrature —_ which has a variable bandwidth, non comy rents for NTSC demodulator, low-pass filter, burst dependent on the time constant (for PAL, th Wrals are phase gate, loop filter 1 and signal (VTR), generates two corrected) The CCU an se cv divider/discrete time oscillator increment signals (INC1 and INC2) signals are transmitted to the (DTO1). The DTO1 is controlled by with different delays. INC2 is eaourkiler and PAL switch stage the standard identification signals programmable via the increment (see note 3). At this stage si oe CCFRO - CCFA1 and the Hue signai —_ delay signal (IDEL). INC1 corrects which do not comy f vith the which influences the demodulation the regenerated subcarrier selected standard ave removed. in phase of the chrominance signal. frequency at DTO1 and INC2 . . performs phase incrementing of the PAL mode this stage restores . Synchronization path DTO2. The crystal clock generator the correct phase of the V signal. . - . Be ni a provides a stable 24.576 MHz clock The signals are then transmitted to In the synchronization circuit, input to DTO2 which in turn supplies the time multiplexed interface and prefilter synchronization is Pl . rat upp : . the 4-bit DAC with a digital control output wa UVO - UV3. implemented to normalize the signal of 432 or 429 times the line synchronization pulse siopes. A "on agi , . frequency. The analog output LFCO, Notes synchronization-slicer provides the f . ti from the DAC, is transmitted to the Th . detected synchronization pulses SAASOS7A (CGC). 1. canted by the AG sign al (SP) to the horizontal and vertical " rocessing and phase detect: which is derived from the eiages 9 ance sector Output interface amplitude and colour-killer The signals OEY, OEC, CO, Cl and Getector stage (ACKD). A HORIZONTAL AND VERTICAL PROCESSING CD control the output interface (see non-standard burst-to-amplitude ; ; Fig.6). All but one of these signals ratio results in the automatic The horizontal and vertical are received via the I?C-bus, except colour-leveling stage functioning processing compnses partofaPLL = 4. Gn signal which is detected in as an amplitude detector to circuit for regeneration of the the S-DMSD. A power-ON reset ensure correct amplitude and horizontal synchronization (HS) and results in these signals being set to avoid overflow/limiter defects. an adaptive filter for detection of the zero 2. The comb-filter can be altered yerical i ieellnarae (WS). The from alternate to non-alternate lorizontal and vertical processing mode by the ALT signal. also generates: 3. The colour-killer and PAL * coincidence signal (HLOCK) switching stages are controlled which controls the mute function by the amplitude and * standard identification signal colour-killer detection circutt (FD) which identifies nominal using the AC1 and CD signals. 525 or 625 lines per picture. May 1991 3-582 M8 711082b 007b468 643 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification Digital multistandard TV decoder SAA9051 Table 1 Vertical Noise limiter (VNL) signal ouTPuT | 0 | VNLbypassed [1 [WNtactie Table 2 CO, Cl and CD signals [0 [x | _x _|wwo-wa__feseurOrFem SSCS } 1 {| o [| 0 _[Uvo-uvs colour OFF (controlled by CD) ; 1 {| o | 1 [Uvo-uv3s colour ON (controlled by CD) [tft x [uve ws Jootourfores oN SCSC~*@ Where: X = don't care. Table 3 OEC, OEY, FOE, BL, D1 - D7 and UVO - UV3 signals CS pa ft fo active [active factve OP [et Jastve es aes Lo ft fo factve Tactive factve OP Where: X =don'tcare . HIZS = HIGH-impedance Z-state. Note to Table 3 Combinations other than those shown in Table 3 are not allowed. FOE signal synchronization data lines (HS and PC bus interface In PIPCO (picture-in-picture ¥) or the blanking data line (BL), {see Tables 1 to 3) controller, SAA9068) applications, 9 The following control signals are the PIPCO requires access to the received via the I?C bus interface: digital YUV-bus on a pixel CS signal © standard identification signals time-base. This requirement is. The CS signal is transmitted from (CCFRO, CCFR1, ALT, s YPN) catered for by PIPCO generated the digital SECAM decoder (DSD) ; ’ lo signal FOE, which forces all data during the horizontal-blanking period * video recorder/TV time constant output of the S-DMSD and DSD and is received via the UV2 input ({VTR) (SAA9056) into the (see Fig.6). The CS bit is read by e hue control (HUE) HIGH-impedance Z-state. The FOE the S-DMSD once per line at us « delay programming of the signal does not affect the clock cycle number 748 (see Fig.8). horizontal signals (HS, HC, HSY) May 1991 3-583 MB 71108eb O07b8b4 S17 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification — See Digital multistandard TV decoder SAA9051 ee * increment-delay (IDEL) luminance and sync output * SECAM chrominance delay * luminance aperture-correction enable (OEY) compensation (SCDCO, SCDC1, control (BY, PF, BP1, BP2, * chrominance output enable SCDC2, SCDC3, SCDC4, COR2, COR1, AP2, AP1) (OEC) SCDC5, SCDC6). * luminance delay compensation switch signals (source select * horizontal sync (HSY) and clamp (YOLO, YDL1, YDL2) signals SSO, SS1, $S2, SS3) (HC) pulse disable (SYC). * fixed clock generation command ¢ additional output for circuit Signals transmitted from the (HPLL) control (AFCC) S-DMSD via the ?C bus are: * internal colour ON/OFF (CO) * chrominance source select * standard identification signals * internal colour forced ON, test CVBS/chrominance input/output (FD, CS) purposes only (Cl) (CTIYC). + colour-killer status signal (CD) . vertical noise limiter (VNL) © coincidence information (HLOCK) active/bypassed ¢ power-on-reset of S-DMSD (PONRES). May 1991 3-584 ME 7110826 0076870 23] - www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification eee es Digital multistandard TV decoder SAA9051 +63 +63 Preserves +47 a —-5- i luminance +8 a ———— | ron lane chrominance nominal) t * ievel syne -50 L—— tb (a) (b) +127 +63 +63 luminance +84 ‘output o ° range | U-component output range Sonera ° -64 64 (c) {d) (e) 7226075 (a) CVBS1 to CVBS7 input range (b) 101 to 107 input range (c) Y output range (d) U output range (B-Y) (e) V output range (R-Y) Fig.4 Diagram showing input/output range of the S-DMSD; all levels in EBU colour bar, values in binary, 100% luminance and 75% chrominance amplitude. May 1991 3-585 @® 7110826 0076471 178 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification Digital multistandard TV decoder SAA9051 ee s aé $3 i 2e 2g 5 = ae EB ; 8 é = ra e a 31s & 2 3 2 2 & 2 3 5, 2 glee 3 323 2 Byes a 3 rot € 8 5 rot g Blass Ld 2 8 ees m7 rf B 8 rot i= 1 i] oa be4 S tt o ~ 1 ot irs} : 113 . a beae tog bade ( les 1 189 Lig i 3 3 3s . ° 8 rot 3 tl Ey May 1991 2686 M@ 711082b 007b872 OOF www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification Ee Digital multistandard TV decoder SAA9051 a Ee 2 $a 3 fF) <2 5 3°? . a ee ee? s 5 YS TTT)" * - Ltt le § 8g SS £ eenne g t 3 3 a 3 Bee o B22 = Bra pas oO gp lg > 2 LO = ci 3 re}

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Philips Semiconductors Product specification a Digital multistandard TV decoder SAA9051 ee * * . IN & i i LON eS on Ps © j a: Ssg5 5 y Eo: S538 3 a A . q { a N NaN NaN N s = ase ¢ @ pqs P< : ie £ oO cn + g H £ 3 = 4 ~ we A 3 = A N £ \\ \\ 3 = . E = H $ oS cS > _ 2 be be} 2 _ - a 5 J a co a i ce [PNG Ed 3 la 8 S \\g 2 g 4 3 ne g 28 5 oe > May 1991 3-588 ME 7110826 0076874 1a? a - www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Serniconductors Product specification we Digital multistandard TV decoder SAA9051 — w—w 5 g 8 2 8 = es fi sé sexe re 8 - Es Se ns ET g8ss& § © -8 -3 & c a nS RG a } ¥ N = . s 7S = 3 5 . 8 8 2 [ay = Q a ° 2 NY : S 2 = — 3 N i s ge 2 2 BN 8 = an Fy e Fa — - .= ~ n Fa i (2) g ® _§N fal aN 6 -3 g a — é <4 o 2 a 1 2.8 2 = 6 1[ 1g SxS D pe ott ° u = 5 2 5 g Ps 3 : £ fe Hy £e sos9 3 — 7 2 7 bx] Fa — PS — ~ — —PSs, — bt 5 23 or | Bi: fe Be s5us 2 Ss | |* 5 5 Hy es Pa e s ee) 3 8 5 58 5S 3338 $ ee eee ee us a 3 5 g ge ° 3 $e3 2 ° ao& é . May 1991 3-589 MB 7110826 0076875 613 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors. Product specification eo Digital multistandard TV decoder SAA9051 ee Table 4 Slave addresses SLAVE RECEIVER ADDRESS pawns fol + fo) oj, oft [ol + | 0 [pray value GAren Pepe foto forty + [+ [0 pinay value e hex) Where: * = logic 0, receiver mode . * = logic 1, transmitter mode. SLAVE RECEIVER ORGANIZATION Slave address and receiver format There are two slave addresses, programmable via input SA, which determine the operating mode of the S-DMSD, see Table 4. Table 5 Subaddress byte and data byte formats REGISTER FUNCTION | , SUB DATA BYTE aporess| ov | os | os | pa | oo | o2 | o1 | oo | increment delay DEL_[00__|no7 [A06 [AOS [hoa [ADS __[ADe [AO [ADO | tHsYstanime [or |ar7_|aie[ats_[ara”[aig_[ai2 [att [aro | [HSYstopume [02 |aar”[aze [Aas [Aza [azo [azz [acs [az0 | tcsanime —___[oa_|aav_[ase [ass [aaa [asa [ase [Ast [A30__| [HO-stepne Joa [aa [aas_[aas [aaa [aes [aaa [ast [ato] HS startime (afer PHT) [05 [AST _[a56 [Ass [Ass [ASS [ase [ast [A50__| [Horzontalpeaking __[os__[BY [PF [apa [epi [ome [oon [ape [arr __| [Gontois [08 HPLC [FS vi [CO [ALT _|VPN _[COFRi | COFAD teenie Joo |vw._[oey_joec_| x [ci [arco [ser [sso __| SECAM delay fReseved ——SSC«diO OS MP RP KP RX [| xP xP x | x | Where: X = don't care. May 1991 3-590 MH 7110826 O07b87b 7ST www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification Ss Digital multistandard TV decoder SAA9051 LL Notes to Table 5 1. The subaddress is automatically incremented. This enables quick initialization, within one transmission, by the ’C-bus controller. 2. The subaddresses shown are acknowledged by the device. Subaddresses 10 to 1F (reserved for the SECAM decoder SAA9056) are not acknowledged. The subaddress counter wraps-around from 1F to 00. Subaddresses 20 to FF are not allowed. 3. After power-on-reset the control registers 1 to 3 (subaddresses 08, 09 and OA) are, with the exception of bits YDLO - YDL2 of counter 3, set to logic 0. All other registers are undefined. 4. Prior to a reset of the IC all outputs are undefined. 5. The least significant bit of an analog control or alignment register is defined as AXO. Susappress 00 Table 6 Increment delay control IDEL (application dependent) DECIMAL DELAY TIME CONTROL BITS* MULTIPLIER (STEP SIZE = 2/13.5 MHz = 148 ns) [ a07 | aos | 0s] A04 | A03 | A02 | aot | Aco | -1 -148 ns (min. value) 1 1 1 1 1 1 1 1 to -110 —16.3 us (outside available range) 1 ie} it) 1 0 0 1 0 -111 16.44 us 1 0 0 1 i) oO i) 1 to 214 —31.7 ps (max. value if FS = logic 1) 0 0 1 tt) 1 oO 1 0 -31.85 1s (outside central counter range if 0 0 1 0 1 0 0 1 FS = logic 1)"* [-216 | -82 us (max. value if FS = logic 0) 0 o +7 0 4 0 0 0 -217 32.148 ys (outside central counter if FS = tt) 0 1 i i) 1 1 1 to logic 0) -256 -37.9 1s (outside central counter) 0 0 Qo 0 Q 0 0 0 Where: * Asign bit, designated A08 and internally set to HIGH, indicate values are always negative. ** The horizontal PLL does not operate in this condition. The system clock frequency is set to a value fixed by the last update and is within + 7.1% of the nominal frequency. Mav 1991 3-591 @™ 7110826 0076477 bob www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification a Digital multistandard TV decoder SAA9051 ee SUBADDRESS 01 Table 7 Horizontal synchronization HSY start time (application dependent) DECIMAL DELAY TIME CONTROL BITS MULTIPLIER (STEP SIZE = 1/13.5 MHz = 74 ns) [at7 [ate] ats [ata [ata] aiz] att] Ato | +191 ~14.2 1s (max. negative value) 1 QO 1 1 1 1 1 1 to +H 0.074 ps 0 0 0 0 0 oO 0 1 -1 +0.074 ps 1 1 1 1 1 1 1 1 to 64 +4.7 js (max. positive value) 1 1 0 0 0 0 0 0 Supaporess 02 Table 8 Honzontal synchronization HSY stop time (application dependent) . DECIMAL DELAY TIME CONTROL BITS MULTIPLIER (STEP SIZE = 1/13.5 MHz = 74 ns) [ a27 | az6 | a2s | a24| aa] az2 | a2t| 20 | +191 -14.2 us (max. negative value) 1 0 1 1 4 1 1 1 to +1 -0.074 ps i 0 ) 0 t) 9 i} 1 [0 [ousreterenoopont’—=SC~=~“~‘~sCC -1 +0.074 us 1 1 1 1 1 1 1 1 to 64 +4.7 us (max. positive value) 1 1 0 () 0 0 0 0 Susappress 03 Table 9 Horizontal clamp HC start time (application dependent) DECIMAL DELAY TIME CONTROL BITS MULTIPLIER (STEP SIZE = 1/13.5 MHz = 74 ns) | aa7 [36 | ass | 94 | a33 | aa2 [agi | A320 | +127 -9.4 us (max. negative value) 0 1 1 1 1 1 1 1 to . +H ~0.074 ps 0 QO 0 0 0 [) 0 1 +0.074 ps 1 1 1 1 1 1 1 1 +9.5 us (max. positive value) 1 0 0 0 0 0 0 0 Mav 1991 3-592 ME 7110826 0076878 Sco www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification a eeeeeeeeeSSSSSSSSFSSSSSSeeEeSeeSeee ee Digital multistandard TV decoder SAA9051 ns Susappress 04 Table 10 Horizontal clamp HC stop time (application dependent) DECIMAL DELAY TIME CONTROL BITS MULTIPLIER (STEP SIZE = 1/13.5 MHz = 74 ns) [ aa7 [Aas [a4s|aga] aaa] aaz]adi| Ado | +127 —9.4 js (max. negative value) 0 1 1 1 1 1 1 1 to H ~0.074 ps 0 0 0 0 0 0 0 1 [0 «| Osrreference point oo 0 0 0 0 0 oO -1 +0,074 ps 1 1 1 1 1 1 1 1 to -128 +9.5 [1s (max. positive value) 1 0 0 0 0 0 0 0 Susaporess 05 Table 11 Horizontal synchronization HS start time after PHI1 (application dependent); 50 Hz; 625 tines (FS = 0) DECIMAL DELAY TIME CONTROL BITS MULTIPLIER (STEP SIZE = 4/13.5 MHz = 296 ns) | a87 | Ase | ass [ a54 | asa as2 | ast | ASO | +127 forbidden; outside available central counter i) 1 1 1 1 1 1 1 to range +109 forbidden; outside available central counter QO 1 1 0 1 1 0 1 range +108 -32 ps (max. negative value) 0 1 1 0 1 1 0 ie) to +1 -0.296 us 0 ie) i} i) 0 i} 0 1 [0 =| Ousreference point 0 0 0 0 0 0 0 0 -1 40.296 ps 1 1 1 1 1 1 1 1 to —107 +31.7 ps (max. positive value) 1 0 0 1 iv} 1 0 1 -108 forbidden; outside available central counter 1 i) tv) 1 0 1 0 0 to range -128 forbidden; outside available central counter 1 0 0 0 0 0 0 9 range Mow 1004 3-593 @ 7110826 0076879 469 a www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification cae Digital multistandard TV decoder SAAQ9051 Table 12 Horizontal synchronization start time after PHI1 (application dependent); 60 Hz; 525 lines (FS = 1) DECIMAL DELAY TIME CONTROL BITS MLTR | (STePsme=a%ssuna=2s6ne) [sz] ase] ate] ast] Ase] asa] Ast] a0 +127 forbidden; outside available central counter 0 1 1 1 1 1 1 4 to range +107 forbidden; outside available central counter 0 1 1 i} 1 0 1 1 range +106 -31.8 us (max. negative value) 0 1 1 () 1 t) 1 0 to . +H —0.294 ps 0 0 0 0 0 0 0 1 [0 ]Ousveteencepont—=S=SC~C~“~ir COCO -1 +0.294 ps 1 4 1 1 1 1 1 1 to -107 +31.5 ss (max. positive value) 1 0 0 1 o 1 is) 1 -108 forbidden; outside available central counter 1 0 0 1 o 41 Q ) to range 128 forbidden; outside available central counter 1 i) 0 0 0 0 0 0 range Programming IDEL, HSY,HC and — «_‘t,; processing time of DTO2 and © HSY stop time =t,, — b HS the DAC (LL3 clock cycles) The variables IDEL, HSY, HC and * t; chrominance bandpass and Programming range of HSY HS are programmed using data gain control stage delay times starl/stop time: +191 to -64 words via the l?C-bus. In the © {ogc} clock generator circuit delay (LL3 clock cycles). following examples a decrease in time value corresponds to an increase in © tyooi analog-to-digital converter HC . delay time Referring to Fig.10 point (1) and IDEL (SEE Fic.9) © typ; input switch detay time. periods c and d: The IDEL data word compensates As delay t, and t, are known + HC starttime = t,, - ¢ for the time delays in data constants, tiog, is programmed in the (LL3 clock cycles) processing between loop fitter 2, range of -115 to -214/216 LL3 clock « HC stoptime=t,, - d quadrature demodutator and cycles, as follows: (LL3 clock cycles) internai/external (system) signal © tog =-115 - 0.5 Pr . i" = . rogramming range of HC start/stop paths. The intemal delay (tres) iS the (* - toge — taoc ~ tw) time: +127 to -128 (LL3 clock period required for INC1 to pass . cycles). from loop filter 2, through the * Value to be fixed. 'ycles). divider and DTO1. This delay Hs corrects the relationship between HSY the subcarrier frequency and the line Referring to Fig.10 point (1) and The HS reference positions in PAL frequency. The external path is a periods a and b: and NTSC modes are shown in result of the following time delays Fig.10 at points (3) and (4) (time delay is given in term of LL3 © HSY start time =t, - a respectively. To move the HS pulse clock cycles): (LL3 clock cycles) to the centre of blanking pulse BL I i i 5 © tei programmable delay time the following equation is used Afaw 1004 3-594 @E 7110826 00768480 140 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification —_— OOS Digital multistandard TV decoder SAA9051 SK SSSSSSSSSSSSSSSSSSSSSSSSSSSSS * HS (NTSC): Programming of the luminance which can be programmed (zero Position of HS relative to the path of the S-DMSD 388 Matz (NTEC) bythe co trol bit Zero point (LL3 clock cycles) The VBS (without chrominance) or : iz (NTSC) by the con! 4LL3 clock cycles CVBS input signal enters the YPN. Bit BY activates the bypass . function for the Y/G mode of the © HS (PAL); Prefilter (a high-pass transfer S-DMSD. The chrominance trap : i function with maximum gain of - " + position of HS relative to the 9.5 dB). The control bit PF switches output signal is then divided into zero point (LL3 clock cycles) ° ). . ‘ontro! c three Channels as described in 4LL3 clock cycies the fiter into the bypass mode. The ection ‘Luminance path’, next stage is the chrominance trap . The length of HS is 64 LL3 clock cycles. May 1991 3-595 Mi 711082eb 0076841 017 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification si ES ne Digital multistandard TV decoder SAA9051 ee ' > = 1 i i 1 - ao 4 § Plog 3 BE 4 es buts Zz 2: 8 8258 Fey 2g ars ae] |? 8 z a ir

23 Be aoe 8 g

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Philips Semiconductors Product specification ———$ SSS Digital multistandard TV decoder SAA9051 SSSSSSSSSSsSSSSSSSeSee T | 8 ; oo 3 3| - i Co g¢ pf | | 23 | | i | BS | i : es Pres = O43 | H 2 | os i H = 2% :

1 H o * 5

7 i : j so 3 el o H 3 . #8 i : 3 ee] 8 | (} qe 8 3 | | 23 3 i z | i { t aoe © ils | a4 + of | f° ets i 2 - € = [oe e || 558 | 28 a 2 ge] |8 238 8 ae | 2523 SE 8 z | i {| £228 TT = =| 2268 B) 8, t t ZEnS8 css @s2a Seas Al g — & ® 2 3 a ¢ foe Es Soe of! z- «$2Se32 g g 2 8 $ 838 Z & eB eaetstt é gf: 4 & E 5 BSS 2x s sea rE ge ie ® : i fsa igs il pe GE + b g3ebe6 es g e Eg iy cores 8 Hi BE 5 a voy g ES 3 2 5 2 8253 tf 2 2 é >ars88 - g 55828 May 1991 3-597 ME 7110826 0076883 95T ‘ www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification aes eee Digital multistandard TV decoder SAAQ9051 a 4 wee x ES g<i0 pono a nab - 41 i} wl | al | i al i) 8 \\ | | G) a |B 2| Fa 1 5| 3 | & a 9 g L-——~ re a] ° = = = rc rs = < BI g8a 8 g HE a8 a Fy ee EEE : 2 | ey ° vi ° >So g

8 Se c=

3 ge: 3 oad ag ~ 2 ae ic Sse s Sze 2 as g|< N $3 gH} FE 3} 2 = s & asl sé bs rn ia Fe 5 |< E May 1991 3-598 Mi 7120826 0076844 42h ‘www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification Digital multistandard TV decoder SAA9051 _— oS Supaopress 06 Table 13 Chrominance trap select (BY switches the chrominance trap to the bypass mode; YPN selects the notch-frequency) CONTROL BITS CHROMINANCE TRAP BY (SA06, D7) YPN (SAO8, D2) NTSO (58 WE) a [pas Table 14 Disconnecting the luminance prefilter (user dependent) a Table 15 Bandpass control (BP1 and BP2 control the centre frequency of the bandpass filter, see Figs 13 to 16) CONTROL BITS BANDPASS TYPE (CENTRE FREQUENCY) BP2 (SA06, D5) BP1 (SA06, D4) pea wa) ee type 2 (3.8 MHz) a ype 5 (26 WHA) ee [type 4(2.9MH2) Table 16 Coring threshold level (COR1 and COR2 contro} the suppression of low amplitude and high frequency signal components, see Fig. 12) CONTROL BITS THRESHOLD COR2 (SA06, D3) COR1 (SA06, D2) a [comgon(Spisoftepis) <b | Cd conng on (6 bis of 12 Bis) Ss Note The thresholds are related the word width of the bandpass filter (12 bits). Table 17 Aperture correction factor (AP1 and AP2 select the weighting factor K of the high frequency (HF) luminance components, see Fig.11) CONTROL BITS WEIGHTING FACTOR K AP2 (SA06, Dt) AP1 (SA06, D0) a a CO GO May 1991 3-599 MB 7110826 0076885 ?be www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification Digital multistandard TV decoder SAA9051 a ocean bits 4 w ttt tty of + | of] Foret ie Li7 TTT T w TE ET TET | ~64 ~82 0 32 ny 0 (a) for COR2 = 0 and COR1 = 1 (b) for COR2 = 1 and COR1 = 0 (c) for COR2 = 1 and COR1 = 1 Fig.12 Coring stage response. 7z28081 2 —— — io) _ Via rane a Lo NE frequency response (MHz) Fig.13 Magnitude of the frequency response of the unlimited summation signal (combining Channel 1 and Channel! 2); PAL mode; prefilter OFF; Responses 1 to 5 show various comb-filter combinations programmable by bits BP2 and BP1, via the I?C-bus. May 1991 3-600 MB 7110825 OO7b88b bTT ae www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Phitps Semiconductors Product specification $e ees Oo Digital multistandard TV decoder SAA9051 ff — _YK 7228082 12, (eB) 4 . fia fem | \\ [eo ee \\UF W/E — )- =12 a © 2 4 6 a frequency response (MHz) Fig.14 Magnitude of the frequency response of the unlimited summation signal (combining Channel 1 and Channel 2); PAL mode: prefilter ON; Responses 1 to 5 show various comb-filter combinations programmable by bits BP2 and BP4, via the I?C-bus. 2 7z26083 (48) _f a LZ i <1 a \\ [i So | | on i /a=> ae \\ YA ain \\ |_| \\ \\f 7 | ee ee ee 0 2 ‘ 6 8 Irequency response (MHz) Fig.15 Magnitude of the frequency response of the unlimited summation signal (combining Channel 1 and Channel 2); NTSC mode; prefilter OFF; Responses 1 to 5 show various comb-filter combinations programmable by bits BP2 and BP, via the I@C-bus. May 1991 3-601 Mi 7110826 0076487 535 a www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification ple eee Digital muitistandard TV decoder SAA9051 i EEE EEE 7Z28084 2 — zee i) {—~ | @* YA we { inagntuce I< ACS Ls eo \\ 1 f VA | Zo \\ 7 — ire es ie - 125 2 4 . 8 trequency response (MHz) Fig.16 Magnitude of the frequency response of the unlimited summation signal (combining Channel 1 and Channel 2); NTSC mode; prefilter ON; Responses 1 to 5 show various comb-filter combinations programmable by bits BP2 and BP1, via the I?C-bus. Susaporess 07 Table 18 Hue phase (user dependent, see notes 1 to 3) HUE PHASE (deg) CONTROL BITS [an [awe [ae [am [an [am] an | 7 | 7E6I60 a a fo +i|iiftotfo fo fo fo foo fo | [ooo 1 29 | o | o fo fo fo fT eo fo | Notes to Table 18 1. Step size per least significant bit (A70) = 1.4 degree. 2. Reference point for positive colour difference signals = 0 degree. 3. The hue phase may be shifted +180 degrees from the reference point using bit A77, the colour difference signals are then switched from normally positive to negative polarity. May 1991 3-602 MH 7110826 0076448 471 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philps Semiconductors Product specification $$ A SSSSSSSSSSSSSSSshsasaee ees Digital multistandard TV decoder SAA9051 ——SSSSSSeSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSsssFsSssheFeFeFeFFFssSeeF Supappress 08 Table 19 Horizontal clock PLL (application dependent) horizontal clock PLL open, horizontal frequency fixed horzeral ook PLL closed ee Table 20 Field frequency select (system mode dependent) [60He:s25tinemode TP C~=*”

50 Hr; 625:ine mode ee

Table 21 VTR/TV mode select (system mode dependent) FUNCTION CONTROL BIT VTR (SA08, D5) [vTRmode Table 22 Colour on control (system mode dependent) FUNCTION CONTROL BIT CO (SA08, D4) a Table 23 Alternate/non—alternate mode (system mode dependent} FUNCTION CONTROL BIT ALT (SA08, D3) aerate ede (PAL) rr non-aitemate mode (NTSC) ee Table 24 Chrominance trap select and amplitude matching (system mode dependent) CHROMINANCE TRAP CONTROL BIT YPN (SA08, D2) Table 25 Colour carrier frequency control (system mode dependent) CONTROL BITS COLOUR CARRIER FREQUENCY CCFR1 (SA08, D1) | CCFRO (SA08, D0) 4 433 618 75 Hz (PAL-B, G, H, 1; NTSC 4.43) a [9875 6149He(PALM)

3 Ba 05628 He (PALA) rs a

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Philips Semiconductors Product specification Sli cei eT Digital multistandard TV decoder SAA9051 OE Susappress 09 . Table 26 Vertical noise limiter. [SS Funcrion | CONTROL BIT VNL (S09, D7) WNL bypassed re Table 27 Y-output enable (system mode dependent) ouiputs D1 -D7 and BL acive outputs D1 - D7 and BL HIGH-impedance Z-state ee Table 28 Chrominance output enable (system mode dependent) ‘outputs UVO - UV3 active; if CD = logic 1, chrominance signal output; if CD = logic 0, zero signal outputs UVO - U3 HIGH impedance Zale re Table 29 Intemal colour forced ON/OFF (test purposes only) CONTROL BIT Ci (SA09, D3) colourforced ON, FCO=logic1(CD=X)orcolourOFF,ifCO=logic0(CD=X) | 1 i colour OFF, if CO = logic 0 (CD = X) or colour controlled by CD, if CO = logic 1 rr Where: X = don't care. Table 30 Additional output for circuit control [rncrow CONTROL BIT AFCC Suipot FOG = HIGH re output AFCC = LOW [Lo Table 31 Source-select (system mode dependent) output SS0- 863 = HIGH a ee output $50 683 = LOW re May 1991 3-604 MB 7110826 0076890 OcT www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification ee Digital multistandard TV decoder SAA9051 Table 32 Source select (pin and subaddress) CONTROL BIT a SUBADDRESS ‘ AFCO a a a 0A, 05 a 09,00 Susaporess 0A Table 33 Disabling of HSY and HC pulses (system mode dependent) jp FuncTiON CONTROL BIT SYC(SADA, 07 HSY and HC output pulses disabled HSY and HC output pulses enabled Table 34 Chrominance input/output 3-state control CVS ouput ave rr output HiGhmpedance Zia ee Table 35 Chrominance source select FUNCTION CONTROL BIT YC (SAOA, D5) TIC separate nputs ee Table 36 Variable delay compensation of the luminance path (YDLO - YDL2 control the luminance delay in order to compensate different chrominance delays throughout the system) CONTROL BITS (SAQA, D2 .. DO) DELAY (N =) a a a a a OO a a | Notes to Table 36 1. The delay is given in terms of clock cycles: 2. 13.5 MHz = N x 74 ns. May 1991 3-605 M@ 7110426 0076891 Thh www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification slik ele lebred leet neo od oes Digital multistandard TV decoder SAA9051 a SUBADDRESS 0B Table 37 SECAM chrominance delay compensation (system mode dependent) betas | __sepcs | scpes| scpes | sones | scoca | sever | scoco_| a a a ODO a OO DCCs Sn OS OO a OO GSO GO (OSU a A SO OD a PC OE SO OO Po TTTCUdOCS Pp eC th fT of Po fo fT a a GG a OD Psd Cd DG SD OD a Notes to Table 37 1. * = Delay in number of LL3 clock cycles. 2. SAOB, D7 don't care. May 1991 3-606 Mm 7110826 0076892 IT2 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification Caterham Digital multistandard TV decoder SAA9051 ee SLAVE TRANSMITTER ORGANIZATION Slave transmitter format ‘stat acknowledge: no acknowledge condition y trom siave ! é ’ Ld is] sxcmons: || a AG 110] 010] 4 4SAj4 MBASS9 i condition Fig.17 Siave transmitter format (a general call address is not acknowledged). The format of data byte 1 Is: Table 38 a ponnes | moox [1 | ro [0 | o | oj 0 | Data bits DO, D3 and D5 are fixed in slave transmitter byte. Table 39 Description of data byte 1

DESCRIPTION

PONRES Status bit for power-on-reset (RES) and after a power failure. logic 1 after the first power-on-reset and after a power failure Aiso settologic 1 after a severe voltage dip that may have disturbed slave receiver data in the PAL/NTSC decoder (SAA9051). PONRES sets all data bits of control registers 1 and 2 to zero. logic 0 after a successful read of the PAL/NTSC decoder status byte HLOCK Status bit for honzontal frequency lock (transmitter identification, stop or mute bit): logic 1 if horizontal frequency is not locked (no transmitter available); logic 0 if horizontal frequency is locked (transmitter received) FD Detected field frequency status bit: logic 1 when received signal has 60 Hz synchronization pulses; logic 0 when received signal has 50 Hz synchronization pulses cD PAL/NTSC colour-detected status bit: logic 1 when PAL/NTSC colour signal is detected; logic 0 when no PAL/NTSC colour signal is detected cs SECAM colour-detected status bit: logic 1 when SECAM colour signal is detected; logic 0 when no SECAM colour signal is detected. May 1991 3-607 @@ 7110826 0076493 635 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification eae) Digital multistandard TV decoder SAA9051 en Defauit coefficients set for the analog-to-digital converters. The The slave addresses are as follows: S-DMSD and SAAS056 3-state outputs of the chrominance © S-DMSD; 8A or BE The default coefficients are set for ADC are controlled by the SS3 . aan switch in this example (all numbers. * SAA9056; BA or BE operation with the TDA8703 or are hex values) TDA8708, these devices are ° Table 40 Slave address (SAA9051 part) SUBADDRESS | FUNCTION | SHORT DELAY LONG DELAY foo ifinccdeley SEE [oe [HY stop [os [HC sat [oe | HE stop : fos HS sta [oe «| He peeaking 02 (62 NTSC) 02 (62 NTSC) [or [HUE contr ce foe ——deonort————=*dS PNT) 38 (7NTSO) foo Jeon? Side SSSSC«*dS (08 SECA [oa |eontors______| 8 (@8 WE oc 58 (28 VIC mee) Notes to Table 40 1. Subaddress 05; application dependent. 2. Subaddress 08; HPLL is in the VTR mode. Hex value for TV mode is 18 (57 for NTSC). Table 41 Slave address (SAA9056 part) tuminance delay CO - FF [2 burt gate sia [esd burst gate stop [se a a a Ce CCE) May 1991 3-608 MB 7110826 0076894 775 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification Digital multistandard TV decoder SAA9051 Table 42 Operating modes of the S-DMSD [iweur [er | ve [ssa] ce [coo] wav vow [ev] re | aur [orn | corno | REWARKS | [eves [1(0) | 0 [1m] o Jew) [ea] o Totot + | oo [oo To we [o[fifofo fa Ja jon Pitot s+ | o Po P| jovas [i | o [rm]o fem fem | i Pot+t +f o Ts tT | we Tojfsfofofa Ja fopvititafo Ta tT [eves [rio { o [i@] o few faa] o Tofot ss Ti Too 7 we Jota fofofa ja jo Pitot s Tt Po P| Ser PRL Ee oe Be ve [ofolo]1 [sje jos] o fom jom om |__| CVBS | 1 (0) 1(0)| 0 |B(A) | B(A) use FS = 4 for 60 Hz vertical frequency YIG A O(1) 1 use FS = 1 : for 60 Hz vertical frequency oves [TO] 0 [TOL few sm] +][o]+]o, +]ay | we [otiftofofa ja fopitipofa pa ft Notes to Table 42 1. SS3 is assumed to control the 3-state output of the chrominance ADC (active LOW). 2. To avoid data collision care must be taken with the programming of CT and SS3 (in this equal they are always equal). Where: A= short time delay B = long time delay. May 1991 3.609 @@ 7110826 0076895 £01 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification ee eee Digital multistandard TV decoder SAA9051 a g 2 a8 FE use vse ese 332 $33 338 3 we Fs & 3_ Jeet a5 eg = & 338 28 33 § ze 38 3 be $ =* € = 8 § gg 3 ivf Zo a gz Fi 3 Fi 38 2 z £ 38 2 28 = 88 rs 38 z 5 8_.|3 23 3 5 5? [BBR * 8 8 : 3 é oO 8 5 9 © 2 2 & g ° ‘J ef] ze elf] ¢& S320 as g°3| 82 2°8 gf 8 & re) May 1991 3-610 @™ 7110826 OO7b89b 54d ‘www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification Digital multistandard TV decoder SAA9051 > 3 33 u5g e565 #5 Z—jeee| SSE) E+ieee 3038 388 38 7 5 8 zee ge Pe Z zs ou £ #5 £8 D gt 2 Ea > a oO gol z 5¢ 2 - 5 3 z 3 32 = = o °o z 38 “ gs z a8 3 ¢ = | g zzsls? , gqizl2! : & 5” [B8E|E2 @ s| 2 Es 5 <q P g g A A t t $ 3 May 1991 3-671 Wi 711082b 0076897 444 ‘www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification PRMpS SOMICONCUCIOTS Eee Digital multistandard TV decoder SAA9051 a 3 < Hy z 3 5 3 3 82 3 > 53 bed N FY s wee woe wee 388 508 3338 5 cf

2 ES¢ 2 ”

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Philips Semiconductors Product specificaton —_— Digital multistandard TV decoder SAA9051 ee

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Philips Semiconductors Product specification ee Digital multistandard TV decoder SAA9051 ae ? : A 3 2 ai 5 8 38 i By ese eoe Wee 238 333 S22 z w z 2 8_ Eee as ee 3 & [38a 28 38 € #8 28 Q 8 2? g = |& wg 2 3_,| 3 Fe g 2 2 Ze no @ |8 38 : = sa 3S § @ Pr & ra) i] N 3%5/2 : 2 ERE e 2 . 3|* Fe 3 : 5 3 i | BEN a a g 8 s ge SZEl 382 5£E\\, 8 2°3| ge 2°8 t 1 g Fi is B 2 > g 3 May 1991 3-614 ° M@™ 7110826 0076900 579 a ‘www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification Digital multistandard TV decoder SAA9051 as LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134) Wis ree a iv [input votagerange SCO [Vo extputvotage range iow = 20mA operaing arent temperature range | (io ‘foto —*d [ian [storage temperature ange «| —S~w 88 ids HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it 1s good practice to take normal precautions appropriate to handling MOS devices (see ‘Handling MOS Devices’) . May 1991 3-615 M@ 7210826 0076901 735 mf www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification ete Digital multistandard TV decoder SAA9051 SS CHARACTERISTICS Vp = 4.5 V to 5.5 V; Tarp = 0 to +70 °C; unless otherwise specified [Ven [soppy votage Ls es to [suppiyeurent_——SSSSS—idote «dO 00 [mv Ve ens 2-4 6-17, Sede | CS CO CR CL CO RC Wa [pine 2-4.6-17,20-25, sande [em [Vw [pnsaaaoangay TS [oo i [ons2-46-17, 20-23, 0-a, oars] OCA INPUT CAPACITANCE [oping eo er [_[pne 2-3, 14-17,20-@aoandes | «didi CG HIGH-impedance| 75 pF Z-state Output votTace LOW Vow pins 6 - 13, 24 - 26, 29 - 32, 42,45 -50,53, [Iq =2.0mA v 55 - 58, 65 - 66 and 68 Wa [pre doandaiSSSCSCS~d ACC Output voitace HIGH Vou pins 6 - 13, 24 - 26, 29 - 32, 42, 45- 50,53, | !4,=-0.5mA Voo. v 55 - 58, 65 - 66 and 68 to _[pins 48-50, 50 and 65-8 CC Vacs) | output voltage (peak-to-peak value) RLZIOKACL Jy 9 v <15pF poe _lowtme verve ag fe |b | Timing (see Fig.23) LLB cycle time [ees feo ns Heavies | cy actor ere [ist [UL ris and fal nes a lovee [iputdatasetupime SSS Sd May 1991 3-616 M@™ 7210826 00765902 b7) www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification Sn ee eter Digital multistandard TV decoder SAA9051 | SYMBOL PARAMETER conpmion | min. | Typ | MAX. | UNIT | Timing (see Fig.23) input data olde a CC CC Tbe [outputdetanoigtme | bo output data delay time except HSY and HC; 50 C, =25 pF, log = 2.0 mA; Von = 22V ty HSY and HC output delay time C, = 25 pF; loc = 2.0 mA, Von = 2.6 V Crystal oscillator (see Fig.20) fh, nominal frequency | third harmonic - 24 676 [- [MHz | ih _|permssive devatonoth Sidi [sTit, [temperature deviation fromfy | faz x toe [| [Corn lad eapactance ee CCC R__|manrmum resonanceressiance | ——SSSSC*iSCid id G.__|metoralapactace «|i id id Co parallel capacitance [|- | 3.5 +20% i; [pF Notes to the characteristics 1. Inputs LOW and outputs not connected, Vj, = 5 V. 2. 4-bit tnangular waveform clocked at 24 576 MHz, AC coupled at pin 36. 3. Rising and falling edges of the clock signal are assumed to be smooth e.g due to roll-off low-pass filtering. { 2 a Purchase of Philips’ °C components conveys a license under the Philips’ |2C patent to use the | LL components in the |?C-system provided the system conforms to the I?C specifications defined by UA Philips i (Bus) May 1991 °y 3-617 mM 7120826 0076903 508 mm www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Philips Semiconductors Product specification Ee Digital multistandard TV decoder SAA9051 nn —24v clock LL3 15v o8v aol | bee ae] le -e|tsu ew ae YYy 2ov l= 'on YY 22v 7228090 Fig.23 Timing diagram. 6 8pF H 24 576 MHz am JU xm ees Watz (310 harmonic) ‘SAA9051 SAA9051 yi PF XTALI | 4, XTAL | 4, 10 pH ° £20% MBABSO + 1 nF Bs @) ©) Fig.24 Oscillator circuit requirements; (a) with quartz crystal; (b) with extemal clock. May 1991 3-618 MB 7110826 0076904 444 ml www.chipdocs.com Be sure to visit ChipDocs web site for more information.