SAA7283GP

SAA7283 PHILIPS | Alldatasheet

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Preliminary specification File under Integrated Circuits, IC02

1996 Oct 24

Terrestrial Digital Sound Decoder (TDSD3)

1996 Oct 24 2

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283

FEATURES

• Single-chip solution including FM and vision filters, analog demodulator and audio switching
• Dual standard with automatic selection between PAL system I and BGH including French NICAM L system)
• Single low-radiation crystal oscillator for improved EMC
• Stereo bitstream audio DACs
• Programmable attenuator for matching levels of NICAM and FM audio sources at the output of the device
• Full EBU NICAM 728 specification demodulation and decoding
• Digital Audio Interface conforming with EBU/IEC 958
• Automatic mute function which switches from NICAM to FM sound when NICAM fails
• Compatible with either single-ended or differential DQPSK input signals
• Microcomputer controlled via I2C-bus (up to 400 kHz specification).

APPLICATIONS

• Television receivers
• Video cassette recorders. GENERAL DESCRIPTION The SAA7283 is a NICAM receiver solution, developing the well established high quality Terrestrial Digital Sound decoder family from Philips Semiconductors. This innovative IC with analog front-end, offers more impressive features and flexibility with minimum external circuitry. The SAA7283 takes, as input, a second IF (intercarrier) Terrestrial TV PAL signal, and performs all the Differential Quadrature Phase Shift Keying (DQPSK) demodulation, digital decoding and digital-to-analog conversion necessary to produce a complete NICAM receiver on a single integrated circuit. The demodulator function includes integrated baseband filters for pulse shaping and unwanted signal rejection, automatic gain control, a low jitter integrated VCO, digital monostable for precise data sampling points and a multi-standard controller to enable automatic locking to either a PAL system I or PAL system BGH input signal (including French NICAM L system). The decoder function performs the descrambling, de-interleaving and reformatting operations required to recover the original data words. The data words are processed through a stereo digital filter, digital de-emphasis network, second order noise shaper and 256 times oversampling Bitstream audio DAC. The SAA7283 then provides a switching output buffer for selecting between FM, NICAM and daisy-chain inputs, and a programmable level attenuation matrix for matching levels of the FM and NICAM audio sources at the output of the device. An additional feature is the inclusion of a Digital Audio Interface (DAI) output IEC 958, which may be disabled if required.

ORDERING INFORMATION

SAA7283ZP SDIP52 plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1 SAA7283GP QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm); body 14× 20 × 2.8 mm SOT319-2

1996 Oct 24 3

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDD supply voltage 4.5 5.0 5.5 V IDD supply current − 205 − mA fclk clock frequency − 8.192 − MHz Tamb operating ambient temperature −20 +25 +70 °C

1996 Oct 24 4

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 BLOCK DIAGRAM handbook, full pagewidth QUADRATURE MIXERS, BASEBAND FILTERS AND AGC GAIN STAGE MGB464 PORT2 ADSEL DOBM SDA SCL DATAOUT EXTR FMR PCLK OPR DATAIN OSC XTAL CLKLPF OPL FML EXTL PORM PORA REMVE PKDET REMO CEYE SEYE COFF SOFF DQPSK MIXREF VCLK VCONT VDDD VSSD VSSX VSSF2 VDDF2 VRCF IREF VROF V DDF1 V SSF1 VSSDAC VROA VRCA VSSA VDDA MUTE RESET SAA7283GP COSINE SINE CARRIER LOOP PHASE DETECTOR AND DATA SLICERS AGC CONTROLLER BITRATE CLOCK RECOVERY CARRIER LOOP QUADRATURE VCO CRYSTAL OSCILLATOR I C2 DAI DIGITAL FILTER, GAIN, J17 DE-EMPHASIS NOISE SHAPER (RIGHT CHANNEL) BITSTREAM DAC (RIGHT CHANNEL) OUTPUT SWITCHES AND BUFFER (RIGHT CHANNEL) NOISE SHAPER (LEFT CHANNEL) BITSTREAM DAC (LEFT CHANNEL) OUTPUT SWITCHES AND BUFFER (LEFT CHANNEL) NICAM 728 DECODER AND DEVICE CONTROLLER 11 4 (1) 29 28 Fig.1 Block diagram (QFP64). (1) Represents controller bus.

1996 Oct 24 5

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 PINNING SYMBOL PIN

DESCRIPTION

SDIP52 QFP64 (1) MUTE 1 57 active LOW mute input; function defined by MUTEDEF (control bit in the I2C-bus register) DOBM 2 59 digital audio interface output that can be 3-stated via I 2C-bus VDDA 3 61 analog supply voltage for the audio channels VSSA 4 62 analog ground connection for the audio channels VRCA 5 63 internal audio reference voltage buffer (high-impedance node) EXTR 6 2 external analog input to the right audio channel FMR 7 3 FM sound input to the right audio channel OPR 8 4 analog output from the right audio channel n.c. 9 and 10 9 and 10 not connected; left open-circuit in application V ROA 11 7 internal audio reference voltage buffer output VSSDAC 12 8 quiet ground connection to DACs n.c. 13 and 14 − not connected; left open-circuit in application OPL 15 11 analog output from the left audio channel FML 16 12 FM sound input to the left audio channel EXTL 17 13 external analog input to the left audio channel PORM 18 14 active LOW power-on reset mute input; mute cleared by setting silence bit HIGH in I2C-bus (internal pull-up) PORA 19 15 power-on reset audio select input (internal pull-up) REMVE 20 16 carrier loop-filter connection REMO 21 17 carrier loop-filter output SEYE 22 21 sine channel eye pattern output for monitoring SOFF 23 22 sine channel offset compensator capacitor output V SSF1 24 23 demodulator ground connection 1 VCLK 25 24 carrier loop VCO clock output for monitoring V DDF1 26 25 demodulator supply voltage 1 VCONT 27 27 carrier loop VCO control voltage input MIXREF 28 28 mixer voltage reference or input when using differential DQPSK signal DQPSK 29 29 DQPSK input signal COFF 30 30 cosine channel offset compensator capacitor output CEYE 31 31 cosine channel eye pattern output for monitoring PKDET 32 34 AGC peak detector storage capacitor output V ROF 33 35 internal demodulator reference voltage buffered output IREF 34 36 internal demodulator reference current output VRCF 35 37 internal demodulator reference voltage unbuffered output VDDF2 36 38 demodulator supply voltage 2 VSSF2 37 39 demodulator ground connection 2 n.c. 38 40 not connected; left open-circuit in application CLKLPF 39 41 clock loop-phase comparator output

1996 Oct 24 6

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 Note 1. Pins 1, 5, 6, 18, 19, 20, 26, 32, 33, 51, 52, 58, 60 and 64 are not connected; left open-circuit in application. XTAL 40 42 8.192 MHz crystal oscillator input OSC 41 43 8.192 MHz crystal oscillator output V SSX 42 44 crystal oscillator ground connection DATAIN 43 45 serial data input at 728 kbits/s to decoder V SSD 44 48 digital ground connection PCLK 45 47 728 kHz output clock to DQPSK demodulator V DDD 46 49 digital supply voltage RESET 47 50 active LOW power-on reset input DATAOUT 48 46 serial data output at 728 kbits/s from DQPSK demodulator SCL 49 53 serial clock input for I 2C-bus SDA 50 54 serial data input/output for I 2C-bus ADSEL 51 55 input that defines I 2C-bus address bit 0 (internal pull-up) PORT2 52 56 output that is directly controlled from Port 2 bit in I 2C-bus SYMBOL PIN SDIP52 QFP64 (1)

1996 Oct 24 7

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 Fig.2 Pin configuration for SOT247. handbook, halfpage 13 40 MGB463 PORT2 ADSELDOBM SDA SCL DATAOUT EXTR FMR PCLKOPR n.c. DATAINn.c. OSC XTALn.c. CLKLPFn.c. OPL FML EXTL PORM PORA REMVE PKDETREMO CEYESEYE COFFSOFF DQPSK MIXREFVCLK VCONT VDDD VSSD VSSX VSSF2 VDDF2 VRCF IREF VROF V DDF1 VSSF1 VSSDAC VROA VRCA VSSA VDDA MUTE RESET n.c. SAA7283ZP

1996 Oct 24 8

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 Fig.3 Pin configuration for SOT319. handbook, full pagewidth MGB462 DATAOUT EXTR FMR PCLK OPR n.c. DATAIN n.c. OSC XTAL n.c. CLKLPF n.c. OPL FML EXTL PORM PORA REMVE PKDET REMO VDDD VSSD VSSX VSSF2 VDDF2 VRCF IREF VROF VSSDAC VROA RESET n.c. SAA7283GP n.c. n.c. n.c. n.c. n.c. CEYE SEYE COFF SOFF DQPSK MIXREF VCLK VCONT V DDF1 V SSF1 n.c. n.c. n.c. PORT2 ADSEL DOBM SDA SCL V RCA V SSA V DDA MUTE n.c. n.c. n.c. n.c.

1996 Oct 24 9

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 FUNCTIONAL DESCRIPTION DQPSK demodulation Q UADRATURE MIXERS ,BASEBAND FILTERS AND AUTOMATIC GAIN CONTROL (AGC) The DQPSK signal is fed into two differential input mixers, where it is mixed with quadrature phases generated by the carrier-loop quadrature VCO. The quadrature signals modulated onto the NICAM carrier are thus recovered. The mixers can be driven by either a single-ended or differential source. In single-ended mode, the device is driven directly from the sound IF down-converter into the DQPSK input pin, with the MIXREF pin decoupled. In differential mode, the signal is applied between the DQPSK and MIXREF pins. The outputs from the mixers are then fed into a pulse-shaping filter, and FM/vision filter stage which filters out all interference components, including AM carrier for French NICAM L system. The signal from the filtering stages is then fed into the AGC, which ensures that the phase comparator gain remains constant, irrespective of the input signal level. This is important to maintain the stability of Costas loop PLL. AGC CONTROLLER The AGC controller monitors the I and Q channel signals at the input to the carrier loop-phase comparator and generates a reference voltage to set the AGC output level. E YE BUFFER A differential to the single-ended converter provides the baseband signal as an output at the pins CEYE and SEYE for the I and Q channels respectively for eye-height monitoring. B IT RATE CLOCK RECOVERY The I and Q channels are processed using edge detectors and monostables, which generate a signal with a coherent component at the data symbol rate. The outputs from the I and Q channel monostables are each compared with the clock derived from PCLK (364 kHz nominal), the resultant output is used to derive a 3-state control signal used to control two current sources at the CLKLPF output. This error signal is loop filtered and used to control the master clock oscillator. The bit rate clock, PCLK, and symbol clock are derived from the master clock. NICAM 728 decoding D ECODING FUNCTIONS The device performs all decoding functions in accordance with the EBU NICAM 728 specification. After locking to the frame alignment word, the data is de-scrambled by application of the defined pseudo random binary sequence, and the device synchronizes to the periodic frame flag bit C0. The relevant control information and scale factor word is extracted, and with the integrated RAM the data is de-interleaved and the scale factor word is extracted, and expanded to 14 bits. Parity checking on the eleventh bit of each sample word is carried out to reveal any sound sample errors, which if detected are flagged, with the last good sample being held. Automatic muting Enable when AMDIS = LOW. The I 2C-bus section has two registers which define an upper and lower limit for the automatic muting function. When the number of errors within a 128 ms period exceeds the number stored in the upper error limit register, then the automatic muting will switch the device output to the FM input, (dependent on the relevant control bits in the I 2C-bus) and mute (set to zero) the data input to the filter (in that order). When the error count in a 128 ms period is less than the value stored in the lower error limit register then the data into the filter is uninterrupted, and the device output is switched back to the DAC (dependent on the value of the relevant control bits in the I 2C-bus). During the muting operation the open-drain pinMUTE is pulled LOW and the AM bit in the status-byte is set HIGH. Figure 4 shows the dependency of the automatic muting function on error_count, RSSF, C4OV, output state and application mode. The automatic muting function, if enabled, will override user mute via the MUTE pin/bit. When the transmission is DATA format or currently undefined format (C3 = logic 1) the device will automatically switch to the FM inputs regardless of RSSF/ C4OV states, and whether the automatic muting function AMDIS is enabled or disabled.

1996 Oct 24 10

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 User mute The error counter is an 8-bit counter which locks at count 255. The counter is reset and its output sent to the I 2C-bus every 128 ms. This enables the user to interrogate the number of errors occurring within a 128 ms period. The user can then mute the device by pulling pin MUTE LOW (this function is also provided by theMUTE bit in the I2C-bus) or setting SILENCE bit LOW in I2C-bus to switch input of audio switching buffers to analog ground. Switching buffers The analog switches select between the output of the DACs, the FM input and an external input (EXT). Switching is controlled by bits in the I 2C-bus and internal switching function. The external analog inputs should be ≤1.1 V (RMS) at the input pin, and the output buffers have a voltage drive of 1 V (RMS). NICAM/FM audio level matching Differing audio headroom and alignment levels occur between systems I and BGH, due to the differing systems and broadcast standards. In order to match the NICAM and FM audio output levels without requiring application changes, the device will automatically switch in 4.6 dB attenuation network in the NICAM path for system BGH (this can be disabled by setting the NICLEV bit LOW in I 2C-bus). A programmable attenuation network in the FM path only, controlled by bits in I2C-bus, provides additional flexibility for user to match FM and NICAM audio levels (see Table 9). Power-on reset state Two pins control the initial set-up of the device during power-on reset. PORA (Power-On Reset Audio) When pulled LOW the device will be configured with a 12 dB gain in the oversampling filter and the C4OV bit in the I2C-bus will be set HIGH. This pin when HIGH will configure the device with a 6 dB gain in the oversampling filter and will set C4OV bit in the I2C-bus LOW. PORM (Power-On Reset Mute) This pin when LOW will mute the output of the device at power-on by setting the SILENCE bit in the I2C-bus LOW. To put the device back into a normal mode of operation the SILENCE bit in the I 2C-bus must be set HIGH.

1996 Oct 24 11

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 Fig.4 Flow diagram showing SAA7283 automatic muting function. (1) Indicating that a mute may occur when user returns to NICAM source. handbook, full pagewidth MGB465 DUAL MONO MODE LEFT = RIGHT = M1 SELECTED SOUND APPLICATION DUAL MONO ERROR_COUNT ERROR_MAX EXT or FM INPUT SWITCHED IN C4ov BIT = 0 Output is unchanged AM bit = LOW MUTEB pin = HIGH Output is unchanged AM bit = HIGH MUTEB pin = LOW (1) (1) RSSF = 1 Output is switched to FM input AM bit = HIGH MUTEB pin = LOW Output is unchanged AM bit = LOW MUTEB pin = HIGH Output is unchanged AM bit = LOW MUTEB pin = HIGH NO NO NO NO YES YES YESYES YES NO NO YES When error_count is less than error_min, the output is switched back to NICAM and AM bit = LOW, MUTEB pin = HIGH When error_count is less than error_min, AM bit = LOW, MUTEB pin = HIGH

1996 Oct 24 12

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 I2C-BUS FORMATS The SAA7283 contains an I2C-bus slave transceiver (up to 400 kHz) permitting a master device to:

• Read decoder status information derived from the transmitted digital audio signal
• Read an error count byte to determine the bit error rate for user mute purposes and to indicate quality of NICAM signal
• Write control codes to select PAL I or PAL BGH configurations
• Write control codes to select the available analog switching configurations
• Write upper and lower error count limits for automatic muting function
• Read additional transmitted data bits. Their purpose has yet to be defined but accessibility is provided to allow future services to be implemented in receiver software. I2C-bus slave address An address select pin (ADSEL) is provided to allow selection of one of two different slave addresses. The logic state of the ADSEL pin is reflected in the least significant bit of the I2C-bus slave address. Slave address = 101101X (R/W) [ADSEL = 1, address = B6 (R/W) ADSEL = 0, address = B4 (R/W)]. Table 1 SAA7283 slave address The SAA7283 does not acknowledge the I2C-bus general call address. Slave receiver format The slave receiver format is shown in Table 2. Table 2 Slave receiver format Table 3 Explanation of Table 2 The sub-address is auto-incremented by the SAA7283, for each data byte received. When the sub-address is equal to 04 (HEX), on reception of the next data byte, the sub-address will reset to 00 (HEX). BITS A7 A6 A5 A4 A3 A2 A1 A0 1 0 1 1 0 1 selected by ADSEL read/write START slave_addr ACK sub_addr ACK data_byte ACK n-bytes data_byte ACK STOP ITEM DESCRIPTION START I 2C-bus start condition Slave_addr 101101XW X logic 0 when ADSEL = 0; logic 1 when ADSEL = 1 W logic 0, I 2C-bus write to slave receiver ACK I 2C-bus acknowledge condition generated by slave receiver Sub_addr sub-address range 00 to 04 (HEX) Data_byte data byte transmitted to slave receiver STOP I 2C-bus stop condition

1996 Oct 24 13

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 I2C-bus slave receiver register map Table 4 Slave receiver data byte SUB-ADDRESS D7 D6 D5 D4 D3 D2 D1 D0

000 M1/ M2 DMSEL SSWIT3 SSWIT2 SSWIT1 PORT2 MUTEDEF AMDIS

001 EMAX7 EMAX6 EMAX5 EMAX4 EMAX3 EMAX2 EMAX1 EMAX0

010 EMIN7 EMIN6 EMIN5 EMIN4 EMIN3 EMIN2 EMIN1 EMIN0

C4OV MUTE SILENCE DAIE FM3 FM2 FM1 FM0

100 ASYS BG/ I NICLEV STLOCK −−−−

This bit selects either mono channel M1 or M2 to be the output on the left and right channel dependent on the transmitted control bits C1 and C2 indicating a mono transmission and the value of bit DMSEL (see Table 5). Power-on resets to logic 1. DMSEL DMSEL is the dual mono selection bit, for transmissions consisting of two independent mono signals. Selection is in conjunction with M1/ M2 (see Table 5). Power on resets to logic 0. SSWIT1, SSWIT2 AND SSWIT3 These bits control the analog switching, selecting between the FM, external, and NICAM signals. With the NICAM source the signals select whether the de-emphasis is performed and what gain is applied after the filtering and de-emphasis stage. The signal states and their meaning are listed in Table 7. Power-on resets to 010 with PORA pin HIGH, and to 011 with PORA pin LOW. PORT2 PORT2 controls a bit out, providing direct access to a dedicated output pin (PORT2) via the I 2C-bus. See Table 6. Power-on resets to logic 0. MUTEDEF This defines the operation of the user definableMUTE pin orMUTE I2C-bus bit when it is pulled LOW externally or set LOW in the I2C-bus respectively. When this bit is HIGH, pulling theMUTE pin/I2C-bus bit LOW will mute (set to zero) the digital data and switch the output to the FM input, depending on relevant control bits (see Table 8). When this bit is LOW, pulling the MUTE pin/I2C-bus bit LOW will only mute the digital data under the same conditions. Power-on resets to LOW. AMDIS This bit enables and disables the automatic mute function. Power-on resets to enabled = LOW. EMAX7 TO EMAX0 This is the upper error limit register which defines the number of errors in 128 ms period which will cause automatic mute to switch IN. User definable, but power-on resets to 50 (HEX). EMIN7 TO EMIN0 This is the lower error limit register which defines the number of errors in 128 ms period which will cause automatic mute to switch OUT. User definable, but power-on resets to 14 (HEX). C4OV When set LOW this bit overrides the status of the transmitted C4-bit when muting. When this bit is HIGH muting takes place in accordance with EBU specification. Power-on resets to HIGH when the PORA pin is held LOW during power-up, and power-on resets to LOW when PORA is HIGH. MUTE This reflects the function of the MUTEB pin. When this bit is set LOW the external MUTEB pin is pulled LOW and the action is dependent on the MUTEDEF bit (see Table 8). Power-on resets to HIGH. SILENCE When set LOW this bit silences the outputs of the device by switching the input of the audio switching buffers to analog ground. When the PORM pin is held LOW at power-on reset the silence bit is initialized to zero. With PORM bit HIGH the silence bit is initialized HIGH.

1996 Oct 24 14

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 DAIE When set HIGH this bit switches in the Digital Audio Interface output to the DOBM pin. When set LOW the DOBM output is 3-stated. Power-on resets to HIGH. FM3 TO FM0 These bits set the level of attenuation of the FM audio signal (see Table 9). Power-on resets 0000 = 0 dB attenuation. ASYS When this bit is HIGH it activates the automatic standard switch mode. When set LOW, the standard must be set by the BG/ I bit. Power-on resets to HIGH. BG/I When this bit is HIGH it switches the DQPSK demodulator to system BGH and attenuates the digital audio level by 4.6 dB (if NICLEV is set HIGH). When LOW, the DQPSK demodulator switches to system I (with no 4.6 dB attenuation). Power-on resets to HIGH. NICLEV When this bit is set LOW it overrides the 4.6 dB NICAM audio level compensation, irrespective of whether the device is in automatic or manual system mode. When set HIGH the 4.6 dB compensation level is applied in system BGH. Power-on resets to HIGH. STLOCK When STLOCK is set HIGH it will stop the automatic system switch after the device has achieved an INSYNC condition, should the demodulator lose lock at any time. This minimizes the re-acquisition time. When set LOW the device will be permitted to change system after an INSYNC condition has been reached. Power-on resets to LOW. Table 5 Output as a function of M1/ M2 and DMSEL DMSEL M1/ M2 FUNCTION 0 0 selects DIGITAL; L = M2, R = M2 0 1 selects DIGITAL; L = M1, R = M1 1 0 selects DIGITAL; L = M2, R = M1 1 1 selects DIGITAL; L = M1, R = M2 Table 6 Port 2 control PORT2 PIN OUTPUT STATE

0 LOW

1 HIGH

Table 7 SSWIT signal states and function Note 1. Where X = don’t care. SSWIT3 SSWIT2 SSWIT1 FUNCTION 0 0 0 NICAM source de-emphasis switched out, no gain 0 0 1 NICAM source de-emphasis switched in, no gain 0 1 0 NICAM source de-emphasis switched in, +6 dB gain; power-on reset when PORA = HIGH 0 1 1 NICAM source de-emphasis switched in, +12 dB gain; power-on reset when PORA = LOW (1) 0 external inputs switched in, no change to previous de-emphasis/gain setting

1 X 1 FM inputs switched in, no change to previous de-emphasis/gain setting

1996 Oct 24 15

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 Table 8 Action of pullingMUTE pin/I2C-bus bit LOW Note 1. WithMUTE pin/i2C-bus bit pulled LOW. If user has manually selected FM or NICAM inputs, no switching will occur. Table 9 FM attenuation control Slave transmitter format The slave transmitter format is shown in Table 10. Table 10Slave transmitter format TRANSMITTED C4 BIT (RSSF) C4OV TRANSMISSION MODE OUTPUT ACTION (1) MUTEDEF = 1 MUTEDEF = 0 1 1 or 0 stereo/mono/dual mono with La n dR=M 1 mute digital data and switch to FM mute digital data only 1 1 or 0 dual mono with M2 selected in either Lo rR no action no action 0 1 all modes no action no action 0 0 all modes mute digital data and switch to FM mute digital data only FM ATTENUATION (dB) FM3 FM2 FM1 FM0 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 1 0 1010 1 1 1011 1 2 1100 Not defined 1101 Not defined 1110 Not defined 1111 START slave_addr ACK data_byte ACK n-bytes data_byte ACK STOP

1996 Oct 24 16

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 Table 11Explanation of Table 10 I2C slave transmitter register map The bus master can perform single-byte, two-byte, three-byte, four-byte or five-byte read in the order shown in Table 12. Table 12Slave transmitter data byte ITEM DESCRIPTION START I 2C-bus start condition Slave_addr 101101XR X logic 0 when ADSEL = 0; logic 1 when ADSEL = 1 R logic 1, I 2C-bus read from slave transmitter ACK I 2C-bus acknowledge condition generated by slave receiver Data_byte data byte transmitted from slave receiver ACK master device negative acknowledge to indicate last byte STOP I 2C-bus stop condition BYTE D7 D6 D5 D4 D3 D2 D1 D0 STATUS BYTE 1 PONRES S/ MD / S VDSP RSSF O SA M CFC ERROR BYTE ERR7 ERR6 ERR5 ERR4 ERR3 ERR2 ERR1 ERR0 AD BYTE 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 AD BYTE 1 OVW SAD 0 CI1 CI2 AD10 AD9 AD8 STATUS BYTE 2 C1 C2 C3 BG/ I 0000 PONRES When set HIGH this bit indicates that a power-on reset has occurred. It is cleared after the status byte has been read. S/M This bit gives the stereo or mono broadcast indication. Set HIGH indicates stereo transmission. D/S When HIGH this bit indicates a dual mono broadcast. VDSP When this bit is HIGH, it indicates that the digital data transmission is a sound source. When LOW the transmission is either data or undefined format. RSSF This bit reflects the state of the C4 bit in the NICAM transmission. When set LOW, the FM sound content does not match the digital transmission, and switching to FM by automatic mute or setting MUTE LOW is prevented (ifC4OV = HIGH). O S When HIGH this bit indicates that the device has both frame and C0 (16 frame) synchronization. AM When HIGH this bit indicates that the automatic mute function has switched from NICAM to FM. When LOW the automatic mute function has not activated a switch. CFC When LOW this bit indicates a configuration change at the C0 (16 frame) boundary. it is reset after reading the status byte. ERR7 TO ERR0 These bits indicate the number of errors occurring in the previous 128 ms period. AD7 TO AD0 These bits contain the eight least significant additional data bits.

1996 Oct 24 17

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 OVW This bit is set when new additional data bits are written to the I2C-bus without the previous bits being read. SAD This bit is set HIGH when new additional data is written into the I2C-bus, and cleared by the action of reading the data. CI1 AND CI2 These are the CI bits decoded by majority logic from the parity checks of the last ten samples in a frame. AD10, AD9 AND AD8 These are the three most significant additional data bits. C1, C2AND C3 These are the transmitted control bits, see Table 13. BG/I When set HIGH this bit indicates that the DQPSK demodulator is switched to system BGH. When LOW, indicates that DQPSK demodulator is switched to system I. Indicator bits Table 13 is the truth table for the indicator bits. Table 13Indicator bits functional truth table TRANSMISSION C1 C2 C3 S/ MD / S VDSP OS Stereo 0 0 0 1 0 1 1 M 1 + M 2 0100111 M1 + data 1 0 0 0 0 1 1 Transparent data 1 1 0 0 0 0 1 Any currently undefined combination of C1, C2 and C3 0 0 0 1 Decoder unsynchronized ( OS = logic 0) 0 0 0 0

1996 Oct 24 18

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 DIGITAL AUDIO INTERFACE IEC/EBU 958 Block structure The output is grouped into a block of 192 consecutive frames providing, for each channel the 192 channel status data bits. The start of a block is designated by a special sub-frame preamble. Frame structure Each frame is uniquely composed of two sub-frames. The rate of transmission of frames corresponds exactly to the source sampling frequency. In the 2-channel operation, samples taken from both channels are transmitted by time multiplexing in consecutive sub-frames. Sub-frames related to Channel 1 (left or ‘A’ channel in stereophonic operation and primary channel in monophonic operation) normally use preamble M. However the preamble is changed to preamble B once every 192 frames. This defines the block structure used to organize the channel status information. Sub-frames of Channel 2 (right or ‘B’ channel in stereophonic operation and secondary channel in monophonic operation) always use preamble W. Sub-frame structure Each frame is divided into 32 time-slots numbered 0 to 31. Time-slots 0 to 3 carry one of three permitted preambles. These are used to affect synchronization of sub-frames, frames and blocks. Time-slots 4 to 27 carry the audio sample word in linear two's complement representation. The most significant bit is carried by time-slot 27. Time-slot 28 carries the validity flag associated with the audio sample word. This flag is set to logic 0 if the audio sample is reliable. If set to logic 1 then the sample is unreliable. Time-slot 29 carries one bit of the user data channel. In this application this is not used and so is set to logic 0. Time-slot 30 carries one bit of the channel status word associated with the audio channel transmitted in the same sub-frame. Time-slot 31 carries a parity bit such that time-slots 4 to 31 inclusive will carry an even number of ones and an even number of zeros. Fig.5 Frame format. handbook, full pagewidth MLB155 M channel 1 sub-frame W channel 2 B channel 1 W channel 2 M channel 1 W channel 2 sub-frame frame 0 start of block frame 1frame 191 Fig.6 Sub-frame structure. handbook, full pagewidth MLB156 sync preamble logical 0 bits audio sample word M S B VUCP L S B 40 28 3127 validity flag user data = logic 0 channel status parity bit 31 1 1 2

1996 Oct 24 19

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 Channel coding Time-slots are encoded as biphase mark data. Each bit transmitted is represented by a symbol comprising two consecutive binary states. The first state of a symbol is always different from the second state of the previous symbol. The second state of the symbol is identical to the first if the bit being transmitted is logic 0, however it is different if the bit is logic 1 (see Table 14). Table 14Channel coding Preambles Preambles are specific patterns providing synchronization and identification of the sub-frames and blocks. A set of three preambles is used. These preambles are transmitted in the time allocated to four time-slots and are represented by eight successive states. The first state of the preamble is always different from the second state of the previous symbol. Depending on this state the preambles are as shown in Table 15. PRECEDING STATE 0 1 TRANSMITTED BIT CHANNEL CODING 01 1 0 0 11 0 0 1 Table 15Preambles The preambles preceding each digital audio sample are used to indicate the beginning of a sample as follows:

• Preamble B indicates the start of Channel A data and the beginning of a block
• Preamble M indicates the start of Channel A data but not the beginning of a block
• Preamble W indicates the start of Channel B data. Channel status The channel status information is organized in 192-bit words. The first bit of each word is carried in the frame with Preamble B. The 192-bit word is organized into sections as shown in Table 16. PRECEDING STATE 0 1 PREAMBLE CHANNEL CODING B 11101000 00010111 M 11100010 00011101 W 11100100 00011011 Table 16Channel status codes BIT CODE DESCRIPTION 0 0 consumer 1 0 sound data 2 1 digital copy permitted 3 and 4 00 indicates digital de-emphasis switched in 11 indicates digital de-emphasis switched out 50 − 6 and 7 00 − 8 to 5 00110001 category code 16 to 19 0000 source code (don't care) 20 to 23 0000 channel number (don't care) 24 to 27 1100 sampling frequency (32 kHz) 28 and 29 00 clock accuracy (level II) 30 to 191 all 0s −

1996 Oct 24 20

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 LIMITING VALUES In accordance with the Absolute Maximum Rating Systems (IEC 134). Notes 1. All VDD and VSS connections must be made externally to the same power supply. 2. Electrostatic handling is equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor with a 15 ns rise time. 3. Electrostatic handling is equivalent to discharging a 200 pF capacitor via a 0Ω series resistor with a 15 ns rise time. QUALITY AND RELIABILITY This device will meet Philips Semiconductors General Quality Specification for Business group“Consumer Integrated Circuits SNW-FQ-611-Part E”. SYSTEM PERFORMANCE Bit Error Rate (BER) Table 17 shows input signal conditions which typically produce bit error rates of less than 10−3. Signal levels given in dB are related to the picture carrier reference level (0 dB) and based on the output level of the Philips range of sound IF down-converter ICs. All measurements at 2nd IF (intercarrier) frequencies (NICAM and FM only) using Philips Semiconductors TDSD3 Applications Board. Table 17System performance Acquisition time Maximum acquisition time = 1 s, measured from power-on reset to in-sync condition achieved. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V DDF1 , VDDF2 , VDDA supply voltage (all supplies) note 1 −0.3 +6.5 V VSSF1 , VSSF2 , VSSA ground supply voltage V SSD − 0.5 V SSD + 0.5 V VI(max) maximum input voltage (any input) 0V DD V VO(max) maximum output voltage 0 V DD V IIOK DC input or output diode current −± 20 mA IO(max) output current (each output) −± 10 mA Tamb ambient operating temperature −20 +70 °C Tstg storage temperature −55 +125 °C electrostatic handling Vstat(HBM) Human Body Model note 2 −2 000 +2000 V Vstat(MM) Machine Model note 3 −200 +200 V INPUT SIGNAL CONDITIONS SYSTEM I SYSTEM BG UNIT FM overmodulation [NICAM =−20 dB, FM =−10 dB (I)/−13 dB (B/G)] 170 105 kHz NICAM level with respect to picture carrier (FM deviation =±50 kHz) FM =−10 dB (I)/−13 dB (B/G) −44 −43 dB NICAM carrier-to-noise ratio (NICAM = −20 dB, FM deviation =±50 kHz) FM =−10 dB (I)/−13 dB (B/G) 9 10.5 dB

1996 Oct 24 21

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 CHARACTERISTICS VDD = 4.5 to 5.5 V; Tamb = −20 to +70°C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Digital supplies(note 1) VDDD digital supply voltage 4.5 5.0 5.5 V VSSD digital ground supply voltage − 0 − V IDDD digital supply current − 15 − mA Audio supplies (note 1) VDDA audio supply voltage 4.5 5.0 5.5 V VSSA audio ground supply voltage − 0 − V VSSDAC DAC ground supply voltage − 0 − V IDDA audio supply current − 19 − mA Demodulator supplies(note 1) VDDF1 1st front-end supply voltage 4.5 5.0 5.5 V VSSF1 1st front-end ground supply voltage − 0 − V IDDF1 1st front-end supply current − 46 − mA VDDF2 2nd front-end supply voltage 4.5 5.0 5.5 V VSSF2 2nd front-end ground supply voltage − 0 − V IDDF2 2nd front-end supply current − 125 − mA Digital inputs DATAIN (TTL/CMOS COMPATIBLE INPUT LEVELS ) VIL LOW level input voltage 0 − 0.8 V VIH HIGH level input voltage 2.0 − VDD V ILI input leakage current −10 − +10 µA C i input capacitance −− 10 pF ADSEL, PORM AND PORA (TTL/CMOS COMPATIBLE INPUT LEVELS WITH INTERNAL PULL -UP ) VIL LOW level input voltage 0 − 0.8 V VIH HIGH level input voltage 2.0 − VDD V R i(pu) input pull-up resistance − 50 − kΩ C i input capacitance −− 10 pF RESET AND SCL (CMOS/I2C-BUS INPUT LEVELS WITH SCHMITT TRIGGER ) VIL LOW level input voltage 0 − 1.5 V VIH HIGH level input voltage 3.0 − VDD V Vhys hysteresis − 0.05VDD − V ILI input leakage current −10 − +10 µA C i input capacitance −− 10 pF

1996 Oct 24 22

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 Digital input/output SDA (I2C-BUS LEVELS WITH SCHMITT TRIGGER /OPEN -DRAIN OUTPUT ) VIL LOW level input voltage 0 − 1.5 V VIH HIGH level input voltage 3.0 − VDD V Vhys hysteresis 0.05V DD −− V ILI input leakage current −10 − +10 µA C i input capacitance −− 10 pF VOL LOW level output voltage I OL =+ 3m A 0 − 0.4 V C L load capacitance active pull-up −− 400 pF passive pull-up −− 200 pF MUTE (TTL/CMOS COMPATIBLE INPUT LEVELS /OPEN -DRAIN OUTPUT WITH INTERNAL PULL -UP ) VIL LOW level input voltage 0 − 0.8 V VIH HIGH level input voltage 2.0 − VDD V C i input capacitance −− 10 pF VOL LOW level output voltage I OL =+ 3m A 0 − 0.4 V VOH HIGH level output voltage I OH = −3 mA 2.4 − VDD V C i load capacitance with active pull-up −− 50 pF Zi input impedance − 50 − kΩ Digital outputs PORT2, PCLK AND DATAOUT ( PUSH -PULL OUTPUT ) VOL LOW level output voltage I OL =+ 2m A 0 − 0.4 V VOH HIGH level output voltage I OH = −2 mA 2.4 − VDD V C L load capacitance −− 50 pF DOBM (3-STATE PUSH -PULL OUTPUT ) VOL LOW level output voltage I OL =+ 2m A 0 − 0.4 V VOH HIGH level output voltage I OH = −2 mA 2.4 − VDD V C L load capacitance −− 50 pF ILI 3-state leakage current V I= 0 to VDD −10 − +10 µA ANALOG SECTION (measured at V DD =5V ; Tamb =2 5°C) Demodulator analog references VRCF OUTPUT Vo output signal voltage supply dependent − 0.5VDDF2 − V C i input capacitance −− 10 pF VROF OUTPUT Vo output signal voltage defined by V RCF − 0.5VDDF2 − V C i input capacitance −− 10 pF SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1996 Oct 24 23

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 IREF OUTPUT Vo output signal voltage defined by V RCF − 0.5VDDF2 − V C i input capacitance −− 10 pF Isink output sink current with external 10 kΩ resistor from pin to VSSF2 − 250 −µ A Signal path analog inputs DQPSK AND MIXREF R i input resistance − 12.5 − kΩ ViDQPSK(rms) NICAM input signal voltage Vnom (RMS value) − 43 − mV ViDR AGC range with respect to ViDQPSK +8.5 +10 − dB −25 −30 − dB ViCUM(rms) cumulative input signal voltage (RMS value) note 2 −− 464 mV C i input capacitance −− 10 pF Baseband outputs CEYE AND SEYE Vo(p-p) eye pattern output signal voltage (peak-to-peak value) in-lock; note 3; system I − 1.25 − V in-lock; note 3; system B/G − 1.79 − V VI/Q channel matching 20log 10 (VCEYE /VSEYE ) −2 0 +2 dB COFF AND SOFF VO offset compensator DC output voltage defined by VRCF − 0.5VDDF2 − V Baseband filters SYSTEM I Afo pass band cut-off attenuation fi= 6552 MHz + 182 kHz 1.9 3.1 4.6 dB FMr FM rejection f i= 6.0 MHz ± 50 kHz − 65 − dB FMomr FM rejection (overmodulated FM) f i= 6.0 MHz ± 80 kHz 45 50 − dB CCr colour-carrier rejection f i= 4.43 MHz − 78 − dB SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1996 Oct 24 24

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 SYSTEM BGH Afo pass band cut-off attenuation fi= 5850 MHz + 182 kHz 1.7 3.1 4.5 dB FMr FM rejection f i= 5.5 MHz ± 50 kHz − 50 − dB AMr (SECAM) AM rejection (for SECAM L system) fi= 6.5 MHz − 56 − dB FMomr FM rejection (overmodulated FM) f i= 5.5 MHz ± 80 kHz 25 30 − dB CCr colour-carrier rejection f i= 4.43 MHz − 73 − dB Baseband demodulator output REMO Vo output voltage limits 0.2 − VDD − 0.5 V Kp carrier loop-phase detector gain system I − 1.2 − V/rad system B/G − 0.9 − V/rad fp carrier loop pull-in frequency 4 −− kHz Φ offset carrier loop-phase detector offset phase shift = 45°− 4 0 +4 deg fn carrier loop bandwidth (natural frequency) 2 − 5 kHz Baseband remodulator filter feedback REMVE Vo carrier loop filter virtual earth voltage defined by VRCF − 0.5VDDF2 − V Fine frequency calibration current (on to REMVE node) Isource output source current − 15 −µ A Isink output sink current − 15 −µ A ILI 3-state leakage current −0.25 0 +0.25 µA ffstep fine frequency calibration step 0.8 2 8 kHz Voltage controlled oscillator VCONT Vi input signal voltage 0.5 − VDD − 0.5 V C i input capacitance −− 10 pF SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1996 Oct 24 25

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 VCO (MEASURED AT V CLK PIN) fVCO VCO frequency after DAC calibration fSYS = 6552 MHz (system I) or f SYS = 5.85 MHz (system BGH) fSYS − 75 − fSYS + 75 kHz VCO frequency after fine frequency calibration fSYS − 4 − fSYS + 4 kHz KVCO VCO slope system I −139 −186 −232 kHz/V system B/G −191 −255 −319 kHz/V DAC STEP VCO calibrating DAC step size −50 +30 +50 kHz ItoQ in-phase to quadrature phase accuracy − 90 − deg ϕj VCO phase jitter note 4 −− 8.1 ns Clock recovery loop and crystal oscillator XTAL C i input capacitance −− 10 pF Vbias DC bias voltage − 3.63 − V OSC Vosc(p-p) oscillator voltage amplitude (peak to peak value) − 1.4 − V Vbias DC bias voltage − 2.33 − V G v small signal voltage gain − 1.0 − V/V C o output capacitance −− 10 pF C RYSTAL SPECIFICATION (FUNDAMENTAL MODE ) fi crystal input frequency − 8.192 − MHz C L load capacitance − 15 − pF C1 series capacitance 21 −− fF C0 parallel capacitance −− 5p F S pulling sensitivity determined by C L, C1 and C0 −26.25 −− 10−6/pF R r resonance resistance −− 40 Ω R DLD resonance resistance; drive level dependency −− 120 Ω Xa ageing −−± 51 0 −6/year Trange temperature range −20 +25 +70 °C Xj adjustment tolerance −−± 30 10 −6 Xd drift across T range −−± 30 10 −6 C LOCK RECOVERY LOOP CURRENT SOURCE (CLKLPF) ILI 3-state leakage current atπ⁄2 phase shift 0.5≤ VCLKLPF ≤ VDD − 0.5; note 5 −50 + 5 µA ϕgm phase comparator transconductance 0.5≤ VCLKLPF ≤ VDD − 0.5; note 5 57 63.5 70 µA/rad SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1996 Oct 24 26

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 Analog references VRCA OUTPUT Vo output signal voltage supply dependent − 0.5VDDA − V C i input capacitance −− 10 pF VROA OUTPUT Vo output signal voltage defined by V RCA − 0.5VDDA − V C i input capacitance −− 10 pF Digital filter fs output sample frequency − 128 − kHz PR pass band ripple at 0 Hz to 15 kHz −−± 0.01 dB SBA stop band attenuation at f ≥ 17 kHz 30 −− dB Digital de-emphasis DEV deviation from ideal −−± 0.09 dB FM audio inputs FML AND FMR (SELECTED VIA I2C-BUS CONTROL ) Zi input impedance 0 dB FM attenuation set − 40 − kΩ −12 dB FM attenuation set − 160 − kΩ G output gain programmable in 1 dB steps − 0t o 1 2 − dB G a output gain accuracy −0.5 0 +0.5 dB Vain(rms) input voltage level (RMS value) −− 1.1 V S/N signal-to-noise ratio 90 95 − dB THD total harmonic distortion −− 85 −70 dB EXT audio input EXTL AND EXTR (SELECTED VIA I2C-BUS CONTROL ) Zi input impedance − 40 − kΩ G output gain − 0 − dB G a output gain accuracy − 0 − dB Vain(rms) input voltage level (RMS value) −− 1.1 V S/N signal-to-noise ratio 90 95 − dB THD total harmonic distortion −− 85 −70 dB NICAM internal DAC (selected via I2C-bus control) Vo(rms) NICAM output voltage level (RMS value) 0 dB; VROA = 2.5 V 0.94 1 1.06 V THD+N total harmonic distortion plus noise notes 6 and 7 −− 80 −75 dB DIGS digital silence level MUTE on −− 80 − dB AUDIOS audio silence level SILENCE on = 0 −80 −− dB SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1996 Oct 24 27

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 Notes 1. It is assumed that all supplies are externally connected at the same source, and consequently that maximum and minimum values apply simultaneously to each supply. 2. Cumulative input level based on FM at 0 dB and NICAM at−10 dB with respect to picture carrier. 3. The signal amplitude present at the SEYE and CEYE pins depends on whether the demodulator is in or out-of-lock. When out-of-lock, the signal at the pins is√2 times the in-lock situation. 4. VCO jitter is measured in System I over 100 cycles of the VCO clock. 5. With 10 kΩ resistor from I REF to VSSF2 . 6. Audio performance is limited by the dynamic range of the NICAM 728 system. Due to compansion, the quantization noise is never lower than−62 dB with respect to the input level. 7. Measured with a−30 dB, 1 kHz NICAM 728 input signal. 8. Note that a transmitter must internally provide at least a hold time to bridge the undefined region (max. 300 ns) of the falling edge of SCL. 9. If a fast I2C-bus device is used in an up to 100 kbit/s I2C-bus system, then the requirement tSU;DAT ≥ 250 ns is always fulfilled if this device cannot stretch the LOW level of the SCL signal. If a device stretches the LOW level of the SCL signal, then data to SDA must be asserted (t RD(max) +tSU;DAT ) = 1000 + 250 = 1250 ns before the SCL signal is released to be compatible with the up to 100 kbit/s I2C-bus specification. Audio outputs OPL AND OPR C L output load capacitance −− 300 pF R L output load resistance 3 −− kΩ CHM channel matching 0 dB, 1 kHz −0.5 0 +0.5 dB PSRR power supply rejection ratio − 40 − dB Timing (all timing values refer to VIH and VIL levels) DATAIN WITH RESPECT TO PCLK (see Fig.9) tSU;DAT data set-up time 100 −− ns tHD;DAT data hold time 250 −− ns SDA WITH RESPECT TO SCL(see Fig.10) fSCL SCL clock frequency 0 − 400 kHz tBUF bus free time 1300 −− ns tHD;STA START code hold time 600 −− ns tLOW SCL clock LOW time 1300 −− ns tHIGH SCL clock HIGH time 600 −− ns tSU;STA START code set-up time 600 −− ns tHD;DAT data hold time note 8 0 −− ns tSU;DAT data set-up time note 9 100 −− ns tr SDA and SCL rise time 50 − 300 ns tf SDA and SCL fall time 50 − 300 ns tSU;STO STOP code set-up time 600 −− ns SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1996 Oct 24 28

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 Fig.7 VDD external circuitry. handbook, full pagewidth MGB466 VDDDV DDF2V DDF1 VDDA µ F 100 nF Ω2.2 supply µ F 100 nF Ω2.2 100 nF Ω22 100 nF 10 Ω SAA7283

1996 Oct 24 29

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 Fig.8 System block diagram showing SAA7283. handbook, full pagewidth MGB467 STEREO BITSTREAM DAC AND SWITCHES NICAM DECODER DAI I C2 SAA7283 AUDIO OUTPUTS EXTERNAL AUDIO INPUTS DOBM DQPSK DEMODULATOR I C-BUS2

8.192 MHz

6 MHz (I)

5.5 MHz (BG)

(TDA9803) SAW FILTER TUNER RF INPUT

39.5 MHz (I)

38.9 MHz (BG)

– 6 dB 32.95 33.5 39.5 MHz (I) 33.05 33.4 38.9 MHz (BG) LEFT RIGHT ANALOG FM SOUND

1996 Oct 24 30

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 Fig.9 Data output timing. handbook, full pagewidth MLB158 PCLK DATA tSU;DAT tHD;DAT Fig.10 I2C-bus timing. handbook, full pagewidth MBC764 tBUF tf tHIGH tSU;DAT tSU;STO tHD;DAT tSU;STA tr tLOW tHD;STA SDA SCL SDA

1996 Oct 24 31

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283

APPLICATION INFORMATION

handbook, full pagewidth 202122242526272829303132 23 646362605958575655545352 61 DATAOUT EXTR FMR PCLK OPR n.c. DATAIN n.c. OSC XTAL n.c. CLKLPF n.c. OPL FML EXTL PORM PORA REMVE PKDET REMO VDDD VSSD VSSX V SSF2 VDDF2 VRCF IREF VROF V SSDAC VROA RESET TEST SAA7283 n.c. n.c. n.c. n.c. n.c. CEYE SEYE COFF SOFF DQPSK MIXREF VCLK VCONT VDDF1 VSSF1 n.c. n.c. n.c. PORT2 ADSEL DOBM SDA SCL VRCA VSSA VDDA MUTE n.c. n.c. n.c. n.c. MGB468 Ω100 VSSF2 VDDF2 Ω2.2 100 nF µF 220 pF 100 nF µF 10 100 nF µF Ω10 k Ω22 k330 nF 22 nF VSSF2 100 pF 100 pF Ω1 M µH6.8 BB405 VSSF2 100 nF VSSD Ω22 BAW62Ω680 k 470 nF VDDD VSSD VDDD VSSA VSSD 100 nF µ F VSSA 100 nF VSSA Ω10 VDDA digital audio interface SCL SDA VSSD I C bus connector pFΩ1 M VSSA Ω10 kµF47 audio left 100 nF µF VSSA VSSA VSSA Ω1.8 k 47 nF Ω33 k pFΩ1 M VSSA Ω10 kµ F47 audio right 220 nF EXTL FML FMR EXTR 220 nF 220 nF 220 nF VSSA VSSF2 µF 100 nF µF VSSF1 Ω1 k pF VSSF1 VSSF1 390 pF VSSF1 VSSF1 µF 100 nF µF VSSF1 Ω2.2 VDDF1 DQPSK input VSS V (5 V)DD supply connector Fig.11 Application diagram for QFP64.

1996 Oct 24 32

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 PACKAGE OUTLINES UNIT b1 cE e M HL REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm DIMENSIONS (mm are the original dimensions) SOT247-1 90-01-22 95-03-11 b max.wM Ee1 1.3 0.8 0.53 0.40 0.32 0.23 47.9 47.1 14.0 13.7 3.2 15.24 17.15 M H c (e )1 M E A L seating plane w M D A 2 Z b E pin 1 index 0 5 10 mm scale Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1)D (1)Z e A max. 12A min. A max. SDIP52: plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1

1996 Oct 24 33

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 UNIT A 1 A 2 A 3 bp cE (1) eH E LL p QZ ywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 0.25 0.05 2.90 2.65 0.25 0.50 0.35 0.25 0.14 14.1 13.9 1 18.2 17.6 1.4 1.2 1.2 0.8 o o0.2 0.10.21.95 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 SOT319-2 92-11-17 95-02-04 D (1) (1)(1) 20.1 19.9 H D 24.2 23.6 EZ 1.2 0.8 D e θ E A 1 A Lp Q detail X L (A )3 B y c EH A 2 D Z D A Z E e v M A 51 33 X pin 1 index bp DH bp v M B w M w M 0 5 10 mm scale QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mmSOT319-2 A max. 3.20

1996 Oct 24 34

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). SDIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T stg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. R EPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300°C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400°C, contact may be up to 5 seconds. QFP R EFLOW SOLDERING Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary from 50 to 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250°C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheat for 45 minutes at 45°C. W AVE SOLDERING Wave soldering isnot recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed:

• A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used.
• The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260°C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250°C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. R EPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300°C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320°C.

1996 Oct 24 35

Philips Semiconductors Preliminary specification Terrestrial Digital Sound Decoder (TDSD3) SAA7283 DEFINITIONS LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I 2C COMPONENTS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Where application information is given, it is advisory and does not form part of the specification. Purchase of Philips I 2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.

Internet: http://www.semiconductors.philips.com Philips Semiconductors – a worldwide company © Philips Electronics N.V. 1996 SCA52 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 247 9145, Fax. +7 095 247 9144 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 São Paulo, SÃO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria:Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil:see South America Bulgaria:Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

72 Tat Chee Avenue, Kowloon Tong, HONG KONG,

Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580/xxx France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Printed in The Netherlands 537021/1200/01/pp36 Date of release: 1996 Oct 24 Document order number: 9397 750 01421