SAA3500H

SAA3500H PHILIPS

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 32

Technical content

Datasheet sections

• 2000 Jun 14
• 1 FEATURES
• 2 APPLICATIONS
• 3 GENERAL DESCRIPTION
• 4 QUICK REFERENCE DATA
• 5 ORDERING INFORMATION
• 6 BLOCK DIAGRAM
• 7 PINNING
• 8 FUNCTIONAL DESCRIPTION
• 9 INTERFACE DESCRIPTION
• 9.1 Input interface
• 9.2 Memory interface
• 9.3 Parallel output interface
• 9.4 Serial output interface
• 9.5 Simple full capacity output
• 9.6 RDI output
• 9.7 Microcontroller interface
• 9.7.2 L3-bus mode
• 9.7.3 Microcontroller interface registers
• 10 LIMITING VALUES
• 11 THERMAL CHARACTERISTICS
• 12 DC CHARACTERISTICS
• 13 AC CHARACTERISTICS
• 14 APPLICATION INFORMATION
• 14.1 Clock oscillator
• 14.2 Reset input
• 14.3 Boundary scan test interface
• 15 PACKAGE OUTLINE
• 16 SOLDERING
• 16.1 Introduction to soldering surface mount
• 16.2 Reflow soldering
• 16.3 Wave soldering
• 16.4 Manual soldering
• 16.5 Suitability of surface mount IC packages for
• 17 DATA SHEET STATUS
• 18 DEFINITIONS
• 19 DISCLAIMERS
• 20 PURCHASE OF PHILIPS I

Preliminary specification File under Integrated Circuits, IC01

2000 Jun 14

Digital audio broadcast channel decoder

2000 Jun 14 3

Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H

1 FEATURES

• Digital Audio Broadcast (DAB) full-capacity demodulator and decoder
• Supports DAB transmission modes I, II, III and IV
• Integrated Analog-to-Digital Converter (ADC) for IF input
• Digital mixer with on-chip digital Automatic Frequency Control (AFC) and Automatic Gain Control (AGC)
• Detectors for null symbol, DAB mode and transmitter identification
• On-chip or external synchronization algorithms and control loops
• On-chip timing PLL and DCXO
• Dynamic DAB multiplex reconfiguration supported
• Equal and unequal error protection for up to 64 sub-channels
• Fast information channel buffering
• Simple full capacity output
• Receiver data interface
• Serial output for three sub-channels
• I2C-bus or L3-bus control interface.

2 APPLICATIONS

• Mobile receivers (FM/DAB car radios)
• Personal Computer add-ons
• Test and measurement equipment
• Portable radios.

3 GENERAL DESCRIPTION

The Philips SAA3500H is a Digital Audio Broadcast (DAB) channel decoder according to the ETSI specification ETS 300 401. The SAA3500H is a successor to the Philips FADIC and SIVIC chip set and provides an IF ADC, digital mixer, full DAB ensemble demodulation and decoding as well as time and frequency synchronization functions. Because of the full-speed Viterbi decoding capacity and a high-speed receiver data output interface, DAB data reception is not limited by the SAA3500H channel decoder.

4 QUICK REFERENCE DATA

5 ORDERING INFORMATION

SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDD supply voltage 3.0 3.3 3.6 V Vi(max) maximum input voltage −0.5 − VDD + 0.5 V IDD DC supply current −− 180 mA fclk clock frequency − 24576 − kHz Tamb ambient temperature −40 +25 +85 °C Tstg storage temperature −65 − +150 °C TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION SAA3500H QFP100 plastic quad flat package; 100 leads (lead length 1.95 mm); body 14× 20 × 2.7 mm; high stand-off height SOT317-1

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Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H

6 BLOCK DIAGRAM

INP[9:0] IQS AGC SLI OCLK MCI D[7:0] CCLK CDATA SOD[1:3] REF SFCOSOV[1:3]SOC RDO RDC TDI TCK TMS TRST ADCLK MCLK OIQ OUT[7:0] A[17:0] NULL DETECTOR, TIMEBASE, DCXO OSCO AD CONVERTER (8 BIT)ADC AIF FREQUENCY & TIME DE-INTERLEAVER ADE OCIR OEN RESET RDE BYP FSO FSI A17 RD WR SAA3500H 39 to 32 62 to 68, 81 to 91 71 to 78 21 7 to 21 20 25 24 19 41 4 5 55 51 52 54 53 50 to to 44 43 56 58 57 59 Fig.1 Block diagram.

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Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H

7 PINNING

SYMBOL PIN TYPE DESCRIPTION ADC 1 input analog-to-digital converter DC input AIF 2 input analog-to-digital converter IF input V SSA 3 ground analog supply ground ADE 99 input analog-to-digital converter enable (active LOW) V DDA 100 supply analog voltage supply (+3.3 V) INP[0:9] 8 to 17 input 2048 kHz IF or baseband digital parallel input data (8 or 10 bits) ADCLK 19 output analog-to-digital clock output 8192 kHz if BYP = HIGH, 4096 kHz ifBYP = LOW IQS 20 input clock signal indicating I or Q baseband data if BYP = LOW; signal for swapping I and Q data bytes ifBYP = HIGH BYP 21 input IF input stage bypass (active LOW) FSI 22 input frame sync input (LOW indicates DAB null symbol detection) FSO 23 output null detector/frame sync output (LOW indicates DAB null symbol position) SLI 24 output AGC synchronization lock indicator (HIGH if synchronized) AGC 25 output AGC level comparator output (HIGH if input sample > reference level, else LOW) OSCI 4 input oscillator or system clock input, 24576 kHz OSCO 5 output oscillator output MCLK 41 output master clock output, 24576 kHz V SS 7, 18, 26, 40, 60, 80 and 94 supply digital supply ground VDD 6, 28, 42 and supply digital voltage supply (+3.3 V) TEST 92 input connect to ground for proper operation OUT[0:7] 32 to 39 output baseband or channel impulse response output OCLK 27 output output data clock (negative edge indicates new data) OIQ 29 output output I or Q select signal if OCIR = HIGH, or frame trigger ifOCIR = LOW OCIR 30 input output select: baseband if OCIR = HIGH, CIR ifOCIR = LOW OEN 31 input output enable (active LOW) CFIC 51 output microcontroller interface signal indicating Fast Information Channel (FIC) processing CMODE 52 input microcontroller interface mode input (only L3-bus) CDATA 53 I/O microcontroller interface serial data I 2C-bus or L3-bus (5 V tolerant) CCLK 54 input microcontroller interface clock input I 2C-bus or L3-bus RESET 55 input chip reset input (active LOW) A[17:11] 62 to 68 output address outputs external RAM A[10:0] 81 to 91 output address outputs external RAM WR 61 output write data to RAM (active LOW) RD 69 output read data from RAM (active LOW) A17 70 output address bit 17 inverted for second RAM (128k × 8) D[0:7] 71 to 78 I/O data input/output external RAM

2000 Jun 14 6

Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H SOV3 44 output serial output valid data 3 SOV2 45 output serial output valid data 2 SOV1 46 output serial output valid data 1 SOD3 47 output serial output data 3 SOD2 48 output serial output data 2 SOD1 49 output serial output data 1 (from channel decoder) SOC 50 output serial output clock (384 kHz continuous) REF 43 output receiver error flag [from Viterbi decoder, for Simple Full Capacity Output (SFCO)] SFCO 56 output simple full capacity output (direct from Viterbi decoder) RDC 57 output receiver data clock (6144 kHz continuous) or SFCO clock (burst) RDE 58 input RDI output enable (active LOW) RDO 59 output receiver data interface bi-phase output TDO 93 output boundary scan test serial output TCK 95 input boundary scan test clock input TDI 96 input boundary scan test serial input TMS 97 input boundary scan test mode select input TRST 98 input boundary scan test reset input SYMBOL PIN TYPE DESCRIPTION

2000 Jun 14 7

Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H 5130 100 50MXXxxx SAA3500H OCIR OIQ VDD OCLK VSS AGC SLI FSO FSI BYP IQS ADCLK VSS INP9 INP8 INP7 INP6 INP5 INP4 INP3 INP2 INP1 INP0 VSS VDD OSCO OSCI VSSA AIF ADC CFIC CMODE CDATA CCLK RESET SFCO RDC RDE RDO VSS WR A17 A16 A15 A14 A13 A12 A11 RD A17 VDD VSS VDDA TRST TMS TDI TCK VSS TDO TEST A10 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 VSS MCLK VDD REF SOV3 SOV2 SOV1 SOD3 SOD2 SOD1 SOC OEN ADE Fig.2 Pin configuration.

2000 Jun 14 8

Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H

8 FUNCTIONAL DESCRIPTION

The 2.048 MHz IF signal is digitized by an 8-bit flash Analog-to-Digital Converter (ADC), which samples at 8.192 MHz. The required input level is limited to a peak-to-peak voltage of 2 V. Due to a fast sample-and-hold circuit sub-sampling is possible, so that all IF frequencies of N× 8.192±2.048 MHz can be used. If a higher resolution ADC is wanted, an external ADC can be connected. The digital mixer accepts a 2.048 MHz IF signal at its input and converts it to baseband with In-phase (I) and Quadrature-phase (Q) components. The mixer frequency is adjusted on a DAB frame basis with 1 Hz resolution to prevent performance degradation. The mixer output signals are digitally filtered and subjected to internal Automatic Gain Control (AGC) before entering the subsequent Fast Fourier Transform (FFT) stage. The output of the digital AGC detectors indicates for each input sample whether the level is below or above the reference input level. By means of external filtering and gain control, the signal can be used to adjust the input signal level of the analog-to-digital converter (external AGC). The on-chip null detector operates on the digital baseband signal and indicates the coarse position of the DAB null symbol ( FSO = LOW), which is used for time base initialization. The spacing of detected null symbols is used to detect the DAB transmission mode. The time base counts samples on a symbol and a frame basis in order to generate the internal control windows for the FFT and to generate a frame sync signal ( FSO) during the null symbol. Initialization of the time base is determined by the null detector signal ( FSI) and the selected DAB mode. After time base initialization the SAA3500H will be in symbol processing mode and the null detector will be deactivated. The OFDM symbol demodulator applies a real-time FFT and differential demodulation to the baseband signal. The output is quantized to 4-bit metrics for the Viterbi decoder. The position of the FFT window is adjusted on a DAB frame basis in order to avoid Inter-Symbol Interference (ISI). The FFT result of the reference symbol is processed by the synchronization core, which performs two functions: estimation of the frequency error of the baseband signal, which is needed to adjust the digital mixer (AFC), and calculation of the Channel Impulse Response (CIR) to be used for positioning of the FFT window and the system clock. All timing and frequency control loops are realized in the synchronization core and can be influenced from the control interface. The Viterbi decoder is preceded by frequency and time de-interleaving of the incoming metrics in external RAM, to distribute burst errors caused by channel fading. Variable rate decoding is done with 3.072 Mb/s decision speed. Output bits are re-encoded and compared to corresponding input bits in order to generate an error flag signal. Sub-channel selection is done on a Capacity Unit (CU) basis. All standardized Unequal Error Protection (UEP) puncturing schemes for audio and Equal Error Protection (EEP) schemes for data are provided. Up to 64 sub-channels can be selected separately, which means virtually unlimited DAB decoding capabilities. The output interface provides a full-speed standardized Receiver Data Interface (RDI) for all sub-channel data. This allows to extend every DAB receiver with external decoders for all kind of services. A dedicated interface is provided for the Philips SAA2502H audio source decoder, which completes the DAB receiver. The system clock of 24.576 MHz, can be generated by an integrated DCXO, which is internally locked to the DAB signal. The clock is available on the MCLK pin to provide a synchronous clock to the MPEG decoder and microcontroller. The I 2C-bus or L3-bus configurable control interface provides access to Automatic Frequency Control (AFC), Channel Impulse Response (CIR), Fast Information Channel (FIC) and sub-channel selection controls.

2000 Jun 14 9

Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H

9 INTERFACE DESCRIPTION

9.1 Input interface

The input interface can be used in 3 different modes, depending on the bypass ( BYP) and IQ Select (IQS) pins. Digital input data should be in two’s complement format (optionally: offset binary) and synchronized with the ADCLK output signal. Input data are read on the rising edge of ADCLK. Table 1 Input modes In case of baseband input the IQ select signal shall indicate whether the current sample is either I or Q data (INP[9:0]). Digital IF input is, typically, at a frequency of 2048 kHz. It is possible to apply sub-sampling on a N× 8.192±2.048 MHz (N = 1, 2, 3,...,19) IF signal, but care should be taken with the jitter of the crystal clock, which is proportional to N. To use the on-chip null detector, pins FSI andFSO shall simply be connected to each other. When using an external null detector, theFSI input shall indicate the position of the null symbol in the baseband signal (FSI = LOW). The negative edge may have a maximum delay of 512 samples with respect to an ideal null detector. The delay compensation can be set via the I2C/L3 interface (register ATCWinControl). TheFSI input provides edge jitter suppression of up to 40 samples starting from the first negative edge. Once the SAA3500H is in symbol processing mode, the FSI signal is ignored. During the null detection state, the Sync Lock Indicator (SLI) will be continuously LOW.

9.2 Memory interface

An external SRAM memory of either 128 or 256 kbytes is required to store the metrics from the data de-interleaver for half (432 CUs) or full (864 CUs) decoding capacity, respectively. The upper address line A17 is available both true and inverted ( A17) to allow memory extension without an address decoder. 3.3 V RAMs should be used with either an 8 or (2×) 4-bit data bus and an access time of≤80 ns. Input data are read on the rising edge ofRD, output data shall be latched on the rising edge ofWR. BYP IQS DESCRIPTION 0 clk digital baseband input sampled at 2048 kHz and with I and Q data multiplexed 1 0 digital IF input sampled at 8192 kHz, internal I/Q demodulator 1 1 digital IF input sampled at 8192 kHz, internal I/Q demodulator with I and Q swapped ADCLK INP[9:0] IQS 4096 kHz 10 bits 2048 kHz Q 0 I1 Q 1 I2 Q 2 Fig.3 Baseband input signals (BYP = LOW). ADCLK INP[9:0] 8192 kHz 10 bits Fig.4 IF input signals [BYP = HIGH, IQS = LOW (no swap) or HIGH (swap)].

2000 Jun 14 10

Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H A[17:0] D[7:0] RD WR Fig.5 RAM access.

9.3 Parallel output interface

The digital parallel output interface can be used in 3 different modes depending on theOCIR and OEN select pins. Output data shall be latched on the falling edge of OCLK. Table 2 Parallel output modes X = don’t care. By means of an external digital-to-analog converter, either the CIR or I/Q data can be displayed on an oscilloscope. Digital output data is clocked out on the falling edge of the OCLK output signal. In case of baseband output the OIQ signal indicates, if the current sample is either I or Q data. OCIR OEN DESCRIPTION 0 0 channel impulse response sampled at 64 kHz, OIQ = frame trigger 1 0 baseband sampled at 2048 kHz and with I and Q data multiplexed X 1 OUT[7:0], OIQ and OCLK disabled OCLK OUT[7:0] OIQ QI Q I Q 4096 kHz signed 2048 kHz Fig.6 Baseband output signals (OCIR = HIGH,OEN = LOW). OCLK OIQ 64 kHz unsignedOUT[7:0] trigger Fig.7 CIR output signals (OCIR = LOW, OEN = LOW).

2000 Jun 14 11

Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H In the CIR output mode the channel impulse response is clocked out in a burst of N (unsigned) samples at 64 kHz each frame after CIR processing (bit SyncBusy = logic 0). The edges of the frame trigger signal (OIQ) allow to trigger a CIR display either at the start of the symbol or at the start of the symbol guard. In the latter case the CIR peak for a Gaussian channel will be at the left of the display.

9.4 Serial output interface

The serial output interface is intended for transferring up to three sub-channels to the source decoder(s) with a total maximum bit rate of 384 kbit/s. The sub-channels for these outputs should be selected with the appropriate I 2C or L3 commands. The output clock is 384 kHz. Each sub-channel has its own serial data and data valid line, but the clock is common. Serial output data shall be latched on the rising edge of SOC.

9.5 Simple full capacity output

This interface provides serial access to all the Viterbi decoder output bits without any formatting. Transmission framing is indicated by the CFIC window, which can also be used to separate the FIC data (CFIC = HIGH) from the Main Service Channel (MSC) data (CFIC = LOW). The bit CFICMode can be used to signal on CFIC the beginning of the selected sub-channels (CFICMode = logic 0). The clock is a 3072 kHz burst clock, activated for each new output bit. Accompanied with the data is the error flag, obtained by re-encoding the Viterbi output bits and comparison with the corresponding Viterbi decoder input bits (REF = HIGH for error bit).

9.6 RDI output

For external use a bi-phase modulated output (RDO) is provided, which carries all the FIC and MSC data, formatted according to the DAB receiver data interface specification “EN 50255”, which is based on the IEC 60958 digital audio interface. Optionally, a clock (6144 kHz) and word select signal (48 kHz) can be provided (instead of SFCO signals). Transmitter Identification Information (TII) is not signalled on this RDI. The FIC however is always signalled, with the Cyclic Redundancy Check (CRC) performed and the Error Check Field containing the resulting CRC (normally 0). Selected sub-channels will be directed to the RDI interface in the extended capacity mode (22 bits for MSC), but the number of RDI frames and the reliability are not signalled (i.e., set to all logic 0s and all logic 1s, respectively). SOC SOV SOD Fig.8 DAB3 serial output. RDC CFIC SFCO REF CFICMode = 0 Fig.9 Simple full capacity output (CFICMode = logic 1).

2000 Jun 14 12

Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H In case SFCO data output is not desired, a particular ‘RDI plus’ mode can be selected, which provides a continuous 6144 kHz clock on RDC, synchronous to the bi-phase RDI data and accompanied by a fixed word select signal, to allow RDI source reception without an extra clock recovery circuit. Output data shall be latched on the rising edge of RDC.

9.7 Microcontroller interface

The microcontroller interface of the SAA3500H operates in one of two distinct modes of operation: I 2C-bus or L3-bus. Mode setting is determined at initialization, as described in Fig.12. On either control bus data are transferred in 8-bit packets, or bytes. The interface uses three signals and the function in the L3-bus mode or I 2C-bus mode is indicated in Table 3. Table 3 Control bus modes During a hard reset of the device, the microcontroller interface mode is determined. As a consequence, the interface cannot be used while the reset signal is asserted. Mandatory action must be taken for correct microcontroller interface start-up at a hard reset, as explained in Fig.12. SIGNAL L3-BUS MODE I 2C-BUS MODE DIRECTION DESCRIPTION CDATA L3DATA SDA input/output microcontroller interface serial data CCLK L3CLK SCL input microcontroller interface bit clock CMODE L3MODE none input microcontroller interface mode select RDO Fig.10 RDI output (normal mode,RDE = LOW). RDC SFCO RDO Channel 2 (32 bits)Channel 1 (32 bits) Fig.11 RDI output (RDI plus mode,RDE = LOW). RESET CCLK CMODE L3-bus mode I2C-bus mode phase 1 phase 2 phase 3 Fig.12 Microcontroller interface initialization procedure.

2000 Jun 14 13

Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H In phase 1, the level of the CMODE signal determines the microcontroller interface mode, while reset is asserted. CMODE = HIGH defines I2C-bus mode, CMODE = LOW defines L3-bus mode. No transfers can be performed, as CCLK must be HIGH. In phase 2, which is for L3-bus mode of operation only, it is mandatory to take CMODE HIGH, then LOW again after reset has been de-asserted, to correctly initialize the interface unit. This must occur before any L3-bus transfer (even to or from other devices) is performed. CCLK shall remain HIGH during this phase. In phase 3, the first transfer can be performed on the microcontroller interface. Any deviation from these steps may result in undefined behaviour of the microcontroller interface, even with the possibility of disturbing transfers to other devices connected to the control bus. At a hardware reset, all writeable data items are forced to their default values. The microcontroller interface provides access to all blocks, which generate or need control information. Selections on the SAA3500H are at the sub-channel level, the required sub-channel parameters should be obtained via the Multiplex Configuration Information (MCI), which is part of the FIC. The CFIC window from the SAA3500H indicates FIC decoding. FIC data from the I 2C/L3 interface will be invalid, if CFIC = HIGH. It is therefore recommended to connect CFIC to a microcontroller interrupt input pin. With regard to the real-time processing requirements, it is highly recommended to use a 16-bit microcontroller. 9.7.1 I 2C-BUS MODE The implemented I2C-bus interface is of the 400 kbit/s, 7-bit address type. The CDATA output driver is of the ‘open drain’ type in order to be compliant with the I2C-bus specification. The device address is as follows: Table 4 I2C-bus device address Bit 7 to bit 1 comprise the 7-bit I2C-bus slave address, while bit 0 indicates the transfer direction of data and acknowledge bits as follows: Table 5 Read and write operation to the microcontroller in I2C-bus mode Fundamentals of the I2C-bus interface protocol are shown in Fig.13. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

1101011 R / W

0 data from microcontroller to SAA3500H all acknowledge generated by SAA3500H 1 data from SAA3500H to microcontroller acknowledge for data generated by microcontroller

2000 Jun 14 14

Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H For full details of the I2C-bus interface specification, please, refer to the I2C-bus specification (http://www.semiconductors.com/handbook/various_38.html), which is also available on request.

9.7.2 L3- BUS MODE

The L3-bus device address is composed as follows: Table 6 L3-bus device address Note 1. The ‘Data Operation Mode’ bits DOM1 and DOM0 define the current sub-mode of the microcontroller interface until the next time a device address is received (see Table 7). Table 7 Read and write operation to the microcontroller in L3-bus mode Fundamentals of the L3-bus interface protocol are shown in Fig.14. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

011011 DOM1

(1) DOM0 (1) DOM1 DOM0 FUNCTION REMARK 0 0 data from microcontroller to SAA3500H general purpose data transfer 0 1 data from SAA3500H to microcontroller general purpose data transfer 1 0 control from microcontroller to SAA3500H register selection for data transfer 1 1 status from SAA3500H to microcontroller short device status message CCLK CDATA 927 81 MSB LSB 92 781 ACK R/WMSB ACK P STOP condition S START condition address transfer data transfer Fig.13 I2C-bus data transfer example.

2000 Jun 14 15

Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H For full details of the L3-bus interface specification, please, refer to the SAA2502H data sheet (order number 9397 750 03068 or at http://www.semiconductors.com/products).

9.7.3 M ICROCONTROLLER INTERFACE REGISTERS

Communication between the microcontroller and the SAA3500H is by addressing registers and writing or reading data. All addresses and register contents are in hexadecimal notation. The following registers are available for the writing of data: Table 8 Writeable registers ADDRESS (HEX) NAME DESCRIPTION SETTING AFTER RESET (HEX)

00 Control control 1F

01 Configuration configuration FF

10 CIFCount CIF count and occurrence change flag 00 00 00

20 CurSubChSel current sub-channel selection 00 00 00 00

21 NextSubChSel next sub-channel selection 00 00 00 00

30 SOD1 select sub-channel for serial output SOD1 40

31 SOD2 select sub-channel for serial output SOD2 40

32 SOD3 select sub-channel for serial output SOD3 40

40 AGCExternal setting of thresholds for external AGC 61 0C

41 AGCInternal settings of the internal AGC D0 49

42 AGCFixed internal AGC switch off and fixed gain setting 00

50 NullDetMargin null detector margin 40

51 TIIControl TII main/sub identifier 00 00

60 MixerFreqInput digital mixer frequency control input 80 00 00

62 CarrierShift carrier shift by n carrier positions 00

63 AFCGain AFC loop gain 10

70 ATCWinControl ATC window control input or FFT window position and null

detector delay compensation

71 CIRThreshold CIR detector thresholds, edge and range 02 02

73 ATCGains ATC loops gains; clock I and P gains and window gain 02 04 20

Fig.14 L3-bus command transfer example.

2000 Jun 14 16

Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H The following registers are available for the reading of data: Table 9 Readable registers A description of how to use the individual registers is given in a separate application note.

10 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134). Notes 1. All supply connections must be made to the same external power supply unit. 2. Machine model: equivalent to discharging a 200 pF capacitor through a 0Ω series resistor (‘0Ω ’ is actually 0.75µH+1 0 Ω ). 3. Human body model: equivalent to discharging a 100 pF capacitor through a 1500Ω series resistor.

11 THERMAL CHARACTERISTICS

(HEX) NAME DESCRIPTION BYTES TO READ

00 Status internal processing status 1

10 FICErrCount FIC error count per frame 2

20 to 2B FICData FIC data inclusive CRC result 32

51 TIIOutput TII complex phase values 6

60 AFCLoopOutput AFC loop output for digital mixer frequency control 3

61 CarrierDev AFC carrier deviation detector 2

70 ATCWinOutput ATC window loop output for FFT window position 1

71 ATCDetector ATC CIR detector output 3

72 ATCClockOutput ATC clock loop output for external VCXO 1

76 CIRPower power of CIR response 2

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V DD DC supply voltage note 1 −0.5 +6 V Vi input voltage −0.5 V DD + 0.5 V IDD supply current − 200 mA Ii input current −10 +10 mA Io output current −10 +10 mA Ptot total power dissipation − 650 mW Tstg storage temperature −65 +150 °C Tamb operating ambient temperature −40 +85 °C Ves electrostatic handling voltage note 2 −300 +300 V note 3 −3000 +3000 V SYMBOL PARAMETER CONDITIONS VALUE UNIT R th(j-a) thermal resistance from junction to ambient in free air 60 K/W

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Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H

12 DC CHARACTERISTICS

VDD = 3.0 to 3.6 V; Tamb = −40 to +85°C; all voltages referenced to ground (VSS ); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD(tot) total DC supply voltage note 1 3.0 3.3 3.6 V IDD(tot) total DC supply current −− 180 mA Dissipation Ptot total power dissipation −− 650 mW Inputs CMOS LEVEL INPUT (INP[9:0],FSI, CCLKAND TCK) VIH HIGH-level input voltage 2.0 −− V VIL LOW-level input voltage −− 0.8 V |ILI| input leakage current V I= 0 or VI=V DD −− 1 µA C i input capacitance − 5 − pF CMOS LEVEL INPUT ,PULL -UP (BYP, CMODE, IQS, OCIR, OEN, RDE, TDI, TMSAND TRST) VIH HIGH-level input voltage 2.0 −− V VIL LOW-level input voltage −− 0.8 V R pu(VDD)(int) internal pull-up resistor to VDD 16 33 78 k Ω C i input capacitance − 5 − pF CMOS LEVEL INPUT ,HYSTERESIS ,PULL -UP (RESET) VIH(hys) HIGH-level hysteresis input, rising edge 1.4 − 1.9 V VIL(hys) LOW-level hysteresis input, falling edge 0.9 − 1.45 V Vhys hysteresis voltage 0.4 − 0.7 V R pu(VDD)(int) internal pull-up resistor to VDD 16 33 78 k Ω C i input capacitance − 5 − pF Inputs/outputs CMOS LEVEL INPUT ,HYSTERESIS ,OPEN DRAIN OUTPUT (CDATA) VIH(hys) HIGH-level hysteresis input, rising edge 1.4 − 1.9 V VIL(hys) LOW-level hysteresis input, falling edge 0.9 − 1.45 V Vhys hysteresis voltage 0.4 − 0.7 V VOL LOW-level output voltage I LOAD =3m A −− 0.4 V CMOS LEVEL INPUT , OUTPUT STAGE (D[7:0]) VIH HIGH-level input voltage 2.0 −− V VIL LOW-level input voltage −− 0.8 V |ILI| input leakage current V I= 0 or VI=V DD −− 1 µA VOH HIGH-level output voltage I LOAD = −1.5 mA 2.4 −− V VOL LOW-level output voltage I LOAD = 1.5 mA −− 0.4 V 1.5 mA

2000 Jun 14 18

Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H Note 1. All supply connections must be made to the same external power supply unit.

13 AC CHARACTERISTICS

VDD = 3.0 to 3.6 V; Tamb =2 5°C; all voltages referenced to ground (VSS ); unless otherwise specified. Outputs CMOS LEVEL , OUTPUT STAGE (A[17:0],A17, ADCLK, AGC,FSO, OCLK, OIQ,RD, SLI, SOD[1:3], SOV[1:3] AND WR) VOH HIGH-level output voltage I LOAD = −1.5 mA 2.4 −− V VOL LOW-level output voltage I LOAD = 1.5 mA −− 0.4 V C LOAD output load capacitance −− 30 pF CMOS LEVEL ,3 - STATE OUTPUT STAGE , (OUT[7:0]) VOH HIGH-level output voltage I LOAD = −1.5 mA 2.4 −− V VOL LOW-level output voltage I LOAD = 1.5 mA −− 0.4 V |ILO | output leakage current inactive mode; VO = 0 or VO =V DD −− 1 µA C LOAD output load capacitance −− 30 pF CMOS LEVEL , OUTPUT STAGE (CFIC, MCLK, RDC, RDO, REF , SFCO, SOCAND TDO) VOH HIGH-level output voltage I LOAD = −3 mA 2.4 −− V VOL LOW-level output voltage I LOAD =3m A −− 0.4 V C LOAD output load capacitance −− 50 pF SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Oscillator input (OSC) fi(OSC) input frequency note 1 − 24576 − kHz δOSC input clock duty factor 40 − 60 % Reset input (RESET) tCL,RESET reset LOW duration note 2 60 × T −− ns Input interface (ADCLK,BYP, INP[9:0] and IQS) BASEBAND INPUT (BYP = LOW); see Fig.15 Tcy,ADCLK ADCLK cycle time − 244 − ns tCL,ADCLK ADCLK LOW time − 122 − ns tCH,ADCLK ADCLK HIGH time − 122 − ns th,INP INP[9:0] hold time 5 −− ns th,IQS IQS hold time −− 80 ns SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 1.5 mA 1.5 mA 3 mA

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Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H IFINPUT (BYP = HIGH); see Fig.16 Tcy,ADCLK ADCLK cycle time − 122 − ns tCL,ADCLK ADCLK LOW time − 80 − ns tCH,ADCLK ADCLK HIGH time − 42 − ns th,INP INP[9:0] hold time 5 −− ns td,INP INP[9:0] delay time −− 25 ns Memory interface (A17, A[17:0], D[7:0],RD and WR); see Figs 17 and 18 Tcy,A address cycle time − 326 − ns tCL,RD RD LOW time − 163 − ns td,RD RD delay time − 40 − ns th,RD RD hold time − 0 − ns tCL,WR WR LOW time − 163 − ns td,WR WR delay time 0 40 − ns td,D data delay time − 0 − ns th,D data hold time −− 5n s Parallel output interface (OCIR, OCLK, OEN, OIQ and OUT[9:0]) BASEBAND OUTPUT (OCIR = HIGH); see Fig.19 Tcy,OCLK OCLK cycle time − 244 − ns tCL,OCLK OCLK LOW time − 122 − ns tCH,OCLK OCLK HIGH time − 122 − ns tsu,OUT OUT[7:0] set-up time − 15 − ns tsu,OIQ OIQ set-up time − 17 − ns CIR OUTPUT (OCIR = LOW); see Fig.20 Tcy,OCLK OCLK cycle time − 15.6 −µ s tCL,OCLK OCLK LOW time − 8.3 −µ s tCH,OCLK OCLK HIGH time − 7.3 −µ s tsu,OUT OUT[7:0] set-up time − 0 − ns tsu,OIQ OIQ set-up time − 0 − ns Serial output interface (SOC, SOD[3:1] and SOV[3:1]);see Fig.21 Tcy,SOC SOC cycle time − 2.6 −µ s tCL,SOC SOC LOW time − 1.3 −µ s tCH,SOC SOC HIGH time − 1.3 −µ s th,SOD SOD hold time − 0 − ns tsu,SOV SOV set-up time − 4 − ns th,SOV SOV hold time − 2 − ns SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H Simple full capacity output interface (CFIC, RDC, REF and SFCO);see Fig.22 tCH,CFIC CFIC HIGH time DAB mode I − 3.738 − ms DAB mode II − 0.935 − ms DAB mode III − 1.246 − ms DAB mode IV − 1.869 − ms tSH,CFIC CFIC strobe HIGH time bit CFICMode = 0 − 75 − ns bit CFICMode = 1− 0 − ns tsu,CFIC CFIC set-up time − 165 − ns th,CFIC CFIC hold time − 80 − ns Tcy,RDC RDC cycle time 325 −− ns tCH,RDC RDC HIGH time 250 −− ns tCL,RDC RDC LOW time − 75 − ns tsu,SFCO SFCO set-up time − 5 − ns tsu,REF REF set-up time − 165 − ns th,REF REF hold time −− 160 − ns RDI output interface (RDC,RDE, RDO and SFCO) N ORMAL MODE ; see Fig.23 tONE ONE time − 163 − ns tZERO ZERO time − 326 − ns RDI PLUS MODE ; see Fig.24 Tcy,RDC RDC cycle time − 163 − ns tCH,RDC RDC HIGH time − 86 − ns tCL,RDC RDC LOW time − 77 − ns Tcy,SFCO SFCO cycle time − 20.8 −µ s tCH,SFCO SFCO HIGH time − 10.4 −µ s tCL,SFCO SFCO LOW time − 10.4 −µ s tsu,SFCO SFCO set-up time − 4 − ns th,SFCO SFCO hold time − 0 − ns Microcontroller interface INITIALIZATION PROCEDURE ; see Fig.25 tCL,RESET RESET LOW time note 2 60 × T −− ns td,RES-MOD delay time fromRESET to CMODE note 2 10 × T −− ns tCH,CMODE CMODE HIGH time note 2 10 × T −− ns td,MOD-CLK delay time from CMODE to first CCLK note 2 10 × T −− ns SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H Notes 1. In a real application, the clock frequency may vary in a range of±50 ppm due to timing synchronization. L3-BUS MICROCONTROLLER TO SLAVE DEVICE ; see Figs 26 and 28 tcL L3CLK LOW time note 2 T + 10 −− ns tcH L3CLK HIGH time note 2 T + 10 −− ns td1 L3MODE set-up time before first L3CLK LOW 10 −− ns th1 L3DATA hold time after L3CLK HIGH 10 −− ns th2 L3MODE hold time after last L3CLK HIGH 15 −− ns tsu L3DATA set-up time before L3CLK HIGH note 2 T + 10 −− ns tL L3MODE LOW time note 2 T + 10 −− ns L3-BUS SLAVE DEVICE TO MICROCONTROLLER ; see Fig.27 td2 L3MODE HIGH to L3DATA enabled time 0 − 20 ns td3 L3MODE HIGH to L3DATA stable time −− 20 ns td4 L3CLK HIGH to L3DATA stable time note 2 −− 2T + 30 ns td5 L3MODE LOW to L3DATA disabled time 0 − 20 ns th3 L3DATA hold time after L3CLK HIGH note 2 T −− ns I2C-BUS INPUTS /OUTPUT (CDATA AND CCLK) tf,I2C output fall time −− 250 ns fCCLK CCLK clock frequency −− 400 kHz SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT ADCLK INP[9:0] IQS tCH,ADCLK Tcy,ADCLK tCL,ADCLK th,IQS th,INP Fig.15 Baseband input timing (BYP = LOW). ADCLK INP[9:0] tCH,ADCLK Tcy,ADCLK tCL,ADCLK td,INPth,INP Fig.16 IF input timing [BYP = HIGH, IQS = LOW (no swap) or HIGH (swap)].

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Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H A[17:0] D[7:0] RD Tcy,A td,RD tCL,RD th,D Fig.17 RAM access read timing. A[17:0] D[7:0] WR Tcy,A tCL,WR td,D th,D td,WR Fig.18 RAM access write timing. OCLK OUT[7:0] OIQ tCH,OCLK Tcy,OCLK tsu,OIQ tCL,OCLK tsu,OUT Fig.19 Baseband output timing (OCIR = HIGH, OEN = LOW). OCLK OUT[7:0] OIQ tCH,OCLK Tcy,OCLK tsu,OIQ tCL,OCLK tsu,OUT Fig.20 CIR output timing (OCIR = LOW, OEN = LOW). SOC SOD SOV tCH,SOC Tcy,SOC tCL,SOC th,SOD tsu,SOV th,SOV Fig.21 DAB3 serial output timing.

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Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H RDC CFIC SFCO REF tCL,RDC tSH,CFIC Tcy,RDC tCH,RDC th,REFtsu,SFCO tCH,CFIC tsu,CFIC tsu,REF th,CFIC Fig.22 Simple full capacity output timing. RDO tONE tZERO Fig.23 RDI output timing (normal mode,RDE = LOW). RDC SFCO RDO tCL,SFCO tCH,RDC Tcy,SFCO Tcy,RDC th,SFCO tCL,RDC tCH,SFCO tsu,SFCO Fig.24 RDI output timing (RDI plus mode,RDE = LOW).

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Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H RESET CCLK CMODE tCH,CMODE td,RES-MOD tCL,RESET td,MOD-CLK Fig.25 Microcontroller interface initialization timing. handbook, full pagewidth MGB507 td1 h2 cLt cHt h1t sut t L3CLK L3MODE L3DATA Fig.26 Timing of L3-bus addressing mode. handbook, full pagewidth MGB508 L3DATA microcontroller to IC td1 h2 cLt cHt h1tsut t d2t d3t h3t d4t d5t L3DATA IC to microcontroller L3CLK L3MODE Fig.27 Timing of L3-bus data transfer mode.

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Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H handbook, full pagewidth MGB509 tL L3CLK L3MODE d5t h2t td1 d2t L3DATA IC to microcontroller Fig.28 Timing of L3-bus halt mode.

14 APPLICATION INFORMATION

A suggestion for an application block diagram is shown in Fig.29. TUNER BAND III/L SAW FILTER AGC SAA3500H SAA2502H RAM (256k · 8) MICROCONTROLLER RDI I2S L/R SPDIF DA I2C or L3-BUS DAB3

24.576 MHz

Fig.29 Typical application diagram.

14.1 Clock oscillator

To perform automatic fine tuning of the clock signal, the microcontroller reads data from the SAA3500H and controls an external (VCXO) crystal oscillator. The following requirements should be met by that oscillator: Table 10VCXO specification

14.2 Reset input

The reset signal is active LOW and should have a minimum duration of 60 clock cycles.

14.3 Boundary scan test interface

For normal operation set TRST LOW, TCK LOW or HIGH, TDI and TMS not connected or HIGH. The boundary scan chain has a length of 84 and a 5-bit instruction code.PARAMETER VALUE UNIT Frequency 24576 kHz Pull range ±50 ppm Operating temperature −40 to +85 °C Frequency drift with temperature≤±20 ppm Tolerance and ageing ≤±10 ppm

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Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H

15 PACKAGE OUTLINE

UNIT A 1 A 2 A 3 bp cE (1) eH E LL p Zywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 0.36 0.10 2.87 2.57 0.25 0.40 0.25 0.25 0.13 14.1 13.9 0.65 18.2 17.6 1.0 0.6 o o0.151.95 0.1 0.2 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 SOT317-1 MO-112 97-08-01 99-12-27 D (1) (1)(1) 20.1 19.9 H D 24.2 23.6 EZ 0.8 0.4 D bpe θ E A 1 A Lp detail X L (A )3 B c DH bp EH A 2 v M B D Z D A Z E e v M A 100 80 51 pin 1 index X y w M w M 0 5 10 mm scale A max. 3.3 100 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height QFP100: plastic quad flat package; SOT317-1

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Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H

16 SOLDERING

16.1 Introduction to soldering surface mount

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used.

16.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250°C. The top-surface temperature of the packages should preferable be kept below 230°C.

16.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis ispreferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250°C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

16.4 Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320°C.

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Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H

16.5 Suitability of surface mount IC packages for wave and reflow soldering methods

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. PACKAGE SOLDERING METHOD WAVE REFLOW (1) BGA, SQFP not suitable suitable HLQFP , HSQFP , HSOP , HTSSOP , SMS not suitable(2) suitable PLCC (3), SO, SOJ suitable suitable LQFP , QFP , TQFP not recommended (3)(4) suitable SSOP , TSSOP , VSO not recommended (5) suitable

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Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H

17 DATA SHEET STATUS

1. Please consult the most recently issued data sheet before initiating or completing a design. DATA SHEET STATUS PRODUCT STATUS DEFINITIONS (1) Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

18 DEFINITIONS

Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

19 DISCLAIMERS

Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

20 PURCHASE OF PHILIPS I

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.

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Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H NOTES

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Philips Semiconductors Preliminary specification Digital audio broadcast channel decoder SAA3500H NOTES

© Philips Electronics N.V. SCA All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Internet: http://www.semiconductors.philips.com 2000 69 Philips Semiconductors – a worldwide company For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria:Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil:see South America Bulgaria:Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

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