SAA32MXXX

SAA32M4 ETC1 | Alldatasheet

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Technical content

128Mb: x4, x8, x16 DDR SDRAM PDF: 09005aef80505d1b / Source: 09005aef80469e44 128Mb: x4, x8, x16 DDR SDRAM Rev: 11/23/2004 www.spectek.com SpecTek reserves the right to change products or specifications without notice. © 2001, 2002, 2004 SpecTek DOUBLE DATA RATE (DDR) SDRAM

• PC1600 and PC2100 compatible
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• Bi-directional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 hastwo – one per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible) Options: Designation: Family SpecTek Memory SAA Configuration

32 Meg x 4 (8 Meg x 4 x 4 banks) 32M4

16 Meg x 8 (4 Meg x 8 x 4 banks) 16M8

8 Meg x 16 (2 Meg x 16 x 4 banks) 8M16

DDR 128 Megabit Design Yx6x (Call SpecTek Sales for details on availability of “x” placeholders) Voltage and refresh 2.5V, Auto Refresh V4 2.5V, Self or Auto Refresh R4 Plastic Package – OCPL 66-pin TSOP TL (400 mil width, 0.65mm pin pitch) Timing – Cycle Time 7.5ns @ CL = 2.5 (PC2100) -75A 10ns @ CL = 2.5 (PC1600) -8A Part number example: SAA16M8T95AV4TL-75A (For part numbers prior to December 2004, refer to page 13 for decoding.)

128Mb: x4, x8, x16 DDR SDRAM PDF: 09005aef80505d1b / Source: 09005aef80469e44 128Mb: x4, x8, x16 DDR SDRAM Rev: 11/23/2004 www.spectek.com SpecTek reserves the right to change products or specifications without notice. © 2001, 2002, 2004 SpecTek GENERAL DESCRIPTION The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM. The 128Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2 n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 128Mb DDR SDRAM effectively consists of a single 2 n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-h alf-clock-cycle data transfers at the I/O pins. A bi-directional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte and one for the upper byte. The 128Mb DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power- saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All full drive strength outputs are SSTL_2, Class II compatible. NOTE 1: The functionality and the timing specifications discussed in this data sheet are for the DLL-enabled mode of operation. NOTE 2: Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the x16 is divided in to two bytes — the lower byte and upper byte. For the lower byte (DQ0 through DQ7) DM refers to LDM and DQS refers to LDQS; and for the upper byte (DQ8 through DQ15) DM refers to UDM and DQS refers to UDQS. ABSOLUTE MAXIMUM RATINGS* VDD Supply Voltage VDDQ Supply VREF and Inputs Voltage I/O Pins Voltage Disclaimer: Except as specifically provided in this document, SpecTek makes no warranties, expressed or implied, including, but not limited to, any implied warranties of merchantability or fitness for a particular purpose. Any claim against SpecTek must be made within 1 year from the date of shipment from SpecTek, and SpecTek has no liability thereafter. Any liability is limited to replacement of the defective items or return of amounts paid for defective items (at buyer’s election). In no event will SpecTek be responsible for special, indirect, consequential or incidental damages, even if SpecTek has been advised for the possibility of such damages. SpecTek’s liability from any cause pursuant to this specification shall be limited to general monetary damages in an amount not to exceed the total purchase price of the products covered by this specification, regardless of the form in which legal or equitable action may be brought against SpecTek.

128Mb: x4, x8, x16 DDR SDRAM PDF: 09005aef80505d1b / Source: 09005aef80469e44 128Mb: x4, x8, x16 DDR SDRAM Rev: 11/23/2004 www.spectek.com SpecTek reserves the right to change products or specifications without notice. © 2001, 2002, 2004 SpecTek DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (25°C < TA < +70°C; VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V) PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES Supply Voltage VDD 2.3 2.7 V 41 I/O Supply Voltage VDDQ 2.3 2.7 V 41, 44 I/O Reference Voltage V REF 0.49 X VDDQ 0.51 X VDDQ V 6, 44 I/O Termination Voltage (system) V TT VREF – 0.04 V REF – 0.04 V 7, 44 Input High (Logic 1) Voltage V IH (DC) V REF + 0.15 V DD + 0.3 V 28 Input Low (Logic 0) Voltage V IL (DC) -0.3 V REF – 0.15 V 28 Clock Input Voltage Level; CK and CK# V IN -0.3 V DDQ + 0.3 V Clock Input Differential Voltage; CK and CK# V ID 0.36 V DDQ + 0.6 V 8 Clock Input Crossing Point Voltage; CK and CK# V IX 1.15 1.35 V 9 INPUT LEAKAGE CURRENT Any input, 0V < VIN < VDD, VREF pin 0V < VIN < 1.35V (All other pins not under test = 0V) II -2 2 μA OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V < VOUT < VDDQ) IOZ -7 7 μA IOH -16.8 -- mAOUTPUT LEVELS: Full drive option - x4 , x8, x16 High Current (VOUT = VDDQ-0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF,maximum VTT) IOL 16.8 -- mA 37, 39 IOHR -9 -- mAOUTPUT LEVELS: Reduced drive option - x16 only High Current (VOUT = VDDQ-0.763V, minimum VREF, minimum VTT) Low Current (VOUT = 0.763V, maximum VREF,maximum VTT) IOLR 9- - m A 38, 39

128Mb: x4, x8, x16 DDR SDRAM PDF: 09005aef80505d1b / Source: 09005aef80469e44 128Mb: x4, x8, x16 DDR SDRAM Rev: 11/23/2004 www.spectek.com SpecTek reserves the right to change products or specifications without notice. © 2001, 2002, 2004 SpecTek AC INPUT OPERATING CONDITIONS (25°C < TA < + 70°C; VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V) PARAMETER/CONDITION SYMBOL MIN MAX UNIT S NOTES Input High (Logic 1) Voltage V IH (AC)V REF + 0.310 -- V 14, 28, Input Low (Logic 0) Voltage V IL (AC)- - V REF – 0.310 V 14, 28, Clock Input Differential Voltage; CK and CK# V ID (AC) 0.7 V DDQ + 0.6 V 8 Clock Input Crossing Point Voltage; CK and CK# V IX (AC) 0.5 X V DDQ – 0.2 0.5 X V DDQ + 0.2 V 9 I/O Reference Voltage V REF (AC) 0.49 X V DDQ 0.51 X VDDQ V6

128Mb: x4, x8, x16 DDR SDRAM PDF: 09005aef80505d1b / Source: 09005aef80469e44 128Mb: x4, x8, x16 DDR SDRAM Rev: 11/23/2004 www.spectek.com SpecTek reserves the right to change products or specifications without notice. © 2001, 2002, 2004 SpecTek CAPACITANCE (x4, x8) (25°C < TA < +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V) PARAMETER SYMBOL MIN MAX UNITS NOTES Delta Input/Output Capacitance: DQs, DQS, DM DC IO -- 0.50 pF 24 Delta Input Capacitance: Command and Address DC I1 -- 0.50 pF 29 Delta Input Capacitance: CK, CK# DC I2 -- 0.25 pF 29 Delta Input Capacitance: DQs, DQS, DM C IO 4.0 5.0 pF Input Capacitance: Command and Address C I1 2.0 3.0 pF Input Capacitance: CK, CK# C I2 2.0 3.0 pF Input Capacitance: CKE C I3 2.0 3.0 pF IDD SPECIFICATIONS AND CONDITIONS (x4, x8) (25°C < TA < +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V) PARAMETER/CONDITION SYMBOL -75 -8 UNITS NOTES OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles; IDD0 105 100 mA 22, 48 OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD1 120 115 mA 22, 48 PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK(MIN); CKE=LOW; IDD2P 10 10 mA 23, 32, IDLE STANDBY CURRENNT: CS# = HIGH; All banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM IDD2N 50 45 mA 51 ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3P 18 18 mA 23, 32, ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. I DD3N 50 45 mA 22 OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R 120 110 mA 22, 48 OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W 120 110 mA 22 AUTO REFRESH CURRENT tRC = tRFC (MIN) IDD5 250 225 mA 22, 50 SELF REFRESH CURRENT (Part number ‘R’ only) I DD72 2 m A1 1 OPERATING CURRENT: Four bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tRC (MIN); Address and control inputs change only during Active, READ, or WRITE commands. IDD8 330 285 mA 22, 49

128Mb: x4, x8, x16 DDR SDRAM PDF: 09005aef80505d1b / Source: 09005aef80469e44 128Mb: x4, x8, x16 DDR SDRAM Rev: 11/23/2004 www.spectek.com SpecTek reserves the right to change products or specifications without notice. © 2001, 2002, 2004 SpecTek CAPACITANCE (x16) (25°C < TA < +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V) PARAMETER SYMBOL MIN MAX UNITS NOTES Delta Input/Output Capacitance: DQ0 – DQ7, LDQS, LDM DC IOL -- 0.50 pF 24 Delta Input/Output Capacitance: DQ8-DQ15, UDQS, UDM DC IOU -- 0.50 pF 24 Delta Input Capacitance: Command and Address DC I1 -- 0.50 pF 29 Delta Input Capacitance: CK, CK# DC I2 -- 0.25 pF 29 Input/Output Capacitance: DQs, LDQS, UDQS, LDM, UDM C IO 4.0 5.0 pF Input Capacitance: Command and Address C I1 2.0 3.0 pF Input Capacitance: CK, CK# C I2 2.0 3.0 pF Input Capacitance: CKE C I3 2.0 3.0 pF IDD SPECIFICATIONS AND CONDITIONS (x16) (25°C < TA < +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V) PARAMETER/CONDITION SYMBOL -75 -8 UNITS NOTES OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles; IDD0 115 105 mA 22, 48 OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD1 140 115 mA 22, 48 PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK(MIN); CKE=LOW; IDD2P 10 10 mA 23, 32, IDLE STANDBY CURRENNT: CS# = HIGH; All banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. V IN = VREF for DQ, DQS, and DM IDD2N 50 45 mA 51 ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3P 18 18 mA 23, 32, ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. I DD3N 50 45 mA 22 OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R 170 160 mA 22, 48 OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W 150 145 mA 22 AUTO REFRESH CURRENT tRC = tRFC (MIN) IDD5 255 225 mA 22, 50 SELF REFRESH CURRENT (Part number ‘R’ only) I DD72 2 m A1 1 OPERATING CURRENT: Four bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tRC (MIN); Address and control inputs change only during Active, READ, or WRITE commands. IDD8 330 285 mA 22, 49

128Mb: x4, x8, x16 DDR SDRAM PDF: 09005aef80505d1b / Source: 09005aef80469e44 128Mb: x4, x8, x16 DDR SDRAM Rev: 11/23/2004 www.spectek.com SpecTek reserves the right to change products or specifications without notice. © 2001, 2002, 2004 SpecTek ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (25°C < TA < +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V) AC CHARACTERISTICS -75 -8 PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES Access window of DQs from CK/CK# tAC -0.75 +0.75 -0.8 +0.8 ns CK high-level width tCH 0.45 0.55 0.45 0.55 tCK 30 CK low-level width tCL 0.45 0.55 0.45 0.55 tCK 30 CL = 2.5 tCK (2.5) 7.5 12 10 12 ns 52Clock cycle time DQ and DM input hold time relative to DQS tDH 0.5 0.6 ns 26, 31 DQ and DM input setup time relative to DQS tDS 0.5 0.6 ns 26, 31 DQ and DM input pulse width (for each input) tDIPW 1.75 2 ns 31 Access window of DQS from CK/CK# tDQSCK - 0.75 +0.75 - 0.8 +0.8 ns DQS input high pulse width tDQSH 0.35 0.35 tCK DQS input low pulse width tDQSL 0.35 0.35 tCK DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ 0.5 0.6 ns 25, 26 DQS-DQ skew, first DQS to last DQ valid, per access tDQSQA 0.7 0.8 ns 36 Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 tCK DQS falling edge to CK rising – setup time tDSS 0.2 0.2 tCK DQS falling edge from CK rising – hold time tDSH 0.2 0.2 tCK Half clock period tHP tCH, tCL tCH, tCL ns 34 Data-out high-impedance window from CK/CK# tHZ -0.75 +0.75 -0.8 +0.8 ns 18 Data-out low-impedance window from CK/CK# tLZ -0.75 +0.75 -0.8 +0.8 ns 18 Address and control input hold time (fast slew rate) tIHf .90 1.1 ns 14 Address and control input setup time (fast slew rate) tISf .90 1.1 ns 14 Address and control input hold time (slow slew rate) tIHs 1 1.1 ns 14 Address and control input setup time (slow slew rate) tISs 1 1.1 ns 14 LOAD MODE REGISTER command cycle time tMRD 15 16 ns DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH tHP - tQHS tHP - tQHS ns 25, 26 Data hold skew factor tQHS 0.75 1 ns ACTIVE to PRECHARGE command tRAS 45 16,000 50 16,000 ns 35 ACTIVE to READ with Auto precharge command tRAP ns 46 ACTIVE to ACTIVE/AUTO REFRESH command period tRC 65 70 ns AUTO REFRESH command period tRFC 75 80 ns 50 ACTIVE to READ or WRITE delay tRCD 20 20 ns PRECHARGE command period tRP 20 20 ns DQS read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 42 DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK ACTIVE bank a to ACTIVE bank b command tRRD 15 15 ns

128Mb: x4, x8, x16 DDR SDRAM PDF: 09005aef80505d1b / Source: 09005aef80469e44 128Mb: x4, x8, x16 DDR SDRAM Rev: 11/23/2004 www.spectek.com SpecTek reserves the right to change products or specifications without notice. © 2001, 2002, 2004 SpecTek ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS, (continued) AC CHARACTERISTICS -75 -8 PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES DQS write preamble tWPRE 0.25 0.25 tCK DQS write preamble setup time tWPRES 0 0 ns 20, 21 DQS write postamble tWPST 0.4 0.6 0.4 0.6 tCK 19 Write recovery time tWR 15 15 ns Internal WRITE to READ command delay tWTR 1 1 tCK Data valid output window na tQH - tDQSQ tQH - tDQSQ ns 25 REFRESH to REFRESH command interval tREFC 140.6 140.6 μs 23 Average periodic refresh interval tREFI 15.6 15.6 μs 23 Terminating voltage delay to Vdd tVTD 0 0 ns Exit SELF REFRESH to non-READ command (Part number R only) tXSNR 75 80 ns Exit SELF REFRESH to READ command (Part number R only) tXSRD 200 200 tCK

128Mb: x4, x8, x16 DDR SDRAM PDF: 09005aef80505d1b / Source: 09005aef80469e44 128Mb: x4, x8, x16 DDR SDRAM Rev: 11/23/2004 www.spectek.com SpecTek reserves the right to change products or specifications without notice. © 2001, 2002, 2004 SpecTek NOTES 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: properly initialized, and is averaged at the defined cycle rate. 4. AC timing and I DD tests may use a VIL-t o - VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between V IL(AC) and VIH(AC). 5. The AC and DC input level specifications areas defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. V REF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non- common mode) on V REF may not exceed ±2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to V REF and must track variations in the DC level of VREF. 8. VID is the magnitude of the difference between the input level on CK and the input level on CK#. 9. The value of Vix is expected to equal VddQ/2 of the transmitting device and must track variations in the DC level of the same. 10. Idd is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at CL = 2.5 for –7.5 and -8 with the outputs open. 11. Enables on-chip refresh and address counters. 12. I DD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 13. This parameter is sampled. V DD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, TA = 25°C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 14. Command/Address input slew rate = 0.5V/ns. For -7 and -75 with slew rates 1V/ns and faster, tIS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. 15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. 16. Inputs are not recognized as valid until V REF stabilizes. Exception: during the period before V REF stabilizes, CKE < 0.3 x VDDQ is recognized as LOW. 17. The output timing reference level, as measured at the timing reference point indicated in Note 3, is V TT. 18. tHZ and t LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS.

128Mb: x4, x8, x16 DDR SDRAM PDF: 09005aef80505d1b / Source: 09005aef80469e44 128Mb: x4, x8, x16 DDR SDRAM Rev: 11/23/2004 www.spectek.com SpecTek reserves the right to change products or specifications without notice. © 2001, 2002, 2004 SpecTek NOTES, continued 22. MIN ( tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 23. The refresh period 64ms. This equates to an average refresh rate of 15.625μs. However, an AUTO REFRESH command must be asserted at least once every 140.6μs; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maxi-or mum amount for any given device. 25. The valid data window is derived by achieving other specifications - tHP ( tCK/2), tDQSQ, and tQH ( tQH = tHP - tQHS). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 26. Referenced to each output group: x4 = DQS with DQ0-DQ3; x8 = DQS with DQ0-DQ7; x16 = LDQS with DQ0-DQ7 and UDQS with DQ8- DQ15. 27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period ( tRFC [MIN]) else CKE is LOW (i.e., during standby). 28. To maintain a valid level, the transitioning edge of the input must: a) Sustain a constant slew rate from the Current AC level through to the target AC level, V IL(AC) VIH(AC). b) Reach at least the target AC level. c) After the AC target level is reached, continue to maintain at least the target DC level, V IL(DC) or VIH(DC). 29. The Input capacitance per pin group will not differ by more than this maximum amount for any given device. 30. CK and CK# input slew rate must be >1V/ns. 31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. 32. VDD must not vary more than 4% if CKE is not active while any bank is active. 33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount. 34. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK/ inputs, collectively during bank active. 35. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN) can be satisfied prior to the internal precharge command being issued. 36. Applies to x16 only. First DQS (LDQS or UDQS) to transition to last DQ (DQ0-DQ15) to transition valid. Initial JEDEC specifications suggested this to be same as tDQSQ. 37. Note 37 is not used. 38. Note 38 is not used. 39. Note 39 is not used. 40. V IH overshoot: VIH(MAX) = VDDQ+1.5V for a pulse width < 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL(MIN) = -1.5V for a pulse width < 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 41. VDD and VDDQ must track each other. 42. Note 42 is not used. 43. Note 43 is not used. 44. During initialization, VddQ, Vtt, and Vref must be equal to or less than Vdd + 0.3V. Alternatively, Vtt may be 1.35V maximum during power up, even if Vdd /VddQ are 0 volts, provided a minimum of 42 ohms of series resistance is used between the Vtt supply and the input pin.

128Mb: x4, x8, x16 DDR SDRAM PDF: 09005aef80505d1b / Source: 09005aef80469e44 128Mb: x4, x8, x16 DDR SDRAM Rev: 11/23/2004 www.spectek.com SpecTek reserves the right to change products or specifications without notice. © 2001, 2002, 2004 SpecTek NOTES, continued 45. Note 45 is not used. 46. tRAP > tRCD. 47. Note 47 is not used. 48. Random addressing changing 50% of data changing at every transfer. 49. Random addressing changing 100% of data changing at every transfer. 50. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later. 51. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.” 52. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles.

128Mb: x4, x8, x16 DDR SDRAM PDF: 09005aef80505d1b / Source: 09005aef80469e44 128Mb: x4, x8, x16 DDR SDRAM Rev: 11/23/2004 www.spectek.com SpecTek reserves the right to change products or specifications without notice. © 2001, 2002, 2004 SpecTek

128Mb: x4, x8, x16 DDR SDRAM PDF: 09005aef80505d1b / Source: 09005aef80469e44 128Mb: x4, x8, x16 DDR SDRAM Rev: 11/23/2004 www.spectek.com SpecTek reserves the right to change products or specifications without notice. © 2001, 2002, 2004 SpecTek PART NUMBERS FOR PRODUCT PRIOR TO DECEMBER 2004 OPTIONS MARKING

• Configuration

32 Meg x 4 (8 Meg x 4 x 4 banks) S40032

16 Meg x 8 (4 Meg x 8 x 4 banks) S80016

8 Meg x 16 (2 Meg x 16 x 4 banks) S16008

• Voltage and refresh 2.5V, Auto Refresh VH 2.5V, Self or Auto Refresh RH
• Parent Device Configuration

32 Meg x 4 8

16 Meg x 8 7

8 Meg x 16 9

• Plastic Package – OCPL 66-pin TSOP TW (400 mil width, 0.65mm pin pitch)
• Timing – Cycle Time 7.5ns @ CL = 2.5 (PC2100) -75A 10ns @ CL = 2.5 (PC1600) -8A (Example part number: S80016VH7TW-75A) http://www.spectek.com/menus/part_guides.asp