SA8028 PHILIPS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 28
Technical content
/C0080 /C0115 /C0111/C0110/C0111 /C0115 SA8028
2.5 GHz sigma delta fractional-N /
760 MHz IF integer frequency synthesizers
Supersedes data of 2002 Jan 09 File under Integrated Circuits — IC17
2002 Feb 22
Philips Semiconductors Product data SA80282.5 GHz sigma delta fractional-N /
22002 Feb 22 853-2277 27777
The SA8028 BICMOS device integrates programmable dividers, charge pumps and phase comparators to implement phase–locked loops. The device is designed to operate from 3 NiCd cells, in pocket phones, with low current and nominal 3 V supplies. The synthesizer operates at VCO input frequencies up to 2.5 GHz. The synthesizer has fully programmable RF, IF, and reference dividers. All divider ratios are supplied via a 3-wire serial programming bus. The RF divider is a fractional-N divider with programmable integer ratios from 33 to 509 and a fractional resolution of 22 programmable bits (23 bits internal). A 2 nd order sigma-delta modulator is used to achieve fractional division. Separate power and ground pins are provided to the charge pumps and digital circuits. VDDCP must be equal to or greater than VDD . The ground pins should be externally connected to prevent large currents from flowing across the die and thus causing damage. The charge pump current (gain) is fully programmable, while I SET is set by an external resistance at the RSET pin (refer to section 1.5, RF and IF Charge Pumps). The phase/frequency detector charge pump outputs allow for implementing a passive loop filter.
FEATURES
- Extremely low phase noise: L(f) = –101 dBc/Hz at 5 kHz offset at 800 MHz
- Low power
- Programmable Normal & Integral charge pump outputs: Maximum output = 10.4 mA
- Digital fractional spurious compensation
- Hardware and software power-down
- IDDsleep < 0.1 µA (typ) at VDD = 3.0 V
- Seperate supply for VDD and VDDCP
- Programmable loop filter bandwidth
APPLICATIONS
- 500 to 2500 MHz wireless equipment
- Cellular phones, all standards including: CDMA : IS95-B,C WCDMA 3G : WCDMA / UMTS GSM : EDGE / GPRS TDMA : IS136 and EDGE GAIT : GSM and TDMA
- WLAN
- Wireless PDAs
- Satellite tuners and all other high frequency equipment
- Extreme fine frequency resolution applications 137 TOP VIEW 8 9 10 11 12 192021222324 CLOCK REFin+ REFin– SR02176 N/C VDDPre GND GND Pre RFin+ RFin– GND CP PHP PHI GND PHA IFin N/C DATA STROBE PON LOCK TEST V DD CP VDDCP R SET
Figure 1. HBCC24 pin configuration.
ORDERING INFORMATION
SA8028W HBCC24 Plastic, heatsink bottom chip carrier; 24 terminals; body 4 x 4 x 0.65 mm (CSP package)SOT564-1
Philips Semiconductors Product data SA80282.5 GHz sigma delta fractional-N /
2002 Feb 22 3
VDDCP = VDD = VDDpre= +3.0 V, Tamb = +25°C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDD , VDDpre Digital supply voltage VDD = VDDpre 2.7 – 3.6 V VDDCP Charge pump supply voltage VDDCP ≥ VDD , VDDpre 2.7 – 3.6 V IDDtotal Total supply current RF and IF. on – 7.6 – mA IDDsleep Total supply current in power-down mode – 0.1 1 µA fRFin VCO Input frequency range 500 – 2500 MHz fIFin Input frequency range 100 – 760 MHz fREFin Crystal reference input frequency 5 – 30 MHz fCOMPMAX Maximum phase comparator frequency RF phase comparator; max. limit is indicative – – 30 MHz Tamb Operating ambient temperature –40 – +85 °C
2002 Feb 22 4
Figure 2. HBCC24 Block Diagram
Philips Semiconductors Product data SA80282.5 GHz sigma delta fractional-N /
2002 Feb 22 5
In accordance with the Absolute Maximum Rating System SYMBOL PARAMETER MIN. MAX. UNIT VDD Digital supply voltage –0.3 +3.6 V VDDCP Charge pump supply voltage –0.3 +3.6 V VDDpre Analog supply voltage –0.3 +3.6 V ΔVDD Difference in supply voltages VDDCP – VDDpre (VDDCP ≥ VDDpre, VDD ) –0.3 +0.9 V Vn All input pins –0.3 VDD + 0.3 V ΔVGND Difference in voltage between GNDpre, GNDCP and GND (these pins should be connected together) –0.3 +0.3 V Tstg Storage temperature –55 +125 °C Tamb Operating ambient temperature –40 +85 °C Tj Maximum junction temperature 150 °C Handling Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. THERMAL CHARACTERISTICS SYMBOL PARAMETER VALUE UNIT R th j–a HBCC24: Thermal resistance from junction to ambient in still air30 °C/W
Philips Semiconductors Product data SA80282.5 GHz sigma delta fractional-N /
2002 Feb 22 6
VDDCP = VDD = VDDpre= +3.0 V, Tamb = +25°C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDD , VDDpre Digital supply voltage, prescaler supply voltageVDD = VDDpre 2.7 – 3.6 V VDDCP Charge pump supply voltage VDDCP ≥ VDD, VDDpre 2.7 – 3.6 V IDDTotal Synthesizer operational total supply currentfREF = 20 MHz (with RF on, IF on) – 7.6 – mA (with RF on, IF off) – 6.4 – mA IDDsleep Total supply current in power-down mode logic levels 0 or VDD – 0.1 1 µA RF divider input fRFin RF VCO input frequency range 500 – 2500 MHz VRFin AC-coupled input signal level R in (external) = Rs = 50 Ω ; single-ended drive; –15 – 0 dBm g max. limit is indicative @ 500 to 2500 MHz 112 – 632 mV pp ZRFin Input impedance Re (Z) fRFin = 2.4 GHz – 300 – Ω C RFin Typical pin input capacitance fRFin = 2.4 GHz – 1 – pF N RF RF divider ratio ranges Limited test coverage 33 – 509 FCOMPmax Maximum phase comparator frequency RF phase comparator – – 30 MHz IF divider input fIFin Input frequency range 100 – 760 MHz VIFin AC-coupled input signal level fIFin: 100 MHz to 500 MHz R (external) R 50 Ω ; –15 – 0 dBm R in (external) = R S = 50 Ω ; max. limit is indicative 112 – 632 mV pp fIFin: 500 MHz to 760 MHz R (external) R 50 Ω ; –10 – 0 dBm R in (external) = R S = 50 Ω ; max. limit is indicative 200 – 632 mV pp ZFin Input impedance Re (Z) fRFin = 500 MHz – 3.9 – kΩ C Fin Typical pin input capacitance fRFin = 500 MHz – 0.5 – pF N IF IF division ratio 128 – 16383 Reference divider input fREFin Input frequency range from TCXO 5 – 30 MHz VREFin AC-coupled input signal level single-ended drive; max. limit is indicative 360 – 1300 mV PP ZREFin Input impedance Re (Z) fREF = 20 MHz – 10 – kΩ C REFin Typical pin input capacitance fREF = 20 MHz – 1 – pF R REF Reference division ratio SA = ”000”, IF loop 4 – 1023 Charge pump current setting resistor input R SET External resistor from pin to ground 6 7.5 15 kΩ VSET Regulated voltage at pin R SET = 7.5 kΩ – 1.22 – V Charge pump outputs; RSET = 7.5 kΩ ICP Charge pump current ratio to ISET 1 Current gain = IPH /ISET –15 – +15 % IMATCH Sink-to-source current matching VPH = 1/2 VDDCP –10 – +10 % IZOUT Output current variation versus VPH 2 VPH in compliance range –10 – +10 % ILPH Charge pump off leakage current VPH = 1/2 VDDCP –10 – +10 nA VPH Charge pump voltage compliance 0.6 – VDDCP –0.7 V
2002 Feb 22 7
noise of 900 MHz RF signal at 5 kHz offset. noise of 1800 MHz RF signal at 5 kHz offset. noise of 800 MHz RF signal at 5 kHz offset. noise of 2100 MHz RF signal at 5 kHz offset. ISET = bias current for charge pumps.
- The relative output current variation is defined as:
Figure 3. Relative output current variation.
2002 Feb 22 8
1.0 FUNCTIONAL DESCRIPTION
(typically a VCO) is used to generate the desired output frequency. synthesizer operates at VCO input frequencies up to 760 MHz. Figure 4. PLL block diagram.
1.1 RF Fractional-N divider
(AC-coupled) to one of the inputs while the other one is AC grounded. allowable division ratios, see the “characteristics” table. During each RF divider cycle, one divider output pulse is generated. characteristic is +20 dB/dec for offset frequencies up to approx.
1.2 IF divider
fully programmable bipolar prescaler followed by a CMOS counter. programmed into the C-Word for the IF divider.
1.3 Reference divider (see Figure 5)
(not reference divider) to the input of the RF phase detector. Figure 5. Reference divider.
2002 Feb 22 9
1.4 Phase detector (see Figure 6)
time (backlash time, τ) at every cycle providing improved linearity. for the IF synthesizer, the reference input to the IF phase detector is the output from the reference divider. τ (backlash time) is the delay that fixes the minimum allowable charge pump activity time. Figure 6. Phase detector structure with timing.
2002 Feb 22 10
1.5 RF and IF Charge Pumps
Table 1. RF and IF charge pump currents
- ISET = VSET /RSET: bias current for charge pumps.
- CP1 = 1 is used to disable the PHI pump.
- IPHP–SU is the total current at pin PHP during speed up condition.
1.6 Charge Pumps Speed-up Mode
some programmability to the loop filter bandwidth. dis-spu = 1 (in D-word <D16>). Figure 7. Typical passive 3-pole loop filter.
1.7 Lock Detect
(AND/ORed) with the RF phase detector indicates a lock condition. when both counters are powered down.
1.8 Power-down mode
programming the PD = Power Down bits (<B10, B9>) in the B-word). 2.4.2 illustrates how power-down mode can be implemented. bits now programmed for power-up. reset to all zeros, following initial power-up, to avoid unknown states.
2002 Feb 22 11
2.0 SERIAL PROGRAMMING BUS
A simple 3-line bidirectional serial bus is used to program the circuit. typical programming sequence is illustrated in Figure 10. time between words must be observed (refer to Figure 8). feature to output the contents of an addressable internal register. i.e., by sending a D-word with the TreadN-bit (<D11>) set to “high”. input mode, even when the chip is in the output mode. Table 2. Serial bus timing requirements (see Figures 8 and 9) Figure 8. Serial bus “Write” timing diagram.
2002 Feb 22 12
Figure 9. Serial bus “Read” timing diagram.
2002 Feb 22 13
Figure 10. Typical programming sequence
2002 Feb 22 14
2.1 Data format
LSB first in, and MSB last in. Table 3. Format of programmed data
2.2 Register addressing
Table 4. Register addressing Notice that the register addresses are the MSB in each word; thus, the last to be clocked into the registers.
2.3 A-word register
Table 5. A-word, length 24 bits
2.3.1 The fractional multiplier <A21:A0>
maximum length). This leaves 22 bits (Kn<22:1>) available for external programming. Refer to Table 6. Calculating the desired VCO output frequency can be easily accomplished by using the following equation, Equation (1). where fref is the reference frequency at the REF input pin and N is the integer multiplier. Kn, once again, is the fractional multiplier. Determine the Kn value required for generating a VCO frequency of 2100 MHz with a reference frequency of 19.68 MHz.
2002 Feb 22 15
Table 6. Kn values for the fractional divider
2.4 B-word register
Table 7. B-word, length 24 bits R-Divider R0..R9, Reference divider values, see section “characteristics” for allowed divider ratios. N-Divider Nn sets the integer part of the RF divider ratio, see section “characteristics” for allowed ratios.
2.4.1 The RF divider <B8:B0>
the input of the REFin is the comparison frequency.
19.68 MHz /C0042
19.68 MHz
2002 Feb 22 16
Table 8. Allowable integer values (N) for the RF divider
2.4.2 Power–down <B10:B9>
the end of the A-word. STROBE does not need to be held high until that second falling edge of the RF divider output pulse has occurred. current when the bus is inactive. It can always capture new programmed data, even during power-down. signal must be toggled only after the A-word has been sent and STROBE has gone high and then low. divider must be powered up for the RF phase detector to become active. zeros, following initial power-up, to avoid unknown states. Table 9. Power-down Truth Table
2002 Feb 22 17
2.4.3 Programming the IF Reference Divider <B21:B12>
zeros. Table 10 lists the allowable R values. Table 10. R Values for the IF Reference Divider
2.5 C-word Register
Table 11. C-word, length 24 bits A-Divider A0..A13, IF divider values , see section “characteristics for allowed for divider ratios. CP1, CP0: Charge pump current ratio, see table of charge pump currents. Reset bit 1 → Tsigrst : resets the sigma-delta modulator after each loading of an A-word.
2.5.1 Programming the SA Counter <C2:C0>
The 3 bit SA register determines which of the 5 divider outputs (refer to table 11) is selected as the IF phase detector’s input (see Figure 5). Table 12. IF phase comparator frequency
- fref is the input frequency at the REFin pin.
2.5.2 Programming the Reset Bits <B11>, <C3>
has gone high at the end of the A-word.
2002 Feb 22 18
2.5.3 Programming the Lock Detect <C4:C5>
Lock detection is available only for the RF and IF phase detector. A ‘0’ in bit <C4:C5> is used for TTL, while a ‘1’ in bit <C4:C5> is used for RTL. Table 13. Lock detect select
- Combined RF_IF lock detect signal present at the lock pin (push/pull).
2.5.4 Programming the Charge Pump Gain <C7:C6>
The RF phase detector drives the charge pumps on the PHP and PHI pins, while the IF phase detector drives the charge pump on the PHA pin.
2.5.5 Programming the IF Divider for the IF Loop <C21:C8>
possible values that can be programmed into the C-word for the IF divider. Table 14. Allowable Values (A) for the IF Divider
2.6 D-word Register
power-up, to avoid unknown states. Table 15. D-word, length 24 bits D word address Fixed to 110. Tdis-spu Speed-up mode disabled. NOTE: All other test bits must be set to 0 for normal operation. Tspu: Speed up Speed-up mode always on. NOTE: All other test bits must be set to 0 for normal operation. refer to Section 2.0, Serial Programming Bus.
2002 Feb 22 19
3.0 Typical Performance Characteristics
Figure 11. PHI_SU charge pump output vs. Iset Figure 12. PHI_SU charge pump output vs. temperature Figure 13. PHI_SU charge pump output vs. Iset Figure 14. PHI_SU charge pump output vs. temperature
2002 Feb 22 20
Figure 15. PHP charge pump output vs. Iset Figure 16. PHP charge pump output vs. temperature Figure 17. PHP charge pump output vs. Iset Figure 18. PHP charge pump output vs. temperature
2002 Feb 22 21
Figure 19. PHP_SU charge pump output vs. Iset Figure 20. PHP_SU charge pump output vs. temperature Figure 21. PHP_SU charge pump output vs. Iset Figure 22. PHP_SU charge pump output vs. temperature
2002 Feb 22 22
Figure 23. PHA charge pump output vs. Iset Figure 24. PHA charge pump output vs. temperature Figure 25. PHA charge pump output vs. Iset Figure 26. PHA charge pump output vs. temperature
2002 Feb 22 23
Figure 27. RF (main) divider input sensitivity vs. frequency Figure 28. RF (main) divider input sensitivity vs. frequency Figure 29. RF (main) fractional divider input sensitivity vs. Figure 30. RF (main) fractional divider input sensitivity Figure 31. IF (aux) divider input sensitivity vs. frequency and Figure 32. IF (aux) divider input sensitivity vs. frequency and
2002 Feb 22 24
Figure 33. Reference divider input sensitivity vs. frequency Figure 34. Reference divider input sensitivity vs. frequency Figure 35. Total supply current vs. temperature
Philips Semiconductors Product data SA80282.5 GHz sigma delta fractional-N /
2002 Feb 22 25
4.0 Application Schematic
Philips Semiconductors Product data SA80282.5 GHz sigma delta fractional-N /
2002 Feb 22 26
HBCC24: plastic, heatsink bottom chip carrier; 24 terminals; body 4 x 4 x 0.65 mm SOT564-1
Philips Semiconductors Product data SA80282.5 GHz sigma delta fractional-N /
2002 Feb 22 27
Philips Semiconductors Product data SA80282.5 GHz sigma delta fractional-N /
2002 Feb 22 28
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 02-02 Document order number: 9397 750 09499 /C0080 /C0115 /C0111/C0110/C0111 /C0115 Data sheet status[1] Objective data Preliminary data Product data Product status[2] Development Qualification Production Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.