SA8016 PHILIPS | Alldatasheet
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/C0080 /C0115 /C0111/C0110/C0111 /C0115 SA8016 2.5GHz low voltage fractional-N synthesizer Product specification Supersedes data of 1999 Apr 16
1999 Nov 04
Philips Semiconductors Product specification SA80162.5GHz low voltage fractional-N synthesizer
21999 Nov 04 853–2142 22636
The SA8016 BICMOS device integrates programmable dividers, charge pumps and a phase comparator to implement a phase-locked loop. The device is designed to operate from 3 NiCd cells, in pocket phones, with low current and nominal 3 V supplies. The synthesizer operates at VCO input frequencies up to 2.5 GHz. The synthesizer has fully programmable main and reference dividers. All divider ratios are supplied via a 3-wire serial programming bus. Separate power and ground pins are provided to the analog and digital circuits. The ground leads should be externally short-circuited to prevent large currents flowing across the die and thus causing damage. V DDCP must be greater than or equal to VDD . The charge pump current (gain) is set by an external resistance at the RSET pin. Only passive loop filters could be used; the charge pump operates within a wide voltage compliance range to provide a wider tuning range.
FEATURES
- Low phase noise
- Low power
- Fully programmable main divider
- Internal fractional spurious compensation
- Hardware and software power down
- Split supply for VDD and VDDCP
APPLICATIONS
- 350–2500 MHz wireless equipment
- Cellular phones (all standards)
- WLAN
- Portable battery-powered radio equipment. SR01505 16LOCK TEST VDD GND RFin+ RFin– GND CP PHP PON STROBE DATA CLOCK REFin+ REFin– R SET VDDCP
Figure 1. TSSOP16 Pin Configuration Figure 2. HBCC24 Pin configuration
ORDERING INFORMATION
SA8016DH TSSOP16 Plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 SA8016WC HBCC24 Plastic, heatsink bottom chip carrier; 24 terminals; body 4 × 4 × 0.65 mm (CSP package) SOT564-1
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Figure 3. Block Diagram (TSSOP16)
Philips Semiconductors Product specification SA80162.5GHz low voltage fractional-N synthesizer
1999 Nov 04 4
VDDPre 1 Prescaler supply voltage GND 2 Digital ground GND Pre 3 Prescaler ground RFin+ 4 RF input to main divider RFin– 5 RF input to main divider N/C 6 Not connected N/C 7 Not connected GND CP 8 Charge pump ground PHP 9 Main normal charge pump N/C 10 Not connected VDDCP 11 Charge pump supply voltage R SET 12 External resistor from this pin to ground sets the charge pump current N/C 13 Not connected N/C 14 Not connected REFin– 15 Reference input REFin+ 16 Reference input CLOCK 17 Programming bus clock input DATA 18 Programming bus data input N/C 19 Not connected STROBE 20 Programming bus enable input PON 21 Power down control LOCK 22 Lock detect output TEST 23 Test (should be either grounded or connected to V DD ) VDD 24 Digital supply NOTE: 1. GND CP is connected to the die-pad.
Philips Semiconductors Product specification SA80162.5GHz low voltage fractional-N synthesizer
1999 Nov 04 5
In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDD Digital supply voltage –0.3 +5.5 V VDDCP Analog supply voltage –0.3 +5.5 V ΔVDDCP –VDD Difference in voltage between VDDCP and VDD (VDDCP ≥ VDD ) –0.3 +2.8 V Vn Voltage at pins 1, 2, 5, 6, 11 to 16 –0.3 VDD + 0.3 V V1 Voltage at pin 8, 9 –0.3 VDDCP + 0.3 V ΔVGND Difference in voltage between GNDCP and GND (these pins should be connected together) –0.3 +0.3 V Tstg Storage temperature –55 +125 °C Tamb Operating ambient temperature –40 +85 °C Tj Maximum junction temperature 150 °C Handling Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. THERMAL CHARACTERISTICS SYMBOL PARAMETER VALUE UNIT R th j–a Thermal resistance from junction to ambient in free air 120 K/W
Philips Semiconductors Product specification SA80162.5GHz low voltage fractional-N synthesizer
1999 Nov 04 6
VDDCP = VDD = +3.0V, Tamb = +25°C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply; pins 3, 9 VDD Digital supply voltage 2.7 – 5.5 V VDDCP Analog supply voltage VDDCP = VDD 2.7 – 5.5 V IDDTotal Synthesizer operational total supply currentVDD = +3.0 V – 8.0 9.5 mA IStandby Total supply current in power-down mode logic levels 0 or VDD – 1 µA RFin main divider input; pins 5, 6 fVCO VCO input frequency 350 – 2500 MHz VRFin(rms) AC-coupled input signal level R in (external) = Rs = 50Ω ; single-ended drive; max. limit is indicative @ 500 to 2500 MHz –18 – 0 dBm ZIRFin Input impedance (real part) fVCO = 2.4 GHz – 210 – Ω C IRFin Typical pin input capacitance fVCO = 2.4 GHz – 1.0 – pF N main Main divider ratio 512 – 65535 fPCmax Maximum loop comparison frequency indicative, not tested – – 4 MHz Reference divider input; pins 11, 12 fREFin Input frequency range from TCXO 5 – 40 MHz VRFin AC-coupled input signal level single-ended drive; max. limit is indicative 360 – 1300 mV PP ZREFin Input impedance (real part) fREF = 20 MHz – 10 – kΩ C REFin Typical pin input capacitance fREF = 20 MHz – 1.0 – pF R REF Reference division ratio 4 – 1023 Charge pump current setting resistor input; pin 10 R SET External resistor from pin to ground 6 7.5 15 kΩ VSET Regulated voltage at pin R SET =7.5 kΩ – 1.25 – V Charge pump outputs (including fractional compensation pump); pin 8; RSET =7.5kΩ , FC=80 ICP Charge pump current ratio to ISET 1 Current gain IPH /ISET –15 +15 % IMATCH Sink-to-source current matching VPH =1/2 VDDCP –10 +10 % IZOUT Output current variation versus VPH 2 VPH in compliance range –10 +10 % ILPH Charge pump off leakage current VPH =1/2 VCC –10 +10 nA VPH Charge pump voltage compliance 0.7 – VDDCP –0.8 V
1999 Nov 04 7
of 900 MHz RF signal at 1 kHz offset. of 1800 MHz RF signal at 1 kHz offset. of 800 MHz RF signal at 1 kHz offset. of 2100 MHz RF signal at 1 kHz offset. bias current for charge pumps.
- The relative output current variation is defined as:
Figure 4. Relative Output Current Variation
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counter. Total divide ratios range from 512 to 65536. state of the main divider to avoid introducing a phase disturbance. values between 4 and 1023 followed by a three bit binary counter. every cycle (backlash time) providing improved linearity. Figure 5. Reference Divider
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Figure 6. Phase Detector Structure with Timing
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Low, charge pump will exit speed up mode. IPUMP_TOTAL = IPUMP + ICOMP . SET , programming or speed-up operation. FRD is the fractional accumulator value. NOTE: For a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output. Figure 7. Waveforms for NF = 2 Modulo 5 → fraction = 2/5
1930.140 MHz
Figure 8. Current Injection Concept
Philips Semiconductors Product specification SA80162.5GHz low voltage fractional-N synthesizer
1999 Nov 04 11
CP0 IPHP IPHP–SU 0 3xISET 15xlSET 1 1xlSET 5xlSET NOTES: 1. ISET =VSET /RSET bias current for charge pumps. 2. IPHP–SU is the total current at pin PHP during speed up condition. Lock Detect The output LOCK maintains a logic ‘1’ when the auxiliary phase detector ANDed with the main phase detector indicates a lock condition. The lock condition for the main and auxiliary synthesizers is defined as a phase difference of less than /C00341 period of the frequency at the input REFin+, –. One counter can fulfill the lock condition when the other counter is powered down. Out of lock (logic ‘0’) is indicated when both counters are powered down. Power-down mode The power-down signal can be either hardware (PON) or software (PD). The PON signal is exclusively ORed with the PD bits in B-word. If PON = 0, then the part is powered up when PD = 1. PON can be used to invert the polarity of the software bit PD. When the synthesizer is reactivated after power-down, the main and reference dividers are synchronized to avoid possibility of random phase errors on power-up.
Philips Semiconductors Product specification SA80162.5GHz low voltage fractional-N synthesizer
1999 Nov 04 12
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to program all counter divide ratios, fractional compensation DAC, selection and enable bits. The programming data is structured into 24 bit words; each word includes 2 or 3 address bits. Figure 9 shows the timing diagram of the serial input. When the STROBE goes active HIGH, the clock is disabled and the data in the shift register remains unchanged. Depending on the address bits, the data is latched into different working registers or temporary registers. In order to fully program the synthesizer, 2 words must be sent: B, and A. Table 1 shows the format and the contents of each word. The D word is normally used for testing purposes. When sending the B-word, data bits FC7–0 for the fractional compensation DAC are not loaded immediately. Instead they are stored in temporary registers. Only when the A-word is loaded, these temporary registers are loaded together with the main divider ratio. Serial bus timing characteristics (See Figure 9) VDD = VDDCP =+3.0V; Tamb = +25°C unless otherwise specified. SYMBOL PARAMETER MIN. TYP. MAX. UNIT Serial programming clock; CLK tr Input rise time – 10 40 ns tf Input fall time – 10 40 ns Tcy Clock period 100 – – ns Enable programming; STROBE tSTART Delay to rising clock edge 40 – – ns tW Minimum inactive pulse width 1/fCOMP – – ns tSU;E Enable set-up time to next clock edge 20 – – ns Register serial input data; DATA tSU;DAT Input data to clock set-up time 20 – – ns tHD;DAT Input data to clock hold time 20 – – ns
Application information
tSU;DAT tHD;DAT tr tw tf tSU;E tSTART Tcy MSB Figure 9. Serial Bus Timing Diagram
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Table 1. Format of programmed data Table 2. A word, length 24 bits Fractional Modulus selectFM 0 = modulo 8, 1 = modulo 5. Fractional-N Increment NF2..0 Fractional N Increment values 000 to 111. N-Divider N0..N15, Main divider values 512 to 65535 allowed for divider ratio. Table 3. B word, length 24 bits R-Divider R0..R9, Reference divider values 4 to 1023 allowed for divider ration. CP0: Charge pump current ratio, see table of charge pump currents. 0 Main lock detect signal present at the LOCK pin (push/pull). 1 Main lock detect signal present at the LOCK pin (open drain). When main loop is in power down mode, the lock indicator is low. Power down Main = 1: power to main divider, reference divider, main charge pumps, Main = 0 to power down. Fractional CompensationFC7..0 Fractional Compensation charge pump current DAC, values 0 to 255. Table 4. D word, length 24 bits Tspu: Speed up = 1 Forces the main charge pumps in speed-up mode all the time. NOTE : All test bits must be set to 0 for normal operation.
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Figure 10. Php Charge Pump Output vs. ISET Figure 11. Php Charge Pump Output vs. Temperature Figure 12. Php Charge Pump Output vs. ISET Figure 13. Php Charge Pump Output vs. Temperature Figure 14. Php–su Charge Pump Output vs. ISET Figure 15. Php–su Charge Pump Output vs. Temperature
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Figure 16. Php–su Charge Pump Output vs. ISET Figure 17. Php–su Charge Pump Output vs. Temperature Figure 18. Main Divider Input Sensitivity vs. Frequency and Figure 19. Main Divider Input Sensitivity vs. Frequency and Figure 20. Reference Divider Input Sensitivity vs. Frequency Figure 21. Reference Divider Input Sensitivity vs. Frequency
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Figure 22. Current Supply Over VDD
2.5GHz low voltage fractional-N frequency synthesizer Philips Semiconductors Product specification SA8016
1999 Nov 04 17
HBCC24: plastic, heatsink bottom chip carrier; 24 terminals; body 4 x 4 x 0.65 mm SOT564-1
2.5GHz low voltage fractional-N frequency synthesizer Philips Semiconductors Product specification SA8016
1999 Nov 04 18
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
2.5GHz low voltage fractional-N frequency synthesizer Philips Semiconductors Product specification SA8016
1999 Nov 04 19
2.5GHz low voltage fractional-N frequency synthesizer Philips Semiconductors Product specification SA8016
1999 Nov 04 20
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 11-99 Document order number: 9397 750 06564 /C0080 /C0115 /C0111/C0110/C0111 /C0115 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.