SA25C1024 ETC | Alldatasheet
Document overview
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Technical content
Features
- = Saifun NROM™ Flash Cell
- = Serial Peripheral Interface (SPI) Compatible
- = Supports SPI Modes 0 (0,0) and 3 (1,1)
- = Byte and Page Write Modes (up to 128 bytes)
- = Single Supply Voltage: – 2.7V to 3.6V (L) – 4.5V to 5.5V (H)
- = 10MHz Clock Rate
- = Block Write Protection: – Protect ¼, ½, or Entire Array
- = Write Protect Pin and Write Disable Instructions of both Hardware and Software Data Protection
- = Self-timed Write Cycle (10mS max)
- = 100,000 Write Cycles (Minimum)
- = 20 Year Data Retention
- = Low-power Standby Current (less than 1µµµµA)
- = 8-SOIC Narrow Package (0.150” Wide Body, JEDEC SOIC)
- = Temperature Range: – Industrial: -40°C to +85°C – Commercial: 0°C to +70°C General Description SA25C1024 is a 1Mb CMOS non-volatile serial EEPROM, organized as a 128K x 8-bit memory. The SA25C1024 is available in a space-saving, 8-lead narrow SOIC package. In addition, it is available in a wide range of voltages – 2.7-3.6 V and 4.5-5.5 V. The SA25C1024 is enabled through the Chip Select (CSb) pin and is accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO) and Serial Data Clock (SCK). All write cycles are completely self-timed, and no separate ERASE cycle is required before write. (continued) 1Mb EEPROM SPI with 10MHz and Low Standby http://www.saifun.com Saifun NROMTM is a trademark of Saifun Semiconductors Ltd.
(continued) Programming the status register with top ¼, top ½ or entire array write protection enables BLOCK WRITE protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WPb pin to protect against inadvertent write attempts to the status register. The HOLDb pin may be used to suspend any serial communication without resetting the serial sequence.
Figure 1. SOIC 8 – Narrow/PDIP Package (Top View) Table 1. Pin Names
Ordering Information
X N MN Blank E L H 1024 C SA Interface Density Voltage Operating Range Temp. Range Package
Description
8-pin SOIC (SO8, 150 mil width) 0 to 70 oC -40 to +85 oC 2.7 V to 3.6 V 4.5 V to 5.5 V
1024 Kb with Write Protect
Figure 2: SA25C1024 Ordering Information
Ambient Storage Temperature -65 °C to +150 °C All input or output voltages with respect to Ground 4.5 V to -0.3 V (L) 6.5 V to -0.3 V (H) Lead Temperature (Soldering, 10 seconds) +235 °C Latch Up Specifications Latch Up 100 mA on all pins, +125°C ESD Specifications Human Body Model Per MIL-STD 883 Method 3015.7 Voltage Levels 500 V to 5 KV, in increments of 500 V; proceed to 8000 V or until failure Machine Model Per JEDEC standard JESD22-A115 Voltage levels 50 V to 300 V, in increments of 50 V; proceed to 500 V or until failure Operating Conditions Ambient Operating Temperature: SA25C1024 SA25C1024E 0 °C to +70 °C -40 °C to +85 °C Positive Power Supply: SA25C1024L SA25C1024H 2.7 V to 3.6 V 4.5 V to 5.5 V
- /G20 TAI = -40 ºC to 85 ºC, VCC = 2.7-3.6 V/4.5-5.5 V
- /G20 TAC = 0 ºC to 70 ºC, VCC = 2.7-3.6 V/4.5-5.5 V
Table 2. DC Characteristics
0.2 V L
0.8 V H
*Typical values are at TAI = 25 ºC and 3 V/5 V.
Figure 3. AC Measurements I/O Waveform Table 3. AC Measurements Table 4. AC Characteristics
10 MHz
The device that generates the SCK. Slave As the SCK pin is always an input, the SA25C1024 always operates as a slave. Transmitter/Receiver The SA25C1024 has separate pins designated for data transmission and reception. Serial Opcode The first byte is received after the device is selected. This byte contains the opcode that defines the operation to be performed (for more details, refer to Table 5, page 10). Invalid Opcode If an invalid opcode is received, no data is shifted into the SA25C1024, and the serial output pin remains in a high impedance state until a CSb falling edge is detected again, which reinitializes the serial communication. Chip Select (CSb) The SA25C1024 is selected when the CSb pin is low. When the device is not selected, data is not accepted via the SI pin, and the SO pin remains in a high impedance state. HOLDb The HOLDb pin is used in conjunction with the CSb pin to select the SA25C1024. When the device is selected and a serial sequence is underway, HOLDb can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLDb pin must be brought low while the SCK pin is low. To resume serial communication, the HOLDb pin is brought high while the SCK pin is low (SCK may still toggle during HOLDb). Inputs to the SI pin are ignored while the SO pin is in the high impedance state. Write Protect The WPb pin enables write operations to the Status register when held high. When the WPb pin is brought low and the WPBEN bit is 1, all write operations to the status register are inhibited (for more details, refer to Table 8, page 11). If WPb goes low while CSb is still low, the write to the status register is interrupted. If the internal write cycle has already been initiated, WPb going low has no effect on any write operation to the status register. The WPb pin function is blocked when the WPBEN bit in the status register is 0, which enables the user to install the SA25F020 in a system with the WPb pin tied to ground but still able to write to the status register. All WPb pin functions are enabled when the WPBEN bit is set to 1.
sending any write instruction. Table 7. Block Write Protect Bits disable the WPb pin via the WPBEN bit. to the status register are disabled. to 0 as long as the WPb pin is held low. Table 8. WPBEN Operation
- After the CSb line is pulled low to select
- The data (D7-D0) at the specified
Table 9. Read Status Register Definition ignored except the RDSR instruction.
- After the CSb line is pulled low to select
- Programming starts after the CSb pin is
Figure 7. HOLDb Timing
3 Byte Address
Figure 8. Read Timing Figure 9. Write Timing
All measurements are in inches (millimeters), unless otherwise specified. Figure 12. 8-pin SOIC Package
Figure 13. 8-pin Molded Small Outline Package (MN), 0.150” Wide Body, JEDEC SOIC
Figure 14. Molded Dual-in-line Package (N) Package Number N08E
Saifun Semiconductors Ltd. Headquarters ELROD Building 45 Hamelacha St. Sappir Industrial Park Netanya 42505 Israel Fax: +972-9-892-8445 Email: tech_support@saifun.com http://www.saifun.com
Revision History
Rev Date Description of Change Amendment 1.0 1-Sep-02 Initial Release 0 1.1 27-Jan-03 ESD scheme modification 1 Prepared by Approved by Approved by Signature Date Golan M. Shalhov Product Line Manager Shai Eisen Design Project Manager Doron Vertesh Director EEPROM SBU 27-Jan-03 © Saifun Semiconductors Ltd. 2003 Saifun reserves the right, without notice, to change any of the products described in this guide, in order to improve functionality, reliability or design. Saifun assumes no liability arising from the application or use of any product described in this guide; and under its patent rights, gives no authorization for the use of this product or associated products. The Buyer will not hold Saifun responsible for direct or indirect damages and expenses, as well as any claim of injury or death, associated with the unauthorized use, including claims of manufacture or design negligence. Other company and brand products and service names are trademarks or registered trademarks of their respective holders. Life Support Policy Saifun's products are not authorized for use as critical components in life support devices or systems without the express writ ten approval of the President of Saifun Semiconductors Ltd. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.