SA25C020 ETC | Alldatasheet

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Technical content

Features

  • = Saifun NROM™ Cell
  • = Serial Peripheral Interface (SPI) Compatible, Supports SPI Modes 0 (0,0) and 3 (1,1)
  • = Byte and Page Write Operation: – 1024 pages (256 Bytes/Page) – Single Byte or Page Write Cycle in 10ms Typical
  • = Single Supply Voltage: 2.7V to 3.6V
  • = 25MHz Clock Rate
  • = Block Write Protection: Protect Quarter, Half or Entire Array
  • = Write Protect Pin and Write Disable Instructions of Both Hardware and Software Data Protection
  • = 100,000 Erase Cycles (Minimum)
  • = More than 20-Year Data Retention
  • = Low-power Standby Current (less than 1µA)
  • = 8-SOIC Narrow Package
  • = MLF Leadless Package
  • = Temperature Range: – Industrial: -40°C to +85°C – Commercial: 0°C to +70°C 2Mb EEPROM with 25MHz SPI Bus Interface http://www.saifun.com Saifun NROMTM is a trademark of Saifun Semiconductors Ltd.

SA25C020 Advanced Information SAIFUN General Description The SA25C020 is a 2Mb (512K X 4) CMOS non-volatile serial EEPROM. This device fully conforms to the SPI 4-wire protocol, is enabled through the Chip Select (CSb) pin, and uses Clock (SCK), Data-in (SI) and Data-out (SO) pins to synchronously control data transfer between the SPI microcontroller and the Serial EEPROM. The memory can be written from 1 up to 256 bytes at a time via the Byte / Page Write (PW) instruction. The memory consists of 1024 pages or 262,144 bytes. Each device requires only a 3.0V power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The SA25C020 does not require a V PP supply. The HOLDb pin may be used to suspend any serial communication without resetting the serial sequence. In addition, the serial interface allows a minimal-pin-count packaging designed to simplify PC board layout requirements and offers the designer a variety of low-voltage and low-power options. The SA25C020 is available in a space-saving, 8-lead narrow SOIC package The SA25C020 is part of the SPI EEPROM family. It is designed to work with any SPI- compatible, high-speed microcontroller, and offers both hardware (WPb pin) and Software (“block protect”) data protection. For example, programming a 2-bit code into the status register prevents program with top ¼, top ½ or entire array write protection and enables block write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WPb pin to protect against inadvertent write attempts to the status register. Saifun’s SPI Serial EEPROM products are designed and tested for applications requiring high endurance and low power consumption for a continuously reliable non-volatile solution for all markets.

SA25C020 Advanced Information SAIFUN Table of Contents

  • = 262,144 bytes (8 bits each)
  • = 1024 pages (256 bytes each) Each byte or page can be individually written with the bits programmed from 1 to 0 and from 0 to 1. HOLDb WPb Vcc GND SO SI SCK CSb PSSRAM IO Array - R X D E CLogic Array - L DATA PATHRD

Figure 1. SA25C020 Block Diagram

Figure 2. SOIC 8 (150 mil)/PDIP/MLF Package (Top View) Table 1. Pin Names

SA25C020 Advanced Information SAIFUN

Ordering Information

X Blank E L 020 C SA Interface Density Voltage Operating Range Temp. Range Package

Description

-40 to +85 C o 2.7 V to 3.6 V

2 Mb with Write Protect

o N MN MLF 8-pin DIP 8-pin SOIC (150 mil) 8-lead MLF X Blank F Non Lead Free Lead Free Figure 3. SA25C020 Ordering Information

SA25C020 Advanced Information SAIFUN Product Specifications Absolute Maximum Ratings Storage Temperature -65 °C to +150 °C All input or output voltages with respect to Ground 4.5 V to -0.3 V Lead Temperature (Soldering, 10 seconds) +235 °C ESD/Latch Up Specification (JEDEC 8 Spec) Human Body Model Minimum 4 KV Machine Model Minimum 500 V Charge Device Model Minimum 1 KV Latch Up 100 mA on all pins +125°C Operating Conditions Operating Temperature: SA25C020 SA25C020 E 0 °C to +70 °C -40 °C to +85 °C Positive Power Supply: SA25C020 2.7 V to 3.6 V

Applicable over recommended operating range from TAI = -40 ºC to 85 ºC, VCC = 2.7-3.6 V. Table 2. DC Characteristics

25 MHz 9 12 mA

*Typical values are at TAI = 25 ºC and 3 V.

Table 3. AC Test Conditions

25 MHz

  • 256 bytes in the checkerboard programming formation.

Figure 6. AC Measurements I/O Waveform Table 4. AC Measurements

SA25C020 Advanced Information SAIFUN Signal Description Chip Select (CSb) This is an active-low input pin to the device that is generated by the master controlling the device. A low level on this pin selects the device, while a high level deselects the device. All serial communications with the device are enabled only when this pin is held low. Serial Clock (SCK) This is an input pin to the device that is generated by the master controlling the device. It is a clock signal that synchronizes the communication between a master and the device. All input information (SI) to the device is latched on the rising edge of this clock input, while output data (SO) from the device is driven after the falling edge of this clock input. Serial Input (SI) This is an input pin to the device that is generated by the master controlling the device. The master transfers input information (instruction, addresses and the data to be programmed) into the device serially via this pin. This input information is latched on the rising edge of the SCK. Serial Output (SO) This is an output pin from the device that is used to transfer output data to the controlling master. Output data is serially shifted out on this pin after the falling edge of the SCK. Hold (HOLDb) This is an active low input pin to the device that is generated by the master controlling the device. When driven low, this pin suspends any current communication with the device. The suspended communication can be resumed by driving this pin high. This feature eliminates the need to re-transmit the entire sequence by enabling the master to resume the communication from where it was left off. This pin should be tied high if this feature is not used. Refer to Hold Condition , page 15, for additional details. Write Protect (WPb) This is an active low input pin to the device. This pin allows enabling and disabling of writes to the device's memory array and status register. When this pin is held low, writes to the memory array and status register are disabled; when it is held high, they are enabled. Refer to Write Protect , page 16, for additional details.

SA25C020 Advanced Information SAIFUN Serial Interface These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:

  • = CPOL=0, CPHA=0
  • = CPOL=1, CPHA=1 In both of these modes, input data is latched on the rising edge of SCK, and output data is available from the falling edge of SCK. The difference between the two modes, as shown in Figure 7, is the clock polarity when the bus master is in Standby mode and is not transferring data, as follows:
  • = SCK remains at 0 for CPOL = 0, CPHA = 0
  • = SCK remains at 1 for CPOL = 1, CPHA = 1 MSB MSB CS CS SO SI CPOL CPHA

Figure 7. Supported SPI Modes The device that generates the SCK. SA25C020 always operates as a slave.

SO pin remains in a high impedance state. low is not a legal operation. Figure 8. Hold Condition

SA25C020 Advanced Information SAIFUN Write Protect The WPb pin enables write operations to the status register when held high. When the WPb pin is brought low and the WPBEN bit is 1, all write operations to the status register are inhibited (for more details, refer to Table 9, page 21). If WPb goes low while CSb is still low, the write to the status register is interrupted. If the internal write cycle has already been initiated, WPb going low has no effect on any write operations to the status register. The WPb pin function is blocked when the WPBEN bit in the status register is 0, which enables the user to install the SA25C020 in a system with the WPb pin tied to ground but still able to write to the status register. All WPb pin functions are enabled when the WPBEN bit is set to 1.

sending any write instruction. Table 7. Read Status Register Definition and the status register is write protected. Bits 6 through 4 are always 0.

  1. The CSb pin is pulled low to select
  2. The data on the SI pin becomes
  3. The data from the status register is

Figure 10. Read Status Register (RDSR) Instruction Sequence

Table 8. Block Write Protect Bits disable the WPb pin via the WPBEN bit. to the status register are disabled. to 0 while the WPb pin is held low. Table 9. WPBEN Operation

  1. When the WPb pin is held high
  2. When the WPb pin is held low, the
  1. After the CSb line is pulled low to
  2. Upon completion, any data on the
  3. The data (D7-D0) at the specified

sequence is shown in Figure 14. Figure 14. Read (READ) Instruction Sequence

SA25C020 Advanced Information SAIFUN Byte or Page Write (PW) The Byte or Page Write instruction allows bytes to be programmed and erased in the memory (changing bits from 1 to 0 and from 0 to 1). In order to program to the SA25C020, two separate instructions must be executed. The device must first be write enabled via the WREN instruction, and then a Byte or Page Write sequence (which consists of four bytes plus data) may be executed. The address of the memory locations to be written must be outside the protected address field location selected by the Block Write Protection level. During an internal Write cycle, all commands are ignored except the RDSR instruction. A Byte or Page Write instruction requires the following sequence: After the CSb line is pulled low to select the device, the WRITE opcode is transmitted via the SI line, followed by the byte address and the data (D7-D0) to be written. Programming starts after the CSb pin is brought high. The CSb pin's low-to-high transition must occur during the SCK low time, immediately after the clock in the D0 (LSB) data bit. The instruction sequence is shown in Figure 15, page 25. As soon as CSb is driven high, the self-timed Write cycle (whose duration is defined as T PW) is initiated. While the Page Write cycle is in progress, the status register may be read to check the value of the Write in Progress (/RDY) bit. The /RDY bit is 1 during the self-timed Page Write cycle, and 0 when it is completed. The Write Enable Latch (WEN) bit is reset at some unspecified time before the cycle is completed. The SA25C020's PW operation is capable of up to a 256-byte writing, from 1 to 256 bytes at a time (changing bits from 1 to 0 and from 0 to 1), provided that they lie in consecutive addresses on the same page of memory. After each byte is received, the eight low-order address bits are internally incremented by one. If more than 256 bytes of data are transmitted, the address counter rolls over and the previously written data is overwritten. The SA25C020 is automatically returned to the write disable state at the completion of a Write cycle. NOTES: 1. If the device is not write enabled, the device ignores the PW instruction and returns to the standby state when CSb is brought high. A new CSb falling edge is required to re-initiate the serial communication. 2. A PW instruction applied to a page that is protected by the Block Protect (BP1, BP0) bits (as described in Table 7, page 18, and Table 8, page 21) is not executed.

Figure 15. Byte or Page Write (PW) Instruction Sequence

Write Status Register cycle is in progress). has no effect on the cycle in progress. in on SI during the rising edge of SCK. sequence is shown in Figure 16. Signature to be output repeatedly. Figure 16. Read Electronic Signature (Read Id) Instruction Sequence

  • = VCC(min) at powerup, and then for a further delay of t PU (as described in Table 10)
  • = VSS at powerdown A simple pull-up resistor on CSb can usually be used to insure safe and proper powerup and powerdown. To avoid data corruption and inadvertent write operations during powerup, a Power On Reset (POR) circuit is included. The logic inside the device is held at reset while V CC is less than the POR threshold value (V POR), all operations are disabled and the device does not respond to any instructions. The device ignores all instructions until a time delay of t PU has elapsed after the moment that V CC rises above the VWI threshold. However, correct operation of the device is not guaranteed if by this time V CC is still below V CC(min). No Write Status Register, Program or Erase instructions should be sent until t PU reaches the minimum VCC threshold after VCC. At powerup, the device is in Standby mode (not SP mode) and the WEN bit is reset. Normal precautions must be taken for supply rail decoupling to stabilize the V CC feed. Each device in a system should have the V CC rail decoupled by a suitable capacitor close to the package pins (this capacitor is generally of the order of 0.1 µF). All operations are disabled and the device does not respond to any instructions when V CC drops at powerdown from the operating voltage to below the V POR threshold. (The designer must be aware that if a powerdown occurs while a Write, Program or Erase cycle is in progress, data corruption can result.)

Table 10. Powerup

All measurements are in inches (millimeters), unless otherwise specified. Figure 17. 8-pin SOIC Package

Figure 18. 8-pin MLF Leadless Package

Figure 19. Molded Dual-in-line Package (N) Package Number N08E

SA25C020 Advanced Information SAIFUN Contact Information International Headquarters United States Saifun Semiconductors Ltd. ELROD Building 45 Hamelach St. Sappir Industrial Park Netanya 42504 Israel Saifun Semiconductors Inc. 2350 Mission College Blvd. Suite 1070 Santa Clara, CA 95054 U.S.A. Tel: +1-408-982-5888 Fax: +1-408-982-5890 Email: tech_support@saifun.com http://www.saifun.com

Revision History

Rev Date Description of Change 0.0 20-July-03 Initial Release © Saifun Semiconductors Ltd. 2003 Saifun reserves the right, without notice, to change any of the products described in this guide, in order to improve functionality, reliability or design. Saifun assumes no liability arising from the application or use of any product described in this guide; and under its patent rights, gives no authorization for the use of this product or associated products. The Buyer will not hold Saifun responsible for direct or indirect damages and expenses, as well as any claim of injury or death, associated with the unauthorized use, including claims of manufacture or design negligence. Saifun and Saifun NROM are trademarks or registered trademarks of Saifun Semiconductors Ltd. Other company and brand products and service names are trademarks or registered trademarks of their respective holders. Life Support Policy Saifun's products are not authorized for use as critical components in life support devices or systems without the express writ ten approval of the President of Saifun Semiconductors Ltd. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.