SA24C1024LMFF

SA24C1024 ETC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 27

Technical content

Features

• = Saifun NROM™ NVM Technology
• = Operating voltage: 2.7V to 3.6V
• = Clock frequency: 100/400/1700/3400 kHz
• = Low power consumption – 0.5µµµµA standby current typical (L version) – <0.2µµµµA standby current typical (LZ version)
• = Write Modes – Byte Mode – Page Mode (128 Bytes/Page)
• = Schmitt trigger inputs
• = Hardware and software write protection for entire or partial array
• = Endurance: up to 1 million data changes
• = Data Retention: Greater than 40 years
• = Packages: 8-Pin DIP and 8-Pin SOIC and MLF Leadless
• = Temperature range – Commercial: 0 °C to +70 °C – Industrial (E): -40 °C to +85 °C 1024Kb EEPROM IIC http://www.saifun.com Saifun NROMTM is a trademark of Saifun Semiconductors Ltd.

The SA24C1024 is a 1024Kbit CMOS non- volatile serial EEPROM organized as 128K x 8 bit memory. This device conforms to Extended IIC 2-wire protocol, which enables accessing of memory in excess of 16 Kbits on an IIC bus. This serial communication protocol uses a Clock signal (SCL) and a Data signal (SDA) to synchronously clock data between a Master (for example, a microcontroller) and a Slave (EEPROM). The SA24C1024 offers hardware write protection whereby the entire memory array can be write-protected by pulling the WP pin to logic HIGH. The entire memory then becomes unalterable until the WP pin is switched to logic LOW. The device also features programmable write protect with options of full, half or a quadrant of the array. The LZ version of the SA24C1024 offers very low standby current, which makes it suitable for low power applications. The SA24C1024 is designed to minimize pin count and simplify PC board layout requirements. This device is offered in both SO and DIP packages. A leadless microleadframe package and CSP are under development. Saifun’s EEPROMs are designed and tested for applications requiring high endurance, high reliability and low power consumption.

Figure 1. SA24C1024 Block Diagram

Figure 2. SO Package (MW), Dual Inline (N) – Top For more details, refer to package number N08E and M08D. Table 1. Pin Names SDA IIC Data Input/Output Pin Open Collector/Drain type. When LOW, writing is allowed to the memory array. defined in Write Protect (WP), page 14.

Ordering Information

L LZ 1024 C SA Interface Density Voltage Operating Range

Description

2.7 V to 3.6 V 2.7 V to 3.6 V < 0.7 µA Standby Current

1 Mb with Write Protect

X Blank X Tube Tape and Reel PP Package N MW MF 8-pin DIP 8-pin SOIC (200 mil) 8-lead MLF F Blank F Non-lead Free Lead-free Leads E Blank E Temp. Range 0 to 70 C -40 to +85 C o o Figure 4. SA24C1024 Ordering Information

Absolute Maximum Ratings Operating Conditions Ambient Storage Temperature –65 °C to +150 °C All Input or Output Voltages with Respect to Ground 4.5 V to -0.3 V Lead Temperature (Soldering, 10 seconds) +300 °C ESD Rating 2000 V min. ESD/Latch up Specification (JEDEC 8 Spec) Human Body Model Minimum 2 KV Machine Model Minimum 500 V Latch up 100 mA on all pins, +125 °C Operating Conditions Ambient Operating Temperature:

• = SA24C1024
• = SA24C1024E 0°C to +70°C –40°C to +85°C Positive Power Supply:
• = SA24C1024
• = SA24C1024LZ 2.7 V to 3.6 V 2.7 V to 3.6 V

VCC (2.7 V to 3.6 V) DC Electrical Characteristics Limits Symbol Parameter Test Conditions Min Typ (Notes) Max Units fSCL = 100 kHz (Read) 2 3 mA fSCL = 100 kHz (Write) 8 11 mA fSCL = 400 KHZ (Read) 2 3 mA fSCL = 400 kHz (Write) 8 11 mA fSCL = 1.7 MHz (Read) 5 7 mA fSCL = 1.7 MHz (Write) 8 11 mA fSCL = 3.4 MHz (Read) 5 7 mA ICCA Active Power Supply Current fSCL = 3.4 MHz (Write) 8 11 mA ISB Standby Current (L) V IN = GND or VCC 0.5 1 µA Standby Current (LZ) VIN = GND or VCC 0.2 0.7 µA= IIL Input Leakage Current VIN = GND to VCC 0.1 1 µA IOL Output Leakage Current VOUT = GND to VCC 0.1 1 µA VIL Input Low Voltage -0.3 V CC x 0.3 V VIH Input High Voltage VCC * 0.7 V CC + 0.5 V VOL Output Low Voltage I OL = 3 mA 0.4 V Notes: (1) Typical values are TA = +25 °C and nominal supply voltage of 3 V. (2) Write frequency is 50 Hz. Capacitance TA = +25 °C, f = 100/400 kHz/1.7 MHz/3.4 MHz, VCC = 3V (see note 2) Symbol Test Conditions Max Units CI/O Input/Output Capacitance (SDA) V I/O = 0 V 8 pF CIN Input Capacitance (A0, A1, A2, SCL) V IN = 0 V 6 pF Notes: (1) This parameter is periodically sampled and not 100% tested. (2) Typical values are T A = +25 °C and nominal supply voltage of 3 V.

Figure 5. AC Testing Input/Output Waveforms

2 This parameter is not tested but ensured by characterization. Figure 6. Bus Timing

signal (SCL) and a Data signal (SDA). to discontinue the communication).

10100 A 1 A d d 1 6 R / W (LSB)

Figure 9. Slave Address

The IIC bus is designed to support a variety of devices, such as RAMs, EPROMs, and so on, as well as EEPROMS. In order to properly identify the various devices on the IIC bus, a 4-bit Device Type identifier string is used. For EEPROMS, this 4-bit string is 1-0-1-0. Every IIC device on the bus internally compares this 4-bit string to its own Device Type string to ensure proper device selection. Device/Page Block Selection When multiple devices of the same type (for example, multiple EEPROMS) are present on the IIC bus, the A1 address information bit is used in device selection. Every IIC device on the bus internally compares the first 2 bits of the Device/Page Block selection string to its own physical configuration (0, A1pin – for the SA24C1024, the Device/Page Block selection MSB is always 0) to ensure proper device selection. This comparison is carried out in addition to the Device Type comparison. In addition to selecting an EEPROM, the second and third Device/Page Block selection bits (A1, add16) can be viewed as selection controls to a page block within the selected EEPROM. Each page block is 512 Kbits (64 KBytes) in size. Read/Write Bit The last bit of the Slave address indicates whether the intended access is Read or Write. If the bit is 1, the access is Read; if it is 0, the access is Write. Acknowledge Acknowledge is an active LOW pulse on the SDA line that is driven by an addressed receiver to the addressing transmitter to indicate receipt of 8 bits of data. The receiver provides an ACK pulse for every 8 bits of data received. This handshake mechanism is done as follows: 1. After transmitting 8 bits of data, the transmitter releases the SDA line and waits for the ACK pulse. 2. The addressed receiver, if present, then drives the ACK pulse on the SDA line during the 9th clock and releases the SDA line back to the transmitter. For more details, see Figure 12. Array Address#1 This is an 8-bit information that contains the most significant 8 bits (without the MSB bit, which is the add16 bit located in the Slave address byte) of the 17-bit memory array address. Array Address#0 This is an 8-bit information that contains the least significant 8 bits of the 17-bit memory array address.

protected against accidental programming. This pin has an internal pulldown circuit. Table 2. Write Protection Truth Table

1 YES 0 NO

1 NO 0 YES

1 YES 1 YES

1 NO 1 NO

0 Don't Care Don't Care YES

to 0 during all accesses to the device.

Choice 2: Programmable Write Protect (1) The Programmable Write protection is available to customers by contacting a Sales Representative. For this option, use an internal 8-bit wide internal NV-Latch with the following definition: T/BA10A11A12A13A14A15A16 Bit 0Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7 Address Protection Range - Bit[7:1] These 7 MSBs of array address determine the address range that needs to be protected. Top or Bottom Selection - Bit[0] 0 = Protects from address 0x0000 up to the address set in Bits[7:1]. 1 = Protects from address 1xFFFF up to the address set in Bits[7:1]. 1 Predefined on Sort. Not a user command. Example (1024K ) Write Protection Area NV-Latch Bit Setting - Bits [7:0] Result

1 Full Array

Address bits (A16:A10) issued during the Write command are compared against bits[7:1] of this NV-Latch. As bit[0] of this NV-Latch is set to 1, Write is not allowed as long as the comparison results in a greater than or equal to status.

2 Bottom Half

(0x0000 – 0x0FFFF) 1-0-0-0-0-0-0-0 As in example 1.

3 Bottom Quadrant

(0x0000 – 0x07FFF) 0-1-0-0-0-0-0-0 As in example 1.

4 Top Quadrant

Address bits (A16:A10) issued during the Write command are compared against bits[7:1] of this NV-Latch. As bit[0] of this NV-Latch is set to 1, Write is allowed as long as the comparison results in a greater than or equal to status.

5 Top Half

(0x10000 – 0x1FFFF) 1-0-0-0-0-0-0-1 As in example 4. 6 No Write Protection 0-0-0-0-0-0-0-0 As in example 4.

The SA24C1024 supports a bidirectional bus-oriented protocol, which defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is defined as the Master and the device that is controlled is the Slave. The Master always initiates data transfers and provides the clock for both transmit and receive operations. The SA24C1024 is therefore considered to be the Slave in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions. For more details, see Figure 10. START Condition All commands are preceded by the START condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SA24C1024 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition has been met. For more details, see Figure 11. STOP Condition All communications are terminated by a STOP condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The STOP condition is also used by the SA24C1024 to place the device in the standby power mode. For more details, see Figure 11. SA24C1024 Array Addressing During Read/Write operations, addressing the EEPROM memory array involves providing the Slave address with the Most Significant Address bit (add16), as well as two address bytes, Word Address 1 and Word Address 0. The Word Address 1 byte contains the 8 MSBs of the array address, while the Word Address 0 byte contains the 8 LSBs of the array address.

Two address bytes are required after the Slave address, which contains the Most Significant Address bit (add16), for a byte Write operation. These 17 address bits select one out of the 128K locations in the memory. The Master provides these address bytes, and for each address byte received, the SA24C1024 responds with an ACK pulse. The Master then provides a byte of data to be written into the memory. Upon receipt of this data, the SA24C1024 again responds with an ACK pulse. The Master then terminates the transfer by generating a STOP condition, at which time the SA24C1024 begins the internal write cycle to the memory. While the internal write cycle is in progress, the SA24C1024 inputs are disabled, and the device does not respond to any requests from the Master for the duration of t WR. For more details regarding the address, acknowledge and data transfer sequence, see Figure 13. Page Write To minimize write cycle time, the SA24C1024 offers a Page Write feature, which allows simultaneous programming of up to 128 contiguous bytes. To facilitate this feature, the memory array is organized in terms of “pages.” A page consists of 128 contiguous byte locations starting at every 128-byte address boundary (for example, starting at array address 0x00000, 0x00080, 0x00100, and so on). The Page Write operation is confined to a single page, which means that it does not cross over to locations on the next page but rolls over to the beginning of the page whenever the end of the page is reached and additional data bytes continue to be provided. A Page Write operation can be initiated to begin at any location within a page (the starting address of the Page Write operation does not have to be the starting address of a page). Page Write is initiated in the same manner as the Byte Write operation; however, rather than terminate the cycle after transmitting the first data byte, the Master can further transmit up to 127 more bytes. After the receipt of each byte, the SA24C1024 responds with an ACK pulse, increments the internal address counter to the next address, and is ready to accept the next data. If the Master transmits more than 128 bytes prior to generating the STOP condition, the address counter rolls over and previously loaded data is re-loaded. As with the Byte Write operation, all inputs are disabled until completion of the internal write cycle. For more details regarding the address, acknowledge, and data transfer sequence, see Figure 14.

Read operations are initiated in the same manner as Write operations, with the exception that the R/ W bit of the Slave address is set to 1. There are three basic Read operations: current address Read, random Read, and sequential Read. Current Address Read Internally the SA24C1024 contains an address counter that maintains the address of the last byte accessed, incremented by 1. Therefore, if the last access (either a Read or Write) was to address n, the next Read operation would access data from address n + 1. Upon receipt of the Slave address with R/ W set to 1, the SA24C1024 issues an ACK pulse and transmits the 8- bit word. The Master does not acknowledge the transfer but does generate a STOP condition, which causes the SA24C1024 to discontinue transmission. For more details regarding the sequence of address, acknowledge and data transfer, see Figure 15. Random Read Random Read operations enable the Master to access any memory location in a random manner. Prior to issuing the Slave address with the R/ W bit set to 1, the Master must first perform a “dummy” Write operation. The Master issues the START condition, the Slave address's R/ W bit is set to 0 and the byte address is read. After the byte address is acknowledged, the Master immediately issues another START condition and the Slave address's R/ W bit is set to 1. This is followed by an ACK from the SA24C1024 and then by the 8-bit word. The Master does not acknowledge the transfer but does generate the STOP condition, which causes the SA24C1024 to discontinue transmission. For more details regarding address, acknowledge, and data transfer sequence, see Figure 16. Sequential Read Sequential Reads can be initiated as either a current address Read or random access Read. The first word is transmitted in the same manner as the other Read modes; however, the Master responds with an ACK pulse, indicating it requires additional data. The SA24C1024 continues to output data for each ACK received. The Read operation is terminated either by the Master not responding with an ACK pulse or by generating a STOP condition.

• = S mode: Maximum bit transfer rates of 100 Kbps.
• = F mode: Maximum bit transfer rates of 400 Kbps.
• = HS mode: Maximum bit transfer rates of 3.4 Mbps. After reset and initialization, the device must be put in F mode. The Master on the bus can then choose to switch the connected Slave devices to HS mode. The Slave device must recognize the "S 00001XXX A" sequence and then must switch its internal circuit from F mode to HS mode. Each device must also recognize the STOP condition and switch back to F mode. Timings and flow can be seen in Figure 18 and Figure 19.

Figure 18. Data Transfer

Figure 19. A Complete HS Mode Transfer

All measurements are in inches (millimeters), unless otherwise specified. Figure 20. 8-pin Molded Small Outline Package (MW8), Package Number M08D

Figure 21. Molded Dual-in-Line Package (N), Package Number N08E

Figure 22. 8-pin MLF Leadless Package

International Headquarters United States Saifun Semiconductors Ltd. ELROD Building 45 Hamelach St. Sappir Industrial Park Netanya 42504 Israel Fax: +972-9-892-8445 Saifun Semiconductors Inc. 2350 Mission College Blvd. Suite 1070 Santa Clara, CA 95054 U.S.A. Tel: +1-408-982-5888 Fax: +1-408-982-5890 Email: tech_support@saifun.com http://www.saifun.com

Revision History

Rev Date Description of Change 0.0 05-Sep-02 Initial release 1.0 05-Dec-02 Editing and review 1.1 26-Aug-03 Endurance, MLF Package and t DH © Saifun Semiconductors Ltd. 2003 Saifun reserves the right, without notice, to change any of the products described in this guide, in order to improve functionality, reliability or design. Saifun assumes no liability arising from the application or use of any product described in this guide; and under its patent rights, gives no authorization for the use of this product or associated products. Saifun makes no warranty for use of its products, other than expressly provided by Saifun in any applicable warranty. The Buyer will not hold Saifun responsible for direct or indirect damages and expenses, as well as any claim of injury or death, associated with the unauthorized use, including claims of manufacture or design negligence. Saifun and Saifun NROM are trademarks or registered trademarks of Saifun Semiconductors Ltd. Other company and brand products and service names are trademarks or registered trademarks of their respective holders. Life Support Policy Saifun's products are not authorized for use as critical components in life support devices or systems without the express writ ten approval of the President of Saifun Semiconductors Ltd. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.