SA2400A

SA2400A PHILIPS | Alldatasheet

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/C0080 /C0115 /C0111/C0110/C0111 /C0115 SA2400A Single chip transceiver for

2.45 GHz ISM band

Philips Semiconductors Product data SA2400ASingle chip transceiver for 2.45 GHz ISM band

22002 Nov 04 853-2320 28727

1. DESCRIPTION The SA2400A is a fully integrated single IC RF transceiver designed for 2.45 GHz wireless LAN (WLAN) applications. It is a direct conversion radio architecture that is fabricated on an advanced

30 GHz f

T BiCMOS process. The SA2400A combines a receiver, transmitter, and LO generation into a single IC. The receiver consists of a low-noise amplifier, down-conversion mixers, fully integrated channel filters, and an Automatic Gain Control (AGC) with an on-chip closed loop. The transmitter contains power ramping, filters, up-conversion, and pre-drivers. The LO generation is formed by an entirely on-chip VCO and a fractional-N synthesizer. Typical system performance parameters for the receiver are 93 dB gain, 7.5 dB noise figure, input-referred third-order intercept point (IIP3) of +1 dBm, AGC settling time of 8 µs, and Tx-to-Rx switching time of 3 µs. The transmitter typical system performance parameters are an output power range from –7 dBm to +8 dBm in 1 dB steps, –40 dBc carrier leakage after calibration, 22 dB sideband suppression, in-band common mode rejection of 30 dB, and Rx-to-Tx switching time of 3 µs. 2. FUNCTIONAL BLOCKS AND FEATURES The block diagram of the SA2400A Direct Conversion transceiver is given in Figure 1. It consists of the following functional blocks: A 79 dB adjustable gain range direct conversion zero IF receiver with 3 µs (typical) Tx to Rx switching time, and comprising the following: – Front-end LNA with two internal gain states – A fast on-chip closed loop composite RF and IF AGC with zoomed analog RSSI output and 8 µs settling time – Quadrature downconverters from 2.45 GHz RF directly to zero IF – On-chip fast baseband DC cancellation with automatically stepped bandwidths of 10 MHz, 1 MHz, 100 kHz, and 10 kHz, settling within 8–13 µs for a DC error of 10% that decays to 1%. – Fully integrated channel filters, appropriate for 11 Msymbols/s QPSK modulation RF bandwidth. An I/Q upconverter from baseband directly to 2.45 GHz, with +8 dBm output power, –40 dBc typical carrier leakage (calibrated) and 3 µs (typical) Rx to Tx switching time, and comprising the following: – Wide band IQ modulator producing better than 14% EVM for

11 Msymbols/s QPSK modulation

– Integrated reconstruction and spectral shaping filters at I and Q modulation input that is driven by an external D/A. High common mode rejection to input ground bounce. – FIR-DACs for digital I/Q input feeding the analog signal path and including additional filtering for spectral shaping. – 2.45 GHz power amplifier driver with +8 dBm maximum output, 15 dB adjustable gain in 1 dB steps and a second switched output at –1.5 dBm power level with similar gain adjustments that are set by a separate register. – Completely on-chip calibration for Carrier Leakage compensation. – Internal power ramping with 2 µs delay and 0.5 µs ramp-up time. A fractional-N frequency synthesizer with on-chip VCO and XO A 3-wire bus for control of most blocks An additional high speed 3-wire bus for full control of Rx-Gain and DC-offset compensation parameters with 44Mbits/s. Fast Tx-Rx switching based on a single digital input pin. Reference currents and voltage for supply of Baseband Processor and PA-chip. 3. APPLICATIONS IEEE 802.11 and 802.11b radios – Supports DSSS and CCK modulation – Supports data rates: 1, 2, 5.5, and 11 Mbps

2.45 GHz ISM band wireless communication devices

Table 1. Ordering Information

DESCRIPTION

plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2

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2 RSSI

2 LOCK

Figure 1. SA2400A functional block diagram.

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Figure 2. Pin configuration.

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Table 2. Pin description

35 Transmit input AI/DI

36 Transmit input AI/DI

Philips Semiconductors Product data SA2400ASingle chip transceiver for 2.45 GHz ISM band

2002 Nov 04 6

1. FUNCTIONAL DESCRIPTION The SA2400A transceiver is intended for operation in the 2.45 GHz band, specifically for IEEE 802.11b 1 and 2 Mbits/s DSSS, and 5.5 and 11 Mbits/s CCK standards. Throughout this document, the operating RF frequency refers to the ISM band between 2.4 GHz and 2.5 GHz.

6.1 RF VCO

The local oscillator is common to both the transmitter and the receiver. The RF VCO is a differential 4.8 GHz oscillator with the frequency determining components internal to the IC. The VCO is connected internally to a frequency divider and a quadrature generator circuit which produces the LO for the IQ up- and downmixer. The divider output is also internally connected to the synthesizer, which can be programmed in order to produce steps of 0.5 MHz for the desired LO frequency. At the time of power-up, the VCO must be calibrated by invoking the VCOCALIB mode by means of the three-wire bus. This operation will select an appropriate frequency band in the VCO, thus compensating for process tolerances. The calibration takes up to 2.2 ms, after which the IC automatically enters the SLEEP mode. The synthesizer registers 0x00 through 0x03 must be re-programmed after completing the VCOCALIB. The 2.45 GHz LO can also be injected externally.

6.2 RF Low Noise Amplifier

The RF LNA has differential inputs and an external balun is needed in the case of single-ended operation. It has two gain states which are controlled internally by the on-chip automatic gain control, or manually via the 3-wire bus.

6.3 Downconversion mixers

The RF signal is converted down directly to baseband by quadrature image-reject mixers.

6.4 Receiver low-pass filter, baseband amplifiers

The I and Q low-pass filters are fully integrated Chebychev active filters. The I and Q pass band extends from DC to a –3 dB corner at 7 MHz. Additional adjustable gain is provided in baseband amplifiers to achieve a total adjustable gain range of 79 dB. The Rx output is provided in the form of differential I and Q signals, which must be DC coupled to the ADC inputs on a base band IC.

6.5 DC cancellation

The Rx chain also integrates a high-pass filter (DC notch) for cancellation of the DC offset inherent to zero-IF operation. The high-pass filter has a programmable lower 3 dB cutoff frequency of 10 MHz, 1 MHz, 100 kHz or 10 kHz. The DC offset cancellation occurs simultaneously with the AGC settling process. During the AGC settling phase (see below) the cutoff frequency is dynamically selected between 10 MHz and 1 MHz to quickly reduce DC offset values from +50 dBc to below –20 dBc relative to a –76 dBm antenna input signal before the RSSI (see below) is internally sampled. After the AGC settling, the high pass is configured for 100 kHz for 5 µs before switching to a final 10 kHz cutoff frequency. The low value of 10 kHz is required for minimizing the signal distortion created by a high-pass function at zero frequency. The high-pass will then remain set to the 10 kHz cutoff frequency until a new AGC cycle is started. Whenever there is a frequency change in the high-pass filter lower cutoff, the DC offset can change from a very low value to about 50% (1 MHz ≥ 100 kHz step) or 10% (100 kHz ≥ 10 kHz step) of the signal level. This DC offset then decays according to the high-pass response of the filter. The cutoff frequency of the high-pass filter can also be selected manually by using the RXMGC mode.

6.6 AGC

The receiver contains a fully integrated Automatic Gain Control loop. It works by adjusting the internal gain such that the Rx output amplitude, as measured by the RSSI (see below), meets a predefined target value. By default, the AGC is always set to a default maximum gain (adjustable by register value GMAX) whenever the SA2400A enters the RECEIVE mode of operation from another operational mode. It takes 5 µs for the receiver to settle when it enters this mode, which includes the time for DC offsets to be removed with a 1 MHz lower cut-off frequency of the high-pass filtering. This lower cut-off frequency of 1 MHz remains unchanged as long as the AGC remains in the default maximum gain state. The AGC must be invoked by providing a 0-to-1 transition on the AGCRESET pin, and keeping the signal on that pin to 1 for at least 5 µs. By successively reducing the gain from its initial maximum value, the loop searches for the correct gain value to provide a nominal output amplitude of 500 mV peak, differential for a QPSK signal (within ±3 dB dynamic error) at the output pins. This is achieved after a maximum of 8 µs. This time is defined by wait periods necessary to settle the receiver after gain switching actions. The individual wait periods can be adjusted by means of register settings. After completing the AGC settling process, the AGCSET pin is set to 1 by the algorithm. The receiver gain then will not change again until another pulse is issued on the AGCRESET pin. For a subsequent AGC operation, the receiver needs to enter its maximum gain state again. If another AGCRESET signal (as described above) is issued, the settling period will take an extra 3 µs, up to a total of 11 µs, since the first 3 µs will be spent on entering maximum gain mode and settling the receiver thereafter. To shorten this operation, the receiver can be forced to maximum gain (e.g., at a time when no signal is present) by issuing a 0–1–0 pulse of maximum 1 µs pulse width on the AGCRESET pin. The receiver will then enter maximum gain mode (the AGCSET signal will not be set to 1 after this), and a following 0-to-1 transition on the AGCRESET pin will start the settling sequence from maximum gain, which will then take a maximum of 8 µs. The receiver gain can also be selected manually by using the RXMGC mode. The settling target can be adjusted by ±7 dB from the nominal level of 500 mV peak, differential by means of register settings. Note: When doing measurements with a single-tone RF signal, the amplitude at the Rx outputs after settling the AGC will be lower, at about 300 mV peak, differential.

Philips Semiconductors Product data SA2400ASingle chip transceiver for 2.45 GHz ISM band

2002 Nov 04 7

6.7 AGC Handshake

On the digital input pin AGCRESET, a 0-to-1 transition clears AGCSET output to logic 0 and starts the AGC cycle. At the end of the AGC settling, the AGCSET output is asserted to logic 1. The AGCRESET input can then be reset to logic 0. At any time in the RECEIVE mode the AGC can be forced to the maximum gain by giving the AGCRESET signal as described, but by additionally re-setting it to logic 0 within 1 µs. The AGCSET indication is not given in this case and the receiver settling time is 3 µs. The channel filters will be set to have a lower cut-off of 1 MHz. For a timing diagram, please see the receiver parameters section.

6.8 RSSI

The Receive Signal Strength Indicator (RSSI) is implemented as an error signal comparing the signal level at the Rx output to the nominal value of 500 mV peak,differential. It has a –10 dBc to +10 dBc operational range relative to the nominal signal level. Since the RSSI acts on the modulated RF signal envelope that is extracted from the baseband I and Q signals, it includes DC offsets, and will therefore show transient decaying errors when the AC coupling lower cut-off frequency is changed. The RSSI signal reflects on a logarithmic scale the amplitude of the instantaneous modulated RF signal (envelope). The RSSI signal is filtered by a low-pass filter with 0.5 MHz upper cut-off frequency. The SA2400A receiver is designed to give at least –10 dBc RSSI at maximum gain, when there is no signal present, i.e., with only thermal noise. However, due to process spreads (e.g., gain, noise figure, IQ low-pass filter bandwidth, etc.), the RSSI may show higher than –10 dBc. In case a calibration is required for setting this noise power to –10 dBc, the AGC’s maximum gain (GMAX) can be changed in the range of 85 to 54 dB in steps of 1 dB via register settings. The programmed value of maximum gain is never altered by the AGC settling or by forcing the AGC to maximum gain. Only the RXMGC mode can set the AGC gain to values higher than GMAX. The RXMGC mode does not change the value of GMAX.

6.9 Receiver blocking immunity

The receiver is designed to exceed the IEEE802.11 specifications for the blocking and intermodulation. It can accept continuous or randomly pulsed interfering single- or multi-tone signals that are more than 35 dB stronger than the wanted signal, and up to –10 dBm of interference level. The spurious I and Q outputs are maintained to smaller than –20 dBc of the wanted signal level.

6.10 Transmitter and IQ upconverter

The transmitter inputs are designed to be driven from a Baseband IC in one of two modes: a) in analog mode, differential I and Q inputs expect current signals driven by DACs in the Baseband IC; or b) in digital mode, single-ended inputs expect two binary data streams. In this case, integrated FIR–DACS provide additional filtering. The data streams are sampled with the reference clock. For timing specifications, please see the transmitter parameters section. The wide band IQ upconverter includes spectral shaping reconstruction filters (4 th order low-pass Butterworth with 9.75 MHz 3 dB upper cut-off frequency). At +8 dBm maximum transmitter output level the out-of-band (FCC forbidden band) spurious signal power is less than –77 dBc (integrated over 1 MHz with a 100 kHz resolution bandwidth) for the 11 Msymbols/sec CCK modulation (footnote 1). This implies that the spectral regrowth is dominated by any external PA that may be used to boost the transmission power level. In analog mode, it is assumed that the input baseband IQ signals as delivered from the Baseband IC are pulse shaped. By using the on-chip calibration loop, the transmitter Carrier Leakage can be reduced to levels far less than required by the standard. An RF power meter detects the LO level, converts it into a digital signal and a state machine determines the compensation values which are fed through a DAC directly to the IQ inputs. This mode is activated by setting the IC into the DCALIB mode by means of 3-wire bus programming. This calibration is designed to compensate for any DC offsets delivered by the ADCs on the Baseband IC. The DCALIB cannot be used when the IC is using the digital-input Tx mode. The IQ gain and phase imbalance, reconstruction filter roll-off and in-channel noise produce a modulation EVM of less than 12% for 11 Msymbols/sec QPSK. The transmitter has two switched outputs, one with –1.5 dBm output power and the other one with +8 dBm output power. The input pin TX_HI is used to select between the two RF output ports. The 8 dBm output port is differential and is designed to work seamlessly (no external filtering required) with the SA2411 power amplifier. Upon entering the Tx mode, the ramping up of the RF Tx signal is delayed by an internal power ramping circuit. The ramping up time is fixed, while the delay prior to ramping up can be programmed by register settings. Note: When switching out of the Transmit mode (either into Receive mode by transition on TXRX pin, or into another mode by 3-wire programming), the reference clock input (pins XTAL_1 and XTAL_2) needs to be active since a digital timer is being used.

6.11 Reference current and voltage outputs

The IC provides a temperature-constant reference current of 1 mA or 300 µA (selectable), active in Tx mode, as well as a 2.5 V reference voltage. 1. For a CCK signal, the peak signal power is 21.7 dB lower than the total power integrated over the 22 MHz band. The SA2400A guarantees better than 56 dBc suppression of the second sidelobe (greater than 22 MHz frequency offset). Consequently, the power level in the forbidden bands is at least 77 dBc below the transmitted integrated power.

2002 Nov 04 8

Table 3. Absolute Maximum Ratings Table 4. Recommended Operating Conditions

1. When the digital input mode is used, the lower limit of the ambient operating temperature is higher than –30 °C. Preliminary characterization

results suggest a limit of –20 °C. This does not apply if the analog input mode is used.

1. OPERATIONAL MODES AND CURRENT CONSUMPTION

Table 5. Operational modes and current consumption Transmitter ON with 8 dBm driver. Transmitter ON with –1.5 dBm driver. TXRX = LOW Synthesizer ON. Receiver ON.

• TX/RX ⇒ internal AGC
• RXMGC ⇒ 3-wire bus programming
• FASTTXRXMGC ⇒ fast 3-wire bus n/a 81 95 105 WAIT WAIT Only Synthesizer and Xtal oscillator ONn/a 27 31 34 FCALIB FCALIB Calibrates cut-off frequency of Tx and Rx filters internally. Automatic transition to SLEEP mode upon completion. 3 µs – n/a – DCALIB DCALIB Maintain TX mode for 5 µs before calibration. Quiescent IQ input. Analog mode used. Calibration to reduce transmitter carrier leakage. Automatic transition to SLEEP mode upon completion. 20 µs – n/a – VCOCALIB VCOCALIB Calibrates internal VCO. 2200 µs – n/a – RESET RESET Resets IC into power-up state (SLEEP mode and all registers at default values) n/a – n/a – NOTE: 1. All digital inputs connected to GND or VDD .

Philips Semiconductors Product data SA2400ASingle chip transceiver for 2.45 GHz ISM band

2002 Nov 04 9

8.1 RESET

Shuts down all blocks except the 3-wire digital section, and programs internal registers to known default values that are described in section 13. This ensures that the SA2400A transmitter, receiver, synthesizer and other blocks enter a known state when made active. The SA2400A enters the SLEEP state automatically after the RESET state. Before entering either the TXRX or RXMGC active states, the internal registers can be reprogrammed to change their values from the default values. A power-up of the digital supply also forces the SA2400A to the RESET mode.

8.2 SLEEP

All blocks (except the xtal osc) are OFF. The xtal osc can be separately shut down. Note that the 3-wire bus will remain operational in all modes as long as the digital supply is ON. The SA2400A retains programmed values of all active modes when it comes out of the sleep mode. This includes the synthesizer operation. Programmed via 3-wire bus.

8.3 WAIT

The PLL is on. Receiver and the transmitter are both OFF. This mode is useful for a quick turn-around to either TXRX or RXMGC modes. Transition to or from this mode is done via the 3-wire bus.

8.4 RXMGC

Only the PLL and Receiver are operating. The AGC gain is manually set by the value of a register field.

8.5 TXRX

In this mode the logic level on the TX/RX input pin determines the operational mode: 1 = TRANSMIT, 0 = RECEIVE. This way, no 3-wire bus programming is necessary to switch between Tx and Tx, resulting in faster switching. When entering the RECEIVE mode (either via 3-wire programming to TXRX mode with TX/RX pin at logic zero, or by a 1-to-0 transition of TX/RX pin when already in the TXRX mode), the Receiver is set to maximum gain. An AGC cycle is initiated by a 0-to-1 change on the AGC_RESET digital input pin. At any time in the RECEIVE mode, the AGC can be forced to the maximum gain setting by giving a 1 µs pulse on the AGC_RESET input while the TX/RX input is held at logic 0.

8.6 FASTTXRXMGC

It is similar to the RXMGC mode, except that the manual AGC gain programming can be done faster, as described in Section 14.5.

8.7 FCALIB

This mode needs to be programmed after power ON in order to internally calibrate the cut-off frequency of the on-chip transmit and receive active filters. Upon completion of the calibration, the IC will automatically switch to Main Mode = SLEEP. This calibration takes a maximum of 3 µs measured from the end of the programming sequence. The result of this calibration can be read out from register word 0x04.

8.8 DCALIB

If the analog Tx inputs are used, this mode needs to be programmed at least once after power ON in order to reduce the transmitter carrier leakage. This mode should be programmed after being in TX mode for at least 5 µs. Upon completion of the calibration, the IC will automatically switch to Main Mode = SLEEP. This calibration takes a maximum of 20 µs measured from the end of the programming sequence. The result of this calibration can be read out from register 0x07.

8.9 VCOCALIB

This mode needs to be programmed at least once after power ON in order to calibrate the internal VCO. Upon completion of the calibration, the IC will automatically switch to Main Mode = SLEEP. This calibration takes a maximum of 2.2 ms from the end of the programming sequence. After this calibration, the synthesizer must be re-programmed by writing the register words 0x00 through 0x03. The result of this calibration can be read out from register 0x08.

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Receiver channel center frequency, as the IF output is at 0 Hz. Table 6. SA2400A Receiver properties S11 (RF input) Incl balun+matching. 50 Ω unbalanced. Note 3. a) TX to RX mode transition. (measured after 5 µs TX–RX settling time). used. AGC delay registers (0x05) at default values. With constant RF input during this time. Note 3. frequency error within 25 ppm of final value. Note 3. Less than the piece-wise linear interpolation. Note 3. jammer at 25 MHz offset. Note 3.

Philips Semiconductors Product data SA2400ASingle chip transceiver for 2.45 GHz ISM band

2002 Nov 04 11

Specification UnitsMaxTyp MinConditions LO leakage to antenna All gain modes. Incl balun – –75 –57 dBm Residual sideband Rejection Measured with single tone at 2 MHz offset from carrier. Includes both IQ gain and phase error. Notes 3, 7. 22 29 – dB Ripple band width of filter Note 4. 5.6 6.3 7.0 MHz 3 dB band width of filter Indicative, not tested. Note 4. – 7 – MHz In-band amplitude ripple DC to ripple band width edge. Note 3. – – 0.6 dB peak Out-of-band attenuation Relative to minimum in-band gain > 11 MHz 25 – – dB > 22 MHz 55 – – dB Lower 3 dB cut-off frequency of AC li Cascade of two 1st order high-pass filters. coupling a) NARROW BAND – 10 – kHz b) INTERMEDIATE BAND – 100 – kHz c) WIDE BAND – 1000 – kHz Output load resistance Pin to GND, differential. Note 5. 15 – – kΩ Output load capacitance Pin to GND – – 6 pF Nominal I & Q output voltage Differential at the load specified. Note 6. – 0.5 – V peak Maximum I & Q output voltage Saturated, differential – – 1.5 V peak Common mode IQ voltage Programmable (see 0x04) Mode 1 VCC /2–0.25 VCC /2 VCC /2+0.25 V Mode 2 1.0 1.25 1.5 V 1 dB compression level at output1 MHz tone, differential. Maximum gain. 1 – – V peak Total Harmonic Distortion (measured at max and min gains) Input 1 – 5 MHz signal, 1 V peak differential sinusoidal at output, output spurs measured differential up to 100 MHz. Ratio of rms total spurious distortion to rms fundamental. Receiver in minimum gain. Note 3. – 2 4 % Receiver in maximum gain. Note 3. – 5 10 % Phase Imbalance Signal tone input at 2 MHz offset from carrier. Indicative, not tested. – 4 – deg I, /I to Q, /Q amplitude imbalanceratio of signal at I pin to /I pin; Same for Q and /Q pins. – 0.1 – dB RSSI voltage in settled state (internal AGC) Corresponds to I, Q output signal levels when AGC_RESET is used, with RF input between –10 and –80 dBm. 1 MHz tone, 0.5 V peak differential. ACGTARGET = 0 1.25 1.55 1.95 V RSSI voltage difference 1 dB change in input power compared to settled state – 64.5 – mV RSSI minimum voltage Signal power = –10 dBc – 0.9 – V RSSI maximum output voltage Signal power = +10 dBc – 2.2 – V RSSI error –10 dBc < signal power < +10 dBc – ±1 – dB NOTES: 1. Corresponds to –15 dBm input level at IC input, assuming typical 5 dB loss from the antenna to the IC input. The AGCTARGET register should be set to “+5” which causes the AGC to settle to an output amplitude greater than the specified nominal value. A resistive divider network at the output can be used to adjust the actual IQ output levels to the BB ADC range. 2. Guaranteed by design. 3. Verified by bench characterization and found to have sufficient margin for production. 4. At power-up time, the filter bandwidth is undefined. It needs to be calibrated with the internal tuner (FCALIB mode). 5. For unsymmetrical loading, attach the same load impedance to the unused pin; condition: for 80% of nominal output voltage swing. 6. Nominal I/Q output levels are understood as the levels the SA2400A will settle to after an AGCRESET action is performed with an RF input signal modulated by a Barker sequence, and with AGCTARGET = 0. 7. RSB = 20*log(sqrt([1+K 2 + 2Kcosϕ]/[1+K2 – 2Kcosϕ])), where K = linear gain imbalance, and ϕ = phase imbalance.

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9.1 AGC handshake and timing

Figure 3. AGC handshake and timing. Table 7. AGC timing

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3%. The LO frequency is the same as the Transmitter channel center frequency, as the transmit IF input is at 0 Hz. Table 8. SA2400A Transmitter properties change of TX/RX pin). Note 2. Carrier Leakage Analog input mode selected. No signal input, only quiescent current. RX to TX switching time Note 2. signal. Measured at upconverted transmitter output. Note 2. relative to in-band 1 MHz tone. Note 2. IQ input signal current rangeInto each arm of differential inputs that sink current to ground. Analog input selected. Note 4. IQ input quiescent currentInto each arm of differential inputs that sink current to ground. Resulting I/Q bias voltageWith 300 µA quiescent current into each arm of differential inputs.

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1. The 44 MHz common mode digital ground bounce on the I and Q inputs is assumed to be less than –30 dBc relative to signal level.
2. Verified by bench characterization and found to have sufficient margin for production.
3. The power ramping-up delay can be programmed to 2, 3, 4, 5 µs. See the 3-wire bus control register map. The default is 2 µs.
4. The differential input signal current is the difference between the I and /I (Q and /Q) instantaneous currents. The peak differential current is

therefore (Imax –Imin)/2 = 500 µA. 44 MHz or 22 MHz is supported. Table 9. Synthesizer and VCO Specifications

1. This is measured at the Output1 RF port with the SA2400A in transmit mode, with static DC offset signals to the transmitter I and Q inputs.

band around the carrier is less than –30 dBc.

1. The relative output current variation is defined as:/C0068IZOUT

Philips Semiconductors Product data SA2400ASingle chip transceiver for 2.45 GHz ISM band

2002 Nov 04 15

Figure 4. 12. FUNCTIONAL DESCRIPTION

12.1 Main Fractional-N divider

The divider consists of a fully programmable bipolar prescaler followed by a CMOS counter. Total divide ratios range from 512 to 65535. At the completion of a main divider cycle, a main divider output pulse is generated which will drive the main phase comparator. Also, the fractional accumulator is incremented by the value of NF. The accumulator works with modulo Q set by FM (Synthesizer Register A). When the accumulator overflows, the overall division ratio N will be increased by 1 to N + 1, the average division ratio over Q main divider cycles (either 5 or 8) will be Nfrac/C0043N /C0041NF Q The output of the main divider will be modulated with a fractional phase ripple. The phase ripple is proportional to the contents of the fractional accumulator and is nulled by the fractional compensation charge pump. The reloading of a new main divider ratio is synchronized to the state of the main divider to avoid introducing a phase disturbance.

12.2 Reference divider

The reference divider consists of a divider with programmable values between 4 and 1023 followed by a 3-bit binary counter. The 3-bit SM register (see Figure 5) determines which of the five output pulses are selected as the main phase detector input. SR02354 DIVIDE BY R /2 /2 /2 /2REFERENCE INPUT SM=“000” SM=“001” SM=“010” SM=“011” SM=“100” TO MAIN PHASE DETECTORFigure 5. Reference Divider

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12.3 Phase detector (see Figure 6)

(τ) at every cycle (backlash time) providing improved linearity. Figure 6. Phase Detector Structure with Timing

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12.4 Main output charge pumps and fractional

word and stays active until a different word is sent.

12.5 Principle of fractional compensation

IPUMP_TOTAL = IPUMP + ICOMP . FRD is the fractional accumulator value.

12.6 Lock Detect

synthesizer is powered down.

12.7 Power-down mode

avoid possibility of random phase errors on power-up. NOTE: For a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output. Figure 7. Waveforms for NF = 2 Modulo 5 → fraction = 2/5 Figure 8. Current Injection Concept

2002 Nov 04 18

1. SA2400A OTHER FUNCTIONALITY

Table 10 specifies functionality not described elsewhere in this document. Table 10. SA2400A Other Functionality

1. 3-WIRE BUS/LOGIC CONTROL

• The pin SEN is an “enable” signal. It is level sensitive: If SEN is of LOW value, the 3-wire bus interface on the SA2400A is enabled. This means that each rising edge on the SCLK pin (see below) will be taken as a shift cycle, and address/data bits are expected on SDATA (see below). If SEN is HIGH, the 3-wire bus interface is disabled. No register settings will change regardless of activity on SCLK and SDATA.
• The pin SCLK is the “shift clock” input. If the 3-wire bus is enabled, address or data bits will be clocked in from the SDATA pin with rising edges of SCLK. In output mode, SDATA bits are set on the falling edge of SCLK in order to be sampled on the rising edge by the controller.
• The pin SDATA is the bi-directional “data” pin. It is internally configured as “input” or “output” depending on the operation (WRITE or READ). Each operation consists of 32 bits. Out of these, the first 7 bits form an address word, followed by a READ/WRITE indicator bit. The following 24 bits are the data word corresponding to the chosen address. The 3-wire bus interface contains an internal counter (state machine) which determines beginning and end of address and data word, the “write” pulse to the internal registers, and the direction of the bi-directional SDATA pin. Consequently, with the 32 nd rising SCLK edge of a WRITE cycle, the current data word is stored in the internal register of the programmed address. Following SCLK edges will be taken as the beginning of the following cycle. No programming on SEN is needed to separate cycles. If the SEN signal is switched to HIGH (i.e., DISABLE) at any time, the current cycle will be disregarded. Any bits that have been shifted in so far via SDATA will be disregarded. The internal counter is reset to zero.

14.1 Description of WRITE cycle

1. (start) SEN is LOW or is changed to LOW, i.e., 3-wire interface is
2. (SCLK edge 1 through 7) 7 address bits are clocked in, LSB first.
3. (SCLK edge 8) The READ/WRITE bit is clocked in with the rising

edge of SCLK. ‘1’ = WRITE, ‘0’ = READ.

1. (SCLK edges 9 through 32) 24 data bits are clocked in, LSB first,

Figure 9. WRITE cycle timing diagram of the 3-wire bus

2002 Nov 04 19

14.2 Description of READ cycle

1. (start) SEN is LOW or is changed to LOW, i.e., 3-wire interface is
2. (SCLK edge 1 through 7) 7 address bits are clocked in, LSB first.
3. (SCLK edge 8) The READ/WRITE bit is clocked in with the rising

edge of SCLK. ‘1’ = WRITE, ‘0’ = READ.

1. (SCLK edges 9 through 32) 24 data bits are clocked out, LSB

with the following rising edge). Figure 10. READ cycle timing diagram of the 3-wire bus data remains latched during power-down (sleep mode). Table 11. 3-wire bus/logic control AC characteristics

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14.4.1 Data Format

Table 12. Format of programmed data Table 13. Overview

00 Synthesizer: Main divider settings WRITE ONLY

01 Synthesizer: Reference divider and fractional compensation WRITE ONLY

02 Synthesizer: charge pump current and additional division WRITE ONLY

03 Synthesizer: test modes WRITE ONLY

04 Main operation modes, filter tuner, other controls

05 Rx AGC adjustment settings

06 Manual receiver control settings

07 Transmitter settings

08 VCO settings (only bits 0 through 9)

1. The synthesizer registers (addresses 00 to 03) cannot be read.
2. After programming register 0x01 it is necessary to also program register 0x00 to load the content of FC[7:0] into the internal working register.
3. After programming register 0x00 it is necessary to program some other register (e.g., 0x04) to avoid keeping the charge pump current

setting in php-speedup mode.

1. After running the VCOCALIB mode, it is necessary to re-program registers 0x00 through 0x03.

Table 14. Address 00: Synthesizer Register A Table 15. Address 01: Synthesizer Register B

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Table 16. Address 02: Synthesizer Register C programming new words, it is recommended to keep the speedup mode always disabled by setting the Tphpsu (0x03, bit 16) to ‘1’. NOTE: The only recommended charge pump current setting mode is CP[1:0] = 10, php-speedup not activated. Table 17. Address 03: Synthesizer Register D

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Table 18. Address 04: Main chip operation modes, filter tuner, other controls

• All calibration modes (*CALIB) require the crystal oscillator to be ON (bit XO = 1).
• DCALIB (Tx LO leakage calibration) requires being in Tx mode for 5 µs before calibration. 4 vei Use external vco input (vcoextin) 5 veo Make internal vco available at vco pads (vcoextout) 6 rxlv Rx output common mode voltage: 0–VDD /2, 1–1.25 V 7 digin Use digital Tx inputs (FIRDAC) 8 xo Xtal oscillator ON 9 clk Reference clock output ON 10 in22 Xtal input frequency: 0–44 MHz, 1–22 MHz

11 Not used

19 adc ‘1’: in Rx mode, the RSSI-ADC is always on. ‘0’: the RSSI-ADC is only on during AGC operation. Table 19. Address 05: AGC adjustment settings

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Table 20. Address 06: Manual receiver control settings 0–9 receiver gain Write: In RXMGC mode, this sets the receiver gain. Read: In other modes, the AGC controlled gain is available for readout here. 10–11 corner freq. DC offset cancellation cornerpoint select. Write: In RXMGC mode, this sets the cornerpoint. Read: In other modes, the cornerpoint as controlled by the AGC is available for readout here. {rxosXon,rxosXval} = ‘10001’ → offset = 16 mV etc. 23 ahsn AGC with high Signal-to-Noise (switch LNA at step 52 instead of step 60). Table 21. Address 07: Transmitter settings 8–9 txramp Tx ramp-up delay programming: 00–1 µs, 01–2 µs, 10–3 µs, 11–4 µs. Ramp-up time always 1 µs. Write: with test mode, these bits set the offset. Read: in normal mode, automatically controlled settings can be read out here (sign plus three bits). {txosXon,txosXval} = ‘11000’ → offset = –2.5 µA; {txosXon,txosXval} = ‘10001’ → offset = 5.0 µA etc. Table 22. Address 08: VCO settings Write: with test mode, these bits set the VCO band. Read: in normal mode, the result ot the calibration (VCOCAL) can be read out here (0000 = highest frequencies). 4 vcerr VCO calibration error flag (no band with low enough frequency could be found).

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14.4.2 Programming Example

• Input Xtal is 44 MHz, comparison frequency fcomp = 4 MHz ⇒ reference division ratio R = 11
• Target frequency is 2412 MHz, fcomp = 4 MHz ⇒ main divider ratio N = 603 (no fractional N) – write this word to register 00: 00 0 000 0000001001011011 00 (note two leading zeros – unused bits 22, 23) – write this word to register 01: 00 0000001011 00 1 0 xxxxxxxx (x = no significance) Program synthesizer for 2.462 GHz band
• Input Xtal is 44 MHz, comparison frequency fcomp = 4 MHz ⇒ reference division ratio R = 11
• Target frequency is 2462 MHz, fcomp = 4 MHz ⇒ main divider ratio N = 615.5 (fractional 4/8) – write this word to register 00: 00 0 100 0000001001100111 00 – write this word to register 01: 00 0000001011 00 1 0 01010000 Fractional compensation setting should be set in the application (depends on the loop parameters) with the help of the SA8027 application note. The nominal value is FC = 640 / FM (FM = modulus, see address 00).

14.5 Fast serial interface for Receiver–AGC

interface and the dedicated bus).

14.5.1 Description of “fast programming” cycle

1. Set the chip to FASTTXRXMGC mode by programming

register 4 with the correct value.

1. With each rising edge on pin SCLK, a new data bit is expected at

programming order is LSB first.

1. With the 12th rising edge on SCLK, an internal counter will

register. The bits will immediately effect the receiver settings.

1. The regular 3-wire bus is still accessible and can be

affect receiver gain settings when SEN is LOW. Figure 11. “Fast programming” cycle timing diagram

14.6 Fast serial interface AC characteristics

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Figure 12. TX to RX switching time versus temperature Figure 13. TX to RX switching time versus supply voltage Figure 14. Noise Figure versus input power Figure 15. RX residual sideband suppression versus Figure 16. RX residual sideband suppression versus Figure 17. Spectrum of RX sideband rejection at 4 MHz offset

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Figure 18. TX ramp-up (1 µs/div). Figure 19. Noise Figure vs. input power for two LNA switching modes. Figure 20. Transmitter error vector magnitude (EVM) versus Figure 21. Transmitter error vector magnitude (EVM) versus supply voltage (Tamb = 25 °C). Figure 22. RX to TX switching time versus temperature Figure 23. RX to TX switching time versus supply voltage

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Figure 24. TX constellation and EVM.

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Figure 25. Total sleep ICC . Figure 26. VCO 0011 bandwidth. Figure 27. VCO 0111 f1. Figure 28. Total TX LOW ICC .

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Figure 29. Output power TX LOW, g = 1111. Figure 30. Total TX HIGH ICC . Figure 31. Output power TX HIGH, g = 1111. Figure 32. PLL phase noise @ 500 kHz.

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Figure 33. TX HIGH spectral mask, adjacent channel. Figure 34. TX LOW spectral mask, adjacent channel. Figure 35. Total RX ICC . Figure 36. RXMGC I max gain.

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Figure 37. RXMGC Q max gain. Figure 38. RX filter ripple bandwidth.

Philips Semiconductors Product data SA2400ASingle chip transceiver for 2.45 GHz ISM band

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LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2

Philips Semiconductors Product data SA2400ASingle chip transceiver for 2.45 GHz ISM band

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REVISION HISTORY

_1 20021104 Product data; initial version. Engineering Change Notice 853–2320 28727 (date: 20020809).

Philips Semiconductors Product data SA2400ASingle chip transceiver for 2.45 GHz ISM band

2002 Nov 04 34

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to:  Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 11-02 Document order number: 9397 750 09632 /C0080 /C0115 /C0111/C0110/C0111 /C0115 Data sheet status[1] Objective data Preliminary data Product data Product status[2] [3] Development Qualification Production Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Level I II III