S9KEA64P64M20SF0_V01 NXP | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Key features
- 1.1 Operating characteristics
- 1.2 Performance
- 1.3 Memories and memory interfaces
- 1.4 Clocks
- 1.5 System peripherals
- 1.6 Security and integrity modules
- 1.7 Human-machine interface
- 1.8 Analog modules
- 1.9 Timers
- 1.10 Communication interfaces
- 1.11 Package options
- 2 Ordering parts
- 2.1 Determining valid orderable parts
- 3 Part identification
- 3.1 Description
- 3.2 Format
- 3.3 Fields
- 3.4 Example
- 4 Ratings
- 4.1 Thermal handling ratings
- 4.2 Moisture handling ratings
- 4.3 ESD handling ratings
- 4.4 Voltage and current operating ratings
- 5 General
- 5.1 Nonswitching electrical specifications
- 5.1.1 DC characteristics
- 5.1.2 Supply current characteristics
- 5.1.3 EMC performance
- 5.2 Switching specifications
- 5.2.1 Control timing
- 5.2.2 FTM module timing
- 5.3 Thermal specifications
- 5.3.1 Thermal characteristics
- 6 Peripheral operating requirements and
- 6.1 Core modules
- 6.1.1 SWD electricals
- 6.2 External oscillator (OSC) and ICS
- 6.3 NVM specifications
- 6.4 Analog
- 6.4.1 ADC characteristics
- 6.4.2 Analog comparator (ACMP) electricals
- 6.5 Communication interfaces
- 6.5.1 SPI switching specifications
- 7 Dimensions
- 7.1 Obtaining package dimensions
- 8 Pinout
- 8.1 Signal multiplexing and pin assignments
- 9 Revision History
- 10 Legal information
KEA64 Sub-Family Data Sheet Supports the following: S9KEAZN16AMLC(R), S9KEAZN32AMLC(R), S9KEAZN64AMLC(R), S9KEAZN16AMLH(R), S9KEAZN32AMLH(R), and S9KEAZN64AMLH(R) Rev. 7 — 30 January 2024 Data sheet
1 Key features
1.1 Operating characteristics
- Voltage range: 2.7 to 5.5 V
- Flash write voltage range: 2.7 to 5.5 V
- Temperature range (ambient): -40 to 125°C
1.2 Performance
- Up to 40 MHz Arm® Cortex-M0+ core and up to 20 MHz bus clock
- Single cycle 32-bit x 32-bit multiplier
- Single cycle I/O access port
1.3 Memories and memory interfaces
- Up to 64 KB flash
- Up to 256 B EEPROM
- Up to 4 KB RAM
1.4 Clocks
- Oscillator (OSC) - supports 32.768 kHz crystal or 4 MHz to 20 MHz crystal or ceramic resonator; choice of low power or high gain oscillators
- Internal clock source (ICS) - internal FLL with internal or external reference, 31.25 kHz pre-trimmed internal reference for 40 MHz system and core clock.
- Internal 1 kHz low-power oscillator (LPO)
1.5 System peripherals
- Power management module (PMC) with three power modes: Run, Wait, Stop
- Low-voltage detection (LVD) with reset or interrupt, selectable trip points
- Watchdog with independent clock source (WDOG)
- Programmable cyclic redundancy check module (CRC)
- Serial wire debug interface (SWD)
- Bit manipulation engine (BME)
1.6 Security and integrity modules
- 64-bit unique identification (ID) number per chip
NXP Semiconductors S9KEA64P64M20SF0 KEA64 Sub-Family Data Sheet Supports the following: S9KEAZN16AMLC(R), S9KEAZN32AMLC(R), S9KEAZN64AMLC(R), S9KEAZN16AMLH(R), S9KEAZN32AMLH(R), and S9KEAZN64AMLH(R)
1.7 Human-machine interface
- Up to 57 general-purpose input/output (GPIO)
- Two up to 8-bit keyboard interrupt modules (KBI)
- External interrupt (IRQ)
1.8 Analog modules
- One up to 16-channel 12-bit SAR ADC, operation in Stop mode, optional hardware trigger (ADC)
- Two analog comparators containing a 6-bit DAC and programmable reference input (ACMP)
1.9 Timers
- One 6-channel FlexTimer/PWM (FTM)
- Two 2-channel FlexTimer/PWM (FTM)
- One 2-channel periodic interrupt timer (PIT)
- One real-time clock (RTC)
1.10 Communication interfaces
- Two SPI modules (SPI)
- Up to three UART modules (UART)
- One I2C module (I2C)
1.11 Package options
- 64-pin LQFP
- 32-pin LQFP
2 Ordering parts
2.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: KEAZN64 .
3 Part identification
3.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.
3.2 Format
Part numbers for this device have the following format: Q B KEA A C FFF M T PP N S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Data sheet Rev. 7 — 30 January 2024
NXP Semiconductors S9KEA64P64M20SF0 KEA64 Sub-Family Data Sheet Supports the following: S9KEAZN16AMLC(R), S9KEAZN32AMLC(R), S9KEAZN64AMLC(R), S9KEAZN16AMLH(R), S9KEAZN32AMLH(R), and S9KEAZN64AMLH(R)
3.3 Fields
This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • S = Automotive qualified
- P = Prequalification B Memory type • 9 = Flash KEA Kinetis Auto family • KEA A Key attribute • Z = M0+ core
- F = M4 W/ DSP & FPU
- C= M4 W/ AP + FPU C CAN availability • N = CAN not available
- (Blank) = CAN available FFF Program flash memory size • 16 = 16 KB
- 32 = 32 KB
- 64 = 64 KB M Maskset identifier • A = TSMC10 Mask Rev2
- W0 = TSMC11 Mask Rev0
- B = TSMC10 Mask Rev2 or TSMC11 Mask Rev0 T Temperature range (°C) • C = –40 to 85
- V= –40 to 105
- M = –40 to 125
- LH = 64 LQFP (10 mm x 10 mm) N Packaging type • R = Tape and reel
- (Blank) = Trays
3.4 Example
This is an example part number: S9KEAZN64AMLH
4 Ratings
4.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C [1] TSDR Solder temperature, lead-free — 260 °C [2] [1] Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. [2] Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Data sheet Rev. 7 — 30 January 2024
4.2 Moisture handling ratings
[1] Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
4.3 ESD handling ratings
[1] Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). Thresholds of Microelectronic Components.
- Test was performed at 125 °C case temperature (Class II).
- I/O pins pass +100/-100 mA I-test with IDD current limit at 800 mA (VDD collapsed during positive injection).
- I/O pins pass +70/-100 mA I-test with IDD current limit at 1000 mA for VDD.
- Supply groups pass 1.5 Vccmax.
- RESET_B pin was only tested with negative I-test due to product conditioning requirement.
4.4 Voltage and current operating ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. to the device. For functional operating conditions, refer to the remaining tables in this document. Table 1. Voltage and current operating ratings [1] Maximum rating of VDD also applies to VIN. S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
5 General
5.1 Nonswitching electrical specifications
5.1.1 DC characteristics
This section includes information about power supply requirements and I/O pin characteristics.
5 V — — –100IOHT Output high
5 V — — 100IOLT Output low
Table 2. DC characteristics S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
Table 2. DC characteristics...continued [1] Typical values are measured at 25 °C. Characterized, not tested. [2] Limit applies to both maximum absolute maximum ramp rate and typical operating conditions. [3] Only PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0, and PTH1 support high current output. [4] The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured externally on the pin. and negative clamp voltages, then use the larger value. injection current (VIn > VDD) is higher than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. clock is present, or clock rate is very low (which would reduce overall power consumption). Table 3. LVD and POR specification S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
Table 3. LVD and POR specification...continued [1] Maximum is highest voltage that POR is guaranteed. [2] Rising thresholds are falling threshold + hysteresis. Figure 1. Typical VDD-VOH Vs. IOH (standard drive strength) (VDD = 5 V) S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
Figure 8. Typical VOL Vs. IOL (high drive strength) (VDD = 3 V)
5.1.2 Supply current characteristics
This section includes information about power supply current in various operating modes.
1 MHz
Table 4. Supply current characteristics S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
Table 4. Supply current characteristics...continued [1] Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value. [2] RTC adder causes IDD to increase typically by less than 1 µA; RTC clock source is 1 kHz LPO clock. [3] LVD is periodically woken up from Stop by 5% duty cycle. The period is equal to or less than 2 ms.
5.1.3 EMC performance
S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
targeted at optimizing EMC performance.
- AN2321: Designing for Board Level Electromagnetic Compatibility
- AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers
- AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers
- AN2764: Improving the Transient Immunity Performance of Microcontroller-Based Applications
- AN1259: System Design and Layout Techniques for Noise Reduction in MCU-Based Systems
5.2 Switching specifications
5.2.1 Control timing
1 System and core clock fSys DC — 40 MHz
2 Bus frequency (tcyc = 1/fBus) fBus DC — 20 MHz
5 Reset low drive trstdrv 34 × tcyc — — ns
Table 5. Control timing [1] Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated. [2] This is the shortest pulse that is guaranteed to be recognized as a RESET pin request. mode, the synchronizer is bypassed so shorter pulses can be recognized. [4] Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 125 °C. Figure 9. Reset timing S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
Figure 10. KBIPx timing
5.2.2 FTM module timing
Table 6. FTM input timing Figure 11. Timer external clock Figure 12. Timer input capture pulse
5.3 Thermal specifications
5.3.1 Thermal characteristics
difference between pin voltage and VSS or VDD will be very small. S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
Table 7. Thermal attributes temperature, air flow, power dissipation of other components on the board, and board thermal resistance. [2] Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal. [3] Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. [5] Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored. [6] Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization. iteratively for any value of TA. S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 SWD electricals
- Serial wire debug MHz J2 SWD_CLK cycle period 1/J1 — ns J3 SWD_CLK clock pulse width
- Serial wire debug ns J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 3 — ns J11 SWD_CLK high to SWD_DIO data valid — 35 ns J12 SWD_CLK high to SWD_DIO high-Z 5 — ns
Table 8. SWD full voltage range electricals Figure 13. Serial wire clock input timing Figure 14. Serial wire data timing S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
6.2 External oscillator (OSC) and ICS characteristics
2 Load capacitors C1, C2 See Note[2]
3 Feedback
4 MHz — 0 — kΩ
8 MHz — 0 — kΩ
16 MHz
6 Crystal start-up
7 Internal reference start-up time tIRST — 20 50 µs
8 Internal reference clock (IRC) frequency trim
9 Internal
10 DCO output
11 Factory trimmed
12 Deviation
Table 9. OSC and ICS specifications (temperature range = -40 to 125 °C ambient) S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
13 Frequency
14 FLL acquisition time[4],[6] tAcquire — — 2 ms
15 Long term jitter of DCO output clock (averaged
Table 9. OSC and ICS specifications (temperature range = -40 to 125 °C ambient)...continued [1] Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value. [2] See crystal or resonator manufacturer's recommendation. [3] Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO = 0. [4] This parameter is characterized and not tested on each device. [5] Proper PC board layout procedures must be followed to achieve specifications. crystal oscillator frequency increase the CJitter percentage for a given interval. Figure 15. Typical crystal or resonator circuit
6.3 NVM specifications
Table 10. Flash and EEPROM characteristics S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
Table 10. Flash and EEPROM characteristics...continued Program and erase operations do not require any special power sources other than the normal VDD supply.
6.4 Analog
6.4.1 ADC characteristics
Table 11. 5 V 12-bit ADC operating conditions S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
- fADCK > 4 MHz
- fADCK < 4 MHz 10-bit mode
- fADCK > 4 MHz
- fADCK < 4 MHz Analog source resistance 8-bit mode (all valid fADCK) RAS — — 10 kΩ External to MCU High speed (ADLPC=0) 0.4 — 8.0ADC conversion clock frequency Low power (ADLPC=1) fADCK 0.4 — 4.0 MHz —
Table 11. 5 V 12-bit ADC operating conditions...continued Figure 16. ADC input impedance equivalency diagram Table 12. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
Table 12. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)...continued S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
6.4.2 Analog comparator (ACMP) electricals
Table 13. Comparator electrical specifications
6.5 Communication interfaces
6.5.1 SPI switching specifications
high-drive strength is enabled for SPI output pins. Table 14. SPI master mode timing S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
Table 15. SPI slave mode timing...continued Figure 19. SPI slave mode timing (CPHA = 0) S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
Figure 20. SPI slave mode timing (CPHA=1)
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
8 Pinout
8.1 Signal multiplexing and pin assignments
For the pin muxing details see section Signal Multiplexing and Signal Descriptions of KEA64 Reference Manual.
9 Revision History
The following table provides a revision history for this document. 'Description' and 'Values' in 'Field' M. S9KEA64P64M20SF0 v. 6 21 October 2019 • Added row Tramp in Table 2. number of instances of IIC to 1. S9KEA64P64M20SF0 v. 3 18 July 2014 • Section 4.3 section is updated. Table 16. Revision History S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
- Figures in Section 5.1.1 section are updated.
- Specs updated in following tables: – Table 9. – Table 4. S9KEA64P64M20SF0 v. 2 18 June 2014 • Parameter Classification section is removed.
- Classification column is removed from all the tables in the document.
- Section 5.1.2 section is updated. S9KEA64P64M20SF0 v. 1 11 March 2014 Initial Release
Table 16. Revision History...continued S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
NXP Semiconductors S9KEA64P64M20SF0 KEA64 Sub-Family Data Sheet Supports the following: S9KEAZN16AMLC(R), S9KEAZN32AMLC(R), S9KEAZN64AMLC(R), S9KEAZN16AMLH(R), S9KEAZN32AMLH(R), and S9KEAZN64AMLH(R)
10 Legal information
10.1 Data sheet status
Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
10.2 Definitions
Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
10.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Data sheet Rev. 7 — 30 January 2024
NXP Semiconductors S9KEA64P64M20SF0 KEA64 Sub-Family Data Sheet Supports the following: S9KEAZN16AMLC(R), S9KEAZN32AMLC(R), S9KEAZN64AMLC(R), S9KEAZN16AMLH(R), S9KEAZN32AMLH(R), and S9KEAZN64AMLH(R) Suitability for use in automotive applications — This NXP product has been qualified for use in automotive applications. If this product is used by customer in the development of, or for incorporation into, products or services (a) used in safety critical applications or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (such products and services hereinafter referred to as “Critical Applications”), then customer makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, customer assumes all risk related to use of any products in Critical Applications and NXP and its suppliers shall not be liable for any such use by customer. Accordingly, customer will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys’ fees) that NXP may incur related to customer’s incorporation of any product in a Critical Application. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document, including the legal information in that document, is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. NXP B.V. — NXP B.V. is not an operating company and it does not distribute or sell products.
10.4 Trademarks
Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK- PLUS, ULINKpro, μVision, Versatile — are trademarks and/or registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere. The related technology may be protected by any or all of patents, copyrights, designs and trade secrets. All rights reserved. S9KEA64P64M20SF0 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Data sheet Rev. 7 — 30 January 2024