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Technical content

Supports the following: S9KEAZ64AMLK(R), S9KEAZ128AMLK(R), S9KEAZ64AVLK(R), S9KEAZ128AVLK(R), S9KEAZ64ACLK(R), S9KEAZ128ACLK(R), S9KEAZ64AMLH(R), S9KEAZ128AMLH(R), S9KEAZ64AVLH(R), S9KEAZ128AVLH(R), S9KEAZ64ACLH(R) and S9KEAZ128ACLH(R) Key features

  • Operating characteristics – Voltage range: 2.7 to 5.5 V – Flash write voltage range: 2.7 to 5.5 V – Temperature range (ambient): -40 to 125°C
  • Performance – Up to 48 MHz ARM® Cortex-M0+ core – Single cycle 32-bit x 32-bit multiplier – Single cycle I/O access port
  • Memories and memory interfaces – Up to 128 KB flash – Up to 16 KB RAM
  • Clocks – Oscillator (OSC) - supports 32.768 kHz crystal or 4 MHz to 24 MHz crystal or ceramic resonator; choice of low power or high gain oscillators – Internal clock source (ICS) - internal FLL with internal or external reference, 37.5 kHz pre-trimmed internal reference for 48 MHz system clock – Internal 1 kHz low-power oscillator (LPO)
  • System peripherals – Power management module (PMC) with three power modes: Run, Wait, Stop – Low-voltage detection (LVD) with reset or interrupt, selectable trip points – Watchdog with independent clock source (WDOG) – Programmable cyclic redundancy check module (CRC) – Serial wire debug interface (SWD) – Aliased SRAM bitband region (BIT-BAND) – Bit manipulation engine (BME)
  • Security and integrity modules – 80-bit unique identification (ID) number per chip
  • Human-machine interface – Up to 71 general-purpose input/output (GPIO) – Two 32-bit keyboard interrupt modules (KBI) – External interrupt (IRQ)
  • Analog modules – One up to 16-channel 12-bit SAR ADC, operation in Stop mode, optional hardware trigger (ADC) – Two analog comparators containing a 6-bit DAC and programmable reference input (ACMP) Freescale Semiconductor Document Number S9KEA128P80M48SF0 Data Sheet: Technical Data Rev 4, 09/2014 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2014 Freescale Semiconductor, Inc.
  • Timers – One 6-channel FlexTimer/PWM (FTM) – Two 2-channel FlexTimer/PWM (FTM) – One 2-channel periodic interrupt timer (PIT) – One pulse width timer (PWT) – One real-time clock (RTC)
  • Communication interfaces – Two SPI modules (SPI) – Up to three UART modules (UART) – Two I2C modules (I2C) – One MSCAN module (MSCAN)
  • Package options – 80-pin LQFP – 64-pin LQFP KEA128 Sub-Family Data Sheet, Rev4, 09/2014. 2 Freescale Semiconductor, Inc.

KEA128 Sub-Family Data Sheet, Rev4, 09/2014. Freescale Semiconductor, Inc. 3

1.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: KEAZ128. Part identification

2.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.

2.2 Format

Part numbers for this device have the following format: Q B KEA A C FFF M T PP N

2.3 Fields

This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • S = Automotive qualified

  • P = Prequalification B Memory type • 9 = Flash KEA Kinetis Auto family • KEA A Key attribute • Z = M0+ core
  • F = M4 W/ DSP & FPU
  • C= M4 W/ AP + FPU C CAN availability • N = CAN not available
  • (Blank) = CAN available Table continues on the next page... Ordering parts KEA128 Sub-Family Data Sheet, Rev4, 09/2014. 4 Freescale Semiconductor, Inc.

FFF Program flash memory size • 128 = 128 KB M Maskset revision • A = 1 st Fab version

  • B = Revision after 1 st version T Temperature range (°C) • C = –40 to 85
  • V= –40 to 105
  • M = –40 to 125
  • LK = 80 LQFP (14 mm x 14 mm) N Packaging type • R = Tape and reel
  • (Blank) = Trays

2.4 Example

This is an example part number: S9KEAZ128AMLK Ratings

3.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

3.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. Ratings KEA128 Sub-Family Data Sheet, Rev4, 09/2014. Freescale Semiconductor, Inc. 5

3.3 ESD handling ratings

  1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
  2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

  1. Determined according to JEDEC Standard JESD78D, IC Latch-up Test. The test produced the following results:
  • Test was performed at 125 °C case temperature (Class II).
  • I/O pins pass +100/-100 mA I-test with I DD current limit at 400 mA (VDD collapsed during positive injection).
  • I/O pins pass +50/-100 mA I-test with I DD current limit at 1000 mA for VDD.
  • Supply groups pass 1.5 V ccmax.
  • RESET_B pin was only tested with negative I-test due to product conditioning requirement.

3.4 Voltage and current operating ratings

operating conditions, refer to the remaining tables in this document. associated with the pin is enabled. Table 1. Voltage and current operating ratings

  1. Maximum rating of VDD also applies to VIN.

KEA128 Sub-Family Data Sheet, Rev4, 09/2014. 6 Freescale Semiconductor, Inc.

4.1.1 DC characteristics

Table 2. DC characteristics

3 V — — –60

3 V — — 60

Table continues on the next page... KEA128 Sub-Family Data Sheet, Rev4, 09/2014.

Table 2. DC characteristics (continued)

  1. Typical values are measured at 25 °C. Characterized, not tested.
  2. Only PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0, and PTH1 support high current output.
  3. The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured
  4. All functional non-supply pins, except for PTA2 and PTA3, are internally clamped to VSS and VDD. PTA2 and PTA3 are true

open drain I/O pins that are internally clamped to VSS.

  1. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,

calculate resistance values for positive and negative clamp voltages, then use the larger value.

  1. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current

is very low (which would reduce overall power consumption). Table 3. LVD and POR specification Table continues on the next page... KEA128 Sub-Family Data Sheet, Rev4, 09/2014. 8 Freescale Semiconductor, Inc.

Table 3. LVD and POR specification (continued)

  1. Maximum is highest voltage that POR is guaranteed.
  2. Rising thresholds are falling threshold + hysteresis.
  3. voltage Factory trimmed at VDD = 5.0 V, Temp = 125 °C

Figure 1. Typical VDD-VOH Vs. IOH (standard drive strength) (VDD = 5 V) KEA128 Sub-Family Data Sheet, Rev4, 09/2014.

Figure 8. Typical VOL Vs. IOL (high drive strength) (VDD = 3 V)

4.1.2 Supply current characteristics

This section includes information about power supply current in various operating modes. Table 4. Supply current characteristics Table continues on the next page... KEA128 Sub-Family Data Sheet, Rev4, 09/2014.

Table 4. Supply current characteristics (continued) Table continues on the next page... KEA128 Sub-Family Data Sheet, Rev4, 09/2014. 14 Freescale Semiconductor, Inc.

  1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
  2. The high current is observed at high temperature.
  3. RTC adder cause <1 µA IDD increase typically, RTC clock source is 1 kHz LPO clock.
  4. LVD is periodically woken up from Stop by 5% duty cycle. The period is equal to or less than 2 ms.

4.1.3 EMC performance

guidance specifically targeted at optimizing EMC performance.

  • AN2321: Designing for Board Level Electromagnetic Compatibility
  • AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers
  • AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers
  • AN2764: Improving the Transient Immunity Performance of Microcontroller-Based

Applications

  • AN1259: System Design and Layout Techniques for Noise Reduction in MCU- Based Systems Switching specifications

4.2.1 Control timing

Table 5. Control timing

1 System and core clock fSys DC — 48 MHz

2 Bus frequency (tcyc = 1/fBus) fBus DC — 24 MHz

Table continues on the next page... KEA128 Sub-Family Data Sheet, Rev4, 09/2014.

Table 5. Control timing (continued)

5 Reset low drive trstdrv 34 × tcyc — — ns

6 IRQ pulse width Asynchronous path2 tILIH 100 — — ns

7 Keyboard interrupt pulse

8 Port rise and fall time -

  1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
  2. This is the shortest pulse that is guaranteed to be recognized as a RESET pin request.
  3. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.

  1. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 125 °C.

Figure 9. Reset timing Figure 10. KBIPx timing

4.2.2 FTM module timing

synchronizers operate from the current bus rate clock. Table 6. FTM input timing Table continues on the next page... KEA128 Sub-Family Data Sheet, Rev4, 09/2014. 16 Freescale Semiconductor, Inc.

Table 6. FTM input timing (continued) Figure 11. Timer external clock Figure 12. Timer input capture pulse

4.3.1 Thermal characteristics

KEA128 Sub-Family Data Sheet, Rev4, 09/2014.

Table 7. Thermal attributes

  1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
  2. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
  3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
  4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

  1. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.
  2. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization. KEA128 Sub-Family Data Sheet, Rev4, 09/2014. 18 Freescale Semiconductor, Inc.

be obtained by solving the above equations iteratively for any value of TA.

5 Peripheral operating requirements and behaviors

5.1 Core modules

5.1.1 SWD electricals

Table 8. SWD full voltage range electricals

  • Serial wire debug MHz J2 SWD_CLK cycle period 1/J1 — ns J3 SWD_CLK clock pulse width
  • Serial wire debug ns J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 3 — ns J11 SWD_CLK high to SWD_DIO data valid — 35 ns J12 SWD_CLK high to SWD_DIO high-Z 5 — ns J3 J3 J4 J4 SWD_CLK (input)

Figure 13. Serial wire clock input timing KEA128 Sub-Family Data Sheet, Rev4, 09/2014.

Figure 14. Serial wire data timing

5.2 External oscillator (OSC) and ICS characteristics

Table 9. OSC and ICS specifications (temperature range = -40 to 125 °C ambient)

1 Crystal or

2 Load capacitors C1, C2 See Note2

3 Feedback

4 Series resistor -

5 Series resistor -

4 MHz — 0 — kΩ

8 MHz — 0 — kΩ

Table continues on the next page... KEA128 Sub-Family Data Sheet, Rev4, 09/2014. 20 Freescale Semiconductor, Inc.

Table 9. OSC and ICS specifications (temperature range = -40 to 125 °C ambient) (continued)

16 MHz — 0 — kΩ

6 Crystal start-up

7 Internal reference start-up time tIRST — 20 50 µs

8 Internal reference clock (IRC) frequency trim

9 Internal

10 DCO output

11 Factory trimmed

12 Deviation of IRC

13 Frequency

14 FLL acquisition time4,6 tAcquire — — 2 ms

15 Long term jitter of DCO output clock (averaged

  1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
  2. See crystal or resonator manufacturer's recommendation.
  3. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO =
  4. This parameter is characterized and not tested on each device.
  5. Proper PC board layout procedures must be followed to achieve specifications.
  6. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, or

the reference, this specification assumes it is already running.

  1. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.

KEA128 Sub-Family Data Sheet, Rev4, 09/2014.

Figure 15. Typical crystal or resonator circuit

5.3 NVM specifications

Table 10. Flash characteristics Table continues on the next page... KEA128 Sub-Family Data Sheet, Rev4, 09/2014. 22 Freescale Semiconductor, Inc.

Table 10. Flash characteristics (continued)

  1. Minimum times are based on maximum fNVMOP and maximum fNVMBUS
  2. Typical times are based on typical fNVMOP and maximum fNVMBUS
  3. Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging

the Flash Memory Module section in the reference manual.

5.4 Analog

5.4.1 ADC characteristics

Table 11. 5 V 12-bit ADC operating conditions

  • Low
  • High VREFL VREFH VSSA VDDA/2 VDDA/2 VDDA V — Supply voltage Absolute VDDA 2.7 — 5.5 V — Delta to VDD (VDD-VDDA) ΔVDDA -100 0 +100 mV — Input voltage VADIN VREFL — VREFH V — Input capacitance CADIN — 4.5 5.5 pF — Input resistance RADIN — 3 5 kΩ — Analog source resistance 12-bit mode
  • f ADCK > 4 MHz
  • f ADCK < 4 MHz RAS — kΩ External to MCU 10-bit mode
  • f ADCK > 4 MHz
  • f ADCK < 4 MHz 8-bit mode (all valid fADCK) — — 10 ADC conversion clock frequency High speed (ADLPC=0) fADCK 0.4 — 8.0 MHz — Low power (ADLPC=1) 0.4 — 4.0 Peripheral operating requirements and behaviors KEA128 Sub-Family Data Sheet, Rev4, 09/2014. Freescale Semiconductor, Inc. 23
  1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production. Figure 16. ADC input impedance equivalency diagram Table 12. 12-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) Table continues on the next page... KEA128 Sub-Family Data Sheet, Rev4, 09/2014. 24 Freescale Semiconductor, Inc.

Table 12. 12-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

  1. Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

  1. 1 LSB = (VREFH - VREFL)/2N
  2. IIn = leakage current (refer to DC characteristics)

KEA128 Sub-Family Data Sheet, Rev4, 09/2014.

5.4.2 Analog comparator (ACMP) electricals

Table 13. Comparator electrical specifications

5.5 Communication interfaces

5.5.1 SPI switching specifications

rate control is disabled and high-drive strength is enabled for SPI output pins. Table 14. SPI master mode timing Table continues on the next page... KEA128 Sub-Family Data Sheet, Rev4, 09/2014. 26 Freescale Semiconductor, Inc.

Table 15. SPI slave mode timing Figure 19. SPI slave mode timing (CPHA = 0) KEA128 Sub-Family Data Sheet, Rev4, 09/2014. 28 Freescale Semiconductor, Inc.

Figure 20. SPI slave mode timing (CPHA=1)

5.5.2 MSCAN

Table 16. MSCAN wake-up pulse characteristics

6.1 Obtaining package dimensions

Package dimensions are provided in package drawings. KEA128 Sub-Family Data Sheet, Rev4, 09/2014.

7.1 Signal multiplexing and pin assignments

8 Revision History

The following table provides a revision history for this document. Table 17. Revision History

  • Classification column is removed from all the tables in the document.
  • New section added - Supply current characteristics. Rev. 3 18 July 2014 • Added supported part numbers.
  • ESD handling ratings section is updated.
  • Figures in DC characteristics section are updated.
  • Specs updated in following tables:
  • Table 9. Rev. 4 03 Sept 2014 • Data Sheet type changed to "Technical Data". Pinout KEA128 Sub-Family Data Sheet, Rev4, 09/2014. 30 Freescale Semiconductor, Inc.

How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer's technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale, the Freescale logo, and Kinetis are trademarks of Freescale service names are the property of their respective owners. ARM and Cortex-M0+ are the registered trademarks of ARM Limited. ©2014 Freescale Semiconductor, Inc. Document Number S9KEA128P80M48SF0 Revision 4, 09/2014