MC9S12ZVMB_V01 NXP | Alldatasheet
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nxp.com MC9S12ZVMB-Family Reference Manual Rev. 1.3
07 MAR 2017
MC9S12ZVMB Family Reference Manual Rev. 1.3
2 NXP Semiconductors
The MC9S12ZVMB-Family is targeted for safety relevant systems and has been developed using an ISO26262 compliant development system under the NXP Safe Assure program. For details of device usage in safety relevant systems refer to the MC9S12ZVMB Safety Manual. The document revision on the Internet is the most current. To verify this is the latest revision, refer to: nxp.com This document contains information for all modules except the CPU. For CPU information please refer to the CPU S12Z Reference Manual. The following revision history table summarizes changes to this document. The individual module sections contain revision history tables with more detailed information.. Table 0-1. Revision History Date Revision Description 26 Nov 2015 1.1 Updated family member comparison table Corrected Figure 1-10 Updated ordering information in Appendix K 24 Mar 2016 1.2 Added Grade0 row to device summary Table 1-2 Corrected number of external ADC channels Section 1.4.11 Specified unused VSUPHS must be connected to VSUP or VDDX Section 1.7.3.6 Adjusted VREG temperature sensor electrical parameter valuesTable B-1 Changed ADC maximum frequency from 8.34MHz to 8MHz Table C-1 Adjusted HVI input resistance in PIM chapter Figure 2-42 Corrected pin name from VRH0 to VRH_0 Figure 1-4 Minor formating and error corrections (see PIM, GDU, SRAM_ECC revision histories) Corrected write access limitations for GDU registers Added bootstrap switch diode to GDU Figure 18-17 Added GDU current sense unity bandwidth and input resistance to Table E-1 Changed RESET pin input pulse passed parameter minimum value Table A-11 Added bootstrap diode resistance parameter Table E-1 16 Sep 2016 1.3 DRAFT A Added to applications list in device overview Added temperature sensor application information Section 1.13.1 Renamed CPMU alternate temperature sensor to DVBE temperature sensor Enhanced power dissipation info Table A-7, Figure A-2 Updated PT2 leakage values Table A-10 Updated current consumption values Table A-16, Table A-17 Updated DVBE temperature sensor values Table B-1 Updated VBG temperature dependence value, Table B-1 Added desaturation thresholds to GDU electrical specification Table E-1 Updated VLS current limit threshold Table E-1 Added parameter GHD division ratio through phase mux.Table E-1 07 Mar 2017 1.3 Clarified VDDX range for test and characterization Table A-10, Table C-1 Updated ISUPS values at 105C Table A-17 Updated V DVBE parameter value Table B-1 Updated temperature sensor application information Section 1.13.1 Updated GDU tdelon, tdeloff parameter values Table E-1 Added Rbsdon and IVBS parameter values Table E-1 Updated gate drive footnote Table E-1 Updated current injection considerations C.1.1.4/C-692, Table A-12
MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 3 Chapter 1 Device Overview MC9S12ZVMB-Family
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Port Integration Module (S12ZVMBPIMV3)
MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 5 Chapter 3 Memory Mapping Control (S12ZMMCV1) Chapter 4 Interrupt (S12ZINTV0)
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Background Debug Controller (S12ZBDCV2) Chapter 6 S12Z DebugLite (S12ZDBGV3) Module
MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 7 Chapter 7 ECC Generation Module (SRAM_ECCV3) Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11)
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Analog-to-Digital Converter
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9.9.6 RVL swapping in RVL double buffer mode and related registers ADCIMDRI and
Supply Voltage Sensor - (BATSV3) Chapter 11 Timer Module (TIM16B4CV3) Block Description
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Pulse Width Modulator with Fault Protection (PMF15B6CV4) Chapter 13 Programmable Trigger Unit (PTUV3)
MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 11 Chapter 14 Serial Communication Interface (S12SCIV6)
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Serial Peripheral Interface (S12SPIV5) 15.2.3 SS Chapter 16 High-Side Driver Module - HSDRV2C (HSDRV2CV3)
MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 13 Chapter 17 LIN Physical Layer (S12LINPHYV2) Chapter 18 Gate Drive Unit (GDU2PHV2)
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Flash Module (S12ZFTMRZ)
MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 15 Appendix A Appendix B Appendix C Appendix D Appendix E Appendix F Appendix G Appendix H
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Package Information
Ordering Information
Detailed Register Address Map
MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductor 17 Chapter 1 Device Overview MC9S12ZVMB-Family Table 1-1. Revision History
1.1 Introduction
The S12 MagniV product line is a highly optimized, automotive family of devices which integrate, beside the typical digital peripherals, additional analog battery level (12 V) components. The MC9S12ZVMB-Family is a new member of the S12 MagniV product line based on the enhanced performance, linear address space S12Z core and delivers an optimized solution with the integration of several key system components into a single device, optimizing system architecture and achieving significant space savings. The particular differentiating features of this family are the enhanced S12Z core, the combination of an ADC synchronized to PWM signals using a Programmable Trigger Unit (PTU) and the integration of “high-voltage” analog modules, including the voltage regulator (VREG), Gate Drive Unit (GDU) and a Local Interconnect Network (LIN) physical layer. These features enable a fully integrated single chip solution to drive external power MOSFETs for motor drive applications. The MC9S12ZVMB-Family includes error correction code (ECC) on RAM and flash memory, EEPROM for diagnostic or data storage, a fast analog-to-digital converter (ADC) and a frequency modulated phase locked loop (PLL) that improves the EMC performance. The MC9S12ZVMB-Family delivers all the advantages and efficiencies of a 16-bit MCU while retaining the low cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of existing S12 families. In addition to the peripheral module I/O ports, further I/O ports are available with interrupt capability allowing wake-up from stop or wait modes. The MC9S12ZVMB-Family is a general-purpose family of devices suitable for a range of applications, including:
- Brush DC motors that need driving in 2 directions, along with PWM control for — Window lift — Trunk opener — Sun roof Version Number Revision Date Sections Affected Description of Changes 0.4 11.Jun.2015 General Initial version for S12ZVMB64 product 0.5 16.Jul.2015 General Removed async_event connections Added GDU to TIM1 IC2 connection Changed pin order to improve VLS bond out 0.6 17.Jul.2016 Section 1.1 Added applications
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— Sliding doors — Seat positioning
1.2 Features
This section describes the key features of the MC9S12ZVMB-Family.
1.2.1 MC9S12ZVMB-Family member comparison
Table 1-2 provides a summary of feature set differences within the MC9S12ZVMB-Family. All other features are common to all family members. Table 1-2. MC9S12ZVMB-Family devices Feature S12ZVMBA S12ZVMB Flash memory 64 KB 48 KB 64 KB 48 KB 64 KB 48 KB 64 KB 48 KB Grade 0 qualification (Ta up to 150 C) Yes No Yes No EEPROM 512 Byte RAM 4 KB Physical Layer LIN High Voltage Inputs 3 High Side Drivers 2 FET pre-driver (GDU) 2 HS + 2 LS Max. PWM frequency 20 kHz
2 HS + 2 LS
Max. PWM frequency 1 kHz Integrated Current Sense Op-Amp 1 VREG ballast transistor support yes SCI 2 (1) 1. One SCI internally mapped to LIN physical layer SPI 1 16-Bit Timer channels 4+4 15-bit PMF channels(2) 2. Four PWM channels internally mapped to GDU, 2 PWM channels for GPIO/HS ADC channels mapped to pins 5 9 5 9 EVDD (20 mA source) 1 NGPIO (25 mA sink) 1 General purpose I/O 15 24 15 24
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1.2.2 ADC module versions
This device family features ADC V3. The ADC module description includes a superset of features for V1, V2 and V3. It also summarizes these minor version differences.
1.2.3 S12ZVMBA versions
The FET-Predriver on the S12ZVMB version cannot be driven directly from the PMF PWM channels at a frequency of greater than 1KHz. Otherwise the S12ZVMB device is identical to the S12ZVMBA device.
1.3 Chip-Level features
On-chip modules available within the family include the following features:
- S12Z CPU core
- 64 KB or 48 KB on-chip flash with ECC
- 512 Byte EEPROM with ECC
- 4 KB on-chip SRAM with ECC
- Phase locked loop (IPLL) frequenc y multiplier with internal filter
- 1 MHz internal RC oscillator with +/-1.3% accuracy over junction temperature range up to 150C
- 4-20 MHz amplitude contro lled pierce oscillator
- Internal COP (watchdog) module
- 6-channel, 15-bit pulse width modul ator with fault protection (PMF)
- Low-side and High-side FET pre-drivers for each phase — Gate drive pre-regulator (11 V LDO) — High-side gate supply generated using bootstra p circuit with internal diode and external capacitor — Sustaining charge pump with tw o external capacitors and diodes — High-side drain (GHD) monitoring on in ternal ADC channel using GHD/5 voltage
- Analog-to-digital converter (ADC) with 10-bit resolution and up to 9 channels available on external pins
- One serial peripheral interface (SPI) module
- One serial communication interf ace (SCI) module with interface to internal LIN physical layer transceiver (with RX connected to a timer channel for frequency calibration purposes, if desired)
- One additional SCI (not connected to LIN physical layer)
- On-chip LIN physical layer transceiver full y compliant with the LIN 2.2 and SAE J2602-2 standards
- Two 4-channel timer modules (TIM) with input capture/output compare
- One programmable trigger unit (PTU ) for ADC trigger synchronization
- On-chip voltage regulator (VREG) for regula tion of input supply and all internal voltages
- One current sense circuit for over-curr ent detection or torque measurement
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- Autonomous periodic interrupt (API)
- Two High-side Driver outputs
- Three High V oltage Input (HVI) pins
- One 20mA high-current output for use as Hall sensor supply
- Supply voltage sensor wi th low battery warning
- One high current (25 mA sink) NGPIO
- Chip temperature sensor
1.4 Module features
The following sections provide more details of the integrated modules.
1.4.1 S12Z central processor unit (CPU)
The S12Z CPU is a revolutionary high-speed core, with code size and execution efficiencies over the S12X CPU. The S12Z CPU also provides a linear memory map eliminating the inconvenience and performance impact of page swapping.
- Harvard Architecture - para llel data and code access
- 3 stage pipeline
- 32-Bit wide instruction and databus
- 32-Bit arithmetic logic unit (ALU)
- 24-bit addressing, of 16 MByte linear address space
- Instruction and addressing modes opti mized for C-programming & compilation — Multiply and accumulate (MAC) unit 32bit += 32bit*32bit — Hardware divider — Single cycle multi-bit shifts (Barrel shifter) — Special instructions for fixed point math
- Unimplemented opcode traps
- Unprogrammed byte value (0xFF) defaults to SWI instruction
1.4.1.1 Background de bug controller (BDC)
- Background debug controller (BDC ) with single-wire interface — Non-intrusive memory access commands — Supports in-circuit programmi ng of on-chip nonvolatile memory
1.4.1.2 Debugger (DBG)
- Three comparators (A, B and D) — Comparator A compares the full address bus and full 32-bit data bus — Comparators B and D compar e the full address bus only
Chapter 1 Device Overview MC9S12ZVMB-Family MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 21 — Each comparator can be configured to monito r PC addresses or addresses of data accesses — Each comparator can select eith er read or write access cycles — Comparator matches can force st ate sequencer state transitions
- Three comparator modes — Simple address/data comparator match mode — Inside address range match — Outside address range match
- State sequencer control — State transitions forced by comparator matches — State transitions forced by software write to TRIG — State transitions forced by an external event
- The following types of breakpoints — CPU breakpoint entering acti ve BDM on breakpoint (BDM) — CPU breakpoint executing SWI on breakpoint (SWI)
1.4.2 Embedded memory
1.4.2.1 Memory access integrity
- Illegal address detection
- ECC support on embedded NVM and SRAM
1.4.2.2 Flash
On-chip flash memory features the following:
- Up to 64KB of program flash memory — 32 data bits plus 7 syndrome EC C (error correction code) bits allow single bit fault correction and double bit fault detection — Erase sector size of 512 bytes — Automated program and erase algorithm — User margin level setting for reads — Protection scheme to prevent accidental program or erase
1.4.2.3 EEPROM
- Up to 512 Bytes EEPROM — 16 data bits plus 6 syndrome ECC bits — Single bit error correction, double bit error detection — Erase sector size 4 bytes, pr ogram with word resolution — Automated program and erase algorithm — User margin level setting for reads
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1.4.2.4 SRAM
- Up to 4 Kbytes of gene ral-purpose RAM with ECC — Single bit error correction and double bit error detection
1.4.3 Clocks, reset & powe r management unit (CPMU)
- Real time interrupt (RTI)
- Clock monitor, supervising the corr ect function of the oscillator (CM)
- Computer operating properly (COP) watchdog — Configurable as window COP for enhanced failure detection — Can be initialized out of reset usi ng option bits located in flash memory
- System reset generation
- Autonomous periodic interrupt (API ) (combination with cyclic, watchdog) — Trimmable RC oscillator timebase th at can remain active in STOP mode
- Low Power Operation — RUN mode - main full performance opera ting mode with the entire device clocked — WAIT mode - the internal CPU clock is switched off, so the CPU does not execute instructions — Pseudo STOP - system clocks are stopped but th e oscillator, RTI, COP, and API modules can be enabled — STOP - the oscillator is stopped in this mode, all clocks are switched off and all counters and dividers remain frozen, with the exception of the COP and API which can optionally run from ACLK
1.4.3.1 Internal pha se-locked loop (IPLL)
- Phase-locked-loop clock frequency multiplier — No external components required — Reference divider and multiplier al low large variety of clock rates — Automatic bandwidth control mode for low-jitter operation — Automatic frequency lock detector — Configurable option to spread spectrum for reduced EMC radiation (frequency modulation) — Reference clock sources: – Internal 1 MHz RC oscillator (IRC) – External 4-20 MHz crys tal oscillator/resonator
1.4.3.2 Internal RC oscillator (IRC)
- Trimmable internal 1 MHz reference clock. — Trimmed accuracy for te mperature options V , M: 1.3%max. — Trimmed accuracy for temperature option W: 1.45%max
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1.4.4 External oscillator (XOSCLCP)
- Amplitude controlled Pierce oscill ator using 4 MHz to 20 MHz crystal — Current gain control on amplitude output — Signal with low harmonic distortion — Low power — Good noise immunity — Eliminates need for extern al current limiting resistor — Trans conductance sized for optimum start-up margin for typical crystals — Oscillator pins shared with GPIO functionality 1.4.5 4 channel timer (TIM)
- 4 x 16-bit channels Timer module fo r input capture or output compare
- 16-bit free-running counter wi th 8-bit precision prescaler
1.4.6 Pulse width modulator wi th fault protection (PMF)
- 6 x 15-bit channel PWM resolution
- Each pair of channels can be combined to ge nerate a PWM signal (with independent control of edges of PWM signal)
- Dead time insertion available for each complementary pair
- Center-aligned or edge-aligned outputs
- Programmable clock select logic wi th a wide range of frequencies
- Programmable fault detection
1.4.7 Programmable trigger unit (PTU)
- Synchronizes ADC triggers based on PMF signal edges
- One 16 bit counter as time base for all trigger events
- One trigger generator(TG0) Up to 32 trigger events per trigger generator
- Global Load OK support, to guarantee c oherent update of all control loop modules
- Trigger values stored in system memory
- Software generated reload event a nd trigger event generation for debugging
1.4.8 LIN physical layer transceiver
- Compliant with LIN physical layer 2.2 specification
- Compliant with the SAE J2602-2 LIN standard
- Standby mode with glitch-filtered wake-up
- Slew rate selection optim ized for the baud rates:
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— 10.4 kBit/s — 20 kBit/s — Fast Mode (up to 250 kBit/s)
- Selectable pull-up of 34 k or 330 k (in Shutdown Mode, 330 k only)
- Current limitation for LI N Bus pin falling edge.
- Over-current protection.
- LIN TxD-dominant timeout featur e monitoring the LPTxD signal.
- Automatic transmitter shutdow n in case of an over-current or TxD-dominant timeout.
- Fulfills the OEM “Hardware Requi rements for LIN (CAN and FlexRay) Interfaces in Automotive Applications” v1.3.
1.4.9 Serial communication interface module (SCI)
- Full-duplex or single-wire operation
- Standard mark/space non-return-to-zero (NRZ) format
- Selectable IrDA 1.4 return-to- zero-inverted (RZI) format with programmable pulse widths
- 16-bit baud rate selection
- Programmable character length
- Programmable polarity for transmitter and receiver
- Active edge receive wakeup
- Break detect and transmit collision detect supporting LIN
1.4.10 Serial peripheral interface module (SPI)
- Configurable 8- or 16-bit data size
- Full-duplex or single-wire bidirectional
- Double-buffered transmit and receive
- Master or slave mode
- MSB-first or LS B-first shifting
- Serial clock phase and polarity options
1.4.11 Analog-to-digital converter module (ADC)
- Selectable 10-bit or 8-bit resolution
- Up to 12 external channe ls & 8 internal channels
- 2.2us for single 10-bit resolution conversion
- Left or right aligned result data
- Continuous conversion mode
- Programmers model with list based co mmand and result storage architecture
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- ADC directly writes resu lts to RAM, preventing stall of further conversions
- Internal signals monitored by the ADC module — VRH, VRL, (VRL+VRH)/2 — Vsup monitor — VREG Vbg, and Temperature Sensor — Delta VBE Temperature Sensor — GDU phase, GDU DC-link — High V oltage Inputs (PL[2:0])
- External pins can also be us ed as digital I/O with keyboard wake-up interrupt capability
1.4.12 Supply voltage sensor (BATS)
- Monitoring of supply (VSUP) voltage
- Internal ADC interface from an internal resistive divider
- Optional generation of low or high voltage interrupts
1.4.13 On-chip voltage regulator system (VREG)
- V oltage regulator — Linear voltage regulator directly supplied by VSUP — Low-voltage detect on VSUP — Power-on reset (POR) — Low-voltage reset (L VR) for VDDX domain — Over-temperature interrupt
- Internal voltage regulator — Linear voltage regulator with bandgap reference — Low-voltage detect on VDDA — Power-on reset (POR) circuit — Low-voltage reset for VDD domain
1.4.14 Gate drive unit (GDU)
- Low-side and High-side FET pre-driv ers for 2 phases of 2 half bridges
- Gate drive pre-regulator LDO (L ow Dropout V oltage Regulator)
- High-side gate supply done via bootstrap circuit with internal diode and external capacitor
- Sustaining charge pump with two external capacitors and diodes
- FET-Predriver short circui t (desaturation) detection
- Over and under voltage detection and shutdown
- Over current monitor with optional shutdown
- Monitoring of FET High-side drain (GHD) voltage
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- Diagnostic failure management
- Integrated OP-amp functionality
1.4.15 High side driver
- Selectable gate control: HSDR[HSDRx] re gister bits or PWM or timer channels
- Open-load detection
- Slew rate control
- Over-current shutdown, comprising of: — Interrupt flag generation — Driver shutdown — Optional masking window
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1.5 Block diagram
Figure 1-1. MC9S12ZVMB-Family block diagram RESET EXTAL XTAL BKGD VSUP Real Time Interrupt Clock Monitor Background TEST Debug Controller Interrupt Module PAD[8:0]/KWAD[8:0] S12ZCPU COP Watchdog PLL with Frequency Modulation option Debug Module Reset Generation and Test Entry Auton. Periodic Int. MOSI0 SS0 SCK0 MISO0SPI0 5V Voltage (Nominal input 12V) Block Diagram shows the maximum configuration Not all pins or all peripherals are available on all devices and packages. Rerouting options are not shown. PE0 PE1 PTAD IRC BATS Voltage Supply Monitor BDC DBG VDDX VSSX VSS High Voltage Input HVI[2:0]KWL[2:0]/PL[2:0] VSUP SCI1 RXD1 TXD1 PMF PWM[5:4] CPMU ADC AN[8:0] VRH_[2:0] VRL_0 VDDA VSSA LP Pierce Oscillator 10-bit Analog-Digital Converter 15-bit 6 channel Pulse Width Modulator PP[1:0]/KWP[1:0] PTP Asynchronous Serial IF Synchronous Serial IF Flash with ECC
48 K or 64 K bytes
4 K bytes
Clock Power Management Unit Internal RC Oscillator XOSCLCP PTEPTL LIN LINPHY LIN LGND LGND RXD0 TXD0LPTXD LPRXD TIM0 IOC0[3:0]16-bit 4-channel Timer PT[7:0] PTT GDU Gate Drive Unit GHD CP VCP VLS_OUT VBS[1:0] GHG[1:0] GHS[1:0] VLS GLG[1:0] GLS[1:0] GHD CP VCP VLS_OUT VBS[1:0] GHG[1:0] GHS[1:0] VLS GLG[1:0] GLS[1:0] High Side Driver HSDRV VSUPHS HS0 HS1 GDU-AMP Current Sense Circuit AMPP0 AMPM0 AMP0 PWM[3:0] PTU PTURE Programmable Trigger Unit PTUT0 TIM1 IOC1[3:0]16-bit 4-channel Timer SCI0 RXD0 TXD0Asynchronous Serial IF BCTL Regulator PWM[3:0] IC1_[3,2,0]
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1.6 Device memory map
Table 1-3 shows the device register memory map. All modules that can be instantiated more than once on S12 devices are listed with an index number, even if they are only instantiated once on this device family. Table 1-3. Module register address ranges Address Module Size (Bytes) 0x0000–0x0003 Part ID Register Section 1.6.1 4 0x0004–0x000F Reserved 12 0x0010–0x001F INT 16 0x0020–0x006F Reserved 80 0x0070–0x008F MMC 32 0x0090–0x00FF MMC Reserved 112 0x0100–0x017F DBG 128 0x0180–0x01FF Reserved 128 0x0200–0x037F PIM 384 0x0380–0x039F FTMRZ 32 0x03A0–0x03BF Reserved 32 0x03C0–0x03CF SRAM ECC 16 0x03D0–0x03FF Reserved 48 0x0400–0x042F TIM1 48 0x0430–0x043F Reserved 16 0x0440–0x04FF Reserved 192 0x0500–0x053F PMF 64 0x0540–0x057F Reserved 64 0x0580–0x059F PTU 32 0x05A0–0x05BF Reserved 32 0x05C0–0x05EF TIM0 48 0x05F0–0x05FF Reserved 16 0x0600–0x063F ADC0 64 0x0640–0x067F Reserved 64 0x0680–0x069F Reserved 32 0x06A0–0x06BF GDU 32 0x06C0–0x06DF CPMU 32 0x06E0–0x06EF Reserved 16 0x06F0–0x06F7 BATS 8 0x06F8–0x06FF Reserved 8 0x0700–0x0707 SCI0 8
Chapter 1 Device Overview MC9S12ZVMB-Family MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 29 NOTE Reserved register space shown above is not allocated to any module. This register space is reserved for future use. Writing to these locations has no effect. Read access to these locations returns zero. 0x0708–0x070F Reserved 8 0x0710–0x0717 SCI1 8 0x0718–0x077F Reserved 104 0x0780–0x0787 SPI0 8 0x0788–0x097F Reserved 504 0x0980–0x0987 LINPHY0 8 0x0988–0x09BF Reserved 56 0x09C0–0x09C7 HSDRV0 8 0x09C8–0x0FFF Reserved 1592 Table 1-4. MC9S12ZVMB-Family memory address ranges Device Address Memory Block Size (Bytes) MC9S12ZVB64 0x00_1000–0x00_1FFF SRAM 4K MC9S12ZVB64 0x10_0000–0x10_01FF EEPROM 512 Bytes MC9S12ZVB64 0xFF_0000–0xFF_FFFF Program Flash 64K MC9S12ZVB48 0x00_1000–0x00_1FFF SRAM 4K MC9S12ZVB48 0x10_0000–0x10_01FF EEPROM 512 Bytes MC9S12ZVB48 0xFF_4000–0xFF_FFFF Program Flash 48K Table 1-3. Module register address ranges Address Module Size (Bytes)
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Figure 1-2. MC9S12ZVMB-Family global memory map. 0x00_1000 0x00_0000 0x10_0000 0x1F_4000 0x80_0000 0xFF_FFFF RAM EEPROM Unmapped Program NVM Register Space
4 KByte
max. 8 KByte max. 2 KByte max. 128 KByte
6 MByte
0x1F_8000 Unmapped address range 0x1F_C000 Reserved (read only) 6 KByte NVM IFR 256 Byte Reserved 512 Byte 0x20_0000
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1.6.1 Part ID assignments
The part ID is located in four 8-bit registers at addresses 0x0000-0x0003. The read-only value is a unique part ID for each revision of the chip. Table 1-5 shows the assigned part ID number and mask set number.
1.7 Signal description and device pinouts
This section describes signals that connect off-chip. It includes pin out diagrams, a table of signal properties, and detailed discussion of signals. Internal inter module signal mapping at device level is described in 1.8 Internal signal mapping.
1.7.1 Pin assignment overview
Table 1-6 provides a summary of which ports are available. NOTE To avoid current drawn from floating inputs, all non-bonded pins should be configured as output or configured as input with a pull up or pull down device enabled
1.7.2 Detailed external signal descriptions
This section describes the properties of signals available at device pins. Signal names associated with modules that can be instantiated more than once are indexed, even if the module is only instantiated once. If a signal already includes a channel number, then the index is inserted before the channel number. Thus TIMx_y corresponds to TIM instance x, channel number y. Table 1-5. Assigned part ID numbers Device Mask Set Number Part ID MC9S12ZVMB64 N17S 0x06160000 Table 1-6. Port availability by package option Port 64 LQFP 48 LQFP Port AD PAD[8:0] PAD[4:0] Port E PE[1:0] PE[1:0] Port L (HVI) PL[2:0] PL[2:0] Port P PP[1:0] PP[1:0] Port T PT[7:0] PT[2:0] sum of ports 24 15
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1.7.2.1 RESET — External reset signal
The RESET signal is an active low bidirectional control signal. It acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset. The RESET pin has an internal pull-up device.
1.7.2.2 TEST — Test pin
This input only pin is reserved for factory test. This pin has an internal pull-down device. NOTE The TEST pin must be tied to ground in all applications.
1.7.2.3 MODC — Mode C signal
The MODC signal is used as an MCU operating mode select during reset. The state of this signal is latched to the MODC bit at the rising edge of RESET. The signal has an internal pull-up device.
1.7.2.4 PAD[8:0] / KWAD[8:0] — Port AD, input pins of ADC
PAD[8:0] are general-purpose input or output signals. The signals can be configured on per signal basis as interrupt inputs with wake-up capability (KWAD[8:0]). These signals can have a pull-up or pull-down device selected and enabled on per signal basis. During and out of reset the pull devices are disabled.
1.7.2.5 PE[1:0] — Port E I/O signals
PE[1:0] are general-purpose input or output signals. The signals can have a pull-up or pull-down device, enabled by on a per pin basis. Out of reset the pull-down devices are enabled.
1.7.2.6 PL[2:0] / KWL[2:0] — Port L input signals
PL[2:0] are the high voltage input signals. These signals can be configured on a per signal basis as interrupt inputs with wake-up capability (KWL[2:0]). These signals can alternatively be used as analog inputs measured by the ADC.
1.7.2.7 PP[1:0] / KWP[1:0] — Port P I/O signals
PP[1:0] are general-purpose input or output signals. The signals can be configured on per signal basis as interrupt inputs with wake-up capability (KWP[1:0]). They can have a pull-up or pull-down device selected and enabled on per signal basis. During and out of reset the pull devices are disabled. The PP0 pin features the EVDD option, for an increased high-side current drive with low voltage drop.
1.7.2.8 PT[7:0] — Port T I/O signals
PT[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected and enabled on per signal basis. During and out of reset the pull devices are disabled. The PT2 pin features the NGPIO option, for an increased Low-side current drive with low voltage drop.
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1.7.2.9 AN0_[11:0] — ADC input signals
These are the analog inputs of the Analog-to-Digital Converter. ADC0 has up to 9 analog input channels connected to PAD[8:0] port pins. The channels AN_[11:9] are connected to HVI[2:0] respectively.
1.7.2.10 VRH_0, VRL_0— ADC reference inputs
VRH_0 and VRL_0 are the reference voltage inputs for the analog-to-digital converter.
1.7.2.11 SPI0 signals
1.7.2.11.1 SS0 signal
This signal is associated with the slave select SS functionality of the serial peripheral interface SPI0.
1.7.2.11.2 SCK0 signal
This signal is associated with the serial clock SCK functionality of the serial peripheral interface SPI0.
1.7.2.11.3 MISO0 signal
This signal is associated with the MISO functionality of the serial peripheral interface SPI0. This signal acts as master input during master mode or as slave output during slave mode.
1.7.2.11.4 MOSI0 signal
This signal is associated with the MOSI functionality of the serial peripheral interface SPI0. This signal acts as master output during master mode or as slave input during slave mode
1.7.2.12 SCI[1:0] signals
1.7.2.12.1 RXD[1:0] signals
These signals are associated with the receive functionality of the serial communication interfaces (SCI[1:0]).
1.7.2.12.2 TXD[1:0] signals
These signals are associated with the transmit functionality of the serial communication interfaces (SCI[1:0]).
1.7.2.13 Timer IOC0_[3:0] signals
The signals IOC0_[3:0] are associated with the input capture or output compare functionality of the timer (TIM0) module.
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1.7.2.14 Timer IOC1_[3:0] signals
The signals IOC1_[3:0] are associated with the input capture or output compare functionality of the timer (TIM1) module.
1.7.2.15 PWM[5:4] signals
The signals PWM[5:4] are associated with the PMF module digital channel outputs.
1.7.2.16 PTU signals
1.7.2.16.1 PTUT0 signal
This is the PTU trigger output signal, routed to a pin for debugging purposes.
1.7.2.16.2 PTURE signal
This signal is the PTU reload enable output signal. This signal is routed to a pin for debugging purposes.
1.7.2.17 Interrupt signals — IRQ and XIRQ
IRQ is a maskable level or falling edge sensitive input. XIRQ is a non-maskable level-sensitive interrupt.
1.7.2.18 Oscillator and clock signals
1.7.2.18.1 Oscillator pi ns — EXTAL and XTAL
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the internal PLLCLK, independent of EXTAL and XTAL. XTAL is the oscillator output.
1.7.2.18.2 ECLK
This signal is associated with the output of the bus clock (ECLK). NOTE This feature is only intended for debug purposes at room temperature. It must not be used for clocking external devices in an application.
1.7.2.19 BDC and debug signals
1.7.2.19.1 BKGD — Backg round debug signal
The BKGD signal is used as a pseudo-open-drain signal for the background debug communication. The BKGD signal has an internal pull-up device.
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1.7.2.19.2 DBGEEV — Ex ternal event input
This signal is the DBG external event input. It is input only. Within the DBG module, it allows an external event to force a state sequencer transition A falling edge at the external event signal constitutes an event. Rising edges have no effect. The maximum frequency of events is half the internal core bus frequency.
1.7.2.20 FAULT5 — External fault input
This is the PMF fault input signal, with configurable polarity, that can be used to disable PMF operation when asserted.
1.7.2.21 LIN Physical layer signals
1.7.2.21.1 LIN0
This pad is connected to the single-wire LIN data bus.
1.7.2.21.2 LP0TXD
This is the LIN physical layer transmitter input signal.
1.7.2.21.3 LP0RXD
This is the LIN physical layer receiver output signal.
1.7.2.21.4 LP0DR1
This is the LIN LP0DR1 register bit, visible at the designated pin for debug purposes.
1.7.2.22 HS[1:0] High-Side driver output signals
Outputs of the two high-side drivers.
1.7.2.23 Gate drive unit (GDU) signals
These are associated with driving the external FETs.
1.7.2.23.1 GHD — FET predri ver high-side drain input
This is the drain connection of the external high-side FETs. The voltage present at this input is scaled down by an internal voltage divider, and can be routed to the internal ADC.
1.7.2.23.2 VBS[1:0] - Bootst rap capacitor connections
These signals are the bootstrap capacitor connections for phases HS[1:0]. The capacitor connected between HS[1:0] and these signals provides the gate voltage and current to drive the external FET.
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1.7.2.23.3 GHG[1:0] - Hi gh-side gate signals
These pins are the gate drives for the high-side power FETs. The drivers provide a high current with low impedance to turn on and off the high-side power FETs.
1.7.2.23.4 GHS[1:0] - High-side source signals
These pins are the source connection for the high-side power FETs and the drain connection for the low- side power FETs. The low voltage end of the bootstrap capacitor is also connected to this pin.
1.7.2.23.5 VLS - Voltage supply for low -side drivers
This pin is the voltage supply pin for the low-side FET pre-drivers. It should be connected to the voltage regulator output pin VLS_OUT.
1.7.2.23.6 GLG[1:0] - Low-side gate signals
These pins are the gate drives for the low-side power FETs. The drivers provide a high current with low impedance to turn on and off the low-side power FETs.
1.7.2.23.7 GLS[1:0] - Low-side source signals
These pins are the low-side source connections for the low-side power FETs. The pins are the power ground pins used to return the gate currents from the low-side power FETs.
1.7.2.23.8 CP - Charge pump output signal
This pin is the switching node of the charge pump circuit. The supply voltage for charge pump driver is the output of the voltage regulator VLS_OUT. The output voltage of this pin switches typically between 0V and 11V . This pin must be left unconnected if not used.
1.7.2.23.9 VCP - Charge pump input for high-side driver supply
This is the charge pump input for the FET high-side gate drive supply circuit. The pin must be left unconnected if not used.
1.7.2.23.10 VLS_OUT - 11V Voltage regulator output
This pin is the output of the GDU integrated voltage regulator. The output voltage is typically 11V . The input voltage to the voltage regulator is the VSUP pin.
1.7.2.23.11 AMPP0 - Current sen se amplifier non-inverting input
This is the current sense amplifier non-inverting input.
1.7.2.23.12 AMPM0 - Current sen se amplifier inverting input
This is the current sense amplifier inverting input.
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1.7.2.23.13 AMP0 - Current sense amplifier output
This is the current sense amplifier output.
1.7.3 Power supply pins
The power and ground pins are described below. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. NOTE All ground pins must be connected together in the application.
1.7.3.1 VDDX1, VSSX[5:1] — Digital I/O power and ground pins
VDDX1 is the voltage regulator output to supply the digital I/O drivers. The VSSX pins are the ground pins for the output drivers and GDU drivers. Bypass requirements on VDDX/VSSX depend on how heavily the MCU pins are loaded.
1.7.3.2 VDDA, VSSA — Po wer supply pins for ADC
These are the power supply and ground pins for the analog-to-digital converter and the voltage regulator.
1.7.3.3 VSS — Core ground pin
The voltage supply of nominally 1.8V is generated by the internal voltage regulator.
1.7.3.4 LGND — LINPHY ground pin
LGND is the ground pin for the LIN physical layer LINPHY .
1.7.3.5 VSUP — Voltage supply pin for voltage regulator
VSUP is the main supply pin typically coming from the car battery/alternator in the 12V supply voltage range. This is the voltage supply input from which the voltage regulator generates the on-chip voltage supplies. It must be protected externally against a reverse battery connection.
1.7.3.6 VSUPHS Voltage supply pin for high-side drivers
VSUPHS is the 12V/18V shared supply voltage pin for the high-side drivers. It must be protected externally against a reverse battery connection. NOTE If not used VSUPHS must be connected either to VSUP or VDDX. It must not be connected to VSSX
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1.7.3.7 EVDD
This is a high current, low voltage drop output intended for supplying external devices in a range of up to 20mA. Configuring the pin direction as output automatically enables the high current capability. It includes an over current protection feature.
1.7.3.8 NGPIO
This is a high current, low voltage drop output intended for increased low side current driving capability in a range of up to 25mA. Configuring the pin direction as output automatically enables the high current capability. It includes an over current protection feature.
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1.7.4 Package and pinouts
The following package options are offered.
- 48LQFP
- 64LQFP The pin outs are shown in the following diagrams. The signal to pin mapping is specified in Table 1-7 Pins specified as N.C. have no physical connection to silicon. Figure 1-3. MC9S12ZVMB-Family 48-pin LQFP pin out MC9S12ZVMB-Family 48LQFP GLS1 GLG1 VLS VSSX4 VBS1 GHG1 GHS1 GHS0 GHG0 VBS0 VSSX3 GLG0 VSUPHS BKGD RESET TEST PAD4 PAD3 PAD2 PAD1 VDDA VSSA PAD0 GLS0 VSUP VLS_OUT CP VSSX1 VCP GHD PL2 PL1 PL0 HS1 VSSX2 HS0 PP0 VDDX1 PT2 VSS PE0 PE1 PP1 PT1 PT0 BCTL LIN0 LGND
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Figure 1-4. MC9S12ZVMB-Family 64-pin LQFP pin out PT4 PT5 PT6 PT7 GLS1 GLG1 VLS VSSX4 VBS1 GHG1 GHS1 GHS0 GHG0 VBS0 VSSX3 GLG0 .BKGD RESET TEST PAD8 PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 VRH_0 VDDA VSSA PAD0 GLS0 VSUP VLS_OUT CP VSSX1 VCP GHD N.C. PL2 PL1 PL0 N.C. HS1 VSSX2 HS0 VSUPHS N.C. N.C. PP0 VDDX1 PT2 VSSX5 VSS PE0 PE1 N.C PP1 PT1 PT0 PT3 BCTL LIN0 LGND MC9S12ZVMB 64-pin LQFP
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1.7.5 Pin and signal mapping overview
Please refer to the PIM chapter for priority and routing information. Table 1-7. Pin summary (Sheet 1 of 3) LQFP Option Function Power Domai n Internal Pull Resistor 64 48 Pin 1st Func. 2nd Func. 3rd Func. 4th Func. 5th Func. 6th Func. CTRL Rese t State 2 2 VLS_OU T 8 7 PL2 HVI2 KWL2 IC1_2 AN0_11 — — — — — 9 8 PL1 HVI1 KWL1 IC1_1 AN0_10 — — — — — 10 9 PL0 HVI0 KWL0 IC1_0 AN0_9 — — — — — 1 2 1 0 H S 1 O C 1 _ 2 P W M 5 ———— V SUPHS —— 1 4 1 2 H S 0 O C 1 _ 1 P W M 4 ———— V SUPHS —— 1 7 1 4 B K G D M O D C ————— V DDX —U p 18 15 RESET —————— V DDX TEST pin Up 1 9 1 6 T E S T —————— — R E S E T D o w n 2 0 — P A D 8 K W A D 8 A N 0 _ 8 ———— V DDA PERADH/ PPSADH Off 2 1 — P A D 7 K W A D 7 A N 0 _ 7 ———— V DDA PERADL/ PPSADL Off 2 2 — P A D 6 K W A D 6 A N 0 _ 6 ———— V DDA PERADL/ PPSADL Off
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2 3 — P A D 5 K W A D 5 A N 0 _ 5 ———— V DDA PERADL/ PPSADL Off 24 17 PAD4 KWAD4 AN0_4 SS0 — — — V DDA PERADL/ PPSADL Off 25 18 PAD3 KWAD3 AN0_3 PTUT0 — — — V DDA PERADL/ PPSADL Off 26 19 PAD2 KWAD2 AN0_2 AMP0 — — — V DDA PERADL/ PPSADL Off 27 20 PAD1 KWAD1 AN0_1 AMPM0 — — — V DDA PERADL/ PPSADL Off 31 23 PAD0 KWAD0 AN0_0 AMPP0 — — — V DDA PERADL/ PPSADL Off DDX PERT/ PPST Off Table 1-7. Pin summary (Sheet 2 of 3) LQFP Option Function Power Domai n Internal Pull Resistor 64 48 Pin 1st Func. 2nd Func. 3rd Func. 4th Func. 5th Func. 6th Func. CTRL Rese t State
Chapter 1 Device Overview MC9S12ZVMB-Family MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 43 4 6 — P T 6 I O C 1 _ 2 ————— V DDX PERT/ PPST Off 4 7 — P T 5 I O C 1 _ 1 ————— V DDX PERT/ PPST Off 4 8 — P T 4 I O C 1 _ 0 ————— V DDX PERT/ PPST Off (weak 5 2 — P T 3 I O C 0 _ 3 ————— V DDX PERT/ PPST Off 53 40 PT0 IOC0_0 MOSI0 RXD0 RXD1 XIRQ — V DDX PERT/ PPST Off 54 41 PT1 IOC0_1 MISO0 PWM2 TXD0 TXD1 LP0DR1 V DDX PERT/ PPST Off 55 42 PP1 KWP1 PWM5 FAULT5 SCK0 — — V DDX PERP/ PPSP Off 57 43 PE1 XTAL TXD1 PWM1 DBGEE V —— V DDX PERE/ PPSE Down 58 44 PE0 EXTAL RXD1 PWM0 — — V DDX PERE/ PPSE Down 61 46 PT2 (NGPIO) IOC0_2 PWM3 LP0RX D FAULT5 ECLK — V DDX PERT/ PPST Off 63 48 PP0 (EVDD) KWP0 PWM4 PTURE IRQ LP0TXD — V DDX PERP/ PPSP Off Table 1-7. Pin summary (Sheet 3 of 3) LQFP Option Function Power Domai n Internal Pull Resistor 64 48 Pin 1st Func. 2nd Func. 3rd Func. 4th Func. 5th Func. 6th Func. CTRL Rese t State
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1.8 Internal signal mapping
This section specifies the mapping of inter-module signals at device level.
1.8.1 ADC connectivity
1.8.1.1 ADC reference voltages
VRH_[2:1] are always mapped to VDDA, VRH_0 is mapped to VDDA in the 48LQFP package option but mapped to a dedicated VRH_0 pin in the 64LQFP package option. The preferred reference is VRH_0. VRL_0 is always mapped to VSSA.
1.8.1.2 ADC internal channels
The ADC0 internal channel mapping is shown in Table 1-8. The PL[2:0] High V oltage Inputs are connected to ADC0 external channels, AN[11:9] respectively.
1.8.1.3 ADC digital input signals
The ADC input Seq_abort is unused and forced to an inactive state at device level The ADC Restart input is connected to ptu_reload. The ADC input LoadOK is connected to the glb_ldok at device level The ADC Trigger input has routing options to the following sources:
- Internal TIM0 OC2
- Internal PTUT0 signal (Default)
- Internal PMF reload event (PWM generator A) Table 1-8. Usage of ADC0 internal channels ADCCMD_1 CH_SEL[5:0] ADC Channel Usage 0 0 1 0 0 0 Internal_0 ADC0 temperature sensor 0 0 1 0 0 1 Internal_1 VREG temper ature sensor or bandgap (V BG)(1) 1. Selectable in CPMU 0 0 1 0 1 0 Internal_2 GDU phase multiplexer voltage 0 0 1 0 1 1 Internal_3 GDU DC link voltage monitor 0 0 1 1 0 0 Internal_4 BATS VSUP sense voltage 0 0 1 1 0 1 Internal_5 Reserved 0 0 1 1 1 0 Internal_6 Reserved 0 0 1 1 1 1 Internal_7 Delta VBE temperature sensor
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1.8.2 GDU timer connectivity
TIM1 IC3 can be mapped to the GDU using PIM (see the PIM specification) in order to measure the tdelon and tdeloff times.
1.8.3 PTU connectivity
PTU reload_is_async is unused and forced to an inactive state at device level.
1.8.4 PMF connectivity
1.8.5 Motor control loop inte rface connectivity overview
Table 1-10 and Figure 1-5 describe motor control loop connectivity that concerns device level inter module operation specific for motor control. Table 1-9. Internal mapping of PMF signals PMF Connection Usage PWM0 GDU HS driver GHG[0] PWM1 GDU LS driver GLG[0] PWM2 GDU HS driver GHG[1] PWM3 GDU LS driver GLG[1] FAULT5 External FAULT5 pin FAULT4 GHD Over voltage (GOVA = 0) or GDU over current (GOCA = 0) FAULT3 VLS under voltage FAULT2 Tied to b0 FAULT1 GDU Desaturation[1] or GDU over current (GOCA = 1) or GHD over voltage (GOVA =1) FAULT0 GDU Desaturation[0] or GDU over current (GOCA = 1) IS2 Tied to 0x1 IS1 GDU Phase Status[1] IS0 GDU Phase Status[0] async_event Tied to 0x0 async_event_edge_sel[1:0] Tied to 0x3(both edges active) Table 1-10. Control loop interface connectivity Device Level Event PMF PTU ADC0 GDU pmf_reload reloada (1) reload ptu_reload ptu_reload Restart reload glb_ldok glb_ldok glb_ldok LoadOK Phase MUX selector
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Figure 1-5. Motor control module interfaces
1.8.6 BDC clock source connectivity
The BDC clock, BDCCLK, is mapped to the IRCCLK generated in the CPMU module. The BDC clock, BDCFCLK is mapped to the device bus clock, generated in the CPMU module. trigger_0 PTUT0 Trigger (MUX Option) 1. PMF events reloadb and reloadc are not connected at device level Table 1-10. Control loop interface connectivity Device Level Event PMF PTU ADC0 GDU PMF ADC0 GDU M pmf_reload dc_bus_voltage sine/ sensor cosine reloada Restart PTU ptu_reload &PTUE TriggerOC2 glb_ldok PTUT0 async_event reload
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1.8.7 LINPHY connectivity
The VLINSUP supply is internally connected to the device VSUP pin.
1.8.8 FTMRZ connectivity
The soc_erase_all_req input to the flash module is driven directly by a BDC erase flash request resulting from the BDC ERASE_FLASH command. The FTMRZ FCLKDIV register is forced to 0x05 by the BDC ERASE_FLASH command. This configures the clock frequency correctly for the initial bus frequency on leaving reset. The bus frequency must not be changed before launching the ERASE_FLASH command.
1.8.9 CPMU connectivity
The API_EXTCLK clock generated in the CPMU is not mapped to a device pin in the MC9S12ZVMB- Family. The VDDF supply voltage is not mapped to device pins.
1.9 Modes of operation
The MCU can operate in different configuration modes, as described in 1.9.1 Chip configuration modes. The MCU can operate in different power modes to facilitate power saving when full system performance is not required. These are described in 1.9.3 Low power modes. The MCU features a Background Debug Mode (BDM), as described in 1.9.2 Debugging modes.
1.9.1 Chip configuration modes
The different modes and the security state of the MCU affect the debug features (enabled or disabled). The operating mode out of reset is determined by the state of the MODC signal during reset (Table 1-11). The MODC bit in the MODE register shows the current operating mode and provides limited mode switching during operation. The state of the MODC signal is latched into this bit on the rising edge of RESET.
1.9.1.1 Normal single-chip mode
This mode is intended for normal device operation. The opcode from the on-chip memory is being executed after reset (requires the reset vector to be programmed correctly). The processor program is executed from internal memory. Table 1-11. Chip modes Chip Modes MODC Normal single chip 1 Special single chip 0
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1.9.1.2 Special single-chip mode
This mode is used for debugging operation, boot-strapping, or security related operations.The background debug mode (BDM) is active on leaving reset in this mode.
1.9.2 Debugging modes
The background debug mode (BDM) can be activated by the BDC module or directly when resetting into Special Single-Chip mode. Detailed information can be found in the BDC module section. Some modules feature a software programmable option to freeze the module status whilst the background debug mode is active to facilitate debugging. This is referred to as freeze mode at module level. Writing to internal memory locations using the debugger, whilst code is running or at a breakpoint, can change the flow of application code. The MC9S12ZVMB-Family supports BDC communication throughout the device Stop mode. During Stop mode, writes to control registers can alter the operation and lead to unexpected results. It is thus recommended not to reconfigure the peripherals during STOP using the debugger.
1.9.3 Low power modes
The device has two dynamic-power modes (run and wait) and two static low-power modes (stop and pseudo stop). For a detailed description refer to the CPMU section.
- Dynamic power mode: Run — Run mode is the main full pe rformance operating mode with the entire device clocked. The user can configure the device operating speed through selection of the clock source and the phase locked loop (PLL) frequency. To save power, unused peripherals must not be enabled.
- Dynamic power mode: Wait — This mode is entered when the CPU executes th e WAI instruction. In this mode the internal CPU clock is switched off. All peripherals can be active in system wait mode. For further power consumption the peripherals can individually turn off their local clocks. Asserting RESET, XIRQ, IRQ, or any other interrupt that is not masked, either locally or globally by a CCR bit, ends system wait mode.
- Static power modes: Static power (Stop) modes are entered following the CPU STOP instruction. If NVM commands are being processed then Stop mode entry is delayed, until they have been completed, then the Stop request is acknowledged and the device enters either Stop or Pseudo Stop mode. — Pseudo-stop: In this mode the system clocks ar e stopped but the oscillator is still running and the real time interrupt (RTI), watchdog (COP) and Autonomous Periodic Interrupt (API) may be enabled. Other peripherals are turned off. This mode consumes more current than system STOP mode but, as the oscillator continues to run, the full speed wake up time from this mode is significantly shorter. — Stop: In this mode, if the BDC is disabled, the oscillator is stopped, clocks are switched off and the VREG enters reduced power mode (RPM). The counters and dividers remain frozen. The autonomous periodic interrupt (API) may remain active but has a very low power consumption.
Chapter 1 Device Overview MC9S12ZVMB-Family MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 49 The key pad and SCI transceiver modules can be configured to wake the device, whereby current consumption is negligible. If the BDC is enabled, when the device enters Stop mode, the VREG remains in full performance mode. With BDC enabled and BDCCIS bit set, then all clocks remain active to allow BDC access to internal peripherals. If the BDC is enabled and BDCCIS is clear, then the BDCSI clock remains active to allow further BDC communication, but other clocks (with the exception of the API) are switched off. With the BDC enabled during Stop, the VREG full performance mode and clock activity lead to higher current consumption than with BDC disabled. If the BDC is enabled in Stop mode, then the BATS voltage monitoring remains enabled.
1.10 Security
The MCU security mechanism prevents unauthorized access to the flash memory. It must be emphasized that part of the security must lie with the application code. An extreme example would be application code that dumps the contents of the internal memory. This would defeat the purpose of security. Also, if an application has the capability of downloading code through a serial port and then executing that code (e.g. an application containing bootloader code), then this capability could potentially be used to read the EEPROM and flash memory contents even if the microcontroller is in the secure state. In this example, the security of the application could be enhanced by requiring a response authentication before any code can be downloaded. Device security details are also described in the flash block description.
1.10.1 Features
The security features of the S12Z chip family are:
- Prevent external access of the non-volatile memories (flash, EEPROM) content
- Restrict execution of NVM commands
- Prevent BDC access of internal resources
1.10.2 Securing the microcontroller
The chip can be secured by programming the security bits located in the options/security byte in the flash memory array. These non-volatile bits keep the device secured through reset and power-down. This byte can be erased and programmed like any other flash location. Two bits of this byte are used for security (SEC[1:0]). The contents of this byte are copied into the flash security register (FSEC) during a reset sequence. The meaning of the security bits SEC[1:0] is shown in Table 1-12. For security reasons, the state of device security is controlled by two bits. To put the device in unsecured mode, these bits must be programmed to SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’.
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Please refer to the flash block description for more security byte details.
1.10.3 Operation of the secured microcontroller
By securing the device, unauthorized access to the EEPROM and Flash memory contents is prevented. Secured operation has the following effects on the microcontroller:
1.10.3.1 Normal single chip mode (NS)
- .Background debug controller (BDC) operation is completely disabled
- Execution of flash and EEPROM commands is restri cted (described in flash block description).
1.10.3.2 Special single chip mode (SS)
- Background debug controller (B DC) commands are restricted
- Execution of flash and EEPROM commands is restri cted (described in flash block description). In special single chip mode the device is in active BDM after reset. In special single chip mode on a secure device, only the BDC mass erase and BDC control and status register commands are possible. BDC access to memory mapped resources is disabled. The BDC can only be used to erase the EEPROM and flash memory without giving access to their contents.
1.10.4 Unsecuring the microcontroller
Unsecuring the microcontroller can be done using three different methods: 1. Back-door key access 2. Reprogramming the security bits 3. Complete memory erase
1.10.4.1 Unsecuring the MCU us ing the back-door key access
In normal single chip mode, security can be temporarily disabled using the back-door key access method. This method requires that:
- The back-door key has been programmed to a valid value
- The KEYEN[1:0] bits within the flas h options/security byte select ‘enabled’. Table 1-12. Security bits SEC[1:0] Security State 00 1 (secured) 01 1 (secured) 10 0 (unsecured) 11 1 (secured)
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- The application program programmed into the microcontroller has the capability to write to the back-door key locations The back-door key values themselves should not normally be stored within the application data, which means the application program would have to be designed to receive the back-door key values from an external source (e.g. through a serial port). The back-door key access method allows debugging of a secured microcontroller without having to erase the flash. This is particularly useful for failure analysis. NOTE No back-door key word is allowed to have the value 0x0000 or 0xFFFF.
1.10.5 Reprogramming the security bits
Security can also be disabled by erasing and reprogramming the security bits within the flash options/security byte to the unsecured value. Since the erase operation will erase the entire sector (0x7F_FE00–0x7F_FFFF) the back-door key and the interrupt vectors will also be erased; this method is not recommended for normal single chip mode. The application software can only erase and program the flash options/security byte if the flash sector containing the flash options/security byte is not protected (see flash protection). Thus flash protection is a useful means of preventing this method. The microcontroller enters the unsecured state after the next reset following the programming of the security bits to the unsecured value. This method requires that:
- The application software previously programmed into the microcontroller has been designed to have the capability to erase and program the flash options/security byte.
- The flash sector containing the flash options/security byte is not protected.
1.10.6 Complete memory erase
The microcontroller can be unsecured by erasing the entire EEPROM and flash memory contents. If ERASE_FLASH is successfully completed, then the flash unsecures the device and programs the security byte automatically.
1.11 Resets and interrupts
1.11.1 Resets
Table 1-13. lists all reset sources and the vector locations. Resets are explained in detail in the S12CPMU module description.
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Table 1-13. Reset sources and vector locations
1.11.2 Interrupt vectors
Table 1-14 lists all interrupt sources and vectors in the default order of priority. The interrupt module description provides an interrupt vector base register (IVBR) to relocate the vectors. Vector Address Reset Source CCR Mask Local Enable 0xFFFFFC Power-On Reset (POR) None None Low Voltage Reset (LVR) None None External pin RESET None None Clock monitor reset None OSCE Bit in CPMUOSC register OMRE Bit in CPMUOSC2 register COP watchdog reset None CR[2: 0] in CPMUCOP register Table 1-14. Interrupt vector locations (Sheet 1 of 4) Vector Address(1) Interrupt Source CCR Mask Local Enable Wake up from STOP Wake up from WAIT Vector base + 0x1F8 Unimplemented page1 op-code trap (SPARE) None None - - Vector base + 0x1F4 Unimplemented page2 op-code trap (TRAP) None None - - Vector base + 0x1F0 Software inte rrupt instruction (SWI) None None - - Vector base + 0x1EC System call interrupt instruction (SYS) None None - - Vector base + 0x1E8 Machine exception None None - - Vector base + 0x1E4 Reserved Vector base + 0x1E0 Reserved Vector base + 0x1DC Spurious interrupt — None - - Vector base + 0x1D8 XIRQ interrupt request X bit None Yes Yes Vector base + 0x1D4 IRQ interrupt request I bit IRQCR(IRQEN) Yes Yes Vector base + 0x1D0 RTI time-out interrupt I bit CPMUINT (RTIE) See CPMU section Yes Vector base + 0x1CC TIM0 timer channel 0 I bit TIM0TIE (C0I) No Yes Vector base + 0x1C8 TIM0 timer channel 1 I bit TIM0TIE (C1I) No Yes Vector base + 0x1C4 TIM0 timer channel 2 I bit TIM0TIE (C2I) No Yes Vector base + 0x1C0 TIM0 timer channel 3 I bit TIM0TIE (C3I) No Yes Vector base + 0x1BC to Vector base + 0x1B0 Reserved Vector base + 0x1AC TIM0 timer overflow I bit TIM0TSCR2(TOI) No Yes Vector base + 0x1A8 Reserved
Chapter 1 Device Overview MC9S12ZVMB-Family MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 53 Vector base + 0x1A4 Reserved Vector base + 0x1A0 SPI0 I bit SPI0CR1 (SPIE, SPTIE) No Yes Vector base + 0x19C SCI0 I bit SCI0CR2 (TIE, TCIE, RIE, ILIE) No Yes SCI0ACR1(RXEDGIE) Yes Yes Vector base + 0x198 SCI1 I bit SCI1CR2 (TIE, TCIE, RIE, ILIE) No Yes SCI0ACR1(RXEDGIE) Yes Yes Vector base + 0x194 Reserved Vector base + 0x190 Reserved Vector base + 0x18C ADC0 Error I bit ADC0EIE (IA_EIE, CMD_EIE, EOL_EIE, TRIG_EIE, RSTAR_EIE, LDOK_EIE) ADC0IE(CONIF_OIE) No Yes Vector base + 0x188 ADC0 sequence abort done I bit ADC0IE(SEQAD_IE) No Yes Vector base + 0x184 ADC0 conversion complete I bit ADC0CONIE[15:0] No Yes Vector base + 0x180 Oscillator status interrupt I bit CPMUINT (OSCIE) No Yes Vector base + 0x17C PLL lock interrupt I bit CPMUINT (LOCKIE) No Yes Vector base + 0x178 to Vector base + 0x174 Reserved Vector base + 0x170 RAM error I bit EECIE (SBEEIE) No Yes Vector base + 0x16C to Vector base + 0x168 Reserved Vector base + 0x164 FLASH error I bit FERCNFG (SFDIE) No Yes Vector base + 0x160 FLASH command I bit FCNFG (CCIE) No Yes Vector base + 0x15C to Vector base + 0x148 Reserved Vector base + 0x144 LINPHY over-current interrupt I bit LPIE (LPERR) No Yes Vector base + 0x140 BATS supply voltage monitor interrupt I bit BATIE (BVHIE,BVLIE) No Yes Vector base + 0x13C GDU Desaturation Error I bit GDUIE (GDSEIE) No Yes Vector base + 0x138 GDU Voltage/Current Limit Detected I bit GDUIE (GOCIE[0], GHHDFIE, GLVLSFIE) No Yes Vector base + 0x134 HSDRV over-current interrupt I bit HSIE (HSOCIE) No Yes Table 1-14. Interrupt vector locations (Sheet 1 of 4) Vector Address(1) Interrupt Source CCR Mask Local Enable Wake up from STOP Wake up from WAIT
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Vector base + 0x110 NGPIO over-current (Port T) I bit OCIET[2] No Yes Vector base + 0x10C Port P interrupt I bit PIEP[1:0] Yes Yes Vector base + 0x108 EVDD over-current I bit OCIEP[0] No Yes Vector base + 0x104 Low-voltage interrupt (LVI) I bit CPMUCTRL (LVIE) No Yes Vector base + 0x100 Autonomous periodical interrupt (API) I bit CPMUAPICTRL (APIE) Yes Yes Vector base + 0x0FC High temperature in terrupt I bit CPMUHTCTL(HTIE) No Yes Vector base + 0x0F8 Reserved Vector base + 0x0F4 Port AD interrupt I bit PIEADH(PIEADH0) PIEADL(PIEADL[7:0]) Yes Yes Vector base + 0x0F0 PTU Reload Overrun I bit PTUIEH(PTUROIE) No Yes Vector base + 0x0EC PTU Trigger0 Error I bit PTUIEL(TG0AEIE,TG0REIE, TG0TEIE) No Yes Vector base + 0x0E8 Reserved Vector base + 0x0E4 PTU Trigger0 Done I bit PTUIEL[TG0DIE] No Yes Vector base + 0x0E0 to Vector base + 0x0D4 Reserved Vector base + 0x0D0 PMF Reload A I bit PMFENCA(PWMRIEA) No Yes Vector base + 0x0CC PMF Reload B I bit PMFENCB(PWMRIEB) No Yes Vector base + 0x0C8 PMF Reload C I bit PMFENCC(PWMRIEC) No Yes Vector base + 0x0C4 PMF Fault I bit PMFFIE(FIE[5:0]) No Yes Vector base + 0x0C0 PMF Reload Overrun I bit PMFROIE(PMFROIEA,PMF ROIEB,PMFROIEC) No Yes Vector base + 0x0BC Port L interrupt I bit PIEL[2:0] Yes Yes Vector base + 0x0B8 to Vector base + 0x0B0 Reserved Vector base + 0x0AC TIM1 timer channel 0 I bit TIM1TIE (C0I) No Yes Vector base + 0x0A8 TIM1 timer channel 1 I bit TIM1TIE (C1I) No Yes Vector base + 0x0A4 TIM1 timer channel 2 I bit TIM1TIE (C2I) No Yes Vector base + 0x0A0 TIM1 timer channel 3 I bit TIM1TIE (C3I) No Yes Vector base + 0x09C to Vector base + 0x090 Reserved Table 1-14. Interrupt vector locations (Sheet 1 of 4) Vector Address(1) Interrupt Source CCR Mask Local Enable Wake up from STOP Wake up from WAIT
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1.11.3 Effects of reset
When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections for register reset states. On each reset, the flash module executes a reset sequence to load flash configuration registers.
1.11.3.1 Flash configura tion reset sequence phase
On each reset, the flash module will hold CPU activity while loading flash module registers from the flash memory If double faults are detected in the reset phase, flash module protection and security may be active on leaving reset. This is explained in more detail in the flash module description.
1.11.3.2 Reset while flash command active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed.
1.11.3.3 I/O pins
Refer to the PIM section for reset configurations of all peripheral module ports.
1.11.3.4 RAM
The system RAM arrays, including their ECC syndromes, are initialized following a power on reset. All other RAM arrays are not initialized out of any type of reset. With the exception of a power-on-reset the RAM content is unaltered by a reset occurrence.
1.12 Module device level dependencies
1.12.1 CPMU COP and GDU GSUF configuration
The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register are loaded from the flash configuration field byte at global address 0xFF_FE0E during the reset sequence. The GSUF bit in the Vector base + 0x08C TIM1 timer overflow I bit TIM1TSCR2(TOI) No Yes Vector base + 0x088 to Vector base + 0x010 Reserved 1. 15 bits vector address based Table 1-14. Interrupt vector locations (Sheet 1 of 4) Vector Address(1) Interrupt Source CCR Mask Local Enable Wake up from STOP Wake up from WAIT
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GDUF register is also loaded from the Flash configuration field byte at global address 0xFF_FE0E during the reset sequence. See Table 1-15, Table 1-17 and Table 1-17 for coding.
1.12.2 Flash IFR mapping
1.12.3 BDC command restriction
The BDC command READ_DBGTB returns 0x00 on this device because the DBG module does not feature a trace buffer. Table 1-15. Initial COP rate configuration NV[2:0] in FOPT Register CR[2:0] in CPMUCOP Register 000 111 001 110 010 101 011 100 100 011 101 010 110 001 111 000 Table 1-16. Initial WCOP configuration NV[3] in FOPT Register WCOP in CPMUCOP Register Table 1-17. Initial GSUF configuration NV[7] in FOPT Register GSUF in GDUF Register Table 1-18. Flash IFR mapping 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 I F R B y t e A d d r e s s DVBE Temperature sensor ADC result (probe) 0x1F_C054 & 0x1F_C055
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1.13 Application information
1.13.1 Temperature sensor
The DVBE temperature sensor output is mapped to the ADC internal channel 7. It is tested in production at 26C, using conversions of ADC internal channel 7 and storing the result to the flash location 0x1F_C054, 0x1F_C055 as a 12-bit right aligned value. The accuracy of the controlled production test temperature is 26 C +/-3 °C. The slope is linear over the device operating temperature range. The accuracy of the slope dV/dT is 6 mV/C +/-0.2 mV/C. The typical application is to use the temperature sensor to warn if device or application temperature is approaching the maximum limit in order to take precautionary measures. The following example uses an application aiming to detect a maximum temperature of 126°C, whereby the difference between the maximum level and tested level is 100C (for calculation simplicity) Figure 1-6 illustrates the effect of the slope variation alone. Typically a 100C difference corresponds to 600 mV (100 x 6 mV) change in the DVBE output compared to the stored value from 26C production test (V26). Thus the application could be configured to detect a 600 mV change with respect to V26. Considering the dV/dT slope minimum/maximum specification, an inaccuracy of +/-20 mV may exist over the 100C range, whereby +/-20 mV corresponds to a +/-3.3C. Thus, if configured to detect V26 + 600 mV , the detection could occur at 129.3C, as shown by the red 5.8 mV/C slope of Figure 1-6. To compensate for the minimum dV/dT the application could be configured to detect a 580 mV change with respect to V26. Note that the result stored in flash is a 12-bit value. However the ADC is only specified to 10-bit accuracy for applications. Thus the full 12-bit value in flash should be considered for V26 calculation.
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Figure 1-6. DVBE effect of slope inaccuracy Voltage (V) Temperature (C) V26 126 6 mV/C 5.8 mV/C 6.2 mV/C 0.6 V 0.58 V 129.3
Chapter 1 Device Overview MC9S12ZVMB-Family MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 59 Furthermore the production test temperature control accuracy is limited to +/-3C. Figure 1-7 illustrates the effect of this limitation, whereby the value V26 actually corresponds to a test temperature of 29C. Thus, if configured to detect V26 + 600mV , the detection could be offset by 3C and in this case would occur at 129C for a typical slope. Considering further inaccuracy for the minimum slope results in an actual temperature limit detection at 132.3C as shown in Figure 1-7. Further compensation can be applied, if necessary by adjusting the detection level. Figure 1-7. Effect of slope plus V26 reference inaccuracy The ADC uses the on chip generated VDDA as the VRH reference. The accuracy of VRH can also be considered. In order to compensate for VRH load variation, the reference voltage can be indirectly measured using the internal reference voltage VBG. VBG is mapped to ADC channel internal_1. Thus a VRH reference can be obtained by applying a clean, unloaded VRH and converting VBG. The resulting ADC conversion result of VBG can be stored to flash for reference. By measuring the voltage VBG in the application environment and comparing the result to the reference value stored in flash, it is possible to determine the current ADC reference voltage VRH: Voltage (V) Temperature (C) V26 126 6 mV/C 5.8 mV/C 0.6 V 0.562 V 129 26 Typical slope from V26 Typical offset slope from V26 Minimum dV/dT offset slope from V26 132.3
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VRH = (StoredReference/ConvertedReference) x 5V Eqn. 1-1 The absolute value of the DVBE conversion can be determined as follows: VDVBE = ConvertedDVBE x (StoredReference/ConvertedReference) x 5V/2n Eqn. 1-2 ConvertedDVBE: Result of the analog to digital conversion of the DVBE ConvertedReference: Result of internal channel conversion StoredReference: Reference value from clean, unloaded VRH, VBG conversion n: ADC resolution (10 bit) VRH variation over temperature can also be considered, whereby the maximum VRH differential between 26C and 126C is typically -46mV (126C value is always less than the 26C value). This correlates to a maximum VRH induced error of -4C when applied to the VDVBE of Equation 1-2.
1.13.2 SCI baud rate detection
The baud rate for SCI0 and SCI1 is achieved by using a timer channel to measure the data rate on the RXD signal. 1. Establish the link: — For SCI0: Set [T0IC3RR1:T0IC3RR0]=0b01 to re route TIM0 input capture channel 3 (IC0_3) to the RXD0 signal of SCI0. — For SCI1: Set [T0IC3RR1:T0IC3RR0]=0b11 to re route TIM0 input capture channel 3 (IC0_3) to the RXD1 signal of SCI1. 2. Determine pulse width of inco ming data: Configure TIM0 IC3 to measure time between incoming signal edges.
1.13.3 BDCM complementary mode operation
This section describes BDCM control using center aligned complementary mode with deadtime insertion. The brushed DC motor power stage topology is a classical full bridge as shown in Figure 1-8. The brushed DC motor is driven by the DC voltage source. A rotational field is created by means of commutator and brushes on the motor.
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Assuming first quadrant operation, forward accelerating operation, the applied voltage at node A must exceed the applied voltage at node B (Figure 1-8). Thus the PWM0 duty cycle must exceed the PWM2 duty cycle. The PWM duty cycle of PWM0 defines the voltage at the first power stage branch. The PWM duty cycle of PWM2 defines the voltage at the second power stage branch. Modulating the PWM duty cycle every period using the function FPWM then the duty cycle is expressed as: PWM0 duty-cycle = 0.5 + (0.5 * FPWM); For -1<=FPWM <= 1; PWM2 duty-cycle = 0.5 - (0.5 * FPWM)
1.13.3.1 Control loop timing considerations
Delays within the separate control loop elements require consideration to ensure correct synchronization. Regarding the raw PWM signal as the starting point and stepping through the control loop stages, the factors shown in Figure 1-10 contribute to delays within the control loop, starting with the deadtime insertion, going through the external FETs and back into the internal ADC measurements of external voltages and currents. Figure 1-10. Control loop delay overview The PWM deadtime (TDEAD_X) is an integral number of bus clock cycles, configured by the PMF deadtime registers. The GDU propagation delays (tdelon, tdeloff) are specified in the electrical parameter Table E-1. The FET turn on times (tGHGON) are load dependent but are specified for particular loads in the electrical parameter Table E-1. The current sense amplifier delay is highly dependent on external components. The ADC delay until a result is available is specified as the conversion period NCONV in Table C-1. PWM with PWM base PWM cycle deadtime GDU propagation FET turn on Current sense settling time ADC delay TDEAD_x tdelon tHGON (tcslsst)
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1.13.4 Power domain considerations
The MC9S12ZVMB-Family power domains are illustrated in Figure 1-11. More detailed information is included in the individual module descriptions. Figure 1-11. Power domain overview The system supply voltage VRBATP is a reverse battery protected input voltage. It must be protected against reverse battery connections and must not be connected directly to the battery voltage (VBAT). The device supply voltage VSUP provides the input voltage for the internal regulator, VREG_AUTO, and to the GDU LDO. The VDDX domain supplies the device I/O pins, VDDA supplies the ADC and internal bias current generators. The VDDA and VDDX pins must be connected at board level, they are not GHHDF CORE RAM’s PLL IRC OSC FLASH PADS GDU LDO LINPHY VREG_AUTO 1.8 V 2.8 V 5 V VDDA VSSA VSS VLS_OUT GHD GLG GLS GPIO VSSX VSUP (12 V/18 V) VDDX LIN LGND GFDE PORF LVRF GLVLSF CPS INT INT RES RES BATS INTADC VRH_SEL VRL_SEL VRH VRL VSSA VDDA ADC GCPE VLS (11V) CP VCP VRBATP VSUPHS (12 V/18 V) HS VDD VDDF VRH_0
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connected directly internally. ESD protection diodes exist between VDDX and VDDA, therefore forcing a common operating range. The VDD domain supplies the internal device logic. The VDDF domain supplies sections of the internal Flash NVM circuitry. The LINPHY pull-up resistor is internally connected to the VSUP voltage. The external connections for the VSUP pin must ensure a reverse battery protection. The High-side driver supply, VSUPHS, also requires an external reverse battery protection.
1.13.4.1 Voltage domain monitoring
The BATS module monitors the voltage on the VSUP pin, providing status and flag bits, an interrupt and a connection to the ADC, for accurate measurement of the scaled VSUP level. The POR circuit monitors the VDD (internal) and VDDA domains, ensuring a reset assertion until an adequate voltage level is attained. The LVR circuit monitors the VDD, VDDF and VDDX domains, generating a reset when the voltage in any of these domains drops below the specified assert level. The VDDX LVR monitor is disabled when the VREG is in reduced power mode. A low voltage interrupt circuit monitors the VDDA domain. The GDU High-side drain voltage, pin GHD, is monitored within the GDU and mapped to an interrupt. A connection to the ADC is provided for accurate measurement of a scaled GHD level.
1.13.4.2 FET-predriver (GDU) supplies
A dedicated low drop regulator is used to generate the VLS_OUT voltage from VSUP. The VLS_OUT voltage is used to supply the Low-side drivers and can be externally, directly connected to the VLS input.
1.13.4.3 Bootstrap precharge
The FET-predriver High-side driver must provide a sufficient gate-source voltage and sufficient charge for the gate capacitance of the external FETs. A bootstrap circuit is used to provide sufficient charge, whereby the capacitor CBS is first charged to VLS_OUT via an internal diode, when the Low-side driver is active Figure 1-12. When the High-side driver switches on, the charge on this capacitor, supplies the FET- predriver via the VBSx pin. The CBS capacitor can only be charged if the Low-side driver is active, so after a long period of inactivity of the Low-side driver, the CBS capacitor becomes discharged. In this case, the Low-side driver must be switched on to charge CBS before commencing High-side driving. The time it takes to discharge the bootstrap capacitor CBS can be calculated from the size of the bootstrap capacitor CBS and the leakage current on VBSx pin. The bootstrap capacitors must be precharged before turning on the high-side drivers for the first time. This can be done by using the PMF software output control mechanism: PMFOUTC = 0x0F; // SW control on all outputs PMFOUTB = 0x0A; // All high-sides off, all low-sides on The PWM signals should be configured to start with turning on the low-side before the high-side drivers in order to assure precharged bootstraps. Therefore invert the PWM signals:
Chapter 1 Device Overview MC9S12ZVMB-Family MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 65 PMFCINV = 0x0F; // Invert all channels to precharge bootstraps
1.13.4.4 High-side charge pump for 100% duty cycle
A charge pump voltage is used to supply the High-side FET-predriver with enough current to maintain the gate source voltage. To generate this voltage an external charge pump is driven by the pin CP, switching between 0 V and 11 V . The pumped voltage is then applied to the pin VCP. At 100% duty cycle operation the low-side turn on time is zero, which can cause bootstrap charge to decay. In order to speed-up the high-side gate voltage level directly after commutation, the software should drive the first PWM cycle with a duty cycle meeting an on-time of at least tminpulse for the low-side drivers and then switch back to 100% again. The GDU High-side drain voltage, pin GHD, is supplied from VBAT through a reverse battery protection circuit. In a typical application the charge pump is used to switch on an external NMOS, N1, with source connected to VBAT, by generating a voltage of VBAT+VLS-(2 x Vdiode). In a reverse battery scenario, the external bipolar turns on, ensuring that the GHD pin is isolated from VBAT by the external NMOS, N1.
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Figure 1-12. High-side supply and charge pump concept GCPE VLS_OUT (11 V) CP VCP VBSx 0 V 11 V 1000 uF (Motor Dependent) S D 1 nF GHSx GHD High-side Low-side VBAT CBS 10 nF Diode voltage drop = Vdiode GCPCD GHGx
MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductor 67 Chapter 2 Port Integration Module (S12ZVMBPIMV3) Table 2-1. Revision History Rev. No. (Item No.) Date (Submitted By) Sections Affected Substantial Change(s) V03.00 19 Jun 2015 • Initial release for S12ZVMB-family V03.01 7 Jul 2015 • Incorporated feedback from review V03.02 14 Jul 2015 2.3.2.6/2-
- Added TIM1 IC0 routing option V03.03 22 Jul 2015 • Typos and formatting V03.04 24 Jul 2015 2.3.2.5/2-
- Changed write restrictions of MODRR4 register
- Typos and formatting V03.05 30 Jul 2015 • Typos and formatting V03.06 5 Aug 2015 2.1.1/2-68 2.2/2-71 2.3.1/2-77 2.3.2.6/2-
- Added PT7
- Typos and formatting V03.06 5 Aug 2015 2.1.1/2-68 2.2/2-71 2.3.1/2-77 2.3.2.6/2-
- Added PT7
- Typos and formatting V03.07 13 Aug 2015 Table 2-4 Table 2-44
- Typos and formatting V03.08 28 Aug 2015 2.1.1/2-68 2.3.1/2-77 2.3.2.1/2- 83Table 2- Table 2-6
- Changed SPI0 (SCLK) routing V03.09 1 Sep 2015 2.3.4.5/2- Table 2-45
- Corrections
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2.1 Introduction
2.1.1 Overview
The S12ZVMB-family port integration module establishes the interface between the peripheral modules and the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins. This document covers:
- Port E
- P o r t A D V03.10 16 Sep 2015 2.1.1/2-68 2.2/2-71
- Corrections V03.11 23 Nov 2015 2.4.6/2- 110
- Corrections V03.12 23 Mar 2016 • Corrections GPIO DBG SCI1 PMF External Oscillator Pins PTE1 DBGEE V TXD1 PWM1 XTAL PE1 PTE0 RXD1 PWM0 EXTAL PE0 GPIO/KWU ADC0 SPI0 GDU PTU Pins PTADH0 AN0_8 PAD8 PTADL7 AN0_7 PAD7 PTADL6 AN0_6 PAD6 PTADL5 AN0_5 PAD5 Rev. No. (Item No.) Date (Submitted By) Sections Affected Substantial Change(s)
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- P o r t T
- Port P PTADL4 AN0_4 SS0 PAD4 PTADL3 AN0_3 PTUT0 PAD3 PTADL2 AN0_2 AMP0 PAD2 PTADL1 AN0_1 AMPM0 PAD1 PTADL0 AN0_0 AMPP0 PAD0 GPIO TIM0 TIM1 PMF SPI0 SCI0 SCI1 LINPHY0 PMF ECLK/ XIRQ Pins PTT7 IOC1_3 PT7 PTT6 IOC1_2 PT6 PTT5 IOC1_1 PT5 PTT4 IOC1_0 PT4 PTT3 IOC0_3 PT3 PTT2 IOC0_2 PWM3 LP0RXD FAULT5 ECLK PT2 PTT1 IOC0_1 PWM2 MISO0 TXD0 TXD1 LP0DR1 PT1 PTT0 IOC0_0 MOSI0 RXD0 RXD1 XIRQ PT0 GPIO/KWU PMF SPI0 PTU PMF LINPHY0 IRQ Pins PTP1 PWM5 SCK0 FAULT5 PP1 PTP0 PWM4 PTURE LP0TXD IRQ PP0
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- Port L Most I/O pins can be configured by register bits to select data direction and to enable and select pullup or pulldown devices. NOTE This document shows the superset of all available features offered by the S12ZVMB device family. Refer to the package and pinout section in the device overview for functions not available for a particular device or package option.
2.1.2 Features
The PIM includes these distinctive registers:
- Data registers for ports E, AD, T, P when used as general-purpose I/O
- Data direction registers for ports E, AD , T, P when used as general-purpose I/O
- Control registers to enable pull devices on ports E, AD, T, P
- Control registers to select pullups or pulldowns on ports E, AD, T, P
- Control register to enable digi tal input buffers on port AD and L
- Interrupt enable register for pin interr upts and key-wakeup (KWU) on port AD, P and L
- Interrupt flag register for pin interr upts and key-wakeup (KWU) on port AD, P and L
- Control register to configure IRQ pin operation
- Control register to enable ECLK output
- Routing registers to support signa l relocation on external pins and control internal routings: — 2 PWM channels to alternative pins (1 option each) — 4 TIM0 channels to alternative pins — Various SCI0-LINPHY0 rout ing options for standalone use and conformance testing — SCI1 to alternative pins (1 option) — HSDRV control selection from PWMT IM OC or related register bit — Internal RXD0 and RXD1 link to TIM0 input ca pture channel (IC0_3) for baud rate detection — Internal ACLK link to TIM0 input capture channel (IC0_2) for calibration and clock monitoring purposes HVI/KWU ADC0 TIM1 Pins PTIL2 AN0_11 IC1_2 PL2 PTIL1 AN0_10 IC1_1 PL1 PTIL0 AN0_9 IC1_0 PL0
Chapter 2 Port Integration Module (S12ZVMBPIMV3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 71 A standard port pin has the following minimum features:
- Input/output selection
- 5V output drive
- 5V digital and analog input
- Input with selectable pullup or pulldown device Optional features supported on dedicated pins:
- Interrupt input with glitch filtering
- High current drive strength from VDDX with over-current protection
- High current drive strength to VS SX with over-current protection
- Selectable drive strength fo r high current capable outputs
2.2 External Signal Description
This section lists and describes the signals that do connect off-chip. Table 2-8 shows all pins with the pins and functions that are controlled by the PIM. Routing options are denoted in parentheses. NOTE If there is more than one function associated with a pin, the output priority is indicated by the position in the table from top (highest priority) to bottom (lowest priority). Inputs do not arbitrate priority unless noted differently in Table 2-45. Table 2-2. BKGD Pin Functions and Priorities Port Pin Pin Function & Priority I/O Description Routing Register Bit Func. after Reset BKG D BKGD MODC (1) 1. Function active when RESET asserted I MODC input during RESET — BKGD BKGD I/O S12ZBDC communication —
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Table 2-3. Port E Pin Functions and Priorities Port Pin Pin Function & Priority I/O Description Routing Register Bit Func. after Reset E PE1 XTAL — CPMU OSC signal — GPIO (PWM1) O PWM channel 1 P0C1RR (TXD1) I/O SCI1 transmit SCI1RR DBGEEV I DBG external event — PTE[1] I/O GPIO — PE0 EXTAL — CPMU OSC signal — (PWM0) O PWM channel 0 P0C0RR (RXD1) I SCI1 receive SCI1RR PTE[0] I/O GPIO —
Chapter 2 Port Integration Module (S12ZVMBPIMV3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 73 Table 2-4. Port AD Pin Functions and Priorities Port Pin Pin Function & Priority I/O Description Routing Register Bit Func. after Reset AD PAD8 AN8 I ADC0 analog input — GPIO PTADH[0]/ KWADH[0] I/O GPIO with pin-interrupt and key-wakeup — PAD7-5 AN7-5 I ADC0 analog input — PTADL[7:5]/ KWADL[7:5] I/O GPIO with pin-interrupt and key-wakeup — PAD4 SS0 I/O SPI0 slave select — AN4 I ADC0 analog input — PTADL[4]/ KWADL[4] I/O GPIO with pin-interrupt and key-wakeup — PAD3 PTUT0 O PTU trigger 0 — AN3 I ADC0 analog input — PTADL[3]/ KWADL[3] I/O GPIO with pin-interrupt and key-wakeup — PAD2 AMP0 O GDU AMP0 output — AN2 I ADC0 analog input — PTADL[2]/ KWADL[2] I/O GPIO with pin-interrupt and key-wakeup — PAD1 AMPM0 I GDU AMP0 inverting input (-) — AN1 I ADC0 analog input — PTADL[1]/ KWADL[1] I/O GPIO with pin-interrupt and key-wakeup — PAD0 AMPP0 I GDU AMP0 non-inverting input (+) — AN0 I ADC0 analog input — PTADL[0]/ KWADL[0] I/O GPIO with pin-interrupt and key-wakeup —
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Table 2-5. Port T Pin Functions and Priorities Port Pin Pin Function & Priority I/O Description Routing Register Bit Func. after Reset T PT7 IOC1_3 I/O TIM1 channel 3 T1IC3RR GPIO PTT[7] I/O GPIO — PT6 IOC1_2 I/O TIM1 channel 2 T1IC2RR,T1OC2RR PTT[6] I/O GPIO — PT5 IOC1_1 I/O TIM1 channel 1 T1IC1RR,T1OC1RR PTT[5] I/O GPIO — PT4 IOC1_0 I/O TIM1 channel 0 T1IC0RR PTT[4] I/O GPIO — PT3 IOC0_3 I/O TIM0 channel 3 T0IC3RR1-0 PTT[3] I/O GPIO — PT2(1) 1. High current capable low-side output with over-current interrupt and protection for all sources (see 2.4.5.3/2-110) ECLK O Free-running clock — FAULT5 I PMF fault FAULT5RR (LP0RXD) O LINPHY0/HVPHY0 receive output S0L0RR2-0 (PWM3) O PMF channel 3 P0C3RR IOC0_2 I/O TIM0 channel 2 T0IC2RR PTT[2]/ NGPIO I/O GPIO — PT1 (LP0DR1) O LPTXD0 direct control by LP0DR[LP0DR1] S0L0RR2-0 TXD1 I/O SCI1 transmit SCI1RR (TXD0) I/O SCI0 transmit S0L0RR2-0 MISO0 I/O SPI0 master in/slave out — (PWM2) O PMF channel 2 P0C2RR IOC0_1 I/O TIM0 channel 1 — PTT[1] I/O GPIO — PT0 XIRQ (2) 2. The interrupt is enabled by clearing the X mask bit in the CPU CCR. The pin is forced to input upon first clearing of the X bit and is held in this state until reset. A stop or wait recovery using XIRQ with the X bit set is not available. I Non-maskable level-sensitive interrupt — RXD1 I SCI1 receive SCI1RR (RXD0) I SCI0 receive S0L0RR2-0 MOSI0 I/O SPI0 master out/slave in — IOC0_0 I/O TIM0 channel 0 — PTT[0] I/O GPIO —
Chapter 2 Port Integration Module (S12ZVMBPIMV3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 75 Table 2-6. Port P Pin Functions and Priorities Table 2-7. Port L Pin Functions and Priorities Port Pin Pin Function & Priority I/O Description Routing Register Bit Func. after Reset P PP1 (FAULT5) I PMF fault FAULT5RR GPIO SCK0 I/O SPI0 serial clock — PWM5 O PMF channel 5 P0C5RR PTP[1]/ KWP[1] I/O GPIO with pin-interrupt and key-wakeup — PP0(1) 1. High current capable high-side output with over-current interrupt and protection for all sources (see 2.4.5.3/2-110) IRQ I Maskable level- or falling edge-sensitive interrupt (LP0TXD) I LINPHY0/HVPHY0 transmit input S0L0RR2-0 PTURE O PTU reload event with over-current interrupt; high-current capable (20 mA) PWM4 O PMF channel 4 with over-current interrupt; high-current capable (20 mA) P0C4RR PTP[0]/ KWP[0]/ EVDD I/O General-purpose; with interrupt and wakeup Switchable external power supply output with over-current interrupt; high-current capable (20 mA) Port Pin Pin Function & Priority I/O Description Routing Register Bit Func. after Reset L PL2 IOC1_2 I TIM1 input capture channel 2 T1IC2RR HVI AN11 I ADC0 analog input AN11 PTIL[2]/ KWL[2] I HVI with pin-interrupt and key-wakeup — PL1 IOC1_1 I TIM1 input capture channel 1 T1IC1RR AN10 I ADC0 analog input AN10 PTIL[1]/ KWL[1] I HVI with pin-interrupt and key-wakeup — PL0 IOC1_0 I TIM1 input capture channel 0 T1IC0RR AN9 I ADC0 analog input AN9 PTIL[0]/ KWL[0] I HVI with pin-interrupt and key-wakeup —
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Table 2-8. HSDRV Pin Functions and Priorities
2.2.1 Internal Routing Options
The following table summarizes the internal routing options.
2.3 Memory Map and Register Definition
This section provides a detailed description of all port integration module registers. Subsection 2.3.1 shows all registers and bits at their related addresses within the global SOC register map. A detailed Port Pin Pin Function & Priority I/O Description Routing Register Bit Func. after Reset N/A (1) 1. Not a PIM port. Listed here for priority information only. Refer to section S12HSDRV. HS1 (PWM5) O PMF channel 5 P0C5RR HSDRV (OC1_2) O TIM1 output compare channel 2 T1OC2RR HSDR[HSDR1] O High-side driver 1 — HS0 (PWM4) O PMF channel 4 P0C4RR (OC1_1) O TIM1 output compare channel 1 T1OC1RR HSDR[HSDR0] O High-side driver 0 — Table 2-9. Internal Routing Options Internal Signal Connects to Routing Bits ACLK IC0_2 T0IC2RR RXD0, RXD1 IC0_3 T0IC3RR1-0 TIM0 OC2 ADC0 Trigger TRIG0RR1-0 PMF reload PTU trigger 0 HVI0 IC1_0 T1IC0RR HVI1 IC1_1 T1IC1RR HVI2 IC1_2 T1IC2RR
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2.3.1 Register Map
Name B i t 7 654321 B i t 0 0x0200 MODRR0 R0 0 Reserved SCI1RR S0L0RR2-0W 0x0201 MODRR1 R 000000 TRIG0RR1-0W 0x0202 MODRR2 R 00000000 W 0x0203 MODRR3 R 000 T0IC3RR1-0 T0IC2RR W 0x0204 MODRR4 R FAULT5R R P0C5RR P0C4RR P0C3RR P0C2RR P0C1RR P0C0RRW 0x0205 MODRR5 R T1IC3RR T1IC2RR T1IC1RR T1IC0RR T1OC2RR T1OC1RR W 0x0206– 0x0207 Reserved R 00000000 W 0x0208 ECLKCTL R NECLK 0000000 W 0x0209 IRQCR R IRQE IRQEN 000000 W 0x020A– 0x020C Reserved R 00000000 W 0x020D Reserved R 00000 Reserved ReservedW 0x020E Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x020F Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x0210– 0x025F Reserved R 00000000 W 0x0260 PTE R 000000 PTE1 PTE0W
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W 0x0262 PTIE R 000000 P T I E 1 P T I E 0 W 0x0263 Reserved R 00000000 W 0x0264 DDRE R 000000 DDRE1 DDRE0W 0x0265 Reserved R 00000000 W 0x0266 PERE R 000000 PERE1 PERE0W 0x0267 Reserved R 00000000 W 0x0268 PPSE R 000000 PPSE1 PPSE0W 0x0269– 0x027F Reserved R 00000000 W 0x0280 PTADH R 0000000 PTADH0W 0x0281 PTADL R PTADL7 PTADL6 PTADL5 PTADL4 PTADL3 PTADL2 PTADL1 PTADL0 W 0x0282 PTIADH R 0000000 P T I A D H 0 W 0x0283 PTIADL R PTIADL7 PTIADL6 PTIADL5 PTIADL4 PTIADL3 PTIADL2 PTIADL1 PTIADL0 W 0x0284 DDRADH R 0000000 DDRADH0W 0x0285 DDRADL R DDRADL7 DDRADL6 DDRADL5 DDRADL4 DDRADL3 DDRADL2 DDRADL1 DDRADL0 W 0x0286 PERADH R 0000000 PERADH0W Global Address Register Name B i t 7 654321 B i t 0
Chapter 2 Port Integration Module (S12ZVMBPIMV3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 79 0x0287 PERADL R PERADL7 PERADL6 PERADL5 PERADL4 PERADL3 PERADL2 PERADL1 PERADL0 W 0x0288 PPSADH R 0000000 PPSADH0W 0x0289 PPSADL R PPSADL7 PPSADL6 PPSADL5 PPSADL4 PPSADL3 PPSADL2 PPSADL1 PPSADL0 W 0x028A– 0x028B Reserved R 00000000 W 0x028C PIEADH R 0000000 PIEADH0W 0x028D PIEADL R PIEADL7 PIEADL6 PIEADL5 PIEADL4 PIEADL3 PIEADL2 PIEADL1 PIEADL0 W 0x028E PIFADH R 0000000 PIFADH0W 0x028F PIFADL R PIFADL7 PIFADL6 PIFADL5 PIFADL4 PIFADL3 PIFADL2 PIFADL1 PIFADL0 W 0x0290– 0x0297 Reserved R 00000000 W 0x0298 DIENADH R 0000000 DIENADH0W 0x0299 DIENADL R DIENADL7 DIENADL6 DIENADL5 DIENADL4 DIENADL3 DIENADL2 DIENADL1 DIENADL0 W 0x029A– 0x02BF Reserved R 00000000 W 0x02C0 PTT R PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 W 0x02C1 PTIT R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 W 0x02C2 DDRT R DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 W 0x02C3 PERT R PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 W Global Address Register Name B i t 7 654321 B i t 0
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R PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 W 0x02C5– 0x02C8 Reserved R 00000000 W 0x02C9 OCPET R 00000 OCPET2 W 0x02CA OCIET R 00000 OCIET2 W 0x02CB OCIFT R 00000 OCIFT2 W 0x02CC Reserved R 00000000 W 0x02CD RDRT R 00000 RDRT2 W 0x02CE– 0x02CF Reserved R 00000000 W 0x02D0– 0x02EF Reserved R 00000000 W 0x02F0 PTP R 000000 PTP1 PTP0 W 0x02F1 PTIP R 000000 P T I P 1 P T I P 0 W 0x02F2 DDRP R 000000 DDRP1 DDRP0 W 0x02F3 PERP R 000000 PERP1 PERP0 W 0x02F4 PPSP R 000000 PPSP1 PPSP0 W 0x02F5 Reserved R 00000000 W 0x02F6 PIEP R 000000 PIEP1 PIEP0 W Global Address Register Name B i t 7 654321 B i t 0
Chapter 2 Port Integration Module (S12ZVMBPIMV3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 81 0x02F7 PIFP R 000000 PIFP1 PIFP0 W 0x02F8 Reserved R 00000000 W 0x02F9 OCPEP R 0000000 OCPEP0 W 0x02FA OCIEP R 0000000 OCIEP0 W 0x02FB OCIFP R 0000000 OCIFP0 W 0x02FC Reserved R 00000000 W 0x02FD RDRP R 0000000 RDRP0W 0x02FE– 0x02FF Reserved R 00000000 W 0x0300– 0x032F Reserved R 00000000 W 0x0330 Reserved R 00000000 W 0x0331 PTIL R 00000 P T I L 2 P T I L 1 P T I L 0 W 0x0332 Reserved R 00000000 W 0x0333 PTPSL R 00000 PTPSL2 PTPSL1 PTPSL0W 0x0334 PPSL R 00000 PPSL2 PPSL1 PPSL0W 0x0335 Reserved R 00000000 W 0x0336 PIEL R 00000 PIEL2 PIEL1 PIEL0W Global Address Register Name B i t 7 654321 B i t 0
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2.3.2 PIM Regis ters 0x0200-0x020F
This section describes registers implemented in address range 0x0200-0x020F. These registers serve for specific PIM related functions not part of the generic port registers.
- If not stated differently, writing to reserv ed bits has no effect and read returns zero.
- All register read accesses are synchronous to internal clocks.
- Register bits can be written at a ny time if not stated differently. 0x0337 PIFL R 00000 PIFL2 PIFL1 PIFL0W 0x0338– 0x0339 Reserved R 00000000 W 0x033A PTABYPL R 00000 PTABYPL2 PTABYPL1 PTABYPL0W 0x033B PTADIRL R 00000 PTADIRL2 PTADIRL1 PTADIRL0W 0x033C DIENL R 00000 DIENL2 DIENL1 DIENL0W 0x033D PTAENL R 00000 PTAENL2 PTAENL1 PTAENL0W 0x033E PIRL R 00000 PIRL2 PIRL1 PIRL0W 0x033F PTTEL R 00000 PTTEL2 PTTEL1 PTTEL0W 0x0340– 0x037F Reserved R 00000000 W Global Address Register Name B i t 7 654321 B i t 0
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2.3.2.1 Module Routing Register 0 (MODRR0)
Address 0x0200 Access: User read(1) 1. Read: Anytime Write: Once in normal, anytime in special mode 76543210 R0 0 Reserved SCI1RR S0L0RR2-0 W Routing Option — — — — SCI1 SCI0-LINPHY0 interface R e s e t 00000000 Figure 2-1. Module Routing Register 0 (MODRR0) Table 2-10. MODRR0 Routing Register Field Descriptions Field Description SCI1RR Module Routing Register — SCI1 routing
1 TXD1 on PE1; RXD1 on PE0
0 TXD1 on PT1; RXD1 on PT0
Module Routing Register — SCI0-LINPHY0 routing Selection of SCI0-LINPHY0 interface routing options to support probing and conformance testing. Refer to Figure 2-2 for an illustration and Table 2-11 for preferred settings. Note: SCI0 must be enabled for TXD0 routing to take effect on pin. LINPHY0 must be enabled for LPRXD0 and LPDR[LPDR1] routings to take effect on pins.
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Figure 2-2. SCI0-to-LINPHY0 Routing Options Illustration NOTE For standalone usage of SCI0 on external pins set S0L0RR[2:0]=0b110 and disable LINPHY0 (LPCR[LPE]=0). This releases the LINPHY0 associated pins to other shared functions. Table 2-11. Preferred Interface Configurations S0L0RR[2:0] Description
000 Default setting:
SCI0 connects to LINPHY0, interface internal only
001 Direct control setting:
LP0DR[LPDR1] register bit controls LPTXD0, interface internal only
100 Probe setting:
SCI0 connects to LINPHY0, interface accessible on 2 external pins
110 Conformance test setting:
Interface opened and all 4 signals routed externally LPRXD0 LPTXD0 TXD0 / LPDR1 RXD0 TIM0 input capture channel 3 S0L0RR2S0L0RR1S0L0RR0 SCI0 LINPHY0 TXD0 RXD0 LPTXD0 LPRXD0 LPDR1 LIN
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2.3.2.2 Module Routing Register 1 (MODRR1)
2.3.2.3 Module Routing Register 2 (MODRR2)
Address 0x0201 Access: User read/write(1) 1. Read: Anytime Write: Anytime 76543210 R 000000 TRIG0RR2-0 W R e s e t 00000000 Figure 2-3. Module Routing Register 1 (MODRR1) Table 2-12. MODRR1 Routing Register Field Descriptions Field Description 1-0 TRIG0RR 1-0 Module Routing Register — ADC0 trigger source
11 Reserved
10 TIM0 output compare channel 2 connected to ADC0 trigger input(1)
01 PMF reload connected to ADC0 trigger input
00 PTU trigger 0 connected to ADC0 trigger input
- Output compare function on pin remains active unless disabled in timer config register TIM0OCPD[OCPD2]=1 Address 0x0202 Access: User read/write(1) 1. Read: Anytime Write: Never 76543210 R 00000000 W R e s e t 00000000 Figure 2-4. Module Routing Register 2 (MODRR2)
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2.3.2.4 Module Routing Register 3 (MODRR3)
2.3.2.5 Module Routing Register 4 (MODRR4)
Address 0x0203 Access: User read/write(1) 1. Read: Anytime Write: Anytime 76543210 R 000 T0IC3RR1-0 T0IC2RR W R e s e t 00000000 Figure 2-5. Module Routing Register 3 (MODRR3) Table 2-13. MODRR3 Routing Register Field Descriptions Field Description 4-3 T0IC3RR1 Module Routing Register — IC0_3 routing If timer channel is not used with a pin (T0IC3RR0=1) then one out of two internal sources can be selected as input.
11 TIM0 input capture channel 3 connected to RXD1
10 Reserved
01 TIM0 input capture channel 3 connected to RXD0
00 TIM0 input capture channel 3 connected to PT3
Module Routing Register — IC0_2 routing
1 TIM0 input capture channel 2 connected to ACLK
0 TIM0 input capture channel 2 connected to PT2
Address 0x0204 Access: User read (1) 1. Read: Anytime Write: Once in normal, anytime in special mode 76543210 R FAULT5RR P0C5RR P0C4RR P0C3RR P0C2RR P0C1RR P0C0RR W Routing Option FAULT5 — PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 R e s e t 00000000 Figure 2-6. Module Routing Register 4 (MODRR4)
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2.3.2.6 Module Routing Register 5 (MODRR5)
Table 2-14. MODRR4 Routing Register Field Descriptions Field Description FAULT5RR Module Routing Register — FAULT5 routing
1 FAULT5 connected to PT2
0 FAULT5 connected to PP1
Module Routing Register — PWM5 routing
1 PWM5 connected to HS1
0 PWM5 connected to PP1
Module Routing Register — PWM4 routing
1 PWM4 connected to HS0
0 PWM4 connected to PP0
Module Routing Register — PWM3/GDU probe routing
1 PWM3/GDU signal visible at PT2
0 PWM3/GDU internal only
Module Routing Register — PWM2/GDU probe routing
1 PWM2/GDU signal visible at PT1
0 PWM2/GDU internal only
Module Routing Register — PWM1/GDU probe routing
1 PWM1/GDU signal visible at PE1
0 PWM1/GDU internal only
Module Routing Register — PWM0/GDU probe routing
1 PWM0/GDU signal visible at PE0
0 PWM0/GDU internal only
Address 0x0205 Access: User read/write (1) 1. Read: Anytime Write: Once in normal, anytime in special mode 76543210 R T1IC3RR T1IC2RR T1IC1RR T1IC0RR T1OC2RR T1OC1RR W R e s e t 00000000 Figure 2-7. Module Routing Register 1 (MODRR5)
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Table 2-15. MODRR5 Routing Register Field Descriptions Field Description T1IC3RR Module Routing Register — IC1_3 routing
1 TIM1 input capture channel 3 connected to GDU dead time measurement feature
0 TIM1 input capture channel 3 connected to PT7
Module Routing Register — IC1_2 routing
1 TIM1 input capture channel 2 connected to HVI2
0 TIM1 input capture channel 2 connected to PT6
Module Routing Register — IC1_1 routing
1 TIM1 input capture channel 1 connected to HVI1
0 TIM1 input capture channel 1 connected to PT5
Module Routing Register — IC1_0 routing
1 TIM1 input capture channel 0 connected to HVI0
0 TIM1 input capture channel 0 connected to PT4
Module Routing Register — OC1_2 routing
1 TIM1 output compare channel 2 connected to HS1
0 TIM1 output compare channel 2 connected to PT6
Module Routing Register — OC1_1 routing
1 TIM1 output compare channel 1 connected to HS0
0 TIM1 output compare channel 1 connected to PT5
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2.3.2.7 ECLK Control Register (ECLKCTL)
2.3.2.8 IRQ Control Register (IRQCR)
Address 0x0208 Access: User read/write(1) 1. Read: Anytime Write: Anytime 76543210 R NECLK 0000000 W R e s e t : 10000000 Figure 2-8. ECLK Control Register (ECLKCTL) Table 2-16. ECLKCTL Register Field Descriptions Field Description NECLK No ECLK — Disable ECLK output This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate equivalent to the internal bus clock.
1 ECLK disabled
0 ECLK enabled
Address 0x0209 Access: User read/write (1) 1. Read: Anytime Write: IRQE: Once in normal mode, anytime in special mode IRQEN: Anytime 76543210 R IRQE IRQEN 000000 W R e s e t 00000000 Figure 2-9. IRQ Control Register (IRQCR) Table 2-17. IRQCR Register Field Descriptions Field Description IRQE IRQ select edge sensitive only — 1 IRQ pin configured to respond only to falling edges. Falling edges on the IRQ pin are detected anytime when IRQE=1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.
0 IRQ configured for low level recognition
IRQ enable —
1 IRQ pin is connected to interrupt logic
0 IRQ pin is disconnected from interrupt logic
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2.3.2.9 Reserved Register
2.3.2.10 Reserved Register
Address 0x020D Access: User read/write(1) 1. Read: Anytime Write: Only in special mode. This reserved register is designed for factory test purposes only and is not intended for general user access. Writing to this register when in special modes can alter the modules functionality. 76543210 R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W R e s e t xxxxxxxx Figure 2-10. Reserved Register Address 0x020E Access: User read/write(1) 1. Read: Anytime Write: Only in special mode This reserved register is designed for factory test purposes only and is not intended for general user access. Writing to this register when in special modes can alter the modules functionality. 76543210 R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W R e s e t xxxxxxxx Figure 2-11. Reserved Register
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2.3.2.11 Reserved Register
This reserved register is designed for factory test purposes only and is not intended for general user access. Writing to this register when in special modes can alter the modules functionality.
2.3.3 PIM Generic Registers
This section describes the details of all PIM registers.
- Writing to reserved bits has no effect and read returns zero.
- All register read accesses are synchronous to internal clocks.
- All registers can be wr itten at any time, however a specific configuration might not become active. E.g. a pullup device does not become active while the port is used as a push-pull output.
- General-purpose data output avai lability depends on prioritization; input data registers always reflect the pin status independent of the use.
- Pull-device availabili ty, pull-device polarity, wired-or mode, key-wake up functionality are independent of the prioritization unless noted differently.
- For availability of individual bits refer to Section 2.3.1, “Register Map” and Table 2-44. NOTE This is a generic description of the standard PIM registers. Refer to Table 2- 44 to determine the implemented bits in the respective register. Address 0x020F Access: User read/write(1) 1. Read: Anytime Write: Only in special mode 76543210 R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W R e s e t xxxxxxxx Figure 2-12. Reserved Register
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2.3.3.1 Port Data Register
2.3.3.2 Port Input Register
Access: User read/write (1) 1. Read: Anytime. The data source is depending on the data direction value. Write: Anytime 76543210 R PTx7 PTx6 PTx5 PTx4 PTx3 PTx2 PTx1 PTx0 W R e s e t 00000000 Figure 2-13. Port Data Register Table 2-18. Port Data Register Field Descriptions Field Description 7-0 PTx7-0 Port Data — General purpose input/output data This register holds the value driven out to the pin if the pin is used as a general purpose output. When not used with the alternative function (refer to Table 2-8), these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Address 0x0262 PTIE 0x0282 PTIADH 0x0283 PTIADL 0x02C1 PTIT 0x02F1 PTIP 0x0331 PTIL Access: User read only (1) 1. Read: Anytime Write:Never 76543210 R PTIx7 PTIx6 PTIx5 PTIx4 PTIx3 PTIx2 PTIx1 PTIx0 W R e s e t 00000000 Figure 2-14. Port Input Register Table 2-19. Port Input Register Field Descriptions Field Description 7-0 PTIx7-0 Port Input — Data input A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins.
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2.3.3.3 Data Direction Register
2.3.3.4 Pull Device Enable Register
Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R DDRx7 DDRx6 DDRx5 DDRx4 DDRx3 DDRx2 DDRx1 DDRx0 W R e s e t 00000000 Figure 2-15. Data Direction Register Table 2-20. Data Direction Register Field Descriptions Field Description 7-0 DDRx7-0 Data Direction — Select general-purpose data direction This bit determines whether the pin is a general-purpose input or output. If a peripheral module controls the pin the content of the data direction register is ignored. Independent of the pin usage with a peripheral module this register determines the source of data when reading the associated data register address. Note: Due to internal synchronization circuits, it can take up to two bus clock cycles until the correct value is read on port data and port input registers, when changing the data direction register.
1 Associated pin is configured as output
0 Associated pin is configured as input
Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R PERx7 PERx6 PERx5 PERx4 PERx3 PERx2 PERx1 PERx0 W Reset P o r t s E : 00000011 O t h e r s : 00000000 Figure 2-16. Pull Device Enable Register
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2.3.3.5 Polarity Select Register
2.3.3.6 Port Interrupt Enable Register
Table 2-21. Pull Device Enable Register Field Descriptions Field Description 7-0 PERx7-0 Pull Enable — Activate pull device on input pin This bit controls whether a pull device on the associated port input or open-drain output pin is active. If a pin is used as push-pull output this bit has no effect. The polarity is selected by the related polarity select register bit. On open- drain output pins only a pullup device can be enabled.
1 Pull device enabled
0 Pull device disabled
Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R PPSx7 PPSx6 PPSx5 PPSx4 PPSx3 PPSx2 PPSx1 PPSx0 W Reset P o r t s E : 00000011 O t h e r s : 00000000 Figure 2-17. Polarity Select Register Table 2-22. Polarity Select Register Field Descriptions Field Description 7-0 PPSx7-0 Pull Polarity Select — Configure pull device and pin interrupt edge polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin. If a port has interrupt functionality this bit also selects the polarity of the active edge.
1 Pulldown device selected; rising edge selected
0 Pullup device selected; falling edge selected
Access: User read/write (1) 76543210 R PIEx7 PIEx6 PIEx5 PIEx4 PIEx3 PIEx2 PIEx1 PIEx0 W R e s e t 00000000 Figure 2-18. Port Interrupt Enable Register
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2.3.3.7 Port Interrupt Flag Register
- Read: Anytime Write: Anytime Table 2-23. Port Interrupt Enable Register Field Descriptions Field Description 7-0 PIEx7-0 Port Interrupt Enable — Activate pin interrupt (KWU) This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if the pin is operating in input or output mode when in use with the general-purpose or related peripheral function.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
Access: User read/write (1) 1. Read: Anytime Write: Anytime, write 1 to clear 76543210 R PIFx7 PIFx6 PIFx5 PIFx4 PIFx3 PIFx2 PIFx1 PIFx0 W R e s e t 00000000 Figure 2-19. Port Interrupt Flag Register Table 2-24. Port Interrupt Flag Register Field Descriptions Field Description 7-0 PIFx7-0 Port Interrupt Flag — Signal pin event (KWU) This flag asserts after a valid active edge was detected on the related pin (see Section 2.4.5.2, “Pin Interrupts and Key-Wakeup (KWU)”). This can be a rising or a falling edge based on the state of the polarity select register. An interrupt will occur if the associated interrupt enable bit is set. Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred
0 No active edge occurred
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2.3.3.8 Digital Input Enable Register
2.3.3.9 Reduced Drive Register
Access: User read/write(1) 1. Read: Anytime Write: Anytime 76543210 R DIENx7 DIENx6 DIENx5 DIENx4 DIENx3 DIENx2 DIENx1 DIENx0 W R e s e t 00000000 Figure 2-20. Digital Input Enable Register Table 2-25. Digital Input Enable Register Field Descriptions Field Description 7-0 DIENx7-0 Digital Input Enable — Input buffer control This bit controls the digital input function. If set to 1 the input buffers are enabled and the pin can be used with the digital function. If a peripheral module is enabled which uses the pin with a digital function, the input buffer is activated and the register bit is ignored. If the pin is used with an analog function this bit shall be cleared to avoid shoot-through current.
1 Associated pin is configured as digital input
0 Associated pin digital input is disabled
Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R RDRx7 RDRx6 RDRx5 RDRx4 RDRx3 RDRx2 RDRx1 RDRx0 W R e s e t 00000000 Figure 2-21. Reduced Drive Register Table 2-26. Reduced Drive Register Field Descriptions Field Description 7-0 RDRx7-0 Reduced Drive Register — Select reduced drive for output pin This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin. 1 Reduced drive selected (approx. 1/10 of the full drive strength)
0 Full drive strength enabled
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2.3.3.10 PIM Reserved Register
2.3.4 PIM Generic Register Exceptions
This section lists registers with deviations from the generic description in one or more register bits.
2.3.4.1 Port T Polarity Select Register (PPST)
Address (any reserved) Access: User read(1) 1. Read: Always reads 0x00 Write: Unimplemented 76543210 R 00000000 W R e s e t 00000000 Figure 2-22. PIM Reserved Register Address 0x02C4 PPST Access: User read/write(1) 1. Read: Anytime Write: Anytime 76543210 R PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 W R e s e t 00000000 Figure 2-23. Port T Polarity Select Register (PPST) Table 2-27. Port T Polarity Select Register Field Descriptions Field Description 7-3 PPST7-3 See Section 2.3.3.5, “Polarity Select Register”. PPST2 Pull Polarity Select — Configure pull device and pin interrupt edge polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin. If a port has interrupt functionality this bit also selects the polarity of the active edge. This bit selects whether a high or a low level on FAULT5 generates a fault event in PMF, if FAULT5RR is set.
1 Pulldown device selected; rising edge selected; active-high level selected on FAULT5 input
0 Pullup device selected; falling edge selected; active-low level selected on FAULT5 input
See Section 2.3.3.5, “Polarity Select Register”.
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2.3.4.2 Port T Over-Current Protect ion Enable Register (OCPET)
2.3.4.3 Port T Over-Current Inte rrupt Enable Register (OCIET)
Address 0x02C9 Access: User read/write(1) 1. Read: Anytime Write:Anytime 76543210 R 00000 OCPET2 W R e s e t 00000000 Figure 2-24. Over-Current Protection Enable Register (OCPET) Table 2-28. OCPET Register Field Descriptions Field Description OCPET2 Over-Current Protection Enable — Activate over-current detector on PT2 Refer to Section 2.5.3, “Over-Current Protection on PP0 (EVDD)”
1 PT2 over-current detector enabled
0 PT2 over-current detector disabled
Address 0x02CA Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R 00000 OCIET2 W R e s e t 00000000 Figure 2-25. Port T Over-Current Interrupt Enable Register Table 2-29. OCIET Register Field Descriptions Field Description OCIET2 Over-Current Interrupt Enable — This bit enables or disables the over-current interrupt on PT2.
1 PT2 over-current interrupt enabled
0 PT2 over-current interrupt disabled (interrupt flag masked)
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2.3.4.4 Port T Over-Current Inte rrupt Flag Register (OCIFT)
2.3.4.5 Port P Polarity Select Register (PPSP)
Address 0x02CB Access: User read/write(1) 1. Read: Anytime Write: Anytime, write 1 to clear 76543210 R 00000 OCIFT2 W R e s e t 00000000 Figure 2-26. Port T Over-Current Interrupt Flag Register (OCIFT) Table 2-30. OCIFT Register Field Descriptions Field Description OCIFT2 Over-Current Interrupt Flag — This flag asserts if an over-current condition is detected on PT2 (Section 2.4.5.3, “Over-Current Interrupt and Protection”). Writing a logic “1” to the corresponding bit field clears the flag.
1 PT2 over-current event occurred
0 No PT2 over-current event occurred
Address 0x02F4 Access: User read/write(1) 1. Read: Anytime Write: Anytime 76543210 R 000000 PPSP1 PPSP0 W R e s e t 00000000 Figure 2-27. Port P Polarity Select Register (PPSP) Table 2-31. Port P Polarity Select Register Field Descriptions Field Description PPSP1 Pull Polarity Select — Configure pull device and pin interrupt edge polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin. If a port has interrupt functionality this bit also selects the polarity of the active edge. This bit selects whether a high or a low level on FAULT5 generates a fault event in PMF, if FAULT5RR is cleared See Section 2.3.3.5, “Polarity Select Register”.
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2.3.4.6 Port P Over-Current Protect ion Enable Register (OCPEP)
2.3.4.7 Port P Over-Current Inte rrupt Enable Register (OCIEP)
Address 0x02F9 Access: User read/write(1) 1. Read: Anytime Write:Anytime 76543210 R 0000000 OCPEP0 W R e s e t 00000000 Figure 2-28. Over-Current Protection Enable Register (OCPEP) Table 2-32. OCPEP Register Field Descriptions Field Description OCPEP0 Over-Current Protection Enable — Activate over-current detector on PP0 Refer to Section 2.5.4, “Over-Current Protection on PT2”
1 PP0 over-current detector enabled
0 PP0 over-current detector disabled
Address 0x02FA Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R 0000000 OCIEP0 W R e s e t 00000000 Figure 2-29. Port P Over-Current Interrupt Enable Register Table 2-33. OCIEP Register Field Descriptions Field Description OCIEP0 Over-Current Interrupt Enable — This bit enables or disables the over-current interrupt on PP0.
1 PP0 over-current interrupt enabled
0 PP0 over-current interrupt disabled (interrupt flag masked)
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2.3.4.8 Port P Over-Current Inte rrupt Flag Register (OCIFP)
Address 0x02FB Access: User read/write(1) 1. Read: Anytime Write: Anytime, write 1 to clear 76543210 R 0000000 OCIFP0 W R e s e t 00000000 Figure 2-30. Port P Over-Current Interrupt Flag Register Table 2-34. OCIFP Register Field Descriptions Field Description OCIFP0 Over-Current Interrupt Flag — This flag asserts if an over-current condition is detected on PP0 (Section 2.4.5.3, “Over-Current Interrupt and Protection”). Writing a logic “1” to the corresponding bit field clears the flag.
1 PP0 over-current event occurred
0 No PP0 over-current event occurred
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2.3.4.9 Port L Input Register (PTIL)
2.3.4.10 Port L Pull Select Register (PTPSL)
Address 0x0331 Access: User read only(1) 1. Read: Anytime Write: Never 76543210 R 00000 P T I L 2 P T I L 1 P T I L 0 W R e s e t 00000000 Figure 2-31. Port L Input Register (PTIL) Table 2-35. PTIL Register Field Descriptions Field Description 2-0 PTIL2-0 Port Input Data Register Port L — A read returns the synchronized input state if the associated HVI pin is used in digital mode, that is the related DIENL bit is set to 1 and the pin is not used in analog mode (PTAENL=0). See Section 2.3.4.15, “Port L ADC Connection Enable Register (PTAENL)”. A one is read in any other case(1). Address 0x0333 Access: User read/write(1) 1. Read: Anytime Write: Anytime 76543210 R 0 0 0 0 0 PTPSL2 PTPSL1 PTPSL0 W R e s e t 00000000 Figure 2-32. Port L Pull Select Register (PTPSL) Table 2-36. PTPSL Register Field Descriptions Field Description 2-0 PTPSL2-0 Port L Pull Select — This bit selects a pull device on the HVI pin in analog mode for open input detection. By default a pulldown device is active as part of the input voltage divider. If this bit set to 1 and PTTEL=1 and not in stop mode a pullup to a level close to VDDX takes effect and overrides the weak pulldown device. Refer to Section 2.5.5, “Open Input Detection on PL[2:0] (HVI)”).
1 Pullup enabled
0 Pulldown enabled
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2.3.4.11 Port L Polarity Select Register (PPSL)
2.3.4.12 Port L ADC Bypass Register (PTABYPL)
Address 0x0334 PPSL Access: User read/write(1) 1. Read: Anytime Write: Anytime 76543210 R 0 0 0 0 0 PPSL2 PPSL1 PPSL0 W R e s e t 00000000 Figure 2-33. Port L Polarity Select Register (PPSL) Table 2-37. PPSL Register Field Descriptions Field Description 2-0 PPSL2-0 Polarity Select — This bit selects the polarity of the active interrupt edge on the associated HVI pin.
1 Rising edge selected
0 Falling edge selected
Address 0x033A Access: User read/write(1) 1. Read: Anytime Write: Anytime 76543210 R 0 0 0 0 0 PTABYPL2 PTABYPL1 PTABYPL0 W R e s e t 00000000 Figure 2-34. Port L ADC Bypass Register (PTBYPL) Table 2-38. PTABYPL Register Field Descriptions Field Description 2-0 PTABYPL 2-0 Port L ADC Connection Bypass — This bit bypasses and powers down the impedance converter stage in the signal path from the analog input pin to the ADC channel input. This bit takes effect only if using direct input connection to the ADC channel (PTADIRL=1).
1 Impedance converter bypassed
0 Impedance converter used
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2.3.4.13 Port L ADC Direct Register (PTADIRL)
2.3.4.14 Port L Digital Input Enable Register (DIENL)
Address 0x033B Access: User read/write(1) 1. Read: Anytime Write: Anytime 76543210 R 0 0 0 0 0 PTADIRL2 PTADIRL1 PTADIRL0 W R e s e t 00000000 Figure 2-35. Port L ADC Direct Register (PTADIRL) Table 2-39. PTADIRL Register Field Descriptions Field Description 2-0 PTADIRL 2-0 Port L ADC Direct Connection — This bit connects the analog input signal directly to the ADC channel bypassing the voltage divider. This bit takes effect only in analog mode (PTAENL=1).
1 Input pin directly connected to ADC channel
0 Input voltage divider active on analog input to ADC channel
Address 0x33C Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R 00000 DIENL2 DIENL1 DIENL0 W R e s e t 00000000 Figure 2-36. Port L Digital Input Enable Register (DIENL) Table 2-40. DIENL Register Field Descriptions Field Description 2-0 DIENL2-0 Digital Input Enable Port L — Input buffer control This bit controls the HVI digital input function. If set to 1 the input buffer is enabled and the HVI pin can be used with the digital function. If the analog input function is enabled (PTAENL=1) the input buffer of the selected HVI pin is forced off(1) in run mode and is released to be active in stop mode(2) only if DIENL=1.
1 Associated pin digital input is enabled if not used as analog input in run mode1
0 Associated pin digital input is disabled1
- “Stop mode” is limited to RPM; refer to Table 2-47.
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2.3.4.15 Port L ADC Connectio n Enable Register (PTAENL)
2.3.4.16 Port L Input Divider Ra tio Selection Register (PIRL)
Address 0x033D Access: User read/write(1) 1. Read: Anytime Write: Anytime 76543210 R 0 0 0 0 0 PTAENL2 PTAENL1 PTAENL0 W R e s e t 00000000 Figure 2-37. Port L ADC Connection Enable Register (PTAENL) Table 2-41. PTAENL Register Field Descriptions Field Description 2-0 PTAENL 2-0 Port L ADC Connection Enable — This bit enables the analog signal link to an ADC channel. If set to 1 the analog input function takes precedence over the digital input in run mode by forcing off the input buffer if not overridden by PTTEL=1. Note: When enabling the resistor paths to ground by setting PTAENL=1, a delay of tUNC_HVI + two bus cycles must be accounted for.
1 ADC connection enabled
0 ADC connection disabled
Address 0x033E Access: User read/write(1) 1. Read: Anytime Write: Anytime 76543210 R 00000 PIRL2 PIRL1 PIRL0 W R e s e t 00000000 Figure 2-38. Port L Input Divider Ratio Selection Register (PIRL) Table 2-42. PIRL Register Field Descriptions Field Description 2-0 PIRL2-0 Port L Input Divider Ratio Select — This bit selects one of two voltage divider ratios for the associated HVI pin in analog mode. 1R a t i oL_HVI selected 0R a t i oH_HVI selected
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2.3.4.17 Port L Test Enable Register (PTTEL)
2.4 Functional Description
2.4.1 General
Each pin except BKGD and HVI can act as general-purpose I/O. In addition each pin can act as an output or input of a peripheral module.
2.4.2 Registers
Table 2-44 lists the implemented configuration bits which are available on each port. These registers except the pin input registers can be written at any time, however a specific configuration might not become active. For example a pullup device does not become active while the port is used as a push-pull output. Unimplemented bits read zero. Address 0x033F Access: User read/write(1) 1. Read: Anytime Write: Anytime 76543210 R 00000 PTTEL2 PTTEL1 PTTEL0 W R e s e t 00000000 Figure 2-39. Port L Test Enable Register (PTTEL) Table 2-43. PTTEL Register Field Descriptions Field Description 2-0 PTTEL2-0 Port L Test Enable — This bit forces the input buffer of the HVI pin active while using the analog function to support open input detection Note: In direct mode (PTADIRL=1) the digital input buffer is not enabled.
1 Input buffer enabled when used with analog function and not in direct mode (PTADIRL=0)
0 Input buffer disabled when used with analog function
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2.4.3 Pin I/O Control
Figure 1-38Figure 2-40 illustrates the data paths to and from an I/O pin. Input and output data can always be read via the input register (PTIx, Section 2.3.3.2, “Port Input Register”) independent if the pin is used as general-purpose I/O or with a shared peripheral function. If the pin is configured as input (DDRx=0, Section 2.3.3.3, “Data Direction Register”), the pin state can also be read through the data register (PTx, Section 2.3.3.1, “Port Data Register”). Figure 2-40. Illustration of I/O pin functionality The general-purpose data direction configuration can be overruled by an enabled peripheral function shared on the same pin (Table 2-45). If more than one peripheral function is available and enabled at the Table 2-44. Bit Indices of Implemented Register Bits per Port Port Data Register Port Input Register Data Direction Register Pull Device Enable Register Polarity Select Register Port Interrupt Enable Register Port Interrupt Flag Register Digital Input Enable Register Reduced Drive Register Wired-Or Mode Register Port PT PTI DDR PER PPS PIE PIF DIE RDR WOM A D H 00000000 — — PTx DDRx output enable port enable Pin data out Periph. data in Module synch.PTIx
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same time, the highest ranked module according the predefined priority scheme (see Table 2-2 to Table 2- 8) will take precedence on the pin.
2.4.4 Pull Devices
Every I/O pin provides an individually selectable pullup and pulldown device to avoid current consumption caused by floating inputs. A pull device is enabled with pull enable register bits PERx (Section 2.3.3.4, “Pull Device Enable Register”; 0=disabled; 1=enabled) and the pull direction is selected with port polarity select register bits PPSx (Section 2.3.3.5, “Polarity Select Register”; 0=pullup, 1=pulldown). The reset states are given at the individual register descriptions. If a pin is used as an output either by setting the data direction bit (DDRx=1) or by an enabled peripheral feature the pull devices are disabled in order to avoid increased current consumption. If a pin is used as open-drain output (WOMx=1) then the pulldown device is disabled.
2.4.5 Interrupts
This section describes the interrupts generated by the PIM and their individual sources. Vector addresses and interrupt priorities are defined at MCU level. Table 2-45. Effect of Enabled Features Enabled Feature(1) 1. If applicable the appropriate routing configuration must be set for the signals to take effect on the pins. Related Signal(s) Effect on I/O state CPMU OSC EXTAL, XTAL CPMU takes control TIMx output compare y IOCx_y Forced output TIMx input capture y IOCx_y None (2) 2. DDR maintains control SPIx MISOx, MOSIx, SCKx, SSx SPI takes control SCIx TXDx SCI takes control RXDx Forced input PMF channel X PWMX Forced output PMF fault input FAULT5 Forced input PTU PTURE, PTUT0 Forced output ADCx ANx None 2 (3) 3. To use the digital input function the related bit in Digital Input Enable Register (DIENADH/L) must be set to logic level “1”. AMP AMP , AMPP, AMPM None 2 3 IRQ IRQ Forced input XIRQ XIRQ Forced input LINPHY LP0TXD Forced input LP0RXD Forced output LP0DR1 Forced output DBG DBGEEV none
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2.4.5.1 XIRQ, IRQ Interrupts
The XIRQ pin allows requesting non-maskable interrupts after reset initialization.During reset, the X bit in the condition code register is set and any interrupts are masked until software enables them. The IRQ pin allows requesting asynchronous interrupts. The interrupt input is disabled out of reset. To enable the interrupt the IRQCR[IRQEN] bit must be set and the I bit cleared in the condition code register. The interrupt can be configured for level-sensitive or falling-edge-sensitive triggering. If IRQCR[IRQEN] is cleared while an interrupt is pending, the request will deassert. Both interrupts are able to wake-up the device from stop mode. Means for glitch filtering are not provided on these pins.
2.4.5.2 Pin Interrupts and Key-Wakeup (KWU)
Ports AD, P and L offer pin interrupt and key-wakeup capability. The related interrupt enable (PIE) as well as the sensitivity to rising or falling edges (PPS) can be individually configured on per-pin basis. All bits/pins in a port share the same interrupt vector. Interrupts can be used with the pins configured as inputs or outputs. An interrupt is generated when a bit in the port interrupt flag (PIF) and its corresponding port interrupt enable (PIE) are both set. The pin interrupt feature is also capable to wake up the CPU when it is in stop or wait mode (key-wakeup). A digital filter on each pin prevents short pulses from generating an interrupt. A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level. Else the sampling logic is restarted. In run and wait mode the filters are continuously clocked by the bus clock. Pulses with a duration of tPULSE <n P_MASK/fbus are assuredly filtered out while pulses with a duration of tPULSE >n P_PASS/fbus guarantee a pin interrupt. In stop mode the filter clock is generated by an RC-oscillator.The minimum pulse length varies over process conditions, temperature and voltage (Figure 2-41). Pulses with a duration of tPULSE <t P_MASK are assuredly filtered out while pulses with a duration of tPULSE >t P_PASS guarantee a wakeup event. Please refer to the appendix table “Pin Timing Characteristics” for pulse length limits. Table 2-46. PIM Interrupt Sources Module Interrupt Sources Local Enable XIRQ None IRQ IRQCR[IRQEN] Port AD pin interrupt PIEADH[PIEADH] PIEADL[PIEADL] Port P pin interrupt PIEP[PIEP] Port L pin interrupt PIEL[PIEL] Port T over-current interrupt OCIET[OCIET] Port P over-current interrupt OCIEP[OCIEP]
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To maximize current saving the RC oscillator is active only if the following condition is true on any individual pin: Sample count <= 4 (at active or passive level) and interrupt flag not set (PIF[x]=0). Figure 2-41. Interrupt Glitch Filter (here: active low level selected)
2.4.5.3 Over-Current Interrupt and Protection
In case of an over-current condition on high-current capable outputs (see Section 2.5.3, “Over-Current Protection on PP0 (EVDD)” and 2.5.4, “Over-Current Protection on PT2”) the related over-current interrupt flag OCIF[OCIF] asserts. This flag generates an interrupt if the related enable bit OCIE[OCIE] is set. An asserted flag immediately forces the related output independent of its driving source (such as for example TIM output, PWM or port register bit) to its disabled level to protect the device. The flag must be cleared to re-enable the driver.
2.4.6 High-Voltage Input
A high-voltage input (HVI) on port L has the following features:
- Input voltage level up to V HVI
- Digital input function with pin inte rrupt and wakeup from stop capability
- Analog input function with selectab le divider ratio routable to ADC channels. Optional direct input bypassing voltage divider and impedance converter. Capable to wakeup from stop (pin interrupts in run mode not available). Open input detection. Figure 2-42 shows a block diagram of the HVI. NOTE The term stop mode (STOP) is limited to voltage regulator operating in reduced performance mode (RPM). Refer to “Low Power Modes” section in device overview. Glitch, filtered out, no interrupt flag set Valid pulse, interrupt flag set uncertain tP_MASK tP_PASS
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2.4.6.1 Digital Mode Operation
In digital mode (PTAENL=0) the input buffer is enabled if DIENL=1. The synchronized pin input state determined at threshold level VTH_HVI can be read in register PTIL. An interrupt flag (PIFL) is set on input transitions if enabled (PIEL=1) and configured for the related edge polarity (PPSL). Wakeup from stop mode is supported.
2.4.6.2 Analog Mode Operation
In analog mode (PTAENL=1) the input buffer is forced off (except if HVI test enabled and not in direct mode: PTTEL=1 & PTADIRL=0) and the voltage applied to a selectable HVI pin can be measured on its related ADC channel (refer to device overview section for channel assignment). One of two input divider PL (HVI) PTIL PIRL ADC REXT_HVI PTAENL VHVI (DIENL & (PTAENL | STOP)) Input Buffer Impedance Converter PTAENL & STOP & PTADIRL PTAENL & STOP & PTADIRL VDDX & STOP PTAENL | (PTAENL & PTADIRL & PTTEL & STOP) 140K 400K 110K 440K PTAENL & PTTEL & PTPSL & PTADIRL & PTABYPL 10K & PTADIRL & STOP
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ratios (RatioH_HVI, RatioL_HVI) can be chosen (PIRL) on the analog input or the voltage divider can be bypassed (PTADIRL=1). Additionally in latter case the impedance converter in the ADC signal path can be used or bypassed in direct input mode (PTABYPL). In run mode the digital input buffer of the selected pin is disabled to avoid shoot-through current (unless PTTEL is set and the voltage divider is not bypassed). Thus pin interrupts cannot be generated. In stop mode (RPM) the digital input buffer is enabled only if DIENL=1 to support wakeup functionality. Table 2-47 shows the HVI input configuration depending on register bits and operation mode. NOTE An external resistor REXT_HVI must always be connected to the high- voltage input to protect the device pins from fast transients and to achieve the specified pin input divider ratios when using the HVI in analog mode.
2.5 Initialization and Application Information
2.5.1 Port Data and Data Direction Register writes
It is not recommended to write PORTx/PTx and DDRx in a word access. When changing the register pins from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data register before enabling the outputs.
2.5.2 SCI Baud Rate Detection
The baud rate for SCI0 and SCI1 can be determined by using a timer channel to measure the data rate on the related RXD signal. 1. Establish the link: Table 2-47. HVI Input Configurations Mode DIENL PTAENL Digital Input Analog Input Resulting Function Run 0 0 off off Input disabled (Reset) 01 o f f 1 enabled Analog input, interrupt not supported 1 0 enabled off Digital input, interrupt supported 11 o f f (1) 1. Enabled if PTTEL=1 & PTADIRL=0) enabled Analog input, interrupt not supported Stop(2) 2. The term “stop mode” is limited to voltage regulator operating in reduced performance mode (RPM; refer to “Low Power Modes” section in device overview). In any other case the HVI input configuration defaults to “run mode”. Therefore set PTAENL=0 before entering stop mode in order to generally support wakeup from stop. 0 0 off off Input disabled, wakeup from stop not supported01 o f f o f f 1 0 enabled off Digital input, wakeup from stop supported 1 1 enabled off
Chapter 2 Port Integration Module (S12ZVMBPIMV3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 113 — For SCI0: Set MODRR3[T0IC3RR1:T0IC3RR0]= 2b01 to route TIM0 input capture channel 3 to internal RXD0 signal of SCI0. — For SCI1: Set MODRR3[T0IC3RR1 :T0IC3RR0]=2b11 to route TIM0 input capture channel 3 to internal RXD1 signal of SCI1. 2. Determine pulse width of incomi ng data: Configure TIM0 input capture channel 3 to measure time between incoming signal edges.
2.5.3 Over-Current Protection on PP0 (EVDD)
Pins PP0 can be used as general-purpose I/O or due to its increased current capability in output mode as a switchable external power supply pin (EVDD) for external devices like Hall sensors. EVDD connects the load to the digital supply VDDX. An over-current monitor is implemented to protect the controller from short circuits or excess currents on the output which can only arise if the pin is configured for full drive. Although the full drive current is available on the high and low side, the protection is only available on the high side when sourcing current from EVDD to VSSX. There is also no protection to voltages higher than VDDX. To power up the over-current monitor set the related OCPE bit. In stop mode the over-current monitor is disabled for power saving. The increased current capability cannot be maintained to supply the external device. Therefore when using the pin as power supply the external load must be powered down prior to entering stop mode by driving the output low. An over-current condition is detected if the output current level exceeds the threshold IOCD in run mode. The output driver is immediately forced low and the over-current interrupt flag OCIF asserts. Refer to Section 2.4.5.3, “Over-Current Interrupt and Protection”.
2.5.4 Over-Current Protection on PT2
Pin PT2 can be used as general-purpose I/O or due to their increased current capability in output mode as a switchable external power ground pin for external devices like LEDs supplied by VDDX. PT2 are connecting to the digital ground VSSX. Similar protection mechanisms as for EVDD apply for PT2 accordingly in an inverse way.
2.5.5 Open Input Detect ion on PL[2:0] (HVI)
The connection of an external pull device on a high-voltage input can be validated by using the built-in pull functionality of the HVI. Depending on the application type an external pulldown circuit can be detected with the internal pullup device whereas an external pullup circuit can be detected with the internal pulldown device which is part of the input voltage divider. Note that the following procedures make use of a function that overrides the automatic disable mechanism of the digital input buffer when using the HVI in analog mode. Make sure to switch off the override function when using the HVI in analog mode after the check has been completed.
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External pulldown device (Figure 2-43): 1. Enable analog function on HVI in non -direct mode (PTAENL=1, PTADIRL=0) 2. Select internal pullup device on HVI (PTPSL=1) 3. Enable function to force input buffe r active on HVI in analog mode (PTTEL=1) 4. Verify PTIL=0 for a connected external pul ldown device; read PTIL=1 for an open input Figure 2-43. Digital Input Read with Pullup Enabled External pullup device (Figure 2-44): 1. Enable analog function on HVI in non -direct mode (PTAENL=1, PTADIRL=0) 2. Select internal pulldown device on HVI (PTPSL=0) 3. Enable function to force input buffe r active on HVI in analog mode (PTTEL=1) 4. Verify PTIL=1 for a connected external pul lup device; read PTIL=0 for an open input HVI 40K 500K VDDX Digital in110K / 550K min. 1/10 * VDDX 10K PIRL=0 / PIRL=1 HV Supply
Chapter 2 Port Integration Module (S12ZVMBPIMV3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 115 Figure 2-44. Digital Input Read with Pulldown Enabled HVI 40K 610K / 1050K Digital in max. 10/11 * VHVI (PIRL=0) PIRL=0 / PIRL=1 max. 21/22 * VHVI (PIRL=1) 10K HV Supply
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MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductor 117 Chapter 3 Memory Mapping Control (S12ZMMCV1) Table 3-1. Revision History
3.1 Introduction
The S12ZMMC module controls the access to all internal memories and peripherals for the S12ZCPU, and the S12ZBDC module. It also provides direct memory access for the ADC module. The S12ZMMC determines the address mapping of the on-chip resources, regulates access priorities and enforces memory protection. Figure 3-1 shows a block diagram of the S12ZMMC module. Revision Number Revision Date Sections Affected Description of Changes V01.05 6 Aug 2012 Fixed wording V01.06 12 Feb 2013 Figure 3-8 3.3.2.2/3-122
- Changed “KByte:to “KB”
- Corrected the description of the MMCECH/L register V01.07 3 May 2013 • Fixed typos
- Removed PTU references
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3.1.1 Glossary
3.1.2 Overview
The S12ZMMC provides access to on-chip memories and peripherals for the S12ZCPU, the S12ZBDC, and the ADC. It arbitrates memory accesses and determines all of the MCU memory maps. Furthermore, the S12ZMMC is responsible for selecting the MCUs functional mode.
3.1.3 Features
- S12ZMMC mode operation control
- Memory mapping for S12ZCPU, S12ZBDC, and ADC — Maps peripherals and memories into a 16 MByte address space for the S12ZCPU, the S12ZBDC, and the ADC — Handles simultaneous accesses to different on-chip resources (NVM, RAM, and peripherals)
- Access violation de tection and logging — Triggers S12ZCPU machine exceptions upon de tection of illegal memory accesses and uncorrectable ECC errors — Logs the state of the S12ZCPU and the cause of the access error
3.1.4 Modes of Operation
3.1.4.1 Chip configuration modes
The S12ZMMC determines the chip configuration mode of the device. It captures the state of the MODC pin at reset and provides the ability to switch from special-single chip mode to normal single chip-mode. Table 3-2. Glossary Of Terms Term Definition MCU Microcontroller Unit CPU S12Z Central Processing Unit BDC S12Z Background Debug Controller ADC Analog-to-Digital Converter unmapped address range Address space that is not assigned to a memory reserved address range Address space that is reserved for future use cases illegal access Memory access, that is not supported or prohibited by the S12ZMMC, e.g. a data store to NVM access violation Either an illegal access or an uncorrectable ECC error byte 8-bit data word 16-bit data
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3.1.4.2 Power modes
The S12ZMMC module is only active in run and wait mode.There is no bus activity in stop mode.
3.1.5 Block Diagram
e Figure 3-1. S12ZMMC Block Diagram
3.2 External Signal Description
The S12ZMMC uses two external pins to determine the devices operating mode: RESET and MODC (Table 3-3) See device overview for the mapping of these signals to device pins.
3.3 Memory Map and Register Definition
3.3.1 Memory Map
A summary of the registers associated with the MMC block is shown in Figure 3-2. Detailed descriptions of the registers and bits are given in the subsections that follow. Table 3-3. External System Pins Associated With S12ZMMC Pin Name Description RESET External reset signal. The RESET signal is active low. MODC This input is captured in bit MODC of the MODE register when the external RESET pin deasserts. Memory Protection Crossbar Switch Register Block Run Mode Controller S12ZCPU S12ZBDC ADC EEPROM RAM PeripheralsProgram Flash
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3.3.2 Register Descriptions
This section consists of the S12ZMMC control and status register descriptions in address order. Address Name Bit 7 6 5 4 3 2 1 Bit 0 0x0070 MODE R MODC 000 0 0 0 0 W 0x0071- 0x007F Reserved R 0 0 0 0 0 0 0 0 W 0x0080 MMCECH R ITR[3:0] TGT[3:0]W 0x0081 MMCECL R ACC[3:0] ERR[3:0]W 0x0082 MMCCCRH R CPUU 0 0 0 0 0 0 0 W 0x0083 MMCCCRL R 0 CPUX 0 CPUI 0 0 0 0 W 0x0084 Reserved R 0 0 0 0 0 0 0 0 W 0x0085 MMCPCH R CPUPC[23:16] W 0x0086 MMCPCM R CPUPC[15:8] W 0x0087 MMCPCL R CPUPC[7:0] W 0x0088- 0x00FF Reserved R 0 0 0 0 0 0 0 0 W = Unimplemented or Reserved Figure 3-2. S12ZMMC Register Summary
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3.3.2.1 Mode Register (MODE)
Read: Anytime. Write: Only if a transition is allowed (see Figure 3-4). The MODE register determines the operating mode of the MCU. CAUTION Figure 3-4. Mode Transition Diagram Address: 0x0070 76543210 R MODC 0000000 W Reset MODC 1 0000000 1. External signal (see Table 3-3). = Unimplemented or Reserved Figure 3-3. Mode Register (MODE) Table 3-4. MODE Field Descriptions Field Description MODC Mode Select Bit — This bit determines the current operating mode of the MCU. Its reset value is captured from the MODC pin at the rising edge of the RESET pin. Figure 3-4 illustrates the only valid mode transition from special single-chip mode to normal single chip mode. Reset with MODC pin = 1 Reset with MODC pin = 0 Special Single-Chip Mode (SS) Normal Single-Chip Mode (NS) write access to MODE: 1 MODC bit
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3.3.2.2 Error Code Register (MMCECH, MMCECL)
Figure 3-5. Error Code Register (MMCEC) Read: Anytime Write: Write of 0xFFFF to MMCECH:MMCECL resets both registers to 0x0000 Table 3-5. MMCECH and MMCECL Field Descriptions Address: 0x0080 (MMCECH) 76543210 R ITR[3:0] TGT[3:0] W R e s e t 00000000 Address: 0x0081 (MMCECL) 76543210 R ACC[3:0] ERR[3:0] W R e s e t 00000000 Field Description 7-4 (MMCECH) ITR[3:0] Initiator Field — The ITR[3:0] bits capture the initiator whic h caused the access violation. The initiator is captured in form of a 4 bit value which is assigned as follows: 0: none (no error condition detected) 1: S12ZCPU 2: reserved 3: ADC 4-15: reserved 3-0 (MMCECH) TGT[3:0] Target Field — The TGT[3:0] bits captur e the target of the faulty access. The target is captured in form of a 4 bit value which is assigned as follows: 0: none 1: register space 2: RAM 3: EEPROM 4: program flash 5: IFR 6-15: reserved
Chapter 3 Memory Mapping Control (S12ZMMCV1) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 123 The MMCEC register captures debug information about access violations. It is set to a non-zero value if a S12ZCPU access violation or an uncorrectable ECC error has occurred. At the same time this register is set to a non-zero value, access information is captured in the MMCPCn and MMCCCRn registers. The MMCECn, the MMCPCn and the MMCCCRn registers are not updated if the MMCECn registers contain a non-zero value. The MMCECn registers are cleared by writing the value 0xFFFF.
3.3.2.3 Captured S12ZCPU Condition Code Register (MMCCCRH, MMCCCRL)
Figure 3-6. Captured S12ZCPU Condition Code Register (MMCCCRH, MMCCCRL) Read: Anytime Write: Never 7-4 (MMCECL) ACC[3:0] Access Type Field — The ACC[3:0] bits capture the type of memory access, which caused the access violation. The access type is captured in form of a 4 bit value which is assigned as follows: 0: none (no error condition detected) 1: opcode fetch 2: vector fetch 3: data load 4: data store 5-15: reserved 3-0 (MMCECL) ERR[3:0] Error Type Field — The EC[3:0] bits capture the type of the acce ss violation. The type is captured in form of a 4 bit value which is assigned as follows: 0: none (no error condition detected) 1: access to an illegal address 2: uncorrectable ECC error 3-15:reserved Address: 0x0082 (MMCCCRH) 76543210 RC P U U 0 0 0 0 0 0 0 W R e s e t 00000000 Address: 0x0083 (MMCCCRL) 76543210 R 0 CPUX 0 CPUI 0 0 0 0 W R e s e t 00000000 Field Description
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Table 3-6. MMCCCRH and MMCCCRL Field Descriptions
3.3.2.4 Captured S12ZCPU Program Counter (MMCPCH, MMCPCM, MMCPCL)
Figure 3-7. Captured S12ZCPU Program Counter (MMCPCH, MMCPCM, MMCPCL) Read: Anytime Write: Never Field Description 7 (MMCCCRH) CPUU S12ZCPU User State Flag — This bit shows the state of the user /supervisor mode bit in the S12ZCPU’s CCR at the time the access violation has occurred. The S12ZCPU user state flag is read-only; it will be automatically updated when the next error condition is flagged through the MMCEC register. This bit is undefined if the error code registers (MMCECn) are cleared. 6 (MMCCCRL) CPUX S12ZCPU X-Interrupt Mask— This bit shows the state of the X-in terrupt mask in the S12ZCPU’s CCR at the time the access violation has occurred. The S12ZCPU X-interrupt mask is read-only; it will be automatically updated when the next error condition is flagged through the MMCEC register. This bit is undefined if the error code registers (MMCECn) are cleared. 4 (MMCCCRL) CPUI S12ZCPU I-Interrupt Mask— This bit shows the state of the I-interrupt mask in the CPU’s CCR at the time the access violation has occurred. The S12ZCPU I-interrupt mask is read-only; it will be automatically updated when the next error condition is flagged through the MMCEC register. This bit is undefined if the error code registers (MMCECn) are cleared. Address: 0x0085 (MMCPCH) 76543210 R CPUPC[23:16] W R e s e t 00000000 Address: 0x0086 (MMCPCM) 76543210 RC P U P C [ 1 5 : 8 ] W R e s e t 00000000 Address: 0x0087 (MMCPCL) 76543210 R CPUPC[7:0] W R e s e t 00000000
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3.4 Functional Description
This section provides a complete functional description of the S12ZMMC module.
3.4.1 Global Memory Map
The S12ZMMC maps all on-chip resources into an 16MB address space, the global memory map. The exact resource mapping is shown in Figure 3-8. The global address space is used by the S12ZCPU, ADC, and the S12ZBDC module. Field Description 7–0 (MMCPCH) 7–0 (MMCPCM) 7–0 (MMCPCL) CPUPC[23:0] S12ZCPU Program Counter Value— The CPUPC[23:0] stores the CPU’s program counter value at the time the access violation occurred. CPUPC[23:0] always points to the instruction which triggered the violation. These bits are undefined if the error code registers (MMCECn) are cleared.
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Figure 3-8. Global Memory Map 0x00_1000 0x00_0000 0x10_0000 0x1F_4000 0x80_0000 0xFF_FFFF RAM EEPROM Unmapped Program NVM Register Space 4 KB max. 1 MByte - 4 KB max. 1 MByte - 48 KB max. 8 MByte 0x1F_8000 Unmapped address range 0x1F_C000 Reserved (read only) 6 KBKB NVM IFR 256 Byte Reserved 512 Byte 0x20_0000
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3.4.2 Illegal Accesses
The S12ZMMC module monitors all memory traffic for illegal accesses. See Table 3-8 for a complete list of all illegal accesses. Illegal accesses are reported in several ways:
- All illegal accesses perf ormed by the S12ZCPU trigger machine exceptions.
- All illegal accesses performed through the S12ZBDC interface, are captured in the ILLACC bit of the BDCCSRL register. Table 3-8. Illegal memory accesses S12ZCPU S12ZBDC ADC Register space Read access ok ok illegal access Write access ok ok illegal access Code execution illegal access RAM Read access ok ok ok Write access ok ok ok Code execution ok EEPROM Read access ok (1) 1. Unsupported NVM accesses during NVM command execution (“collisions”), are treated as illegal accesses. ok1 ok1 Write access illegal access illegal access illegal access Code execution ok 1 Reserved Space Read access ok ok illegal access Write access only permitted in SS mode ok illegal access Code execution illegal access Reserved Read-only Space Read access ok ok illegal access Write access illegal access illegal access illegal access Code execution illegal access NVM IFR Read access ok 1 ok1 illegal access Write access illegal access illegal access illegal access Code execution illegal access Program NVM Read access ok 1 ok1 ok1 Write access illegal access illegal access illegal access Code execution ok 1 Unmapped Space Read access illegal access illegal access illegal access Write access illegal access illegal access illegal access Code execution illegal access
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- All illegal accesses pe rformed by the ADC module trigger error interrupts. See ADC section for details. NOTE Illegal accesses caused by S12ZCPU opcode prefetches will also trigger machine exceptions, even if those opcodes might not be executed in the program flow. To avoid these machine exceptions, S12ZCPU instructions must not be executed from the last (high addresses) 8 bytes of RAM, EEPROM, and Flash.
3.4.3 Uncorrectable ECC Faults
RAM and flash use error correction codes (ECC) to detect and correct memory corruption. Each uncorrectable memory corruption, which is detected during a S12ZCPU or ADC access triggers a machine exception. Uncorrectable memory corruptions which are detected during a S12ZBDC access, are captured in the RAMWF or the RDINV bit of the BDCCSRL register.
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4.1 Introduction
The INT module decodes the priority of all system exception requests and provides the applicable vector for processing the exception to the CPU. The INT module supports:
- I-bit and X-bit maskable interrupt requests
- One non-maskable unimpleme nted page1 op-code trap Table 4-1. Revision History Version Number Revision Date Effective Date Description of Changes V00.01 17 Apr 2009 all Initial version based on S12XINT V2.06 V00.02 14 Jul 2009 all Reduce RESET vectors from three to one. V00.03 05 Oct 2009 all Removed dedicated ECC machine exception vector and marked vector-table entry “reserved for future use”. Added a second illegal op-code vector (to distinguish between SPARE and TRAP). V00.04 04 Jun 2010 all Fixed remaining descriptions of RESET vectors. Split non-maskable hardware interrupts into XGATE software error and machine exception requests. Replaced mentions of CCR (old name from S12X) with CCW (new name). V00.05 12 Jan 2011 all Corrected wrong IRQ vector address in some descriptions. V00.06 22 Mar 2011 all Added vectors for RAM ECC and NVM ECC machine exceptions. And moved position to 1E0..1E8. Moved XGATE error interrupt to vector 1DC. Remaining vectors accordingly. Removed illegal address reset as a potential reset source. V00.07 15 Apr 2011 all Removed illegal address reset as a potential reset source from Exception vector table as well. Added the other possible reset sources to the table. Changed register addresses according to S12Z platform definition. V00.08 02 May 2011 all Reduced machine exception vectors to one. Removed XGATE error interrupt. Moved Spurious interrupt vector to 1DC. Moved vector base address to 010 to make room for NVM non-volatile registers. V00.09 12 Aug 2011 all Added: Machine excepti ons can cause wake-up from STOP or WAIT V00.10 21 Feb 2012 all Corrected reset value for INT_CFADDR register V00.11 02 Jul 2012 all Removed references and functions related to XGATE V00.12 22 May 2013 all added footnote ab out availability of “Wake-up from STOP or WAIT by XIRQ with X bit set” feature
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- One non-maskable unimpleme nted page2 op-code trap
- One non-maskable software interrupt (SWI)
- One non-maskable system call interrupt (SYS)
- One non-maskable machine exception vector request
- One spurious interrupt vector request
- One system reset vector request Each of the I-bit maskable interrupt requests can be assigned to one of seven priority levels supporting a flexible priority scheme. The priority scheme can be used to implement nested interrupt capability where interrupts from a lower level are automatically blocked if a higher level interrupt is being processed.
4.1.1 Glossary
The following terms and abbreviations are used in the document.
4.1.2 Features
- Interrupt vector ba se register (IVBR)
- One system reset vect or (at address 0xFFFFFC).
- One non-maskable unimplemented page1 op-code trap (SPARE) vector (at address vector base1 + 0x0001F8).
- One non-maskable unimplemented page2 op-code trap (TRAP) vector (at address vector base1 + 0x0001F4).
- One non-maskable software interrupt reque st (SWI) vector (at address vector base1 + 0x0001F0).
- One non-maskable system call interrupt re quest (SYS) vector (at address vector base1 + 0x00001EC).
- One non-maskable machine exception vect or request (at address vector base1 + 0x0001E8.
- One spurious interrupt vect or (at address vector base1 + 0x0001DC). Table 4-2. Terminology Term Meaning CCW Condition Code Register (in the S12Z CPU) DMA Direct Memory Access INT Interrupt IPL Interrupt Processing Level ISR Interrupt Service Routine MCU Micro-Controller Unit IRQ refers to the interrupt request associated with the IRQ pin XIRQ refers to the interrupt request associated with the XIRQ pin 1. The vector base is a 24-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used as the upper 15 bits of the address) and 0x000 (used as the lower 9 bits of the address).
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- One X-bit maskable interrupt vect or request associated with XIRQ (at address vector base1 + 0x0001D8).
- One I-bit maskable interrupt vect or request associated with IRQ (at address vector base1 + 0x0001D4).
- up to 113 additional I-bit maskable interrupt vector requests (at addresses vector base1 + 0x000010 .. vector base + 0x0001D0).
- Each I-bit maskable interrupt request has a configurable priority level.
- I-bit maskable interrupts can be nest ed, depending on their priority levels.
- Wakes up the system from stop or wait mode when an appropriate interrupt request occurs or whenever XIRQ is asserted, even if X interrupt is masked.
4.1.3 Modes of Operation
- Run mode This is the basic mode of operation.
- Wait mode In wait mode, the INT module is capable of waking up the CPU if an eligible CPU exception occurs. Please refer to Section 4.5.3, “Wake Up from Stop or Wait Mode” for details.
- Stop Mode In stop mode, the INT module is capable of waking up the CPU if an eligible CPU exception occurs. Please refer to Section 4.5.3, “Wake Up from Stop or Wait Mode” for details.
4.1.4 Block Diagram
Figure 4-1 shows a block diagram of the INT module.
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Figure 4-1. INT Block Diagram
4.2 External Signal Description
The INT module has no external signals.
4.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the INT module.
4.3.1 Module Memory Map
Table 4-3 gives an overview over all INT module registers. Table 4-3. INT Memory Map Address Use Access 0x000010–0x000011 Interrupt Vect or Base Register (IVBR) R/W 0x000012–0x000016 RESERVED — 0x000017 Interrupt Request Conf iguration Address Register (INT_CFADDR) R/W 0x000018 Interrupt Request Conf iguration Data Register 0 (INT_CFDATA0) R/W Wake Up Current IVBR One Set Per Channel Interrupt Requests Interrupt Requests CPU Vector Address New IPL IPL (Up to 117 Channels) PRIOLVLnPriority Level = configuration bits from the associated channel configuration register IVBR = Interrupt Vector Base IPL = Interrupt Processing Level PRIOLVL0 PRIOLVL1 PRIOLVL2 Peripheral To CPU Priority Decoder Non I Bit Maskable Channels Priority Level Filter Highest Pending IPL
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4.3.2 Register Descriptions
This section describes in address order all the INT module registers and their individual bits. 0x000019 Interrupt Request Conf iguration Data Register 1 (INT_CFDATA1) R/W 0x00001A Interrupt Request Configuration Data Register 2 (INT_CFDATA2 R/W 0x00001B Interrupt Request Configuration Data Register 3 (INT_CFDATA3) R/W 0x00001C Interrupt Request Configuration Data Register 4 (INT_CFDATA4) R/W 0x00001D Interrupt Request Configuration Data Register 5 (INT_CFDATA5) R/W 0x00001E Interrupt Request Configuration Data Register 6 (INT_CFDATA6) R/W 0x00001F Interrupt Request Configuration Data Register 7 (INT_CFDATA7) R/W Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x000010 IVBR R IVB_ADDR[15:8] W 0x000011 R IVB_ADDR[7:1] W 0x000017 INT_CFADDR R 0 INT_CFADDR[6:3] 000 W 0x000018 INT_CFDATA0 R 0 0 0 0 0 PRIOLVL[2:0] W 0x000019 INT_CFDATA1 R 0 0 0 0 0 PRIOLVL[2:0] W 0x00001A INT_CFDATA2 R 0 0 0 0 0 PRIOLVL[2:0] W 0x00001B INT_CFDATA3 R 0 0 0 0 0 PRIOLVL[2:0] W 0x00001C INT_CFDATA4 R 0 0 0 0 0 PRIOLVL[2:0] W = Unimplemented or Reserved Figure 4-2. INT Register Summary Table 4-3. INT Memory Map
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4.3.2.1 Interrupt Vector Base Register (IVBR)
Read: Anytime Write: Anytime
4.3.2.2 Interrupt Request Configurat ion Address Register (INT_CFADDR)
Read: Anytime 0x00001D INT_CFDATA5 R 0 0 0 0 0 PRIOLVL[2:0] W 0x00001E INT_CFDATA6 R 0 0 0 0 0 PRIOLVL[2:0] W 0x00001F INT_CFDATA7 R 0 0 0 0 0 PRIOLVL[2:0] W Address: 0x000010 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R IVB_ADDR[15:1] 0 W R e s e t 1111111111111110 Figure 4-3. Interrupt Vector Base Register (IVBR) Table 4-4. IVBR Field Descriptions Field Description 15–1 IVB_ADDR [15:1] Interrupt Vector Base Address Bits — These bits represent the upper 15 bi ts of all vector addresses. Out of reset these bits are set to 0xFFFE (i.e., vectors are located at 0xFFFE00–0xFFFFFF). Note: A system reset will initialize the interrupt vector base register with “0xFFFE” before it is used to determine the reset vector address. Therefore, changing the IVBR has no effect on the location of the reset vector (0xFFFFFC–0xFFFFFF). Address: 0x000017 76543210 INT_CFADDR[6:3] 000 W R e s e t 00001000 = Unimplemented or Reserved Figure 4-4. Interrupt Configuration Address Register (INT_CFADDR) Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 4-2. INT Register Summary
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4.3.2.3 Interrupt Request Configuration Data Registers (INT_CFDATA0–7)
The eight register window visible at addresses INT_CFDATA0–7 contains the configuration data for the block of eight interrupt requests (out of 128) selected by the interrupt configuration address register (INT_CFADDR) in ascending order. INT_CFDATA0 represents the interrupt configuration data register of the vector with the lowest address in this block, while INT_CFDATA7 represents the interrupt configuration data register of the vector with the highest address, respectively. Table 4-5. INT_CFADDR Field Descriptions Field Description 6–3 INT_CFADDR[6:3] Interrupt Request Configuration Data Register Select Bits — These bits determine which of the 128 configuration data registers are accessible in the 8 register window at INT_CFDATA0–7. The hexadecimal value written to this register corresponds to the upper 4 bits of the vector number (multiply with 4 to get the vector address offset). If, for example, the value 0x70 is written to this register, the configuration data register block for the 8 interrupt vector requests starting with vector at address (vector base + (0x70*4 = 0x0001C0)) is selected and can be accessed as INT_CFDATA0–7. Address: 0x000018 76543210 R 00000 PRIOLVL[2:0] W R e s e t 0000000 1 (1) 1. Please refer to the notes following the PRIOLVL[2:0] description below. = Unimplemented or Reserved Figure 4-5. Interrupt Request Configuration Data Register 0 (INT_CFDATA0) Address: 0x000019 76543210 R 00000 PRIOLVL[2:0] W R e s e t 0000000 1 (1) 1. Please refer to the notes following the PRIOLVL[2:0] description below. = Unimplemented or Reserved Figure 4-6. Interrupt Request Configuration Data Register 1 (INT_CFDATA1) Address: 0x00001A 76543210 R 00000 PRIOLVL[2:0]W R e s e t 0000000 1 (1) = Unimplemented or Reserved Figure 4-7. Interrupt Request Configuration Data Register 2 (INT_CFDATA2)
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- Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x00001B 76543210 R 00000 PRIOLVL[2:0] W R e s e t 0000000 1 (1) 1. Please refer to the notes following the PRIOLVL[2:0] description below. = Unimplemented or Reserved Figure 4-8. Interrupt Request Configuration Data Register 3 (INT_CFDATA3) Address: 0x00001C 76543210 R 00000 PRIOLVL[2:0] W R e s e t 0000000 1 (1) 1. Please refer to the notes following the PRIOLVL[2:0] description below. = Unimplemented or Reserved Figure 4-9. Interrupt Request Configuration Data Register 4 (INT_CFDATA4) Address: 0x00001D 76543210 R 00000 PRIOLVL[2:0]W R e s e t 0000000 1 (1) 1. Please refer to the notes following the PRIOLVL[2:0] description below. = Unimplemented or Reserved Figure 4-10. Interrupt Request Configuration Data Register 5 (INT_CFDATA5) Address: 0x00001E 76543210 R 00000 PRIOLVL[2:0] W R e s e t 0000000 1 (1) 1. Please refer to the notes following the PRIOLVL[2:0] description below. = Unimplemented or Reserved Figure 4-11. Interrupt Request Configuration Data Register 6 (INT_CFDATA6)
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4.4 Functional Description
The INT module processes all exception requests to be serviced by the CPU module. These exceptions include interrupt vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the subsections below. Address: 0x00001F 76543210 R 00000 PRIOLVL[2:0] W R e s e t 0000000 1 (1) 1. Please refer to the notes following the PRIOLVL[2:0] description below. = Unimplemented or Reserved Figure 4-12. Interrupt Request Configuration Data Register 7 (INT_CFDATA7) Table 4-6. INT_CFDATA0–7 Field Descriptions Field Description 2–0 PRIOLVL[2:0] Interrupt Request Priority Level Bits — The PRIOLVL[2:0] bits configure the interrupt request priority level of the associated interrupt request. Out of reset all interrupt requests are enabled at the lowest active level (“1”). Please also refer to Table 4-7 for available interrupt request priority levels. Note: Write accesses to configuration data registers of unused interrupt channels are ignored and read accesses return all 0s. For information about what interrupt channels are used in a specific MCU, please refer to the Device Reference Manual for that MCU. Note: When non I-bit maskable request vectors are selected, writes to the corresponding INT_CFDATA registers are ignored and read accesses return all 0s. The corresponding vectors do not have configuration data registers associated with them. Note: Write accesses to the configuration register for the spurious interrupt vector request (vector base + 0x0001DC) are ignored and read accesses return 0x07 (request is handled by the CPU, PRIOLVL = 7). Table 4-7. Interrupt Priority Levels Priority PRIOLVL2 PRIOLVL1 PRIOLVL0 Meaning 0 0 0 Interrupt request is disabled low 0 0 1 Priority level 1 0 1 0 Priority level 2 0 1 1 Priority level 3 1 0 0 Priority level 4 1 0 1 Priority level 5 1 1 0 Priority level 6 high 1 1 1 Priority level 7
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4.4.1 S12Z Exception Requests
The CPU handles both reset requests and interrupt requests. The INT module contains registers to configure the priority level of each I-bit maskable interrupt request which can be used to implement an interrupt priority scheme. This also includes the possibility to nest interrupt requests. A priority decoder is used to evaluate the relative priority of pending interrupt requests.
4.4.2 Interrupt Prioritization
After system reset all I-bit maskable interrupt requests are configured to be enabled, are set up to be handled by the CPU and have a pre-configured priority level of 1. Exceptions to this rule are the non- maskable interrupt requests and the spurious interrupt vector request at (vector base + 0x0001DC) which cannot be disabled, are always handled by the CPU and have a fixed priority levels. A priority level of 0 effectively disables the associated I-bit maskable interrupt request. If more than one interrupt request is configured to the same interrupt priority level the interrupt request with the higher vector address wins the prioritization. The following conditions must be met for an I-bit maskable interrupt request to be processed. 1. The local interrupt enabled bit in the peripheral module must be set. 2. The setup in the configuration register associated with the interrupt request channel must meet the following conditions: a) The priority level must be set to non zero. b) The priority level must be greater than the current interrupt processing level in the condition code register (CCW) of the CPU (PRIOLVL[2:0] > IPL[2:0]). 3. The I-bit in the condition code regist er (CCW) of the CPU must be cleared. 4. There is no access violatio n interrupt request pending. 5. There is no SYS, SWI, SPARE, TRAP, Machine Exception or XIRQ request pending. NOTE All non I-bit maskable interrupt requests always have higher priority than I- bit maskable interrupt requests. If an I-bit maskable interrupt request is interrupted by a non I-bit maskable interrupt request, the currently active interrupt processing level (IPL) remains unaffected. It is possible to nest non I-bit maskable interrupt requests, e.g., by nesting SWI, SYS or TRAP calls.
4.4.2.1 Interrupt Priority Stack
The current interrupt processing level (IPL) is stored in the condition code register (CCW) of the CPU. This way the current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The new IPL is copied to the CCW from the priority level of the highest priority active interrupt request channel which is configured to be handled by the CPU. The copying takes place when the interrupt vector is fetched. The previous IPL is automatically restored from the stack by executing the RTI instruction.
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4.4.3 Priority Decoder
The INT module contains a priority decoder to determine the relative priority for all interrupt requests pending for the CPU. A CPU interrupt vector is not supplied until the CPU requests it. Therefore, it is possible that a higher priority interrupt request could override the original exception which caused the CPU to request the vector. In this case, the CPU will receive the highest priority vector and the system will process this exception first instead of the original request. If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the CPU defaults to that of the spurious interrupt vector. NOTE Care must be taken to ensure that all exception requests remain active until the system begins execution of the applicable service routine; otherwise, the exception request may not get processed at all or the result may be a spurious interrupt request (vector at address (vector base + 0x0001DC)).
4.4.4 Reset Exception Requests
The INT module supports one system reset exception request. The different reset types are mapped to this vector (for details please refer to the Clock and Power Management Unit module (CPMU)): 1. Pin reset 2. Power-on reset 3. Low-voltage reset 4. Clock monitor reset request 5. COP watchdog reset request
4.4.5 Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the INT module upon request by the CPU are shown in Table 4-8. Generally, all non-maskable interrupts have higher priorities than maskable interrupts. Please note that between the four software interrupts (Unimplemented op-code trap page1/page2 requests, SWI request, SYS request) there is no real priority defined since they cannot occur simultaneously (the S12Z CPU executes one instruction at a time). Table 4-8. Exception Vector Map and Priority Vector Address(1) Source 0xFFFFFC Pin reset, power-o n reset, low-voltage reset, clock monitor reset, COP watchdog reset (Vector base + 0x0001F8) Unimplemented p age1 op-code trap (SPARE) vector request (Vector base + 0x0001F4) Unimplemented p age2 op-code trap (TRAP) vector request (Vector base + 0x0001F0) Software interr upt instruction (SWI) vector request (Vector base + 0x0001EC) System call in terrupt instruction (SYS) vector request
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4.4.6 Interrupt Vector Table Layout
The interrupt vector table contains 128 entries, each 32 bits (4 bytes) wide. Each entry contains a 24-bit address (3 bytes) which is stored in the 3 low-significant bytes of the entry. The content of the most significant byte of a vector-table entry is ignored. Figure 4-13 illustrates the vector table entry format. Figure 4-13. Interrupt Vector Table Entry
4.5 Initialization/Application Information
4.5.1 Initialization
After system reset, software should:
- Initialize the interrupt vector base register if the interrupt vector table is not located at the default location (0xFFFE00–0xFFFFFB).
- Initialize the interrupt processing level c onfiguration data registers (INT_CFADDR, INT_CFDATA0–7) for all interrupt vector requests with the desired priority levels. It might be a good idea to disable unused interrupt requests.
- Enable I-bit maskable interrupts by clearing the I-bit in the CCW.
- Enable the X-bit maskable interrupt by cl earing the X-bit in the CCW (if required).
4.5.2 Interrupt Nesting
The interrupt request priority level scheme makes it possible to implement priority based interrupt request nesting for the I-bit maskable interrupt requests.
- I-bit maskable interrupt requests can be interrupt ed by an interrupt request with a higher priority, so that there can be up to seven nested I-bit maskable interrupt requests at a time (refer to Figure 4- 14 for an example using up to three nested interrupt requests). (Vector base + 0x0001E8) Machine exception vector request (Vector base + 0x0001E4) Reserved (Vector base + 0x0001E0) Reserved (Vector base + 0x0001DC) Spurious interrupt (Vector base + 0x0001D8) XIRQ interrupt request (Vector base + 0x0001D4) IRQ interrupt request (Vector base + 0x000010 Vector base + 0x0001D0) Device specific I-bit maskable interrupt sources (priority determined by the associated configuration registers, in descending order) 1. 24 bits vector address based (unused) ISR Address Table 4-8. Exception Vector Map and Priority Vector Address(1) Source
Chapter 4 Interrupt (S12ZINTV0) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 141 I-bit maskable interrupt requests cannot be interrupted by other I-bit maskable interrupt requests per default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the I-bit in the CCW (CLI). After clearing the I-bit, I-bit maskable interrupt requests with higher priority can interrupt the current ISR. An ISR of an interruptible I-bit maskable interrupt request could basically look like this:
- Service interrupt, e.g., clear in terrupt flags, copy data, etc.
- Clear I-bit in the CCW by executi ng the CPU instruction CLI (thus allowing interrupt requests with higher priority)
- Process data
- Return from interrupt by ex ecuting the instruction RTI Figure 4-14. Interrupt Processing Example
4.5.3 Wake Up from Stop or Wait Mode
4.5.3.1 CPU Wake Up from Stop or Wait Mode
Every I-bit maskable interrupt request which is configured to be handled by the CPU is capable of waking the MCU from stop or wait mode. Additionally machine exceptions can wake-up the MCU from stop or wait mode. To determine whether an I-bit maskable interrupts is qualified to wake up the CPU or not, the same settings as in normal run mode are applied during stop or wait mode:
- If the I-bit in the CCW is set, all I-bit mask able interrupts are masked from waking up the MCU.
- An I-bit maskable interrupt is ignored if it is c onfigured to a priority level below or equal to the current IPL in CCW. The X-bit maskable interrupt request can wake up the MCU from stop or wait mode at anytime, even if the X-bit in CCW is set1. If the X-bit maskable interrupt request is used to wake-up the MCU with the X- Reset L1 (Pending) L3 (Pending) RTI RTI RTI RTI Stacked IPL Processing Levels IPL in CCW
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bit in the CCW set, the associated ISR is not called. The CPU then resumes program execution with the instruction following the WAI or STOP instruction. This feature works following the same rules like any interrupt request, i.e. care must be taken that the X-bit maskable interrupt request used for wake-up remains active at least until the system begins execution of the instruction following the WAI or STOP instruction; otherwise, wake-up may not occur. 1. The capability of the XIRQ pin to wake-up the MCU with the X bit set may not be available if, for example, the XIRQ pin is shared with other peripheral modules on the device. Please refer to the Port Integration Module (PIM) section of the MCU reference manual for details.
MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductor 143 Chapter 5 Background Debug Controller (S12ZBDCV2)
5.1 Introduction
The background debug controller (BDC) is a single-wire, background debug system implemented in on- chip hardware for minimal CPU intervention. The device BKGD pin interfaces directly to the BDC. The S12ZBDC maintains the standard S12 serial interface protocol but introduces an enhanced handshake protocol and enhanced BDC command set to support the linear instruction set family of S12Z devices and offer easier, more flexible internal resource access over the BDC serial interface. Table 5-1. Revision History Revision Number Revision Date Sections Affected Description of Changes “Low-Power Modes Included BACKGROUND/ Stop mode dependency “BDC Control Status Register Low (BDCCSRL) Improved NORESP description and added STEP1/ Wait mode dependency “BDC Control Status Register Low (BDCCSRL) Improved NORESP description of STEP1/ Wait mode dependency “Stop Mode Improved STOP and BACKGROUND interdepency description “BACKGROUND Section 5.4.7.1, “Long-ACK Hardware Handshake Protocol Removed misleading WAIT and BACKGROUND interdepency description Added subsection dedicated to Long-ACK “READ_DBGTB Noted that READ_DBGTB is only available for devices featuring a trace buffer. “Wait Mode Improved description of NORESP dependence on WAIT and BACKROUND “Stop Mode Section 5.3.2, “Register Descriptions Corrected name of clock that can stay active in Stop mode
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5.1.1 Glossary
5.1.2 Features
The BDC includes these distinctive features:
- Single-wire communication wi th host development system
- SYNC command to determine communication rate
- Genuine non-intrusive handshake protocol
- Enhanced handshake protoc ol for error detection and stop mode recognition
- Active out of reset in special single chip mode
- Most commands not requi ring active BDM, for minimal CPU intervention
- Full global memory map access without paging
- Simple flash mass erase capability
5.1.3 Modes of Operation
S12 devices feature power modes (run, wait, and stop) and operating modes (normal single chip, special single chip). Furthermore, the operation of the BDC is dependent on the device security status.
5.1.3.1 BDC Modes
The BDC features module specific modes, namely disabled, enabled and active. These modes are dependent on the device security and operating mode. In active BDM the CPU ceases execution, to allow BDC system access to all internal resources including CPU internal registers.
5.1.3.2 Security and Oper ating mode Dependency
In device run mode the BDC dependency is as follows
- Normal modes, unsecure device General BDC operation available. The BDC is disabled out of reset. Table 5-2. Glossary Of Terms Term Definition DBG On chip Debug Module BDM Active Background Debug Mode CPU S12Z CPU SSC Special Single Chip Mode (device operating mode NSC Normal Single Chip Mode (device operating mode) BDCSI Background Debug Controller Serial Interface. This refers to the single pin BKGD serial interface. EWAIT Optional S12 feature which allows external devices to delay external accesses until deassertion of EWAIT
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- Normal modes, secure device BDC disabled. No BDC access possible.
- Special single chip mode, unsecure BDM active out of reset. All BDC commands are available.
- Special single chip mode, secure BDM active out of reset. Restricted command set available. When operating in secure mode, BDC operation is restricted to allow checking and clearing security by mass erasing the on-chip flash memory. Secure operation prevents BDC access to on-chip memory other than mass erase. The BDC command set is restricted to those commands classified as Always-available.
5.1.3.3 Low-Power Modes
5.1.3.3.1 Stop Mode
The execution of the CPU STOP instruction leads to stop mode only when all bus masters (CPU, or others, depending on the device) have finished processing. The operation during stop mode depends on the ENBDC and BDCCIS bit settings as summarized in Table 5-3 A disabled BDC has no influence on stop mode operation. In this case the BDCSI clock is disabled in stop mode thus it is not possible to enable the BDC from within stop mode. STOP Mode With BDC Enabled And BDCCIS Clear If the BDC is enabled and BDCCIS is clear, then the BDC prevents the BDCCLK clock (Figure 5-5) from being disabled in stop mode. This allows BDC communication to continue throughout stop mode in order to access the BDCCSR register. All other device level clock signals are disabled on entering stop mode. NOTE This is intended for application debugging, not for fast flash programming. Thus the CLKSW bit must be clear to map the BDCSI to BDCCLK. With the BDC enabled, an internal acknowledge delays stop mode entry and exit by 2 BDCSI clock + 2 bus clock cycles. If no other module delays stop mode entry and exit, then these additional clock cycles represent a difference between the debug and not debug cases. Furthermore if a BDC internal access is being executed when the device is entering stop mode, then the stop mode entry is delayed until the internal access is complete (typically for 1 bus clock cycle). Table 5-3. BDC STOP Operation Dependencies ENBDC BDCCIS Description Of Operation 0 0 BDC has no effect on STOP mode. 0 1 BDC has no effect on STOP mode. 1 0 Only BDCCLK clock continues 1 1 All clocks continue
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Accesses to the internal memory map are not possible when the internal device clocks are disabled. Thus attempted accesses to memory mapped resources are suppressed and the NORESP flag is set. Resources can be accessed again by the next command received following exit from Stop mode. A BACKGROUND command issued whilst in stop mode remains pending internally until the device leaves stop mode. This means that subsequent active BDM commands, issued whilst BACKGROUND is pending, set the ILLCMD flag because the device is not yet in active BDM. If ACK handshaking is enabled, then the first ACK, following a stop mode entry is long to indicate a stop exception. The BDC indicates a stop mode occurrence by setting the BDCCSR bit STOP. If the host attempts further communication before the ACK pulse generation then the OVRUN bit is set. STOP Mode With BDC Enabled And BDCCIS Set If the BDC is enabled and BDCCIS is set, then the BDC prevents core clocks being disabled in stop mode. This allows BDC communication, for access of internal memory mapped resources, but not CPU registers, to continue throughout stop mode. A BACKGROUND command issued whilst in stop mode remains pending internally until the device leaves stop mode. This means that subsequent active BDM commands, issued whilst BACKGROUND is pending, set the ILLCMD flag because the device is not yet in active BDM. If ACK handshaking is enabled, then the first ACK, following a stop mode entry is long to indicate a stop exception. The BDC indicates a stop mode occurrence by setting the BDCCSR bit STOP. If the host attempts further communication before the ACK pulse generation then the OVRUN bit is set.
5.1.3.3.2 Wait Mode
The device enters wait mode when the CPU starts to execute the WAI instruction. The second part of the WAI instruction (return from wait mode) can only be performed when an interrupt occurs. Thus on entering wait mode the CPU is in the middle of the WAI instruction and cannot permit access to CPU internal resources, nor allow entry to active BDM. Thus only commands classified as Non-Intrusive or Always-Available are possible in wait mode. On entering wait mode, the WAIT flag in BDCCSR is set. If the ACK handshake protocol is enabled then the first ACK generated after WAIT has been set is a long-ACK pulse. Thus the host can recognize a wait mode occurrence. The WAIT flag remains set and cannot be cleared whilst the device remains in wait mode. After the device leaves wait mode the WAIT flag can be cleared by writing a “1” to it. A BACKGROUND command issued whilst in wait mode sets the NORESP bit and the BDM active request remains pending internally until the CPU leaves wait mode due to an interrupt. The device then enters BDM with the PC pointing to the address of the first instruction of the ISR. With ACK disabled, further Non-Intrusive or Always-Available commands are possible, in this pending state, but attempted Active-Background commands set NORESP and ILLCMD because the BDC is not in active BDM state. With ACK enabled, if the host attempts further communication before the ACK pulse generation then the OVRUN bit is set.
Chapter 5 Background Debug Controller (S12ZBDCV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 147 Similarly the STEP1 command issued from a WAI instruction cannot be completed by the CPU until the CPU leaves wait mode due to an interrupt. The first STEP1 into wait mode sets the BDCCSR WAIT bit. If the part is still in Wait mode and a further STEP1 is carried out then the NORESP and ILLCMD bits are set because the device is no longer in active BDM for the duration of WAI execution.
5.1.4 Block Diagram
A block diagram of the BDC is shown in Figure 5-1. Figure 5-1. BDC Block Diagram
5.2 External Signal Description
A single-wire interface pin (BKGD) is used to communicate with the BDC system. During reset, this pin is a device mode select input. After reset, this pin becomes the dedicated serial interface pin for the BDC. BKGD is a pseudo-open-drain pin with an on-chip pull-up. Unlike typical open-drain pins, the external RC time constant on this pin due to external capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively driven speed-up pulses to force rapid rise times on this pin without risking harmful drive level conflicts. Refer to Section 5.4.6, “BDC Serial Interface” for more details. BKGD HOST SYSTEM SERIAL INTERFACE CONTROL INSTRUCTION DECODE AND BUS INTERFACE AND CONTROL LOGIC ADDRESS DATA BUS CONTROL BDCSI CORE CLOCK ERASE FLASH FLASH ERASED CPU CONTROL AND SHIFT REGISTER FLASH SECURE BDCCSR REGISTER AND DATAPATH CONTROL CLOCK DOMAIN CONTROL FSM
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5.3 Memory Map and Register Definition
5.3.1 Module Memory Map
Table 5-4 shows the BDC memory map.
5.3.2 Register Descriptions
The BDC registers are shown in Figure 5-2. Registers are accessed only by host-driven communications to the BDC hardware using READ_BDCCSR and WRITE_BDCCSR commands. They are not accessible in the device memory map.
5.3.2.1 BDC Control Status Register High (BDCCSRH)
Figure 5-3. BDC Control Status Register High (BDCCSRH) Table 5-4. BDC Memory Map Global Address Module Size (Bytes) Not Applicable BDC registers 2 Global Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 Not Applicable BDCCSRH R ENBDC BDMACT BDCCIS STEAL CLKSW UNSEC ERASE W Not Applicable BDCCSRL R WAIT STOP RAMWF OVRUN NORESP RDINV ILLACC ILLCMD W = Unimplemented, Reserved 0 = Always read zero Figure 5-2. BDC Register Summary Register Address: This register is not in the device memory map. It is accessible using BDC inherent addressing commands 7 6 54 3 2 1 0 R ENBDC BDMACT BDCCIS STEAL CLKSW UNSEC ERASE W Reset Secure AND SSC-Mode 1 1 00 0 0 0 0 Unsecure AND SSC-Mode 1 1 00 0 0 1 0 Secure AND NSC-Mode 0 0 00 0 0 0 0 Unsecure AND NSC-Mode 0 0 00 0 0 1 0 = Unimplemented, Reserved 0 = Always read zero
Chapter 5 Background Debug Controller (S12ZBDCV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 149 Read: All modes through BDC operation only. Write: All modes through BDC operation only, when not secured, but subject to the following: — Bits 7,3 and 2 can only be written by WRITE_BDCCSR commands. — Bit 5 can only be written by WR ITE_BDCCSR commands when the device is not in stop mode. — Bits 6, 1 and 0 cannot be written. They can only be updated by internal hardware. Table 5-5. BDCCSRH Field Descriptions Field Description ENBDC Enable BDC — This bit controls whether the BDC is enable d or disabled. When enabled, active BDM can be entered and non-intrusive commands can be carried out. When disabled, active BDM is not possible and the valid command set is restricted. Further information is provided in Table 5-7.
0 BDC disabled
1 BDC enabled
Note: ENBDC is set out of reset in special single chip mode. BDMACT BDM Active Status — This bit becomes set upon entering active BDM. BDMACT is cleared as part of the active BDM exit sequence.
0 BDM not active
Note: BDMACT is set out of reset in special single chip mode. BDCCIS BDC Continue In Stop — If ENBDC is set then BDCCIS selects the type of BDC operation in stop mode (as shown in Table 5-3). If ENBDC is clear, then the BDC has no effect on stop mode and no BDC communication is possible.If ACK pulse handshaking is enabled, then the first ACK pulse following stop mode entry is a long ACK. This bit cannot be written when the device is in stop mode.
0 Only the BDCCLK clock continues in stop mode
1 All clocks continue in stop mode
Steal enabled with ACK— This bit forces immediate internal accesses with the ACK handshaking protocol enabled. If ACK handshaking is disabled then BDC accesses steal the next bus cycle.
0 If ACK is enabled then BDC accesses await a free cycle, with a timeout of 512 cycles
1 If ACK is enabled then BDC accesses ar e carried out in the next bus cycle
Clock Switch — The CLKSW bit controls the BDCSI clock source. This bit is initialized to “0” by each reset and can be written to “1”. Once it has been set, it can only be cleared by a reset. When setting CLKSW a minimum delay of 150 cycles at the initial clock speed must elapse before the next command can be sent. This guarantees that the start of the next BDC command uses the new clock for timing subsequent BDC communications.
0 BDCCLK used as BDCSI clock source
1 Device fast clock used as BDCSI clock source
Note: Refer to the device specification to determine which clock connects to the BDCCLK and fast clock inputs. UNSEC Unsecure — If the device is unsecure, the UNSEC bit is set automatically. 0 Device is secure. 1 Device is unsecure. Note: When UNSEC is set, the device is unsecure and the state of the secure bits in the on-chip Flash EEPROM can be changed. ERASE Erase Flash — This bit can only be set by the dedicated ERASE_FLASH command. ERASE is unaffected by write accesses to BDCCSR. ERASE is cleared either when the mass erase sequence is completed, independent of the actual status of the flash array or by a soft reset. Reading this bit indicates the status of the requested mass erase sequence.
0 No flash mass erase sequence pending completion
1 Flash mass erase sequence pending completion.
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5.3.2.2 BDC Control Status Register Low (BDCCSRL)
Figure 5-4. BDC Control Status Register Low (BDCCSRL) Read: BDC access only. Write: Bits [7:5], [3:0] BDC access only, restricted to flag clearing by writing a “1” to the bit position. Write: Bit 4 never. It can only be cleared by a SYNC pulse. If ACK handshaking is enabled then BDC commands with ACK causing a BDCCSRL[3:1] flag setting condition also generate a long ACK pulse. Subsequent commands that are executed correctly generate a normal ACK pulse. Subsequent commands that are not correctly executed generate a long ACK pulse. The first ACK pulse after WAIT or STOP have been set also generates a long ACK. Subsequent ACK pulses are normal, whilst STOP and WAIT remain set. Long ACK pulses are not immediately generated if an overrun condition is caused by the host driving the BKGD pin low whilst a target ACK is pending, because this would conflict with an attempted host transmission following the BKGD edge. When a whole byte has been received following the offending BKGD edge, the OVRUN bit is still set, forcing subsequent ACK pulses to be long. Unimplemented BDC opcodes causing the ILLCMD bit to be set do not generate a long ACK because this could conflict with further transmission from the host. If the ILLCMD is set for another reason, then a long ACK is generated for the current command if it is a BDC command with ACK. Register Address: This register is not in the device memory map. It is accessible using BDC inherent addressing commands 7 6 54 3 2 1 0 R WAIT STOP RAMWF OVRUN NORESP RDINV ILLACC ILLCMD W Reset 0 0 00 0 0 0 0 Table 5-6. BDCCSRL Field Descriptions Field Description WAIT WAIT Indicator Flag — Indicates that the device entered wait mode. Writing a “1” to this bit whilst in wait mode has no effect. Writing a “1” after exiting wait mode, clears the bit.
0 Device did not enter wait mode
1 Device entered wait mode. STOP STOP Indicator Flag — Indicates that the CPU requested stop mo de following a STOP instruction. Writing a “1” to this bit whilst not in stop mode clears the bit. Writing a “1” to this bit whilst in stop mode has no effect. This bit can only be set when the BDC is enabled.
0 Device did not enter stop mode
1 Device entered stop mode. RAMWF RAM Write Fault — Indicates an ECC double fault during a BDC write access to RAM. Writing a “1” to this bit, clears the bit. 0 No RAM write double fault detected. 1 RAM write double fault detected.
Chapter 5 Background Debug Controller (S12ZBDCV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 151 OVRUN Overrun Flag — Indicates unexpected host activity before command completion. This occurs if a new command is received before the current command completion. With ACK enabled this also occurs if the host drives the BKGD pin low whilst a target ACK pulse is pending To protect internal resources from misinterpreted BDC accesses following an overrun, internal accesses are suppressed until a SYNC clears this bit. A SYNC clears the bit. 0 No overrun detected. 1 Overrun detected when issuing a BDC command. NORESP No Response Flag — Indicates that the BDC internal action or data access did not complete. This occurs in the following scenarios: a) If no free cycle for an access is found within 512 core clock cycles. This could typically happen if a code loop without free cycles is executing with ACK enabled and STEAL clear. b) With ACK disabled or STEAL set, when an internal access is not complete before the host starts data/BDCCSRL retrieval or an internal write access is not complete before the host starts the next BDC command. c) Attempted internal memory or SYNC_PC accesses during STOP mode set NORESP if BDCCIS is clear. In the above cases, on setting NORESP, the BDC aborts the access if permitted. (For devices supporting EWAIT, BDC external accesses with EWAIT assertions, prevent a command from being aborted until EWAIT is deasserted). d) If a BACKGROUND command is issued whilst the device is in wait mode the NORESP bit is set but the command is not aborted. The active BDM request is completed when the device leaves wait mode. Furthermore subsequent CPU register access commands during wait mode set the NORESP bit, should it have been cleared. e) If a command is issued whilst awaiting return from Wait mode. This can happen when using STEP1 to step over a CPU WAI instruction, if the CPU has not returned from Wait mode before the next BDC command is received. f) If STEP1 is issued with the BDC enabled as the device enters Wait mode regardless of the BDMACT state. When NORESP is set a value of 0xEE is returned for each data byte associated with the current access. Writing a “1” to this bit, clears the bit. 0 Internal action or data access completed. 1 Internal action or data access did not complete. RDINV Read Data Invalid Flag — Indicates invalid read data due to an ECC error during a BDC initiated read access. The access returns the actual data read from the location. Writing a “1” to this bit, clears the bit. 0 No invalid read data detected. 1 Invalid data returned during a BDC read access. ILLACC Illegal Access Flag — Indicates an attempted i llegal access. This is set in the following cases: When the attempted access addresses unimplemented memory When the access attempts to write to the flash array When a CPU register access is attempted with an invalid CRN (Section 5.4.5.1, “BDC Access Of CPU Registers). Illegal accesses return a value of 0xEE for each data byte Writing a “1” to this bit, clears the bit. 0 No illegal access detected. 1 Illegal BDC access detected. Table 5-6. BDCCSRL Field Descriptions (continued) Field Description
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5.4 Functional Description
5.4.1 Security
If the device resets with the system secured, the device clears the BDCCSR UNSEC bit. In the secure state BDC access is restricted to the BDCCSR register. A mass erase can be requested using the ERASE_FLASH command. If the mass erase is completed successfully, the device programs the security bits to the unsecure state and sets the BDC UNSEC bit. If the mass erase is unsuccessful, the device remains secure and the UNSEC bit is not set. For more information regarding security, please refer to device specific security information.
5.4.2 Enabling BDC And Entering Active BDM
BDM can be activated only after being enabled. BDC is enabled by setting the ENBDC bit in the BDCCSR register, via the single-wire interface, using the command WRITE_BDCCSR. After being enabled, BDM is activated by one of the following1:
- The BDC BACKGROUND command
- A CPU BGND instruction
- The DBG Breakpoint mechanism Alternatively BDM can be activated directly from reset when resetting into Special Single Chip Mode. The BDC is ready for receiving the first command 10 core clock cycles after the deassertion of the internal reset signal. This is delayed relative to the external pin reset as specified in the device reset documentation. On S12Z devices an NVM initialization phase follows reset. During this phase the BDC commands classified as always available are carried out immediately, whereas other BDC commands are subject to delayed response due to the NVM initialization phase. NOTE After resetting into SSC mode, the initial PC address must be supplied by the host using the WRITE_Rn command before issuing the GO command. ILLCMD Illegal Command Flag — Indicates an illegal BDC command. This bit is set in the following cases: When an unimplemented BDC command opcode is received. When a DUMP_MEM{_WS}, FILL_MEM{_WS} or READ_SAME{_WS} is attempted in an illegal sequence. When an active BDM command is received whilst BDM is not active When a non Always-available command is received whilst the BDC is disabled or a flash mass erase is ongoing. When a non Always-available command is received whilst the device is secure Read commands return a value of 0xEE for each data byte Writing a “1” to this bit, clears the bit. 0 No illegal command detected. 1 Illegal BDC command detected. 1. BDM active immediately out of special single-chip reset. Table 5-6. BDCCSRL Field Descriptions (continued) Field Description
Chapter 5 Background Debug Controller (S12ZBDCV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 153 When BDM is activated, the CPU finishes executing the current instruction. Thereafter only BDC commands can affect CPU register contents until the BDC GO command returns from active BDM to user code or a device reset occurs. When BDM is activated by a breakpoint, the type of breakpoint used determines if BDM becomes active before or after execution of the next instruction. NOTE Attempting to activate BDM using a BGND instruction whilst the BDC is disabled, the CPU requires clock cycles for the attempted BGND execution. However BACKGROUND commands issued whilst the BDC is disabled are ignored by the BDC and the CPU execution is not delayed.
5.4.3 Clock Source
The BDC clock source can be mapped to a constant frequency clock source or a PLL based fast clock. The clock source for the BDC is selected by the CLKSW bit as shown in Figure 5-5. The BDC internal clock is named BDCSI clock. If BDCSI clock is mapped to the BDCCLK by CLKSW then the serial interface communication is not affected by bus/core clock frequency changes. If the BDC is mapped to BDCFCLK then the clock is connected to a PLL derived source at device level (typically bus clock), thus can be subject to frequency changes in application. Debugging through frequency changes requires SYNC pulses to re-synchronize. The sources of BDCCLK and BDCFCLK are specified at device level. BDC accesses of internal device resources always use the device core clock. Thus if the ACK handshake protocol is not enabled, the clock frequency relationship must be taken into account by the host. When changing the clock source via the CLKSW bit a minimum delay of 150 cycles at the initial clock speed must elapse before a SYNC can be sent. This guarantees that the start of the next BDC command uses the new clock for timing subsequent BDC communications. Figure 5-5. Clock Switch
5.4.4 BDC Commands
BDC commands can be classified into three types as shown in Table 5-7. BDCSI Clock Core clock CLKSW BDCCLK BDC serial interface and FSM BDC device resource interface BDCFCLK
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Non-intrusive commands are used to read and write target system memory locations and to enter active BDM. Target system memory includes all memory and registers within the global memory map, including external memory. Active background commands are used to read and write all memory locations and CPU resources. Furthermore they allow single stepping through application code and to exit from active BDM. Non-intrusive commands can only be executed when the BDC is enabled and the device unsecure. Active background commands can only be executed when the system is not secure and is in active BDM. Non-intrusive commands do not require the system to be in active BDM for execution, although, they can still be executed in this mode. When executing a non-intrusive command with the ACK pulse handshake protocol disabled, the BDC steals the next bus cycle for the access. If an operation requires multiple cycles, then multiple cycles can be stolen. Thus if stolen cycles are not free cycles, the application code execution is delayed. The delay is negligible because the BDC serial transfer rate dictates that such accesses occur infrequently. For data read commands, the external host must wait at least 16 BDCSI clock cycles after sending the address before attempting to obtain the read data. This is to be certain that valid data is available in the BDC shift register, ready to be shifted out. For write commands, the external host must wait 16 bdcsi cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDC shift register before the write has been completed. The external host must wait at least for 16 bdcsi cycles after a control command before starting any new serial command. Table 5-7. BDC Command Types Command Type Secure Status BDC Status CPU Status Command Set Always-available Secure or Unsecure Enabled or Disabled —
- Read/write access to BDCCSR
- Mass erase flash memory using ERASE_FLASH
- S Y N C
- ACK enable/disable Non-intrusive Unsecure Enabled Code execution allowed
- Read/write access to BDCCSR
- Memory access
- Memory access with status
- Mass erase flash memory using ERASE_FLASH
- Debug register access
- BACKGROUND
- S Y N C
- ACK enable/disable Active background Unsecure Active Code execution halted
- Read/write access to BDCCSR
- Memory access
- Memory access with status
- Mass erase flash memory using ERASE_FLASH
- Debug register access
- Read or write CPU registers
- Single-step the application
- Exit active BDM to return to the application program (GO)
- S Y N C
- ACK enable/disable
Chapter 5 Background Debug Controller (S12ZBDCV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 155 If the ACK pulse handshake protocol is enabled and STEAL is cleared, then the BDC waits for the first free bus cycle to make a non-intrusive access. If no free bus cycle occurs within 512 core clock cycles then the BDC aborts the access, sets the NORESP bit and uses a long ACK pulse to indicate an error condition to the host. Table 5-8 summarizes the BDC command set. The subsequent sections describe each command in detail and illustrate the command structure in a series of packets, each consisting of eight bit times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles in the high state. The time for an 8-bit command is 8 16 target BDCSI clock cycles. The nomenclature below is used to describe the structure of the BDC commands. Commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most significant bit first) / = separates parts of the command d = delay 16 target BDCSI clock cycles (DLY) dack = delay (16 cycles) no ACK; or delay (=> 32 cycles) then ACK.(DACK) ad24 = 24-bit memory address in the host-to-target direction rd8 = 8 bits of read data in the target-to-host direction rd16 = 16 bits of read data in the target-to-host direction rd24 = 24 bits of read data in the target-to-host direction rd32 = 32 bits of read data in the target-to-host direction rd64 = 64 bits of read data in the target-to-host direction rd.sz = read data, size defined by sz, in the target-to-host direction wd8 = 8 bits of write data in the host-to-target direction wd16 = 16 bits of write data in the host-to-target direction wd32 = 32 bits of write data in the host-to-target direction wd.sz = write data, size defined by sz, in the host-to-target direction ss = the contents of BDCCSRL in the target-to-host direction sz = memory operand size (00 = byte, 01 = word, 10 = long) (sz = 11 is reserved and currently defaults to long) crn = core register number, 32-bit data width WS = command suffix signaling the operation is with status Table 5-8. BDC Command Summary Command Mnemonic Command Classification ACK Command Structure Description SYNC Always Available N/A N/A (1) Request a timed reference pulse to determine the target BDC communication speed ACK_DISABLE Always Available No 0x03/d Disable the communication handshake. This command does not issue an ACK pulse. ACK_ENABLE Always Available Yes 0x02/dack Enable the communication handshake. Issues an ACK pulse after the command is executed. BACKGROUND Non-Intrusive Yes 0x04/dack Halt th e CPU if ENBDC is set. Otherwise, ignore as illegal command.
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DUMP_MEM.sz Non-Intrusive Yes (0x32+4 x sz)/dack/ rd.sz Dump (read) memory based on operand size (sz). Used with READ_MEM to dump large blocks of memory. An initial READ_MEM is executed to set up the starting address of the block and to retrieve the first result. Subsequent DUMP_MEM commands retrieve sequential operands. DUMP_MEM.sz_WS Non-Intrusive No (0x33+4 x sz)/d/ ss/rd.sz Dump (read) memory based on operand size (sz) and report status. Used with READ_MEM{_WS} to dump large blocks of memory. An initial READ_MEM{_WS} is executed to set up the starting address of the block and to retrieve the first result. Subsequent DUMP_MEM{_WS} commands retrieve sequential operands. FILL_MEM.sz Non-Intrusive Yes (0x12+4 x sz)/wd.sz/ dack Fill (write) memory based on operand size (sz). Used with WRITE_MEM to fill large blocks of memory. An initial WRITE_MEM is executed to set up the starting address of the block and to write the first operand. Subsequent FILL_MEM commands write sequential operands. FILL_MEM.sz_WS Non-Intrusive No (0x13+4 x sz)/wd.sz/ d/ss Fill (write) memory based on operand size (sz) and report status. Used with WRITE_MEM{_WS} to fill large blocks of memory. An initial WRITE_MEM{_WS} is executed to set up the starting address of the block and to write the first operand. Subsequent FILL_MEM{_WS} commands write sequential operands. GO Active Background Yes 0x08/dack Resume CPU user code execution GO_UNTIL (2) Active Background Yes 0x0C/dack Go to user program. ACK is driven upon returning to active background mode. NOP Non-Intrusive Yes 0x00/dack No operation READ_Rn Active Background Yes (0x60+CRN)/dack/rd32 Read the requested CPU register READ_MEM.sz Non-Intrusive Yes (0x30+4 x sz)/ad24/dack/ rd.sz Read the appropriately-sized (sz) memory value from the location specified by the 24- bit address READ_MEM.sz_WS Non-Intrusive No (0x31 +4 x sz)/ad24/d/ss/rd.sz Read the appropriately-sized (sz) memory value from the location specified by the 24- bit address and report status READ_DBGTB Non-Intrusive Yes (0x07)/dack/rd32/d ack/rd32 Read 64-bits of DBG trace buffer Table 5-8. BDC Command Summary (continued) Command Mnemonic Command Classification ACK Command Structure Description
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5.4.4.1 SYNC
The SYNC command is unlike other BDC commands because the host does not necessarily know the correct speed to use for serial communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host: 1. Ensures that the BKGD pin is high for at leas t 4 cycles of the slowest possible BDCSI clock without reset asserted. 2. Drives the BKGD pin low for at least 128 cy cles of the slowest possible BDCSI clock. 3. Drives BKGD high for a brief speed-up pulse to get a fast rise time. (This speedup pulse is typically one cycle of the host clock which is as fast as the maximum target BDCSI clock). 4. Removes all drive to the BKGD pi n so it reverts to high impedance. 5. Listens to the BKGD pin for the sync response pulse. READ_SAME.sz Non-Intrusive Yes (0x50+4 x sz)/dack/rd .sz Read from location. An initial READ_MEM defines the address, subsequent READ_SAME reads return content of same address READ_SAME.sz_WS Non-Intrusive No (0x 51+4 x sz)/d/ss/rd.sz Read from location. An initial READ_MEM defines the address, subsequent READ_SAME reads return content of same address READ_BDCCSR Always Available No 0x2D/rd16 Read the BDCCSR register SYNC_PC Non-Intrusive Yes 0x01/dack/rd24 Read current PC WRITE_MEM.sz Non-Intrusive Yes (0x10+4 x sz)/ad24/wd.sz/dack Write the appropriately-sized (sz) memory value to the location specified by the 24-bit address WRITE_MEM.sz_WS Non-Intrusive No (0x11+4 x sz)/ad24/wd. sz/d/ss Write the appropriately-sized (sz) memory value to the location specified by the 24-bit address and report status WRITE_Rn Active Background Yes (0x40+CRN)/wd32/dack Write the requested CPU register WRITE_BDCCSR Always Available No 0x0D/wd16 Write the BDCCSR register ERASE_FLASH Always Available No 0x95/d Mass erase internal flash STEP1 (TRACE1) Active Background Yes 0x09/dack Execute one CPU command. 1. The SYNC command is a special operation which does not have a command code. 2. The GO_UNTIL command is identical to the GO command if ACK is not enabled. Table 5-8. BDC Command Summary (continued) Command Mnemonic Command Classification ACK Command Structure Description
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Upon detecting the sync request from the host (which is a much longer low time than would ever occur during normal BDC communications), the target: 1. Discards any incomplete command 2. Waits for BKGD to return to a logic high. 3. Delays 16 cycles to allow the host to stop driving the high speed-up pulse. 4. Drives BKGD low for 128 BDCSI clock cycles. 5. Drives a 1-cycle high speed-up pulse to force a fast rise time on BKGD. 6. Removes all drive to the BKGD pi n so it reverts to high impedance. 7. Clears the OVRRUN flag (if set). The host measures the low time of this 128-cycle SYNC response pulse and determines the correct speed for subsequent BDC communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed and the serial protocol can easily tolerate this speed error. If the SYNC request is detected by the target, any partially executed command is discarded. This is referred to as a soft-reset, equivalent to a timeout in the serial communication. After the SYNC response, the target interprets the next negative edge (issued by the host) as the start of a new BDC command or the start of new SYNC request. A SYNC command can also be used to abort a pending ACK pulse. This is explained in Section 5.4.8, “Hardware Handshake Abort Procedure.
5.4.4.2 ACK_DISABLE
Disables the serial communication handshake protocol. The subsequent commands, issued after the ACK_DISABLE command, do not execute the hardware handshake protocol. This command is not followed by an ACK pulse.
5.4.4.3 ACK_ENABLE
Disable host/target handshake protocol Always Available 0x03 host target D L Y Enable host/target handshake protocol Always Available 0x02 host target D A C K
Chapter 5 Background Debug Controller (S12ZBDCV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 159 Enables the hardware handshake protocol in the serial communication. The hardware handshake is implemented by an acknowledge (ACK) pulse issued by the target MCU in response to a host command. The ACK_ENABLE command is interpreted and executed in the BDC logic without the need to interface with the CPU. An ACK pulse is issued by the target device after this command is executed. This command can be used by the host to evaluate if the target supports the hardware handshake protocol. If the target supports the hardware handshake protocol, subsequent commands are enabled to execute the hardware handshake protocol, otherwise this command is ignored by the target. Table 5-8 indicates which commands support the ACK hardware handshake protocol. For additional information about the hardware handshake protocol, refer to Section 5.4.7, “Serial Interface Hardware Handshake (ACK Pulse) Protocol,” and Section 5.4.8, “Hardware Handshake Abort Procedure.”
5.4.4.4 BACKGROUND
Provided ENBDC is set, the BACKGROUND command causes the target MCU to enter active BDM as soon as the current CPU instruction finishes. If ENBDC is cleared, the BACKGROUND command is ignored. A delay of 16 BDCSI clock cycles is required after the BACKGROUND command to allow the target MCU to finish its current CPU instruction and enter active background mode before a new BDC command can be accepted. The host debugger must set ENBDC before attempting to send the BACKGROUND command the first time. Normally the host sets ENBDC once at the beginning of a debug session or after a target system reset. During debugging, the host uses GO commands to move from active BDM to application program execution and uses the BACKGROUND command or DBG breakpoints to return to active BDM. A BACKGROUND command issued during stop or wait modes cannot immediately force active BDM because the WAI instruction does not end until an interrupt occurs. For the detailed mode dependency description refer to Section 5.1.3.3, “Low-Power Modes. The host can recognize this pending BDM request condition because both NORESP and WAIT are set, but BDMACT is clear. Whilst in wait mode, with the pending BDM request, non-intrusive BDC commands are allowed. Enter active background mode (if enabled) Non-intrusive 0x04 host target D A C K
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DUMP_MEM{_WS} is used with the READ_MEM{_WS} command to access large blocks of memory. An initial READ_MEM{_WS} is executed to set-up the starting address of the block and to retrieve the first result. The DUMP_MEM{_WS} command retrieves subsequent operands. The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register. Subsequent DUMP_MEM{_WS} commands use this address, perform the memory read, increment it by the current operand size, and store the updated address in the temporary register. If the with-status option is specified, DUMP_MEM.sz Read memory specified by debug address register, then increment address Non-intrusive 0x32 Data[7-0] host target D A C K target host 0x36 Data[15-8] Data[7-0] host target D A C K target host target host 0x3A Data[31-24] Data[23-16] Data[15-8] Data[7-0] host target D A C K target host target host target host target host DUMP_MEM.sz_WS Read memory specified by debug address register with status, then increment address Non-intrusive 0x33 BDCCSRL Data[7-0] host target D L Y target host target host 0x37 BDCCSRL Data[15-8] Data[7-0] host target D L Y target host target host target host 0x3B BDCCSRL Data[31-24] Data23-16] Data[15-8] Data[7-0] host target D L Y target host target host target host target host target host
Chapter 5 Background Debug Controller (S12ZBDCV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 161 the BDCCSRL status byte is returned before the read data. This status byte reflects the state after the memory read was performed. If enabled, an ACK pulse is driven before the data bytes are transmitted. The effect of the access size and alignment on the next address to be accessed is explained in more detail in Section 5.4.5.2, “BDC Access Of Device Memory Mapped Resources”. NOTE DUMP_MEM{_WS} is a valid command only when preceded by SYNC, NOP, READ_MEM{_WS}, or another DUMP_MEM{_WS} command. Otherwise, an illegal command response is returned, setting the ILLCMD bit. NOP can be used for inter-command padding without corrupting the address pointer. The size field (sz) is examined each time a DUMP_MEM{_WS} command is processed, allowing the operand size to be dynamically altered. The examples show the DUMP_MEM.B{_WS}, DUMP_MEM.W{_WS} and DUMP_MEM.L{_WS} commands. FILL_MEM.sz Write memory specified by debug address register, then increment address Non-intrusive 0x12 Data[7-0] host target host target D A C K 0x16 Data[15-8] Data[7-0] host target host target host target D A C K 0x1A Data[31-24] Data[23-16] Data[15-8] Data[7-0] host target host target host target host target host target D A C K FILL_MEM.sz_WS Write memory specified by debug address register with status, then increment address Non-intrusive 0x13 Data[7-0] BDCCSRL host target host target D L Y target host
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FILL_MEM{_WS} is used with the WRITE_MEM{_WS} command to access large blocks of memory. An initial WRITE_MEM{_WS} is executed to set up the starting address of the block and write the first datum. If an initial WRITE_MEM{_WS} is not executed before the first FILL_MEM{_WS}, an illegal command response is returned. The FILL_MEM{_WS} command stores subsequent operands. The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register. Subsequent FILL_MEM{_WS} commands use this address, perform the memory write, increment it by the current operand size, and store the updated address in the temporary register. If the with-status option is specified, the BDCCSRL status byte is returned after the write data. This status byte reflects the state after the memory write was performed. If enabled an ACK pulse is generated after the internal write access has been completed or aborted. The effect of the access size and alignment on the next address to be accessed is explained in more detail in Section 5.4.5.2, “BDC Access Of Device Memory Mapped Resources” NOTE FILL_MEM{_WS} is a valid command only when preceded by SYNC, NOP, WRITE_MEM{_WS}, or another FILL_MEM{_WS} command. Otherwise, an illegal command response is returned, setting the ILLCMD bit. NOP can be used for inter command padding without corrupting the address pointer. The size field (sz) is examined each time a FILL_MEM{_WS} command is processed, allowing the operand size to be dynamically altered. The examples show the FILL_MEM.B{_WS}, FILL_MEM.W{_WS} and FILL_MEM.L{_WS} commands. 5.4.4.7 GO This command is used to exit active BDM and begin (or resume) execution of CPU application code. The CPU pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at 0x17 Data[15-8] Data[7-0] BDCCSRL host target host target host target D L Y target host 0x1B Data[31-24] Data[23-16] Data[15-8] Data[7-0] BDCCSRL host target host target host target host target host target D L Y target host Go Non-intrusive 0x08 host target D A C K FILL_MEM.sz_WS
Chapter 5 Background Debug Controller (S12ZBDCV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 163 the current address in the PC. If any register (such as the PC) is altered by a BDC command whilst in BDM, the updated value is used when prefetching resumes. If enabled, an ACK is driven on exiting active BDM. If a GO command is issued whilst the BDM is inactive, an illegal command response is returned and the ILLCMD bit is set.
5.4.4.8 GO_UNTIL
This command is used to exit active BDM and begin (or resume) execution of application code. The CPU pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at the current address in the PC. If any register (such as the PC) is altered by a BDC command whilst in BDM, the updated value is used when prefetching resumes. After resuming application code execution, if ACK is enabled, the BDC awaits a return to active BDM before driving an ACK pulse. timeouts do not apply when awaiting a GO_UNTIL command ACK. If a GO_UNTIL is not acknowledged then a SYNC command must be issued to end the pending GO_UNTIL. If a GO_UNTIL command is issued whilst BDM is inactive, an illegal command response is returned and the ILLCMD bit is set. If ACK handshaking is disabled, the GO_UNTIL command is identical to the GO command.
5.4.4.9 NOP
NOP performs no operation and may be used as a null command where required. Go Until Active Background 0x0C host target D A C K No operation Active Background 0x00 host target D A C K
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5.4.4.10 READ_Rn
This command reads the selected CPU registers and returns the 32-bit result. Accesses to CPU registers are always 32-bits wide, regardless of implemented register width. Bytes that are not implemented return Access Of CPU Registers for the CRN address decoding. If enabled, an ACK pulse is driven before the data bytes are transmitted. If the device is not in active BDM, this command is illegal, the ILLCMD bit is set and no access is performed. Read CPU register Active Background 0x60+CRN Data [31-24] Data [23-16] Data [15-8] Data [7-0] host target D A C K target host target host target host target host READ_MEM.sz Read memory at the specified address Non-intrusive 0x30 Address[23-0] Data[7-0] host target host target D A C K target host 0x34 Address[23-0] Data[15-8] Data[7-0] host target host target D A C K target host target host 0x38 Address[23-0] Data[31-24] Data[23-16] Data[15-8] Data[7-0] host target host target D A C K target host target host target host target host
Chapter 5 Background Debug Controller (S12ZBDCV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 165 Read data at the specified memory address. The address is transmitted as three 8-bit packets (msb to lsb) immediately after the command. The hardware forces low-order address bits to zero longword accesses to ensure these accesses are on 0- modulo-size alignments. Byte alignment details are described in Section 5.4.5.2, “BDC Access Of Device Memory Mapped Resources”. If the with-status option is specified, the BDCCSR status byte is returned before the read data. This status byte reflects the state after the memory read was performed. If enabled, an ACK pulse is driven before the data bytes are transmitted. The examples show the READ_MEM.B{_WS}, READ_MEM.W{_WS} and READ_MEM.L{_WS} commands.
5.4.4.12 READ_DBGTB
This command is only available on devices, where the DBG module includes a trace buffer. Attempted use of this command on devices without a traace buffer return 0x00. Read 64 bits from the DBG trace buffer. Refer to the DBG module description for more detailed information. If enabled an ACK pulse is generated before each 32-bit longword is ready to be read by the host. After issuing the first ACK a timeout is still possible whilst accessing the second 32-bit longword, since this requires separate internal accesses. The first 32-bit longword corresponds to trace buffer line READ_MEM.sz_WS Read memory at the specified address with status Non-intrusive 0x31 Address[23-0] BDCCSRL Data[7-0] host target host target D L Y target host target host 0x35 Address[23-0] BDCCSRL Data [15-8] Data [7-0] host target host target D L Y target host target host target host 0x39 Address[23-0] BDCCSRL Data[31-24] Data[23-16 ] Data [15-8] Data [7-0] host target host target D L Y target host target host target host target host target host Read DBG trace buffer Non-intrusive 0x07 TB Line [31- 24] TB Line [23- 16] TB Line [15- TB Line [7- TB Line [63- 56] TB Line [55- 48] TB Line [47- 40] TB Line [39- 32] host target D A C K target host target host target host target host D A C K target host target host target host target host
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bits[31:0]; the second to trace buffer line bits[63:32]. If ACK handshaking is disabled, the host must wait 16 clock cycles (DLY) after completing the first 32-bit read before starting the second 32-bit read. Read from location defined by the previous READ_MEM. The previous READ_MEM command defines the address, subsequent READ_SAME commands return contents of same address. The example shows the sequence for reading a 16-bit word size. Byte alignment details are described in Section 5.4.5.2, “BDC Access Of Device Memory Mapped Resources”. If enabled, an ACK pulse is driven before the data bytes are transmitted. NOTE READ_SAME{_WS} is a valid command only when preceded by SYNC, NOP, READ_MEM{_WS}, or another READ_SAME{_WS} command. Otherwise, an illegal command response is returned, setting the ILLCMD bit. NOP can be used for inter-command padding without corrupting the address pointer.
5.4.4.14 READ_BDCCSR
READ_SAME Read same location specified by previous READ_MEM{_WS} Non-intrusive 0x54 Data[15-8] Data[7-0] host target D A C K target host target host READ_SAME_WS Read same location specified by previous READ_MEM{_WS} Non-intrusive 0x55 BDCCSRL Data [15-8] Data [7-0] host target D L Y target host target host target host Read BDCCSR Status Register Always Available 0x2D BDCCSR [15:8] BDCCSR [7-0] host target D L Y target host target host
Chapter 5 Background Debug Controller (S12ZBDCV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 167 Read the BDCCSR status register. This command can be executed in any mode.
5.4.4.15 SYNC_PC
This command returns the 24-bit CPU PC value to the host. Unsuccessful SYNC_PC accesses return 0xEE for each byte. If enabled, an ACK pulse is driven before the data bytes are transmitted. The value of 0xEE is returned if a timeout occurs, whereby NORESP is set. This can occur if the CPU is executing the WAI instruction, or the STOP instruction with BDCCIS clear, or if a CPU access is delayed by EWAIT. If the CPU is executing the STOP instruction and BDCCIS is set, then SYNC_PC returns the PC address of the instruction following STOP in the code listing. This command can be used to dynamically access the PC for performance monitoring as the execution of this command is considerably less intrusive to the real-time operation of an application than a BACKGROUND/read-PC/GO command sequence. Whilst the BDC is not in active BDM, SYNC_PC returns the PC address of the instruction currently being executed by the CPU. In active BDM, SYNC_PC returns the address of the next instruction to be executed on returning from active BDM. Thus following a write to the PC in active BDM, a SYNC_PC returns that written value. Sample current PC Non-intrusive 0x01 PC data[23–16] PC data[15–8] PC data[7–0] host target D A C K target host target host target host
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Write data to the specified memory address. The address is transmitted as three 8-bit packets (msb to lsb) immediately after the command. If the with-status option is specified, the status byte contained in BDCCSRL is returned after the write data. This status byte reflects the state after the memory write was performed. The examples show the WRITE_MEM.B{_WS}, WRITE_MEM.W{_WS}, and WRITE_MEM.L{_WS} commands. If enabled an ACK pulse is generated after the internal write access has been completed or aborted. WRITE_MEM.sz Write memory at the specified address Non-intrusive 0x10 Address[23-0] Data[7–0] host target host target host target D A C K 0x14 Address[23-0] Data[15–8] Data[7–0] host target host target host target host target D A C K 0x18 Address[23-0] Data[31–24] Da ta[23–16] Data[15–8] Data[7–0] host target host target host target host target host target host target D A C K WRITE_MEM.sz_WS Write memory at the specified address with status Non-intrusive 0x11 Address[23-0] Data[7–0] BDCCSRL host target host target host target D L Y target host 0x15 Address[23-0] Data[15–8] Data[7–0] BDCCSRL host target host target host target host target D L Y target host 0x19 Address[23-0] Data[31–24] Da ta[23–16] Data[15–8] Data[7–0] BDCCSRL host target host target host target host target host target host target D L Y target host
Chapter 5 Background Debug Controller (S12ZBDCV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 169 The hardware forces low-order address bits to zero longword accesses to ensure these accesses are on 0- modulo-size alignments. Byte alignment details are described in Section 5.4.5.2, “BDC Access Of Device Memory Mapped Resources”.
5.4.4.17 WRITE_Rn
If the device is in active BDM, this command writes the 32-bit operand to the selected CPU general- CPU registers are always 32-bits wide, regardless of implemented register width. If enabled an ACK pulse is generated after the internal write access has been completed or aborted. If the device is not in active BDM, this command is rejected as an illegal operation, the ILLCMD bit is set and no operation is performed.
5.4.4.18 WRITE_BDCCSR
16-bit write to the BDCCSR register. No ACK pulse is generated. Writing to this register can be used to configure control bits or clear flag bits. Refer to the register bit descriptions.
5.4.4.19 ERASE_FLASH
Mass erase the internal flash. This command can always be issued. On receiving this command twice in succession, the BDC sets the ERASE bit in BDCCSR and requests a flash mass erase. Any other BDC command following a single ERASE_FLASH initializes the sequence, such that thereafter the Write general-purpose CPU register Active Background 0x40+CRN Data [31–24] Data [23–16] Data [15–8] Data [7–0] host target host target host target host target host target D A C K Write BDCCSR Always Available 0x0D BDCCSR Data [15-8] BDCCSR Data [7-0] host target D L Y host target host target Erase FLASH Always Available 0x95 host target D L Y
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ERASE_FLASH must be applied twice in succession to request a mass erase. If 512 BDCSI clock cycles elapse between the consecutive ERASE_FLASH commands then a timeout occurs, which forces a soft reset and initializes the sequence. The ERASE bit is cleared when the mass erase sequence has been completed. No ACK is driven. During the mass erase operation, which takes many clock cycles, the command status is indicated by the ERASE bit in BDCCSR. Whilst a mass erase operation is ongoing, Always-available commands can be issued. This allows the status of the erase operation to be polled by reading BDCCSR to determine when the operation is finished. The status of the flash array can be verified by subsequently reading the flash error flags to determine if the erase completed successfully. ERASE_FLASH can be aborted by a SYNC pulse forcing a soft reset. NOTE: Device Bus Frequency Considerations The ERASE_FLASH command requires the default device bus clock frequency after reset. Thus the bus clock frequency must not be changed following reset before issuing an ERASE_FLASH command.
5.4.4.20 STEP1
This command is used to step through application code. In active BDM this command executes the next CPU instruction in application code. If enabled an ACK is driven. If a STEP1 command is issued and the CPU is not halted, the command is ignored.
5.4.5 BDC Access Of Internal Resources
Unsuccessful read accesses of internal resources return a value of 0xEE for each data byte. This enables a debugger to recognize a potential error, even if neither the ACK handshaking protocol nor a status command is currently being executed. The value of 0xEE is returned in the following cases.
- Illegal address access, whereby ILLACC is set
- Invalid READ_SAME or DUMP_MEM sequence
- Invalid READ_Rn command (BDM inactive or CRN incorrect)
- Internal resource read with timeout, whereby NORESP is set Step1 Active Background 0x09 host target D A C K
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5.4.5.1 BDC Access Of CPU Registers
The CRN field of the READ_Rn and WRITE_Rn commands contains a pointer to the CPU registers. The mapping of CRN to CPU registers is shown in Table 5-9. Accesses to CPU registers are always 32-bits wide, regardless of implemented register width. This means that the BDC data transmission for these commands is 32-bits long. The valid bits of the transfer are listed in the Valid Data Bits column. The other bits of the transmission are redundant. Attempted accesses of CPU registers using a CRN of 0xD,0xE or 0xF is invalid, returning the value 0xEE for each byte and setting the ILLACC bit.
5.4.5.2 BDC Access Of Devi ce Memory Mapped Resources
The device memory map is accessed using READ_MEM, DUMP_MEM, WRITE_MEM, FILL_MEM and READ_SAME, which support different access sizes, as explained in the command descriptions. When an unimplemented command occurs during a DUMP_MEM, FILL_MEM or READ_SAME sequence, then that sequence is ended. Illegal read accesses return a value of 0xEE for each byte. After an illegal access FILL_MEM and READ_SAME commands are not valid, and it is necessary to restart the internal access sequence with READ_MEM or WRITE_MEM. An illegal access does not break a DUMP_MEM sequence. After read accesses that cause the RDINV bit to be set, DUMP_MEM and READ_SAME commands are valid, it is not necessary to restart the access sequence with a READ_MEM. The hardware forces low-order address bits to zero for longword accesses to ensure these accesses are realigned to 0-modulo-size alignments. Word accesses map to 2-bytes from within a 4-byte field as shown in Table 5-10. Thus if address bits [1:0] are both logic “1” the access is realigned so that it does not straddle the 4-byte boundary but accesses data from within the addressed 4-byte field. Table 5-9. CPU Register Number (CRN) Mapping CPU Register Valid Data Bits Command Opcode Command Opcode D0 [7:0] WRITE_D0 0x40 READ_D0 0x60 D1 [7:0] WRITE_D1 0x41 READ_D1 0x61 D2 [15:0] WRITE_D2 0x42 READ_D2 0x62 D3 [15:0] WRITE_D3 0x43 READ_D3 0x63 D4 [15:0] WRITE_D4 0x44 READ_D4 0x64 D5 [15:0] WRITE_D5 0x45 READ_D5 0x65 D6 [31:0] WRITE_D6 0x46 READ_D6 0x66 D7 [31:0] WRITE_D7 0x47 READ_D7 0x67 X [23:0] WRITE_X 0x48 READ_X 0x68 Y [23:0] WRITE_Y 0x49 READ_Y 0x69 SP [23:0] WRITE_SP 0x4A READ_SP 0x6A PC [23:0] WRITE_PC 0x4B READ_PC 0x6B CCR [15:0] WRITE_CCR 0x4C READ_CCR 0x6C
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Table 5-10. Field Location to Byte Access Mapping
5.4.5.2.1 FILL_MEM and DUMP_MEM Increments and Alignment
FILL_MEM and DUMP_MEM increment the previously accessed address by the previous access size to calculate the address of the current access. On misaligned longword accesses, the address bits [1:0] are forced to zero, therefore the following FILL_MEM or DUMP_MEM increment to the first address in the next 4-byte field. This is shown in Table 5-11, the address of the first DUMP_MEM.32 following READ_MEM.32 being calculated from 0x004000+4. When misaligned word accesses are realigned, then the original address (not the realigned address) is incremented for the following FILL_MEM, DUMP_MEM command. Misaligned word accesses can cause the same locations to be read twice as shown in rows 6 and 7. The hardware ensures alignment at an attempted misaligned word access across a 4-byte boundary, as shown in row 7. The following word access in row 8 continues from the realigned address of row 7. d Address[1:0] Access Size 00 01 10 11 Note 00 32-bit Data[31:24] Data[23:16] Data [15:8] Data [7:0] 01 32-bit Data[31:24] Data[23:16] Data [15:8] Data [7:0] Realigned 10 32-bit Data[31:24] Data[23:16] Data [15:8] Data [7:0] Realigned 11 32-bit Data[31:24] Data[23:16] Data [15:8] Data [7:0] Realigned 00 16-bit Data [15:8] Data [7:0] 01 16-bit Data [15:8] Data [7:0] 10 16-bit Data [15:8] Data [7:0] 11 16-bit Data [15:8] Data [7:0] Realigned 00 8-bit Data [7:0] 01 8-bit Data [7:0] 10 8-bit Data [7:0] 11 8-bit Data [7:0] Denotes byte that is not transmitted Table 5-11. Consecutive Accesses With Variable Size Row Command Address Address[1:0] 00 01 10 11 1 READ_MEM.32 0x004003 11 Acce ssed Accessed Accessed Accessed 2 DUMP_MEM.32 0x004004 00 Acce ssed Accessed Accessed Accessed 3 DUMP_MEM.16 0x004008 00 Accessed Accessed 4 DUMP_MEM.16 0x00400A 10 Accessed Accessed 5 DUMP_MEM.08 0x00400C 00 Accessed 6 DUMP_MEM.16 0x00400D 01 Accessed Accessed 7 DUMP_MEM.16 0x00400E 10 Accessed Accessed 8 DUMP_MEM.16 0x004010 01 Accessed Accessed
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5.4.5.2.2 READ_SAME Effect s Of Variable Access Size
READ_SAME uses the unadjusted address given in the previous READ_MEM command as a base address for subsequent READ_SAME commands. When the READ_MEM and READ_SAME size parameters differ then READ_SAME uses the original base address buts aligns 32-bit and 16-bit accesses, where those accesses would otherwise cross the aligned 4-byte boundary. Table 5-12 shows some examples of this. d
5.4.6 BDC Serial Interface
The BDC communicates with external devices serially via the BKGD pin. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the BDC. The BDC serial interface uses an internal clock source, selected by the CLKSW bit in the BDCCSR register. This clock is referred to as the target clock in the following explanation. Table 5-12. Consecutive READ_SAME Accesses With Variable Size Row Command Base Address 00 01 10 11 1 READ_MEM.32 0x004003 Acce ssed Accessed Accessed Accessed 2 READ_SAME.32 — Accessed A ccessed Accessed Accessed 3 READ_SAME.16 — Accessed Accessed 4 READ_SAME.08 — Accessed 5 READ_MEM.08 0x004000 Accessed 6 READ_SAME.08 — Accessed 7 READ_SAME.16 — Accessed Accessed 8 READ_SAME.32 — Accessed A ccessed Accessed Accessed 9 READ_MEM.08 0x004002 Accessed 10 READ_SAME.08 — Accessed 11 READ_SAME.16 — Accessed Accessed 12 READ_SAME.32 — Accesse d Accessed Accessed Accessed 13 READ_MEM.08 0x004003 Accessed 14 READ_SAME.08 — Accessed 15 READ_SAME.16 — Accessed Accessed 16 READ_SAME.32 — Accesse d Accessed Accessed Accessed 17 READ_MEM.16 0x004001 Accessed Accessed 18 READ_SAME.08 — Accessed 19 READ_SAME.16 — Accessed Accessed 20 READ_SAME.32 — Accesse d Accessed Accessed Accessed 21 READ_MEM.16 0x004003 Accessed Accessed 22 READ_SAME.08 — Accessed 23 READ_SAME.16 — Accessed Accessed 24 READ_SAME.32 — Accesse d Accessed Accessed Accessed
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The BDC serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per bit. The interface times out if during a command 512 clock cycles occur between falling edges from the host. The timeout forces the current command to be discarded. The BKGD pin is a pseudo open-drain pin and has a weak on-chip active pull-up that is enabled at all times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide brief drive-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host for transmit cases and the target for receive cases. The timing for host-to-target is shown in Figure 5-6 and that of target-to-host in Figure 5-7 and Figure 5-8. All cases begin when the host drives the BKGD pin low to generate a falling edge. Since the host and target operate from separate clocks, it can take the target up to one full clock cycle to recognize this edge; this synchronization uncertainty is illustrated in Figure 5-6. The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle earlier. Synchronization between the host and target is established in this manner at the start of every bit time. Figure 5-6 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic requires the pin be driven high no later than eight target clock cycles after the falling edge for a logic 1 transmission. Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals. Figure 5-6. BDC Host-to-Target Serial Bit Timing Figure 5-7 shows the host receiving a logic 1 from the target system. The host holds the BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must release the low EARLIEST START TARGET SENSES BIT LEVEL
10 CYCLES
(TARGET MCU) HOST TRANSMIT 1 HOST TRANSMIT 0 PERCEIVED START OF BIT TIME OF NEXT BIT
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Figure 5-8. BDC Target-to-Host Serial Bit Timing (Logic 0)
5.4.7 Serial Interface Hardware Ha ndshake (ACK Pulse) Protocol
BDC commands are processed internally at the device core clock rate. Since the BDCSI clock can be asynchronous relative to the bus frequency, a handshake protocol is provided so the host can determine when an issued command has been executed. This section describes the hardware handshake protocol. The hardware handshake protocol signals to the host controller when a BDC command has been executed by the target. This protocol is implemented by a low pulse (16 BDCSI clock cycles) followed by a brief speedup pulse on the BKGD pin, generated by the target MCU when a command, issued by the host, has been successfully executed (see Figure 5-9). This pulse is referred to as the ACK pulse. After the ACK pulse has finished, the host can start the bit retrieval if the last issued command was a read command, or start a new command if the last command was a write command or a control command. Figure 5-9. Target Acknowledge Pulse (ACK) (TARGET MCU) HOST DRIVE TO BKGD PIN TARGET MCU DRIVE AND PERCEIVED START OF BIT TIME HIGH-IMPEDANCE BKGD PIN
16 CYCLES
(TARGET MCU) TARGET TRANSMITS HIGH-IMPEDANCE BKGD PIN HIGH-IMPEDANCE MINIMUM DELAY FROM THE BDC COMMAND
32 CYCLES
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The ACK handshake protocol does not support nested ACK pulses. If a BDC command is not acknowledged by an ACK pulse, the host needs to abort the pending command first in order to be able to issue a new BDC command. The host can decide to abort any possible pending ACK pulse in order to be sure a new command can be issued. Therefore, the protocol provides a mechanism in which a command, and its corresponding ACK, can be aborted. Commands With-Status do not generate an ACK, thus if ACK is enabled and a With-Status command is issued, the host must use the 512 cycle timeout to calculate when the data is ready for retrieval.
5.4.7.1 Long-ACK Hardware Handshake Protocol
If a command results in an error condition, whereby a BDCCSRL flag is set, then the target generates a “Long-ACK” low pulse of 64 BDCSI clock cycles, followed by a brief speed pulse. This indicates to the host that an error has occurred. The host can subsequently read BDCCSR to determine the type of error. Whether normal ACK or Long-ACK, the ACK pulse is not issued earlier than 32 BDCSI clock cycles after the BDC command was issued. The end of the BDC command is assumed to be the 16th BDCSI clock cycle of the last bit. The 32 cycle minimum delay differs from the 16 cycle delay time with ACK disabled. If a BDC access request does not gain access within 512 core clock cycles, the request is aborted, the NORESP flag is set and a Long-ACK pulse is transmitted to indicate an error case. Following a STOP or WAI instruction, if the BDC is enabled, the first ACK, following stop or wait mode entry is a long ACK to indicate an exception.
5.4.8 Hardware Handsh ake Abort Procedure
The abort procedure is based on the SYNC command. To abort a command that has not responded with an ACK pulse, the host controller generates a sync request (by driving BKGD low for at least 128 BDCSI clock cycles and then driving it high for one BDCSI clock cycle as a speedup pulse). By detecting this long low pulse in the BKGD pin, the target executes the SYNC protocol, see Section 5.4.4.1, “SYNC”, and assumes that the pending command and therefore the related ACK pulse are being aborted. After the SYNC protocol has been completed the host is free to issue new BDC commands. The host can issue a SYNC close to the 128 clock cycles length, providing a small overhead on the pulse Figure 5-11 shows a SYNC command being issued after a READ_MEM, which aborts the READ_MEM command. Note that, after the command is aborted a new command is issued by the host.
Chapter 5 Background Debug Controller (S12ZBDCV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 179 Figure 5-11. ACK Abort Procedure at the Command Level (Not To Scale) Figure 5-12 shows a conflict between the ACK pulse and the SYNC request pulse. The target is executing a pending BDC command at the exact moment the host is being connected to the BKGD pin. In this case, an ACK pulse is issued simultaneously to the SYNC command. Thus there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. As this is not a probable situation, the protocol does not prevent this conflict from happening. Figure 5-12. ACK Pulse and SYNC Request Conflict
5.4.9 Hardware Handshake Disa bled (ACK Pulse Disabled)
The default state of the BDC after reset is hardware handshake protocol disabled. It can also be disabled by the ACK_DISABLE BDC command. This provides backwards compatibility with the existing host devices which are not able to execute the hardware handshake protocol. For host devices that support the hardware handshake protocol, true non-intrusive debugging and error flagging is offered. If the ACK pulse protocol is disabled, the host needs to use the worst case delay time at the appropriate places in the protocol. READ_MEM.B READ_BDCCSRBKGD PIN ADDRESS[23-0] HOST TARGET BDC DECODES READ_MEM.B CMD IS ABORTED BY THE SYNC REQUEST NEW BDC COMMAND AND TRYS TO EXECUTE HOST TARGET HOST TARGET SYNC RESPONSE FROM THE TARGET NEW BDC COMMAND (NOT TO SCALE) (NOT TO SCALE) BDCSI clock (TARGET MCU) TARGET MCU DRIVES TO BKGD PIN BKGD PIN
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If the handshake protocol is disabled, the access is always independent of free cycles, whereby BDC has higher priority than CPU. Since at least 2 bytes (command byte + data byte) are transferred over BKGD the maximum intrusiveness is only once every few hundred cycles. After decoding an internal access command, the BDC then awaits the next internal core clock cycle. The relationship between BDCSI clock and core clock must be considered. If the host retrieves the data immediately, then the BDCSI clock frequency must not be more than 4 times the core clock frequency, in order to guarantee that the BDC gains bus access within 16 the BDCSI cycle DLY period following an access command. If the BDCSI clock frequency is more than 4 times the core clock frequency, then the host must use a suitable delay time before retrieving data (see 5.5.1/5-181). Furthermore, for stretched read accesses to external resources via a device expanded bus (if implemented) the potential extra stretch cycles must be taken into consideration before attempting to obtain read data. If the access does not succeed before the host starts data retrieval then the NORESP flag is set but the access is not aborted. The NORESP state can be used by the host to recognize an unexpected access conflict due to stretched expanded bus accesses. Although the NORESP bit is set when an access does not succeed before the start of data retrieval, the access may succeed in following bus cycles if the internal access has already been initiated.
5.4.10 Single Stepping
When a STEP1 command is issued to the BDC in active BDM, the CPU executes a single instruction in the user code and returns to active BDM. The STEP1 command can be issued repeatedly to step through the user code one instruction at a time. If an interrupt is pending when a STEP1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. In this case the stacking counts as one instruction. The device re-enters active BDM with the program counter pointing to the first instruction in the interrupt service routine. When stepping through the user code, the execution of the user code is done step by step but peripherals are free running. Some peripheral modules include a freeze feature, whereby their clocks are halted when the device enters active BDM. Timer modules typically include the freeze feature. Serial interface modules typically do not include the freeze feature. Hence possible timing relations between CPU code execution and occurrence of events of peripherals no longer exist. If the handshake protocol is enabled and BDCCIS is set then stepping over the STOP instruction causes the Long-ACK pulse to be generated and the BDCCSR STOP flag to be set. When stop mode is exited due to an interrupt the device enters active BDM and the PC points to the start of the corresponding interrupt service routine. Stepping can be continued. Stepping over a WAI instruction, the STEP1 command cannot be finished because active BDM cannot be entered after CPU starts to execute the WAI instruction. Stepping over the WAI instruction causes the BDCCSR WAIT and NORESP flags to be set and, if the handshake protocol is enabled, then the Long-ACK pulse is generated. Then the device enters wait mode, clears the BDMACT bit and awaits an interrupt to leave wait mode. In this time non-intrusive BDC commands are possible, although the STEP1 has actually not finished. When an interrupt occurs the device leaves wait mode, enters active BDM and the PC points to the start of the corresponding interrupt service routine. A further ACK related to stepping over the WAI is not generated.
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5.4.11 Serial Communication Timeout
The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command was issued. In this case, the target waits for a rising edge on BKGD in order to answer the SYNC request pulse. When the BDC detects the rising edge a soft reset is generated, whereby the current BDC command is discarded. If the rising edge is not detected, the target keeps waiting forever without any timeout limit. If a falling edge is not detected by the target within 512 clock cycles since the last falling edge, a timeout occurs and the current command is discarded without affecting memory or the operating mode of the MCU. This is referred to as a soft-reset. This timeout also applies if 512 cycles elapse between 2 consecutive ERASE_FLASH commands. The soft reset is disabled whilst the internal flash mass erase operation is pending completion. timeouts are also possible if a BDC command is partially issued, or data partially retrieved. Thus if a time greater than 512 BDCSI clock cycles is observed between two consecutive negative edges, a soft-reset occurs causing the partially received command or data retrieved to be discarded. The next negative edge at the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDC command, or the start of a SYNC request pulse.
5.5 Application Information
5.5.1 Clock Frequency Considerations
Read commands without status and without ACK must consider the frequency relationship between BDCSI and the internal core clock. If the core clock is slow, then the internal access may not have been carried out within the standard 16 BDCSI cycle delay period (DLY). The host must then extend the DLY period or clock frequencies accordingly. Taking internal clock domain synchronizers into account, the minimum number of BDCSI periods required for the DLY is expressed by: #DLY > 3(f(BDCSI clock) / f(core clock)) + 4 and the minimum core clock frequency with respect to BDCSI clock frequency is expressed by Minimum f(core clock) = (3/(#DLY cycles -4))f(BDCSI clock) For the standard 16 period DLY this yields f(core clock)>= (1/4)f(BDCSI clock)
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MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductor 183 Chapter 6 S12Z DebugLite (S12ZDBGV3) Module
6.1 Introduction
The DBG module provides on-chip breakpoints with flexible triggering capability to allow non-intrusive debug of application software. The DBG module is optimized for the S12Z architecture and allows debugging of CPU module operations. Typically the DBG module is used in conjunction with the BDC module, whereby the user configures the DBG module for a debugging session over the BDC interface. Once configured the DBG module is armed and the device leaves active BDM returning control to the user program, which is then monitored by the DBG module. Alternatively the DBG module can be configured over a serial interface using SWI routines. Table 6-1. Revision History Table Revision Number Revision Date Sections Affected Description Of Changes 3.00 23.MAY.2012 General Updated for DBGV3 using conditional text 3.01 27.JUN.2012 General Added Lite to module na me. Corrected DBGEFR register format issue “Debug Event Flag Register (DBGEFR) Removed ME2 flag from DBGEFR “Avoiding Unintended Breakpoint Re- triggering Modified step over breakpoint information 3.04 19.DEC.2012 General Formatting corrections 3.05 19.APR.2013 General Specified DB GC1[0] reserved bit as read only “Register Descriptions Added explicit names to state control register bit fields
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6.1.1 Glossary
6.1.2 Overview
The comparators monitor the bus activity of the CPU. A single comparator match or a series of matches can generate breakpoints. A state sequencer determines if the correct series of matches occurs. Similarly an external event can generate breakpoints.
6.1.3 Features
- Three comparators (A, B, and D) — Comparator A compares the full a ddress bus and full 32-bit data bus — Comparator A features a data bus mask register — Comparators B and D compar e the full address bus only — Each comparator can be configured to monitor PC addresses or addresses of data accesses — Each comparator can select eith er read or write access cycles — Comparator matches can force st ate sequencer state transitions
- Three comparator modes — Simple address/data co mparator match mode — Inside address range mode, Addmin Address Addmax — Outside address range match mode, Address Addminor Address Addmax
- State sequencer control — State transitions forced by comparator matches — State transitions forced by software write to TRIG — State transitions forced by an external event
- The following types of breakpoints — CPU breakpoint entering acti ve BDM on breakpoint (BDM) — CPU breakpoint executing SWI on breakpoint (SWI) Table 6-2. Glossary Of Terms Term Definition COF Change Of Flow. Change in the program flow due to a conditional branch, indexed jump or interrupt PC Program Counter BDM Background Debug Mode. In this mode CPU application code execution is halted. Execution of BDC “active BDM” commands is possible. BDC Background Debug Controller WORD 16-bit data entity CPU S12Z CPU module
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6.1.4 Modes of Operation
The DBG module can be used in all MCU functional modes. The DBG module can issue breakpoint requests to force the device to enter active BDM or an SWI ISR. The BDC BACKGROUND command is also handled by the DBG to force the device to enter active BDM. When the device enters active BDM through a BACKGROUND command with the DBG module armed, the DBG remains armed.
6.1.5 Block Diagram
B Figure 6-1. Debug Module Block Diagram
6.2 External Signal Description
6.2.1 External Event Input
The DBG module features an external event input signal, DBGEEV . The mapping of this signal to a device pin is specified in the device specific documentation. This function can be enabled and configured by the EEVE field in the DBGC1 control register. This signal is input only and allows an external event to force a state sequencer transition. With the external event function enabled, a falling edge at the external event pin constitutes an event. Rising edges have no effect. The maximum frequency of events is half the internal core bus frequency. The function is explained in the EEVE field description. NOTE Due to input pin synchronization circuitry, the DBG module sees external events 2 bus cycles after they occur at the pin. Thus an external event occurring less than 2 bus cycles before arming the DBG module is perceived to occur whilst the DBG is armed. CPU BUS BUS INTERFACE MATCH0 COMPARATOR B COMPARATOR D COMPARATOR A STATE SEQUENCER MATCH1 MATCH3 BREAKPOINT COMPARATOR MATCH CONTROL AND EVENT CONTROL REQUESTS REGISTERS TRIG EXTERNAL EVENT
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When the device is in stop mode the synchronizer clocks are disabled and the external events are ignored.
6.3 Memory Map and Registers
6.3.1 Module Memory Map
A summary of the registers associated with the DBG module is shown in Figure 6-2. Detailed descriptions of the registers and bits are given in the subsections that follow. Address Name Bit 7 6 5 4 3 2 1 Bit 0 0x0100 DBGC1 R ARM 0 reserved BDMBP BRKCPU reserved EEVE1 0 WT R I G 0x0101 DBGC2 R 000000 ABCMW 0x0102 Reserved R 00000000 W 0x0103 Reserved R 00000000 W 0x0104 Reserved R 00000000 W 0x0105 Reserved R 00000000 W 0x0106 Reserved R 00000000 W 0x0107 DBGSCR1 R C3SC1 C3SC0 00 C1SC1 C1SC0 C0SC1 C0SC0W 0x0108 DBGSCR2 R C3SC1 C3SC0 00 C1SC1 C1SC0 C0SC1 C0SC0W 0x0109 DBGSCR3 R C3SC1 C3SC0 00 C1SC1 C1SC0 C0SC1 C0SC0W 0x010A DBGEFR R 0 TRIGF 0 EEVF ME3 0 ME1 ME0 W 0x010B DBGSR R 0 0 0 0 0 SSF2 SSF1 SSF0 W 0x010C- 0x010F Reserved R 00000000 W 0x0110 DBGACTL R0 NDB INST 0 RW RWE reserved COMPEW Figure 6-2. Quick Reference to DBG Registers
Chapter 6 S12Z DebugLite (S12ZDBGV3) Module MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 187 0x0111- 0x0114 Reserved R 00000000 W 0x0115 DBGAAH R DBGAA[23:16]W 0x0116 DBGAAM R DBGAA[15:8]W 0x0117 DBGAAL R DBGAA[7:0]W 0x0118 DBGAD0 R Bit 31 30 29 28 27 26 25 Bit 24W 0x0119 DBGAD1 R Bit 23 22 21 20 19 18 17 Bit 16W 0x011A DBGAD2 R Bit 15 14 13 12 11 10 9 Bit 8W 0x011B DBGAD3 R B i t 7 654321 B i t 0W 0x011C DBGADM0 R Bit 31 30 29 28 27 26 25 Bit 24W 0x011D DBGADM1 R Bit 23 22 21 20 19 18 17 Bit 16W 0x011E DBGADM2 R Bit 15 14 13 12 11 10 9 Bit 8W 0x011F DBGADM3 R B i t 7 654321 B i t 0W 0x0120 DBGBCTL R0 0 INST 0 RW RWE reserved COMPEW 0x0121- 0x0124 Reserved R 00000000 W 0x0125 DBGBAH R DBGBA[23:16]W 0x0126 DBGBAM R DBGBA[15:8]W 0x0127 DBGBAL R DBGBA[7:0]W 0x0128- 0x012F Reserved R 00000000 W 0x0130- 0x013F Reserved R 00000000 W Address Name Bit 7 6 5 4 3 2 1 Bit 0 Figure 6-2. Quick Reference to DBG Registers
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6.3.2 Register Descriptions
This section consists of the DBG register descriptions in address order. When ARM is set in DBGC1, the only bits in the DBG module registers that can be written are ARM, and TRIG
6.3.2.1 Debug Control Register 1 (DBGC1)
Read: Anytime Write: Bit 7 Anytime . An ongoing profiling session must be finished before DBG can be armed again. Bit 6 can be written anytime but always reads back as 0. Bits 5:0 anytime DBG is not armed. NOTE On a write access to DBGC1 and simultaneous hardware disarm from an internal event, the hardware disarm has highest priority, clearing the ARM bit and generating a breakpoint, if enabled. 0x0140 DBGDCTL R0 0 INST 0 RW RWE reserved COMPEW 0x0141- 0x0144 Reserved R 00000000 W 0x0145 DBGDAH R DBGDA[23:16]W 0x0146 DBGDAM R DBGDA[15:8]W 0x0147 DBGDAL R DBGDA[7:0]W 0x0148- 0x017F Reserved R 00000000 W Address: 0x0100 76543210 0x0100 ARM reserved BDMBP BRKCPU reserved EEVE1 0 TRIG R e s e t 00000000 Figure 6-3. Debug Control Register (DBGC1) Address Name Bit 7 6 5 4 3 2 1 Bit 0 Figure 6-2. Quick Reference to DBG Registers
Chapter 6 S12Z DebugLite (S12ZDBGV3) Module MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 189 NOTE When disarming the DBG by clearing ARM with software, the contents of bits[5:0] are not affected by the write, since up until the write operation, ARM = 1 preventing these bits from being written. These bits must be cleared using a second write if required.
6.3.2.2 Debug Control Register2 (DBGC2)
Read: Anytime. Write: Anytime the module is disarmed. This register configures the comparators for range matching. Table 6-3. DBGC1 Field Descriptions Field Description ARM Arm Bit — The ARM bit controls whether the DBG module is a rmed. This bit can be set and cleared by register writes and is automatically cleared when the state sequencer returns to State0 on completing a debugging session. On setting this bit the state sequencer enters State1. 0 Debugger disarmed. No breakpoint is generated when clearing this bit by software register writes.
1 Debugger armed
Immediate Trigger Request Bit — This bit when written to 1 requests an immediate transition to final state independent of comparator status. This bit always reads back a 0. Writing a 0 to this bit has no effect. 0 No effect. 1 Force state sequencer immediately to final state. BDMBP Background Debug Mode Enable — This bit determines if a CPU br eakpoint causes the system to enter Background Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDC is not enabled, then no breakpoints are generated. 0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint. 1 Breakpoint to BDM, if BDC enab led. Otherwise no breakpoint. BRKCPU CPU Breakpoint Enable — The BRKCPU bit controls whether the debugger requests a breakpoint to CPU upon transitions to State0. Please refer to Section 6.4.5, “Breakpoints for further details.
0 Breakpoints disabled
1 Breakpoints enabled
External Event Enable — The EEVE1 bit enables the external event function. 0 External event function disabled.
1 External event is mapped to the state sequencer, replacing comparator channel 3
Address: 0x0101 76543210 R 000000 ABCMW R e s e t 00000000 = Unimplemented or Reserved Figure 6-4. Debug Control Register2 (DBGC2)
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6.3.2.3 Debug State Control Register 1 (DBGSCR1)
Read: Anytime. Write: If DBG is not armed. The state control register 1 selects the targeted next state whilst in State1. The matches refer to the outputs of the comparator match control logic as depicted in Figure 6-1 and described in Section 6.3.2.8, “Debug Comparator A Control Register (DBGACTL)”. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. Table 6-4. DBGC2 Field Descriptions Field Description 1–0 ABCM[1:0] A and B Comparator Match Control — These bits determine the A and B comparator match mapping as described in Table 6-5. Table 6-5. ABCM Encoding ABCM Description (1) 1. Currently defaults to Match0 mapped to inside range: Match1 disabled Address: 0x0107 76543210 R C3SC1 C3SC0 C1SC1 C1SC0 C0SC1 C0SC0 W R e s e t 00000000 Figure 6-6. Debug State Control Register 1 (DBGSCR1) Table 6-7. DBGSCR1 Field Descriptions Field Description 1–0 C0SC[1:0] Channel 0 State Control. These bits select the targeted next state whilst in State1 following a match0. 3–2 C1SC[1:0] Channel 1 State Control. These bits select the targeted next state whilst in State1 following a match1. 7–6 C3SC[1:0] Channel 3 State Control. If EEVE !=10, these bits select the targeted next state whilst in State1 following a match3. If EEVE = 10, these bits select the targeted next state whilst in State1 following an external event.
Chapter 6 S12Z DebugLite (S12ZDBGV3) Module MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 191 In the case of simultaneous matches, the match on the higher channel number (3...0) has priority.
6.3.2.4 Debug State Control Register 2 (DBGSCR2)
Read: Anytime. Write: If DBG is not armed The state control register 2 selects the targeted next state whilst in State2. The matches refer to the outputs of the comparator match control logic as depicted in Figure 6-1 and described in Section 6.3.2.8, “Debug Comparator A Control Register (DBGACTL)”. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. In the case of simultaneous matches, the match on the higher channel number (3...0) has priority. Table 6-8. State1 Match State Sequencer Transitions CxSC[1:0] Function
00 Match has no effect
01 Match forces sequencer to State2
10 Match forces sequencer to State3
11 Match forces sequencer to Final State
Address: 0x0108 76543210 R C3SC1 C3SC0 C1SC1 C1SC0 C0SC1 C0SC0 W R e s e t 00000000 Figure 6-7. Debug State Control Register 2 (DBGSCR2) Table 6-9. DBGSCR2 Field Descriptions Field Description 1–0 C0SC[1:0] Channel 0 State Control. These bits select the targeted next state whilst in State2 following a match0. 3–2 C1SC[1:0] Channel 1 State Control. These bits select the targeted next state whilst in State2 following a match1. 7–6 C3SC[1:0] Channel 3 State Control. If EEVE !=10, these bits select the targeted next state whilst in State2 following a match3. If EEVE =10, these bits select the targeted next state whilst in State2 following an external event. Table 6-10. State2 Match State Sequencer Transitions CxSC[1:0] Function
01 Match forces sequencer to State1
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6.3.2.5 Debug State Control Register 3 (DBGSCR3)
Read: Anytime. Write: If DBG is not armed. The state control register three selects the targeted next state whilst in State3. The matches refer to the outputs of the comparator match control logic as depicted in Figure 6-1 and described in Section 6.3.2.8, “Debug Comparator A Control Register (DBGACTL)”. Comparators must be enabled by setting the comparator enable bit in the associated DBGxCTL control register.
6.3.2.6 Debug Event Flag Register (DBGEFR)
Address: 0x0109 76543210 R C3SC1 C3SC0 C1SC1 C1SC0 C0SC1 C0SC0 W R e s e t 00000000 Figure 6-8. Debug State Control Register 3 (DBGSCR3) Table 6-11. DBGSCR3 Field Descriptions Field Description 1–0 C0SC[1:0] Channel 0 State Control. These bits select the targeted next state whilst in State3 following a match0. 3–2 C1SC[1:0] Channel 1 State Control. These bits select the targeted next state whilst in State3 following a match1. 7–6 C3SC[1:0] Channel 3 State Control. If EEVE !=10, these bits select the targeted next state whilst in State3 following a match3. If EEVE =10, these bits select the targeted next state whilst in State3 following an external event. Table 6-12. State3 Match State Sequencer Transitions CxSC[1:0] Function
10 Match forces sequencer to State2
Address: 0x010A 76543210 R 0 TRIGF 0 EEVF ME3 0 ME1 ME0 W R e s e t 00000000 = Unimplemented or Reserved Figure 6-9. Debug Event Flag Register (DBGEFR)
Chapter 6 S12Z DebugLite (S12ZDBGV3) Module MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 193 Read: Anytime. Write: Never DBGEFR contains flag bits each mapped to events whilst armed. Should an event occur, then the corresponding flag is set. With the exception of TRIGF, the bits can only be set when the ARM bit is set. The TRIGF bit is set if a TRIG event occurs when ARM is already set, or if the TRIG event occurs simultaneous to setting the ARM bit.All other flags can only be cleared by arming the DBG module. Thus the contents are retained after a debug session for evaluation purposes. A set flag does not inhibit the setting of other flags.
6.3.2.7 Debug Status Register (DBGSR)
Read: Anytime. Write: Never. Table 6-13. DBGEFR Field Descriptions Field Description TRIGF TRIG Flag — Indicates the occurrence of a TRIG event during the debug session.
0 No TRIG event
1 TRIG event
External Event Flag — Indicates the occurrence of an external event during the debug session.
0 No external event
1 External event
3–0 ME[3:0] Match Event[3:0]— Indicates a comparator match event on the corresponding comparator channel Address: 0x010B 76543210 R 0 0 0 0 0 SSF2 SSF1 SSF0 W Reset POR = Unimplemented or Reserved Figure 6-10. Debug Status Register (DBGSR) Table 6-14. DBGSR Field Descriptions Field Description 2–0 SSF[2:0] State Sequencer Flag Bits — The SSF bits indicate the current State Sequencer state. During a debug session on each transition to a new state these bits are updated. If the debug session is ended by software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer before disarming. If a debug session is ended by an internal event, then the state sequencer returns to State0 and these bits are cleared to indicate that State0 was entered during the session. On arming the module the state sequencer enters State1 and these bits are forced to SSF[2:0] = 001. See Table 6-15
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6.3.2.8 Debug Comparator A Control Register (DBGACTL)
Read: Anytime. Write: If DBG not armed. Table 6-15. SSF[2:0] — State Sequence Flag Bit Encoding SSF[2:0] Current State
000 State0 (disarmed)
001 State1
010 State2
011 State3
100 Final State
101,110,111 Reserved Address: 0x0110 76543210 NDB INST RW RWE reserved COMPE W R e s e t 00000000 = Unimplemented or Reserved Figure 6-11. Debug Comparator A Control Register Table 6-16. DBGACTL Field Descriptions Field Description NDB Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator register value or when the data bus differs from the register value. This bit is ignored if the INST bit in the same register is set.
0 Match on data bus equivalence to comparator register contents
1 Match on data bus difference to comparator register contents
Instruction Select — This bit configures the comparator to compare PC or data access addresses.
0 Comparator compares addresses of data accesses
1 Comparator compares PC address
Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the associated comparator. The RW bit is ignored if RWE is clear or INST is set.
0 Write cycle is matched
1 Read cycle is matched
Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated comparator. This bit is ignored when INST is set.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
Enable Bit — Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled
Chapter 6 S12Z DebugLite (S12ZDBGV3) Module MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 195 Table 6-17 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if INST is set, because matches based on opcodes reaching the execution stage are data independent.
6.3.2.9 Debug Comparator A Addre ss Register (DBGAAH, DBGAAM, DBGAAL)
Read: Anytime. Write: If DBG not armed. Table 6-17. Read or Write Comparison Logic Table RWE Bit RW Bit RW Signal Comment 0 x 0 RW not used in comparison 0 x 1 RW not used in comparison 1 0 0 Write match 10 1 N o m a t c h 11 0 N o m a t c h 1 1 1 Read match Address: 0x0115, DBGAAH 23 22 21 20 19 18 17 16 R DBGAA[23:16] W R e s e t 00000000 Address: 0x0116, DBGAAM 15 14 13 12 11 10 9 8 R DBGAA[15:8] W R e s e t 00000000 Address: 0x0117, DBGAAL 76543210 R DBGAA[7:0] W R e s e t 00000000 Figure 6-12. Debug Comparator A Address Register Table 6-18. DBGAAH, DBGAAM, DBGAAL Field Descriptions Field Description 23–16 DBGAA [23:16] Comparator Address Bits [23:16]— These comparator address bits contro l whether the comparator compares the address bus bits [23:16] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
15–0 DBGAA [15:0] Comparator Address Bits [15:0]— These comparator address bits contro l whether the comparator compares the address bus bits [15:0] to a logic one or logic zero.
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6.3.2.10 Debug Comparator A Data Register (DBGAD)
Read: Anytime. Write: If DBG not armed. This register can be accessed with a byte resolution, whereby DBGAD0, DBGAD1, DBGAD2, DBGAD3 map to DBGAD[31:0] respectively.
6.3.2.11 Debug Comparator A Data Mask Register (DBGADM)
Read: Anytime. Write: If DBG not armed. Address: 0x0118, 0x0119, 0x011A, 0x011B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 W R e s e t 000000000 0000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 B it 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W R e s e t 000000000 0000000 Figure 6-13. Debug Comparator A Data Register (DBGAD) Table 6-19. DBGAD Field Descriptions Field Description 31–16 Bits[31:16] (DBGAD0, DBGAD1) Comparator Data Bits — These bits control whether the comparator compares the data bus bits to a logic one or logic zero. The comparator data bits are only used in comparison if the corresponding data mask bit is logic 1.
0 Compare corresponding data bit to a logic zero
1 Compare corresponding data bit to a logic one
15–0 Bits[15:0] (DBGAD2, DBGAD3) Comparator Data Bits — These bits control whether the comparator compares the data bus bits to a logic one or logic zero. The comparator data bits are only used in comparison if the corresponding data mask bit is logic 1. Address: 0x011C, 0x011D, 0x011E, 0x011F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 W R e s e t 000000000 0000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 B it 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W R e s e t 000000000 0000000 Figure 6-14. Debug Comparator A Data Mask Register (DBGADM)
Chapter 6 S12Z DebugLite (S12ZDBGV3) Module MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 197 This register can be accessed with a byte resolution, whereby DBGADM0, DBGADM1, DBGADM2, DBGADM3 map to DBGADM[31:0] respectively.
6.3.2.12 Debug Comparator B Control Register (DBGBCTL)
Read: Anytime. Write: If DBG not armed. Table 6-20. DBGADM Field Descriptions Field Description 31–16 Bits[31:16] (DBGADM0, DBGADM1) Comparator Data Mask Bits — These bits control whether the comparat or compares the data bus bits to the corresponding comparator data compare bits.
0 Do not compare corresponding data bit
1 Compare corresponding data bit
Bits[15:0] (DBGADM2, DBGADM3) Comparator Data Mask Bits — These bits control whether the comparat or compares the data bus bits to the corresponding comparator data compare bits. Address: 0x0120 76543210 R0 0 INST RW RWE reserved COMPE W R e s e t 00000000 = Unimplemented or Reserved Figure 6-15. Debug Comparator B Control Register Table 6-21. DBGBCTL Field Descriptions Field(1) 1. If the ABCM field selects range mode comparisons, then DBGACTL bits configure the comparison, DBGBCTL is ignored.
Description
Instruction Select — This bit configures the comparator to compare PC or data access addresses. Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the associated comparator. The RW bit is ignored if RWE is clear or INST is set. Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated comparator. This bit is ignored when INST is set. Enable Bit — Determines if comparator is enabled
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Table 6-22 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if INST is set, as matches based on instructions reaching the execution stage are data independent.
6.3.2.13 Debug Comparator B Addre ss Register (DBGBAH, DBGBAM, DBGBAL)
Read: Anytime. Write: If DBG not armed. Table 6-22. Read or Write Comparison Logic Table RWE Bit RW Bit RW Signal Comment 0 x 0 RW not used in comparison 0 x 1 RW not used in comparison 1 0 0 Write match 10 1 N o m a t c h 11 0 N o m a t c h 1 1 1 Read match Address: 0x0125, DBGBAH 23 22 21 20 19 18 17 16 R DBGBA[23:16] W R e s e t 00000000 Address: 0x0126, DBGBAM 15 14 13 12 11 10 9 8 R DBGBA[15:8] W R e s e t 00000000 Address: 0x0127, DBGBAL 76543210 R DBGBA[7:0] W R e s e t 00000000 Figure 6-16. Debug Comparator B Address Register Table 6-23. DBGBAH, DBGBAM, DBGBAL Field Descriptions Field Description 23–16 DBGBA [23:16] Comparator Address Bits [23:16]— These comparator address bits contro l whether the comparator compares the address bus bits [23:16] to a logic one or logic zero. 15–0 DBGBA [15:0] Comparator Address Bits[15:0]— These comparator address bits co ntrol whether the comparator compares the address bus bits [15:0] to a logic one or logic zero.
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6.3.2.14 Debug Comparator D Control Register (DBGDCTL)
Read: Anytime. Write: If DBG not armed. Table 6-25 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if INST is set, because matches based on opcodes reaching the execution stage are data independent. Address: 0x0140 76543210 R0 0 INST RW RWE reserved COMPE W R e s e t 00000000 = Unimplemented or Reserved Figure 6-17. Debug Comparator D Control Register Table 6-24. DBGDCTL Field Descriptions Field(1) 1. If the CDCM field selects range mode comparisons, then DBGCCTL bits configure the comparison, DBGDCTL is ignored. Instruction Select — This bit configures the comparator to compare PC or data access addresses. Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the associated comparator. The RW bit is ignored if RWE is clear or INST is set. Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated comparator. This bit is ignored if INST is set. Enable Bit — Determines if comparator is enabled Table 6-25. Read or Write Comparison Logic Table RWE Bit RW Bit RW Signal Comment 0 x 0 RW not used in comparison 0 x 1 RW not used in comparison 1 0 0 Write match 10 1 N o m a t c h 11 0 N o m a t c h 1 1 1 Read match
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6.3.2.15 Debug Comparator D Addre ss Register (DBGDAH, DBGDAM, DBGDAL)
Read: Anytime. Write: If DBG not armed.
6.4 Functional Description
This section provides a complete functional description of the DBG module.
6.4.1 DBG Operation
The DBG module operation is enabled by setting ARM in DBGC1. When armed it can be used to generate breakpoints to the CPU. The DBG module is made up of comparators, control logic, and the state sequencer, Figure 6-1. The comparators monitor the bus activity of the CPU. Comparators can be configured to monitor opcode addresses (effectively the PC address) or data accesses. Comparators can be configured during data Address: 0x0145, DBGDAH 23 22 21 20 19 18 17 16 R DBGDA[23:16] W R e s e t 00000000 Address: 0x0146, DBGDAM 15 14 13 12 11 10 9 8 R DBGDA[15:8] W R e s e t 00000000 Address: 0x0147, DBGDAL 76543210 R DBGDA[7:0] W R e s e t 00000000 Figure 6-18. Debug Comparator D Address Register Table 6-26. DBGDAH, DBGDAM, DBGDAL Field Descriptions Field Description 23–16 DBGDA [23:16] Comparator Address Bits [23:16]— These comparator address bits contro l whether the comparator compares the address bus bits [23:16] to a logic one or logic zero. 15–0 DBGDA [15:0] Comparator Address Bits[15:0]— These comparator address bits co ntrol whether the comparator compares the address bus bits [15:0] to a logic one or logic zero.
Chapter 6 S12Z DebugLite (S12ZDBGV3) Module MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 201 accesses to mask out individual data bus bits and to use R/W access qualification in the comparison. Comparators can be configured to monitor a range of addresses. When configured for data access comparisons, the match is generated if the address (and optionally data) of a data access matches the comparator value. Configured for monitoring opcode addresses, the match is generated when the associated opcode reaches the execution stage of the instruction queue, but before execution of that opcode. When a match with a comparator register value occurs, the associated control logic can force the state sequencer to another state (see Figure 6-19). The state sequencer can transition freely between the states 1, 2 and 3. On transition to Final State, a breakpoint can be generated and the state sequencer returns to state0, disarming the DBG . Independent of the comparators, state sequencer transitions can be forced by the external event input or by writing to the TRIG bit in the DBGC1 control register.
6.4.2 Comparator Modes
The DBG contains three comparators, A, B, and D. Each comparator compares the address stored in DBGXAH, DBGXAM, and DBGXAL with the PC (opcode addresses) or selected address bus (data accesses). Furthermore, comparator A can compare the data buses to values stored in DBGXD3-0 and allow data bit masking. The comparators can monitor the buses for an exact address or an address range. The comparator configuration is controlled by the control register contents and the range control by the DBGC2 contents. The comparator control register also allows the type of data access to be included in the comparison through the use of the RWE and RW bits. The RWE bit controls whether the access type is compared for the associated comparator and the RW bit selects either a read or write access for a valid match. The INST bit in each comparator control register is used to determine the matching condition. By setting INST, the comparator matches opcode addresses, whereby the databus, data mask, RW and RWE bits are ignored. The comparator register must be loaded with the exact opcode address. The comparator can be configured to match memory access addresses by clearing the INST bit. Each comparator match can force a transition to another state sequencer state (see Section 6.4.3, “Events”). Once a successful comparator match has occurred, the condition that caused the original match is not verified again on subsequent matches. Thus if a particular data value is matched at a given address, this address may not contain that data value when a subsequent match occurs. Match[0, 1, 3] map directly to Comparators [A, B, D] respectively, except in range modes (see Section 6.3.2.2, “Debug Control Register2 (DBGC2)”). Comparator priority rules are described in the event priority section (Section 6.4.3.4, “Event Priorities”).
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6.4.2.1 Exact Address Comparator Match
With range comparisons disabled, the match condition is an exact equivalence of address bus with the value stored in the comparator address registers. Qualification of the type of access (R/W) is also possible. Code may contain various access forms of the same address, for example a 16-bit access of ADDR[n] or byte access of ADDR[n+1] both access n+1. The comparators ensure that any access of the address defined by the comparator address register generates a match, as shown in the example of Table 6-27. Thus if the comparator address register contains ADDR[n+1] any access of ADDR[n+1] matches. This means that a 16-bit access of ADDR[n] or 32-bit access of ADDR[n-1] also match because they also access ADDR[n+1]. The right hand columns show the contents of DBGxA that would match for each access. If the comparator INST bit is set, the comparator address register contents are compared with the PC, the data register contents and access type bits are ignored. The comparator address register must be loaded with the address of the first opcode byte.
6.4.2.2 Address and Da ta Comparator Match
Comparator A features data comparators, for data access comparisons. The comparators do not evaluate if accessed data is valid. Accesses across aligned 32-bit boundaries are split internally into consecutive accesses. The data comparator mapping to accessed addresses for the CPU is shown in Table 6-28, whereby the Address column refers to the lowest 2 bits of the lowest accessed address. This corresponds to the most significant data byte. The fixed mapping of data comparator bytes to addresses within a 32-bit data field ensures data matches independent of access size. To compare a single data byte within the 32-bit field, the other bytes within that field must be masked using the corresponding data mask registers. This ensures that any access of that byte (32-bit,16-bit or 8-bit) with matching data causes a match. If no bytes are masked then the data comparator always compares all 32-bits and can only generate a match on a 32-bit access with correct 32- bit data value. In this case, 8-bit or 16-bit accesses within the 32-bit field cannot generate a match even if Table 6-27. Comparator Address Bus Matches Access Address ADDR[n] ADDR[n+1] ADDR[n+2] ADDR[n+3] 32-bit ADDR[n] Match Match Match Match 16-bit ADDR[n] Match Match No Match No Match 16-bit ADDR[n+1] No Matc h Match Match No Match 8-bit ADDR[n] Match No Match No Match No Match Table 6-28. Comparator Data Byte Alignment Address[1:0] Data Comparator
00 DBGxD0
01 DBGxD1
10 DBGxD2
11 DBGxD3
Chapter 6 S12Z DebugLite (S12ZDBGV3) Module MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 203 the contents of the addressed bytes match because all 32-bits must match. In Table 6-29 the Access Address column refers to the address bits[1:0] of the lowest accessed address (most significant data byte). Table 6-29. Data Register Use Dependency On CPU Access Type For a match of a 32-bit access with data compare, the address comparator must be loaded with the address of the lowest accessed byte. For Case1 Table 6-29 this corresponds to 000, for Case2 it corresponds to 001. To compare all 32-bits, it is required that no bits are masked.
6.4.2.3 Data Bus Comparison NDB Dependency
The NDB control bit allows data bus comparators to be configured to either match on equivalence or on difference. This allows monitoring of a difference in the contents of an address location from an expected value. When matching on an equivalence (NDB=0), each individual data bus bit position can be masked out by clearing the corresponding mask bit, so that it is ignored in the comparison. A match occurs when all data bus bits with corresponding mask bits set are equivalent. If all mask register bits are clear, then a match is based on the address bus only, the data bus is ignored. When matching on a difference, mask bits can be cleared to ignore bit positions. A match occurs when any data bus bit with corresponding mask bit set is different. Clearing all mask bits, causes all bits to be ignored and prevents a match because no difference can be detected. In this case address bus equivalence does not cause a match. Bytes that are not accessed are ignored. Thus when monitoring a multi byte field for a difference, partial accesses of the field only return a match if a difference is detected in the accessed bytes. Memory Address[2:0] Case Access Address Access Size 000 001 010 011 100 101 110 1 00 32-bit DBGxD0 DBGxD1 DBGxD2 DBGxD3 2 01 32-bit DBGxD1 DBGxD2 DBGxD3 DBGxD0 3 10 32-bit DBGxD2 DBGxD3 DBGxD0 DBGxD1 4 11 32-bit DBGxD3 DBGxD0 DBGxD1 DBGxD2 5 00 16-bit DBGxD0 DBGxD1 6 01 16-bit DBGxD1 DBGxD2 7 10 16-bit DBGxD2 DBGxD3 8 11 16-bit DBGxD3 DBGxD0 9 00 8-bit DBGxD0 10 01 8-bit DBGxD1 11 10 8-bit DBGxD2 12 11 8-bit DBGxD3 13 00 8-bit DBGxD0 Denotes byte that is not accessed.
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6.4.2.4 Range Comparisons
Range comparisons are accurate to byte boundaries. Thus for data access comparisons a match occurs if at least one byte of the access is in the range (inside range) or outside the range (outside range). For opcode comparisons only the address of the first opcode byte is compared with the range. When using the AB comparator pair for a range comparison, the data bus can be used for qualification by using the comparator A data and data mask registers. The DBGACTL RW and RWE bits can be used to qualify the range comparison on either a read or a write access. The corresponding DBGBCTL bits are ignored. The DBGACTL COMPE/INST bits are used for range comparisons. The DBGBCTL COMPE/INST bits are ignored in range modes.
6.4.2.4.1 Inside Range (CompA_Addr address CompB_Addr)
In the Inside Range comparator mode, comparator pair A and B can be configured for range comparisons by the control register (DBGC2). The match condition requires a simultaneous valid match for both comparators. A match condition on only one comparator is not valid.
6.4.2.4.2 Outside Range (address < CompA_Addr or address > CompB_Addr)
In the Outside Range comparator mode, comparator pair A and B can be configured for range comparisons. A single match condition on either of the comparators is recognized as valid. Outside range mode in combination with opcode address matches can be used to detect if opcodes are from an unexpected range. NOTE When configured for data access matches, an outside range match would typically occur at any interrupt vector fetch or register access. This can be avoided by setting the upper or lower range limit to $FFFFFF or $000000 respectively. Interrupt vector fetches do not cause opcode address matches.
6.4.3 Events
Events are used as qualifiers for a state sequencer change of state. The state control register for the current state determines the next state for each event. An event can immediately initiate a transition to the next state sequencer state whereby the corresponding flag in DBGSR is set. Table 6-30. NDB and MASK bit dependency NDB DBGADM Comment 0 0 Do not compare data bus bit. 0 1 Compare data bus bit. Match on equivalence. 1 0 Do not compare data bus bit. 1 1 Compare data bus bit. Match on difference.
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6.4.3.1 Comparator Match Events
6.4.3.1.1 Opcode Address Comparator Match
The comparator is loaded with the address of the selected instruction and the comparator control register INST bit is set. When the opcode reaches the execution stage of the instruction queue a match occurs just before the instruction executes, allowing a breakpoint immediately before the instruction boundary. The comparator address register must contain the address of the first opcode byte for the match to occur. Opcode address matches are data independent thus the RWE and RW bits are ignored. CPU compares are disabled when BDM becomes active.
6.4.3.1.2 Data Access Comparator Match
Data access matches are generated when an access occurs at the address contained in the comparator address register. The match can be qualified by the access data and by the access type (read/write). The breakpoint occurs a maximum of 2 instructions after the access in the CPU flow. Note, if a COF occurs between access and breakpoint, the opcode address of the breakpoint can be elsewhere in the memory map. Opcode fetches are not classed as data accesses. Thus data access matches are not possible on opcode fetches.
6.4.3.2 External Event
The DBGEEV input signal can force a state sequencer transition, independent of internal comparator matches. The DBGEEV is an input signal mapped directly to a device pin and configured by the EEVE field in DBGC1. The external events can change the state sequencer state. If configured to change the state sequencer state, then the external match is mapped to DBGSCRx bits C3SC[1:0]. The DBGEFR bit EEVF is set when an external event occurs.
6.4.3.3 Setting The TRIG Bit
Independent of comparator matches it is possible to initiate a breakpoint by writing the TRIG bit in DBGC1 to a logic “1”. This forces the state sequencer into the Final State. the transition to Final State is followed immediately by a transition to State0. Breakpoints, if enabled, are issued on the transition to State0.
6.4.3.4 Event Priorities
If simultaneous events occur, the priority is resolved according to Table 6-31. Lower priority events are suppressed. It is thus possible to miss a lower priority event if it occurs simultaneously with an event of a higher priority. The event priorities dictate that in the case of simultaneous matches, the match on the higher comparator channel number (3,1,0) has priority. If a write access to DBGC1 with the ARM bit position set occurs simultaneously to a hardware disarm from an internal event, then the ARM bit is cleared due to the hardware disarm.
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6.4.4 State Sequence Control
Figure 6-19. State Sequencer Diagram The state sequencer allows a defined sequence of events to provide a breakpoint. When the DBG module is armed by setting the ARM bit in the DBGC1 register, the state sequencer enters State1. Further transitions between the states are controlled by the state control registers and depend upon event occurrences (see Section 6.4.3, “Events). From Final State the only permitted transition is back to the disarmed State0. Transition between the states 1 to 3 is not restricted. Each transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current state. If breakpoints are enabled, then an event based transition to State0 generates the breakpoint request. A transition to State0 resulting from writing “0” to the ARM bit does not generate a breakpoint request.
6.4.4.1 Final State
When the Final State is reached the state sequencer returns to State0 immediately and the debug module is disarmed.If breakpoints are enabled, a breakpoint request is generated on transitions to State0.
6.4.5 Breakpoints
Breakpoints can be generated by state sequencer transitions to State0. Transitions to State0 are forced by the following events
- Through comparator matches via Final State. Table 6-31. Event Priorities Priority Source Action Highest TRIG Force immediately to final state DBGEEV Force to next state as defined by state control registers (EEVE=2’b10) Match3 Force to next state as defined by state control registers Match1 Force to next state as defined by state control registers Lowest Match0 Force to next state as defined by state control registers State1 Final State State3 ARM = 1 State2 State 0 (Disarmed)
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- Through software writing to the TRIG bit in the DBGC1 register via Final State.
- Through the external event input (DBGEEV) via Final State. Breakpoints are not generated by software writes to DBGC1 that clear the ARM bit.
6.4.5.1 Breakpoints From Compara tor Matches or External Events
Breakpoints can be generated when the state sequencer transitions to State0 following a comparator match or an external event.
6.4.5.2 Breakpoints Generated Via The TRIG Bit
When TRIG is written to “1”, the Final State is entered. In the next cycle TRIG breakpoints are possible even if the DBG module is disarmed.
6.4.5.3 DBG Breakpoint Priorities
6.4.5.3.1 DBG Breakpoint Prio rities And BDC Interfacing
Breakpoint operation is dependent on the state of the S12ZBDC module. BDM cannot be entered from a breakpoint unless the BDC is enabled (ENBDC bit is set in the BDC). If BDM is already active, breakpoints are disabled. In addition, while executing a BDC STEP1 command, breakpoints are disabled. When the DBG breakpoints are mapped to BDM (BDMBP set), then if a breakpoint request, either from a BDC BACKGROUND command or a DBG event, coincides with an SWI instruction in application code, (i.e. the DBG requests a breakpoint at the next instruction boundary and the next instruction is an SWI) then the CPU gives priority to the BDM request over the SWI request. On returning from BDM, the SWI from user code gets executed. Breakpoint generation control is summarized in Table 6-32.
6.5 Application Information
6.5.1 Avoiding Unintended Breakpoint Re-triggering
Returning from an instruction address breakpoint using an RTI or BDC GO command without PC modification, returns to the instruction that generated the breakpoint. If an active breakpoint or trigger still Table 6-32. Breakpoint Mapping Summary BRKCPU BDMBP Bit (DBGC1[4]) BDC Enabled BDM Active Breakpoint Mapping
0 X X X No Breakpoint
1011 N o B r e a k p o i n t
1110 B r e a k p o i n t t o B D M
1111 N o B r e a k p o i n t
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exists at that address, this can re-trigger, disarming the DBG . If configured for BDM breakpoints, the user must apply the BDC STEP1 command to increment the PC past the current instruction. If configured for SWI breakpoints, the DBG can be re configured in the SWI routine. If a comparator match occurs at an SWI vector address then a code SWI and DBG breakpoint SWI could occur simultaneously. In this case the SWI routine is executed twice before returning.
6.5.2 Breakpoints from other S12Z sources
The DBG is neither affected by CPU BGND instructions, nor by BDC BACKGROUND commands.
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7.1 Introduction
The purpose of ECC logic is to detect and correct as much as possible memory data bit errors. These soft errors, mainly generated by alpha radiation, can occur randomly during operation. "Soft error" means that only the information inside the memory cell is corrupt; the memory cell itself is not damaged. A write access with correct data solves the issue. If the ECC algorithm is able to correct the data, then the system can use this corrected data without any issues. If the ECC algorithm is able to detect, but not correct the error, then the system is able to ignore the memory read data to avoid system malfunction. The ECC value is calculated based on an aligned 2 byte memory data word. Depending on the device integration, the maximum supported access width can be 2 or 4 bytes. Please see the device overview section for the information about the maximum supported access width on the device. In a system with a maximum access width of 2 bytes, a 2 byte access to a 2 byte aligned address is classed as an aligned access. If the system supports a 4-byte access width, then a 2-byte access to a 2 byte aligned address or a 4 byte access to a 4 byte aligned address are classed as aligned accesses. All other access types are classed as non-aligned accesses. A non-aligned write access requires a read-modify-write operationThe ECC algorithm is able to detect and correct single bit ECC errors. Double bit ECC errors will be detected but the system is not able to correct these errors. This kind of ECC code is called SECDED code. This ECC code requires 6 additional parity bits for each 2 byte data word.
7.1.1 Features
The SRAM_ECC module provides the ECC logic for the system memory based on a SECDED algorithm. The SRAM_ECC module includes the following features:
- SECDED ECC code Table 7-1. Revision History Table Rev. No. (Item No.) Date Sections Affected Substantial Change(s) V01.00 26-Jul.-11 all Initial version V1 V02.00 10-May-12 all Initial version V2, added support for max access width of 2 byte V03.00 31-Mar-15 7.3 describe the new behavior in case of non-aligned write to Double Bit ECC error memory location V03.01 23-Mar-16 7.3.7 Described ECC debug corner case for non-aligned reads
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– Single bit error detection and correction per 2 byte data word – Double bit error detection per 2 byte data word
- Memory initialization function
- Byte wide system memory write access
- Automatic single bit ECC error co rrection for read and write accesses
- Debug logic to read and write raw use data and ECC values
7.2 Memory Map and Register Definition
This section provides a detailed description of all memory and registers for the SRAM_ECC module.
7.2.1 Register Summary
Figure 7-1 shows the summary of all implemented registers inside the SRAM_ECC module.
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7.2.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field functions follow the register diagrams, in bit order.
7.2.2.1 ECC Status Register (ECCSTAT)
Figure 7-2. ECC Status Register (ECCSTAT) Table 7-2. ECCSTAT Field Description
7.2.2.2 ECC Interrupt Enable Register (ECCIE)
Figure 7-3. ECC Interrupt Enable Register (ECCIE) Table 7-3. ECCIE Field Description Module Base + 0x00000 Access: User read only (1) 1. Read: Anytime Write: Never 76543 21 0 R 0 0 0 0 0 0 0 RDY W R e s e t 00000 00 0 Field Description RDY ECC Ready— Shows the status of the ECC module.
0 Internal SRAM initialization is ongoing, access to the SRAM is disabled
1 Internal SRAM initialization is done, access to the SRAM is enabled
Module Base + 0x00001 Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543 21 0 R 0 0 0 00 00 SBEEIE W R e s e t 00000 00 0 Field Description SBEEIE Single bit ECC Error Interrupt Enable — Enables Single ECC Error interrupt.
0 Interrupt request is disabled
1 Interrupt will be requested whenever SBEEIF is set
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7.2.2.3 ECC Interrupt Flag Register (ECCIF)
Figure 7-4. ECC Interrupt Flag Register (ECCIF) Table 7-4. ECCIF Field Description Module Base + 0x0002 Access: User read/write (1) 1. Read: Anytime Write: Anytime, write 1 to clear 76543 21 0 R 0 0 0 00 00 SBEEIF W R e s e t 00000 00 0 Field Description SBEEIF Single bit ECC Error Interrupt Flag — The flag is set to 1 when a single bit ECC error occurs.
0 No occurrences of single bit ECC error since the last clearing of the flag
1 Single bit ECC error has occurred since the last clearing of the flag
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7.2.2.4 ECC Debug Pointer Register (ECCDPTRH, ECCDPTRM,
ECCDPTRL) Module Base + 0x0007 Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R DPTR[23:16] W R e s e t 00000000 Module Base + 0x0008 Access: User read/write 76543210 R DPTR[15:8] W R e s e t 00000000 Module Base + 0x0009 Access: User read/write 76543210 R DPTR[7:1] W R e s e t 00000000 = Unimplemented Figure 7-5. ECC Debug Pointer Register (ECCDPTRH, ECCDPTRM, ECCDPTRL) Table 7-5. ECCDPTR Register Field Descriptions Field Description DPTR [23:0] ECC Debug Pointer — This register contains the system memory address which will be used for a debug access. Address bits not relevant for SRAM address space are not writeable, so the software should read back the pointer value to make sure the register contains the intended memory address. It is possible to write an address value to this register which points outside the system memory. There is no additional monitoring of the register content; therefore, the software must make sure that the address value points to the system memory space.
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7.2.2.5 ECC Debug Data (ECCDDH, ECCDDL)
7.2.2.6 ECC Debug ECC (ECCDE)
Figure 7-7. ECC Debug ECC (ECCDE) Table 7-7. ECCDE Field Description Module Base + 0x000C Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R DDATA[15:8] W R e s e t 00000000 Module Base + 0x000D Access: User read/write 76543210 R DDATA[7:0] W R e s e t 00000000 = Unimplemented Figure 7-6. ECC Debug Data (ECCDDH, ECCDDL) Table 7-6. ECCDD Register Field Descriptions Field Description DDATA [23:0] ECC Debug Raw Data — This register contains the ra w data which will be written into the system memory during a debug write command or the read data from the debug read command. Module Base + 0x000E Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R 0 0 DECC[5:0] W R e s e t 00000000 Field Description 5:0 DECC[5:0] ECC Debug ECC — This register contains the raw ECC value which will be written into the system memory during a debug write command or the ECC read value from the debug read command.
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7.2.2.7 ECC Debug Command (ECCDCMD)
Figure 7-8. ECC Debug Command (ECCDCMD) Table 7-8. ECCDCMD Field Description
7.3 Functional Description
Depending on the system integration the max memory access width can be 4 byte, but the ECC value is generated based on an aligned 2 byte data word. Depending on the access type, the access is separated into different access cycles. Table 7-9 shows the different access types with the expected number of access cycles and the performed internal operations. Module Base + 0x000F Access: User read/write (1) 1. Read: Anytime Write: Anytime, in special mode only 76543210 R ECCDRR 0 0 000 ECCDW ECCDR W R e s e t 00000000 Field Description ECCDRR ECC Disable Read Repair Function— Writing one to this register bit will disable the automatic single bit ECC error repair function during read access; see also chapter 7.3.7, “ECC Debug Behavior”.
0 Automatic single ECC error repair function is enabled
1 Automatic single ECC error repair function is disabled
ECC Debug Write Command — Writing one to this register bit will perform a debug write access, to the system memory. During this access the debug data word (DDATA) and the debug ECC value (DECC) will be written to the system memory address defined by DPTR. If the debug write access is done, this bit is cleared. Writing 0 has no effect. It is not possible to set this bit if the previous debug access is ongoing (ECCDW or ECCDR bit set). ECCDR ECC Debug Read Command — Writing one to this register bit will perform a debug read access from the system memory address defined by DPTR. If the debug read access is done, this bit is cleared and the raw memory read data are available in register DDATA and the raw ECC value is available in register DECC. Writing 0 has no effect. If the ECCDW and ECCDR bit are set at the same time, then only the ECCDW bit is set and the Debug Write Command is performed. It is not possible to set this bit if the previous debug access is ongoing (ECCDW or ECCDR bit set). Table 7-9. Memory access cycles Access type ECC error access cycle Internal operation Memory content Error indication Aligned write — 1 write to memory new data —
Chapter 7 ECC Generation Module (SRAM_ECCV3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 217 The single bit ECC error generates an interrupt when enabled. The double bit ECC errors are reported by the SRAM_ECC module, but handled at MCU level. For more information, see the MMC description.
7.3.1 Aligned Memory Write Access
During an aligned memory write access, no ECC check is performed. The internal ECC logic generates the new ECC value based on the write data and writes the data word together with the generated ECC value into the memory.
7.3.2 Non-aligned Memory Write Access
Non-aligned write accesses are separated into a read-modify-write operation. During the first cycle, the logic reads the data from the memory and performs an ECC check. If no ECC errors were detected then the logic generates the new ECC value based on the read and write data and writes the new data word together with the new ECC value into the memory.If the module detects a single bit ECC error during the read cycle, then the logic generates the new ECC value based on the corrected read and new write read. In the next cycle, the new data word and the new ECC value are written into the memory. The SBEEIF bit is set. Hence, the single bit ECC error was corrected by the write access. Figure 7-9 shows an example of a 2 byte non-aligned memory write access. Even if a double bit ECC error occurs during the read cycle, the undefined read data will be used to generate the new write data word. A new ECC value will be calculated based on the undefined write data word. ECC value and the new write data word will be written into the memory. Therefore the data written to the memory are ECC clean. Non-aligned write no 2 read data from the memory old + new data —write old + new data to the memory single bit 2 read data from the memory corrected + new data SBEEIFwrite corrected + new data to the memory double bit 2 read data from the memory undefined(1) machine exceptionwrite data to memory read access no 1 read from memory unchanged - single bit 1 read data from the memory corrected data SBEEIFwrite corrected data back to memory double bit 1 read from memory unchanged read data marked as invalid machine exception 1. The write data are generated based on data with double bit ECC error. This generated data word is undefined, but shows no ECC error. Table 7-9. Memory access cycles Access type ECC error access cycle Internal operation Memory content Error indication
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Figure 7-9. 2 byte non-aligned write access
7.3.3 Memory Read Access
During each memory read access an ECC check is performed. If the logic detects a single bit ECC error, then the module corrects the data, so that the access initiator module receives correct data. Additionally, the logic writes the corrected data back to the memory, so that this read access repairs the single bit ECC error. This automatic ECC read repair function is disabled by setting the ECCDRR bit. If a single bit ECC error was detected, then the SBEEIF flag is set. If the logic detects a double bit ECC error, then the data word is flagged as invalid, so that the access initiator module can ignore the data.
7.3.4 Memory Initialization
To avoid spurious ECC error reporting, memory operations that allow a read before a first write (like the read-modify-write operation of the non-aligned access) require that the memory contains valid ECC values before the first read-modify-write access is performed. The ECC module provides logic to initialize the complete memory content with zero during the power up phase. During the initialization process the access to the SRAM is disabled and the RDY status bit is cleared. If the initialization process is done, SRAM access is possible and the RDY status bit is set.
7.3.5 Interrupt Handling
This section describes the interrupts generated by the SRAM_ECC module and their individual sources. Vector addresses and interrupt priority are defined at the MCU level. ECC2 byte use data correct read data read out data and correct if single bit ECC error was found write data ECCcorrect read data write data ECC2 byte use data correct read data read out data and correct if single bit ECC error was found write data ECCcorrect read data write data 4 byte write data to system memory 4 byte read data from system memory 2 byte write data
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7.3.6 ECC Algorithm
The table below shows the equation for each ECC bit based on the 16 bit data word. Table 7-11. ECC Calculation
7.3.7 ECC Debug Behavior
For debug purposes, it is possible to read and write the uncorrected use data and the raw ECC value directly from the memory. For these debug accesses a register interface is available. The debug access is performed with the lowest priority; other memory accesses must be done before the debug access starts. If a debug access is requested during an ongoing memory initialization process, then the debug access is performed if the memory initialization process is done. If the ECCDRR bit is set, then the automatic single bit ECC error repair function for all read accesses is disabled. In this case a read access from a system memory location with single bit ECC error will produce correct data and the single bit ECC error is flagged by the SBEEIF, but the data inside the system memory are unchanged. By writing wrong ECC values into the system memory the debug access can be used to force single and double bit ECC errors to check the software error handling. It is not possible to set the ECCDW or ECCDR bit if the previous debug access is ongoing (ECCDW or ECCDR bit active). This ensures that the ECCDD and ECCDE registers contains consistent data. The software should read out the status of the ECCDW and ECCDR register bit before a new debug access is requested.
7.3.7.1 ECC Debug Memory Write Access
Writing one to the ECCDW bit performs a debug write access to the memory address defined by register DPTR. During this access, the raw data DDATA and the ECC value DECC are written directly into the system memory. If the debug write access is done, the ECCDW register bit is cleared. The debug write access is always a 2 byte aligned memory access, so that no ECC check is performed and no single or double bit ECC error indication is activated. Table 7-10. SRAM_ECC Interrupt Sources Module Interrupt Sources Local Enable Single bit ECC error ECCIE[SBEEIE] ECC bit Use data ECC[2] ~ ( ^ ( data[15:0] & 0xE1D1 ) ) ECC[3] ~ ( ^ ( data[15:0] & 0xEE60 ) ) ECC[4] ~ ( ^ ( data[15:0] & 0x3E8A ) )
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7.3.7.2 ECC Debug Memory Read Access
Writing one to the ECCDR bit performs a debug read access from the memory address defined by register DPTR. If the ECCDR bit is cleared then the register DDATA contains the uncorrected read data from the memory. The register DECC contains the ECC value read from the memory. Independent of the ECCDRR register bit setting, the debug read access will not perform an automatic ECC repair during read access. During the debug read access no ECC check is performed, so that no single or double bit ECC error indication is activated. After inserting an ECC error with the ECC Debug Write Command such that an error exists in both the high and the low 16 bit fields of a misaligned 32-bit word, then a read access of that misaligned 32-bit returns corrected data to MMC, however only the first 16-bits are corrected in the memory during this first 32-bit misaligned read. Thus a subsequent debug access of the lower 16-bit field returns uncorrected data. If the ECCDW and the ECCDR bits are set at the same time, then only the debug write access is performed.
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8.1 Introduction
This specification describes the function of the Clock, Reset and Power Management Unit (S12CPMU_UHV_V11).
- The Pierce oscillator (XOSCLCP) provides a robust, low-noise and low-power external clock source. It is designed for optimal start-up margin with typical crystal oscillators.
- The V oltage regulator (VREGAUTO) operates from the range 6V to 18V. It provides all the required chip internal voltages and voltage monitors.
- The Phase Locked Loop (PLL) provi des a highly accurate frequency multiplier with internal filter.
- The Internal Reference Clock (IRC 1M) provides a 1MHz internal clock. Rev. No. (Item No) Date (Submitted By) Sections Affected Substantial Change(s) V11.00 18 May 2015
- initial version for VMB64, copied from ZVL128
- removed VREG5VEN Bit
- DVBE Temperature sensor: Added enable bit to CPMUHTCTL register Added to Feature list Added to Signal Descriptions V11.01 16 Sept. 2015 • CPMUHTCTL register: corrected and improved register description of ATEMPEN bit. V11.02 23 Nov. 2015 • Improved wording related to “ADC channel”.
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8.1.1 Features
The Pierce Oscillator (XOSCLCP) contains circuitry to dynamically control current gain in the output amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity.
- Supports crystals or resonators from 4MHz to 20MHz.
- High noise immunity due to input hysteresis and spike filtering.
- Low RF emissions with peak-t o-peak swing limited dynamically
- Transconductance (gm) sized for optimum start-up margin for typical crystals
- Dynamic gain control eliminates the need for external current limiting resistor
- Integrated resistor eliminates th e need for external bias resistor
- Low power consumption: Operates from internal 1.8V (nominal) supply, Amplitude control limits power
- Optional oscillator clock monitor reset
- Optional full swing mode for higher immunity ag ainst noise injection on the cost of higher power consumption and increased emission The V oltage Regulator (VREGAUTO) has the following features:
- Input voltage range from 6 to 18V (nominal operating range)
- Low-voltage detect (LVD) with low-voltage interrupt (LVI)
- Power-on reset (POR)
- Low-voltage reset (LVR)
- On Chip Temperature Sensor and Bandga p V oltage measurement via ADC channel.
- On Chip DVBE temperature sensor measurement via ADC channel
- V oltage Regulator providing Full Performanc e Mode (FPM) and Reduced Performance Mode (RPM)
- External ballast device support to reduce internal power dissipation
- Capable of supplying both the MCU in ternally plus external components
- Over-temperature interrupt The Phase Locked Loop (PLL) has the following features:
- Highly accurate and phase lo cked frequency multiplier
- Configurable internal filter fo r best stability and lock time
- Frequency modulation for define d jitter and reduced emission
- Automatic frequency lock detector
- Interrupt request on entry or exit from locked condition
- PLL clock monitor reset
- Reference clock either external (crystal) or internal square wave (1MHz IRC1M) based.
- PLL stability is sufficient for LIN communication in slave mode, even if using IRC1M as reference clock
Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 223 The Internal Reference Clock (IRC1M) has the following features:
- Frequency trimming (A factory trim value for 1MHz is loaded from Flash Memory into the CPMUIRCTRIMH and CPMUIRCTRIML registers after reset, which can be overwritten by application if required)
- Temperature Coefficient (TC) trimming. (A factory trim value is loaded from Flash Memory into the IRCTRIM register to turn off TC trimming after reset. Application can trim the TC if required by overwriting the IRCTRIM register). Other features of the S12CPMU_UHV_V11 include
- Oscillator clock monitor to detect loss of crystal
- Autonomous periodical interrupt (API)
- Bus Clock Generator — Clock switch to select either PLLCLK or external crystal/resonator based Bus Clock — PLLCLK divider to adjust system speed
- System Reset generation from th e following possible sources: — Power-on reset (POR) — Low-voltage reset (LVR) — COP system watchdog, COP rese t on time-out, windowed COP — Loss of oscillation (Oscillator clock monitor fail) — Loss of PLL clock (PLL clock monitor fail) — External pin RESET
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8.1.2 Modes of Operation
This subsection lists and briefly describes all operating modes supported by the S12CPMU_UHV_V11.
8.1.2.1 Run Mode
The voltage regulator is in Full Performance Mode (FPM). NOTE The voltage regulator is active, providing the nominal supply voltages with full current sourcing capability (see also Appendix for VREG electrical parameters). The features ACLK clock source, Low V oltage Interrupt (LVI), Low V oltage Reset (LVR) and Power-On Reset (POR) are available. The Phase Locked Loop (PLL) is on. The Internal Reference Clock (IRC1M) is on. The API is available.
- PLL Engaged Internal (PEI) — This is the default mode after System Reset and Power-On Reset. — The Bus Clock is based on the PLLCLK. — After reset the PLL is confi gured for 50MHz VCOCLK operation. Post divider is 0x03, so PLLCLK is VCOCLK divided by 4, that is 12.5MHz and Bus Clock is 6.25MHz. The PLL can be re-configured for other bus frequencies. — The reference clock for the PLL (REFCLK) is based on internal reference clock IRC1M.
- PLL Engaged External (PEE) — The Bus Clock is based on the PLLCLK. — This mode can be entered from default mode PEI by performing the following steps: – Configure the PLL for desired bus frequency. – Program the reference divider (REFDIV[3:0] bits) to divide down oscillator frequency if necessary. – Enable the external os cillator (OSCE bit). – Wait for oscillator to start up (U POSC=1) and PLL to lock (LOCK=1).
- PLL Bypassed External (PBE) — The Bus Clock is based on th e Oscillator Clock (OSCCLK). — The PLLCLK is always on to qua lify the external oscillator clock. Therefore it is necessary to make sure a valid PLL configuration is used for the selected oscillator frequency. — This mode can be entered from default mode PEI by performing the following steps: – Make sure the PLL configuration is vali d for the selected oscillator frequency. – Enable the external os cillator (OSCE bit).
Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 225 – Wait for oscillator to start up (UPOSC=1). – Select the Oscillator Cloc k (OSCCLK) as source of the Bus Clock (PLLSEL=0). — The PLLCLK is on and used to qual ify the external oscillator clock.
8.1.2.2 Wait Mode
For S12CPMU_UHV_V11 Wait Mode is the same as Run Mode.
8.1.2.3 Stop Mode
Stop mode can be entered by executing the CPU STOP instruction. See device level specification for more details. The voltage regulator is in Reduced Performance Mode (RPM). NOTE The voltage regulator output voltage may degrade to a lower value than in Full Performance Mode (FPM), additionally the current sourcing capability is substantially reduced (see also Appendix for VREG electrical parameters). Only clock source ACLK is available and the Power On Reset (POR) circuitry is functional. The Low V oltage Interrupt (LVI) and Low V oltage Reset (LVR) are disabled. The API is available. The Phase Locked Loop (PLL) is off. The Internal Reference Clock (IRC1M) is off. Core Clock and Bus Clock are stopped. Depending on the setting of the PSTP and the OSCE bit, Stop Mode can be differentiated between Full Stop Mode (PSTP = 0 or OSCE=0) and Pseudo Stop Mode (PSTP = 1 and OSCE=1). In addition, the behavior of the COP in each mode will change based on the clocking method selected by COPOSCSEL[1:0].
- Full Stop Mode (PSTP = 0 or OSCE=0) External oscillator (XOSCLCP) is disabled. — If COPOSCSEL1=0: The COP and RTI counters halt during Full Stop Mode. After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK (PLLSEL=1). COP and RTI are running on IRCCLK (COPOSCSEL0=0, RTIOSCSEL=0). — If COPOSCSEL1=1: The clock for the COP is derived from ACLK (trimmable internal RC-Oscillator clock). During Full Stop Mode the ACLK for the COP can be stopped (COP static) or running (COP active) depending on the setting of bit CSAD. When bit CSAD is set the ACLK clock source for the COP is stopped during Full Stop Mode and COP continues to operate after exit from Full Stop Mode. For this COP configuration (ACLK clock source, CSAD set) a latency time (please refer
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to CSAD bit description for details) occurs when entering or exiting (Full, Pseudo) Stop Mode. When bit CSAD is clear the ACLK clock source is on for the COP during Full Stop Mode and COP is operating. During Full Stop Mode the RTI counter halts. After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK (PLLSEL=1). The COP runs on ACLK and RTI is running on IRCCLK (COPOSCSEL0=0, RTIOSCSEL=0).
- Pseudo Stop Mode (PSTP = 1 and OSCE=1) External oscillator (XOSCLCP) continues to run. — If COPOSCSEL1=0: If the respective enable bits are set (PCE=1 and PRE=1) the COP and RTI will continue to run with a clock derived from the oscillator clock. The clock configuration bits PLLSEL, COPOSCSEL0, RTIOSCSEL are unchanged. — If COPOSCSEL1=1: If the respective enable bit for the RTI is set (PRE=1) the RTI will continue to run with a clock derived from the oscillator clock. The clock for the COP is derived from ACLK (trimmable internal RC-Oscillator clock). During Pseudo Stop Mode the ACLK for the COP can be stopped (COP static) or running (COP active) depending on the setting of bit CSAD. When bit CSAD is set the ACLK for the COP is stopped during Pseudo Stop Mode and COP continues to operate after exit from Pseudo Stop Mode. For this COP configuration (ACLK clock source, CSAD set) a latency time (please refer to CSAD bit description for details) occurs when entering or exiting (Pseudo, Full) Stop Mode. When bit CSAD is clear the ACLK clock source is on for the COP during Pseudo Stop Mode and COP is operating. The clock configuration bits PLLSEL, COPOSCSEL0, RTIOSCSEL are unchanged. NOTE When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time of the external oscillator t UPOSC before entering Pseudo Stop Mode.
8.1.2.4 Freeze Mode (BDM active)
For S12CPMU_UHV_V11 Freeze Mode is the same as Run Mode except for RTI and COP which can be frozen in Active BDM Mode with the RSBCK bit in the CPMUCOP register. After exiting BDM Mode RTI and COP will resume its operations starting from this frozen status. Additionally the COP can be forced to the maximum time-out period in Active BDM Mode. For details please see also the RSBCK and CR[2:0] bit description field of Table 8-14 in Section 8.3.2.12, “S12CPMU_UHV_V11 COP Control Register (CPMUCOP)
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8.1.3 S12CPMU_UHV_V11 Block Diagram
Figure 8-1. Block diagram of S12CPMU_UHV_V11 S12CPMU_UHV EXTAL XTAL System Reset Power-On Detect Loop Reference Divider Voltage VSUP Internal Reset Generator Divide by Phase Post Divider 1,2,.32 VCOCLK LOCKIE IRCTRIM[9:0] SYNDIV[5:0] LOCK REFDIV[3:0] 2*(SYNDIV+1) Pierce Oscillator 4MHz-20MHz OSCE PORF divide by 2 ECLKPOSTDIV[4:0] Power-On Reset Controlled locked Loop with internal Filter (PLL) REFCLK FBCLK REFFRQ[1:0] VCOFRQ[1:0] Lock detect Regulator 6V to 18V Autonomous Periodic Interrupt (API) API Interrupt VSS PLLSEL VSSX VDDA VDDX Low Voltage Detect LVRF PLLCLK Reference Clock (IRC1M) OSCCLK Monitor osc monitor fail Real Time Interrupt (RTI) RTI Interrupt PSTP CPMURTI Oscillator status Interrupt (XOSCLCP) High Temperature Sense HT Interrupt Low Voltage Interrupt APICLK RTICLK IRCCLK OSCCLK RTIOSCSEL COP time-out PRE UPOSC=0 sets PLLSEL bit API_EXTCLK RC Osc. UPOSC RESET OSCIE APIE RTIE HTDS HTIE LVDS LVIELow Voltage Detect VDDA OSCCLK divide by 4 Bus Clock VSSA ADC vsup monitor (VREGAUTO) ECLK2X (Core Clock) (Bus Clock) COP time-outCOP Watchdog CPMUCOP COPCLKIRCCLK OSCCLK COPOSCSEL0 to Reset Generator PCE UPOSC UPOSC=0 clears ACLK COPOSCSEL1 CSAD divide by 2 ACLK divide by 2 IRCCLK OSCCLK IRCCLK PLL lock interrupt BCTL OMRF COPRF PMRF PLL monitor fail VDDX, VDD, VDDF OSCMOD
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Figure 8-2 shows a block diagram of the XOSCLCP. Figure 8-2. XOSCLCP Block Diagram EXTAL XTAL Gain Control VDD=1.8V Rf OSCCLKPeak Detector VSS VSS VSS C1 C2 Quartz Crystals Ceramic Resonators or Clock Monitor monitor failOSCMOD
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8.2 Signal Description
This section lists and describes the signals that connect off chip as well as internal supply nodes and special signals.
8.2.1 RESET
Pin RESET is an active-low bidirectional pin. As an input it initializes the MCU asynchronously to a known start-up state. As an open-drain output it indicates that an MCU-internal reset has been triggered.
8.2.2 EXTAL and XTAL
These pins provide the interface for a crystal to control the internal clock generator circuitry. EXTAL is the input to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. If XOSCLCP is enabled, the MCU internal OSCCLK_LCP is derived from the EXTAL input frequency. If OSCE=0, the EXTAL pin is pulled down by an internal resistor of approximately 200 k and the XTAL pin is pulled down by an internal resistor of approximately 700 k. NOTE Freescale recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. The loop controlled circuit (XOSCLCP) is not suited for overtone resonators and crystals.
8.2.3 VSUP — Regulator Power Input Pin
Pin VSUP is the power input of VREGAUTO. All currents sourced into the regulator loads flow through this pin. A suitable reverse battery protection network can be used to connect VSUP to the car battery supply network.
8.2.4 VDDA, VSSA — Regula tor Reference Supply Pins
Pins VDDA and VSSA,are used to supply the analog parts of the regulator. Internal precision reference circuits are supplied from these signals. An off-chip decoupling capacitor (220 nF(X7R ceramic)) between VDDA and VSSA is required and can improve the quality of this supply. VDDA has to be connected externally to VDDX.
8.2.5 VDDX, VSSX — Pad Supply Pins
VDDX is the supply domain for the digital Pads. An off-chip decoupling capacitor (10F plus 220 nF(X7R ceramic)) between VDDX and VSSX is required.
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This supply domain is monitored by the Low V oltage Reset circuit. VDDX has to be connected externally to VDDA.
8.2.6 BCTL — Base Control Pin for external PNP
BCTL is the ballast connection for the on chip voltage regulator. It provides the base current of an external BJT (PNP) of the VDDX and VDDA supplies. An additional 1K resistor between emitter and base of the BJT is required. See the device specification if this pin is available on this device.
8.2.7 VSS — Core Logic Ground Pin
VSS is the core logic supply return pin. It must be grounded.
8.2.8 VDD — Internal Regulator Output Supply (Core Logic)
Node VDD is a device internal supply output of the voltage regulator that provides the power supply for the internal core logic. This supply domain is monitored by the Low V oltage Reset circuit and The Power On Reset circuit.
8.2.9 VDDF — Internal Regulato r Output Supply (NVM Logic)
Node VDDF is a device internal supply output of the voltage regulator that provides the power supply for the NVM logic. This supply domain is monitored by the Low V oltage Reset circuit.
8.2.10 API_EXTCLK — API e xternal clock output pin
This pin provides the signal selected via APIES and is enabled with APIEA bit. See the device specification if this clock output is available on this device and to which pin it might be connected.
8.2.11 TEMPSENSE — Internal Temp erature Sensor Output Voltage
Depending on the VSEL setting either the voltage level generated by the temperature sensor or the VREG bandgap voltage is driven to a channel input of the ADC Converter. See device level specification for connectivity of ADC channels.
8.2.12 DVBE TEMPSENSE — DVBE Inte rnal Temperature Sensor Output
The voltage level generated by the DVBE temperature sensor is driven to a channel input of the ADC. See device level specification for connectivity of ADC channels.
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8.3 Memory Map and Registers
This section provides a detailed description of all registers accessible in the S12CPMU_UHV_V11.
8.3.1 Module Memory Map
The S12CPMU_UHV_V11 registers are shown in Figure 8-3. Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 RESERVED R0 0 0 0 0 0 0 0 W 0x0001 RESERVED CPMU VREGTRIM0 R 0 0 0 0 U U U U W 0x0002 RESERVED CPMU VREGTRIM1 R0 0 U U U 0 0 0 W 0x0003 CPMURFLG PORF LVRF COPRF OMRF PMRF W 0x0004 CPMU SYNR R VCOFRQ[1:0] SYNDIV[5:0] W 0x0005 CPMU REFDIV R REFFRQ[1:0] REFDIV[3:0] W 0x0006 CPMU POSTDIV R0 0 0 POSTDIV[4:0] W 0x0007 CPMUIFLG R RTIF LOCKIF LOCK 0 OSCIF UPOSC W 0x0008 CPMUINT R RTIE LOCKIE OSCIE W 0x0009 CPMUCLKS R PLLSEL PSTP CSAD COP OSCSEL1 PRE PCE RTI OSCSEL COP OSCSEL0W 0x000A CPMUPLL R0 0 FM1 FM0 00 0 0 W 0x000B CPMURTI R RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 W 0x000C CPMUCOP R WCOP RSBCK 00 0 CR2 CR1 CR0 W WRTMASK 0x000D RESERVED CPMUTEST0 R0 0 0 0 0 0 0 0 W = Unimplemented or Reserved Figure 8-3. CPMU Register Summary
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W 0x000F CPMU ARMCOP R0 0 0 0 0 0 0 0 W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0010 CPMU HTCTL R ATEMPEN VSEL HTE HTDS HTIE HTIF W 0x0011 CPMU LVCTL R0 0 0 0 0 L V D S LVIE LVIF W 0x0012 CPMU APICTL R APICLK APIES APIEA APIFE APIE APIF W 0x0013 CPMUACLKTR R ACLKTR5 ACLKTR4 ACLKTR3 ACLKTR2 ACLKTR1 ACLKTR0 W 0x0014 CPMUAPIRH R APIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8 W 0x0015 CPMUAPIRL R APIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0 W 0x0016 RESERVED R 0 0 0 0 0 0 0 0 W 0x0017 CPMUHTTR R HTOE 000 HTTR3 HTTR2 HTTR1 HTTR0 W 0x0018 CPMU IRCTRIMH R TCTRIM[4:0] IRCTRIM[9:8] W 0x0019 CPMU IRCTRIML R IRCTRIM[7:0] W 0x001A CPMUOSC R OSCE Reserved 000 0 0 W 0x001B CPMUPROT R0 0 0 0 0 0 0 PROT W 0x001C RESERVED CPMUTEST2 R 0 0 0 0 0 W 0x001D CPMU VREGCTL R0 0 0 0 0 0 EXTXON INTXON W 0x001E CPMUOSC2 R0 0 0 0 0 0 OMRE OSCMOD W 0x001F RESERVED R0 0 0 0 0 0 0 0 W Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 8-3. CPMU Register Summary
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8.3.2 Register Descriptions
This section describes all the S12CPMU_UHV_V11 registers and their individual bits. Address order is as listed in Figure 8-3
8.3.2.1 Reserved Register CPMUVREGTRIM0
This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU_UHV_V11’s functionality. Read: Anytime Write: Only in Special Mode
8.3.2.2 Reserved Register CPMUVREGTRIM1
This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU_UHV_V11’s functionality. Module Base + 0x0001 76543210 R0 0 0 0 U W R e s e t 0000FFFF Power on Reset 00000000 Note: After de-assert of System Reset a value is automatically loaded from the Flash memory. Figure 8-4. Reserved Register (CPMUVREGTRIM0)
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Read: Anytime Write: Only in Special Mode
8.3.2.3 S12CPMU_UHV_V11 Rese t Flags Register (CPMURFLG)
This register provides S12CPMU_UHV_V11 reset flags. Read: Anytime Write: Refer to each bit for individual write conditions Module Base + 0x0002 76543210 R0 0 U 000 W Reset 0 0 F F F 0 0 0 Power on Reset 00000000 Note: After de-assert of System Reset a value is automatically loaded from the Flash memory. Figure 8-5. Reserved Register (CPMUVREGTRIM1) Module Base + 0x0003 76543210 PORF LVRF COPRF OMRF PMRF W Reset 0 Note 1 Note 2 0 Note 3 0 Note 4 Note 5 1. PORF is set to 1 when a power on reset occurs. Unaffected by System Reset. 2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by System Reset. Set by power on reset. 3. COPRF is set to 1 when COP reset occurs. Unaffected by System Reset. Cleared by power on reset. 4. OMRF is set to 1 when an oscillator clock monitor reset occurs. Unaffected by System Reset. Cleared by power on reset. 5. PMRF is set to 1 when a PLL clock monitor reset occurs. Unaffected by System Reset. Cleared by power on reset. = Unimplemented or Reserved Figure 8-6. S12CPMU_UHV_V11 Flags Register (CPMURFLG)
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8.3.2.4 S12CPMU_UHV_V11 Synthe sizer Register (CPMUSYNR)
The CPMUSYNR register controls the multiplication factor of the PLL and selects the VCO frequency range. Read: Anytime Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime. Else write has no effect. NOTE Writing to this register clears the LOCK and UPOSC status bits. Table 8-2. CPMURFLG Field Descriptions Field Description PORF Power on Reset Flag — PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Power on reset has not occurred. 1 Power on reset has occurred. LVRF Low Voltage Reset Flag — LVRF is set to 1 when a low voltage reset occurs on the VDD, VDDF or VDDX domain. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Low voltage reset has not occurred. 1 Low voltage reset has occurred. COPRF COP Reset Flag — COPRF is set to 1 when a COP (Computer Operating Properly) reset occurs. Refer to 8.5.5, “Computer Operating Properly Watchdog (COP) Reset and 8.3.2.12, “S12CPMU_UHV_V11 COP Control Register (CPMUCOP) for details.This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 COP reset has not occurred. 1 COP reset has occurred. OMRF Oscillator Clock Monitor Reset Flag — OMRF is set to 1 when a loss of oscillator (crystal) clock occurs. Refer to8.5.3, “Oscillator Clock Monitor Reset for details.This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Loss of oscillator clock reset has not occurred. 1 Loss of oscillator clock reset has occurred. PMRF PLL Clock Monitor Reset Flag — PMRF is set to 1 when a loss of PLL clock occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Loss of PLL clock re set has not occurred. 1 Loss of PLL clock reset has occurred. Module Base + 0x0004 76543210 R VCOFRQ[1:0] SYNDIV[5:0] W R e s e t 01011000 Figure 8-7. S12CPMU_UHV_V11 Synthesizer Register (CPMUSYNR)
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fVCO must be within the specified VCO frequency lock range. Bus frequency fbus must not exceed the specified maximum. The VCOFRQ[1:0] bits are used to configure the VCO gain for optimal stability and lock time. For correct PLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK frequency as shown in Table 8-3. Setting the VCOFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking and/or insufficient stability).
8.3.2.5 S12CPMU_UHV_V11 Reference Divider Register (CPMUREFDIV)
The CPMUREFDIV register provides a finer granularity for the PLL multiplier steps when using the external oscillator as reference. Read: Anytime Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime. Else write has no effect. NOTE Write to this register clears the LOCK and UPOSC status bits. Table 8-3. VCO Clock Frequency Selection VCOCLK Frequency Ranges VCOFRQ[1:0] 32MHz <= fVCO <= 48MHz 00 48MHz < fVCO <= 64MHz 01 Reserved 10 Reserved 11 Module Base + 0x0005 76543210 R REFFRQ[1:0] REFDIV[3:0] W R e s e t 00001111 Figure 8-8. S12CPMU_UHV_V11 Reference Divider Register (CPMUREFDIV) fVCO 2f REF SYNDIV 1+=If PLL has locked (LOCK=1)
Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 237 The REFFRQ[1:0] bits are used to configure the internal PLL filter for optimal stability and lock time. For correct PLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK frequency as shown in Table 8-4. If IRC1M is selected as REFCLK (OSCE=0) the PLL filter is fixed configured for the 1MHz <= fREF <= 2MHz range. The bits can still be written but will have no effect on the PLL filter configuration. For OSCE=1, setting the REFFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking and/or insufficient stability). Table 8-4. Reference Clock Frequency Selection if OSC_LCP is enabled REFCLK Frequency Ranges (OSCE=1) REFFRQ[1:0] 1MHz <= fREF <= 2MHz 00 2MHz < fREF <= 6MHz 01 6MHz < fREF <= 12MHz 10 fREF >12MHz 11 fREF fOSC If XOSCLCP is disabled (OSCE=0) fREF fIRC1M=
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8.3.2.6 S12CPMU_UHV_V11 Post Di vider Register (CPMUPOSTDIV)
The POSTDIV register controls the frequency ratio between the VCOCLK and the PLLCLK. Read: Anytime Write: If PLLSEL=1 write anytime, else write has no effect When changing the POSTDIV[4:0] value or PLL transitions to locked stated (lock=1), it takes up to 32 Bus Clock cycles until fPLL is at the desired target frequency. This is because the post divider gradually changes (increases or decreases) fPLL in order to avoid sudden load changes for the on-chip voltage regulator.
8.3.2.7 S12CPMU_UHV_V11 Interru pt Flags Register (CPMUIFLG)
This register provides S12CPMU_UHV_V11 status bits and interrupt flags. Module Base + 0x0006 76543210 R0 0 0 POSTDIV[4:0] W R e s e t 00000011 = Unimplemented or Reserved Figure 8-9. S12CPMU_UHV_V11 Post Divider Register (CPMUPOSTDIV) fPLL fVCO If PLL is not locked (LOCK=0) fPLL fVCO fbus fPLL
Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 239 Read: Anytime Write: Refer to each bit for individual write conditions Module Base + 0x0007 76543210 R RTIF LOCKIF LOCK 0 OSCIF UPOSC W R e s e t 00000000 = Unimplemented or Reserved Figure 8-10. S12CPMU_UHV_V11 Flags Register (CPMUIFLG) Table 8-5. CPMUIFLG Field Descriptions Field Description RTIF Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request. 0 RTI time-out has not yet occurred. 1 RTI time-out has occurred. LOCKIF PLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (LOCKIE=1), LOCKIF causes an interrupt request. 0 No change in LOCK bit. 1 LOCK bit has changed. LOCK Lock Status Bit — LOCK reflects the current state of PLL lock condition. Writes have no effect. While PLL is unlocked (LOCK=0) f PLL is fVCO / 4 to protect the system from high core clock frequencies during the PLL stabilization time tlock. 0 VCOCLK is not within the desired tolerance of the target frequency. fPLL = fVCO/4. 1 VCOCLK is within the desired to lerance of the target frequency. fPLL = fVCO/(POSTDIV+1). OSCIF Oscillator Interrupt Flag — OSCIF is set to 1 when UPOSC status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (OSCIE=1), OSCIF causes an interrupt request. 0 No change in UPOSC bit. 1 UPOSC bit has changed. UPOSC Oscillator Status Bit — UPOSC reflects the status of the oscillat or. Writes have no effect. Entering Full Stop Mode UPOSC is cleared. 0 The oscillator is off or oscillation is not qualified by the PLL. 1 The oscillator is qualified by the PLL.
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8.3.2.8 S12CPMU_UHV_V11 Interrupt Enable Register (CPMUINT)
This register enables S12CPMU_UHV_V11 interrupt requests. Read: Anytime Write: Anytime Module Base + 0x0008 76543210 R RTIE LOCKIE OSCIE W R e s e t 00000000 = Unimplemented or Reserved Figure 8-11. S12CPMU_UHV_V11 Interrupt Enable Register (CPMUINT) Table 8-6. CPMUINT Field Descriptions Field Description RTIE Real Time Interrupt Enable Bit 0 Interrupt requests from RTI are disabled. 1 Interrupt will be requested whenever RTIF is set. LOCKIE PLL Lock Interrupt Enable Bit 0 PLL LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set. OSCIE Oscillator Corrupt Interrupt Enable Bit 0 Oscillator Corrupt interrupt requests are disabled. 1 Interrupt will be requested whenever OSCIF is set.
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8.3.2.9 S12CPMU_UHV_V11 Clock Select Register (CPMUCLKS)
This register controls S12CPMU_UHV_V11 clock selection. Read: Anytime Write:
- Only possible if PROT=0 (CPM UPROT register) in all MCU Modes (Normal and Special Mode).
- All bits in Special Mode (if PROT=0).
- PLLSEL, PSTP, PRE, PCE, RTIOSCSEL: In Normal Mode (if PROT=0).
- CSAD: In Normal Mode (if PROT=0) unt il CPMUCOP write once has taken place.
- COPOSCSEL0: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place. If COPOSCSEL0 was cleared by UPOSC=0 (entering Full Stop Mode with COPOSCSEL0=1 or insufficient OSCCLK quality), then COPOSCSEL0 can be set once again.
- COPOSCSEL1: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place. COPOSCSEL1 will not be cleared by UPOSC=0 (entering Full Stop Mode with COPOSCSEL1=1 or insufficient OSCCLK quality if OSCCLK is used as clock source for other clock domains: for instance core clock etc.). NOTE After writing CPMUCLKS register, it is strongly recommended to read back CPMUCLKS register to make sure that write of PLLSEL, RTIOSCSEL and COPOSCSEL was successful. This is because under certain circumstances writes have no effect or bits are automatically changed (see CPMUCLKS register and bit descriptions). NOTE When using the oscillator clock as system clock (write PLLSEL = 0) it is highly recommended to enable the oscillator clock monitor reset feature (write OMRE = 1 in CPMUOSC2 register). If the oscillator monitor reset feature is disabled (OMRE = 0) and the oscillator clock is used as system clock, the system might stall in case of loss of oscillation. Module Base + 0x0009 76543210 R PLLSEL PSTP CSAD COP OSCSEL1 PRE PCE RTI OSCSEL COP OSCSEL0W R e s e t 10000000 = Unimplemented or Reserved Figure 8-12. S12CPMU_UHV_V11 Clock Select Register (CPMUCLKS)
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Table 8-7. CPMUCLKS Descriptions Field Description PLLSEL PLL Select Bit This bit selects the PLLCLK as source of the System Clocks (Core Clock and Bus Clock). PLLSEL can only be set to 0, if UPOSC=1. UPOSC= 0 sets the PLLSEL bit. Entering Full Stop Mode sets the PLLSEL bit. 0 System clocks are derived from OSCCLK if oscillator is up (UPOSC=1, fbus = fosc / 2). 1 System clocks are derived from PLLCLK, f bus = fPLL / 2. PSTP Pseudo Stop Bit This bit controls the functionality of the oscillator during Stop Mode. 0 Oscillator is disabled in Stop Mode (Full Stop Mode). 1 Oscillator continues to run in Stop Mode (P seudo Stop Mode), option to run RTI and COP. Note: Pseudo Stop Mode allows for faster STOP recovery and reduces the mechanical stress and aging of the resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption. Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time of the external oscillator tUPOSC before entering Pseudo Stop Mode. CSAD COP in Stop Mode ACLK Disable — If this bit is set the ACLK for the COP in Stop Mode is disabled. Hence the COP is static while in Stop Mode and continues to operate after exit from Stop Mode. For CSAD = 1 and COP is running on ACLK (COPOSCSEL1 = 1) the following applies: Due to clock domain crossing synchronization there is a latency time of 2 ACLK cycles to enter Stop Mode. After exit from STOP mode (when interrupt service routine is entered) the software has to wait for 2 ACLK cycles before it is allowed to enter Stop mode again (STOP instruction). It is absolutely forbidden to enter Stop Mode before this time of 2 ACLK cycles has elapsed. 0 COP running in Stop Mode (ACLK for COP enabled in Stop Mode).
1 COP stopped in Stop Mode (ACLK for COP disabled in Stop Mode)
COP Clock Select 1 — COPOSCSEL0 and COPOSCSEL1 combined determine the clock source to the COP (see also Table 8-8). If COPOSCSEL1 = 1, COPOSCSEL0 has no effect regarding clock select and changing the COPOSCSEL0 bit does not re-start the COP time-out period. COPOSCSEL1 selects the clock source to the COP to be either ACLK (derived from trimmable internal RC- Oscillator) or clock selected via COPOSCSEL0 (IRCCLK or OSCCLK). Changing the COPOSCSEL1 bit re-starts the COP time-out period. COPOSCSEL1 can be set independent from value of UPOSC. UPOSC= 0 does not clear the COPOSCSEL1 bit.
0 COP clock source defined by COPOSCSEL0
1 COP clock source is ACLK derived fr om a trimmable internal RC-Oscillator
RTI Enable During Pseudo Stop Bit — PRE enables the RTI during Pseudo Stop Mode. 0 RTI stops running during Pseudo Stop Mode. 1 RTI continues running during Pseudo Stop Mode if RTIOSCSEL=1. Note: If PRE=0 or RTIOSCSEL=0 then the RTI will go static while Stop Mode is active. The RTI counter will not be reset. PCE COP Enable During Pseudo Stop Bit — PCE enables the COP during Pseudo Stop Mode.
0 COP stops running during Pseudo Stop Mode
1 COP continues running during Pseudo Stop Mode if COPOSCSEL=1
Note: If PCE=0 or COPOSCSEL=0 then the COP will go static while Stop Mode is active. The COP counter will not be reset.
Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 243 Table 8-8. COPOSCSEL1, COPOSCSEL0 clock source select description RTIOSCSEL RTI Clock Select— RTIOSCSEL selects the clock source to the RTI. Either IRCCLK or OSCCLK. Changing the RTIOSCSEL bit re-starts the RTI time-out period. RTIOSCSEL can only be set to 1, if UPOSC=1. UPOSC= 0 clears the RTIOSCSEL bit. 0 RTI clock source is IRCCLK. 1 RTI clock source is OSCCLK. COP OSCSEL0 COP Clock Select 0 — COPOSCSEL0 and COPOSCSEL1 combined determine the clock source to the COP (see also Table 8-8) If COPOSCSEL1 = 1, COPOSCSEL0 has no effect regarding clock select and changing the COPOSCSEL0 bit does not re-start the COP time-out period. When COPOSCSEL1=0,COPOSCSEL0 selects the clock source to the COP to be either IRCCLK or OSCCLK. Changing the COPOSCSEL0 bit re-starts the COP time-out period. COPOSCSEL0 can only be set to 1, if UPOSC=1. UPOSC= 0 clears the COPOSCSEL0 bit. 0 COP clock source is IRCCLK.
1 COP clock source is OSCCLK
COPOSCSEL1 COPOSCSEL0 COP clock source 0 0 IRCCLK 0 1 OSCCLK 1x A C L K Table 8-7. CPMUCLKS Descriptions (continued) Field Description
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8.3.2.10 S12CPMU_UHV_V11 PLL Control Register (CPMUPLL)
This register controls the PLL functionality. Read: Anytime Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect. NOTE Write to this register clears the LOCK and UPOSC status bits. NOTE Care should be taken to ensure that the bus frequency does not exceed the specified maximum when frequency modulation is enabled. Module Base + 0x000A 76543210 R0 0 FM1 FM0 0000 W R e s e t 00000000 Figure 8-13. S12CPMU_UHV_V11 PLL Control Register (CPMUPLL) Table 8-9. CPMUPLL Field Descriptions Field Description 5, 4 FM1, FM0 PLL Frequency Modulation Enable Bits — FM1 and FM0 enable frequency modulation on the VCOCLK. This is to reduce noise emission. The modulation frequency is fref divided by 16. See Table 8-10 for coding. Table 8-10. FM Amplitude selection FM1 FM0 FM Amplitude / fVCO Variation
00 F M o f f
01 1% 10 2% 11 4%
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8.3.2.11 S12CPMU_UHV_V11 RTI Control Register (CPMURTI)
This register selects the time-out period for the Real Time Interrupt. The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode) and RTIOSCSEL=1 the RTI continues to run, else the RTI counter halts in Stop Mode. Read: Anytime Write: Anytime NOTE A write to this register starts the RTI time-out period. A change of the RTIOSCSEL bit (writing a different value or loosing UPOSC status) re- starts the RTI time-out period. Module Base + 0x000B 76543210 R RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 W R e s e t 00000000 Figure 8-14. S12CPMU_UHV_V11 RTI Control Register (CPMURTI) Table 8-11. CPMURTI Field Descriptions Field Description RTDEC Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values. 0 Binary based divider value. See Table 8-12 1 Decimal based divider value. See Table 8-13 6–4 RTR[6:4] Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI.See Table 8- 12 and Table 8-13. 3–0 RTR[3:0] Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to provide additional granularity.Table 8-12 and Table 8-13 show all possible divide values selectable by the CPMURTI register.
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Table 8-12. RTI Frequency Divide Rates for RTDEC = 0 RTR[3:0] RTR[6:4] = 000 (OFF) 001 (210) 010 (211) 011 (212) 100 (213) 101 (214) 110 (215) 111 (216) 0000 (1) OFF(1) 1. Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility. 210 211 212 213 214 215 216 0001 (2) OFF 2x2 10 2x211 2x212 2x213 2x214 2x215 2x216 0010 (3) OFF 3x2 10 3x211 3x212 3x213 3x214 3x215 3x216 0011 (4) OFF 4x2 10 4x211 4x212 4x213 4x214 4x215 4x216 0100 (5) OFF 5x2 10 5x211 5x212 5x213 5x214 5x215 5x216 0101 (6) OFF 6x2 10 6x211 6x212 6x213 6x214 6x215 6x216 0110 (7) OFF 7x2 10 7x211 7x212 7x213 7x214 7x215 7x216 0111 (8) OFF 8x2 10 8x211 8x212 8x213 8x214 8x215 8x216 1000 (9) OFF 9x2 10 9x211 9x212 9x213 9x214 9x215 9x216 1001 (10) OFF 10x2 10 10x211 10x212 10x213 10x214 10x215 10x216 1010 (11) OFF 11x2 10 11x211 11x212 11x213 11x214 11x215 11x216 1011 (12) OFF 12x2 10 12x211 12x212 12x213 12x214 12x215 12x216 1100 (13) OFF 13x2 10 13x211 13x212 13x213 13x214 13x215 13x216 1101 (14) OFF 14x2 10 14x211 14x212 14x213 14x214 14x215 14x216 1110 (15) OFF 15x2 10 15x211 15x212 15x213 15x214 15x215 15x216 1111 (16) OFF 16x2 10 16x211 16x212 16x213 16x214 16x215 16x216
Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 247 Table 8-13. RTI Frequency Divide Rates for RTDEC=1 RTR[3:0] RTR[6:4] = 000 (1x103) 001 (2x103) 010 (5x103) 011 (10x103) 100 (20x103) 101 (50x103) 110 (100x103) 111 (200x103) 0000 (1) 1x103 2x103 5x103 10x103 20x103 50x103 100x103 200x103 0001 (2) 2x103 4x103 10x103 20x103 40x103 100x103 200x103 400x103 0010 (3) 3x103 6x103 15x103 30x103 60x103 150x103 300x103 600x103 0011 (4) 4x103 8x103 20x103 40x103 80x103 200x103 400x103 800x103 0100 (5) 5x103 10x103 25x103 50x103 100x103 250x103 500x103 1x106 0101 (6) 6x103 12x103 30x103 60x103 120x103 300x103 600x103 1.2x106 0110 (7) 7x103 14x103 35x103 70x103 140x103 350x103 700x103 1.4x106 0111 (8) 8x103 16x103 40x103 80x103 160x103 400x103 800x103 1.6x106 1000 (9) 9x103 18x103 45x103 90x103 180x103 450x103 900x103 1.8x106 1001 (10) 10 x103 20x103 50x103 100x103 200x103 500x103 1x106 2x106 1010 (11) 11 x103 22x103 55x103 110x103 220x103 550x103 1.1x106 2.2x106 1011 (12) 12x103 24x103 60x103 120x103 240x103 600x103 1.2x106 2.4x106 1100 (13) 13x103 26x103 65x103 130x103 260x103 650x103 1.3x106 2.6x106 1101 (14) 14x103 28x103 70x103 140x103 280x103 700x103 1.4x106 2.8x106 1110 (15) 15x103 30x103 75x103 150x103 300x103 750x103 1.5x106 3x106 1111 (16) 16x103 32x103 80x103 160x103 320x103 800x103 1.6x106 3.2x106
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8.3.2.12 S12CPMU_UHV_V11 COP Control Register (CPMUCOP)
This register controls the COP (Computer Operating Properly) watchdog. The clock source for the COP is either ACLK, IRCCLK or OSCCLK depending on the setting of the COPOSCSEL0 and COPOSCSEL1 bit (see also Table 8-8). In Stop Mode with PSTP=1 (Pseudo Stop Mode), COPOSCSEL0=1 and COPOSCEL1=0 and PCE=1 the COP continues to run, else the COP counter halts in Stop Mode with COPOSCSEL1 =0. In Full Stop Mode and Pseudo Stop Mode with COPOSCSEL1=1 the COP continues to run. Read: Anytime Write: 1. RSBCK: Anytime in Special Mode; write to “1” but not to “0” in Normal Mode 2. WCOP, CR2, CR1, CR0: — Anytime in Special Mode, when WRTM ASK is 0, otherwise it has no effect — Write once in Normal Mode, when WRTM ASK is 0, otherwise it has no effect. – Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition. – Writing WCOP to “0” has no effect, but counts for the “write once” condition. When a non-zero value is loaded from Flash to CR[2:0] the COP time-out period is started. A change of the COPOSCSEL0 or COPOSCSEL1 bit (writing a different value) or loosing UPOSC status while COPOSCSEL1 is clear and COPOSCSEL0 is set, re-starts the COP time-out period. In Normal Mode the COP time-out period is restarted if either of these conditions is true: 1. Writing a non-zero value to CR[2:0] (anytime in special mode, once in normal mode) with WRTMASK = 0. 2. Writing WCOP bit (anytime in Special Mode , once in Normal Mode) with WRTMASK = 0. 3. Changing RSBCK bit from “0” to “1”. In Special Mode, any write access to CPMUCOP register restarts the COP time-out period. Module Base + 0x000C 76543210 R WCOP RSBCK 000 CR2 CR1 CR0 W WRTMASK R e s e t F0000FFF After de-assert of System Reset the values are automatically loaded from the Flash memory. See Device specification for details. = Unimplemented or Reserved Figure 8-15. S12CPMU_UHV_V11 COP Control Register (CPMUCOP)
Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 249 Table 8-14. CPMUCOP Field Descriptions Field Description WCOP Window COP Mode Bit — When set, a write to the CPMUARMCOP regi ster must occur in the last 25% of the selected period. A write during the first 75% of the selected period generates a COP reset. As long as all writes occur during this window, $55 can be written as often as desired. Once $AA is written after the $55, the time-out logic restarts and the user must wait until the next window before writing to CPMUARMCOP. Table 8-15 shows the duration of this window for the seven available COP rates.
0 Normal COP operation
1 Window COP operation
COP and RTI Stop in Active BDM Mode Bit 0 Allows the COP and RTI to keep running in Active BDM mode. 1 Stops the COP and RTI counters whene ver the part is in Active BDM mode. WRTMASK Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP and CR[2:0] bits while writing the CPMUCOP register. It is intended for BDM writing the RSBCK without changing the content of WCOP and CR[2:0].
0 Write of WCOP and CR[2:0] has an ef fect with this write of CPMUCOP
1 Write of WCOP and CR[2:0] has no ef fect with this write of CPMUCOP. (Does not count for “write once”.) 2–0 CR[2:0] COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see Table 8-15 and Table 8-16). Writing a nonzero value to CR[2:0] enables the COP counter and starts the time-out period. A COP counter time- out causes a System Reset. This can be avoided by periodically (before time-out) initializing the COP counter via the CPMUARMCOP register. While all of the following four conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at highest time-out period ( 2 24 cycles) in normal COP mode (Window COP mode disabled): 1) COP is enabled (CR[2:0] is not 000) 2) BDM mode active 3) RSBCK = 0 4) Operation in Special Mode Table 8-15. COP Watchdog Rates if COPOSCSEL1=0. (default out of reset) CR2 CR1 CR0 COPCLK Cycles to time-out (COPCLK is either IRCCLK or OSCCLK depending on the COPOSCSEL0 bit) 0 0 0 COP disabled 001 2 14 010 2 16 011 2 18 100 2 20 101 2 22 110 2 23 111 2 24
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Table 8-16. COP Watchdog Rates if COPOSCSEL1=1. CR2 CR1 CR0 COPCLK Cycles to time-out (COPCLK is ACLK divided by 2) 0 0 0 COP disabled 001 2 010 2 9 011 2 11 100 2 13 101 2 15 110 2 16 111 2 17
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8.3.2.13 Reserved Register CPMUTEST0
This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU_UHV_V11’s functionality. Read: Anytime Write: Only in Special Mode
8.3.2.14 Reserved Register CPMUTEST1
This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU_UHV_V11’s functionality. Read: Anytime Write: Only in Special Mode Module Base + 0x000D 76543210 R 00000000 W R e s e t 00000000 = Unimplemented or Reserved Figure 8-16. Reserved Register (CPMUTEST0) Module Base + 0x000E 76543210 R 00000000 W R e s e t 00000000 = Unimplemented or Reserved Figure 8-17. Reserved Register (CPMUTEST1)
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8.3.2.15 S12CPMU_UHV_V11 COP Timer Arm/Reset Register (CPMUARMCOP)
This register is used to restart the COP time-out period. Read: Always reads $00 Write: Anytime When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect. When the COP is enabled by setting CR[2:0] nonzero, the following applies: Writing any value other than $55 or $AA causes a COP reset. To restart the COP time-out period write $55 followed by a write of $AA. These writes do not need to occur back-to-back, but the sequence ($55, $AA) must be completed prior to COP end of time-out period to avoid a COP reset. Sequences of $55 writes are allowed. When the WCOP bit is set, $55 and $AA writes must be done in the last 25% of the selected time-out period; writing any value in the first 75% of the selected period will cause a COP reset.
8.3.2.16 H igh Temperature Control Register (CPMUHTCTL)
The CPMUHTCTL register configures the temperature sense features. Read: Anytime Write: ATEMPEN, VSEL, HTE, HTIE and HTIF are write anytime, HTDS is read only Module Base + 0x000F 76543210 R 00000000 W ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit R e s e t 00000000 Figure 8-18. S12CPMU_UHV_V11 CPMUARMCOP Register Module Base + 0x0010 76543210 R ATEMPEN VSEL HTE HTDS HTIE HTIF W R e s e t 00000000 = Unimplemented or Reserved Figure 8-19. High Temperature Control Register (CPMUHTCTL)
Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 253 NOTE The voltage at the temperature sensor can be computed as follows: VHT(temp) = VHT(150) - (150 - temp) * dVHT Table 8-17. CPMUHTCTL Field Descriptions Field Description ATEMPEN DVBE Temperature Sensor Enable Bit — This bit enables the DVBE temp erature sensor. The output voltage of the sensor can be converted with an ADC channel. See device level specification for availability and connectivity 0 DVBE temperature sensor is disabled. 1 DVBE temperature sensor is enabled.In Stop mode the DVBE temperature sensor is always disabled to reduce power consumption. VSEL Voltage Access Select Bit — If set, the bandgap reference voltage V BG can be accessed internally (i.e. multiplexed to an internal Analog to Digital Converter channel). If not set, the die temperature proportional voltage VHT of the temperature sensor can be accessed internally. See device level specification for connectivity. For any of these access the HTE bit must be set.
0 An internal temperature proportional voltage V
HT can be accessed internally. 1 Bandgap reference voltage V BG can be accessed internally. HTE High Temperature Sensor/Bandgap Voltage Enable Bit — This bit enables the high temperature sensor and bandgap voltage amplifier. 0 The temperature sensor and bandgap voltage amplifier is disabled. 1 The temperature sensor and bandgap voltage amplifier is enabled. HTDS High Temperature Detect Status Bit — This read-only status bit re flects the temperature status. Writes have no effect. 0 Junction Temperature is below level T HTID or RPM. 1 Junction Temperature is above level T HTIA and FPM. HTIE High Temperature Interrupt Enable Bit 0 Interrupt request is disabled. 1 Interrupt will be requested whenever HTIF is set. HTIF High Temperature Interrupt Flag — HTIF is set to 1 when HTDS status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (HTIE=1), HTIF causes an interrupt request. 0 No change in HTDS bit. 1 HTDS bit has changed.
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Figure 8-20. Voltage Access Select C HTD VBG ADC Ref ChannelVSEL TEMPSENSE
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8.3.2.17 Low Voltage Control Register (CPMULVCTL)
The CPMULVCTL register allows the configuration of the low-voltage detect features. Read: Anytime Write: LVIE and LVIF are write anytime, LVDS is read only Module Base + 0x0011 76543210 R 00000 L V D S LVIE LVIF W R e s e t 00000U0U The Reset state of LVDS and LVIF depends on the external supplied VDDA level = Unimplemented or Reserved Figure 8-21. Low Voltage Control Register (CPMULVCTL) Table 8-18. CPMULVCTL Field Descriptions Field Description LVDS Low-Voltage Detect Status Bit — This read-only status bit reflects the voltage level on VDDA. Writes have no effect. 0 Input voltage VDDA is above level V LVID or RPM. 1 Input voltage VDDA is below level V LVIA and FPM. LVIE Low-Voltage Interrupt Enable Bit 0 Interrupt request is disabled. 1 Interrupt will be requested whenever LVIF is set. LVIF Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request. 0 No change in LVDS bit. 1 LVDS bit has changed.
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8.3.2.18 Autonomous Periodical Interru pt Control Register (CPMUAPICTL)
The CPMUAPICTL register allows the configuration of the autonomous periodical interrupt features. Read: Anytime Write: Anytime Module Base + 0x0012 76543210 R APICLK APIES APIEA APIFE APIE APIF W R e s e t 00000000 = Unimplemented or Reserved Figure 8-22. Autonomous Periodical Interrupt Control Register (CPMUAPICTL) Table 8-19. CPMUAPICTL Field Descriptions Field Description APICLK Autonomous Periodical Interrupt Clock Select Bit — Selects the clock source fo r the API. Writable only if APIFE = 0. APICLK cannot be changed if APIFE is set by the same write operation. 0 Autonomous Clock (ACLK) used as source. 1 Bus Clock used as source. APIES Autonomous Periodical Interrupt External Select Bit — Selects the waveform at the external pin API_EXTCLK as shown in Figure 8-23. See device level specification for connectivity of API_EXTCLK pin. 0 If APIEA and APIFE are set, at the ex ternal pin API_EXTCLK periodic high pulses are visible at the end of every selected period with the size of half of the minimum period (APIR=0x0000 in Table 8-23). 1 If APIEA and APIFE are set, at the external pin API_EXTCLK a clock is visible with 2 times the selected API Period. APIEA Autonomous Periodical Interrupt External Access Enable Bit — If set, the waveform selected by bit APIES can be accessed externally. See device level specification for connectivity. 0 Waveform selected by APIES can not be accessed externally. 1 Waveform selected by APIES can be accessed externally, if APIFE is set. APIFE Autonomous Periodical Interrupt Feature Enable Bit — Enables the API feature and starts the API timer when set. 0 Autonomous periodical interrupt is disabled. 1 Autonomous periodical interrupt is enabled and timer starts running. APIE Autonomous Periodical Interrupt Enable Bit 0 API interrupt request is disabled. 1 API interrupt will be requested whenever APIF is set. APIF Autonomous Periodical Interrupt Flag — APIF is set to 1 when the in t he API configured time has elapsed. This flag can only be cleared by writing a 1.Writing a 0 has no effect. If enabled (APIE = 1), APIF causes an interrupt request. 0 API time-out has not yet occurred. 1 API time-out has occurred.
Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 257 Figure 8-23. Waveform selected on API_EXTCLK pin (APIEA=1, APIFE=1) APIES=0 APIES=1 API period API min. period / 2
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8.3.2.19 Autonomous Clock Trim ming Register (CPMUACLKTR)
The CPMUACLKTR register configures the trimming of the Autonomous Clock (ACLK - trimmable internal RC-Oscillator) which can be selected as clock source for some CPMU features. Read: Anytime Write: Anytime Module Base + 0x0013 76543210 R ACLKTR5 ACLKTR4 ACLKTR3 ACLKTR2 ACLKTR1 ACLKTR0 W R e s e t FFFFFF00 After de-assert of System Reset a value is automatically loaded from the Flash memory. Figure 8-24. Autonomous Clock Trimming Register (CPMUACLKTR) Table 8-20. CPMUACLKTR Field Descriptions Field Description 7–2 ACLKTR[5:0] Autonomous Clock Period Trimming Bits — See Table 8-21 for trimming effects. The ACLKTR[5:0] value represents a signed number influencing the ACLK period time. Table 8-21. Trimming Effect of ACLKTR[5:0] ACLKTR[5:0] Decimal ACLK frequency 100000 -32 lowest 100001 -31 increasing.... 111111 -1 000000 0 mid 000001 +1 increasing.... 011110 +30 011111 +31 highest
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8.3.2.20 Autonomous Periodical Inte rrupt Rate High and Low Register
(CPMUAPIRH / CPMUAPIRL) The CPMUAPIRH and CPMUAPIRL registers allow the configuration of the autonomous periodical interrupt rate. Read: Anytime Write: Anytime if APIFE=0, Else writes have no effect. The period can be calculated as follows depending on logical value of the APICLK bit: APICLK=0: Period = 2*(APIR[15:0] + 1) * (ACLK Clock Period * 2) APICLK=1: Period = 2*(APIR[15:0] + 1) * Bus Clock Period NOTE For APICLK bit clear the first time-out period of the API will show a latency time between two to three fACLK cycles due to synchronous clock gate release when the API feature gets enabled (APIFE bit set). Module Base + 0x0014 76543210 R APIR15 APIR14 APIR13 APIR1 2 APIR11 APIR10 APIR9 APIR8 W R e s e t 00000000 = Unimplemented or Reserved Figure 8-25. Autonomous Periodical Interrupt Rate High Register (CPMUAPIRH) Module Base + 0x0015 76543210 R APIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0 W R e s e t 00000000 Figure 8-26. Autonomous Periodical Interrupt Rate Low Register (CPMUAPIRL) Table 8-22. CPMUAPIRH / CPMUAPIRL Field Descriptions Field Description 15-0 APIR[15:0] Autonomous Periodical Interrupt Rate Bits — These bits define the time -out period of the API. See Table 8- 23 for details of the effect of the autonomous periodical interrupt rate bits.
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Table 8-23. Selectable Autonomous Periodical Interrupt Periods APICLK APIR[15:0] Selected Period 0 0000 0.2 ms (1) 1. When fACLK is trimmed to 20KHz. 0 0001 0.4 ms 1 0 0002 0.6 ms 1 0 0003 0.8 ms 1 0 0004 1.0 ms 1 0 0005 1.2 ms 1 0 FFFD 13106.8 ms 1 0 FFFE 13107.0 ms 1 0 FFFF 13107.2 ms 1 1 0000 2 * Bus Clock period 1 0001 4 * Bus Clock period 1 0002 6 * Bus Clock period 1 0003 8 * Bus Clock period 1 0004 10 * Bus Clock period 1 0005 12 * Bus Clock period
1 FFFD 131068 * Bus Clock period
1 FFFE 131070 * Bus Clock period
1 FFFF 131072 * Bus Clock period
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8.3.2.21 Reserved Register CPMUTEST3
This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU_UHV_V11’s functionality. Read: Anytime Write: Only in Special Mode Module Base + 0x0016 76543210 R 00000000 W R e s e t 00000000 = Unimplemented or Reserved Figure 8-27. Reserved Register (CPMUTEST3)
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8.3.2.22 High Temperature Tr imming Register (CPMUHTTR)
The CPMUHTTR register configures the trimming of the S12CPMU_UHV_V11 temperature sense. Read: Anytime Write: Anytime Module Base + 0x0017 76543210 R HTOE 000 HTTR3 HTTR2 HTTR1 HTTR0 W R e s e t 0000FFFF After de-assert of System Reset a trim value is automatically loaded from the Flash memory. See Device specification for details. = Unimplemented or Reserved Figure 8-28. High Temperature Trimming Register (CPMUHTTR) Table 8-25. CPMUHTTR Field Descriptions Field Description HTOE High Temperature Offset Enable Bit — If set the temperature sense offset is enabled. 0 The temperature sense offset is disabled. HTTR[3:0] bits don’t care. 1 The temperature sense offset is enabled. HTTR[3:0] select the temperature offset. 3–0 HTTR[3:0] High Temperature Trimming Bits — See Table 8-26 for trimming effects. Table 8-26. Trimming Effect of HTTR HTTR[3:0] Temperature sensor voltage VHT Interrupt threshold temperatures THTIA and THTID 0000 lowest highest 0001 increasing decreasing.... 1110 1111 highest lowest
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8.3.2.23 S12CPMU_UHV_V11 IRC1M Trim Registers (CPMUIRCTRIMH /
CPMUIRCTRIML) Read: Anytime Write: Anytime if PROT=0 (CPMUPROT register). Else write has no effect NOTE Writes to these registers while PLLSEL=1 clears the LOCK and UPOSC status bits. Module Base + 0x0018 15 14 13 12 11 10 9 8 R TCTRIM[4:0] IRCTRIM[9:8] W R e s e t FFFFF0FF After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to provide trimmed Internal Reference Frequency fIRC1M_TRIM. Figure 8-29. S12CPMU_UHV_V11 IRC1M Trim High Register (CPMUIRCTRIMH) Module Base + 0x0019 76543210 R IRCTRIM[7:0] W R e s e t FFFFFFFF After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to provide trimmed Internal Reference Frequency fIRC1M_TRIM. Figure 8-30. S12CPMU_UHV_V11 IRC1M Trim Low Register (CPMUIRCTRIML) Table 8-27. CPMUIRCTRIMH/L Field Descriptions Field Description 15-11 TCTRIM[4:0] IRC1M temperature coefficient Trim Bits Trim bits for the Temperature Coefficient (TC) of the IRC1M frequency. Table 8-28 shows the influence of the bits TCTRIM[4:0] on the relationship between frequency and temperature. Figure 8-32 shows an approximate TC variation, relative to the nominal TC of the IRC1M (i.e. for TCTRIM[4:0]=0x00000 or 0x10000). 9-0 IRCTRIM[9:0] IRC1M Frequency Trim Bits — Trim bits for Internal Reference Clock After System Reset the factory programmed trim value is automatically loaded into these registers, resulting in a Internal Reference Frequency f IRC1M_TRIM.See device electrical characteristics for value of fIRC1M_TRIM. The frequency trimming consists of two different trimming methods: A rough trimming controlled by bits IRCTRIM[9:6] can be done with frequency leaps of about 6% in average. A fine trimming controlled by bits IRCTRIM[5:0] can be done with frequency leaps of about 0.3% (this trimming determines the precision of the frequency setting of 0.15%, i.e. 0.3% is the distance between two trimming values). Figure 8-31 shows the relationship between the trim bits and the resulting IRC1M frequency.
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Figure 8-31. IRC1M Frequency Trimming Diagram IRCTRIM[9:0] $000 IRCTRIM[9:6] IRCTRIM[5:0] IRC1M frequency (IRCCLK) 600KHz 1.5MHz 1MHz $3FF
Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 265 Figure 8-32. Influence of TCTRIM[4:0] on the Temperature Coefficient NOTE The frequency is not necessarily linear with the temperature (in most cases it will not be). The above diagram is meant only to give the direction (positive or negative) of the variation of the TC, relative to the nominal TC. Setting TCTRIM[4:0] at 0x00000 or 0x10000 does not mean that the temperature coefficient will be zero. These two combinations basically switch off the TC compensation module, which results in the nominal TC of the IRC1M. frequency temperature TCTRIM[4:0] = 0x11111 TCTRIM[4:0] = 0x01111 - 40C 150C TCTRIM[4:0] = 0x10000 or 0x00000 (nominal TC) 0x00001 0x00010 0x00011 0x00100 0x00101 ... 0x01111 0x11111 ... 0x10101 0x10100 0x10011 0x10010 0x10001 TC increases TC decreases
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Table 8-28. TC trimming of the frequency of the IRC1M at ambient temperature NOTE Since the IRC1M frequency is not a linear function of the temperature, but more like a parabola, the above relative variation is only an indication and should be considered with care. TCTRIM[4:0] IRC1M Indicative relative TC variation IRC1M indicative frequency drift for relative TC variation 00000 0 (nominal TC of the IRC) 0% 00001 -0.27% -0.5% 00010 -0.54% -0.9% 00011 -0.81% -1.3% 00100 -1.08% -1.7% 00101 -1.35% -2.0% 00110 -1.63% -2.2% 00111 -1.9% -2.5% 01000 -2.20% -3.0% 01001 -2.47% -3.4% 01010 -2.77% -3.9% 01011 -3.04 -4.3% 01100 -3.33% -4.7% 01101 -3.6% -5.1% 01110 -3.91% -5.6% 01111 -4.18% -5.9% 10000 0 (nominal TC of the IRC) 0% 10001 +0.27% +0.5% 10010 +0.54% +0.9% 10011 +0.81% +1.3% 10100 +1.07% +1.7% 10101 +1.34% +2.0% 10110 +1.59% +2.2% 10111 +1.86% +2.5% 11000 +2.11% +3.0% 11001 +2.38% +3.4% 11010 +2.62% +3.9% 11011 +2.89% +4.3% 11100 +3.12% +4.7% 11101 +3.39% +5.1% 11110 +3.62% +5.6% 11111 +3.89% +5.9%
Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 267 Be aware that the output frequency varies with the TC trimming. A frequency trimming correction is therefore necessary. The values provided in Table 8-28 are typical values at ambient temperature which can vary from device to device.
8.3.2.24 S12CPMU_UHV_V11 Osc illator Register (CPMUOSC)
This registers configures the external oscillator (XOSCLCP). Read: Anytime Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect. NOTE. Write to this register clears the LOCK and UPOSC status bits. Module Base + 0x001A 76543210 R OSCE 0000000 W R e s e t 00000000 = Unimplemented or Reserved Figure 8-33. S12CPMU_UHV_V11 Oscillator Register (CPMUOSC) Table 8-29. CPMUOSC Field Descriptions Field Description OSCE Oscillator Enable Bit — This bit enables the external oscillator (XOSCLCP). The UPOSC status bit in the CPMIUFLG register indicates when the oscillation is stable and when OSCCLK can be selected as source of the Bus Clock or source of the COP or RTI.If the oscillator clock monitor reset is enabled (OMRE = 1 in CPMUOSC2 register), then a loss of oscillation will lead to an oscillator clock monitor reset. 0 External oscillator is disabled. REFCLK for PLL is IRCCLK. 1 External oscillator is enabled. Oscillator clock monitor is enabled. External oscillator is qualified by PLLCLK. REFCLK for PLL is the external oscillator clock divided by REFDIV. If OSCE bit has been set (write “1”) the EXTAL and XTAL pins are exclusively reserved for the oscillator and they can not be used anymore as general purpose I/O until the next system reset. Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time of the external oscillator tUPOSC before entering Pseudo Stop Mode.
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8.3.2.25 S12CPMU_UHV_V11 Protection Register (CPMUPROT)
This register protects the following important configuration registers from accidental overwrite: CPMUSYNR, CPMUREFDIV , CPMUCLKS, CPMUPLL, CPMUIRCTRIMH/L, CPMUOSC and CPMUOSC2 Read: Anytime Write: Anytime Module Base + 0x001B 76543210 R 0000000 PROT W R e s e t 00000000 Figure 8-34. S12CPMU_UHV_V11 Protection Register (CPMUPROT) Field Description PROT Clock Configuration Registers Protection Bit — This bit protects the clock and voltage regulator configuration registers from accidental overwrite (see list of protected registers above): Writing 0x26 to the CPMUPROT register clears the PROT bit, other write accesses set the PROT bit. 0 Protection of clock and voltage regulator configuration registers is disabled. 1 Protection of clock and voltage regulator configuration registers is enabled. (see list of protected registers above).
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8.3.2.26 Reserved Register CPMUTEST2
This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU_UHV_V11’s functionality. Read: Anytime Write: Only in Special Mode Module Base + 0x001C 76543210 R 0 0 0 0 0 W R e s e t 00000000 = Unimplemented or Reserved Figure 8-35. Reserved Register CPMUTEST2
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8.3.2.27 Voltage Regulator Control Register (CPMUVREGCTL)
The CPMUVREGCTL allows to enable or disable certain parts of the voltage regulator.This register must be configured after system startup. Read: Anytime Write: Once in normal modes, anytime in special modes Module Base + 0x001D 76543210 R 000000 EXTXON INTXON W R e s e t 00000011 = Unimplemented or Reserved Figure 8-36. Voltage Regulator Control Register (CPMUVREGCTL) Table 8-30. Effects of writing the EXTXON and INTXON bits value of EXTXON to be written value of INTXON to be written Write Access 0 0 blocked, no effect 0 1 legal access 1 0 legal access 1 1 blocked, no effect Table 8-31. CPMUVREGCTL Field Descriptions Field Description EXTXON External voltage regulator Enable Bit for VDDX domain — Should be set to 1 if external BJT is present on the PCB, cleared otherwise.
0 VDDX control loop does not use external BJT
1 VDDX control loop uses external BJT
Internal voltage regulator Enable Bit for VDDX domain— Should be set to 1 if no external BJT is present on the PCB, cleared otherwise.
0 VDDX control loop does not use internal power transistor
1 VDDX control loop uses internal power transistor
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8.3.2.28 S12CPMU_UHV_V11 Osc illator Register 2 (CPMUOSC2)
This registers configures the external oscillator (XOSCLCP). Read: Anytime Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect. Module Base + 0x001E 76543210 R 000000 OMRE OSCMOD W R e s e t 00000000 Figure 8-37. S12CPMU_UHV_V11 Oscillator Register 2 (CPMUOSC2) Table 8-32. CPMUOSC2 Field Descriptions Field Description OMRE This bit enables the oscillator clock monitor reset. If OSCE bit in CPMUOSC register is 1, then the OMRE bit can not be changed (writes will have no effect).
0 Oscillator clock monitor reset is disabled
1 Oscillator clock monitor reset is enabled
This bit selects the mode of the external oscillator (XOSCLCP) If OSCE bit in CPMUOSC register is 1, then the OSCMOD bit can not be changed (writes will have no effect).
0 External oscillator configured for loop cont rolled mode (reduced amplitude on EXTAL and XTAL))
1 External oscillator configured for full swing mode (full swing amplitude on EXTAL and XTAL)
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8.4 Functional Description
8.4.1 Phase Locked Loop wi th Internal Filter (PLL)
The PLL is used to generate a high speed PLLCLK based on a low frequency REFCLK. The REFCLK is by default the IRCCLK which is trimmed to fIRC1M_TRIM=1MHz. If using the oscillator (OSCE=1) REFCLK will be based on OSCCLK. For increased flexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency REFCLK using the REFDIV[3:0] bits. Based on the SYNDIV[5:0] bits the PLL generates the VCOCLK by multiplying the reference clock by a 2, 4, 6,... 126, 128. Based on the POSTDIV[4:0] bits the VCOCLK can be divided in a range of 1,2, 3, 4, 5, 6,... to 32 to generate the PLLCLK. NOTE Although it is possible to set the dividers to command a very high clock frequency, do not exceed the specified bus frequency limit for the MCU. fVCO 2f REF SYNDIV 1+= fREF fOSC If oscillator is disabled (OSCE=0) fREF fIRC1M= fPLL fVCO If PLL is not locked (LOCK=0) fPLL fVCO fbus fPLL
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Several examples of PLL divider settings are shown in Table 8-33. The following rules help to achieve optimum stability and shortest lock time:
- Use lowest possible f VCO / fREF ratio (SYNDIV value).
- Use highest possible REFCLK frequency f REF. The phase detector inside the PLL compares the feedback clock (FBCLK = VCOCLK/(SYNDIV+1)) with the reference clock (REFCLK = (IRC1M or OSCCLK)/(REFDIV+1)). Correction pulses are generated based on the phase difference between the two signals. The loop filter alters the DC voltage on the internal filter capacitor, based on the width and direction of the correction pulse which leads to a higher or lower VCO frequency. The user must select the range of the REFCLK frequency (REFFRQ[1:0] bits) and the range of the VCOCLK frequency (VCOFRQ[1:0] bits) to ensure that the correct PLL loop bandwidth is set. The lock detector compares the frequencies of the FBCLK and the REFCLK. Therefore the speed of the lock detector is directly proportional to the reference clock frequency. The circuit determines the lock condition based on this comparison. So e.g. a failure in the reference clock will cause the PLL not to lock. If PLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and for instance check the LOCK bit. If interrupt requests are disabled, software can poll the LOCK bit continuously (during PLL start-up) or at periodic intervals. In either case, only when the LOCK bit is set, the VCOCLK will have stabilized to the programmed frequency.
- The LOCK bit is a read-only indica tor of the locked state of the PLL.
- The LOCK bit is set when the VCO frequency is within the tolerance, Lock, and is cleared when the VCO frequency is out of the tolerance, unl.
- Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling the LOCK bit. In case of loss of reference clock (e.g. IRCCLK) the PLL will not lock or if already locked, then it will unlock. The frequency of the VCOCLK will be very low and will depend on the value of the VCOFRQ[1:0] bits. Table 8-33. Examples of PLL Divider Settings fosc REFDIV[3:0] f REF REFFRQ[1:0] SYNDIV[5:0] f VCO VCOFRQ[1:0] POSTDIV[4:0] f PLL fbus off $00 1MHz 00 $18 50MHz 01 $03 12.5MHz 6.25MHz off $00 1MHz 00 $18 50MHz 01 $00 50MHz 25MHz 4MHz $00 4MHz 01 $05 48MHz 00 $00 48MHz 24MHz
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8.4.2 Startup from Reset
An example for startup of the clock system from Reset is given in Figure 8-38. Figure 8-38. Startup of clock system after Reset System PLLCLK = Reset fVCORST CPU reset state vector fetch, program execution LOCK POSTDIV $03 (default target fPLL=fVCO/4 = 12.5MHz) fPLL increasing fPLL=12.5MHz tlock SYNDIV $18 (default target fVCO=50MHz) $00 fPLL=50MHz example change of POSTDIV ) ( RESET Pin ) ( 768 cycles startup fVCORST nSTARTUP cycles fBUS 512 cycles fVCORST 256 cycles f VCORST Core Clock Bus Clock = fBUS increasing fBUS=6.25MHz fBUS=25MHz ) ( ) (Core Clock/2
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8.4.3 Stop Mode using PLLCLK as source of the Bus Clock
An example of what happens going into Stop Mode and exiting Stop Mode after an interrupt is shown in Figure 8-39. Disable PLL Lock interrupt (LOCKIE=0) before going into Stop Mode. Figure 8-39. Stop Mode using PLLCLK as source of the Bus Clock Depending on the COP configuration there might be an additional significant latency time until COP is active again after exit from Stop Mode due to clock domain crossing synchronization. This latency time occurs if COP clock source is ACLK and the CSAD bit is set (please refer to CSAD bit description for details).
8.4.4 Full Stop Mode using Oscillato r Clock as source of the Bus Clock
An example of what happens going into Full Stop Mode and exiting Full Stop Mode after an interrupt is shown in Figure 8-40. Disable PLL Lock interrupt (LOCKIE=0) and oscillator status change interrupt (OSCIE=0) before going into Full Stop Mode. PLLCLK CPU LOCK tlock STOP instructionexecution interrupt continue execution wake up tSTP_REC
Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 277 Figure 8-40. Full Stop Mode using Oscillator Clock as source of the Bus Clock Depending on the COP configuration there might be an additional significant latency time until COP is active again after exit from Stop Mode due to clock domain crossing synchronization. This latency time occurs if COP clock source is ACLK and the CSAD bit is set (please refer to CSAD bit description for details). CPU UPOSC tlock STOP instructionexecution interrupt continue execution wake up tSTP_RECCore Clock select OSCCLK as Core/Bus Clock by writing PLLSEL to “0” PLLSEL automatically set when going into Full Stop Mode OSCCLK PLLCLK crystal/resonator starts oscillating tUPOSC
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8.4.5 External Oscillator
8.4.5.1 Enabling the External Oscillator
An example of how to use the oscillator as source of the Bus Clock is shown in Figure 8-41. Figure 8-41. Enabling the external oscillator PLLSEL OSCE OSCCLK Core enable external oscillator by writing OSCE bit to one. crystal/resonator starts oscillating UPOSC UPOSC flag is set upon successful start of oscillation select OSCCLK as Core/Bus Clock by writing PLLSEL to zero Clock based on PLL Clock based on OSCCLK tUPOSC
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8.4.6 System Clock Configurations
8.4.6.1 PLL Engaged Internal Mode (PEI)
This mode is the default mode after System Reset or Power-On Reset. The Bus Clock is based on the PLLCLK, the reference clock for the PLL is internally generated (IRC1M). The PLL is configured to 50 MHz VCOCLK with POSTDIV set to 0x03. If locked (LOCK=1) this results in a PLLCLK of 12.5 MHz and a Bus Clock of 6.25 MHz. The PLL can be re-configured to other bus frequencies. The clock sources for COP and RTI can be based on the internal reference clock generator (IRC1M) or the RC-Oscillator (ACLK).
8.4.6.2 PLL Engaged Ex ternal Mode (PEE)
In this mode, the Bus Clock is based on the PLLCLK as well (like PEI). The reference clock for the PLL is based on the external oscillator. The clock sources for COP and RTI can be based on the internal reference clock generator or on the external oscillator clock or the RC-Oscillator (ACLK). This mode can be entered from default mode PEI by performing the following steps: 1. Configure the PLL for desired bus frequency. 2. Enable the external Oscillator (OSCE bit). 3. Wait for oscillator to star t-up and the PLL being locked (LOCK = 1) and (UPOSC =1). 4. Clear all flags in the CPMUIFLG register to be able to detect any future status bit change. 5. Optionally status interrupts can be enabled (CPMUINT register). Loosing PLL lock status (LOCK=0) means loosing the oscillator status information as well (UPOSC=0). The impact of loosing the oscillator status (UPOSC=0) in PEE mode is as follows:
- The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the PLL locks again. Application software needs to be prepared to deal with the impact of loosing the oscillator status at any time.
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8.4.6.3 PLL Bypassed External Mode (PBE)
In this mode, the Bus Clock is based on the external oscillator clock. The reference clock for the PLL is based on the external oscillator. The clock sources for COP and RTI can be based on the internal reference clock generator or on the external oscillator clock or the RC-Oscillator (ACLK). This mode can be entered from default mode PEI by performing the following steps: 1. Make sure the PLL configuration is valid. 2. Enable the external Oscillator (OSCE bit) 3. Wait for the oscillator to start-up and the PLL being locked (LOCK = 1) and (UPOSC =1) 4. Clear all flags in the CPMUIFLG register to be able to detect any status bit change. 5. Optionally status interrupts can be enabled (CPMUINT register). 6. Select the Oscillator clock as source of the Bus clock (PLLSEL=0) Loosing PLL lock status (LOCK=0) means loosing the oscillator status information as well (UPOSC=0). The impact of loosing the oscillator status (UPOSC=0) in PBE mode is as follows:
- PLLSEL is set automatically and the Bus clock is switched back to the PLL clock.
- The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the PLL locks again. NOTEApplication software needs to be prepared to deal with the impact of loosing the oscillator status at any time. When using the oscillator clock as system clock (write PLLSEL = 0) it is highly recommended to enable the oscillator clock monitor reset feature (write OMRE = 1 in CPMUOSC2 register). If the oscillator monitor reset feature is disabled (OMRE = 0) and the oscillator clock is used as system clock, the system might stall in case of loss of oscillation.
8.5 Resets
8.5.1 General
All reset sources are listed in Table 8-34. There is only one reset vector for all these reset sources. Refer to MCU specification for reset vector address. Table 8-34. Reset Summary Reset Source Local Enable Power-On Reset (POR) None Low Voltage Reset (LVR) None External pin RESET None PLL Clock Monitor Reset None
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8.5.2 Description of Reset Operation
Upon detection of any reset of Table 8-34, an internal circuit drives the RESET pin low for 512 PLLCLK cycles. After 512 PLLCLK cycles the RESET pin is released. The internal reset of the MCU remains asserted while the reset generator completes the 768 PLLCLK cycles long reset sequence.In case the RESET pin is externally driven low for more than these 768 PLLCLK cycles (External Reset), the internal reset remains asserted longer. NOTE While System Reset is asserted the PLLCLK runs with the frequency fVCORST. Figure 8-42. RESET Timing
8.5.3 Oscillator Clock Monitor Reset
If the external oscillator is enabled (OSCE=1)and the oscillator clock monitor reset is enabled (OMRE=1), then in case of loss of oscillation or the oscillator frequency drops below the failure assert frequency fCMFA (see device electrical characteristics for values), the S12CPMU_UHV_V11 generates an Oscillator Clock Monitor Reset. In Full Stop Mode the external oscillator and the oscillator clock monitor are disabled. Oscillator Clock Monitor Reset OSCE Bit in CPMUOSC register and OMRE Bit in CPMUOSC2 register COP Reset CR[2:0] in CPMUCOP register Table 8-34. Reset Summary Reset Source Local Enable PLLCLK 512 cycles 256 cycles S12_CPMU drives possibly RESET driven low RESET S12_CPMU releases fVCORST RESET pin low RESET pin fVCORST
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8.5.4 PLL Clock Monitor Reset
In case of loss of PLL clock oscillation or the PLL clock frequency is below the failure assert frequency fPMFA (see device electrical characteristics for values), the S12CPMU_UHV_V11 generates a PLL Clock Monitor Reset. In Full Stop Mode the PLL and the PLL clock monitor are disabled.
8.5.5 Computer Operating Prop erly Watchdog (COP) Reset
The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly. When the COP is being used, software is responsible for keeping the COP from timing out. If the COP times out it is an indication that the software is no longer being executed in the intended sequence; thus COP reset is generated. The clock source for the COP is either ACLK, IRCCLK or OSCCLK depending on the setting of the COPOSCSEL0 and COPOSCSEL1 bit. Depending on the COP configuration there might be a significant latency time until COP is active again after exit from Stop Mode due to clock domain crossing synchronization. This latency time occurs if COP clock source is ACLK and the CSAD bit is set (please refer to CSAD bit description for details) Table 8-35 gives an overview of the COP condition (run, static) in Stop Mode depending on legal configuration and status bit settings: Table 8-35. COP condition (run, static) in Stop Mode COPOSCSEL1 CSAD PSTP PCE COPOSCSEL0 OSCE UPOSC COP counter behavior in Stop Mode (clock source) 10 x x xx x R u n ( A C L K ) 11 x x xx x S t a t i c ( A C L K ) 0x 1 1 11 1 R u n ( O S C C L K ) 0 x 1 1 0 0 x Static (IRCCLK) 0 x 1 1 0 1 x Static (IRCCLK) 0 x 1 0 0 x x Static (IRCCLK) 0x 1 0 11 1 S t a t i c ( O S C C L K ) 0x 0 11 1 1 S t a t i c ( O S C C L K ) 0 x 0 1 0 1 x Static (IRCCLK) 0 x 0 1 0 0 0 Static (IRCCLK) 0 x 0 0 1 1 1 Satic (OSCCLK) 0 x 0 0 0 1 1 Static (IRCCLK) 0 x 0 0 0 1 0 Static (IRCCLK) 0 x 0 0 0 0 0 Static (IRCCLK)
Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 283 Three control bits in the CPMUCOP register allow selection of seven COP time-out periods. When COP is enabled, the program must write $55 and $AA (in this order) to the CPMUARMCOP register during the selected time-out period. Once this is done, the COP time-out period is restarted. If the program fails to do this and the COP times out, a COP reset is generated. Also, if any value other than $55 or $AA is written, a COP reset is generated. Windowed COP operation is enabled by setting WCOP in the CPMUCOP register. In this mode, writes to the CPMUARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out period. A premature write will immediately reset the part. In MCU Normal Mode the COP time-out period (CR[2:0]) and COP window (WCOP) setting can be automatically pre-loaded at reset release from NVM memory (if values are defined in the NVM by the application). By default the COP is off and no window COP feature is enabled after reset release via NVM memory. The COP control register CPMUCOP can be written once in an application in MCU Normal Mode to update the COP time-out period (CR[2:0]) and COP window (WCOP) setting loaded from NVM memory at reset release. Any value for the new COP time-out period and COP window setting is allowed except COP off value if the COP was enabled during pre-load via NVM memory. The COP clock source select bits can not be pre-loaded via NVM memory at reset release. The IRC clock is the default COP clock source out of reset. The COP clock source select bits (COPOSCSEL0/1) and ACLK clock control bit in Stop Mode (CSAD) can be modified until the CPMUCOP register write once has taken place. Therefore these control bits should be modified before the final COP time-out period and window COP setting is written. The CPMUCOP register access to modify the COP time-out period and window COP setting in MCU Normal Mode after reset release must be done with the WRTMASK bit cleared otherwise the update is ignored and this access does not count as the write once.
8.5.6 Power-On Reset (POR)
The on-chip POR circuitry detects when the internal supply VDD drops below an appropriate voltage level. The POR is deasserted, if the internal supply VDD exceeds an appropriate voltage level (voltage levels not specified, because the internal supply can not be monitored externally).The POR circuitry is always active. It acts as LVR in Stop Mode.
8.5.7 Low-Voltage Reset (LVR)
The on-chip LVR circuitry detects when one of the supply voltages VDD, VDDX and VDDF drops below an appropriate voltage level. If LVR is deasserted the MCU is fully operational at the specified maximum speed. The LVR assert and deassert levels for the supply voltage VDDX are VLVRXA and VLVRXD and are specified in the device Reference Manual.The LVR circuitry is active in Run- and Wait Mode.
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8.6 Interrupts
The interrupt vectors requested by the S12CPMU_UHV_V11 are listed in Table 8-36. Refer to MCU specification for related vector addresses and priorities.
8.6.1 Description of Interrupt Operation
8.6.1.1 Real Time Interrupt (RTI)
The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode), RTIOSCSEL=1 and PRE=1 the RTI continues to run, else the RTI counter halts in Stop Mode. The RTI can be used to generate hardware interrupts at a fixed periodic rate. If enabled (by setting RTIE=1), this interrupt will occur at the rate selected by the CPMURTI register. At the end of the RTI time- out period the RTIF flag is set to one and a new RTI time-out period starts immediately. A write to the CPMURTI register restarts the RTI time-out period.
8.6.1.2 PLL Lock Interrupt
The S12CPMU_UHV_V11 generates a PLL Lock interrupt when the lock condition (LOCK status bit) of the PLL changes, either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting the LOCKIE bit to zero. The PLL Lock interrupt flag (LOCKIF) is set to1 when the lock condition has changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
8.6.1.3 Oscillator Status Interrupt
When the OSCE bit is 0, then UPOSC stays 0. When OSCE=1 the UPOSC bit is set after the LOCK bit is set. Table 8-36. S12CPMU_UHV_V11 Interrupt Vectors Interrupt Source CCR Mask Local Enable RTI time-out interrupt I bit CPMUINT (RTIE) PLL lock interrupt I bit CPMUINT (LOCKIE) Oscillator status interrupt I bit CPMUINT (OSCIE) Low voltage interrupt I bit CPMULVCTL (LVIE) High temperature interrupt I bit CPMUHTCTL (HTIE) Autonomous Periodical Interrupt I bit CPMUAPICTL (APIE)
Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 285 Upon detection of a status change (UPOSC) the OSCIF flag is set. Going into Full Stop Mode or disabling the oscillator can also cause a status change of UPOSC. Any change in PLL configuration or any other event which causes the PLL lock status to be cleared leads to a loss of the oscillator status information as well (UPOSC=0). Oscillator status change interrupts are locally enabled with the OSCIE bit. NOTE Loosing the oscillator status (UPOSC=0) affects the clock configuration of the system1. This needs to be dealt with in application software.
8.6.1.4 Low-Voltage Interrupt (LVI)
In FPM the input voltage VDDA is monitored. Whenever VDDA drops below level VLVIA, the status bit LVDS is set to 1. When VDDA rises above level VLVID the status bit LVDS is cleared to 0. An interrupt, indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable bit LVIE = 1.
8.6.1.5 HTI - High Temperature Interrupt
In FPM the junction temperature TJ is monitored. Whenever TJ exceeds level THTIA the status bit HTDS is set to 1. Vice versa, HTDS is reset to 0 when TJ get below level THTID. An interrupt, indicated by flag HTIF = 1, is triggered by any change of the status bit HTDS, if interrupt enable bit HTIE = 1.
8.6.1.6 Autonomous Peri odical Interrupt (API)
The API sub-block can generate periodical interrupts independent of the clock source of the MCU. To enable the timer, the bit APIFE needs to be set. The API timer is either clocked by the Autonomous Clock (ACLK - trimmable internal RC oscillator) or the Bus Clock. Timer operation will freeze when MCU clock source is selected and Bus Clock is turned off. The clock source can be selected with bit APICLK. APICLK can only be written when APIFE is not set. The APIR[15:0] bits determine the interrupt period. APIR[15:0] can only be written when APIFE is cleared. As soon as APIFE is set, the timer starts running for the period selected by APIR[15:0] bits. When the configured time has elapsed, the flag APIF is set. An interrupt, indicated by flag APIF = 1, is triggered if interrupt enable bit APIE = 1. The timer is re-started automatically again after it has set APIF. The procedure to change APICLK or APIR[15:0] is first to clear APIFE, then write to APICLK or APIR[15:0], and afterwards set APIFE. The API Trimming bits ACLKTR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency is desired. See Table 8-21 for the trimming effect of ACLKTR[5:0]. 1. For details please refer to “8.4.6 System Clock Configurations”
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The first period after enabling the counter by APIFE might be reduced by API start up delay tsdel. It is possible to generate with the API a waveform at the external pin API_EXTCLK by setting APIFE and enabling the external access with setting APIEA.
8.7 Initialization/Application Information
8.7.1 General Initialization Information
Usually applications run in MCU Normal Mode. It is recommended to write the CPMUCOP register in any case from the application program initialization routine after reset no matter if the COP is used in the application or not, even if a configuration is loaded via the flash memory after reset. By doing a “controlled” write access in MCU Normal Mode (with the right value for the application) the write once for the COP configuration bits (WCOP,CR[2:0]) takes place which protects these bits from further accidental change. In case of a program sequencing issue (code runaway) the COP configuration can not be accidentally modified anymore.
8.7.2 Application informatio n for COP and API usage
In many applications the COP is used to check that the program is running and sequencing properly. Often the COP is kept running during Stop Mode and periodic wake-up events are needed to service the COP on time and maybe to check the system status. For such an application it is recommended to use the ACLK as clock source for both COP and API. This guarantees lowest possible IDD current during Stop Mode. Additionally it eases software implementation using the same clock source for both, COP and API. The Interrupt Service Routine (ISR) of the Autonomous Periodic Interrupt API should contain the write instruction to the CPMUARMCOP register. The value (byte) written is derived from the “main routine” (alternating sequence of $55 and $AA) of the application software. Using this method, then in the case of a runtime or program sequencing issue the application “main routine” is not executed properly anymore and the alternating values are not provided properly. Hence the COP is written at the correct time (due to independent API interrupt request) but the wrong value is written (alternating sequence of $55 and $AA is no longer maintained) which causes a COP reset. If the COP is stopped during any Stop Mode it is recommended to service the COP shortly before Stop Mode is entered.
8.7.3 Application Information for PLL and Oscillator Startup
The following C-code example shows a recommended way of setting up the system clock system using the PLL and Oscillator:
Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 287 /* Procedure proposed by to setup PLL and Oscillator */ /* example for OSC = 4 MHz and Bus Clock = 25MHz, That is VCOCLK = 50MHz */ /* Initialize */ /* PLL Clock = 50 MHz, divide by one */ CPMUPOSTDIV = 0x00; /* Generally: Whenever changing PLL reference clock (REFCLK) frequency to a higher value */ /* it is recommended to write CPMUSYNR = 0x00 in order to stay within specified */ /* maximum frequency of the MCU */ CPMUSYNR = 0x00; /* configure PLL reference clock (REFCLK) for usage with Oscillator */ /* OSC=4MHz divide by 4 (3+1) = 1MHz, REFCLK range 1MHz to 2 MHz (REFFRQ[1:0] = 00) */ CPMUREFDV = 0x03; /* enable external Oscillator, switch PLL reference clock (REFCLK) to OSC */ CPMUOSC = 0x80; /* multiply REFCLK = 1MHz by 2*(24+1)*1MHz = 50MHz */ /* VCO range 48 to 80 MHz (VCOFRQ[1:0] = 01) */ CPMUSYNR = 0x58; /* clear all flags, especially LOCKIF and OSCIF */ CPMUIFLG = 0xFF; /* put your code to loop and wait for the LOCKIF and OSCIF or */ /* poll CPMUIFLG register until both UPOSC and LOCK status are “1” */ /* that is CPMIFLG == 0x1B */ /* in case later in your code you want to disable the Oscillator and use the */ /* 1MHz IRCCLK as PLL reference clock */ /* Generally: Whenever changing PLL reference clock (REFCLK) frequency to a higher value */ /* it is recommended to write CPMUSYNR = 0x00 in order to stay within specified */ /* maximum frequency of the MCU */ CPMUSYNR = 0x00; /* disable OSC and switch PLL reference clock to IRC */ CPMUOSC = 0x00; /* multiply REFCLK = 1MHz by 2*(24+1)*1MHz = 50MHz */ /* VCO range 48 to 80 MHz (VCOFRQ[1:0] = 01) */ CPMUSYNR = 0x58; /* clear all flags, especially LOCKIF and OSCIF */ CPMUIFLG = 0xFF; /* put your code to loop and wait for the LOCKIF or */ /* poll CPMUIFLG register until both LOCK status is “1” */ /* that is CPMIFLG == 0x18 */
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9.1 Differences ADC12B_LBA V1 vs V2 vs V3
Device reference manuals specify which module version is integrated on the device. Some reference manuals support families of devices, with device dependent module versions. This chapter describes the superset. The feature differences are listed in Table 9-2. Table 9-2. Comparison of ADC12B_LBA Module Versions Table 9-1. Revision History Revision Number Revision Date Sections Affected Description of Changes V1.37 19. Apr 2013 - Updates from review of reference manual to fix typos etc. Provided more detailed information regarding captured information in bits RIDX_IMD[5:0] for different scenarios of Sequence Abort Event execution. V1.40 02. Oct 2013 entire document Updated formatting and wording correction for entire document (for technical publications). V2.00 14. Oct. 2014 9.3/9-291, 9.5.2.15/9-320, 9.5.2.17/9-325, Figure 9-2./9-295, Added option bits to conversion command for top level SoC specific feature/function implementation option. 9.1/9-289 Changed ADCCMD_1 VRH_SEL, VRL_SEL Single document for all versions (V1,V2,V3) V3.02 23. Mar 2016 Table 9-9 Clarified CMD_EIF not set for reserved (12-bit) resolution setting F e a t u r e V 1V 2V 3 ADC Command Register 0 (ADCCMD_0), ADC Command Register 2 (ADCCMD_2): OPT[3:0] bits No Yes Yes ADC Command Register 1 (ADCCMD_1):VRH_SEL[1:0] No No Yes ADC Command Register 1 (ADCCMD_1):VRH_SEL,VRL_SEL Yes Yes No
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9.2 Introduction
The ADC12B_LBA is an n-channel multiplexed input successive approximation analog-to-digital converter. Refer to device electrical specifications for ADC parameters and accuracy. The List Based Architecture (LBA) provides flexible conversion sequence definition as well as flexible oversampling. The order of channels to be converted can be freely defined. Also, multiple instantiations of the module can be triggered simultaneously (matching sampling point across multiple module instantiations). There are four register bits which control the conversion flow (please refer to the description of register ADCFLWCTL). The four conversion flow control bits of register ADCFLWCTL can be modified in two different ways:
- Via data bus accesses
- Via internal interface Signals (Trigger, Restart, LoadOK, and Seq_Abort; see also Figure 9-2). Each Interface Signal is associated with one conversion flow control bit. For information regarding internal interface connectivity related to the conversion flow control please refer to the device overview of the reference manual. The ADCFLWCTL register can be controlled via internal interface only or via data bus only or by both depending on the register access configuration bits ACC_CFG[1:0]. The four bits of register ADCFLWCTL reflect the captured request and status of the four internal interface Signals (LoadOK, Trigger, Restart, and Seq_abort; see also Figure 9-2) if access configuration is set accordingly and indicate event progress (when an event is processed and when it is finished). Conversion flow error situations are captured by corresponding interrupt flags in the ADCEIF register. There are two conversion flow control modes (Restart Mode, Trigger Mode). Each mode causes a certain behavior of the conversion flow control bits which can be selected according to the application needs. conversion flow control Mode Configurations for more information regarding conversion flow control. Because internal components of the ADC are turned on/off with bit ADC_EN, the ADC requires a recovery time period (t REC) after ADC is enabled until the first conversion can be launched via a trigger. When bit ADC_EN gets cleared (transition from 1’b1 to 1’b0) any ongoing conversion sequence will be aborted and pending results, or the result of current conversion, gets discarded (not stored). The ADC cannot be re-enabled before any pending action or action in process is finished respectively aborted, which could take up to a maximum latency time of tDISABLE (see device level specification for more details).
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9.3 Key Features
- Programmer’s Model with List Based Architect ure for conversion command and result value organization
- Selectable resolution of 8-bit, 10-bit,
- Channel select control for n external analog input channels
- Provides up to eight device internal channe ls (please see the device reference manual for connectivity information and Figure 9-2)
- Programmable sample time
- A sample buffer amplifier for channel sampling (i mproved performance in view to influence of channel input path resistance versus conversion accuracy)
- Left/right justified result data
- Individual selectable VRH_0/1 and VRL_0/1 in puts (ADC12B_LBA V1 and V2) or VRH_0/1/2 inputs (ADC12B_LBA V3) on a conversion command basis (please see Figure 9-2, Table 9-2)
- Special conversions for selected VRH_0/1 (V 1 and V2) or VRH_0/1/2 (V3), VRL_0/1 (V1 and V2) or VRL_0 (V3), (VRL_0/1 + VRH_0/1) / 2 (V1 and V2) or (VRL_0 + VRH_0/1/2) / 2 (V3) (please see Table 9-2)
- 15 conversion interrupts with flexible in terrupt organization per conversion result
- One dedicated interrupt for “End Of List” type commands
- Command Sequence List (CSL) with a ma ximum number of 64 command entries
- Provides conversion sequence abort
- Restart from top of active Command Sequence List (CSL)
- The Command Sequence List and Result Value List are implemented in double buffered manner (two lists in parallel for each function)
- Conversion Command (CSL) loading possible from System RAM or NVM
- Single conversion flow control register with software selectable access path
- Two conversion flow contro l modes optimized to different application use cases
- Four option bits in the conversion command for top level SoC specific feature/function implementation option (Please refer to the device reference manual for details of the top level feature/function if implemented)
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9.3.1 Modes of Operation
9.3.1.1 Conversion Modes
This architecture provides single, multiple, or continuous conversion on a single channel or on multiple channels based on the Command Sequence List.
9.3.1.2 MCU Operating Modes
- MCU Stop Mode Before issuing an MCU Stop Mode request the ADC should be idle (no conversion or conversion sequence or Command Sequence List ongoing). If a conversion, conversion sequence, or CSL is in progress when an MCU Stop Mode request is issued, a Sequence Abort Event occurs automatically and any ongoing conversion finish. After the Sequence Abort Event finishes, if the STR_SEQA bit is set (STR_SEQA=1), then the conversion result is stored and the corresponding flags are set. If the STR_SEQA bit is cleared (STR_SEQA=0), then the conversion result is not stored and the corresponding flags are not set. The microcontroller then enters MCU Stop Mode without SEQAD_IF being set. Alternatively, the Sequence Abort Event can be issued by software before an MCU Stop Mode request. As soon as flag SEQAD_IF is set the MCU Stop Mode request can be is issued. With the occurrence of the MCU Stop Mode Request until exit from Stop Mode all flow control signals (RSTA, SEQA, LDOK, TRIG) are cleared. After exiting MCU Stop Mode, the following happens in the order given with expected event(s) depending on the conversion flow control mode: — In ADC conversion flow control mode “Trigge r Mode” a Restart Event is expected to simultaneously set bits TRIG and RSTA, causing the ADC to execute the Restart Event (CMD_IDX and RVL_IDX cleared) followed by the Trigger Event. The Restart Event can be generated automatically after exit from MCU Stop Mode if bit AUT_RSTA is set. — In ADC conversion flow control mode “Restart M ode”, a Restart Event is expected to set bit RSTA only (ADC already aborted at MCU Stop Mode entry hence bit SEQA must not be set simultaneously) causing the ADC to execute the Restart Event (CDM_IDX and RVL_IDX cleared). The Restart Event can be generated automatically after exit from MCU Stop Mode if bit AUT_RSTA is set. — The RVL buffer select (RVL_SEL) is not change d if a CSL is in process at MCU Stop Mode request. Hence the same buffer will be used after exit from Stop Mode that was used when the Stop Mode request occurred.
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- MCU Wait Mode Depending on the ADC Wait Mode configuration bit SWAI, the ADC either continues conversion in MCU Wait Mode or freezes conversion at the next conversion boundary before MCU Wait Mode is entered. ADC behavior for configuration SWAI =1’b0: The ADC continues conversion during Wait Mode according to the conversion flow control sequence. It is assumed that the conversion flow control sequence is continued (conversion flow control bits TRIG , RSTA, SEQA, and LDOK are serviced accordingly). ADC behavior for configuration SWAI = 1’b1: At MCU Wait Mode request the ADC should be idle (no conversion or conversion sequence or Command Sequence List ongoing). If a conversion, conversion sequence, or CSL is in progress when an MCU Wait Mode request is issued, a Sequence Abort Event occurs automatically and any ongoing conversion finish. After the Sequence Abort Event finishes, if the STR_SEQA bit is set (STR_SEQA=1), then the conversion result is stored and the corresponding flags are set. If the STR_SEQA bit is cleared (STR_SEQA=0), then the conversion result is not stored and the corresponding flags are not set. Alternatively the Sequence Abort Event can be issued by software before MCU Wait Mode request. As soon as flag SEQAD_IF is set, the MCU Wait Mode request can be issued. With the occurrence of the MCU Wait Mode request until exit from Wait Mode all flow control signals (RSTA, SEQA, LDOK, TRIG) are cleared. After exiting MCU Wait Mode, the following happens in the order given with expected event(s) depending on the conversion flow control mode: — In ADC conversion flow control mode “Trigger M ode”, a Restart Event is expected to occur. This simultaneously sets bit TRIG and RSTA causing the ADC to execute the Restart Event (CMD_IDX and RVL_IDX cleared) followed by the Trigger Event. The Restart Event can be generated automatically after exit from MCU Wait Mode if bit AUT_RSTA is set. — In ADC conversion flow control mode “Restart M ode”, a Restart Event is expected to set bit RSTA only (ADC already aborted at MCU Wait Mode entry hence bit SEQA must not be set simultaneously) causing the ADC to execute the Restart Event (CDM_IDX and RVL_IDX cleared). The Restart Event can be generated automatically after exit from MCU Wait Mode if bit AUT_RSTA is set. — The RVL buffer select (RVL_SEL) is not change d if a CSL is in process at MCU Wait Mode request. Hence the same RVL buffer will be used after exit from Wait Mode that was used when Wait Mode request occurred.
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In principle, the MCU could stay in Wait Mode for a shorter period of time than the ADC needs to abort an ongoing conversion (range of µµµµs). Therefore in case a Sequence Abort Event is issued automatically due to MCU Wait Mode request a following Restart Event after exit from MCU Wait Mode can not be executed before ADC has finished this Sequence Abort Event. The Restart Event is detected but it is pending. This applies in case MCU Wait Mode is exited before ADC has finished the Sequence Abort Event and a Restart Event is issued immediately after exit from MCU Wait Mode. Bit READY can be used by software to detect when the Restart Event can be issued without latency time in processing the event (see also Figure 9-1). Figure 9-1. Conversion Flow Control Diagram - Wait Mode (SWAI=1’b1, AUT_RSTA=1’b0)
- MCU Freeze Mode Depending on the ADC Freeze Mode configuration bit FRZ_MOD, the ADC either continues conversion in Freeze Mode or freezes conversion at next conversion boundary before the MCU Freeze Mode is entered. After exit from MCU Freeze Mode with previously frozen conversion sequence the ADC continues the conversion with the next conversion command and all ADC interrupt flags are unchanged during MCU Freeze Mode. CSL_0 Active AN3 AN1 AN4 IN5 AN6 AN1 Wait Mode request (SWAI=1’b1), Automatic Sequence Abort Event Wait Mode entry Wake-up Event Idle Active AN3 AN1 AN4 Abort Sequence_n EOS Sequence_0 AN5 AN2 AN0 Sequence_1 Trigger Begin from top of current CSL READY=1’b1 Restart Event Earliest point of time to issue Restart Event without latency t
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9.3.2 Block Diagram
Figure 9-2. ADC12B_LBA Block Diagram Successive Approximation Register (SAR) and C-DAC VSSA ANx ext. MUX Result List Result_0 Result_1 Sample & Hold VDDA VRH_0 VRH_1 Sequence Abort Int. Comparator Clock Prescaler System Clock ADC Clock Seq_abort Trigger Restart Result 63 AN2 AN1 AN0 Conversion (RAM) DMA access Command Comm_0 Comm_1 Comm 63 Sequence (RAM/ DMA access List Error handler active Active Alternative- Sequence Command List Idle/ LoadOK FlowCtrl Issue Error/ see reference manual for connectivity ADC Temperature Sense VREG_sense Internal_7 Internal_6 Internal_5 Internal_4 Internal_3 Internal_2 Channel int. MUX Channel (Conversion Flow, Timing, Interrupt) Control Unit Conversion Int. (RAM/ information (EN) Data Bus Alternative Result List (RAM) VRL_1 (V1, V2) VRL_0 Int. regarding ADC internal interface PIM Final Buffer Buffer AMP NVM) NVM) ADC10B_LBA Option Bits VRH_2 (V3)
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9.4 Signal Description
This section lists all inputs to the ADC12B_LBA block.
9.4.1 Detailed Signal Descriptions
This pin serves as the analog input Channel x. The maximum input channel number is n. Please refer to the device reference manual for the maximum number of input channels.
9.4.1.2 VRH_0, VRH_1, VRH_2, VRL_0, VRL_1
VRH_0/1/2 are the high reference voltages, VRL_0/1 are the low reference voltages for a ADC conversion selectable on a conversion command basis. Please refer to the device overview information for availability and connectivity of these pins. VRH_2 is only available on ADC12B_LBA V3. VRL_1 is only available on ADC12B_LBA V1 and V2. See also Table 9-2.
9.4.1.3 VDDA, VSSA
These pins are the power supplies for the analog circuitry of the ADC12B_LBA block.
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9.5 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the ADC12B_LBA.
9.5.1 Module Memory Map
Figure 9-3 gives an overview of all ADC12B_LBA registers. NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level. Address Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 ADCCTL_0 R ADC_EN ADC_SR FRZ_MOD SWAI ACC_CFG[1:0] STR_SEQ A MOD_CFGW 0x0001 ADCCTL_1 R CSL_BMO D RVL_BMO D SMOD_AC C AUT_RST A 00 0 0 W 0x0002 ADCSTS R CSL_SEL RVL_SEL DBECC_E RR Reserved READY 0 0 0 W 0x0003 ADCTIM R0 PRS[6:0]W 0x0004 ADCFMT R DJM 000 0 SRES[2:0]W 0x0005 ADCFLWCTL R SEQA TRIG RSTA LDOK 00 0 0 W 0x0006 ADCEIE R IA_EIE CMD_EIE EOL_EIE Reserved TRIG_EIE RSTAR_EI E LDOK_EIE 0 W 0x0007 ADCIE R SEQAD_IE CONIF_OI E Reserved 00 0 0 0 W 0x0008 ADCEiF R IA_EIF CMD_EIF EOL_EIF Reserved TRIG_EIF RSTAR_EI F LDOK_EIF 0 W 0x0009 ADCIF R SEQAD_IF CONIF_OI F Reserved 00 0 0 0 W 0x000A ADCCONIE_0 R CON_IE[15:8]W 0x000B ADCCONIE_1 R CON_IE[7:1] EOL_IEW 0x000C ADCCONIF_0 R CON_IF[15:8]W 0x000D ADCCONIF_1 R CON_IF[7:1] EOL_IFW 0x000E ADCIMDRI_0 R CSL_IMD RVL_IMD 00 0 0 00 0x000F ADCIMDRI_1 R 0 0 RIDX_IMD[5:0] W = Unimplemented or Reserved Figure 9-3. ADC12B_LBA Register Summary (Sheet 1 of 3)
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0x0010 ADCEOLRI R CSL_EOL RVL_EOL 0 0 0 0 0 0 W 0x0011 Reserved R0 0 0 0 0 0 0 0 W 0x0012 Reserved R0 0 0 0 0 0 0 0 W 0x0013 Reserved R Reserved Reserved 0 0 W 0x0014 ADCCMD_0 (V1) R CMD_SEL 00 INTFLG_SEL[3:0]W 0x0014 ADCCMD_0 (V2, V3) R CMD_SEL OPT[1:0] IN TFLG_SEL[3:0]W 0x0015 ADCCMD_1 (V1, V2) R VRH_SEL VRL_SEL CH_SEL[5:0]W 0x0015 ADCCMD_1 (V3) R VRH_SEL[1:0] CH_SEL[5:0]W 0x0016 ADCCMD_2 (V1) R SMP[4:0] 00 ReservedW 0x0016 ADCCMD_2 (V2, V3) R SMP[4:0] OPT[3:2] ReservedW 0x0017 ADCCMD_3 R Reserved Reserved ReservedW 0x0018 Reserved R ReservedW 0x0019 Reserved R ReservedW 0x001A Reserved R ReservedW 0x001B Reserved R ReservedW 0x001C ADCCIDX R0 0 C M D _ I D X [ 5 : 0 ] W 0x001D ADCCBP_0 R CMD_PTR[23:16]W 0x001E ADCCBP_1 R CMD_PTR[15:8]W 0x001F ADCCBP_2 R CMD_PTR[7:2] 00 W 0x0020 ADCRIDX R 0 0 RES_IDX[5:0] W 0x0021 ADCRBP_0 R0 0 0 0 RES_PTR[19:16]W 0x0022 ADCRBP_1 R RES_PTR[15:8]W 0x0023 ADCRBP_2 R RES_PTR[7:2] 00 W Address Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 9-3. ADC12B_LBA Register Summary (Sheet 2 of 3)
Chapter 9 Analog-to-Digital Converter MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 299 0x0024 ADCCROFF0 R 0 CMDRES_OFF0[6:0] W 0x0025 ADCCROFF1 R0 CMDRES_OFF1[6:0]W 0x0026 Reserved R0 0 0 0 ReservedW 0x0027 Reserved R ReservedW 0x0028 Reserved R Reserved 00 W 0x0029 Reserved R Reserved 0 Reserved W 0x002A- 0x003F Reserved R0 0 0 0 0 0 0 0 W Address Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 9-3. ADC12B_LBA Register Summary (Sheet 3 of 3)
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9.5.2 Register Descriptions
This section describes in address order all the ADC12B_LBA registers and their individual bits.
9.5.2.1 ADC Control Register 0 (ADCCTL_0)
Read: Anytime Write:
- Bits ADC_EN, ADC_SR, FRZ_MOD and SWAI writable anytime
- Bits MOD_CFG , STR_SEQA and ACC_CFG[1: 0] writable if bit ADC_EN clear or bit SMOD_ACC set Module Base + 0x0000 15 14 13 12 11 10 9 8 R ADC_EN ADC_SR FRZ_MOD SWAI ACC_CFG[1:0] STR_SEQA MOD_CFG W R e s e t 00000000 = Unimplemented or Reserved Figure 9-4. ADC Control Register 0 (ADCCTL_0) Table 9-3. ADCCTL_0 Field Descriptions Field Description ADC_EN ADC Enable Bit — This bit enables the ADC (e.g. sample buffer amplifier etc.) and controls accessibility of ADC register bits. When this bit gets cleared any ongoing conversion sequence will be aborted and pending results or the result of current conversion gets discarded (not stored). The ADC cannot be re-enabled before any pending action or action in process is finished or aborted, which could take up to a maximum latency time of tDISABLE (see device reference manual for more details). Because internal components of the ADC are turned on/off with this bit, the ADC requires a recovery time period REC) after ADC is enabled until the first conversion can be launched via a trigger. 0 ADC disabled. 1 ADC enabled. ADC_SR ADC Soft-Reset — This bit causes an ADC Soft-Reset if set after a severe error occurred (see list of severe errors in Section 9.5.2.9, “ADC Error Interrupt Flag Register (ADCEIF) that causes the ADC to cease operation). It clears all overrun flags and error flags and forces the ADC state machine to its idle state. It also clears the Command Index Register, the Result Index Register, and the CSL_SEL and RVL_SEL bits (to be ready for a new control sequence to load new command and start execution again from top of selected CSL). A severe error occurs if an error flag is set which cause the ADC to cease operation. In order to make the ADC operational again an ADC Soft-Reset must be issued. Once this bit is set it can not be cleared by writing any value. It is cleared only by ADC hardware after the Soft- Reset has been executed. 0 No ADC Soft-Reset issued. 1 Issue ADC Soft-Reset. FRZ_MOD Freeze Mode Configuration — This bit influences conversion flow during Freeze Mode. 0 ADC continues conversion in Freeze Mode. 1 ADC freezes the conversion at next conv ersion boundary at Freeze Mode entry. SWAI Wait Mode Configuration — This bit infl uences conversion flow during Wait Mode. 0 ADC continues conversion in Wait Mode. 1 ADC halts the conversion at next conversion boundary at Wait Mode entry.
Chapter 9 Analog-to-Digital Converter MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 301 NOTE Each conversion flow control bit (SEQA, RSTA, TRIG , LDOK) must be controlled by software or internal interface according to the requirements described in Section 9.6.3.2.4, “The two conversion flow control Mode Configurations and overview summary in Table 9-11. 11-10 ACC_CFG[1 :0] ADCFLWCTL Register Access Configuration — These bits define if the register ADCFLWCTL is controlled via internal interface only or data bus only or both. See Table 9-4. for more details. STR_SEQA Control Of Conversion Result Storage and RSTAR_EIF flag setting at Sequence Abort or Restart Event — This bit controls conversion result storage and RSTAR_EIF flag setting when a Sequence Abort Event or Restart Event occurs as follows: If STR_SEQA = 1’b0 and if a:
- Sequence Abort Event or Restart Event is issued during a conversion the data of this conversion is not stored and the respective conversion complete flag is not set
- Restart Event only is issued before the last conversion of a CSL is finished and no Sequence Abort Event is in process (SEQA clear) causes the RSTA_EIF error flag to be asserted and bit SEQA gets set by hardware If STR_SEQA = 1’b1 and if a:
- Sequence Abort Event or Restart Event is issued during a conversion the data of this conversion is stored and the respective conversion complete flag is set and Intermediate Result Information Register is updated.
- Restart Event only occurs during the last conversion of a CSL and no Sequence Abort Event is in process (SEQA clear) does not set the RSTA_EIF error flag
- Restart Event only is issued before the CSL is finished and no Sequence Abort Event is in process (SEQA clear) causes the RSTA_EIF error flag to be asserted and bit SEQA gets set by hardware MOD_CFG (Conversion Flow Control) Mode Configuration — This bit defines the conversion flow control after a Restart Event and after execution of the “End Of List” command type: - Restart Mode - Trigger Mode (For more details please see also section Section 9.6.3.2, “Introduction of the Programmer’s Model and following.) 0 “Restart Mode” selected. 1 “Trigger Mode” selected. Table 9-4. ADCFLWCTL Register Access Configurations ACC_CFG[1] ACC_CFG[0] A DCFLWCTL Access Mode 0 0 None of the access paths is enabled (default / reset configuration) 0 1 Single Access Mode - Internal Interface (ADCFLWCTL access via internal interface only) 1 0 Single Access Mode - Data Bus (ADCFLWCTL access via data bus only) 1 1 Dual Access Mode (ADCFLWCTL register access via internal interface and data bus) Table 9-3. ADCCTL_0 Field Descriptions (continued) Field Description
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9.5.2.2 ADC Control Register 1 (ADCCTL_1)
Read: Anytime Write:
- Bit CSL_BMOD and RVL_BMOD writable if bit ADC_EN clear or bit SMOD_ACC set
- Bit SMOD_ACC only writable in MCU Special Mode
- Bit AUT_RSTA writable anytime Module Base + 0x0001 76543210 R CSL_BMOD RVL_BMOD SMOD_ACC AUT_RSTA 0000 W R e s e t 00000000 = Unimplemented or Reserved Figure 9-5. ADC Control Register 1 (ADCCTL_1) Table 9-5. ADCCTL_1 Field Descriptions Field Description CSL_BMOD CSL Buffer Mode Select Bit — This bit defines the CSL buffe r mode. This bit is only writable if ADC_EN is clear. 0 CSL single buffer mode. 1 CSL double buffer mode. RVL_BMOD RVL Buffer Mode Select Bit — This bit defines the RVL buffer mode.
0 RVL single buffer mode
1 RVL double buffer mode
SMOD_ACC Special Mode Access Control Bit — This bit controls regi ster access rights in MCU Special Mode. This bit is automatically cleared when leaving MCU Special Mode. Note: When this bit is set also the ADCCMD register is writeable via the data bus to allow modification of the current command for debugging purpose. But this is only possible if the current command is not already processed (conversion not started). Please see access details given for each register. Care must be taken when modifying ADC registers while bit SMOD_ACC is set to not corrupt a possible ongoing conversion. 0 Normal user access - Register write rest rictions exist as specified for each bit. 1 Special access - Register write restrictions are lifted. AUT_RSTA Automatic Restart Event after exit from MCU Stop and Wait Mode (SWAI set) — This bit controls if a Restart Event is automatically generated after exit from MCU Stop Mode or Wait Mode with bit SWAI set. It can be configured for ADC conversion flow control mode “Trigger Mode” and “Restart Mode” (anytime during application runtime). 0 No automatic Restart Event af ter exit from MCU Stop Mode. 1 Automatic Restart Event occurs after exit from MCU Stop Mode.
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9.5.2.3 ADC Status Register (ADCSTS)
It is important to note that if flag DBECC_ERR is set the ADC ceases operation. In order to make the ADC operational again an ADC Soft-Reset must be issued. An ADC Soft-Reset clears bits CSL_SEL and RVL_SEL. Read: Anytime Write:
- Bits CSL_SEL and RVL_SEL anytime if bit AD C_EN is clear or bit SMOD_ACC is set
- Bits DBECC_ERR and READY not writable Module Base + 0x0002 76543210 R CSL_SEL RVL_SEL DBECC_ER R Reserved READY 0 0 0 W R e s e t 00001000 = Unimplemented or Reserved Figure 9-6. ADC Status Register (ADCSTS) Table 9-6. ADCSTS Field Descriptions Field Description CSL_SEL Command Sequence List Select bit — This bit controls and indicates which ADC Command List is active. This bit can only be written if ADC_EN bit is clear. This bit toggles in CSL double buffer mode when no conversion or conversion sequence is ongoing and bit LDOK is set and bit RSTA is set. In CSL single buffer mode this bit is forced to 1’b0 by bit CSL_BMOD. 0 ADC Command List 0 is active. 1 ADC Command List 1 is active. RVL_SEL Result Value List Select Bit — This bit controls and indicates which ADC Result List is active. This bit can only be written if bit ADC_EN is clear. After storage of the initial Result Value List this bit toggles in RVL double buffer mode whenever the conversion result of the first conversion of the current CSL is stored or a CSL got aborted. In RVL single buffer mode this bit is forced to 1’b0 by bit RVL_BMOD. Please see also Section 9.3.1.2, “MCU Operating Modes for information regarding Result List usage in case of Stop or Wait Mode. 0 ADC Result List 0 is active. 1 ADC Result List 1 is active. DBECC_ER R Double Bit ECC Error Flag — This flag indicates that a double bit ECC error occurred during conversion command load or result storage and ADC ceases operation. In order to make the ADC operational again an ADC Soft-Reset must be issued. This bit is cleared if bit ADC_EN is clear. 0 No double bit ECC error occurred. 1 A double bit ECC error occurred. READY Ready For Restart Event Flag — This flag indicates that ADC is in its idle state and ready for a Restart Event. It can be used to verify after exit from Wait Mode if a Restart Event can be issued and processed immediately without any latency time due to an ongoing Sequence Abort Event after exit from MCU Wait Mode (see also the Note in Section 9.3.1.2, “MCU Operating Modes). 0 ADC not in idle state. 1 ADC is in idle state.
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9.5.2.4 ADC Timing Register (ADCTIM)
Read: Anytime Write: These bits are writable if bit ADC_EN is clear or bit SMOD_ACC is set Module Base + 0x0003 76543210 PRS[6:0] W R e s e t 00000101 = Unimplemented or Reserved Figure 9-7. ADC Timing Register (ADCTIM)) Table 9-7. ADCTIM Field Descriptions Field Description 6-0 PRS[6:0] ADC Clock Prescaler — These 7bits are the binary prescaler value PRS. The ADC conversion clock frequency is calculated as follows: Refer to Device Specification for allowed frequency range of fATDCLK. fATD CLK fBUS 2x PRS 1+
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9.5.2.5 ADC Format Register (ADCFMT)
Read: Anytime Write: Bits DJM and SRES[2:0] are writable if bit ADC_EN clear or bit SMOD_ACC set Module Base + 0x0004 76543210 R DJM 0000 SRES[2:0] W R e s e t 00000000 = Unimplemented or Reserved Figure 9-8. ADC Format Register (ADCFMT) Table 9-8. ADCFMT Field Descriptions Field Description DJM Result Register Data Justification — Conversion result data format is always unsigned. This bit controls justification of conversion result data in the conversion result list. 0 Left justified data in the conversion result list. 1 Right justified data in the conversion result list. 2-0 SRES[2:0] ADC Resolution Select — These bits select the resolution of conversion results. See Table 9-9 for coding. Table 9-9. Selectable Conversion Resolution SRES[2] SRES[1] SRES[0] ADC Resolution 0 0 0 8-bit data 0 0 1 Reserved (1) 1. This reserved setting causes a severe error at ADC conversion start whereby the CMD_EIF flag is set and ADC ceases operation 0 1 0 10-bit data 0 1 1 Reserved 10 0 R e s e r v e d (2) 2. This reserved setting does not cause an error; CMD_EIF is not set 1 x x Reserved
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9.5.2.6 ADC Conversion Flow Control Register (ADCFLWCTL)
Bit set and bit clear instructions should not be used to access this register. When the ADC is enabled the bits of ADCFLWCTL register can be modified after a latency time of three Bus Clock cycles. All bits are cleared if bit ADC_EN is clear or via ADC soft-reset. Read: Anytime Write:
- Bits SEQA, TRIG , RSTA, LDOK can only be set if bit ADC_EN is set.
- Writing 1’b0 to any of these bits does not have an effect Timing considerations (Trigger Event - channel sample start) depending on ADC mode configuration:
- Restart Mode When the Restart Event has been processed (initial command of current CSL is loaded) it takes two Bus Clock cycles plus two ADC conversion clock cycles (pump phase) from the Trigger Event (bit TRIG set) until the select channel starts to sample. During a conversion sequence (back to back conversions) it takes five Bus Clock cycles plus two ADC conversion clock cycles (pump phase) from current conversion period end until the newly selected channel is sampled in the following conversion period.
- Trigger Mode When a Restart Event occurs a Trigger Event is issued simultaneously. The time required to process the Restart Event is mainly defined by the internal read data bus availability and therefore can vary. In this mode the Trigger Event is processed immediately after the Restart Event is finished and both conversion flow control bits are cleared simultaneously. From de-assert of bit TRIG until sampling begins five Bus Clock cycles are required. Hence from occurrence of a Restart Event until channel sampling it takes five Bus Clock cycles plus an uncertainty of a few Bus Clock cycles. For more details regarding the sample phase please refer to Section 9.6.2.2, “Sample and Hold Machine with Sample Buffer Amplifier. Module Base + 0x0005 76543210 R SEQA TRIG RSTA LDOK 0000 W R e s e t 00000000 = Unimplemented or Reserved Figure 9-9. ADC Conversion Flow Control Register (ADCFLWCTL)
Chapter 9 Analog-to-Digital Converter MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 307 Table 9-10. ADCFLWCTL Field Descriptions Field Description SEQA Conversion Sequence Abort Event — This bit indicates that a conversion sequence abort event is in progress. When this bit is set the ongoing conversion sequence and current CSL will be aborted at the next conversion boundary. This bit gets cleared when the ongoing conversion sequence is aborted and ADC is idle. This bit can only be set if bit ADC_EN is set. This bit is cleared if bit ADC_EN is clear. Data Bus Control: This bit can be controlled via the data bus if access control is configured accordingly via ACC_CFG[1:0]. Writing a value of 1’b0 does not clear the flag. Writing a one to this bit does not clear it but causes an overrun if the bit has already been set. See Section 9.6.3.2.6, “Conversion flow control in case of conversion sequence control bit overrun scenarios for more details. Internal Interface Control: This bit can be controlled via the internal interface Signal “Seq_Abort” if access control is configured accordingly via ACC_CFG[1:0]. After being set an additional request via the internal interface Signal “Seq_Abort” causes an overrun. See also conversion flow control in case of overrun situations. General: In both conversion flow control modes (Restart Mode and Trigger Mode) when bit RSTA gets set automatically bit SEQA gets set when the ADC has not reached one of the following scenarios: - A Sequence Abort request is about to be executed or has been executed. - “End Of List” command type has been executed or is about to be executed In case bit SEQA is set automatically the Restart error flag RSTA_EIF is set to indicate an unexpected Restart Request. 0 No conversion sequence abort request. 1 Conversion sequence abort request. TRIG Conversion Sequence Trigger Bit — This bit starts a conversion sequence if set and no conversion or conversion sequence is ongoing. This bit is cleared when the first conversion of a sequence starts to sample. This bit can only be set if bit ADC_EN is set. This bit is cleared if bit ADC_EN is clear. Data Bus Control: This bit can be controlled via the data bus if access control is configured accordingly via ACC_CFG[1:0]. Writing a value of 1’b0 does not clear the flag. After being set this bit can not be cleared by writing a value of 1’b1 instead the error flag TRIG_EIF is set. See also Section 9.6.3.2.6, “Conversion flow control in case of conversion sequence control bit overrun scenarios for more details. Internal Interface Control: This bit can be controlled via the internal interface Signal “Trigger” if access control is configured accordingly via ACC_CFG[1:0]. After being set an additional request via internal interface Signal “Trigger“ causes the flag TRIG_EIF to be set. 0 No conversion sequence trigger. 1 Trigger to start conversion sequence.
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Restart Event (Restart from Top of Command Sequence List) — This bit indicates that a Restart Event is executed. The ADC loads the conversion command from top of the active Sequence Command List when no conversion or conversion sequence is ongoing. This bit is cleared when the first conversion command of the sequence from top of active Sequence Command List has been loaded into the ADCCMD register. This bit can only be set if bit ADC_EN is set. This bit is cleared if bit ADC_EN is clear. Data Bus Control: This bit can be controlled via the data bus if access control is configured accordingly via ACC_CFG[1:0]. Writing a value of 1’b0 does not clear the flag. Writing a one to this bit does not clear it but causes an overrun if the bit has already been set. See also Section 9.6.3.2.6, “Conversion flow control in case of conversion sequence control bit overrun scenarios for more details. Internal Interface Control: This bit can be controlled via the internal interface Signal “Restart” if access control is configured accordingly via ACC_CFG[1:0]. After being set an additional request via internal interface Signal “Restart“ causes an overrun. See conversion flow control in case of overrun situations for more details. General: In conversion flow control mode “Trigger Mode” when bit RSTA gets set bit TRIG is set simultaneously if one of the following has been executed: - “End Of List” command type has been executed or is about to be executed - Sequence Abort Event 0 Continue with commands from active Sequence Command List. 1 Restart from top of acti ve Sequence Command List. LDOK Load OK for alternative Command Sequence List — This bit indicates if the preparation of the alternative Sequence Command List is done and Command Sequence List must be swapped with the Restart Event. This bit is cleared when bit RSTA is set (Restart Event executed) and the Command Sequence List got swapped. This bit can only be set if bit ADC_EN is set. This bit is cleared if bit ADC_EN is clear. This bit is forced to zero if bit CSL_BMOD is clear. Data Bus Control: This bit can be controlled via the data bus if access control is configured accordingly via ACC_CFG[1:0]. Writing a value of 1’b0 does not clear the flag. To set bit LDOK the bits LDOK and RSTA must be written simultaneously. control in case of conversion sequence control bit overrun scenarios for more details. Internal Interface Control: This bit can be controlled via the internal interface Signal “LoadOK” and “Restart” if access control is configured accordingly via ACC_CFG[1:0]. With the assertion of Interface Signal “Restart” the interface Signal “LoadOK” is evaluated and bit LDOK set accordingly (bit LDOK set if Interface Signal “LoadOK” asserted when Interface Signal “Restart” asserts). General: Only in “Restart Mode” if a Restart Event occurs without bit LDOK being set the error flag LDOK_EIF is set except when the respective Restart Request occurred after or simultaneously with a Sequence Abort Request. The LDOK_EIF error flag is also not set in “Restart Mode” if the first Restart Event occurs after: - ADC got enabled - Exit from Stop Mode - ADC Soft-Reset 0 Load of alternative list done. 1 Load alternative list. Table 9-10. ADCFLWCTL Field Descriptions (continued) Field Description
Chapter 9 Analog-to-Digital Converter MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 309 For a detailed description of all conversion flow control bit scenarios please see also Section 9.6.3.2.4, “The two conversion flow control Mode Configurations, Section 9.6.3.2.5, “The four ADC conversion flow control bits and Section 9.6.3.2.6, “Conversion flow control in case of conversion sequence control bit overrun scenarios Table 9-11. Summary of Conversion Flow Control Bit Scenarios RSTA TRIG SEQA LDOK Conversion Flow Control Mode Conversion Flow Control Scenario 0 0 0 0 Both Modes Valid 0 0 0 1 Both Modes Can Not Occur 0 0 1 0 Both Modes Valid 0 0 1 1 Both Modes Can Not Occur 0 1 0 0 Both Modes Valid 0 1 0 1 Both Modes Can Not Occur 0 1 1 0 Both Modes Can Not Occur 0 1 1 1 Both Modes Can Not Occur 1 0 0 0 Both Modes Valid 1 0 0 1 Both Modes Valid 1 0 1 0 Both Modes Valid 1 0 1 1 Both Modes Valid 1 1 0 0 “Restart Mode” Error flag TRIG_EIF set “Trigger Mode” Valid 1 1 0 1 “Restart Mode” Error flag TRIG_EIF set “Trigger Mode” Valid 1 1 1 0 “Restart Mode” Error flag TRIG_EIF set “Trigger Mode” Valid 1 1 1 1 “Restart Mode” Error flag TRIG_EIF set “Trigger Mode” Valid (1) (2) (3) (4) (5) (6) 1. Swap CSL buffer 2. Start conversion sequence 3. Prevent RSTA_EIF and LDOK_EIF 4. Load conversion command from top of CSL 5. Abort any ongoing conversion, conversion sequence and CSL 6. Bit TRIG set automatically in Trigger Mode
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9.5.2.7 ADC Error Interrupt Enable Register (ADCEIE)
Read: Anytime Write: Anytime Module Base + 0x0006 76543210 R IA_EIE CMD_EIE EOL_EIE Reserved TRIG_EIE RSTAR_EIE LDOK_EIE W R e s e t 00000000 = Unimplemented or Reserved Figure 9-10. ADC Error Interrupt Enable Register (ADCEIE) Table 9-12. ADCEIE Field Descriptions Field Description IA_EIE Illegal Access Error Interrupt Enable Bit — This bit enables the illegal access error interrupt. 0 Illegal access error interrupt disabled. 1 Illegal access error interrupt enabled. CMD_EIE Command Value Error Interrupt Enable Bit — This bit enables the command value error interrupt. 0 Command value interrupt disabled. 1 Command value interrupt enabled. EOL_EIE ”End Of List” Error Interrupt Enable Bit — This bit enables the “End Of List” error interrupt. 0 “End Of List” error interrupt disabled. 1 “End Of List” error interrupt enabled. TRIG_EIE Conversion Sequence Trigger Error Interrupt Enable Bit — This bit enables the conversion sequence trigger error interrupt. 0 Conversion sequence trigger error interrupt disabled. 1 Conversion sequence trigger error interrupt enabled. RSTAR_EIE Restart Request Error Interrupt Enable Bit— This bit enables the restart request error interrupt. 0 Restart Request error interrupt disabled. 1 Restart Request error interrupt enabled. LDOK_EIE Load OK Error Interrupt Enable Bit — This bit enables the Load OK error interrupt. 0 Load OK error interrupt disabled. 1 Load OK error interrupt enabled.
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9.5.2.8 ADC Interrupt En able Register (ADCIE)
Read: Anytime Write: Anytime Module Base + 0x0007 76543210 R SEQAD_IE CONIF_OIE Reserved 00000 W R e s e t 00000000 = Unimplemented or Reserved Figure 9-11. ADC Interrupt Enable Register (ADCIE) Table 9-13. ADCIE Field Descriptions Field Description SEQAD_IE Conversion Sequence Abort Done Interrupt Enable Bit — This bit enables the conversion sequence abort event done interrupt. 0 Conversion sequence abort event done interrupt disabled. 1 Conversion sequence abort event done interrupt enabled. CONIF_OIE ADCCONIF Register Flags Overrun Interrupt Enable — This bit enables the flag which indicates if an overrun situation occurred for one of the CON_IF[15:1] flags or for the EOL_IF flag. 0 No ADCCONIF Register Flag overrun occurred. 1 ADCCONIF Register Flag overrun occurred.
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9.5.2.9 ADC Error Interrupt Flag Register (ADCEIF)
If one of the following error flags is set the ADC ceases operation:
- I A _ E I F
- C M D _ E I F
- E O L _ E I F
- T R I G _ E I F In order to make the ADC operational again an ADC Soft-Reset must be issued which clears above listed error interrupt flags. The error interrupt flags RSTAR_EIF and LDOK_EIF do not cause the ADC to cease operation. If set the ADC continues operation. Each of the two bits can be cleared by writing a value of 1’b1. Both bits are also cleared if an ADC Soft-Reset is issued. All bits are cleared if bit ADC_EN is clear. Writing any flag with value 1’b0 does not clear a flag. Writing any flag with value 1’b1 does not set the flag. Read: Anytime Write:
- Bits RSTAR_EIF and LDOK_E IF are writable anytime
- Bits IA_EIF, CMD_EIF, EOL_EIF and TRIG_EIF are not writable Module Base + 0x0008 76543210 R IA_EIF CMD_EIF EOL_EIF Reserved TRIG_EIF RSTAR_EIF LDOK_EIF W R e s e t 00000000 = Unimplemented or Reserved Figure 9-12. ADC Error Interrupt Flag Register (ADCEIF) Table 9-14. ADCEIF Field Descriptions Field Description IA_EIF Illegal Access Error Interrupt Flag — This flag indicates that storing the conversion result caused an illegal access error or conversion command loading from outside system RAM or NVM area occurred. The ADC ceases operation if this error flag is set (issue of type severe). 0 No illegal access error occurred. 1 An illegal access error occurred. CMD_EIF Command Value Error Interrupt Flag — This flag indicates that an invalid command is loaded (Any command that contains reserved bit settings) or illegal format setting selected (reserved SRES[2:0] bit settings). The ADC ceases operation if this error flag is set (issue of type severe). 0 Valid conversion command loaded. 1 Invalid conversion command loaded. EOL_EIF “End Of List” Error Interrupt Flag — This flag indicates a missing “End Of List” command type in current executed CSL. The ADC ceases operation if this error flag is set (issue of type severe). 0 No “End Of List” error. 1 “End Of List” command type missing in current executed CSL.
Chapter 9 Analog-to-Digital Converter MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 313 TRIG_EIF Trigger Error Interrupt Flag — This flag indicates that a trigger error occurred. This flag is set in “Restart” Mode when a conversion sequence got aborted and no Restart Event occurred before the Trigger Event or if the Trigger Event occurred before the Restart Event was finished (conversion command has been loaded). This flag is set in “Trigger” Mode when a Trigger Event occurs before the Restart Event is issued to start conversion of the initial Command Sequence List. In “Trigger” Mode only a Restart Event is required to start conversion of the initial Command Sequence List. This flag is set when a Trigger Event occurs before a conversion sequence got finished. This flag is also set if a Trigger occurs while a Trigger Event is just processed - first conversion command of a sequence is beginning to sample (see also Section 9.6.3.2.6, “Conversion flow control in case of conversion sequence control bit overrun scenarios). This flag is also set if the Trigger Event occurs automatically generated by hardware in “Trigger Mode” due to a Restart Event and simultaneously a Trigger Event is generated via data bus or internal interface. The ADC ceases operation if this error flag is set (issue of type severe). 0 No trigger error occurred. 1 A trigger error occurred. RSTAR_EIF Restart Request Error Interrupt Flag — This flag indicates a flow control issue. It is set when a Restart Request occurs after a Trigger Event and before one of the following conditions was reached: - The “End Of List” command type has been executed - Depending on bit STR_SEQA if the “End Of List” command type is about to be executed - The current CSL has been aborted or is about to be aborted due to a Sequence Abort Request. The ADC continues operation if this error flag is set. This flag is not set for Restart Request overrun scenarios (see also Section 9.6.3.2.6, “Conversion flow control in case of conversion sequence control bit overrun scenarios). 0 No Restart request error situation occurred. 1 Restart request error situation occurred. LDOK_EIF Load OK Error Interrupt Flag — This flag can only be set in “Restart Mode”. It indicates that a Restart Request occurred without LDOK. This flag is not set if a Sequence Abort Event is already in process (bit SEQA set) when the Restart Request occurs or a Sequence Abort Request occurs simultaneously with the Restart Request. The LDOK_EIF error flag is also not set in “Restart Mode” if the first Restart Event occurs after: - ADC got enabled - Exit from Stop Mode - ADC Soft-Reset - ADC used in CSL single buffer mode The ADC continues operation if this error flag is set. 0 No Load OK error situation occurred. 1 Load OK error situation occurred. Table 9-14. ADCEIF Field Descriptions (continued) Field Description
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9.5.2.10 ADC Interrupt Flag Register (ADCIF)
After being set any of these bits can be cleared by writing a value of 1’b1 or via ADC soft-reset (bit ADC_SR). All bits are cleared if bit ADC_EN is clear. Writing any flag with value 1’b0 does not clear the flag. Writing any flag with value 1’b1 does not set the flag. Read: Anytime Write: Anytime NOTE In RVL double buffer mode a conversion interrupt flag (CON_IF[15:1]) or End Of List interrupt flag (EOL_IF) overrun is detected if one of these bits is set when it should be set again due to conversion command execution. In RVL single buffer mode a conversion interrupt flag (CON_IF[15:1]) overrun is detected only. The overrun is detected if any of the conversion interrupt flags (CON_IF[15:1]) is set while the first conversion result of a CSL is stored (result of first conversion from top of CSL is stored). Module Base + 0x0009 76543210 R SEQAD_IF CONIF_OIF Reserved 00000 W R e s e t 00000000 = Unimplemented or Reserved Figure 9-13. ADC Interrupt Flag Register (ADCIF) Table 9-15. ADCIF Field Descriptions Field Description SEQAD_IF Conversion Sequence Abort Done Interrupt Flag — This flag is set when the Sequence Abort Event has been executed except the Sequence Abort Event occurred by hardware in order to be able to enter MCU Stop Mode or Wait Mode with bit SWAI set.This flag is also not set if the Sequence Abort request occurs during execution of the last conversion command of a CSL and bit STR_SEQA being set. 0 No conversion sequence abort request occurred. 1 A conversion sequence abort request occurred. CONIF_OIF ADCCONIF Register Flags Overrun Interrupt Flag — This flag indicates if an overrun situation occurred for one of the CON_IF[15:1] flags or for the EOL_IF flag. In RVL single buffer mode (RVL_BMOD clear) an overrun of the EOL_IF flag is not indicated (For more information please see Note below). 0 No ADCCONIF Register Flag overrun occurred. 1 ADCCONIF Register Flag overrun occurred.
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9.5.2.11 ADC Conversion Interr upt Enable Register (ADCCONIE)
Read: Anytime Write: Anytime Module Base + 0x000A 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 R CON_IE[15:1] EOL_I EW R e s e t 0000000000 00000 0 = Unimplemented or Reserved Figure 9-14. ADC Conversion Interrupt Enable Register (ADCCONIE) Table 9-16. ADCCONIE Field Descriptions Field Description 15-1 CON_IE[15:1] Conversion Interrupt Enable Bits — These bits enable the individual interrupts which can be triggered via interrupt flags CON_IF[15:1]. 0 ADC conversion interrupt disabled. 1 ADC conversion interrupt enabled. EOL_IE End Of List Interrupt Enable Bit — This bit enables the end of conversion sequence list interrupt. 0 End of list interrupt disabled. 1 End of list interrupt enabled.
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9.5.2.12 ADC Conversion Interr upt Flag Register (ADCCONIF)
After being set any of these bits can be cleared by writing a value of 1’b1. All bits are cleared if bit ADC_EN is clear or via ADC soft-reset (bit ADC_SR set). Writing any flag with value 1’b0 does not clear the flag. Writing any flag with value 1’b1 does not set the flag. Read: Anytime Write: Anytime NOTE These bits can be used to indicate if a certain packet of conversion results is available. Clearing a flag indicates that conversion results have been retrieved by software and the flag can be used again (see also Section 9.9.6, “RVL swapping in RVL double buffer mode and related registers ADCIMDRI and ADCEOLRI. NOTE Overrun situation of a flag CON_IF[15:1] and EOL_IF are indicated by flag CONIF_OIF. Module Base + 0x000C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CON_IF[15:1] EOL_I FW R e s e t 0000000000 000000 = Unimplemented or Reserved Figure 9-15. ADC Conversion Interrupt Flag Register (ADCCONIF) Table 9-17. ADCCONIF Field Descriptions Field Description 15-1 CON_IF[15:1] Conversion Interrupt Flags — These bits could be set by the binary coded interrupt select bits INTFLG_SEL[3:0] when the corresponding conversion command has been processed and related data has been stored to RAM. See also notes below. EOL_IF End Of List Interrupt Flag — This bit is set by the binary coded conversion command type select bits CMD_SEL[1:0] for “end of list” type of commands and after such a command has been processed and the related data has been stored RAM. See also second note below
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9.5.2.13 ADC Intermediate Result Information Register (ADCIMDRI)
This register is cleared when bit ADC_SR is set or bit ADC_EN is clear. Read: Anytime Write: Never Module Base + 0x000E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CSL_I MD RVL_I MD 0 0 0 00000 R I D X _ I M D [ 5 : 0 ] W R e s e t 0 0 0000000000000 0 = Unimplemented or Reserved Figure 9-16. ADC Intermediate Result Information Register (ADCIMDRI) Table 9-18. ADCIMDRI Field Descriptions Field Description CSL_IMD Active CSL At Intermediate Event — This bit indicates the active (used) CSL at the occurrence of a conversion interrupt flag (CON_IF[15:1]) (occurrence of an intermediate result buffer fill event) or when a Sequence Abort Event gets executed. 0 CSL_0 active (used) when a conversi on interrupt flag (CON_IF[15:1]) got set. 1 CSL_1 active (used) when a conversi on interrupt flag (CON_IF[15:1]) got set. RVL_IMD Active RVL At Intermediate Event — This bit indicates the active (used) RVL buffer at the occurrence of a conversion interrupt flag (CON_IF[15:1]) (occurrence of an intermediate result buffer fill event) or when a Sequence Abort Event gets executed. 0 RVL_0 active (used) when a conversion interrupt flag (CON_IF[15:1]) got set. 1 RVL_1 active (used) when a conversion interrupt flag (CON_IF[15:1]) got set. 5-0 RIDX_IMD[5 :0] RES_IDX Value At Intermediate Event — These bits indicate the result index (RES_IDX) value at the occurrence of a conversion interrupt flag (CON_IF[15:1]) (occurrence of an intermediate result buffer fill event) or occurrence of EOL_IF flag or when a Sequence Abort Event gets executed to abort an ongoing conversion (the result index RES_IDX is captured at the occurrence of a result data store). When a Sequence Abort Event has been processed flag SEQAD_IF is set and the RES_IDX value of the last stored result is provided. Hence in case an ongoing conversion is aborted the RES_IDX value captured in RIDX_IMD bits depends on bit STORE_SEQA: - STORE_SEQA =1: The result index of the aborted conversion is provided - STORE_SEQA =0: The result index of the last stored result at abort execution time is provided In case a CSL is aborted while no conversion is ongoing (ADC waiting for a Trigger Event) the last captured result index is provided. In case a Sequence Abort Event was initiated by hardware due to MCU entering Stop Mode or Wait Mode with bit SWAI set, the result index of the last stored result is captured by bits RIDX_IMD but flag SEQAD_IF is not set.
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The register ADCIMDRI is updated and simultaneously a conversion interrupt flag CON_IF[15:1] occurs when the corresponding conversion command (conversion command with INTFLG_SEL[3:0] set) has been processed and related data has been stored to RAM.
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9.5.2.14 ADC End Of List Result Information Register (ADCEOLRI)
This register is cleared when bit ADC_SR is set or bit ADC_EN is clear. Read: Anytime Write: Never NOTE The conversion interrupt EOL_IF occurs and simultaneously the register ADCEOLRI is updated when the “End Of List” conversion command type has been processed and related data has been stored to RAM. Module Base + 0x0010 76543210 R CSL_EOL RVL_EOL 000000 W R e s e t 00000000 = Unimplemented or Reserved Figure 9-17. ADC End Of List Result Information Register (ADCEOLRI) Table 9-19. ADCEOLRI Field Descriptions Field Description CSL_EOL Active CSL When “End Of List” Command Type Executed — This bit indicates the active (used) CSL when a “End Of List” command type has been executed and related data has been stored to RAM. 0 CSL_0 active when “End Of List” command type executed. 1 CSL_1 active when “End Of List” command type executed. RVL_EOL Active RVL When “End Of List” Command Type Executed — This bit indicates the active (used) RVL when a “End Of List” command type has been executed and related data has been stored to RAM. 0 RVL_0 active when “End Of List” command type executed. 1 RVL_1 active when “End Of List” command type executed.
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9.5.2.15 ADC Command Register 0 (ADCCMD_0)
Read: Anytime Write: Only writable if bit SMOD_ACC is set (see also Section 9.5.2.2, “ADC Control Register 1 (ADCCTL_1) bit SMOD_ACC description for more details) NOTE If bit SMOD_ACC is set modifying this register must be done carefully - only when no conversion and conversion sequence is ongoing. Module Base + 0x0014 31 30 29 28 27 26 25 24 R CMD_SEL INTFLG_SEL[3:0] W R CMD_SEL OPT[1:0] (1) 1. Only available on ADC12B_LBA V2 and V3 (see Table 9-2 for details) INTFLG_SEL[3:0] W R e s e t 00000000 = Unimplemented or Reserved Figure 9-18. ADC Command Register 0 (ADCCMD_0) Table 9-20. ADCCMD_0 Field Descriptions Field Description 31-30 CMD_SEL[1:0] Conversion Command Select Bits — These bits define the type of current conversion described in Table 9-21. ADC12B_LBA V2 and V3 (includes OPT[1:0]) 29-28 OPT[1:0] Option Bits — These two option bits can be used to control a SoC level feature/function. These bits are used together with Option bits OPT[2:3]. Please refer to the device reference manual for details of the feature/functionality controlled by these bits 27-24 INTFLG_SEL[ 3:0] Conversion Interrupt Flag Select Bits — These bits define which interrupt flag is set in the ADCIFH/L register at the end of current conversion.The interrupt flags ADCIF[15:1] are selected via binary coded bits INTFLG_SEL[3:0]. See also Table 9-22 Table 9-21. Conversion Command Type Select CMD_SEL[1] CMD_SEL[0] Conversion Command Type Description 0 0 Normal Conversion 0 1 End Of Sequence (Wait for Trigger to execute next sequence or for a Restart)
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Table 9-22. Conversion Interrupt Flag Select CON_IF[15:1] INTFLG_SEL[3 ] INTFLG_SEL[2] INTFLG_SEL[1] INTFLG_SEL[0] Comment 0x0000 0 0 0 0 No flag set 0x0001 0 0 0 1 Only one flag can be set (one hot coding)0x0002 0 0 1 0 0x0004 0 0 1 1 0x0008 0 1 0 0 0x0010 0 1 0 1 0x0800 1 1 0 0 0x1000 1 1 0 1 0x2000 1 1 1 0 0x4000 1 1 1 1
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9.5.2.16 ADC Command Register 1 (ADCCMD_1)
A command which contains reserved bit settings causes the error flag CMD_EIF being set and ADC cease operation. The CMD_EIF is never set for Internal_x channels, even if the channels are specified as reserved in the Device Overview section of the Reference Manual. Read: Anytime Write: Only writable if bit SMOD_ACC is set (see also Section 9.5.2.2, “ADC Control Register 1 (ADCCTL_1) bit SMOD_ACC description for more details) NOTE If bit SMOD_ACC is set modifying this register must be done carefully - only when no conversion and conversion sequence is ongoing. Module Base + 0x0015 23 22 21 20 19 18 17 16 R VRH_SEL(1) 1. Only available on ADC12B_LBA V1 and V2 (see Table 9-2 for details) VRL_SEL1 CH_SEL[5:0] W R VRH_SEL1:0 2. Only available on ADC12B_LBA V3 (see Table 9-2 for details) CH_SEL[5:0] W R e s e t 00000000 = Unimplemented or Reserved Figure 9-19. ADC Command Register 1 (ADCCMD_1) Table 9-23. ADCCMD_1 Field Descriptions Field Description ADC12B_LBA V1 and V2 (includes VRH_SEL/VRL_SEL) VRH_SEL Reference High Voltage Select Bit — This bit selects the high voltage reference for current conversion. 0 VRH_0 input selected as high voltage reference. 1 VRH_1 input selected as high voltage reference. VRL_SEL Reference Low Voltage Select Bit — This bit selects the low voltage reference for current conversion. 0 VRL_0 input selected as low voltage reference. 1 VRL_1 input selected as low voltage reference. ADC12B_LBA V3 (includes VRH_SEL[1:0]) 23-22 VRH_SEL Reference High Voltage Select Bit — These bits select the high voltage reference for current conversion.
00 VRH_0 input selected as high voltage reference
01 VRH_1 input selected as high voltage reference
10 VRH_2 input selected as high voltage reference
CH_SEL[5:0] ADC Input Channel Select Bits — These bits select the input channel for the current conversion. See Table 9- 24 for channel coding information.
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ANx in Table 9-24 is the maximum number of implemented analog input channels on the device. Please refer to the device overview of the reference manual for details regarding number of analog input channels. Table 9-24. Analog Input Channel Select CH_SEL[5] CH_SEL[4] CH_SEL[3] CH_SEL[2] CH_SEL[1] CH_SEL[0] Analog Input Channel
000000 V R L _ 0 / 1 ( V 1 , V 2 , s e e Table 9-2)
VRL_0 (V3, see Table 9-2)
000001 V R H _ 0 / 1 ( V 1 , V 2 , s e e Table 9-2)
VRH_0/1/2 (V3, see Table 9-2) 0 0 0 0 1 0 (VRH_0/1 + VRL_0/1) / 2 (V1, V2, see Table 9-2) (VRH_0/1/2 + VRL_0) / 2 (V3, see Table 9-2)
000011 R e s e r v e d
000100 R e s e r v e d
000101 R e s e r v e d
000110 R e s e r v e d
000111 R e s e r v e d
001000 I n t e r n a l _ 0
(ADC temperature sense)
001001 I n t e r n a l _ 1
001010 I n t e r n a l _ 2
001011 I n t e r n a l _ 3
001100 I n t e r n a l _ 4
001101 I n t e r n a l _ 5
001110 I n t e r n a l _ 6
001111 I n t e r n a l _ 7
010000 A N 0
010001 A N 1
010010 A N 2
010011 A N 3
010100 A N 4
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9.5.2.17 ADC Command Register 2 (ADCCMD_2)
A command which contains reserved bit settings causes the error flag CMD_EIF being set and ADC cease operation. Read: Anytime Write: Only writable if bit SMOD_ACC is set (see also Section 9.5.2.2, “ADC Control Register 1 (ADCCTL_1) bit SMOD_ACC description for more details) NOTE If bit SMOD_ACC is set modifying this register must be done carefully - only when no conversion and conversion sequence is ongoing. Module Base + 0x0016 15 14 13 12 11 10 9 8 R SMP[4:0] Reserved W R SMP[4:0] OPT[3:2] (1) 1. Only available on ADC12B_LBA V2 and V3 (see Table 9-2 for details) Reserved W R e s e t 00000000 = Unimplemented or Reserved Figure 9-20. ADC Command Register 2 (ADCCMD_2) Table 9-25. ADCCMD_2 Field Descriptions Field Description 15-11 SMP[4:0] Sample Time Select Bits — These four bits select the length of the sample time in units of ADC conversion clock cycles. Note that the ADC conversion clock period is itself a function of the prescaler value (bits PRS[6:0]). Table 9-26 lists the available sample time lengths. ADC12B_LBA V2 and V3 (includes OPT[3:2]) 10-9 OPT[3:2] Option Bits — These two option bits can be used to control a SoC level feature/function. These bits are used together with Option bits OPT[1:0]. Please refer to the device reference manual for details of the feature/functionality controlled by these bits. Table 9-26. Sample Time Select SMP[4] SMP[3] SMP[2] SMP[1] SMP[0] Sample Time in Number of ADC Clock Cycles 00000 4 00001 5 00010 6 00011 7
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10101 R e s e r v e d
10110 R e s e r v e d
10111 R e s e r v e d
Table 9-26. Sample Time Select SMP[4] SMP[3] SMP[2] SMP[1] SMP[0] Sample Time in Number of ADC Clock Cycles
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9.5.2.18 ADC Command Register 3 (ADCCMD_3)
R Reserved Reserved Reserved W R e s e t 00000000 = Unimplemented or Reserved Figure 9-21. ADC Command Register 3 (ADCCMD_3)
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9.5.2.19 ADC Command Ind ex Register (ADCCIDX)
It is important to note that these bits do not represent absolute addresses instead it is a sample index (object size 32bit). Read: Anytime Write: NA Module Base + 0x001C 76543210 R 0 0 CMD_IDX[5:0] W R e s e t 00000000 = Unimplemented or Reserved Figure 9-22. ADC Command Index Register (ADCCIDX) Table 9-27. ADCCIDX Field Descriptions Field Description 5-0 CMD_IDX [5:0] ADC Command Index Bits — These bits represent the command in dex value for the conversion commands relative to the two CSL start addresses in the memory map. These bits do not represent absolute addresses Sequence Lists (CSLs) for more details.
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9.5.2.20 ADC Command Base Pointer Register (ADCCBP)
Read: Anytime Write: Bits CMD_PTR[23:2] writable if bit ADC_EN clear or bit SMOD_ACC set Module Base + 0x001D 23 22 21 20 19 18 17 16 R CMD_PTR[23:16] W R e s e t 00000000 Module Base + 0x001E 15 14 13 12 11 10 9 8 R CMD_PTR[15:8] W R e s e t 00000000 Module Base + 0x001F 76543210 R CMD_PTR[7:2] W R e s e t 00000000 = Unimplemented or Reserved Figure 9-23. ADC Command Base Pointer Registers (ADCCBP_0, ADCCBP_1, ADCCBP_2)) Table 9-28. ADCCBP Field Descriptions Field Description 23-2 CMD_PTR [23:2] ADC Command Base Pointer Address — These bits define the base address of the two CSL areas inside the system RAM or NVM of the memory map. They are used to calculate the final address from which the “Introduction of the two Command Sequence Lists (CSLs).
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9.5.2.21 ADC Result Index Register (ADCRIDX)
It is important to note that these bits do not represent absolute addresses instead it is a sample index (object size 16bit). Read: Anytime Write: NA Module Base + 0x0020 76543210 R 0 0 RES_IDX[5:0] W R e s e t 00000000 = Unimplemented or Reserved Figure 9-24. ADC Result Index Register (ADCRIDX) Table 9-29. ADCRIDX Field Descriptions Field Description 5-0 RES_IDX[5:0] ADC Result Index Bits — These read only bits represent the index value for the conversion results relative to the two RVL start addresses in the memory map. These bits do not represent absolute addresses instead it (RVLs) for more details.
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9.5.2.22 ADC Result Base Pointer Register (ADCRBP)
Read: Anytime Write: Bits RES_PTR[19:2] writeable if bit ADC_EN clear or bit SMOD_ACC set Module Base + 0x0021 23 22 21 20 19 18 17 16 R0 0 0 0 RES_PTR[19:16] W R e s e t 00000000 Module Base + 0x0022 15 14 13 12 11 10 9 8 R RES_PTR[15:8] W R e s e t 00000000 Module Base + 0x0023 76543210 R RES_PTR[7:2] W R e s e t 00000000 = Unimplemented or Reserved Figure 9-25. ADC Result Base Pointer Registers (ADCRBP_0, ADCRBP_1, ADCRBP_2)) Table 9-30. ADCRBP Field Descriptions Field Description 19-2 RES_PTR[19:2] ADC Result Base Pointer Address — These bits define the ba se address of the list areas inside the system RAM of the memory map to which conversion results will be stored to at the end of a conversion. These bits Lists (RVLs).
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9.5.2.23 ADC Command and Result Offset Register 0 (ADCCROFF0)
Read: Anytime Write: NA Module Base + 0x0024 76543210 R 0 CMDRES_OFF0[6:0] W R e s e t 00000000 = Unimplemented or Reserved Figure 9-26. ADC Command and Result Offset Register 0 (ADCCROFF0) Table 9-31. ADCCROFF0 Field Descriptions Field Description 6-0 CMDRES_OF [6:0] ADC Command and Result Offset Value — These read only bits represent the conversion command and result offset value relative to the conversion command base pointer address and result base pointer address in the memory map to refer to CSL_0 and RVL_0. It is used to calculate the address inside the system RAM to which the result at the end of the current conversion is stored to and the area (RAM or NVM) from which the conversion commands are loaded from. This is a zero offset (null offset) which can not be modified. These bits do not represent absolute addresses instead it is a sample offset (object size 16bit for RVL, object size 32bit
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9.5.2.24 ADC Command and Result Offset Register 1 (ADCCROFF1)
It is important to note that these bits do not represent absolute addresses instead it is an sample offset (object size 16bit for RVL, object size 32bit for CSL). Read: Anytime Write: These bits are writable if bit ADC_EN clear or bit SMOD_ACC set Module Base + 0x0025 76543210 CMDRES_OFF1[6:0] W R e s e t 00000000 = Unimplemented or Reserved Figure 9-27. ADC Command and Result Offset Register 1 (ADCCROFF1) Table 9-32. ADCCROFF1 Field Descriptions Field Description 6-0 CMDRES_OF [6:0] ADC Result Address Offset Value — These bits represent the conversion command and result offset value relative to the conversion command base pointer address and result base pointer address in the memory map to refer to CSL_1 and RVL_1. It is used to calculate the address inside the system RAM to which the result at the end of the current conversion is stored to and the area (RAM or NVM) from which the conversion commands are loaded from. These bits do not represent absolute addresses instead it is an sample offset (object size 16bit for RVL, object size 32bit for CSL).,These bits can only be modified if bit ADC_EN is clear. “Introduction of the two Result Value Lists (RVLs) for more details.
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9.6 Functional Description
9.6.1 Overview
The ADC12B_LBA consists of an analog sub-block and a digital sub-block. It is a successive approximation analog-to-digital converter including a sample-and-hold mechanism and an internal charge scaled C-DAC (switched capacitor scaled digital-to-analog converter) with a comparator to realize the successive approximation algorithm.
9.6.2 Analog Sub-Block
The analog sub-block contains all analog circuits (sample and hold, C-DAC, analog Comparator, and so on) required to perform a single conversion. Separate power supplies VDDA and VSSA allow noise from the MCU circuitry to be isolated from the analog sub-block for improved accuracy.
9.6.2.1 Analog Input Multiplexer
The analog input multiplexers connect one of the external or internal analog input channels to the sample and hold storage node.
9.6.2.2 Sample and Hold Machin e with Sample Buffer Amplifier
The Sample and Hold Machine controls the storage and charge of the storage node (sample capacitor) to the voltage level of the analog signal at the selected ADC input channel. This architecture employs the advantage of reduced crosstalk between channels. The sample buffer amplifier is used to raise the effective input impedance of the A/D machine, so that external components (higher bandwidth or higher impedance connected as specified) are less significant to accuracy degradation. During the sample phase, the analog input connects first via a sample buffer amplifier with the storage node always for two ADC clock cycles (“Buffer” sample time). For the remaining sample time (“Final” sample time) the storage node is directly connected to the analog input source. Please see also Figure 9-28 for illustration and the Appendix of the device reference manual for more details. The input analog signals are unipolar and must be within the potential range of VSSA to VDDA. During the hold process, the analog input is disconnected from the storage node.
Chapter 9 Analog-to-Digital Converter MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 335 Figure 9-28. Sampling and Conversion Timing Example (8-bit Resolution, 4 Cycle Sampling) Please note that there is always a pump phase of two ADC_CLK cycles before the sample phase begins, hence glitches during the pump phase could impact the conversion accuracy for short sample times.
9.6.3 Digital Sub-Block
The digital sub-block contains a list-based programmer’s model and the control logic for the analog sub- block circuits.
9.6.3.1 Analog-to-Digital (A/D) Machine
The A/D machine performs the analog-to-digital conversion. The resolution is program selectable to be either 8- or 10- bits. The A/D machine uses a successive approximation architecture. It functions by comparing the sampled and stored analog voltage with a series of binary coded discrete voltages. By following a binary search algorithm, the A/D machine identifies the discrete voltage that is nearest to the sampled and stored voltage. Only analog input signals within the potential range of VRL_0/1 to VRH_0/1/3 (availability of VRL_1 and VRH_2 see Table 9-2) (A/D reference potentials) will result in a non-railed digital output code.
9.6.3.2 Introduction of the Programmer’s Model
The ADC_LBA provides a programmer’s model that uses a system memory list-based architecture for definition of the conversion command sequence and conversion result handling. The Command Sequence List (CSL) and Result Value List (RVL) are implemented in double buffered manner and the buffer mode is user selectable for each list (bits CSL_BMOD, RVL_BMOD). The 32-bit wide conversion command is double buffered and the currently active command is visible in the ADC register map at ADCCMD register space. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 "Buffer" Sample Time (2 cycles) "Final" Sample Time (N - 2 cycles) Total Sample Time (N = SMP[4:0]) SAR Sequence (Resolution Dependent Length: SRES[2:0]) Sample CAP hold phase ADC_CLK
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9.6.3.2.1 Introduction of The Co mmand Sequence List (CSL) Format
A Command Sequence List (CSL) contains up to 64 conversion commands. A user selectable number of successive conversion commands in the CSL can be grouped as a command sequence. This sequence of conversion commands is successively executed by the ADC at the occurrence of a Trigger Event. The commands of a sequence are successively executed until an “End Of Sequence” or “End Of List” command type identifier in a command is detected (command type is coded via bits CMD_SEL[1:0]). The number of successive conversion commands that belong to a command sequence and the number of command sequences inside the CSL can be freely defined by the user and is limited by the 64 conversion commands a CSL can contain. A CSL must contain at least one conversion command and one “end of list” command type identifier. The minimum number of command sequences inside a CSL is zero and the maximum number of command sequences is 63. A command sequence is defined with bits CMD_SEL[1:0] in the register ADCCMD_M by defining the end of a conversion sequence. The Figure 9- 29 and Figure 9-30 provides examples of a CSL. Figure 9-29. Example CSL with sequences and an “End Of List” command type identifier Command_1 Command_2 Command_3 Command_4 Command_5 Command_6 Command_7 Command_8 Command_9 Command_10 Command_11 Command_12 Command_13 CSL_0/1 End Of Sequence normal conversion Command Coding Information normal conversion normal conversion normal conversion normal conversion normal conversion 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 CMD_SEL[1:0]done by bits End Of Sequence normal conversion normal conversion End Of List normal conversion normal conversion Sequence_1 Sequence_2 Sequence_3 Waiting for trigger to proceed Waiting for trigger to proceed Waiting for trigger to proceed Wait for RSTA or LDOK+RSTA
Chapter 9 Analog-to-Digital Converter MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 337 Figure 9-30. Example CSL for continues conversion Command_1 Command_2 Command_3 Command_4 Command_5 Command_6 Command_7 Command_8 Command_9 Command_10 Command_11 Command_12 Command_13 CSL_0 normal conversion normal conversion Command coding information normal conversion normal conversion normal conversion normal conversion normal conversion 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 CMD_SEL[1:0]done by bits normal conversion normal conversion normal conversion End Of List, wrap to top, continue normal conversion normal conversion continuous conversion Initial trigger only
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9.6.3.2.2 Introduction of the tw o Command Sequence Lists (CSLs)
The two Command Sequence Lists (CSLs) can be referred to via the Command Base Pointer Register plus the Command and Result Offset Registers plus the Command Index Register (ADCCBP, ADCCROFF_0/1, ADCCIDX). The final address for conversion command loading is calculated by the sum of these registers (e.g.: ADCCBP+ADCCROFF_0+ADCCIDX or ADCCBP+ADCCROFF_1+ADCCIDX). Bit CSL_BMOD selects if the CSL is used in double buffer or single buffer mode. In double buffer mode, the CSL can be swapped by flow control bits LDOK and RSTA. For detailed information about when and how the CSL is swapped, please refer to Section 9.6.3.2.5, “The four ADC conversion flow control bits - description of Restart Event + CSL Swap, Section 9.9.7.1, “Initial Start of a Command Sequence List and Section 9.9.7.3, “Restart CSL execution with new/other CSL (alternative CSL becomes active CSL) — CSL swapping Which list is actively used for ADC command loading is indicated by bit CSL_SEL. The register to define the CSL start addresses (ADCCBP) can be set to any even location of the system RAM or NVM area. It is the user’s responsibility to make sure that the different ADC lists do not overlap or exceed the system RAM or the NVM area, respectively. The error flag IA_EIF will be set for accesses to ranges outside system RAM area and cause an error interrupt if enabled. Figure 9-31. Command Sequence List Schema in Double Buffer Mode Memory Map 0x00_0000 Register Space RAM or NVM Space RAM or NVM start address RAM or NVM end address CSL_0 (active) ADCCBP+(ADCCROFF_0) CSL_1 (alternative)ADCCBP+(ADCCROFF_1) ADCCBP+(ADCCROFF_0+ ADCCBP+(ADCCROFF_1+ Scenario with: CSL_SEL = 1’b0 Memory Map 0x00_0000 Register Space RAM or NVM Space RAM / NVM start address RAM or NVM end address CSL_1 (active) ADCCBP+(ADCCROFF_0) CSL_0 (alternative) ADCCBP+(ADCCROFF_1) ADCCBP+(ADCCROFF_0+ ADCCMDP+(ADCCROFF_1+ Scenario with: CSL_SEL = 1’b1 ADCCIDX(max)) ADCCIDX(max)) ADCCIDX(max)) ADCCIDX(max)) Note: Address register names in () are not absolute addresses instead they are a sample offset or sample index
Chapter 9 Analog-to-Digital Converter MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 339 Figure 9-32. Command Sequence List Schema in Single Buffer Mode While the ADC is enabled, one CSL is active (indicated by bit CSL_SEL) and the corresponding list should not be modified anymore. At the same time the alternative CSL can be modified to prepare the ADC for new conversion sequences in CSL double buffered mode. When the ADC is enabled, the command address registers (ADCCBP, ADCCROFF_0/2, ADCCIDX) are read only and register ADCCIDX is under control of the ADC. Memory Map 0x00_0000 Register Space RAM or NVM Space RAM or NVM start address RAM or NVM end address CSL_0 (active) ADCCBP+(ADCCROFF_0) ADCCBP+(ADCCROFF_0+ CSL_SEL = 1’b0 (forced by CSL_BMOD) ADCCIDX(max)) Note: Address register names in () are not absolute addresses instead they are a sample offset or sample index
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9.6.3.2.3 Introduction of the tw o Result Value Lists (RVLs)
The same list-based architecture as described above for the CSL has been implemented for the Result Value List (RVL) with corresponding address registers (ADCRBP, ADCCROFF_0/1, ADCRIDX). The final address for conversion result storage is calculated by the sum of these registers (e.g.: ADCRBP+ADCCROFF_0+ADCRIDX or ADCRBP+ADCCROFF_1+ADCRIDX). The RVL_BMOD bit selects if the RVL is used in double buffer or single buffer mode. In double buffer mode the RVL is swapped:
- Each time an “End Of Li st” command type got executed followed by the first conversion from top of the next CSL and related (first) result is about to be stored
- A CSL got aborted (bit SEQA=1’b1) and ADC ente rs idle state (becomes ready for new flow control events) Using the RVL in double buffer mode the RVL is not swapped after exit from Stop Mode or Wait Mode with bit SWAI set. Hence the RVL used before entry of Stop or Wait Mode with bit SWAI set is overwritten after exit from the MCU Operating Mode (see also Section 9.3.1.2, “MCU Operating Modes). Which list is actively used for the ADC conversion result storage is indicated by bit RVL_SEL. The register to define the RVL start addresses (ADCRBP) can be set to any even location of the system RAM area. It is the user’s responsibility to make sure that the different ADC lists do not overlap or exceed the system RAM area. The error flag IA_EIF will be set for accesses to ranges outside system RAM area and cause an error interrupt if enabled. Figure 9-33. Result Value List Schema in Double Buffer Mode Memory Map 0x00_0000 Register Space RAM Space RAM start address RAM end address RVL_0 (active) ADCRBP+(ADCCROFF_0) RVL_1 (alternative)ADCRBP+(ADCCROFF_1) ADCRBP+(ADCCROFF_0+ ADCRBP+(ADCCROFF_1+ Scenario with: RVL_SEL = 1’b0 Memory Map 0x00_0000 Register Space RAM Space RAM start address RAM end address RVL_1 (active) ADCRBP+(ADCCROFF_0) RVL_0 (alternative) ADCRBP+(ADCCROFF_1) ADCRBP+(ADCCROFF_0+ ADCRBP+(ADCCROFF_1+ Scenario with: RVL_SEL = 1’b1 ADCRIDX(max)) ADCRIDX(max)) ADCRIDX(max)) ADCRIDX(max)) Note: Address register names in () are not absolute addresses instead they are a sample offset or sample index
Chapter 9 Analog-to-Digital Converter MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 341 Figure 9-34. Result Value List Schema in Single Buffer Mode While ADC is enabled, one Result Value List is active (indicated by bit RVL_SEL). The conversion Result Value List can be read anytime. When the ADC is enabled the conversion result address registers (ADCRBP, ADCCROFF_0/1, ADCRIDX) are read only and register ADCRIDX is under control of the ADC. A conversion result is always stored as 16bit entity in unsigned data representation. Left and right justification inside the entity is selected via the DJM control bit. Unused bits inside an entity are stored zero. Table 9-33. Conversion Result Justification Overview Conversion Resolution (SRES[1:0]) Left Justified Result (DJM = 1’b0) Right Justified Result (DJM = 1’b1) 8 bit {Result[7:0],8’b00000000} {8’b00000000,Result[7:0]} 10 bit {Result[9:0],6’b000000} {6’b000000,Result[9:0]} Memory Map 0x00_0000 Register Space RAM Space RAM start address RAM end address RVL_0 (active) ADCRBP+(ADCCROFF_0) ADCRBP+(ADCCROFF_0+ RVL_SEL = 1’b0 (forced by bit RVL_BMOD) ADCRIDX(max)) Note: Address register names in () are not absolute addresses instead they are a sample offset or sample index
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9.6.3.2.4 The two conversion flow control Mode Configurations
The ADC provides two modes (“Trigger Mode” and “Restart Mode”) which are different in the conversion control flow. The “Restart Mode” provides precise timing control about the sample start point but is more complex from the flow control perspective, while the “Trigger Mode” is more simple from flow control point of view but is less controllable regarding conversion sample start. Following are the key differences: In “Trigger Mode” configuration, when conversion flow control bit RSTA gets set the bit TRIG gets set automatically. Hence in “Trigger Mode” the applications should not set the bit TRIG and bit RSTA simultaneously (via data bus or internal interface), because it is a flow control failure and the ADC will cease operation. In “Trigger Mode” configuration, after the execution of the initial Restart Event the current CSL can be executed and controlled via Trigger Events only. Hence, if the “End Of List” command is reached a restart of conversion flow from top of current CSL does not require to set bit RSTA because returning to the top of current CSL is done automatically. Therefore the current CSL can be executed again after the “End Of List” command type is executed by a Trigger Event only. In “Restart Mode” configuration, the execution of a CSL is controlled via Trigger Events and Restart Events. After execution of the “End Of List” command the conversion flow must be continued by a Restart Event followed by a Trigger Event and the Trigger Event must not occur before the Restart Event has finished. For more details and examples regarding flow control and application use cases please see following section and Section 9.9.7, “Conversion flow control application information.
9.6.3.2.5 The four ADC c onversion flow control bits
There are four bits to control conversion flow (execution of a CSL and CSL exchange in double buffer mode). Each bit is controllable via the data bus and internal interface depending on the setting of ACC_CFG[1:0] bits (see also Figure 9-2). In the following the conversion control event to control the conversion flow is given with the related internal interface signal and corresponding register bit name together with information regarding: — Function of the conversion control event — How to request the event — When is the event finished — Mandatory requirements to executed the event A summary of all event combinations is provided by Table 9-11.
- Trigger Event Internal Interface Signal: Trigger Corresponding Bit Name: TRIG – Function: Start the first conversion of a conversion sequence which is defined in the active Command Sequence List
Chapter 9 Analog-to-Digital Converter MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 343 – Requested by: - Positive edge of internal interface signal Trigger - Write Access via data bus to set control bit TRIG – When finished: This bit is cleared by the ADC when the first conversion of the sequence is beginning to sample – Mandatory Requirements: - In all ADC conversion flow control modes bit TRIG is only set (Trigger Event executed) if the Trigger Event occurs while no conversion or conversion sequence is ongoing (ADC idle) - In ADC conversion flow control mode “Restart Mode” with a Restart Event in progress it is not allowed that a Trigger Event occurs before the background command load phase has finished (Restart Event has been executed) else the error flag TRIG_EIF is set - In ADC conversion flow control mode “Trigger Mode” a Restart Event causes bit TRIG being set automatically. Bit TRIG is set when no conversion or conversion sequence is ongoing (ADC idle) and the RVL done condition is reached by one of the following: * A “End Of List” command type has been executed * A Sequence Abort Event is in progress or has been executed The ADC executes the Restart Event followed by the Trigger Event. - In ADC conversion flow control mode “Trigger Mode” a Restart Event and a simultaneous Trigger Event via internal interface or data bus causes the TRIG_EIF bit being set and ADC cease operation.
- Restart Event (with current active CSL) Internal Interface Signal: Restart Corresponding Bit Name: RSTA – Function: - Go to top of active CSL (clear index register for CSL) - Load one background command register and wait for Trigger (CSL offset register is not switched independent of bit CSL_BMOD) - Set error flag RSTA_EIF when a Restart Request occurs before one of the following conditions was reached: * The "End Of List" command type has been executed * Depending on bit STR_SEQA if the "End Of List" command type is about to be executed * The current CSL has been aborted or is about to be aborted due to a Sequence Abort Request. – Requested by: - Positive edge of internal interface signal Restart - Write Access via data bus to set control bit RSTA – When finished: This bit is cleared when the first conversion command of the sequence from top of active Sequence Command List is loaded – Mandatory Requirement: - In all ADC conversion flow control modes a Restart Event causes bit RSTA to be set. Bit
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SEQA is set simultaneously by ADC hardware if: * ADC not idle (a conversion or conversion sequence is ongoing and current CSL not finished) and no Sequence Abort Event in progress (bit SEQA not already set or set simultaneously via internal interface or data bus) * ADC idle but RVL done condition not reached The RVL done condition is reached by one of the following: * A “End Of List” command type has been executed * A Sequence Abort Event is in progress or has been executed (bit SEQA already set or set simultaneously via internal interface or data bus) The ADC executes the Sequence Abort Event followed by the Restart Event for the conditions described before or only a Restart Event. - In ADC conversion flow control mode “Trigger Mode” a Restart Event causes bit TRIG being set automatically. Bit TRIG is set when no conversion or conversion sequence is ongoing (ADC idle) and the RVL done condition is reached by one of the following: * A “End Of List” command type has been executed * A Sequence Abort Event is in progress or has been executed The ADC executes the Restart Event followed by the Trigger Event. - In ADC conversion flow control mode “Trigger Mode” a Restart Event and a simultaneous Trigger Event via internal interface or data bus causes the TRIG_EIF bit being set and ADC cease operation.
- Restart Event + CSL Exchange (Swap) Internal Interface Signals: Restart + LoadOK Corresponding Bit Names: RSTA + LDOK – Function: Go to top of active CSL (clear index register for CSL) and switch to other offset register for address calculation if configured for double buffer mode (exchange the CSL list) Requested by: - Internal interface with the assertion of Interface Signal Restart the interface Signal LoadOK is evaluated and bit LDOK is set accordingly (bit LDOK set if Interface Signal LoadOK asserted when Interface Signal Restart asserts). - Write Access via data bus to set control bit RSTA simultaneously with bit LDOK. – When finished: Bit LDOK can only be cleared if it was set as described before and both bits (LDOK, RSTA) are cleared when the first conversion command from top of active Sequence Command List is loaded – Mandatory Requirement: No ongoing conversion or conversion sequence Details if using the internal interface: If signal Restart is asserted before signal LoadOK is set the conversion starts from top of currently active CSL at the next Trigger Event (no exchange of CSL list). If signal Restart is asserted after or simultaneously with signal LoadOK the conversion starts from top of the other CSL at the next Trigger Event (CSL is switched) if CSL is
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- Sequence Abort Event Internal Interface Signal: Seq_Abort Corresponding Bit Name: SEQA – Function: Abort any possible ongoing conversion at next conversion boundary and abort current conversion sequence and active CSL – Requested by: - Positive edge of internal interface signal Seq_Abort - Write Access via data bus to set control bit SEQA – When finished: This bit gets cleared when an ongoing conversion is finished and the result is stored and/or an ongoing conversion sequence is aborted and current active CSL is aborted (ADC idle, RVL done) – Mandatory Requirement: - In all ADC conversion flow control modes bit SEQA can only be set if: * ADC not idle (a conversion or conversion sequence is ongoing) * ADC idle but RVL done condition not reached The RVL done condition is not reached if: * An “End Of List” command type has not been executed * A Sequence Abort Event has not been executed (bit SEQA not already set) - In all ADC conversion flow control modes a Sequence Abort Event can be issued at any time - In ADC conversion flow control mode “Restart Mode” after a conversion sequence abort request has been executed it is mandatory to set bit RSTA. If a Trigger Event occurs before a Restart Event is executed (bit RSTA set and cleared by hardware), bit TRIG is set, error flag TRIG_EIF is set, and the ADC can only be continued by a Soft-Reset. After the Restart Event the ADC accepts new Trigger Events (bit TRIG set) and begins conversion from top of the currently active CSL. - In ADC conversion flow control mode “Restart Mode” after a Sequence Abort Event has been executed, a Restart Event causes only the RSTA bit being set. The ADC executes a Restart Event only. – In both conversion flow control modes (“ Restart Mode” and “Trigger Mode”) when conversion flow control bit RSTA gets set automatically bit SEQA gets set when the ADC has not reached one of the following scenarios: * An “End Of List” command type has been executed or is about to be executed * A Sequence Abort request is about to be executed or has been executed. In case bit SEQA is set automatically the Restart error flag RSTA_EIF is set to indicate an unexpected Restart Request.
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9.6.3.2.6 Conversion flow cont rol in case of conversion sequence control bit overrun
Restart Request Overrun: If a legal Restart Request is detected and no Restart Event is in progress, the RSTA bit is set due to the request. The set RSTA bit indicates that a Restart Request was detected and the Restart Event is in process. In case further Restart Requests occur while the RSTA bit is set, this is defined a overrun situation. This scenario is likely to occur when bit STR_SEQA is set or when a Restart Event causes a Sequence Abort Event. The request overrun is captured in a background register that always stores the last detected overrun request. Hence if the overrun situation occurs more than once while a Restart Event is in progress, only the latest overrun request is pending. When the RSTA bit is cleared, the latest overrun request is processed and RSTA is set again one cycle later. LoadOK Overrun: Simultaneously at any Restart Request overrun situation the LoadOK input is evaluated and the status is captured in a background register which is alternated anytime a Restart Request Overrun occurs while Load OK Request is asserted. The Load OK background register is cleared as soon as the pending Restart Request gets processed. Trigger Overrun: If a Trigger occurs whilst bit TRIG is already set, this is defined as a Trigger overrun situation and causes the ADC to cease conversion at the next conversion boundary and to set bit TRIG_EIF. A overrun is also detected if the Trigger Event occurs automatically generated by hardware in “Trigger Mode” due to a Restart Event and simultaneously a Trigger Event is generated via data bus or internal interface. In this case the ADC ceases operation before conversion begins to sample. In “Trigger Mode” a Restart Request Overrun does not cause a Trigger Overrun (bit TRIG_EIF not set). Sequence Abort Request Overrun: If a Sequence Abort Request occurs whilst bit SEQA is already set, this is defined as a Sequence Abort Request Overrun situation and the overrun request is ignored.
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9.6.3.3 ADC List Usage and Conv ersion/Conversion Sequence Flow
It is the user’s responsibility to make sure that the different lists do not overlap or exceed the system RAM area respectively the CSL does not exceed the NVM area if located in the NVM. The error flag IA_EIF will be set for accesses done outside the system RAM area and will cause an error interrupt if enabled for lists that are located in the system RAM. Generic flow for ADC register load at conversion sequence start/restart:
- It is mandatory that the ADC is idle (no ongoing conversion or conversion sequence).
- It is mandatory to have at least one CSL with valid entries. See also Section 9.9.7.2, “Restart CSL execution with currently active CSL or Section 9.9.7.3, “Restart CSL execution with new/other CSL (alternative CSL becomes active CSL) — CSL swapping for more details on possible scenarios.
- A Restart Event occurs, which causes the index registers to be cleared (register ADCCIDX and ADCRIDX are cleared) and to point to the top of the corresponding lists (top of active RVL and CSL).
- Load conversion command to backgr ound conversion command register 1.
- The control bit(s) RSTA (a nd LDOK if set) are cleared.
- Wait for Trigger Event to start conversion. Generic flow for ADC register load during conversion:
- The index registers AD CCIDX is incremented.
- The inactive background command register is loaded with a new conversion command. Generic flow for ADC result storage at end of conversion:
- Index register ADCRIDX is increm ented and the conversion result is stored in system RAM. As soon as the result is successfully stored, any conversion interrupt flags are set accordingly.
- At the conversion boundary the other background comm and register becomes active and visible in the ADC register map.
- If the last executed conversion command was of type “End Of Sequence”, the ADC waits for the Trigger Event.
- If the last executed conversion command was of t ype “End Of List” and the ADC is configured in “Restart Mode”, the ADC sets all related flags and stays idle awaiting a Restart Event to continue.
- If the last executed conversion command was of t ype “End Of List” and the ADC is configured in “Trigger Mode”, the ADC sets all related flags and automatically returns to top of current CSL and is awaiting a Trigger Event to continue.
- If the last executed conversion command was of type “Normal Conversion” the ADC continues command execution in the order of the current CSL (continues conversion).
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9.7 Resets
At reset the ADC12B_LBA is disabled and in a power down state. The reset state of each individual bit is listed within Section 9.5.2, “Register Descriptions” which details the registers and their bit-fields.
9.8 Interrupts
The ADC supports three types of interrupts:
- Conversion Interrupt
- Sequence Abort Interrupt
- Error and Conversion Flow Control Issue Interrupt Each of the interrupt types is associated with individual interrupt enable bits and interrupt flags.
9.8.1 ADC Conversion Interrupt
The ADC provides one conversion interrupt associated to 16 interrupt enable bits with dedicated interrupt flags. The 16 interrupt flags consist of:
- 15 conversion interrupt flags which can be associated to any conversion completion.
- One additional interrupt flag which is fixed to the “End Of List” conversion command type within the active CSL. The association of the conversion number with the interrupt flag number is done in the conversion command.
9.8.2 ADC Sequence Ab ort Done Interrupt
The ADC provides one sequence abort done interrupt associated with the sequence abort request for conversion flow control. Hence, there is only one dedicated interrupt flag and interrupt enable bit for conversion sequence abort and it occurs when the sequence abort is done.
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9.8.3 ADC Error and Conversion Flow Control Issue Interrupt
The ADC provides one error interrupt for four error classes related to conversion interrupt overflow, command validness, DMA access status and Conversion Flow Control issues, and CSL failure. The following error interrupt flags belong to the group of severe issues which cause an error interrupt if enabled and cease ADC operation:
- I A _ E I F
- C M D _ E I F
- E O L _ E I F
- T R I G _ E I F In order to make the ADC operational again, an ADC Soft-Reset must be issued which clears the above listed error interrupt flags. NOTE It is important to note that if flag DBECC_ERR is set, the ADC ceases operation as well, but does not cause an ADC error interrupt. Instead, a machine exception is issued. In order to make the ADC operational again an ADC Soft-Reset must be issued. Remaining error interrupt flags cause an error interrupt if enabled, but ADC continues operation. The related interrupt flags are:
- R S T A R _ E I F
- LDOK_EIF
- CONIF_OIF
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9.9 Use Cases and Application Information
9.9.1 List Usage — CSL single buffer mode and RVL single buffer mode
In this use case both list types are configured for single buffer mode (CSL_BMOD=1’b0 and RVL_BMOD=1’b0, CSL_SEL and RVL_SEL are forced to 1’b0). The index register for the CSL and RVL are cleared to start from the top of the list with next conversion command and result storage in the following cases:
- The conversion flow reaches th e command containing the “End-of-List” command type identifier
- A Restart Request occurs at a sequence boundary
- After an aborted conversion or conversion sequence Figure 9-35. CSL Single Buffer Mode — RVL Single Buffer Mode Diagram
9.9.2 List Usage — CSL single buffer mode and RVL double buffer mode
In this use case the CSL is configured for single buffer mode (CSL_BMOD=1’b0) and the RVL is configured for double buffer mode (RVL_BMOD=1’b1). In this buffer configuration only the result list RVL is switched when the first conversion result of a CSL is stored after a CSL was successfully finished or a CSL got aborted. Figure 9-36. CSL Single Buffer Mode — RVL Single Buffer Mode Diagram The last entirely filled RVL (an RVL where the corresponding CSL has been executed including the “End Of List “ command type) is shown by register ADCEOLRI. The CSL is used in single buffer mode and bit CSL_SEL is forced to 1’b0. CSL_0 CSL_1 (unused) RVL_0 RVL_1 (unused) CSL_0 CSL_1 (unused) RVL_0 RVL_1
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9.9.3 List Usage — CSL do uble buffer mode and RVL double buffer mode
In this use case both list types are configured for double buffer mode (CSL_BMOD=1’b1 and RVL_BMOD=1’b1) and whenever a Command Sequence List (CSL) is finished or aborted the command Sequence List is swapped by the simultaneous assertion of bits LDOK and RSTA. Figure 9-37. CSL Double Buffer Mode — RVL Double Buffer Mode Diagram This use case can be used if the channel order or CSL length varies very frequently in an application.
9.9.4 List Usage — CSL double buffer mode and RVL single buffer mode
In this use case the CSL is configured for double buffer mode (CSL_BMOD=1’b1) and the RVL is configured for single buffer mode (RVL_BMOD=1’b0). The two command lists can be different sizes and the allocated result list memory area in the RAM must be able to hold as many entries as the larger of the two command lists. Each time when the end of a Command Sequence List is reached, if bits LDOK and RSTA are set, the commands list is swapped. Figure 9-38. CSL Double Buffer Mode — RVL Single Buffer Mode Diagram CSL_0 CSL_1 RVL_0 RVL_1 CSL_0 CSL_1 RVL_0 RVL_1 (unused)
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9.9.5 List Usage — CSL do uble buffer mode and RVL double buffer mode
In this use case both list types are configured for double buffer mode (CSL_BMOD=1’b1) and RVL_BMOD=1’b1). This setup is the same as Section 9.9.3, “List Usage — CSL double buffer mode and RVL double buffer mode but at the end of a CSL the CSL is not always swapped (bit LDOK not always set with bit RSTA). The Result Value List is swapped whenever a CSL is finished or a CSL got aborted. Figure 9-39. CSL Double Buffer Mode — RVL Double Buffer Mode Diagram
9.9.6 RVL swapping in RVL double buffer mode and related registers
When using the RVL in double buffer mode, the registers ADCIMDRI and ADCEOLRI can be used by the application software to identify which RVL holds relevant and latest data and which CSL is related to this data. These registers are updated at the setting of one of the CON_IF[15:1] or the EOL_IF interrupt flags. As described in the register description Section 9.5.2.13, “ADC Intermediate Result Information Register (ADCIMDRI) and Section 9.5.2.14, “ADC End Of List Result Information Register (ADCEOLRI), the register ADCIMDRI, for instance, is always updated at the occurrence of a CON_IF[15:1] interrupt flag amongst other cases. Also each time the last conversion command of a CSL is finished and the corresponding result is stored, the related EOL_IF flag is set and register ADCEOLRI is updated. Hence application software can pick up conversion results, or groups of results, or an entire result list driven fully by interrupts. A use case example diagram is shown in Figure 9-40. CSL_0 CSL_1 RVL_0 RVL_1
Chapter 9 Analog-to-Digital Converter MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 353 Figure 9-40. RVL Swapping — Use Case Diagram RVL Buffer RVL_0 CSL_0 Initial Restart Event EOL CSL_1 EOL CSL_0 Stop Mode request while conversion RVL_1 Stop Mode entry Wake-up Event with AUT_RSTA= 1’b1 RVL_0 CSL_0 t CSL Buffer RVL swap due to EOL no RVL swap RVL values before Stop Mode entry are overwritten RVL_EOL 1’b0 1’b1 CSL_EOL 1’b0 1’b1 bits are valid bits not valid until first EOL EOL_IF 1’b1 set by hardware cleared by software 1’b1 before next EOL should be cleared by software before Stop Mode entry return to execute from top of CSL followed by next CSL to store first result of ongoing and before EOL RVL_IMD 1’b0 1’b1 CSL_IMD 1’b0 1’b1 CON_IF[15:1] 0x0001 INT_1 0x0000 0x0000 Flag should be cleared by software before it is set again bits are valid bits not valid until first INT EOL: INT_x: INT_2 0x0010 ”End Of List” command type processed One of the CON_IF interrupt flags occurs INT_1 0x0001 1’b0 1’b0 RIDX_IMD[5:0] 0x050x00 0x0A 0x08 0x050x0B tdelay Delay can vary depending on the DMA performance, and ADC configuration (conversion flow using the Trigger to proceed through the CSL) tdelay: Comments:
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9.9.7 Conversion flow contro l application information
The ADC12B_LBA provides various conversion control scenarios to the user accomplished by the following features. The ADC conversion flow control can be realized via the data bus only, the internal interface only, or by both access methods. The method used is software configurable via bits ACC_CFG[1:0]. The conversion flow is controlled via the four conversion flow control bits: SEQA, TRIG , RSTA, and LDOK. Two different conversion flow control modes can be configured: Trigger Mode or Restart Mode Single or double buffer configuration of CSL and RVL.
9.9.7.1 Initial Start of a Command Sequence List
At the initial start of a Command Sequence List after device reset all entries for at least one of the two CSL must have been completed and data must be valid. Depending on if the CSL_0 or the CSL_1 should be executed at the initial start of a Command Sequence List the following conversion control sequence must be applied: If CSL_0 should be executed at the initial conversion start after device reset: A Restart Event and a Trigger Event must occur (depending to the selected conversion flow control mode the events must occur one after the other or simultaneously) which causes the ADC to start conversion with commands loaded from CSL_0. If CSL_1 should be executed at the initial conversion start after device reset: Bit LDOK must be set simultaneously with the Restart Event followed by a Trigger Event (depending on the selected conversion flow control mode the Trigger events must occur simultaneously or after the Restart Event is finished). As soon as the Trigger Event gets executed the ADC starts conversion with commands loaded from CSL_1. As soon as a new valid Restart Event occurs the flow for ADC register load at conversion sequence start as described in Section 9.6.3.3, “ADC List Usage and Conversion/Conversion Sequence Flow Description applies.
9.9.7.2 Restart CSL execution with currently active CSL
To restart a Command Sequence List execution it is mandatory that the ADC is idle (no conversion or conversion sequence is ongoing). If necessary, a possible ongoing conversion sequence can be aborted by the Sequence Abort Event (setting bit SEQA). As soon as bit SEQA is cleared by the ADC, the current conversion sequence has been aborted and the ADC is idle (no conversion sequence or conversion ongoing). After a conversion sequence abort is executed it is mandatory to request a Restart Event (bit RSTA set). After the Restart Event is finished (bit RSTA is cleared), the ADC accepts a new Trigger Event (bit TRIG can be set) and begins conversion from the top of the currently active CSL. In conversion flow control
Chapter 9 Analog-to-Digital Converter MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 355 mode “Trigger Mode” only a Restart Event is necessary if ADC is idle to restart Conversion Sequence List execution (the Trigger Event occurs automatically). It is possible to set bit RSTA and SEQA simultaneously, causing a Sequence Abort Event followed by a Restart Event. In this case the error flags behave differently depending on the selected conversion flow control mode:
- Setting both flow control bits simultaneously in conversion flow control mode “Restart Mode” prevents the error flags RSTA_EIF and LDOK_EIF from occurring.
- Setting both flow control bits simultaneously in conversion flow control mode “Trigger Mode” prevents the error flag RSTA_EIF from occurring. If only a Restart Event occurs while ADC is not idle and bit SEQA is not set already (Sequence Abort Event in progress) a Sequence Abort Event is issued automatically and bit RSTAR_EIF is set. Please see also the detailed conversion flow control bit mandatory requirements and execution information
9.9.7.3 Restart CSL execution with new/ other CSL (alternative CSL becomes
active CSL) — CSL swapping After all alternative conversion command list entries are finished the bit LDOK can be set simultaneously with the next Restart Event to swap command buffers. To start conversion command list execution it is mandatory that the ADC is idle (no conversion or conversion sequence is ongoing). If necessary, a possible ongoing conversion sequence can be aborted by the Sequence Abort Event (setting bit SEQA). As soon as bit SEQA is cleared by the ADC, the current conversion sequence has been aborted and the ADC is idle (no conversion sequence or conversion ongoing). After a conversion sequence abort is executed it is mandatory to request a Restart Event (bit RSTA set) and simultaneously set bit LDOK to swap the CSL buffer. After the Restart Event is finished (bit RSTA and LDOK are cleared), the ADC accepts a new Trigger Event (bit TRIG can be set) and begins conversion from the top of the newly selected CSL buffer. In conversion flow control mode “Trigger Mode” only a Restart Event (simultaneously with bit LDOK being set) is necessary to restart conversion command list execution with the newly selected CSL buffer (the Trigger Event occurs automatically). It is possible to set bits RSTA, LDOK and SEQA simultaneously, causing a Sequence Abort Event followed by a Restart Event. In this case the error flags behave differently depending on the selected conversion flow control mode:
- Setting these three flow control bits simultaneously in “Restart Mode” prevents the error flags RSTA_EIF and LDOK_EIF from occurring.
- Setting these three flow control bits simultaneously in “Trigger Mode” prevents the error flag RSTA_EIF from occurring. If only a Restart Event occurs while ADC is not idle and bit SEQA is not set already (Sequence Abort Event in progress) a Sequence Abort Event is issued automatically and bit RSTAR_EIF is set.
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Please see also the detailed conversion flow control bit mandatory requirements and execution information
9.9.8 Continuous Conversion
Applications that only need to continuously convert a list of channels, without the need for timing control or the ability to perform different sequences of conversions (grouped number of different channels to convert) can make use of the following simple setup:
- “Trigger Mode” configuration
- Single buffer CSL
- Depending on data transfer rate either us e single or double buffer RVL configuration
- Define a list of conversion commands which onl y contains the “End Of List” command with automatic wrap to top of CSL After finishing the configuration and enabling the ADC an initial Restart Event is sufficient to launch the continuous conversion until next device reset or low power mode. In case a Low Power Mode is used: If bit AUT_RSTA is set before Low Power Mode is entered the conversion continues automatically as soon as a low power mode (Stop Mode or Wait Mode with bit SWAI set) is exited. Figure 9-41. Conversion Flow Control Diagram — Continuous Conversion (with Stop Mode) CSL_0 Active AN3 AN1 AN4 IN5 Initial Restart Event EOL AN3 AN1 AN4 IN5 EOL AN3 AN1 Stop Mode request, Automatic Sequence Abort Event Idle Stop Mode entry Wake-up Event with Idle AUT_RSTA Active AN3 AN1 AN4 Abort t
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9.9.9 Triggered Conversion — Single CSL
Applications that require the conversion of one or more groups of different channels in a periodic and timed manner can make use of a configuration in “Trigger Mode” with a single CSL containing a list of sequences. This means the CSL consists of several sequences each separated by an “End of Sequence” command. The last command of the CSL uses the “End Of List” command with wrap to top of CSL and waiting for a Trigger (CMD_SEL[1:0] =2’b11). Hence after the initial Restart Event each sequence can be launched via a Trigger Event and repetition of the CSL can be launched via a Trigger after execution of the “End Of List” command. Figure 9-42. Conversion Flow Control Diagram — Triggered Conversion (CSL Repetition) Figure 9-43. Conversion Flow Control Diagram — Triggered Conversion (with Stop Mode) In case a Low Power Mode is used: If bit AUT_RSTA is set before Low Power Mode is entered, the conversion continues automatically as soon as a low power mode (Stop Mode or Wait Mode with bit SWAI set) is exited. CSL_0 Active AN3 AN1 AN4 IN5 Initial Restart Event EOS AN2 AN0 AN4 IN3 EOS AN3 AN1 AN4AN6 AN1 IN1 EOL Trigger Trigger Trigger Sequence_0 Sequence_1 Sequence_0Sequence_2 Repetition of CSL_0 t CSL_0 Active AN3 AN1 AN4 IN5 initial Restart Event EOS AN21AN0 AN4 IN3 EOS AN6 AN1 Stop Mode request, Automatic Sequence Abort Event Idle Stop Mode entry Wake-up Event with Idle AUT_RSTA Active AN3 AN1 AN4 Abort Sequence_0 Sequence_1 Trigger Trigger EOS Sequence_0Sequence_2 AN5 AN2 AN0 Sequence_1 Trigger Begin from top of current CSL t
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9.9.10 Fully Timing Controlled Conversion
As described previously, in “Trigger Mode” a Restart Event automatically causes a trigger. To have full and precise timing control of the beginning of any conversion/sequence the “Restart Mode” is available. In “Restart Mode” a Restart Event does not cause a Trigger automatically; instead, the Trigger must be issued separately and with correct timing, which means the Trigger is not allowed before the Restart Event (conversion command loading) is finished (bit RSTA=1’b0 again). The time required from Trigger until sampling phase starts is given (refer to Section 9.5.2.6, “ADC Conversion Flow Control Register (ADCFLWCTL), Timing considerations) and hence timing is fully controllable by the application. Additionally, if a Trigger occurs before a Restart Event is finished, this causes the TRIG_EIF flag being set. This allows detection of false flow control sequences. Figure 9-44. Conversion Flow Control Diagram — Fully Timing Controlled Conversion (with Stop Mode) Unlike the Stop Mode entry shown in Figure 9-43 and Figure 9-44 it is recommended to issue the Stop Mode at sequence boundaries (when ADC is idle and no conversion/conversion sequence is ongoing). Any of the Conversion flow control application use cases described above (Continuous, Triggered, or Fully Timing Controlled Conversion) can be used with CSL single buffer mode or with CSL double buffer mode. If using CSL double buffer mode, CSL swapping is performed by issuing a Restart Event with bit LDOK set. CSL_0 Active AN3 AN1 AN4 IN5 any Restart Event EOS AN21AN0 AN4 IN3 EOS AN6 AN1 Stop Mode request, Automatic Sequence Abort Event Idle Stop Mode entry Wake-up Event with Idle AUT_RSTA Active AN3 AN1 AN4 Abort Sequence_0 Sequence_1 Trigger Trigger EOS Sequence_0Sequence_2 AN5 AN2 AN0 Sequence_1 Trigger Begin from top of current CSL Trigger conversion command load phase t
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10.1 Introduction
The BATS module provides the functionality to measure the voltage of the chip supply pin VSUP.
10.1.1 Features
The VSUP pin can be routed via an internal divider to the internal Analog to Digital Converter. Independent of the routing to the Analog to Digital Converter, it is possible to route this voltage to a comparator to generate a low or a high voltage interrupt to alert the MCU.
10.1.2 Modes of Operation
The BATS module behaves as follows in the system power modes: 1. Run mode The activation of the VSUP Level Sense Enable (BSUSE=1) or ADC connection Enable (BSUAE=1) closes the path from VSUP pin through the resistor chain to ground and enables the associated features if selected. 2. Stop mode During stop mode operation the path from the VSUP pin through the resistor chain to ground is opened and the low and high voltage sense features are disabled. The content of the configuration register is unchanged. Table 10-1. Revision History Table Rev. No. (Item No.) Data Sections Affected Substantial Change(s) V01.00 15 Dec 2010 all Initial Version V02.00 16 Mar 2011 10.3.2.1 10.4.2.1 - added BVLS[1] to support four voltage level - moved BVHS to register bit 6 V03.00 26 Apr 2011 all - removed Vsense V03.10 04 Oct 2011 10.4.2.1 and 10.4.2.2 - removed BSESE
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10.1.3 Block Diagram
Figure 10-1 shows a block diagram of the BATS module. See device guide for connectivity to ADC channel. Figure 10-1. BATS Block Diagram
10.2 External Signal Description
This section lists the name and description of all external ports.
10.2.1 VSUP — Voltage Supply Pin
This pin is the chip supply. It can be internally connected for voltage measurement. The voltage present at this input is scaled down by an internal voltage divider, and can be routed to the internal ADC or to a comparator. VSUP to ADC ... BVLC BVHC BSUAE BSUSE BVHS BVLS[1:0] Comparator 1automatically closed if BSUSE and/or BSUAE is active, open during Stop mode
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10.3 Memory Map and Register Definition
This section provides the detailed information of all registers for the BATS module.
10.3.1 Register Summary
Figure 10-2 shows the summary of all implemented registers inside the BATS module. NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level.
10.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Unused bits read back zero. Address Offset Register Name B i t 7 654321 B i t 0 0x0000 BATE BVHS BVLS[1:0] BSUAE BSUSE W 0x0001 BATSR R 000000 B V H C B V L C W 0x0002 BATIE R 000000 BVHIE BVLIE W 0x0003 BATIF R 000000 BVHIF BVLIF W 0x0004 - 0x0005 Reserved R 00000000 W 0x0006 - 0x0007 Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W = Unimplemented Figure 10-2. BATS Register Summary
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10.3.2.1 BATS Module Enable Register (BATE)
When opening the resistors path to ground by changing BSUSE or BSUAE then for a time TEN_UNC + two bus cycles the measured value is invalid. This is to let internal nodes be charged to correct value. BVHIE, BVLIE might be cleared for this time period to avoid false interrupts. Module Base + 0x0000 Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 BVHS BVLS[1:0] BSUAE BSUSE W R e s e t 00000000 = Unimplemented Figure 10-3. BATS Module Enable Register (BATE) Table 10-2. BATE Field Description Field Description BVHS BATS Voltage High Select — This bit selects the trigger level for the Voltage Level High Condition (BVHC).
0 Voltage level V HBI1 is selected
1 Voltage level V HBI2 is selected
5:4 BVLS[1:0] BATS Voltage Low Select — This bit selects the trigger level for the Voltage Level Low Condition (BVLC).
00 Voltage level VLBI1 is selected
01 Voltage level VLBI2 is selected
10 Voltage level VLBI3 is selected
11 Voltage level VLBI4 is selected
BATS VSUP ADC Connection Enable — This bit connects the VSUP pin through the resistor chain to ground and connects the ADC channel to the divided down voltage.
0 ADC Channel is disconnected
1 ADC Channel is connected
BATS VSUP Level Sense Enable — This bit connects the VSUP pin through the resistor chain to ground and enables the Voltage Level Sense features measuring BVLC and BVHC.
0 Level Sense features disabled
1 Level Sense features enabled
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10.3.2.2 BATS Module Status Register (BATSR)
Figure 10-5. BATS Voltage Sensing Module Base + 0x0001 Access: User read only (1) 1. Read: Anytime Write: Never 76543210 R 0 0 0 0 0 0 BVHC BVLC W R e s e t 00000000 = Unimplemented Figure 10-4. BATS Module Status Register (BATSR) Table 10-3. BATSR - Register Field Descriptions Field Description BVHC BATS Voltage Sense High Condition Bit — This status bit indicates that a high voltage at VSUP, depending on selection, is present.
0 Vmeasured VHBI_A (rising edge) or Vmeasured VHBI_D (falling edge)
1 Vmeasured VHBI_A (rising edge) or Vmeasured VHBI_D (falling edge)
BATS Voltage Sense Low Condition Bit — This status bi t indicates that a low voltage at VSUP, depending on selection, is present.
0 Vmeasured VLBI_A (falling edge) or Vmeasured VLBI_D (rising edge)
1 Vmeasured VLBI_A (falling edge) or Vmeasured VLBI_D (rising edge)
t V VLBI_A VLBI_D VHBI_A VHBI_D
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10.3.2.3 BATS Interrupt Enable Register (BATIE)
10.3.2.4 BATS Interrupt Flag Register (BATIF)
Module Base + 0x0002 Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R 000000 BVHIE BVLIE W R e s e t 00000000 = Unimplemented Figure 10-6. BATS Interrupt Enable Register (BATIE) Table 10-4. BATIE Register Field Descriptions Field Description BVHIE BATS Interrupt Enable High — Enables High Voltage Interrupt . 0 No interrupt will be requested whenever BVHIF flag is set .
1 Interrupt will be requested whenever BVHIF flag is set
BATS Interrupt Enable Low — Enables Low Voltage Interrupt . 0 No interrupt will be requested whenever BVLIF flag is set . 1 Interrupt will be requested whenever BVLIF flag is set . Module Base + 0x0003 Access: User read/write (1) 1. Read: Anytime Write: Anytime, write 1 to clear 76543210 R 000000 BVHIF BVLIF W R e s e t 00000000 = Unimplemented Figure 10-7. BATS Interrupt Flag Register (BATIF)
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10.3.2.5 Reserved Register
These reserved registers are designed for factory test purposes only and are not intended for general user access. Writing to these registers when in special mode can alter the module’s functionality.
10.4 Functional Description
10.4.1 General
The BATS module allows measuring the voltage on the VSUP pin. The voltage at the VSUP pin can be routed via an internal voltage divider to an internal Analog to Digital Converter Channel. Also the BATS module can be configured to generate a low and high voltage interrupt based on VSUP. The trigger level of the high and low interrupt are selectable.
10.4.2 Interrupts
This section describes the interrupt generated by the BATS module. The interrupt is only available in CPU run mode. Entering and exiting CPU stop mode has no effect on the interrupt flags. To make sure the interrupt generation works properly the bus clock frequency must be higher than the V oltage Warning Low Pass Filter frequency (fVWLP_filter). Table 10-5. BATIF Register Field Descriptions Field Description BVHIF BATS Interrupt Flag High Detect — The flag is set to 1 when BVHC status bit changes. 0 No change of the BVHC status bit since the last clearing of the flag. 1 BVHC status bit has changed since the last clearing of the flag. BVLIF BATS Interrupt Flag Low Detect — The flag is set to 1 when BVLC status bit changes. 0 No change of the BVLC status bit since the last clearing of the flag. 1 BVLC status bit has changed since the last clearing of the flag. Module Base + 0x0006 Module Base + 0x0007 Access: User read/write(1) 1. Read: Anytime Write: Only in special mode 76543210 R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W R e s e t xxxxxxxx Figure 10-8. Reserved Register
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The comparator outputs BVLC and BVHC are forced to zero if the comparator is disabled (configuration bit BSUSE is cleared). If the software disables the comparator during a high or low V oltage condition (BVHC or BVLC active), then an additional interrupt is generated. To avoid this behavior the software must disable the interrupt generation before disabling the comparator. The BATS interrupt vector is named in Table 10-6. Vector addresses and interrupt priorities are defined at MCU level. The module internal interrupt sources are combined into one module interrupt signal.
10.4.2.1 BATS Voltage Low Condition Interrupt (BVLI)
To use the V oltage Low Interrupt the Level Sensing must be enabled (BSUSE =1). If measured when a) V LBI1 selected with BVLS[1:0] = 0x0 Vmeasure VLBI1_A (falling edge) or Vmeasure VLBI1_D (rising edge) or when b) V LBI2 selected with BVLS[1:0] = 0x1 at pin VSUP Vmeasure VLBI2_A (falling edge) or Vmeasure VLBI2_D (rising edge) or when c) V LBI3 selected with BVLS[1:0] = 0x2 Vmeasure VLBI3_A (falling edge) or Vmeasure VLBI3_D (rising edge) or when d) V LBI4 selected with BVLS[1:0] = 0x3 Vmeasure VLBI4_A (falling edge) or Vmeasure VLBI4_D (rising edge) then BVLC is set. BVLC status bit indicates that a low voltage at pin VSUP is present. The Low V oltage Interrupt flag (BVLIF) is set to 1 when the V oltage Low Condition (BVLC) changes state . The Interrupt flag BVLIF can only be cleared by writing a 1. If the interrupt is enabled by bit BVLIE the module requests an interrupt to MCU (BATI).
10.4.2.2 BATS Voltage High Condition Interrupt (BVHI)
To use the V oltage High Interrupt the Level Sensing must be enabled (BSUSE=1). Table 10-6. BATS Interrupt Sources Module Interrupt Source Module Internal Interrupt Source Local Enable BATS Interrupt (BATI) BATS Voltage Low Condition Interrupt (BVLI) BVLIE = 1 BATS Voltage High Condition Interrupt (BVHI) BVHIE = 1
Chapter 10 Supply Voltage Sensor - (BATSV3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 367 If measured when a) V HBI1 selected with BVHS = 0 Vmeasure VHBI1_A (rising edge) or Vmeasure VHBI1_D (falling edge) or when a) V HBI2 selected with BVHS = 1 Vmeasure VHBI2_A (rising edge) or Vmeasure VHBI2_D (falling edge) then BVHC is set. BVHC status bit indicates that a high voltage at pin VSUP is present. The High V oltage Interrupt flag (BVHIF) is set to 1 when a V oltage High Condition (BVHC) changes state. The Interrupt flag BVHIF can only be cleared by writing a 1. If the interrupt is enabled by bit BVHIE the module requests an interrupt to MCU (BATI).
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MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductor 369 Chapter 11 Timer Module (TIM16B4CV3) Block Description
11.1 Introduction
The basic scalable timer consists of a 16-bit, software-programmable counter driven by a flexible programmable prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. This timer could contain up to 4 input capture/output compare channels . The input capture function is used to detect a selected transition edge and record the time. The output compare function is used for generating output signals or for timer software delays. A full access for the counter registers or the input capture/output compare registers should take place in one clock cycle. Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word.
11.1.1 Features
The TIM16B4CV3 includes these distinctive features:
- Up to 4 channels available. (refer to device specification for exact number)
- All channels have same input ca pture/output compare functionality.
- Clock prescaling.
- 16-bit counter.
11.1.2 Modes of Operation
Stop: Timer is off because clocks are stopped. Freeze: Timer counter keeps on running, unl ess TSFRZ in TSCR1 is set to 1. Wait: Counters keeps on running, unless TSWAI in TSCR1 is set to 1. Table 11-1. V03.02 Apri,12,2010 11.3.2.9/11-378 11.4.3/11-385 -update TCRE bit description V03.03 Jan,14,2013 -single source generate different channel guide
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Normal: Timer counter keep on running, unless TEN in TSCR1 is cleared to 0.
11.1.3 Block Diagrams
Figure 11-1. TIM16B4CV3 Block Diagram Figure 11-2. Interrupt Flag Setting Prescaler 16-bit Counter Input capture Output compare IOC0 IOC2 IOC1 IOC3 Timer overflow interrupt Timer channel 0 interrupt Timer channel 2 interrupt Registers Bus clock Input capture Output compare Input capture Output compare Input capture Output compare Channel 0 Channel 1 Channel 2 Channel 3 Timer channel 1 interrupt Timer channel 3 interrupt IOCn Edge detector 16-bit Main Timer TCn Input Capture Reg. Set CnF Interrupt
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11.2 External Signal Description
The TIM16B4CV3 module has a selected number of external pins. Refer to device specification for exact number.
11.2.1 IOC3 - IOC0 — Input Captur e and Output Compare Channel 3-0
Those pins serve as input capture or output compare for TIM16B4CV3 channel . NOTE For the description of interrupts see Section 11.6, “Interrupts”.
11.3 Memory Map and Register Definition
This section provides a detailed description of all memory and registers.
11.3.1 Module Memory Map
The memory map for the TIM16B4CV3 module is given below in Figure 11-3. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the TIM16B4CV3 module and the address offset for each register.
11.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Only bits related to implemented channels are valid. Register Name B i t 76 5 4 3 2 1B i t 0 0x0000 TIOS R RESERV ED RESERV ED RESERV ED RESERV ED IOS3 IOS2 IOS1 IOS0W 0x0001 CFORC R 00000000 W RESERV ED RESERV ED RESERV ED RESERV ED FOC3 FOC2 FOC1 FOC0 0x0004 TCNTH R TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8W 0x0005 TCNTL R TCNT7 TCNT6 TCNT5 TCNT4 T CNT3 TCNT2 TCNT1 TCNT0W 0x0006 TSCR1 R TEN TSWAI TSFRZ TFFCA PRNT 000 W 0x0007 TTOV R RESERV ED RESERV ED RESERV ED RESERV ED TOV3 TOV2 TOV1 TOV0W 0x0008 TCTL1 R RESERV ED RESERV ED RESERV ED RESERV ED RESERV ED RESERV ED RESERV ED RESERV EDW Figure 11-3. TIM16B4CV3 Register Summary (Sheet 1 of 2)
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11.3.2.1 Timer Input Capture/O utput Compare Select (TIOS)
Read: Anytime Write: Anytime 0x0009 TCTL2 R O M 3O L 3O M 2O L 2O M 1O L 1O M 0O L 0W 0x000A TCTL3 R RESERV ED RESERV ED RESERV ED RESERV ED RESERV ED RESERV ED RESERV ED RESERV EDW 0x000B TCTL4 R EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0AW 0x000C TIE R RESERV ED RESERV ED RESERV ED RESERV ED C3I C2I C1I C0IW 0x000D TSCR2 R TOI 000 RESERV ED PR2 PR1 PR0W 0x000E TFLG1 R RESERV ED RESERV ED RESERV ED RESERV ED C3F C2F C1F C0FW 0x000F TFLG2 R TOF 0000000 W 0x0010–0x001F TCxH–TCxL(1) R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8W R B i t 7B i t 6B i t 5B i t 4B i t 3B i t 2B i t 1B i t 0W 0x0024–0x002B Reserved R W 0x002C OCPD R RESERV ED RESERV ED RESERV ED RESERV ED OCPD3 OCPD2 OCPD1 OCPD0W 0x002D Reserved R 0x002E PTPSR R PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0W 0x002F Reserved R W 1. The register is available only if corresponding channel exists. Module Base + 0x0000 76543210 R RESERVED RESERVED RESERVED RESERVED IOS3 IOS2 IOS1 IOS0 W R e s e t 00000000 Figure 11-4. Timer Input Capture/Output Compare Select (TIOS) Register Name B i t 76 5 4 3 2 1B i t 0 Figure 11-3. TIM16B4CV3 Register Summary (Sheet 2 of 2)
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11.3.2.2 Timer Compare Force Register (CFORC)
Read: Anytime but will always return 0x0000 (1 state is transient) Write: Anytime
11.3.2.3 Timer Count Register (TCNT)
Table 11-2. TIOS Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field Description 3:0 IOS[3:0] Input Capture or Output Compare Channel Configuration 0 The corresponding implemented channel acts as an input capture. 1 The corresponding implemented channel acts as an output compare. Module Base + 0x0001 76543210 R 00000000 W RESERVED RESERVED RESERVED RESERVED FOC3 FOC2 FOC1 FOC0 R e s e t 00000000 Figure 11-5. Timer Compare Force Register (CFORC) Table 11-3. CFORC Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field Description 3:0 FOC[3:0] Note: Force Output Compare Action for Channel 3:0 — A write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare “x” to occur immediately. The action taken is the same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not get set. If forced output compare on any channel occurs at the same time as the successful output compare then forced output compare action will take precedence and interrupt flag won’t get set. Module Base + 0x0004 15 14 13 12 11 10 9 9 R TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 W R e s e t 00000000 Figure 11-6. Timer Count Register High (TCNTH)
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The 16-bit main timer is an up counter. A full access for the counter register should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. Read: Anytime Write: Has no meaning or effect in the normal mode; only writable in special modes . The period of the first count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock.
11.3.2.4 Timer System C ontrol Register 1 (TSCR1)
Read: Anytime Write: Anytime Module Base + 0x0005 76543210 R TCNT7 TCNT6 TCNT5 TCNT4 T CNT3 TCNT2 TCNT1 TCNT0 W R e s e t 00000000 Figure 11-7. Timer Count Register Low (TCNTL) Module Base + 0x0006 76543210 R TEN TSWAI TSFRZ TFFCA PRNT 000 W R e s e t 00000000 = Unimplemented or Reserved Figure 11-8. Timer System Control Register 1 (TSCR1) Table 11-4. TSCR1 Field Descriptions Field Description TEN Timer Enable 0 Disables the main timer, including the counter. Can be used for reducing power consumption. 1 Allows the timer to function normally. If for any reason the timer is not active, there is no 64 clock for the pulse accumulator because the 64 is generated by the timer prescaler. TSWAI Timer Module Stops While in Wait 0 Allows the timer module to continue running during wait. 1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU out of wait. TSWAI also affects pulse accumulator.
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11.3.2.5 Timer Toggle On Ov erflow Register 1 (TTOV)
Read: Anytime Write: Anytime TSFRZ Timer Stops While in Freeze Mode 0 Allows the timer counter to continue running while in freeze mode. 1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation. TSFRZ does not stop the pulse accumulator. TFFCA Timer Fast Flag Clear All 0 Allows the timer flag clearing to function normally. 1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010–0x001F) causes the corresponding channel flag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNT register (0x0004, 0x0005) clears the TOF flag. This has the advantage of eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag clearing due to unintended accesses. PRNT Precision Timer 0 Enables legacy timer. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler selection. 1 Enables precision timer. All bits of the PTPSR register are used for Precision Timer Prescaler Selection, and all bits. This bit is writable only once out of reset. Module Base + 0x0007 76543210 R RESERVED RESERVED RESERVED RESERVED TOV3 TOV2 TOV1 TOV0 W R e s e t 00000000 Figure 11-9. Timer Toggle On Overflow Register 1 (TTOV) Table 11-5. TTOV Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field Description 3:0 TOV[3:0] Toggle On Overflow Bits — TOVx toggles output compare pin on over flow. This feature only takes effect when in output compare mode. When set, it takes precedence over forced output compare 0 Toggle output compare pin on overflow feature disabled. 1 Toggle output compare pin on overflow feature enabled. Table 11-4. TSCR1 Field Descriptions (continued) Field Description
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11.3.2.6 Timer Control Register 1/Time r Control Register 2 (TCTL1/TCTL2)
Read: Anytime Write: Anytime Module Base + 0x0008 76543210 R RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED W R e s e t 00000000 Figure 11-10. Timer Control Register 1 (TCTL1) Module Base + 0x0009 76543210 R OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 W R e s e t 00000000 Figure 11-11. Timer Control Register 2 (TCTL2) Table 11-6. TCTL1/TCTL2 Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero Field Description 3:0 OMx Output Mode — These four pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output tied to OCx. Note: For an output line to be driven by an OCx the OCPDx must be cleared. 3:0 OLx Output Level — These fourpairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output tied to OCx. Note: For an output line to be driven by an OCx the OCPDx must be cleared. Table 11-7. Compare Result Output Action OMx OLx Action 0 0 No output compare action on the timer output signal 0 1 Toggle OCx output line 1 0 Clear OCx output line to zero 1 1 Set OCx output line to one
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11.3.2.7 Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)
Read: Anytime Write: Anytime. Module Base + 0x000A 76543210 R RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED W R e s e t 00000000 Figure 11-12. Timer Control Register 3 (TCTL3) Module Base + 0x000B 76543210 R EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A W R e s e t 00000000 Figure 11-13. Timer Control Register 4 (TCTL4) Table 11-8. TCTL3/TCTL4 Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field Description 3:0 EDGnB EDGnA Input Capture Edge Control — These four pairs of control bits configure the input capture edge detector circuits. Table 11-9. Edge Detector Circuit Configuration EDGnB EDGnA Configuration 0 0 Capture disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only 1 1 Capture on any edge (rising or falling)
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11.3.2.8 Timer Interrupt En able Register (TIE)
Read: Anytime Write: Anytime.
11.3.2.9 Timer System C ontrol Register 2 (TSCR2)
Read: Anytime Write: Anytime. Module Base + 0x000C 76543210 R RESERVED RESERVED RESERVED RESERVED C3I C2I C1I C0I W R e s e t 00000000 Figure 11-14. Timer Interrupt Enable Register (TIE) Table 11-10. TIE Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero Field Description 3:0 C3I:C0I Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set, the corresponding flag is enabled to cause a interrupt. Module Base + 0x000D 76543210 R TOI 000 RESERVED PR2 PR1 PR0 W R e s e t 00000000 = Unimplemented or Reserved Figure 11-15. Timer System Control Register 2 (TSCR2) Table 11-11. TSCR2 Field Descriptions Field Description TOI Timer Overflow Interrupt Enable 0 Interrupt inhibited. 1 Hardware interrupt requested when TOF flag set. 2:0 PR[2:0] Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the Bus Clock as shown in Table 11-12.
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11.3.2.10 Main Timer I nterrupt Flag 1 (TFLG1)
Read: Anytime Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero will not affect current status of the bit. Table 11-12. Timer Clock Selection PR2 PR1 PR0 Timer Clock 0 0 0 Bus Clock / 1 0 0 1 Bus Clock / 2 0 1 0 Bus Clock / 4 0 1 1 Bus Clock / 8 1 0 0 Bus Clock / 16 1 0 1 Bus Clock / 32 1 1 0 Bus Clock / 64 1 1 1 Bus Clock / 128 Module Base + 0x000E 76543210 R RESERVED RESERVED RESERVED RESERVED C3F C2F C1F C0F W R e s e t 00000000 Figure 11-16. Main Timer Interrupt Flag 1 (TFLG1) Table 11-13. TRLG1 Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field Description 3:0 C[3:0]F Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output compare event occurs. Clearing requires writing a one to the corresponding flag bit while TEN is set to one. Note: When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel (0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared.
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11.3.2.11 Main Timer I nterrupt Flag 2 (TFLG2)
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit to one while TEN bit of TSCR1 . Read: Anytime Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared). Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set. Module Base + 0x000F 76543210 R TOF 0000000 W R e s e t 00000000 Unimplemented or Reserved Figure 11-17. Main Timer Interrupt Flag 2 (TFLG2) Table 11-14. TRLG2 Field Descriptions Field Description TOF Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 is set to one .
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11.3.2.12 Timer Input Ca pture/Output Compare Registers High and Low 0–
3(TCxH and TCxL) 1 This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to a reserved register have no functional effect. Reads from a reserved register return zeroes. Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a defined transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare. Read: Anytime Write: Anytime for output compare function.Writes to these registers have no meaning or effect during input capture. All timer input capture/output compare registers are reset to 0x0000. NOTE Read/Write access in byte mode for high byte should take place before low byte otherwise it will give a different result. Module Base + 0x0010 = TC0H 0x0012 = TC1H 0x0014=TC2H 0x0016=TC3H 0x0018=RESERVD 0x001A=RESERVD 0x001C=RESERVD 0x001E=RESERVD 15 14 13 12 11 10 9 0 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W R e s e t 00000000 Figure 11-18. Timer Input Capture/Output Compare Register x High (TCxH) Module Base + 0x0011 = TC0L 0x0013 = TC1L 0x0015 =TC2L 0x0017=TC3L 0x0019 =RESERVD 0x001B=RESERVD 0x001D=RESERVD 0x001F=RESERVD 76543210 R B i t 7B i t 6B i t 5B i t 4B i t 3B i t 2B i t 1B i t 0 W R e s e t 00000000 Figure 11-19. Timer Input Capture/Output Compare Register x Low (TCxL)
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11.3.2.13 Output Compare Pin Disconnect Register(OCPD)
Read: Anytime Write: Anytime All bits reset to zero.
11.3.2.14 Precision Timer Prescal er Select Register (PTPSR)
Read: Anytime Write: Anytime All bits reset to zero. Module Base + 0x002C 76543210 R RESERVED RESERVED RESERVED RESERVED OCPD3 OCPD2 OCPD1 OCPD0 W R e s e t 00000000 Figure 11-20. Output Compare Pin Disconnect Register (OCPD) Table 11-15. OCPD Field Description Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field Description 3:0 OCPD[3:0] Output Compare Pin Disconnect Bits 0 Enables the timer channel port. Output Compare action will occur on the channel pin. These bits do not affect the input capture . 1 Disables the timer channel port. Output Compare acti on will not occur on the channel pin, but the output compare flag still become set. Module Base + 0x002E 76543210 R PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 W R e s e t 00000000 Figure 11-21. Precision Timer Prescaler Select Register (PTPSR)
Chapter 11 Timer Module (TIM16B4CV3) Block Description MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 383 ... The Prescaler can be calculated as follows depending on logical value of the PTPS[7:0] and PRNT bit: PRNT = 1 : Prescaler = PTPS[7:0] + 1 Table 11-17. Precision Timer Prescaler Selection Examples when PRNT = 1
11.4 Functional Description
This section provides a complete functional description of the timer TIM16B4CV3 block. Please refer to the detailed timer block diagram in Figure 11-22 as necessary. Table 11-16. PTPSR Field Descriptions Field Description 7:0 PTPS[7:0] Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler. These are effective only when the PRNT bit of TSCR1 is set to 1. Table 11-17 shows some selection examples in this case. The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 Prescale Factor 00000000 1 00000001 2 00000010 3 00000011 4 00010011 2 0 00010100 2 1 00010101 2 2 11111100 2 5 3 11111101 2 5 4 11111110 2 5 5 11111111 2 5 6
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Figure 11-22. Detailed Timer Block Diagram
11.4.1 Prescaler
The prescaler divides the Bus clock by 1, 2, 4, 8, 16, 32, 64 or 128. The prescaler select bits, PR[2:0], select the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2). The prescaler divides the Bus clock by a prescalar value. Prescaler select bits PR[2:0] of in timer system control register 2 (TSCR2) are set to define a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32, 64 and 128 when the PRNT bit in TSCR1 is disabled. PRESCALER CHANNEL 0 IOC0 PIN 16-BIT COUNTER LOGIC PR[2:1:0] TC0 16-BIT COMPARATOR TCNT(hi):TCNT(lo) CHANNEL 1 TC1 16-BIT COMPARATOR INTERRUPT LOGIC TOF TOI C0F C1F EDGE DETECT IOC1 PIN LOGICEDGE DETECT CxF CHANNELn-1 TCn-1 16-BIT COMPARATOR Cn-1F IOCn-1 PIN LOGIC EDGE DETECT OM:OL0 TOV0 OM:OL1 TOV1 OM:OLn-1 TOVn-1 EDG1A EDG1B EDG(n-1)A EDG(n-1)B EDG0B CxI CH. n-1COMPARE CH.n-1 CAPTURE CH. 1 CAPTURE IOC1 PIN IOC0 PIN IOCn-1 PIN TE CH. 1 COMPARE CH. 0COMPARE CH. 0 CAPTURE CHANNEL2 EDG0A IOC0 IOC1 IOCn-1 TOF C0F C1F Cn-1F MUX PRE-PRESCALER PTPSR[7:0] tim source Clock 1
0 PRNT
n is channels number.
Chapter 11 Timer Module (TIM16B4CV3) Block Description MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 385 By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced. In this case, it is possible to set additional prescaler settings for the main timer counter in the present timer by
11.4.2 Input Capture
Clearing the I/O (input/output) select bit, IOSx, configures channel x as an input capture channel. The input capture function captures the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the timer transfers the value in the timer counter into the timer channel registers, TCx. The minimum pulse width for the input capture input is greater than two Bus clocks. An input capture on channel x sets the CxF flag. The CxI bit enables the CxF flag to generate interrupt requests. Timer module must stay enabled (TEN bit of TSCR1 register must be set to one) while clearing CxF (writing one to CxF).
11.4.3 Output Compare
Setting the I/O select bit, IOSx, configures channel x when available as an output compare channel. The output compare function can generate a periodic pulse with a programmable polarity, duration, and frequency. When the timer counter reaches the value in the channel registers of an output compare channel, the timer can set, clear, or toggle the channel pin if the corresponding OCPDx bit is set to zero. An output compare on channel x sets the CxF flag. The CxI bit enables the CxF flag to generate interrupt requests. Timer module must stay enabled (TEN bit of TSCR1 register must be set to one) while clearing CxF (writing one to CxF). The output mode and level bits, OMx and OLx, select set, clear, toggle on output compare. Clearing both OMx and OLx results in no output compare action on the output compare channel pin. Setting a force output compare bit, FOCx, causes an output compare on channel x. A forced output compare does not set the channel flag. Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch. When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin.
11.4.3.1 OC Channel Initialization
The internal register whose output drives OCx can be programmed before the timer drives OCx. The desired state can be programmed to this internal register by writing a one to CFORCx bit with TIOSx, OCPDx and TEN bits set to one. Set OCx: Write a 1 to FOCx while TEN=1, IOSx=1, OMx=1, OLx=1 and OCPDx=1 Clear OCx: Write a 1 to FOCx while TEN=1, IOSx=1, OMx=1, OLx=0 and OCPDx=1
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Setting OCPDx to zero allows the internal register to drive the programmed state to OCx. This allows a glitch free switch over of port from general purpose I/O to timer output once the OCPDx bit is set to zero.
11.5 Resets
The reset state of each individual bit is listed within Section 11.3, “Memory Map and Register Definition” which details the registers and their bit fields
11.6 Interrupts
This section describes interrupts originated by the TIM16B4CV3 block. Table 11-18 lists the interrupts generated by the TIM16B4CV3 to communicate with the MCU. The TIM16B4CV3 could use up to 5 interrupt vectors. The interrupt vector offsets and interrupt numbers are chip dependent.
11.6.1 Channel [3:0] Interrupt (C[3:0]F)
This active high outputs will be asserted by the module to request a timer channel 7 – 0 interrupt. The TIM block only generates the interrupt and does not service it. Only bits related to implemented channels are valid.
11.6.2 Timer Overflow Interrupt (TOF)
This active high output will be asserted by the module to request a timer overflow interrupt. The TIM block only generates the interrupt and does not service it. Table 11-18. TIM16B4CV3 Interrupts Interrupt Offset Vector Prio rity Source Description C[3:0]F — — — Timer Channel 3–0 Active high timer channel interrupts 3–0 TOF — — — Timer Overflow Timer Overflow interrupt
MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductor 387 Chapter 12 Pulse Width Modulator with Fault Protection (PMF15B6CV4) Table 12-1. Revision History Glossary Rev. No. (Item No.) Date (Submitted By) Sections Affected Substantial Change(s) V03.22 02 Sep 2013 12.3.2.4/12-401 12.3.2.11/12-406
- Corrected PINVx bit descriptions
- Improved read description of PMFOUTB V03.23 10 Oct 2013 12.2.8/12-392 12.3.2.18/12-412 12.3.2.22/12-416 12.8.1.1/12-456
- Corrected pmf_reload_is_async signal description
- Enhanced note at PMFCINV register
- Corrected write value limitations for PMFMODx registers
- Corrected register write protection bit names
- Orthographical corrections after review V03.24 08 Nov 2013 12.3.2.8/12-404 Table 12-15 12.4.7/12-440
- Updated PMFFIF bit description
- Updated note to QSMP table
- Updated Asymmetric PWM output description
- Replaced ‘fault clearing’ with ‘fault recovery’ to avoid ambiguity with flags
- Various minor corrections. V03.25 03 Dec 2013 12.3.2.18/12-412 • Updated note at PMFCINV register V04.00 03 Dec 2013 12.3.2.3/12-400 12.3.2.11/12-406 12.3.2.18/12-412
- Added write protection to REV1-0 bits (WP)
- Added PWM read through PMFOUTB (generator output read option)
- Updated note at CINVn bits Table 12-2. Glossary of Terms Term Definition Set Discrete signal is in active logic state. Clear A discrete signal is in inactive logic state. Pin External physical connection. Signal Electronic construct whose state or change in state conveys information. PWM active state Normal output Positive polarity PWM logic level high causing external power device to conduct PWM inactive or disabled state Inverted output Negative polarity PWM logic level low causing external power device not to conduct
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12.1 Introduction
Device reference manuals specify which module version is integrated on the device. Some reference manuals support families of devices, with device dependent module versions. This chapter describes the superset. The feature differences are listed in Table 12-3. Table 12-3. Comparison of PMF15B6C Module Versions The Pulse width Modulator with Fault protection (PMF) module can be configured for one, two, or three complementary pairs. For example:
- One complementary pair and four independent PWM outputs
- Two complementary pairs a nd two independent PWM outputs
- Three complementary pairs and zero independent PWM outputs
- Zero complementary pairs a nd six independent PWM outputs All PWM outputs can be generated from the same counter, or each pair can have its own counter for three independent PWM frequencies. Complementary operation permits programmable deadtime insertion, distortion correction through current sensing by software, and separate top and bottom output polarity PWM clock Clock supplied to PWM and deadtime generators. Based on core clock. Rate depends on prescaler setting. PWM cycle PWM period determined by modulus register and PW M clock rate. Note the differences in edge- or center- aligned mode. triggered double-buffered registers take effect at the next PWM reload event. Commutation cycle For 6-step moto r control only. Started by an event external to the PMF module (async_event). This may be a delayed Hall effect or back-EMF zero crossing event determining the rotor position. Commutation cycle triggered double-buffered registers take effect at the next commutation event and optionally the PWM counters are restarted. Index x Related to time bases. x = A, B or C Index n Related to PWM channels. n = 0, 1, 2, 3, 4, or 5 Index m Related to fault inputs. m = 0, 1, 2, 3, 4, or 5 Feature V3 V4 Write protection (WP) on REV1-0 bits not available available Ability to read the PWM output value through PMFOUTB register not available available Table 12-2. Glossary of Terms Term Definition
Chapter 12 Pulse Width Modulator with Fault Protection (PMF15B6CV4) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 389 control. Each counter value is programmable to support a continuously variable PWM frequency. Both edge- and center-aligned synchronous pulse width-control and full range modulation from 0 percent to 100 percent, are supported. The PMF is capable of controlling most motor types: AC induction motors (ACIM), both brushless (BLDC) and brush DC motors (BDC), switched (SRM) and variable reluctance motors (VRM), and stepper motors.
12.1.1 Features
- Three complementary PWM signal pairs, or six independent PWM signals
- Edge-aligned or center-aligned mode
- Features of compleme ntary channel operation: — Deadtime insertion — Separate top and bottom pulse width correc tion via current status inputs or software — Three variants of PWM output: – Asymmetric in center-aligned mode – Variable edge placement in edge-aligned mode – Double switching in center-aligned mode
- Three 15-bit counters based on core clock
- Separate top and botto m polarity control
- Half-cycle reload capability
- Integral reload rates from 1 to 16
- Programmable fault protection
- Link to timer output comp are for 6-step BLDC commutation support with optional counter restart Reload overrun interrupt
- PWM compare output polarity control Software-controlled PWM outputs, complementary or independent
12.1.2 Modes of Operation
Care must be exercised when using this module in the modes listed in Table 12-4. Some applications require regular software updates for proper operation. Failure to do so could result in destroying the hardware setup. Because of this, PWM outputs are placed in their inactive states in STOP mode, and optionally under WAIT and FREEZE modes. PWM outputs will be reactivated (assuming they were active to begin with) when these modes are exited. Table 12-4. Modes When PWM Operation is Restricted Mode Description STOP PWM outputs are disabled WAIT PWM outputs are disabled as a function of the PMFWAI bit FREEZE PWM outputs are disabled as a function of the PMFFRZ bit
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12.1.3 Block Diagram
Figure 12-1 provides an overview of the PMF module. Figure 12-1. PMF Block Diagram PMFDTM REGISTER REGISTERS PMFMOD PWMRIE PWMEN LDOK EDGE OUTCTL0 OUT0 PRESCALER PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM INTERRUPT CONTROL FAULT CORE REGISTERS PMFVAL0-5 PMFCNT REGISTERS CLOCK GENERATORS MUX, SWAP & CURRENT SENSE OUT2 OUT4 PROTECTION FAULT3 FAULT0 FAULT1 FAULT2 REGISTERS PMFDMAP POLARITY CONTROL FAULT PIN FILTERS FIF0PWMRF RELOAD A INTERRUPT REQUEST FAULT0-5 INTERRUPT REQUEST ISENS FIF0-5 FIE0-5 FMOD0 FMOD1 FMOD2 FMOD3 REGISTER PMFFEN FIF2 FIF1 FIF3 LDFQ OUTCTL2 OUTCTL4 OUTCTL1 OUT1 OUT3 OUT5 OUTCTL3 OUTCTL5 HALF PWMRF INDEP TOPNEG BOTNEG TOP/BOTTOM GENERATION IPOL DT 0—5 IS0 IS1 IS2 MULTIPLE REGISTERS OR BITS FOR TIMEBASE A, B, OR C A,B,C MTG RELOAD B INTERRUPT REQUEST RELOAD C INTERRUPT REQUEST QSMP0 QSMP2 QSMP1 QSMP3 DEADTIME INSERTION PRSC RSTRT Reset Single-underline denotes buffered registers taking effect at PWM reload (pmf_reloada,b,c) Double-underline denotes buffered registers taking effect at commutation event (async_event) PMFROIF PMFROIE RELOAD OVERRUN A or B or C INTERRUPT REQUEST FMOD4 FAULT4 FIF4 QSMP4 FMOD5 FIF5 QSMP5 FAULT5 pmf_reloada,b,c (PWM reload) pmf_reload_is_async (PWM reload qualifier) PINVA,B,C PRSCA,B,C PECA,B,C PMFMODA,B,C PMFVAL0-5 (Global load OK) glb_ldok (Commutation Event) async_event OUTCTL0-5 OUTC0-5 MSK0-5 pmf_reloada,b,c (PWM reload) async_event with restart
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12.2 Signal Descriptions
If the signals are not used exclusively internally, the PMF has external pins named PWM0–5, FAULT0–5, and IS0–IS2. Refer to device overview section.
12.2.1 PWM0–PWM5 Pins
PWM0–PWM5 are the output signals of the six PWM channels. NOTE On MCUs with an integrated gate drive unit the PWM outputs are connected internally to the GDU inputs. In these cases the PWM signals may optionally be available on pins for monitoring purposes. Refer to the device overview section for routing options and pin locations.
12.2.2 FAULT0–FAULT5 Pins
FAULT0–FAULT5 are input signals for disabling selected PWM outputs (FAULT0-3) or drive the outputs to a configurable active/inactive state (FAULT4-5). NOTE On MCUs with an integrated gate drive unit (GDU) either one or more FAULT inputs may be connected internally or/and available on an external pin. Refer to the device overview section for availability and pin locations.
12.2.3 IS0 –IS2 Pins
IS0–IS2 are current status signals for top/bottom pulse width correction in complementary channel operation while deadtime is asserted. NOTE Refer to the device overview section for signal availability on pins.
12.2.4 Global Load OK Signal — glb_ldok
This device-internal PMF input signal is connected to the global load OK bit at integration level. For each of the three PWM generator time bases the use of the global load OK input can be enabled individually (GLDOKA,B,C).
12.2.5 Commutation Event Signal — async_event
This device-internal PMF input signal is connected to the source of the asynchronous event generator (preferably timer output compare channel) at integration level. The commutation event input must be enabled to take effect (ENCE=1). When this bit is set the PMFOUTC, PMFOUT, and MSKx registers switch from non-buffered to async_event triggered double
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buffered mode. In addition, if restart is enabled (RSTRTx=1), the commutation event generates both “PWM reload event” and “PWM reload-is-asynchronous event” simultaneously.
12.2.6 Commutation Event Edge Select Signal —
async_event_edge_sel[1:0] These device-internal PMF input signals select the active edge for the async_event input. Refer to the device overview section to determine if the selection is user configurable or tied constant at integration level. Table 12-5. Commutation Event Edge Selection
12.2.7 PWM Reload Event Signals — pmf_reloada,b,c
These device-internal PMF output signals assert once per control cycle and can serve as triggers for other implemented IP modules. Signal pmf_reloadb and pmf_reloadc are related to time base B and C, respectively, while signal pmf_reloada is off out of reset and can be programmed for time base A, B, or C. Refer to the device overview section to determine the signal connections.
12.2.8 PWM Reload-Is-Asynchronous Signal — pmf_reload_is_async
This device-internal PMF output signal serves as a qualifier to the PMF reload event signal pmf_reloada. Whenever the async_event signal causes pmf_reloada output to assert also the pmf_reload_is_async output asserts for the same duration, except if asynchronous event and generated PWM reload event occur in the same cycle. async_event_edge-sel[1:0] async_event active edge 00 direct input 01 rising edge 10 falling edge 11 both edges
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12.3 Memory Map and Registers
12.3.1 Module Memory Map
A summary of the registers associated with the PMF module is shown in Figure 12-2. Detailed descriptions of the registers and bits are given in the subsections that follow. NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level. Address Offset Register Name B i t 7 654321 B i t 0 0x0000 PMFCFG0 R WP MTG EDGEC EDGEB EDGEA INDEPC INDEPB INDEPA W 0x0001 PMFCFG1 ENCE BOTNEGC TOPNEGC BOTNEGB TOPNEGB BOTNEGA TOPNEGA W 0x0002 PMFCFG2 R REV1 REV0 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 W 0x0003 PMFCFG3 R PMFWAI PMFFRZ VLMODE PINVC PINVB PINVA W 0x0004 PMFFEN FEN5 FEN4 FEN3 FEN2 FEN1 FEN0 W 0x0005 PMFFMOD FMOD5 FMOD4 FMOD3 FMOD2 FMOD1 FMOD0 W 0x0006 PMFFIE FIE5 FIE4 FIE3 FIE2 FIE1 FIE0 W 0x0007 PMFFIF FIF5 FIF4 FIF3 FIF2 FIF1 FIF0 W 0x0008 PMFQSMP0 R0 0 0 0 QSMP5 QSMP4 W 0x0009 PMFQSMP1 R QSMP3 QSMP2 QSMP1 QSMP0 W 0x000A- 0x000B Reserved R 00000000 W = Unimplemented or Reserved Figure 12-2. Quick Reference to PMF Registers (Sheet 1 of 5)
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OUTCTL5 OUTCTL4 OUTCTL3 OUTCTL2 OUTCTL1 OUTCTL0 W 0x000D PMFOUTB R0 0 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 W 0x000E PMFDTMS R 0 0 DT5 DT4 DT3 DT2 DT1 DT0 W 0x000F PMFCCTL R0 0 ISENS IPOLC IPOLB IPOLA W 0x0010 PMFVAL0 R PMFVAL0 W 0x0011 PMFVAL0 R PMFVAL0 W 0x0012 PMFVAL1 R PMFVAL1 W 0x0013 PMFVAL1 R PMFVAL1 W 0x0014 PMFVAL2 R PMFVAL2 W 0x0015 PMFVAL2 R PMFVAL2 W 0x0016 PMFVAL3 R PMFVAL3 W 0x0017 PMFVAL3 R PMFVAL3 W 0x0018 PMFVAL4 R PMFVAL4 W 0x0019 PMFVAL4 R PMFVAL4 W 0x001A PMFVAL5 R PMFVAL5 W Address Offset Register Name B i t 7 654321 B i t 0 = Unimplemented or Reserved Figure 12-2. Quick Reference to PMF Registers (Sheet 2 of 5)
Chapter 12 Pulse Width Modulator with Fault Protection (PMF15B6CV4) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 395 0x001B PMFVAL5 R PMFVAL5 W 0x001C PMFROIE R 00000 PMFROIE C PMFROIE B PMFROIE AW 0x001D PMFROIF R 00000 PMFROIF C PMFROIF B PMFROIF AW 0x001E PMFICCTL R0 0 PECC PECB PECA ICCC ICCB ICCA W 0x001F PMFCINV R0 0 CINV5 CINV4 CINV3 CINV2 CINV1 CINV0 W 0x0020 PMFENCA R PWMENA GLDOKA 000 RSTRTA LDOKA PWMRIEA W 0x0021 PMFFQCA R LDFQA HALFA PRSCA PWMRFA W 0x0022 PMFCNTA R 0 PMFCNTA W 0x0023 PMFCNTA R PMFCNTA W 0x0024 PMFMODA PMFMODA W 0x0025 PMFMODA R PMFMODA W 0x0026 PMFDTMA R0 0 0 0 PMFDTMA W 0x0027 PMFDTMA R PMFDTMA W 0x0028 PMFENCB R PWMENB GLDOKB 000 RSTRTB LDOKB PWMRIEB W 0x0029 PMFFQCB R LDFQB HALFB PRSCB PWMRFB W Address Offset Register Name B i t 7 654321 B i t 0 = Unimplemented or Reserved Figure 12-2. Quick Reference to PMF Registers (Sheet 3 of 5)
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W 0x002B PMFCNTB R PMFCNTB W 0x002C PMFMODB PMFMODB W 0x002D PMFMODB R PMFMODB W 0x002E PMFDTMB R0 0 0 0 PMFDTMB W 0x002F PMFDTMB R PMFDTMB W 0x0030 PMFENCC R PWMENC GLDOKC 000 RSTRTC LDOKC PWMRIEC W 0x0031 PMFFQCC R LDFQC HALFC PRSCC PWMRFC W Address Offset Register Name B i t 7 654321 B i t 0 = Unimplemented or Reserved Figure 12-2. Quick Reference to PMF Registers (Sheet 4 of 5)
Chapter 12 Pulse Width Modulator with Fault Protection (PMF15B6CV4) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 397 0x0032 PMFCNTC R 0 PMFCNTC W 0x0033 PMFCNTC RP M F C N T C W 0x0034 PMFMODC PMFMODC W 0x0035 PMFMODC R PMFMODC W 0x0036 PMFDTMC R0 0 0 0 PMFDTMC W 0x0037 PMFDTMC R PMFDTMC W 0x0038 PMFDMP0 R DMP05 DMP04 DMP03 DMP02 DMP01 DMP00 W 0x0039 PMFDMP1 R DMP15 DMP14 DMP13 DMP12 DMP11 DMP10 W 0x003A PMFDMP2 R DMP25 DMP24 DMP23 DMP22 DMP21 DMP20 W 0x003B PMFDMP3 R DMP35 DMP34 DMP33 DMP32 DMP31 DMP30 W 0x003C PMFDMP4 R DMP45 DMP44 DMP43 DMP42 DMP41 DMP40 W 0x003D PMFDMP5 R DMP55 DMP54 DMP53 DMP52 DMP51 DMP50 W 0x003E PMFOUTF R0 0 OUTF5 OUTF4 OUTF3 OUTF2 OUTF1 OUTF0 W 0x003F Reserved R 00000000 W Address Offset Register Name B i t 7 654321 B i t 0 = Unimplemented or Reserved Figure 12-2. Quick Reference to PMF Registers (Sheet 5 of 5)
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12.3.2 Register Descriptions
12.3.2.1 PMF Configure 0 Register (PMFCFG0)
Address: Module Base + 0x0000 Access: User read/write (1) 1. Read: Anytime Write: This register cannot be modified after the WP bit is set 76543210 R WP MTG EDGEC EDGEB EDGEA INDEPC INDEPB INDEPA W R e s e t 00000000 Figure 12-3. PMF Configure 0 Register (PMFCFG0) Table 12-6. PMFCFG0 Field Descriptions Field Description WP Write Protect— This bit enables write protection to be used for all write-protectable registers. While clear, WP allows write-protected registers to be written. When set, WP prevents any further writes to write-protected registers. Once set, WP can be cleared only by reset.
0 Write-protectable registers may be written
1 Write-protectable registers are write-protected
Multiple Timebase Generators — This bit determines the number of timebase counters used. This bit cannot be modified after the WP bit is set. If MTG is set, PWM generators B and C and registers 0x0028 – 0x0037 are availabled.The three generators have their own variable frequencies and are not synchronized. If MTG is cleared, PMF registers from 0x0028 – 0x0037 can not be written and read zeroes, and bits EDGEC and EDGEB are ignored. Pair A, Pair B, and Pair C PWMs are synchronized to PWM generator A and use registers from 0x0020 – 0x0027.
0 Single timebase generator
1 Multiple timebase generators
Edge-Aligned or Center-Aligned PWM for Pair C — This bit determines whether PWM4 and PWM5 channels will use edge-aligned or center-aligned waveforms. This bit has no effect if MTG bit is cleared. This bit cannot be modified after the WP bit is set.
0 PWM4 and PWM5 are center-aligned PWMs
1 PWM4 and PWM5 are edge-aligned PWMs
Edge-Aligned or Center-Aligned PWM for Pair B — This bit determines whether PWM2 and PWM3 channels will use edge-aligned or center-aligned waveforms. This bit has no effect if MTG bit is cleared. This bit cannot be modified after the WP bit is set.
0 PWM2 and PWM3 are center-aligned PWMs
1 PWM2 and PWM3 are edge-aligned PWMs
Edge-Aligned or Center-Aligned PWM for Pair A— This bit determines whether PWM0 and PWM1 channels will use edge-aligned or center-aligned waveforms. It determines waveforms for Pair B and Pair C if the MTG bit is cleared. This bit cannot be modified after the WP bit is set.
0 PWM0 and PWM1 are center-aligned PWMs
1 PWM0 and PWM1 are edge-aligned PWMs
Independent or Complementary Operation for Pair C— This bit determines if the PWM channels 4 and 5 will be independent PWMs or complementary PWMs. This bit cannot be modified after the WP bit is set.
0 PWM4 and PWM5 are complementary PWM pair
1 PWM4 and PWM5 are independent PWMs
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12.3.2.2 PMF Configure 1 Register (PMFCFG1)
A normal PWM output or positive polarity means that the PWM channel outputs high when the counter value is smaller than or equal to the pulse width value and outputs low otherwise. An inverted output or negative polarity means that the PWM channel outputs low when the counter value is smaller than or equal to the pulse width value and outputs high otherwise. NOTE The TOPNEGx and BOTNEGx are intended for adapting to the polarity of external predrivers on devices driving the PWM output directly to pins. If an integrated GDU is driven it must be made sure to keep the reset values of these bits in order not to violate the deadtime insertion. INDEPB Independent or Complementary Operation for Pair B— This bit determines if the PWM channels 2 and 3 will be independent PWMs or complementary PWMs. This bit cannot be modified after the WP bit is set.
0 PWM2 and PWM3 are complementary PWM pair
1 PWM2 and PWM3 are independent PWMs
Independent or Complementary Operation for Pair A— This bit determines if the PWM channels 0 and 1 will be independent PWMs or complementary PWMs. This bit cannot be modified after the WP bit is set.
0 PWM0 and PWM1 are complementary PWM pair
1 PWM0 and PWM1 are independent PWMs
Address: Module Base + 0x0001 Access: User read/write (1) 1. Read: Anytime Write: This register cannot be modified after the WP bit is set 76543210 ENCE BOTNEGC TOPNEGC BOTNEGB TOPNEGB BOTNEGA TOPNEGA W R e s e t 00000000 Figure 12-4. PMF Configure 1 Register (PMFCFG1) Table 12-7. PMFCFG1 Field Descriptions Field Description ENCE Enable Commutation Event — This bit enables the commutation event input and activates buffering of registers PMFOUTC and PMFOUTB and MSKx bits.This bit cannot be modified after the WP bit is set.If set to zero the commutation event input is ignored and writes to the above registers and bits will take effect immediately. If set to one, the commutation event input is enabled and the value written to the above registers and bits does not take effect until the next commutation event occurs.
0 Commutation event input disabled and PMFOUTC, PMFOUTB and MSKn not buffered
1 Commutation event input enabled and PMFOUTC, PMFOUTB and MSKn buffered
Pair C Bottom-Side PWM Polarity — This bit determines the polarity for Pair C bottom-side PWM (PWM5). This bit cannot be modified after the WP bit is set.
0 Positive PWM5 polarity
1 Negative PWM5 polarity
Table 12-6. PMFCFG0 Field Descriptions (continued) Field Description
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12.3.2.3 PMF Configure 2 Register (PMFCFG2)
Pair C Top-Side PWM Polarity — This bit determines the polarity for Pair C top-side PWM (PWM4). This bit cannot be modified after the WP bit is set.
0 Positive PWM4 polarity
1 Negative PWM4 polarity
Pair B Bottom-Side PWM Polarity — This bit determines the polarity for Pair B bottom-side PWM (PWM3). This bit cannot be modified after the WP bit is set.
0 Positive PWM3 polarity
1 Negative PWM3 polarity
Pair B Top-Side PWM Polarity — This bit determines the polarity for Pair B top-side PWM (PWM2). This bit cannot be modified after the WP bit is set.
0 Positive PWM2 polarity
1 Negative PWM2 polarity
Pair A Bottom-Side PWM Polarity — This bit determines the polarity for Pair A bottom-side PWM (PWM1). This bit cannot be modified after the WP bit is set.
0 Positive PWM1 polarity
1 Negative PWM1 polarity
Pair A Top-Side PWM Polarity — This bit determines the polarity for Pair A top-side PWM (PWM0). This bit cannot be modified after the WP bit is set.
0 Positive PWM0 polarity
1 Negative PWM0 polarity
Address: Module Base + 0x0002 Access: User read/write (1) 1. Read: Anytime Write: Anytime except REV[1:0] which cannot be modified after the WP bit is set1. 76543210 R REV1 REV0 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 W R e s e t 00000000 Figure 12-5. PMF Configure 2 Register (PMFCFG2) Table 12-8. PMFCFG2 Field Descriptions Field Description 7-6 REV[1:0] Select timebase counter to output reload event on pmf_reloada These bits select if timebase generator A, B or C provides the reload event on output signal pmf_reloada. This register cannot be modified after the WP bit is set.(1)
00 Reload event generation disabled
01 PWM generator A generates reload event
10 PWM generator B generates reload event
11 PWM generator C generates reload event
Table 12-7. PMFCFG1 Field Descriptions (continued) Field Description
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12.3.2.4 PMF Configure 3 Register (PMFCFG3)
5–0 MSK[5:0] Mask PWMn — Note: MSKn are buffered if ENCE is set. The value written does not take effect until the next commutation cycle begins. Reading MSKn returns the value in the buffer and not necessarily the value the output control is currently using. 0P W Mn is unmasked 1P W Mn is masked and the channel is set to a value of 0 percent duty cycle n is 0, 1, 2, 3, 4, and 5. 1. only valid for module version V4 Address: Module Base + 0x0003 Access: User read/write (1) 1. Read: Anytime Write: This register cannot be modified after the WP bit is set, except for bits PINVA, PINVB and PINVC 76543210 R PMFWAI PMFFRZ VLMODE PINVC PINVB PINVA W R e s e t 00000000 Figure 12-6. PMF Configure 3 Register (PMFCFG3) Table 12-9. PMFCFG3 Field Descriptions Field Description PMFWAI PMF Stops While in WAIT Mode — When set to zero, the PWM generators will continue to run while the chip is in WAIT mode. In this mode, the peripheral clock continues to run but the CPU clock does not. If the device enters WAIT mode and this bit is one, then the PWM outputs will be switched to their inactive state until WAIT mode is exited. At that point the PWM outputs will resume operation as programmed in the PWM registers. This bit cannot be modified after the WP bit is set.
0 PMF continues to run in WAIT mode
1 PMF is disabled in WAIT mode
PMF Stops While in FREEZE Mode — When set to zero, the PWM generat ors will continue to run while the chip is in FREEZE mode. If the device enters FREEZE mode and this bit is one, then the PWM outputs will be switched to their inactive state until FREEZE mode is exited. At that point the PWM outputs will resume operation as programmed in the PWM registers. This bit cannot be modified after the WP bit is set.
0 PMF continues to run in FREEZE mode
1 PMF is disabled in FREEZE mode
Table 12-8. PMFCFG2 Field Descriptions (continued) Field Description
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12.3.2.5 PMF Fault Enab le Register (PMFFEN)
4–3 VLMODE [1:0] Value Register Load Mode — This field determines the way the value registers are being loaded. This register cannot be modified after the WP bit is set.
00 Each value register is accessed independently
01 Writing to value register zero also writes to value registers one to five
10 Writing to value register zero also writes to value registers one to three
11 Reserved (defaults to independent access)
PWM Invert Complement Source Pair C — This bit controls PWM4/PWM5 pair. When set, this bit inverts the COMPSRCC signal. This bit has no effect in independent mode. Note: PINVC is buffered. The value written does not take effect until the LDOK bit or global load OK is set and the next PWM load cycle begins. Reading PINVC returns the value in the buffer and not necessarily the value in use.
0 No inversion
1 COMPSRCC inverted only in complementary mode
PWM Invert Complement Source Pair B — This bit controls PWM2/PWM3 pair. When set, this bit inverts the COMPSRCB signal. This bit has no effect in independent mode. Note: PINVB is buffered. The value written does not take effect until the LDOK bit or global load OK is set and the next PWM load cycle begins. Reading PINVB returns the value in the buffer and not necessarily the value in use.
1 COMPSRCB inverted only in complementary mode
PWM Invert Complement Source Pair A — This bit controls PWM0/PWM1 pair. When set, this bit inverts the COMPSRCA signal. This bit has no effect on in independent mode. Note: PINVA is buffered. The value written does not take effect until the LDOKA bit or global load OK is set and the next PWM load cycle begins. Reading PINVA returns the value in the buffer and not necessarily the value in use.
1 COMPSRCA inverted only in complementary mode
Address: Module Base + 0x0004 Access: User read/write (1) 1. Read: Anytime Write: This register cannot be modified after the WP bit is set 76543210 FEN5 FEN4 FEN3 FEN2 FEN1 FEN0W R e s e t 00000000 Figure 12-7. PMF Fault Enable Register (PMFFEN) Table 12-9. PMFCFG3 Field Descriptions (continued) Field Description
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12.3.2.6 PMF Fault Mode Register (PMFFMOD)
12.3.2.7 PMF Fault Interrupt Enable Register (PMFFIE)
Table 12-10. PMFFEN Field Descriptions Field Description 6,4-0 FEN[5:0] Fault m Enable — This register cannot be modified after the WP bit is set. 0F A U L Tm input is disabled 1F A U L Tm input is enabled for fault protection m is 0, 1, 2, 3, 4 and 5 Address: Module Base + 0x0005 Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 FMOD5 FMOD4 FMOD3 FMOD2 FMOD1 FMOD0 W R e s e t 00000000 Figure 12-8. PMF Fault Mode Register (PMFFMOD) Table 12-11. PMFFMOD Field Descriptions Field Description 6,4-0 FMOD[5:0] Fault m Pin Recovery Mode — This bit selects automatic or manual recovery of FAULTm input faults. See
0 Manual fault recovery of FAULT m input faults
1 Automatic fault recovery of FAULT m input faults
m is 0, 1, 2, 3, 4 and 5. Address: Module Base + 0x0006 Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 FIE5 FIE4 FIE3 FIE2 FIE1 FIE0 W R e s e t 00000000 Figure 12-9. PMF Fault Interrupt Enable Register (PMFFIE)
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12.3.2.8 PMF Fault Interru pt Flag Register (PMFFIF)
12.3.2.9 PMF Fault Qualifying Samp les Register 0-1 (PMFQSMP0-1)
Table 12-12. PMFFIE Field Descriptions Field Description 6,4-0 FIE[5:0] Fault m Pin Interrupt Enable — This bit enables CPU interrupt requests to be generated by the FAULTm input. The fault protection circuit is independent of the FIEm bit and is active when FENm is set. If a fault is detected, the PWM outputs are disabled or switched to output control according to the PMF Disable Mapping registers. 0F A U L Tm CPU interrupt requests disabled 1F A U L Tm CPU interrupt requests enabled m is 0, 1, 2, 3, 4 and 5. Address: Module Base + 0x0007 Access: User read/write (1) 1. Read: Anytime Write: Anytime. Write 1 to clear. 76543210 FIF5 FIF4 FIF3 FIF2 FIF1 FIF0 W R e s e t 00000000 Figure 12-10. PMF Fault Interrupt Flag Register (PMFFIF) Table 12-13. PMFFIF Field Descriptions Field Description 6,4-0 FIF[5:0] Fault m Interrupt Flag — This flag is set after the required number of samples have been detected after an edge to the active level(1) on the FAULTm input. Writing a logic one to FIFm clears it. Writing a logic zero has no effect. If a set flag is attempted to be cleared and a flag setting event occurs in the same cycle, then the flag remains set. The fault protection is enabled when FENm is set even when the PWMs are not enabled; therefore, a fault will be latched in, requiring to be cleared in order to prevent an interrupt.
0 No fault on the FAULT m input
1 Fault on the FAULT m input
Note: Clearing FIFm satisfies pending FIFm CPU interrupt requests. m is 0, 1, 2, 3, 4 and 5. 1. The active input level may be defined or programmable at SoC level. The default for internally connected resources is active- high. For availability and configurability of fault inputs on pins refer to the device overview section. Address: Module Base + 0x0008 Access: User read/write (1) 1. Read: Anytime Write: This register cannot be modified after the WP bit is set. 76543210 R0 0 0 0 QSMP5 QSMP4 W R e s e t 00000000 Figure 12-11. PMF Fault Qualifying Samples Register (PMFQSMP0)
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12.3.2.10 PMF Output Control Register (PMFOUTC)
Address: Module Base + 0x0009 Access: User read/write (1) 1. Read: Anytime Write: This register cannot be modified after the WP bit is set. 76543210 R QSMP3 QSMP2 QSMP1 QSMP0 W R e s e t 00000000 Figure 12-12. PMF Fault Qualifying Samples Register (PMFQSMP1) Table 12-14. PMFQSMP0-1 Field Descriptions Field Description 7–0 QSMPm[1:0] Fault m Qualifying Samples — This field indicates the number of consecutive samples taken at the FAULT m input to determine if a fault is detected. The first sample is qualified after two bus cycles from the time the fault is present and each sample after that is taken every four core clock cycles. See Table 12-15. This register cannot be modified after the WP bit is set. m is 0, 1, 2, 3, 4 and 5. Table 12-15. Qualifying Samples QSMPm[1:0] Number of Samples 00 1 sample (1) 1. There is an asynchronous path from fault inputs FAULT3-0, FAULT4 if DMPn4=b10, and FAULT5 if DMPn5=b10 to disable PWMs immediately but the fault is qualified in two bus cycles. 01 5 samples 10 10 samples 11 15 samples Address: Module Base + 0x000C Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R0 0 OUTCTL5 OUTCTL4 OUTCTL3 OUTCTL2 OUTCTL1 OUTCTL0 W R e s e t 00000000 Figure 12-13. PMF Output Control Register (PMFOUTC)
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12.3.2.11 PMF Output Control Bit Register (PMFOUTB)
a Table 12-18. Software Output Control Table 12-16. PMFOUTC Field Descriptions Field Description 5–0 OUTCTL[5:0] OUTCTLn Bits — These bits enable software control of their corresponding PWM output. When OUTCTL n is set, the OUTn bit takes over the directly controls the level of the PWMn output. Note: OUTCTLn is buffered if ENCE is set. If ENCE is set, then the value written does not take effect until the next commutation cycle begins. Reading OUTCTLn returns the value in the buffer and not necessarily the value the output control is currently using.If ENCE is not set, then the OUTn bits take immediately effect when OUTCTLn bit is set. If the OUTCTLn bit is cleared then the OUTn control is disabled at the next PMF cycle start. When operating the PWM in complementary mode, these bits must be switched in pairs for proper operation. That is OUTCTL0 and OUTCTL1 must have the same value; OUTCTL2 and OUTCTL3 must have the same value; and OUTCTL4 and OUTCTL5 must have the same value. Otherwise see the behavior described on chapter Section 12.8.2, “BLDC 6-Step Commutation”.
0 Software control disabled
1 Software control enabled
n is 0, 1, 2, 3, 4 and 5. Address: Module Base + 0x000D Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R0 0 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 W R e s e t 00000000 Figure 12-14. PMF Output Control Bit Register (PMFOUTB) Table 12-17. PMFOUTB Field Descriptions Field Description 5–0 OUT[5:0] OUTn Bits — If the corresponding OUTCTL n bit is set, these bits control the PWM outputs, illustrated in Table 12-18. If the related OUTCTLn=1 a read returns the register contents OUTn else the current PWM output states are returned(1) On module version V3 the read returns always the register value. Note: OUTn is buffered if ENCE is set. The value written does not take effect until the next commutation cycle begins. Reading OUTn (with OUTCTLn=1) returns the value in the buffer and not necessarily the value the output control is currently using. n is 0, 1, 2, 3, 4 and 5. 1. only valid for module version V4 OUTn Bit Complementary Channel Operation Independent Channel Operation OUT0 1 — PWM0 is active 0 — PWM0 is inactive 1 — PWM0 is active 0 — PWM0 is inactive
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12.3.2.12 PMF Deadtime Sample Register (PMFDTMS)
12.3.2.13 PMF Correction Control Register (PMFCCTL)
OUT1 1 — PWM1 is complement of PWM0 0 — PWM1 is inactive 1 — PWM1 is active 0 — PWM1 is inactive OUT2 1 — PWM2 is active 0 — PWM2 is inactive 1 — PWM2 is active 0 — PWM2 is inactive OUT3 1 — PWM3 is complement of PWM2 0 — PWM3 is inactive 1 — PWM3 is active 0 — PWM3 is inactive OUT4 1 — PWM4 is active 0 — PWM4 is inactive 1 — PWM4 is active 0 — PWM4 is inactive OUT5 1 — PWM5 is complement of PWM4 0 — PWM5 is inactive 1 — PWM5 is active 0 — PWM5 is inactive Address: Module Base + 0x000E Access: User read/write (1) 1. Read: Anytime Write: Never 76543210 R 0 0 DT5 DT4 DT3 DT2 DT1 DT0 W R e s e t 00000000 Figure 12-15. PMF Deadtime Sample Register (PMFDTMS) Table 12-19. PMFDTMS Field Descriptions Field Description 5–0 DT[5:0] DTn Bits — The DT n bits are grouped in pairs, DT0 and DT1, DT2 and DT3, DT4 and DT5. Each pair reflects the corresponding IS input value as sampled at the end of deadtime. n is 0, 1, 2, 3, 4 and 5. Address: Module Base + 0x000F Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R0 0 ISENS IPOLC IPOLB IPOLA W R e s e t 00000000 Figure 12-16. PMF Correction Control Register (PMFCCTL) OUTn Bit Complementary Channel Operation Independent Channel Operation
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The IPOLx bits take effect at the beginning of the next PWM cycle, regardless of the state of the LDOK bit or global load OK. Select top/bottom software correction by writing 01 to the current select bits, ISENS[1:0], in the PWM control register. Reading the IPOLx bits read the buffered value and not necessarily the value currently in effect. Table 12-20. PMFCCTL Field Descriptions Field Description 5–4 ISENS[1:0] Current Status Sensing Method — This field selects the top/bottom correction scheme, illustrated in Table 12- 21. Note: The user must provide current sensing circuitry causing the voltage at the corresponding input to be low for positive current and high for negative current. The top PWMs are PWM 0, 2, and 4 and the bottom PWMs are PWM 1, 3, and 5. Note: The ISENS bits are not buffered. Changing the current status sensing method can affect the present PWM cycle. IPOLC Current Polarity — This buffered bit selects the PMF Value register for PWM4 and PWM5 in top/bottom software correction in complementary mode.
0 PMF Value 4 register in next PWM cycle
1 PMF Value 5 register in next PWM cycle
Current Polarity — This buffered bit selects the PMF Value register for PWM2 and PWM3 in top/bottom software correction in complementary mode.
0 PMF Value 2 register in next PWM cycle
1 PMF Value 3 register in next PWM cycle
Current Polarity — This buffered bit selects the PMF Value register for PWM0 and PWM1 in top/bottom software correction in complementary mode.
0 PMF Value 0 register in next PWM cycle
1 PMF Value 1 register in next PWM cycle
Table 12-21. Correction Method Selection ISENS Correction Method
00 No correction (1)
- The current status inputs can be used as general purpose input/output ports.
01 Manual correction
10 Current status sample correction on inputs IS0 , IS1, and IS2 during deadtime(2)
- The polarity of the related IS input is latched when both the top and bottom PWMs are off. At the 0% and 100% duty cycle boundaries, there is no deadtime, so no new current value is sensed.
11 Current status sample on inputs IS0 , IS1, and IS2(3)
At the half cycle in center-aligned operation At the end of the cycle in edge-aligned operation 3. Current is sensed even with 0% or 100% duty cycle.
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12.3.2.14 PMF Value 0-5 Register (PMFVAL0-PMFVAL5)
12.3.2.15 PMF Reload Overrun Inte rrupt Enable Register (PMFROIE)
Address: Module Base + 0x0010 PMFVAL0 Module Base + 0x0012 PMFVAL1 Module Base + 0x0014 PMFVAL2 Module Base + 0x0016 PMFVAL3 Module Base + 0x0018 PMFVAL4 Module Base + 0x001A PMFVAL5 Access: User read/write (1) 1. Read: Anytime Write: Anytime 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PMFVALn W R e s e t 000000000 0000000 Figure 12-17. PMF Value n Register (PMFVALn) Table 12-22. PMFVALn Field Descriptions Field Description 15–0 PMFVALn PMF Value n Bits — The 16-bit signed value in this buffered register is the pulse width in PWM clock periods. A value less than or equal to zero deactivates the PWM output for the entire PWM period. A value greater than, or equal to the modulus, activates the PWM output for the entire PWM period. See Table 12-40. The terms activate and deactivate refer to the high and low logic states of the PWM output. Note: PMFVALn is buffered. The value written does not take effect until the related or global load OK bit is set and the next PWM load cycle begins. Reading PMFVALn returns the value in the buffer and not necessarily the value the PWM generator is currently using. n is 0, 1, 2, 3, 4 and 5. Address: Module Base + 0x001C Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R 00000 PMFROIEC PMFROIEB PMFROIEA W R e s e t 00000000 Figure 12-18. PMF Interrupt Enable Register (PMFROIE) Table 12-23. PMFROIE Descriptions Field Description PMFROIEC Reload Overrun Interrupt Enable C —
0 Reload Overrun Interrupt C disabled
1 Reload Overrun Interrupt C enabled
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12.3.2.16 PMF Interrupt Flag Register (PMFROIF)
Reload Overrun Interrupt Enable B —
0 Reload Overrun Interrupt B disabled
1 Reload Overrun Interrupt B enabled
Reload Overrun Interrupt Enable A —
0 Reload Overrun Interrupt A disabled
1 Reload Overrun Interrupt A enabled
Address: Module Base + 0x001D Access: User read/write (1) 1. Read: Anytime Write: Anytime. Write 1 to clear. 76543210 R 00000 PMFROIFC PMFROIFB PMFROIFA W R e s e t 00000000 Figure 12-19. PMF Interrupt Flag Register (PMFROIF) Table 12-24. PMFROIF Field Descriptions Field Description PMFROIFC Reload Overrun Interrupt Flag C — If a reload event occurs when the LDOKC or global load OK bit is not set then this flag will be set.
0 No Reload Overrun C occurred
1 Reload Overrun C occurred
Reload Overrun Interrupt Flag B — If a reload event occurs when the LDOKB or global load OK bit is not set then this flag will be set.
0 No Reload Overrun B occurred
1 Reload Overrun B occurred
Reload Overrun Interrupt Flag A — If PMFCFG2[REV1:REV0]=01 and a reload event occurs when the LDOKA or global load OK bit is not set then this flag will be set. If PMFCFG2[REV1:REV0]=10 and a reload event occurs when the LDOKB or global load OK bit is not set then this flag will be set. If PMFCFG2[REV1:REV0]=11 and a reload event occurs when the LDOKC or global load OK bit is not set then this flag will be set. If PMFCFG2[REV1:REV0]=00 no flag will be generated.
0 No Reload Overrun A occurred
1 Reload Overrun A occurred
Table 12-23. PMFROIE Descriptions (continued) Field Description
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12.3.2.17 PMF Internal Correction Control Register (PMFICCTL)
This register is used to control PWM pulse generation for various applications, such as a power-supply phase-shifting application. ICCx bits apply only in center-aligned operation during complementary mode. These control bits determine whether values set in the IPOLx bits control or the whether PWM count direction controls which PWM value register is used. NOTE The ICCx bits are buffered. The value written does not take effect until the next PWM load cycle begins regardless of the state of the LDOK bit or global load OK. Reading ICCx returns the value in a buffer and not necessarily the value the PWM generator is currently using. The PECx bits apply in edge-aligned and center-aligned operation during complementary mode. Setting the PECx bits overrides the ICCx settings. This allows the PWM pulses generated by both the odd and even PWM value registers to be ANDed together prior to the complementary logic and deadtime insertion. NOTE The PECx bits are buffered. The value written does not take effect until the related LDOK bit or global load OK is set and the next PWM load cycle begins. Reading PECn returns the value in a buffer and not necessarily the value the PWM generator is currently using. Address: Module Base + 0x001E Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R0 0 PECC PECB PECA ICCC ICCB ICCA W R e s e t 00000000 Figure 12-20. PMF Internal Correction Control Register (PMFICCTL) Figure 12-21. PMF Internal Correction Control Register (PMFICCTL) Descriptions Field Description PECC Pulse Edge Control — This bit controls PWM4/PWM5 pair.
0 Normal operation
1 Allow one of PMFVAL4 and PMFVAL5 to activate the PWM pulse and the other to deactivate the pulse
Pulse Edge Control — This bit controls PWM2/PWM3 pair.
1 Allow one of PMFVAL2 and PMFVAL3 to activate the PWM pulse and the other to deactivate the pulse
Pulse Edge Control — This bit controls PWM0/PWM1 pair.
1 Allow one of PMFVAL0 and PMFVAL1 to activate the PWM pulse and the other to deactivate the pulse
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12.3.2.18 PMF Compare Invert Register (PMFCINV)
Internal Correction Control — This bit controls PWM4/PWM5 pair.
0 IPOLC setting determines whether to use the PMFVAL4 or PMFVAL5 register
1 Use PMFVAL4 register when the PWM counter is counting up. Use PMFVAL5 register when counting down. ICCB Internal Correction Control — This bit controls PWM2/PWM3 pair.
0 IPOLB setting determines whether to use the PMFVAL2 or PMFVAL3 register
1 Use PMFVAL2 register when the PWM counter is counting up. Use PMFVAL3 register when counting down. ICCA Internal Correction Control — This bit controls PWM0/PWM1 pair.
0 IPOLA setting determines whether to use the PMFVAL0 or PMFVAL1 register
1 Use PMFVAL0 register when the PWM counter is counting up. Use PMFVAL1 register when counting down. Address: Module Base + 0x001F Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R0 0 CINV5 CINV4 CINV3 CINV2 CINV1 CINV0 W R e s e t 00000000 Figure 12-22. PMF Compare Invert Register (PMFCINV) Figure 12-23. PMF Compare Invert Register (PMFCINV) Descriptions Field Description CINV5 PWM Compare Invert 5 — This bit controls the polarity of PWM compare output 5. Please see the output operations in Figure 12-42 and Figure 12-43.
0 PWM output 5 is high when PMFCNTC (PMFCNTA if MTG=0) is less than PMFVAL5
1 PWM output 5 is high when PMFCNTC (PMFCNTA if MTG=0) is greater than PMFVAL5
PWM Compare Invert 4 — This bit controls the polarity of PWM compare output 4. Please see the output operations in Figure 12-42 and Figure 12-43.
0 PWM output 4 is high when PMFCNTC (PMFCNTA if MTG=0) is less than PMFVAL4
1 PWM output 4 is high when PMFCNTC (PMFCNTA if MTG=0) is greater than PMFVAL4
PWM Compare Invert 3 — This bit controls the polarity of PWM compare output 3. Please see the output operations in Figure 12-42 and Figure 12-43.
0 PWM output 3 is high when PMFCNTB (PMFCNTA if MTG=0) is less than PMFVAL3
1 PWM output 3 is high when PMFCNTB (PMFCNTA if MTG=0) is greater than PMFVAL3
PWM Compare Invert 2 — This bit controls the polarity of PWM compare output 2. Please see the output operations in Figure 12-42 and Figure 12-43.
0 PWM output 2 is high when PMFCNTB (PMFCNTA if MTG=0) is less than PMFVAL2
1 PWM output 2 is high when PMFCNTB (PMFCNTA if MTG=0) is greater than PMFVAL2
Figure 12-21. PMF Internal Correction Control Register (PMFICCTL) Descriptions (continued) Field Description
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12.3.2.19 PMF Enable Control A Register (PMFENCA)
PWM Compare Invert 1 — This bit controls the polarity of PWM compare output 1. Please see the output operations in Figure 12-42 and Figure 12-43.
0 PWM output 1 is high when PMFCNTA is less than PMFVAL1
1 PWM output 1 is high when PMFCNTA is greater than PMFVAL1. CINV0 PWM Compare Invert 0 — This bit controls the polarity of PWM compare output 0. Please see the output operations in Figure 12-42 and Figure 12-43. 0 PWM output 0 is high when PMFCNTA is less than PMFVAL0.
1 PWM output 0 is high when PMFCNTA is greater than PMFVAL0
Address: Module Base + 0x0020 Access: User read/write (1) 1. Read: Anytime Write: Anytime except GLDOKA and RSTRTA which cannot be modified after the WP bit is set. 76543210 R PWMENA GLDOKA 000 RSTRTA LDOKA PWMRIEA W R e s e t 00000000 Figure 12-24. PMF Enable Control A Register (PMFENCA) Table 12-25. PMFENCA Field Descriptions Field Description PWMENA PWM Generator A Enable — When MTG is clear, this bit when set enables the PWM generators A, B and C and PWM0–5 outputs. When PWMENA is clear, PWM generators A, B and C are disabled, and the PWM0–5 outputs are in their inactive states unless the corresponding OUTCTL bits are set. When MTG is set, this bit when set enables the PWM generator A and the PWM0 and PWM1 outputs.When PWMENA is clear, the PWM generator A is disabled and PWM0 and PWM1 outputs are in their inactive states unless the OUTCTL0 and OUTCTL1 bits are set. After setting this bit a reload event is generated at the beginning of the PWM cycle.
0 PWM generator A and PWM0-1 (2–5 if MTG = 0) outputs disabled unless the respective OUTCTL bit is set
1 PWM generator A and PWM0-1 (2–5 if MTG = 0) outputs enabled
Global Load Okay A — When this bit is set, a PMF external global load OK defined on device level replaces the function of LDOKA. This bit cannot be modified after the WP bit is set.
0 LDOKA controls reload of double buffered registers
1 PMF external global load OK controls reload of double buffered registers
Restart Generator A — When this bit is set, PWM generator A wi ll be restarted at the next commutation event. This bit cannot be modified after the WP bit is set. 0 No PWM generator A restart at the next commutation event.
1 PWM generator A restarts at the next commutation event
Figure 12-23. PMF Compare Invert Register (PMFCINV) Descriptions (continued) Field Description
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12.3.2.20 PMF Frequency Contr ol A Register (PMFFQCA)
Load Okay A — When MTG is clear, this bit allows loads of the PRSCA bits, the PMFMODA register, and the PMFVAL0-5 registers into a set of buffers. The buffered prescaler A divisor, PWM counter modulus A value, and all PWM pulse widths take effect at the next PWM reload. When MTG is set, this bit allows loads of the PRSCA bits, the PMFMODA register, and the PMFVAL0–1 registers into a set of buffers. The buffered prescaler divisor A, PWM counter modulus A value, and PWM0–1 pulse widths take effect at the next PWM reload. Set LDOKA by reading it when it is logic zero and then writing a logic one to it. LDOKA is automatically cleared after the new values are loaded, or can be manually cleared before a reload by writing a logic zero to it. Reset clears LDOKA.
0 Do not load new modulus A, prescaler A, and PWM0–1 (2–5 if MTG = 0) values
1 Load prescaler A, modulus A, and PWM0–1 (2–5 if MTG = 0) values
Note: Do not set PWMENA bit before setting the LDOKA bit and do not clear the LDOKA bit at the same time as setting the PWMENA bit. PWMRIEA PWM Reload Interrupt Enable A — This bit enables the PWMRFA flag to generate CPU interrupt requests.
0 PWMRFA CPU interrupt requests disabled
1 PWMRFA CPU interrupt requests enabled
Address: Module Base + 0x0021 Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R LDFQA HALFA PRSCA PWMRFA W R e s e t 00000000 Figure 12-25. PMF Frequency Control A Register (PMFFQCA) Table 12-26. PMFFQCA Field Descriptions Field Description 7–4 LDFQA[3:0] Load Frequency A — This field selects the PWM load frequency according to Table 12-27. See Section 12.4.12.3, “Load Frequency” for more details. Note: The LDFQA field takes effect when the current load cycle is complete, regardless of the state of the LDOKA bit or global load OK. Reading the LDFQA field reads the buffered value and not necessarily the value currently in effect. HALFA Half Cycle Reload A — This bit enables half-cycle reloads in c enter-aligned PWM mode. This bit has no effect on edge-aligned PWMs. It takes effect immediately. When set, reload opportunities occur also when the counter matches the modulus in addition to the start of the PWM period at count zero. See Section 12.4.12.3, “Load Frequency” for more details.
0 Half-cycle reloads disabled
1 Half-cycle reloads enabled
Table 12-25. PMFENCA Field Descriptions (continued) Field Description
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12.3.2.21 PMF Counter A Register (PMFCNTA)
This register displays the state of the 15-bit PWM A counter. 2–1 PRSCA[1:0] Prescaler A — This buffered field selects the PWM clock frequency illustrated in Table 12-28. Note: Reading the PRSCA field reads the buffered value and not necessarily the value currently in effect. The PRSCA field takes effect at the beginning of the next PWM cycle and only when the LDOKA bit or global load OK is set. PWMRFA PWM Reload Flag A — This flag is set at the beginning of ev ery reload cycle regardless of the state of the LDOKA bit or global load OK. Clear PWMRFA by reading PMFFQCA with PWMRFA set and then writing a logic one to the PWMRFA bit. If another reload occurs before the clearing sequence is complete, writing logic one to PWMRFA has no effect.
0 No new reload cycle sinc e last PWMRFA clearing
1 New reload cycle since last PWMRFA clearing
Note: Clearing PWMRFA satisfies pending PWMRFA CPU interrupt requests. Table 12-27. PWM Reload Frequency A LDFQA[3:0] PWM Reload Frequency LDFQ[3:0] PWM Reload Frequency
0000 Every PWM opportunity 1000 Every 9 PWM opportunities
0001 Every 2 PWM opportunities 1001 Every 10 PWM opportunities
0010 Every 3 PWM opportunities 1010 Every 11 PWM opportunities
0011 Every 4 PWM opportunities 1011 Every 12 PWM opportunities
0100 Every 5 PWM opportunities 1100 Every 13 PWM opportunities
0101 Every 6 PWM opportunities 1101 Every 14 PWM opportunities
0110 Every 7 PWM opportunities 1110 Every 15 PWM opportunities
0111 Every 8 PWM opportunities 1111 Every 16 PWM opportunities
Table 12-28. PWM Prescaler A PRSCA[1:0] Prescaler Value P A PWM Clock Frequency fPWM_A 00 1 f core 01 2 f core/2 10 4 f core/4 11 8 f core/8 Address: Module Base + 0x0022 Access: User read/write (1) 1. Read: Anytime Write: Never 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R0 P M F C N T A W R e s e t 000000000 0000000 Figure 12-26. PMF Counter A Register (PMFCNTA) Table 12-26. PMFFQCA Field Descriptions (continued) Field Description
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12.3.2.22 PMF Counter Modulo A Register (PMFMODA)
The 15-bit unsigned value written to this register is the PWM period in PWM clock periods. NOTE The PWM counter modulo register is buffered. The value written does not take effect until the LDOKA bit or global load OK is set and the next PWM load cycle begins. Reading PMFMODA returns the value in the buffer. It is not necessarily the value the PWM generator A is currently using.
12.3.2.23 PMF Deadtime A Register (PMFDTMA)
The 12-bit value written to this register is the number of PWM clock cycles in complementary channel operation. A reset sets the PWM deadtime register to the maximum value of 0x0FFF, selecting a deadtime of 4095 PWM clock cycles. Deadtime is affected by changes to the prescaler value. The deadtime duration is determined as follows: TDEAD_A = PMFDTMA / fPWM_A = PMFDTMA PA Tcore Eqn. 12-1
12.3.2.24 PMF Enable Control B Register (PMFENCB)
Address: Module Base + 0x0024 Access: User read/write (1) 1. Read: Anytime Write: Anytime. Do not write a modulus value of zero for center-aligned operation. Do not write a modulus of zero or one in edge-aligned mode. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMFMODA W R e s e t 000000000 0000000 Figure 12-27. PMF Counter Modulo A Register (PMFMODA) Address: Module Base + 0x0026 Access: User read/write (1) 1. Read: Anytime Write: This register cannot be modified after the WP bit is set. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0000 PMFDTMA W R e s e t 000011111 1111111 Figure 12-28. PMF Deadtime A Register (PMFDTMA) Address: Module Base + 0x0028 Access: User read/write (1) 76543210 R PWMENB GLDOKB 000 RSTRTB LDOKB PWMRIEB W R e s e t 00000000 Figure 12-29. PMF Enable Control B Register (PMFENCB)
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12.3.2.25 PMF Frequency Contr ol B Register (PMFFQCB)
- Read: Anytime. Returns zero if MTG is clear. Write: Anytime if MTG is set.GLDOKB and RSTRTB cannot be modified after the WP bit is set. Table 12-29. PMFENCB Field Descriptions Field Description PWMENB PWM Generator B Enable — If MTG is clear, this bit reads zero and cannot be written. If MTG is set, this bit when set enables the PWM generator B and the PWM2 and PWM3 outputs. When PWMENB is clear, PWM generator B is disabled, and the PWM2 and PWM3 outputs are in their inactive states unless the corresponding OUTCTL bits are set. After setting this bit a reload event is generated at the beginning of the PWM cycle.
0 PWM generator B and PWM2–3 outputs disabled unless the respective OUTCTL bit is set
1 PWM generator B and PWM2–3 outputs enabled
Global Load Okay B — When this bit is set, a PMF external global load OK defined on device level replaces the function of LDOKB. This bit cannot be modified after the WP bit is set.
0 LDOKB controls double reload of buffered registers
Restart Generator B — When this bit is set, PWM generator B wi ll be restarted at the next commutation event. This bit cannot be modified after the WP bit is set.
0 No PWM generator B restart at the next commutation event
1 PWM generator B restart at the next commutation event
Load Okay B — If MTG is clear, this bit reads zero and cannot be written. If MTG is set, this bit loads the PRSCB bits, the PMFMODB register and the PMFVAL2-3 registers into a set of buffers. The buffered prescaler divisor B, PWM counter modulus B value, PWM2–3 pulse widths take effect at the next PWM reload. Set LDOKB by reading it when it is logic zero and then writing a logic one to it. LDOKB is automatically cleared after the new values are loaded, or can be manually cleared before a reload by writing a logic zero to it. Reset clears LDOKB.
0 Do not load new modulus B, prescaler B, and PWM2–3 values
1 Load prescaler B, modulus B, and PWM2–3 values
Note: Do not set PWMENB bit before setting the LDOKB bit and do not clear the LDOKB bit at the same time as setting the PWMENB bit. PWMRIEB PWM Reload Interrupt Enable B — If MTG is clear, this bit reads zero and cannot be written. If MTG is set, this bit enables the PWMRFB flag to generate CPU interrupt requests.
0 PWMRFB CPU interrupt requests disabled
1 PWMRFB CPU interrupt requests enabled
Address: Module Base + 0x0029 Access: User read/write (1) 1. Read: Anytime. Returns zero if MTG is clear. Write: Anytime if MTG is set. 76543210 R LDFQB HALFB PRSCB PWMRFB W R e s e t 00000000 Figure 12-30. PMF Frequency Control B Register (PMFFQCB)
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Table 12-30. PMFFQCB Field Descriptions Field Description 7–4 LDFQB[3:0] Load Frequency B — This field selects the PWM load frequency according to Table 12-31. See Section 12.4.12.3, “Load Frequency” for more details. Note: The LDFQB field takes effect when the current load cycle is complete, regardless of the state of the LDOKB bit or global load OK. Reading the LDFQB field reads the buffered value and not necessarily the value currently in effect. HALFB Half Cycle Reload B — This bit enables half-cycle reloads in c enter-aligned PWM mode. This bit has no effect on edge-aligned PWMs. It takes effect immediately. When set, reload opportunities occur also when the counter matches the modulus in addition to the start of the PWM period at count zero. See Section 12.4.12.3, “Load Frequency” for more details. 2–1 PRSCB[1:0] Prescaler B — This buffered field selects the PWM clock frequency illustrated in Table 12-32. Note: Reading the PRSCB field reads the buffered value and not necessarily the value currently in effect. The PRSCB field takes effect at the beginning of the next PWM cycle and only when the LDOKB bit or global load OK is set. PWMRFB PWM Reload Flag B — This flag is set at the beginning of ev ery reload cycle regardless of the state of the LDOKB bit. Clear PWMRFB by reading PMFFQCB with PWMRFB set and then writing a logic one to the PWMRFB bit. If another reload occurs before the clearing sequence is complete, writing logic one to PWMRFB has no effect.
0 No new reload cycle sinc e last PWMRFB clearing
1 New reload cycle since last PWMRFB clearing
Note: Clearing PWMRFB satisfies pending PWMRFB CPU interrupt requests. Table 12-31. PWM Reload Frequency B LDFQB[3:0] PWM Reload Frequency LDFQ[3:0] PWM Reload Frequency Table 12-32. PWM Prescaler B PRSCB[1:0] Prescaler Value P B PWM Clock Frequency fPWM_B 00 1 f core 01 2 f core/2 10 4 f core/4 11 8 f core/8
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12.3.2.26 PMF Counter B Register (PMFCNTB)
This register displays the state of the 15-bit PWM B counter.
12.3.2.27 PMF Counter Modulo B Register (PMFMODB)
The 15-bit unsigned value written to this register is the PWM period in PWM clock periods. NOTE The PWM counter modulo register is buffered. The value written does not take effect until the LDOKB bit or global load OK is set and the next PWM load cycle begins. Reading PMFMODB returns the value in the buffer. It is not necessarily the value the PWM generator B is currently using.
12.3.2.28 PMF Deadtime B Register (PMFDTMB)
The 12-bit value written to this register is the number of PWM clock cycles in complementary channel operation. A reset sets the PWM deadtime register to the maximum value of 0x0FFF, selecting a deadtime Address: Module Base + 0x002A Access: User read/write (1) 1. Read: Anytime. Returns zero if MTG is clear. Write: Never 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PMFCNTB W R e s e t 000000000 0000000 Figure 12-31. PMF Counter B Register (PMFCNTB) Address: Module Base + 0x002C Access: User read/write (1) 1. Read: Anytime. Returns zero if MTG is clear. Write: Anytime if MTG is set.Do not write a modulus value of zero for center-aligned operation. Do not write a modulus of zero or one in edge-aligned mode. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R0 PMFMODB W R e s e t 000000000 0000000 Figure 12-32. PMF Counter Modulo B Register (PMFMODB) Address: Module Base + 0x002E Access: User read/write (1) 1. Read: Anytime. Returns zero if MTG is clear. Write: Anytime if MTG is set. This register cannot be modified after the WP bit is set. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0000 PMFDTMB W R e s e t 000011111 1111111 Figure 12-33. PMF Deadtime B Register (PMFDTMB)
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of 4095 PWM clock cycles. Deadtime is affected by changes to the prescaler value. The deadtime duration is determined as follows: TDEAD_B = PMFDTMB / fPWM_B = PMFDTMB PB Tcore Eqn. 12-2
12.3.2.29 PMF Enable Control C Register (PMFENCC)
Address: Module Base + 0x0030 Access: User read/write (1) 1. Read: Anytime. Returns zero if MTG is clear. Write: Anytime if MTG is set. GLDOKC and RSTRTC cannot be modified after the WP bit is set. 76543210 R PWMENC GLDOKC 000 RSTRTC LDOKC PWMRIEC W R e s e t 00000000 Figure 12-34. PMF Enable Control C Register (PMFENCC) Table 12-33. PMFENCC Field Descriptions Field Description PWMENC PWM Generator C Enable — If MTG is clear, this bit reads zero and cannot be written. If MTG is set, this bit when set enables the PWM generator C and the PWM4 and PWM5 outputs. When PWMENC is clear, PWM generator C is disabled, and the PWM4 and PWM5 outputs are in their inactive states unless the corresponding OUTCTL bits are set. After setting this bit a reload event is generated at the beginning of the PWM cycle.
0 PWM generator C and PWM4–5 outputs disabled unless the respective OUTCTL bit is set
1 PWM generator C and PWM4–5 outputs enabled
Global Load Okay C — When this bit is set, a PMF external global load OK defined on device level replaces the function of LDOKC. This bit cannot be modified after the WP bit is set.
0 LDOKC controls reload of double buffered registers
Restart Generator C — When this bit is set, PWM generator C w ill be restarted at the next commutation event. This bit cannot be modified after the WP bit is set.
0 No PWM generator C restart at the next commutation event
1 PWM generator C restart at the next commutation event
Load Okay C — If MTG is clear, this bit reads zero and can not be written. If MTG is set, this bit loads the PRSCC bits, the PMFMODC register and the PMFVAL4–5 registers into a set of buffers. The buffered prescaler divisor C, PWM counter modulus C value, PWM4–5 pulse widths take effect at the next PWM reload. Set LDOKC by reading it when it is logic zero and then writing a logic one to it. LDOKC is automatically cleared after the new values are loaded, or can be manually cleared before a reload by writing a logic zero to it. Reset clears LDOKC.
0 Do not load new modulus C, prescaler C, and PWM4–5 values
1 Load prescaler C, modulus C, and PWM4–5 values
Note: Do not set PWMENC bit before setting the LDOKC bit and do not clear the LDOKC bit at the same time as setting the PWMENC bit.
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12.3.2.30 PMF Frequency Contr ol C Register (PMFFQCC)
PWM Reload Interrupt Enable C — If MTG is clear, this bit reads zero and cannot be written. If MTG is set, this bit enables the PWMRFC flag to generate CPU interrupt requests.
0 PWMRFC CPU interrupt requests disabled
1 PWMRFC CPU interrupt requests enabled
Address: Module Base + 0x0031 Access: User read/write (1) 1. Read: Anytime. Returns zero if MTG is clear. Write: Anytime if MTG is set. 76543210 R LDFQC HALFC PRSCC PWMRFC W R e s e t 00000000 Figure 12-35. PMF Frequency Control C Register (PMFFQCC) Table 12-34. PMFFQCC Field Descriptions Field Description 7–4 LDFQC[3:0] Load Frequency C — This field selects the PWM load frequency according to Table 12-35. See Section 12.4.12.3, “Load Frequency” for more details. Note: The LDFQC field takes effect when the current load cycle is complete, regardless of the state of the LDOKC bit or global load OK. Reading the LDFQC field reads the buffered value and not necessarily the value currently in effect. HALFC Half Cycle Reload C — This bit enables half-cycle reloads in c enter-aligned PWM mode. This bit has no effect on edge-aligned PWMs. It takes effect immediately. When set, reload opportunities occur also when the counter matches the modulus in addition to the start of the PWM period at count zero. See Section 12.4.12.3, “Load Frequency” for more details. 2–1 PRSCC[1:0] Prescaler C — This buffered field selects the PWM clock frequency illustrated in Table 12-36. Note: Reading the PRSCC field reads the buffered value and not necessarily the value currently in effect. The PRSCC field takes effect at the beginning of the next PWM cycle and only when the LDOKC bit or global load OK is set. PWMRFC PWM Reload Flag C — This flag is set at the beginning of ev ery reload cycle regardless of the state of the LDOKC bit or global load OK. Clear PWMRFC by reading PMFFQCC with PWMRFC set and then writing a logic one to the PWMRFC bit. If another reload occurs before the clearing sequence is complete, writing logic one to PWMRFC has no effect.
0 No new reload cycle sinc e last PWMRFC clearing
1 New reload cycle since last PWMRFC clearing
Note: Clearing PWMRFC satisfies pending PWMRFC CPU interrupt requests. Table 12-33. PMFENCC Field Descriptions (continued) Field Description
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12.3.2.31 PMF Counter C Register (PMFCNTC)
This register displays the state of the 15-bit PWM C counter.
12.3.2.32 PMF Counter Modulo C Register (PMFMODC)
The 15-bit unsigned value written to this register is the PWM period in PWM clock periods. Table 12-35. PWM Reload Frequency C LDFQC[3:0] PWM Reload Frequency LDFQ[3:0] PWM Reload Frequency Table 12-36. PWM Prescaler C PRSCC[1:0] Prescaler Value P C PWM Clock Frequency fPWM_C 00 1 f core 01 2 f core/2 10 4 f core/4 11 8 f core/8 Address: Module Base + 0x0032 Access: User read/write (1) 1. Read: Anytime. Returns zero if MTG is clear. Write: Never 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PMFCNTC W R e s e t 000000000 0000000 Figure 12-36. PMF Counter C Register (PMFCNTC) Address: Module Base + 0x 0034 Access: User read/write (1) 1. Read: Anytime. Returns zero if MTG is clear. Write: Anytime if MTG is set. Do not write a modulus value of zero for center-aligned operation. Do not write a modulus of zero or one in edge-aligned mode. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMFMODC W R e s e t 000000000 0000000 Figure 12-37. PMF Counter Modulo C Register (PMFMODC)
Chapter 12 Pulse Width Modulator with Fault Protection (PMF15B6CV4) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 423 NOTE The PWM counter modulo register is buffered. The value written does not take effect until the LDOKC bit or global load OK is set and the next PWM load cycle begins. Reading PMFMODC returns the value in the buffer. It is not necessarily the value the PWM generator A is currently using.
12.3.2.33 PMF Deadtime C Register (PMFDTMC)
The 12-bit value written to this register is the number of PWM clock cycles in complementary channel operation. A reset sets the PWM deadtime register to the maximum value of 0x0FFF, selecting a deadtime of 4095 PWM clock cycles. Deadtime is affected by changes to the prescaler value. The deadtime duration is determined as follows: TDEAD_C = PMFDTMC / fPWM_C = PMFDTMC PC Tcore Eqn. 12-3
12.3.2.34 PMF Disable Mapping Registers (PMFDMP0-5)
Address: Module Base + 0x0036 Access: User read/write (1) 1. Read: Anytime. Returns zero if MTG is clear. Write: Anytime if MTG is set.This register cannot be modified after the WP bit is set. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0000 PMFDTMC W R e s e t 000011111 1111111 Figure 12-38. PMF Deadtime C Register (PMFDTMC) Address: Module Base + 0x0038 PMFDMP0 Module Base + 0x0039 PMFDMP1 Module Base + 0x003A PMFDMP2 Module Base + 0x003B PMFDMP3 Module Base + 0x003C PMFDMP4 Module Base + 0x003D PMFDMP5 Access: User read/write (1) 1. Read: Anytime Write: This register cannot be modified after the WP bit is set. 76543210 R DMPn5D M P n4D M P n3D M P n2D M P n1D M P n0W R e s e t 00000000 Figure 12-39. PMF Disable Mapping Register (PMFDMP0-5)
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12.3.2.35 PMF Output Control on Fault Register (PMFOUTF)
Table 12-37. PMFDMP0-5 Field Descriptions Field Description 7-6 DMPn5 PWM Disable Mapping Channel n FAULT5 — This bit selects for PWM n whether the output is disabled or forced to OUTFn at a FAULT5 event. Disabling PWMn has priority over forcing PWMn to OUTFn. This register cannot be modified after the WP bit is set. This setting takes effect at the next cycle start.
00 PWMn unaffected by FAULT5 event (interrupt flag setting only)
01 PWMn unaffected by FAULT5 event (interrupt flag setting only)
10 PWMn disabled on FAULT5 event
11 PWMn forced to OUTFn on FAULT5 event
n is 0, 1, 2, 3, 4 and 5. 5-4 DMPn4 PWM Disable Mapping Channel n FAULT4 — This bit selects for PWM n whether the output is disabled or forced to OUTFn at a FAULT4 event. Disabling PWMn has priority over forcing PWMn to OUTFn. This register cannot be modified after the WP bit is set. This setting takes effect at the next cycle start.
00 PWMn unaffected by FAULT4 event (interrupt flag setting only)
01 PWMn unaffected by FAULT4 event (interrupt flag setting only)
10 PWMn disabled on FAULT4 event
11 PWMn forced to OUTFn on FAULT4 event
n is 0, 1, 2, 3, 4 and 5. 3-0 DMPn PWM Disable Mapping Channel n FAULT3-0 — This bit selects for PWMn if the output is disabled at a FAULT3- 0 event. Disabling PWMn has priority over forcing PWMn to OUTFn. This bit cannot be modified after the WP bit is set. FAULT3-0 have priority over FAULT5-4.This setting takes effect at the next cycle start. 0P W Mn unaffected by FAULT3-0 event 1P W Mn disabled on FAULT3-0 event n is 0, 1, 2, 3, 4 and 5. Address: Module Base + 0x003E Access: User read/write (1) 1. Read: Anytime Write: This register cannot be modified after the WP bit is set. 76543210 R0 0 OUTF5 OUTF4 OUTF3 OUTF2 OUTF1 OUTF0 W R e s e t 00000000 Figure 12-40. PMF Output Control on Fault Register (PMFOUTF) Table 12-38. PMFOUTF Field Descriptions Field Description 5–0 OUTF[5:0] OUTF Bits — When the corresponding DMP n4 or DMPn5 bits are set to switch to output control on a related FAULT4 or FAULT5 event, these bits control the PWM outputs, illustrated in Table 12-39.This register cannot be modified after the WP bit is set.
Chapter 12 Pulse Width Modulator with Fault Protection (PMF15B6CV4) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 425 Table 12-39. Software Output Control on FAULT4 or FAULT5 Event OUTFn Bit Complementary Channel Operation Independent Channel Operation OUTF0 1 — PWM0 is active 0 — PWM0 is inactive 1 — PWM0 is active 0 — PWM0 is inactive OUTF1 1 — PWM1 is complement of PWM0 0 — PWM1 is inactive 1 — PWM1 is active 0 — PWM1 is inactive OUTF2 1 — PWM2 is active 0 — PWM2 is inactive 1 — PWM2 is active 0 — PWM2 is inactive OUTF3 1 — PWM3 is complement of PWM2 0 — PWM3 is inactive 1 — PWM3 is active 0 — PWM3 is inactive OUTF4 1 — PWM4 is active 0 — PWM4 is inactive 1 — PWM4 is active 0 — PWM4 is inactive OUTF5 1 — PWM5 is complement of PWM4 0 — PWM5 is inactive 1 — PWM5 is active 0 — PWM5 is inactive
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12.4 Functional Description
12.4.1 Block Diagram
A block diagram of the PMF is shown in Figure 12-1. The MTG bit allows the use of multiple PWM generators (A, B, and C) or just a single generator (A). PWM0 and PWM1 constitute Pair A, PWM2 and PWM3 constitute Pair B, and PWM4 and PWM5 constitute Pair C. Figure 12-41 depicts Pair A signal paths of PWM0 and PWM1. Pairs B and C have the same structure. Figure 12-41. Detail of PWM0 and PWM1 Signal Paths NOTE It is possible to have both channels of a complementary pair to be high. For example, if the TOPNEGA (negative polarity for PWM0), BOTNEGA (negative polarity for PWM1), MSK0 and MSK1 bits are set, both the PWM complementary outputs of generator A will be high. See Section 12.3.2.2, “PMF Configure 1 Register (PMFCFG1)” for the description of TOPNEG and BOTNEG bits, and Section 12.3.2.3, “PMF Configure 2 Register (PMFCFG2)” for the description of the MSK0 and MSK1 bits. INDEPA 1OUTF0 OUT0 Fault4-5 Detect OUTCTL0 CINV0 Gen. 0 0 0 0 0 0 1 1 0 x x 1 x PECA in deadtime Fault0-3 Detect MSK0 TOPNEGA PWM0 1OUTF1 OUT1 OUTCTL1 CINV1 Gen. 1 MSK1 PWM1 (OUTCTL1 & PWMENA) | (~OUTCTL1 & OUT1) COMP SRCA BOTNEGA Fault4-5 Detect PINVA Complementary Mode Independent Mode Softw. Output Control Generated PWM Softw. Output Control Generated PWM = Functional Block = Configuration Register Bit ICCA IPOLA Count direction ISENS IS0 (A) (A) Correction MODA VAL1 VAL0 DTMA Deadtime Dist. Correction and Asymmetric PWM
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12.4.2 Prescaler
To permit lower PWM frequencies, the prescaler produces the PWM clock frequency by dividing the core clock frequency by one, two, four, and eight. Each PWM generator has its own prescaler divisor. Each prescaler is buffered and will not be used by its PWM generator until the corresponding Load OK bit is set and a new PWM reload cycle begins.
12.4.3 PWM Generator
Each PWM generator contains a 15-bit up/down PWM counter producing output signals with software- selectable
- Alignment — The logic state of each pair EDGE bit determines whether the PWM pair outputs are edge-aligned or center-aligned
- Period — The value written to each pair PWM count er modulo register is used to determine the PWM pair period. The period can also be varied by using the prescaler
- With edge-aligned output, the modulus is th e period of the PWM output in clock cycles
- With center-aligned output, the modulus is one-h alf of the PWM output period in clock cycles
- Pulse width — The number written to the PWM va lue register determines the pulse width duty cycle of the PWM output in clock cycles — With center-aligned output, the pul se width is twice the value written to the PWM value register — With edge-aligned output, the pulse width is the value written to the PWM value register
12.4.3.1 Alignment and Compare Output Polarity
Each edge-align bit, EDGEx, selects either center-aligned or edge-aligned PWM generator outputs. PWM compare output polarity is selected by the CINVn bit field in the source control (PMFCINV) register. Please see the output operations in Figure 12-42 and Figure 12-43. The PWM compare output is driven to a high state when the value of PWM value (PMFV ALn) register is greater than the value of PWM counter, and PWM compare is counting downwards if the corresponding channel CINVn=0. Or, the PWM compare output is driven to low state if the corresponding channel CINVn=1. The PWM compare output is driven to low state when the value of PWM value (PMFV ALn) register matches the value of PWM counter, and PWM counter is counting upwards if the corresponding channel CINVn=0. Or, the PWM compare output is driven to high state if the corresponding channel CINVn=1.
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Figure 12-42. Center-Aligned PWM Output Figure 12-43. Edge-Aligned PWM Output
12.4.3.2 Period
A PWM period is determined by the value written to the PWM counter modulo registers PMFMODx. The PWM counter is an up/down counter in center-aligned mode. In this mode the PWM highest output resolution is two core clock cycles. PWM period = (PWM modulus) (PWM clock period) 2 Eqn. 12-4 Figure 12-44. Center-Aligned PWM Period Up/Down Counter Modulus = 4 Alignment Reference PWM Compare Output Duty Cycle = 50% CINVn= 0 CINVn = 1 Up Counter Modulus = 4 Alignment Reference PWM Compare Output Duty Cycle = 50% CINVn = 0 CINVn = 1 UP/DOWN COUNTERER PWM CLOCK PERIOD PWM PERIOD = 8 x PWM CLOCK PERIOD MODULUS = 4 C O U N T E R 1234 3210
Chapter 12 Pulse Width Modulator with Fault Protection (PMF15B6CV4) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 429 NOTE Because of the equals-comparator architecture of this PMF, the modulus equals zero case is considered illegal in center-aligned mode. Therefore, the modulus register does not return to zero, and a modulus value of zero will result in waveforms inconsistent with the other modulus waveforms. If a modulus of zero is loaded, the counter will continually count down from 0x7FFF. This operation will not be tested or guaranteed. Consider it illegal. However, the deadtime constraints and fault conditions will still be guaranteed. In edge-aligned mode, the PWM counter is an up counter. The PWM output resolution is one core clock cycle. PWM period = PWM modulus PWM clock period Eqn. 12-5 Figure 12-45. Edge-Aligned PWM Period NOTE In edge-aligned mode the modulus equals zero and one cases are considered illegal.
12.4.3.3 Duty Cycle
The signed 16-bit number written to the PMF value registers (PMFV ALn) is the pulse width in PWM clock periods of the PWM generator output (or period minus the pulse width if CINVn=1). NOTE A PWM value less than or equal to zero deactivates the PWM output for the entire PWM period. A PWM value greater than or equal to the modulus activates the PWM output for the entire PWM period when CINVn=0, and vice versa if CINVn=1. UP COUNTERER PWM CLOCK PERIOD PWM PERIOD = 4 x PWM CLOCK PERIOD MODULUS = 4 C O U N T E R 1234 1 Duty cycle PMFVAL
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Center-aligned operation is illustrated in Figure 12-46. PWM pulse width = (PWM value) (PWM clock period) 2 Eqn. 12-6 Figure 12-46. Center-Aligned PWM Pulse Width Edge-aligned operation is illustrated in Figure 12-47. PWM pulse width = (PWM value) (PWM clock period) Eqn. 12-7 Table 12-40. PWM Value and Underflow Conditions PMFVALn Condition PWM Value Used 0x0000–0x7FFF Normal Value in registers 0x8000–0xFFFF Underflow 0x0000 P/DOWN COUNTERER MODULUS = 4 PWM VALUE = 0 0/4 = 0% PWM VALUE = 1 1/4 = 25% PWM VALUE = 2 2/4 = 50% PWM VALUE = 3 3/4 = 75% PWM VALUE = 4 4/4 = 100% COUNTER 1234 32 10 1234 32 10
Chapter 12 Pulse Width Modulator with Fault Protection (PMF15B6CV4) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 431 Figure 12-47. Edge-Aligned PWM Pulse Width
12.4.4 Independent or Comple mentary Channel Operation
Writing a logic one to an INDEPx bit configures a pair of the PWM outputs as two independent PWM channels. Each PWM output has its own PWM value register operating independently of the other channels in independent channel operation. Writing a logic zero to a INDEPx bit configures the PWM output as a pair of complementary channels. The PWM outputs are paired as shown in Figure 12-48 in complementary channel operation. Figure 12-48. Complementary Channel Pairs UP COUNTERER PWM VALUE = 0 MODULUS = 4 PWM VALUE = 1 PWM VALUE = 2 PWM VALUE = 3 PWM VALUE = 4 0/4 = 0% 1/4 = 25% 2/4 = 50% 3/4 = 75% 4/4 = 100% COUNTER 123 PWM CHANNELS 0 AND 1 PMFVAL1 PWM CHANNELS 2 AND 3 PWM CHANNELS 4 AND 5 REGISTER TOP BOTTOM TOP BOTTOM TOP BOTTOM PMFVAL0 REGISTER PMFVAL3 REGISTER PMFVAL2 REGISTER PMFVAL5 REGISTER PMFVAL4 REGISTER PAIR A PAIR B PAIR C
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The complementary channel operation is for driving top and bottom transistors in a motor drive circuit, such as the one in Figure 12-49. Figure 12-49. Typical 3-Phase AC Motor Drive In complementary channel operation following additional features exist:
- Deadtime insertion
- Separate top and bottom pulse width correc tion via current status inputs or software
- Three variants of PWM output: — Asymmetric in center-aligned mode — Variable edge placement in edge-aligned mode — Double switching in center-aligned mode
12.4.5 Deadtime Generators
While in complementary operation, each PWM pair can be used to drive top/bottom transistors, as shown in Figure 12-50. Ideally, the PWM pairs are an inversion of each other. When the top PWM channel is active, the bottom PWM channel is inactive, and vice versa. NOTE To avoid a short-circuit on the DC bus and endangering the transistor, there must be no overlap of conducting intervals between the top and bottom transistor. But the transistor’s characteristics make its switching-off time longer than switching-on time. To avoid the conducting overlap of the top and bottom transistors, deadtime needs to be inserted in the switching period. Deadtime generators automatically insert software-selectable activation delays into each pair of PWM outputs. The deadtime register (PMFDTMx) specifies the number of PWM clock cycles to use for deadtime delay. Every time the deadtime generator inputs changes state, deadtime is inserted. Deadtime forces both PWM outputs in the pair to the inactive state. A method of correcting this, adding to or subtracting from the PWM value used, is discussed next. PWM PWM AC INPUTS TO MOTOR PWM PWM PWM PWM A B C PHASE
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Figure 12-52. Deadtime at Duty Cycle Boundaries Figure 12-53. Deadtime and Small Pulse Widths NOTE The waveform at the output is delayed by two core clock cycles for deadtime insertion.
12.4.6 Top/Bottom Correction
In complementary mode, either the top or the bottom transistor controls the output voltage. However, deadtime has to be inserted to avoid overlap of conducting interval between the top and bottom transistor. Both transistors in complementary mode are off during deadtime, allowing the output voltage to be determined by the current status of the load and introduce distortion in the output voltage. See Figure 12- 54. On AC induction motors running open-loop, the distortion typically manifests itself as poor low-speed performance, such as torque ripple and rough operation. PWM0, NO DEADTIME PWM1, NO DEADTIME PWM0, DEADTIME = 2 PWM1, DEADTIME = 2 MODULUS = 3 PWM VALUE = 1 PWM VALUE = 3 PWM VALUE = 3 PWM VALUE = 1 MODULUS = 3 PWM0, NO DEADTIME PWM0, DEADTIME = 3 PWM1, NO DEADTIME PWM1, DEADTIME = 3 2PWM VALUE PWM Value = 1PWM Value = 2PWM Value = 3
Chapter 12 Pulse Width Modulator with Fault Protection (PMF15B6CV4) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 435 Figure 12-54. Deadtime Distortion During deadtime, load inductance distorts output voltage by keeping current flowing through the diodes. This deadtime current flow creates a load voltage that varies with current direction. With a positive current flow, the load voltage during deadtime is equal to the bottom supply, putting the top transistor in control. With a negative current flow, the load voltage during deadtime is equal to the top supply putting the bottom transistor in control. Remembering that the original PWM pulse widths were shortened by deadtime insertion, the averaged sinusoidal output will be less than the desired value. However, when deadtime is inserted, it creates a distortion in motor current waveform. This distortion is aggravated by dissimilar turn-on and turn-off delays of each of the transistors. By giving the PWM module information on which transistor is controlling at a given time, this distortion can be corrected. For a typical circuit in complementary channel operation, only one of the transistors will be effective in controlling the output voltage at any given time. This depends on the direction of the motor current for that pair. See Figure 12-54. To correct distortion one of two different factors must be added to the desired PWM value, depending on whether the top or bottom transistor is controlling the output voltage. Therefore, the software is responsible for calculating both compensated PWM values prior to placing them in an odd- numbered/even numbered PWM register pair. Either the odd or the even PMFV AL register controls the pulse width at any given time. For a given PWM pair, whether the odd or even PMFV AL register is active depends on either:
- The state of the current status input, IS , for that driver
- The state of the odd/even correction bit, IPOLx, for that driver if ICC bits in the PMFICCTL register are set to zeros
- The direction of PWM counter if ICC bits in the PMFICCTL register are set to ones To correct deadtime distortion, software can decrease or increase the value in the appropriate PMFV AL register. DESIRED DEADTIME PWM TO TOP POSITIVE NEGATIVE PWM TO BOTTOM POSITIVE CURRENT NEGATIVE CURRENT LOAD VOLTAGE TRANSISTOR TRANSISTOR LOAD VOLTAGE LOAD VOLTAGE CURRENT CURRENT
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- In edge-aligned operation, decreasi ng or increasing the PWM value by a correction value equal to the deadtime typically compensates for deadtime distortion.
- In center-aligned operation, decreasing or increa sing the PWM value by a correction value equal to one-half the deadtime typically compensates for deadtime distortion. In the complementary channel operation, ISENS selects one of three correction methods:
- Manual correction
- Automatic current status correction during deadtime
- Automatic current status correction when the PWM counter value equals the value in the PWM counter modulus registers NOTE External current status sensing circuitry is required at the corresponding inputs which produces a logic zero level for positive current and logic one for negative current. PWM 0, 2, and 4 are considered the top PWMs while the bottom PWMs are PWM 1, 3, and 5.
12.4.6.1 Manual Correction
The IPOLx bits select either the odd or the even PWM value registers to use in the next PWM cycle. Table 12-41. Correction Method Selection ISENS Correction Method
- The current status inputs can be used as general purpose input/output ports.
- The polarity of the IS input is latched when both the top and bottom PWMs are off. At the 0% and 100% duty cycle boundaries, there is no deadtime, so no new current value is sensed.
At the half cycle in center-aligned operation At the end of the cycle in edge-aligned operation 3. Current is sensed even with 0% or 100% duty cycle. Table 12-42. Top/Bottom Manual Correction Bit Logic state Output Control IPOLA 0 PMFVAL0 controls PWM0/PWM1 pair
1 PMFVAL1 controls PWM0/PWM1 pair
IPOLB 0 PMFVAL2 controls PWM2/PWM3 pair
1 PMFVAL3 controls PWM2/PWM3 pair
IPOLC 0 PMFVAL4 controls PWM4/PWM5 pair
1 PMFVAL5 controls PWM4/PWM5 pair
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Sampled results will be DT0 = 0 and DT1 = 1. Thus, the best time to change one PWM value register to another is just before the current zero crossing. Figure 12-57. Output Voltage Waveforms
12.4.6.2 Current-Sen sing Correction
A current sense input, IS, for a PWM pair selects either the odd or the even PWM value registers to use in the next PWM cycle. The selection is based on user-provided current sense circuitry driving the related IS input high for negative current and low for positive current. Previously shown, the current direction can be determined by the output voltage during deadtime. Thus, a simple external voltage sensor can be used when current status is completed during deadtime, ISENS = 10. Deadtime does not exist at the 100 percent and zero percent duty cycle boundaries. Therefore, the second automatic mode must be used for correction, ISENS = 11, where current status is sampled at the half cycle Table 12-43. Top/Bottom Current Sense Correction Pin Logic State Output Control IS0 0 PMFVAL0 controls PWM0/PWM1 pair IS1 0 PMFVAL2 controls PWM2/PWM3 pair IS2 0 PMFVAL4 controls PWM4/PWM5 pair T = DEADTIME INTERVAL BEFORE ASSERTION OF TOP PWM B = DEADTIME INTERVAL BEFORE ASSERTION OF BOTTOM PWM
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Figure 12-61. Correction with Negative Current
12.4.7 Asymmetric PWM Output
In complementary center-aligned mode, the PWM duty cycle is able to change alternatively at every half cycle. The count direction of the PWM counter selects either the odd or the even PWM value registers to use in the PWM cycle. For counting up, select even PWM value registers to use in the PWM cycle. For counting down, select odd PWM value registers to use in the PWM cycle. The related CINVn bits of the PWM pair must select the same polarity for both generators. NOTE If an ICCx bit in the PMFICCTL register changes during a PWM period, the new value does not take effect until the next PWM period. ICCx bits take effect at the end of each PWM cycle regardless of the state of the related LDOKx bit or global load OK. Table 12-44. Top/Bottom Corrections Selected by ICCn Bits Bit Logic State Output Control ICCA 0 IPOLA Controls PWM0/PWM1 Pair
1 PWM Count Direction Co ntrols PWM0/PWM1 Pair
ICCB 0 IPOLB Controls PWM2/PWM3 Pair
1 PWM Count Direction Co ntrols PWM2/PWM3 Pair
ICCC 0 IPOLC Controls PWM4/PWM5 Pair
1 PWM Count Direction Co ntrols PWM4/PWM5 Pair
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12.4.8 Variable Edge Placement PWM Output
In complementary edge-aligned mode, the timing of both edges of the PWM output can be controlled using the PECx bits in the PMFICCTL register and the CINVn bits in the PMFCINV register. The edge-aligned signal created by the even value register and the associated CINVn bit is ANDed with the signal created by the odd value register and its associated CINVn bit. The resulting signal can optionally be negated by PINVx and is then fed into the complement and deadtime logic (Figure 12-63). If the value of the inverted register exceeds the non-inverted register value, no output pulse is generated (0% or 100% duty cycle). See right half of Figure 12-64. In contrast to asymmetric PWM output mode, the PWM phase shift can pass the PWM cycle boundary. Figure 12-63. Logic AND Function with Signal Inversions Modulus = 4 0 Up/Down Counter Even PWM Value = 1 Odd PWM Value = 3 Even PWM Value = 3 Odd PWM Value = 1 Even PWM Value Odd PWM Value Odd PWM Value Even PWM Value PINVA PWM GENERATOR 1 PWM GENERATOR 0 CINV0 CINV1 PECA=1 to complement COMPSRC logic and dead time insertion
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Figure 12-64. Variable Edge Placement Waveform - Phase Shift PWM Output (Edge-Aligned)
12.4.9 Double Switching PWM Output
By using the AND function in Figure 12-63 in complementary center-aligned mode, the PWM output can be configured for double switching operation (Figure 12-65, Figure 12-66). By setting the non-inverted value register greater or equal to the PWM modulus the output function can be switched to single pulse generation on PWM reload cycle basis. Up Counter Modulus = 9 PMFVAL0 = 3; CINV0 =1 PMFVAL0 = 6; CINV0 =1 PMFVAL1 = 6; CINV1 =0 PMFVAL1 = 3; CINV1 =0 PWM0 (PINVA=0) PWM0 (PINVA=1) 100% EDGEA=1 PECA=1
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12.4.10 Output Polarity
Output polarity of the PWMs is determined by two options: TOPNEG and BOTNEG. The top polarity option, TOPNEG , controls the polarity of PWM0, PWM2, and PWM4. The bottom polarity option, BOTNEG , controls the polarity of PWM1, PWM3, and PWM5. Positive polarity means when the PWM is an active level its output is high. Conversely, negative polarity means when the PWM is driving an active level its output is low. If TOPNEG is set, PWM0, PWM2, and PWM4 outputs become active-low. When BOTNEG is set, PWM1, PWM3, and PWM5 outputs are active-low. When these bits are clear, their respective PWM outputs are active-high. See Figure 12-67. Figure 12-67. PWM Polarity
12.4.11 Software Output Control
Setting output control enable bit, OUTCTLn, enables software to drive the PWM outputs instead of the PWM generator. In independent mode, with OUTCTLn = 1, the output bit OUTn, controls the PWMn channel. In complementary channel operation the even OUTCTLn bit is used to enable software output control for the pair. The OUTCTLn bits must be switched in pairs for proper operation. The OUTCTLn and OUTn bits are in the PWM output control register. NOTE During software output control, TOPNEG and BOTNEG still control output polarity. It will take up to 3 core clock cycles to see the effect of output control on the PWM outputs. UP/DOWN COUNTERER PWM = 0 PWM = 1 PWM = 2 PWM = 3 PWM = 4 EDGE-ALIGNED MODULUS = 4 UP/DOWN COUNTERER PWM = 0 PWM = 1 PWM = 2 PWM = 3 PWM = 4 MODULUS = 4 UP COUNTERER PWM = 0 PWM = 2 PWM = 3 PWM = 4 PWM = 1 MODULUS = 4 CENTER-ALIGNED POSITIVE POLARITY POSITIVE POLARITY UP COUNTERER PWM = 0 PWM = 2 PWM = 3 PWM = 4 PWM = 1 MODULUS = 4 CENTER-ALIGNED NEGATIVE POLARITY EDGE-ALIGNED NEGATIVE POLARITY
Chapter 12 Pulse Width Modulator with Fault Protection (PMF15B6CV4) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 445 In independent PWM operation, setting or clearing the OUTn bit activates or deactivates the PWMn output. In complementary channel operation, the even-numbered OUTn bits replace the PWM generator outputs as inputs to the deadtime generators. Complementary channel pairs still cannot drive active level simultaneously, and the deadtime generators continue to insert deadtime in both channels of that pair, whenever an even OUTn bit toggles. Even OUTn bits control the top PWM signals while the odd OUT bits control the bottom PWM signals with respect to the even OUTn bits. Setting the odd OUTn bit makes its corresponding PWM the complement of its even pair, while clearing the odd OUTn bit deactivates the odd PWM. Setting the OUTCTLn bits does not disable the PWM generators and current status sensing circuitry. They continue to run, but no longer control the outputs. When the OUTCTLn bits are cleared, the outputs of the PWM generator become the inputs to the deadtime generators at the beginning of the next PWM cycle. Software can drive the PWM outputs even when PWM enable bit (PWMENx) is set to zero. NOTE Avoid an unexpected deadtime insertion by clearing the OUTn bits before setting and after clearing the OUTCTLn bits. Figure 12-68. Setting OUT0 with OUTCTL Set in Complementary Mode MODULUS = 4 PWM VALUE = 2 DEADTIME = 2 PWM0 PWM1 PWM0 WITH DEADTIME PWM1 WITH DEADTIME OUTCTL0 OUT0 PWM0 PWM1 OUT1
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Figure 12-69. Clearing OUT0 with OUTCTL Set in Complementary Mode Figure 12-70. Setting OUTCTL with OUT0 Set in Complementary Mode MODULUS = 4 PWM VALUE = 2 DEADTIME = 2 PWM0 PWM1 PWM0 WITH DEADTIME PWM1 WITH DEADTIME OUTCTL0 OUT0 PWM0 PWM1 OUT1 MODULUS = 4 PWM VALUE = 2 DEADTIME = 2 PWM0 PWM1 PWM0 WITH DEADTIME PWM1 WITH DEADTIME OUTCTL0 OUT0 PWM0 PWM1 OUT1
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12.4.12 PWM Generator Loading
12.4.12.1 Load Enable
The load okay bit, LDOK, enables loading the PWM generator with:
- A prescaler divisor—from the PRSC bits in PMFFQC register
- A PWM period—from the PWM counter modulus registers
- A PWM pulse width—from the PWM value registers LDOK prevents reloading of these PWM parameters before software is finished calculating them. Setting LDOK allows the prescaler bits, PMFMOD and PMFV AL registers to be loaded into a set of buffers. The loaded buffers are used by the PWM generator at the beginning of the next PWM reload cycle. Set LDOK by reading it when it is a logic zero and then writing a logic one to it. After the PWM reload event, LDOK is automatically cleared. If LDOK is set in the same cycle as the PWM reload event occurs, then the current buffers will be used and the LDOK is valid at the next PWM reload event. See Figure 12-71. If an asserted LDOK bit is attempted to be set again one cycle prior to the PWM reload event, then the buffers will loaded and LDOK will be cleared automatically. Else if the write access to the set LDOK bit occurs in the same cycle with the reload event, the buffers will also be loaded but the LDOK remains valid also for the next PWM reload event. See Figure 12-72. Figure 12-71. Setting cleared LDOK bit at PWM reload event bus clock LDOK write LDOK bit PWM reload bus clock LDOK write LDOK bit PWM reload
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Figure 12-72. Setting asserted LDOK bit at PWM reload event
12.4.12.2 Global Load Enable
If a global load enable bit GLDOKA, B, or C is set, the global load OK bit defined on device level as input to the PMF replaces the function of the related local LDOKA, B, or C bits. The global load OK signal is typically shared between multiple IP blocks with the same double buffer scheme. Software handling must be transferred to the global load OK bit at the chip level.
12.4.12.3 Load Frequency
The LDFQ3, LDFQ2, LDFQ1, and LDFQ0 bits in the PWM control register (PMFFQCx) select an integral loading frequency of 1 to 16-PWM reload opportunities. The LDFQ bits take effect at every PWM reload opportunity, regardless the state of the related load okay bit or global load OK. The half bit in the PMFFQC register controls half-cycle reloads for center-aligned PWMs. If the half bit is set, a reload opportunity occurs at the beginning of every PWM cycle and half cycle when the count equals the modulus. If the half bit is not set, a reload opportunity occurs only at the beginning of every cycle. Reload opportunities can only occur at the beginning of a PWM cycle in edge-aligned mode. NOTE Setting the half bit takes effect immediately. Depending on whether the counter is incrementing or decrementing at this point in time, reloads at even-numbered reload frequencies (every 2, 4, 6,... reload opportunities) will occur only when the counter matches the modulus or only when the counter equals zero, respectively (refer to example of reloading at every two opportunities in Figure 12-74). NOTE Loading a new modulus on a half cycle will force the count to the new modulus value minus one on the next clock cycle. Half cycle reloads are possible only in center-aligned mode. Enabling or disabling half-cycle reloads in edge-aligned mode will have no effect on the reload rate. bus clock LDOK write LDOK bit PWM reload bus clock LDOK write LDOK bit PWM reload
Chapter 12 Pulse Width Modulator with Fault Protection (PMF15B6CV4) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 449 Figure 12-73. Full Cycle Reload Frequency Change Figure 12-74. Half Cycle Reload Frequency Change
12.4.12.4 Reload Flag
The PWMRF reload flag is set at every reload opportunity, regardless of whether an actual reload occurs (as determined by the related LDOK bit or global load OK). If the PWM reload interrupt enable bit PWMRIE is set, the PWMRF flag generates CPU interrupt requests allowing software to calculate new PWM parameters in real time. When PWMRIE is not set, reloads still occur at the selected reload rate without generating CPU interrupt requests. Figure 12-75. PWMRF Reload Interrupt Request Figure 12-76. Full-Cycle Center-Aligned PWM Value Loading RELOAD CHANGE UP/DOWN EVERY TWO OPPORTUNITIES EVERY OPPORTUNITY COUNTERER RELOAD FREQUENCY EVERY FOUR OPPORTUNITIES RELOAD CHANGE UP/DOWN EVERY TWO OPPORTUNITIES EVERY OPPORTUNITY COUNTERER RELOAD FREQUENCY EVERY TWO OPPORTUNITIES EVERY FOUR OPPORTUNITIES (HALF bit set while counting down) (HALF bit set while counting up) (HALF bit set while counting up) (other case not shown) VDD CPU INTERRUPT PWM RELOAD REQUEST DQ CLK CLR READ PWMRF AS 1 THEN WRITE 1 TO PWMRF RESET PWMRF PWMRIE PWM HALF = 0, LDFQ[3:0] = 0000 = RELOAD EVERY CYCLE LDOK = 1 MODULUS = 3 PWM VALUE = 1 PWMRF = 1 UP/DOWN COUNTERER
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Figure 12-77. Full-Cycle Center-Aligned Modulus Loading Figure 12-78. Half-Cycle Center-Aligned PWM Value Loading Figure 12-79. Half-Cycle Center-Aligned Modulus Loading UP/DOWN PWM HALF = 0, LDFQ[3:0] = 0000 = RELOAD EVERY CYCLE LDOK = 1 MODULUS = 2 PWM VALUE = 1 PWMRF = 1 COUNTERER PWM HALF = 1, LDFQ[3:0] = 0000 = RELOAD EVERY HALF-CYCLE LDOK = 1 MODULUS = 3 PWM VALUE = 1 PWMRF = 1 UP/DOWN COUNTERER UP/DOWN PWM HALF = 1, LDFQ[3:0] = 0000 = RELOAD EVERY HALF-CYCLE LDOK = 1 MODULUS = 2 PWM VALUE = 1 PWMRF = 1 COUNTERER
Chapter 12 Pulse Width Modulator with Fault Protection (PMF15B6CV4) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 451 Figure 12-80. Edge-Aligned PWM Value Loading Figure 12-81. Edge-Aligned Modulus Loading
12.4.12.5 Reload Overrun Flag
If a LDOK bit was not set before the PWM reload event, then the related reload overrun error flag is set (PMFROIFx). If the PWM reload overrun interrupt enable bit PMFROIEx is set, the PMFROIFx flag generates a CPU interrupt request allowing software to handle the error condition. Figure 12-82. PMFROIF Reload Overrun Interrupt Request UP ONLY PWM LDFQ[3:0] = 0000 = RELOAD EVERY CYCLE COUNTERER LDOK = 1 MODULUS = 3 PWM VALUE = 1 PWMRF = 1 UP ONLY PWM LDFQ[3:0] = 0000 = RELOAD EVERY CYCLE LDOK = 1 MODULUS = 3 PWM VALUE = 2 PWMRF = 1 COUNTERER VDD CPU INTERRUPT PWM RELOAD REQUEST DQ CLK CLR WRITE 1 TO PMFROIF RESET PMFROIF PMFROIE
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12.4.12.6 Synchronizati on Output (pmf_reload)
The PMF uses reload events to output a synchronization pulse, which can be used as an input to the timer module. A high-true pulse occurs for each PWM cycle start of the PWM, regardless of the state of the related LDOK bit or global load OK and load frequency.
12.4.13 Fault Protection
Fault protection can disable any combination of PWM outputs (for all FAULT0-5 inputs) or switch to output control register PMFOUTF on a fault event (for FAULT4-5 only). Faults are generated by an active level1 on any of the FAULT inputs. Each FAULT input can be mapped arbitrarily to any of the PWM outputs. In complementary mode, if a FAULT4 or FAULT5 event is programmed to switch to output control on a fault event resulting in a PWM active state on a particular output, then the transition will take place after deadtime insertion. Thus an asynchronous path to disable the PWM output is not available. On a fault event the PWM generator continues to run. The fault decoder affects the PWM outputs selected by the fault logic and the disable mapping register. The fault protection is enabled even when the PWM is not enabled; therefore, a fault will be latched in and will be cleared in order to prevent an interrupt when the PWM is enabled.
12.4.13.1 Fault Input Sample Filter
Each fault input has a sample filter to test for fault conditions. After every bus cycle setting the FAULTm input at logic zero, the filter synchronously samples the input once every four bus cycles. QSMP determines the number of consecutive samples that must be logic one for a fault to be detected. When a fault is detected, the corresponding FAULTm flag, FIFm, is set. FIFm can only be cleared by writing a logic one to it. If the FIEm, FAULTm interrupt enable bit is set, the FIFm flag generates a CPU interrupt request. The interrupt request latch remains set until:
- Software clears the FIF m flag by writing a logic one to it
- Software clears the FIE m bit by writing a logic zero to it
- A reset occurs
12.4.13.2 Automatic Fault Recovery
Setting a fault mode bit, FMODm, configures faults from the FAULTm input for automatically reenabling the PWM outputs. When FMODm is set, disabled PWM outputs are enabled when the FAULTm input returns to logic zero and a new PWM half cycle begins. See Figure 12-83. Clearing the FIFm flag does not affect disabled PWM outputs when FMODm is set. 1. The active input level may be defined or programmable at SoC level. The default for internally connected resources is active- high. For availability and configurability of fault inputs on pins refer to the device overview section.
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12.4.13.3 Manual Fault Recovery
Clearing a fault mode bit, FMODm, configures faults from the FAULTm input for manually reenabling the PWM outputs:
- PWM outputs disabled by the FAULT0 input or the FAULT2 input are enabled by clearing the corresponding FIFm flag. The time at which the PWM outputs are enabled depends on the corresponding QSMP bit setting. If QSMPm = 00, the PWM outputs are enabled on the next IP bus cycle when the logic level detected by the filter at the fault input is logic zero. If QSMPm = 01,10 or 11, the PWMs are enabled when the next PWM half cycle begins regardless of the state of the logic level detected by the filter at the fault. See Figure 12-84 and Figure 12-85.
- PWM outputs disabled by the FAULT1 or FAULT3-5 inputs are enabled when — Software clears the corresponding FIF m flag — The filter detects a logic zero on the fault i nput at the start of the next PWM half cycle boundary. See Figure 12-86. Figure 12-84. Manual Fault Recovery (Faults 0 and 2) — QSMP = 00 PWMS ENABLED PWMS DISABLED PWMS ENABLED FAULT INPUT DISABLEDENABLED PWMS ENABLED FAULT0 OR FAULT2 PWMS ENABLED PWMS DISABLED FIFm CLEARED
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Figure 12-85. Manual Fault Recovery (Faults 0 and 2) — QSMP = 01, 10, or 11 Figure 12-86. Manual Fault Recovery (Faults 1 and 3-5) NOTE PWM half-cycle boundaries occur at both the PWM cycle start and when the counter equals the modulus, so in edge-aligned operation full-cycles and half-cycles are equal. NOTE Fault protection also applies during software output control when the OUTCTLn bits are set. Fault recovery still occurs at half PWM cycle boundaries while the PWM generator is engaged, PWMEN equals one. But the OUTn bits can control the PWM outputs while the PWM generator is off, PWMEN equals zero. Thus, fault recovery occurs at IPbus cycles while the PWM generator is off and at the start of PWM cycles when the generator is engaged.
12.5 Resets
All PMF registers are reset to their default values upon any system reset.
12.6 Clocks
The gated system core clock is the clock source for all PWM generators. The system clock is used as a clock source for any other logic in this module. The system bus clock is used as clock for specific control registers and flags (LDOKx, PWMRFx, PMFOUTB). PWMS ENABLED FAULT0 OR FAULT2 PWMS ENABLED PWMS DISABLED FIFm CLEARED PWMS ENABLED FAULT1 OR FAULT3 PWMS ENABLED PWMS DISABLED FIFm CLEARED
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12.7 Interrupts
This section describes the interrupts generated by the PMF and their individual sources. Vector addresses and interrupt priorities are defined at SoC-level.
12.8 Initialization and Application Information
12.8.1 Initialization
Initialize all registers; read, then set the related LDOK bit or global load OK before setting the PWMEN bit. With LDOK set, setting PWMEN for the first time after reset immediately loads the PWM generator thereby setting the PWMRF flag. PWMRF generates a CPU interrupt request if the PWMRIE bit is set. In complementary channel operation with current-status correction selected, PWM value registers one, three, and five control the outputs for the first PWM cycle. NOTE Even if LDOK is not set, setting PWMEN also sets the PWMRF flag. To prevent a CPU interrupt request, clear the PWMRIE bit before setting PWMEN. Setting PWMEN for the first time after reset without first setting LDOK loads a prescaler divisor of one, a PWM value of 0x0000, and an unknown modulus. The PWM generator uses the last values loaded if PWMEN is cleared and then set while LDOK equals zero. Initializing the deadtime register, after setting PWMEN or OUTCTLn, can cause an improper deadtime insertion. However, the deadtime can never be shorter than the specified value. Table 12-45. PMF Interrupt Sources Module Interrupt Sources (Interrupt Vector) Associated Flags Local Enable PMF reload A PWMRFA PMFENCA[PWMRIEA] PMF reload B(1) 1. If MTG=0: Interrupt mirrors PMF reload A interrupt PWMRFB PMFENCB[PWMRIEB] PMF reload C1 PWMRFC PMFENCC[PWMRIEC] PMF fault PMFFIF[FIF0] PMFFIF[FIF1] PMFFIF[FIF2] PMFFIF[FIF3] PMFFIE[FIE0] PMFFIE[FIE1] PMFFIE[FIE2] PMFFIE[FIE3] PMF reload overrun PMFROIF[PMFROIFA] PMFROIF[PMFROIFB] PMFROIF[PMFROIFC] PMFROIE[PMFROIEA] PMFROIE[PMFROIEB] PMFROIE[PMFROIEC]
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Figure 12-87. PWMEN and PWM Outputs in Independent Operation Figure 12-88. PWMEN and PWM Outputs in Complementary Operation When the PWMEN bit is cleared:
- The PWM n outputs lose priority on associated outputs unless OUTCTLn = 1
- The PWM counter is cl eared and does not count
- The PWM generator for ces its outputs to zero
- The PWMRF flag and pending CPU interrupt requests are not cleared
- All fault circuitry re mains active unless FENm = 0
- Software output control remains active
- Deadtime insertion continues during software output control
12.8.1.1 Register Write Protection
The following configuration registers and bits can be write protected: PMFCFG0, PMFCFG1, PMFCFG3, PMFFEN, PMFQSMP0-1, PMFENCA[RSTRTA,GLDOKA], PMFENCB[RSTRTB,GLDOKB], PMFENCC[RSTRTC,GLDOKC], PMFDTMA,B,C, PMFDMP0-5, PMFOUTF NOTE Make sure to set the write protection bit WP in PMFCFG0 after configuring and prior to enabling PWM outputs and fault inputs.
12.8.2 BLDC 6-Step Commutation
12.8.2.1 Unipolar Switching Mode
Unipolar switching mode uses registers PMFOUTC and PMFOUTB to perform commutation. HI-Z ACTIVE HI-Z IPBus PWMEN PWM CLOCK BIT OUTPUTS HI-Z ACTIVE IPBus PWMEN PWM CLOCK BIT OUTPUTS HI-Z
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12.8.2.2 Bipolar Switching Mode
Bipolar switching mode uses register bits MSK5-0 and PINV A, B, C to perform commutation. The recommended setup is: PMFCFG0[INDEPC,INDEPB,INDEPA] = 0x0; // Complementary mode PMFCFG1[ENCE] = 1; // Enable commutation event PMFCFG2[MSK5:MSK0] = 0x30; // Branch A<->B, mask C // 0° PMFCFG3[PINVC,PINVB,PINVA] = 0x2; // Invert B The commutation sequence is: PMFCFG2[MSK5:MSK0] = 0x03; // Branch C<->B, mask A // 60° PMFCFG3[PINVC,PINVB,PINVA] = 0x2; // Invert B PMFCFG2[MSK5:MSK0] = 0x0c; // Branch C<->A, mask B // 120° OUTCTL (odd,even) OUT (odd,even) PWM (odd) PWM (even) 00 xx PWMgen(even) PWMgen(even) 11 10 OUTB(even) =1 OUTB(even)=0 01 x0 0 OUTB(even)=0 Branch Channel 0 ° 60° 120° 180° 240° 300° A P W M 0 P W M g e n 000 PWM1 PWMgen 0 1 0 BP W M 2 0 0 P W M g e n 0 0 PWM3 1 0 PWMgen 0 1 C P W M 4 000 P W M g e n PWM5 0 1 0 PWMgen
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PMFCFG3[PINVC,PINVB,PINVA] = 0x1; // Invert A PMFCFG2[MSK5:MSK0] = 0x30; // Branch B<->A, mask C // 180° PMFCFG3[PINVC,PINVB,PINVA] = 0x1; // Invert A PMFCFG2[MSK5:MSK0] = 0x03; // Branch B<->C, mask A // 240° PMFCFG3[PINVC,PINVB,PINVA] = 0x4; // Invert C PMFCFG2[MSK5:MSK0] = 0x0c; // Branch A<->C, mask B // 300° PMFCFG3[PINVC,PINVB,PINVA] = 0x4; // Invert C PMFCFG2[MSK5:MSK0] = 0x30; // Branch A<->B, mask A // 360° PMFCFG3[PINVC,PINVB,PINVA] = 0x2; // Invert B Table 12-48. Bipolar Switching Sequence Branch Channel 0 ° 60° 120° 180° 240° 300° A PWM0 PWMgen Masked PWMgen Masked PWMgen PWM1 PWMgen Masked PWMgen Masked PWMgen B PWM2 PWMgen Masked PWMgen Masked PWM3 PWMgen Masked PWMgen Masked C PWM4 Masked PWMgen Masked PWMgen PWM5 Masked PWMgen Masked PWMgen
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13.1 Introduction
In PWM driven systems it is important to schedule the acquisition of the state variables with respect to PWM cycle. The Programmable Trigger Unit (PTU) is intended to completely avoid CPU involvement in the time acquisitions of state variables during the control cycle that can be half, full, multiple PWM cycles. All acquisition time values are stored inside the global memory map, basically inside the system memory; see the MMC section for the supported memory area. In such cases the pre-setting of the acquisition times needs to be completed during the previous control cycle to where the actual acquisitions are to be made.
13.1.1 Features
The PTU module includes these distinctive features:
- One 16 bit counter as time base for all trigger events
- One trigger generator(TG0)
- Up to 32 trigger events per trigger generator
- Global Load OK support, to guarantee c oherent update of all control loop modules
- Trigger values stored inside the global me mory map, basically inside system memory
- Software generated reload event a nd Trigger event generation for debugging
13.1.2 Modes of Operation
The PTU module behaves as follows in the system power modes: 1. Run mode All PTU features are available. Table 13-1. Revision History Table Rev. No. (Item No.) Data Sections Affected Substantial Change(s) 3.0 16. Jul. 2013 - removed second TG Table 13-2. Terminology Term Meaning TG Trigger Generator EOL End of trigger list
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- Wait mode All PTU features are available. 3. Freeze Mode Depends on the PTUFRZ register bit setting the internal counter is stopped and no trigger events will be generated. 4. Stop mode The PTU is disabled and the internal counter is stopped; no trigger events will be generated. The content of the configuration register is unchanged.
13.1.3 Block Diagram
Figure 13-1 shows a block diagram of the PTU module. Figure 13-1. PTU Block Block Diagram
13.2 External Signal Description
This section lists the name and description of all external ports.
13.2.1 PTUT0 — PTU Trigger 0
If enabled (PTUT0PE is set) this pin shows the internal trigger_0 event. Trigger Generator (TG) Time BaseBus Clock Global Memory Map PTU PTURE PTUT0 Trigger 1 Trigger 2 ... Trigger n Counter Control Logicreload reload_is_async Module ptu_reload_is_async ptu_reload trigger_0 glb_ldok
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13.2.2 PTURE — PTUE Reload Event
If enabled (PTUREPE is set) this pin shows the internal reload event.
13.3 Memory Map and Register Definition
This section provides the detailed information of all registers for the PTU module.
13.3.1 Register Summary
Figure 13-2 shows the summary of all implemented registers inside the PTU module. NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level. Address Offset Register Name B i t 7 654321 B i t 0 0x0000 PTUE PTUFRZ 00000 TG0ENW 0x0001 PTUC R 0000000 PTULDOKW 0x0002 PTUIEH R 0000000 PTUROIEW 0x0003 PTUIEL R 0000 TG0AEIE TG0REIE TG0TEIE TG0DIEW 0x0004 PTUIFH R 000000 PTUDEEF PTUROIFW 0x0005 PTUIFL R 0000 TG0AEIF TG0REIF TG0TEIF TG0DIFW 0x0006 TG0LIST R 0000000 T G 0 L I S T W 0x0007 TG0TNUM R 0 0 0 TG0TNUM[4:0] W 0x0008 TG0TVH R TG0TV[15:8] W = Unimplemented Figure 13-2. PTU Register Summary
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13.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Unused bits read back zero. 0x0009 TG0TVL R TG0TV[7:0] W 0x000A - 0x000D Reserved R 00000000 W 0x000E PTUCNTH R PTUCNT[15:8] W 0x000F PTUCNTL R PTUCNT[7:0] W 0x0010 Reserved R 00000000 W 0x0011 PTUPTRH R PTUPTR[23:16] W 0x0012 PTUPTRM R PTUPTR[15:8] W 0x0013 PTUPTRL R PTUPTR[7:1] W 0x0014 TG0L0IDX R 0 TG0L10DX[6:0] W 0x0015 TG0L1IDX TG0L1IDX[6:0]W 0x0016 - 0x001E Reserved R 00000000 W 0x001F PTUDEBUG PTUREPE
0 PTUT0P
E 0000 W PTUFRE TG0FTE Address Offset Register Name B i t 7 654321 B i t 0 = Unimplemented Figure 13-2. PTU Register Summary
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13.3.2.1 PTU Module Enable Register (PTUE)
13.3.2.2 PTU Module Control Register (PTUC)
Module Base + 0x0000 Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 PTUFRZ 00000 TG0EN W Reset 00000000 = Unimplemented Figure 13-3. PTU Module Enable Register (PTUE) Table 13-3. PTUE Register Field Description Field Description PTUFRZ PTU Stop in Freeze Mode — In freeze mode, there is an option to disable the input clock to the PTU time base counter. If this bit is set, whenever the MCU is in freeze mode, the input clock to the time base counter is disabled. In this way, the counters can be stopped while in freeze mode so that once normal program flow is continued, the counter is re-enabled.
0 Allow time base counter to continue while in freeze mode
1 Disable time base counter clock whenever the part is in freeze mode
Trigger Generator 0 Enable — This bit enables trigger generator 0.
0 Trigger generator 0 is disabled
1 Trigger generator 0 is enabled
Module Base + 0x0001 Access: User read/write (1) 1. Read: Anytime Write: write 1 anytime, write 0 if TG0EN is cleared 76543210 R 0000000 PTULDOK W R e s e t 00000000 = Unimplemented Figure 13-4. PTU Module Control Register (PTUC) Table 13-4. PTUC Register Field Descriptions Field Description PTULDOK Load Okay — When this bit is set by the software, this allows the trigger generator to switch to the alternative list and load the trigger time values at the next reload event from the new list. If the reload event occurs when the PTULDOK bit is not set then the trigger generator generates a reload overrun event and uses the previously used list. At the next reload event this bit is cleared by control logic. Write 0 is only possible if TG0EN is cleared. The PTULDOK can be used by other module as global load OK (glb_ldok).
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13.3.2.3 PTU Interrupt Enable Register High (PTUIEH)
13.3.2.4 PTU Interrupt Enable Register Low (PTUIEL)
Module Base + 0x0002 Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R 0000000 PTUROIE W Reset 00000000 = Unimplemented Figure 13-5. PTU Interrupt Enable Register High (PTUIEH) Table 13-5. PTUIEH Register Field Descriptions Field Description PTUROIE PTU Reload Overrun Interrupt Enable — Enables PTU reload overrun interrupt.
0 No interrupt will be requested whenever PTUROIF is set
1 Interrupt will be requested whenever PTUROIF is set
Module Base + 0x0003 Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R 0000 TG0AEIE TG0REIE TG0TEIE TG0DIE W Reset 00000000 = Unimplemented Figure 13-6. PTU Interrupt Enable Register Low (PTUIEL) Table 13-6. PTUIEL Register Field Descriptions Field Description TG0AEIE Trigger Generator 0 Memory Access Error Interrupt Enable — Enables trigger generator memory access error interrupt.
0 No interrupt will be requested whenever TG0AEIF is set
1 Interrupt will be requested whenever TG0AEIF is set
Trigger Generator 0 Reload Error Interrupt Enable — Enables trigger generator reload error interrupt.
0 No interrupt will be requested whenever TG0REIF is set
1 Interrupt will be requested whenever TG0REIF is set
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0 No interrupt will be requested whenever TG0TEIF is set
1 Interrupt will be requested whenever TG0TEIF is set
Trigger Generator 0 Done Interrupt Enable — Enables trigger generator done interrupt.
0 No interrupt will be requested whenever TG0DIF is set
1 Interrupt will be requested whenever TG0DIF is set
Table 13-6. PTUIEL Register Field Descriptions Field Description
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13.3.2.5 PTU Interrupt Flag Register High (PTUIFH)
13.3.2.6 PTU Interrupt Flag Register Low (PTUIFL)
Module Base + 0x0004 Access: User read/write (1) 1. Read: Anytime Write: Anytime, write 1 to clear 76543210 R 000000 PTUDEEF PTUROIF W Reset 00000000 = Unimplemented Figure 13-7. PTU Interrupt Flag Register High (PTUIFH) Table 13-7. PTUIFH Register Field Descriptions Field Description PTUDEEF PTU Double bit ECC Error Flag — This bit is set if the read data from the memory contains double bit ECC errors. While this bit is set the trigger generation of both trigger generators stops.
0 No double bit ECC error occurs
1 Double bit ECC error occurs
PTU Reload Overrun Interrupt Flag — If reload event o ccurs when the PTULDOK bit is not set then this bit will be set. This bit is not set if the reload event was forced by an asynchronous commutation event.
0 No reload overrun occurs
1 Reload overrun occurs
Module Base + 0x0005 Access: User read/write (1) 1. Read: Anytime Write: Anytime, write 1 to clear 76543210 R 0000 TG0AEIF TG0REIF TG0EIF TG0DIF W Reset 00000000 = Unimplemented Figure 13-8. PTU Interrupt Flag Register Low (PTUIFL)
Chapter 13 Programmable Trigger Unit (PTUV3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 467 Table 13-8. PTUIFL Register Field Descriptions Field Description TG0AEIF Trigger Generator 0 Memory Access Error Interrupt Flag — This bit is set if trigger generator 0 uses a read address outside the memory address range, see the MMC section for the supported memory area.
0 No trigger generator 0 memory access error occurred
1 Trigger generator 0 memory access error occurred
Trigger Generator 0 Reload Error Interrupt Flag — This bi t is set if a new reload event occurs when the trigger generator has neither reached the end of list symbol nor the maximum possible triggers. This bit is not set if the reload event was forced by an asynchronous commutation event.
0 No trigger generator 0 reload error occurs
1 Trigger generator 0 reload error occurs
Trigger Generator 0 Timing Error Interrupt Flag — This bit is set if the trigger generator receives a time value which is below the current counter value.
0 No trigger generator 0 error occurs
1 Trigger generator 0 error occurs
Trigger Generator 0 Done Interrupt Flag —This bit is set if the trigger generator receives the end of list symbol or the maximum number of generated trigger events was reached.
0 Trigger generator 0 is running
1 Trigger generator 0 is done
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13.3.2.7 Trigger Generator 0 List Register (TG0LIST)
13.3.2.8 Trigger Generator 0 Trigger Number Register (TG0TNUM)
Module Base + 0x0006 Access: User read/write (1) 1. Read: Anytime Write: Anytime, if TG0EN bit is cleared 76543210 R 0000000 T G 0 L I S T W Reset 00000000 = Unimplemented Figure 13-9. Trigger Generator 0 List Register (TG0LIST) Table 13-9. TG0LIST Register Field Descriptions Field Description TG0LIST Trigger Generator 0 List — This bit shows the number of the current used list.
0 Trigger generator 0 is using list 0
1 Trigger generator 0 is using list 1
Module Base + 0x0007 Access: User read only (1) 1. Read: Anytime Write: Never 76543210 R 0 0 0 TG0TNUM[4:0] W Reset 00000000 = Unimplemented Figure 13-10. Trigger Generator 0 Trigger Number Register (TG0TNUM) Table 13-10. TG0TNUM Register Field Descriptions Field Description 4:0 TG0TNUM[4:0] Trigger Generator 0 Trigger Number — This register shows the number of generated triggers since the last reload event. After the generation of 32 triggers this register shows zero. The next reload event clears this register. See also Figure 13-17.
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13.3.2.9 Trigger Generator 0 Trigger Value (TG0TVH, TG0TVL)
Module Base + 0x0008 Access: User read only (1) 1. Read: Anytime Write: Never 76543210 RT G 0 T V [ 1 5 : 8 ] W Reset 00000000 Module Base + 0x0009 Access: User read only 76543210 R TG0TV[7:0] W Reset 00000000 = Unimplemented Figure 13-11. Trigger Generator 0 Trigger Value Register (TG0TVH, TG0TVL) Table 13-11. TG0TV Register Field Descriptions Field Description TG0TV[15:0] Trigger Generator 0 Trigger Value — This register contains the trigger value to generate the next trigger. If the time base counter reach this value the next trigger event is generated. If the trigger generator reached the end of list (EOL) symbol then this value is visible inside this register. If the last generated trigger was trigger number 32 then the last used trigger value is visible inside this register. See also Figure 13-17.
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13.3.2.10 PTU Counter Register (PTUCNTH, PTUCNTL)
Module Base + 0x000E Access: User read only (1) 1. Read: Anytime Write: Never 76543210 R PTUCNT[15:8] W R e s e t 00000000 Module Base + 0x000F Access: User read only 76543210 R PTUCNT[7:0] W Reset 00000000 = Unimplemented Figure 13-12. PTU Counter Register (PTUCNTH, PTUCNTL) Table 13-12. PTUCNT Register Field Descriptions Field Description PTUCNT[15:0] PTU Time Base Counter value — Th is register contains the current status of the internal time base counter. If both TG are done with the execution of the trigger list then the counter also stops. The counter is restarted by the next reload event.
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13.3.2.11 PTU Pointer Register (PTUPTRH, PTUPTRM, PTUPTRL)
Module Base + 0x0011 Access: User read/write (1) 1. Read: Anytime Write: Anytime, if TG0En bit are cleared 76543210 R PTUPTR[23:16] W Reset 00000000 Module Base + 0x0012 Access: User read/write 76543210 R PTUPTR[15:8] W Reset 00000000 Module Base + 0x0013 Access: User read/write 76543210 R PTUPTR[7:1] W Reset 00000000 = Unimplemented Figure 13-13. PTU List Add Register (PTUPTRH, PTUPTRM, PTUPTRL) Table 13-13. PTUPTR Register Field Descriptions Field Description PTUPTR [23:0] PTU Pointer — This register cannot be modified if TG0EN bi t is set. This register defines the start address of the used list area inside the global memory map. For more information see Section 13.4.2, “Memory based trigger event list”.
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13.3.2.12 Trigger Generator 0 List 0 Index (TG0L0IDX)
13.3.2.13 Trigger Generator 0 List 1 Index (TG0L1IDX)
Module Base + 0x0014 Access: User read only (1) 1. Read: Anytime Write: Never 76543210 R 0 TG0L0IDX[6:0] W Reset 00000000 = Unimplemented Figure 13-14. Trigger Generator 0 List 0 Index (TG0L0IDX) Table 13-14. TG0L0IDX Register Field Descriptions Field Description 6:0 TG0L0IDX [6:0] Trigger Generator 0 List 0 Index Register — This register defines offset of the start point for the trigger event list 0 used by trigger generator 0. This register is read only, so the list 0 for trigger generator 0 will start at the PTUPTR address. For more information see Section 13.4.2, “Memory based trigger event list”. Module Base + 0x0015 Access: User read/write (1) 1. Read: Anytime Write: Anytime, if TG0EN bit is cleared 76543210 TG0L1IDX[6:0] W R e s e t 00000000 = Unimplemented Figure 13-15. Trigger Generator 0 List 1 Index (TG0L1IDX) Table 13-15. TG0L1IDX Register Field Descriptions Field Description 6:0 TG0L1IDX [6:0] Trigger Generator 0 List 1 Index Register — This regist er cannot be modified after the TG0EN bit is set. This register defines offset of the start point for the trigger event list 1 used by trigger generator 0. For more information see Section 13.4.2, “Memory based trigger event list”.
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13.3.2.14 PTU Debug Register (PTUDEBUG)
13.4 Functional Description
13.4.1 General
The PTU module consists of one trigger generator (TG0). If the trigger generator is disabled then the PTU is disabled, the trigger generation stops and the memory accesses are disabled. The trigger generation of the PTU module is synchronized to the incoming reload event. This reload event resets and restarts the internal time base counter and makes sure that the first trigger value from the actual trigger list is loaded. Furthermore the corresponding module is informed that a new control cycle has started. If the counter value matches the current trigger value then a trigger event is generated. In this way, the reload event is delayed by the number of bus clock cycles defined by the current trigger value. After this, a new trigger value is loaded from the memory and the TG0 wait for the next match. So up to 32 trigger events per control cycle can be generated. If the trigger value is 0x0000 or 32 trigger events have been Module Base + 0x001F Access: User read/write (1) 1. Read: Anytime Write: only in special mode 76543210 PTUREPE PTUT0PE 0000 W PTUFRE TG0FTE R e s e t 00000000 = Unimplemented Figure 13-16. PTU Debug Register (PTUDEBUG) Table 13-16. PTUDEBUG Register Field Descriptions Field Description PTUREPE PTURE Pin Enable — This bit enables the output port for pin PTURE.
0 PTURE output port are disabled
1 PTURE output port are enabled
PTU PTUT0 Pin Enable — This bit enables the output port for pin PTUT0.
0 PTUT0 output port are disabled
1 PTUT0 output port are enabled
Force Reload event generation — If one of the TGs is enabled then writing 1 to this bit will generate a reload event. The reload event forced by PTUFRE does not set the PTUROIF interrupt flag. Also the ptu_reload signal asserts for one bus clock cyclet. Writing 0 to this bit has no effect. Always reads back as 0. This behavior is not available during stop or freeze mode. TG0FTE Trigger Generator 0 Force Trigger Event — If TG0 is enabled then writing 1 to this bit will generate a trigger event independent on the list based trigger generation. Writing 0 to this bit has no effect. Always reads back as 0. This behavior is not available during stop or freeze mode.
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generated during this control cycle, the TG0DIF bit is set and the TG0 waits for the next reload event. Figure 13-17 shows an example of the trigger generation. Figure 13-17. TG0 trigger generation example NOTE If the trigger list contains less than 32 trigger values a delay between the generation of the last trigger and the assertion of the done interrupt flag will be visible. During this time the PTU loads the next trigger value from the memory to evaluate the EOL symbol.
13.4.2 Memory based trigger event list
The lists with the trigger values are located inside the global memory map. The location of the trigger lists in the memory map is configured with registers PTUPTR and TG0LxIDX. If the TG0 is enabled then the associated TG0LxIDX and PTUPTR registers are locked. The trigger values inside the trigger list are 16 bit values. Each 16 bit value defines the delay between the reload event and the trigger event in bus clock cycles. A delay value of 0x0000 will be interpreted as End t Delay T0 Delay T1 Delay T2 Control Cycle PTUCNT TG0LIST TG0TNUM 0 1 2 3 0 T0 T1 T2 0x0000 TG0DIF outgoing trigger events TG0TV reload event reload event
Chapter 13 Programmable Trigger Unit (PTUV3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 475 Of trigger List (EOL) symbol. The list must be sorted in ascending order. If a subsequent value is smaller than the previous value or the loaded trigger value is smaller than the current counter value then the TG0TEIF error indication is generated and the trigger generation of this list is stopped until the next reload event. For more information about these error scenario see Section 13.4.5.5, “Trigger Generator Timing Error”. The module is not able to access memory area outside the 256 byte window starting at the memory address defined by PTUPTR. Figure 13-18. Global Memory map usage
13.4.3 Reload mechanism
The trigger generator uses two lists to load the trigger values from the memory. One list can be updated by the CPU while the other list is used to generate the trigger events. After enabling, the TG0 use the lists in alternate order. When the update of alternate trigger list is done, the SW must set the PTULDOK bit. If the load OK bit is set at the time of reload event, the TG switches to the alternate list and loads the first trigger value from this trigger event list. The reload event clears the PTULDOK bit. The TG0LIST bits shows the currently use list number. This bit is writeable if TG0 is disabled. If the PTULDOK bit was not set before the reload event then the reload overrun error flag is set (PTUROIF)and TG0 do not switch to the alternative list. The current trigger list is used to load the trigger values. Figure 13-19 shows an example. The PTULDOK bit can be used by other modules as glb_ldok. To reduce the used memory size, it is also possible to set TG0L0IDX equal to TG0L1IDX. In this case the trigger generator is using only one physical list of trigger events even if the trigger generator logic is switching between both pointers. The SW must make sure, that the CPU does not update the trigger list before the execution of the trigger list is done. The time window to update the trigger list starts at the trigger generator done interrupt flag (TG0DIF) and ends with the next reload event. Even if only one Delay T0 Delay T1 Delay T2 0x0000 (EOL symbol) unused Delay T0 Delay T1 Delay T2 0x0000 (EOL symbol) unused 0x00_0000 PTUPTR + TG0L0IDX Global Memory Map PTUPTR + TG0L1IDX start address TG0 trigger event list 0 start address TG0 trigger event list 1 max accessible memory area: 256 byte
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physical trigger event list is used the TG0LIST shows a swap between list 0 and 1 at every reload event with set PTULDOK bit. Figure 13-19. TG0 Reload behavior with local PTULDOK
13.4.4 Async reload event
If the reload and reload_is_async are active at the same time then an async reload event happens. The PTU behavior on an async reload event is the same like on the reload event described in Section 13.4.3, “Reload mechanism” above. The only difference is, that during an async reload event the error interrupt flags PTUROIF and TG0REIF are not generated.
13.4.5 Interrupts and error handling
This sections describes the interrupts generated by the PTU module and their individual sources, Vector addresses and interrupt priority are defined by MCU level.
13.4.5.1 PTU Double Bit ECC Error
If the trigger generator reads trigger values from the memory which contains double bit ECC errors then the PTUDEEF is set. These read data are ignored and the execution of the trigger generator is stopped until Table 13-17. PTU Interrupt Sources Module Interrupt Sources Local Enable PTU Reload Overrun Error PTUIEH[PTUROIE] TG0 Error PTUIEL[TG0 AEIE,TG0REIE,TG0TEIE] TG0 Done PTUIEL[TG0DIE] PTULDOK TG0LIST PTUROIF set by SW switch to new list index PTULDOK bit was not stay at current list index set by CPU set reload overrun error flag TG0DIF TG0DIF reload event
Chapter 13 Programmable Trigger Unit (PTUV3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 477 the PTUDEEF flag was cleared. To make sure the trigger generator starts in a define state it is required to execute follow sequence: 1. disable the trigger generator 2. configure the PTU if required 3. clear the PTUDEEF 4. enable the trigger generator
13.4.5.2 PTU Reload Overrun Error
If the PTULDOK bit is not set during the reload event then the PTUROIF bit is set. If enabled (PTUROIE is set) an interrupt is generated. For more information see Section 13.4.3, “Reload mechanism”. During an async reload event the PTUROIF interrupt flag is not set.
13.4.5.3 Trigger Generator Memory Access Error
The trigger generator memory access error flag (TG0AEIF) is set if the used read address is outside the accessible memory address area; see the MMC section for the supported memory area. The loaded trigger values are ignored and the execution of this trigger list is stopped until the next reload event. If enabled (TG0AEIE is set) an interrupt will be generated.
13.4.5.4 Trigger Generator Reload Error
The trigger generator reload error flag (TG0REIF) is set if a new reload event occurs before the trigger generator reaches the EOL symbol or the maximum number of generated triggers. Independent from this error condition the trigger generator reloads the new data from the trigger list and starts to generate the trigger. During an async reload event the TG0REIF interrupt flag is not set. If the trigger value loaded from the memory contains double bit ECC errors (PTUDEEF flag is set) then the data are ignored and the trigger generator reload error flag (TG0REIF) is not set.
13.4.5.5 Trigger Gene rator Timing Error
The PTU module requires minimum 6 core clock cycles to reload the next trigger values from the memory. This reload time defines the minimum possible distance between two consecutive trigger values within a trigger list or the distance between the reload event and the first trigger value. The trigger generator timing error flag (TG0TEIF) is set if the loaded trigger value is smaller than the current counter value. The execution of this trigger list is stopped until the next reload event. There are different reasons for the trigger generator error condition:
- reload time exceeds time of next trigger event
- reload time exceeds the time betw een two consecutive trigger values
- a subsequent trigger value is smal ler than the predecessor trigger value If the trigger value loaded from the memory contains double bit ECC errors (PTUDEEF flag is set) then the data are ignored and the trigger generator timing error flag (TG0TEIF) is not set.
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If enabled (TG0EIE is set) an interrupt will be generated.
13.4.5.6 Trigger Generator Done
The trigger generator done flag (TG0DIF) is set if the loaded trigger value contains 0x0000 or if the number of maximum trigger events (32) was reached. Please note, that the time which is required to load the next trigger value defines the delay between the generation of the last trigger and the assertion of the done flag. If enabled (TG0DIE is set) an interrupt is generated.If the trigger value loaded from the memory contains double bit ECC errors (PTUDEEF flag is set) then the data are ignored and the trigger generator done flag (TG0DIF) is not set.
13.4.6 Debugging
To see the internal status of the trigger generator the register TG0LIST, TG0TNUM, and TG0TV can be used. The TG0LIST register shows the number of currently used list. The TG0TNUM shows the number of generated triggers since the last reload event. If the maximum number of triggers was generated then this register shows zero. The trigger value loaded from the memory to generate the next trigger event is visible inside the TG0TV register. If the execution of the trigger list is done then these registers are unchanged until the next reload event. The next PWM reload event clears the TG0TNUM register and toggles the used trigger list if PTULDOK was set. To generate a reload event or trigger event independent from the PWM status the debug register bits PTUFRE or TG0FTE can be used. A write one to this bits will generate the associated event. This behavior is not available during stop or freeze mode.
MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductor 479 Chapter 14 Serial Communication Interface (S12SCIV6)
14.1 Introduction
This block guide provides an overview of the serial communication interface (SCI) module. The SCI allows asynchronous serial communications with peripheral devices and other CPUs.
14.1.1 Glossary
IR: InfraRed IrDA: Infrared Design Associate IRQ: Interrupt Request LIN: Local Interconnect Network Table 14-1. Revision History Version Number Revision Date Effective Date Author Description of Changes 05.03 12/25/2008 remove redundancy comments in Figure1-2 05.04 08/05/2009 fix typo, SCIBDL reset value be 0x04, not 0x00 05.05 06/03/2010 fix typo, Table 14-4,SCICR1 Even parity should be PT=0 fix typo, on page 14-500,should be BKDIF,not BLDIF 06.01 05/29/2012 update register ma p, change BD,move IREN to SCIACR2 06.02 10/17/2012 fix typo on page 14-483 and on page 14-484;fix typo of version V6 update fast data tolerance calculation and add notes. 06.03 10/25/2012 fix typo Table 14-2, SBR[15:4],not SBR[15:0] 06.04 12/19/2012 fix typo Table 14-7,14.4.1/14-494 06.05 02/22/2013 fix typo Figure 14-1./14-481 Figure 14-4./14-483 06.06 03/11/2013 fix typo of BDL reset value,Figure 14-4 fix typo of Table 14-2,Table 14-17,reword 14.4.4/14-496 06.07 09/03/2013 update Figure 14-14./14-494 Figure 14-16./14-498 Figure 14-20./14-503 update 14.4.4/14-496,more detail for two baud add note for Table 14-17./14-497 update Figure 14-2./14-482,Figure 14-12./14-492
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LSB: Least Significant Bit MSB: Most Significant Bit NRZ: Non-Return-to-Zero RZI: Return-to-Zero-Inverted RXD: Receive Pin SCI : Serial Communication Interface TXD: Transmit Pin
14.1.2 Features
The SCI includes these distinctive features:
- Full-duplex or single-wire operation
- Standard mark/space non-return-to-zero (NRZ) format
- Selectable IrDA 1.4 retu rn-to-zero-inverted (RZI) format with programmable pulse widths
- 16-bit baud rate selection
- Programmable 8-bit or 9-bit data format
- Separately enabled tr ansmitter and receiver
- Programmable polarity for transmitter and receiver
- Programmable transmitter output parity
- Two receiver wakeup methods: — Idle line wakeup — Address mark wakeup
- Interrupt-driven operation with eight flags: — Transmitter empty — Transmission complete — Receiver full — Idle receiver input — Receiver overrun — Noise error — Framing error — Parity error — Receive wakeup on active edge — Transmit collision detect supporting LIN — Break Detect supporting LIN
- Receiver framing error detection
- Hardware parity checking
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- 1/16 bit-time noise detection
14.1.3 Modes of Operation
The SCI functions the same in normal, special, and emulation modes. It has two low power modes, wait and stop modes.
- Run mode
- Wait mode
- Stop mode
14.1.4 Block Diagram
Figure 14-1 is a high level block diagram of the SCI module, showing the interaction of various function blocks. Figure 14-1. SCI Block Diagram
14.2 External Signal Description
The SCI module has a total of two external pins. SCI Data Register RXD Data In Data Out TXD Receive Shift RegisterInfrared Decoder Receive & Wakeup Control Data Format Control Transmit Control Bus Clock Transmit Shift Register SCI Data Register Receive Interrupt Generation Transmit Interrupt Generation Infrared Encoder IDLE RDRF/OR TC TDRE BRKD BERR RXEDG SCI Interrupt Request Baud Rate Generator Receive Baud Rate Transmit Generator
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14.2.1 TXD — Transmit Pin
The TXD pin transmits SCI (standard or infrared) data. It will idle high in either mode and is high impedance anytime the transmitter is disabled.
14.2.2 RXD — Receive Pin
The RXD pin receives SCI (standard or infrared) data. An idle line is detected as a line high. This input is ignored when the receiver is disabled and should be terminated to a known voltage.
14.3 Memory Map and Register Definition
This section provides a detailed description of all the SCI registers.
14.3.1 Module Memory Map and Register Definition
The memory map for the SCI module is given below in Figure 14-2. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the SCI module and the address offset for each register.
14.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Writes to a reserved register locations do not have any effect and reads of these locations return a zero. Details of register bit and field function follow the register diagrams, in bit order. Register Name B i t 7 654321 B i t 0 0x0000 SCIBDH1 R SBR15 SBR14 SBR13 SBR12 SBR11 SBR10 SBR9 SBR8 W 0x0001 SCIBDL1 R SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W 0x0002 SCICR11 R LOOPS SCISWAI RSRC M WAKE ILT PE PT W 0x0000 SCIASR12 R RXEDGIF 0000 BERRV BERRIF BKDIF W = Unimplemented or Reserved Figure 14-2. SCI Register Summary (Sheet 1 of 2)
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14.3.2.1 SCI Baud Rate Re gisters (SCIBDH, SCIBDL)
Read: Anytime, if AMAP = 0. 0x0001 SCIACR12 R RXEDGIE 00000 BERRIE BKDIE W 0x0002 SCIACR22 R IREN TNP1 TNP0 BERRM1 BERRM0 BKDFE W 0x0003 SCICR2 R TIE TCIE RIE ILIE TE RE RWU SBK W 0x0004 SCISR1 R TDRE TC RDRF IDLE OR NF FE PF W 0x0005 SCISR2 R AMAP TXPOL RXPOL BRK13 TXDIR RAF W 0x0006 SCIDRH RR 8 000 Reserved Reserved Reserved W 0x0007 SCIDRL R R 7R 6R 5R 4R 3R 2R 1R 0 W T 7T 6T 5T 4T 3T 2T 1T 0 1.These registers are accessible if the AMAP bit in the SCISR2 register is set to zero. 2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one. Module Base + 0x0000 76543210 R SBR15 SBR14 SBR13 SBR12 SBR11 SBR10 SBR9 SBR8 W R e s e t 00000000 Figure 14-3. SCI Baud Rate Register (SCIBDH) Module Base + 0x0001 76543210 R SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W R e s e t 01000000 Figure 14-4. SCI Baud Rate Register (SCIBDL) Register Name B i t 7 654321 B i t 0 = Unimplemented or Reserved Figure 14-2. SCI Register Summary (Sheet 2 of 2)
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Write: Anytime, if AMAP = 0. NOTE Those two registers are only visible in the memory map if AMAP = 0 (reset condition). The SCI baud rate register is used by to determine the baud rate of the SCI, and to control the infrared modulation/demodulation submodule.
14.3.2.2 SCI Control Register 1 (SCICR1)
Read: Anytime, if AMAP = 0. Write: Anytime, if AMAP = 0. NOTE This register is only visible in the memory map if AMAP = 0 (reset condition). Table 14-2. SCIBDH and SCIBDL Field Descriptions Field Description SBR[15:0] SCI Baud Rate Bits — The baud rate for the SCI is determined by the bits in this register. The baud rate is calculated two different ways depending on the state of the IREN bit. The formulas for calculating the baud rate are: When IREN = 0 then, SCI baud rate = SCI bus clock / (SBR[15:0]) When IREN = 1 then, SCI baud rate = SCI bus clock / (2 x SBR[15:1]) Note: The baud rate generator is disabled after reset and not started until the TE bit or the RE bit is set for the first time. The baud rate generator is disabled when (SBR[15:4] = 0 and IREN = 0) or (SBR[15:5] = 0 and IREN = 1). Note: . User should write SCIBD by word access. The updated SCIBD may take effect until next RT clock start, write SCIBDH or SCIBDL separately may cause baud generator load wrong data at that time,if second write later then RT clock. Module Base + 0x0002 76543210 R LOOPS SCISWAI RSRC M WAKE ILT PE PT W R e s e t 00000000 Figure 14-5. SCI Control Register 1 (SCICR1)
Chapter 14 Serial Communication Interface (S12SCIV6) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 485 Table 14-4. SCICR1 Field Descriptions Field Description LOOPS Loop Select Bit — LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must be enabled to use the loop function.
0 Normal operation enabled
1 Loop operation enabled
The receiver input is determined by the RSRC bit. SCISWAI SCI Stop in Wait Mode Bit — SCISWAI disables the SCI in wait mode.
0 SCI enabled in wait mode
1 SCI disabled in wait mode
Receiver Source Bit — When LOOPS = 1, the RSRC bit determines the source for the receiver shift register input. See Table 14-5.
0 Receiver input internally connected to transmitter output
1 Receiver input connected externally to transmitter
M Data Format Mode Bit — MODE determines whether data charac ters are eight or nine bits long.
0 One start bit, eight data bits, one stop bit
1 One start bit, nine data bits, one stop bit
Wakeup Condition Bit — WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received data character or an idle condition on the RXD pin.
0 Idle line wakeup
1 Address mark wakeup
Idle Line Type Bit — ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions.
0 Idle character bit count begins after start bit
1 Idle character bit count begins after stop bit
Parity Enable Bit — PE enables the parity function. When enabled, the parity function inserts a parity bit in the most significant bit position.
0 Parity function disabled
1 Parity function enabled
Parity Type Bit — PT determines w hether the SCI generates and checks for even parity or odd parity. With even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit.
0 Even parity
1 Odd parity
Table 14-5. Loop Functions LOOPS RSRC Function 0 x Normal operation 1 0 Loop mode with transmitter output inte rnally connected to receiver input 1 1 Single-wire mode with TXD pin connected to receiver input
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14.3.2.3 SCI Alternative Status Register 1 (SCIASR1)
Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1
14.3.2.4 SCI Altern ative Control Register 1 (SCIACR1)
Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Module Base + 0x0000 76543210 R RXEDGIF
0000 B E R R V
W R e s e t 00000000 = Unimplemented or Reserved Figure 14-6. SCI Alternative Status Register 1 (SCIASR1) Table 14-6. SCIASR1 Field Descriptions Field Description RXEDGIF Receive Input Active Edge Interrupt Flag — RXEDGIF is asserted, if an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the RXD input occurs. RXEDGIF bit is cleared by writing a “1” to it.
0 No active receive on the receive input has occurred
1 An active edge on the receive input has occurred
Bit Error Value — BERRV reflects the state of the RXD input w hen the bit error detect circuitry is enabled and a mismatch to the expected value happened. The value is only meaningful, if BERRIF = 1.
0 A low input was sampled, when a high was expected
1 A high input reassembled, when a low was expected
Bit Error Interrupt Flag — BERRIF is asserted, when the bit error detect circuitry is enabled and if the value sampled at the RXD input does not match the transmitted value. If the BERRIE interrupt enable bit is set an interrupt will be generated. The BERRIF bit is cleared by writing a “1” to it.
0 No mismatch detected
1 A mismatch has occurred
Break Detect Interrupt Flag — BKDIF is asserted, if the break detect circuitry is enabled and a break signal is received. If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing a “1” to it.
0 No break signal was received
1 A break signal was received
R RXEDGIE 00000 BERRIE BKDIEW R e s e t 00000000 = Unimplemented or Reserved Figure 14-7. SCI Alternative Control Register 1 (SCIACR1)
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14.3.2.5 SCI Altern ative Control Register 2 (SCIACR2)
Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 14-7. SCIACR1 Field Descriptions Field Description RXEDGIE Receive Input Active Edge Interrupt Enable — RXEDGIE enables the receive input active edge interrupt flag, RXEDGIF, to generate interrupt requests.
0 RXEDGIF interrupt requests disabled
1 RXEDGIF interrupt requests enabled
Bit Error Interrupt Enable — BERRIE enables the bit error interrupt flag, BERRIF, to generate interrupt requests.
0 BERRIF interrupt requests disabled
1 BERRIF interrupt requests enabled
Break Detect Interrupt Enable — BKDIE enables the break detect interrupt flag, BKDIF, to generate interrupt requests.
0 BKDIF interrupt requests disabled
1 BKDIF interrupt requests enabled
R IREN TNP1 TNP0 BERRM1 BERRM0 BKDFE W R e s e t 00000000 = Unimplemented or Reserved Figure 14-8. SCI Alternative Control Register 2 (SCIACR2) Table 14-8. SCIACR2 Field Descriptions Field Description IREN Infrared Enable Bit — This bit enables/disables the infr ared modulation/demodulation submodule.
0 IR disabled
1 IR enabled
6:5 TNP[1:0] Transmitter Narrow Pulse Bits — These bits enable whether the SCI transmits a 1/16, 3/16, 1/32 or 1/4 narrow pulse. See Table 14-9. 2:1 BERRM[1:0] Bit Error Mode — Those two bits determines the functiona lity of the bit error detect feature. See Table 14-10. BKDFE Break Detect Feature Enable — BKDFE enables the break detect circuitry.
0 Break detect circuit disabled
1 Break detect circuit enabled
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14.3.2.6 SCI Control Register 2 (SCICR2)
Read: Anytime Write: Anytime Table 14-9. IRSCI Transmit Pulse Width TNP[1:0] Narrow Pulse Width 11 1/4 10 1/32 01 1/16 00 3/16 Table 14-10. Bit Error Mode Coding BERRM1 BERRM0 Function 0 0 Bit error detect circuit is disabled 0 1 Receive input sampling occurs during the 9th time tick of a transmitted bit (refer to Figure 14-19) 1 0 Receive input sampling occurs during the 13th time tick of a transmitted bit (refer to Figure 14-19)
11 R e s e r v e d
R TIE TCIE RIE ILIE TE RE RWU SBK W R e s e t 00000000 Figure 14-9. SCI Control Register 2 (SCICR2) Table 14-11. SCICR2 Field Descriptions Field Description TIE Transmitter Interrupt Enable Bit — TIE enables the transmit data regi ster empty flag, TDRE, to generate interrupt requests.
0 TDRE interrupt requests disabled
1 TDRE interrupt requests enabled
Transmission Complete Interrupt Enable Bit — TCIE enables the transmission complete flag, TC, to generate interrupt requests.
0 TC interrupt requests disabled
1 TC interrupt requests enabled
Receiver Full Interrupt Enable Bit — RIE enables the receive data register full flag, RDRF, or the overrun flag, OR, to generate interrupt requests.
0 RDRF and OR interrupt requests disabled
1 RDRF and OR interrupt requests enabled
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14.3.2.7 SCI Status Register 1 (SCISR1)
The SCISR1 and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts. Also, these registers can be polled by the MCU to check the status of these bits. The flag-clearing procedures require that the status register be read followed by a read or write to the SCI data register.It is permissible to execute other instructions between the two steps as long as it does not compromise the handling of I/O, but the order of operations is important for flag clearing. Read: Anytime Write: Has no meaning or effect ILIE Idle Line Interrupt Enable Bit — ILIE enables the idle line flag, IDLE, to generate interrupt requests.
0 IDLE interrupt requests disabled
1 IDLE interrupt requests enabled
Transmitter Enable Bit — TE enables the SCI transmitter and configures the TXD pin as being controlled by the SCI. The TE bit can be used to queue an idle preamble.
0 Transmitter disabled
1 Transmitter enabled
Receiver Enable Bit — RE enables the SCI receiver.
0 Receiver disabled
1 Receiver enabled
Receiver Wakeup Bit — Standby state 0 Normal operation. 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. SBK Send Break Bit — Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s if BRK13 is set). Toggling implies clearing the SBK bit before the break character has finished transmitting. As long as SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13 or 14 bits).
0 No break characters
1 Transmit break characters
R TDRE TC RDRF IDLE OR NF FE PF W R e s e t 11000000 = Unimplemented or Reserved Figure 14-10. SCI Status Register 1 (SCISR1) Table 14-11. SCICR2 Field Descriptions (continued) Field Description
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Table 14-12. SCISR1 Field Descriptions Field Description TDRE Transmit Data Register Empty Flag — TDRE is set when the transmit shift register receives a byte from the SCI data register. When TDRE is 1, the transmit data register (SCIDRH/L) is empty and can receive a new value to transmit.Clear TDRE by reading SCI status register 1 (SCISR1), with TDRE set and then writing to SCI data register low (SCIDRL).
0 No byte transferred to transmit shift register
1 Byte transferred to transmit shift re gister; transmit data register empty
Transmit Complete Flag — TC is set low when there is a transmission in progress or when a preamble or break character is loaded. TC is set high when the TDRE flag is set and no data, preamble, or break character is being transmitted.When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data register low (SCIDRL). TC is cleared automatically when data, preamble, or break is queued and ready to be sent. TC is cleared in the event of a simultaneous set and clear of the TC flag (transmission not complete).
0 Transmission in progress
1 No transmission in progress
Receive Data Register Full Flag — RDRF is set when the data in the receive shift register transfers to the SCI data register. Clear RDRF by reading SCI status register 1 (SCISR1) with RDRF set and then reading SCI data register low (SCIDRL).
0 Data not available in SCI data register
1 Received data available in SCI data register
Idle Line Flag — IDLE is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M =1) appear on the receiver input. Once the IDLE flag is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag.Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL).
0 Receiver input is either active now or has never become active since the IDLE flag was last cleared
1 Receiver input has become idle
Note: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE flag. OR Overrun Flag — OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected. Clear OR by reading SCI status register 1 (SCISR1) with OR set and then reading SCI data register low (SCIDRL).
0 No overrun
Note: OR flag may read back as set when RDRF flag is clear. This may happen if the following sequence of events occurs: 1. After the first frame is received, read status register SCISR1 (returns RDRF set and OR flag clear); 2. Receive second frame without readi ng the first frame in the data register (the second frame is not received and OR flag is set); 3. Read data register SCIDRL (returns first frame and clears RDRF flag in the status register); 4. Read status register SCISR1 (returns RDRF clear and OR set). Event 3 may be at exactly the same time as event 2 or any time after. When this happens, a dummy SCIDRL read following event 4 will be required to clear the OR flag if further frames are to be received. NF Noise Flag — NF is set when the SCI detect s noise on the receiver input. NF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1(SCISR1), and then reading SCI data register low (SCIDRL).
0 No noise
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14.3.2.8 SCI Status Register 2 (SCISR2)
Read: Anytime Write: Anytime FE Framing Error Flag — FE is set when a logic 0 is accepted as the stop bit. FE bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. FE inhibits further data reception until it is cleared. Clear FE by reading SCI status register 1 (SCISR1) with FE set and then reading the SCI data register low (SCIDRL).
0 No framing error
1 Framing error
Parity Error Flag — PF is set when the parity enable bit (PE) is set and the parity of the received data does not match the parity type bit (PT). PF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low (SCIDRL).
0 No parity error
1 Parity error
R AMAP 00 TXPOL RXPOL BRK13 TXDIR RAF W R e s e t 00000000 = Unimplemented or Reserved Figure 14-11. SCI Status Register 2 (SCISR2) Table 14-13. SCISR2 Field Descriptions Field Description AMAP Alternative Map — This bit controls which registers sharing the same address space are accessible. In the reset condition the SCI behaves as previous versions. Setting AMAP=1 allows the access to another set of control and status registers and hides the baud rate and SCI control Register 1.
0 The registers labelled SCIBDH (0x0000),SCIBDL (0x0001), SCICR1 (0x0002) are accessible
1 The registers labelled SCIASR1 (0x0000),SCIAC R1 (0x0001), SCIACR2 (0x00002) are accessible
Transmit Polarity — This bit control the polarity of the transmitt ed data. In NRZ format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for inverted polarity.
0 Normal polarity
1 Inverted polarity
Table 14-12. SCISR1 Field Descriptions (continued) Field Description
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14.3.2.9 SCI Data Registers (SCIDRH, SCIDRL)
Read: Anytime; reading accesses SCI receive data register Write: Anytime; writing accesses SCI transmit data register; writing to R8 has no effect RXPOL Receive Polarity — This bit control the polarity of the received data. In NRZ format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for inverted polarity. Break Transmit Character Length — This bit determines whether the transmit break character is 10 or 11 bit respectively 13 or 14 bits long. The detection of a framing error is not affected by this bit.
0 Break character is 10 or 11 bit long
1 Break character is 13 or 14 bit long
Transmitter Pin Data Direction in Single-Wire Mode — This bit determines whether the TXD pin is going to be used as an input or output, in the single-wire mode of operation. This bit is only relevant in the single-wire mode of operation.
0 TXD pin to be used as an input in single-wire mode
1 TXD pin to be used as an output in single-wire mode
Receiver Active Flag — RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RAF is cleared when the receiver detects an idle character.
0 No reception in progress
1 Reception in progress
Reserved Reserved Reserved W R e s e t 00000000 = Unimplemented or Reserved Figure 14-12. SCI Data Registers (SCIDRH) Module Base + 0x0007 76543210 R R 7R 6R 5R 4R 3R 2R 1R 0 W T7 T6 T5 T4 T3 T2 T1 T0 R e s e t 00000000 Figure 14-13. SCI Data Registers (SCIDRL) Table 14-13. SCISR2 Field Descriptions (continued) Field Description
Chapter 14 Serial Communication Interface (S12SCIV6) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 493 NOTE The reserved bit SCIDRH[2:0] are designed for factory test purposes only, and are not intended for general user access. Writing to these bit is possible when in special mode and can alter the modules functionality. NOTE If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten.The same value is transmitted until T8 is rewritten In 8-bit data format, only SCI data register low (SCIDRL) needs to be accessed. When transmitting in 9-bit data format and using 8-bit write instructions, write first to SCI data register high (SCIDRH), then SCIDRL.
14.4 Functional Description
This section provides a complete functional description of the SCI block, detailing the operation of the design from the end user perspective in a number of subsections. Figure 14-14 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, serial communication between the CPU and remote devices, including other CPUs. The SCI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. Table 14-14. SCIDRH and SCIDRL Field Descriptions Field Description SCIDRH Received Bit 8 — R8 is the ninth data bit received when the SCI is configured for 9-bit data format (M = 1). SCIDRH Transmit Bit 8 — T8 is the ninth data bit transmitted when the SCI is configured for 9-bit data format (M = 1). SCIDRL 7:0 R[7:0] T[7:0] R7:R0 — Received bits seven through zero for 9-bit or 8-bit data formats T7:T0 — Transmit bits seven through zero for 9-bit or 8-bit formats
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Figure 14-14. Detailed SCI Block Diagram
14.4.1 Infrared Interface Submodule
This module provides the capability of transmitting narrow pulses to an IR LED and receiving narrow pulses and transforming them to serial bits, which are sent to the SCI. The IrDA physical layer specification defines a half-duplex infrared communication link for exchange data. The full standard includes data rates up to 16 Mbits/s. This design covers only data rates between 2.4 Kbits/s and 115.2 Kbits/s. The infrared submodule consists of two major blocks: the transmit encoder and the receive decoder. The SCI transmits serial bits of data which are encoded by the infrared submodule to transmit a narrow pulse SCI Data Receive Shift Register SCI Data Register Transmit Shift Register Register Receive Generator SBR15:SBR0 Bus Transmit Control16 Receive and Wakeup Data Format Control Control PF FE NF RDRF IDLE TIE OR TCIE TDRE TC RAF LOOPS RWU RE PE ILT PT WAKE M Clock ILIE RIE RXD RSRC SBK LOOPS TE RSRC IREN R16XCLK Ir_RXD TXDIr_TXD R16XCLK R32XCLK TNP[1:0] IREN Transmit Encoder Receive Decoder SCRXD SCTXD Infrared Infrared TC TDRE RDRF/OR IDLE Active Edge Detect Break Detect RXD BKDFE BERRM[1:0] BKDIE BKDIF RXEDGIE RXEDGIF BERRIE BERRIF SCI Interrupt Request LIN Transmit Collision Detect Generator Baud Rate Baud Rate Transmit
Chapter 14 Serial Communication Interface (S12SCIV6) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 495 for every zero bit. No pulse is transmitted for every one bit. When receiving data, the IR pulses should be detected using an IR photo diode and transformed to CMOS levels by the IR receive decoder (external from the MCU). The narrow pulses are then stretched by the infrared submodule to get back to a serial bit stream to be received by the SCI.The polarity of transmitted pulses and expected receive pulses can be inverted so that a direct connection can be made to external IrDA transceiver modules that use active low pulses. The infrared submodule receives its clock sources from the SCI. One of these two clocks are selected in the infrared submodule in order to generate either 3/16, 1/16, 1/32 or 1/4 narrow pulses during transmission. The infrared block receives two clock sources from the SCI, R16XCLK and R32XCLK, which are configured to generate the narrow pulse width during transmission. The R16XCLK and R32XCLK are internal clocks with frequencies 16 and 32 times the baud rate respectively. Both R16XCLK and R32XCLK clocks are used for transmitting data. The receive decoder uses only the R16XCLK clock.
14.4.1.1 Infrared Transmit Encoder
The infrared transmit encoder converts serial bits of data from transmit shift register to the TXD pin. A narrow pulse is transmitted for a zero bit and no pulse for a one bit. The narrow pulse is sent in the middle of the bit with a duration of 1/32, 1/16, 3/16 or 1/4 of a bit time. A narrow high pulse is transmitted for a zero bit when TXPOL is cleared, while a narrow low pulse is transmitted for a zero bit when TXPOL is set.
14.4.1.2 Infrared Receive Decoder
The infrared receive block converts data from the RXD pin to the receive shift register. A narrow pulse is expected for each zero received and no pulse is expected for each one received. A narrow high pulse is expected for a zero bit when RXPOL is cleared, while a narrow low pulse is expected for a zero bit when RXPOL is set. This receive decoder meets the edge jitter requirement as defined by the IrDA serial infrared physical layer specification.
14.4.2 LIN Support
This module provides some basic support for the LIN protocol. At first this is a break detect circuitry making it easier for the LIN software to distinguish a break character from an incoming data stream. As a further addition is supports a collision detection at the bit level as well as cancelling pending transmissions.
14.4.3 Data Format
The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data format where zeroes are represented by light pulses and ones remain low. See Figure 14-15 below.
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Figure 14-15. SCI Data Formats Each data character is contained in a frame that includes a start bit, eight or nine data bits, and a stop bit. Clearing the M bit in SCI control register 1 configures the SCI for 8-bit data characters. A frame with eight data bits has a total of 10 bits. Setting the M bit configures the SCI for nine-bit data characters. A frame with nine data bits has a total of 11 bits. When the SCI is configured for 9-bit data characters, the ninth data bit is the T8 bit in SCI data register high (SCIDRH). It remains unchanged after transmission and can be used repeatedly without rewriting it. A frame with nine data bits has a total of 11 bits.
14.4.4 Baud Rate Generation
A 16-bit modulus counter in the two baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 65535 written to the SBR15:SBR0 bits determines the baud rate. The value Table 14-15. Example of 8-Bit Data Formats Start Bit Data Bits Address Bits Parity Bits Stop Bit 1 8001 1 7011 17 1 (1) 1. The address bit identifies the frame as an address Table 14-16. Example of 9-Bit Data Formats Start Bit Data Bits Address Bits Parity Bits Stop Bit 1 9001 1 8011 18 1 (1) 1. The address bit identifies the frame as an address Bit 5 Start Bit Bit 0 Bit 1 Next STOP Bit Start Bit 8-Bit Data Format (Bit M in SCICR1 Clear) Start Bit Bit 0 NEXT STOP Bit START Bit 9-Bit Data Format (Bit M in SCICR1 Set) Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 2 Bit 3 Bit 4 Bit 6 Bit 7 POSSIBLE PARITY Bit Possible Parity Bit Standard SCI Data Infrared SCI DataStandard SCI Data Infrared SCI Data
Chapter 14 Serial Communication Interface (S12SCIV6) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 497 from 0 to 4095 written to the SBR15:SBR4 bits determines the baud rate clock with SBR3:SBR0 for fine adjust. The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL) for both transmit and receive baud generator. The baud rate clock is synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter. The receiver has an acquisition rate of 16 samples per bit time. Baud rate generation is subject to one source of error:
- Integer division of the bus clock may not give the exact target frequency. Table 14-17 lists some examples of achieving target baud rates with a bus clock frequency of 25 MHz. When IREN = 0 then, SCI baud rate = SCI bus clock / (SCIBR[15:0]) Table 14-17. Baud Rates (Example: Bus Clock = 25 MHz) Bits SBR[15:0] Receiver(1) Clock (Hz) 1. 16x faster then baud rate Transmitter(2) Clock (Hz) 2. divide 1/16 form transmit baud generator Target Baud Rate Error (%) 109 3669724.8 229,357.8 230,400 .452 217 1843318.0 115,207.4 115,200 .006 651 614439.3 38,402.5 38,400 .006 1302 307219.7 19,201.2 19,200 .006 2604 153,609.8 9600.6 9,600 .006 5208 76,804.9 4800.3 4,800 .006 10417 38,398.8 2399.9 2,400 .003 20833 19,200.3 1200.02 1,200 .00 41667 9599.9 600.0 600 .00 65535 6103.6 381.5
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14.4.5 Transmitter
Figure 14-16. Transmitter Block Diagram
14.4.5.1 Transmitter Character Length
The SCI transmitter can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1) determines the length of data characters. When transmitting 9-bit data, bit T8 in SCI data register high (SCIDRH) is the ninth bit (bit 8).
14.4.5.2 Character Transmission
To transmit data, the MCU writes the data bits to the SCI data registers (SCIDRH/SCIDRL), which in turn are transferred to the transmitter shift register. The transmit shift register then shifts a frame out through the TXD pin, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit shift register. PE PT H876543210L 11-Bit Transmit Register Stop Start TIE TDRE TCIE SBK TC Parity Generation MSB SCI Data RegistersLoad from SCIDR Shift Enable Preamble (All 1s) Break (All 0s) Transmitter Control M Internal Bus SBR15:SBR4 Transmit baud 16Bus Clock TE SCTXD TXPOL LOOPS LOOP RSRC CONTROL To Receiver Transmit Collision Detect TDRE IRQ TC IRQ SCTXD SCRXD (From Receiver) TCIE BERRIF BER IRQ BERRM[1:0] generator SBR3:SBR0
Chapter 14 Serial Communication Interface (S12SCIV6) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 499 The SCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from the buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this flag by writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting out the first byte. To initiate an SCI transmission: 1. Configure the SCI: a) Select a baud rate. Write this value to the SCI baud registers (SCIBDH/L) to begin the baud rate generator. Remember that the baud rate generator is disabled when the baud rate is zero. Writing to the SCIBDH has no effect without also writing to SCIBDL. b) Write to SCICR1 to configure word le ngth, parity, and other configuration bits (LOOPS,RSRC,M,WAKE,ILT,PE,PT). c) Enable the transmitter, interrupts, receive, a nd wake up as required, by writing to the SCICR2 register bits (TIE,TCIE,RIE,ILIE,TE,RE,RWU,SBK). A preamble or idle character will now be shifted out of the transmitter shift register. 2. Transmit Procedure for each byte: a) Poll the TDRE flag by reading the SCISR1 or responding to the TDRE interrupt. Keep in mind that the TDRE bit resets to one. b) If the TDRE flag is set, write the data to be transmitted to SCIDRH/L, where the ninth bit is written to the T8 bit in SCIDRH if the SCI is in 9-bit data format. A new transmission will not result until the TDRE flag has been cleared. 3. Repeat step 2 for each subsequent transmission. NOTE The TDRE flag is set when the shift register is loaded with the next data to be transmitted from SCIDRH/L, which happens, generally speaking, a little over half-way through the stop bit of the previous frame. Specifically, this transfer occurs 9/16ths of a bit time AFTER the start of the stop bit of the previous frame. Writing the TE bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic 1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from the SCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit position. Hardware supports odd or even parity. When parity is enabled, the most significant bit (MSB) of the data character is the parity bit. The transmit data register empty flag, TDRE, in SCI status register 1 (SCISR1) becomes set when the SCI data register transfers a byte to the transmit shift register. The TDRE flag indicates that the SCI data register can accept new data from the internal data bus. If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCICR2) is also set, the TDRE flag generates a transmitter interrupt request.
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When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic 1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal goes low and the transmit signal goes idle. If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE to go high after the last frame before clearing TE. To separate messages with preambles with minimum idle line time, use this sequence between messages: 1. Write the last byte of the first message to SCIDRH/L. 2. Wait for the TDRE flag to go high, indicating the tr ansfer of the last frame to the transmit shift register. 3. Queue a preamble by clearing and then setting the TE bit. 4. Write the first byte of the second message to SCIDRH/L.
14.4.5.3 Break Characters
Writing a logic 1 to the send break bit, SBK, in SCI control register 2 (SCICR2) loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCI control register 1 (SCICR1). As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next frame. The SCI recognizes a break character when there are 10 or 11(M = 0 or M = 1) consecutive zero received. Depending if the break detect feature is enabled or not receiving a break character has these effects on SCI registers. If the break detect feature is disabled (BKDFE = 0):
- Sets the framing error flag, FE
- Sets the receive data register full flag, RDRF
- Clears the SCI data registers (SCIDRH/L)
- May set the overrun flag, OR, noise flag, NF, parity error flag, PE, or the receiver active flag, RAF (see 3.4.4 and 3.4.5 SCI Status Register 1 and 2) If the break detect feature is enabled (BKDFE = 1) there are two scenarios The break is detected right from a start bit or is detected during a byte reception.
- Sets the break detect interrupt flag, BKDIF
- Does not change the data register full flag, RDRF or overrun flag OR
- Does not change the framing error flag FE, parity error flag PE.
- Does not clear the SCI da ta registers (SCIDRH/L)
- May set noise flag NF, or receiver active flag RAF. 1. A Break character in this context are either 10 or 11 consecutive zero received bits
Chapter 14 Serial Communication Interface (S12SCIV6) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 501 Figure 14-17 shows two cases of break detect. In trace RXD_1 the break symbol starts with the start bit, while in RXD_2 the break starts in the middle of a transmission. If BRKDFE = 1, in RXD_1 case there will be no byte transferred to the receive buffer and the RDRF flag will not be modified. Also no framing error or parity error will be flagged from this transfer. In RXD_2 case, however the break signal starts later during the transmission. At the expected stop bit position the byte received so far will be transferred to the receive buffer, the receive data register full flag will be set, a framing error and if enabled and appropriate a parity error will be set. Once the break is detected the BRKDIF flag will be set. Figure 14-17. Break Detection if BRKDFE = 1 (M = 0)
14.4.5.4 Idle Characters
An idle character (or preamble) contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCI control register 1 (SCICR1). The preamble is a synchronizing idle character that begins the first transmission initiated after writing the TE bit from 0 to 1. If the TE bit is cleared during a transmission, the TXD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the frame currently being transmitted. NOTE When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current frame shifts out through the TXD pin. Setting TE after the stop bit appears on TXD causes data previously written to the SCI data register to be lost. Toggle the TE bit for a queued idle character while the TDRE flag is set and immediately before writing the next byte to the SCI data register. If the TE bit is clear and the transmission is complete, the SCI is not the master of the TXD pin Start Bit Position Stop Bit Position BRKDIF = 1 FE = 1 BRKDIF = 1 RXD_1 RXD_2 123 4567 8 91 0 123 4567 8 91 0 Zero Bit Counter Zero Bit Counter . . . . . .
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14.4.5.5 LIN Transmit Collision Detection
This module allows to check for collisions on the LIN bus. Figure 14-18. Collision Detect Principle If the bit error circuit is enabled (BERRM[1:0] = 0:1 or = 1:0]), the error detect circuit will compare the transmitted and the received data stream at a point in time and flag any mismatch. The timing checks run when transmitter is active (not idle). As soon as a mismatch between the transmitted data and the received data is detected the following happens:
- The next bit transmit ted will have a high level (TXPOL = 0) or low level (TXPOL = 1)
- The transmission is aborted and the byte in transmit buffer is discarded.
- the transmit data register empty and the transmission complete flag will be set
- The bit error interrupt fl ag, BERRIF, will be set.
- No further transmissions will take place until the BERRIF is cleared. Figure 14-19. Timing Diagram Bit Error Detection If the bit error detect feature is disabled, the bit error interrupt flag is cleared. NOTE The RXPOL and TXPOL bit should be set the same when transmission collision detect feature is enabled, otherwise the bit error interrupt flag may be set incorrectly. TXD Pin RXD Pin LIN Physical InterfaceSynchronizer Stage Bus Clock Receive Shift Register Transmit Shift Register LIN Bus Compare Sample Bit Error Point Output Transmit Shift Register 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 0 Input Receive Shift Register BERRM[1:0] = 0:1 BERRM[1:0] = 1:1 Compare Sample Points Sampling Begin Sampling Begin Sampling End Sampling End
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14.4.6 Receiver
Figure 14-20. SCI Receiver Block Diagram
14.4.6.1 Receiver Character Length
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in SCI data register high (SCIDRH) is the ninth bit (bit 8).
14.4.6.2 Character Reception
During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register is the read-only buffer between the internal data bus and the receive shift register. After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set, All 1s M WAKE ILT PE PT RE H876543210L 11-Bit Receive Shift Register Stop Start Data Wakeup Parity Checking MSB SCI Data Register ILIE RWU RDRF OR NF FE PE Internal Bus Bus SBR15:SBR4 Receive Baud Clock IDLE RAF Recovery Logic RXPOL LOOPS Loop RSRC Control SCRXD From TXD Pin or Transmitter Idle IRQ RDRF/OR IRQ Break Detect Logic Active Edge Detect Logic BRKDFE BRKDIE BRKDIF RXEDGIE RXEDGIF Break IRQ RX Active Edge IRQ RIE Generator SBR3:SBR0
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indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request.
14.4.6.3 Data Sampling
The RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock (see Figure 14-21) is re-synchronized immediatelly at bus clock edge:
- After every start bit
- After the receiver detects a data bit change from lo gic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0) To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s.When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.Figure 14-21. Receiver Data Sampling To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Figure 14-18 summarizes the results of the start bit verification samples. If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. Table 14-18. Start Bit Verification RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag
000 Yes 0
001 Yes 1
010 Yes 1
011 No 0
100 Yes 1
101 No 0
110 No 0
111 No 0
Chapter 14 Serial Communication Interface (S12SCIV6) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 505 To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 14-19 summarizes the results of the data bit samples. NOTE The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit (logic 0). To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 14-20 summarizes the results of the stop bit samples. In Figure 14-22 the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found. Table 14-19. Data Bit Recovery RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 Table 14-20. Stop Bit Recovery RT8, RT9, and RT10 Samples F raming Error Flag Noise Flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0
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Figure 14-22. Start Bit Search Example 1 In Figure 14-23, verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful. Figure 14-23. Start Bit Search Example 2 In Figure 14-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful. Reset RT Clock RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT1 RT1 RT2 RT3 RT4 RT7 RT6 RT5 RT10 RT9 RT8 RT14 RT13 RT12 RT11 RT15 RT16 RT1 RT2 RT3 Samples RT Clock RT Clock Count Start Bit RXD 11 0111 1 0 0 0 00 LSB 0 0 Reset RT Clock RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT11 RT10 RT9 RT14 RT13 RT12 RT2 RT1 RT16 RT15 RT3 RT4 RT5 RT6 RT7 Samples RT Clock RT Clock Count Actual Start Bit RXD 11 1111 0 0 0 0 LSB Perceived Start Bit
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Figure 14-26. Start Bit Search Example 5 In Figure 14-27, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the noise flag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are ignored. Figure 14-27. Start Bit Search Example 6
14.4.6.4 Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it sets the framing error flag, FE, in SCI status register 1 (SCISR1). A break character also sets the FE flag because a break character has no stop bit. The FE flag is set at the same time that the RDRF flag is set.
14.4.6.5 Baud Rate Tolerance
A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical values. A framing error will occur if the receiver clock is misaligned in such a way that the majority of the RT8, RT9, and RT10 stop bit samples are a logic zero. Reset RT Clock RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT7 RT6 RT5 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 Samples RT Clock RT Clock Count Start Bit RXD 11 111 0 1 0 LSB 11 1 1 1 00 000 00 0 No Start Bit Found Reset RT Clock RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT7 RT6 RT5 RT10 RT9 RT8 RT14 RT13 RT12 RT11 RT15 RT16 RT1 RT2 RT3 Samples RT Clock RT Clock Count Start Bit RXD 11 111 0 0 0 LSB 11 1 1 0 11 0
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14.4.6.5.1 Slow Data Tolerance
Figure 14-28 shows how much a slow received frame can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10. Figure 14-28. Slow Data Let’s take RTr as receiver RT clock and RTt as transmitter RT clock. For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles +7 RTr cycles = 151 RTr cycles to start data sampling of the stop bit. With the misaligned character shown in Figure 14-28, the receiver counts 151 RTr cycles at the point when the count of the transmitting device is 9 bit times x 16 RTt cycles = 144 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data character with no errors is: For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 7 RTr cycles = 167 RTr cycles to start data sampling of the stop bit. With the misaligned character shown in Figure 14-28, the receiver counts 167 RTr cycles at the point when the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is:
14.4.6.5.2 Fast Data Tolerance
Figure 14-29 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. MSB Stop RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 Data Samples Receiver RT Clock
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Figure 14-29. Fast Data For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles + 9 RTr cycles = 153 RTr cycles to finish data sampling of the stop bit. With the misaligned character shown in Figure 14-29, the receiver counts 153 RTr cycles at the point when the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is: For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 9 RTr cycles = 169 RTr cycles to finish data sampling of the stop bit. With the misaligned character shown in Figure 14-29, the receiver counts 169 RTr cycles at the point when the count of the transmitting device is 11 bit times x 16 RTt cycles = 176 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is: NOTE Due to asynchronous sample and internal logic, there is maximal 2 bus cycles between startbit edge and 1st RT clock, and cause to additional tolerance loss at worst case. The loss should be 2/SBR/10*100%, it is small.For example, for highspeed baud=230400 with 25MHz bus, SBR should be 109, and the tolerance loss is 2/109/10*100=0.18%, and fast data tolerance is 4.375%-0.18%=4.195%.
14.4.6.6 Receiver Wakeup
To enable the SCI to ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCI control register 2 (SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The SCI will still load the receive data into the SCIDRH/L registers, but it will not set the RDRF flag. The transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. Idle or Next FrameStop RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 Data Samples Receiver RT Clock
Chapter 14 Serial Communication Interface (S12SCIV6) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 511 The WAKE bit in SCI control register 1 (SCICR1) determines how the SCI is brought out of the standby state to process an incoming message. The WAKE bit enables either idle line wakeup or address mark wakeup.
14.4.6.6.1 Idle Input line Wakeup (WAKE = 0)
In this wakeup method, an idle condition on the RXD pin clears the RWU bit and wakes up the SCI. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another idle character appears on the RXD pin. Idle line wakeup requires that messages be separated by at least one idle character and that no message contains idle characters. The idle character that wakes a receiver does not set the receiver idle bit, IDLE, or the receive data register full flag, RDRF. The idle line type bit, ILT, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. ILT is in SCI control register 1 (SCICR1).
14.4.6.6.2 Address Mark Wakeup (WAKE = 1)
In this wakeup method, a logic 1 in the most significant bit (MSB) position of a frame clears the RWU bit and wakes up the SCI. The logic 1 in the MSB position marks a frame as an address frame that contains addressing information. All receivers evaluate the addressing information, and the receivers for which the message is addressed process the frames that follow.Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another address frame appears on the RXD pin. The logic 1 MSB of an address frame clears the receiver’s RWU bit before the stop bit is received and sets the RDRF flag. Address mark wakeup allows messages to contain idle characters but requires that the MSB be reserved for use in address frames. NOTE With the WAKE bit clear, setting the RWU bit after the RXD pin has been idle can cause the receiver to wake up immediately.
14.4.7 Single-Wire Operation
Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation, the RXD pin is disconnected from the SCI. The SCI uses the TXD pin for both receiving and transmitting.
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Figure 14-30. Single-Wire Operation (LOOPS = 1, RSRC = 1) Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting the RSRC bit connects the TXD pin to the receiver. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1).The TXDIR bit (SCISR2[1]) determines whether the TXD pin is going to be used as an input (TXDIR = 0) or an output (TXDIR = 1) in this mode of operation. NOTE In single-wire operation data from the TXD pin is inverted if RXPOL is set.
14.4.8 Loop Operation
In loop operation the transmitter output goes to the receiver input. The RXD pin is disconnected from the SCI. Figure 14-31. Loop Operation (LOOPS = 1, RSRC = 0) Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Clearing the RSRC bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1). NOTE In loop operation data from the transmitter is not recognized by the receiver if RXPOL and TXPOL are not the same.
14.5 Initialization/Application Information
14.5.1 Reset Initialization
See Section 14.3.2, “Register Descriptions”. RXD Transmitter Receiver TXD RXD Transmitter Receiver TXD
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14.5.2 Modes of Operation
14.5.2.1 Run Mode
Normal mode of operation. To initialize a SCI transmission, see Section 14.4.5.2, “Character Transmission”.
14.5.2.2 Wait Mode
SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1 (SCICR1).
- If SCISWAI is clear, the SCI operates nor mally when the CPU is in wait mode.
- If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver enable bit, RE, or the transmitter enable bit, TE. If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The transmission or reception resumes when either an internal or external interrupt brings the CPU out of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and resets the SCI.
14.5.2.3 Stop Mode
The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not affect the SCI register states, but the SCI bus clock will be disabled. The SCI operation resumes from where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset aborts any transmission or reception in progress and resets the SCI. The receive input active edge detect circuit is still active in stop mode. An active edge on the receive input can be used to bring the CPU out of stop mode.
14.5.3 Interrupt Operation
This section describes the interrupt originated by the SCI block.The MCU must service the interrupt requests. Table 14-21 lists the eight interrupt sources of the SCI. Table 14-21. SCI Interrupt Sources Interrupt Source Local Enable Description TDRE SCISR1[7] TIE Active high level. Indicates t hat a byte was transferred from SCIDRH/L to the transmit shift register. TC SCISR1[6] TCIE Active high level. Indi cates that a transmit is complete. RDRF SCISR1[5] RIE Active high level. The RDRF interr upt indicates that received data is available in the SCI data register. OR SCISR1[3] Active high level. This interrupt indicates that an overrun condition has occurred. IDLE SCISR1[4] ILIE Active high level. Indica tes that receiver input has become idle. RXEDGIF SCIASR1[7] RXEDGIE Active high level. Indicates t hat an active edge (falling for RXPOL = 0, rising for RXPOL = 1) was detected.
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14.5.3.1 Description of Interrupt Operation
The SCI only originates interrupt requests. The following is a description of how the SCI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent. The SCI only has a single interrupt line (SCI Interrupt Signal, active high operation) and all the following interrupts, when generated, are ORed together and issued through that port.
14.5.3.1.1 TDRE Description
The TDRE interrupt is set high by the SCI when the transmit shift register receives a byte from the SCI data register. A TDRE interrupt indicates that the transmit data register (SCIDRH/L) is empty and that a new byte can be written to the SCIDRH/L for transmission.Clear TDRE by reading SCI status register 1 with TDRE set and then writing to SCI data register low (SCIDRL).
14.5.3.1.2 TC Description
The TC interrupt is set by the SCI when a transmission has been completed. Transmission is completed when all bits including the stop bit (if transmitted) have been shifted out and no data is queued to be transmitted. No stop bit is transmitted when sending a break character and the TC flag is set (providing there is no more data queued for transmission) when the break character has been shifted out. A TC interrupt indicates that there is no transmission in progress. TC is set high when the TDRE flag is set and no data, preamble, or break character is being transmitted. When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data register low (SCIDRL).TC is cleared automatically when data, preamble, or break is queued and ready to be sent.
14.5.3.1.3 RDRF Description
The RDRF interrupt is set when the data in the receive shift register transfers to the SCI data register. A RDRF interrupt indicates that the received data has been transferred to the SCI data register and that the byte can now be read by the MCU. The RDRF interrupt is cleared by reading the SCI status register one (SCISR1) and then reading SCI data register low (SCIDRL).
14.5.3.1.4 OR Description
The OR interrupt is set when software fails to read the SCI data register before the receive shift register receives the next frame. The newly acquired data in the shift register will be lost in this case, but the data already in the SCI data registers is not affected. The OR interrupt is cleared by reading the SCI status register one (SCISR1) and then reading SCI data register low (SCIDRL). BERRIF SCIASR1[1] BERRIE Active high level. Indicates that a mismatch between transmitted and received data in a single wire application has happened. BKDIF SCIASR1[0] BRKDIE Active high level. Indicates that a break character has been received. Table 14-21. SCI Interrupt Sources
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14.5.3.1.5 IDLE Description
The IDLE interrupt is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M = 1) appear on the receiver input. Once the IDLE is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag. Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL).
14.5.3.1.6 RXEDGIF Description
The RXEDGIF interrupt is set when an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternative status register 1.
14.5.3.1.7 BERRIF Description
The BERRIF interrupt is set when a mismatch between the transmitted and the received data in a single wire application like LIN was detected. Clear BERRIF by writing a “1” to the SCIASR1 SCI alternative status register 1. This flag is also cleared if the bit error detect feature is disabled.
14.5.3.1.8 BKDIF Description
The BKDIF interrupt is set when a break signal was received. Clear BKDIF by writing a “1” to the SCIASR1 SCI alternative status register 1. This flag is also cleared if break detect feature is disabled.
14.5.4 Recovery from Wait Mode
The SCI interrupt request can be used to bring the CPU out of wait mode.
14.5.5 Recovery from Stop Mode
An active edge on the receive input can be used to bring the CPU out of stop mode.
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MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductor 517 Chapter 15 Serial Peripheral Interface (S12SPIV5)
15.1 Introduction
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven.
15.1.1 Glossary of Terms
15.1.2 Features
The SPI includes these distinctive features:
- Master mode and slave mode
- Selectable 8 or 16-bit transfer width
- Bidirectional mode
- Slave select output
- Mode fault error flag with CPU interrupt capability
- Double-buffered data register
- Serial clock with progr ammable polarity and phase
- Control of SPI operation during wait mode
15.1.3 Modes of Operation
The SPI functions in three modes: run, wait, and stop. Table 15-1. Revision History Revision Number Revision Date Sections Affected Description of Changes V05.00 24 Mar 2005 15.3.2/15-521 - Added 16-bit transfer width feature. SPI Serial Peripheral Interface SS Slave Select SCK Serial Clock MOSI Master Output, Slave Input MISO Master Input, Slave Output MOMI Master Output, Master Input SISO Slave Input, Slave Output
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- Run mode This is the basic mode of operation.
- Wait mode SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in run mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI clock generation turned off. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and transmission of data continues, so that the slave stays synchronized to the master.
- Stop mode The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and transmission of data continues, so that the slave stays synchronized to the master. For a detailed description of operating modes, please refer to Section 15.4.7, “Low Power Mode Options”.
15.1.4 Block Diagram
Figure 15-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.
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15.2 External Signal Description
This section lists the name and description of all ports including inputs and outputs that do, or may, connect off chip. The SPI module has a total of four external pins.
15.2.1 MOSI — Master Out/Slave In Pin
This pin is used to transmit data out of the SPI module when it is configured as a master and receive data when it is configured as slave. SPI Control Register 1 SPI Control Register 2 SPI Baud Rate Register SPI Status Register SPI Data Register Shifter Port Control Logic MOSI SCK Interrupt Control SPI MSB LSB LSBFE=1 LSBFE=0 LSBFE=0 LSBFE=1 Data In LSBFE=1 LSBFE=0 Data Out Baud Rate Generator PrescalerBus Clock Counter Clock Select SPPR 3 3SPR Baud Rate Phase + Polarity Control Master Slave SCK In SCK OutMaster Baud Rate Slave Baud Rate Phase + Polarity Control Control Control CPOL CPHA BIDIROE SPC0 Shift Sample ClockClock MODFSPIF SPTEF SPI Request Interrupt SS MISO
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15.2.2 MISO — Master In/Slave Out Pin
This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data when it is configured as master.
15.2.3 SS — Slave Select Pin
This pin is used to output the select signal from the SPI module to another peripheral with which a data transfer is to take place when it is configured as a master and it is used as an input to receive the slave select signal when the SPI is configured as slave.
15.2.4 SCK — Serial Clock Pin
In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.
15.3 Memory Map and Register Definition
This section provides a detailed description of address space and registers used by the SPI.
15.3.1 Module Memory Map
The memory map for the SPI is given in Figure 15-2. The address listed for each register is the sum of a base address and an address offset. The base address is defined at the SoC level and the address offset is defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have no effect. Register Name B i t 7 654321 B i t 0 0x0000 SPICR1 R SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFEW 0x0001 SPICR2 R0 XFRW 0 MODFEN BIDIROE 0 SPISWAI SPC0W 0x0002 SPIBR R0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0W 0x0003 SPISR R SPIF 0 SPTEF MODF 0 0 0 0 W 0x0004 SPIDRH R R15 R14 R13 R12 R11 R10 R9 R8 T15 T14 T13 T12 T11 T10 T9 T8W 0x0005 SPIDRL R R 7R 6R 5R 4R 3R 2R 1R 0 T7 T6 T5 T4 T3 T2 T1 T0W 0x0006 Reserved R W = Unimplemented or Reserved Figure 15-2. SPI Register Summary
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15.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
15.3.2.1 SPI Control Register 1 (SPICR1)
Read: Anytime Write: Anytime 0x0007 Reserved R W Module Base +0x0000 76543210 R SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE W R e s e t 00000100 Figure 15-3. SPI Control Register 1 (SPICR1) Table 15-2. SPICR1 Field Descriptions Field Description SPIE SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set. 0 SPI interrupts disabled. 1 SPI interrupts enabled. SPE SPI System Enable Bit — This bit enables the SPI system and dedi cates the SPI port pins to SPI system functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset. 0 SPI disabled (lower power consumption). 1 SPI enabled, port pins are dedicated to SPI functions. SPTIE SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF flag is set. 0 SPTEF interrupt disabled. 1 SPTEF interrupt enabled. MSTR SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode. Switching the SPI from master to slave or vice versa forces the SPI system into idle state. 0 SPI is in slave mode. 1 SPI is in master mode. CPOL SPI Clock Polarity Bit — This bit selects an inverted or non-inve rted SPI clock. To transmit data between SPI modules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Active-high clocks selected. In idle state SCK is low. 1 Active-low clocks selected. In idle state SCK is high. Register Name B i t 7 654321 B i t 0 = Unimplemented or Reserved Figure 15-2. SPI Register Summary
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15.3.2.2 SPI Control Register 2 (SPICR2)
Read: Anytime Write: Anytime; writes to the reserved bits have no effect CPHA SPI Clock Phase Bit — This bit is used to select the SPI clock fo rmat. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Sampling of data occurs at odd edges (1,3,5,...) of the SCK clock. 1 Sampling of data occurs at even edges (2,4,6,...) of the SCK clock. SSOE Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by asserting the SSOE as shown in Table 15-3. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. LSBFE LSB-First Enable — This bit does not affect the position of t he MSB and LSB in the data register. Reads and writes of the data register always have the MSB in the highest bit position. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Data is transferred most significant bit first. 1 Data is transferred least significant bit first. Table 15-3. SS Input / Output Selection MODFEN SSOE Master Mode Slave Mode
00 S S not used by SPI SS input
01 S S not used by SPI SS input
10S S input with MODF feature SS input
11 S S is slave select output SS input
W R e s e t 00000000 = Unimplemented or Reserved Figure 15-4. SPI Control Register 2 (SPICR2) Table 15-2. SPICR1 Field Descriptions (continued) Field Description
Chapter 15 Serial Peripheral Interface (S12SPIV5) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 523 Table 15-4. SPICR2 Field Descriptions Field Description XFRW Transfer Width — This bit is used for selecting the data transfer width. If 8-bit transfer width is selected, SPIDRL becomes the dedicated data register and SPIDRH is unused. If 16-bit transfer width is selected, SPIDRH and SPIDRL form a 16-bit data register. Please refer to Section 15.3.2.4, “SPI Status Register (SPISR) for information about transmit/receive data handling and the interrupt flag clearing mechanism. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 8-bit Transfer Width (n = 8)(1) 1 16-bit Transfer Width (n = 16)1 1. n is used later in this document as a placeholder for the selected transfer width. MODFEN Mode Fault Enable Bit — This bit allows the MODF failure to be detected. If the SPI is in master mode and MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin configuration, refer to Table 15-3. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0S S port pin is not used by the SPI. 1S S port pin with MODF feature. BIDIROE Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0 set, a change of this bit will abort a transmission in progress and force the SPI into idle state. 0 Output buffer disabled. 1 Output buffer enabled. SPISWAI SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode. 0 SPI clock operates normally in wait mode. 1 Stop SPI clock generation when in wait mode. SPC0 Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in Table 15-5. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. Table 15-5. Bidirectional Pin Configurations Pin Mode SPC0 BIDIROE MISO MOSI Master Mode of Operation Normal 0 X Master In Master Out Bidirectional 1 0 MISO not used by SPI Master In 1M a s t e r I / O Slave Mode of Operation Normal 0 X Slave Out Slave In Bidirectional 1 0 Slave In MOSI not used by SPI
1 Slave I/O
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15.3.2.3 SPI Baud Rate Register (SPIBR)
Read: Anytime Write: Anytime; writes to the reserved bits have no effect The baud rate divisor equation is as follows: BaudRateDivisor = (SPPR + 1) 2(SPR + 1) Eqn. 15-1 The baud rate can be calculated with the following equation: Baud Rate = BusClock / BaudRateDivisor Eqn. 15-2 NOTE For maximum allowed baud rates, please refer to the SPI Electrical Specification in the Electricals chapter of this data sheet. Module Base +0x0002 76543210 SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 W R e s e t 00000000 = Unimplemented or Reserved Figure 15-5. SPI Baud Rate Register (SPIBR) Table 15-6. SPIBR Field Descriptions Field Description 6–4 SPPR[2:0] SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in Table 15-7. In master mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state. 2–0 SPR[2:0] SPI Baud Rate Selection Bits — These bits specify the SPI baud rates as shown in Table 15-7. In master mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state. Table 15-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 1 of 3) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate 000 0 0 0 2 1 2 . 5 M b i t / s 000 0 0 1 4 6 . 2 5 M b i t / s 0 0 0 0 1 0 8 3.125 Mbit/s 0 0 0 0 1 1 16 1.5625 Mbit/s 0 0 0 1 0 0 32 781.25 kbit/s 0 0 0 1 0 1 64 390.63 kbit/s 0 0 0 1 1 0 128 195.31 kbit/s 0 0 0 1 1 1 256 97.66 kbit/s 001 0 0 0 4 6 . 2 5 M b i t / s 0 0 1 0 0 1 8 3.125 Mbit/s 0 0 1 0 1 0 16 1.5625 Mbit/s
Chapter 15 Serial Peripheral Interface (S12SPIV5) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 525 0 0 1 0 1 1 32 781.25 kbit/s 0 0 1 1 0 0 64 390.63 kbit/s 0 0 1 1 0 1 128 195.31 kbit/s 0 0 1 1 1 0 256 97.66 kbit/s 0 0 1 1 1 1 512 48.83 kbit/s 0 1 0 0 0 0 6 4.16667 Mbit/s 0 1 0 0 0 1 12 2.08333 Mbit/s 0 1 0 0 1 0 24 1.04167 Mbit/s 0 1 0 0 1 1 48 520.83 kbit/s 0 1 0 1 0 0 96 260.42 kbit/s 0 1 0 1 0 1 192 130.21 kbit/s 0 1 0 1 1 0 384 65.10 kbit/s 0 1 0 1 1 1 768 32.55 kbit/s 0 1 1 0 0 0 8 3.125 Mbit/s 0 1 1 0 0 1 16 1.5625 Mbit/s 0 1 1 0 1 0 32 781.25 kbit/s 0 1 1 0 1 1 64 390.63 kbit/s 0 1 1 1 0 0 128 195.31 kbit/s 0 1 1 1 0 1 256 97.66 kbit/s 0 1 1 1 1 0 512 48.83 kbit/s 0 1 1 1 1 1 1024 24.41 kbit/s 1 0 0 0 0 0 10 2.5 Mbit/s 1 0 0 0 0 1 20 1.25 Mbit/s 1 0 0 0 1 0 40 625 kbit/s 1 0 0 0 1 1 80 312.5 kbit/s 1 0 0 1 0 0 160 156.25 kbit/s 1 0 0 1 0 1 320 78.13 kbit/s 1 0 0 1 1 0 640 39.06 kbit/s 1 0 0 1 1 1 1280 19.53 kbit/s 1 0 1 0 0 0 12 2.08333 Mbit/s 1 0 1 0 0 1 24 1.04167 Mbit/s 1 0 1 0 1 0 48 520.83 kbit/s 1 0 1 0 1 1 96 260.42 kbit/s 1 0 1 1 0 0 192 130.21 kbit/s 1 0 1 1 0 1 384 65.10 kbit/s 1 0 1 1 1 0 768 32.55 kbit/s 1 0 1 1 1 1 1536 16.28 kbit/s 1 1 0 0 0 0 14 1.78571 Mbit/s 1 1 0 0 0 1 28 892.86 kbit/s 1 1 0 0 1 0 56 446.43 kbit/s 1 1 0 0 1 1 112 223.21 kbit/s 1 1 0 1 0 0 224 111.61 kbit/s Table 15-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 2 of 3) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate
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15.3.2.4 SPI Status Register (SPISR)
Read: Anytime Write: Has no effect 1 1 0 1 0 1 448 55.80 kbit/s 1 1 0 1 1 0 896 27.90 kbit/s 1 1 0 1 1 1 1792 13.95 kbit/s 1 1 1 0 0 0 16 1.5625 Mbit/s 1 1 1 0 0 1 32 781.25 kbit/s 1 1 1 0 1 0 64 390.63 kbit/s 1 1 1 0 1 1 128 195.31 kbit/s 1 1 1 1 0 0 256 97.66 kbit/s 1 1 1 1 0 1 512 48.83 kbit/s 1 1 1 1 1 0 1024 24.41 kbit/s 1 1 1 1 1 1 2048 12.21 kbit/s Module Base +0x0003 76543210 R SPIF 0 SPTEF MODF 0 0 0 0 W R e s e t 00100000 = Unimplemented or Reserved Figure 15-6. SPI Status Register (SPISR) Table 15-8. SPISR Field Descriptions Field Description SPIF SPIF Interrupt Flag — This bit is set after received data has been transferred into the SPI data register. For information about clearing SPIF Flag, please refer to Table 15-9. 0 Transfer not yet complete. 1 New data copied to SPIDR. SPTEF SPI Transmit Empty Interrupt Flag — If set, this bit indicates that th e transmit data register is empty. For information about clearing this bit and placing data into the transmit data register, please refer to Table 15-10. 0 SPI data register not empty. 1 SPI data register empty. MODF Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in Section 15.3.2.2, “SPI Control Register 2 (SPICR2)”. The flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to the SPI control register 1. 0 Mode fault has not occurred. 1 Mode fault has occurred. Table 15-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 3 of 3) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate
Chapter 15 Serial Peripheral Interface (S12SPIV5) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 527 Table 15-9. SPIF Interrupt Flag Clearing Sequence Table 15-10. SPTEF Interrupt Flag Clearing Sequence XFRW Bit SPIF Interrupt Flag Clearing Sequence
0 Read SPISR with SPIF == 1 then Read SPIDRL
1 Read SPISR with SPIF == 1
Byte Read SPIDRL (1) 1. Data in SPIDRH is lost in this case. or Byte Read SPIDRH (2) 2. SPIDRH can be read repeatedly without any effect on SPIF. SPIF Flag is cleared only by the read of SPIDRL after reading SPISR with SPIF == 1. Byte Read SPIDRL or Word Read (SPIDRH:SPIDRL) XFRW Bit SPTEF In terrupt Flag Clearing Sequence
0 Read SPISR with SPTEF == 1 then Write to SPIDRL (1)
- Any write to SPIDRH or SPIDRL with SPTEF == 0 is effectively ignored.
1 Read SPISR with SPTEF == 1
Byte Write to SPIDRL 1(2) 2. Data in SPIDRH is undefined in this case. or Byte Write to SPIDRH 1(3) 3. SPIDRH can be written repeatedly without any effect on SPTEF. SPTEF Flag is cleared only by writing to SPIDRL after reading SPISR with SPTEF == 1. Byte Write to SPIDRL 1 or Word Write to (SPIDRH:SPIDRL) 1
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15.3.2.5 SPI Data Register (SPIDR = SPIDRH:SPIDRL)
Read: Anytime; read data only valid when SPIF is set Write: Anytime The SPI data register is both the input and output register for SPI data. A write to this register allows data to be queued and transmitted. For an SPI configured as a master, queued data is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag SPTEF in the SPISR register indicates when the SPI data register is ready to accept new data. Received data in the SPIDR is valid when SPIF is set. If SPIF is cleared and data has been received, the received data is transferred from the receive shift register to the SPIDR and SPIF is set. If SPIF is set and not serviced, and a second data value has been received, the second received data is kept as valid data in the receive shift register until the start of another transmission. The data in the SPIDR does not change. If SPIF is set and valid data is in the receive shift register, and SPIF is serviced before the start of a third transmission, the data in the receive shift register is transferred into the SPIDR and SPIF remains set (see Figure 15-9). If SPIF is set and valid data is in the receive shift register, and SPIF is serviced after the start of a third transmission, the data in the receive shift register has become invalid and is not transferred into the SPIDR (see Figure 15-10). Module Base +0x0004 76543210 R R15 R14 R13 R12 R11 R10 R9 R8 W T 1 5T 1 4T 1 3T 1 2T 1 1T 1 0 T 9 T 8 R e s e t 00000000 Figure 15-7. SPI Data Register High (SPIDRH) Module Base +0x0005 76543210 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 R e s e t 00000000 Figure 15-8. SPI Data Register Low (SPIDRL)
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15.4 Functional Description
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or SPI operation can be interrupt driven. The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set, the four associated SPI port pins are dedicated to the SPI function as:
- Slave select (SS )
- Serial clock (SCK)
- Master out/slave in (MOSI)
- Master in/slave out (MISO) Receive Shift Register SPIF SPI Data Register Data A Data B Data A Data A Received Data B Received Data C Data C SPIF Serviced Data C Received Data B = Unspecified = Reception in progress Receive Shift Register SPIF SPI Data Register Data A Data B Data A Data A Received Data B Received Data C Data C SPIF Serviced Data C Received Data B Lost = Unspecified = Reception in progress
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The main element of the SPI system is the SPI data register. The n-bit1 data register in the master and the n-bit1 data register in the slave are linked by the MOSI and MISO pins to form a distributed 2n-bit1 register. When a data transfer operation is performed, this 2n-bit1 register is serially shifted n1 bit positions by the S-clock from the master, so data is exchanged between the master and the slave. Data written to the master SPI data register becomes the output data for the slave, and data read from the master SPI data register after a transfer operation is the input data from the slave. A read of SPISR with SPTEF = 1 followed by a write to SPIDR puts data into the transmit data register. When a transfer is complete and SPIF is cleared, received data is moved into the receive data register. This data register acts as the SPI receive data register for reads and as the SPI transmit data register for writes. A common SPI data register address is shared for reading data from the read data buffer and for writing data to the transmit data register. The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI control register 1 (SPICR1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simply selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered SCK edges or on even numbered SCK edges (see Section 15.4.3, “Transmission Formats”). The SPI can be configured to operate as a master or as a slave. When the MSTR bit in SPI control register1 is set, master mode is selected, when the MSTR bit is clear, slave mode is selected. NOTE A change of CPOL or MSTR bit while there is a received byte pending in the receive shift register will destroy the received byte and must be avoided.
15.4.1 Master Mode
The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by writing to the master SPI data register. If the shift register is empty, data immediately transfers to the shift register. Data begins shifting out on the MOSI pin under the control of the serial clock.
- Serial clock The SPR2, SPR1, and SPR0 baud rate selection bits, in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI baud rate register, control the baud rate generator and determine the speed of the transmission. The SCK pin is the SPI clock output. Through the SCK pin, the baud rate generator of the master controls the shift register of the slave peripheral.
- MOSI, MISO pin In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is determined by the SPC0 and BIDIROE control bits.
- S S pin If MODFEN and SSOE are set, the SS pin is configured as slave select output. The SS output becomes low during each transmission and is high when the SPI is in idle state. If MODFEN is set and SSOE is cleared, the SS pin is configured as input for detecting mode fault error. If the SS input becomes low this indicates a mode fault error where another master tries to 1. n depends on the selected transfer width, please refer to Section 15.3.2.2, “SPI Control Register 2 (SPICR2)
Chapter 15 Serial Peripheral Interface (S12SPIV5) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 531 drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional mode). So the result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state. This mode fault error also sets the mode fault (MODF) flag in the SPI status register (SPISR). If the SPI interrupt enable bit (SPIE) is set when the MODF flag becomes set, then an SPI interrupt sequence is also requested. When a write to the SPI data register in the master occurs, there is a half SCK-cycle delay. After the delay, SCK is started within the master. The rest of the transfer operation differs slightly, depending on the clock format specified by the SPI clock phase bit, CPHA, in SPI control register 1 (see Section 15.4.3, “Transmission Formats”). NOTE A change of the bits CPOL, CPHA, SSOE, LSBFE, XFRW, MODFEN, SPC0, or BIDIROE with SPC0 set, SPPR2-SPPR0 and SPR2-SPR0 in master mode will abort a transmission in progress and force the SPI into idle state. The remote slave cannot detect this, therefore the master must ensure that the remote slave is returned to idle state.
15.4.2 Slave Mode
The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear.
- Serial clock In slave mode, SCK is the SPI clock input from the master.
- MISO, MOSI pin In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI control register 2.
- S S pin The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI must be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is forced into idle state. The SS input also controls the serial data output pin, if SS is high (not selected), the serial data output pin is high impedance, and, if SS is low, the first bit in the SPI data register is driven out of the serial data output pin. Also, if the slave is not selected (SS is high), then the SCK input is ignored and no internal shifting of the SPI shift register occurs. Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin. NOTE When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave’s serial data output line.
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As long as no more than one slave device drives the system slave’s serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves. If the CPHA bit in SPI control register 1 is clear, odd numbered edges on the SCK input cause the data at the serial data input pin to be latched. Even numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data output pin. After the nth1 shift, the transfer is considered complete and the received data is transferred into the SPI data register. To indicate transfer is complete, the SPIF flag in the SPI status register is set. NOTE A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or BIDIROE with SPC0 set in slave mode will corrupt a transmission in progress and must be avoided.
15.4.3 Transmission Formats
During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. Optionally, on a master SPI device, the slave select line can be used to indicate multiple-master bus contention. Figure 15-11. Master/Slave Transfer Block Diagram
15.4.3.1 Clock Phase and Polarity Controls
Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase and polarity. 1. n depends on the selected transfer width, please refer to Section 15.3.2.2, “SPI Control Register 2 (SPICR2) SHIFT REGISTER SHIFT REGISTER BAUD RATE GENERATOR MASTER SPI SLAVE SPI MOSI MOSI MISO MISO SCK SCK SS SSVDD
Chapter 15 Serial Peripheral Interface (S12SPIV5) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 533 The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format. The CPHA clock phase control bit selects one of two fundamentally different transmission formats. Clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements.
15.4.3.2 CPHA = 0 Transfer Format
The first edge on the SCK line is used to clock the first data bit of the slave into the master and the first data bit of the master into the slave. In some peripherals, the first bit of the slave’s data is available at the slave’s data out pin as soon as the slave is selected. In this format, the first SCK edge is issued a half cycle after SS has become low. A half SCK cycle later, the second edge appears on the SCK line. When this second edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the shift register, depending on LSBFE bit. After this second edge, the next bit of the SPI master data is transmitted out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK line, with data being latched on odd numbered edges and shifted on even numbered edges. Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in. After 2n1 (last) SCK edges:
- Data that was previously in the master SPI data register should now be in the slave data register and the data that was in the slave data register should be in the master.
- The SPIF flag in the SPI status register is set, indicating that the transfer is complete. Figure 15-12 is a timing diagram of an SPI transfer where CPHA = 0. SCK waveforms are shown for CPOL = 0 and CPOL = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave and the MOSI signal is the output from the master. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI. 1. n depends on the selected transfer width, please refer to Section 15.3.2.2, “SPI Control Register 2 (SPICR2)
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Figure 15-12. SPI Clock Format 0 (CPHA = 0), with 8-bit Transfer Width selected (XFRW = 0) tL Begin End SCK (CPOL = 0) SAMPLE I CHANGE O SEL SS (O) Transfer SCK (CPOL = 1) MSB first (LSBFE = 0): LSB first (LSBFE = 1): MSB LSB LSB MSB Bit 5 Bit 2 Bit 6 Bit 1 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 CHANGE O SEL SS (I) MOSI pin MISO pin Master only MOSI/MISO tT If next transfer begins here for tT, tl, tL Minimum 1/2 SCK tI tL tL = Minimum leading time before the first SCK edge tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time) tL, tT, and tI are guaranteed for the master mode and required for the slave mode. 1 234 56 789 1 0 1 1 1 2 1 3 1 4 1 5 1 6SCK Edge Number End of Idle State Begin of Idle State
Chapter 15 Serial Peripheral Interface (S12SPIV5) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 535 Figure 15-13. SPI Clock Format 0 (CPHA = 0), with 16-Bit Transfer Width selected (XFRW = 1) In slave mode, if the SS line is not deasserted between the successive transmissions then the content of the SPI data register is not transmitted; instead the last received data is transmitted. If the SS line is deasserted for at least minimum idle time (half SCK cycle) between successive transmissions, then the content of the SPI data register is transmitted. In master mode, with slave select output enabled the SS line is always deasserted and reasserted between successive transfers for at least minimum idle time.
15.4.3.3 CPHA = 1 Transfer Format
Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin, the second edge clocks data into the system. In this format, the first SCK edge is issued by setting the CPHA bit at the beginning of the n1-cycle transfer operation. The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This first edge commands the slave to transfer its first data bit to the serial data input pin of the master. A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave. 1. n depends on the selected transfer width, please refer to Section 15.3.2.2, “SPI Control Register 2 (SPICR2) tL Begin End SCK (CPOL = 0) SAMPLE I CHANGE O SEL SS (O) Transfer SCK (CPOL = 1) MSB first (LSBFE = 0) LSB first (LSBFE = 1) MSB LSB LSB MSB Bit 13 Bit 2 Bit 14 Bit 1 Bit 12 Bit 3 Bit 11 Bit 4 Bit 5 CHANGE O SEL SS (I) MOSI pin MISO pin Master only MOSI/MISO tT If next transfer begins here for tT, tl, tL Minimum 1/2 SCK tI tL tL = Minimum leading time before the first SCK edge tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time) tL, tT, and tI are guaranteed for the master mode and required for the slave mode. 1 2 3 4 5 6 7 8 9 10111213141516SCK Edge Number End of Idle State Begin of Idle State 17181920212223242526272829303132 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 6Bit 5 Bit 7 Bit 8 Bit 9 Bit 10Bit 11Bit 12Bit 13Bit 14
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When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of n1 edges on the SCK line with data being latched on even numbered edges and shifting taking place on odd numbered edges. Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in. After 2n1 SCK edges:
- Data that was previously in the SPI data register of the master is now in the data register of the slave, and data that was in the data register of the slave is in the master.
- The SPIF flag bit in SPISR is set indicating that the transfer is complete. Figure 15-14 shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI. Figure 15-14. SPI Clock Format 1 (CPHA = 1), with 8-Bit Transfer Width selected (XFRW = 0) tL tT for tT, tl, tL Minimum 1/2 SCK tI tL If next transfer begins here Begin End SCK (CPOL = 0) SAMPLE I CHANGE O SEL SS (O) Transfer SCK (CPOL = 1) MSB first (LSBFE = 0): LSB first (LSBFE = 1): MSB LSB LSB MSB Bit 5 Bit 2 Bit 6 Bit 1 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 CHANGE O SEL SS (I) MOSI pin MISO pin Master only MOSI/MISO tL = Minimum leading time before the first SCK edge, not required for back-to-back transfers tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers 1 234 56 789 1 0 1 1 1 2 1 3 1 4 1 5 1 6SCK Edge Number End of Idle State Begin of Idle State
Chapter 15 Serial Peripheral Interface (S12SPIV5) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 537 Figure 15-15. SPI Clock Format 1 (CPHA = 1), with 16-Bit Transfer Width selected (XFRW = 1) The SS line can remain active low between successive transfers (can be tied low at all times). This format is sometimes preferred in systems having a single fixed master and a single slave that drive the MISO data line.
- Back-to-back transfers in master mode In master mode, if a transmission has completed and new data is available in the SPI data register, this data is sent out immediately without a trailing and minimum idle time. The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set one half SCK cycle after the last SCK edge.
15.4.4 SPI Baud Rate Generation
Baud rate generation consists of a series of divider stages. Six bits in the SPI baud rate register (SPPR2, SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the divisor to the SPI module clock which results in the SPI baud rate. The SPI clock rate is determined by the product of the value in the baud rate preselection bits (SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor equation is shown in Equation 15-3. tL Begin End SCK (CPOL = 0) SAMPLE I CHANGE O SEL SS (O) Transfer SCK (CPOL = 1) MSB first (LSBFE = 0) LSB first (LSBFE = 1) MSB LSB LSB MSB Bit 13 Bit 2 Bit 14 Bit 1 Bit 12 Bit 3 Bit 11 Bit 4 Bit 5 CHANGE O SEL SS (I) MOSI pin MISO pin Master only MOSI/MISO tT If next transfer begins here for tT, tl, tL Minimum 1/2 SCK tI tL tL = Minimum leading time before the first SCK edge, not required for back-to-back transfers tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers 1 2 3 4 5 6 7 8 9 10111213141516SCK Edge Number End of Idle State Begin of Idle State 17181920212223242526272829303132 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 6Bit 5 Bit 7 Bit 8 Bit 9 Bit 10Bit 11Bit 12Bit 13Bit 14
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BaudRateDivisor = (SPPR + 1) 2(SPR + 1) Eqn. 15-3 When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection bits (SPR2–SPR0) are 001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor becomes 4. When the selection bits are 010, the module clock divisor becomes 8, etc. When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When the preselection bits are 010, the divisor is multiplied by 3, etc. See Table 15-7 for baud rate calculations for all bit conditions, based on a 25 MHz bus clock. The two sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc. The baud rate generator is activated only when the SPI is in master mode and a serial transfer is taking place. In the other cases, the divider is disabled to decrease IDD current. NOTE For maximum allowed baud rates, please refer to the SPI Electrical Specification in the Electricals chapter of this data sheet.
15.4.5 Special Features
15.4.5.1 SS Output
The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin is connected to the SS input pin of the external device. The SS output is available only in master mode during normal SPI operation by asserting SSOE and MODFEN bit as shown in Table 15-3. The mode fault feature is disabled while SS output is enabled. NOTE Care must be taken when using the SS output feature in a multimaster system because the mode fault feature is not available for detecting system errors between masters.
15.4.5.2 Bidirectional Mode (MOMI or SISO)
The bidirectional mode is selected when the SPC0 bit is set in SPI control register 2 (see Table 15-11). In this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI.
Chapter 15 Serial Peripheral Interface (S12SPIV5) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 539 The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is configured as an output, serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift register.
- The SCK is output for the master mode and input for the slave mode.
- The SS is the input or output for the master mode, and it is always the input for the slave mode.
- The bidirectional mode does not affect SCK and SS functions. NOTE In bidirectional master mode, with mode fault enabled, both data pins MISO and MOSI can be occupied by the SPI, though MOSI is normally used for transmissions in bidirectional mode and MISO is not used by the SPI. If a mode fault occurs, the SPI is automatically switched to slave mode. In this case MISO becomes occupied by the SPI and MOSI is not used. This must be considered, if the MISO pin is used for another purpose.
15.4.6 Error Conditions
The SPI has one error condition:
- Mode fault error
15.4.6.1 Mode Fault Error
If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more than one master may be trying to drive the MOSI and SCK lines simultaneously. This condition is not permitted in normal operation, the MODF bit in the SPI status register is set automatically, provided the MODFEN bit is set. In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case Table 15-11. Normal Mode and Bidirectional Mode When SPE = 1 Master Mode MSTR = 1 Slave Mode MSTR = 0 Normal Mode SPC0 = 0 Bidirectional Mode SPC0 = 1 SPI MOSI MISO Serial Out Serial In SPI MOSI MISO Serial In Serial Out SPI MOMISerial Out Serial In BIDIROE SPI SISO Serial In Serial Out BIDIROE
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the SPI system is configured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur in slave mode. If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output buffer is disabled. So SCK, MISO, and MOSI pins are forced to be high impedance inputs to avoid any possibility of conflict with another output driver. A transmission in progress is aborted and the SPI is forced into idle state. If the mode fault error occurs in the bidirectional mode for a SPI system configured in master mode, output enable of the MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in the bidirectional mode for SPI system configured in slave mode. The mode fault flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to SPI control register 1. If the mode fault flag is cleared, the SPI becomes a normal master or slave again. NOTE If a mode fault error occurs and a received data byte is pending in the receive shift register, this data byte will be lost.
15.4.7 Low Power Mode Options
15.4.7.1 SPI in Run Mode
In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled state. SPI registers remain accessible, but clocks to the core of this module are disabled.
15.4.7.2 SPI in Wait Mode
SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI control register 2.
- If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode
- If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU is in wait mode. – If SPISWAI is set and the SPI is configured for master, any transmission and reception in progress stops at wait mode entry. The transmission and reception resumes when the SPI exits wait mode. – If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in progress continues if the SCK continues to be driven from the master. This keeps the slave synchronized to the master and the SCK. If the master transmits several bytes while the slave is in wait mode, the slave will continue to send out bytes consistent with the operation mode at the start of wait mode (i.e., if the slave is currently sending its SPIDR to the master, it will continue to send the same byte. Else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte).
Chapter 15 Serial Peripheral Interface (S12SPIV5) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 541 NOTE Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even though the shift register will continue to operate, the rest of the SPI is shut down (i.e., a SPIF interrupt will not be generated until exiting stop or wait mode). Also, the byte from the shift register will not be copied into the SPIDR register until after the slave SPI has exited wait or stop mode. In slave mode, a received byte pending in the receive shift register will be lost when entering wait or stop mode. An SPIF flag and SPIDR copy is generated only if wait mode is entered or exited during a tranmission. If the slave enters wait mode in idle mode and exits wait mode in idle mode, neither a SPIF nor a SPIDR copy will occur.
15.4.7.3 SPI in Stop Mode
Stop mode is dependent on the system. The SPI enters stop mode when the module clock is disabled (held high or low). If the SPI is in master mode and exchanging data when the CPU enters stop mode, the transmission is frozen until the CPU exits stop mode. After stop, data to and from the external SPI is exchanged correctly. In slave mode, the SPI will stay synchronized with the master. The stop mode is not dependent on the SPISWAI bit.
15.4.7.4 Reset
The reset values of registers and signals are described in Section 15.3, “Memory Map and Register Definition”, which details the registers and their bit fields.
- If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit garbage, or the data last received from the master before the reset.
- Reading from the SPIDR after re set will always read zeros.
15.4.7.5 Interrupts
The SPI only originates interrupt requests when SPI is enabled (SPE bit in SPICR1 set). The following is a description of how the SPI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt priority are chip dependent. The interrupt flags MODF, SPIF, and SPTEF are logically ORed to generate an interrupt request.
15.4.7.5.1 MODF
MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the MODF feature (see Table 15-3). After MODF is set, the current transfer is aborted and the following bit is changed:
- MSTR = 0, The master bit in SPICR1 resets. The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing process which is described in Section 15.3.2.4, “SPI Status Register (SPISR)”.
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15.4.7.5.2 SPIF
SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does not clear until it is serviced. SPIF has an automatic clearing process, which is described in Section 15.3.2.4, “SPI Status Register (SPISR)”.
15.4.7.5.3 SPTEF
SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process, which is described in Section 15.3.2.4, “SPI Status Register (SPISR)”.
MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductor 543 Chapter 16 High-Side Driver Module - HSDRV2C (HSDRV2CV3) Table 16-1. Revision History Table
16.1 Introduction
The HSDRV2C module provides two high-side drivers typically used to drive LED or resistive loads.
16.1.1 Features
The HSDRV2C module includes two independent high-side drivers with common high power supply. Each driver has the following features:
- Selectable gate control: HSDR[HSDRx] re gister bits or PWM or timer channels.
- Open-load detection.
- Slew rate control.
- Over-current shutdown, comprising of: — Interrupt flag generation — Driver shutdown Rev. No. (Item No.) Date (Submitted By) Sections Affected Substantial Change(s); V1.00 10 December 2010 All - Initial V2.00 07 Sep 2012 All - Added description and register bi ts for over-current masking feature V2.02 05 August 2013 All - Removed open-load detection feature V3.00 14 October 2013 All - Cleaning V3.02 12 February 2014 All - Added single channel configuration V3.03 12 February 2015 All - Clean-ups - Re-added opn-load detection feature - Added slew rate control feature V3.04 03 Mar 2015 All - Clean-ups
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— Optional masking window
16.1.2 Modes of Operation
The HSDRV2C module behaves as follows in the system power modes: 1. MCU run mode The activation of the HSCR[HSE0] or HSCR[HSE1] bits enable the related high-side drivers. The driver is controlled by the selected source. 2. MCU stop mode During stop mode operation the high-side drivers are shut down. That means the high-side drivers are disabled and the drivers are turned off. The bits in the data register which control the drivers (HSDR[1:0]) are cleared automatically. After returning from stop mode the drivers are re-enabled and the state of the HSCR[HSEx] bits is restored automatically. If the data register bits (HSDR[HSDRx]) are chosen as source in the PIM module, then the respective high-side driver stays turned off until the software sets the associated bit in the data register (HSDR[HSDRx]). When the timer or PWM are chosen as source, the respective high-side driver is controlled by the timer or PWM without further handling. When it is required that the driver stays turned off after the stop mode for this case (PWM or timer), the software must take the appropriate action to turn off the driver before entering stop mode.
16.1.3 Block Diagram
Figure 16-1 shows a block diagram of the HSDRV2C module. The module consists of a control and an output stage. The high-side driver gate control can be routed. See PIM chapter for routing options.
Chapter 16 High-Side Driver Module - HSDRV2C (HSDRV2CV3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 545 Figure 16-1. HSDRV2C Block Diagram
16.2 External Signal Description
Table 16-2 shows the external pins associated with the HSDRV2C module.
16.2.1 HS[0], HS[1] — Hi gh Side Driver Pins
Outputs of the two high-side drivers, intended to drive LEDs or resistive loads.
16.2.2 VSUPHS — High Si de Driver Power Pin
Power supply for the high-side driver. This pin must be connected to the main power supply with the appropriate reverse battery protection network.
16.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the HSDRV2C module. Table 16-2. HSDRV2C Signal Properties Name Function Reset State HS[1:0] High-side driver outputs 0, 1 disabled (off) VSUPHS High Voltage Power Supply for both high side drivers disabled (off) HS1 VSUPHS HS0 HS1 control HS0 control HS0 Open Load HS0 Over Current HS1 Over Current HS1 Open Load
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16.3.1 Module Memory Map
A summary of registers associated with the HSDRV2C module is shown in Table 16-3. Detailed descriptions of the registers and bits are given in the following sections. NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level. Table 16-3. Register Summary Address Offset Register Name B i t 7 654321 B i t 0 0x0000 HSDR R 000000 HSDR1 HSDR0W 0x0001 HSCR R0 0 HSOCME1 HSOCME0 HSOLE1 HSOLE0 HSE1 HSE0W 0x0002 HSSLR R0 0 0 0 HSSLCU1 HSSLCU0 HSSLEN1 HSSLEN0W 0x0003 Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedW 0x0004 Reserved R 00000000 W 0x0005 HSSR R 000000 H S O L 1 H S O L 0 W 0x0006 HSIE R HSOCIE 0000000 W 0x0007 HSIF R 000000 HSOCIF1 HSOCIF0W
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16.3.2 Register Definition
16.3.3 Port HS Data Register (HSDR)
16.3.4 HSDRV2C Configur ation Register (HSCR)
Module Base + 0x0000 Access: User read/write(1) 1. Read: Anytime The data source (HSDRx or alternate function) depends on the HSE control bit settings. Write: Anytime 76543210 R 000000 HSDR1 HSDR0 W Altern. Read Function 2. See PIM chapter for detailed routing description. OC2 R e s e t 00000000 = Unimplemented Figure 16-2. Port HS Data Register (HSDR) Table 16-4. Port HS Data Register (HSDR) Field Descriptions Field Description 1-0 HSDRx Port HS Data — Data register output or rout ed timer output or routed PWM output This register can be used to control the high-side drivers if selected as control source. See PIM section for routing details. If the associated HSCR[HSEx] bit is set to 0, a read returns the value of the Port HS Data Register (HSDR[HSDRx]). If the associated HSCR[HSEx] bit is set to 1, a read returns the value of the selected control source for the driver. When entering in STOP mode the Port HS Data Register (HSDR) is cleared.
0 High-side driver is turned off
1 High-side driver is turned on
Note: After enabling the high-side driver with the HSCR[HSEx] bit, software must wait for a minimum settling time tHS_settling before turning on the high-side driver. Module Base + 0x0001 Access: User read/write(1) 76543210 R0 0 HSOCME1 HSOCME0 HSOLE1 HSOLE0 HSE1 HSE0 W R e s e t 00000000 = Unimplemented Figure 16-3. HSDRV2C Configuration Register (HSCR)
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- Read: Anytime Write: Anytime, except HSOCME (see description) Table 16-5. HSDRV Configuration Register (HSCR) Field Descriptions Field Description 5-4 HSOCMEx HSDRV2C Over-Current Mask Enable These bits enable the masking of the over-current shutdown for tHSOCM for the related high-side driver, after switching on the driver. This bit is only writable if the associated high-side driver is disabled (HSCR[HSEx]=0) 0 over-current masking window is disabled 1 over-current masking window is enabled 3-2 HSOLEx HSDRV2C High-Load Resistance Open-Load Detection Enable These bits enable the measurement function to detect an open-load condition on the related high-side driver operating on high-load resistance loads. If the high-side driver is enabled and is not being driven by the selected source, then the high-load resistance detection circuit is activated when this bit is set to ‘1’. 0 high-load resistance open-load detection is disabled 1 high-load resistance open-load detection is enabled 1-0 HSEx HSDRV2C Enable These bits control the bias for the associated high-side driver circuit.
0 High-side driver is disabled
1 High-side driver is enabled
Note: After enabling the high-side driver (HSCR[HSEx]=1), a settling time tHS_settling is required before the high-side driver is allowed to be turned on (e.g. by writing to the HSDR).
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16.3.5 HSDRV2C Slew Rate Control Register (HSSLR)
Module Base + 0x0002 Access: User read/write(1) 1. Read: Anytime Write: Anytime, except HSSLCU, HSSLEN (see description) 76543210 R 0000 HSSLCU1 HSSLCU0 HSSLEN1 HSSLEN0 W R e s e t 00000000 = Unimplemented Figure 16-4. HSDRV2C Slew Rate Control Register (HSSLR) Table 16-6. HSDRV2C Slew Rate Control Register (HSSLR) Field Descriptions Field Description 3-2 HSSLCUx Slew Current Reduction Enable The maximum output current is reduced for ~4 us when the associated driver is switched on to reduce the emission if the high-side driver is used as an off-board driver.These bits are only writable if the associated high-side driver is disabled (HSCR[HSEx]=0)
0 Slew current reduction disabled
1 Slew current reduction enabled
The voltage slew rate is limited for ~8 us when the associated driver is switched on to reduce the emission if the high-side driver is used as an off-board driver. These bits are only writable if the associated high-side driver is disabled (HSCR[HSEx]=0)
0 Slew rate control disabled
1 Slew rate contol enabled
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16.3.6 Reserved Register
This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special mode can alter the module’s functionality. Module Base + 0x0003 Access: User read/write(1) 1. Read: Anytime Write: Only in special mode 76543210 R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W R e s e t xxxxxxxx = Unimplemented Figure 16-5. Reserved Register Table 16-7. Reserved Register Field Descriptions Field Description 7-0 Reserved These reserved bits are used for test purposes. Writing to these bits can alter the module functionality.
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16.3.7 HSDRV2C Status Register (HSSR)
16.3.8 HSDRV2C Interrupt Enable Register (HSIE)
Module Base + 0x0005 Access: User read(1) 1. Read: Anytime Write: No Write 76543210 R 000000 H S O L 1 H S O L 0 W R e s e t 00000000 = Unimplemented Figure 16-6. HSDRV2C Status Register (HSSR) Table 16-8. HSDRV Status Register (HSSR) Field Descriptions Field Description 1-0 HSOLx HSDRV2C Open-Load Status Bits These bits reflect the open-load condition of the associated the driver pin. A delay of tHLROLDT must be granted after enabling the high-load resistance open-load detection function in order to read valid data.
0 No open-load condition, IHS |IHLROLDC
1 Open-load condition, IHS IHLROLDC
Module Base + 0x0006 Access: User read/write(1) 1. Read: Anytime Write: Anytime 76543210 R HSOCIE 0000000 W R e s e t 00000000 = Unimplemented Figure 16-7. HSDRV2C Interrupt Enable Register (HSIE) Table 16-9. HSDRV Interrupt Enable Register (HSIE) Field Descriptions Field Description HSOCIE HSDRV2C Over-Current Interrupt Enable 1Interrupt is requested whenever a HSIF[HSOCIFx] flag is set
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16.3.9 HSDRV2C Interrupt Flag Register (HSIF)
16.4 Functional Description
16.4.1 General
The HSDRV2C module provides two high-side drivers able to drive LED or resistive loads. The drivers can be controlled directly through register bits or alternatively by dedicated timer or PWM channels. See PIM chapter for routing details. The following sub-section describes the open-load and over-current detection features for both drivers.
16.4.2 Open Load Detection
A “High-load resistance Open Load Detection” can be enabled for the driver by setting the associated HSCR[HSEOLx] bit (refer to Section 16.3.4, “HSDRV2C Configuration Register (HSCR)”. This detection is only active when the associated driver is enabled and it is not being driven. To detect an open- load condition a small current IHVOLDC will flow through the load. If the driving pin HS[x] stays at a voltage above an internal threshold then an open load will be detected for the associated high-side driver. The open-load condition is flagged in the HSDRV Status Register (HSSR). Module Base + 0x0007 Access: User read/write(1) 1. Read: Anytime Write: Write 1 to clear, writing 0 has no effect 76543210 R 000000 HSOCIF1 HSOCIF0 W R e s e t 00000000 = Unimplemented Figure 16-8. HSDRV2C Interrupt Flag Register (HSIF) Table 16-10. HSDRV Interrupt Flag Register (HSIF) Field Descriptions Field Description 1-0 HSOCIFx HSDRV2C Over-Current Interrupt Flags These flags are set when an over-current event occurs on the associated high-side driver (| IHS | > | IOCTHSX |). While set the associated high-side driver is turned off. Once the flag is cleared, the driver is controlled again by the source selected in PIM module.
0 No over-current event occurred since last clearing of flag
1 An over-current event occurred since last clearing of flag
Chapter 16 High-Side Driver Module - HSDRV2C (HSDRV2CV3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 553 NOTE The open-load detection is only active if the selected source (e.g. PWM, Timer, HSDR[HSDRx]) for the high-side driver is turned off.
16.4.3 Over-Current Shutdown
The high-side drivers have an over-current shutdown feature with a current threshold of IOCTHSX. If an over-current is detected the associated interrupt flag is set in the HSDRV2C Interrupt Flag Register (HSIF). As long as an over-current interrupt flag remains set, the associated high-side driver is turned off to protect the circuit. Clearing an over-current interrupt flag re-enables control of the associated high-side driver from the selected source in the PIM module.The over-current detection and driver shutdown can be masked for an initial THSOCM after switching the driver on. This can be achieved by setting the associated HSCR[HSOCMEx] register bit. HSCR[HSOCMEx] is only writable while the associated driver is disabled (HSCR[HSEx]=0).
16.4.4 Interrupts
This section describes the interrupt generated by HSDRV2C module. The interrupt is only available in MCU run mode. Entering and exiting MCU stop mode has no effect on the interrupt flags. The interrupt generated by HSDRV2C module is shown in Table 16-11. Vector addresses and interrupt priorities are defined at MCU level.
16.4.4.1 HSDRV2C Over Current Interrupt (HSOCI)
If an over-current is detected the related interrupt flag HSOCIFx asserts. Depending on the setting of the HSDRV2C Error Interrupt Enable (HSOCIE) bit an interrupt is requested. Table 16-11. HSDRV2C Interrupt Sources Module Interrupt Source Module Internal Interrupt Source Local Enable HSDRV2C Interrupt (HSI) HSDRV2C Over-C urrent Interrupt (HSOCI) HSOCIE = 1
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MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductor 555 Chapter 17 LIN Physical Layer (S12LINPHYV2) Table 17-1. Revision History Table
17.1 Introduction
The LIN (Local Interconnect Network) bus pin provides a physical layer for single-wire communication in automotive applications. The LIN Physical Layer is designed to meet the LIN Physical Layer 2.2 specification from LIN consortium.
17.1.1 Features
The LIN Physical Layer module includes the following distinctive features:
- Compliant with LIN Phys ical Layer 2.2 specification. Rev. No. (Item No.) Date (Submitted By) Sections Affected Substantial Change(s) V01.00 10 Dec 2010 All - Initial Version V02.00 25 June 2012 All - Added LIN TxD-dominant timeout feature V02.06 11 Jan 2013 All -Added application note to help the ISR development for the Interrupts (timeout and overcurrent) V02.08 10 Apr 2013 Register and interrupt descriptions, application section - Added notes regarding the correct handling of clearing LPOCIF and LPDTIF. V02.09 27 Jun 2013 Feature list - Added the SAE J2602-2 LIN compliance. V02.10 21 Aug 2013 Overcurrent and TxD-dominant timeout interrupt descriptions - Specified the time after which the interrupt flags are set again after having been cleared while the error condition is still present. V02.11 19 Sep 2013 All - Removed preliminary note. - Fixed grammar and spelling throughout the document. V02.12 20 Sep 2013 Standby Mode - Clarified Standby mode behavior. V02.13 8 Oct 2013 All - More grammar, spelling, and formating fixes throughout the document.
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- Compliant with the SAE J2602-2 LIN standard.
- Standby mode with glitch-filtered wake-up.
- Slew rate selection optimized for the baud ra tes: 10.4 kbit/s, 20 kbit/s and Fast Mode (up to 250 kbit/s).
- Switchable 34 k /330 k pullup resistors (in shutdown mode, 330 konly
- Current limitation for LI N Bus pin falling edge.
- Overcurrent protection.
- LIN TxD-dominant timeout featur e monitoring the LPTxD signal.
- Automatic transmitter shutdow n in case of an overcurrent or TxD-dominant timeout.
- Fulfills the OEM “Hardware Requi rements for LIN (CAN and FlexRay) Interfaces in Automotive Applications” v1.3. The LIN transmitter is a low-side MOSFET with current limitation and overcurrent transmitter shutdown. A selectable internal pullup resistor with a serial diode structure is integrated, so no external pullup components are required for the application in a slave node. To be used as a master node, an external resistor of 1 k must be placed in parallel between VLINSUP and the LIN Bus pin, with a diode between VLINSUP and the resistor. The fall time from recessive to dominant and the rise time from dominant to recessive is selectable and controlled to guarantee communication quality and reduce EMC emissions. The symmetry between both slopes is guaranteed.
17.1.2 Modes of Operation
The LIN Physical Layer can operate in the following four modes: 1. Shutdown Mode The LIN Physical Layer is fully disabled. No wake-up functionality is available. The internal pullup resistor is replaced by a high ohmic one (330 k) to maintain the LIN Bus pin in the recessive state. All registers are accessible. 2. Normal Mode The full functionality is available. Both receiver and transmitter are enabled. 3. Receive Only Mode The transmitter is disabled and the receiver is running in full performance mode. 4. Standby Mode The transmitter of the LIN Physical Layer is disabled. If the wake-up feature is enabled, the internal pullup resistor can be selected (330 k or 34 k). The receiver enters a low power mode and optionally it can pass wake-up events to the Serial Communication Interface (SCI). If the wake-up feature is enabled and if the LIN Bus pin is driven with a dominant level longer than tWUFR followed by a rising edge, the LIN Physical Layer sends a wake-up pulse to the SCI, which requests a wake-up interrupt. (This feature is only available if the LIN Physical Layer is routed to the SCI).
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17.1.3 Block Diagram
Figure 17-1 shows the block diagram of the LIN Physical Layer. The module consists of a receiver with wake-up control, a transmitter with slope and timeout control, a current sensor with overcurrent protection as well as a registers control block. Figure 17-1. LIN Physical Layer Block Diagram NOTE The external 220 pF capacitance between LIN and LGND is strongly recommended for correct operation.
17.2 External Signal Description
This section lists and describes the signals that connect off chip as well as internal supply nodes and special signals. /g1/g2/g3 /g4/g1/g5/g6/g7 /g4/g1/g8/g6/g7 /g4/g1/g7/g8/g9 /g5/g10/g11/g12/g13/g14/g15 /g16/g13/g17/g15/g18/g13/g19 /g20/g21/g22/g12/g23/g14/g24 /g16/g13/g17/g15/g18/g13/g19 /g5/g18/g21/g17/g25/g11/g10/g15/g15/g12/g18 /g8/g12/g26/g12/g10/g27/g12/g18 /g8 /g4/g2/g28/g1/g29/g30/g31/g16/g32/g28/g5/g8/g32/g4 /g33 /g4/g2/g28 /g34/g4/g2/g28/g35/g36/g1/g37 /g4/g38/g28/g7 /g39/g39/g40/g31/g24/g41 /g8/g12/g26/g13/g11/g11/g12/g17/g42/g12/g42 /g26/g43/g10/g24/g31/g12/g42/g44/g12 /g35/g19/g13/g24/g12 /g16/g13/g17/g15/g18/g13/g19 /g32/g27/g12/g18/g23/g26/g14/g18/g18/g12/g17/g15 /g16/g13/g17/g15/g18/g13/g19 /g1/g14/g19/g19/g23/g14/g24/g31 /g16/g13/g17/g15/g18/g13/g19 /g37/g5/g43/g12/g31/g34/g4/g2/g28/g35/g36/g1/g31/g25/g14/g24/g24/g19/g45/g31/g11/g21/g24/g24/g10/g17/g44/g31/g10/g25/g31/g42/g12/g25/g26/g18/g10/g46/g12/g42/g31/g10/g17/g31/g42/g12/g27/g10/g26/g12/g31/g19/g12/g27/g12/g19/g31/g42/g13/g26/g14/g11/g12/g17/g15/g21/g15/g10/g13/g17
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17.2.1 LIN — LIN Bus Pin
This pad is connected to the single-wire LIN data bus.
17.2.2 LGND — LIN Ground Pin
This pin is the device LIN ground connection. It is used to sink currents related to the LIN Bus pin. A de- coupling capacitor external to the device (typically 220 pF, X7R ceramic) between LIN and LGND can further improve the quality of this ground and filter noise.
17.2.3 VLINSUP — Positive Power Supply
External power supply to the chip. The VLINSUP supply mapping is described in device level documentation.
17.2.4 LPTxD — LIN Transmit Pin
This pin can be routed to the SCI, LPDR1 register bit, an external pin, or other options. Please refer to the PIM chapter of the device specification for the available routing options. This input is only used in normal mode; in other modes the value of this pin is ignored.
17.2.5 LPRxD — LIN Receive Pin
This pin can be routed to the SCI, an external pin, or other options. Please refer to the PIM chapter of the device specification for the available routing options. In standby mode this output is disabled, and sends only a short pulse in case the wake-up functionality is enabled and a valid wake-up pulse was received in the LIN Bus.
17.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the LIN Physical Layer.
17.3.1 Module Memory Map
A summary of the registers associated with the LIN Physical Layer module is shown in Table 17-2. Detailed descriptions of the registers and bits are given in the subsections that follow. NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level.
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17.3.2 Register Descriptions
This section describes all the LIN Physical Layer registers and their individual bits. Address Offset Register Name B i t 7 654321 B i t 0 0x0000 LPDR R 000000 LPDR1 LPDR0 W 0x0001 LPCR R 0000 LPE RXONLY LPWUE LPPUEW 0x0002 Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedW 0x0003 LPSLRM R LPDTDIS 00000 LPSLR1 LPSLR0W 0x0004 Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedW 0x0005 LPSR R L P D T 0000000 W 0x0006 LPIE R LPDTIE LPOCIE 000000 W 0x0007 LPIF R LPDTIF LPOCIF 000000 W Figure 17-2. Register Summary
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17.3.2.1 Port LP Data Register (LPDR)
Table 17-2. LPDR Field Description
17.3.2.2 LIN Control Register (LPCR)
Table 17-3. LPCR Field Description Module Base + Address 0x0000 Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R 000000 LPDR1 LPDR0 W R e s e t 00000011 = Unimplemented Figure 17-3. Port LP Data Register (LPDR) Field Description LPDR1 Port LP Data Bit 1 — The LIN Physical Layer LPTxD input (see Figure 17-1) can be directly controlled by this register bit. The routing of the LPTxD input is done in the Port Inetrgation Module (PIM). Please refer to the PIM chapter of the device Reference Manual for more info. LPDR0 Port LP Data Bit 0 — Read-only bit. The LIN Physical Layer LPRxD output state can be read at any time. Module Base + Address 0x0001 Access: User read/write (1) 1. Read: Anytime Write: Anytime, 76543210 R0 0 0 0 LPE RXONLY LPWUE LPPUEW R e s e t 00000000 = Unimplemented Figure 17-4. LIN Control Register (LPCR) Field Description LPE LIN Enable Bit — If set, this bit enables the LIN Physical Layer. 0 The LIN Physical Layer is in shutdown mode. None of the LIN Physical Layer functions are available, except that the bus line is held in its recessive state by a high ohmic (330k) resistor. All registers are normally accessible. 1 The LIN Physical Layer is not in shutdown mode. RXONLY Receive Only Mode bit — This bit controls RXONLY mode. 0 The LIN Physical Layer is not in receive only mode. 1 The LIN Physical Layer is in receive only mode.
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17.3.2.3 Reserved Register
This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special mode can alter the module’s functionality.
17.3.2.4 LIN Slew Rate Mode Register (LPSLRM)
LIN Wake-Up Enable — This bit controls the wake-up feature in standby mode. 0 In standby mode the wake-up feature is disabled. 1 In standby mode the wake-up feature is enabled. LPPUE LIN Pullup Resistor Enable — Selects pullup resistor. 0 The pullup resistor is high ohmic (330 k).
1 The 34 kpullup is switched on (except if LPE=0 or when in standby mode with LPWUE=0)
Module Base + Address 0x0002 Access: User read/write (1) 1. Read: Anytime Write: Only in special mode 76543210 R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W R e s e t xxxxxxxx = Unimplemented Figure 17-5. LIN Test register Table 17-4. Reserved Register Field Description Field Description 7-0 Reserved These reserved bits are used for test purposes. Writing to these bits can alter the module functionality. Module Base + Address 0x0003 Access: User read/write (1) 1. Read: Anytime Write: Only in shutdown mode (LPE=0) 76543210 R LPDTDIS 00000 LPSLR1 LPSLR0 W R e s e t 00000000 = Unimplemented Figure 17-6. LIN Slew Rate Mode Register (LPSLRM) Field Description
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Table 17-5. LPSLRM Field Description
17.3.2.5 Reserved Register
This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special mode can alter the module’s functionality. Table 17-6. Reserved Register Field Description Field Description LPDTDIS TxD-dominant timeout disable Bit — This bit disables t he TxD-dominant timeout feature. Disabling this feature is only recommended for using the LIN Physical Layer for other applications than LIN protocol. It is only writable in shutdown mode (LPE=0). 0 TxD-dominant timeout feature is enabled. 1 TxD-dominant timeout feature is disabled. 1-0 LPSLR[1:0] Slew-Rate Bits — Please see section Section 17.4.2, “Slew Rate and LIN Mode Selection for details on how the slew rate control works. These bits are only writable in shutdown mode (LPE=0). 00 Normal Slew Rate (optimized for 20 kbit/s). 01 Slow Slew Rate (optimized for 10.4 kbit/s). 10 Fast Mode Slew Rate (up to 250 kbit/s). This mode is not compliant with the LIN Protocol (LIN electrical characteristics like duty cycles, reference levels, etc. are not fulfilled). It is only meant to be used for fast data transmission. Please refer to section Section 17.4.2.2, “Fast Mode (not LIN compliant) for more details on fast mode.Please note that an external pullup resistor stronger than 1 k might be necessary for the range 100 kbit/s to 250 kbit/s. 11 Reserved . Module Base + Address 0x0004 Access: User read/write (1) 1. Read: Anytime Write: Only in special mode 76543210 R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W R e s e t xxxxxxxx = Unimplemented Figure 17-7. Reserved Register Field Description 7-0 Reserved These reserved bits are used for test purposes. Writing to these bits can alter the module functionality.
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17.3.2.6 LIN Status Register (LPSR)
17.3.2.7 LIN Interrupt Enable Register (LPIE)
Module Base + Address 0x0005 Access: User read/write (1) 1. Read: Anytime Write: Never, writes to this register have no effect 76543210 RL P D T 0 0 0 0 0 0 0 W R e s e t 00000000 = Unimplemented Figure 17-8. LIN Status Register (LPSR) Table 17-7. LPSR Field Description Field Description LPDT LIN Transmitter TxD-dominant timeout Status Bit — This read-only bit signals that the LPTxD pin is still dominant after a TxD-dominant timeout. As long as the LPTxD is dominant after the timeout the LIN transmitter is shut down and the LPTDIF is set again after attempting to clear it. 0 If there was a TxD-dominant timeout, LPTxD has ceased to be dominant after the timeout. 1 LPTxD is still dominant after a TxD-dominant timeout. Module Base + Address 0x0006 Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R LPDTIE LPOCIE 000000 W R e s e t 00000000 = Unimplemented Figure 17-9. LIN Interrupt Enable Register (LPIE)
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17.3.2.8 LIN Interrupt Fl ags Register (LPIF)
Table 17-9. LPIF Field Description Table 17-8. LPIE Field Description Field Description LPDTIE LIN transmitter TxD-dominant timeout Interrupt Enable — 0 Interrupt request is disabled. 1 Interrupt is requested if LPDTIF bit is set. LPOCIE LIN transmitter Overcurrent Interrupt Enable — 0 Interrupt request is disabled. 1 Interrupt is requested if LPOCIF bit is set. Module Base + Address 0x0007 Access: User read/write (1) 1. Read: Anytime Write: Writing ‘1’ clears the flags, writing a ‘0’ has no effect 76543210 R LPDTIF LPOCIF 000000 W R e s e t 00000000 = Unimplemented Figure 17-10. LIN Interrupt Flags Register (LPIF) Field Description LPDTIF LIN Transmitter TxD-dominant timeout Interrupt Flag — LPDTIF is set to 1 when LPTxD is still dominant (0) after tTDLIM of the falling edge of LPTxD. For protection, the transmitter is disabled. This flag can only be cleared by writing a 1. Writing a 0 has no effect. Please make sure that LPDTIF=1 before trying to clear it. Clearing LPDTIF is not allowed if LPDTIF=0 already. If the LPTxD is still dominant after clearing the flag, the transmitter stays disabled and this flag is set again (see 17.4.4.2 TxD-dominant timeout Interrupt). If interrupt requests are enabled (LPDTIE= 1), LPDTIF causes an interrupt request. 0 No TxD-dominant timeout has occurred. 1 A TxD-dominant timeout has occurred. LPOCIF LIN Transmitter Overcurrent Interrupt Flag — LPOCIF is set to 1 when an overcurrent event happens. For protection, the transmitter is disabled. This flag can only be cleared by writing a 1. Writing a 0 has no effect. Please make sure that LPOCIF=1 before trying to clear it. Clearing LPOCIF is not allowed if LPOCIF=0 already. If the overcurrent is still present or LPTxD is dominant after clearing the flag, the transmitter stays disabled and this flag is set again (see17.4.4.1 Overcurrent Interrupt). If interrupt requests are enabled (LPOCIE= 1), LPOCIF causes an interrupt request. 0 No overcurrent event has occurred. 1 Overcurrent event has occurred.
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17.4 Functional Description
17.4.1 General
The LIN Physical Layer module implements the physical layer of the LIN interface. This physical layer can be driven by the SCI (Serial Communication Interface) module or directly through the LPDR register.
17.4.2 Slew Rate and LIN Mode Selection
The slew rate can be selected for Electromagnetic Compatibility (EMC) optimized operation at 10.4 kbit/s and 20 kbit/s as well as at fast baud rate (up to 250 kbit/s) for test and programming. The slew rate can be chosen with the bits LPSLR[1:0] in the LIN Slew Rate Mode Register (LPSLRM). The default slew rate corresponds to 20 kbit/s. The LIN Physical Layer can also be configured to be used for non-LIN applications (for example, to transmit a PWM pulse) by disabling the TxD-dominant timeout (LPDTDIS=1). Changing the slew rate (LPSLRM Register) during transmission is not allowed in order to avoid unwanted effects. To change the register, the LIN Physical Layer must first be disabled (LPE=0). Once it is updated the LIN Physical Layer can be enabled again. NOTE For 20 kbit/s and Fast Mode communication speeds, the corresponding slew rate MUST be set; otherwise, the communication is not guaranteed (violation of the specified LIN duty cycles). For 10.4 kbit/s, the 20 kbit/s slew rate can be set but the EMC performance is worse. The up to 250 kbit/s slew rate must be chosen ONLY for fast mode, not for any of the 10.4 kbit/s or 20 kbit/s LIN compliant communication speeds. 17.4.2.1 10.4 kbit/s and 20 kbit/s When the slew rate is chosen for 10.4 kbit/s or 20 kbit/s communication, a control loop is activated within the module to make the rise and fall times of the LIN bus independent from VLINSUP and the load on the bus.
17.4.2.2 Fast Mode (not LIN compliant)
Choosing this slew rate allows baud rates up to 250 kbit/s by having much steeper edges (please refer to electricals). As for the 10.4 kbit/s and 20 kbit/s modes, the slope control loop is also engaged. This mode is used for fast communication only, and the LIN electricals are not supported (for example, the LIN duty cycles). A stronger external pullup resistor might be necessary to sustain communication speeds up to 250 kbit/s. The LIN signal (and therefore the receive LPRxD signal) might not be symmetrical for high baud rates with high loads on the bus.
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Please note that if the bit time is smaller than the parameter tOCLIM (please refer to electricals), then no overcurrent is reported nor does an overcurrent shutdown occur. However, the current limitation is always engaged in case of a failure.
17.4.3 Modes
Figure 17-11 shows the possible mode transitions depending on control bits, stop mode, and error conditions.
17.4.3.1 Shutdown Mode
The LIN Physical Layer is fully disabled. No wake-up functionality is available. The internal pullup resistor is high ohmic only (330 k) to maintain the LIN Bus pin in the recessive state. LPTxD is not monitored in this mode for a TxD-dominant timeout. All the registers are accessible. Setting LPE causes the module to leave the shutdown mode and to enter the normal mode or receive only mode (if RXONLY bit is set). Clearing LPE causes the module to leave the normal or receive only modes and go back to shutdown mode.
17.4.3.2 Normal Mode
The full functionality is available. Both receiver and transmitter are enabled. The internal pullup resistor can be chosen to be high ohmic (330 k) if LPPUE = 0, or LIN compliant (34 k if LPPUE = 1. If RXONLY is set, the module leaves normal mode to enter receive only mode. If the MCU enters stop mode, the LIN Physical Layer enters standby mode.
17.4.3.3 Receive Only Mode
Entering this mode disables the transmitter and immediately stops any on-going transmission. LPTxD is not monitored in this mode for a TxD-dominant timeout. The receiver is running in full performance mode in all cases. To return to normal mode, the RXONLY bit must be cleared. If the device enters stop mode, the module leaves receive only mode to enter standby mode.
17.4.3.4 Standby Mode with Wake-Up Feature
The transmitter of the LIN Physical Layer is disabled and the receiver enters a low power mode. NOTE Before entering standby mode, ensure no transmissions are ongoing. If LPWUE is not set, no wake up feature is available and the standby mode has the same electrical properties as the shutdown mode. This allows a low-power consumption of the device in stop mode if the wake-up feature is not needed.
Chapter 17 LIN Physical Layer (S12LINPHYV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 567 If LPWUE is set the receiver is able to pass wake-up events to the SCI (Serial Communication Interface). If the LIN Physical Layer receives a dominant level longer than tWUFR followed by a rising edge, it sends a pulse to the SCI which can generate a wake-up interrupt. Once the device exits stop mode, the LIN Physical Layer returns to normal or receive only mode depending on the status of the RXONLY bit. NOTE Since the wake-up interrupt is requested by the SCI, the wake-up feature is not available if the SCI is not used. The internal pullup resistor is selectable only if LPWUE = 1 (wake-up enabled). If LPWUE = 0, the internal pullup resistor is not selectable and remains at 330 k regardless of the state of the LPPUE bit. If LPWUE = 1, selecting the 330 k pullup resistor (LPPUE = 0) reduces the current consumption in standby mode. NOTE When using the LIN wake-up feature in combination with other non-LIN device wake-up features (like a periodic time interrupt), some care must be taken. If the device leaves stop mode while the LIN bus is dominant, the LIN Physical Layer returns to normal or receive only mode and the LIN bus is re-routed to the RXD pin of the SCI and triggers the edge detection interrupt (if the interrupt’s priority of the hardware that awakes the MCU is less than the priority of the SCI interrupt, then the SCI interrupt will execute first). It is up to the software to decide what to do in this case because the LIN Physical Layer can not guarantee it was a valid wake-up pulse.
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Figure 17-11. LIN Physical Layer Mode Transitions /g1/g2/g3/g2/g4 /g1/g2/g3/g4/g5/g6/g7/g8 /g5/g6/g7/g8/g9/g10/g10 /g1/g6/g7/g8/g9/g10/g10 /g11/g12/g13/g8/g14/g15/g16/g16/g15/g14/g7/g8/g17/g2/g18/g19 /g9/g6/g10/g11/g12/g13 /g11/g20/g21/g8/g22/g23/g24/g8/g1/g6/g9/g13/g11/g25/g22/g26 /g14/g15/g16/g15/g17/g18/g15/g19/g20/g8/g13/g21 /g1/g6/g9/g13/g11/g25/g22/g23 /g5/g6/g7/g8/g9/g27 /g1/g6/g7/g8/g9/g27/g8/g28/g10/g15/g16/g16/g8/g14/g2/g29/g10/g30/g29/g31/g18/g27/g32/g2/g33 /g11/g12/g13/g8/g14/g15/g16/g16/g15/g14/g7/g8/g17/g2/g18/g19/g8/g28/g11/g20/g20/g34/g21/g8/g22/g8/g26/g33 /g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g35/g4/g29/g30/g27/g36/g8/g28/g11/g20/g20/g34/g21/g8/g22/g23/g33 /g5/g6/g7/g8/g9/g10/g10 /g1/g6/g7/g8/g9/g27/g8/g28/g10/g15/g16/g16/g8/g14/g2/g29/g10/g30/g29/g31/g18/g27/g32/g2/g33 /g11/g12/g13/g8/g14/g15/g16/g16/g15/g14/g7/g8/g17/g2/g18/g19/g8/g28/g11/g20/g20/g34/g21/g8/g22/g8/g26/g33 /g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g35/g4/g29/g30/g27/g36/g8/g28/g11/g20/g20/g34/g21/g8/g22/g23/g33 /g1/g4/g12/g8/g5/g22/g21 /g35/g5 /g9/g20/g22/g23 /g5/g6/g7/g8/g9/g10/g10 /g1/g6/g7/g8/g9/g27/g8/g28/g11/g20/g17/g34/g21/g8/g22/g8/g23/g33/g8/g28/g16/g30/g37/g8/g14/g30/g37/g2/g29/g33 /g8/g8/g8/g8/g8/g8/g8/g9/g10/g10/g8/g28/g11/g20/g17/g34/g21/g8/g22/g8/g26/g33 /g11/g12/g13/g8/g14/g15/g16/g16/g15/g14/g7/g8/g17/g2/g18/g19/g8/g28/g11/g20/g20/g34/g21/g8/g22/g8/g26/g33 /g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g8/g35/g4/g29/g30/g27/g36/g8/g28/g11/g20/g20/g34/g21/g8/g22/g23/g33 /g5/g6/g8/g5/g29/g18/g27/g3/g31/g38/g4/g4/g2/g29 /g1/g6/g8/g1/g2/g32/g2/g38/g39/g2/g29 /g11/g20/g21/g22/g26 /g11/g20/g21/g22/g26 /g11/g20/g21/g22/g23/g24/g8/g1/g6/g9/g13/g11/g25/g22/g23 /g1/g6/g9/g13/g11/g25/g22/g26 /g35/g5 /g9/g20/g22/g26/g24/g8/g1/g6/g9/g13/g11/g25/g22/g23 /g35/g5 /g9/g20/g22/g23 /g35/g5 /g9/g20/g22/g26/g24/g8/g1/g6/g9/g13/g11/g25/g22/g26
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17.4.4 Interrupts
The interrupt vector requested by the LIN Physical Layer is listed in Table 17-10. Vector address and interrupt priority is defined at the MCU level. The module internal interrupt sources are combined into a single interrupt request at the device level.
17.4.4.1 Overcurrent Interrupt
The transmitter is protected against overcurrent. In case of an overcurrent condition occurring within a time frame called tOCLIM starting from LPTxD falling edge, the current through the transmitter is limited (the transmitter is not shut down). The masking of an overcurrent event within the time frame tOCLIM is meant to avoid “false” overcurrent conditions that can happen during the discharging of the LIN bus. If an overcurrent event occurs out of this time frame, the transmitter is disabled and the LPOCIF flag is set. In order to re-enable the transmitter again, the following prerequisites must be met: 1) Overcurrent condition is over 2) LPTxD is recessive or the LIN Physical Layer is in shutdown or receive only mode for a minimum of a transmit bit time. To re-enable the transmitter then, the LPOCIF flag must be cleared (by writing a 1). NOTE Please make sure that LPOCIF=1 before trying to clear it. It is not allowed to try to clear LPOCIF if LPOCIF=0 already. After clearing LPOCIF, if the overcurrent condition is still present or the LPTxD pin is dominant while being in normal mode, the transmitter remains disabled and the LPOCIF flag is set again after a time to indicate that the attempt to re-enable has failed. This time is equal to:
- minimum 1 IRC period (1 us) + 2 bus periods
- maximum 2 IRC period s (2 us) + 3 bus periods If the bit LPOCIE is set in the LPIE register, an interrupt is requested. Figure 17-12 shows the different scenarios for overcurrent interrupt handling. Table 17-10. Interrupt Vectors Module Interrupt Source Module Internal Interrupt Source Local Enable LIN Interrupt (LPI) LIN Txd-Dominant Timeout Interrupt (LPDTIF) LPDTIE = 1 LIN Overcurrent Interrupt (LPOCIF) LPOCIE = 1
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Figure 17-12. Overcurrent interrupt handling
17.4.4.2 TxD-dominan t timeout Interrupt
To protect the LIN bus from a network lock-up, the LIN Physical Layer implements a TxD-dominant timeout mechanism. When the LPTxD signal has been dominant for more than tDTLIM the transmitter is disabled and the LPDT status flag and the LPDTIF interrupt flag are set. In order to re-enable the transmitter again, the following prerequisites must be met: 1) TxD-dominant condition is over (LPDT=0) 2) LPTxD is recessive or the LIN Physical Layer is in shutdown or receive only mode for a minimum of a transmit bit time To re-enable the transmitter then, the LPDTIF flag must be cleared (by writing a 1). NOTE Please make sure that LPDTIF=1 before trying to clear it. It is not allowed to try to clear LPDTIF if LPDTIF=0 already. /g1/g2/g3/g4/g5 /g1/g6/g7 /g8/g9/g10/g11/g12/g13/g14/g11/g11/g10/g15/g16 /g1/g2/g17/g18/g6/g19 /g16/g20/g21/g20/g16/g17/g18/g1/g6/g22 /g23/g24 /g23/g24 /g23/g24 /g25 /g26/g27 /g25/g28/g20/g19/g29/g30/g31/g20/g13/g29/g10/g30/g11/g10/g32/g33/g20/g16/g11/g30/g15/g23/g34/g35/g16/g16/g10/g11/g20/g11/g10/g12/g10/g15/g30/g36/g29/g10/g20/g15/g8/g16/g20/g23/g14/g13/g13/g10/g23/g23/g37/g14/g29/g20/g36/g10/g13/g30/g14/g23/g10/g20/g8/g9/g10/g11/g12/g13/g14/g11/g11/g10/g15/g16/g20/g35/g23/g20/g23/g16/g35/g29/g29/g20/g38/g11/g10/g23/g10/g15/g16 /g26/g28/g20/g19/g29/g30/g31/g20/g13/g29/g10/g30/g11/g10/g32/g33/g20/g16/g11/g30/g15/g23/g34/g35/g16/g16/g10/g11/g20/g11/g10/g12/g10/g15/g30/g36/g29/g10/g20/g15/g8/g16/g20/g23/g14/g13/g13/g10/g23/g23/g37/g14/g29/g20/g36/g10/g13/g30/g14/g23/g10/g20/g1/g2/g3/g4/g5/g20/g35/g23/g20/g32/g8/g34/g35/g15/g30/g15/g16 /g27/g28/g20/g19/g29/g30/g31/g20/g13/g29/g10/g30/g11/g10/g32/g33/g20/g16/g11/g30/g15/g23/g34/g35/g16/g16/g10/g11/g20/g11/g10/g12/g10/g15/g30/g36/g29/g10/g20/g23/g14/g13/g13/g10/g23/g23/g37/g14/g29
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17.5 Application Information
17.5.1 Module Initialization
The following steps should be used to configure the module before starting the transmission: 1. Set the slew rate in the LPSLRM regist er to the desired transmission baud rate. 2. When using the LIN Physical Layer for other purposes than LIN transmission, de-activate the dominant timeout feature in the LPSLRM register if needed. 3. In most cases, the internal pullup s hould be enabled in the LPCR register. 4. Route the desired source in the PI M module to the LIN Physical Layer. 5. Select the transmit mode (Receive only m ode or Normal mode) in the LPCR register. 6. If the SCI is selected as source , activate the wake-up feature in the LPCR register if needed for the application (SCI active edge interrupt must also be enabled). 7. Enable the LIN Physical Layer in the LPCR register. 8. Wait for a minimum of a transmit bit. 9. Begin transmission if needed. NOTE It is not allowed to try to clear LPOCIF or LPDTIF if they are already cleared. Before trying to clear an error flag, always make sure that it is already set.
17.5.2 Interrupt handling in In terrupt Service Routine (ISR)
Both interrupts (TxD-dominant timeout and overcurrent) represent a failure in transmission. To avoid more disturbances on the transmission line, the transmitter is de-activated in both cases. The interrupt subroutine must take care of clearing the error condition and starting the routine that re-enables the transmission. For that purpose, the following steps are recommended: 1. First, the cause of the interrupt must be cleared: — The overcurrent will be gone after the transmitter has been disabled. — The TxD-dominant timeout condition will be go ne once the selected source for LPTxD has turned recessive. 2. Clear the corresponding enable bit (LPDTIE or LP OCIE) to avoid entering the ISR again until the flags are cleared. 3. Notify the application of the error condi tion (LIN Error handler) and leave the ISR. In the LIN Error handler, the following sequence is recommended: 1. Disable the LIN Physical Layer (LPCR) while re-configuring the transmission. — If the receiver must remain enabled, set the LI N Physical Layer into receive only mode instead. 2. Do all required configurations (SCI , etc.) to re-enable the transmission. 3. Wait for a transmit bit (this is needed to successfully re-enable the transmitter). 4. Clear the error flag.
Chapter 17 LIN Physical Layer (S12LINPHYV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 573 5. Enable the interrupts again (LPDTIE and LPOCIE). 6. Enable the LIN Physical Layer or leav e the receive only mode (LPCR register). 7. Wait for a minimum of a transmit bit before beginning transmission again. If there is a problem re-enabling the transmitter, then the error flag will be set again during step 3 and the ISR will be called again.
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MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductor 575 Chapter 18 Gate Drive Unit (GDU2PHV2)
18.1 Introduction
The GDU2PH module is a Field Effect Transistor (FET) pre-driver designed for two phase motor control applications.
18.1.1 Features
The GDU2PH module includes these distinctive features:
- 11V voltage regulator for FET pre-drivers
- 2-phase bridge FET pre-drivers
- Bootstrap circuit for high-side FET pre-dr ivers with external bootstrap capacitor
- Charge pump for static hi gh-side driver operation
- Phase voltage measurement with internal ADC
- Low-side current measurement amplifiers for DC phase current measurement
- V oltage measurement on GHD pin (D C-Link voltage) with internal ADC
- Desaturation comparator for high-side drivers and low-side drivers protection
- Undervoltage detection on F ET pre-driver supply pin VLS
- Overcurrent comparators with programmable voltage threshold
- Overvoltage detection on 2- phase bridge supply GHD pin
18.1.2 Modes of Operation
The GDU2PH module behaves as follows in the system power modes: 1. Run mode Table 18-1. Revision History Table Version Number Revision Date Description of Changes V02.00 29-July-2016 Added Note to Figure 18-1 and 18.2.5/18-578 on VLS pin. V02.01 16-Sep-2016 Global renami ng of HD pin to GHD Corrected pin names in Table 18-9.
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All features are available. 2. Wait mode All features are available. 3. Stop mode The GDU2PH is disabled in stop mode. The high-side drivers, low-side drivers, charge pump, voltage regulator and current sense amplifier are switched off. The GDU will weakly pull the gates of the MOSFET to their source potential. On entering stop mode the GDUE register bits are cleared. GFDE=0, GCPE=0 and GCSE0=0. NOTE The device does not support putting the MOSFET in specific state during stop mode as GDU charge pump clock is not running. This means device can not be put in stop mode if FETs needs to be in specific state to protect the system.
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18.1.3 Block Diagram
Figure 18-1 shows a block diagram of the GDU2PH module. 1 1. On some devices VLS[1] and VLS[0] are connected together internally and routed to a single VLS pin. The device overview information specifies if a single VLS pin or VLS[1:0] are featured. VBS[2:0] GHG[1:0] GHS[1:0] VLS[1:0] GLG[1:0] GLS[1:0] CP VCP GHD VSUP VLS_OUT AMP AMPM AMPP Charge Pump Current Sense Amplifiers Voltage Regulator Register Level Shifters FET Pre-Drivers Control Error ADC Channels PWM Channels IP Bus
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Figure 18-1. GDU Block Diagram
18.2 External Signal Description
18.2.1 GHD — High-Sid e Drain Connection
This pin is the power supply for the 2-phase bridge (DC-link voltage). NOTE The GHD pin should be connected as near as possible to the drain connections of the high-side MOSFETs.
18.2.2 VBS[1:0] — Bootstrap Capacitor Connection Pins
These pins are the bootstrap capacitor connections for phases GHS[1:0]. The capacitor is connected between GHS[1:0] and this pin. The bootstrap capacitor provides the gate voltage and current to drive the gate of the external power FET.
18.2.3 GHG[1:0] — High-Side Gate Pins
These pins are the gate drives for the high-side power FETs. The drivers provide a high current with low impedance to turn on and off the high-side power FETs.
18.2.4 GHS[1:0] — High-Side Source Pins
These pins are the source connection for the high-side power FETs and the drain connection for the low- side power FETs. The low voltage end of the bootstrap capacitor is also connected to this pin.
18.2.5 VLS[1:0] — Voltage Supply for Low-Side Pre-Drivers
These pins are the voltage supply pins for the two low-side FET pre-drivers. These pins should be connected to the voltage regulator output pin VLS_OUT. The output voltage on VLS_OUT pin is typically VVLS=11V. On some devices VLS[1] and VLS[0] are connected together internally and routed to a single VLS pin. The device overview information specifies if a single VLS pin or VLS[1:0] are featured. NOTE It is recommended to add a 110nF-220nF X7R ceramic capacitor close to each VLS pin.
18.2.6 GLG[1:0] — Low-Side Gate Pins
These pins are the gate drives for the low-side power FETs. The drivers provide a high current with low impedance to turn on and off the the low-side power FETs.
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18.2.6.1 GLS[1:0] — Lo w-Side Source Pins
These pins are the low-side source connections for the low-side power FETs. The pins are the power ground pins used to return the gate currents from the low-side power FETs.
18.2.6.2 AMPP — Current Sense Am plifier Non-Inverting Input Pin
The pin is the non-inverting input to the current sense amplifier.
18.2.6.3 AMPM — Current Sense Amplifier Inverting Input Pin
The pin is the inverting input to the current sense amplifiers.
18.2.6.4 AMP — Current Se nse Amplifier Output Pin
The pin is the output of the current sense amplifier. At the MCU level this pin is shared with an ADC channel. For ADC channel assignment, see MCU pinout section.
18.2.6.5 CP — Charge Pump Output Pin
This pin is the switching node of the charge pump circuit. The supply voltage for charge pump driver is the output of the voltage regulator VVLS. The output voltage of this pin switches typically between 0V and 11V.
18.2.6.6 VCP — Charge Pump Input for High-Side Driver Supply
This pin is the charge pump input for the high-side FET pre-driver supply VBS[2:0].
18.2.6.7 VSUP — Battery Vo ltage Supply Input Pin
This pin should be connected to the battery voltage. It is the input voltage to the integrated voltage regulator. The output of the voltage regulator is pin VLS_OUT.
18.2.6.8 VLS_OUT — Voltag e Regulator Output Pin
This pin is the output of the integrated voltage regulator. The ouput voltage is typically VVLS=11V. The input voltage to the voltage regulator is the VSUP pin. NOTE A 4.7uF or 10uF capacitor should be connected to this pin for stability of the the voltage regulator output.
18.3 Memory Map and Register Definition
This section provides the detailed information of all registers for the GDU2PH module.
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18.3.1 Register Summary
Figure 18-2 shows the summary of all implemented registers inside the GDU2PH module. NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level. Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 GDUE R GWP GOVA 000 GCSE0 GCPE GFDEW 0x0001 GDUCTR R GHHDLVL GVLSLVL GBKTIM 2[3:0] GBKTIM1[1:0] W 0x0002 GDUIE R 0 0 0 0 GOCIE0 GDSEIE GHHDIE GLVLSIEW 0x0003 GDUDSE R0 0 GDHSIF[1:0] 00 GDLSIF[1:0] W 0x0004 GDUSTAT R 0 GPHS[1:0] 0 GOCS0 0 GHHDS GLVLSS W 0x0005 GDUSRC GSRCHS[2:0] GSRCLS[2:0]W 0x0006 GDUF R GSUF GHHDF GLVLSF GOCIF0 GHHDIF GLVLSIFW 0x0007 Reserved R 00000000 W 0x0008 Reserved R 00000000 W 0x0009 GDUPHMUX R 000000 GPHMX[1:0]W 0x000A GDUCSO R 00000 GCSO0[2:0]W 0x000B GDUDSLVL R GDSFHS GDSLHS[2:0] GDSFLS GDSLLS[2:0] W = Unimplemented Figure 18-2. GDU Register Summary
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18.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Unused bits read back zero. 0x000C GDUPHL R 0 0 0 0 0 0 GPHL[1:0] W 0x000D GDUCLK2 R0 0 0 0 GCPCD[3:0]W 0x000E GDUOC0 R GOCA0 GOCE0 GOCT0[4:0]W 0x000F Reserved R 00000000 W 0x0010 GDUCTR1 R 00000 GBSWOFF[1:0] TDELW 0x0011- 0x001F 00000000 Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented Figure 18-2. GDU Register Summary
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18.3.2.1 GDU Module Enable Register (GDUE)
Module Base + 0x0000 Access: User read/write (1) 1. Read: Anytime Write: Anytime, write protected bits only if GWP=0. On entry in stop mode bits GCSE0, GCPE and GFDE are cleared. After exit from stop mode write protected bits GCPE and GFDE can be written once when GWP=1. 76543210 R GWP GOVA 000 GCSE0 GCPE GFDE W R e s e t 00000001 = Unimplemented Figure 18-3. GDU Module Enable Register (GDUE) Table 18-2. GDUE Register Field Description Field Description GWP GDU Write Protect— This bit enables write protection to be used for the write protectable bits. While clear, GWP allows write protectable bits to be written. When set GWP prevents any further writes to write protectable bits. Once set , GWP is cleared by reset.
0 Write-protectable bits may be written
1 Write-protectable bits cannot be written
GDU Overvoltage Action — This bit cannot be modified after GWP bit is set. 0 If an overvoltage condition on GHD pin occurs and GHHDF is set the high-side FET pre-drivers are turned off and the low-side FET pre-drivers are turned on. 1 If an overvoltage condition on GHD pin occurs and GHHDF is set the high-side FET pre-drivers and the low- side FET pre-drivers are turned off. GCSE0 GDU Current Sense Amplifier 0 Enable— This bit enables the current sense amplifier. See Section 18.4.8, “Current Sense Amplifier and Overcurrent Comparator
0 Current sense amplifier 0 is disabled
1 Current sense amplifier 0 is enabled
GDU Charge Pump Enable — This bit enables the charge pump. This bit cannot be modified after GWP bit is set. See Section 18.4.4, “Charge Pump
0 Charge pump is disabled
1 Charge pump is enabled
GDU FET Pre-Driver Enable — This bit enables the low-side and high-side FET pre-drivers. This bit cannot be Pre-Driver.
0 Low-side and high-side drivers are disabled
1 Low-side and high-side drivers are enabled
It is not allowed to set and clear GFDE bit periodically in order to switch on and off the FET pre-drivers. In order to switch on and off the FET pre-drivers the PMF module has to be used to mask and un-mask the PWM channels.
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18.3.2.2 GDU Control Register (GDUCTR)
The register bits GBKTIM1 and GBKTIM2 must be set to the required values before the PWM channel is activated. Once the PWM channel is activated, the value of GBKTIM1 & GBKTIM2 must not change. If a different blanking time is required, the PWM channel has to be turned off before new values to GBKTIM1 & GBKTIM2 are written. Module Base + 0x0001 Access: User read/write (1) 1. Read: Anytime Write: Only if GWP=0 76543210 R GHHDLVL GVLSLVL GBKTIM2[3:0] GBKTIM1[1:0] W R e s e t 01010000 = Unimplemented Figure 18-4. GDU2PH Control Register (GDUCTR) Table 18-3. GDUCTR Register Field Descriptions Field Description GHHDLVL GDU High GHD Level Select — Selects the voltage threshold of th e overvoltage detection on GHD pin. This bit cannot be modified after GWP bit is set.
0 Voltage thresholds of the overvoltage detection on GHD pin configured for VHVHDLA and VHVHDLD
1 Voltage thresholds of the overvoltage detection on GHD pin configured for VHVHDHA and VHVHDHD
(Not featured on GDUV4) GDU VLS Level Select — Selects the voltage threshold of the undervoltage detection on VLS pin. This bit cannot be modified after GWP bit is set.
0 Voltage thresholds of the undervoltage detection on VLS pin configured for V LVLSLA and VLVLSLD
1 Voltage thresholds of the undervoltage detection on VLS pin configured for V LVLSHA and VLVLSHD
GBKTIM2[3:0] GDU Blanking Time — These bits adjust the blanking time t BLANK of the desaturation error comparators. The resulting blanking time tBLANK can be calculated from the equation below. For GBKTIM2[3:0]=$F no desaturation errors are captured and the drivers are unprotected and the charge pump will not connect to the high-side drivers. These bits cannot be modified after GWP bit is set. 1-0 GBKTIM1[1:0] GDU Blanking Time — These bits adjust the blanking time t BLANK of the desaturation error comparators. The resulting blanking time tBLANK can be calculated from the equation in the field description below.These bits cannot be modified after GWP bit is set. tBLANK GBKTIM2 1+ · 2GBKTIM1 1+ 2+ TBUS=
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18.3.2.3 GDU Interrupt Enable Register (GDUIE)
18.3.2.4 GDU Desaturation Error Flag Register (GDUDSE)
Module Base + 0x0002 Access: User read write (1) 1. Read: Anytime Write: Anytime 76543210 R 0000 GOCIE0 GDSEIE GHHDIE GLVLSIE W R e s e t 00000000 = Unimplemented Figure 18-5. GDU2PH Interrupt Enable Register (GDUIE) Table 18-4. GDUIE Register Field Descriptions Field Description GOCIE0 GDU Overcurrent Interrupt Enable — Enables overcurrent interrupt.
0 No interrupt will be requested if the flag GOCIF0 in the GDUF register is set
1 Interrupt will be requested if the flag GOCIF0 in the GDUF register is set
GDU Desaturation Error Interrupt Enable — Enables desaturation error interrupt on low-side or high-side drivers
0 No interrupt will be requested if any of the flags in the GDUDSE register is set
1 Interrupt will be requested if any of t he flags in the GDUDSE register is set
GDU High GHD Interrupt Enable — Enables the high GHD interrupt.
0 No interrupt will be requested whenever GHHDIF flag is set
1 Interrupt will be requested whenever GHHDIF flag is set
GDU Low VLS Interrupt Enable — Enables the interrupt which indicates low VLS supply
0 No interrupt will be requested whenever GLVLSIF flag is set
1 Interrupt will be requested whenever GLVLSIF flag is set
Module Base + 0x0003 Access: User read/write (1) 1. Read: Anytime Write: Anytime, write 1 to clear 76543210 R0 0 GDHSIF[1:0] GDLSIF[1:0] W R e s e t 00000000 = Unimplemented Figure 18-6. GDU2PH Desaturation Error Flag Register (GDUDSE)
Chapter 18 Gate Drive Unit (GDU2PHV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 585 Table 18-5. GDUDSE Register Field Descriptions Field Description 5-4 GDHSIF[1:0] GDU High-Side Driver Desaturation Interrupt Flags — The flag is set by hardware to “1” when a desaturation error on associated high-side driver pin GHS[1:0] occurs. If the GDSEIE bit is set an interrupt is requested. Writing a logic “1” to the bit field clears the flag.
0 No desaturation error on high-side driver
1 Desaturation error on high-side driver
GDLSIF[1:0] GDU Low-Side Driver Desaturation Interrupt Flag — The flag is set to “1” when a desaturation error on associated low-side driver pin GLS[1:0] occurs. If the GDSEIE bit is set an interrupt is requested. Writing a logic “1” to the bit field clears the flag.
0 No desaturation error on low-side driver
1 Desaturation error on low-side driver
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18.3.2.5 GDU Status Register (GDUSTAT)
18.3.2.6 GDU Slew Rate Control Register (GDUSRC)
Module Base + 0x0004 Access: User read only (1) 1. Read: Anytime Write: Never 76543210 R 0 GPHS[1:0] GOCS0 0 GHHDS GLVLSS W R e s e t 00000000 = Unimplemented Figure 18-7. GDU2PH Status Register (GDUSTAT) Table 18-6. GDUSTAT Register Field Descriptions Field Description 6-5 GPHS[1:0] GDU Phase Status — The status bits are set to 1 when the voltage on associated pin GHS[1:0] is greater than VHD/2. The flags are cleared when the voltage on associated pin GHS[1:0] is less than VHD/2. See Section 18.4.6, “Phase Comparators
0 Voltage on pin GHSx is V HSx < VHD/2
1 Voltage on pin GHSx is V HSx > VHD/2
GDU Overcurrent Status — The status bits are set to 1 when the voltage on the overcurrent comparator input is above the threshold voltage VOCT. The flag is cleared when the voltage on the overcurrent comparator input is less than VOCT.Section 18.4.8, “Current Sense Amplifier and Overcurrent Comparator
0 Voltage on overcurrent comparator input is is less than V OCT
1 Voltage on overcurrent comparator is greater than V OCT
GDU High GHD Supply Status — The status bit is set to 1 when the voltage on GHD pin is above the threshold voltage VHVHDLA or VHVHDHA depending on the value of the GHHDLVL bit. The flag is cleared when the voltage on GHD pin is less than VHVHDLD or VHVHDHD depending on the value of the GHHDLVL bit.
0 Voltage on pin GHD is less than V HVHDLD or VHVHDHD
1 Voltage on pin GHD is greater than V HVHDLA or VHVHDHA
GDU Low VLS Status — The status bit is set to 1 when the voltage on VLS_OUT pin is below the threshold voltage VLVLSA. The flag is cleared when the voltage on VLS_OUT pin is greater than VLVLSD.
0 Voltage on pin VLS_OUT is greater than V LVLSD
1 Voltage on pin VLS_OUT is less than V LVLSA
Module Base + 0x0005 Access: User read/write (1) 76543210 GSRCHS[2:0] GSRCLS[2:0] W R e s e t 01000100 = Unimplemented Figure 18-8. GDU Slew Rate Control Register (GDUSRC)
Chapter 18 Gate Drive Unit (GDU2PHV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 587 1. Read: Anytime Write: Only if GWP=0 Table 18-7. GDU Slew Rate Control Register Field Descriptions Field Description 6:4 GSRCHS[2:0] GDU Slew Rate Control Bits High-Side FET Pre-Drivers — These bits control the slew rate on the HG[2:0] pins (see FET Pre-Driver Details) .These bits cannot be modified after GWP bit is set. 000 : slowest 111 : fastest 3:0 GSRCLS[2:0] GDU Slew Rate Control Bits Low-Side FET Pre-Drivers — These bits control the slew rate on the LG[2:0] pins (see FET Pre-Driver Details). These bits cannot be modified after GWP bit is set. 000 : slowest 111 : fastest
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18.3.2.7 GDU Flag Register (GDUF)
Module Base + 0x0006 Access: User read/write (1) 1. Read: Anytime Write: Anytime, write 1 to clear flag 76543210 R GSUF GHHDF GLVLSF GOCIF0 GHHDIF GLVLSIF W Reset 0 0 X (2) 2. Out of power on reset the flags may be set.
0000 X (2)
= Unimplemented Figure 18-9. GDU Flag Register (GDUF) Table 18-8. GDUF Register Field Descriptions Field Description GSUF GDU Start-up Flag — The start-up flag is loaded from the flash option field after system reset deasserts. Writing a logic “1” to the bit field clears the flag. If the flag is set all high-side FET pre-drivers are turned off and all low- side FET pre-drivers are turned on. If the flag is cleared and there is no error condition present all high-side and low-side FET pre-drivers are driven by the pwm channels.
0 High-side and low-side FET pre-dr ivers are driven by pwm channels
1 High-side FET pre-drivers turned off and low-side FET pre-drivers are turned on
GDU High VHD Supply Flag — The flag controls the state of the FET pre-drivers. If the flag is set and GOVA=0 the high-side pre-drivers are turned off and the low-side pre-drivers are turned on. If GOVA=1 all high-side and low-side FET pre-drivers are turned off. If the flag is cleared and no other error condition is present the high- side and low-side pre-drivers are driven by the PWM channels. The flag is set by hardware if a high voltage condition on GHD pin occurs. The flag is set if the voltage on pin GHD is greater than the threshold voltage VHVHDLA or VHVHDHA . Writing a logic “1” to the bit field clears the flag. GDU Low VLS Supply Flag — The flag controls the state of the FET pre-drivers. If the flag is set all high-side and low-side pre-drivers are turned off. If the flag is cleared and no other error condition is present the high-side and low-side pre-drivers are driven by the PWM channels. The flag is set by hardware if a low voltage condition on VLS_OUT pin occurs. The flag is set if the voltage on pin VLS drops below the threshold voltage VLVLSA. Writing a logic “1” to the bit field clears the flag.
0 VLS Supply is above V LVLSD
1 VLS Supply is below V LVLSA, all high-side and low-side FET pre-drivers are turned off
GDU Overcurrent Interrupt Flag — The interrupt flags are set by hardware if an overcurrent condition occurs. The flags are set if the voltage on the overcurrent comparator input is greater than the threshold voltage VOCT. If the GOCIE bit is set an interrupt is requested. Writing a logic “1” to the bit field clears the flag. If the GOCA bit is cleared all high-side FET pre-drivers are turned off and fault[3] is asserted. If GOCA is set all high-side and low-side FET pre-drivers are turned off and fault[1:0] are asserted.
0 Voltage on overcurrent comparator input is less than V OCT
1 Voltage on overcurrent comp arator is greater than VOCT
GDU High VHD Supply Interrupt Flag— The interrupt flag is set by hardwar e if GHHDF is set or if GHHDS is cleared. If the GHHDIE bit is set an interrupt is requested. Writing a logic “1” to the bit field clears the flag. GLVLSIF GDU Low VLS Supply Interrupt Flag— The interrupt flag is set by hardw are if GLVLSF is set or GLVLSS is cleared. If the GLVLSIE bit is set an interrupt is requested.Writing a logic “1” to the bit field clears the flag.
Chapter 18 Gate Drive Unit (GDU2PHV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 589 NOTE The purpose of the GSUF flag is to allow dissipation of the energy in the motor coils through the low side FETs in case of short reset pulses whilst the motor is spinning.
18.3.2.8 GDU Phase Mux Register (GDUPHMUX)
Module Base + 0x0009 Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R 000000 GPHMX[1:0] W R e s e t 00000000 = Unimplemented Figure 18-10. GDU Phase Mux Register (GDUPHMUX) Table 18-9. GDU Phase Mux Register Field Descriptions Field Description [1:0] GPHMUX GDU Phase Multiplexer — These buffered bits are used to select t he voltage which is routed to internal ADC channel.The value written to the GDUPHMUX register does not take effect until the LDOK bit is set and the next PWM reload cycle begins. Reading GDUPHMUX register reads the value in the buffer. It is not necessary the value which is currently used.
00 Pin GHD selected , V
GHD / 12 connected to ADC channel
01 Pin GHS0 selected , VHS0 / 6 connected to ADC channel
10 Pin GHS1 selected , VHS1 / 6 connected to ADC channel
11 Reserved.
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18.3.2.9 GDU Current Sense Offset Register (GDUCSO)
18.3.2.10 GDU Desaturation Level Register (GDUDSLVL)
Module Base + 0x000A Access: User read/write (1) 1. Read: Anytime Write: Anytime 76543210 R 00000 GCSO0[2:0] W R e s e t 00000000 = Unimplemented Figure 18-11. GDU Current Sense Offset (GDUCSO) Table 18-10. GDUCSO Register Field Descriptions Field Description (See also Section 18.4.8, “Current Sense Amplifier and Overcurrent Comparator) 2:0 GCSO0[2:0] GDU Current Sense Amplifier 0 Offset — These bits adjust the offset of the current sense amplifier.
000 No offset
001 Offset is +3mV
010 Offset is +6mV
011 Offset is +9mV
100 No offset
101 Offset is -9mV
110 Offset is -6mV.
111 Offset is -3mV
Module Base + 0x000B Access: User read/write (1) 1. Read: Anytime Write: Only if GWP=0 76543210 R GDSFHS GDSLHS[2:0] GDSFLS GDSLLS[2:0] W R e s e t 00000111 = Unimplemented Figure 18-12. GDU Desaturation Level Register (GDUDSLVL)
Chapter 18 Gate Drive Unit (GDU2PHV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 591 Table 18-11. GDU Desaturation Level Register Field Descriptions Field Description GDSFHS GDU Desaturation Filter Characteristic for High-Side Drivers — This bit adjusts the desaturation filter characteristic of the three high-side FET pre-drivers. These bits cannot be modified after GWP bit is set. See Section 18.4.5, “Desaturation Error. 6:4 GDSLHS GDU Desaturation Level for High-Side Drivers — These bits adjust the desatur ation levels of the high-side FET pre-drivers. These bits cannot be modified after GWP bit is set. See Section 18.4.5, “Desaturation Error 000 Vdesaths = VHD - 0.35V (typical value) 001 to 110 see device electrical specification 111 Vdesaths = VHD - 1.40V (typical value) GDSFLS GDU Desaturation Filter Characteristic for Low-Side Drivers — This bit adjusts the desaturation filter characteristic of the three low-side FET pre-drivers. These bits cannot be modified after GWP bit is set. See Section 18.4.5, “Desaturation Error. 2:0 GDSLLS GDU Desaturation Level for Low-Side Drivers — These bits adjust the desaturation level of the low-side FET pre-drivers. These bits cannot be modified after GWP bit is set. See Section 18.4.5, “Desaturation Error 000 Vdesatls = 0.35V (typical value) 001 to 110 see device electrical specification 111 Vdesatls = 1.40V (typical value)
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18.3.2.11 GDU Phase Log Register (GDUPHL)
18.3.2.12 GDU Clock Control Register 2 (GDUCLK2)
The GCPCD bits must be set to the required value before GCPE bit is set. If a different charge pump clock frequency is required GCPE has to be cleared before new values to GCPCD bits are written. Module Base + 0x000C Access: User read only (1) 1. Read: Anytime Write: never 76543210 R 000000 G P H L [ 1 : 0 ] W R e s e t 00000000 = Unimplemented Figure 18-13. GDU Phase Log Register (GDUPHL) Table 18-12. GDU Phase Log Register Field Descriptions Field Description 1:0 GPHL[1:0] GDU Phase Log Bits— If a desaturation error occu rs the phase status bits GPHS[1:0] in register GDUSTAT are copied to this register. The GDUPHL register is cleared only on reset. See Section 18.4.5, “Desaturation Error Module Base + 0x000D Access: User read/write (1) 1. Read: Anytime Write: Only if GWP=0 76543210 R 0000 GCPCD[3:0] W R e s e t 00000000 Figure 18-14. GDU Clock Control Register 2 (GDUCLK2) Table 18-13. GDUCLK2 Register Field Descriptions Field Description 3-0 GCPCD[3:0] GDU Charge Pump Clock Divider — These bits select the clock divider factor which is used to divide down the bus clock frequency fBUS for the charge pump clock fCP. See Table 18-14 for divider factors. These bits cannot be modified after GWP bit is set. See also Section 18.4.4, “Charge Pump
Chapter 18 Gate Drive Unit (GDU2PHV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 593 Table 18-14. Charge Pump Clock Divider Factors k = fBUS / fCP GCPCD[3:0] f CP 0000 fBUS / 16 0001 fBUS / 24 0010 fBUS / 32 0011 fBUS / 48 0100 fBUS / 64 0101 fBUS / 96 0110 fBUS / 100 0111 fBUS / 128 1000 fBUS / 192 1001 fBUS / 200 1010 fBUS / 256 1011 fBUS / 384 1100 fBUS / 400 1101 fBUS / 512 1110 fBUS / 768 1111 fBUS / 800
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18.3.2.13 GDU Overcurrent Register 0 (GDUOC0)
18.3.2.14 GDU Control Register 1 (GDUCTR1)
Module Base + 0x000E Access: User read/write (1) 1. Read: Anytime Write: Only if GWP=0 76543210 R GOCA0 GOCE0 GOCT0[4:0] W R e s e t 00000000 = Unimplemented Figure 18-15. GDU Overcurrent Register 0 (GDUOC0) Table 18-15. GDUOC0 Register Field Descriptions Field Description GOCA0 GDU Overcurrent Action — This bit cannot be modified after GWP bit is set. This bit controls the action in case of an overcurrent event. See Table 18-20 and Table 18-19 GOCE0 GDU Overcurrent Comparator Enable — This bit cannot be modified after GWP bit is set.
0 Overcurrent Comparator is disabled
1 Overcurrent Comparator is enabled
4:0 GOCT0[4:0] GDU Overcurrent Comparator Threshold — These bits cannot be modified after GWP bit is set. The overcurrent comparator threshold voltage is the output of a 6-bit digital-to-analog converter. The upper bit of the digital inputs is tied to one. The other bits of the digital inputs are driven by GOCT0. The overcurrent comparator threshold voltage can be calculated from equation below. Module Base + 0x0010 Access: User read/write (1) 1. Read: Anytime Write: Only if GWP=0 76543210 R 00000 GBSWOFF[1:0] TDEL W R e s e t 00000000 = Unimplemented Figure 18-16. GDU Control Register 1 (GDUCTR1) Voct0 32 GOCT0+ VDDA
Chapter 18 Gate Drive Unit (GDU2PHV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 595 Table 18-16. GDUCTR1 Register Field Descriptions
18.4 Functional Description
18.4.1 General
The PMF module provides the values to be driven onto the outputs of the low-side and high-side FET pre- drivers. If the FET pre-drivers are enabled, the PMF channels drive their corresponding high-side or low- side FET pre-drivers according Table 18-17.
18.4.2 Low-Side FET Pre-Drivers
The two low-side FET pre-drivers turn on and off the external low-side power FETs. The energy required to charge the gate capacitance of the power FET CG is drawn from the output of the voltage regulator VLS. See Figure 18-17. The register bits GSRCLS[2:0] in the GDUSRC Register (see Figure 18-8) control the slew rate of the low-side FET pre-drivers in order to control fast voltage changes dv/dt (see also Section 18.5.1, “FET Pre-Driver Details). Field Description 2:1 GBSWOFF GDU Bootstrap Switches Off — These bits cannot be modified after GWP bit is set. The GDU integrates a bootstrap switch for each phase to charge the off chip bootstrap capacitor (see Figure 18-17). If the corresponding low-side driver is turned on and no overvoltage or corresponding desaturation error condition is present and corresponding GBSWOFF bit is cleared the bootstrap switch is turned on and charges the bootstrap capacitor. If GBSWOFF is set the corresponding bootstrap switch is always turned off and an external bootstrap diode is required to charge the bootstrap capacitor. GBSWOFF[0] corresponds to phase 0 and GBSWOFF[1] corresponds to phase 1. TDEL tdelon / tdeloff Control — This bit controls the parameters t delon and tdeloff. It cannot be modified after GWP bit is set. This bit must be set to meet the min and max values for tdelon and tdeloff specified in the electrical specification. If this bit is cleared the values for tdelon and tdeloff are out of spec. Table 18-17. PMF Channel Assignment PMF Channel PMF Channel Assignment
0 High-Side Gate and Source Pins GHG[0], GHS[0]
1 Low-Side Gate and Source Pins GLG[0], GLS[0]
2 High-Side Gate and Source Pins GHG[1], GHS[1]
3 Low-Side Gate and Source Pins GLG[1], GLS[1]
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18.4.3 High-Side FET Pre-Driver
The two high-side FET pre-drivers turn on and off the external high-side power FETs. The required charge for the gate capacitance of the external power FET is delivered by the bootstrap capacitor. After the supply voltage is applied to the microcontroller or after exit from stop mode, the low-side FET pre-drivers should be activated for a short time in order to charge the bootstrap capacitor CBS. Care must be taken after a long period of inactivity of the low-side FET pre-drivers to verify that the bootstrap capacitor CBS is not discharged. The register bits GSRCHS[2:0] in the GDUSRC Register (see Figure 18-8) control the slew rate of the high-side FET pre-driver in order to control fast voltage changes dv/dt (see also Section 18.5.1, “FET Pre- Driver Details). NOTE The minimum PWM pulse on & off time must be tminpulse. NOTE If the GFDE bit is cleared the high-side gate and source pins and the low- side gate and source pins are shorted with an internal resistor. The voltage differences are VHGx-VHSx~ 0V and VLGx-VLSx ~ 0V so that the external FETs are turned off. NOTE The PWM channel outputs for high-side and low-side drivers are delayed by two core clock cycles.
Chapter 18 Gate Drive Unit (GDU2PHV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 597 Figure 18-17. FET Pre-Driver Circuit and Voltage Regulator NOTE Optional charge pump input RC filter can be used to avoid over pumping effect when voltage spikes are present on the high-side drains. Vref + VBAT hs_on ls_on VLS_OUT CP VCP VBSx GHGx GHSx VLSx GLGx GLSx CBS Rsense VSUP GSRCHS[2:0] GSRCLS[2:0] Reverse Battery Protection GCPE GCPCD[3:0] GHD GHHDIF 100 220nF optional charge pump filter CG CG Charge Pump Connect CFILT RFILT optional RC filter to VBS pin 10uF Bootstrap Switch on/off SW1
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Optional RC filter to VBS pin should be used to avoid overshoot above maximum voltage on VBS pin. The RC filter needs to be carefully designed in order not to influence the charging time of the bootstrap capacitor CBS. NOTE The bootstrap switch SW1 is turned on when the corresponding low-side driver is turned on and no high voltage condition on GHD pin and no desaturation error is flagged and corresponding GBSWOFF=0. If GBSWOFF=1 the switch is always turned off and an external bootstrap diode is required.
18.4.4 Charge Pump
The GDU module integrates the necessary hardware to build a charge pump with external components.The charge pump is used to maintain the high-side driver gate source voltage VGS when PWM is running at 100% duty cycle. The external components needed are capacitors and diodes The supply voltage of the charge pump driver on pin CP is VVLS. The output voltage on pin CP typically switches between 0 and 11V. The charge pump clock frequency depends on the setting of GCPCD bits. The transistor P2 shown in Figure 18-17 connects VCP pin to VBSx pin. Figure 18-18 shows the timing diagram when transistor P2 connects VCP to VBSx. Figure 18-18. Timing Diagram Charge Pump Connect GCPE PWM predrivers on GHG charge pump connect tdelon tHGON tdelon / tdeloff : GDU propagation delay tHGON / tHGOFF : HS driver turn on/off time tBLANK: Blanking Time (see GDUCTR register) During this time desaturation error flags can be set and charge pump is connected to VBSx tBLANK tHGOFF tdeloff
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18.4.5 Desaturation Error
A desaturation error is generated if the output signal at GHSx does not properly reflect the drive condition of the low-side and high-side FET pre-drivers. The GDU integrates two desaturation comparators for the low-side FET pre-drivers and two desaturation comparators for the high-side FET pre-drivers. If the low-side power FET T2 (see Figure 18-20) is turned on and the drain source voltage VDS2 of T2 is greater than Vdesatls after the blanking time tBLANK a desaturation error will be flagged. In this case the associated desaturation error flag GDLSIF[1:0] will be set (see Figure 18-6) and the low-side power FET T2 will be turned off. The level of the voltage Vdesatls can be adjusted in the range of 0.35V to 1.40V (see Figure 18-12). If the high-side power FET T1 (see Figure 18-20) is turned on and the drain source voltage VDS1 is greater than Vdesaths after the blanking time tBLANK a desaturation error will be flagged.In this case the associated desaturation error flag GDHSIF[1:0] will be set (see Figure 18-6) and the high-side power FET T1 will be turned off. The level of the voltage Vdesaths can be adjusted in the range of 0.35 to 1.40V (see Figure 18- 12). The output of the desaturation comparator of the low-side and high-side drivers are filtered. The filter characteristic is controlled by the GDSFHS and GDSFLS bits as shown in Figure 18-19 and Table 18-18. Figure 18-19. Filter Characteristic of Desaturation Comparator Output The low-side and high-side desaturation interrupt flags GDHSIF and GDLSIF are cleared by writing a one to the associated flag. After the flag is cleared the associated low-side or high-side FET pre-driver is enabled again and is driven by the source selected in the PMF module. Table 18-18. Filter Characteristic of Desaturation Comparator Output(1) 1. Table shows typical values which are not production tested.Values are derived from simulation. GDSFHS/GDSFLS t DSFHS tDSFLS 0 200ns 150ns 1 500ns 400ns tDSFHS / tDSFLS Desturation Comparator Output Desaturation Filter output
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Figure 18-20. Desaturation Comparators and Phase Comparators
18.4.6 Phase Comparators
The GDU module includes two phase comparators. The phase comparators compare the voltage on the GHS[1:0] pins with one half voltage on GHD pin. If VHSx is greater than 0.5 VHD the associated phase status bit GPHS[1:0] is set. (see Figure 18-7) If the VHSx is less than 0.5 VHD the associated phase status bit GPHS[1:0] is cleared. If a desaturation error is detected the state of the phase status bit GPHS[1:0] are copied to the GDUPHL register. The phase flags get unlocked when the associated desaturation interrupt flag is cleared. hs_on ls_on GHGx GHSx GLGx Rsense VHD VHD/2 Vdesatls GDSLLS[2:0] Desat. Comp. Phase Comp. Desaturation Phase Status Vdesaths GDSLHS[2:0]Desat. Comp. Desaturation VDS2 High-Side FET Low-Side FET Pre-Driver Pre-Driver GLSx VDS1 + = GHD Error High-Side. GDSFHS Filter High-Side Driver Error Low-Side. Low-Side Driver GDSFLS Filter
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18.4.7 Fault Protection Features
The GDU includes a number of fault protection features against overvoltage, overcurrent, undervoltage and power bridge faults like phase shorted to ground or supply. These fault protection features allow selection of the appropriate low side and high side driver state in case of a fault condition, shown in Table 18-20. In addition five fault outputs are provided to signal detected faults to other modules of the MCU. For connectivity of the fault outputs see the device specific information. Table 18-19 shows the logic equations for the five fault outputs. Table 18-19. Fault Outputs Logic Equations Fault Output Logic Equation Fault[0] ( GDLSIF[0] | GDHSIF[0]) | (GOCIF[0] & GOCA0) Fault[1] ( GDLSIF[1] | GDHSIF[1]) | (GOCIF[0] & GOCA0) Fault[2] GLVLSF Fault[3] GHHDF | (GOCIF0 & ~GOCA0)
Chapter 18 Gate Drive Unit (GDU2PHV2) NXP Semiconductors 602 NOTE Since all MOSFET transistors are turned off, VBSX can reach phase voltage plus bootstrap voltage which may exceed allowable levels during high supply voltage conditions. If such operating condition exist the application must make sure that VBSX levels are clamped below maximum ratings for example by using clamping diodes. Table 18-20. Fault Protection Features Summary(1) 1. The error conditions listed in this table will not switch off the charge pump. Prior ity Condition GSUF GHHDF GOCIF0 GLVLSF GDHSIF [1:0] GDLSIF [1:0] GHS GHS GLS GLS low high normal operation,no error condition, FET pre-driver driven by PMF module 0 0 0 0 00 00 PWM [2] PWM [0] PWM [3] PWM [1] startup condition after reset deassert, no error condition 1 0 0 0 00 00 off off on on overvoltage on GHD pin GOVA=0 x 1 0 0 00 000 off off on on overcurrent condition comparator 0 GOCA0=0 x x 1 0 00 00 off off on on undervoltage condition on VLS_OUT pin x x x 1 00 00 off off off off overcurrent condition comparator 0 GOCA0=1 x x 1 x 00 00 off off off off desaturation error condition on high-side FET pre-drivers x x x x 01 00 PWM [2] off PWM [3] PWM [1] x x x x 10 00 off PWM [0] PWM [3] PWM [1] desaturation error condition on low-side FET pre-drivers x x x x 00 01 PWM [2] PWM [0] PWM [3] off x x x x 00 10 PWM [2] PWM [0] off PWM [1] overvoltage on GHD pin GOVA=1 x 1 x x xx xx off off off off
Chapter 18 Gate Drive Unit (GDU2PHV2) NXP Semiconductors 603 Figure 18-21. Short to Supply Detection GLGx GHGx GHSx Phase Status Desat. Error VHD
0.5 VHD
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Figure 18-22. Short to Ground Detection GHGx GLGx GHSx Phase Status Desat. Error VHD
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18.4.8 Current Sense Amplifie r and Overcurrent Comparator
The current sense amplifier is usually connected as a differential amplifier ( see Figure 18-23). It senses the current flowing through the external power FET as a voltage across the current sense resistor Rsense. In order to measure both positive and negative currents, an external reference has to be used. The output of the current sense amplifier can be connected to an ADC channel. For more details on ADC channel assignment, refer to Device Overview Internal Signal Mapping Section. The input offset voltage of the current sense amplifier can be adjusted with the GCSO[2:0] bits in the GDUCSO register. (see Figure 18- 11) The output of the current sense amplifier is connected to the plus input of the overcurrent comparator. The minus input is driven by the output voltage of a 6 Bit DA converter. The digital input of the DA converter is {1,GOCT0[4:0]}. In order to use the overcurrent comparator GOCE0 and GCSE0 have to be set. Figure 18-23. Current Sense Amplifier Connected as Differential Amplifier
18.4.9 GDU DC Link Voltage Monitor
In addition to the feature described in Section 18.3.2.8, “GDU Phase Mux Register (GDUPHMUX) the voltage on pin GHD divide by 5 is routed to an ADC channel. See device specific information for ADC channel number. This feature is only available if GFDE is set. AMPP0 Rsense Voffset GCSO0[2:0] AMPM0AMP0 Rn / aRn Vref Rp / a Rp Vsense Output Voltage to ADC VAMP = a Vsense + Vref GCSE0 I GOCE0 Voct GOCT0[4:0] Overcurrent Condition a V sense + Vref > Voct 6 bit DAC
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18.4.10 Interrupts
This section describes the interrupts generated in the GDU module. The interrupts are only available in CPU run mode. Entering and exiting stop mode has no effect on the interrupt flags. The GDU module has two interrupt vectors which are listed in Table 18-21. The low-side and high-side desaturation error flags are combined into one interrupt line and the over and under voltage detection are combined into another interrupt line. (see device specific section interrupt vector table) Table 18-21. GDU Module Interrupt Sources # GDU Module Interrupt Source Module Internal Interrupt Source Local Enable
0 GDU desaturation error
GDU low-side and high-side desaturation error flags GDHSF[2:0] and GDLSF[2:0] GDSEIE = 1
1 GDU over/under voltage
GDU low voltage condition on pin VLS (GLVLSIF) GLVLSIE = 1 GDU high voltage condition on pin GHD (GHHDIF) GHHDIE = 1 GDU Overcurrent Condition (GOCIF0) GOCIE0=1
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18.5 Application Information
18.5.1 FET Pre-Driver Details
The basic concept of the high-side driver is shown in Figure 18-24. If the FET pre-driver is switched on the transistor T2 is driving the output HG. For on resistance Rgduon of transistor T2 refer to GDU electricals. The output current is limited to IOUT which is derived from the reference current IREF. The current source is controlled by the slew rate control bits GSRCHS[2:0]. If the FET pre-driver is switched off transistors T3 and T4 are switched on. For on resistance Rgduoffn and Rgduoffp of transistors T3 and T4 refer to GDU electricals. The reference current IREF is controlled by the slew rate control bits GSRCHS[2:0] :
- I REF = 10uA + GSRCHS 10uA, [10uA, 20uA . . . 80uA] Assuming an ideal op-amp the voltage across R1 is equal voltage across R2 and IOUT2 is given by:
- V 1 = V2 = IREF R1 = IOUT2 R2
- I OUT2 = IREF (R1/R2) With the ratio of the transistor sizes of T1 and T2 k=450, and the ratio of the resistors R1/R2=36, and neglect the current through RHSpul the output current IOUT is:
- I OUT1 = k IOUT2
- I OUT = IOUT1 + IOUT2 = IREF (R1/R2) (1+k)
- I OUT ~ IREF (R1/R2) k Figure 18-24. FET Pre-Driver Concept for High-Side Driver RgduoffpRgduoffn GSRCHS[2:0] VBS HG GHS R1 R2 Driver Off Driver On RHSpul IREF Iout2 Iout1 Iout T1 T2 T3 T4 Rgduon CG
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FET pre-driver concept shown in Figure 18-24 for the high-side driver applies also to low-side driver. The reference current for the low-side driver is controlled by GSRCLS[2:0].
18.5.2 GDU Intrinsic Dead Time
The basic point of dead time is to prevent cross conduction of the high-side and low-side power MOSFETs. The GDU adds an amount of dead time to the PWM signals driving the high-side and low-side power MOSFETs. A PWM signal applied to the input of the GDU does not appear instantly on the output. There is propagation delay (tdelon, tdeloff) through the FET pre-drivers and it takes time to turn on and off the gates of the power MOSFETs (tHGON, tHGOFF) (see Figure 18-25). The propagation delay and the turn on and off time change over temperature. There are differences between propagation delay paths to the high-side MOSFETs and low-side MOSFETs. Worst case must be considered. The turn on time tHGON depends also on the setting of the slew rate control bits GSRCLS[2:0] and GSRCHS[2:0]. Figure 18-25. Driver on/off Delay and on/off Time1 Figure 18-26 shows examples of intrinsic dead times. For example assuming minimum values for tHGON and tdelon for the high side gate HG0 and minimum values for tHGOFF and tdeloff for low-side gate LG0 no additional dead time setting in the PMF module is required and the PWM channels can change at the same time without cross conduction of the power MOSFETs. 1. Note that tHGON and tHGOFF is the turn on and turn off time for high-side and low-side gate tdelon tdelofftHGON tHGOFF PWMx Channel GHGx/GLGx
Chapter 18 Gate Drive Unit (GDU2PHV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 609 Figure 18-26. Examples of Intrinsic Dead Time PWM0 PWM1 tdelon_min tHGOFF_max dead time = tdelon_min - tdeloff_min - tHGOFF_min tdelon_max tdeloff_min tdeloff_max tHGOFF_min tHGON_max tHGON_min GHG0 min turn on delay and min turn on time GHG0 max turn on delay and max turn on time GLG0 min turn off delay and min turn off time GLG0 max turn off delay and max turn off time dead time = tdelon_max - tdeloff_max - tHGOFF_max dead time set in PMF
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if CBS = 20 CG then the resulting gate voltage is VG = 0.95 VBS.
18.5.3 On Chip GDU t delon and tdeloff Measurement
The S12ZVMB MCU provides the capability to measure the GDU tdelon and tdeloff delays of the high-side and low-side drivers with the on chip timer. The timing diagram Figure 18-27 shows the basic concept. The high-side and low-side drivers provide the feedback signals hs0_fb and ls0_fb which indicate that the drivers are turned on or off. The feedback signals and the related pwm signals are used to generate the gdu_del_on_off output signal. (see Figure 18-27) This signal can be routed to TIM1 input capture channel IOC1_3 for pulse width measurement. Following below are the steps to do the delay measurement:
- 1. Route gdu_del_on_off signal to TIM1 IOC1_3 in PIM routing register MODRR5.T1IC3RR
- 2. Setup TIM1 IOC1_3 fo r pulse width measurement
- 3. Use software control of PWM output feature PMFOUTC and PMFOUTB to assert PWM0
- 4. Store measured pulse width (t delon of high-side driver 0) in RAM
- 5. Use software control of PWM output feature PMFOUTC and PMFOUTB to deassert PWM0
- 6. Store measured pulse width (t deloff of high-side driver 0) in RAM
- repeat 3 to 6 for all PWM channels
Chapter 18 Gate Drive Unit (GDU2PHV2) NXP Semiconductors 611 Figure 18-27. Measurement of GDU tdelon and tdeloff PWM0 hs0_fb PWM1 ls0_fb tdelon tdeloff Signal routed to TIM1 IOC1_0 for pulse width measurement gdu_delay_on_off tdelon tdeloff
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MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductor 613 Chapter 19 Flash Module (S12ZFTMRZ)
19.1 Introduction
The P-Flash (Program Flash) and EEPROM memory sizes are specified at device level (Reference Manual device overview chapter). The description in the following sections is valid for all P-Flash and EEPROM memory sizes. The Flash memory is ideal for single-supply applications allowing for field reprogramming without requiring external high voltage sources for program or erase operations. The Flash module includes a memory controller that executes commands to modify Flash memory contents. The user interface to the memory controller consists of the indexed Flash Common Command Object (FCCOB) register which is written to with the command, global address, data, and any required command parameters. The memory controller must complete the execution of a command before the FCCOB register can be written to with a new command. CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. Table 19-1. Revision History Revision Number Revision Date Sections Affected Description of Changes V02.03 12 Apr 2012 19.3/19-618 Corrected many typo. Changed caution note V02.04 17 May 2012 19.3.2.6/19-630 - Removed flag DFDIE V02.05 11 Jul 2012 - Added explanation about when MGSTAT[1:0] bits are cleared, Section 19.3.2.7 - Added note about possibility of reading P-Flash and EEPROM simultaneously, Section 19.4.6 V02.06 18 Mar 2013 - Standardized nomenclature in references to memory sizes V02.07 24 May 2013 - Revised references to NVM Resource Area to improve readability FCCOB1 to FCCOB2 V02.9 15 Oct 2014 Created memory-size independe nt version of this module description
MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductor 614 It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory from the same block. Simultaneous P-Flash and EEPROM operations are discussed in Section 19.4.6. Both P-Flash and EEPROM memories are implemented with Error Correction Codes (ECC) that can resolve single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read by half-phrase, only one single bit fault in an aligned 4 byte half-phrase containing the byte or word accessed will be corrected.
19.1.1 Glossary
Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. EEPROM Memory — The EEPROM memory constitutes th e nonvolatile memory store for data. EEPROM Sector — The EEPROM sector is the smallest po rtion of the EEPROM memory that can be erased. The EEPROM sector consists of 4 bytes. NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters required for Flash command execution. Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes two sets of aligned double words with each set including 7 ECC bits for single bit fault correction and double bit fault detection within each double word. P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications. P-Flash Sector — The P-Flash sector is the sm allest portion of the P-Flash memory that can be erased. Each P-Flash sector contains 512 bytes. Program IFR — Nonvolatile information regist er located in the P-Flash block that contains the Version ID, and the Program Once field.
19.1.2 Features
19.1.2.1 P-Flash Features
- Derivatives featuring up to and including 128 KB of P-Flash include one P-Flash block
- Derivatives featuring more than 128 KB of P-Flash include two Flash blocks
- In each case the P-Flash sector size is 512 bytes
- Single bit fault correction and double bit fault det ection within a 32-bit double word during read operations
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- Automated program and erase algorithm with verify and generation of ECC parity bits
- Fast sector erase and phrase program operation
- Ability to read the P-Flash memory while programming a word in the EEPROM memory
- Flexible protection scheme to prevent accid ental program or erase of P-Flash memory
19.1.2.2 EEPROM Features
- The EEPROM memory is composed of one Fl ash block divided into sectors of 4 bytes
- Single bit fault correction and double bit fault detection within a word during read operations
- Automated program and erase algorithm with verify and generation of ECC parity bits
- Fast sector erase and word program operation
- Protection scheme to prevent acciden tal program or erase of EEPROM memory
- Ability to program up to four words in a burst sequence
19.1.2.3 Other Flash Module Features
- No external high-voltage power supply require d for Flash memory program and erase operations
- Interrupt generation on Flash command completion and Flash error detection
- Security mechanism to prevent unau thorized access to the Flash memory
19.1.3 Block Diagram
The block diagrams of the Flash modules are shown in the following figures.
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Figure 19-1. FTMRZ Block Diagram (Single P-Flash Block plus EEPROM block) sector 0 sector 1 final sector Bus Clock Divider Clock Command Interrupt Request FCLK Protection Security Registers Flash Interface 16bit internal bus P-Flash Error Interrupt Request CPU sector 0 sector 1 final sector EEPROM Memory Controller
Chapter 19 Flash Module (S12ZFTMRZ) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 617 Table 19-2. FTMRZ Block Diagram (Two P-Flash blocks plus EEPROM block)
19.2 External Signal Description
The Flash module contains no signals that connect off-chip. sector 0 sector 1 final sector Bus Clock Divider Clock Command Interrupt Request FCLK Protection Security Registers Flash Interface 16bit internal bus P-Flash Error Interrupt Request CPU sector 0 sector 1 final sector EEPROM Memory Controller sector 0 sector 1 final sector P-Flash HardBlock-0S HardBlock-0N (P-Flash+EEPROM)
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19.3 Memory Map and Registers
This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. CAUTION Writing to the Flash registers while a Flash command is executing (that is indicated when the value of flag CCIF reads as ’0’) is not allowed. If such action is attempted, the result of the write operation will be unpredictable. Writing to the Flash registers is allowed when the Flash is not busy executing commands (CCIF = 1) and during initialization right after reset, despite the value of flag CCIF in that case (refer to Section 19.6 for a complete description of the reset sequence).
19.3.1 Module Memory Map
The P-Flash memory is located between global addresses 0x80_0000 and 0xFF_FFFF. The P-Flash is high aligned from 0xFF_FFFF. Thus, for example, a 128 KB P-Flash extends from 0xFF_FFFF to 0xFE_0000. The flash configuration field is mapped to the same addresses independent of the P-Flash memory size, as shown in Figure 19-2. The FPROT register, described in Section 19.3.2.9, can be set to protect regions in the Flash memory from accidental program or erase. Three separate memory regions, one growing upward from global address 0xFF_8000 in the Flash memory (called the lower region), one growing downward from global address 0xFF_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash memory, can be activated for protection. The Flash memory addresses covered by these protectable regions are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader code since it covers the vector space. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 19-4. Table 19-3. FTMRZ Memory Map Global Address (in Bytes) Description 0x0_0000 – 0x0_0FFF Register Space 0x10_0000 – 0x1F_4000 EEPROM memory range. Allocation is device dependent. 0x1F_4000 – 0x1F_FFFF NVM Resource Area (1) (see Figure 19-3) 1. See NVM Resource area description in Section 19.4.4 0x80_0000 – 0xFD_FFFF P-Flash memory range (Hardblock 0S). Allocation is device dependent. 0xFE_0000 – 0xFF_FFFF P-Flash memory range (Har dblock 0N). Allocation is device dependent.
Chapter 19 Flash Module (S12ZFTMRZ) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 619 Table 19-4. Flash Configuration Field Global Address Size (Bytes) Description 0xFF_FE00-0xFF_FE07 8 Backdoor Comparison Key Refer to Section 19.4.7.11, “Verify Backdoor Access Key Command,” and Section 19.5.1, “Unsecuring the MCU using Backdoor Key Access” 0xFF_FE08-0xFF_FE091 2 Protection Override Comparison Key. Refer to Section 19.4.7.17, “Protection Override Command” 0xFF_FE0A- 0xFF_FE0B(1) 1. 0xFF_FE08-0xFF_FE0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0xFF_FE0A - 0xFF_FE0B reserved field should be programmed to 0xFF.
2 Reserved
0xFF_FE0C1 1 P-Flash Protection byte. Refer to Section 19.3.2.9, “P-Flash Protection Register (FPROT)” 0xFF_FE0D1 1 EEPROM Protection byte. Refer to Section 19.3.2.10, “EEPROM Protection Register (DFPROT)” 0xFF_FE0E1 1 Flash Nonvolatile byte Refer to Section 19.3.2.11, “Flash Option Register (FOPT)” 0xFF_FE0F1 1 Flash Security byte Refer to Section 19.3.2.2, “Flash Security Register (FSEC)”
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Figure 19-2. P-Flash Memory Map With Protection Alignment Flash Configuration Field 0xFF_C000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 KB 0xFF_8000 0xFF_9000 0xFF_8400 0xFF_8800 0xFF_A000 P-Flash END = 0xFF_FFFF 0xFF_F800 0xFF_F000 0xFF_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 KB Flash Protected/Unprotected Region
8 KB (up to 29 KB)
16 bytes (0xFF_FE00 - 0xFF_FE0F) Flash Protected/Unprotected Region Size is device dependent P-Flash START Protection Protection Protection Movable End Fixed End Fixed End
Chapter 19 Flash Module (S12ZFTMRZ) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 621 Table 19-5. Program IFR Fields Global Address Size (Bytes) Field Description 0x1F_C000 – 0x1F_C007 8 Reserved 0x1F_C008 – 0x1F_C0B5 174 Reserved 0x1F_C0B6 – 0x1F_C0B7 2 Version ID (1) 1. Used to track firmware patch versions, see Section 19.4.2 0x1F_C0B8 – 0x1F_C0BF 8 Reserved 0x1F_C0C0 – 0x1F_C0FF 64 Program Once Field Refer to Section 19.4.7.6, “Program Once Command” Table 19-6. Memory Controller Resource Fields (NVM Resource Area (1)) 1. See Section 19.4.4 for NVM Resources Area description. Global Address Size (Bytes) Description 0x1F_4000 – 0x1F_41FF 512 Reserved 0x1F_4200 – 0x1F_7FFF 15,872 Reserved 0x1F_8000 – 0x1F_97FF 6,144 Reserved 0x1F_9800 – 0x1F_BFFF 10,240 Reserved 0x1F_C000 – 0x1F_C0FF 256 P-Flash IFR (see Table 19-5) 0x1F_C100 – 0x1F_C1FF 256 Reserved. 0x1F_C200 – 0x1F_FFFF 15,872 Reserved.
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Figure 19-3. Memory Controller Resource Memory Map (NVM Resources Area)
19.3.2 Register Descriptions
The Flash module contains a set of 24 control and status registers located between Flash module base + 0x0000 and 0x0017. In the case of the writable registers, the write accesses are forbidden during Flash command execution (for more detail, see Caution note in Section 19.3). A summary of the Flash module registers is given in Figure 19-4 with detailed descriptions in the following subsections. Address & Name 76543210 0x0000 FCLKDIV RF D I V L D FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 W 0x0001 FSEC R KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 W 0x0002 FCCOBIX R0 0 0 0 0 CCOBIX2 CCOBIX1 CCOBIX0 W Figure 19-4. FTMRZ128K512 Register Summary P-Flash IFR 256 bytes 0x1F_C000 0x1F_41FF 0x1F_4000 Reserved 6 KB Reserved 15872 bytes 0x1F_8000 0x1F_97FF 0x1F_C100 Reserved 16,128 bytes Reserved 512 bytes Reserved 10 KB
Chapter 19 Flash Module (S12ZFTMRZ) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 623 0x0003 FPSTAT R F P O V R D 000000 W S T A T A C K W 0x0004 FCNFG R CCIE
0 ERSAREQ
IGNSF WSTAT[1:0] FDFD FSFD W 0x0005 FERCNFG R 0000000 SFDIE W 0x0006 FSTAT R CCIF ACCERR FPVIOL MGBUSY RSVD MGSTAT1 MGSTAT0 W 0x0007 FERSTAT R 000000 DFDF SFDIF W 0x0008 FPROT R FPOPEN RNV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 W 0x0009 DFPROT(1) R DPOPEN DPS6 DPS5 DPS4 DPS3 DPS2 DPS1 DPS0 W 0x000A FOPT R NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 W 0x000B FRSV1 R 00000000 W 0x000C FCCOB0HI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W 0x000D FCCOB0LO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W 0x000E FCCOB1HI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W 0x000F FCCOB1LO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W 0x0010 FCCOB2HI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W Address & Name 76543210 Figure 19-4. FTMRZ128K512 Register Summary (continued)
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19.3.2.1 Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms. All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable. 0x0011 FCCOB2LO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W 0x0012 FCCOB3HI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W 0x0013 FCCOB3LO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W 0x0014 FCCOB4HI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W 0x0015 FCCOB4LO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W 0x0016 FCCOB5HI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W 0x0017 FCCOB5LO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W = Unimplemented or Reserved 1. Number of implemented DPS bits depends on EEPROM memory size. Offset Module Base + 0x0000 76543210 RF D I V L D FDIVLCK FDIV[5:0] W R e s e t 00000000 = Unimplemented or Reserved Figure 19-5. Flash Clock Divider Register (FCLKDIV) Address & Name 76543210 Figure 19-4. FTMRZ128K512 Register Summary (continued)
Chapter 19 Flash Module (S12ZFTMRZ) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 625 CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). Table 19-7. FCLKDIV Field Descriptions Field Description FDIVLD Clock Divider Loaded
0 FCLKDIV register has not been written since the last reset
1 FCLKDIV register has been written since the last reset
0 FDIV field is open for writing
1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and restore writability to the FDIV field in normal mode. 5–0 FDIV[5:0] Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events during Flash program and erase algorithms. Table 19-8 shows recommended values for FDIV[5:0] based on the BUSCLK frequency. Please refer to Section 19.4.5, “Flash Command Operations,” for more information. Table 19-8. FDIV values for various BUSCLK Frequencies BUSCLK Frequency (MHz) FDIV[5:0] BUSCLK Frequency (MHz) FDIV[5:0] MIN(1) MAX(2) MIN1 MAX2 1.0 1.6 0x00 26.6 27.6 0x1A 1.6 2.6 0x01 27.6 28.6 0x1B 2.6 3.6 0x02 28.6 29.6 0x1C 3.6 4.6 0x03 29.6 30.6 0x1D 4.6 5.6 0x04 30.6 31.6 0x1E 5.6 6.6 0x05 31.6 32.6 0x1F 6.6 7.6 0x06 32.6 33.6 0x20 7.6 8.6 0x07 33.6 34.6 0x21 8.6 9.6 0x08 34.6 35.6 0x22 9.6 10.6 0x09 35.6 36.6 0x23 10.6 11.6 0x0A 36.6 37.6 0x24 11.6 12.6 0x0B 37.6 38.6 0x25 12.6 13.6 0x0C 38.6 39.6 0x26 13.6 14.6 0x0D 39.6 40.6 0x27 14.6 15.6 0x0E 40.6 41.6 0x28 15.6 16.6 0x0F 41.6 42.6 0x29 16.6 17.6 0x10 42.6 43.6 0x2A 17.6 18.6 0x11 43.6 44.6 0x2B 18.6 19.6 0x12 44.6 45.6 0x2C
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19.3.2.2 Flash Security Register (FSEC)
The FSEC register holds all bits associated with the security of the MCU and Flash module. All bits in the FSEC register are readable but not writable. During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the Flash configuration field at global address 0xFF_FE0F located in P-Flash memory (see Table 19-4) as indicated by reset condition F in Figure 19-6. If a double bit fault is detected while reading the P-Flash phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be set to leave the Flash module in a secured state with backdoor key access disabled. 19.6 20.6 0x13 45.6 46.6 0x2D 20.6 21.6 0x14 46.6 47.6 0x2E 21.6 22.6 0x15 47.6 48.6 0x2F 22.6 23.6 0x16 48.6 49.6 0x30 23.6 24.6 0x17 49.6 50.6 0x31 24.6 25.6 0x18 25.6 26.6 0x19 1. BUSCLK is Greater Than this value. 2. BUSCLK is Less Than or Equal to this value. Offset Module Base + 0x0001 76543210 R KEYEN[1:0] RNV[5:2] SEC[1:0] W Reset F (1) 1. Loaded from Flash configuration field, during reset sequence. F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 19-6. Flash Security Register (FSEC) Table 19-9. FSEC Field Descriptions Field Description 7–6 KEYEN[1:0] Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the Flash module as shown in Table 19-10. 5–2 RNV[5:2] Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements. 1–0 SEC[1:0] Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 19-11. If the Flash module is unsecured using backdoor key access, the SEC bits are forced to 10. Table 19-8. FDIV values for various BUSCLK Frequencies BUSCLK Frequency (MHz) FDIV[5:0] BUSCLK Frequency (MHz) FDIV[5:0] MIN(1) MAX(2) MIN1 MAX2
Chapter 19 Flash Module (S12ZFTMRZ) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 627 The security function in the Flash module is described in Section 19.5.
19.3.2.3 Flash CCOB Index Register (FCCOBIX)
The FCCOBIX register is used to indicate the amount of parameters loaded into the FCCOB registers for Flash memory operations. CCOBIX bits are readable and writable while remaining bits read 0 and are not writable.
19.3.2.4 Flash Protection Status Register (FPSTAT)
This Flash register holds the status of the Protection Override feature. Table 19-10. Flash KEYEN States KEYEN[1:0] Status of Backdoor Key Access
00 DISABLED
01 DISABLED
(1) 1. Preferred KEYEN state to disable backdoor key access.
10 ENABLED
11 DISABLED
Table 19-11. Flash Security States SEC[1:0] Status of Security
00 SECURED
01 SECURED
(1) 1. Preferred SEC state to set MCU to secured state.
10 UNSECURED
11 SECURED
Offset Module Base + 0x0002 76543210 R 00000 CCOBIX[2:0] W R e s e t 00000000 = Unimplemented or Reserved Figure 19-7. FCCOB Index Register (FCCOBIX) Table 19-12. FCCOBIX Field Descriptions Field Description 2–0 CCOBIX[1:0] Common Command Register Index— The CCOBIX bits are used to indicate how many words of the FCCOB register array are being read or written to. See 19.3.2.13 Flash Common Command Object Registers (FCCOB),” for more details.
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All bits in the FPSTAT register are readable but are not writable.
19.3.2.5 Flash Configura tion Register (FCNFG)
The FCNFG register enables the Flash command complete interrupt, control generation of wait-states and forces ECC faults on Flash array read access from the CPU. CCIE, IGNSF, WSTAT, FDFD, and FSFD bits are readable and writable, ERSAREQ bit is read only, and remaining bits read 0 and are not writable. Offset Module Base + 0x0003 76543210 R FPOVRD 0 0 0 0 0 0 WSTATACK W R e s e t 00000001 = Unimplemented or Reserved Figure 19-8. Flash Protection Status Register (FPSTAT) Table 19-13. FPSTAT Field Descriptions Field Description FPOVRD Flash Protection Override Status — The FPOVRD bit indicates if the Protection Override feature is currently
0 Protection is not overridden
1 Protection is overridden, contents of registers FPRO T and/or DFPROT (and effective protection limits
determined by their current contents) were determined during execution of command Protection Override WSTATACK Wait-State Switch Acknowledge — The WSTATACK bit indicates that the wait-state configuration is effectively set according to the value configured on bits FCNFG[WSTAT] (see Section 19.3.2.5, “Flash Configuration Register (FCNFG)”). WSTATACK bit is cleared when a change in FCNFG[WSTAT] is requested by writing to those bits, and is set when the Flash has effectively switched to the new wait-state configuration. The application must check the status of WSTATACK bit to make sure it reads as 1 before changing the frequency setup (see Section 19.4.3, “Flash Block Read Access”).
0 Wait-State switch is pending, Flash reads are still happening according to the previous value of
FCNFG[WSTAT]
1 Wait-State switch is complete, Flash reads are already working according to the value set on
FCNFG[WSTAT] Offset Module Base + 0x0004 76543210 R CCIE IGNSF WSTAT[1:0] FDFD FSFD W R e s e t 00000000 = Unimplemented or Reserved Figure 19-9. Flash Configuration Register (FCNFG)
Chapter 19 Flash Module (S12ZFTMRZ) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 629 Table 19-14. FCNFG Field Descriptions Field Description CCIE Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 19.3.2.7) ERSAREQ Erase All Request — Requests the Memory Contro ller to execute the Erase All Blocks command and release security. ERSAREQ is not directly writable but is under indirect user control. Refer to the Reference Manual for assertion of the soc_erase_all_req input to the FTMRZ module.
0 No request or request complete
1 Request to:
a) run the Erase All Blocks command b) verify the erased state c) program the security byte in the Flash Configuration Field to the unsecure state d) release MCU security by setting the SEC field of the FSEC register to the unsecure state as defined in The ERSAREQ bit sets to 1 when soc_erase_all_req is asserted, CCIF=1 and the Memory Controller starts executing the sequence. ERSAREQ will be reset to 0 by the Memory Controller when the operation is completed IGNSF Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see Section 19.3.2.8).
0 All single bit faults detected during array reads are reported
1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated 3–2 WSTAT[1:0] Wait State control bits — The WSTAT[1:0] bits define how many wait-states are inserted on each read access to the Flash as shown on Table 19-15..Right after reset the maximum amount of wait-states is set, to be later re- configured by the application if needed. Depending on the system operating frequency being used the number of wait-states can be reduced or disabled, please refer to the Data Sheet for details. For additional information regarding the procedure to change this configuration please see Section 19.4.3. The WSTAT[1:0] bits should not be updated while the Flash is executing a command (CCIF=0); if that happens the value of this field will not change and no action will take place. FDFD Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array read operations. The FDFD bit is cleared by writing a 0 to FDFD. 0 Flash array read operations will set the DFDF flag in the FERSTAT register only if a double bit fault is detected
1 Any Flash array read operation will force the DFDF flag in the FERSTAT register to be set (see
Section 19.3.2.7) FSFD Force Single Bit Fault Detect — The FSFD bit allows the user to simulate a single bit fault during Flash array read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. 0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected 1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 19.3.2.7) and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see Section 19.3.2.6)
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19.3.2.6 Flash Erro r Configuration Register (FERCNFG)
The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. All assigned bits in the FERCNFG register are readable and writable.
19.3.2.7 Flash Status Register (FSTAT)
The FSTAT register reports the operational status of the Flash module. Table 19-15. Flash Wait-States control WSTAT[1:0] Wait-State configuration
00 ENABLED, maximum number of cycles (1)
- Reset condition. For a target of 100MHz core frequency / 50MHz bus frequency the maximum number required is 1 cycle. 01 reserved (2) 2. Value will read as 01 or 10, as written. In the current implementation the Flash will behave the same as 00 (wait- states enabled, maximum number of cycles). 10 reserved 2
Offset Module Base + 0x0005 76543210 R 0000000 SFDIE W R e s e t 00000000 = Unimplemented or Reserved Figure 19-10. Flash Error Configuration Register (FERCNFG) Table 19-16. FERCNFG Field Descriptions Field Description SFDIE Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault is detected during a Flash block read operation. 0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 19.3.2.8) 1 An interrupt will be requested whenever the SFDIF flag is set (see Section 19.3.2.8)
Chapter 19 Flash Module (S12ZFTMRZ) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 631 CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable but not writable, while remaining bits read 0 and are not writable.
19.3.2.8 Flash Error Status Register (FERSTAT)
The FERSTAT register reflects the error status of internal Flash operations. Offset Module Base + 0x0006 76543210 R CCIF ACCERR FPVIOL MGBUSY RSVD MGSTAT[1:0] W R e s e t 100000 0 (1) 1. Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 19.6). = Unimplemented or Reserved Figure 19-11. Flash Status Register (FSTAT) Table 19-17. FSTAT Field Descriptions Field Description CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation.
0 Flash command in progress
1 Flash command has completed
Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory caused by either a violation of the command write sequence (see Section 19.4.5.2) or issuing an illegal Flash command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR.
0 No access error detected
1 Access error detected
Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an address in a protected area of P-Flash or EEPROM memory during a command write sequence. The FPVIOL bit is cleared by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not possible to launch a command or start a command write sequence.
0 No protection violation detected
1 Protection violation detected
Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller .
0 Memory Controller is idle
1 Memory Controller is busy executing a Flash command (CCIF = 0)
Reserved Bit — This bit is reserved and always reads 0 . 1–0 MGSTAT[1:0] Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error is detected during execution of a Flash command or during the Flash reset sequence. The MGSTAT bits are cleared automatically at the start of the execution of a Flash command. See Section 19.4.7, “Flash Command Description,” and Section 19.6, “Initialization” for details.
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All flags in the FERSTAT register are readable and only writable to clear the flag.
19.3.2.9 P-Flash Protection Register (FPROT)
The FPROT register defines which P-Flash sectors are protected against program and erase operations. Offset Module Base + 0x0007 76543210 R 000000 DFDF SFDIF W R e s e t 00000000 = Unimplemented or Reserved Figure 19-12. Flash Error Status Register (FERSTAT) Table 19-18. FERSTAT Field Descriptions Field Description DFDF Double Bit Fault Detect Flag — The setting of the DFDF flag indicates that a double bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.(1) The DFDF flag is cleared by writing a 1 to DFDF. Writing a 0 to DFDF has no effect on DFDF.(2)
0 No double bit fault detected
1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while command running. See Section 19.4.3, “Flash Block Read Access” for details 1. In case of ECC errors the corresponding flag must be cleared for the proper setting of any further error, i.e. any new error will only be indicated properly when DFDF and/or SFDIF are clear at the time the error condition is detected. 2. There is a one cycle delay in storing the ECC DFDF and SFDIF fault flags in this register. At least one NOP is required after a flash memory read before checking FERSTAT for the occurrence of ECC errors. SFDIF Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation. The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF.
0 No single bit fault detected
1 Single bit fault detected and corrected or a Flash arra y read operation returning invalid data was attempted while command running Offset Module Base + 0x0008 76543210 R FPOPEN RNV6 FPHDIS FPHS[1:0] FPLDIS FPLS[1:0] W Reset F (1) 1. Loaded from Flash configuration field, during reset sequence. F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 19-13. Flash Protection Register (FPROT)
Chapter 19 Flash Module (S12ZFTMRZ) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 633 The (unreserved) bits of the FPROT register are writable Normal Single Chip Mode with the restriction that the size of the protected region can only be increased see Section 19.3.2.9.1, “P-Flash Protection Restrictions,” and Table 19-23.). All (unreserved) bits of the FPROT register are writable without restriction in Special Single Chip Mode. During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte in the Flash configuration field at global address 0xFF_FE0C located in P-Flash memory (see Table 19-4) as indicated by reset condition ‘F’ in Figure 19-13. To change the P-Flash protection that will be loaded during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected. Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. Table 19-19. FPROT Field Descriptions Field Description FPOPEN Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or erase operations as shown in Table 19-20 for the P-Flash block. 0 When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS and FPLS bits 1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS and FPLS bits RNV[6] Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements. FPHDIS Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory ending with global address 0xFF_FFFF.
0 Protection/Unprotection enabled
1 Protection/Unprotection disabled
4–3 FPHS[1:0] Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area in P-Flash memory as shown inTable 19-21. The FPHS bits can only be written to while the FPHDIS bit is set. FPLDIS Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory beginning with global address 0xFF_8000. 1–0 FPLS[1:0] Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area in P-Flash memory as shown in Table 19-22. The FPLS bits can only be written to while the FPLDIS bit is set.
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All possible P-Flash protection scenarios are shown in Figure 19-14 . Although the protection scheme is loaded from the Flash memory at global address 0xFF_FE0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in normal single chip mode while providing as much protection as possible if reprogramming is not required. Table 19-20. P-Flash Protection Function FPOPEN FPHDIS FPLDIS Function (1) 1. For range sizes, refer to Table 19-21 and Table 19-22. 1 1 1 No P-Flash Protection 1 1 0 Protected Low Range 1 0 1 Protected High Range 1 0 0 Protected High and Low Ranges 0 1 1 Full P-Flash Memory Protected 0 1 0 Unprotected Low Range 0 0 1 Unprotected High Range 0 0 0 Unprotected High and Low Ranges Table 19-21. P-Flash Protection Higher Address Range FPHS[1:0] Global Addre ss Range Protected Size 00 0xFF_F800–0xFF_FFFF 2 KB 01 0xFF_F000–0xFF_FFFF 4 KB 10 0xFF_E000–0xFF_FFFF 8 KB 11 0xFF_C000–0xFF_FFFF 16 KB Table 19-22. P-Flash Protection Lower Address Range FPLS[1:0] Global Address Range Protected Size 00 0xFF_8000–0xFF_83FF 1 KB 01 0xFF_8000–0xFF_87FF 2 KB 10 0xFF_8000–0xFF_8FFF 4 KB 11 0xFF_8000–0xFF_9FFF 8 KB
Chapter 19 Flash Module (S12ZFTMRZ) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 635 Figure 19-14. P-Flash Protection Scenarios 7 6 5 4 FPHS[1:0] FPLS[1:0]3 2 1 0 FPHS[1:0] FPLS[1:0] FPHDIS = 1 FPLDIS = 1 FPHDIS = 1 FPLDIS = 0 FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 Scenario Scenario Unprotected region Protected region with size Protected region Prot ected region with size defined by FPLS defined by FPHSnot defined by FPLS, FPHS 0xFF_8000 0xFF_FFFF 0xFF_8000 0xFF_FFFF FLASH START FLASH START FPOPEN = 1FPOPEN = 0
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19.3.2.9.1 P-Flash Pr otection Restrictions
In Normal Single Chip mode the general guideline is that P-Flash protection can only be added and not removed. Table 19-23 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions.
19.3.2.10 EEPROM Protection Register (DFPROT)
The DFPROT register defines which EEPROM sectors are protected against program and erase operations. The (unreserved) bits of the DFPROT register are writable in Normal Single Chip mode with the restriction that protection can be added but not removed. Writes in Normal Single Chip mode must increase the DPS value and the DPOPEN bit can only be written from 1 (protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is irrelevant. All DPOPEN/DPS bit registers are writable without restriction in Special Single Chip Mode. During the reset sequence, fields DPOPEN and DPS of the DFPROT register are loaded with the contents of the EEPROM protection byte in the Flash configuration field at global address 0xFF_FE0D located in Table 19-23. P-Flash Protection Scenario Transitions From Protection Scenario To Protection Scenario(1) 1. Allowed transitions marked with X, see Figure 19-14 for a definition of the scenarios. 01234567
0 XXXX
5 XXXX
6 XX XX
7 XXXXXXXX
Offset Module Base + 0x0009 76543210 R DPOPEN DPS[6:0] (1) 1. The number of implemented DPS bits depends on the EEPROM memory size, as explained below. W Reset F (2) 2. Loaded from Flash configuration field, during reset sequence. F2 F2 F2 F2 F2 F2 F2 = Unimplemented or Reserved Figure 19-15. EEPROM Protection Register (DFPROT)
Chapter 19 Flash Module (S12ZFTMRZ) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 637 P-Flash memory (see Table 19-4) as indicated by reset condition F in Table 19-25.. To change the EEPROM protection that will be loaded during the reset sequence, the P-Flash sector containing the EEPROM protection byte must be unprotected, then the EEPROM protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase containing the EEPROM protection byte during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the EEPROM memory fully protected. Trying to alter data in any protected area in the EEPROM memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. Block erase of the EEPROM memory is not possible if any of the EEPROM sectors are protected. The number of DPS bits depends on the size of the implemented EEPROM. The whole implemented EEPROM range can always be protected. Each DPS value increment increases the size of the protected range by 32-bytes. Thus to protect a 1 KB range DPS[4:0] must be set (protected range of 32 x 32 bytes). Table 19-24. DFPROT Field Descriptions Field Description DPOPEN EEPROM Protection Control
0 Enables EEPROM memory protection from program and erase with protected address range defined by DPS
1 Disables EEPROM memory protec tion from program and erase
6–0 DPS[6:0] EEPROM Protection Size — The DPS bits determine the size of the protected area in the EEPROM memory as shown inTable 19-25. . Table 19-25. EEPROM Protection Address Range DPS[6:0] Global Address Range Protected Size 0000000 0x10_0000 – 0x10_001F 32 bytes 0000001 0x10_0000 – 0x10_003F 64 bytes 0000010 0x10_0000 – 0x10_005F 96 bytes 0000011 0x10_0000 – 0x10_007F 128 bytes 0000100 0x10_0000 – 0x10_009F 160 bytes The Protection Size goes on enlarging in step of 32 bytes, for each DPS value increment 0001111 0x 10_0000 – 0x10_01FF 512 bytes 0011111 0x10_0000 – 0x10_03FF 1K byte 0111111 0x 10_0000 – 0x10_07FF 2K bytes 1111111 0x10_0 000 – 0x10_0FFF 4K bytes
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19.3.2.11 Flash Option Register (FOPT)
The FOPT register is the Flash option register. All bits in the FOPT register are readable but can only be written in special mode. During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash configuration field at global address 0xFF_FE0E located in P-Flash memory (see Table 19-4) as indicated by reset condition F in Figure 19-16. If a double bit fault is detected while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set.
19.3.2.12 Flash Reserved1 Register (FRSV1)
This Flash register is reserved for factory testing. All bits in the FRSV1 register read 0 and are not writable.
19.3.2.13 Flash Common Comma nd Object Registers (FCCOB)
The FCCOB is an array of six words. Byte wide reads and writes are allowed to the FCCOB registers. Offset Module Base + 0x000A 76543210 R NV[7:0] W Reset F (1) 1. Loaded from Flash configuration field, during reset sequence. F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 19-16. Flash Option Register (FOPT) Table 19-26. FOPT Field Descriptions Field Description 7–0 NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device overview for proper use of the NV bits. Offset Module Base + 0x000B 76543210 R 00000000 W R e s e t 00000000 = Unimplemented or Reserved Figure 19-17. Flash Reserved1 Register (FRSV1)
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Offset Module Base + 0x0011 76543210 R CCOB[7:0] W R e s e t 00000000 Figure 19-23. Flash Common Command Object 2 Low Register (FCCOB2LO) Offset Module Base + 0x0012 76543210 R CCOB[15:8] W R e s e t 00000000 Figure 19-24. Flash Common Command Object 3 High Register (FCCOB3HI) Offset Module Base + 0x0013 76543210 R CCOB[7:0] W R e s e t 00000000 Figure 19-25. Flash Common Command Object 3 Low Register (FCCOB3LO) Offset Module Base + 0x0014 76543210 R CCOB[15:8] W R e s e t 00000000 Figure 19-26. Flash Common Command Object 4 High Register (FCCOB4HI) Offset Module Base + 0x0015 76543210 R CCOB[7:0] W R e s e t 00000000 Figure 19-27. Flash Common Command Object 4 Low Register (FCCOB4LO)
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19.3.2.13.1 FCCOB - NVM Command Mode
NVM command mode uses the FCCOB registers to provide a command code and its relevant parameters to the Memory Controller. The user first sets up all required FCCOB fields and then initiates the command’s execution by writing a 1 to the CCIF bit in the FSTAT register (a 1 written by the user clears the CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register all FCCOB parameter fields are locked and cannot be changed by the user until the command completes (as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the FCCOB register array. The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 19-27. The return values are available for reading after the CCIF flag in the FSTAT register has been returned to 1 by the Memory Controller. The value written to the FCCOBIX field must reflect the amount of CCOB words loaded for command execution. Table 19-27 shows the generic Flash command format. The high byte of the first word in the CCOB array contains the command code, followed by the parameters for this specific Flash command. For details on the FCCOB settings required by each command, see the Flash command descriptions in Section 19.4.7. Offset Module Base + 0x0016 76543210 R CCOB[15:8] W R e s e t 00000000 Figure 19-28. Flash Common Command Object 5 High Register (FCCOB5HI) Offset Module Base + 0x0017 76543210 R CCOB[7:0] W R e s e t 00000000 Figure 19-29. Flash Common Command Object 5 Low Register (FCCOB5LO) Table 19-27. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Register Byte FCCOB Parameter Fields (NVM Command Mode)
000 FCCOB0
HI FCMD[7:0] defining Flash command LO Global address [23:16]
001 FCCOB1
HI Global address [15:8] LO Global address [7:0]
010 FCCOB2
HI Data 0 [15:8] LO Data 0 [7:0]
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19.4 Functional Description
19.4.1 Modes of Operation
The module provides the modes of operation normal and special. The operating mode is determined by module-level inputs and affects the FCLKDIV , FCNFG , and DFPROT registers (see Table 19-29.).
19.4.2 IFR Version ID Word
The version ID word is stored in the IFR at address 0x1F_C0B6. The contents of the word are defined in Table 19-28.
- VERNUM: Version number. The first versi on is number 0b_0001 with both 0b_0000 and 0b_1111 meaning ‘none’.
19.4.3 Flash Block Read Access
If data read from the Flash block results in a double-bit fault ECC error (meaning that data is detected to be in error and cannot be corrected), the read data will be tagged as invalid during that access (please look into the Reference Manual for details). Forcing the DFDF status bit by setting FDFD (see Section 19.3.2.5) has effect only on the DFDF status bit value and does not result in an invalid access.
011 FCCOB3
HI Data 1 [15:8] LO Data 1 [7:0]
100 FCCOB4
HI Data 2 [15:8] LO Data 2 [7:0]
101 FCCOB5
HI Data 3 [15:8] LO Data 3 [7:0] Table 19-28. IFR Version ID Fields [15:4] [3:0] Reserved VERNUM Table 19-27. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Register Byte FCCOB Parameter Fields (NVM Command Mode)
Chapter 19 Flash Module (S12ZFTMRZ) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 643 To guarantee the proper read timing from the Flash array, the Flash will control (i.e. pause) the S12Z core accesses, considering that the MCU can be configured to fetch data at a faster frequency than the Flash block can support. Right after reset the Flash will be configured to run with the maximum amount of wait- states enabled; if the user application is setup to run at a slower frequency the control bits FCNFG[WSTAT] (see Section 19.3.2.5) can be configured by the user to disable the generation of wait- states, so it does not impose a performance penalty to the system if the read timing of the S12Z core is setup to be within the margins of the Flash block. For a definition of the frequency values where wait-states can be disabled please refer to the device electrical parameters. The following sequence must be followed when the transition from a higher frequency to a lower frequency is going to happen:
- Flash resets with wait-states enabled;
- system frequency must be conf igured to the lower target;
- user writes to FNCNF[WSTAT] to disable wait-states;
- user reads the value of FPSTAT[WSTATACK], the ne w wait-state configuration will be effective when it reads as 1;
- user must re-write FCLKDIV to set a new value based on the lower frequency. The following sequence must be followed on the contrary direction, going from a lower frequency to a higher frequency:
- user writes to FCNFG[WSTAT] to enable wait-states;
- user reads the value of FPSTAT[WSTATACK], the ne w wait-state configuration will be effective when it reads as 1;
- user must re-write FCLKDIV to set a new value based on the higher frequency;
- system frequency must be set to the upper target. CAUTION If the application is going to require the frequency setup to change, the value to be loaded on register FCLKDIV will have to be updated according to the new frequency value. In this scenario the application must take care to avoid locking the value of the FCLKDIV register: bit FDIVLCK must not be set if the value to be loaded on FDIV is going to be re-written, otherwise a reset is going to be required. Please refer to Section 19.3.2.1, “Flash Clock Divider Register (FCLKDIV) and Section 19.4.5.1, “Writing the FCLKDIV Register.
19.4.4 Internal NVM resource
IFR is an internal NVM resource readable by CPU. The IFR fields are shown in Table 19-5.. The NVM Resource Area global address map is shown in Table 19-6..
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19.4.5 Flash Command Operations
Flash command operations are used to modify Flash memory contents. The next sections describe:
- How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from BUSCLK for Flash program and erase command operations
- The command write sequence used to set Fl ash command parameters and launch execution
- Valid Flash commands available for executi on, according to MCU functional mode and MCU security state.
19.4.5.1 Writing the FCLKDIV Register
Prior to issuing any Flash program or erase command after a reset, the user is required to write the FCLKDIV register to divide BUSCLK down to a target FCLK of 1 MHz. Table 19-8. shows recommended values for the FDIV field based on BUSCLK frequency. NOTE Programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 0.8 MHz. Setting FDIV too high can destroy the Flash memory due to overstress. Setting FDIV too low can result in incomplete programming or erasure of the Flash memory cells. When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written, any Flash program or erase command loaded during a command write sequence will not execute and the ACCERR bit in the FSTAT register will set.
19.4.5.2 Command Write Sequence
The Memory Controller will launch all valid Flash commands entered using a command write sequence. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see Section 19.3.2.7) and the CCIF flag should be tested to determine the status of the current command write sequence. If CCIF is 0, the previous command write sequence is still active, a new command write sequence cannot be started, and all writes to the FCCOB register are ignored.
19.4.5.2.1 Define FCCOB Contents
The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. The CCOBIX bits in the FCCOBIX register must reflect the amount of words loaded into the FCCOB registers (see Section 19.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF flag will remain clear until the Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic command write sequence is shown in Figure 19-30.
Chapter 19 Flash Module (S12ZFTMRZ) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors 645 Figure 19-30. Generic Flash Command Write Sequence Flowchart Write to FCCOBIX register Write: FSTAT register (to launch command) Clear CCIF 0x80 Clear ACCERR/FPVIOL 0x30 Write: FSTAT registeryes no Access Error and Protection Violation Read: FSTAT register START Check FCCOB ACCERR/ FPVIOL Set? EXIT Write: FCLKDIV register Read: FCLKDIV register yes noFDIV Correct? noBit Polling for Command Completion Check yes CCIF Set? to indicate number of parameters to be loaded. Write to FCCOB register to load required command parameter. yes no More Parameters? Availability Check Results from previous Command Note: FCLKDIV must be set after each reset Read: FSTAT register no yes CCIF Set? no yes CCIF Set? Clock Divider Value Check Read: FSTAT register
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19.4.5.3 Valid Flash Module Commands
Table 19-29. present the valid Flash commands, as enabled by the combination of the functional MCU mode (Normal SingleChip NS, Special Singlechip SS) with the MCU security state (Unsecured, Secured). Table 19-29. Flash Commands by Mode and Security State FCMD Command Unsecured Secured NS (1) 1. Unsecured Normal Single Chip mode SS(2) 2. Unsecured Special Single Chip mode. NS (3) 3. Secured Normal Single Chip mode. SS(4) 4. Secured Special Single Chip mode. 0x01 Erase Verify All Blocks 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once 0x08 Erase All Blocks 0x09 Erase Flash Block 0x0A Erase P-Flash Sector 0x0B Unsecure Flash 0x0C Verify Backdoor Access Key 0x0D Set User Margin Level 0x0E Set Field Margin Level 0x10 Erase Verify EEPROM Section 0x11 Program EEPROM 0x12 Erase EEPROM Sector 0x13 Protection Override
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19.4.5.4 P-Flash Commands
Table 19-30 summarizes the valid P-Flash commands along with the effects of the commands on the P- Flash block and other resources within the Flash module.
19.4.5.5 EEPROM Commands
Table 19-31 summarizes the valid EEPROM commands along with the effects of the commands on the EEPROM block. Table 19-30. P-Flash Commands FCMD Command Function on P-Flash Memory 0x01 Erase Verify All Blocks Verify that all P-Flash (and EEPROM) blocks are erased. 0x02 Erase Verify Block Verify t hat a P-Flash block is erased. 0x03 Erase Verify P- Flash Section Verify that a given number of words starting at the address provided are erased. 0x04 Read Once Read a dedicated 64 byte field in the nonvolatile information register in P-Flash block that was previously programmed using the Program Once command. 0x06 Program P-Flash Program a phrase in a P-Flash block. 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and EEPROM) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the DFPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a P-Flash (or EEPROM) block. An erase of the full P-Flash block is only possible when FPLDIS, FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command. 0x0A Erase P-Flash Sector Erase all bytes in a P-Flash sector. 0x0B Unsecure Flash Supports a method of releasing MCU security by erasing all P-Flash (and EEPROM) blocks and verifying that all P-Flash (and EEPROM) blocks are erased. 0x0C Verify Backdoor Access Key Supports a method of releasing MCU security by verifying a set of security keys. 0x0D Set User Margin Level Specifies a user margin read level for all P-Flash blocks. 0x0E Set Field Margin Level Specifies a field margin read level for all P-Flash blocks (special modes only). 0x13 Protection Override Supports a mode to temporarily override Protection configuration (for P-Flash and/or EEPROM) by verifying a key.
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