STS8DNF3LL_07 STMICROELECTRONICS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 12

Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuit
  • 4 Package mechanical data
  • 5 Revision history

Dual N-channel 30V - 0.017Ω - 8A SO-8 Low gate charge STripFET™ II Power MOSFET General features ■ Optimal RDS(on) x Qg trade-off @ 4.5V ■ Conduction losses reduced ■ Switching losses reduced

Description

This application specific Power MOSFET is the second generation of STMicroelectronics unique "Single Feature Size™" strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high efficiency are of paramount importance.

Applications

■ Switching application Internal schematic diagram Type V DSS RDS(on) ID STS8DNF3LL 30V <0.020 Ω 8A S0-8 Order codes Part number Marking Package Packaging STS8DNF3LL S8DNF3LL SO-8 Tape & reel

1 Electrical ratings

Table 1. Absolute maximum ratings

  1. Pulse width limited by safe operating area

Table 2. Thermal data

  1. Mounted on FR-4 board with 0.5 in 2 pad of Cu.

2 Electrical characteristics

Table 3. On/off states Table 4. Dynamic

  1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5.

Table 5. Switching times

Table 6. Source drain diode

  1. Pulse width limited by safe operating area.
  2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%

2.1 Electrical characterist ics (curves)

Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characteristics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance

3 Test circuit

Figure 13. Switching times test circuit for Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at : www.st.com

DIM. mm. inch A 1.75 0.068 a1 0.1 0.25 0.003 0.009 a2 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 c1 45 (typ.) D 4.8 5.0 0.188 0.196 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 F 3.8 4.0 0.14 0.157 L 0.4 1.27 0.015 0.050 M 0.6 0.023 S 8 (max.) SO-8 MECHANICAL DATA

5 Revision history

Table 7. Revision history 30-Jan-2007 10 Typo mistake on Ta ble 1.