S87C752-5N28

83C752 PHILIPS | Alldatasheet

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Technical content

/C0109 /C0110 /C0114 83C752/87C752 80C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count Product specification Supersedes data of 1998 Jan 19 IC20 Data Handbook

1998 May 01

Philips Semiconductors Product specification 83C752/87C75280C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count

21998 May 01 853-1443 19328

DESCRIPTION

The Philips 83C752/87C752 offers many of the advantages of the 80C51 architecture in a small package and at low cost. The 8XC752 Microcontroller is fabricated with Philips high-density CMOS technology. Philips epitaxial substrate minimizes CMOS latch-up sensitivity. The 8XC752 contains a 2k × 8 ROM (83C752) EPROM (87C752), a 64 × 8 RAM, 21 I/O lines, a 16-bit auto-reload counter/timer, a fixed-priority level interrupt structure, a bidirectional inter-integrated circuit (I2C) serial bus interface, an on-chip oscillator, a five channel multiplexed 8-bit A/D converter, and an 8-bit PWM output. The onboard inter-integrated circuit (I2C) bus interface allows the 8XC752 to operate as a master or slave device on the I2C small area network. This capability facilitates I/O and RAM expansion, access to EEPROM, processor-to-processor communication, and efficient interface to a wide variety of dedicated I 2C peripherals. The EPROM version of this device, the 87C752, is available in both quartz-lid erasable and plastic one-time programmable (OTP) packages. Once the array has been programmed, it is functionally equivalent to the masked ROM 83C752. Thus, unless explicitly stated otherwise, all references made to the 83C752 apply equally to the 87C752. The 83C752 supports two power reduction modes of operation referred to as the idle mode and the power-down mode.

FEATURES

• Available in erasable quartz lid or One-Time Programmable plastic packages
• 80C51 based architecture
• Inter-integrated Circuit (I2C) serial bus interface
• Small package sizes – 28-pin DIP – 28-pin PLCC – 28-pin SSOP
• Wide oscillator frequency range
• Low power consumption: – Normal operation: less than 11mA @ 5V, 12MHz – Idle mode – Power-down mode
• 2k × 8 ROM (83C752) EPROM (87C752)
• 64 × 8 RAM
• 16-bit auto reloadable counter/timer
• 5-channel 8-bit A/D converter
• 8-bit PWM output/timer
• Fixed-rate timer
• Boolean processor
• CMOS and TTL compatible
• Well suited for logic replacement, consumer and industrial

applications

ROM EPROM TEMPERATURE RANGE °C AND PACKAGE FREQUENCY DRAWING NUMBER S83C752–1DB S87C752–1DB OTP 0 to +70, 28-pin Plastic Shrink Small Outline Package3.5 to 12MHz SOT341-1 S83C752–1N28 S87C752–1N28 OTP 0 to +70, 28-pin Plastic Dual In-line Package3.5 to 12MHz SOT117-2 S83C752–2N28 S87C752–2N28 OTP –40 to +85, 28-pin Plastic Dual In-line Package3.5 to 12MHz SOT117-2 S83C752–4DB S87C752–4DB OTP 0 to +70, 28-pin Plastic Shrink Small Outline Package3.5 to 16MHz SOT341-1 S83C752–4N28 S87C752–4N28 OTP 0 to +70, 28-pin Plastic Dual In-line Package3.5 to 16MHz SOT117-2 S83C752–5N28 S87C752–5N28 OTP –40 to +85, 28-pin Plastic Dual In-line Package3.5 to 16MHz SOT117-2 S83C752–1A28 S87C752–1A28 OTP 0 to +70, 28-pin Plastic Leaded Chip Carrier3.5 to 12MHz SOT261-3 S83C752–2A28 S87C752–2A28 OTP –40 to +85, 28-pin Plastic Leaded Chip Carrier3.5 to 12MHz SOT261-3 S83C752–4A28 S87C752–4A28 OTP 0 to +70, 28-pin Plastic Leaded Chip Carrier3.5 to 16MHz SOT261-3 S83C752–5A28 S87C752–5A28 OTP –40 to +85, 28-pin Plastic Leaded Chip Carrier3.5 to 16MHz SOT261-3 S83C752–6A28 S87C752–6A28 OTP –55 to +125, 28-pin Plastic Leaded Chip Carrier3.5 to 12MHz SOT261-3 S83C752–6N28 S87C752–6N28 OTP –55 to +125, 28-pin Plastic Dual In-line Package3.5 to 12MHz SOT117-2 NOTE: 1. OTP = One Time Programmable EPROM.

Philips Semiconductors Product specification 83C752/87C75280C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count

1998 May 01 3

INTERRUPT, SERIAL PORT AND TIMER BLOCKS I2C CONTROL PWM P0.0–P0.4 ADC AV SS AV CC PORT 0 DRIVERS RAM ADDR REGISTER PORT 0 LATCH PORT 2 LATCH STACK POINTER PROGRAM ADDRESS REGISTER PC INCRE- MENTER PROGRAM COUNTER PORT 3 DRIVERS PORT 1 DRIVERS PORT 3 LATCH PORT 1 LATCH TIMING AND CONTROL B REGISTER SU00319

Philips Semiconductors Product specification 83C752/87C75280C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count

1998 May 01 4

P3.4/A4 P3.3/A3 P3.2/A2/A10 P3.1/A1/A9 P3.0/A0/A8 P0.2/V PP RST VSS P0.0/SCL/ASEL P1.4/ADC4/D4 AV SS AV CC P1.5/INT0/D5 P1.6/INT1/D6 P1.7/T0/D7 P0.3 P0.4/PWM OUT P3.7/A7 P3.6/A6 P3.5/A5 V CC PLASTIC DUAL IN-LINE PACKAGE AND SHRINK SMALL OUTLINE PACKAGE PLASTIC LEADED CHIP CARRIER 41 2 6 12 18 P0.1/SDA/OE–PGM P1.0/ADC0/D0 P1.1/ADC1/D1 P1.3/ADC3/D3 P1.2/ADC2/D2 Pin Function 1 P3.4/A4 2 P3.3/A3 3 P3.2/A2/A10 4 P3.1/A1/A9 5 P3.0/A0/A8 6 P0.2/V PP 7 P0.1/SDA/OE-PGM 8 P0.0/SCL/ASEL

9 RST

13 P1.0/ADC0/D0 14 P1.1/ADC1/D1 Pin Function 15 P1.2/ADC2/D2 16 P1.3/ADC3/D3 17 P1.4/ADC4/D4 18 AV SS

19 AV CC

20 P1.5/INT0 /D5 21 P1.6/INT1 /D6 22 P1.7/T0/D7 23 P0.3 24 P0.4/PWM OUT 25 P3.7/A7 26 P3.6/A6 27 P3.5/A5 28 V CC SU00318

Philips Semiconductors Product specification 83C752/87C75280C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count

1998 May 01 5

MNEMONIC PIN NO. TYPE NAME AND FUNCTION VSS 12 I Circuit Ground Potential. VCC 28 I Supply voltage during normal, idle, and power-down operation. P0.0–P0.4 8–6 23, 24 1s written to them float, and in that state can be used as high-impedance inputs. P0.3–P0.4 are bidirectional I/O port pins with internal pull-ups. Port 0 also serves as the serial I2C interface. When this feature is activated by software, SCL and SDA are driven low in accordance with the I2C protocol. These pins are driven low if the port register bit is written with a 0 or if the I2C subsystem presents a 0. The state of the pin can always be read from the port register by the program. Port 0.3 and 0.4 have internal pull-ups that function identically to port 3. Pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. To comply with the I2C specification, P0.0 and P0.1 are open drain bidirectional I/O pins with the electrical characteristics listed in the tables that follow. While these differ from “standard TTL” characteristics, they are close enough for the pins to still be used as general-purpose I/O in non-I applications. 6 I VPP (P0.2) – Programming voltage input. (See Note 2.) 7 I OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode. OE/PGM = 1 output enabled (verify mode). OE/PGM = 0 program mode. 8 I ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3. ASEL = 0 low address byte available on port 3. ASEL = 1 high address byte available on port 3 (only the three least significant bits are used). P1.0–P1.7 13–17, 20–22 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. P0.3–P0.4 pins are bidirectional I/O port pins with internal pull-ups. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). Port 1 also serves the special function features of the SC80C51 family as listed below: 20 I INT0 (P1.5): External interrupt. 21 I INT1 (P1.6): External interrupt. 22 I T0 (P1.7): Timer 0 external input. 13–17 I ADC0 (P1.0)–ADC4 (P1.4): Port 1 also functions as the inputs to the five channel multiplexed A/D converter. These pins can be used as outputs only if the A/D function has been disabled. These pins can be used as inputs while the A/D converter is enabled. Port 1 serves to output the addressed EPROM contents in the verify mode and accepts as inputs the value to program into the selected address during the program mode. P3.0–P3.7 5–1, 27–25 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: I IL). Port 3 also functions as the address input for the EPROM memory location to be programmed (or verified). The 11-bit address is multiplexed into this port as specified by P0.0/ASEL. RST 9 I Reset: A high on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to VSS permits a power-on RESET using only an external capacitor to VCC . After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places the device in the programming state allowing programming address, data and V PP to be applied for programming or verification purposes. The RESET serial sequence must be synchronized with the X1 input. X1 11 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the programming state. X2 10 O Crystal 2: Output from the inverting oscillator amplifier. AV CC 1 19 I Analog supply voltage and reference input. AV SS 1 18 I Analog supply and reference ground. NOTE: 1. AVSS (reference ground) must be connected to 0V (ground). AVCC (reference input) cannot differ from VCC by more than ±0.2V, and must be in the range 4.5V to 5.5V. 2. When P0.2 is at or close to 0V, it may affect the internal ROM operation. We recommend that P0.2 be tied to VCC via a small pull-up (e.g., 2kΩ ).

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amplifier which can be configured for use as an on-chip oscillator. reference voltages before an A/D conversion is started. pointer registers (DPH, DPL). Nine of the SFRs are bit addressable. independent 8-bit registers. reduced power modes are in the special function register PCON. Table 1. External Pin Status During Idle and

• Except for PWM output (P0.4).

program instructions as well as constants such as look-up tables. The program memory space contains 2k bytes in the 8XC752. 3FH) are implemented in the 8XC752.

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Figure 1. Port Bit Latches and I/O Buffers these pins may be used as I/O ports. the 80C51, but also includes alternate input functions on all pins. enabled, the analog inputs are floating. applicable). See Figure 1 for port bit configurations. counter are centralized in a single register called TCON. the different interrupt sources of the 8XC752.

Philips Semiconductors Product specification 83C752/87C75280C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count

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EA EAD ETI ES EPWM EX1 ET0 EX0 Position Symbol Function IE.7 EA Global interrupt disable when EA = 0 IE.6 EAD A/D conversion complete IE.5 ETI Timer I IE.4 ES I 2C serial port IE.3 EPWM PWM counter overflow IE.2 EX1 External interrupt 1 IE.1 ET0 Timer 0 overflow IE.0 EX0 External interrupt 0 Serial Communications The 8XC752 contains an I2C serial communications port instead of the 80C51 UART. The I2C serial port is a single bit hardware interface with all of the hardware necessary to support multimaster and slave operations. Also included are receiver digital filters and timer (timer I) for communication watch-dog purposes. The I2C serial port is controlled through four special function registers; I2C control, I2C data, I2C status, and I2C configuration. The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. The main technical features of the bus are:

• Bidirectional data transfer between masters and slaves
• Serial addressing of slaves
• Acknowledgment after each transferred byte
• Multimaster bus
• Arbitration between simultaneously transmitting master without corruption of serial data on bus
• With 82B715, communication distance is extended to beyond 100 feet (30M) A large family of I 2C compatible ICs is available. See the I2C section for more details on the bus and available ICs. The 83C752 I2C subsystem includes hardware to simplify the software required to drive the I2C bus. This circuitry is the same as that on the 83C751. (See the 83C751 section for a detailed discussion of this subsystem). Pulse Width Modulation Output (P0.4) The PWM outputs pulses of programmable length and interval. The repetition frequency is defined by an 8-bit prescaler which generates the clock for the counter. The prescaler register is PWMP. The prescaler and counter are not associated with any other timer. The 8-bit counter counts modulo 255, that is from 0 to 254 inclusive. The value of the 8-bit counter is compared to the contents of a compare register, PWM. When the counter value matches the contents of this register, the output of the PWM is set high. When the counter reaches zero, the output of the PWM is set low. The pulse width ratio (duty cycle) is defined by the contents of the compare register and is in the range of 0 to 1 programmed in increments of 1/255. The PWM output can be set to be continuously high by loading the compare register with 0 and the output can be set to be continuously low by loading the compare register with 255. The PWM output is enabled by a bit in a special function register, PWENA. When enabled, the pin output is driven with a fully active pull-up. That is, when the output is high, a strong pull-up is continuously applied. when disabled, the pin functions as a normal bidirectional I/O pin, however, the counter remains active. The PWM function is disabled during RESET and remains disabled after reset is removed until re-enabled by software. The PWM output is high during power down and idle. The counter is disabled during idle. The repetition frequency of the PWM is given by: f PWM = fOSC / 2 (1 + PWMP) 255 The low/high ratio of the PWM signal is PWM / (255 – PWM) for PWM not equal to 255. For PWM = 255, the output is always low. The repetition frequency range is 92Hz to 23.5kHz for an oscillator frequency of 12MHz. An interrupt will be asserted upon PWM counter overflow if the interrupt is not masked off. The PWM output is an alternative function of P0.4. In order to use this port as a bidirectional I/O port, the PWM output must be disabled by clearing the enable/disable bit in PWENA. In this case, the PWM subsystem can be used as an interval timer by enabling the PWM interrupt.

1998 May 01 9

Table 2. 8XC752 Special Function Registers # SFRs are modified from or added to the 80C51 SFRs.

Philips Semiconductors Product specification 83C752/87C75280C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count

1998 May 01 10

Special Function Register Addresses Special function registers for the 8XC752 are identical to those of the 80C51, except for the changes listed below: 80C51 special function registers not present in the 8XC752 are TMOD (89), P2 (A0) and IP (B8). The 80C51 registers TH1, TL1, SCON, and SBUF are replaced with the 8XC752 registers RTH, RTL, I2CON, and I2DAT, respectively. Additional special function registers are I2CFG (D8) and I2STA (FB), ADCON (A0), ADAT (84), PWM (8E), PWMP (8F), and PWENA (FE). See Table 3. A/D Converter The analog input circuitry consists of a 5-input analog multiplexer and an A to D converter with 8-bit resolution. The conversion takes 40 machine cycles, i.e., 40µs at 12MHz oscillator frequency. The A/D converter is controlled using the ADCON control register. Input channels are selected by the analog multiplexer through ADCON register bits 0–2. The 83C752 contains a five-channel multiplexed 8-bit A/D converter. The conversion requires 40 machine cycles (40µs at 12MHz oscillator frequency). The A/D converter is controlled by the A/D control register, ADCON. Input channels are selected by the analog multiplexer by bits ADCON.0 through ADCON.2. The ADCON register is not bit addressable. ADCON Register MSB LSB X X ENADC ADCI ADCS AADR2 AADR1 AADR0 ADCI ADCS Operation 0 0 ADC not busy, a conversion can be started. 0 1 ADC busy, start of a new conversion is blocked. 1 0 Conversion completed, start of a new conversion is blocked. 1 1 Not possible. INPUT CHANNEL SELECTION ADDR2 ADDR1 ADDR0 INPUT PIN 0 0 0 P1.0 0 0 1 P1.1 0 1 0 P1.2 0 1 1 P1.3 1 0 0 P1.4 Position Symbol Function ADCON.5 ENADC Enable A/D function when ENADC = 1. Reset forces ENADC = 0. ADCON.4 ADCI ADC interrupt flag. This flag is set when an ADC conversion is complete. If IE.6 = 1, an interrupt is requested when ADCI = 1. The ADCI flag is cleared when conversion data is read. This flag is read only. ADCON.3 ADCS ADC start. Setting this bit starts an A/D conversion. Once set, ADCS remains high throughout the conversion cycle. On completion of the conversion, it is reset just before the ADCI interrupt flag is cleared. ADCS cannot be reset by software. ADCS should not be used to monitor the A/D converter status. ADCI should be used for this purpose. ADCON.2 AADR2 Analog input select. ADCON.1 AADR1 Analog input select. ADCON.0 AADR0 Analog input select. This binary coded address selects one of the five analog input port pins of P1 to be input to the converter. It can only be changed when ADCI and ADCS are both low. AADR2 is the most significant bit. The completion of the 8-bit ADC conversion is flagged by ADCI in the ADCON register, and the result is stored in the special function register ADAT. An ADC conversion in progress is unaffected by an ADC start. The result of a completed conversion remains unaffected provided ADCI remains at a logic 1. While ADCS is a logic 1 or ADCI is a logic 1, a new ADC START will be blocked and consequently lost. An ADC conversion in progress is aborted when the idle or power-down mode is entered. The result of a completed conversion (ADCI = logic 1) remains unaffected when entering the idle mode. See Figure 2 for an A/D input equivalent circuit. The analog input pins ADC0-ADC4 may be used as digital inputs and outputs when the A/D converter is disabled by a 0 in the ENADC bit in ADCON. When the A/D is enabled, the analog input channel that is selected by the ADDR2-ADDR0 bits in ADCON cannot be used as a digital input. Reading the selected A/D channel as a digital input will always return a 1. The unselected A/D inputs may always be used as digital inputs. Unselected analog inputs will be floating and may not be used as digital outputs. The A/D reference inputs on the 8XC752 are tied together with the analog supply pins AV CC and AVSS . This means that the reference voltage on the A/D cannot be varied separately from the analog supply pins. AVSS must be connected to 0V and AVCC must be connected to a supply voltage between 4.5V and 5.5V. A/D measurements may be made in the range of 4.5V to 5.5V. Increasing the voltage on the A/D ground reference above 0V or reducing the voltage on the positive A/D reference below 4.5V is not permitted.

1998 May 01 11

be noted that the sampling causes the analog input to present a varying load to an analog source. Figure 2. A/D Input: Equivalent Circuit the actual analog input voltage required to produce the same code. not specified with a code is the maximum over all codes. also integral non-linearity. sometimes be referred to as full scale error. converter resulting from a signal applied to one deselected channel. first transition point to the ideal last transition point. generally expressed in LSBs or in percent of FSR.

1998 May 01 12

similar to mode 2 of the 80C51 counter/timer, extended to 16 bits. controlled using the timer control register (TCON). 0 – Timer 0 is enabled only when TR is 1. TCON.6 C/T 1 – Counter operation from T0 pin. 0 – Timer operation from internal clock. TCON.5 TF 1 – Set on overflow of T0. TCON.2 IT0 1 – INT0 is edge triggered. 0 – INT0 is level sensitive. TCON.0 IT1 1 – INT1 is edge triggered. 0 – INT1 is level sensitive. flags are combined into one register. for use as a fixed time base. interrupt is enabled, will generate an interrupt (see Figure 3). Figure 3. 83C752 Counter/Timer Block Diagram Table 3. I2C Special Function Register Addresses

Philips Semiconductors Product specification 83C752/87C75280C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count

1998 May 01 13

ABSOLUTE MAXIMUM RATINGS 1, 3, 4 PARAMETER RATING UNIT Storage temperature range –65 to +150 °C Voltage from VCC to VSS –0.5 to +6.5 V Voltage from any pin to VSS (except VPP ) –0.5 to VCC + 0.5 V Power dissipation 1.0 W Voltage from VPP pin to VSS –0.5 to + 13.0 V DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, AVCC = 5V ±5, AVSS = 0V4 VCC = 5V ± 10%, VSS = 0V TEST LIMITS4 SYMBOL PARAMETER CONDITIONS MIN Typical1 MAX UNIT ICC Supply current (see Figure 6) Inputs VIL Input low voltage, except SDA, SCL (0 to 70°C) (–40 to +85°C) –0.5 –0.5 0.2VCC –0.1 0.2VCC –0.15 V V VIH Input high voltage, except X1, RST (0 to 70°C) (–40 to +85°C) 0.2VCC +0.9 (0.2VCC +1) VCC +0.5 VCC +0.5 V V VIH1 Input high voltage, X1, RST (0 to 70°C) (–40 to +85°C) 0.7VCC 0.7VCC to 0.1 VCC +0.5 VCC +0.5 V V SDA, SCL, P0.2 VIL1 Input low voltage (0 to 70°C) (–40 to +85°C) –0.5 –0.5 0.3VCC 0.3VCC –0.1 V V VIH2 Input high voltage (0 to 70°C) (–40 to –85°C) 0.7VCC 0.7VCC +0.1 VCC +0.5 VCC +0.5 V Outputs VOL Output low voltage, ports 1, 3, 0.3, and 0.4 (PWM disabled) IOL = 1.6mA2 0.45 V VOL1 Output low voltage, port 0.2 IOL = 3.2mA2 0.45 V VOH Output high voltage, ports 1, 3, 0.3, and 0.4 (PWM disabled) IOH = –60µA, 2.4 V IOH = –25µA 0.75VCC V IOH = –10µA 0.9VCC V IOH = –400µA 2.4 V VOH2 Output high voltage, P0.4 (PWM enabled) IOH = –40µA 0.9VCC V Port 0.0 and 0.1 (I2C) – Drivers IOL = 3mA (V )VOL2 Output low voltage (over VCC range) 0.4 V C Driver, receiver combined: Capacitance 10 pF IIL Logical 0 input current, ports 1, 3, 0.3, and 0.4 (PWM disabled) VIN = 0.45V (0 to 70°C) VIN = 0.45V (0 to +85°C) –50 –75 µA µA ITL Logical 1 to 0 transition current, ports 1, 3, 0.3 and 0.411 VIN = 2V (0 to 70°C) VIN = 2V (–40 to +85°C) –650 –750 µA µA ILI Input leakage current, port 0.0, 0.1 and 0.20.45 < VIN < VCC ±10 µA R RST Reset pull-down resistor 25 175 kΩ C IO Pin capacitance Test freq = 1MHz, Tamb = 25°C 10 pF IPD Power-down current5 VCC = 2 to 5.5V VCC = 2 to 6.0V (83C752) 50 µA VPP VPP program voltage (87C752 only) VSS = 0V VCC = 5V±10% Tamb = 21°C to 27°C 12.5 13.0 V IPP Program current (87C752 only) VPP = 13.0V 50 mA

Philips Semiconductors Product specification 83C752/87C75280C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count

1998 May 01 14

DC ELECTRICAL CHARACTERISTICS (Continued) Tamb = 0°C to +70°C or –40°C to +85°C, AVCC = 5V ±5, AVSS = 0V4 VCC = 5V ± 10%, VSS = 0V TEST LIMITS4 SYMBOL PARAMETER CONDITIONS MIN Typical1 MAX UNIT Analog Inputs (A/D guaranteed only with quartz window covered.) AV CC Analog supply voltage10 AV CC = VCC ±0.2V 4.5 5.5 V AICC Analog operating supply current AV CC = 5.12V 39 mA AV IN Analog input voltage12 AV SS –0.2 AV CC +0.2 V C IA Analog input capacitance 15 pF tADS Sampling time 8tCY s tADC Conversion time 40tCY s R Resolution 8 bits ERA Relative accuracy ±1 LSB OS e Zero scale offset ±1 LSB G e Full scale gain error 0.4 % M CTC Channel to channel matching ±1 LSB C t Crosstalk 0–100kHz –60 dB NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10mA (NOTE: This is 85 °C spec.) Maximum IOL per 8-bit port: 26mA Maximum total IOL for all outputs: 67mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 4. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 5. Power-down ICC is measured with all output pins disconnected; port 0 = VCC ; X2, X1 n.c.; RST = VSS . RST = port 0 = VCC . ICC will be slightly higher if a crystal oscillator is used. port 0 = VCC; RST = VSS . 8. Load capacitance for ports = 80pF. 9. The resistor ladder network is not disconnected in the power down or idle modes. Thus, to conserve power, the user may remove AVCC . 10. If the A/D function is not required, or if the A/D function is only needed periodically, AVCC may be removed without affecting the operation of the digital circuitry. Contents of ADCON and ADAT are not guaranteed to be valid. If AVCC is removed, the A/D inputs must be lowered to 11. These parameters do not apply to P1.0–P1.4 if the A/D function is enabled. 12. The input voltage slew rate should be <10V/ms. The maximum slew rate depends on the clock frequency of the microcontroller. Designers should use low pass filters before the A/D inputs as a precaution to noise edges causing false readings.

1998 May 01 15

indicate the name of a signal or the logical status of that signal. Figure 4. External Clock Drive Figure 5. AC Testing Input/Output

1998 May 01 16

Figure 6. ICC vs. FREQ Maximum I CC values taken at VCC = 5.5V and worst case temperature. Typical ICC values taken at VCC = 5.0V and 25°C. Notes 6 and 7 refer to AC Electrical Characteristics. stream is used to place the 87C752 in the programming mode. (PGM/) signal. This pin is used for the 25 programming pulses. driven low which latches the high order bits of the address internally. clock. This clock should be between 1.2 and 6MHz. transmission of the last data bit, the RESET pin should be held low.

1998 May 01 17

A high voltage VPP level is then applied to the VPP input (P0.2). the conclusion of the last pulse, the PGM/ signal should remain high. 87C752 in the verify mode. (Port 1 is now used as an output port). addressed location in the EPROM array will appear on Port 1. P0.2. The various combinations are shown in Table 4. resulting data pattern is then provided to port 1 as the verify data. encrypted with the first byte in the encryption table, and so forth. limit access to the USER EPROM and encryption key arrays.

1. Additional programming of the USER EPROM is inhibited.
2. Additional programming of the encryption key is inhibited.
3. Verification of the encryption key is inhibited.
4. Verification of the USER EPROM and the security bit levels may

logical complement of the USER EPROM contents). levels may still be verified. address or data information to the 87C752 on ports 1 and 3. results of the verify operation will appear on ports 1.6 and 1.7. and a logical zero if not programmed. Table 4. Implementing Program/Verify Modes

• Pulsed from VIH to VIL and returned to VIH.

1998 May 01 18

1. Address should be valid at least 24tCLCL before the rising edge of P0.2 (VPP ).
2. For a pure verify mode, i.e., no program mode in between, tAVQV is 14tCLCL maximum.

Figure 7. Programming Configuration Figure 8. Entry into Program/Verify Modes

1998 May 01 19

25 PULSES

Figure 9. Program/Verify Cycle

Philips Semiconductors Product specification 83C752/87C75280C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count

1998 May 01 20

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3mm SOT341-1

Philips Semiconductors Product specification 83C752/87C75280C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count

1998 May 01 21

DIP28: plastic dual in-line package; 28 leads (600 mil); long body SOT117-2

Philips Semiconductors Product specification 83C752/87C75280C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count

1998 May 01 22

PLCC28: plastic leaded chip carrer; 28 leads; pedestal SOT261-3

Philips Semiconductors Product specification 83C752/87C75280C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count

1998 May 01 23

Philips Semiconductors Product specification 83C752/87C75280C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count

1998 May 01 24

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 05-98 Document order number: 9397 750 03843 /C0109 /C0110 /C0114 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.