S87C751-4DB

87C751 PHILIPS | Alldatasheet

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/C0109 /C0110 /C0114 83C751/87C751 80C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count Product specification Supersedes data of 1998 Jan 19 IC20 Data Handbook

1998 May 01

Philips Semiconductors Product specification 83C751/87C75180C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

21998 May 01 853-0599 19326

DESCRIPTION

The Philips 83C751/87C751 offers the advantages of the 80C51 architecture in a small package and at low cost. The 8XC751 Microcontroller is fabricated with Philips high-density CMOS technology. Philips epitaxial substrate minimizes CMOS latch-up sensitivity. The 8XC751 contains a 2k × 8 ROM (83C751) EPROM (87C751), a 64 × 8 RAM, 19 I/O lines, a 16-bit auto-reload counter/timer, a five-source, fixed-priority level interrupt structure, a bidirectional inter-integrated circuit (I2C) serial bus interface, and an on-chip oscillator. The on-board inter-integrated circuit (I2C) bus interface allows the 8XC751 to operate as a master or slave device on the I2C small area network. This capability facilitates I/O and RAM expansion, access to EEPROM, processor-to-processor communication, and efficient interface to a wide variety of dedicated I 2C peripherals.

FEATURES

• 80C51 based architecture
• Inter-Integrated Circuit (I2C) serial bus interface
• Small package sizes – 24-pin DIP (300 mil “skinny DIP”) – 24-pin Shrink Small Outline Package – 28-pin PLCC
• 87C751 available in one-time programmable plastic packages
• Wide oscillator frequency range
• Low power consumption: – Normal operation: less than 11mA @ 5V, 12MHz – Idle mode – Power-down mode
• 2k × 8 ROM (83C751) 2k × 8 EPROM (87C751)
• 64 × 8 RAM
• 16-bit auto reloadable counter/timer
• Fixed-rate timer
• Boolean processor
• CMOS and TTL compatible
• Well suited for logic replacement, consumer and industrial

applications

• LED drive outputs PIN CONFIGURATIONS 12 13 24P3.4/A4 P3.3/A3 P3.2/A2/A10 P3.1/A1/A9 P3.0/A0/A8 P0.2/V PP P0.1/SDA/OE–PGM RST V SS P0.0/SCL/ASEL P1.0/D0 P1.1/D1 P1.2/D2 P1.3/D3 P1.4/D4 P1.5/INT0 /D5 P1.6/INT1/D6 P1.7/T0/D7 P3.7/A7 P3.6/A6 P3.5/A5 V CC PLASTIC DUAL IN-LINE PACKAGE AND SHRINK SMALL OUTLINE PACKAGE PLASTIC LEADED CHIP CARRIER 41 2 6 12 18 Pin Function 1 P3.4/A4 2 P3.3/A3 3 P3.2/A2/A10 4 P3.1/A1/A9

5 NC*

6 P3.0/A0/A8 7 P0.2/V PP 8 P0.1/SDA/OE-PGM 9 P0.0//SCLASEL SU00315* DO NOT CONNECT PinFunction

10 NC*

11 RST

15 P1.0/D0 16 P1.1/D1 17 P1.2/D2 18 P1.3/D3 Pin Function 19 P1.4/D4 20 P1.5/INT0 /D5

21 NC*

22 NC*

23 P1.6/INT1 /D6 24 P1.7/T0/D7 25 P3.7/A7 26 P3.6/A6 27 P3.5/A5 28 V CC

Philips Semiconductors Product specification 83C751/87C75180C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

1998 May 01 3

ORDERING INFORMATION

ROM EPROM 1 TEMPERATURE RANGE °C AND PACKAGE FREQUENCY DRAWING NUMBER S83C751–1N24 S87C751–1N24 OTP 0 to +70, Plastic Dual In-line Package 3.5 to 12MHz SOT222-1 S83C751–2N24 S87C751–2N24 OTP –40 to +85, Plastic Dual In-line Package 3.5 to 12MHz SOT222-1 S83C751–4N24 S87C751–4N24 OTP 0 to +70, Plastic Dual In-line Package 3.5 to 16MHz SOT222-1 S83C751–5N24 S87C751–5N24 OTP –40 to +85, Plastic Dual In-line Package 3.5 to 16MHz SOT222-1 S83C751–1A28 S87C751–1A28 OTP 0 to +70, Plastic Leaded Chip Carrier 3.5 to 12MHz SOT261-3 S83C751–2A28 S87C751–2A28 OTP –40 to +85, Plastic Leaded Chip Carrier 3.5 to 12MHz SOT261-3 S83C751–4A28 S87C751–4A28 OTP 0 to +70, Plastic Leaded Chip Carrier 3.5 to 16MHz SOT261-3 S83C751–5A28 S87C751–5A28 OTP –40 to +85, Plastic Leaded Chip Carrier 3.5 to 16MHz SOT261-3 S83C751–1DB S87C751–1DB OTP 0 to +70, Shrink Small Outline Package 3.5 to 12MHz SOT340-1 S83C751–4DB S87C751–4DB OTP 0 to +70, Shrink Small Outline Package 3.5 to 16MHz SOT340-1 NOTE: 1. OTP = One Time Programmable EPROM.

Philips Semiconductors Product specification 83C751/87C75180C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

1998 May 01 4

INTERRUPT, SERIAL PORT AND TIMER BLOCKS I2C CONTROL P0.0–P0.2 PORT 0 DRIVERS RAM ADDR REGISTER PORT 0 LATCH STACK POINTER PROGRAM ADDRESS REGISTER PC INCRE- MENTER PROGRAM COUNTER PORT 3 DRIVERS PORT 1 DRIVERS PORT 3 LATCH PORT 1 LATCH TIMING AND CONTROL B REGISTER SU00316

Philips Semiconductors Product specification 83C751/87C75180C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

1998 May 01 5

PIN NO. MNEMONIC DIP/ SSOP LCC TYPE NAME AND FUNCTION VSS 12 14 I Circuit Ground Potential VCC 24 28 I Supply voltage during normal, idle, and power-down operation. P0.0–P0.2 8–6 9–7 I/O Port 0: Port 0 is a 3-bit open-drain, bidirectional port. Port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. Port 0 also serves as the serial I2C interface. When this feature is activated by software, SCL and SDA are driven low in accordance with the I 2C protocol. These pins are driven low if the port register bit is written with a 0 or if the I2C subsystem presents a 0. The state of the pin can always be read from the port register by the program. To comply with the I2C specification, P0.0 and P0.1 are open drain bidirectional I/O pins with the electrical characteristics listed in the tables that follow. While these differ from “standard TTL” characteristics, they are close enough for the pins to still be used as general-purpose I/O in non-I 2C applications. Port 0 also provides alternate functions for programming the EPROM memory as follows: 6 7 N/A VPP (P0.2) – Programming voltage input. (See Note 1.) 7 8 I OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode. OE/PGM = 1 output enabled (verify mode). OE/PGM = 0 program mode. 8 9 I ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3. ASEL = 0 low address byte available on port 3. ASEL = 1 high address byte available on port 3 (only the three least significant bits are used). 7 8 I/O SDA (P0.1) – I2C data. 8 9 I/O SCL (P0.0) – I2C clock. 23, 24 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). Port 1 serves to output the addressed EPROM contents in the verify mode and accepts as inputs the value to program into the selected address during the program mode. Port 1 also serves the special function features of the 80C51 family as listed below: 18 20 I INT0 (P1.5): External interrupt. 19 23 I INT1 (P1.6): External interrupt. 20 24 I T0 (P1.7): Timer 0 external input. P3.0–P3.7 5–1, 23–21 6, 4–1, 27–25 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: I IL). Port 3 also functions as the address input for the EPROM memory location to be programmed (or verified). The 11-bit address is multiplexed into this port as specified by P0.0/ASEL. RST 9 11 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on RESET using only an external capacitor to VCC . After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places the device in the programming state allowing programming address, data and VPP to be applied for programming or verification purposes. The RESET serial sequence must be synchronized with the X1 input. X1 11 13 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the programming state. X2 10 12 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: 1. When P0.2 is at or close to 0V it may affect the internal ROM operation. We recommend that P0.2 be tied to VCC via a small pullup (e.g., 2kΩ ).

Philips Semiconductors Product specification 83C751/87C75180C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

1998 May 01 6

ABSOLUTE MAXIMUM RATINGS 1, 2 PARAMETER RATING UNIT Storage temperature range –65 to +150 °C Voltage from VCC to VSS –0.5 to +6.5 V Voltage from any pin to VSS (except VPP ) –0.5 to VCC + 0.5 V Power dissipation 1.0 W Voltage on VPP pin to VSS 0 to +13.0 V Maximum IOL per I/O pin 10 mA NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10% for 87C751, VCC = 5V ±10% for 83C751, VSS = 0V1 SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT VIL Input low voltage, except SDA, SCL –0.5 0.2VDD –0.1 V VIH Input high voltage, except X1, RST 0.2VCC +0.9 VCC +0.5 V VIH1 Input high voltage, X1, RST 0.7VCC VCC +0.5 V SDA, SCL, P0.2 VIL1 Input low voltage –0.5 0.3VCC V VIH2 Input high voltage 0.7VCC VCC +0.5 V VOL Output low voltage, ports 1 and 3 IOL = 1.6mA2 0.45 V VOL1 Output low voltage, port 0.2 IOL = 3.2mA2 0.45 V VOH Output high voltage, ports 1 and 3 IOH = –60µA 2.4 V IOH = –25µA 0.75VCC V IOH = –10µA 0.9VCC V Port 0.0 and 0.1 (I2C) – Drivers VOL2 Output low voltage IOL = 3mA 0.4 V Driver, receiver combined: (over VCC range) C Capacitance 10 pF IIL Logical 0 input current, ports 1 and 3 VIN = 0.45V –50 µA ITL Logical 1 to 0 transition current, ports 1 and 33 VIN = 2V (0 to 70°C) VIN = 2V (–40 to +85°C) –650 –750 µA µA ILI Input leakage current, port 0 0.45 < VIN < VCC ±10 µA R RST Internal pull-down resistor 25 175 kΩ C IO Pin capacitance Test freq = 1MHz, Tamb = 25°C 10 pF IPD Power-down current4 VCC = 2 to VCC max 50 µA VPP VPP program voltage (for 87C751 only) VSS = 0V VCC = 5V±10% Tamb = 21°C to 27°C 12.5 13.0 V IPP Program current (for 87C751 only) VPP = 13.0V 50 mA ICC Supply current (see Figure 2) NOTES TO DC ELECTRICAL CHARACTERISTICS ON NEXT PAGE.

Philips Semiconductors Product specification 83C751/87C75180C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

1998 May 01 7

NOTES TO DC ELECTRICAL CHARACTERISTICS: 1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 2. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10mA (NOTE: This is 85 °C spec.) Maximum IOL per 8-bit port: 26mA Maximum total IOL for all outputs: 67mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 3. Pins of ports 1 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 4. Power-down ICC is measured with all output pins disconnected; port 0 = VCC ; X2, X1 n.c.; RST = VSS . RST = port 0 = VCC . ICC will be slightly higher if a crystal oscillator is used. port 0 = VCC ; RST = VSS . AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10% for 87C751, VCC = 5V ±10% for 83C751, VSS = 0V1, 2 12MHz CLOCK VARIABLE CLOCK SYMBOL PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL Oscillator frequency: 3.5 12 MHz 3.5 16 MHz External Clock (Figure 1) tCHCX High time 20 20 ns tCLCX Low time 20 20 ns tCLCH Rise time 20 20 ns tCHCL Fall time 20 20 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 2. Load capacitance for ports = 80pF.

1998 May 01 8

Figure 1. External Clock Drive Figure 2. ICC vs. FREQ Maximum I CC values taken at VCC max and worst case temperature. Typical ICC values taken at VCC = 5.0V and 25°C. Notes 5 and 6 refer to DC Electrical Characteristics.

1998 May 01 9

amplifier which can be configured for use as an on-chip oscillator. machine cycles (24 oscillator periods), while the oscillator is running. CC and RST must come up at the same time for a proper start-up. the same manner as a power-on reset. instruction to invoke power-down is the last instruction executed. Table 1. External Pin Status During Idle and RAM overlapped with the 128-byte special function register area. pre-incremented on a PUSH instruction). Figure 3. Memory Map counter are centralized in a single register called TCON. A watchdog timer, called Timer I, is for use with the I2C subsystem. locations, and reset values.

1998 May 01 10

is no need for the IP SFR, so it is not used. control, I2C data, I2C status, and I2C configuration. have been added (I2STA and I2CFG). bits of P0 SFR have a useful function. independent 8-bit registers. Table 2. I2C Special Function Register Addresses

1998 May 01 11

Table 3. 8XC751 Special Function Registers # SFRs are modified from or added to the 80C51 SFRs.

1998 May 01 12

80C51 but does not include address/data input and output circuitry. bidirectional with no internal pullups. interrupt is enabled, will generate an interrupt. 0 – Timer/counter is enabled when TR is 1. C/T 1 – Counter/timer operation from T0 pin. 0 – Timer operation from internal clock. TF 1 – Set on overflow of TH. TR 1 – Timer/counter enabled. IE0 1 – Edge detected in INT0 . IT0 1 – INT0 is edge triggered. 0 – INT0 is level sensitive. IE1 1 – Edge detected on INT1 . IT1 1 – INT1 is edge triggered. 0 – INT1 is level sensitive. flags are therefore combined into one register. transmission to be repeated. when used as a fixed-rate timer. Figure 4. 83C751 Counter/Timer Block Diagram

Philips Semiconductors Product specification 83C751/87C75180C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

1998 May 01 13

The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. The main features of the bus are:

• Bidirectional data transfer between masters and slaves
• Serial addressing of slaves (no added wiring)
• Acknowledgment after each transferred byte
• Multimaster bus
• Arbitration between simultaneously transmitting masters without corruption of serial data on bus
• The 82B715 extends communication distance to 100 feet (30M). A large family of I2C compatible ICs is available. See the I2C section of this manual for more details on the bus and available ICs. The 83C751 I2C subsystem includes hardware to simplify the software required to drive the I2C bus. The hardware is a single bit interface which in addition to including the necessary arbitration and framing error checks, includes clock stretching and a bus timeout timer. The interface is synchronized to software either through polled loops or interrupts. Refer to the application note AN422, in Section 4, entitled “Using the 8XC751 Microcontroller as an I 2C Bus Master” for additional discussion of the 83C751 I2C interface and sample driver routines. Six time spans are important in I2C operation and are insured by timer I:
• The MINIMUM HIGH time for SCL when this device is the master.
• The MINIMUM LOW time for SCL when this device is a master. This is not very important for a single-bit hardware interface like this one, because the SCL low time is stretched until the software responds to the I2C flags. The software response time normally meets or exceeds the MIN LO time. In cases where the software responds within MIN HI + MIN LO) time, timer I will ensure that the minimum time is met.
• The MINIMUM SCL HIGH TO SDA HIGH time in a stop condition.
• The MINIMUM SDA HIGH TO SDA LOW time between I2C stop and start conditions (4.7µs, see spec.).
• The MINIMUM SDA LOW TO SCL LOW time in a start condition.
• The MAXIMUM SCL CHANGE time while an I2C frame is in progress. A frame is in progress between a start condition and the following stop condition. This time span serves to detect a lack of software response on this 8XC751 as well as external I2C problems. SCL “stuck low” indicates a faulty master or slave. SCL “stuck high” may mean a faulty device, or that noise induced onto the I 2C bus caused all masters to withdraw from I2C arbitration. The first five of these times are 4.7µs (see I2C specification) and are covered by the low order three bits of timer I. Timer I is clocked by the 8XC751 oscillator, which can vary in frequency from 0.5 to 16MHz. Timer I can be preloaded with one of four values to optimize timing for different oscillator frequencies. At lower frequencies, software response time is increased and will degrade maximum performance of the I 2C bus. See special function register I2CFG description for prescale values (CT0, CT1). The MAXIMUM SCL CHANGE time is important, but its exact span is not critical. The complete 10 bits of timer I are used to count out the maximum time. When I 2C operation is enabled, this counter is cleared by transitions on the SCL pin. The timer does not run between I2C frames (i.e., whenever reset or stop occurred more recently than the last start). When this counter is running, it will carry out after 1020 to 1023 machine cycles have elapsed since a change on SCL. A carry out causes a hardware reset of the 83C751 I interface and generates an interrupt if the timer I interrupt is enabled. In cases where the bus hangup is due to a lack of software response by this 83C751, the reset releases SCL and allows I operation among other devices to continue. I2C Interrupts If I2C interrupts are enabled (EA and EI2 are both set to 1), an I2C interrupt will occur whenever the ATN flag is set by a start, stop, arbitration loss, or data ready condition (refer to the description of ATN following). In practice, it is not efficient to operate the I interface in this fashion because the I2C interrupt service routine would somehow have to distinguish between hundreds of possible conditions. Also, since I 2C can operate at a fairly high rate, the software may execute faster if the code simply waits for the I2C interface. Typically, the I2C interrupt should only be used to indicate a start condition at an idle slave device, or a stop condition at an idle master device (if it is waiting to use the I2C bus). This is accomplished by enabling the I2C interrupt only during the aforementioned conditions. I2C Register I2CON 765432 1 0 Read RDAT ATN DRDY ARL STR STP MASTER – Write CXA IDLE CDR CARL CSTR CSTP XSTR XSTP Reading I2CON RDAT The data from SDA is captured into “Receive DATa” whenever a rising edge occurs on SCL. RDAT is also available (with seven low-order zeros) in the I2DAT register. The difference between reading it here and there is that reading I2DAT clears DRDY, allowing the I 2C to proceed on to another bit. Typically, the first seven bits of a received byte are read from I2DAT, while the 8th is read here. Then I2DAT can be written to send the Ack bit and clear DRDY. ATN “ATteNtion” is 1 when one or more of DRDY, ARL, STR, or STP is 1. Thus, ATN comprises a single bit that can be tested to release the I 2C service routine from a “wait loop.” DRDY “Data ReaDY” (and thus ATN) is set when a rising edge occurs on SCL, except at idle slave. DRDY is cleared by writing CDR = 1, or by writing or reading the I2DAT register. The following low period on SCL is stretched until the program responds by clearing DRDY.

Philips Semiconductors Product specification 83C751/87C75180C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

1998 May 01 14

When a program detects ATN = 1, it should next check DRDY. If DRDY = 1, then if it receives the last bit, it should capture the data from RDAT (in I2DAT or I2CON). Next, if the next bit is to be sent, it should be written to I2DAT. One way or another, it should clear DRDY and then return to monitoring ATN. Note that if any of ARL, STR, or STP is set, clearing DRDY will not release SCL to high, so that the I 2C will not go on to the next bit. If a program detects ATN = 1, and DRDY = 0, it should go on to examine ARL, STR, and STP. ARL “Arbitration Loss” is 1 when transmit Active was set, but this 83C751 lost arbitration to another transmitter. Transmit Active is cleared when ARL is 1. There are four separate cases in which ARL is set. 1. If the program sent a 1 or repeated start, but another device sent a 0, or a stop, so that SDA is 0 at the rising edge of SCL. (If the other device sent a stop, the setting of ARL will be followed shortly by STP being set.) 2. If the program sent a 1, but another device sent a repeated start, and it drove SDA low before the 83C751 could drive SCL low. (This type of ARL is always accompanied by STR = 1.) 3. In master mode, if the program sent a repeated start, but another device sent a 1, and it drove SCL low before this 83C751 could drive SDA low. 4. In master mode, if the program sent stop, but it could not be sent because another device sent a 0. STR “STaRt” is set to a 1 when an I 2C start condition is detected at a non-idle slave or at a master. (STR is not set when an idle slave becomes active due to a start bit; the slave has nothing useful to do until the rising edge of SCL sets DRDY.) STP “SToP” is set to 1 when an I 2C stop condition is detected at a non-idle slave or at a master. (STP is not set for a stop condition at an idle slave.) MASTER “MASTER” is 1 if this 83C751 is currently a master on the I2C. MASTER is set when MASTRQ is 1 and the bus is not busy (i.e., if a start bit hasn’t been received since reset or a “Timer I” time-out, or if a stop has been received since the last start). MASTER is cleared when ARL is set, or after the software writes MASTRQ = 0 and then XSTP = 1. Writing I2CON Typically, for each bit in an I 2C message, a service routine waits for ATN = 1. Based on DRDY, ARL, STR, and STP, and on the current bit position in the message, it may then write I2CON with one or more of the following bits, or it may read or write the I2DAT register. CXA Writing a 1 to “Clear Xmit Active” clears the Transmit Active state. (Reading the I2DAT register also does this.) Regarding Transmit Active Transmit Active is set by writing the I2DAT register, or by writing I2CON with XSTR = 1 or XSTP = 1. The I 2C interface will only drive the SDA line low when Transmit Active is set, and the ARL bit will only be set to 1 when Transmit Active is set. Transmit Active is cleared by reading the I2DAT register, or by writing I2CON with CXA = 1. Transmit Active is automatically cleared when ARL is 1. IDLE Writing 1 to “IDLE” causes a slave’s I 2C hardware to ignore the I2C until the next start condition (but if MASTRQ is 1, then a stop condition will make the 83C751 into a master). CDR Writing a 1 to “Clear Data Ready” clears DRDY. (Reading or writing the I2DAT register also does this.) CARL Writing a 1 to “Clear Arbitration Loss” clears the ARL bit. CSTR Writing a 1 to “Clear STaRt” clears the STR bit. CSTP Writing a 1 to “Clear SToP” clears the STP bit. Note that if one or more of DRDY, ARL, STR, or STP is 1, the low time of SCL is stretched until the service routine responds by clearing them. XSTR Writing 1s to “Xmit repeated STaRt” and CDR tells the I hardware to send a repeated start condition. This should only be at a master. Note that XSTR need not and should not be used to send an “initial” (nonrepeated) start; it is sent automatically by the I 2C hardware. Writing XSTR = 1 includes the effect of writing I2DAT with XDAT = 1; it sets Transmit Active and releases SDA to high during the SCL low time. After SCL goes high, the I 2C hardware waits for the suitable minimum time and then drives SDA low to make the start condition. XSTP Writing 1s to “Xmit SToP” and CDR tells the I2C hardware to send a stop condition. This should only be done at a master. If there are no more messages to initiate, the service routine should clear the MASTRQ bit in I2CFG to 0 before writing XSTP with 1. Writing XSTP = 1 includes the effect of writing I2DAT with XDAT = 0; it sets Transmit Active and drives SDA low during the SCL low time. After SCL goes high, the I 2C hardware waits for the suitable minimum time and then releases SDA to high to make the stop condition. NOTE: Because of the manner in which register bit addressing is implemented in the 80C51 family, the I2CON register should never be altered by use of the SETB, CLR, CPL, MOV (bit), or JBC instructions. This is due to the fact that read and write functions of this register are different. Testing of I2CON bits via the JB and JNB instructions is supported.

Philips Semiconductors Product specification 83C751/87C75180C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

1998 May 01 15

RDAT “Receive DATa” is captured from SDA every rising edge of SCL. Reading I2DAT also clears DRDY and the Transmit Active state. XDAT “Xmit Data” sets the data for the next bit. Writing I2DAT also clears DRDY and sets the Transmit Active state. Regarding Software Response Time Because the 83C751 can run at 16MHz, and because the I interface is optimized for high-speed operation, it is quite likely that an I2C service routine will sometimes respond to DRDY (which is set at a rising edge of SCL) and write I2DAT before SCL has gone low again. If XDAT were applied directly to SDA, this situation would produce an I 2C protocol violation. The programmer need not worry about this possibility because XDAT is applied to SDA only when SCL is low. Conversely, a program that includes an I 2C service routine may take a long time to respond to DRDY. Typically, an I2C routine operates on a flag-polling basis during a message, with interrupts from other peripheral functions enabled. If an interrupt occurs, it will delay the response of the I 2C service routine. The programmer need not worry about this very much either, because the I2C hardware stretches the SCL low time until the service routine responds. The only constraint on the response is that it must not exceed the Timer I time-out, which is at least 765 microseconds. I 2C Register I2CFG 7 6 5 4 3210 Read SLAVEN MASTRQ 0 TIRUN – – CT1 CT0 Write SLAVEN MASTRQ CLRTI TIRUN – – CT1 CT0 SLAVEN Writing a 1 to “SLAVe ENable” enables the slave functions of the I2C subsystem. If SLAVEN and MASTRQ are 0, the I2C hardware is disabled. This bit is cleared to 0 by reset and by an I2C time-out. MASTRQ Writing a 1 to “MASTRQ” requests mastership of the I2C. If a frame from another master is in progress when this bit is changed from 0 to 1, action is delayed until a stop condition is detected. Then, or immediately if a frame is not in progress, a start condition is sent and DRDY is set (thus making ATN 1 and generating an I 2C interrupt). When a master wishes to release mastership status of the I2C, it writes a 1 to XSTP in I2CON. MASTRQ is cleared by reset and by an I2C time-out. CLRTI Writing a 1 to this bit clears the Timer I interrupt flag. This bit position always reads as a 0. TIRUN Writing a 1 to this bit lets Timer I run; a zero stops and clears it. Together with SLAVEN, MASTRQ, and MASTER, this bit determines operational modes as shown in Table 4. CT1,0 These two bits are programmed as a function of the OSC rate, to optimize the MIN HI and LO time of SCL when this 83C751 is a master on the I 2C. The time value determined by these bits controls both of these parameters, and also the timing for stop and start conditions. These bits are cleared to 00 by reset. Values to be used in the CT1 and CT0 bits are shown in Table 5. To allow the I2C bus to run at the maximum rate for a particular oscillator frequency, compare the actual oscillator rate to the fOSC max column in the table. The value for CT1 and CT0 is found in the first line of the table where fOSC max is greater than or equal to the actual frequency. The table also shows the osc/12 count for various settings of CT1/CT0. This allows calculation of the actual minimum high and low times for SCL as follows: SCL min high/low time (in microseconds) = 12 * count / osc (in MHz) For instance, at a 16MHz frequency, with CT1/CT0 set to 10, the minimum SCL high and low times will be 5.25µs. The table also shows the Timer I timeout period (given in machine cycles) for each CT1/CT0 combination. The timeout period varies because of the way in which minimum SCL high and low times are measured. When the I 2C interface is operating, Timer I is preloaded at every SCL transition with a value dependent upon CT1/CT0. The preload value is chosen such that a minimum SCL high or low time has elapsed when Timer I reaches a count of 008 (the actual value preloaded into Timer I is 8 minus the osc/12 count).

1998 May 01 16

Table 4. Interaction of TIRUN with SLAVEN, MASTRQ, and MASTER application wants to ignore the I2C at certain times, it should write SLAVEN, MASTRQ, and TIRUN all to zero. not, so that there is no checking for I2C being “hung.” This configuration can be used for very slow I2C operation. Start and Stop conditions. This is the normal state for I2C operation. Table 5. CT1, CT0 Values named bits in the I2CON register. XDATA The content of the transmitter buffer. The interrupt structure is a five-source, one-level interrupt system. (EI2) and Timer I interrupt (ETI) are the other two interrupt sources. are based on the 80C51 interrupt architecture. EX1 IE.2 Enables or disables external interrupt 1. If EX1 = 0, external interrupt 1 is disabled. EX0 IE.0 Enables or disables external interrupt 0. If EX0 = 0, external interrupt 0 is disabled.

Philips Semiconductors Product specification 83C751/87C75180C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

1998 May 01 17

87C751 PROGRAMMING CONSIDERATIONS EPROM Characteristics The 87C751 is programmed by using a modified Quick-Pulse Programming algorithm similar to that used for devices such as the 87C451 and 87C51. It differs from these devices in that a serial data stream is used to place the 87C751 in the programming mode. Figure 5 shows a block diagram of the programming configuration for the 87C751. Port pin P0.2 is used as the programming voltage supply input (V PP signal). Port pin P0.1 is used as the program (PGM/) signal. This pin is used for the 25 programming pulses. Port 3 is used as the address input for the byte to be programmed and accepts both the high and low components of the eleven bit address. Multiplexing of these address components is performed using the ASEL input. The user should drive the ASEL input high and then drive port 3 with the high order bits of the address. ASEL should remain high for at least 13 clock cycles. ASEL may then be driven low which latches the high order bits of the address internally. the high address should remain on port 3 for at least two clock cycles after ASEL is driven low. Port 3 may then be driven with the low byte of the address. The low address will be internally stable 13 clock cycles later. The address will remain stable provided that the low byte placed on port 3 is held stable and ASEL is kept low. Note: ASEL needs to be pulsed high only to change the high byte of the address. Port 1 is used as a bidirectional data bus during programming and verify operations. During programming mode, it accepts the byte to be programmed. During verify mode, it provides the contents of the EPROM location specified by the address which has been supplied to Port 3. The XTAL1 pin is the oscillator input and receives the master system clock. This clock should be between 1.2 and 6MHz. The RESET pin is used to accept the serial data stream that places the 87C751 into various programming modes. This pattern consists of a 10-bit code with the LSB sent first. Each bit is synchronized to the clock input, X1. Programming Operation Figures 6 and 7 show the timing diagrams for the program/verify cycle. RESET should initially be held high for at least two machine cycles. P0.1 (PGM/) and P0.2 (VPP ) will be at VOH as a result of the RESET operation. At this point, these pins function as normal quasi-bidirectional I/O ports and the programming equipment may pull these lines low. However, prior to sending the 10-bit code on the RESET pin, the programming equipment should drive these pins high (V IH). The RESET pin may now be used as the serial data input for the data stream which places the 87C751 in the programming mode. Data bits are sampled during the clock high time and thus should only change during the time that the clock is low. Following transmission of the last data bit, the RESET pin should be held low. Next the address information for the location to be programmed is placed on port 3 and ASEL is used to perform the address multiplexing, as previously described. At this time, port 1 functions as an output. A high voltage V PP level is then applied to the VPP input (P0.2). (This sets Port 1 as an input port). The data to be programmed into the EPROM array is then placed on Port 1. This is followed by a series of programming pulses applied to the PGM/ pin (P0.1). These pulses are created by driving P0.1 low and then high. This pulse is repeated until a total of 25 programming pulses have occurred. At the conclusion of the last pulse, the PGM/ signal should remain high. The V PP signal may now be driven to the VOH level, placing the 87C751 in the verify mode. (Port 1 is now used as an output port). After four machine cycles (48 clock periods), the contents of the addressed location in the EPROM array will appear on Port 1. The next programming cycle may now be initiated by placing the address information at the inputs of the multiplexed buffers, driving the V PP pin to the VPP voltage level, providing the byte to be programmed to Port1 and issuing the 26 programming pulses on the PGM/ pin, bringing V PP back down to the VC level and verifying the byte. Programming Modes The 87C751 has four programming features incorporated within its EPROM array. These include the USER EPROM for storage of the application’s code, a 16-byte encryption key array and two security bits. Programming and verification of these four elements are selected by a combination of the serial data stream applied to the RESET pin and the voltage levels applied to port pins P0.1 and P0.2. The various combinations are shown in Table 6. Encryption Key Table The 87C751 includes a 16-byte EPROM array that is programmable by the end user. The contents of this array can then be used to encrypt the program memory contents during a program memory verify operation. When a program memory verify operation is performed, the contents of the program memory location is XNOR’ed with one of the bytes in the 16-byte encryption table. The resulting data pattern is then provided to port 1 as the verify data. The encryption mechanism can be disable, in essence, by leaving the bytes in the encryption table in their erased state (FFH) since the XNOR product of a bit with a logical one will result in the original bit. The encryption bytes are mapped with the code memory in 16-byte groups. the first byte in code memory will be encrypted with the first byte in the encryption table; the second byte in code memory will be encrypted with the second byte in the encryption table and so forth up to and including the 16the byte. The encryption repeats in 16-byte groups; the 17th byte in the code memory will be encrypted with the first byte in the encryption table, and so forth. Security Bits Two security bits, security bit 1 and security bit 2, are provided to limit access to the USER EPROM and encryption key arrays. Security bit 1 is the program inhibit bit, and once programmed performs the following functions: 1. Additional programming of the USER EPROM is inhibited. 2. Additional programming of the encryption key is inhibited. 3. Verification of the encryption key is inhibited. 4. Verification of the USER EPROM and the security bit levels may still be performed. (If the encryption key array is being used, this security bit should be programmed by the user to prevent unauthorized parties from reprogramming the encryption key to all logical zero bits. Such programming would provide data during a verify cycle that is the logical complement of the USER EPROM contents). Security bit 2, the verify inhibit bit, prevents verification of both the USER EPROM array and the encryption key arrays. The security bit levels may still be verified.

1998 May 01 18

address or data information to the 87C751 on ports 1 and 3. results of the verify operation will appear on ports 1.6 and 1.7. and a logical zero if not programmed. light with wavelengths shorter than approximately 4,000 angstroms. Erasure leaves the array in an all 1s state. Table 6. Implementing Program/Verify Modes

• Pulsed from VIH to VIL and returned to VIH.

Figure 5. Programming Configuration Figure 6. Entry into Program/Verify Modes

1998 May 01 19

1. Address should be valid at least 24tCLCL before the rising edge of P0.2 (VPP ).
2. For a pure verify mode, i.e., no program mode in between, tAVQV is 14tCLCL maximum.

25 PULSES

Figure 7. Program/Verify Cycle

Philips Semiconductors Product specification 83C751/87C75180C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

1998 May 01 20

DIP24: plastic dual in-line package; 24 leads (300 mil) SOT222-1

Philips Semiconductors Product specification 83C751/87C75180C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

1998 May 01 21

PLCC28: plastic leaded chip carrer; 28 leads; pedestal SOT261-3

Philips Semiconductors Product specification 83C751/87C75180C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

1998 May 01 22

SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1

Philips Semiconductors Product specification 83C751/87C75180C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

1998 May 01 23

Philips Semiconductors Product specification 83C751/87C75180C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count

1998 May 01 24

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 05-98 Document order number: 9397 750 03845 /C0109 /C0110 /C0114 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.