80C851 PHILIPS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 22
Technical content
/C0109 /C0110 /C0114 80C851/83C851 CMOS single-chip 8-bit microcontroller with on-chip EEPROM Product specification Supersedes data of 1992 Nov 25 IC20 Data Handbook
1998 Jul 03
Philips Semiconductors Product specification 80C851/83C851CMOS single-chip 8-bit microcontroller with on-chip EEPROM
21998 Jul 03
DESCRIPTION
The Philips 80C851/83C851 is a high-performance microcontroller fabricated with Philips high-density CMOS technology. The 80C851/83C851 has the same instruction set as the 80C51. The Philips CMOS technology combines the high speed and density characteristics of HMOS with the low power attributes of CMOS. The Philips epitaxial substrate minimizes latch-up sensitivity. The 80C851/83C851 contains a 4k × 8 ROM with mask-programmable ROM code protection, a 128 × 8 RAM, 256 × 8 EEPROM, 32 I/O lines, two 16-bit counter/timers, a seven-source, five vector, two-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits. In addition, the 80C851/83C851 has two software selectable modes of power reduction — idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM and EEPROM contents but freezes the oscillator, causing all other chip functions to be inoperative.
FEATURES
- 80C51 based architecture – 4k × 8 ROM – 128 × 8 RAM – Two 16-bit counter/timers – Full duplex serial channel – Boolean processor
- Non-volatile 256 × 8-bit EEPROM (electrically erasable programmable read only memory) – On-chip voltage multiplier for erase/write – 10,000 erase/write cycles per byte – 10 years non-volatile data retention – Infinite number of read cycles – User selectable security mode – Block erase capability
- Mask-programmable ROM code protection
- Memory addressing capability – 64k ROM and 64k RAM
- Power control modes: – Idle mode – Power-down mode
- CMOS and TTL compatible
- 1.2 to 16MHz or 3.5 to 24MHz
- Three package styles
- Three temperature ranges
- ROM code protection
ORDERING INFORMATION
°ROMless Version ROM Version ROMless Version ROM Version TEMPERATURE RANGE °C AND PACKAGE FREQ. (MHz) DRAWING NUMBER P80C851 FBP P83C851 FBP S80C851-4N40 S83C851-4N40 0 to +70, Plastic Dual In-line Package1.2 to 16 SOT129-1 P80C851 IBP P83C851 IBP 0 to +70, Plastic Dual In-line Package3.5 to 24 SOT129-1 P80C851 FBA P83C851 FBA S80C851-4A44 S83C851-4A44 0 to +70, Plastic Leaded Chip Carrier1.2 to 16 SOT187-1 P80C851 IBA P83C851 IBA 0 to +70, Plastic Leaded Chip Carrier3.5 to 24 SOT187-1 P80C851 FBB P83C851 FBB S80C851-4B44 S83C851-4B44 0 to +70, Plastic Quad Flat Pack1.2 to 16 SOT307-2 P80C851 IBB P83C851 IBB 0 to +70, Plastic Quad Flat Pack3.5 to 24 SOT307-2 P80C851 FFP P83C851 FFP S80C851-5N40 S83C851-5N40 –40 to +85, Plastic Dual In-line Package1.2 to 16 SOT129-1 P80C851 FFA P83C851 FFA S80C851-5A44 S83C851-5A44 –40 to +85, Plastic Leaded Chip Carrier1.2 to 16 SOT187-1 P80C851 FFB P83C851 FFB S80C851-5B44 S83C851-5B44 –40 to +85, Plastic Quad Flat Pack1.2 to 16 SOT307-2 P80C851 FHP P83C851 FHP S80C851-6N40 S83C851-6N40 –40 to +125, Plastic Dual In-line Package1.2 to 16 SOT129-1 P80C851 FHA P83C851 FHA S80C851-6A44 S83C851-6A44 –40 to +125, Plastic Leaded Chip Carrier1.2 to 16 SOT187-1 P80C851 FHB P83C851 FHB S80C851-6B44 S83C851-6B44 –40 to +125, Plastic Quad Flat Pack1.2 to 16 SOT307-2
Philips Semiconductors Product specification 80C851/83C851CMOS single-chip 8-bit microcontroller with on-chip EEPROM
1998 Jul 03 3
(4K x 8 ROM) DATA MEMORY (128 x 8 RAM) TWO 16-BIT TIMER/EVENT COUNTERS T0 T1 COUNTERS XTAL2 XTAL1 FREQUENCY REFERENCE INTERNAL INTERRUPTS INT0 INT1 EXTERNAL INTERRUPTS CONTROL PARALLEL PORTS, ADDRESS/DATA BUS AND I/O PINS SERIAL IN SERIAL OUT SHARED WITH PORT 3 EEPROM (256 x 8) LOGIC SYMBOL PORT 0PORT 1PORT 2 PORT 3 ADDRESS AND DATA BUS ADDRESS BUS SECONDARY FUNCTIONS RxD TxD INT0 INT1 WR RD RST EA PSEN ALE VSS XTAL1 XTAL2 VDD
Philips Semiconductors Product specification 80C851/83C851CMOS single-chip 8-bit microcontroller with on-chip EEPROM
1998 Jul 03 4
40P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 RST RxD/P3.0 TxD/P3.1 INT0 /P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 P1.7 WR /P3.6 RD /P3.7 XTAL2 XTAL1 V SS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 V DD DUAL IN-LINE PACKAGE PLASTIC LEADED CHIP CARRIER 614 0 18 28 PLASTIC QUAD FLAT PACK 44 34 12 22 PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS PLCC 614 0 18 28 Pin Function Pin Function
1 NC* 23 NC*
2 P1.0 24 P2.0/A8 3 P1.1 25 P2.1/A9 4 P1.2 26 P2.2/A10 5 P1.3 27 P2.3/A11 6 P1.4 28 P2.4/A12 7 P1.5 29 P2.5/A13 8 P1.6 30 P2.6/A14 9 P1.7 31 P2.7/A15
10 RST 32 PSEN
11 P3.0/RxD 33 ALE
12 NC* 34 NC*
13 P3.1/TxD 35 EA 14 P3.2/INT0 36 P0.7/AD7 15 P3.3/INT1 37 P0.6/AD6 16 P3.4/T0 38 P0.5/AD5 17 P3.5/T1 39 P0.4/AD4 18 P3.6/WR 40 P0.3/AD3 19 P3.7/RD 41 P0.2/AD2 20 XTAL2 42 P0.1/AD1 21 XTAL1 43 P0.0/AD0
22 VSS 44 V DD
- NO INTERNAL CONNECTION PLASTIC QUAD FLAT PACK PIN FUNCTIONS PQFP 44 34 12 22 Pin Function Pin Function 1 P1.5 23 P2.5/A13 2 P1.6 24 P2.6/A14 3 P1.7 25 P2.7/A15
4 RST 26 PSEN
5 P3.0/RxD 27 ALE
6 NC* 28 NC*
7 P3.1/TxD 29 EA 8 P3.2/INT0 30 P0.7/AD7 9 P3.3/INT1 31 P0.6/AD6 10 P3.4/T0 32 P0.5/AD5 11 P3.5/T1 33 P0.4/AD4 12 P3.6/WR 34 P0.3/AD3 13 P3.7RD 35 P0.2/AD2 14 XTAL2 36 P0.1/AD1 15 XTAL1 37 P0.0/AD0
16 VSS 38 V DD
17 NC* 39 V SS
18 P2.0/A8 40 P1.0 19 P2.1/A9 41 P1.1 20 P2.2/A10 42 P1.2 21 P2.3/A11 43 P1.3 22 P2.4/A12 44 P1.4 * NO INTERNAL CONNECTION
Philips Semiconductors Product specification 80C851/83C851CMOS single-chip 8-bit microcontroller with on-chip EEPROM
1998 Jul 03 5
PIN NO. MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION VSS 20 22 16, 39 I Ground: 0V reference. VDD 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0–0.7 39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. 1–3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. 13–19 7–13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: I IL). Port 3 also serves the special features of the SC80C51 family, as listed below: 10 11 5 I RxD (P3.0): Serial input port 11 13 7 O TxD (P3.1): Serial output port 12 14 8 I INT0 (P3.2): External interrupt 13 15 9 I INT1 (P3.3): External interrupt 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VDD . ALE 30 33 27 I/O Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA 31 35 29 I External Access Enable: If during a RESET, EA is held at TTL, level HIGH, the CPU executes out of the internal program memory ROM provided the Program Counter is less than 4096. If during a RESET, EA is held a TTL LOW level, the CPU executes out of external program memory. EA is not allowed to float. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier.
1998 Jul 03 6
Table 1. 8XC851 Special Function Registers # SFRs are modified from or added to the 80C51 SFRs.
Philips Semiconductors Product specification 80C851/83C851CMOS single-chip 8-bit microcontroller with on-chip EEPROM
1998 Jul 03 7
Communications between the CPU and the EEPROM is accomplished via 5 special function registers; 2 address registers (high and low byte), 1 data register for read and write operations, 1 control register, and 1 timer register to adapt the erase/write time to the clock frequency. All registers can be read and written. Figure 1 shows a block diagram of the CPU, the EEPROM and the interface. Register and Functional Address Register (EADRH, EADRL) The lower byte contains the address of one of the 256 bytes. The higher byte (EADRH) is for future extensions and for addressing the security bits (see Security Facilities). The EADRH register address is F3H. The EADRL register address is F2H. Data Register (EDAT) This register is required for read and write operations and also for row/block erase. In write mode, its contents are written to the addressed byte (for “row erase” and “block erase” the contents are don’t care). The write pulse starts all operations, except read. In read mode, EDAT contains the data of the addressed byte. The EDAT register address is F4H. Timer Register (ETIM) The timer register is required to adapt the erase/write time to the oscillator frequency. The user has to ensure that the erase or write (program) time is neither too short or too long. The ETIM register address is F5H. Table 2 contains the values which must be written to the ETIM register by software for various oscillator frequencies (the default value is 08H after RESET). The general formula is: 2ms Write time: f XTAL1 [kHz] 512 2Value (decimal, to be rounded up) 10ms Write time: fXTAL1 [kHz] 96 2Value (decimal) Control Register (ECNTRL) See Figure 2 for a description of this register. The ECNTRL register address is F6H. Table 2. Values for the Timer Register (ETIM) Figure 1. EEPROM Interface Block Diagram
1998 Jul 03 8
serial port interrupt (see Interrupt section). ECNTRL.6 EEINT EEPROM interrupt enable: set and reset by software (active high). ECNTRL.5 EWP Erase/write in progress flag: set and reset by the sequencer (active high). written to one byte at a time. addressed byte are available in the data register. whether an erase/write or write cycle only (data = 00H) is required. takes tTOTOAL = tE + 8 × tW compared to tTOTAL = 8 × tE + 8 × tW (tE = tERASE ⋅ tW = tWRITE ). Page write: For future products. Page erase/write: For future products. Block erase: In this mode all 256 bytes are cleared. The byte containing the security bits is also cleared. BLOCKERASE = tE. The contents of EADRH, EADRL and EDAT are insignificant. Figure 2. Control Register (ECNTRL)
1998 Jul 03 9
illustrates the access to SB. while executing external program memory. mask-programmable ROM security bit is set. test-mode is implemented for test purposes. This mode allows every bit to be tested. Figure 3. EEPROM Protection (Functional and Flowchart)
1998 Jul 03 10
the data sheet must be observed. power-down is the last instruction executed. ports during low current operating modes. in program memory for its service program. flags are cleared by hardware. Table 3. External Pin Status During Idle and Power-Down Modes
- Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
of this specification is not implied.
- This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
- Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise
Philips Semiconductors Product specification 80C851/83C851CMOS single-chip 8-bit microcontroller with on-chip EEPROM
1998 Jul 03 11
DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C (VDD = 5V ±10%), –40°C to +85°C (VDD = 5V ±10%), or –40°C to +125°C (VDD = 5V ±10%), VSS = 0V PART TEST LIMITS SYMBOL PARAMETER TYPE CONDITIONS MIN MAX UNIT VIL Input low voltage, except EA 0 to +70°C –40 to +85°C –40 to +125°C –0.5 –0.5 –0.5 0.2VDD –0.1 0.2VDD –0.15 0.2VDD –0.25 V V V VIL1 Input low voltage to EA 0 to +70°C –40 to +85°C –40 to +125°C –0.5 –0.5 –0.5 0.2VDD –0.3 0.2VDD –0.35 0.2VDD –0.45 V V V VIH Input high voltage, except XTAL1, RST 0 to +70°C –40 to +85°C –40 to +125°C 0.2VDD +0.9 0.2VDD +1.0 0.2VDD +1.0 VDD +0.5 VDD +0.5 VDD +0.5 V V V VIH1 Input high voltage, XTAL1, RST 0 to +70°C –40 to +85°C –40 to +125°C 0.7VDD 0.7VDD +0.1 0.7VD +0.1 VDD +0.5 VDD +0.5 VDD +0.5 VOL Output low voltage, ports 1, 2, 3 6 IOL = 1.6mA4 0.45 V VOL1 Output low voltage, port 0, ALE, PSEN 6 IOL = 3.2mA4 0.45 V VOH Output high voltage, ports 1, 2, 3, ALE, PSEN IOH = –60µA, IOH = –25µA, IOH = –10µA 2.4 0.75VDD 0.9VDD V V V VOH1 Output high voltage, port 0 in external bus mode 5 IOH = –800µA, IOH = –300µA, IOH = –80µA 2.4 0.75VDD 0.9VDD V V V IIL Logical 0 input current, ports 1, 2, 3 0 to +70°C –40 to +85°C –40 to +125°C VIN = 0.45V –50 –75 –75 µA µA µA ITL Logical 1-to-0 transition current, ports 1, 2, 30 to +70°C –40 to +85°C –40 to +125°C VIN = 2.0V –650 –750 –750 µA µA µA IL1 Input leakage current, port 0, EA 0.45V<Vi<VDD ±10 µA IDD Power supply current: Active mode @ 16MHz 1 Active mode @ 24MHz 1 Idle mode @ 16MHz 2 Idle mode @ 24MHz 2 Power down mode 3 See note 7 3.7 5.6 mA mA mA mA µA R RST Internal reset pull-down resistor 50 150 kΩ C IO Pin capacitance f = 1MHz 10 pF NOTES: 1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS +0.5V; VIH = VDD – 0.5V; XTAL2 not connected; EA = RST = Port 0 = VDD . 2. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS +0.5V; VIH = VDD – 0.5V; XTAL2 not connected; EA = Port 0 = VDD ; RST = VSS . 3. The power-down current is measured with all output pins disconnected; XTAL2 not connected; EA = Port 0 = VDD ; RST = XTAL1 = VSS . 4. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the LOW level output voltage of ALE, Port 1 and Port 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make a 1-to-0 transition during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE line may exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 5. Capacitive loading on Port 0 and Port 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily fall below the 0.9VDD specification when the address bits are stabilizing. 6. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per Port pin: 10mA Maximum IOL per 8-bit port – Port 0: 26mA Ports 1, 2, and 3: 15mA Maximum total IOL for all output pins: 71mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 7. See Figures 11 through 14 for IDD test conditions.
Philips Semiconductors Product specification 80C851/83C851CMOS single-chip 8-bit microcontroller with on-chip EEPROM
1998 Jul 03 12
AC ELECTRICAL CHARACTERISTICS 1, 2
16 MHz Version
16MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 4 Oscillator frequency 1.2 16 MHz tLHLL 4 ALE pulse width 85 2tCLCL –40 ns tAVLL 4 Address valid to ALE low 8 tCLCL –55 ns tLLAX 4 Address hold after ALE low 28 tCLCL –35 ns tLLIV 4 ALE low to valid instruction in 150 4tCLCL –100 ns tLLPL 4 ALE low to PSEN low 23 tCLCL –40 ns tPLPH 4 PSEN pulse width 143 3tCLCL –45 ns tPLIV 4 PSEN low to valid instruction in 83 3tCLCL –105 ns tPXIX 4 Input instruction hold after PSEN 0 0 ns tPXIZ 4 Input instruction float after PSEN 38 tCLCL –25 ns tAVIV 4 Address to valid instruction in 208 5tCLCL –105 ns tPLAZ 4 PSEN low to address float 10 10 ns Data Memory tRLRH 5 RD pulse width 275 6tCLCL –100 ns tWLWH 5 WR pulse width 275 6tCLCL –100 ns tRLDV 5 RD low to valid data in 148 5tCLCL –165 ns tRHDX 5 Data hold after RD 0 0 ns tRHDZ 5 Data float after RD 55 2tCLCL –70 ns tLLDV 5 ALE low to valid data in 350 8tCLCL –150 ns tAVDV 5 Address to valid data in 398 9tCLCL –165 ns tLLWL 5, 6 ALE low to RD or WR low 138 238 3tCLCL –50 3tCLCL +50 ns tAVWL 5, 6 Address valid to RD or WR low 120 4tCLCL –130 ns tQVWH 6 Data setup time before WR 288 7tCLCL –150 ns tQVWX 6 Data valid to WR transition 3 tCLCL –60 ns tWHQX 6 Data hold after WR 13 tCLCL –50 ns tRLAZ 5 RD low to address float 0 0 ns tWHLH 5, 6 RD or WR high to ALE high 23 103 tCLCL –40 tCLCL +40 ns External Clock tCHCX 8 High time 20 20 ns tCLCX 8 Low time 20 20 ns tCLCH 8 Rise time 20 20 ns tCHCL 8 Fall time 20 20 ns Erase/write timer constant3 tE/W Erase/write cycle time 4 20 4 20 ms tE Erase time 2 10 2 10 ms tW Write time 2 10 2 10 ms tS Data retention time4 10 10 years NE/W Erase/write cycles5 10,000 10,000 cycles NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. The power-off fall-time of VDD must be less than 1ms to prevent an overwrite pulse from being generated in the EEPROM which can cause spurious parasitic writing to EEPROM cells. If the VDD power-off full-time is greater than 1ms, a power-off reset signal should be generated to prevent this condition from occurring. 4. Test condition: Tamb = +55°C. 5. Number of erase/write cycles for each EEPROM byte.
Philips Semiconductors Product specification 80C851/83C851CMOS single-chip 8-bit microcontroller with on-chip EEPROM
1998 Jul 03 13
AC ELECTRICAL CHARACTERISTICS 1, 2
24 MHz Version
24MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 4 Oscillator frequency 3.5 24 MHz tLHLL 4 ALE pulse width 43 2tCLCL –40 ns tAVLL 4 Address valid to ALE low 17 tCLCL –25 ns tLLAX 4 Address hold after ALE low 17 tCLCL –25 ns tLLIV 4 ALE low to valid instruction in 102 4tCLCL –65 ns tLLPL 4 ALE low to PSEN low 17 tCLCL –25 ns tPLPH 4 PSEN pulse width 80 3tCLCL –45 ns tPLIV 4 PSEN low to valid instruction in 65 3tCLCL –60 ns tPXIX 4 Input instruction hold after PSEN 0 0 ns tPXIZ 4 Input instruction float after PSEN 17 tCLCL –25 ns tAVIV 4 Address to valid instruction in 128 5tCLCL –80 ns tPLAZ 4 PSEN low to address float 10 10 ns Data Memory tRLRH 5 RD pulse width 150 6tCLCL –100 ns tWLWH 5 WR pulse width 150 6tCLCL –100 ns tRLDV 5 RD low to valid data in 118 5tCLCL –90 ns tRHDX 5 Data hold after RD 0 0 ns tRHDZ 5 Data float after RD 55 2tCLCL –28 ns tLLDV 5 ALE low to valid data in 183 8tCLCL –150 ns tAVDV 5 Address to valid data in 210 9tCLCL –165 ns tLLWL 5, 6 ALE low to RD or WR low 75 175 3tCLCL –50 3tCLCL +50 ns tAVWL 5, 6 Address valid to RD or WR low 92 4tCLCL –75 ns tQVWH 6 Data setup time before WR 162 7tCLCL –130 ns tQVWX 6 Data valid to WR transition 12 tCLCL –30 ns tWHQX 6 Data hold after WR 17 tCLCL –25 ns tRLAZ 5 RD low to address float 0 0 ns tWHLH 5, 6 RD or WR high to ALE high 17 67 tCLCL –25 tCLCL +25 ns External Clock tCHCX 8 High time 17 17 ns tCLCX 8 Low time 17 17 ns tCLCH 8 Rise time 5 20 ns tCHCL 8 Fall time 5 20 ns Erase/write timer constant3 tE/W Erase/write cycle time 4 20 4 20 ms tE Erase time 2 10 2 10 ms tW Write time 2 10 2 10 ms tS Data retention time4 10 10 years NE/W Erase/write cycles5 10,000 10,000 cycles NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. The power-off fall-time of VDD must be less than 1ms to prevent an overwrite pulse from being generated in the EEPROM which can cause spurious parasitic writing to EEPROM cells. If the VDD power-off full-time is greater than 1ms, a power-off reset signal should be generated to prevent this condition from occurring. 4. Test condition: Tamb = +55°C. 5. Number of erase/write cycles for each EEPROM byte.
1998 Jul 03 14
Figure 4. External Program Memory Read Cycle Figure 5. External Data Memory Read Cycle
1998 Jul 03 15
Figure 6. External Data Memory Write Cycle Figure 7. Instruction Timing
1998 Jul 03 16
Table 4. External Clock Drive XTAL1 Figure 8. External Clock Drive Figure 9. AC Testing Input/Output AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at 2.0V min for a logic ‘1’ and 0.8V for a logic ‘0’. Figure 10. Float Waveform from the loaded VOH /VOL level occurs. IOH /IOL ≥± 20mA.
1998 Jul 03 17
Figure 11. IDD Test Condition, Active Mode Figure 12. IDD Test Condition, Idle Mode Figure 13. Clock Signal Waveform for IDD Tests Figure 14. IDD Test Condition, Power Down Mode All other pins are disconnected.
CMOS single-chip 8-bit microcontroller with on-chip EEPROM Philips Semiconductors Product specification 80C851/83C851
1998 Jul 03 18
DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1
CMOS single-chip 8-bit microcontroller with on-chip EEPROM Philips Semiconductors Product specification 80C851/83C851
1998 Jul 03 19
PLCC44: plastic leaded chip carrier; 44 leads SOT187-2
CMOS single-chip 8-bit microcontroller with on-chip EEPROM Philips Semiconductors Product specification 80C851/83C851
1998 Jul 03 20
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2
CMOS single-chip 8-bit microcontroller with on-chip EEPROM Philips Semiconductors Product specification 80C851/83C851
1998 Jul 03 21
CMOS single-chip 8-bit microcontroller with on-chip EEPROM Philips Semiconductors Product specification 80C851/83C851
1998 Jul 03 22
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 09-98 Document order number: 9397 750 04368 /C0109 /C0110 /C0114 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.