S80C552-AB

80C552 PHILIPS | Alldatasheet

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/C0080 /C0115 /C0111/C0110/C0111 /C0115 80C552/83C552 Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM Product data Supersedes data of 1998 Aug 13

2002 Sep 03

Philips Semiconductors Product data 80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM

22002 Sep 03 853-1467 28849

DESCRIPTION

The 80C552/83C552 (hereafter generically referred to as 8XC552) Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 8XC552 has the same instruction set as the 80C51. Three versions of the derivative exist:

• 83C552—8 kbytes mask programmable ROM
• 80C552—ROMless version of the 83C552
• 87C552—8 kbytes EPROM (described in a separate chapter) The 8XC552 contains a non-volatile 8k × 8 read-only program memory (83C552), a volatile 256 × 8 read/write data memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16-bit timer coupled to capture and compare latches, a 15-source, two-priority-level, nested interrupt structure, an 8-input ADC, a dual DAC pulse width modulated interface, two serial interfaces (UART and I 2C-bus), a “watchdog” timer and on-chip oscillator and timing circuits. For systems that require extra capability, the 8XC552 can be expanded using standard TTL compatible memories and logic. In addition, the 8XC552 has two software selectable modes of power reduction—idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial ports, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte, and 17 three-byte. With a 16 MHz (24 MHz) crystal, 58% of the instructions are executed in 0.75 µs (0.5 µs) and 40% in 1.5 µs (1 µs). Multiply and divide instructions require 3 µs (2 µs).

FEATURES

• 80C51 central processing unit
• 8k × 8 ROM expandable externally to 64 kbytes
• ROM code protection
• An additional 16-bit timer/counter coupled to four capture registers and three compare registers
• Two standard 16-bit timer/counters
• 256 × 8 RAM, expandable externally to 64 kbytes
• Capable of producing eight synchronized, timed outputs
• A 10-bit ADC with eight multiplexed analog inputs
• Two 8-bit resolution, pulse width modulation outputs
• Five 8-bit I/O ports plus one 8-bit input port shared with analog inputs
• I2C-bus serial I/O port with byte oriented master and slave functions
• Full-duplex UART compatible with the standard 80C51
• On-chip watchdog timer
• Three speed ranges: – 3.5 to 16 MHz – 3.5 to 24 MHz (ROM, ROMless only)
• Three operating ambient temperature ranges: – P83C552xBx: 0°C to +70°C – P83C552xFx: –40°C to +85°C (XTAL frequency max. 24 MHz) – P83C552xHx: –40°C to +125°C (XTAL frequency max. 16 MHz) LOGIC SYMBOL SU01691 PORT 5PORT 4 ADC0-7 CMT0 CMT1 CMSR0-5 RST EW XTAL1 XTAL2 EA ALE PSEN AVref+ AVref– STADC PWM0 PWM1 PORT 0 LOW ORDER ADDRESS AND DATA BUS PORT 1PORT 2PORT 3 CT0I CT1I CT2I CT3I RT2 SCL SDA RxD/DATA TxD/CLOCK INT0 INT1 WR RD VSS VDD AV SS AV DD HIGH ORDER ADDRESS AND DATA BUS

Philips Semiconductors Product data 80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM

2002 Sep 03 3

Plastic Leaded Chip Carrier NC* P3.7/RD P3.6/WR P5.0/ADC0 30 31 32 33 34 35 36 P4.3/CMSR3 P4.4/CMSR4 P4.5/CMSR5 P4.6/CMT0 P4.7/CMT1 P1.0/CT0I RST 37 3828 29 P1.1/CT1I P1.2/CT2I P1.4/T2 P1.3/CT3I PLASTIC LEADED CHIP CARRIER SU00932 P1.5/RT2 P1.6/SCL P1.7/SDA P3.0/RxD P3.2/INT0 P3.1/TxD 39 40 41 42 43 P3.4/T0 P3.5/T1 NC* NC* XTAL2 XTAL1 V SS P2.1/A09 P2.2/A10 P2.3/A11 P2.4/A12 AV SS AV REF+ AV REF– P0.0/AD0 P0.1/AD1 P0.3/AD3 P0.2/AD2 P0.4/AD4 P0.5/AD5 P0.7/AD7 P0.6/AD6 EA ALE PSEN P2.7/A15 P2.5/A13 P2.6/A14 7654321 68 6798 66 65 64 63 62 P4.2/CMSR2 P4.1/CMSR1 P4.0/CMSR0 EW PWM1 PWM0 STADC P5.1/ADC1 P5.2/ADC2 P5.3/ADC3 P5.4/ADC4 P5.5/ADC5 P5.6/ADC6 P5.7/ADC7 AVDD V DD P3.3/INT1 VSS P2.0/A08 * Do not connect.

Philips Semiconductors Product data 80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM

2002 Sep 03 4

P4.1/CMSR1 P4.2/CMSR2 NC* P4.3/CMSR3 P4.4/CMSR4 P4.6/CMT0 P4.5/CMSR5 34 3525 26 P4.7/CMT1 RST P1.1/CT1I P1.0/CT0I PLASTIC QUAD FLAT PACK SU00931 P1.2/CT2I P1.3/CT3I P1.4/T2 P1.5/RT2 P1.7/SDA P1.6/SCL P3.0/RxD P3.1/TxD NC* P3.2/INT0 NC* P3.3/INT1 PP3.4/T0 36 37 38 39 40 P3.5/T1 P3.6/WR P3.7/RD NC* NC* NC* XTAL2 XTAL1 IC V SS VSS VSS NC* P2.0/A08 P2.1/A09 P2.2/A10 P5.7/ADC7 AV DD NC* AV SS AV REF+ P0.0/AD0 AV REF– P0.1/AD1 P0.2/AD2 P0.4/AD4 P0.3/AD3 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA PSEN ALE P2.7/A15 P2.6/A14 NC* P2.5/A13 NC* P2.4/A12 P2.3/A11 78 77 76 75 74 73 72 71 7080 79 69 68 67 66 65 P4.0/SMSR0 NC* NC* EW PWM1 PWM0 STADC IC P5.0/ADC0 P5.1/ADC1 P5.2/ADC2 P5.3/ADC3 P5.4/ADC4 P5.5/ADC5 P5.6/ADC6 * Do not connect. IC = Internally connected (do not use).

Philips Semiconductors Product data 80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM

2002 Sep 03 5

P0 P1 P2 P3 TxD RxD P5 P4 CT0I-CT3I T2 RT2 CMSR0-CMSR5 CMT0, CMT1 RST EW XTAL1 XTAL2 EA ALE PSEN WR RD T0 T1 INT0 INT1 VDD VSS PWM0 PWM1 AV SS AV DD AV REF STADC ADC0-7 SDA SCL 3 3 3 3 3 3 1 1 1 4 115 ALTERNATE FUNCTION OF PORT 0 3 AD0-7 A8-15 T0, T1 TWO 16-BIT TIMER/EVENT COUNTERS PROGRAM MEMORY 8k x 8 ROM DATA MEMORY 256 x 8 RAM DUAL PWM SERIAL I2C PORT 80C51 CORE EXCLUDING ROM/RAM PARALLEL I/O PORTS AND EXTERNAL BUS SERIAL UART PORT 8-BIT PORT FOUR 16-BIT CAPTURE LATCHES 16-BIT TIMER/ EVENT COUNTERS 16-BIT COMPARA- TORS wITH REGISTERS COMPARA- TOR OUTPUT SELECTION WATCHDOG TIMER ALTERNATE FUNCTION OF PORT 1 ALTERNATE FUNCTION OF PORT 2 ALTERNATE FUNCTION OF PORT 3 ALTERNATE FUNCTION OF PORT 4 ALTERNATE FUNCTION OF PORT 5

Philips Semiconductors Product data 80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM

2002 Sep 03 6

ORDERING INFORMATION

TEMPERATURE ( °C) AND PACKAGE FREQ (MHz ) ROMless ROM 1 P80C552EBA P83C552EBA/xxx SOT188-2 0 to +70, Plastic Leaded Chip Carrier 16 P80C552EBB P83C552EBB/xxx SOT318-2 0 to +70, Plastic Quad Flat Pack 16 P80C552EFA P83C552EFA/xxx SOT188-2 –40 to +85, Plastic Leaded Chip Carrier 16 P80C552EFB P83C552EFB/xxx SOT318-2 –40 to +85, Plastic Quad Flat Pack 16 P80C552EHA P83C552EHA/xxx SOT188-2 –40 to +125, Plastic Leaded Chip Carrier 16 P80C552EHB P83C552EHB/xxx SOT318-2 –40 to +125, Plastic Quad Flat Pack 16 P80C552IBA P83C552IBA/xxx SOT188-2 0 to +70, Plastic Leaded Chip Carrier 24 P80C552IBB P83C552IBB/xxx SOT318-2 0 to +70, Plastic Quad Flat Pack 24 P80C552IFA P83C552IFA/xxx SOT188-2 –40 to +85, Plastic Leaded Chip Carrier 24 P80C552IFB P83C552IFB/xxx SOT318-2 –40 to +85, Plastic Quad Flat Pack 24 NOTE: 1. xxx denotes the ROM code number. 2. For EPROM device specification, refer to 87C552 datasheet.

Philips Semiconductors Product data 80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM

2002 Sep 03 7

PIN NO. MNEMONIC PLCC QFP TYPE NAME AND FUNCTION VDD 2 72 I Digital Power Supply: +5 V power supply pin during normal operation, idle and power-down mode. STADC 3 74 I Start ADC Operation: Input starting analog to digital conversion (ADC operation can also be started by software). This pin must not float. PWM0 4 75 O Pulse Width Modulation: Output 0. PWM1 5 76 O Pulse Width Modulation: Output 1. EW 6 77 I Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode. This pin must not float. P0.0-P0.7 57-50 58-51 I/O Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pull-ups when emitting 1s. P1.0-P1.7 16-23 10-17 I/O Port 1: 8-bit I/O port. Alternate functions include: 16-21 10-15 I/O (P1.0-P1.5): Quasi-bidirectional port pins. 22-23 16-17 I/O (P1.6, P1.7): Open drain port pins. 16-19 10-13 I CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2. 20 14 I T2 (P1.4): T2 event input. 21 15 I RT2 (P1.5): T2 timer reset signal. Rising edge triggered. 22 16 I/O SCL (P1.6): Serial port clock line I2C-bus. 23 17 I/O SDA (P1.7): Serial port data line I2C-bus. Port 1 is also used to input the lower order address byte during EPROM programming and verification. A0 is on P1.0, etc. 45-47 I/O Port 2: 8-bit quasi-bidirectional I/O port. Alternate function: High-order address byte for external memory (A08-A15). 23-27 I/O Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include: 24 18 RxD(P3.0): Serial input port. 25 19 TxD (P3.1): Serial output port. 26 20 INT0 (P3.2): External interrupt. 27 23 INT1 (P3.3): External interrupt. 28 24 T0 (P3.4): Timer 0 external input. 29 25 T1 (P3.5): Timer 1 external input. 30 26 WR (P3.6): External data memory write strobe. 31 27 RD (P3.7): External data memory read strobe. 4-8 I/O Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include: 7-12 80, 1-2 4-6 O CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with timer T2. 13, 14 7, 8 O CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2. P5.0-P5.7 68-62, 71-64, I Port 5: 8-bit input port. 1 ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to ADC. RST 15 9 I/O Reset: Input to reset the 8XC552. It also provides a reset pulse as output when timer T3 overflows. XTAL1 35 32 I Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the internal clock generator. Receives the external clock signal when an external oscillator is used. XTAL2 34 31 O Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit when an external clock is used.

2002 Sep 03 8

VSS 36, 37 34-36 I Two Digital ground pins. PSEN 47 48 O Program Store Enable: Active-low read strobe to external program memory. CMOS inputs without an external pull-up. low level, the CPU executes out of external program memory. EA is not allowed to float. AV REF– 58 59 I Analog to Digital Conversion Reference Resistor: Low-end. AV REF+ 59 60 I Analog to Digital Conversion Reference Resistor: High-end.

1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than VDD + 0.5 V or VSS – 0.5 V,

oscillator, as shown in the logic symbol, page 2. the internal clock circuitry is through a divide-by-two flip-flop. the data sheet must be observed. machine cycles (24 oscillator periods), while the oscillator is running. DD and RST must come up at the same time for a proper start-up. the processor in the same manner as a power-on reset. instruction to invoke power-down is the last instruction executed. any instruction in the external program memory space. any other instruction that uses immediate data. Table 1. External Pin Status During Idle and Power-Down Modes

2002 Sep 03 9

Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation. Table 2. Serial Clock Rates

1. These frequencies exceed the upper limit of 100kHz of the I2C-bus specification and cannot be used in an I2C-bus application.
2. At fOSC = 24 MHz the maximum I2C bus rate of 100kHz cannot be realized due to the fixed divider rates.
3. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

of this specification is not implied.

1. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise

Philips Semiconductors Product data 80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM

2002 Sep 03 10

DC ELECTRICAL CHARACTERISTICS VSS , AVSS = 0 V; VDD , AVDD = 5 V ± 10% TEST LIMITS SYMBOL PARAMETER CONDITIONS MIN MAX UNIT IDD Supply current operating: See notes 1 and 2 P83(0)C552EBx fOSC = 16 MHz 45 mA P83(0)C552EFx fOSC = 16 MHz 45 mA P83(0)C552EHx fOSC = 16 MHz 40 mA P83(0)C552IBx fOSC = 24 MHz 55 mA P83(0)C552IFx fOSC = 24 MHz 55 mA IID Idle mode: See notes 1 and 3 P83(0)C552EBx fOSC = 16 MHz 10 mA P83(0)C552EFx fOSC = 16 MHz 10 mA P83(0)C552EHx fOSC = 16 MHz 9 mA P83(0)C552IBx fOSC = 24 MHz 12.5 mA P83(0)C552IFx fOSC = 24 MHz 12.5 mA IPD Power-down current: See notes 1 and 4;

2 V < VPD < VDD max

P83(0)C552xBx 50 µA P83(0)C552xFx 50 µA P83(0)C552xHx 150 µA Inputs VIL1 Input low voltage to EA –0.5 0.2VDD –0.3 V VIL2 Input low voltage to P1.6/SCL, P1.7/SDA5 –0.5 0.3VDD V VIH1 Input high voltage, XTAL1, RST 0.7VDD VDD +0.5 V VIH2 Input high voltage, P1.6/SCL, P1.7/SDA5 0.7VDD 6.0 V IIL Logical 0 input current, ports 1, 2, 3, 4, except P1.6, P1.7VIN = 0.45 V –50 µA ITL Logical 1-to-0 transition current, ports 1, 2, 3, 4, except P1.6, P1.7See note 6 –650 µA ±IIL1 Input leakage current, port 0, EA, STADC, EW 0.45 V < VI < VDD 10 µA ±IIL2 Input leakage current, P1.6/SCL, P1.7/SDA 0 V < VI < 6 V 0 V < VDD < 5.5 V 10 µA ±IIL3 Input leakage current, port 5 0.45 V < VI < VDD 1 µA Outputs VOL Output low voltage, ports 1, 2, 3, 4, except P1.6, P1.7 IOL = 1.6mA7 0.45 V VOL1 Output low voltage, port 0, ALE, PSEN, PWM0 , PWM1 IOL = 3.2mA7 0.45 V VOL2 Output low voltage, P1.6/SCL, P1.7/SDA IOL = 3.0mA7 0.4 V VOH Output high voltage, ports 1, 2, 3, 4, except P1.6/SCL, P1.7/SDA–IOH = 60µA 2.4 V –IOH = 25µA 0.75VDD V –IOH = 10µA 0.9VDD V VOH1 Output high voltage (port 0 in external bus mode, ALE, PSEN PWM0 PWM1 )8 –IOH = 400µA 2.4 V PSEN , PWM0 , PWM1 )8 –IOH = 150µA 0.75VDD V –IOH = 40µA 0.9VDD V VOH2 Output high voltage (RST) –IOH = 400µA 2.4 V –IOH = 120µA 0.8VDD V R RST Internal reset pull-down resistor 50 150 kΩ C IO Pin capacitance Test freq = 1 MHz, Tamb = 25°C 10 pF

Philips Semiconductors Product data 80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM

2002 Sep 03 11

DC ELECTRICAL CHARACTERISTICS (Continued) TEST LIMITS SYMBOL PARAMETER CONDITIONS MIN MAX UNIT Analog Inputs AIDD Analog supply current: operating: (16 MHz) Port 5 = 0 to AVDD 1.2 mA Analog supply current: operating: (24 MHz) Port 5 = 0 to AVDD 1.0 mA AIID Idle mode: P83(0)C552EBx 50 µA P83(0)C552EFx 50 µA P83(0)C552EHx 100 µA P83(0)C552IBx 50 µA P83(0)C552IFx 50 µA AIPD Power-down mode: 2 V < AVPD < AVDD max P83(0)C552xBx 50 µA P83(0)C552xFx 50 µA P83(0)C552xHx 100 µA AV IN Analog input voltage AV SS –0.2 AV DD +0.2 V AV REF Reference voltage: AV REF– AV SS –0.2 V AV REF+ AV DD +0.2 V R REF Resistance between AVREF+ and AVREF– 10 50 kΩ C IA Analog input capacitance 15 pF tADS Sampling time 8tCY µs tADC Conversion time (including sampling time) 50tCY µs DL e Differential non-linearity10, 11, 12 ±1 LSB ILe Integral non-linearity10, 13 ±2 LSB OS e Offset error10, 14 ±2 LSB G e Gain error10, 15 ±0.4 % Ae Absolute voltage error10, 16 ±3 LSB M CTC Channel to channel matching ±1 LSB C t Crosstalk between inputs of port 517 0–100kHz –60 dB NOTES FOR DC ELECTRICAL CHARACTERISTICS: 1. See Figures 10 through 15 for IDD test conditions. 2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns; VIL = VSS + 0.5 V; VIH = VDD – 0.5 V; XTAL2 not connected; EA = RST = Port 0 = EW = VDD ; STADC = VSS . 3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns; VIL = VSS + 0.5 V; VIH = VDD – 0.5 V; XTAL2 not connected; Port 0 = EW = VDD ; EA = RST = STADC = VSS . 4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = VDD ; EA = RST = STADC = XTAL1 = VSS . 5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 1.5 V will be recognized as a logic 0 while an input voltage above 3.0 V will be recognized as a logic 1. 6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2 V. 7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOL s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 8. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD specification when the address bits are stabilizing. 9. The following condition must not be exceeded: VDD – 0.2 V < AVDD < VDD + 0.2 V. continuous conversion of AVIN = –20 mV to 5.12 V in steps of 0.5 mV. 11. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. (See Figure 1.) 12.The ADC is monotonic; there are no missing codes. 13.The integral non-linearity (IL e) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset error. (See Figure 1.)

2002 Sep 03 12

ADC and the ideal transfer curve. 17.This should be considered when both analog and digital signals are simultaneously input to port 5.

1 LSB

1 LSB = AV REF+ – AV REF–

(1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential non-linearity (DLe). (4) Integral non-linearity (ILe). (5) Center of a step of the actual transfer curve. Figure 1. ADC Conversion Characteristic

Philips Semiconductors Product data 80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM

2002 Sep 03 13

AC ELECTRICAL CHARACTERISTICS 1, 2

16 MHz version

16 MHz CLOCK VARIABLE CLOCK

SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 2 Oscillator frequency 3.5 16 MHz tLHLL 2 ALE pulse width 85 2tCLCL –40 ns tAVLL 2 Address valid to ALE low 8 tCLCL –55 ns tLLAX 2 Address hold after ALE low 28 tCLCL –35 ns tLLIV 2 ALE low to valid instruction in 150 4tCLCL –100 ns tLLPL 2 ALE low to PSEN low 23 tCLCL –40 ns tPLPH 2 PSEN pulse width 143 3tCLCL –45 ns tPLIV 2 PSEN low to valid instruction in 83 3tCLCL –105 ns tPXIX 2 Input instruction hold after PSEN 0 0 ns tPXIZ 2 Input instruction float after PSEN 38 tCLCL –25 ns tAVIV 2 Address to valid instruction in 208 5tCLCL –105 ns tPLAZ 2 PSEN low to address float 10 10 ns Data Memory tRLRH 3 RD pulse width 275 6tCLCL –100 ns tWLWH 4 WR pulse width 275 6tCLCL –100 ns tRLDV 3 RD low to valid data in 148 5tCLCL –165 ns tRHDX 3 Data hold after RD 0 0 ns tRHDZ 3 Data float after RD 55 2tCLCL –70 ns tLLDV 3 ALE low to valid data in 350 8tCLCL –150 ns tAVDV 3 Address to valid data in 398 9tCLCL –165 ns tLLWL 3, 4 ALE low to RD or WR low 138 238 3tCLCL –50 3tCLCL +50 ns tAVWL 3, 4 Address valid to WR low or RD low 120 4tCLCL –130 ns tQVWX 4 Data valid to WR transition 3 tCLCL –60 ns tDW 4 Data before WR 288 7tCLCL –150 ns tWHQX 4 Data hold after WR 13 tCLCL –50 ns tRLAZ 3 RD low to address float 0 0 ns tWHLH 3, 4 RD or WR high to ALE high 23 103 tCLCL –40 tCLCL +40 ns External Clock tCHCX 5 High time4 20 20 ns tCLCX 5 Low time4 20 20 ns tCLCH 5 Rise time4 20 20 ns tCHCL 5 Fall time4 20 20 ns Serial Timing – Shift Register Mode4 (Test Conditions: Tamb = 0°C to +70°C; VSS = 0 V; Load Capacitance = 80 pF) tXLXL 6 Serial port clock cycle time 0.75 12tCLCL µs tQVXH 6 Output data setup to clock rising edge492 10tCLCL –133 ns tXHQX 6 Output data hold after clock rising edge8 2tCLCL –117 ns tXHDX 6 Input data hold after clock rising edge0 0 ns tXHDV 6 Clock rising edge to input data valid 492 10tCLCL –133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. tCLCL = 1/fOSC = one oscillator clock period. tCLCL = 83.3ns at fOSC = 12 MHz. tCLCL = 62.5ns at fOSC = 16 MHz. 4. These values are characterized but not 100% production tested.

Philips Semiconductors Product data 80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM

2002 Sep 03 14

AC ELECTRICAL CHARACTERISTICS (Continued)1, 2

24 MHz version

24 MHz CLOCK VARIABLE CLOCK

SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 2 Oscillator frequency 3.5 24 MHz tLHLL 2 ALE pulse width 43 2tCLCL –40 ns tAVLL 2 Address valid to ALE low 17 tCLCL –25 ns tLLAX 2 Address hold after ALE low 17 tCLCL –25 ns tLLIV 2 ALE low to valid instruction in 102 4tCLCL –65 ns tLLPL 2 ALE low to PSEN low 17 tCLCL –25 ns tPLPH 2 PSEN pulse width 80 3tCLCL –45 ns tPLIV 2 PSEN low to valid instruction in 65 3tCLCL –60 ns tPXIX 2 Input instruction hold after PSEN 0 0 ns tPXIZ 2 Input instruction float after PSEN 17 tCLCL –25 ns tAVIV 2 Address to valid instruction in 128 5tCLCL –80 ns tPLAZ 2 PSEN low to address float 10 10 ns Data Memory tRLRH 3 RD pulse width 150 6tCLCL –100 ns tWLWH 4 WR pulse width 150 6tCLCL –100 ns tRLDV 3 RD low to valid data in 118 5tCLCL –90 ns tRHDX 3 Data hold after RD 0 0 ns tRHDZ 3 Data float after RDxs 55 2tCLCL –28 ns tLLDV 3 ALE low to valid data in 183 8tCLCL –150 ns tAVDV 3 Address to valid data in 210 9tCLCL –165 ns tLLWL 3, 4 ALE low to RD or WR low 75 175 3tCLCL –50 3tCLCL +50 ns tAVWL 3, 4 Address valid to WR low or RD low 92 4tCLCL –75 ns tQVWX 4 Data valid to WR transition 12 tCLCL –30 ns tDW 4 Data before WR 162 7tCLCL –130 ns tWHQX 4 Data hold after WR 17 tCLCL –25 ns tRLAZ 3 RD low to address float 0 0 ns tWHLH 3, 4 RD or WR high to ALE high 17 67 tCLCL –25 tCLCL +25 ns External Clock tCHCX 5 High time3 17 17 ns tCLCX 5 Low time3 17 17 ns tCLCH 5 Rise time3 5 20 ns tCHCL 5 Fall time3 5 20 ns Serial Timing – Shift Register Mode3 (Test Conditions: Tamb = 0°C to +70°C; VSS = 0 V; Load Capacitance = 80 pF) tXLXL 6 Serial port clock cycle time 0.5 12tCLCL µs tQVXH 6 Output data setup to clock rising edge 283 10tCLCL –133 ns tXHQX 6 Output data hold after clock rising edge23 2tCLCL –60 ns tXHDX 6 Input data hold after clock rising edge 0 0 ns tXHDV 6 Clock rising edge to input data valid 283 10tCLCL –133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. These values are characterized but not 100% production tested. 4. tCLCL = 1/fOSC = one oscillator clock period. tCLCL = 41.7ns at fOSC = 24 MHz.

Philips Semiconductors Product data 80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM

2002 Sep 03 15

AC ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PARAMETER INPUT OUTPUT I2C Interface (Refer to Figure 9) tHD;STA START condition hold time ≥ 14 tCLCL > 4.0 µs 1 tLOW SCL low time ≥ 16 tCLCL > 4.7 µs 1 tHIGH SCL high time ≥ 14 tCLCL > 4.0 µs 1 tRC SCL rise time ≤ 1 µs – 2 tFC SCL fall time ≤ 0.3 µs < 0.3 µs 3 tSU;DAT1 Data set-up time ≥ 250ns > 20 tCLCL – tRD tSU;DAT2 SDA set-up time (before rep. START cond.) ≥ 250ns > 1 µs 1 tSU;DAT3 SDA set-up time (before STOP cond.) ≥ 250ns > 8 tCLCL tHD;DAT Data hold time ≥ 0ns > 8 tCLCL – tFC tSU;STA Repeated START set-up time ≥ 14 tCLCL > 4.7 µs 1 tSU;STO STOP condition set-up time ≥ 14 tCLCL > 4.0 µs 1 tBUF Bus free time ≥ 14 tCLCL > 4.7 µs 1 tRD SDA rise time ≤ 1 µs – 2 tFD SDA fall time ≤ 0.3 µs < 0.3 µs 3 NOTES: 1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 µs. 3. Spikes on the SDA and SCL lines with a duration of less than 3 tCLCL will be filtered out. Maximum capacitance on bus-lines SDA and SCL = 400 pF. 4. tCLCL = 1/fOSC = one oscillator clock period at pin XTAL1. For 62 ns, 42 ns < tCLCL < 285 ns (16 MHz, 24 MHz > fOSC > 3.5 MHz) the SI01 interface meets the I2C-bus specification for bit-rates up to 100 kbit/s.

2002 Sep 03 16

Figure 2. External Program Memory Read Cycle Figure 3. External Data Memory Read Cycle

2002 Sep 03 17

Figure 4. External Data Memory Write Cycle Figure 5. External Clock Drive XTAL1 Figure 6. Shift Register Mode Timing

2002 Sep 03 18

LOGIC ‘1’ AND VIL MAX FOR A LOGIC ‘0’. Figure 7. AC Testing Input/Output Figure 8. Float Waveform

0.7 VCC

0.3 VCC

Figure 9. Timing SIO1 (I2C) Interface

2002 Sep 03 19

These values are valid only within the frequency specifications of the device under test. Figure 10. 16 MHz Version Supply Current (IDD ) as a Function of Frequency at XTAL1 (fOSC ) These values are valid only within the frequency specifications of the device under test.

5.5 V(2) Maximum operating mode; V DD =

Figure 11. 24 MHz Version Supply Current (IDD ) as a Function of Frequency at XTAL1 (fOSC )

2002 Sep 03 20

Figure 12. IDD Test Condition, Active Mode Figure 13. IDD Test Condition, Idle Mode Figure 14. Clock Signal Waveform for IDD Tests in Active and Figure 15. IDD Test Condition, Power Down Mode a. The following pins must be forced to VDD : EA, RST, Port 0, and EW. b. The following pins must be forced to VSS : STADC, AVss, and AVref–. exceed the IOL1 spec of these pins. d. The following pins must be disconnected: XTAL2 and all pins not specified above. a. The following pins must be forced to VDD : Port 0 and EW. b. The following pins must be forced to VSS : RST, STADC, AVss,, AVref–, and EA. exceed the IOL1 spec of these pins. These pins must not have logic 0 written to them prior to this measurement. d. The following pins must be disconnected: XTAL2 and all pins not specified above. a. The following pins must be forced to VDD : Port 0 and EW. b. The following pins must be forced to VSS : RST, STADC, XTAL1, AVss,, AVref–, and EA. exceed the IOL1 spec of these pins. These pins must not have logic 0 written to them prior to this measurement. d. The following pins must be disconnected: XTAL2 and all pins not specified above.

Philips Semiconductors Product data 80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM

2002 Sep 03 21

PLCC68: plastic leaded chip carrier; 68 leads SOT188-2

Philips Semiconductors Product data 80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM

2002 Sep 03 22

QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT318-2

Philips Semiconductors Product data 80C552/83C552Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM

2002 Sep 03 23

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to:  Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 09-02 Document order number: 9397 750 10294 /C0080 /C0115 /C0111/C0110/C0111 /C0115 Data sheet status[1] Objective data Preliminary data Product data Product status[2] Development Qualification Production Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.