S76HL512T

S76HS512TC0 INFINEON | Alldatasheet

Document overview

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Technical content

Features

• SEMPER™ Flash and HYPERRAM™ 2.0 with HYPERBUS™ interface in multi-chip package (MCP) - 1.8 V, 512Mb SEMPER™ Flash and 64Mb HYPERRAM™ 2.0 (S76HS512TC0) - 3.0 V, 512Mb SEMPER™ Flash and 64Mb HYPERRAM™ 2.0 (S76HL512TC0) - FBGA 24-ball, 8 × 8 × 1.2 mm packages
• HYPERBUS™ interface - 1.8 V I/O (S76HS-TC0) - 3.0 V I/O (S76HL-TC0) - Chip select (CS#) - 8-bit data bus (DQ[7:0]) -D a t a s t r o b e ( D S / R W D S )
• Bidirectional DS/mask
• Output at the start of all transactions to indicate refresh latency
• Output during read transactions as read DS
• Input during write transactions as write data mask (HYPERRAM™ only)
• O p t i o n a l s i g n a l s - INT# output to generate external interrupt
• Busy to ready transition - RSTO# output to generate system level power-on-reset (POR)
• User configurable RSTO# LOW period
• H i g h - p e r f o r m a n c e -D D R
• Two data transfers per clock - Up to 200 MHz clock rate (400-MBps) at 1.8 V V CC - Up to 166 MHz clock rate (333-MBps) at 3.0 V V CC

Supplement Datasheet 2 002-31140 Rev. *B 2022-09-21 512Mb SEMPER™ Flash and 64Mb HYPERRAM™ 2.0 HYPERBUS™ interface, multi-chip package, 1.8 V/3.0 V Table of contents Table of contents

Supplement Datasheet 3 002-31140 Rev. *B 2022-09-21 512Mb SEMPER™ Flash and 64Mb HYPERRAM™ 2.0 HYPERBUS™ interface, multi-chip package, 1.8 V/3.0 V General description

1 General description

This supplementary datasheet provides MCP device related information for HYPERBUS™ MCP family, incorporating both SEMPER™ Flash and HYPERRAM™ with HYPERBUS™ interface memories. The document describes how the features, operation, and ordering options of the related memories have been enhanced or changed from the standard memory devices incorporated in the MCP . The information contained in this document modifies any information on the same topics established by the documents listed in Table 1, and should be used in conjunction with those documents. This document may also contain information that was not previously covered by the listed documents. The information is intended for hardware system designers and software developers of applications, operating systems, or tools.

1.1 HYPERBUS™ MCP family with SEMPER™ Flash and HYPERRAM™

For systems needing both Flash and self-refresh DRAM, the HYPERBUS™ product family includes MCP devices that combine SEMPER™ Flash and HYPERRAM™ in single package. A HYPERBUS™ MCP reduces board space and printed circuit board (PCB) signal routing congestion while also maintaining or improving signal integrity over separately packaged memory configurations. The HYPERBUS™ MCP family offers 1.8 V/3.0 V interface SEMPER™ Flash densities of 512Mb (64MB) in combination with HYPERRAM™ 64Mb (8MB). The SEMPER™ Flash default configuration is HYPERBUS™ interface with configuration bit INTFTP = 1. This supplement datasheet addresses only the MCP related differences from the HYPERBUS™ specification and the individual SEMPER™ Flash and HYPERRAM™ datasheets. For other information related to the individual memories in the MCP , refer to the SEMPER™ Flash, and HYPERRAM™ datasheets with HYPERBUS™ interface. Table 1 Affected documents/related documents Title Infineon publication number S26HS256T , S26HS512T , S26HS01GT , S26HL256T , S26HL512T , S26HL01GT 256Mb/512Mb/1Gb SEMPER™ Flash HYPERBUS™ interface, 1.8 V/3.0 V 002-12337 S27KL0642, S27KS0642 64Mb HYPERRAM™ self-refresh DRAM (PSRAM) HYPERBUS™ interface, 1.8 V/3.0 V 002-24692

Supplement Datasheet 4 002-31140 Rev. *B 2022-09-21 512Mb SEMPER™ Flash and 64Mb HYPERRAM™ 2.0 HYPERBUS™ interface, multi-chip package, 1.8 V/3.0 V HYPERBUS™ MCP signal description

2 HYPERBUS™ MCP signal description

Figure 1 HYPERBUS™ MCP signal diagram RESET# CS1# CS2# CK# VCC VCCQ DQ[7:0] DS/RWDS INT# RSTO# VSS VSSQ CK

Supplement Datasheet 5 002-31140 Rev. *B 2022-09-21 512Mb SEMPER™ Flash and 64Mb HYPERRAM™ 2.0 HYPERBUS™ interface, multi-chip package, 1.8 V/3.0 V HYPERBUS™ MCP signal description Table 2 Signal description Symbol Type Description CS1# Input Chip select 1. Chip select for the SEMPER™ Flash memory. HYPERBUS™ transactions are initiated with a HIGH-to-LOW transition. HYPERBUS™ transactions are terminated with a LOW- to-HIGH transition. CS2# Input Chip select 2. Chip select for the HYPERRAM™ memory. HYPERBUS™ transactions are initiated with a HIGH-to-LOW transition. HYPERBUS™ transactions are terminated with a LOW-to-HIGH transition. CK Input Single-ended clock. Command-address/data information is input or output with respect to the edges of the CK. CK# Input Differential clock. Command-address/data information is input or output with respect to the crossing edges of the CK/CK# pair (Optional). DS / RWDS Input / Output Read data strobe (DS). DS is used for SEMPER™ Flash data read operations only and indicates output data valid for the HYPERBUS™ interface. During a read transaction, while CS# is LOW, DS toggles to synchronize the data output until CS# goes HIGH. Output data during read transactions is edge-aligned with DS. Read-write data strobe (RWDS): Output data during HYPERRAM™ read transactions is edge-aligned with RWDS. RWDS is an input during write transactions to function as a HYPERRAM™ data mask. DQ[7:0] Input / Output Data input/output. Command-address/data information is transferred on these DQs during read and write transactions. INT# Output (open drain) INT output (optional). When LOW, the SEMPER™ Flash de vice is indicating that an internal event has occurred. This signal is intended to be used as a system-level interrupt for the device to indicate that an on-chip event has occurred. INT# is an open-drain output. RESET# Input Hardware RESET (optional). When LOW, the SEMPER™ Flash and HYPERFLASH™ memory's will self-initialize and return to the idle state. DS/RWDS and DQ[7:0] is placed into the High-Z state when RESET# is LOW. RESET# includes a weak pull-up; if RESET# is left unconnected, it will be pulled up to the HIGH state. RSTO# Output (open drain) RSTO# output (optional). RSTO# is an open-drain output used to indicate when a POR is occurring within the SEMPER™ Flash memory and can be used as a system-level reset signal. Upon completion of the internal POR, the RSTO# signal will transition from LOW to HIGH-Z after a user-defined timeout period has elapsed. Upon transition to the HIGH-Z state, the external pull-up resistance will pull RSTO# HIGH and the device immediately is placed into the IDLE state. V CC Power supply Core power VCCQ Power supply Input/output power VSS Power supply Core ground VSSQ Power supply Input/output ground

Supplement Datasheet 6 002-31140 Rev. *B 2022-09-21 512Mb SEMPER™ Flash and 64Mb HYPERRAM™ 2.0 HYPERBUS™ interface, multi-chip package, 1.8 V/3.0 V HYPERBUS™ MCP block diagram

3 HYPERBUS™ MCP block diagram

Figure 2 HYPERBUS™ connections including optional signals Master Slave 0 SEMPERTM Flash VCC VCCQ VCC VCCQ RSTO# RSTO# CS0# CS# CK CK CK#CK# DQ[7:0] DQ[7:0] DS/RWDS DS RESET# RESET# INT#INT# CS1# CS1# CS2# CS# CK CK# DQ[7:0] RWDS RESET# VSS VSSQ VSS VSSQ Slave 1 HYPERRAMTM VCC VCCQ VSS VSSQ MCP

Supplement Datasheet 7 002-31140 Rev. *B 2022-09-21 512Mb SEMPER™ Flash and 64Mb HYPERRAM™ 2.0 HYPERBUS™ interface, multi-chip package, 1.8 V/3.0 V Physical interface 4P h y s i c a l i n t e r f a c e

4.1 HYPERBUS™ MCP — FBGA 24-ball, 5 × 5 footprint

Figure 3 24-ball FBGA, 8 × 8 mm, 5 × 5 ball footprint (top view) RSTO# CS2# RESET# INT# CK# CK VSS VCC DNU VSSQ CS1# DS/ RWDS DQ2 DNU VCCQ DQ1 DQ0 DQ3 DQ4 DQ7 DQ6 DQ5 VCCQ VSSQ B A C D E 12345 Top View Notes 1. C2 and A3 are chip select (CS#) signals 1 and 2 used for SEMPER™ Flash and HYPERRAM™ devices respectively. 2. VSS and VSSQ are internally connected.

Supplement Datasheet 8 002-31140 Rev. *B 2022-09-21 512Mb SEMPER™ Flash and 64Mb HYPERRAM™ 2.0 HYPERBUS™ interface, multi-chip package, 1.8 V/3.0 V Electrical specifications

5 Electrical specifications

The following section describes the device dependent aspects of electrical specifications.

5.1 Absolute maximum ratings

Ambient temperature with power applied: –65°C to +115°C.

5.2 DC characteristics

Only one memory may have its Chip Select active (LOW) at any point in time. For each condition below, refer to the SEMPER™ Flash and HYPERRAM™ datashee ts for the most accurate information:

• Active core read or write current will be that of the selected device plus the standby current of the non-selected device. However, the added standby current is generally not significant because it is less than 300 µA.
• Active I/O read current will be that of the selected device.
• Active clock stop current will be that of the selected device plus the standby current of the non-selected device. However, the added standby current is generally not significant because it is less than 300 µA.
• Program or erase current will be that of the SEMPER™ Flash device. Note however, that program and erase operations are long-time-frame events that extend beyond the duration of a SEMPER™ Flash Chip Select period. Thus, if the HYPERRAM™ is selected for read or write during an on going SEMPER™ Flash program or erase operation, the active current will be the sum of the SEMPER™ Flash pr ogram or erase operation and the HYPERRAM™ read or write current.
• Standby current, when neither memory is selected and no embedded flash operation is in progress, is the sum of the memory standby currents.
• Deep power down (DPD) current is the sum of the memory DPD currents.
• POR current is the sum of the memory standby currents.
• Input leakage current is the sum of the memory input leakage currents. For reference purpose, Table 3 aids in the estimation of the current consumption in these operating conditions. However, see the SEMPER™ Flash and HYPERRAM™ datasheets for the most accurate information.

Supplement Datasheet 9 002-31140 Rev. *B 2022-09-21 512Mb SEMPER™ Flash and 64Mb HYPERRAM™ 2.0 HYPERBUS™ interface, multi-chip package, 1.8 V/3.0 V Electrical specifications Table 3 3.0 V DC characteristics (CMOS compatible) Parameter Description Test conditions Min Typ [6] Max Unit ILI Input leakage current (RESET# HIGH) VIN = VSS to VCC, VCC = VCC max – – ±3.1 µAInput leakage current (RESET# LOW) VIN = VSS to VCC, VCC = VCC max – – +18.0 ILO Output leakage current VOUT = VSS to VCC, VCC = VCC max – – ±3.1 ICC1HF VCC active read current - SEMPER™ Flash reading (core current only, I/O switching current is not included) CS# = V IL, @ 166 MHz, VCC = 3.60 V – 156 173 mA CS# = VIL, @ 200 MHz, VCC = 2.00 V – 156 173 ICC1HR VCC active read current - HYPERRAM™ reading CS# = VIL, @ 166 MHz, VCC = 3.60 V –1 5 2 8 CS# = VIL, @ 200 MHz, VCC = 2.00 V –1 5 2 5 ICC2HR VCC active write current - HYPERRAM™ writing CS# = VIL, @ 166 MHz, VCC = 3.60 V –1 5 2 8 CS# = VIL, @ 200 MHz, VCC = 2.00 V –1 5 2 5 ICC1HFHR VCC active program / erase current - SEMPER™ Flash embedded operation plus HYPERRAM™ reading [4] CS# = VIL, @ 166 MHz, VCC = 3.60 V –6 5 9 2 CS# = VIL, @ 200 MHz, VCC = 2.00 V –6 5 9 1 ICC2HFHR VCC active write current - SEMPER™ Flash embedded operation plus HYPERRAM™ writing [4] CS# = VIL, @ 100 MHz, VCC = 3.60 V – 75 135 CS# = VIL, @ 166 MHz, VCC = 2.00 V – 75 160 ICC3P VCC active program current[3, 4] (512T/01GT) VCC = VCC max – 50 55/66 ICC3E VCC active erase current[3, 4] (512T/01GT) VCC = VCC max – 50 55/66 ICC4I VCC standby current (512T/01GT) CS#, RESET# = VCC, VCC = 2.00 V, 85°C – 91 333/333 µA CS#, RESET# = VCC, VCC = 2.00 V, 105°C – 91 518/550 VCC standby current (512T/01GT) CS#, RESET# = VCC, VCC = 3.60 V, 85°C – 104 376/376 CS#, RESET# = VCC, VCC = 3.60 V, 105°C – 104 548/548 Notes 3. ICC active while embedded algorithm (EA) is in progress. 4. Not 100% tested. 5. Active Clock Stop mode enables the lower power mode when the CK signals remain stable for t ACC + 30 ns. 6. Typical ICC values are measured at tAI = 25°C and VCC = VCCQ = 1.8 V/3.0 V (not applicable to IDPD for 85°C and 105°C). 7. Current specification includes both the SEMPER Flash and HYPERRAM™ die current consumption per the mode of operation of each die.

Supplement Datasheet 10 002-31140 Rev. *B 2022-09-21 512Mb SEMPER™ Flash and 64Mb HYPERRAM™ 2.0 HYPERBUS™ interface, multi-chip package, 1.8 V/3.0 V Electrical specifications ICC6 Active clock Stop mode[5] VIH = VCC, VIL= VSS, VCC = 2.00 V/3.6 V, 85°C –58 mAVIH = VCC, VIL= VSS, VCC = 2.00 V/3.6 V, 105°C –8 1 2 ICC7 VCC current during power-up (POR) CS# = X, VCC = VCC max – – 115 IDPD DPD current SEMPER™ Flash + HYPERRAM™ in DPD (512T / 01GT) CS#, RESET#, V µA CS#, RESET#, VCC = 2.0 V, 105°C – – 30/58 CS#, RESET#, CS#, RESET#, VCC = 3.6 V, 105°C – – 33/61 IHS Hybrid sleep current HYPERRAM™ SEMPER™ Flash in DPD CS# = V CC, VCC = 2.0 V; Full array – 27 218 CS# = VCC, VCC = 3.6 V; Full array – 37 318 Hybrid sleep current HYPERRAM™ SEMPER™ Flash in DPD CS# = V CC, VCC = 2.0 V; Full array – 27 248 CS# = VCC, VCC = 3.6 V; Full array – 37 348 Table 3 3.0 V DC characteristics (CMOS compatible) (Continued) Parameter Description Test conditions Min Typ [6] Max Unit Notes 3. ICC active while embedded algorithm (EA) is in progress. 4. Not 100% tested. 5. Active Clock Stop mode enables the lower power mode when the CK signals remain stable for t ACC + 30 ns. 6. Typical ICC values are measured at tAI = 25°C and VCC = VCCQ = 1.8 V/3.0 V (not applicable to IDPD for 85°C and 105°C). 7. Current specification includes both the SEMPER Flash and HYPERRAM™ die current consumption per the mode of operation of each die.

Supplement Datasheet 11 002-31140 Rev. *B 2022-09-21 512Mb SEMPER™ Flash and 64Mb HYPERRAM™ 2.0 HYPERBUS™ interface, multi-chip package, 1.8 V/3.0 V Electrical specifications

5.3 Capacitance characteristics

5.4 Thermal resistance

Table 4 1.8 V/3.0 V capacitive characteristics Description Parameter Min Max Unit Input capacitance (CK, CK#)[8-10] CI 6.0 10.5 pF Output capacitance (DS/RWDS)[8-10] CO 9.5 10.5 I/O pin capacitance (DQx)[8-10] CIO 9.5 10.5 I/O pin capacitance delta (DQx)[8-10] CIOD – 0.25 INT#, RSTO# pin capacitance, RST#[8-10] COP 9.5 10.5 Notes 8. These values are guaranteed by design and are tested on a sample basis only. 9. Pin capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer. V CC, VCCQ are applied and all other pins (except the pin under test) floating. DQs should be in the HIGH-Z state. 10.The capacitance values for the CK, CK#, RWDS and DQx pins must have similar capacitance values to allow for signal propagation time matching in the system. The capacitance value for CS# is not as critical because there are no critical timings between CS# going active (LOW) and data being presented on the DQs bus. Table 5 Thermal resistance Parameter Description Test condition 24-ball BGA Unit Theta JA Thermal resistance (Junction to ambient) Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA/JESD51. With Still Air (0 m/s) 53.6 °C/WTheta JB Thermal resistance (Junction to board) 28.3 Theta JC Thermal resistance (Junction to case) 16.2

Supplement Datasheet 12 002-31140 Rev. *B 2022-09-21 512Mb SEMPER™ Flash and 64Mb HYPERRAM™ 2.0 HYPERBUS™ interface, multi-chip package, 1.8 V/3.0 V Package diagram

6 Package diagram

Figure 4 24-ball BGA (8 × 8 × 1.2 mm) package outline, 002-24801 N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW "SD" OR "SE" = 0. POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. "e" REPRESENTS THE SOLDER BALL GRID PITCH. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION9. NOTES: ALL DIMENSIONS ARE IN MILLIMETERS. SD b eD eE ME N 0.35

0.00 BSC

1.00 BSC

0.40 0.45 MD E D A A1 0.20

4.00 BSC

8.00 BSC

• 1.20 SE 0.00 BSC DIMENSIONS SYMBOL MIN. NOM. MAX. OR OTHER MEANS. JEDEC SPECIFICATION NO. REF: N/A10. 002-24801 *A

Supplement Datasheet 13 002-31140 Rev. *B 2022-09-21 512Mb SEMPER™ Flash and 64Mb HYPERRAM™ 2.0 HYPERBUS™ interface, multi-chip package, 1.8 V/3.0 V

Ordering information

7 Ordering information

7.1 Ordering code definition

The ordering part number is formed by a valid combination of the following: HC0 B 0T 00I512S76HL Packing type 0 = Tray 3 = 13” tape and reel SEMPER™ flash device technology: T = 45-nm MIRRORBIT™ Process technology Device family: S76HL = Infineon® HYPERBUS™ MCP, 3.0V-only S76HS = Infineon® HYPERBUS™ MCP, 1.8V-only SEMPER™ flash density: 512 = 512Mb Package materials: H = Low-Halogen, Lead (Pb)-free Model number (additional ordering options): 00 = 166 MHz 01 = 200 MHz Temperature range: I = Industrial (–40°C to +85°C) V = Industrial plus (–40°C to +105°C) A = Automotive, AEC-Q100 grade 3 (–40°C to +85°C) B = Automotive, AEC-Q100 grade 2 (–40°C to +105°C) Package type: B = 24-ball FBGA 8 x 8 x 1.2 mm package HYPERRAM™ density: C0 = 64Mb

Supplement Datasheet 14 002-31140 Rev. *B 2022-09-21 512Mb SEMPER™ Flash and 64Mb HYPERRAM™ 2.0 HYPERBUS™ interface, multi-chip package, 1.8 V/3.0 V

7.2 Valid combinations — Standard

Table 6 lists configurations planned to be available in volume. The table will be updated as new combinations are released. Contact your local sales representative to confirm availability of specific combinations and to check on newly released combinations.

7.3 Valid combinations — Automotive grade / AEC-Q100

Table 8 lists configurations that are Automotive grade / AEC-Q100 qualified and are planned to be available in volume. The table will be updated as new combinations are released. Consult your local sales representative to confirm availability of specific combinations and to check on newly released combinations. Production part approval process (PPAP) support is only provided for AEC-Q100 grade products. Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade products in combination with PPAP . Non–AEC-Q100 grade products are not manufactured or documented in full compliance with ISO/TS-16949 requirements. AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require ISO/TS-16949 compliance. Table 6 Valid combinations — Standard (Contact Sales) Device number HYPERRAM™ density Package and material Temperature range Model number Packing type Ordering part number (x = Packing type) Package marking S76HL512T C0 BH I 00 0, 3 S76HL512TC0BHI00x 6HL512TC0I00 V S76HL512TC0BHV00x 6HL512TC0V00 S76HS512T C0 BH I 01 0, 3 S76HS512TC0BHI01x 6HS512TC0I01 V S76HS512TC0BHV01x 6HS512TC0V01 Table 7 Valid combinations — Automotive grade / AEC-Q100 (In Production) Device number HYPERRAM™ density Package and material Temperature range Model number Packing type Ordering part number (x = Packing type) Package marking S76HL512T C0 BH B 00 0, 3 S76HL512TC0BHB00x 6HL512TC0B00 S76HS512T C0 BH B 01 0, 3 S76HS512TC0BHB01x 6HS512TC0B01 Table 8 Valid combinations — Automotive grade / AEC-Q100 (Contact Sales) Device number HYPERRAM™ density Package and material Temperature range Model number Packing type Ordering part number (x = Packing type) Package marking S76HL512T C0 BH A 00 0, 3 S76HL512TC0BHA00x 6HL512TC0A00 S76HS512T C0 BH A 01 0, 3 S76HS512TC0BHA01x 6HS512TC0A01

Supplement Datasheet 15 002-31140 Rev. *B 2022-09-21 512Mb SEMPER™ Flash and 64Mb HYPERRAM™ 2.0 HYPERBUS™ interface, multi-chip package, 1.8 V/3.0 V

Revision history

revision Date Description of changes ** 2021-02-05 Initial release. *A 2021-11-18 Updated HYPERBUS™ MCP signal description : Updated Figure 1. Updated Table 2: Updated Description for CK#. Updated HYPERBUS™ MCP block diagram : Updated Figure 2. Updated Electrical specifications: Updated DC characteristics: Updated Table 3: Updated Description for ILI. Updated Max. value for ICC2HR and IHS. Added Thermal resistance. Updated Package diagram: spec 002-24801 – Changed revision from ** to *A. *B 2022-09-21 Changed status from “Preliminary Supplement” to “Supplement” . Updated Document Title to read as “S76HS512TC0, S76HL512TC0, 512Mb SEMPER™ Flash and 64Mb HYPERR AM™ 2.0 HYPERBUS™ interface, multi-chip package, 1.8 V/3.0 V” . Remove 1Gb SEMPER™ Flash related information in all instances across the document. Updated General description: Updated Table 1. Updated Electrical specifications: Updated DC characteristics: Updated Table 3. Updated Ordering information: Updated Valid combinations — Standard : Updated Table 6. Updated Valid combinations — Automotive grade / AEC-Q100: Added Table 7. Updated Table 8. Updated to new template.

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