S75WS256NDFBFWPA

S75WS256NXX SPANSION | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1 Product Selector Guide
• 2 Ordering Information
• 3 Input/Output Descriptions and Logic Symbol
• 4 MCP Block Diagram
• 5 Connection Diagrams/Physical Dimensions
• 5.1 Special Handling Instructions for FBGA Package
• 5.2 Connection Diagram – Cellular Ram-Based Pinout, 9 x 12 mm
• 5.3 Physical Dimensions
• 5.3.1 Physical Dimensions – xxx084 – Fine Pi tch Ball Grid Array 9 x 12 mm
• 5.4 Look-Ahead Connection Diagram
• 6 Additional Resources
• 7 Product Overview
• 7.1 Memory Map
• 8 Device Operations
• 8.1 Device Operation Table
• 8.2 Asynchronous Read
• 8.3 Synchronous (Burst) Read Mode and Configuration Register
• 8.3.1 Continuous Burst Read Mode
• 8.3.4 Configuration Register
• 8.4 Autoselect
• 8.5 Program/Erase Operations
• 8.5.1 Single Word Programming
• 8.5.2 Write Buffer Programming
• 8.5.3 Sector Erase
• 8.5.4 Chip Erase Command Sequence
• 8.5.5 Erase Suspend/Erase Resume Commands
• 8.5.6 Program Suspend/Program Resume Commands
• 8.5.7 Accelerated Program/Chip Erase
• 8.5.8 Unlock Bypass
• 8.5.9 Write Operation Status
• 8.6 Simultaneous Read/Write
• 8.7 Writing Commands/Command Sequences
• 8.8 Handshaking
• 8.9 Hardware Reset
• 8.10 Software Reset
• 9 Advanced Sector Protection/Unprotection
• 9.1 Lock Register
• 9.2 Persistent Protection Bits
• 9.3 Dynamic Protection Bits
• 9.4 Persistent Protection Bit Lock Bit
• 9.5 Password Protection Method
• 9.6 Advanced Sector Protection Software Examples
• 9.7 Hardware Data Protection Methods
• 9.7.1 WP# Method
• 9.7.2 ACC Method
• 9.7.3 Low V CC Write Inhibit
• 9.7.4 Write Pulse Glitch Protection
• 9.7.5 Power-Up Write Inhibit

Publication Number S75WS-N-00 Revision A Amendment 0 Issue Date February 17, 2005 S75WS256Nxx Based MCPs Stacked Multi-Chip Product (MCP) 256 Megabit (16M x 16-bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory with

128 Mb (8M x 16-Bit) CellularRAM and

512 Mb (32M x 16-bit) Data Storage

Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.

S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005 Advance Information This page intentionally left blank.

Publication Number S75WS-N-00 Revision A Amendment 0 Issue Date February 17, 2005 General Description The S75WS-N Series is a product line of stacked Multi-Chip Product (MCP) packages and consists of the following items: „ One or more S29WSxxxN code Flash „ CellularRAM „ One or more S29RS-N data storage Flash The products covered by this document are listed in the table below: Distinctive Characteristics MCP Features „ Power supply voltage of 1.7 V to 1.95 V „ High Performance — 54 MHz, 66 MHz „ Packages —9 x 1 2 mm 84 ball FBGA „ Operating Temperature — Wireless, –25°C to +85°C S75WS256Nxx Based MCPs Stacked Multi-Chip Product (MCP) 256 Megabit (16M x 16-bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory with

256 Mb 128 Mb 512 Mb

S75WS256NDF „„ „

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Notice On Data Sheet Designations Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, includ- ing development, qualification, initial production , and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their de- sign. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion LLC is developing one or more spe- cific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the prod- uct may discontinue. Spansion LLC therefore pl aces the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without con- tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initia l production, and the subsequent phases in the manufacturing process that occur before full prod uction is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these as- pects of production under consideration. Span sion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifica- tions due to changes in technical specifications.” Combination Some data sheets will contain a combination of products with different designations (Advance In- formation, Preliminary, or Full Production). This type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designat ion is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incor- rect specification. Spansion LLC applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that sub- sequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.

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February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 5 Advance Information

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February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 7 Advance Information Ta bl e s

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February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 11 Advance Information

1 Product Selector Guide

b Note: 0 (Protected), 1 (Unprotected [Default State]) Device Model Numbers MCP Configuration Code Flash Density (Mb) RAM Density (Mb) Data Storage Flash Density (Mb/Gb) Flash Speed (MHz) pSRAM Speed (MHz) DYB Power-Up State (See Note) pSRAM (Cellular RAM) Supplier Package 84 ball FBGA (mm) Code Flash Code pSRAM (Mb) Data Storage Flash S75WS256NDF MA WS256N 128 RS512N 256 128 512 Mb 54 54 29 x 1 2 PA 1 MB 66 66 PB 1

12 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

2 Ordering Information

The ordering part number is formed by a valid combination of the following: Package Marking Note: The BGA package marking omits the leading S75 and packing type designator from the ordering part number. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S75WS 256 N D F BA W M A RAM Supplier; Speed Combination A = Cellular RAM2, 54 MHz B = Cellular RAM2, 66 MHz Package Dimensions and Ball Count; DYB Power Up; Flash Device Family (Data Storage) M = 1.4 mm, 9 x 12, 84 ball; 0; RS P = 1.4 mm, 9 x 12, 84 ball; 1; RS Temperature Range W = Wireless (–25°C to +85°C) Package Type And Material BA = Very Thin Fine-Pitch Ball Grid Array (BGA), Lead (Pb)-free Compliant Package BF = Very Thin Fine-Pitch Ball Grid Array (BGA), Lead (Pb)-free Package Data Storage Density F = 512 Mb Code Flash Density D = 128 Mb Process Technology N = 110 nm, Mirror Bit Technology Flash Density 256 = 256 Mb Device Family S75WS = Multi-chip Product (MCP) 1.8-volt Burst Mode Flash Memory, RAM, and NAND Data Storage T able 2.1 MCP Configurations and Valid Combinations Valid Combinations S75WS256N D F BA, BF W M, P A, B

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 13 Advance Information

3 Input/Output Descri ptions and Logic Symbol

Table 3.1 identifies the input and output package connections provided on the device. T able 3.1 Input/Output Descriptions Symbol Description Amax – A0 Address Inputs (Common) DQ15 - DQ0 Data Inputs/Outputs OE# Output Enable input WE# Write Enable input VSS Ground NC No Connect; not connected internally. RDY Ready output. Indicates the status of the Burst read. (Flash) CLK Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Should be at VIL or VIH while in asynchronous mode. (Common) AVD# Address Valid input. Indicates to device that the valid address is present on the address inputs. (Flash) F-RST# Hardware reset input. F-WP# Hardware write protect input. At VIL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. F-ACC Accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. R-CE# Chip-enable input for pSRAM F-CE# Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode. F1-CE# Chip-enable input for Flash 1. F2-CE# Chip-enable input for Flash 2. F3-CE# Chip-enable input for Flash 3. R-CRE Control Register Enable . (pSRAM – CellularRAM only) F-V CC Flash 1.8 Volt-only single power supply. R-VCC pSRAM Power Supply. R-UB# Upper Byte Control. (pSRAM) R-LB# Lower Byte Control . Note: R-CRE is only present in CellularRAM-compatible pSRAM. DQ15 – DQ0 16Amax – A0 CE# F-WP F-ACC F-CE# R-CE# OE# WE# F-RST# AVD# R-UB# R-LB# R-CRE RDY CLK (See Note)

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4 MCP Block Diagram

Notes: 1. CREs is only present in CellularRAM-compatible pSRAM. 2. CE#f1, CE#f2, and CE#f3 are the chip enable pins for the first, second, and third Flash devices, respectively. CE#f3 may not be needed depending on the package. 3. If necessary. WP# ACC CE# OE# WE# RESET# AVD# DQ15 – DQ0 RDY VCC Flash-only Address Shared Address CLK WP# ACC CE#f1 OE# WE# RESET# AVD# VCCf CE# WE# OE# UB# LB# AVD# CRE VCC VCCs CE#s I/O15 – I/O0 DQ15 – DQ0 VSSQ RDY VSS VCCQ VID Flash 2 Flash 3 Amax – A0 CLK UB#s LB#s CREs Amax – A0 CLK CE#f3 CE#f2 Flash 1 pSRAM (Note 3) (Note 2)— (Note 2)— (Note 2)—

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 15 Advance Information

5 Connection Diagrams/Physical Dimensions

This section contains the I/O designations and package specifications for the S75WS.

5.1 Special Handling Instruc tions for FBGA Package

Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning meth- ods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.

5.2 Connection Diagram – Cellular Ram-Based Pinout, 9 x 12 mm

Figure 5.1 Connection Diagram – Cellular Ram-Based 84-ball Fine-Pitch Ball Grid Array

5.3 Physical Dimensions

5.3.1 Physical Dimensions – xxx084 – Fi ne Pitch Ball Grid Array 9 x 12 mm

Legend: MirrorBit™ Data Flash Only X RAM Only X Flash Shared Only XXX All Shared XXX DNU XXX RFU XXX X Code Flash Only A10 DNU DNU ADV# RFU B3 B4 CLK F-VCC RFU RFU RFU B9B9 RFU F1-WP# C3C3C3C3 R-LB# WE# A11 F2-CE# F-ACC C5C5C5C5 R-UB# RFU A19 D7D7D7D7 A12 D8D8D8D8 A15 D9D9D9D9 F-RST# D5D5D5D5 A18 A20 A13 A21 RDY A17 A23 F5F5F5F5 A10 A14 A22 RFU VSS DQ1 RFU DQ6 A24 A16 RFU F-CE# OE# DQ9 DQ4 DQ13 DQ15 R-CRE DQ3 R-CE1# DQ0 DQ10 R-VCC DQ12 DQ7 VSS F-VCC RFU DQ8 DQ2 A25 DQ5 DQ14 RFU DQ11 RFU RFU RFU RFU RFU RFU RFU F-VCC

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5.4 Look-Ahead Connection Diagram

Look Ahead Pinout – 1.8 V only x 16NOR + x16pSRAM + x16MirrorBit Data Notes: 1. F1 and F2 denote XIP/Co de Flash, while F3 and F4 denote Data/Companion Flash 2. In addition to being defined as F2-CE#, Ball C5 can also be assigned as F1-CE2# for code that has two chip enable signals. Figure 5.2 Look Ahead Pinout – 1.8 V only x 16NOR + x16pSRAM + x16MirrorBit Data To provide customers with a migration path to higher densities, as well as the option to stack more die in a package, Spansion has prepared a standard pinout that supports: „ NOR Flash and SRAM densities up to 4 Gigabits „ NOR Flash and PSRAM densities up to 4 Gigabits „ NOR Flash and PSRAM and DATA STORAGE densities up to 4 Gigabits The signal locations of the resultant MCP device are shown above. Note that for different densi- ties, the actual package outline may vary. However, any pinout in any MCP will be a subset of the pinout above. Legend: xRAM Shared pSRAM Only Flash/xRAM Shared Flash/Data Shared RFU (Reserved for Future Use) Code Flash Only X MirrorBit Data Only XXX X XXX XXX X XXX RFU B1 B10 RFU RFU RFU F-DQS0 N1N1 F-DQS1 N10 RFU RFU RFU RFU P10P2 RFU RFU RFU RFU A10 RFU RFU A7 ACC R-LB# D4 D7 A8WP# D2 D8 A11 F3-CE# D9D6 WE# F3F3 RDY/WAIT# F4F4 A18 F7F7 F2F2 F8F8 A13 F9F9 A21 F6F6 A20 OE# DQ3 DQ9 DQ13F1-CE# J2 J8 DQ15 R-CRE or R-MRS J9J6 DQ4 L3L3 DQ8 L5L5 DQ11 L4L4 DQ2 L7L7 DQ5R-VCC L2 L8L8 DQ14 WP# L9L6L6 A25 VSS F2-CE# C5C4 CLK F-CLK# AVD# R-OE# F2-OE# F-VCC C6C6C6C6 A6 F-RST# R-UB# D4 E7 A19 A12 A15R1-CE2 G3G3 R2-CE1 A17 G4 G4 A10 G7G7 G2G2 A14 G8G8 A22 G9G9 A23 G6G6 H3H3 VSS R2-VCC H5H4H4 DQ1 DQ6 H2H2 A24 A16R2-CE2 DQ0 K3K3 F-VCC DQ10 K4K4 K7K7 DQ12R1-CE1# DQ7 K8K8 K9K9 VSSR1-VCC A26 F-VCC M5M4 VSS R-VCCQ M7M2 A27 F-VCCQ R-CLK# F4-CE#

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 17 Advance Information In some cases, there may be outrigger balls in locations outside the grid shown above. In such cases, the user is recommended to treat these as RFUs, and not connect them to any other signal. In case of any further inquiries about the above look-ahead pinout, please refer to the application note on this subject, or contact your Spansion or Fujitsu sales office.

Publication Number S75WS-N-00 Revision A Amendment 0 Issue Date February 17, 2005 General Description The Spansion S29WS256/128/064N are Mirrorbit™ Flash products fabricated on 110 nm process technology. These burst mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using separate data and address pins. These pr oducts can operate up to 80 MHz and use a single V CC of 1.7 V to 1.95 V that makes them ideal for today’s demanding wireless applications requiring higher density, better per- formance and lowered power consumption. Distinctive Characteristics „ Single 1.8 V read/program/erase (1.70–1.95 V) „ 110 nm MirrorBit™ Technology „ Simultaneous Read/Write operation with zero latency „ 32-word Write Buffer „ Sixteen-bank architecture consisting of 16/8/4 Mwords for WS256N/128N/064N, respectively „ Four 16 Kword sectors at both top and bottom of memory array „ 254/126/62 64 Kword sectors (WS256N/128N/ 064N) „ Programmable burst read modes — Linear for 32, 16 or 8 words linear read with or without wrap-around — Continuous sequential read mode „ Secured Silicon Sector region consisting of 128 words each for factory and customer „ 20-year data retention (typical) „ Cycling Endurance: 100,000 cycles per sector (typical) „ RDY output indicates data available to system „ Command set compatible with JEDEC (42.4) standard „ Hardware (WP#) protection of top and bottom sectors „ Dual boot sector configuration (top and bottom) „ Offered Packages — WS064N: 80-ball FBGA (7 mm x 9 mm) — WS256N/128N: 84-ball FBGA (8 mm x 11.6 mm) „ Low VCC write inhibit „ Persistent and Password methods of Advanced Sector Protection „ Write operation status bits indicate program and erase operation completion „ Suspend and Resume commands for Program and Erase operations „ Unlock Bypass program command to reduce programming time „ Synchronous or Asynchronous program operation, independent of burst control register settings „ ACC input pin to reduce factory programming time „ Support for Common Flash Interface (CFI) „ Industrial Temperature range (contact factory) Performance Characteristics S75WS-N MirrorBit™ Flash Family S29WS256N, S29WS128N, S29WS064N 256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory Data Sheet PRELIMINARY Read Access Times Speed Option (MHz) 80 66 54 Max. Synch. Latency, ns (tIACC) 80 80 80 Max. Synch. Burst Access, ns (tBACC) 9 11.2 13.5 Max. Asynch. Access Time, ns (tACC) 80 80 80 Max CE# Access Time, ns (tCE) 80 80 80 Max OE# Access Time, ns (tOE) 13.5 13.5 13.5 Current Consumption (typical values) Continuous Burst Read @ 66 MHz 35 mA Simultaneous Operation (asynchronous) 50 mA Program (asynchronous) 19 mA Erase (asynchronous) 19 mA Standby Mode (asynchronous) 20 µA Typical Program & Erase Times Single Word Programming 40 µs Effective Write Buffer Programming (VCC) Per Word 9.4 µs Effective Write Buffer Programming (VACC) Per Word 6 µs Sector Erase (16 Kword Sector) 150 ms Sector Erase (64 Kword Sector) 600 ms

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 19 Advance Information

6 Additional Resources

Visit www.amd.com and www.fujitsu.com to obtain the following related documents: Application Notes „ Using the Operation Status Bits in AMD Devices „ Understanding Burst Mode Flash Memory Devices „ Simultaneous Read/Write vs. Erase Suspend/Resume „ MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read „ Design-In Scalable Wireless Solutions with Spansion Products „ Common Flash Interface Version 1.4 Vendor Specific Extensions Specification Bulletins Contact your local sales office for details. Drivers and Software Support „ Spansion low-level drivers „ Enhanced Flash drivers „ Flash file system CAD Modeling Support „ VHDL and Verilog „ IBIS „ ORCAD Technical Support Contact your local sales office or contact Spansion LLC directly for additional technical support: Email US and Canada: HW.support@amd.com Asia Pacific: asia.support@amd.com Europe, Middle East, and Africa Japan: http://edevice.fujitsu.com/jp/support/tech/#b7 Frequently Asked Questions (FAQ) http://ask.amd.com/ http://edevice.fujitsu.com/jp/support/tech/#b7 Phone US: (408) 749-5703 Japan (03) 5322-3324 Spansion LLC Locations 915 DeGuigne Drive, P.O. Box 3453 Sunnyvale, CA 94088-3453, USA Telephone: 408-962-2500 or 1-866-SPANSION Spansion Japan Limited 4-33-4 Nishi Shinjuku, Shinjuku-ku Tokyo, 160-0023 Telephone: +81-3-5302-2200 Facsimile: +81-3-5302-2674 http://www.spansion.com

20 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

7 Product Overview

The S29WS-N family consists of 256, 128 and 64Mbit, 1.8 volts-only, simultaneous read/write burst mode Flash device optimized for today’s wireless designs that demand a large storage array, rich functionality, and low power consumption. These devices are organized in 16, 8 or 4 Mwords of 16 bits each and are capable of continuous, synchronous (burst) read or linear read (8-, 16-, or 32-word aligned group) with or without wrap around. These products also offer single word programming or a 32-word buffer for programming with program/erase and suspend functionality. Additional features include: „ Advanced Sector Protection methods for protecting sectors as required „ 256 words of Secured Silicon area for storing customer and factory secured information. The Secured Silicon Sector is One Time Programmable.

7.1 Memory Map

The S29WS256/128/064N Mbit devices consist of 16 banks organized as shown in Tables Table 7.1, Table 7.2, and Table 7.3. Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA005–SA017) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh. T able 7.1 S29WS256N Sector & Memory Address Map Bank Size Sector Count Sector Size (KB) Bank Sector/ Sector Range Address Range Notes 2 MB 4 32 SA000 000000h–003FFFh Contains four smaller sectors at bottom of addressable memory. SA001 004000h–007FFFh SA002 008000h–00BFFFh SA003 00C000h–00FFFFh 15 128 SA004 to SA018 010000h–01FFFFh to 0F0000h–0FFFFFh All 128 KB sectors. Pattern for sector address range is xx0000h–xxFFFFh. (see note)

2 MB 16 128 1 SA019 to SA034 100000h–10FFFFh to 1F0000h–1FFFFFh

2 MB 16 128 2 SA035 to SA050 200000h–20FFFFh to 2F0000h–2FFFFFh

2 MB 16 128 3 SA051 to SA066 300000h–30FFFFh to 3F0000h–3FFFFFh

2 MB 16 128 4 SA067 to SA082 400000h–40FFFFh to 4F0000h–4FFFFFh

2 MB 16 128 5 SA083 to SA098 500000h–50FFFFh to 5F0000h–5FFFFFh

2 MB 16 128 6 SA099 to SA114 600000h–60FFFFh to 6F0000h–6FFFFFh

2 MB 16 128 7 SA115 to SA130 700000h–70FFFFh to 7F0000h–7FFFFFh

2 MB 16 128 8 SA131 to SA146 800000h–80FFFFh to 8F0000h–8FFFFFh

2 MB 16 128 9 SA147 to SA162 900000h–90FFFFh to 9F0000h–9FFFFFh

2 MB 16 128 10 SA163 to SA178 A00000h–A0FFFFh to AF0000h–AFFFFFh

2 MB 16 128 11 SA179 to SA194 B00000h–B0FFFFh to BF0000h–BFFFFFh

2 MB 16 128 12 SA195 to SA210 C00000h–C0FFFFh to CF0000h–CFFFFFh

2 MB 16 128 13 SA211 to SA226 D00000h–D0FFFFh to DF0000h–DFFFFFh

2 MB 16 128 14 SA227 to SA242 E00000h–E0FFFFh to EF0000h–EFFFFFh

SA243 to SA257 F00000h–F0FFFFh to FE0000h–FEFFFFh 4 32 SA258 FF0000h–FF3FFFh Contains four smaller sectors at top of addressable memory. SA259 FF4000h–FF7FFFh SA260 FF8000h–FFBFFFh SA261 FFC000h–FFFFFFh

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 21 Advance Information Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA005–SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh. T able 7.2 S29WS128N Sector & Memory Address Map Bank Size Sector Count Sector Size (KB) Bank Sector/ Sector Range Address Range Notes 1 MB SA000 000000h–003FFFh Contains four smaller sectors at bottom of addressable memory.

32 SA001 004000h–007FFFh

32 SA002 008000h–00BFFFh

32 SA003 00C000h–00FFFFh

7 128 SA004 to SA010 010000h–01FFFFh to 070000h–07FFFFh All 128 KB sectors. Pattern for sector address range is xx0000h–xxFFFFh. (See Note)

1 MB 8 128 1 SA011 to SA018 080000h–08FFFFh to 0F0000h–0FFFFFh

1 MB 8 128 2 SA019 to SA026 100000h–10FFFFh to 170000h–17FFFFh

1 MB 8 128 3 SA027 to SA034 180000h–18FFFFh to 1F0000h–1FFFFFh

1 MB 8 128 4 SA035 to SA042 200000h–20FFFFh to 270000h–27FFFFh

1 MB 8 128 5 SA043 to SA050 280000h–28FFFFh to 2F0000h–2FFFFFh

1 MB 8 128 6 SA051 to SA058 300000h–30FFFFh to 370000h–37FFFFh

1 MB 8 128 7 SA059 to SA066 380000h–38FFFFh to 3F0000h–3FFFFFh

1 MB 8 128 8 SA067 to SA074 400000h–40FFFFh to 470000h–47FFFFh

1 MB 8 128 9 SA075 to SA082 480000h–48FFFFh to 4F0000h–4FFFFFh

1 MB 8 128 10 SA083 to SA090 500000h–50FFFFh to 570000h–57FFFFh

1 MB 8 128 11 SA091 to SA098 580000h–58FFFFh to 5F0000h–5FFFFFh

1 MB 8 128 12 SA099 to SA106 600000h–60FFFFh to 670000h–67FFFFh

1 MB 8 128 13 SA107 to SA114 680000h–68FFFFh to 6F0000h–6FFFFFh

1 MB 8 128 14 SA115 to SA122 700000h–70FFFFh to 770000h–77FFFFh

SA123 to SA129 780000h–78FFFFh to 7E0000h–7EFFFFh

32 SA130 7F0000h–7F3FFFh

Contains four smaller sectors at top of addressable memory.

32 SA131 7F4000h–7F7FFFh

32 SA132 7F8000h–7FBFFFh

32 SA133 7FC000h–7FFFFFh

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Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA008–SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh. T able 7.3 S29WS064N Sector & Memory Address Map Bank Size Sector Count Sector Size (KB) Bank Sector/ Sector Range Address Range Notes 0.5 MB 4 32 SA000 000000h–003FFFh Contains four smaller sectors at bottom of addressable memory. SA001 004000h–007FFFh SA002 008000h–00BFFFh SA003 00C000h–00FFFFh 3 128 SA004 010000h–01FFFFh All 128 KB sectors. Pattern for sector address range is xx0000h–xxFFFFh. (see note) SA005 020000h–02FFFFh SA006 030000h–03FFFFh

0.5 MB 4 128 1 SA007–SA010 040000h–04FFFFh to 070000h–07FFFFh

0.5 MB 4 128 2 SA011–SA014 080000h–08FFFFh to 0B0000h–0BFFFFh

0.5 MB 4 128 3 SA015–SA018 0C0000h–0CFFFFh to 0F0000h–0FFFFFh

0.5 MB 4 128 4 SA019–SA022 100000h–10FFFFh to 130000h–13FFFFh

0.5 MB 4 128 5 SA023–SA026 140000h–14FFFFh to 170000h–17FFFFh

0.5 MB 4 128 6 SA027–SA030 180000h–18FFFFh to 1B0000h–1BFFFFh

0.5 MB 4 128 7 SA031–SA034 1C0000h–1CFFFFh to 1F0000h–1FFFFFh

0.5 MB 4 128 8 SA035–SA038 200000h–20FFFFh to 230000h–23FFFFh

0.5 MB 4 128 9 SA039–SA042 240000h–24FFFFh to 270000h–27FFFFh

0.5 MB 4 128 10 SA043–SA046 280000h–28FFFFh to 2B0000h–2BFFFFh

0.5 MB 4 128 11 SA047–SA050 2C0000h–2CFFFFh to 2F0000h–2FFFFFh

0.5 MB 4 128 12 SA051–SA054 300000h–30FFFFh to 330000h–33FFFFh

0.5 MB 4 128 13 SA055–SA058 340000h–34FFFFh to 370000h–37FFFFh

0.5 MB 4 128 14 SA059–SA062 380000h–38FFFFh to 3B0000h–3BFFFFh

0.5 MB 3 128 SA063 3C0000h–3CFFFFh SA064 3D0000h–3DFFFFh SA065 3E0000h–3EFFFFh 4 32 SA066 3F0000h–3F3FFFh Contains four smaller sectors a t top of addressable memory. SA067 3F4000h–3F7FFFh SA068 3F8000h–3FBFFFh SA069 3FC000h–3FFFFFh

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 23 Advance Information

8 Device Operations

This section describes the read, program, erase, simultaneous read/write operations, handshak- ing, and reset features of the Flash devices. Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers (see Table 13.1 and Table 13.2). The command register itself does not occupy any addressable memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute the com- mand. The contents of the register serve as in put to the internal stat e machine and the state machine outputs dictate the function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command to return the device to the reading array data mode.

8.1 Device Operation T able

The device must be setup appropriately for each operation. Table 8.1 describes the required state of each control pin for any particular operation. Legend: L = Logic 0, H = Logic 1, X = Don’t Care, I/O = Input/Output.

8.2 Asynchronous Read

All memories require access time to output array data. In an asynchronous read operation, data is read from one memory location at a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive asyn- chronously with the address on its inputs. The device defaults to reading array data asynchronously after device power-up or hardware re- set. Asynchronous read requires that the CLK signal remain at V IL during the entire memory read operation. To read data from the memory array, the system must first assert a valid address on Amax–A0, while driving AVD# and CE# to VIL. WE# must remain at VIH. The rising edge of AVD# latches the address. The OE# signal must be driven to VIL, once AVD# has been driven to VIH. Data is output on A/DQ15-A/DQ0 pins after the access time (t OE) has elapsed from the falling edge of OE#. Ta bl e 8 . 1 D ev i c e O p er a t i on s Operation CE# OE# WE# Addresses DQ15–0 RESET# CLK AVD# Asynchronous Read - Addresses Latched L L H Addr In Data Out H X Asynchronous Read - Addresses Steady State L L H Addr In Data Out H X L Asynchronous Write L H L Addr In I/O H X L Synchronous Write L H L Addr In I/O H Standby (CE#) H X X X HIGH Z H X X Hardware Reset X X X X HIGH Z L X X Burst Read Operations (Synchronous) Load Starting Burst Address L X H Addr In X H Advance Burst to next address with appropriate Data presented on the Data Bus LL H X Burst Data Out HH Terminate current Burst read cycle H X H X HIGH Z H X Terminate current Burst read cycle via RESET# X X H X HIGH Z L X X Terminate current Burst read cycle and start new Burst read cycle LX H A d d r I n I / O H

24 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

8.3 Synchronous (Burst) Read Mode and Configuration Register

When a series of adjacent addresses needs to be read from the device (in order from lowest to highest address), the synchronous (or burst read) mode can be used to significantly reduce the overall time needed for the device to output array data. After an initial access time required for the data from the first address location, subsequent data is output synchronized to a clock input provided by the system. The device offers both continuous and linear me thods of burst read operation, which are dis- Since the device defaults to asynchronous read mode after power-up or a hardware reset, the configuration register must be set to enable the burst read mode. Other Configuration Register settings include the number of wait states to insert before the initial word (t IACC) of each burst access, the burst mode in which to operate, and when RDY indicates data is ready to be read. Prior to entering the burst mode, the system should first determine the configuration register set- tings (and read the current register settings if desired via the Read Configuration Register command sequence), and then write the configuration register command sequence. See 8.3.4 and Table 13.1 for further details. Figure 8.1 Synchronous/Asynchronous State Diagram The device outputs the initial word subject to the following operational conditions: „ tIACC specification: the time from the rising edge of the first clock cycle after addresses are latched to valid data on the device outputs. „ Configuration register setting CR13–CR11: the total number of clock cycles (wait states) that occur before valid data appears on the device outputs. The effect is that t IACC is lengthened. The device outputs subsequent words tBACC after the active edge of each successive clock cycle, which also increments the internal address counter. The device outputs burst data at this rate sub- ject to the following operational conditions: Power-up/ Hardware Reset Asynchronous Read Mode Only Synchronous Read Mode Only Set Burst Mode Configuration Register Command for Synchronous Mode (CR15 = 0) Set Burst Mode Configuration Register Command for Asynchronous Mode (CR15 = 1)

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 25 Advance Information „ Starting address: whether the address is divisible by four (where A[1:0] is 00). A divisible- by-four address incurs the least number of additional wait states that occur after the initial word. The number of additional wait states re quired increases for burst operations in which the starting address is one, two, or three locations above the divisible-by-four address (i.e., where A[1:0] is 01, 10, or 11). „ Boundary crossing: There is a boundary at every 128 words due to the internal architecture of the device. One additional wait state must be inserted when crossing this boundary if the memory bus is operating at a high clock frequency. Please refer to the tables below. „ Clock frequency: the speed at which the device is expected to burst data. Higher speeds require additional wait states after the initial word for proper operation. In all cases, with or without latency, the RDY output indicates when the next data is available to be read. Tables 8.2 – 8.6 reflect wait states required for S29WS256/128/064N devices. Refer to the Con- figuration Register table (CR11 – CR14) and timing diagrams for more details. T able 8.2 Address Latency (S29WS256N) Word Wait States Cycle 0 x ws D0 D1 D2 D3 D4 D5 D6 D7 D8 1 x ws D1 D2 D3 1 ws D4 D5 D6 D7 D8 2 x ws D2 D3 1 ws 1 ws D4 D5 D6 D7 D8 3 x ws D3 1 ws 1 ws 1 ws D4 D5 D6 D7 D8 T able 8.3 Address Latency (S29WS128N/S29WS064N) Word Wait States Cycle 0 5, 6, 7 ws D0 D1 D2 D3 D4 D5 D6 D7 D8 1 5, 6, 7 ws D1 D2 D3 1 ws D4 D5 D6 D7 D8 2 5, 6, 7 ws D2 D3 1 ws 1 ws D4 D5 D6 D7 D8 3 5, 6, 7 ws D3 1 ws 1 ws 1 ws D4 D5 D6 D7 D8 T able 8.4 Address/Boundary Crossing Latency (S29WS256N @ 80/66 MHz) Word Wait States Cycle 0 7, 6 ws D0 D1 D2 D3 1 ws D4 D5 D6 D7 1 7, 6 ws D1 D2 D3 1 ws 1 ws D4 D5 D6 D7 2 7, 6 ws D2 D3 1 ws 1 ws 1 ws D4 D5 D6 D7 3 7, 6 ws D3 1 ws 1 ws 1 ws 1 ws D4 D5 D6 D7

26 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

T able 8.5 Address/Boundary Crossi ng Latency (S29WS256N @ 54MHz) Word Wait States Cycle 0 5 ws D0 D1 D2 D3 D4 D5 D6 D7 D8 1 5 ws D1 D2 D3 1 ws D4 D5 D6 D7 D8 2 5 ws D2 D3 1 ws 1 ws D4 D5 D6 D7 D8 3 5 ws D3 1 ws 1 ws 1 ws D4 D5 D6 D7 D8 Ta bl e 8 . 6 Address/Boundary Crossing Latency (S29WS128N/S29WS064N) Word Wait States Cycle 0 5, 6, 7 ws D0 D1 D2 D3 1 ws D4 D5 D6 D7 1 5, 6, 7 ws D1 D2 D3 1 ws 1 ws D4 D5 D6 D7 2 5, 6, 7 ws D2 D3 1 ws 1 ws 1 ws D4 D5 D6 D7 3 5, 6, 7 ws D3 1 ws 1 ws 1 ws 1 ws D4 D5 D6 D7

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 27 Advance Information Figure 8.2 Synchronous Read

8.3.1 Continuous Burst Read Mode

In the continuous burst read mode, the device outputs sequential burst data from the starting address given and then wrap around to address 000000h when it reaches the highest addressable memory location. The burst read mode continues until the system drives CE# high, or RESET= VIL. Continuous burst mode can also be aborted by asserting AVD# low and providing a new ad- dress to the device. If the address being read crosses a 128-word line boundary (as mentioned above) and the sub- sequent word line is not being programmed or erased, additional latency cycles are required as reflected by the configuration register table (Table 8.8). If the address crosses a bank boundary while the subsequent bank is programming or erasing, the device provides read status information and the clock is ignored. Upon completion of status read or program or erase operation, the host can restart a burst read operation using a new ad- dress and AVD# pulse. Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Write Set Configuration Register Command and Settings: Address 555h, Data D0h Address X00h, Data CR Load Initial Address Address = RA Read Initial Data RD = DQ[15:0] Read Next Data RD = DQ[15:0] Wait tIACC + Programmable Wait State Setting Wait X Clocks: Additional Latency Due to Starting Address, Clock Frequency, and Boundary Crossing End of Data? Yes Crossing Boundary? No Yes Completed Delay X Clocks Unlock Cycle 1 Unlock Cycle 2 RA = Read Address RD = Read Data Command Cycle CR = Configuration Register Bits CR15-CR0 CR13-CR11 sets initial access time (from address latched to valid data) from 2 to 7 clock cycles Note: Setup Configuration Register parameters

28 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

8.3.2 8-, 16-, 32-Word Linear Burst Read with Wrap Around In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from con- secutive addresses that are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode (see Table 8.7). For example, if the starting address in the 8-word mode is 3Ch, the address range to be read would be 38-3Fh, and the burst sequence would be 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the device outputs all words in that burst address group until all word are read, regardless of where the start- ing address occurs in the address group, and then terminates the burst read. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address provided to the device, then wrap back to the first address in the selected address group. Note that in this mode the address pointer does not cross the boundary that occurs every 128 words; thus, no additional wait states are inserted due to boundary crossing. 8.3.3 8-, 16-, 32-Word Linear Burst without Wrap Around If wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-word burst executes up to the maximum memory address of the selected number of words. The burst stops after 8, 16, or 32 addresses and does not wrap around to the first address of the selected group. For example, if the starting address in the 8- word mode is 3Ch, the address range to be read would be 39-40h, and the burst sequence would be 3C-3D-3E-3F-40-41-42-43h if wrap around is not enabled. The next address to be read requires a new address and AVD# pulse. Note that in this burst read mode, the address pointer may cross the boundary that occurs every 128 words, which will incur the additional boundary crossing wait state.

8.3.4 Configuration Register

The configuration register sets various operational parameters associated with burst mode. Upon power-up or hardware reset, the device defaults to the asynchronous read mode, and the config- uration register settings are in their default state. The host system should determine the proper settings for the entire configuration register, an d then execute the Set Configuration Register command sequence, before attempting burst operations. The configuration register is not reset after deasserting CE#. The Configuration Register can also be read using a command sequence (see Table 13.1). The following list describes the register settings. T able 8.7 Burst Address Groups Mode Group Size Group Address Ranges 8-word 8 words 0-7h, 8-Fh, 10-17h,... 16-word 16 words 0-Fh, 10-1Fh, 20-2Fh,... 32-word 32 words 00-1Fh, 20-3Fh, 40-5Fh,...

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 29 Advance Information Reading the Configuration Table. The configuration register can be read with a four-cycle com- mand sequence. See Table 13.1 for sequence details. Once the data has been read from the configuration register, a software reset command is required to set the device into the correct state.

8.4 Autoselect

The Autoselect is used for manufacturer ID, Device identification, and sector protection informa- tion. This mode is primarily intended for programming equipment to automatically match a device with its corresponding programming algorithm. The Autoselect codes can also be accessed in-sys- tem. When verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 8.9). The remaining address bits are don't care. The most significant four bits of the address during the third write cycle selects the bank from which the Autoselect codes are read by the host. All other banks can be accessed normally for data read without exiting the Autoselect mode. „ To access the Autoselect codes, the host system must issue the Autoselect command. T able 8.8 Configuration Register CR Bit Function Settings (Binary) CR15 Set Device Read Mode 0 = Synchronous Read (Burst Mode) Enabled 1 = Asynchronous Read Mode (default) Enabled CR14 Boundary Crossing

54 MHz 66 Mhz 80 MHz

S29WS128N N/A N/A N/A Default value is 0 S29WS256N 0 1 1 0 = No extra boundary crossing latency 1 = With extra boundary crossing latency (default) Must be set to 1 greater than 54 MHz. CR13 Programmable Wait State S29WS064N S29WS128N 011 011 = Data valid on 5th active CLK edge after addresses latched 100 = Data valid on 6th active CLK edge after addresses latched 101 = Data valid on 7th active CLK edge after addresses latched (default) 110 = Reserved 111 = Reserved Inserts wait states before initial data is available. Setting greater number of wait states before initial data reduces latency after initial data. (Notes 1, 2) S29WS256N CR12 S29WS064N S29WS128N 100 S29WS256N CR11 S29WS064N S29WS128N 101 S29WS256N CR10 RDY Polarity 0 = RDY signal active low 1 = RDY signal active high (default) CR9 Reserved 1 = default CR8 RDY 0 = RDY active one clock cycle before data 1 = RDY active with data (default) When CR13-CR11 are set to 000, RDY is active with data regardless of CR8 setting. CR7 Reserved 1 = default CR6 Reserved 1 = default CR5 Reserved 0 = default CR4 Reserved 0 = default CR3 Burst Wrap Around 0 = No Wrap Around Burst 1 = Wrap Around Burst (default) CR2 CR1 CR0 Burst Length 000 = Continuous (default) 010 = 8-Word Linear Burst 011 = 16-Word Linear Burst 100 = 32-Word Linear Burst (All other bit settings are reserved) Notes: 1. Refer to Tables 8.2 - 8.6 for wait states requirements. 2. Refer to Synchronous Burst Read timing diagrams 3. Configuration Register is in the default state upon power-up or hardware reset.

30 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

„ The Autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. „ The Autoselect command may not be written while the device is actively programming or erasing. Autoselect does not support simultaneous operations or burst mode. „ The system must write the reset command to return to the read mode (or erase-suspend- read mode if the bank was previously in Erase Suspend). See Table 13.1 for command sequence details. T able 8.9 Autoselect Addresses Description Address Read Data Manufacturer ID (BA) + 00h 0001h Device ID, Word 1 (BA) + 01h 227Eh Device ID, Word 2 (BA) + 0Eh 2230 (WS256N) 2231 (WS128N) 2232 (WS064N) Device ID, Word 3 (BA) + 0Fh 2200 Indicator Bits (See Note) (BA) + 03h DQ15 - DQ8 = Reserved DQ7 (Factory Lock Bit): 1 = Locked, 0 = Not Locked DQ6 (Customer Lock Bit): 1 = Locked, 0 = Not Locked DQ5 (Handshake Bit): 1 = Reserved, 0 = Standard Handshake DQ4, DQ3 (WP# Protection Boot Code): 00 = WP# Protects both Top Boot and Bottom Boot Sectors. 01, 10, 11 = Reserved DQ2 = Reserved DQ1 (DYB Power up State [Lock Register DQ4]): 1 = Unlocked (user option), 0 = Locked (default) DQ0 (PPB Eraseability [Lock Register DQ3]): 1 = Erase allowed, 0 = Erase disabled Sector Block Lock/ Unlock (SA) + 02h 0001h = Locked, 0000h = Unlocked Note: For WS128N and WS064, DQ1 and DQ0 are reserved.

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 31 Advance Information Notes: 1. Any offset within the device works. 2. BA = Bank Address. The bank address is required. 3. base = base address. The following is a C source code example of using the autoselect function to read the manu- facturer ID. Refer to the Spansion Low Level Driver User Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software develop- ment guidelines. /* Here is an example of Autoselect mode (getting manufacturer ID) */ /* Define UINT16 example: typedef unsigned short UINT16; */ UINT16 manuf_id; /* Auto Select Entry */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */ /* multiple reads can be performed after entry */ manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */ /* Autoselect exit */ *( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */ Software Functions and Sample Code Ta bl e 8 . 1 0 Autoselect Entry (LLD Function = lld_AutoselectEntryCmd) Cycle Operation Byte Address Word Address Data Unlock Cycle 1 Write BAxAAAh BAx555h 0x00AAh Unlock Cycle 2 Write BAx555h BAx2AAh 0x0055h Autoselect Command Write BAxAAAh BAx555h 0x0090h Ta bl e 8 . 1 1 Autoselect Exit (LLD Function = lld_AutoselectExitCmd) Cycle Operation Byte Address Word Address Data Unlock Cycle 1 Write base + XXXh base + XXXh 0x00F0h

32 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

8.5 Program/Erase Operations

These devices are capable of several modes of programming and or erase operations which are described in detail in the following sections. However, prior to any programming and or erase op- eration, devices must be setup appropriately as outlined in the configuration register (Table 8.8). For any program and or erase operations, including writing command sequences, the system must drive AVD# and CE# to V IL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or programming data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. Note the following: „ When the Embedded Program algorithm is complete, the device returns to the read mode. „ The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. „ A 0 cannot be programmed back to a 1. Attempting to do so causes the device to set DQ5 = 1 (halting any further operation and requiring a reset command). A succeeding read shows that the data is still 0. Only erase operations can convert a 0 to a 1. „ Any commands written to the device during the Embedded Program Algorithm are ignored except the Program Suspend command. „ Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program oper- ation is in progress. „ A hardware reset immediately terminates the program operation and the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. „ Programming is allowed in any sequence and across sector boundaries for single word pro- gramming operation.

8.5.1 Single Word Programming

Single word programming mode is the simplest method of programming. In this mode, four Flash command write cycles are used to program an individual Flash address. The data for this pro- gramming operation could be 8-, 16- or 32-bits wide. While this method is supported by all Spansion devices, in general it is not recommended for devices that support Write Buffer Pro- gramming. See Table 13.1 for the required bus cycles and Figure 8.3 for the flowchart. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program oper- ation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. „ During programming, any command (except the Suspend Program command) is ignored. „ The Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program op- eration is in progress. „ A hardware reset immediately terminates the program operation. The program command se- quence should be reinitiated once the device has returned to the read mode, to ensure data integrity.

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 33 Advance Information Figure 8.3 Single Word Program Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Write Program Command: Address 555h, Data A0h Program Data to Address: PA, PD Unlock Cycle 1 Unlock Cycle 2 Setup Command Program Address (PA), Program Data (PD) FAIL. Issue reset command to return to read array mode. Perform Polling Algorithm (see Write Operation Status flowchart) Yes Yes No No Polling Status = Busy? Polling Status = Done? Error condition (Exceeded Timing Limits) PASS. Device is in read mode.

34 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

Note: Base = Base Address. The following is a C source code example of using the single word program function. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. /* Example: Program Command */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)base_addr + 0x555 ) = 0x00A0; /* write program setup command */ *( (UINT16 *)pa ) = data; /* write data to be programmed */ /* Poll for program completion */

8.5.2 Write Buffer Programming

Write Buffer Programming allows the system to write a maximum of 32 words in one program- ming operation. This results in a faster effective word programming time than the standard word programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming occurs. At this point, the system writes the number of word locations minus 1 that are loaded into the page buffer at the Sector Address in which programming occurs. This tells the device how many write buffer addresses are loaded with data and therefore when to expect the Program Buffer to Flash confirm command. The number of locations to program cannot exceed the size of the write buffer or the operation aborts. (Number loaded = the number of locations to program minus 1. For example, if the sys- tem programs 6 address locations, then 05h should be written to the device.) The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed, and selects the write-buffer-page address. All subsequent address/data pairs must fall within the elected-write-buffer-page. The write-buffer-page is selected by using the addresses AMAX - A5. The write-buffer-page addresses must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer- pages. This also means that Write Buffer Programming cannot be performed across multiple sec- tors. If the system attempts to load programming data outside of the selected write-buffer-page, the operation ABORTs.) After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the write buffer. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter is decremented for every data load operation. Also, the last data loaded at a location before the Program Buffer to Flash confirm command is programmed into the device. It is the software's re- sponsibility to comprehend ramifications of loading a write-buffer location more than once. The Software Functions and Sample Code Ta b l e 8 . 1 2 Single Word Program (LLD Function = lld_ProgramCmd) Cycle Operation Byte Address Word Address Data Unlock Cycle 1 Write Base + AAAh Base + 555h 00AAh Unlock Cycle 2 Write Base + 554h Base + 2AAh 0055h Program Setup Write Base + AAAh Base + 555h 00A0h Program Write Word Address Word Address Data Word

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 35 Advance Information counter decrements for each data load operation, NOT for each unique write-buffer-address loca- tion. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the Sector Address. Any other address/data write combinations abort the Write Buffer Programming operation. The device goes busy. The Data Bar polling techniques should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer embedded programming operation can be suspended using the standard sus- pend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device returns to READ mode. The Write Buffer Programming Sequence is ABORTED under any of the following conditions: „ Load a value that is greater than the page buffer size during the Number of Locations to Pro- gram step. „ Write to an address in a sector different than the one specified during the Write-Buffer-Load command. „ Write an Address/Data pair to a different wr ite-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. „ Write data other than the Confirm Command after the specified number of data load cycles. The ABORT condition is indicated by DQ1 = 1, DQ7 = Data# (for the last address location loaded), DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation was ABORTED. A Write-to-Buffer-Abort reset command sequence is requ ired when using the write buffer Programming features in Unlock Bypass mode. Note that the Secured Silicon sector, au- toselect, and CFI functions are unavailable when a program operation is in progress. Write buffer programming is allowed in any sequence of memory (or address) locations. These flash devices are capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. Use of the write buffer is strongly recommended for programming when multiple words are to be programmed. Write buffer programming is approximately eight times faster than programming one word at a time.

36 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

Notes: 1. Base = Base Address. 2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37. 3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible. The following is a C source code example of using the write buffer program function. Refer to the Spansion Low Level Driver User Guide (available on www.amd.com and www.fujitsu.comm) for general information on Spansion Flash memory software develop- ment guidelines. /* Example: Write Buffer Programming Command */ /* NOTES: Write buffer programming limited to 16 words. */ /* All addresses to be written to the flash in */ /* one operation must be within the same flash */ /* page. A flash page begins at addresses */ /* evenly divisible by 0x20. */ UINT16 *src = source_of_data; /* address of source data */ UINT16 *dst = destination_of_data; /* flash destination address */ UINT16 wc = words_to_program -1; /* word count (minus 1) */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)sector_address ) = 0x0025; /* write write buffer load command */ *( (UINT16 *)sector_address ) = wc; /* write word count (minus 1) */ loop: *dst = *src; /* ALL dst MUST BE SAME PAGE */ /* write source data to destination */ dst++; /* increment destination pointer */ src++; /* increment source pointer */ if (wc == 0) goto confirm /* done when word count equals zero */ wc--; /* decrement word count */ goto loop; /* do it again */ confirm: *( (UINT16 *)sector_address ) = 0x0029; /* write confirm command */ /* poll for completion */ /* Example: Write Buffer Abort Reset */ *( (UINT16 *)addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)addr + 0x555 ) = 0x00F0; /* write buffer abort reset */ Software Functions and Sample Code T able 8.13 Write Buffer Program (LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd) Cycle Description Operation Byte Address Word Address Data

1 Unlock Write Base + AAAh Base + 555h 00AAh

2 Unlock Write Base + 554h Base + 2AAh 0055h

3 Write Buffer Load Command Write Program Address 0025h

4 Write Word Count Write Program Address Word Count (N–1)h

Number of words (N) loaded into the write buffer can be from 1 to 32 words. 5 to 36 Load Buffer Word N Write Program Address, Word N Word N Last Write Buffer to Flash Write Sector Address 0029h

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 37 Advance Information Figure 8.4 Write Buffer Programming Operation

8.5.3 Sector Erase

The sector erase function erases one or more sectors in the memory array. (See Table 13.1 and Figure 8.5) The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pat- tern prior to electrical erase. After a successful sector erase, all locations within the erased sector contain FFFFh. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of no less than tSEA occurs. Dur- ing the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than t SEA. Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Issue Write Buffer Load Command: Address 555h, Data 25h Load Word Count to Program Program Data to Address: SA = wc Unlock Cycle 1 Unlock Cycle 2 wc = number of words – 1 Yes YesYes Yes Yes No No No No No wc = 0? Write Buffer Abort Desired? Write Buffer Abort? Polling Status = Done? Error? FAIL. Issue reset command to return to read array mode. Write to a Different Sector Address to Cause Write Buffer Abort PASS. Device is in read mode. Confirm command: SA 29h Wait 4 µs Perform Polling Algorithm (see Write Operation Status flowchart) Write Next Word, Decrement wc: PA data , wc = wc – 1 RESET. Issue Write Buffer Abort Reset Command

38 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

Any sector erase address and command following the exceeded time-out (tSEA) may or may not be accepted. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system can monitor DQ3 to determine if the sector erase timer has timed out (see DQ3: Sector Erase Timeout State Indicator). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and ad- dresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing banks. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. See Write Operation Status for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 8.5 illustrates the algorithm for the erase operation. See Erase/Program Timing for param- eters and timing diagrams. The following is a C source code example of using the sector erase function. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. /* Example: Sector Erase Command */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write additional unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write additional unlock cycle 2 */ *( (UINT16 *)sector_address ) = 0x0030; /* write sector erase command */ Software Functions and Sample Code Ta bl e 8 . 1 4 Sector Erase (LLD Function = lld_SectorEraseCmd) Cycle Description Operation Byte Address Word Address Data

3 Setup Command Write Base + AAAh Base + 555h 0080h

4 Unlock Write Base + AAAh Base + 555h 00AAh

5 Unlock Write Base + 554h Base + 2AAh 0055h

6 Sector Erase Command Write Sector Address Sector Address 0030h

Unlimited additional sectors may be selected for erase; command(s) must be written within tSEA.

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 39 Advance Information Notes: 1. See Table 13.1 for erase command sequence. 2. See the section on DQ3 for informat ion on the sector erase timeout. Figure 8.5 Sector Erase Operation No Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Write Sector Erase Cycles: Address 555h, Data 80h Address 555h, Data AAh Address 2AAh, Data 55h Sector Address, Data 30h Write Additional Sector Addresses FAIL. Write reset command to return to reading array. PASS. Device returns to reading array. Wait 4 µs Perform Write Operation Status Algorithm Select Additional Sectors? Unlock Cycle 1 Unlock Cycle 2 Yes Yes Yes Yes Yes No No No No Last Sector Selected? Done? DQ5 = 1? Command Cycle 1 Command Cycle 2 Command Cycle 3 Specify first sector for erasure Error condition (Exceeded Timing Limits) Status may be obtained by reading DQ7, DQ6 and/or DQ2. Poll DQ3. DQ3 = 1?  Each additional cycle must be written within tSEA timeout  Timeout resets after each additional cycle is written  The host system may monitor DQ3 or wait tSEA to ensure acceptance of erase commands  No limit on number of sectors  Commands other than Erase Suspend or selecting additional sectors for erasure during timeout reset device to reading array data

40 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

8.5.4 Chip Erase Command Sequence

Chip erase is a six-bus cycle operation as indicated by Table 13.1. These commands invoke the Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. After a successful chip erase, all locations of the chip contain FFFFh. The system is not required to provide any controls or timings during these oper- ations. Table 13.1 and Table 13.2 in the appendix show the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and ad- dresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. See Write Operation Status for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hard- ware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. The following is a C source code example of using the chip erase function. Refer to the Span- sion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. /* Example: Chip Erase Command */ /* Note: Cannot be suspended */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write additional unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write additional unlock cycle 2 */ *( (UINT16 *)base_addr + 0x000 ) = 0x0010; /* write chip erase command */

8.5.5 Erase Suspend/Er ase Resume Commands

When the Erase Suspend command is written during the sector erase time-out, the device imme- diately terminates the time-out period and su spends the erase operation. The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the min- imum tSEA time-out period during the sector er ase command sequence. The Erase Suspend command is ignored if written during the chip erase operation. When the Erase Suspend command is written after the tSEA time-out period has expired and dur- ing the sector erase operation, the device requires a maximum of tESL (erase suspend latency) to suspend the erase operation. Software Functions and Sample Code Ta bl e 8 . 1 5 C h i p E r a s e (LLD Function = lld_ChipEraseCmd) Cycle Description Operation Byte Address Word Address Data

6 Chip Erase Command Write Base + AAAh Base + 555h 0010h

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 41 Advance Information After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The de- vice erase suspends all sectors selected for erasure.) Reading at any address within erase- suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6, and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to Table 8.23 for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend- read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. In the erase-suspend-read mode, the system can also issue the Autoselect command sequence. See Write Buffer Programming and Autoselect for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. The following is a C source code example of using the erase suspend function. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. /* Example: Erase suspend command */ *( (UINT16 *)bank_addr + 0x000 ) = 0x00B0; /* write suspend command */ The following is a C source code example of using the erase resume function. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. /* Example: Erase resume command */ *( (UINT16 *)bank_addr + 0x000 ) = 0x0030; /* write resume command */ /* The flash needs adequate time in the resume state */

8.5.6 Program Suspend/Pr ogram Resume Commands

The Program Suspend command allows the system to interrupt an embedded programming op- eration or a Write to Buffer programming operation so that data can read from any non- suspended sector. When the Program Suspend command is written during a programming pro- cess, the device halts the programming operation within t PSL (program suspend latency) and updates the status bits. Addresses are don't-cares when writing the Program Suspend command. Software Functions and Sample Code Ta bl e 8 . 1 6 Erase Suspend (LLD Function = lld_EraseSuspendCmd) Cycle Operation Byte Address Word Address Data

1 Write Bank Address Bank Address 00B0h

Ta b l e 8 . 1 7 Erase Resume (LLD Function = lld_EraseResumeCmd) Cycle Operation Byte Address Word Address Data

1 Write Bank Address Bank Address 0030h

42 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a program- ming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area, then user must use the proper command sequences to enter and exit this region. The system may also write the Autoselect command sequence when the device is in Program Sus- pend mode. The device allows reading Autoselect codes in the suspended sectors, since the codes are not stored in the memory array. When the device exits the Autoselect mode, the device re- verts to Program Suspend mode, and is ready for another valid operation. See Autoselect for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information. The system must write the Program Resume command (address bits are don't care) to exit the Program Suspend mode and continue the programming operation. Further writes of the Program Resume command are ignored. Another Program Suspend command can be written after the de- vice has resumed programming. The following is a C source code example of using the program suspend function. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. /* Example: Program suspend command */ *( (UINT16 *)base_addr + 0x000 ) = 0x00B0; /* write suspend command */ The following is a C source code example of using the program resume function. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. /* Example: Program resume command */ *( (UINT16 *)base_addr + 0x000 ) = 0x0030; /* write resume command */

8.5.7 Accelerated Pr ogram/Chip Erase

Accelerated single word programming, write buffer programming, sector erase, and chip erase operations are enabled through the ACC function. This method is faster than the standard chip program and erase command sequences. The accelerated chip program and erase functions must not be used more than 10 times per sector. In addition, accelerated chip program and erase should be performed at room tem- perature (25°C ±10°C). Software Functions and Sample Code Ta bl e 8 . 1 8 Program Suspend (LLD Function = lld_ProgramSuspendCmd) Cycle Operation Byte Address Word Address Data Ta bl e 8 . 1 9 Program Resume (LLD Function = lld_ProgramResumeCmd) Cycle Operation Byte Address Word Address Data

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 43 Advance Information If the system asserts VHH on this input, the device automatically enters the aforementioned Un- lock Bypass mode and uses the higher voltage on the input to reduce the time required for program and erase operations. The system can then use the Write Buffer Load command se- quence provided by the Unlock Bypass mode. Note that if a Write-to-Buffer-Abort Reset is required while in Unlock Bypass mode, the full 3-cycle RESET command sequence must be used to reset the device. Removing VHH from the ACC input, upon completion of the embedded pro- gram or erase operation, returns the device to normal operation. „ Sectors must be unlocked prior to raising ACC to VHH. „ The ACC pin must not be at VHH for operations other than accelerated programming and ac- celerated chip erase, or device damage may result. „ The ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. „ ACC locks all sector if set to VIL. ACC should be set to VIH for all other conditions.

8.5.8 Unlock Bypass

The device features an Unlock Bypass mode to facilitate faster word programming. Once the de- vice enters the Unlock Bypass mode, only two write cycles are required to program data, instead of the normal four cycles. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. See the Appendix for the requirements for the unlock bypass command sequences. During the unlock bypass mode, only the Read, Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode.

44 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

The following are C source code examples of u sing the unlock bypass entry, program, and exit functions. Refer to the Spansion Low Level Driver User’s Guide (available soon on www.amd.com and www.fujitsu.com) for general information on Spansion Flash “memory software development guidelines. /* Example: Unlock Bypass Entry Command */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)bank_addr + 0x555 ) = 0x0020; /* write unlock bypass command */ /* At this point, programming only takes two write cycles. */ /* Once you enter Unlock Bypass Mode, do a series of like */ /* operations (programming or sector erase) and then exit */ /* Unlock Bypass Mode before beginning a different type of */ /* operations. */ /* Example: Unlock Bypass Program Command */ /* Do while in Unlock Bypass Entry Mode! */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00A0; /* write program setup command */ *( (UINT16 *)pa ) = data; /* write data to be programmed */ /* Poll until done or error. */ /* If done and more to program, */ /* do above two cycles again. */ /* Example: Unlock Bypass Exit Command */ *( (UINT16 *)base_addr + 0x000 ) = 0x0090; *( (UINT16 *)base_addr + 0x000 ) = 0x0000;

8.5.9 Write Operation Status

The device provides several bits to determine the status of a program or erase operation. The following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7. DQ7: Data# Polling. The Data# Polling bit, DQ7, indicates to the host system whether an Em- bedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command se- Software Functions and Sample Code Ta bl e 8 . 2 0 Unlock Bypass Entry (LLD Function = lld_UnlockBypassEntryCmd) Cycle Description Operation Byte Address Word Address Data

3 Entry Command Write Base + AAAh Base + 555h 0020h

T able 8.21 Unlock Bypass Program (LLD Function = lld_UnlockBypassProgramCmd) Cycle Description Operation Byte Address Word Address Data

1 Program Setup Command Write Base + xxxh Base +xxxh 00A0h

2 Program Command Write Program Address Program Address Program Data

T able 8.22 Unlock Bypass Reset (LLD Function = lld_UnlockBypassResetCmd) Cycle Description Operation Byte Address Word Address Data

1 Reset Cycle 1 Write Base + xxxh Base +xxxh 0090h

2 Reset Cycle 2 Write Base + xxxh Base +xxxh 0000h

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 45 Advance Information quence. Note that the Data# Polling is valid only for the last word being programmed in the write- buffer-page during Write Buffer Programming. Reading Data# Polling status on any word other than the last word to be programmed in the write-buffer-page returns false status information. During the Embedded Program algorithm, the de vice outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# polling on DQ7 is active for approxi- mately tPSP, then that bank returns to the read mode. During the Embedded Erase Algorithm, Data# polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling pro- duces a 1 on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately tASP, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asyn- chronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still invalid. Valid data on DQ7-D00 appears on successive read cycles. See the following for more information: Table 8.23, Write Operation Status, shows the outputs for Data# Polling on DQ7. Figure 8.6, Write Operation Status Flowchart, shows the Data# Polling algorithm; and Figure 12.17, Data# Polling Timings (During Embedded Algorithm) , shows the Data# Polling timing diagram.

46 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

Figure 8.6 Write Operation Status Flowchart START Read 1 DQ7=valid data? YES NO Read 1 DQ5=1? YES NO Write Buffer Programming? YES NO Device BUSY, Re-Poll Read3 DQ1=1? YES NO Read 2 Read 3 Read 2 Read 3 Read 2 Read 3 Read3 DQ1=1 AND DQ7 ≠ Valid Data? YES NO (Note 4) Write Buffer Operation Failed DQ6 toggling? YES NO TIMEOUT (Note 1) (Note 3) Programming Operation? DQ6 toggling? YES NO YES NO DQ2 toggling? YES NO Erase Operation Complete Device in Erase/Suspend Mode Program Operation Failed DEVICE ERROR Erase Operation Complete Read3= valid data? YES NO Notes: 1) DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6. 2) DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2. 3) May be due to an attempt to program a 0 to 1. Use the RESET command to exit operation. 4) Write buffer error if DQ1 of last read =1. 5) Invalid state, use RESET command to exit operation. 6) Valid data is the data that is intended to be programmed or all 1's for an erase operation. 7) Data polling algorithm valid for all operations except advanced sector protection. Device BUSY, Re-Poll Device BUSY, Re-Poll Device BUSY, Re-Poll (Note 1) (Note 2) (Note 6) (Note 5)

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 47 Advance Information DQ6: Toggle Bit I . Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algo- rithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and dur- ing the sector erase time-out. During an Embedded Program or Erase algorith m operation, successive read cycles to any ad- dress cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately tASP [all sectors protected toggle time], then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro- tected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops tog- gling. However, the system must also use DQ2 to determine which sectors are erasing or erase- suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately tPAP after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embed- ded Program Algorithm is complete. See the following for additional information: Figure 8.6, Write Operation Status Flowchart ; Figure 12.18, Toggle Bit Timings (During Embedded Algorithm), and Table 8.23 and Table 8.24. T oggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the change in state. DQ2: Toggle Bit II . The Toggle Bit II on DQ2, when used with DQ6, indicates whether a partic- ular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. But DQ2 ca nnot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively eras- ing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 8.23 to compare outputs for DQ2 and DQ6. See the following for additional information: Figure 8.6, the DQ6: Tog- gle Bit I section, and Figures 12.17–12.20. Reading Toggle Bits DQ6/DQ2. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typ- ically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erases operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bi t is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then deter- mine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erases operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through succes- sive read cycles, determining the status as described in the previous paragraph. Alternatively, it

48 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Refer to Figure 8.6 for more details. DQ5: Exceeded Timing Limits. DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1, indicating that the program or erase cycle was not successfully completed. The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was previously programmed to 0 Only an erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a 1. Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). DQ3: Sector Erase Timeout State Indicator. After writing a sector erase command sequence, the system may read DQ3 to de termine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a 0 to a 1. If the time between additional sector erase commands from the system can be assumed to be less than tSEA, the system need not monitor DQ3. See Sector Erase Command Sequence for more details. After the sector erase command is written, the system should read the status of DQ7 (Data# Poll- ing) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is 1, the Embedded Erase algorithm has begun; all further commands (ex- cept Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0 the device accepts additional sector erase commands. To ensure the command has been accepted, the sys- tem software should check the status of DQ3 prior to and following each sub-sequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 8.23 shows the status of DQ3 relative to the other status bits. DQ1: Write to Buffer Abort. DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 produces a 1. The system must issue the Write to Buffer Abort Reset command sequence to return the device to reading array data. See Write Buffer Programming Operation for more details. Ta b l e 8 . 2 3 Write Operation Status Notes: 1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 a valid address when reading status information. Refer to the appropriate subsection for further details. 3. Data are invalid for addresses in a Program Suspended sector. 4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations. 5. The data-bar polling algorithm should be used for Write Buffer Pr ogramming operations. Note that DQ7# during Write Buffer Programming indicates the data-bar for DQ7 data for the Last Loaded Write-buffer Address location. Program Suspend Mode (Note 3) Reading within Program Suspended Sector INVALID (Not Allowed) INVALID (Not Allowed) INVALID (Not Allowed) INVALID (Not Allowed) INVALID (Not Allowed) INVALID (Not Allowed) Reading within Non-Program Suspended Sector Data Data Data Data Data Data Write to Buffer (Note 5) BUSY State DQ7# Toggle 0 N/A N/A 0 Exceeded Timing Limits DQ7# Toggle 1 N/A N/A 0 ABORT State DQ7# Toggle 0 N/A N/A 1

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 49 Advance Information

8.6 Simultaneous Read/Write

The simultaneous read/write feature allows the host system to read data from one bank of mem- ory while programming or erasing another bank of memory. An erase operation may also be suspended to read from or program another location within the same bank (except the sector being erased). Figure 12.24, Back-to-Back Read/Write Cycle Timings, shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Character- istics table for read-while-program and read-while-erase current specification.

8.7 Writing Commands/Command Sequences

When the device is configured for Asynchronous read, only Asynchronous write operations are allowed, and CLK is ignored. When in the Synchronous read mode configuration, the device is able to perform both Asynchronous and Synchronous write operations. CLK and AVD# induced address latches are supported in the Synchronous programming mode. During a synchronous write oper- ation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to V IL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or data. During an asynchronous write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. An erase operation can erase one sector, multiple sectors, or the entire device. Tables 7.1–7.3 indicate the address space that each sector occupies. The device address space is divided into sixteen banks: Banks 1 through 14 contain only 64 Kword sectors, while Banks 0 and 15 contain both 16 Kword boot sectors in addition to 64 Kword sectors. A bank address is the set of address bits required to uniquely select a bank. Similarly, a sector address is the address bits required to uniquely select a sector. I CC2 in DC Characteristics represents the active current spec- ification for the write mode. AC Characteristics—Synchronous and AC Characteristics— Asynchronous Read contain timing specification tables and timing diagrams for write operations.

8.8 Handshaking

The handshaking feature allows the host system to detect when data is ready to be read by simply monitoring the RDY (Ready) pin, which is a dedicated output and controlled by CE#. When the device is configured to operate in synchronous mode, and OE# is low (active), the initial word of burst data becomes available after either the falling or rising edge of the RDY pin (de- pending on the setting for bit 10 in the Configuration Register). It is recommended that the host system set CR13–CR11 in the Configuration Register to the appropriate number of wait states to ensure optimal burst mode operation (see Table 8.8, Configuration Register). Bit 8 in the Configuration Register allows the host to specify whether RDY is active at the same time that data is ready, or one cycle before data is ready.

50 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

8.9 Hardware Reset

The RESET# input provides a hard ware method of resetting the device to reading array data. When RESET# is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/ write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. To ensure data integrity the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence. When RESET# is held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held at VIL, but not at VSS, the standby current is greater. RESET# may be tied to the system reset circuitry which enables the system to read the boot-up firmware from the Flash memory upon a system reset. See Figures 12.5 and 12.12 for timing diagrams.

8.10 Software Reset

Software reset is part of the command set (see Table 13.1) that also returns the device to array read mode and must be used for the following conditions: 1. to exit Autoselect mode 2. when DQ5 goes high during write status oper ation that indicates program or erase cycle was not successfully completed 3. exit sector lock/unlock operation. 4. to return to erase-suspend-read mode if th e device was previously in Erase Suspend mode. 5. after any aborted operationsNote: Base = Base Address. The following is a C source code example of using the reset function. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. /* Example: Reset (software reset of Flash state machine) */ *( (UINT16 *)base_addr + 0x000 ) = 0x00F0; The following are additional points to consider when using the reset command: „ This command resets the banks to the read and address bits are ignored. „ Reset commands are ignored once erasure has begun until the operation is complete. „ Once programming begins, the device ignores reset commands until the operation is com- plete „ The reset command may be written between the cycles in a program command sequence be- fore programming begins (prior to the third cycle). This resets the bank to which the system was writing to the read mode. Software Functions and Sample Code Ta bl e 8 . 2 4 Reset (LLD Function = lld_ResetCmd) Cycle Operation Byte Address Word Address Data Reset Command Write Base + xxxh Base + xxxh 00F0h

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 51 Advance Information „ If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. „ The reset command may be also written during an Autoselect command sequence. „ If a bank has entered the Autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. „ If DQ1 goes high during a Write Buffer Prog ramming operation, the system must write the Write to Buffer Abort Reset command sequence to RESET the device to reading array data. The standard RESET command does not work during this condition. „ To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset com- mand sequence [see command table for details].

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9 Advanced Sector Protection/Unprotection

The Advanced Sector Protection/Unprotection feature disables or enables programming or erase operations in any or all sectors and can be implemented through software and/or hardware meth- ods, which are independent of each other. Th is section describes the various methods of protecting data stored in the memory array. An overview of these methods in shown in Figure 9.1. Figure 9.1 Advanced Sector Protection/Unprotection Hardware Methods Software Methods ACC = VIL (All sectors locked) WP# = VIL (All boot sectors locked) Password Method (DQ2) Persistent Method (DQ1) Lock Register (One Time Programmable) PPB Lock Bit 1,2,3 64-bit Password (One Time Protect) 1 = PPBs Unlocked0 = PPBs Locked Memory Array Sector 0 Sector 1 Sector 2 Sector N-2 Sector N-1 Sector N PPB 0 PPB 1 PPB 2 PPB N-2 PPB N-1 PPB N Persistent Protection Bit (PPB) 4,5 DYB 0 DYB 1 DYB 2 DYB N-2 DYB N-1 DYB N Dynamic Protection Bit (PPB) 6,7,8 6. 0 = Sector Protected, 1 = Sector Unprotected. 7. Protect effective only if PPB Lock Bit is unlocked and corresponding PPB is “1” (unprotected). 8. Volatile Bits: defaults to user choice upon power-up (see ordering options). 4. 0 = Sector Protected, 1 = Sector Unprotected. 5. PPBs programmed individually, but cleared collectively 1. Bit is volatile, and defaults to “1” on reset. 2. Programming to “0” locks all PPBs to their current state. 3. Once programmed to “0”, requires hardware reset to unlock. 3. N = Highest Address Sector.

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 53 Advance Information

9.1 Lock Register

As shipped from the factory, all devices default to the persistent mode when power is applied, and all sectors are unprotected, unless otherwise chosen through the DYB ordering option. The device programmer or host system must then choose which sector protection method to use. Program- ming (setting to 0) any one of the following two one-time programmable, non-volatile bits locks the part permanently in that mode: „ Lock Register Persistent Protection Mode Lock Bit (DQ1) „ Lock Register Password Protection Mode Lock Bit (DQ2) For programming lock register bits refer to Table 13.2. Notes 1. If the password mode is chosen, the password must be programmed before setting the cor- responding lock register bit. 2. After the Lock Register Bits Command Set En try command sequence is written, reads and writes for Bank 0 are disabled, while reads from other banks are allowed until exiting this mode. 3. If both lock bits are selected to be progra mmed (to zeros) at the same time, the operation aborts. 4. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled, and no changes to the protection schem e are allowed. Similarly, if the Persistent Mode Lock Bit is programmed, the Password Mode is permanently disabled. After selecting a sector protection method, each sector can operate in any of the following three states: 1. Constantly locked. The selected sectors are protected and can not be reprogrammed unless PPB lock bit is cleared via a password, hardware reset, or power cycle. 2. Dynamically locked. The selected sectors are protected and can be altered via software commands. 3. Unlocked. The sectors are unprotected and can be erased and/or programmed. These states are controlled by the bit types described in Sections 9.2–9.6.

9.2 Persistent Protection Bits

The Persistent Protection Bits are unique and nonvolatile for each sector and have the same en- durances as the Flash memory. Preprogramming and verification prior to erasure are handled by the device, and therefore do not require system monitoring. T able 9.1 Lock Register Device DQ15-05 DQ4 DQ3 DQ2 DQ1 DQ0 S29WS256N 1 1 1 Password Protection Mode Lock Bit Persistent Protection Mode Lock Bit Customer Secured Silicon Sector Protection Bit S29WS128N/ S29WS064N Undefined DYB Lock Boot Bit 0 = sectors power up protected 1 = sectors power up unprotected PPB One-Time Programmable Bit 0 = All PPB erase command disabled 1 = All PPB Erase command enabled Password Protection Mode Lock Bit Persistent Protection Mode Lock Bit Secured Silicon Sector Protection Bit

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1. Each PPB is individually programmed and all are erased in parallel. 2. While programming PPB for a sector, array data can be read from any other bank, except Bank 0 (used for Data# Polling) and the bank in which sector PPB is being programmed. 3. Entry command disables reads and writes for the bank selected. 4. Reads within that bank return the PPB status for that sector. 5. Reads from other banks are allowed while writes are not allowed. 6. All Reads must be performed using the Asynchronous mode. 7. The specific sector address (A23-A14 WS256N, A22-A14 WS128N, A21-A14 WS064N) are written at the same time as the program command. 8. If the PPB Lock Bit is set, the PPB Progra m or erase command does not execute and times- out without programming or erasing the PPB. 9. There are no means for individually erasing a sp ecific PPB and no specific sector address is required for this operation. 10. Exit command must be issued after the execution which resets the device to read mode and re-enables reads and writes for Bank 0 11. The programming state of the PPB for a given sector can be verified by writing a PPB Status Read Command to the device as described by the flow chart shown in Figure 9.2.

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 55 Advance Information Figure 9.2 PPB Program/Erase Algorithm

9.3 Dynamic Protection Bits

Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYBs only control the protection scheme for unprotected sectors that have their PPBs cleared (erased to 1). By issuing the DYB Set or Clear command sequences, the DYBs are set (pro- grammed to 0) or cleared (erased to 1), thus placing each sector in the protected or unprotected state respectively. This feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. Read Byte Twice Addr = SA0 Enter PPB Command Set. Addr = BA Program PPB Bit. Addr = SA DQ5 = 1? Yes Yes Yes No No No Yes DQ6 = Toggle? DQ6 = Toggle? Read Byte. Addr = SA PASS FAIL Issue Reset Command Exit PPB Command Set DQ0 = '1' (Erase) '0' (Pgm.)? Read Byte Twice Addr = SA0 No Wait 500 µs

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1. The DYBs can be set (programmed to 0) or cleared (erased to 1) as often as needed. When the parts are first shipped, the PPBs are cleared (erased to 1) and upon power up or reset, the DYBs can be set or cleared depending upon the ordering option chosen. 2. If the option to clear the DYBs after power up is chosen, (erased to 1), then the sectorsmay be modified depending upon the PPB state of that sector (see Table 9.2). 3. The sectors would be in the protected state If the option to set the DYBs after power up is chosen (programmed to 0). 4. It is possible to have sectors that are persiste ntly locked with sectors that are left in the dynamic state. 5. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotected state of the sectors respectively. However, if there is a need to change the status of the per- sistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired setting s. Setting the PPB Lock Bit once again locks the PPBs, and the device operates normally again. 6. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command early in the boot code and protect the boot code by holding WP# = VIL. Note that the PPB and DYB bits have the same function when ACC = VHH as they do when ACC =VIH.

9.4 Persistent Protection Bit Lock Bit

The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed to 0), it locks all PPBs and when cleared (programmed to 1), allows the PPBs to be changed. There is only one PPB Lock Bit per device. Notes 1. No software command sequence unlocks this bit unless the device is in the password pro- tection mode; only a hardware reset or a power-up clears this bit. 2. The PPB Lock Bit must be set (programmed to 0) only after all PPBs are configured to the desired settings.

9.5 Password Protection Method

The Password Protection Method allows an even higher level of security than the Persistent Sector Protection Mode by requiring a 64 bit password for unlocking the device PPB Lock Bit. In addition to this password requirement, after power up and reset, the PPB Lock Bit is set 0 to maintain the password mode of operation. Successful execution of the Password Unlock command by entering the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications.

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 57 Advance Information Notes 1. There is no special addressing order required for programming the password. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to pre- vent access. 2. The Password Program Command is only capable of programming 0s. Programming a 1 after a cell is programmed as a 0 results in a time-out with the cell as a 0. 3. The password is all 1s when shipped from the factory. 4. All 64-bit password combinations are valid as a password. 5. There is no means to verify what the password is after it is set. 6. The Password Mode Lock Bit, once set, prev ents reading the 64-bit password on the data bus and further password programming. 7. The Password Mode Lock Bit is not erasable. 8. The lower two address bits (A1–A0) are valid during the Password Read, Password Program, and Password Unlock. 9. The exact password must be entered in or der for the unlocking function to occur. 10. The Password Unlock command cannot be issued any faster than 1 µs at a time to prevent a hacker from running through all the 64-bit combinations in an attempt to correctly match a password. 11. Approximately 1 µs is required for unlocking the device after the valid 64-bit password is given to the device. 12. Password verification is only allowed during the password programming operation. 13. All further commands to the password region are disabled and all operations are ignored. 14. If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the PPB Lock Bit. 15. Entry command sequence must be issued prior to any of any operation and it disables reads and writes for Bank 0. Reads and writes for other banks excluding Bank 0 are allowed. 16. If the user attempts to program or erase a protected sector, the device ignores the com- mand and returns to read mode. 17. A program or erase command to a protected sector enables status polling and returns to read mode without having modified the contents of the protected sector. 18. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing individual status read comm ands DYB Status, PPB Status, and PPB Lock Status to the device.

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Figure 9.3 Lock Register Program Algorithm Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Write Enter Lock Register Command: Address 555h, Data 40h Program Lock Register Data Address XXXh, Data A0h Address 77h*, Data PD Unlock Cycle 1 Unlock Cycle 2 XXXh = Address don’t care * Not on future devices Program Data (PD): See text for Lock Register definitions Caution: Lock register can only be progammed once. Wait 4 µs PASS. Write Lock Register Exit Command: Address XXXh, Data 90h Address XXXh, Data 00h Device returns to reading array. Perform Polling Algorithm (see Write Operation Status flowchart) Yes Yes No No Done? DQ5 = 1? Error condition (Exceeded Timing Limits) FAIL. Write rest command to return to reading array.

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 59 Advance Information

9.6 Advanced Sector Protection Software Examples

Table 9.2 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the sta- tus of the sector. In summary, if the PPB Lock Bit is locked (set to 0), no changes to the PPBs are allowed. The PPB Lock Bit can only be unlocked (reset to 1) through a hardware reset or power cycle. See also Figure 9.1 for an overview of the Advanced Sector Protection feature.

9.7 Hardware Data Protection Methods

The device offers two main types of data protection at the sector level via hardware control: „ When WP# is at VIL, the four outermost sectors are locked (device specific). „ When ACC is at VIL, all sectors are locked. There are additional methods by which intended or accidental erasure of any sectors can be pre- vented via hardware means. The following subsections describes these methods:

9.7.1 WP# Method

The Write Protect feature provides a hardware method of protecting the four outermost sectors. This function is provided by the WP# pin and overrides the previously discussed Sector Protec- tion/Unprotection method. If the system asserts VIL on the WP# pin, the device disables program and erase functions in the outermost boot sectors. The outermost boot sectors are the sectors containing both the lower and upper set of sectors in a dual-boot-configured device. If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the device may result. The WP# pin must be held stable during a command sequence execution

9.7.2 ACC Method

This method is similar to above, except it prot ects all sectors. Once ACC input is set to V IL, all program and erase functions are disabled and hence all sectors are protected.

9.7.3 Low V CC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. Ta bl e 9 . 2 Unique Device PPB Lock Bit 0 = locked 1 = unlocked Sector PPB 0 = protected 1 = unprotected Sector DYB 0 = protected 1 = unprotected Sector Protection Status Any Sector 0 0 x Protected through PPB Any Sector 0 0 x Protected through PPB Any Sector 0 1 1 Unprotected Any Sector 0 1 0 Protected through DYB Any Sector 1 0 x Protected through PPB Any Sector 1 0 x Protected through PPB Any Sector 1 1 0 Protected through DYB Any Sector 1 1 1 Unprotected

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The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO.

9.7.4 Write Pulse Glitch Protection

Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

9.7.5 Power-Up Write Inhibit

If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept com- mands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 61 Advance Information

10 Power Conservation Modes

10.1 Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at V CC ± 0.2 V. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in DC Characteristics represents the standby current specification

10.2 Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption while in asynchronous mode. the device automatically enables this mode when addresses remain stable for tACC + 20 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Stan- dard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. While in synchronous mode, the auto- matic sleep mode is disabled. Note that a new burst operation is required to provide new data. ICC6 in DC Characteristics represents the automatic sleep mode current specification.

10.3 Hardware RESET# Input Operation

The RESET# input provides a hard ware method of resetting the device to reading array data. When RESET# is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/ write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. When RESET# is held at VSS ± 0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS ± 0.2 V, the standby current is greater. RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

10.4 Output Disable (OE#)

When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state.

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11 Secured Silicon Sector Flash Memory Region

The Secured Silicon Sector provides an extra Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 words in length that consists of 128 words for factory data and 128 words for customer-secured areas. All Secured Silicon reads outside of the 256-word address range returns invalid data. The Factory Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not the Factory Se- cured Silicon Sector is locked when shipped from the factory. The Customer Indicator Bit (DQ6) is used to indicate whether or not the Customer Secured Silicon Sector is locked when shipped from the factory. Please note the following general conditions: „ While Secured Silicon Sector access is enabled, simultaneous operations are allowed except for Bank 0. „ On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. „ Reads can be performed in the Asynchronous or Synchronous mode. „ Burst mode reads within Secured Silicon Sector wrap from address FFh back to address 00h. „ Reads outside of sector 0 return memory array data. „ Continuous burst read past the maximum address is undefined. „ Sector 0 is remapped from memory array to Secured Silicon Sector array. „ Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit command must be issued to exit Secured Silicon Sector Mode. „ The Secured Silicon Sector is not accessible when the device is executing an Embedded Pro- gram or Embedded Erase algorithm.

11.1 Factory Secured SiliconSector

The Factory Secured Silicon Sector is always protected when shipped from the factory and has the Factory Indicator Bit (DQ7) permanently set to a 1. This prevents cloning of a factory locked part and ensures the security of the ESN and customer code once the product is shipped to the field. These devices are available pre programmed with one of the following: „ A random, 8 Word secure ESN only within the Factory Secured Silicon Sector „ Customer code within the Customer Secured Silicon Sector through the Spansion TM program- ming service. „ Both a random, secure ESN and customer code through the Spansion programming service. Customers may opt to have their code programmed through the Spansion programming services. Spansion programs the customer's code, with or without the random ESN. The devices are then shipped from the Spansion factory with the Factory Secured Silicon Sector and Customer Secured Silicon Sector permanently locked. Contact your local representative for details on using Spansion programming services. T able 11.1 Addresses Sector Sector Size Address Range Customer 128 words 000080h-0000FFh Factory 128 words 000000h-00007Fh

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 63 Advance Information

11.2 Customer Secured Silicon Sector

The Customer Secured Silicon Sector is typically shipped unprotected (DQ6 set to 0), allowing customers to utilize that sector in any manner they choose. If the security feature is not required, the Customer Secured Silicon Sector can be treated as an additional Flash memory space. Please note the following: „ Once the Customer Secured Silicon Sector area is protected, the Customer Indicator Bit is permanently set to 1. „ The Customer Secured Silicon Sector can be read any number of times, but can be pro- grammed and locked only once. The Customer Secured Silicon Sector lock must be used with caution as once locked, there is no procedure available for unlocking the Customer Secured Silicon Sector area and none of the bits in the Customer Secured Silicon Sector memory space can be modified in any way. „ The accelerated programming (ACC) and unlock bypass functions are not available when pro- gramming the Customer Secured Silicon Sector, but reading in Banks 1 through 15 is avail- able. „ Once the Customer Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence which return the device to the mem- ory array at sector 0.

11.3 Secured Silicon Sector Entry and Secured Silicon Sector Exit Command Sequences

The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector re- gion until the system issues the four-cycle Exit Secured Silicon Sector command sequence. See Command Definition Table [Secured Silicon Sector Command Table, Appendix Table 13.1 for address and data requirements for both command sequences. The Secured Silicon Sector Entry Command allows the following commands to be executed „ Read customer and factory Secured Silicon areas „ Program the customer Secured Silicon Sector After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by sector SA0 within the memory array. This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device.

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The following are C functions and source code examples of using the Secured Silicon Sector Entry, Program, and exit commands. Refer to the Spansion Low Level Driver User’s Guide (available soon on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. Note: Base = Base Address. /* Example: SecSi Sector Entry Command */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)base_addr + 0x555 ) = 0x0088; /* write Secsi Sector Entry Cmd */ Note: Base = Base Address. /* Once in the SecSi Sector mode, you program */ /* words using the programming algorithm. */ Note: Base = Base Address. /* Example: SecSi Sector Exit Command */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)base_addr + 0x555 ) = 0x0090; /* write SecSi Sector Exit cycle 3 */ *( (UINT16 *)base_addr + 0x000 ) = 0x0000; /* write SecSi Sector Exit cycle 4 */ Software Functions and Sample Code Ta bl e 1 1 . 2 Secured Silicon Sector Entry (LLD Function = lld_SecSiSectorEntryCmd) Cycle Operation Byte Address Word Address Data Unlock Cycle 1 Write Base + AAAh Base + 555h 00AAh Unlock Cycle 2 Write Base + 554h Base + 2AAh 0055h Entry Cycle Write Base + AAAh Base + 555h 0088h T able 11.3 Secured Silicon Sector Program (LLD Function = lld_ProgramCmd) Cycle Operation Byte Address Word Address Data Unlock Cycle 1 Write Base + AAAh Base + 555h 00AAh Unlock Cycle 2 Write Base + 554h Base + 2AAh 0055h Program Setup Write Base + AAAh Base + 555h 00A0h Program Write Word Address Word Address Data Word T able 11.4 Secured Silicon Sector Exit (LLD Function = lld_SecSiSectorExitCmd) Cycle Operation Byte Address Word Address Data Unlock Cycle 1 Write Base + AAAh Base + 555h 00AAh Unlock Cycle 2 Write Base + 554h Base + 2AAh 0055h Exit Cycle Write Base + AAAh Base + 555h 0090h

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 65 Advance Information

12.1 Absolute Maximum Ratings

Voltage with Respect to Ground: All Inputs and I/Os except Notes: 1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may undershoot VSS to –2.0 V transitions outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 12.2. 2. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may overshoot VSS to –2.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. Note: The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N.

12.2 Operating Ranges

Wireless (W) Devices Industrial (I) Devices Supply Voltages (Contact local sales office for VIO = 1.35 to +1.70 V.) Note: Operating ranges define those limits between which the device functionality is guaranteed. Figure 12.1 Maximum Negative Overshoot Waveform Figure 12.2 Maximum Positive Overshoot Waveform 20 ns 20 ns +0.8 V –0.5 V 20 ns –2.0 V 20 ns 20 ns VCC +2.0 V VCC +0.5 V 20 ns 1.0 V

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12.3 T est Conditions

Figure 12.3 Te s t S e t u p Note: The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N.

12.4 Key to Switching Waveforms

Note: The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N.

12.5 Switching Waveforms

Figure 12.4 Input Waveforms and Measurement Levels T able 12.1 T est Specifications T est Condition All Speed Options Unit Output Load Capacitance, CL (including jig capacitance) 30 pF Input Rise and Fall Times 3.0 @ 54, 66 MHz 2.5 @ 80 MHz ns Input Pulse Levels 0.0–VIO V Input timing measurement reference levels VIO/2 V Output timing measurement reference levels VIO/2 V Waveform Inputs Outputs Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) CL Device Under Test VIO 0.0 V OutputMeasurement LevelInput VIO/2 V IO/2All Inputs and Outputs

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 67 Advance Information

12.6 V CC Power-up

Notes: 1. V CC >= VIO - 100mV and VCC ramp rate is > 1V / 100µs 2. V CC ramp rate <1V / 100µs, a Hardware Reset is required. 3. The content in this document is Advance information fo r the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N. Figure 12.5 VCC Power-up Diagram Parameter Description T est Setup Speed Unit tVCS VCC Setup Time Min 1 ms VCC VIO RESET# tVCS

68 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

12.7 DC Characteristics

(CMOS Compatible) Notes: 1. Maximum I CC specifications are tested with VCC = VCCmax. 2. V CC= VIO. 3. CE# must be set high when measuring the RDY pin. 4. The I CC current listed is typically less than 3 mA/MHz, with OE# at VIH. 5. I CC active while Embedded Erase or Embedded Program is in progress. 6. Device enters automatic sleep mode when addresses are stable for tACC + 20 ns. Typical sleep mode current is equal to ICC3. 7. V IH = VCC ± 0.2 V and VIL > –0.1 V. 8. Total current during accelerate d programming is the sum of VACC and VCC currents. 9. V ACC = VHH on ACC input. 10. The content in this document is Advance information fo r the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N. Parameter Description (Notes) T est Conditions (Notes 1, 2, 9) Min Ty p Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCCmax ±1 µA ILO Output Leakage Current (3) VOUT = VSS to VCC, VCC = VCCmax ±1 µA ICCB VCC Active burst Read Current CE# = VIL, OE# = VIH, WE# = VIH, burst length = 8

54 MHz 27 54 mA

66 MHz 28 60 mA

80 MHz 30 66 mA

CE# = VIL, OE# = VIH, WE# = VIH, burst length = 16

54 MHz 28 48 mA

66 MHz 30 54 mA

80 MHz 32 60 mA

CE# = VIL, OE# = VIH, WE# = VIH, burst length = 32

54 MHz 29 42 mA

66 MHz 32 48 mA

80 MHz 34 54 mA

CE# = VIL, OE# = VIH, WE# = VIH, burst length = Continuous

54 MHz 32 36 mA

66 MHz 35 42 mA

80 MHz 38 48 mA

I IO1 VIO Non-active Output OE# = VIH 20 30 µA ICC1 VCC Active Asynchronous Read Current (4) CE# = VIL, OE# = VIH, WE# = VIH

10 MHz 27 36 mA

5 MHz 13 18 mA

1 MHz 3 4 mA

ICC2 VCC Active Write Current (5) CE# = VIL, OE# = VIH, ACC = VIH VACC 15µ A VCC 19 52.5 mA ICC3 VCC Standby Current (6, 7) CE# = RESET# = VCC ± 0.2 V VACC 15µ A VCC 20 40 µA ICC4 VCC Reset Current (7) RESET# = VIL, CLK = VIL 70 150 µA ICC5 VCC Active Current (Read While Write) (7) CE# = VIL, OE# = VIH, ACC = VIH @

5 MHz 50 60 mA

ICC6 VCC Sleep Current (7) CE# = VIL, OE# = VIH 24 0µ A IACC Accelerated Program Current (8) CE# = VIL, OE# = VIH, VACC = 9.5 V VACC 62 0 m A VCC 14 20 mA VIL Input Low Voltage VIO = 1.8 V –0.5 0.4 V VIH Input High Voltage VIO = 1.8 V VIO – 0.4 V IO + 0.4 V VOL Output Low Voltage IOL = 100 µA, VCC = VCC min = VIO 0.1 V VOH Output High Voltage IOH = –100 µA, VCC = VCC min = VIO VIO – 0.1 V VHH Voltage for Accelerated Program 8.5 9.5 V VLKO Low VCC Lock-out Voltage 1.0 1.4 V

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 69 Advance Information

12.8 AC Characteristics

12.8.1 CLK Characterization

Note: The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N. Figure 12.6 CLK Characterization

12.8.2 Synchronous/Burst Read

Notes: 1. Addresses are latched on the first rising edge of CLK. 2. Not 100% tested. 3. The content in this document is Advance information fo r the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N. Parameter Description 54 MHz 66 MHz 80 MHz Unit fCLK CLK Frequency Max 54 66 80 MHz tCLK CLK Period Min 18.5 15.1 12.5 ns tCH CLK High Time Min 7.4 6.1 5.0 ns tCL CLK Low Time tCR CLK Rise Time Max 3 3 2.5 ns tCF CLK Fall Time Parameter Description 54 MHz 66 MHz 80 MHz UnitJEDEC Standard tIACC Latency Max 80 ns tBACC Burst Access Time Valid Clock to Output Delay Max 13.5 11.2 9 ns tACS Address Setup Time to CLK (Note 1)M i n 5 4 n s tACH Address Hold Time from CLK (Note 1)M i n 7 6 n s tBDH Data Hold Time from Next Clock Cycle Min 4 3 ns tCR Chip Enable to RDY Valid Max 13.5 11.2 9 ns tOE Output Enable to Output Valid Max 13.5 11.2 ns tCEZ Chip Enable to High Z (Note 2)M a x1 0 n s tOEZ Output Enable to High Z (Note 2)M a x 1 0 n s tCES CE# Setup Time to CLK Min 4 ns tRDYS RDY Setup Time to CLK Min 5 4 3.5 ns tRACC Ready Access Time from CLK Max 13.5 11.2 9 ns tCAS CE# Setup Time to AVD# Min 0 ns tAVC AVD# Low to CLK Min 4 ns tAVD AVD# Pulse Min 8 ns tAOE AVD Low to OE# Low Max 38.4 ns tCLK tCLtCH tCR tCFCLK

70 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

12.8.3 Timing Diagrams

Notes: 1. Figure shows total number of wait states set to five cycles. The total number of wait states can be programmed from two cycles to seven cycles. 2. If any burst address occurs at address + 1 , address + 2, or address + 3, additional clock delay cycles are inserted, and are indicated by RDY. 3. The device is in synchronous mode. Figure 12.7 CLK Synchronous Burst Mode Read Da Da + 1 Da + n OE# Data (n) Addresses Aa AVD# RDY (n) CLK CE# tCES tACS tAVC tAVD tACH tOE tRACC tOEZ tCEZ tIACC tAOE tBDH 5 cycles for initial access shown. 18.5 ns typ. (54 MHz) Hi-Z Hi-Z Hi-Z 123 45 67 tRDYS tBACC Da + 3Da + 2 Da Da + 1 Da + n Data (n + 1) RDY (n + 1) Hi-Z Hi-Z Hi-Z Da + 2Da + 2 Da Da + 1 Da + n Data (n + 2) RDY (n + 2) Hi-Z Hi-Z Hi-Z Da + 1Da + 1 Da Da Da + n Data (n + 3) RDY (n + 3) Hi-Z Hi-Z Hi-Z DaDa tCR

72 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

Notes: 1. Figure assumes 6 wait states for initial access and synchronous read. 2. The Set Configuration Register command sequence has been written with CR8=0; device outputs RDY one cycle before valid data. Figure 12.10 Linear Burst with RDY Set One Cycle Before Data

12.8.4 AC Characterist ics—Asynchronous Read

Notes: 1. Not 100% tested. 2. The content in this document is Advance information fo r the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N. Parameter Description 54 MHz 66 MHz 80 MHz Unit JEDEC Standard tCE Access Time from CE# Low Max 80 ns tACC Asynchronous Access Time Max 80 ns tAVDP AVD# Low Time Min 8 ns tAAVDS Address Setup Time to Rising Edge of AVD# Min 4 ns tAAVDH Address Hold Time from Rising Edge of AVD# Min 7 6 ns tOE Output Enable to Output Valid Max 13.5 ns tOEH Output Enable Hold Time Read Min 0 ns Data# Polling Min 10 ns tOEZ Output Enable to High Z (see Note) Max 10 ns tCAS CE# Setup Time to AVD# Min 0 ns Da+1Da Da+2 Da+3 Da + n OE# Data Addresses Aa AVD# RDY CLK CE# tCES tACS tAVC tAVD tACH tOE tRACC tOEZ tCEZ tIACC tAOE tBDH 6 wait cycles for initial access shown. Hi-Z Hi-Z Hi-Z 123 456 tRDYS tBACC tCR

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 73 Advance Information Note: RA = Read Address, RD = Read Data. Figure 12.11 Asynchronous Mode Read

12.8.5 Hardware Reset (RESET#)

Notes: 1. Not 100% tested. 2. The content in this document is Advance information fo r the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N. Figure 12.12 Reset Timings Parameter Description All Speed Options UnitJEDEC Std. tRP RESET# Pulse Width Min 30 µs tRH Reset High Time Before Read (See Note)M i n 2 0 0 n s tCEWE# Addresses CE# OE# Valid RD tACC tOEH tOE Data tOEZ tAAVDH tAVDP tAAVDS AVD# RA tCAS RESET# tRP CE#, OE# tRH

74 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

12.8.6 Erase/Program Timing

Notes: 1. Not 100% tested. 2. Asynchronous read mode allows Asynchronous program operation only. Synchronous read mode allows both Asynchronous and Synchronous program operation. 3. In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program operation timing, addresses are latched on the rising edge of CLK. 4. See the Erase and Programming Performance section for more information. 5. Does not include the preprogramming time. 6. The content in this document is Advance information fo r the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N. Parameter Description 54 MHz 66 MHz 80 MHz Unit JEDEC Standard tAVAV tWC Write Cycle Time (Note 1)M i n 8 0 n s tAVWL tAS Address Setup Time (Notes 2, 3) Synchronous Min 5n s Asynchronous 0 ns tWLAX tAH Address Hold Time (Notes 2, 3) Synchronous Min ns Asynchronous 20 tAVDP AVD# Low Time Min 8 ns tDVWH tDS Data Setup Time Min 45 20 ns tWHDX tDH Data Hold Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write Min 0 ns tCAS CE# Setup Time to AVD# Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 30 ns tWHWL tWPH Write Pulse Width High Min 20 ns tSR/W Latency Between Read and Write Operations Min 0 ns tVID VACC Rise and Fall Time Min 500 ns tVIDS VACC Setup Time (During Accelerated Programming) Min 1 µs tVCS VCC Setup Time Min 50 µs tELWL tCS CE# Setup Time to WE# Min 5 ns tAVSW AVD# Setup Time to WE# Min 5 ns tAVHW AVD# Hold Time to WE# Min 5 ns tAVSC AVD# Setup Time to CLK Min 5 ns tAVHC AVD# Hold Time to CLK Min 5 ns tCSW Clock Setup Time to WE# Min 5 ns tWEP Noise Pulse Margin on WE# Max 3 ns tSEA Sector Erase Accept Time-out Max 50 µs tESL Erase Suspend Latency Max 20 µs tPSL Program Suspend Latency Max 20 µs tASP Toggle Time During Sector Protection Typ 100 µs tPSP Toggle Time During Programming Within a Protected Sector Typ 1 µs

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 75 Advance Information Figure 12.13 Chip/Sector Erase Operation Timings OE# CE# Data Addresses AVD# WE# CLK VCC tAS tWP tAH tWC tWPH SA tVCS tCS tDH tCH In Progress tWHWH2 VA Complete VA Erase Command Sequence (last two cycles) Read Status Data tDS 10h for chip erase 555h for chip erase VIH VIL tAVDP 55h 2AAh 30h

76 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. In progress and complete refer to status of program operation. 3. A23–A14 for the WS256N (A22–A14 for the WS128N, A21–A 14 for the WS064N) are don’t care during command sequence unlock cycles. 4. CLK can be either V IL or VIH. 5. The Asynchronous programming operation is independent of th e Set Device Read Mode bit in the Configuration Register. Figure 12.14 Asynchronous Program Operation Timings OE# CE# Data Addresses AVD WE# CLK VCC 555h PD tAS tAVSW tAVHW tAH tWC tWPH PA tVCS tWP tDH tCH In Progress tWHWH1 VA Complete VA Program Command Sequence (last two cycles) Read Status Data tDS VIH VIL tAVDP A0h tCS tCAS

78 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

Notes: 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to de termine status. When the Embedded Algorithm operation is completeData# Polling outputs true data. Figure 12.17 Data# Polling Timings (During Embedded Algorithm) Notes: 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to de termine status. When the Embedded Algorithm operation is complete, . Figure 12.18 T oggle Bit Timings (During Embedded Algorithm) WE# CE# OE# High Z tOE High Z Addresses AVD# tOEH tCE tCH tOEZ tCEZ Status Data Status Data tACC VA VA Data WE# CE# OE# High Z tOE High Z Addresses AVD# tOEH tCE tCH tOEZ tCEZ Status Data Status Data tACC VA VA Data

80 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

Notes: 1. RDY(1) active with data (D8 = 1 in the Configuration Register). 2. RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register). 3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. 4. Figure shows the device not crossing a bank in the process of performing an erase or program. 5. RDY does not go low and no additional wait states are re quired if the Burst frequency is <=66 MHz and the Boundary Crossing bit (D14) in the Configuration Register is set to 0 Figure 12.21 Latency with Boundary Crossing when Frequency > 66 MHz CLK Address (hex) C124 C125 C126 C127 C127 C128 C129 C130 C131 D124 D125 D126 D127 D128 D129 D130 (stays high)AVD# RDY(1) Data OE#, CE# (stays low) Address boundary occurs every 128 words, beginning at address 00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing. 7C 7D 7E 7F 7F 80 81 82 83 latency RDY(2) latency tRACC tRACC tRACCtRACC

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 81 Advance Information Notes: 1. RDY(1) active with data (D8 = 1 in the Configuration Register). 2. RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register). 3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. 4. Figure shows the device crossing a bank in the process of performing an erase or program. 5. RDY does not go low and no additional wait states are required if the Burst frequency is < 66 MHz and the Boundary Crossing bit (D14) in the Configuration Register is set to 0. Figure 12.22 Latency with Boundary Crossing into Program/Erase Bank CLK Address (hex) C124 C125 C126 C127 C127 D124 D125 D126 D127 Read Status (stays high)AVD# RDY(1) Data OE#, CE# (stays low) Address boundary occurs every 128 words, beginning at address 00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing. 7C 7D 7E 7F 7F latency RDY(2) latency tRACC tRACC tRACC tRACC

82 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

Wait State Configuration Register Setup: D13, D12, D11 = 111 ⇒ Reserved D13, D12, D11 = 110 ⇒ Reserved D13, D12, D11 = 101 ⇒ 5 programmed, 7 total D13, D12, D11 = 100 ⇒ 4 programmed, 6 total D13, D12, D11 = 011 ⇒ 3 programmed, 5 total D13, D12, D11 = 010 ⇒ 2 programmed, 4 total D13, D12, D11 = 001 ⇒ 1 programmed, 3 total D13, D12, D11 = 000 ⇒ 0 programmed, 2 total Note: 6.Figure assumes address D0 is not at an address boundary, and wait state is set to 101 Figure 12.23 Example of Wait State Insertion Data AVD# OE# CLK 12 3 45 D0 D1 total number of clock cycles following addresses being latched Rising edge of next clock cycle following last wait state triggers next burst data number of clock cycles programmed

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 83 Advance Information Note: Breakpoints in waveforms indicate that system may alternately read array data from the non-busy bank while check- ing the status of the program or erase operation in the busy bank. The system should read status twice to ensure valid information. Figure 12.24 Back-to-Back Read/Write Cycle Timings OE# CE# WE# tOEH Data Addresses AVD# PD/30h AAh RAPA/SA tWC tDS tDH tRC tRC tOE tAS tAH tACC tOEH tWP tGHWL tOEZ tWC tSR/W Last Cycle in Program or Sector Erase Command Sequence Read status (at least two cycles) in same bank and/or array data from other bank Begin another write or program command sequence RD RA 555h RD tWPH

84 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

12.8.7 Erase and Programming Performance

Notes: 1. Typical program and erase times a ssume the following conditions: 25°C, 1.8 V VCC, 10,000 cycles; checkerboard data pattern. 2. Under worst case conditions of 90°C, V CC = 1.70 V, 100,000 cycles. 3. Typical chip programming time is cons iderably less than the maximum chip programming time listed, and is based on utilizing the Write Buffer. 4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See the Appendix for further information about command definitions. 6. Contact the local sales office for mini mum cycling endurance values in specific applications and operating conditions. 7. Refer to Application Note Erase Suspend/Resume Timing for more details. 8. Word programming specification is based upon a single word programming operation not utilizing the write buffer. 9. The content in this document is Advance information fo r the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N. Parameter Ty p (Note 1)M a x ( Note 2) Unit Comments Sector Erase Time 64 Kword V CC 0.6 3.5 s Excludes 00h programming prior to erasure (Note 4) 16 Kword V CC <0.15 2 Chip Erase Time VCC 153.6 (WS256N) 77.4 (WS128N) 39.3 (WS064N) 308 (WS256N) 154 (WS128N) 78 (WS064N) s ACC 130.6 (WS256N) 65.8 (WS128N) 33.4 (WS064N) 262 (WS256N) 132 (WS128N) 66 (WS064N) Single Word Programming Time (Note 8) V CC 40 400 µs ACC 24 240 Effective Word Programming Time utilizing Program Write Buffer V CC 9.4 94 µs ACC 6 60 Total 32-Word Buffer Programming Time VCC 300 3000 µs ACC 192 1920 Chip Programming Time (Note 3) VCC 157.3 (WS256N) 78.6 (WS128N) 39.3 (WS064N) 314.6 (WS256N) 157.3 (WS128N) 78.6 (WS064N) s Excludes system level overhead (Note 5) ACC 100.7 (WS256N) 50.3 (WS128N) 25.2 (WS064N) 201.3 (WS256N) 100.7 (WS128N) 50.3 (WS064N)

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 85 Advance Information

12.8.8 BGA Ball Capacitance

Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C; f = 1.0 MHz. 3. The content in this document is Advance information fo r the S29WS064N and S29WS128N. Content in this document is Preliminary for the S29W256N. Parameter Symbol Parameter Description Te s t S e t u p Ty p. Max Unit CIN Input Capacitance V IN = 0 5.3 6.3 pF COUT Output Capacitance V OUT = 0 5.8 6.8 pF CIN2 Control Pin Capacitance V IN = 0 6.3 7.3 pF

86 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

13 Appendix

This section contains information relating to software control or interfacing with the Flash device. For additional information and assi stance regarding software, see the Additional Resources on

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 87 Advance Information T able 13.1 Memory Array Commands Command Sequence (Notes) Cycles Bus Cycles (Notes 1–5) First Second Third Fourth Fifth Sixth Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Asynchronous Read (6)1 RA RD Reset (7) 1 XXX F0 Auto- select (8) Manufacturer ID 4 555 AA 2AA 55 [BA]555 90 [BA]X00 0001 Device ID (9) 6 555 AA 2AA 55 [BA]555 90 [BA]X01 227E BA+X0E Data BA+X0F 2200 Indicator Bits (10) 4 555 AA 2AA 55 [BA]555 90 [BA]X03 Data Program 4 555 AA 2AA 55 555 A0 PA PD Write to Buffer (11) 6 555 AA 2AA 55 PA 25 PA WC PA PD WBL PD Program Buffer to Flash 1 SA 29 Write to Buffer Abort Reset (12) 3 555 AA 2AA 55 555 F0 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Erase/Program Suspend (13) 1 BA B0 Erase/Program Resume (14) 1 BA 30 Set Configuration Register (18) 4 555 AA 2AA 55 555 D0 X00 CR Read Configuration Register 4 555 AA 2AA 55 555 C6 X00 CR CFI Query (15) 1 [BA]555 98 Unlock Bypass Mode Entry 3 555 AA 2AA 55 555 20 Program (16) 2 XXX A0 PA PD CFI (16) 1 XXX 98 Reset 2 XXX 90 XXX 00 Secured Silicon Sector Entry 3 555 AA 2AA 55 555 88 Program (17) 4 555 AA 2AA 55 555 A0 PA PD Read (17)1 00 Data Exit (17) 4 555 AA 2AA 55 555 90 XXX 00 Legend: X = Don’t care. RA = Read Address. RD = Read Data. PA = Program Address. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK, whichever occurs first. PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first. SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14; WS064N = A21–A14. BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20; WS064N = A21–A18. CR = Configuration Register data bits D15–D0. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1. Notes: 1. See Table 8.1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells indicate read cycles. 4. Address and data bits not specifie d in table, legend, or notes are don’t cares (each hex digit implies 4 bits of data). 5. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 6. No unlock or command cycles required when bank is reading array data. 7. Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock. 8. The system must provide the bank address. See Autoselect section for more information. 9. Data in cycle 5 is 2230 (WS256N), 2232 (WS064N), or 2231 (WS128N). 10. See Table 8.9 for indicator bit values. 11. Total number of cycles in the command sequence is determined by the number of words written to the write buffer. 12. Command sequence resets device for next command after write- to-buffer operation. 13. System may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 14. Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 15. Command is valid when device is ready to read array data or when device is in autoselect mode. Address equals 55h on all future devices, but 555h for WS256N/128N/064N. 16. Requires Entry command sequence prior to execution. Unlock Bypass Reset command is required to return to reading array data. 17. Requires Entry command sequence prior to execution. Secured Silicon Sector Exit Reset command is required to exit this mode; device may otherwise be placed in an unknown state. 18. Requires reset command to configure the Configuration Register.

88 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

T able 13.2 Sector Protection Commands Command Sequence (Notes) Cycles Bus Cycles (Notes 1–4) First Second Third Fourth Fifth Sixth Seventh Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Lock Register Bits Command Set Entry (5) 3 555 AA 2AA 55 555 40 Program (6, 12) 2 XX A0 77/00 data Read (6)1 77 data Command Set Exit (7) 2 XX 90 XX 00 Password Protection Command Set Entry (5) 3 555 AA 2AA 55 555 60 Program [0-3] (8) 2 XX A0 00 PWD[0-3] Unlock 7 00 25 00 03 00 PWD0 01 PWD1 02 PWD2 03 PWD3 00 29 Command Set Exit (7) 2 XX 90 XX 00 Non-Volatile Sector Protection (PPB) Command Set Entry (5) 3 555 AA 2AA 55 [BA]555 C0 PPB Program (10) 2 XX A0 SA 00 All PPB Erase (10, 11) 2 XX 80 00 30 PPB Status Read 1 SA RD(0) Command Set Exit (7) 2 XX 90 XX 00 Global Volatile Sector Protection Freeze (PPB Lock) Command Set Entry (5) 3 555 AA 2AA 55 [BA]555 50 PPB Lock Bit Set 2 XX A0 XX 00 PPB Lock Bit Status Read 1 BA RD(0) Command Set Exit (7) 2 XX 90 XX 00 Volatile Sector Protection (DYB) Command Set Entry (5) 3 555 AA 2AA 55 [BA]555 E0 DYB Set 2 XX A0 SA 00 DYB Clear 2 XX A0 SA 01 DYB Status Read 1 SA RD(0) Command Set Exit (7) 2 XX 90 XX 00 Legend: X = Don’t care. RA = Address of the memory location to be read. PD(0) = Secured Silicon Sector Lock Bit. PD(0), or bit[0]. PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must be set to ‘0’ for protection while PD(2), bit[2] must be left as ‘1’. PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must be set to ‘0’ for protection while PD(1), bit[1] must be left as ‘1’. PD(3) = Protection Mode OTP Bit. PD(3) or bit[3]. SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14; WS064N = A21–A14. BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20; WS064N = A21–A18. PWD3–PWD0 = Password Data. PD3–PD0 present four 16 bit combinations that represent the 64-bit Password PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity. PWD = Password Data. RD(0), RD(1), RD(2) = DQ0, DQ1, or DQ2 protection indicator bit. If protected, DQ0, DQ1, or DQ2 = 0. If unprotected, DQ0, DQ1, DQ2 = 1. Notes: 1. All values are in hexadecimal. 2. Shaded cells indicate read cycles. 3. Address and data bits not specified in table, legend, or notes are don’t cares (each hex digit implies 4 bits of data). 4. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 5. Entry commands are required to en ter a specific mode to enable instructions only available within that mode. 6. If both the Persistent Protection Mode Locking Bit and the Password Protection Mode Locking Bit are set at the same time, the command operation aborts and returns the device to the default Persistent Sector Protection Mode during 2nd bus cycle. Note that on all future devices, addresses equal 00h, but is currently 77h for the WS256N only. See Table 9.1 and Table 9.2 for explanation of lock bits. 7. Exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state. 8. Entire two bus-cycle sequence must be entered for each portion of the password. 9. Full address range is requ ired for reading password. 10. See Figure 9.2 for details. 11. The All PPB Erase command pre-programs all PPBs before erasure to prevent over-erasure. 12. The second cycle address for the lock register program operation is 77 for S29Ws256N; however, for WS128N and Ws064N this address is 00.

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 89 Advance Information

13.1 Common Flash Memory Interface

The Common Flash Interface (CFI) specification outlines device and host system software inter- rogation handshake, which allows specific vendor-specified soft-ware algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-indepen- dent, and forward- and back-ward-compatible fo r the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address (BA)555h any time the device is ready to read array data. The system can read CFI in- formation at the addresses given in Tables 13.3–13.6) within that bank. All reads outside of the CFI address range, within the bank, returns non-valid data. Reads from other banks are allowed, writes are not. To terminate reading CFI data, the system must write the reset command. The following is a C source code example of using the CFI Entry and Exit functions. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. /* Example: CFI Entry command */ *( (UINT16 *)bank_addr + 0x555 ) = 0x0098; /* write CFI entry command */ /* Example: CFI Exit command */ *( (UINT16 *)bank_addr + 0x000 ) = 0x00F0; /* write cfi exit command */ For further information, please refer to the CFI Specification (see JEDEC publications JEP137-A and JESD68.01and CFI Publication 100). Please contact your sales office for copies of these documents. T able 13.3 CFI Query Identification String Addresses Data Description 10h 11h 12h 0051h 0052h 0059h Query Unique ASCII string QRY 13h 14h 0002h 0000h Primary OEM Command Set 15h 16h 0040h 0000h Address for Primary Extended Table 17h 18h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) T able 13.4 System Interface String Addresses Data Description 1Bh 0017h VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 0019h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 0000h V PP Min. voltage (00h = no VPP pin present) 1Eh 0000h V PP Max. voltage (00h = no VPP pin present) 1Fh 0006h Typical timeout per single byte/word write 2 N µs 20h 0009h Typical timeout for Min. size buffer write 2 N µs (00h = not supported) 21h 000Ah Typical timeout per individual block erase 2 N ms 22h 0000h Typical timeout for full chip erase 2 N ms (00h = not supported) 23h 0004h Max. timeout for byte/word write 2 N times typical 24h 0004h Max. timeout for buffer write 2 N times typical 25h 0003h Max. timeout per individual block erase 2 N times typical 26h 0000h Max. timeout for full chip erase 2 N times typical (00h = not supported)

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Ta bl e 1 3 . 5 Device Geometry Definition Addresses Data Description 27h 0019h (WS256N) 0018h (WS128N) 0017h (WS064N) Device Size = 2 N byte 28h 29h 0001h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 0006h 0000h Max. number of bytes in multi-byte write = 2 N (00h = not supported) 2Ch 0003h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 0003h 0000h 0080h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 00FDh (WS256N) 007Dh (WS128N) 003Dh (WS064N) Erase Block Region 2 Information 32h 33h 34h 0000h 0000h 0002h 35h 36h 37h 38h 0003h 0000h 0080h 0000h Erase Block Region 3 Information 39h 3Ah 3Bh 3Ch 0000h 0000h 0000h 0000h Erase Block Region 4 Information T able 13.6 Primary Vendor-Specific Extended Query Addresses Data Description 40h 41h 42h 0050h 0052h 0049h Query-unique ASCII string PRI 43h 0031h Major version number, ASCII 44h 0034h Minor version number, ASCII 45h 0100h Address Sensitive Unlock (Bits 1-0), 0 = Required, 1 = Not Required Silicon Technology (Bits 5-2) 0100 = 0.11 µm 46h 0002h Erase Suspend, 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 0001h Sector Protect, 0 = Not Supported, X = Number of sectors in per group 48h 0000h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 0008h Sector Protect/Unprotect scheme 08 = Advanced Sector Protection 4Ah 00F3h (WS256N) 007Bh (WS128N) 003Fh (WS064N) Simultaneous Operation Number of Sectors in all banks except boot bank 4Bh 0001h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 0000h Page Mode Type, 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page 4Dh 0085h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Eh 0095h ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Fh 0001h Top/Bottom Boot Sector Flag 0001h = Dual Boot Device 50h 0001h Program Suspend. 00h = not supported

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 91 Advance Information 51h 0001h Unlock Bypass, 00 = Not Supported, 01=Supported 52h 0007h Secured Silicon Sector (Customer OTP Area) Size 2 N bytes 53h 0014h Hardware Reset Low Time-out during an embedded algorithm to read mode Maximum 2 N ns 54h 0014h Hardware Reset Low Time-out not during an embedded algorithm to read mode Maximum 2 N ns 55h 0005h Erase Suspend Time-out Maximum 2 N ns 56h 0005h Program Suspend Time-out Maximum 2 N ns 57h 0010h Bank Organization: X = Number of banks 58h 0013h (WS256N) 000Bh (WS128N) 0007h (WS064N) Bank 0 Region Information. X = Number of sectors in bank 59h 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 1 Region Information. X = Number of sectors in bank 5Ah 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 2 Region Information. X = Number of sectors in bank 5Bh 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 3 Region Information. X = Number of sectors in bank 5Ch 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 4 Region Information. X = Number of sectors in bank 5Dh 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 5 Region Information. X = Number of sectors in bank 5Eh 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 6 Region Information. X = Number of sectors in bank 5Fh 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 7 Region Information. X = Number of sectors in bank 60h 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 8 Region Information. X = Number of sectors in bank 61h 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 9 Region Information. X = Number of sectors in bank 62h 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 10 Region Information. X = Number of sectors in bank 63h 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 11 Region Information. X = Number of sectors in bank 64h 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 12 Region Information. X = Number of sectors in bank 65h 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 13 Region Information. X = Number of sectors in bank 66h 0010h (WS256N) 0008h (WS128N) 0004h (WS064N) Bank 14 Region Information. X = Number of sectors in bank 67h 0013h (WS256N) 000Bh (WS128N) 0007h (WS064N) Bank 15 Region Information. X = Number of sectors in bank T able 13.6 Primary Vendor-Specific Extended Query (Continued) Addresses Data Description

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14 Commonly Used T erms

Te r m D e f i n i t i o n ACC ACCelerate. A special purpose input signal which allows for faster programming or erase operation when raised to a specified voltage above VCC. In some devices ACC may protect all sectors when at a low voltage. Amax Most significant bit of the address input [A23 for 256Mbit, A22 for128Mbit, A21 for 64Mbit] Amin Least significant bit of the address input signals (A0 for all devices in this document). Asynchronous Operation where signal relationships are based only on propagation delays and are unrelated to synchronous control (clock) signal. Autoselect Read mode for obtaining manufacturer and device information as well as sector protection status. Bank Section of the memory array consisting of multiple consecutive sectors. A read operation in one bank, can be independent of a program or erase operation in a different bank for devices that offer simultaneous read and write feature. Boot sector Smaller size sectors located at the top and or bottom of Flash device address space. The smaller sector size allows for finer granularity control of erase and protection for code or parameters used to initiate system operation after power-on or reset. Boundary Location at the beginning or end of series of memory locations. Burst Read See synchronous read. Byte 8 bits CFI Common Flash Interface. A Flash memory industry standard specification [JEDEC 137- A and JESD68.01] designed to allow a system to interrogate the Flash to determine its size, type and other performance parameters. Clear Zero (Logic Low Level) Configuration Register Special purpose register which must be programmed to enable synchronous read mode Continuous Read Synchronous method of burst read whereby the device reads continuously until it is stopped by the host, or it has reached the highest address of the memory array, after which the read address wraps around to the lowest memory array address Erase Returns bits of a Flash memory array to th eir default state of a logical One (High Level). Erase Suspend/Erase Resume Halts an erase operation to allow reading or programming in any sector that is not selected for erasure BGA Ball Grid Array package. Spansion LLC offers two variations: Fortified Ball Grid Array and Fine-pitch Ball Grid Array. See the specific package drawing or connection diagram for further details. Linear Read Synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with or without wraparound before requiring a new initial address MCP Multi-Chip Package. A method of combining integrated circuits in a single package by stacking multiple die of the same or different devices. Memory Array The programmable area of the product available for data storage. MirrorBit™ Technology Spansion™ trademarked technology for storin g multiple bits of data in the same transistor.

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 93 Advance Information Page Group of words that may be accessed more rapidly as a group than if the words were accessed individually. Page Read Asynchronous read operation of several words in which the first word of the group takes a longer initial access time and subsequent words in the group take less page access time to be read. Different words in the group are accessed by changing only the least significant address lines. Password Protection Sector protection method which uses a programmable password, in addition to the Persistent Protection method, for protection of sectors in the Flash memory device. Persistent Protection Sector protection method that uses commands and only the standard core voltage supply to control protection of sectors in the Flash memory device. This method replaces a prior technique of requiring a 12V supply to control the protection method. Program Stores data into a Flash memory by selectively clearing bits of the memory array in order to leave a data pattern of ones and zeros. Program Suspend/Program Resume Halts a programming operation to read data from any location that is not selected for programming or erase. Read Host bus cycle that causes the Flash to output data onto the data bus. Registers Dynamic storage bits for holding device control information or tracking the status of an operation. Secured Silicon Secured Silicon. An area consisting of 256 bytes in which any word may be programmed once, and the entire area may be protected once from any future programming. Information in this area may be programmed at the factory or by the user. Once programmed and protected there is no way to change the secured information. This area is often used to store a software readable identification such as a serial number. Sector Protection Use of one or more control bits per sector to indicate whether each sector may be programmed or erased. If the Protection bit for a sector is set the embedded algorithms for program or erase ignores program or erase commands related to that sector. Sector An Area of the memory array in which all bits must be erased together by an erase operation. Simultaneous Operation Mode of operation in which a host system may issue a program or erase command to one bank, that embedded algorithm operation may then proceed while the host immediately follows the embedded algorithm command with reading from another bank. Reading may continue concurrently in any bank other than the one executing the embedded algorithm operation. Synchronous Operation Operation that progresses only when a timing signal, known as a clock, transitions between logic levels (that is, at a clock edge). VersatileIO™ (V IO) Separate power supply or voltage reference signal that allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs. Unlock Bypass Mode that facilitates faster program times by reducing the number of command bus cycles required to issue a write operation command. In this mode the initial two Unlock write cycles, of the usual 4 cycle Program command, are not required – reducing all Program commands to two bus cycles while in this mode. Word Two contiguous bytes (16 bits) located at an even byte boundary. A double word is two contiguous words located on a two word boundary. A quad word is four contiguous words located on a four word boundary. Te r m D e f i n i t i o n

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Special burst read mode where the read address wraps or returns back to the lowest address boundary in the selected range of words, after reading the last Byte or Word in the range, e.g. for a 4 word range of 0 to 3, a read beginning at word 2 would read words in the sequence 2, 3, 0, 1. Write Interchangeable term for a program/erase operation where the content of a register and or memory location is being altered. The term write is often associated with writing command cycles to enter or exit a particular mode of operation. Write Buffer Multi-word area in which multiple words may be programmed as a single operation. A Write Buffer may be 16 to 32 words long and is located on a 16 or 32 word boundary respectively. Write Buffer Programming Method of writing multiple words, up to the maximum size of the Write Buffer, in one operation. Using Write Buffer Programming results in ≥ 8 times faster programming time than by using single word at a time programming commands. Write Operation Status Allows the host system to determine the status of a program or erase operation by reading several special purpose register bits. Te r m D e f i n i t i o n

Publication Number S75WS-N-00 Revision A Amendment 0 Issue Date February 17, 2005 DATA SHEET S29RS512N 512 Megabit (32 M x 16-Bit) CMOS 1.8 Volt-only Read/Write, Burst Mode, Mass Storage Flash Memory for Multi-Chip Products (MCP) Distinctive Characteristics Architectural Advantages „ Single 1.8 volt read, program and erase (1.65 to 1.95 volt) „ Manufactured on 0.11 µm MirrorBitTM process Read/Write operation — Zero latency between read and write operations „ Programable Burst Interface — 2 Modes of Burst Read Operation — Linear Burst: 8, 16, and 32 words with or without wrap-around — Continuous Sequential Burst „ Sector Architecture — one-hundred-twenty-eight 256 Kword sectors „ 100,000 erase cycle per sector typical „ 20-year data retention typical Performance Charcteristics „ Read access times at 80/66/54 MHz — Burst access times of 9.1/11.2/13.5 ns — Synchronous latency of 148 ns — Asynchronous random access times of 143 ns „ High Performance — Typical word programming time of 40 µs — Typical effective word programming time of 9.4 µs utilizing a 32-Word Write Buffer at Vcc Level — Typical effective word programming time of 6 µs utilizing a 32-Word Write Buffer at ACC Level — Typical 2 s sector erase time for 256 Kword sectors „ Power dissipation (typical values, CL = 30 pF) @ 80 MHz — Continuous Burst Mode Read: 35 mA — Program: 19 mA —E r a s e : 1 9 m A — Standby mode: 20 µA Hardware Features „ Sector Protection — Dynamic Protection Bits (DYB) are assigned to every sector — A command sector protection to lock/unlock combinations of individual sectors to prevent/allow program or erase operations within that sector. „ Handshaking feature available — Provides host system with minimum possible latency by monitoring RDY „ ACC input: Acceleration function reduces programming time in a factory setting „ Low VCC write inhibit Software Features „ Software command set compatible with JEDEC 42.4 standards „ Data# Polling and toggle bits — Provides a software method of detecting program and erase operation completion „ Erase Suspend/Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation „ Program Suspend/Resume — Suspends a programming operation to read data from a sector other than the one being programmed, then resume the programming operation „ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences Additional Features „ Program Operation — Ability to perform sync hronous and asynchronous write operation independent of burst control register setting

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The S29RS512N is a 512 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory device, organized as 33,554,432words of 16 bits each. This device uses a single VCC of 1.65 to 1.95 V to read, program, and erase the memory array. A 9.0-volt VHH on ACC may be used for faster program performance in a factory setting environment. The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output En- able (OE#) to control asynchronous read and write operations. For burst operations, the device additionally requires Ready (RDY), and Clock (CLK ). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/microcontrollers for high performance read operations. The burst read mode feature gives system designers flexibility in the interface to the device. The user can preset the burst length and then wrap or non-wrap through the same memory space, or read the currently addressable flash array block in continuous mode. The rising clock edge initiates burst accesses and determines when data will be output. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Em- bedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster program times by requiring only two write cycles to program data instead of four. Additionally, Write Buffer Pro- gramming is available on this family of devices. This feature provides superior programming performance by grouping locations being programmed. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not al- ready programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The Program Suspend/Program Resume feature enables the user to put program on hold to read data from any sector that is not selected for programming. If a read is needed from the Dy- namic Protection area after a program suspend, then the user must use the proper command sequence to enter and exit this region. The program suspend/resume functionality is also avail- able when programming in erase suspend (1 level depth only). The Erase Suspend/Erase Resume feature enables the user to put erase on hold to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the Dynamic Protection area, after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A sys- tem reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory device. The host system can detect whether a memory array program or erase operation is complete by using the device status bit DQ7 (Data# Polling), DQ6/DQ2 (toggle bits), DQ5 (exceeded timing limit), DQ3 (sector erase start timeout state indicator), and DQ1 (write to buffer abort). After a program or erase cycle has been completed, the device automatically returns to reading array data.

February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 97 Data Sheet The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors [The device is fully erased when shipped from the factory]. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. When the ACC pin = VIL, the entire flash memory array is protected. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes. Spansion’s Flash technology combines years of Flash memory manufacturing experience to pro- duce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector. The data is programmed using hot electron injection.

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15 Product Selector Guide

AsynchronousSpeed Option 80 MHz 66 MHz 54 MHz Max Latency, ns (tIACC) 148 160 160 Max Access Time, ns (tACC) 143 Max Burst Access Time, ns (tBACC) 9.1 11.2 13.5 Max CE# Access, ns (tCE) 148 Max OE# Access, ns (tOE) 9.1 11.2 13.5 Max OE# Access, ns (t OE)9 . 1

February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 99 Data Sheet

16 Block Diagram

WE# RESET# ACC CE# OE# DQ15–DQ0 Data Latch Y-Gating Cell Matrix Address Latch Amax–A0* RDY Buffer RDY Burst State Control Burst Address Counter AVD# CLK Amax = A24

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17 Logic Symbol

Note: Amax = A24 for 512Mb. 25 or 24 DQ15–DQ0 Amax– CE# OE# WE# RESET# CLK RDY AVD# ACC

February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 101 Data Sheet

18 Device Bus Operations

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addres- sable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 18.1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. T able 18.1 Device Bus Operations Legend: L = Logic 0, H = Logic 1, X = Don’t Care.

18.1 Requirements for Asynchronous Read Operation (Non-Burst)

To read data from the memory array, the system must first assert a valid address on Amax–A0, while driving AVD# and CE# to VIL. WE# should remain at VIH. The rising edge of AVD# latches the address. The data will appear on DQ15–DQ0. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from the stable CE# to valid data at the outputs. The output enable access time (t OE) is the delay from the falling ed ge of OE# to valid data at the output. The internal state machine is set for reading ar ray data in asynchrono us mode upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory con- tent occurs during the power transition. Operation CE# OE# WE# Addresses DQ15–0 RESET# CLK AVD# Asynchronous Read - Addresses Latched L L H Addr In I/O H X Asynchronous Read - Addresses Steady State L L H Addr In I/O H X L Asynchronous Write L H L Addr In I/O H X L Synchronous Write L H L Addr In I/O H Standby (CE#) H X X X HIGH Z H X X Hardware Reset X X X X HIGH Z L X X Burst Read Operations Load Starting Burst Address L X H Addr In X H Advance Burst to next address with appropriate Data presented on the Data Bus LLH X Burst Data Out HH Terminate current Burst read cycle H X H X HIGH Z H X Terminate current Burst read cycle via RESET# X X H X HIGH Z L X X Terminate current Burst read cycle and start new Burst read cycle L X H Addr In I/O H

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18.2 Requirements for Synchronous (Burst) Read Operation

The device is capable of continuous sequential burst operation and linear burst operation of a pre- set length. When the device first powers up, it is enabled for asynchronous read operation. Prior to entering burst mode, the system should determine how many wait states are desired for the initial word (tIACC) of each burst access, what mode of burst operation is desired and how the RDY signal will transition with valid data. The system would then write the configuration register command sequence. See Set Configuration Register Command Sequence for further details. Table 2-4 shows the address latency scheme for varying frequencies. Address Latency Scheme for < 84Mhz The initial word is output tIACC after the rising edge of the first CLK cycle. Subsequent words are output tBACC after the rising edge of each successive clock cycle, which automatically increments the internal address counter. Note that the device has a fixed internal address boundary that oc- curs every 512 words and there is a boundary crossing latency of 4/8 wait states, when the device is operating at frequencies lower than 56/80Mhz respectively. During the time the device is outputting data with the starting burst address not divisible by four, additional waits are required. For example, if the device is operating at frequency of 80Mhz and if the starting burst address is divisible by four A1:0 = 00, two additional wait state is required. T able 18.2 Address Latency Scheme for < 56Mhz Initial Addr Cycle X X+1 X+2 X+3 Add ws X+4 X+5 X+6

00 D0 D1 D2 D3 0ws D4 D5 D6

01 D1 D2 D3 1ws 0ws D4 D5 D6

10 D2 D3 1ws 1ws 0ws D4 D5 D6

11 D3 1ws 1ws 1ws 0ws D4 D5 D6

T able 18.3 Address Latency Scheme for < 70Mhz Initial Addr Cycle X X+1 X+2 X+3 Add ws X+4 X+5 X+6

00 D0 D1 D2 D3 1ws D4 D5 D6

01 D1 D2 D3 1ws 1ws D4 D5 D6

10 D2 D3 1ws 1ws 1ws D4 D5 D6

11 D3 1ws 1ws 1ws 1ws D4 D5 D6

T able 18.4 Address Latency Scheme for < 84Mhz Initial Addrs Cycle X X+1 X+2 X+3 Add ws X+4 X+5 X+6

00 D0 D1 D2 D3 2ws D4 D5 D6

01 D1 D2 D3 1ws 2ws D4 D5 D6

10 D2 D3 1ws 1ws 2ws D4 D5 D6

11 D3 1ws 1ws 1ws 2ws D4 D5 D6

February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 103 Data Sheet If the starting burst address is at address A1:0 = 01, 10, 11 then three, four or five wait states are required, respectively, until data D4 is read and burst sequence becomes linear. Please refer to Table 18.4 for further details. The RDY output indicates this condition to the system by deasserting.

18.2.1 Continuous Burst

The device will continue to output sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location, until the system drives CE# high, RE- SET# low, or AVD# low in conjunction with a new address. See Table 18.1. 18.2.2 8-, 16-, and 32-Word Linear Burst with Wrap Around The remaining three modes are of the linear wrap around design, in which a fixed number of words are read from consecutive addresses. In each of these modes, the burst addresses read are determined by the group within which the starting address falls. The groups are sized accord- ing to the number of words read in a single burst sequence for a given mode (see Table 18.5.). As an example: if the starting address in the 8-word mode is 3ch, the address range to be read would be 38-3Fh, and the burst sequence would be 3C, 3D, 3E, 3F, 38, 39, 3A, 3Bh. if wrap around is enable. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group and stops at the group size, terminating the burst read. In a similar fashion, the 16-word and 32- word Linear Wrap modes begin their burst se- quence on the starting address written to the device, and then wrap back to the first address in the selected address group. Note that in these three burst read modes the address pointer does not cross the boundary that occurs every 512 words; thus, no wait states are in- serted (except during the initial access). (see Figure 25.4) 18.2.3 8-, 16-, and 32-Word Linear Burst without Wrap Around If wrap around is not enabled, 8-word, 16-word, or 32-word burst will execute linearly up to word boundary. The burst will stop after 8, 16, or 32 addresses and will not wrap around to the first address of the selected group. As an example: if the starting address in the 8-word mode is 3ch, the address range to be read would be 39-40h, and the burst sequence would be 3C, 3D-3E-3F- 40-41-42-43h if wrap around is not enabled. The next address to be read will require a new ad- dress and AVD# pulse. The address range would stay within the address block, causing address FFFFh to be followed by 0000h. Note that in this burst mode, the address pointer may cross the boundary that occurs every 128 words.

18.3 Configuration Register

The device uses a configuration register to se t the various burst parameters: number of wait states, burst read mode, RDY configuration, and synchronous mode active.

18.4 RDY: Ready

The RDY is a dedicated output that, when the device is configured in the Synchronous mode, in- dicates (when at logic low) the system should wait 1 clock cycle before expecting the next word of data. The RDY pin is only controlled by CE#. Using the RDY Configuration Command Sequence, RDY can be set so that a logic low indicates the system should wait 2 clock cycles before expecting valid data. T able 18.5 Burst Address Groups Mode Group Size Group Address Ranges 8-word 8 words 0-7h, 8-Fh, 10-17h,... 16-word 16 words 0-Fh, 10-1Fh, 20-2Fh,... 32-word 32 words 00-1Fh, 20-3Fh, 40-5Fh,...

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The following conditions cause the RDY output to be low: during the initial access (in burst mode), and at the boundary crossing, that occurs every 512 words beginning with address 1FFh.

18.5 Handshaking

The device is equipped with a handshaking feature that allows the host system to simply monitor the RDY signal from the device to determine when the burst data is ready to be read. The host system should use the programmable wait state configuration to set the number of wait states for optimal burst mode operation. The initial word of burst data is indicated by the rising edge of RDY after OE# goes low. For optimal burst mode performance, the host system must set the appropriate number of wait states in the flash device depending on clock frequency. See Set Configuration Register Command Sequence and Requirements for Synchronous (Burst) Read Operation for more information.

18.6 Writing Commands/Command Sequences

The device has the capability of performing an asynchronous or synchronous write operation. While the device is configured in Asynchronous read it is able to perform Asynchronous write op- erations only. CLK is ignored when the device is configured in the Asynchronous mode. When in the Synchronous read mode configuration, the device is able to perform both Asynchronous and Synchronous write operations. CLK and AVD# address latch is supported in the Synchronous pro- gramming mode. During a synchronous write operation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to V IL, and OE# to VIH when providing an address to the de- vice, and drive WE# and CE# to VIL, and OE# to VIH. when writing commands or data. During an asynchronous write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE# (see ). The device features an Unlock Bypass mode to facilitate faster programming. Once the device en- ters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. An erase operation can erase one sector, multiple sectors or the entire device. Table 19.6 indicates the address space that each sector occupies. A sector address is the address bits required to uniquely select a sector. ICC2 in the DC Characteristics section represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations.

18.7 Accelerated Program/Chip Erase Operations

The device offers accelerated program and accelerated chip erase operations through the ACC functionACC is intended to allow faster manufactu ring throughput at the factory and not to be used in system operations. The system can use the Write Buffer Load command sequence. Note that if a Write-to-Buffer- Abort Reset is required, the full 3-cycle RESET command sequence must be used to reset the device. Removing VHH from the ACC input, upon completion of the embedded program or erase operation, returns the device to normal operation. Note that sectors must be unlocked prior to raising ACC to V HH. When at V IL, ACC locks all sectors. ACC should be at V IH for all other conditions. number loaded = the number of locations to program minus 1. For example, if the system will program 6 address locations, then 05h should be written to the device.)

February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 105 Data Sheet The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed, and selects the write-buffer-page address. All subsequent address/data pairs must fall within the selected-write-buffer-page where Amax = 24 for RS512N. The write-buffer-page is selected by addresses Amax - A5. The write-buffer-page addresses must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer-pages. This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write- buffer-page, the operation will ABORT.) After writing the Starting Address/Data pair, the system then writes the remaining address/data paris into the write buffer. Write buffer locations may be loaded in any order. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. Also, the last data loaded at a location before the Program Buffer to Flash confirm command will be programmed into the device. It is the software’s responsibility to comprehend ramifications of loading a write-buffer location more than once. The counter decrements for each data load operation, not for each unique write- buffer-address location. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the Sector Address. Any other address/data write com- binations will abort the Write Buffer Programming operation. The device then goes busy. The Data Bar polling techniques should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer embedded programming operation can be suspended using the standard sus- pend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device will return to READ mode. The Write Buffer Programming Sequence can be ABORTED in the following ways: „ Load a value that is greater than the page buffer size during the Number of Locations to Pro- gram step. „ Write to an address in a sector different than the one specified during the Write-Buffer-Load command. „ Write an Address/Data pair to a different wr ite-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. „ Write data other than the Confirm Command after the specified number of data load cycles. The ABORT condition is indicated by DQ1 = 1, DQ7 = Data# (for the last address location loaded), DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation was ABORTED. A Write-to-Buffer-Abort reset command sequence is required when using the Write- Buffer-Programming features in Unlock Bypass mode. [Use of the write buffer is strongly rec- ommended for programming when multiple words are to be programmed.] from the internal register (which is separate from the memory array)

18.8 Dynamic Sector Protection

The device offers data protection at the sector level and the DYB associated command sequences disables or re-enables both program and erase operations in any sector or sector group. „ Dynamically Locked—The sector is protected and can be changed by a simple command „ Unlocked—The sector is unprotected an d can be changed by a simple command

106 S75WS256Nxx Based MCPs S75WS-N-00_00_A0 February 17, 2005

18.8.1 Dynamic Protection Bit (DYB)

A volatile protection bit is assigned for each sector. After power-up or hardware reset, the con- tents of all DYBs is cleared erased to 1. In other words, the DYB po wers-up in an unprotected state. Each DYB is individually modifiable through the DYB Write Command. The Protection State for each sector is determined by the DYB related to that sector. The DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write com- mand sequences, the DYBs will be set (programmed to 0) or cleared (erased to 1), thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed.

18.9 Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC. The device requires standard access time (t CE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics section represents the standby current specification.

18.10 Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. While in asynchronous mode, the device automatically enables this mode when addresses remain stable for tACC + 20 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Stan- dard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. While in synchronous mode, the Auto- matic Sleep Mode is disabled. Note that a new burst operation is required to provide new data. ICC6 in the DC Characteristics section represents the automatic sleep mode current specification.

18.11 RESET#: Hardware Reset Input

The RESET# input provides a hard ware method of resetting the device to reading array data. When RESET# is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/ write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS, the standby cur- rent will be greater. RESET# may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted t RP operation, the device requires a time of tRH + tRP before the device is ready to read data again. If RESET# is asserted when a program or erase operation is not exe- cuting, the reset operation is completed within a time of tRP (not during Embedded Algorithms). The system can read data tRH after RESET# returns to VIH.

February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 107 Data Sheet Refer to the Synchronous/Burst Read section for RESET# parameters and to Figure 25.9 for the timing diagram.

18.12 Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state.

18.13 Hardware Data Protection

The following hardware data prot ection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise.

18.13.1 Low V CC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO.

18.13.2 Write Pulse Glitch Protection

Noise pulses do not initiate a write cycle.

18.13.3 Logical Inhibit

Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.

108 S75WS256Nxx Based MCPs S75WS-N-00_00_A0 February 17, 2005

19 Sector Address / Memory Address Map

T able 19.6 Sector Address / Memory Address Map for the RS512N Sector Sector Size (A24-A0) Address Range Sector Sector Size (A24-A0) Address Range SA0 256 Kwords 0000000h-003FFFFh SA64 256 Kwords 1000000h-103FFFFh SA1 256 Kwords 0040000h-007FFFFh SA65 256 Kwords 1040000h-107FFFFh SA2 256 Kwords 0080000h-00BFFFFh SA66 256 Kwords 1080000h-10BFFFFh SA3 256 Kwords 00C0000h-00FFFFFh S A67 256 Kwords 10C0000h-10FFFFFh SA4 256 Kwords 0100000h-013FFFFh SA68 256 Kwords 1100000h-113FFFFh SA5 256 Kwords 0140000h-017FFFFh SA69 256 Kwords 1140000h-117FFFFh SA6 256 Kwords 0180000h-01BFFFFh SA70 256 Kwords 1180000h-11BFFFFh SA7 256 Kwords 01C0000h-01FFFFFh S A71 256 Kwords 11C0000h-11FFFFFh SA8 256 Kwords 0200000h-023FFFFh SA72 256 Kwords 1200000h-123FFFFh SA9 256 Kwords 0240000h-027FFFFh SA73 256 Kwords 1240000h-127FFFFh SA10 256 Kwords 0280000h-02BFFFFh SA74 256 Kwords 1280000h-12BFFFFh SA11 256 Kwords 02C0000h-02FFFFFh S A75 256 Kwords 12C0000h-12FFFFFh SA12 256 Kwords 0300000h-033FFFFh SA76 256 Kwords 1300000h-133FFFFh SA13 256 Kwords 0340000h-037FFFFh SA77 256 Kwords 1340000h-137FFFFh SA14 256 Kwords 0380000h-03BFFFFh SA78 256 Kwords 1380000h-13BFFFFh SA15 256 Kwords 03C0000h-03FFFFFh S A79 256 Kwords 13C0000h-13FFFFFh SA16 256 Kwords 0400000h-043FFFFh SA80 256 Kwords 1400000h-143FFFFh SA17 256 Kwords 0440000h-047FFFFh SA81 256 Kwords 1440000h-147FFFFh SA18 256 Kwords 0480000h-04BFFFFh SA82 256 Kwords 1480000h-14BFFFFh SA19 256 Kwords 04C0000h-04FFFFFh S A83 256 Kwords 14C0000h-14FFFFFh SA20 256 Kwords 0500000h-053FFFFh SA84 256 Kwords 1500000h-153FFFFh SA21 256 Kwords 0540000h-057FFFFh SA85 256 Kwords 1540000h-157FFFFh SA22 256 Kwords 0580000h-05BFFFFh SA86 256 Kwords 1580000h-15BFFFFh SA23 256 Kwords 05C0000h-05FFFFFh S A87 256 Kwords 15C0000h-15FFFFFh SA24 256 Kwords 0600000h-063FFFFh SA88 256 Kwords 1600000h-163FFFFh SA25 256 Kwords 0640000h-067FFFFh SA89 256 Kwords 1640000h-167FFFFh SA26 256 Kwords 0680000h-06BFFFFh SA90 256 Kwords 1680000h-16BFFFFh SA27 256 Kwords 06C0000h-06FFFFFh S A91 256 Kwords 16C0000h-16FFFFFh SA28 256 Kwords 0700000h-073FFFFh SA92 256 Kwords 1700000h-173FFFFh SA29 256 Kwords 0740000h-077FFFFh SA93 256 Kwords 1740000h-177FFFFh SA30 256 Kwords 0780000h-07BFFFFh SA94 256 Kwords 1780000h-17BFFFFh SA31 256 Kwords 07C0000h-07FFFFFh S A95 256 Kwords 17C0000h-17FFFFFh SA32 256 Kwords 0800000h-083FFFFh SA96 256 Kwords 1800000h-183FFFFh SA33 256 Kwords 0840000h-087FFFFh SA97 256 Kwords 1840000h-187FFFFh SA34 256 Kwords 0880000h-08BFFFFh SA98 256 Kwords 1880000h-18BFFFFh SA35 256 Kwords 08C0000h-08FFFFFh S A99 256 Kwords 18C0000h-18FFFFFh SA36 256 Kwords 0900000h-093FFFFh SA100 256 Kwords 1900000h-193FFFFh SA37 256 Kwords 0940000h-097FFFFh SA101 256 Kwords 1940000h-197FFFFh SA38 256 Kwords 0980000h-09BFFFFh SA102 256 Kwords 1980000h-19BFFFFh SA39 256 Kwords 09C0000h-09FFFFFh S A103 256 Kwords 19C0000h-19FFFFFh

February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 109 Data Sheet

19.1 Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data in asynchronous mode. The device is ready to read array data after com- pleting an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same device. After completing a programming operation in the Erase Suspend mode, the system may once again read array data from any non-erase-suspended sector within the same device. See the Erase Suspend/Erase Resume Commands section for more information. After the device accepts a Program Suspend command, the device enters the program-suspend- read mode, after which the system can read data from any non-program-suspended sector within the device. See Program Suspend/Program Resume Commands for more information. The system must issue the reset command to return device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the device is in the au- toselect mode. See the Reset Command section for more information. If DQ1 goes high during Write Buffer Programming, the system must issue the Write Buffer Abort Reset command. SA40 256 Kwords 0A00000h-0A3FFFFh SA104 256 Kwords 1A00000h-1A3FFFFh SA41 256 Kwords 0A40000h-0A7FFFFh SA105 256 Kwords 1A40000h-1A7FFFFh SA42 256 Kwords 0A80000h-0ABFFFFh SA106 256 Kwords 1A80000h-1ABFFFFh SA43 256 Kwords 0AC0000h-0AFFFFFh S A107 256 Kwords 1AC0000h-1AFFFFFh SA44 256 Kwords 0B00000h-0B3FFFFh SA108 256 Kwords 1B00000h-1B3FFFFh SA45 256 Kwords 0B40000h-0B7FFFFh SA109 256 Kwords 1B40000h-1B7FFFFh SA46 256 Kwords 0B80000h-0BBFFFFh SA110 256 Kwords 1B80000h-1BBFFFFh SA47 256 Kwords 0BC0000h-0BFFFFFh SA111 256 Kwords 1BC0000h-1BFFFFFh SA48 256 Kwords 0C00000h-0C3FFFFh SA112 256 Kwords 1C00000h-1C3FFFFh SA49 256 Kwords 0C40000h-0C7FFFFh SA113 256 Kwords 1C40000h-1C7FFFFh SA50 256 Kwords 0C80000h-0CBFFFFh SA114 256 Kwords 1C80000h-1CBFFFFh SA51 256 Kwords 0CC0000h-0CFFFFFh SA115 256 Kwords 1CC0000h-1CFFFFFh SA52 256 Kwords 0D00000h-0D3FFFFh SA116 256 Kwords 1D00000h-1D3FFFFh SA53 256 Kwords 0D40000h-0D7FFFFh SA117 256 Kwords 1D40000h-1D7FFFFh SA54 256 Kwords 0D80000h-0DBFFFFh SA118 256 Kwords 1D80000h-1DBFFFFh SA55 256 Kwords 0DC0000h-0DFFFFFh SA119 256 Kwords 1DC0000h-1DFFFFFh SA56 256 Kwords 0E00000h-0E3FFFFh SA120 256 Kwords 1E00000h-1E3FFFFh SA57 256 Kwords 0E40000h-0E7FFFFh SA121 256 Kwords 1E40000h-1E7FFFFh SA58 256 Kwords 0E80000h-0EBFFFFh SA122 256 Kwords 1E80000h-1EBFFFFh SA59 256 Kwords 0EC0000h-0EFFFFFh S A123 256 Kwords 1EC0000h-1EFFFFFh SA60 256 Kwords 0F00000h-0F3FFFFh SA124 256 Kwords 1F00000h-1F3FFFFh SA61 256 Kwords 0F40000h-0F7FFFFh SA125 256 Kwords 1F40000h-1F7FFFFh SA62 256 Kwords 0F80000h-0FBFFFFh SA126 256 Kwords 1F80000h-1FBFFFFh SA63 256 Kwords 0FC0000h-0FFFFFFh SA127 256 Kwords 1FC0000h-1FFFFFFh T able 19.6 Sector Address / Memory Address Map for the RS512N (Continued) Sector Sector Size (A24-A0) Address Range Sector Sector Size (A24-A0) Address Range

110 S75WS256Nxx Based MCPs S75WS-N-00_00_A0 February 17, 2005

See also the Requirements for Asynchronous Read Operation (Non-Burst) and the Requirements for Synchronous (Burst) Read Operation sections for more information. The Asynchronous Read and Synchronous/Burst Read tables provide the read parameters, Figure 25.2, Figure 25.3, and Figure 25.7 show the timings.

19.2 Set Configuration Register Command Sequence

The device uses a configuration register to se t the various burst parameters: number of wait states, burst read mode, RDY configuration, and synchronous mode active. The configuration reg- ister must be set before the device will enter burst mode. The configuration register is loaded with a four-cycle command sequence. The first two cycles are standard unlock sequences. On the third cycle, the data should be D0h and address bits should be 555h. During the fourth cycle, the configuration code should be entered onto the data bus with the address bus set to address 000h or 001h. Once the data has been programmed into the con- figuration register, a software reset command is required to set the device into the correct state. The device will power up or after a hardware reset with the default setting, which is in asynchro- nous mode. The register must be set before the device can enter synchronous mode. The configuration register can not be changed during device operations (program, erase, or sector lock).

19.3 Read Configuration Register Command Sequence

The configuration register can be read with a four-cycle command sequence. The first two cycles are standard unlock sequences. On the third cycl e, the data should be C6h and address bits should be 555h. During the fourth cycle, the configuration code should be read out of the data bus with the address bus set to address 000h or 001h. Once the data has been read from the configuration register, a software reset command is required to set the device into array read mode. Figure 19.1 Synchronous/Asynchronous State Diagram Power-up/ Hardware Reset Asynchronous Read Mode Only Synchronous Read Mode Only Set Burst Mode Configuration Register Command for Synchronous Mode (D15 = 0) Set Burst Mode Configuration Register Command for Asynchronous Mode (D15 = 1)

February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 111 Data Sheet

19.3.1 Read Mode Setting

On power-up or hardware reset, the device is set to be in asynchronous read mode. This setting allows the system to enable or disable burst mode during system operations. Configuration Bit CR0.15 determines this setting: 1 for asynchronous mode, 0 for synchronous mode.

19.3.2 Programmable Wait State Configuration

The programmable wait state feature informs the device of the number of clock cycles that must elapse after AVD# is driven active before data will be available. This value is determined by the input frequency of the device. Configuration Bit CR1.0 & CR0.13–CR0.11 determine the set- ting (see Table 19.7). The wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. The number of wait states that should be programmed into the device is directly related to the clock frequency. Notes: 1. Upon power-up or hardware reset, the default setting is twelve wait states. 2. All other but setting are reserved. It is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. A hardware reset will set the wait state to the default setting.

19.3.3 Programmable Wait State

The host system should set CR1.0 & CR0.13-CR0.11 to 1100/1010/1000 for a clock frequency of 80/66/54 MHz for the system/device to execute at maximum speed.

19.3.4 Boundary Crossing Latency

Additional wait states must be inserted to account for boundary crossing latency. This is done by setting CR0.14 to a ‘1’ (default). If required, CR0.14 can be changed to a ‘0’ to remove the boundary crossing latency. T able 19.7 Programmable Wait State Settings CR1.0 CR0.13 CR0.12 CR0.11 T otal Initial Access Cycles 00 0 0 R e s e r v e d 00 0 1 3 00 1 0 4 00 1 1 5 01 0 0 6 01 0 1 7 01 1 0 R e s e r v e d 01 1 1 R e s e r v e d 10 0 0 8 10 0 1 9 10 1 0 1 0 10 1 1 1 1 1 1 0 0 12 (default) 11 0 1 1 3 11 1 0 R e s e r v e d 11 1 1 R e s e r v e d

112 S75WS256Nxx Based MCPs S75WS-N-00_00_A0 February 17, 2005

19.3.5 Handshaking

For optimal burst mode performance, the host system must set the appropriate number of wait states in the flash device depending on the clock frequency. The autoselect function allows the host system to determine whether the flash device is enabled for handshaking. See the Autoselect Command Sequence for more information.

19.3.6 Burst Length Configuration

The device supports four different read modes: continuous mode, and 8, 16, and 32 word linear with or without wrap around modes. A continuous sequence (default) begins at the starting ad- dress and advances the address pointer until the burst operation is complete. If the highest address in the device is reached during the co ntinuous burst read mode, the address pointer wraps around to the lowest address. For example, an eight-word linear read with wrap around begins on the starting address written to the device and then advances to the next 8 word boundary. The address pointer then returns to the 1st word after the previous eight word boundary, wrapping through the starting location. The sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eight- word mode. Table 19.8 shows the CR0.2-CR0.0 and settings for the four read modes. Note: Upon power-up or hardware reset the default setting is continuous.

19.3.7 Burst Wrap Around

By default, the device will perform burst wrap around with CR0.3 set to a ‘1’. Changing the CR0.3 to a ‘0’ disables burst wrap around.

19.3.8 RDY Configuration

By default, the device is set so that the RDY pin will output VOH whenever there is valid data on the outputs. The device can be set so that RDY goes active one data cycle before active data. CR0.8 determines this setting; 1 for RDY active (default) with data, 0 for RDY active one clock cycle before valid data.

19.3.9 RDY Polarity

By default, the RDY pin will always indicate that the device is ready to handle a new transaction with CR0.10 set to a ‘1’. In this case, the RDY pin is active high. Changing the CR0.10 to a ‘0’ sets the RDY pin to be active low. In this case, the RDY pin will always indicate that the device is ready to handle a new transaction when low. T able 19.8 Burst Length Configuration Burst Modes Address Bits CR0.2 CR0.1 CR0.0 Continuous 0 0 0 8-word linear 0 1 0 16-word linear 0 1 1 32-word linear 1 0 0

February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 113 Data Sheet

19.4 Configuration Register

Table 19.9 shows the address bits that determine the configuration register settings for various device functions. Note: 3.Device will be in the default state upon power-up or hardware reset. T able 19.9 Configuration Register CR0. Bit Function Settings (Binary) CR0.15 Set Device Read Mode 0 = Synchronous Read (Burst Mode) Enabled 1 = Asynchronous Mode (default) CR0.14 Boundary Crossing 0 = No extra boundary crossing latency 1 = With extra boundary crossing latency (default) CR1.0 Programmable Wait State 0000 = Reserved 0001 = Data is valid on the 4th active CLK edge after addresses are latched 0010 = Data is valid on the 5th active CLK edge after addresses are latched 0011 = Data is valid on the 6th active CLK edge after addresses are latched 0100 = Data is valid on the 7th active CLK edge after addresses are latched 0101 = Data is valid on the 8th active CLK edge after addresses are latched 0110 = Reserved 0111 = Reserved 1000 = Data is valid on the 9th active CLK edge after addresses are latched 1001 = Data is valid on the 10th active CLK edge after addresses are latched 1010 = Data is valid on the 11th active CLK edge after addresses are latched 1011 = Data is valid on the 12th active CLK edge after addresses are latched 1100 = Data is valid on the 13th active CLK edge after addresses are latched (default) 1101 = Data is valid on the 14th active CLK edge after addresses are latched 1110 = Reserved 1111 = Reserved CR0.13 CR0.12 CR0.11 CR0.10 RDY Polarity 0 = RDY signal is active low 1 = RDY signal is active high (default) CR0.9 Reserved 1 = default CR0.8 RDY 0 = RDY active one clock cycle before data 1 = RDY active with data (default) CR0.7 Reserved 1 = default CR0.6 Reserved 1 = default CR0.5 Reserved 0 = default CR0.4 Reserved 0 = default CR0.3 Burst Wrap Around 0 = No Wrap Around Burst 1 = Wrap Around Burst (default) CR0.2 Burst Length 000 = Continuous (default) 010 = 8-Word Linear Burst 011 = 16-Word Linear Burst 100 = 32-Word Linear Burst (All other bit settings are reserved) CR0.1 CR0.0

114 S75WS256Nxx Based MCPs S75WS-N-00_00_A0 February 17, 2005

19.5 Reset Command

Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to which the system was writing to the read mode. [Once erasure begins, however, the device ig nores reset commands until the operation is complete]. The reset command may be writ ten between the sequence cycles in a program command se- quence before programming begins (prior to the third cycle). This resets the device to which the system was writing to the read mode. If the program command sequence is written to the device that is in the Erase Suspend mode, writing the reset command returns the device to the erase- suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command se- quence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a device entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that device to the erase-suspend-read mode. If DQ5 goes high during a program or erase op eration, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend and program-suspend-read mode if the device was in Program Suspend). Note: If DQ1 goes high during a Write Buffer Programming operation, the system must write the Write to Buffer Abort Reset command sequence to RESET the device to read- ing array data. The standard RESET command will not work. See Table 19.9 for details on this command sequence.

19.6 Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. The autoselect command sequence may be written to an ad- dress within the device that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autose- lect mode. No subsequent data will be made available if the autoselect data is read in synchronous mode. The system may read at any address within the device any number of times without initi- ating another autoselect command sequence. The following table describes the address requirements for the various autoselect functions, and the resulting data. The device ID is read in three cycles. T able 19.10 Autoselect Addresses Description Address Read Data Manufacturer ID 00h 01h Device ID, Word 1 01h 227Eh Device ID, Word 2 0Eh 2229 (RS512N) Device ID, Word 3 0Fh 2201 (RS512N) Indicator Bits 03h DQ15 - DQ5 = 0 DQ4 & DQ3 = 11 DQ2 - DQ0 = 0

February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 115 Data Sheet The system must write the reset command to return to the read mode (or erase-suspend-read mode if the device was previously in Erase Suspend).

19.7 Program Command Sequence

Programming is a four-bus-cycle operation. The program command sequence is initiated by writ- ing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally gen- erated program pulses and verifies the programmed cell margin. The Command Definitions table shows the address and data requirements for the program command sequence. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program oper- ation by monitoring DQ7 or DQ6/DQ2. Refer to the “Write Operation Status” section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command se- quence should be reinit iated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be pro- grammed from 0 back to a 1. Only erase operations can convert a 0 back to a 1. Attempting to program a 1 over a 0 will result in a programming failure. Note: See the Command Definitions table for program command sequence. Figure 19.2 Program Word Operation

19.8 Write Buffer Programming Command Sequence

Write Buffer Programming Sequence allows for faster programming as compared to the standard Program Command Sequence. See the Write Buffer Programming Operation section for the pro- gram command sequence. T able 19.11 Write Buffer Command Sequence Sequence Address Data Comment Unlock Command 1 555 00AA Not requir ed in the Unlock Bypass mode Unlock Command 2 2AA 0055 Same as above Write Buffer Load Sector Address 0025h Specify the Number of Program Locations Starting Address Word Count Number of locations to program minus 1 Load 1st data word Starting Address Program Data All addresses must be within write-buffer- page boundaries, but do not have to be loaded in any order Load next data word Write Buffer Location Program Data Same as above Load last data word Write Buffer Location Program Data Same as above Write Buffer Program Confirm Sector Address 0029h This command must follow the last write buffer location loaded, or the operation will ABORT Device goes busy Status monitoring through DQ pins (Perform Data Bar Polling on the Last Loaded Address)

116 S75WS256Nxx Based MCPs S75WS-N-00_00_A0 February 17, 2005

Figure 19.3 Write Buffer Programming Operation Write “Write to Buffer” command and Sector Address Write number of addresses to program minus 1 and Sector Address Write program buffer to flash sector address Write first address/data Write to a different sector address FAIL or ABORT PASS Read DQ15 - DQ0 at Last Loaded Address Read DQ15 - DQ0 with address = Last Loaded Address Write next address/data pair WC = WC - 1 WC = 0 ? Part of “Write to Buffer” Command Sequence Ye s Ye s Ye s Ye s Ye sYe s No No No No No No Abort Write to Buffer Operation? DQ7 = Data? DQ7 = Data? DQ5 = 1?DQ1 = 1? Write to buffer ABORTED. Must write “Write-to-buffer Abort Reset” command sequence to return to read mode.

February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 117 Data Sheet

19.8.1 Unlock Bypass Command Sequence

The unlock bypass feature allows the system to primarily program to the device faster than using the standard word program command sequence. The unlock bypass command sequence is initi- ated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock by- pass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. During the unlock bypass mode, only the Unlock Bypass Program command is valid. To exit the unlock bypass mode, the system must issue th e two-cycle unlock bypass reset command se- quence. The first cycle must contain the data 90h. The second cycle need only contain the data 00h. The device then returns to the read mode.

19.9 Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these oper- ations. The Command Definitions table shows the address and da ta requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, the device returns to the read mode and ad- dresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer to the Write Operation Status section for information on these sta- tus bits. Any commands written during the chip erase operation are ignored. However, note that a hard- ware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 20.4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Opera- tions table in the AC Characteristics section for parameters and timing diagrams.

19.10 Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writ- ing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algo- rithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of no less than 50 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be writ- ten. Loading the sector erase buffer may be do ne in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than

118 S75WS256Nxx Based MCPs S75WS-N-00_00_A0 February 17, 2005

tSEA. Any sector erase address and command following the exceeded time-out may or may not be accepted. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. The system can monitor DQ3 to determine if the sector erase timer has timed out (See DQ3: Sec- tor Erase Timer.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the de- vice has returned to reading array data, to ensure data integrity. Figure 20.4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Opera- tions table in the Erase/Program Operations section for parameters and timing diagrams.

19.10.1 Accelerated Sector Erase

Under certain conditions, the device can erase sectors in parallel. This method of erasing sectors is faster than the standard sector erase command sequence. Table 19.6lists the sectors. The accelerated sector erase function must not be used more than 100 times per sector. In addition, accelerated sector erase should be performed at room temperature 30°C (+/-) 5°C. Use the following procedure to perform accelerated sector erase: 1. Unlock all sectors in a sector to be erased using the sector lock/unlock command sequence. All sectors that remain locked will not be erased. 2. Apply 9 V to the ACC input. This voltage must be applied at least 1 µs before executing step 3. 3. Write 80h to any address within a sector to be erased. 4. Write 30h to any address within a sector to be erased. 5. Monitor status bits DQ2/DQ6 or DQ7 to determ ine when erasure is complete, just as in the standard erase operation. See the Write Operation Status section for further details. 6. Lower ACC from 9 V to V CC. 7. Relock sectors as required.

February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 119 Data Sheet

20 Erase Suspend/Erase Resume Commands

Notes: 1.See the Command Definitions table for erase command sequence. 2.See the section on DQ3 for information on the sector erase timer. Figure 20.4 Erase Operation The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the minimum t SEA time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device re- quires a maximum of t ESL (Erase Suspend Latency) to susp end the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device imme- diately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The de- vice erase suspends all sectors selected for erasure.) Reading at any address within erase- suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation Status for information on these status bits. After an erase-suspended program operation is complete, the device returns to the erase-sus- pend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. See Write Buffer Programming Operation and Autoselect Command Sequence for details. To re- sume the sector erase operation, the system must write the Erase Resume command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.

20.1 Program Suspend/Program Resume Commands

The Program Suspend command allows the system to interrupt a embedded programming oper- ation or a Write to Buffer programming operation so that data can read from any non-suspended sector. When the Program Suspend command is written during a programming process, the de- vice halts the programming operation within t PSL (Program Suspend Latency) and updates the status bits. Addresses are don’t-cares when writing the Program Suspend command. After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a program- ming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the SecSi Sector area (One Time Program area), then user must use the proper command sequences to enter and exit this region. The system may also write the autoselect command sequence when the device is in Pro- gram Suspend mode. The device allows reading autoselect codes in the suspended sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to Program Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence for more information.

120 S75WS256Nxx Based MCPs S75WS-N-00_00_A0 February 17, 2005

After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information. The system must write the Program Resume command (address bits are don’t care) to exit the Program Sus- pend mode and continue the pr ogramming operation. Further writes of the Program Resume command are ignored. Another Program Suspend command can be written after the device has resume programming.

20.2 Volatile Sector Protection Command Set

The Volatile Sector Protection Command Set permits the user to set the Dynamic Protection Bit (DYB), clear the Dynamic Protection Bit (DYB), and read the logic state of the Dynamic Protection Bit (DYB). The Volatile Sector Protection Command Set Entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. Note that issuing the Volatile Sector Protection Command Set Entry command disables reads and writes for the device with the command. „ DYB Set Command „ DYB Clear Command „ DYB Status Read Command The DYB Set/Clear command is used to set or cl ear a DYB for a given se ctor. The address bits are issued at the same time as the code 00h or 01h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared (erased to ‘1’) at power-up or hardware reset and are thus in an unprotected state. The programming state of the DYB for a given sector can be verified by writing a DYB Status Read Command to the device. The Volatile Sector Protection Command Set Exit command must be issued after the execu- tion of the commands listed previously to reset the device to read mode. Otherwise the device will hang. Note that issuing the Volatile Sector Protection Command Set Exit command re-enables reads and writes for the device.

February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 121 Data Sheet

21 Command Definitions

Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK which ever comes first. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A24–A14 for the RS512N uniquely select any sector. CR = Configuration Register data bits D15–D0. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1. Notes: 1. See Table 18.1 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of the configuration register verify command, and any cycle reading at RD(0) and RD(1). 4. Data bits DQ15–DQ8 are don’t care in comm and sequences, except for RD, PD, and WD. 5. Unless otherwise noted, address bits Amax–A12 are don’t cares. 6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 7. No unlock or command cycles required when device is reading array data. 8. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status information) or performing sector lock/unlock. 9. The fourth cycle of the autoselect command sequence is a read cycle. See the Autoselect Command Sequence section. 10. 512 Mb: 0Eh = 29h and 0Fh = 01h. 11. See the Autoselect Command Sequence section. 12. The Unlock Bypass command sequence is required prior to this command sequence. 13. The Unlock Bypass Reset command is required to return to read ing array data when the device is in the unlock bypass mode. 14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Er ase Suspend command is valid only during a sector erase operation. 15. The Erase Resume command is valid only during the Erase Suspend mode 16. See the Set Configuration Register Command Sequence section. 17. See the Read Configuration Register Command Sequence section which further provides information on Reset Command to Configure the Configuration Register. 18. The total number of cycles in the command sequence is determin ed by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 37. 19. ACC must be at VHH during the entire operation of this command 20. Command sequence resets device for next command after write-to-buffer operation. 21. Entry commands are needed to enter a specific mode to enable instructions only available within that mode. 22. Write Buffer Programming can be initiated after Unlock Bypass Entry. Command Sequence (Note 1) Cycles Bus Cycles (Notes 1–6) First Second Third Fourth Fifth Sixth Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Asynchronous Read (7) 1 RA RD Reset (8) 1 XXX F0 Autoselect (9) Manufacturer ID 4 555 AA 2AA 55 555 90 X00 0001 Device ID (10) 6 555 AA 2AA 55 555 90 X01 ( 11)X 0 E ( 10)X 0 F( 10) Indicator Bits 4 555 AA 2AA 55 555 90 X03 ( 11) Program 4 555 AA 2AA 55 555 A0 PA Data Write to Buffer (18) 6 555 AA 2AA 55 SA 25 PA WC PA PD WBL PD Program Buffer to Flash 1 SA 29 Write to Buffer Abort Reset (22) 3 555 AA 2AA 55 555 F0 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Erase Suspend (15) 1 XXX B0 Erase Resume (15) 1 XXX 30 Set Configuration Register (16) 4 555 AA 2AA 55 555 D0 X00 or X01 CR Read Configuration Register (17) 4 555 AA 2AA 55 555 C6 X00 or X01 CR Unlock Bypass Mode Unlock Bypass Entry (21) 3 555 AA 2AA 55 555 20 Unlock Bypass Program (12, 13)2 X X A 0 P A P D Unlock Bypass Reset 2 XX 90 XXX 00 Volatile Sector Protection Command Set Definitions DYB Volatile Sector Protection Command Set Entry 3 555 AA 2AA 55 555 E0 DYB Set 2 XX A0 SA 00 DYB Clear 2 XX A0 SA 01 DYB Status Read 1 SA RD(0) Volatile Sector Protection Command Set Exit 2X X 9 0 X X 0 0

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22 Write Operation Status

The device provides several bits to determine the status of a program or erase operation: DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7. Table 22.13 and the following subsections describe the function of these bits. DQ7 and DQ6 each offers a method for determining whether a program or erase operation is complete or in progress.

22.1 DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. Note that the Data# Polling is valid only for the last word being programmed in the write-buffer-page during Write Buffer Programm ing. Reading Data# Polling status on any word other than the last word to be programmed in the write-buffer-page will return false status information. During the Embedded Program algorithm, the de vice outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approxi- mately t PSP, then the device returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling pro- duces a 1 on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately tASP, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asyn- chronously with DQ6–DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still invalid. Valid data on DQ7-D00 will appear on successive read cycles. Table 22.13 shows the outputs for Data# Polling on DQ7. Figure 22.5 shows the Data# Polling algorithm. Figure 25.13 in the AC Characteristics section shows the Data# Polling timing diagram. Notes: 1. VA = Valid adntsbdress for programming. During a sector eras e operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5. Figure 22.5 Data# Polling Algorithm

22.2 DQ6: T oggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the device, and is valid after the rising edge of the final WE# pulse in the com- mand sequence (prior to the program or erase operation), and during the sector erase time-out.

February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 123 Data Sheet During an Embedded Program or Erase algorith m operation, successive read cycles to any ad- dress cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately tASP (All Sectors Protected toggle time), then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro- tected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops tog- gling. However, the system must also use DQ2 to determine which sectors are erasing or erase- suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately tPSP after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embed- ded Program algorithm is complete. See the following for ad ditional information: Figure 22.6, Figure 25.14 (toggle bit timing dia- gram), and Table 22.12. Toggle Bit I on DQ6 requires either OE# or CE# to be deasserted and reasserted to show the change in state. Note: The system should recheck the toggle bit even if DQ5 = 1 because the toggle bit may stop toggling as DQ5 changes to 1. See the subsections on DQ6 and DQ2 for more information. Figure 22.6 T oggle Bit Algorithm

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DQ2: Toggle Bit II The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase- suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. But DQ2 by itself cannot distinguish whether the sector is actively erasing or is erase- suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 22.12 to compare outputs for DQ2 and DQ6. See Figure 22.6 and Figure 25.14 for additional information.

22.3 Reading T oggle Bits DQ6/DQ2

Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would com- pare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. (See Figure 22.6) However, if after the initial two read cycles, the system determines that the toggle bit is still tog- gling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through suc- cessive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation.

22.4 DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1, indicating that the program or erase cycle was not successfully completed. The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was pre- viously programmed to 0 Only an erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 pro- duces a 1. Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if the device was previously in the erase-suspend-pro- gram mode).

22.5 DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a 0 to a 1. If

February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 125 Data Sheet the time between additional sector erase commands from the system can be assumed to be less than tSEA, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Poll- ing) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is 1, the Embedded Erase algorithm has begun; all further commands (ex- cept Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 00 the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 22.13 shows the status of DQ3 relative to the other status bits.

22.6 DQ1: Write to Buffer Abort

DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 pro- duces a ‘1’. The system must issue the Write to Buffer Abort Reset command sequence to return the device to reading array data. See the Write Buffer Programming Operation section for more details. 4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations. 5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location. 6. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may overshoot T able 22.1 Maximum Negative Overshoot Waveform Figure 22.7 Maximum Positive Overshoot Waveform 20 ns 20 ns +0.8 V –0.5 V 20 ns –2.0 V 20 ns 20 ns VCC +2.0 V VCC +0.5 V 20 ns 1.0 V

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23 DC Characteristics

23.1 CMOS Compatible

Notes: 1. Maximum I CC specifications are tested with VCC = VCC max. 2. The I CC current listed is typically less than 2-3 mA/MHz, with OE# at VIH. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Device enters automatic sleep mode when addresses are stable for tACC + 20 ns. Typical sleep mode current is equal to ICC3. 5. Total current during accelerate d programming is the sum of VACC and VCC currents. 6. U IH = VCC ± 0.2 V and VIL > -.1 V 7. Typical test conditions of room temperature and 1.8 V V CC. Parameter Description T est Conditions ( Note 1)M i n Ty p (Note 7) Max Unit ILI Input Load Current V IN = VSS to VCC, VCC = VCCmax ±1 µA ILO Output Leakage Current V OUT = VSS to VCC, VCC = VCCmax ±1 µA ICCB VCC Active burst Read Current CE# = VIL, OE# = VIH, WE# = VIH, burst length =

80 MHz 30 66

54 MHz 27 54

CE# = VIL, OE# = VIH, WE# = VIH, burst length =

80 MHz 32 60

54 MHz 28 48

CE# = V IL, OE# = VIH, WE# = VIH, burst length =

80 MHz 34 54

54 MHz 29 42

CE# = V IL, OE# = VIH, WE# = VIH, burst length = Continuous

80 MHz 38 48

54 MHz 22 36

I CC1 VCC Active Asynchronous Read Current (Note 2) CE# = VIL, OE# = VIH, WE# = VIH (Note 3) CE# = VIL, OE# = VIH, ACC = VIH VCC <35 <50 mA VACC 20 30 µA ICC3 VCC Standby Current (Note 6) CE# = RESET# = VCC ± 0.2 V VCC 20 40 µA VACC 10 15 µA ICC4 VCC Reset Current RESET# = V IL, CLK = VIL 70 150 µA ICC6 VCC Sleep Current CE# = V IL, OE# = VIH 20 40 µA IACC Accelerated Program Current (Note 5) CE# = VIL, OE# = VIH, VACC = 9.5 V VCC <30 <40 mA VACC <15 <20 mA VIL Input Low Voltage –0.5 0.4 V VIH Input High Voltage V CC – 0.4 V CC + 0.4 VOL Output Low Voltage I OL = 100 µA, VCC = VCC min 0.1 V VOH Output High Voltage I OH = –100 µA, VCC = VCC min VCC – 0.1 V VHH Voltage for Accelerated Program 8.5 9.5 V VLKO Low VCC Lock-out Voltage 1.0 1.4 V

February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 127 Data Sheet

24 T est Conditions

Figure 24.1 T est Setup Figure 24.2 Input Waveforms and Measurement Levels T able 24.1 T est Specifications T est Condition All Speed Options Unit Output Load Capacitance, CL (including jig capacitance) 30 pF Input Rise and Fall Times 2.5 ns Input Pulse Levels 0.0–V CC V Input timing measurement reference levels V CC/2 V Output timing measurement reference levels V CC/2 V Waveform Inputs Outputs Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) CL Device Under Test

128 S75WS256Nxx Based MCPs S75WS-N-00_00_A0 February 17, 2005

25 AC Characteristics

25.1 V CC Power-up

Notes: 1. V CC >= VIO - 100mV and VCC ramp rate is > 1V / 100µs 2. V CC ramp rate <1V / 100µs, a Hardware Reset will be required. Figure 25.1 V CC Power-up Diagram

25.2 CLK Characterization

Figure 25.2 CLK Characterization Parameter Description T est Setup Speed Unit tVCS VCC Setup Time Min 1 ms Parameter Description 80 MHz 66 MHz 54 MHz Unit fCLK CLK Frequency Max 80 66 54 MHz tCLK CLK Period Min 12.5 15.1 18.5 ns tCH CLK High Time Min 3.5 6.1 7.40 ns tCL CLK Low Time tCR CLK Rise Time Max 2 3 3 ns tCF CLK Fall Time VCC RESET# tVCS tCLK tCLtCH tCR tCF CLK

February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 129 Data Sheet

25.3 Synchronous/Burst Read

Notes: 1. Addresses are latched on the first rising edge of CLK. 2. Not 100% tested. Parameter Description 80 MHz 66 MHz 54 MHz Unit JEDEC Standard tIACC Latency Max 148 ns tBACC Burst Access Time Valid Clock to Output Delay Max 9.1 11.2 13.5 ns tACS Address Setup Time to CLK (Note 1)M i n 4 4 5 n s tACH Address Hold Time from CLK (Note 1)M i n 2 2 3 n s tBDH Data Hold Time from Next Clock Cycle Min 4 4 5 ns tCR Chip Enable to RDY Valid Max 9.1 11.2 13.5 ns tOE Output Enable to Output Valid Max 9.1 11.2 13.5 ns tCEZ Chip Enable to High Z (Note 2) Max 10 10 10 ns tOEZ Output Enable to High Z (Note 2) Max 10 10 10 ns tCES CE# Setup Time to CLK Min 4 4 4 ns tRDYS RDY Setup Time to CLK Min 4 4 5 ns tRACC Ready Access Time from CLK Max 9.1 11.2 13.5 ns tAAS Address Setup Time to AVD# (Note 1)M i n 4 4 5 n s tAAH Address Hold Time to AVD# (Note 1)M i n 2 2 3 n s tCAS CE# Setup Time to AVD# Min 0 0 0 ns tAVC AVD# Low to CLK Min 4 4 4 ns tAVD AVD# Pulse Min 8 8 8 ns

130 S75WS256Nxx Based MCPs S75WS-N-00_00_A0 February 17, 2005

Notes: 1. Figure shows total number of wait states set to ten cycles. The total number of wait states can be programmed from three cycles to thirteen cycles. 2. If any burst address occurs at address + 1, address + 2, ..., or address + 7, additional clock delay cycles are inserted, and are indicated by RDY. 3. The device is in synchronous mode. 4. In order for the device to operate at 80Mhz/66Mhz/54Mhz, ther e is an additional wait state latency of 2/1/0 accordingly, every 4 clock cycles with the first data being read. Figure 25.3 CLK Synchronous Burst Mode Read Da Da + 1 Da + n OE# Data (n) Addresses Aa AVD# RDY (n) CLK CE# tCES tACS tAVC tAVD tACH tOE tRACC tOEZ tCEZ tIACC tBDH 10 cycles for initial access shown. 18.5 ns typ. (54 MHz) Hi-Z Hi-Z Hi-Z 1 2 3 9 10 11 12 tRDYS tBACC Da + 2 Da Da + 1 Da + n Data (n + 1) RDY (n + 1) Hi-Z Hi-Z Hi-Z Da + 2 Da Da + 1 Da + n Data (n + 2) RDY (n + 2) Hi-Z Hi-Z Hi-Z Da + 1 Da Da Da + n Data (n + 3) RDY (n + 3) Hi-Z Hi-Z Hi-Z Da tCR

132 S75WS256Nxx Based MCPs S75WS-N-00_00_A0 February 17, 2005

Notes: 1. Figure assumes eleven wait states for initial access and synchronous read. 2. The Set Configuration Register command sequence has be en written with A18=0; device will output RDY one cycle before valid data. Figure 25.6 Burst with RDY Set One Cycle Before Data 25.4 Asynchronous Mode Read @ VIO = 1.8 V Notes: 1. Asynchronous Access Time is from the last of ei ther stable addresses or the falling edge of AVD#. 2. Not 100% tested. Parameter Description 80 MHz 66 MHz 54 MHz Unit JEDEC Standard tCE Access Time from CE# Low Max 148 ns tACC Asynchronous Access Time (Note 1) Max 143 ns tAVDP AVD# Low Time Min 8 8 10 ns tAAVDS Address Setup Time to Rising Edge of AVD# Min 4 4 5 ns tAAVDH Address Hold Time from Rising Edge of AVD# Min 2 2 3 ns tOE Output Enable to Output Valid Max 9.1 11.2 13.5 ns tOEH Output Enable Hold Time Read Min 0 0 0 ns Data# Polling Min 10 10 10 ns tOEZ Output Enable to High Z (Note 2) Max 10 10 10 ns tCAS CE# Setup Time to AVD# Min 0 0 0 ns Da+1Da Da+2 Da+3 Da + n OE# Data Addresses Aa AVD# RDY CLK CE# tCES tACS tAVC tAVD tACH tOE tRACC tOEZ tCEZ tIACC tBDH 12 wait cycles for initial access shown. Hi-Z Hi-Z Hi-Z 1 2 3 4 10 11 tRDYS tBACC tCR

February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 133 Data Sheet

25.5 Timing Diagrams

Note: RA = Read Address, RD = Read Data. Figure 25.7 Asynchronous Mode Read with Latched Addresses Note: RA = Read Address, RD = Read Data. Figure 25.8 Asynchronous Mode Read

25.6 Hardware Reset (RESET#)

Note: Not 100% tested. Parameter Description All Speeds Unit JEDEC Std tRP RESET# Pulse Width Min 30 µs tRH Reset High Time Before Read to Read Mode Min 300 µs tRPD RESET# Low to Standby Mode Min 20 µs tCEWE# Addresses CE# OE# Valid RD tACC tOEH tOE Data tOEZ tAAVDH tAVDP tAAVDS AVD# RA tCAS tCEWE# Addresses CE# OE# Valid RD tACC tOEH tOE Data tOEZ AVD# RA

134 S75WS256Nxx Based MCPs S75WS-N-00_00_A0 February 17, 2005

Figure 25.9 Reset Timings RESET# tRP Reset Timings CE#, OE# tRH

February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 135 Data Sheet

25.7 Erase/Program Operations

Notes: 1. Not 100% tested. 2. Asynchronous read mode allows Asynchronous program operation only. Synchronous read mode allows both Asynchronous and Synchronous program operation. 3. In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program operation timing, addresses are latched on the rising edge of CLK. 4. See the Erase and Programming Performance section for more information. Does not include the preprogramming time. Parameter Description 80 MHz 66 MHz 54 MHz Unit JEDEC Standard tAVAV tWC Write Cycle Time (Note 1)M i n 7 0 n s tAVWL tAS Address Setup Time (Notes 2, 3) Synchronous Min ns Asynchronous 0 0 0 tWLAX tAH Address Hold Time (Notes 2, 3) Synchronous Min 223 ns Asynchronous 0 0 0 tAVDP AVD# Low Time Min 8 8 8 ns tDVWH tDS Data Setup Time Min 20 20 25 ns tWHDX tDH Data Hold Time Min 0 0 0 ns tGHWL tGHWL Read Recovery Time Before Write Min 0 0 0 ns tCAS CE# Setup Time to AVD# Min 0 0 0 ns tWHEH tCH CE# Hold Time Min 0 0 0 ns tWLWH tWP Write Pulse Width Min 30 ns tWHWL tWPH Write Pulse Width Highs Min 20 20 25 ns tSR/W Latency Between Read and Write Operations Min 0 0 0 ns tVID VACC Rise and Fall Time Min 500 ns tVIDS VACC Setup Time (During Accelerated Programming) Min 1 µs tVCS VCC Setup Time Min 50 µs tELWL tCS CE# Setup Time to WE# Min 5 ns tAVSW AVD# Setup Time to WE# Min 5 ns tAVHW AVD# Hold Time to WE# Min 2 2 3 ns tAVSC AVD# Setup Time to CLK Min 5 ns tAVHC AVD# Hold Time to CLK Min 2 2 3 ns tCSW Clock Setup Time to WE# Min 5 ns tWEP Noise Pulse Margin on WE# Max 3 ns tSEA Sector Erase Accept Time-out Max 50 µs tESL Erase Suspend Latency Max 20 µs tPSL Program Suspend Latency Max 20 µs tASP Toggle Time During Sector Protection Typ 100 µs tPSP Toggle Time During Programming Within a Protected Sector Typ 1 µs

136 S75WS256Nxx Based MCPs S75WS-N-00_00_A0 February 17, 2005

Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. In progress and complete refer to status of program operation. 3. Amax–A14 are don’t care during command sequence unlock cycles. 4. CLK can be either V IL or VIH. 5. The Asynchronous programming operation is independent of th e Set Device Read Mode bit in the Configuration Register. Figure 25.10 Asynchronous Program Operation Timings: WE# Latched Addresses OE# CE# Data Addresses AVD# WE# CLK VCC 555h PD tAS tAVSW tAVHW tAH tWC tWPH PA tVCS tWP tDH tCH In Progress tWHWH1 VA Complete VA Program Command Sequence (last two cycles) Read Status Data tDS VIH VIL tAVDP A0h tCS tCAS

138 S75WS256Nxx Based MCPs S75WS-N-00_00_A0 February 17, 2005

Notes: 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to de termine status. When the Embedded Algorithm operation is completeData# Polling will output true data. Figure 25.13 Data# Polling Timings (During Embedded Algorithm) Notes: 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to de termine status. When the Embedded Algorithm operation is complete, . Figure 25.14 T oggle Bit Timings (During Embedded Algorithm) WE# CE# OE# High Z tOE High Z Addresses AVD# tOEH tCE tCH tOEZ tCEZ Status Data Status Data tACC VA VA Data WE# CE# OE# High Z tOE High Z Addresses AVD# tOEH tCE tCH tOEZ tCEZ Status Data Status Data tACC VA VA Data

140 S75WS256Nxx Based MCPs S75WS-N-00_00_A0 February 17, 2005

Notes: 1. RDY active with data (D8 = 0 in the Configuration Register). 2. RDY active one clock cycle before data (D8 = 1 in the Configuration Register). 3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. 4. There will be an additional 4/8 wait state latency for 54/80 Mhz respectively. Figure 25.17 Latency with Boundary Crossing Wait State Configuration Register Setup Note: Figure assumes address D0 is not at an address boundary. Figure 25.18 Example of Wait States Insertion CR1.0, CR0.13, CR0.12, CR0.11= 1101 ⇒ 13 total CR1.0, CR0.13, CR0.12, CR0.11= 1100 ⇒ 12 total CR1.0, CR0.13, CR0.12, CR0.11= 1011 ⇒ 11 total CR1.0, CR0.13, CR0.12, CR0.11= 1010 ⇒ 10 total CR1.0, CR0.13, CR0.12, CR0.11= 1001 ⇒ 9 total CR1.0, CR0.13, CR0.12, CR0.11= 1000 ⇒ 8 total CR1.0, CR0.13, CR0.12, CR0.11= 0101 ⇒ 7 total CR1.0, CR0.13, CR0.12, CR0.11= 0100 ⇒ 6 total CR1.0, CR0.13, CR0.12, CR0.11= 0011 ⇒ 5 total CR1.0, CR0.13, CR0.12, CR0.11= 0010 ⇒ 4 total CR1.0, CR0.13, CR0.12, CR0.11= 0001 ⇒ 3 total CLK Address (hex) C508 C509 C510 C511 C511 C512 C513 C514 C515 D508 D509 D510 D511 D512 D513 D514 (stays high)AVD# RDY(1) Data OE#, CE# (stays low) Address boundary occurs every 512 words, beginning at address 0001FFh: (0002FFh, 0003FFh, etc.) Address 000000h is also a boundary crossing. 1FC 1FD 1FE 1FF 1FF 200 201 202 203 latency RDY(2) latency tRACC tRACC tRACCtRACC Data AVD# OE# CLK 12 3 45 D0 D1 total number of clock cycles following AVD# falling edge Rising edge of next clock cycle following last wait state triggers next burst data number of clock cycles programmed 8 9 10 11 12 13 14

February 17, 2005 S75WS-N-00_00_A0 S75WS256Nxx Based MCPs 141 Data Sheet Note: Breakpoints in waveforms indicate that system may alternately read the status of the program or erase operation in the device. The system should read status twice to ensure valid information. Figure 25.19 Back-to-Back Read/Write Cycle Timings OE# CE# WE# tOEH Data Addresses AVD# PD/30h AAh RAPA/SA tWC tDS tDH tRC tRC tOE tAS tAH tACC tOEH tWP tGHWL tOEZ tWC tSR/W Last Cycle in Program or Sector Erase Command Sequence Read status (at least two cycles) in same bank and/or array data from other bank Begin another write or program command sequence RD RA 555h RD tWPH

142 S75WS256Nxx Based MCPs S75WS-N-00_00_A0 February 17, 2005

26 Erase and Programming Performance

Notes: 1. Typical program and erase times assume the following conditions: 25°C, 1.8 V VCC, 100,000 cycles typical. Additionally, programming typically assumes a checkerboard pattern. 2. Under worst case conditions of 90°C, V CC = 1.65 V, 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed. 4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See the Command Definitions table for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 100,000 cycles. Parameter Ty p (Note 1) Max (Note 2) Unit Comments Sector Erase Time 256 Kword VCC 22 0 s Excludes 00h programming prior to erasure (Note 4) ACC 1 10 Chip Erase Time VCC 308 616 s ACC 262 524 Word Programming Time VCC <40 <400 µs Excludes system level overhead (Note 5)ACC <24 <240 Effective Word Programming Time utilizing Program Write Buffer VCC <9.4 <94 µs ACC <6 <60 Total 32-Word BufferProgramming Time VCC <300 <3000 µs ACC <192 <1920 Chip Programming Time (Note 3) VCC <314.6 <629.2 s Excludes system level overhead (Note 5)ACC <201.4 <402.6

Publication Number S75WS-N-00 Revision A Amendment 0 Issue Date February 17, 2005 CellularRAM 128/64/32 Megabit Burst CellularRAM

Features

„ Single device supports asynchronous, page, and burst operations „ VCC Voltages — 1.70V–1.95V V CC „ Random Access Time: 70ns „ Burst Mode Write Access — Continuous burst „ Burst Mode Read Access — 4, 8, or 16 words, or continuous burst „ Page Mode Read Access — Sixteen-word page size — Interpage Read access: 70ns — Intrapage Read access: 20ns „ Low-Power Consumption — Asynchronous Read < 25mA — Intrapage Read < 15mA — Initial access, burst Read < 35mA — Continuous burst Read < 11mA — Standby: 180µA — Deep power-down < 10µA „ Low-Power Features — Temperature Compensated Refresh (TCR) On-chip sensor control — Partial Array Refresh (PAR) — Deep Power-Down (DPD) Mode General Description CellularRAM™ products are High-s peed, CMOS dynamic random acce ss memories developed for low- power, portable applications. These devices include an industry standard burst mode Flash interface that dramatically increases Read/Write bandwidth compar ed with other low-power SRAM or Pseudo SRAM offerings. To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a transparent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device Read/Write performance. Two user-accessible control registers define device operation. The bus configuration register (BCR) de- fines how the CellularRAM device interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self refresh. CellularRAM prod- ucts include three mechanisms to minimize standby current. Partial array refresh (PAR) enables the system to limit refresh to only that part of the DRAM array that contains essential data. Temperature com- pensated refresh (TCR) adjusts the refresh rate to match the device temperature—the refresh rate decreases at lower temperatures to minimize current consumption during standby. Deep power-down (DPD) enables the system to halt the refresh operation altogether when no vital information is stored in the device. The system-configurable refresh mechanisms are accessed through the RCR.

144 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

27 Functional Block Diagram

Note: Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing di- agrams for detailed information. Figure 27.1 Functional Block Diagram 128M: A[22:0] 64M: A[21:0] 32M: A[20:0] Input/ Output MUX and Buffers Control Logic DRAM MEMORY ARRAY CE# WE# OE# CLK ADV# CRE WAIT LB# UB# DQ[7:0] DQ[15:8] Address Decode Logic Refresh Configuration Register (RCR) Bus Configuration Register (BCR)

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 145 Advance Information Note: The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. Wait will be asserted but should be ignored during asynchronous and page mode operations. T able 27.1 Signal Descriptions Symbol T ype Description 128M: A[22:0] 64M: A[21:0] 32M: A[20:0] Input Address Inputs: Inputs for addresses during Read and Write operations. Addresses are internally latched during Read and Write cycles. The address lines are also used to define the value to be loaded into the BCR or the RCR. CLK Input Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When configured for synchronous operation, the address is latched on the first rising CLK edge when ADV# is active. CLK is static (High or Low) during asynchronous access Read and Write operations and during Page Read Access operations. ADV# Input Address Valid: Indicates that a valid address is present on the address inputs. Addresses can be latched on the rising edge of ADV# during asynchronous Read and Write operations. ADV# can be held Low during asynchronous Read and Write operations. CRE Input Configuration Register Enable: When CRE is High, Write operations load the RCR or BCR. CE# Input Chip Enable: Activates the device when Low. When CE# is High, the device is disabled and goes into standby or deep power-down mode. OE# Input Output Enable: Enables the output buffers when Low. When OE# is High, the output buffers are disabled. WE# Input Write Enable: Determines if a given cycle is a Write cycle. If WE# is Low, the cycle is a Write to either a configuration register or to the memory array. LB# Input Lower Byte Enable. DQ[7:0] UB# Input Upper Byte Enable. DQ[15:8] DQ[15:0] Input/ Output Data Inputs/Outputs. Wait Output Wait: Provides data-valid feedback during burst Read and Write operations. The signal is gated by CE#. Wait is used to arbitrate collisions between refresh and Read/Write operations. Wait is asserted when a burst crosses a row boundary. Wait is also used to mask the delay associated with opening a new internal page. Wait is asserted and should be ignored during asynchronous and page mode operations. Wait is High-Z when CE# is High. V CC Supply Device Power Supply: (1.7V–1.95V) Power supply for device core operation. VCCQ Supply I/O Power Supply: (1.7V–1.95V) Power supply for input/output buffers. VSS Supply V SS must be connected to ground. VSSQS u p p l y V SSQ must be connected to ground.

146 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

Notes: 1. CLK may be High or Low, but must be static during synchronous Read, synchronous Write, burst suspend, and DPD modes; and to a chieve standby power during standby and active modes. 2. The Wait polarity is configured through the bus configuration register (BCR[10]). 3. When LB# and UB# are in select mode (Low), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are affected. 4. The device will consume active power in this mode whenever addresses are changed. 5. When the device is in standby mode, address inputs and data in puts/outputs are internally isolated from any external influence. 6. V IN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current. 7. DPD is maintained unt il RCR is reconfigured. T able 27.2 Bus Operations—Asynchronous Mode Mode Power Clk (Note 1) ADV# CE# OE# WE# CRE LB#/ UB# Wait (Note 2) DQ[15:0] (Note 3)N o t e s Read Active X L L L H L L Low-Z Data-Out 4 W r i t e A c t i v e X LLXLLL L o w - Z D a t a - I n 4 Standby Standby X X H X X L X High-Z High-Z 5, 6 No Operation Idle X X L X X L X Low-Z X 4, 6 Configuration Register A c t i v e X LLHLHX L o w - Z H i g h - Z DPD Deep Power-down X X H X X X X High-Z High-Z 7

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 147 Advance Information Notes: 1. CLK may be High or Low, but must be static during asynchronous Read, synchronous Write, burst suspend, and DPD modes; and to achieve standby power during standby and active modes. 2. The Wait polarity is configured through the bus configuration register (BCR[10]). 3. When LB# and UB# are in select mode (Low), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are affected. 4. The device will consume active power in this mode whenever addresses are changed. 5. When the device is in standby mode, address inputs and data in puts/outputs are internally isolated from any external influence. 6. V IN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current. 7. DPD is maintained unt il RCR is reconfigured. 8. Burst mode operation is initialized through the bus configuration register (BCR[15]). T able 27.3 Bus Operations—Burst Mode Mode Power CLK (Note 1) ADV# CE# OE# WE# CRE LB#/ UB# Wait (Note 2) DQ[15:0] (Note 3)N o t e s Async Read Active X L L L H L L Low-Z Data-Out 4 A s y n c W r i t e A c t i v e X LLXLLL L o w - Z D a t a - I n 4 Standby Standby X X H X X L X High-Z High-Z 5, 6 No Operation Idle X X L X X L X Low-Z X 4, 6 Initial Burst Read Active L L X H L L Low-Z Data-Out 4, 8 Initial Burst Write Active L L H L L X Low-Z Data-In 4, 8 Burst Continue Active H L X X L X Low-Z Data-In or Data-Out 4, 8 Burst Suspend Active X X L H X L X Low-Z High-Z 4, 8 Configuration Register Active L L H L H X Low-Z High-Z 8 DPD Deep Power-Down X X H X X X X High-Z High-Z 7

148 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

28 Functional Description

The CellularRAM bus interface supports both asynchronous and burst mode transfers. Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous Read protocol.

28.1 Power-Up Initialization

CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization process. Initialization will configure the BCR and the RCR with their default settings (see Table 31.1 and Table 31.5). VCC and VCCQ must be applied simultaneously. When they reach a sta- ble level at or above 1.7V, the device will require 150 µs to complete its self-initialization process. During the initialization period, CE# should remain High. When initialization is complete, the de- vice is Ready for normal operation. Figure 28.2 Power-Up Initialization Timing VCC VCCQ tPU > 150 μs Device Initialization Device ready for normal operation VCC = 1.7 V

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 149 Advance Information

29 Bus Operating Modes

CellularRAM products incorporate a burst mode interface found on Flash products targeting low- power, wireless applications. This bus interface supports asynchronous, page mode, and burst mode Read and Write transfers. The specific interface supported is defined by the value loaded into the BCR. Page mode is controlled by the refresh configuration register (RCR[7]).

29.1 Asynchronous Mode

CellularRAM products power up in the asynchronous operating mode. This mode uses the industry standard SRAM control bus (CE#, OE#, WE#, LB#/ UB#). Read operations (Figure 29.1) are ini- tiated by bringing CE#, OE#, and LB#/UB# Low while keeping WE# High. Valid data will be driven out of the I/Os after the specified access time has elapsed. Write operations (Figure 29.2) occur when CE#, WE#, and LB#/ UB# are driven Low. During asynchronous Write operations, the OE# level is a don't care, and WE# will override OE#. The data to be written is latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs first). Asynchronous operations (page mode disabled) can either use the ADV input to latch the address, or ADV can be driven Low during the entire Read/Write operation. During asynchronous operation, the CLK input must be held static (High or Low, no transitions). Wait will be driven while the device is enabled and its state should be ignored. Note: ADV must remain Low for page mode operation. Figure 29.1 Read Operation (ADV# Low) Data Valid Address Valid tRC = READ Cycle Time CE# OE# WE# ADDRESS DATA LB#/UB# Don't Care

150 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

29.2 Page Mode Read Operation

Page mode is a performance-enhancing extension to the legacy asynchronous Read operation. In page mode-capable products, an initial asynchronous Read access is performed, then adjacent addresses can be Read quickly by simply changing the low-order address. Addresses A[3:0] are used to determine the members of the 16-address CellularRAM page. Addresses A[4] and higher must remain fixed during the entire page mode access. Figure 29.3 shows the timing for a page mode access. Page mode takes advantage of the fact that adjacent addresses can be Read in a shorter period of time than random addresses. Write operations do not include comparable page mode functionality. During asynchronous page mode operation, the CLK input must be held Low. CE# must be driven High upon completion of a page mode access. Wait will be driven while the device is enabled and its state should be ignored. Page mode is enabled by setting RCR[7] to High. Write operations do not include comparable page mode functionality. ADV must be driven Low during all page mode Read accesses. Figure 29.2 Write Operation (ADV# Low) Data Valid Address Valid tWC = WRITE Cycle Time CE# OE# WE# ADDRESS DATA LB#/UB# Don't Care

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 151 Advance Information

29.3 Burst Mode Operation

Burst mode operations enable High-speed synchronous Read and Write operations. Burst opera- tions consist of a multi-clock sequence that must be performed in an ordered fashion. After CE# goes Low, the address to access is latched on the rising edge of the next clock that ADV# is Low. During this first clock rising edge, WE# indicate s whether the operation is going to be a Read (WE# = High, Figure 29.4) or Write (WE# = Low, Figure 29.5). The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length bursts consist of four, eight, or sixteen words. Continuous bursts have the ability to start at a specified address and burst through the entire memory. The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is transferred between the processor and CellularRAM device. The Wait output asserts as soon as a burst is initiated, and de-asserts to indicate when data is to be transferred into (or out of) the memory. Wait will again be asserted if the burst crosses a row boundary. Once the CellularRAM device has restored the previous row's data and accessed the next row, Wait will be deasserted and the burst can continue (see Figure 34.9). To access other devices on the same bus without the timing penalty of the initial latency for a new burst, burst mode can be suspended. Bursts are suspended by stopping CLK. CLK can be stopped High or Low. If another device will use the data bus while the burst is suspended, OE# should be taken High to disable the CellularRAM outputs; otherwise, OE# can remain Low. Note that the Wait output will continue to be active, and as a result no other devices should directly share the Wait connection to the controller. To continue the burst sequence, OE# is taken Low, then CLK is restarted after valid data is available on the bus. See How Extended Timings Impact CellularRAM™ Operation for restrictions on the maximum CE# Low time during burst operations. If a burst suspension will cause CE# to remain Low for longer than t CEM, CE# should be taken High and the burs t restarted with a new CE# Low/ADV# low cycle. Figure 29.3 Page Mode Read Operation (ADV# Low) CE# OE# WE# ADDRESS DATA LB#/UB# Don't Care ADD[1] ADD[2] ADD[3] tAA D[0] tAPA D[1] tAPA D[2] tAPA D[3] ADD[0]

152 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

Note: Non-default BCR settings: Variable latency; latency code two (three clocks); Wait active Low; Wait asserted dur- ing delay. Figure 29.4 Burst Mode Read (4-word burst) Note: Non-default BCR settings: Variable latency; latency code two (three clocks); Wait active Low; Wait asserted dur- ing delay. Figure 29.5 Burst Mode Write (4-word burst) Don't care Undefined Legend: Latency Code 2 (3 clocks), variable READ Burst Identified (WE# = HIGH) CLK A[22:0] ADV# CE# OE# WE# WAIT DQ[15:0] LB#/UB# Address Valid Address Valid Latency Code 2 (3 clocks), variable WRITE Burst Identified (WE# = LOW) CLK A[22:0] ADV# CE# OE# WE# WAIT DQ[15:0] LB#/UB# Don't careLegend:

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 153 Advance Information

29.4 Mixed-Mode Operation

The device can support a combination of synchronous Read and asynchronous Write operations when the BCR is configured for synchronous op eration. The asynchronous Write operation re- quires that the clock (CLK) remain static (High or Low) during the entire sequence. The ADV# signal can be used to latch the target address, or it can remain Low during the entire Write oper- ation. CE# can remain Low when transitioning between mixed-mode operations with fixed latency enabled. Note that the tCKA period is the same as a Read or Write cycle. This time is required to ensure adequate refresh. Mixed-mode operation facilitates a seamless interface to legacy burst mode Flash memory controllers. See Figure 34.18, Asynchronous Write Followed by Burst Read (timing diagram).

29.5 Wait Operation

The Wait output on a CellularRAM device is typically connected to a shared, system-level Wait sig- nal (Figure 29.6). The shared Wait signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus. Once a Read or Write operation has been initiated, Wait goes active to indicate that the Cellular- RAM device requires additional time before data can be transferred. For Read operations, Wait will remain active until valid data is output from the device. For Write operations, Wait will indicate to the memory controller when data will be accepted into the CellularRAM device. When Wait tran- sitions to an inactive state, the data burst will progress on successive clock edges. CE# must remain asserted during Wait cycles (Wait asserted and Wait configuration BCR[8] = 1). Bringing CE# High during Wait cycles may cause data corruption. (Note that for BCR[8] = 0, the actual Wait cycles end one cycle after Wait de-asserts, and for row boundary crossings, start one cycle after the Wait signal asserts.) When using variable initial access latency (BCR[14] = 0), the Wait output performs an arbitration role for Read or Write operations launched while an on-chip refresh is in progress. If a collision occurs, the Wait pin is asserted for additional clock cycles until the refresh has completed (Figure 29.7 and Figure 29.8). When the refresh operation has completed, the Read or Write op- eration will continue normally. Wait is also asserted when a continuous Read or Write burst crosses the boundary between 128- word rows. The Wait assertion allows time for the new row to be accessed, and permits any pend- ing refresh operations to be performed. Wait will be asserted but should be ignored during asynchronous Read and Write, and page Read operations.

29.6 LB#/UB# Operation

The LB# enable and UB# enable signals support byte-wide data transfers. During Read opera- tions, the enabled byte(s) are driven onto the DQs. The DQs associated with a disabled byte are put into a High-Z state during a Read operation. During Write operations, any disabled bytes will Figure 29.6 Wired or Wait Configuration CellularRAM External Pull-Up/ Pull-Down Resistor Processor READY Other Device WAIT Other Device WAIT WAIT

154 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

not be transferred to the RAM array and the internal value will remain unchanged. During an asyn- chronous Write cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. When both the LB# and UB# are disabled (High) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as CE# remains Low. Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay. Figure 29.7 Refresh Collision During Read Operation Additional WAIT states inserted to allow refresh completion. CLK A[22:0] ADV# CE# OE# WE# WAIT DQ[15:0] LB#/UB# Don't care Undefined Legend: VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL High-ZVOH VOL VOH VOL Address Valid

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 155 Advance Information Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay. Figure 29.8 Refresh Collision During Write Operation Address Valid Additional WAIT states inserted to allow refresh completion. CLK A[22:0] ADV# CE# OE# WE# WAIT DQ[15:0] LB#/UB# Don't care Legend: VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL High-ZVOH VOL D[1] D[2] D[3] VOH VOL D[0]

156 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

30 Low-Power Operation

30.1 Standby Mode Operation

During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby operation occurs when CE# is High. The device will enter a reduced power state upon completion of a Read or Write operation, or when the address and control inputs remain static for an extended period of time. This mode will continue until a change occurs to the address or control inputs.

30.2 T emperature Compensated Refresh

Temperature compensated refresh (TCR) is used to adjust the refresh rate depending on the de- vice operating temperature. DRAM technology requires increasingly frequent refresh operation to maintain data integrity as temperatures increase. More frequent refresh is required due to in- creased leakage of the DRAM ca pacitive storage elements as temperatures rise. A decreased refresh rate at lower temperatures will facilitate a savings in standby current. TCR allows for adequate refresh at four different temperature thresholds (+15 °C, +45°C, +70°C, and +85°C). The setting selected must be for a temperature higher than the case temperature of the CellularRAM device. For example, if the case temperature is 50°C, the system can minimize self refresh current consumption by selecting the +7°0C setting. The +15°C and +45°C settings would result in inadequate refreshing and cause data corruption.

30.3 Partial Array Refresh

Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, three-quarter array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (Table 31.6). Read and Write operations to address ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will become corrupted. When re-enabling additional portions of the array, the new portions are avail- able immediately upon writing to the RCR.

30.4 Deep Power-Down Operation

Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will be- come corrupted when DPD is enabled. When refresh activity has been re-enabled by rewriting the RCR, the CellularRAM device will require 150µs to perform an initialization procedure before nor- mal operations can resume. During this 150µs period, the current consumption will be higher than the specified standby levels, but considerably lower than the active current specification. DPD cannot be enabled or disabled by writing to the RCR using the software access sequence; the RCR should be accessed using CRE instead.

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 157 Advance Information

31 Configuration Registers

Two user-accessible configuration registers define the device operation. The bus configuration register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up, and can be updated any time the devices are op- erating in a standby state.

31.1 Access Using CRE

The configuration registers can be written to using either a synchronous or an asynchronous op- eration when the configuration register enable (CRE) input is High (see Figure 31.1 and Figure 31.2). When CRE is Low, a Read or Write operation will access the memory array. The reg- ister values are written via address pins A[21:0]. In an asynchronous Write, the values are latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever oc- curs first; LB# and UB# are Don’t Care. The BCR is accessed when A[19] is High; the RCR is accessed when A[19] is Low. For Reads, address inputs other than A[19] are Don’t Care, and reg- ister bits 15:0 are output on DQ[15:0].

158 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

Note: A[19] = Low to load RCR; A[19] = High to load BCR. Figure 31.1 Configuration Register Write, Asynchronous Mode Followed by Read Select Control Register OPCODE ADDRESS tAVS tAVH ADDRESS tAVS tAVH tVPH tVP tCBPH Initiate Control Register Access tCW tWP Write Address Bus Value to Control Register DATA VALID Don't care Legend: A[22:0] (except A19) A19 (Note) CRE ADV# CE# OE# WE# LB#/UB# DQ[15:0]

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 159 Advance Information Figure 31.2 Configuration Register Write, Synchronous Mode Followed by Read0 Notes: 1. Non-default BCR settings: Latency code two (three cl ocks); Wait active Low; Wait asserted during delay. 2. A[19] = Low to load RCR; A[19] = High to load BCR. 3. CE# must remain Low to complete a burst-of-one Write. Wait must be monitored— additional Wait cycles caused by refresh collisions require a corresponding number of additional CE# Low cycles. Latch Control Register Value ADDRESS ADDRESS tHD OPCODE tSP Latch Control Register Address tSP tHD tSP tHD tCSP tCBPH (Note 3) High-ZHigh-Z tCEW DATA VALID CLK A[22:0] (except A19) A19 (Note 2) CRE ADV# CE# OE# WE# LB#/UB# WAIT DQ[15:0] Don't care Legend: tSP tHD

160 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

31.2 Bus Configuration Register

The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Table 31.1 below describes the control bits in the BCR. At powerup, the BCR is set to 9D4Fh. The BCR is accessed using CRE and A[19] High. T able 31.1 Bus Configuration Register Definition Note: Burst wrap and length apply to Read operations only. A13 11 0 Latency Counter Initial Latency 32 1 WAIT Polarity 45678 Output Impedance Burst Wrap (BW) (Note) A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Output Impedance Full Drive (default) 1/2 Drive 1/4 Drive Reserved BCR[5] BCR[4] Burst Length (BL) (Note) Reserved Reserved 910 Operating Mode WAIT Polarity Active LOW Active HIGH (default) BCR[10] Reserved 22–20 A14A15A[18:16] 19 18–16 Register SelectReserved A19A[22:20] Reserved Must be set to "0"Must be set to "0"All must be set to "0" Operating Mode Synchronous burst access mode Asynchronous access mode (default) BCR[15] Register Select Select RCR Select BCR BCR[19] Burst Wrap (Note) Burst wraps within the burst length Burst no wrap (default) BCR[3] Must be set to "0" Setting is ignored WAIT Configuration (WC) 1213 BCR[12] BCR[11] Latency CounterBCR[13] Code 0–Reserved Code 1–Reserved Code 2 Code 3 (Default) Code 4 Code 5 Code 6 Code 7–Reserved WAIT Configuration Asserted during delay Asserted one data cycle before delay (default) BCR[8] BCR[1] BCR[0] Burst Length (Note)BCR[2] 4 words 8 words 16 words Continuous burst (default) Reserved Must be set to "0" Others

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 161 Advance Information

31.2.1 Burst Length (BCR[2:0]): Default = Continuous Burst

Burst lengths define the number of words the device outputs during burst Read operations. The device supports a burst length of 4, 8, or 16 words. The device can also be set in continuous burst mode where data is accessed sequentially without regard to address boundaries. Enabling burst no-wrap with BCR[3] = 1 overrides the burst-length setting.

31.2.2 Burst Wrap (BCR[3]): Default = No Wrap

The burst-wrap option determines if a 4-, 8-, or 16-word Read burst wraps within the burst length or steps through sequential addresses. If the wrap option is not enabled, the device accesses data from sequential addresses without regard to burst boundaries. When continuous burst operation is selected, the internal address wraps to 000000h if the burst goes past the last address. En- abling burst nowrap (BCR[3] = 1) overrides the burst-length setting.

31.2.3 Output Impedance (BCR[5:4]) : Default = Outputs Use Full Drive

The output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus loading scenarios. The reduced-strength options are intended for stacked chip (Flash + CellularRAM) environments when there is a dedicated memory bus. The reduced-drive- T able 31.2 Sequence and Burst Length Burst Wrap Starting Address 4-word Burst Length 8-word Burst Length 16-wor d Burst Length Continuous Burst BCR[3] Wrap (Decimal) Linear Linear Linear Linear 0Y e s … …… 1N o … ……

162 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

strength option minimizes the noise generated on the data bus during Read operations. Normal output drive strength should be selected when using a discrete CellularRAM device in a more heavily loaded data bus environment. Outputs are configured at full drive strength during testing.

31.2.4 Wait Configuration (BCR[8]) : Default = Wait Transitions One

Clock Before Data Valid/Invalid The Wait configuration bit is used to determine when Wait transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. The memory controller will use the Wait signal to coordinate data transfer during synchronous Read and Write operations. When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after Wait transitions to the de-asserted or asserted state, respectively (Figure 31.3 and Figure 31.5). When A8 = 1, the Wait signal transitions one clock period prior to the data bus going valid or invalid (Figure 31.4).

31.2.5 Wait Polarity (BCR[10]): Default = Wait Active High

The Wait polarity bit indicates whether an asserted Wait output should be High or Low. This bit will determine whether the Wait signal requires a pull-up or pull-down resistor to maintain the de- asserted state. T able 31.3 Output Impedance BCR[5] BCR[4] DRIVE STRENGTH

00 F u l l

Note: Data valid/invalid immediately after Wait transitions (BCR[8] = 0). See Figure 31.5. Figure 31.3 Wait Configuration (BCR[8] = 0) Note: Valid/invalid data delayed for one clock after Wait transitions (BCR[8] = 1). See Figure 31.5. Figure 31.4 Wait Configuration (BCR[8] = 1) Data[0] Data[1] High-Z CLK WAIT DQ[15:0] Data immediately valid (or invalid) Data[0] High-Z CLK WAIT DQ[15:0] Data valid (or invalid) after one clock delay

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 163 Advance Information

31.2.6 Latency Counter (BCR[13:11]) : Default = Three-Clock Latency

The latency counter bits determine how many clocks occur between the beginning of a Read or Write operation and the first data value transferred. Latency codes from two (three clocks) to six (seven clocks) are allowed (see Table 31.4 and Figure 31.6 below). Note: Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is trans- ferred on the next clock cycle. Note: Non-default BCR setting: Wait active Low. Figure 31.5 Wait Configuration During Burst Operation T able 31.4 Variable Latency Configuration Codes BCR[13:11] Latency Configuration Code Latency (Note) Max Input Clk Frequency (MHz) Normal Refresh Collision 70 ns/80 MHz 85 ns/66 MHz 010 2 (3 clocks) 2 4 75 (13.0 ns) 44 (22.7 ns) 011 3 (4 clocks)—default 3 6 80 (12.5 ns) 66 (15.2 ns) 100 4 (5 clocks) 4 8 Figure 31.6 Latency Counter (Variable Initial Latency, No Refresh Collision) CLK WAIT WAIT DQ[15:0] BCR[8] = 0 DATA VALID IN CURRENT CYCLE BCR[8] = 1 DATA VALID IN NEXT CYCLE Don't care Legend: Code 2 Valid Output Valid Output Valid Output Valid Output Valid Address Valid Output Code 3 (Default) Valid Output Valid Output Valid Output Valid Output Code 4 Valid Output Valid Output Valid Output VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL VOH VOL CLK A[21:0] ADV# A/DQ[15:0] A/DQ[15:0] A/DQ[15:0] Don't care Undefined Legend:

164 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

31.2.7 Operating Mode (BCR[15]): Default = Asynchronous Operation

The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation.

31.3 Refresh Configuration Register

The refresh configuration register (RCR) defines how the CellularRAM device performs its trans- parent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the RCR. Table 31.5 below de- scribes the control bits used in the RCR. At power-up, the RCR is set to 0070h. The RCR is accessed using CRE and A[19] Low.

31.3.1 Partial Array Refresh (RCR[2 :0]): Default = Full Array Refresh

The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, three- quarters array, or none of the array. The mapping of these partitions can start at either the be- ginning or the end of the address map (see Table 31.6 through Table 31.8). T able 31.5 Refresh Configuration Register Mapping T able 31.6 128Mb Address Patterns for PAR (RCR[4] = 1) RCR[2] RCR[1] RCR[0] Active Section Address Space Size Density 0 0 0 Full die 000000h–7FFFFFh 8 Meg x 16 128Mb 0 0 1 One-half of die 000000h–3FFFFFh 4 Meg x 16 64Mb 0 1 0 One-quarter of die 000000h–1FFFFFh 2 Meg x 16 32Mb 0 1 1 One-eighth of die 000000h–0FFFFFh 1 Meg x 16 16Mb 1 0 0 None of die 0 0 Meg x 16 0Mb 1 0 1 One-half of die 400000h–7FFFFFh 4 Meg x 16 64Mb PAR A4 A3 A2 A1 A0 Read Configuration Register Address BusA5A6 All must be set to "0" Deep Power-Down DPD Enable DPD Disable (default) RCR[4] A[18:8] Register SelectReserved Reserved Reserved TCR A[22:20] A19 Register Select Select RCR Select BCR RCR[19] All must be set to "0" RCR[1] RCR[0] Refresh CoverageRCR[2] 0 0 Full array (default)0 0 1 Bottom 1/2 array0 1 0 Bottom 1/4 array0 1 1 Bottom 1/8 array0

011 Top 1/2 array

101 Top 1/4 array

Must be set to "0" Page Page Mode Enable/Disable Page Mode Disabled (default) Page Mode Enable RCR[7] 451 2306 18–81922–20 7

1 None of array00

1 Top 3/4 array11RCR[6] RCR[5] Maximum Case Temp

+85ºC (default)11 +70ºC +45ºC +15ºC

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 165 Advance Information

31.3.2 Deep Power-Down (RCR [4]): Default = DPD Disabled

The deep power-down bit enables and disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled, the Cellular- RAM device will require 150µs to perform an initialization procedure before normal operations can resume. Deep power-down is enabled when RCR[4] = 0, and remains enabled until RCR[4] is set to 1.

31.3.3 Temperature Compensated Refresh (RCR[6:5]): Default = +85ºC

The TCR bits allow for adequate refresh at four different temperature thresholds (+15ºC, +45ºC, +70ºC, and +85ºC). The setting selected must be for a temperature higher than the case tem- perature of the CellurlarRAM device. If the case temperature is +50ºC, the system can minimize self refresh current consumption by selecting the +70ºC setting. The +15ºC and +45ºC settings would result in inadequate refreshing and cause data corruption. 1 1 0 One-quarter of die 600000h–7FFFFFh 2 Meg x 16 32Mb 1 1 1 One-eighth of die 700000h–7FFFFFh 1 Meg x 16 16Mb T able 31.7 64Mb Address Patterns for PAR (RCR[4] = 1) RCR[2] RCR[1] RCR[0] Active Section Address Space Size Density 0 0 0 Full die 000000h–3FFFFFh 4 Meg x 16 64Mb 0 0 1 One-half of die 000000h–2FFFFFh 3 Meg x 16 48Mb 0 1 0 One-quarter of die 000000h–1FFFFFh 2 Meg x 16 32Mb 0 1 1 One-eighth of die 000000h–0FFFFFh 1 Meg x 16 16Mb 1 0 0 None of die 0 0 Meg x 16 0Mb 1 0 1 One-half of die 100000h–3FFFFFh 3 Meg x 16 48Mb 1 1 0 One-quarter of die 200000h–3FFFFFh 2 Meg x 16 32Mb 1 1 1 One-eighth of die 300000h–3FFFFFh 1 Meg x 16 16Mb T able 31.8 32Mb Address Patterns for PAR (RCR[4] = 1) RCR[2] RCR[1] RCR[0] ACTIVE SECTION ADDRESS SPACE SIZE DENSITY 0 0 0 Full die 000000h–1FFFFFh 2 Meg x 16 32Mb 0 0 1 One-half of die 000000h–17FFFFh 1.5 Meg x 16 24Mb 0 1 0 One-quarter of die 000000h–0FFFFFh 1 Meg x 16 16Mb 0 1 1 One-eighth of die 000000h–07FFFFh 512K x 16 8Mb 1 0 0 None of die 0 0 Meg x 16 0Mb 1 0 1 One-half of die 080000h–1FFFFFh 1.5 Meg x 16 24Mb 1 1 0 One-quarter of die 100000h–1FFFFFh 1 Meg x 16 16Mb 1 1 1 One-eighth of die 180000h–1FFFFFh 512K x 16 8Mb T able 31.6 128Mb Address Patterns for PAR (RCR[4] = 1) (Continued) RCR[2] RCR[1] RCR[0] Active Section Address Space Size Density

166 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

31.3.4 Page Mode Operation (RCR[7]): Default = Disabled

The page mode operation bit determines whether page mode is enabled for asynchronous Read operations. In the power-up default state, page mode is disabled.

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 167 Advance Information Voltage to Any Ball Except VCC, VCCQ Operating Temperature (case) Note: *Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

168 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

33 DC Characteristics

Notes: 1. Wireless Temperature (-25ºC < TC < +85ºC); Industrial Temperature (-40ºC < TC < +85ºC). 2. Input signals may overshoot to V CCQ + 1.0V for periods less than 2ns during transitions. 3. Input signals may undershoot to V SS - 1.0V for periods less than 2ns during transitions. 4. BCR[5:4] = 00b. 5. This parameter is specified with the outp uts disabled to avoid external loading effects. The user must add the current required to drive output capacitance expected in the actual system. 6. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR se t to +85°C. To achieve Low standby current, all inputs must be driven to either VCCQ or VSS. T able 33.1 Electrical Characteristics and Operating Conditions Description Conditions Symbol Min Max Units Notes Supply Voltage V CC 1.70 1.95 V I/O Supply Voltage V CCQ W: 1.8V 1.70 1.95 V J: 1.5V 1.35 1.65 V Input High Voltage V IH VCCQ - 0.4 V CCQ + 0.2 V 2 Input Low Voltage V IL -0.20 0.4 V 3 Output High Voltage I OH = -0.2mA V OH 0.80 VCCQV 4 Output Low Voltage I OL = +0.2mA V OL 0.20 VCCQV 4 Input Leakage Current V IN = 0 to VCCQI LI 1µ A Output Leakage Current OE# = VIH or Chip Disabled ILO 1µ A Operating Current Asynchronous Random Read VIN = VCCQ or 0V Chip Enabled, IOUT = 0 ICC1 -70 25 mA 5 -85 20 Asynchronous Page Read -70 15 -85 12 Initial Access, Burst Read VIN = VCCQ or 0V Chip Enabled, IOUT = 0 ICC1

80 MHz 35

66 MHz 30

80 MHz 18

66 MHz 15

IN = VCCQ or 0V Chip Enabled ICC2 -70 25 mA -85 20 Standby Current VIN = VCCQ or 0V CE# = VCCQ ISB

128 M 180

µA 664 M 120

32 M 110

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 169 Advance Information Note: IPAR (MAX) values measured with TCR set to 85°C. Ta bl e 3 3 . 3 Partial Array Refresh Specifications and Conditions Note:IPAR (MAX) values measured with TCR set to 85°C. T able 33.2 T emperature Compensated Refresh Specifications and Conditions Description Conditions Symbol Density Max Case Te m p e r a t u r e Standard Power (No Desig.) Units Temperature Compensated Refresh Standby Current VIN = VCCQ or 0V, CE# = VCCQ ITCR 64 Mb +85°C 120 µA +70°C 105 +45°C8 5 +15°C7 0 32 Mb +85°C 110 +70°C9 5 +45°C8 0 +15°C7 0 Description Conditions Symbol Density Array Partition Standard Power (No Desig.) Units Partially Array Refresh Standby Current VIN = VCCQ or 0V, CE# = VCCQ IPAR 64 Mb Full 120 µA 1/2 115 1/4 110 1/8 105 0 70 32 Mb Full 110 1/2 105 1/4 100 1/8 95 0 70 128 Mb Full 180 0 50 T able 33.4 Deep Power-Down Specifications Description Conditions Symbol T yp Units Deep Power-down V IN = VCCQ or 0V; +25°C; VCC = 1.8V I ZZ 10 µA

170 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

34 AC Characteristics

Notes: 1. AC test inputs are driven at V CCQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns. 2. Input timing begins at V CCQ/2. 3. Output timing ends at V CCQ/2. Figure 34.1 AC Input/Output Reference Waveform Note: All tests are performed with the outputs configured for full drive strength (BCR[5] = 0). Figure 34.2 Output Load Circuit T able 34.1 Output Load Circuit VCCQR 1 / R 2 1.8V 2.7K Ω OutputTest PointsInput (Note 1) VCCQ VSS VCCQ/2 (Note 2) VCCQ/2 (Note 3) DUT VCCQ R230pF Test Point

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 171 Advance Information Notes: 1. All tests are performed with the outputs conf igured for full drive strength (BCR[5] = 0). 2. See How Extended Timings Impact CellularRAM™ Operation below. 3. High-Z to Low-Z timings are tested with the circuit shown in Figure 34.2. The Low-Z timings measure a 4. 100mV transition away from the High-Z (V CCQ/2) level toward either VOH or VOL. 5. Low-Z to High-Z timings are tested with the circuit shown in Figure 34.2. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. T able 34.2 Asynchronous Read Cycle Timing Requirements Parameter Symbol 85ns/66 MHz 70ns/80 MHz Units Notes Min Max Min Max Address Access Time t AA 85 70 ns ADV# Access Time t AADV 85 70 ns Page Access Time t APA 25 20 ns Address Hold from ADV# High t AVH 55 n s Address Setup to ADV# High t AVS 10 10 ns LB#/UB# Access Time t BA 85 70 ns LB#/UB# Disable to DQ High-Z Output t BHZ 88 n s 4 LB#/UB# Enable to Low-Z Output t BLZ 10 10 ns 3 CE# High between Subsequent Mixed-Mode Operations t CBPH 55 n s Maximum CE# Pulse Width t CEM 44 µ s 2 CE# Low to Wait Valid t CEW 17 . 517 . 5 n s Chip Select Access Time t CO 85 70 ns CE# Low to ADV# High t CVS 10 10 ns Chip Disable to DQ and Wait High-Z Output t HZ 88 n s 4 Chip Enable to Low-Z Output t LZ 10 10 ns 3 Output Enable to Valid Output t OE 20 20 ns Output Hold from Address Change t OH 55 n s Output Disable to DQ High-Z Output t OHZ 88 n s 4 Output Enable to Low-Z Output t OLZ 55 n s 3 Page Cycle Time t PC 25 20 ns Read Cycle Time t RC 85 70 ns ADV# Pulse Width Low t VP 10 10 ns ADV# Pulse Width High t VPH 10 10 ns

172 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

Notes: 1. All tests are performed with the outputs conf igured for full drive strength (BCR[5] = 0). 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 34.2. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 3. High-Z to Low-Z timings are tested with the circuit shown in Figure 34.2. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. T able 34.3 Burst Read Cycle Timing Requirements Parameter Symbol 70ns/80 MHz 85ns/66 MHz Units NotesMin Max Min Max Burst to Read Access Time (Variable Latency) t ABA 35 55 ns CLK to Output Delay t ACLK 91 1 n s Address Setup to ADV# High t AVS 10 10 ns Burst OE# Low to Output Delay t BOE 20 20 ns CE# High between Subsequent Mixed-Mode Operations t CBPH 55 n s CE# Low to Wait Valid t CEW 1 7.5 1 7.5 ns CLK Period t CLK 12.5 15 ns CE# Setup Time to Active CLK Edge t CSP 45 n s Hold Time from Active CLK Edge t HD 22 n s Chip Disable to DQ and Wait High-Z Output t HZ 88 n s 2 CLK Rise or Fall Time t KHKL 1.6 1.6 ns CLK to Wait Valid t KHTL 91 1 n s CLK to DQ High-Z Output t KHZ 3838 n s CLK to Low-Z Output t KLZ 2525 n s Output Hold from CLK t KOH 22 n s CLK High or Low Time t KP 33 n s Output Disable to DQ High-Z Output t OHZ 88 n s 2 Output Enable to Low-Z Output t OLZ 55 n s 3 Setup Time to Active CLK Edge t SP 33 n s

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 173 Advance Information Notes: 1. See How Extended Timings Impact CellularRAM™ Operation below. 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 34.2. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 3. High-Z to Low-Z timings are tested with the circuit shown in Figure 34.2. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. T able 34.4 Asynchronous Write Cycle Timing Requirements Parameter Symbol 70 ns/80 MHz 85 ns/66 MHz Units NotesMin Max Min Max Address and ADV# Low Setup Time t AS 00 n s Address Hold from ADV# Going High t AVH 55 n s Address Setup to ADV# Going High t AVS 10 10 ns Address Valid to End of Write t AW 70 85 ns LB#/UB# Select to End of Write t BW 70 85 ns Maximum CE# Pulse Width t CEM 44 µ s 1 CE# Low to Wait Valid t CEW 1 7.5 1 7.5 ns Async Address-to-Burst Transition Time t CKA 70 85 ns CE# Low to ADV# High t CVS 10 10 ns Chip Enable to End of Write t CW 70 85 ns Data Hold from Write Time t DH 00 n s Data Write Setup Time t DW 23 23 ns 1 Chip Disable to Wait High-Z Output t HZ 88 n s Chip Enable to Low-Z Output t LZ 10 10 ns 3 End Write to Low-Z Output t OW 55 n s 3 ADV# Pulse Width t VP 10 10 ns ADV# Pulse Width High t VPH 10 10 ns ADV# Setup to End of Write t VS 70 85 ns Write Cycle Time t WC 70 85 ns Write to DQ High-Z Output t WHZ 88 n s 2 Write Pulse Width t WP 46 55 ns 1 Write Pulse Width High t WPH 10 10 ns Write Recovery Time t WR 00 n s

174 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

34.1 Timing Diagrams

T able 34.5 Burst Write Cycle Timing Requirements Parameter Symbol 70ns/80 MHz 85ns/66 MHz Units NotesMin Max Min Max CE# High between Subsequent Mixed-Mode Operations t CBPH 55 n s CE# Low to Wait Valid t CEW 1 7.5 1 7.5 ns Clock Period t CLK 12.5 15 ns CE# Setup to CLK Active Edge t CSP 45 n s Hold Time from Active CLK Edge t HD 22 n s Chip Disable to Wait High-Z Output t HZ 88 n s CLK Rise or Fall Time t KHKL 1.6 1.6 ns Clock to Wait Valid t KHTL 91 1 n s CLK High or Low Time t KP 33 n s Setup Time to Activate CLK Edge t SP 33 n s Figure 34.3 Initialization Period T able 34.1 Initialization Timing Parameters Parameter Symbol 70ns/80 MHz 85ns/66 MHz Units NotesMin Max Min Max Initialization Period (required before normal operations) t PU 150 150 µs tPUVCC, VCCQ = 1.7V VCC (MIN) Device ready for normal operation

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 175 Advance Information Figure 34.4 Asynchronous Read tOLZ tOE tLZ tBLZ tBA tCO tHZ tAA High-Z High-Z tBHZ tRC tOHZ Don't Care UndefinedLegend: VALID ADDRESS tCBPH VALID OUTPUT tHZtCEW High-Z VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL VIH VIL A[22:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT

176 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

T able 34.2 Asynchronous Read Timing Parameters Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tAA 70 85 ns tBA 70 85 ns tBHZ 88 n s tBLZ 10 10 ns tCBPH 55 n s tCEW 17 . 517 . 5 n s tCO 70 ns tHZ 88 n s tLZ 10 10 ns tOE 20 20 ns tOHZ 88 n s tOLZ 55 n s tRC 70 85 ns

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 177 Advance Information Figure 34.5 Asynchronous Read Using ADV# tOLZ tOE tLZ tBLZ tBA tCO tHZ tAA High-Z High-Z tBHZ tOHZ Don't Care UndefinedLegend: VALID ADDRESS tCBPH VALID OUTPUT tHZtCEW High-Z VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL VIH VIL A[22:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT tVPH tAVS tAVH tCVS tVP tAADV

178 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

T able 34.3 Asynchronous Read Timing Parameters Using ADV# Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tAA 70 85 ns tAADV 70 85 ns tCVS 10 10 ns tAVH 55 n s tAVS 10 10 ns tBA 70 85 ns tBHZ 88 n s tBLZ 10 10 ns tCBPH 55 n s tCEW 17 . 517 . 5 n s tCO 70 85 ns tCVS 10 10 ns tHZ 88 n s tLZ 10 10 ns tOE 20 20 ns tOHZ 88 n s tOLZ 55 n s tVP 10 10 ns tVPH 10 10 ns

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 179 Advance Information Figure 34.6 Page Mode Read tOLZ tOE tLZ tBLZ tBA tHZ tAA High-Z High-Z tBHZ tOHZ Don't Care UndefinedLegend: tCBPH tHZtCEW High-Z VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL VIH VIL A[22:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT tPC tCEM tCO tRC tCBPH VALID ADDRESS VIH VIL A[3:0] VALID ADDRESS VALID ADDRESS VALID ADDRESS VALID ADDRESS tAPA tOH VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT

180 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

T able 34.4 Asynchronous Read Timing Parameters—Page Mode Operation Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tAA 70 85 ns tAPA 20 25 ns tBA 70 85 ns tBHZ 88 n s tBLZ 10 10 ns tCBPH 55 n s tCEM 44 µ s tCEW 17 . 517 . 5 n s tCO 70 85 ns tHZ 88 n s tLZ 10 10 ns tOE 20 20 ns tOH 55 n s tOHZ 88 n s tOLZ 55 n s tPC 20 25 ns tRC 70 85 ns

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 181 Advance Information Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay. Figure 34.7 Single-Access Burst Read Operation—Variable Latency tOHZ tOLZ tACLK tKOH tHZ High-Z High-Z Don't Care UndefinedLegend: VALID ADDRESS VALID OUTPUT tKHTL tCEW High-Z VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL A[22:0] ADV# CE# LB#/UB# VOH VOL VOH VOL DQ[15:0] WAIT tSP tCLK tCSP tBOE tABA tKHKL tKP tKP VIH VIL CLK tSP tHD tHD tHD VIH VIL OE# WE# tSP tHD tSP tHD READ Burst Identified (WE# = HIGH)

182 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

T able 34.5 Burst Read Timing Parameters—Single Access, Variable Latency Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tABA 35 55 ns tACLK 91 1 n s tBOE 20 20 ns tCEW 17 . 517 . 5 n s tCLK 12.5 15 ns tCSP 45 n s tHD 22 n s tHZ 88 n s tKHKL 1.6 1.6 ns tKHTL 91 1 n s tKOH 22 n s tKP 33 n s tOHZ 88 n s tOLZ 55 n s tSP 33 n s

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 183 Advance Information Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay. Figure 34.8 Four-word Burst Read Operation—Variable Latency tOHZ tOLZ High-Z High-Z tCBPH Don't Care UndefinedLegend: tCEW High-Z VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL A[22:0] ADV# CE# LB#/UB# DQ[15:0] WAIT tSP tCSP tBOE tABA tSP tHD tHD VIH VIL OE# WE# tSP tHD tSP tHD READ Burst Identified (WE# = HIGH) Valid Address tCLKtKHKL tKP tKP VIH VIL CLK tHD tHZ VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT tKHTL tKOH tACLK

184 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

T able 34.6 Burst Read Timing Parameters—4-word Burst Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tABA 35 55 ns tACLK 91 1 n s tBOE 20 20 ns tCBPH 55 n s tCEW 17 . 517 . 5 n s tCLK 12.5 15 ns tCSP 45 n s tHD 22 n s tHZ 88 n s tKHKL 1.6 1.6 ns tKHTL 91 1 n s tKOH 22 n s tKP 33 n s tOHZ 88 n s tOLZ 55 n s tSP 33 n s

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 185 Advance Information Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay. Figure 34.9 Four-word Burst Read Operation (with LB#/UB#) tOHZ tOLZ High-Z High-Z tCBPH Don't Care UndefinedLegend: tCEW High-Z VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL A[22:0] ADV# CE# LB#/UB# DQ[15:0] WAIT tSP tCSP tBOE tSP tHD tHD VIH VIL OE# WE# tSP tHD tSP tHD READ Burst Identified (WE# = HIGH) Valid Address tCLK VIH VIL CLK tHD tHZ VALID OUTPUT VALID OUTPUT VALID OUTPUT tKHTL tKOH tACLK High-Z tKHTL tKHTLtKHTL

186 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

Ta bl e 3 4 . 7 B u rs t R e a d T i m i n g Pa r ameters—4-word Burst with LB#/UB# Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tACLK 91 1 n s tBOE 20 20 ns tCBPH 55 n s tCEW 17 . 517 . 5 n s tCLK 12.5 15 ns tCSP 45 n s tHD 22 n s tHZ 88 n s tKHTL 91 1 n s tKHZ 3838 n s tKLZ 2525 n s tKOH 22 n s tOHZ 88 n s tOLZ 55 n s tSP 33 n s

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 187 Advance Information Figure 34.10 Refresh Collision During Write Operation Notes: 1. Non-default BCR settings: Latency code two (three cl ocks); Wait active Low; Wait asserted during delay. 2. OE# can stay Low during burst suspend. If OE# is Low, DQ[15:0] will continue to output valid data. T able 34.8 Burst Read Timing Parameters—Burst Suspend Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tACLK 91 1 n s tBOE 20 20 ns tCBPH 55 n s tCLK 12.5 15 ns tCSP 45 n s tHD 22 n s tHZ 88 n s tKOH 22 n s tOHZ 88 n s tOLZ 55 n s tOHZ tOLZ High-Z High-Z tCBPH Don't Care UndefinedLegend: tCEW High-Z VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL VIH VIL A[22:0] ADV# CE# LB#/UB# DQ[15:0] WAIT tSP tCSP tBOE tSP tHD tHD VIH VIL OE# WE# tSP tHD tSP tHD tCLK VIH VIL CLK tHZ VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT tKOH tACLK (Note 2) tBOE tOLZ VALID OUTPUT VALID OUTPUT Valid Address tOHZ Valid Address

188 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

Notes: 1. Non-default BCR settings: Latency code two (three cl ocks); Wait active Low; Wait asserted during delay. 2. Wait will assert LC + 1 or 2LC + 1 cycles for variable latency (depending upon refresh status). Figure 34.9. Continuous Burst Read Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition T able 34.10 Burst Read Timing Parameters—BCR[8] = 0 Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tACLK 91 1 n s tCLK 12.5 15 ns tKHTL 91 1 n s tKOH 22 n s T able 34.8 Burst Read Timing Parameters—Burst Suspend (Continued) Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tOHZ Don't CareLegend: VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL A[22:0] ADV# CE# LB#/UB# WAIT VIH VIL OE# WE# tCLK VIH VIL CLK (Note 2) tKHTL tKHTL VOH VOL DQ[15:0] tKOHtACLK VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 189 Advance Information Figure 34.11 CE#-Controlled Asynchronous Write tDH tWP tDW tWHZ tBW tAA High-Z High-Z tLZ Don't CareLegend: VALID ADDRESS tHZtCEW High-Z VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL A[22:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] IN WAIT tAS tAW tWR tCW tCEM tWPH VOH VOL DQ[15:0] OUT VALID INPUT

190 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

T able 34.11 Asynchronous Write Timing Parameters—CE#-Controlled Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tAS 00 n s tAW 70 85 ns tBW 70 85 ns tCEM 44 µ s tCEW 17 . 517 . 5 n s tCW 70 85 ns tDH 00 n s tDW 23 23 ns tHZ 88 n s tLZ 10 10 ns tWC 70 85 ns tWHZ 88 n s tWP 46 55 ns tWPH 10 10 ns tWR 00 n s

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 191 Advance Information Figure 34.12 LB#/UB#-Controlled Asynchronous Write tDH tWP tDW tWHZ tBW tWC High-Z High-Z tLZ Don't CareLegend: VALID ADDRESS tHZtCEW High-Z VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL A[22:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] IN WAIT tAS tAW tWR tCW tCEM tWPH VOH VOL DQ[15:0] OUT VALID INPUT

192 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

T able 34.12 Asynchronous Write Timi ng Parameters—LB#/UB#-Controlled Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tAS 00 n s tAW 70 85 ns tBW 70 85 ns tCEM 44 µ s tCEW 17 . 517 . 5 n s tCW 70 85 ns tDH 00 n s tDW 23 23 ns tHZ 88 n s tLZ 10 10 ns tWC 70 85 ns tWHZ 88 n s tWP 46 55 ns tWPH 10 10 ns tWR 00 n s

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 193 Advance Information Figure 34.13 WE#-Controlled Asynchronous Write tDH tWP tDW tWHZ tBW tWC High-Z High-Z tLZ Don't CareLegend: VALID ADDRESS tHZtCEW High-Z VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL A[22:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] IN WAIT tAW tWR tCW tCEM tWPH VOH VOL DQ[15:0] OUT VALID INPUT tOW tAS

194 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

T able 34.13 Asynchronous Write Timing Parameters—WE#-Controlled Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tAS 00 n s tAW 70 85 ns tBW 70 85 ns tCEM 44 µ s tCEW 17 . 517 . 5 n s tCW 70 85 ns tDH 00 n s tDW 23 23 ns tHZ 88 n s tLZ 10 10 ns tOW 55 n s tWC 70 85 ns tWHZ 88 n s tWP 46 55 ns tWPH 10 10 ns tWR 00 n s

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 195 Advance Information Figure 34.14 Asynchronous Write Using ADV# tDH tWP tDW tWHZ tBW High-Z High-Z tLZ Don't CareLegend: tHZtCEW High-Z VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL A[22:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] IN WAIT tAVS tCW tCEM tWPH VOH VOL DQ[15:0] OUT VALID INPUT tOW tAS VALID ADDRESS tAW tAVH tVS tVPtVPH tAS

196 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

T able 34.14 Asynchronous Write Timing Parameters Using ADV# Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tAS 00 n s tAVH 55 n s tAVS 10 10 ns tAW 70 85 ns tBW 70 85 ns tCEM 44 µ s tCEW 17 . 517 . 5 n s tCW 70 85 ns tDH 00 n s tDW 23 23 ns tHZ 88 n s tLZ 10 10 ns tOW 55 n s tAS 00 n s tVP 10 10 ns tVPH 10 10 ns tVS 70 85 ns tWHZ 88 n s tWP 46 55 ns tWPH 10 10 ns

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 197 Advance Information Notes: 1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay; burst length four; burst wrap enabled. Figure 34.15 Burst Write Operation tOHZ High-Z Don't CareLegend: tCEW High-Z VIH VIL VIH VIL VIH VIL VOH VOL VIH VIL A[22:0] ADV# DQ[15:0] WAIT tSP tSP tHD tHD VIH VIL OE# WE# tSP tHD VIH VIL LB#/UB# tSP tHD READ Burst Identified (WE# = LOW) tCLK tKHKL tKP tKP VIH VIL CLK tHZ tKHTL tHDtSP Valid Address tCBPH VIH VIL CE# tCSP tHD (Note 2)

198 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

T able 34.15 Burst Write Timing Parameters Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tCBPH 55 n s tCEW 17 . 517 . 5 n s tCLK 12.5 15 ns tCSP 45 n s tHD 22 n s tHZ 88 n s tKHKL 1.6 1.6 ns tKHTL 91 1 n s tKP 33 n s tSP 33 n s Notes: 1. Non-default BCR settings: Latency code two (three cl ocks); Wait active Low; Wait asserted during delay. 2. Wait will assert LC + 1 or 2LC + 1 cycles for variable latency (depending upon refresh status). Figure 34.16 Continuous Burst Write Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition Don't CareLegend: VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL A[22:0] ADV# CE# LB#/UB# WAIT tCLK VIH VIL CLK (Note 2) VIH VIL OE# tOHZ VIH VIL WE# tKHTL tKHTL VOH VOL DQ[15:0] tHDtSP Valid Input D[n] Valid Input D[n+1] Valid Input D[n+3] Valid Input D[n+2] END OF ROW

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 199 Advance Information T able 34.16 Burst Write Timing Parameters—BCR[8] = 0 Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tCLK 12.5 15 ns tHD 22 n s tKHTL 81 1 n s tSP 33 n s Notes: 1. Non-default BCR settings: Latency code two (three cl ocks); Wait active Low; Wait asserted during delay. 1. To allow self-refresh operations to occur between transactions, CE# must remain High for at least 5ns (t CBPH) to schedule the appropriate internal refresh operation. CE# can stay Low between burst Read and burst Write operations. See How Extended Timings Impact CellularRAM™ Operation for restrictions on the maximum CE# Low time (tCEM). Figure 34.17 Burst Write Followed by Burst Read T able 34.17 Write Timing Parameters—Burst Write Followed by Burst Read Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tCBPH 55 n s tCLK 12.5 20 15 20 ns tCSP 4 2 052 0 n s tHD 22 n s tSP 33 n s tOHZ High-Z High-Z tCBPH High-Z VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL A[22:0] ADV# CE# LB#/UB# DQ[15:0] WAIT tSP tCSP tSP tHD tHD VIH VIL OE# WE# tSP tHD tCLK VIH VIL CLK tHD tBOE Valid Address tSP tHD Valid Address tSP tHD (Note 2) tCSP tSP tHD tSP tHD D[0] D[3]D[2]D[1] Valid Output Valid Output Valid Output Valid Output VOH VOL tKOHtACLKtSP tHD High-Z Don't Care Undefine dLegend:

200 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

T able 34.18 Read Timing Parameters—Burst Write Followed by Burst Read Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tACLK 91 1 n s tBOE 20 20 ns tCLK 12.5 15 ns tCSP 45 n s tHD 22 n s tKOH 22 n s tOHZ 88 n s tSP 33 n s Notes: 1. Non-default BCR settings: Latency code two (three cl ocks); Wait active Low; Wait asserted during delay. 1. When transitioning between asynchronous and variable-latency burst operations, CE# must go High. If CE# goes High, it must re main High for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See How Extended Timings Impact CellularRAM™ Operation for restrictions on the maximum CE# Low time (tCEM). Figure 34.18 Asynchronous Write Followed by Burst Read tOHZ High-Z High-Z VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL A[22:0] ADV# CE# LB#/UB# DQ[15:0] WAIT tCSP tSP tHD VIH VIL OE# WE# tSP tHD tCLK VIH VIL CLK tBOE Valid Address tWC tWC (Note 2) tWP tWPH tSP tHD Valid Output Valid Output Valid Output Valid Output VOH VOL tKOH tACLK High-Z Don't Care UndefinedLegend: Valid Address Valid Address tCKA tSP tHD tBW tCW tAW tWR tCBPH tWC tCEW DATA tWHZ DATA tVPH tAVS tAVH tVP tVS tCVS tAS tDH tDW

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 201 Advance Information T able 34.19 Write Timing Parameters—Asynchronous Write Followed by Burst Read Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tAVH 55 n s tAS 00 n s tAVS 10 10 ns tAW 70 85 ns tBW 70 85 ns tCKA 70 85 ns tCVS 10 10 ns tCW 70 85 ns tDH 00 n s tDW 20 23 ns tVP 10 10 ns tVPH 10 10 ns tVS 70 85 ns tWC 70 85 ns tWHZ 88 n s tWP 46 55 ns tWPH 10 10 ns tWR 00 n s T able 34.20 Read Timing Parameters—Asynchronous Write Followed by Burst Read Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tACLK 91 1 n s tBOE 20 20 ns tCBPH 55 n s tCEW 17 . 517 . 5 n s tCLK 12.5 15 ns tCSP 45 n s tHD 22 n s tKOH 22 n s tOHZ 88 n s tSP 33 n s

202 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

Notes: 1. Non-default BCR settings: Latency code two (three cl ocks); Wait active Low; Wait asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go High. If CE# goes High, it must re main High for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See How Extended Timings Impact CellularRAM™ Operation for restrictions on the maximum CE# Low time (tCEM). Figure 34.19 Asynchronous Write (ADV# Low) Followed By Burst Read tOHZ High-Z High-Z VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL A[22:0] ADV# CE# LB#/UB# DQ[15:0] WAIT tCSP tSP tHD VIH VIL OE# WE# tSP tHD tCLK VIH VIL CLK tBOE Valid Address tWC tWC (Note 2) tWP tWPH tSP tHD Valid Output Valid Output Valid Output Valid Output VOH VOL tKOHtACLK High-Z Don't Care UndefinedLegend: Valid Address Valid Address tCKA tSP tHD tBW tCW tAW tWR tCSP tWC tCEW DATA tDH tWHZ DATA tDW

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 203 Advance Information T able 34.21 Asynchronous Write Timing Parameters—ADV# Low Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tAW 70 85 ns tBW 70 85 ns tCKA 70 85 ns tCW 70 85 ns tDH 00 n s tDW 23 23 ns tWC 70 85 ns tWHZ 88 n s tWP 46 55 ns tWPH 10 10 ns tWR 00 n s T able 34.22 Burst Read Timing Parameters Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tACLK 91 1 n s tBOE 20 20 ns tCBPH 55 n s tCEW 17 . 517 . 5 n s tCLK 12.5 15 ns tCSP 45 n s tHD 22 n s tKOH 22 n s tOHZ 88 n s tSP 33 n s

204 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

Notes: 1. Non-default BCR settings: Latency code two (three cl ocks); Wait active Low; Wait asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go High. If CE# goes High, it must re main High for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See How Extended Timings Impact CellularRAM™ Operation for restrictions on the maximum CE# Low time (tCEM). Figure 34.23. Burst Read Followed by Asynchronous Write (WE#-Controlled) Valid Address tSP tHD tOHZ High-Z High-Z VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL A[22:0] ADV# CE# DQ[15:0] WAIT tHD tWC VIH VIL OE# WE# tCLK VIH VIL CLK tSP tHD (Note 2) tWP tWPHtSP tHD Valid Output tCBPH tKOHtACLK Don't Care UndefinedLegend: Valid Address VIH VIL LB#/UB# tOLZ tAW tWR tCSP tBW tDH tKHTL tDW tSP tHD tHZ tBOE tCEM tCW tAS tCEW tCEW tHZ READ Burst Identified (WE# = HIGH) High-Z Valid Input

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 205 Advance Information T able 34.24 Burst Read Timing Parameters Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tACLK 91 1 n s tBOE 20 20 ns tCBPH 55 n s tCEW 17 . 517 . 5 n s tCLK 12.5 15 ns tCSP 45 n s tHD 22 n s tHZ 88 n s tKHKL 1.6 1.6 ns tKHTL 91 1 n s tKOH 22 n s tKP 33 n s tOHZ 88 n s T able 34.25 Asynchronous Write Timing Parameters—WE# Controlled Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tAS 00 n s tAW 70 85 ns tBW 70 85 ns tCEM 44 µ s tCW 70 85 ns tDH 00 n s tDW 23 23 ns tHZ 88 n s tWC 70 85 ns tWP 46 55 ns tWPH 10 10 ns tWR 00 n s

206 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

Notes: 1. Non-default BCR settings: Latency code two (three cl ocks); Wait active Low; Wait asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go High. If CE# goes High, it must re main High for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See How Extended Timings Impact CellularRAM™ Operation for restrictions on the maximum CE# Low time (tCEM). Figure 34.26. Burst Read Followed by Asynchronous Write Using ADV# Valid Address tSP tHD tOHZ High-Z High-Z VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL A[22:0] ADV# CE# DQ[15:0] WAIT tHD VIH VIL OE# WE# tCLK VIH VIL CLK tSP tHD (Note 2) tWP tWPHtSP tHD Valid Output Valid Input tCBPH tKOHtACLK Don't Care UndefinedLegend: Valid Address tAS VIH VIL LB#/UB# tOLZ tAVS tAVH tCSP tBW tDH tKHTL tDW tSP tHD tHZ tBOE tCEM tAW tCW tVS tVP tVPH tAS tCEW tCEW tHZ READ Burst Identified (WE# = HIGH) High-Z

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 207 Advance Information T able 34.27 Burst Read Timing Parameters Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tACLK 91 1 n s tBOE 20 20 ns tCBPH 55 n s tCEW 17 . 517 . 5 n s tCLK 12.5 15 ns tCSP 45 n s tHD 22 n s tHZ 88 n s tKHKL 1.6 1.6 ns tKHTL 91 1 n s tKOH 22 n s tKP 33 n s tOHZ 88 n s T able 34.28 Asynchronous Write Timing Parameters Using ADV# Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tAS 00 n s tAVH 55 n s tAVS 10 10 ns tAW 70 85 ns tBW 70 85 ns tCEM 44 µ s tCEW 17 . 517 . 5 n s tCW 70 85 ns tDH 00 n s tDW 23 23 ns tHZ 88 n s tVP 10 10 ns tVPH 10 10 ns tVS 70 85 ns tWP 46 55 ns tWPH 10 10 ns tWR 00 n s

208 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

Note: CE# can stay Low when transitioning between asynchronous operations. If CE# goes High, it must remain High for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See How Extended Timings Impact Cel- lularRAM™ Operation for restrictions on the maximum CE# Low time (tCEM). Figure 34.29. Asynchronous Write Followed by Asynchronous Read—ADV# Low tOHZ High-Z High-Z VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL A[22:0] ADV# CE# LB#/UB# DQ[15:0] WAIT tCEM VIH VIL OE# WE# tBLZ tOE Valid Address (Note) tWP tWPH Valid Output VOH VOL tOLZ Don't Care UndefinedLegend: Valid Address Valid Address tBW tCW tAW tWR tCBPH tWC DATA tWHZ DATA tAS tDH tDW tHZ tHZ tBHZ tAA tHZ tLZ

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 209 Advance Information T able 34.30 Write Timing Parameters—ADV# Low Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tAS 00 n s tAW 70 85 ns tBW 70 85 ns tCW 70 85 ns tDH 00 n s tDW 23 23 ns tHZ 88 n s tWC 70 85 ns tWHZ 88 n s tWP 46 55 ns tWPH 10 10 ns tWR 00 n s T able 34.31 Read Timing Parameters—ADV# Low Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tAA 70 85 ns tBHZ 88 n s tBLZ 10 10 ns tCBPH 55 n s tCEM 44 µ s tHZ 88 n s tLZ 10 10 ns tOE 20 20 ns tOHZ 88 n s tOLZ 55 n s

210 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

Note: CE# can stay Low when transitioning between asynchronous operations. If CE# goes High, it must remain High for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See How Extended Timings Impact Cel- lularRAM™ Operation for restrictions on the maximum CE# Low time (tCEM). Figure 34.32. Asynchronous Write Followed by Asynchronous Read tOHZ High-Z High-Z VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL A[22:0] ADV# CE# LB#/UB# DQ[15:0] WAIT tCEM VIH VIL OE# WE# tBLZ tOLZ Valid Address (Note) tWP tWPH Valid Output VOH VOL tOE Don't Care UndefinedLegend: Valid Address Valid Address tBW tCW tAW tWR tCBPH tWC DATA tWHZ DATA tAS tDH tDW tBHZ tAA tHZ tLZ tAVS tAVH tVPH tVP tVS tCVS tAS

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 211 Advance Information T able 34.33 Write Timing Parameters—Asynchronous Write Followed by Asynchronous Read Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tAS 00 n s tAVH 55 n s tAVS 10 10 ns tAW 70 85 ns tBW 70 85 ns tCVS 10 10 ns tCW 70 85 ns tDH 00 n s tDW 23 23 ns tVP 10 10 ns tVPH 10 10 ns tVS 70 85 ns tWC 70 85 ns tWHZ 88 n s tWP 46 55 ns tWPH 10 10 ns tWR 00 n s T able 34.34 Read Timing Parameters—Asynchronous Write Followed by Asynchronous Read Symbol 70ns/80 MHz 85ns/66 MHz UnitsMin Max Min Max tAA 70 85 ns tBHZ 88 n s tBLZ 10 10 ns tCBPH 55 n s tCEM 44 µ s tHZ 88 n s tLZ 10 10 ns tOE 20 20 ns tOHZ 88 n s tOLZ 55 n s

212 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

35 How Extended Timings Impact CellularRAM™ Operation

35.1 Introduction

This section describes CellularRAM™ timing requirements in systems that perform extended operations. CellularRAM products use a DRAM technology that periodically requires refresh to ensure against data corruption. CellularRAM devices include on-chip circuitry that performs the required refresh in a manner that is completely transparent in systems with normal bus timings. The refresh cir- cuitry imposes constraints on timings in systems that take longer than 4µs to complete an operation. Write operations are affected if the device is configured for asynchronous operation. Both Read and Write operations are affected if the device is configured for page or burst-mode operation.

35.2 Asynchronous Write Operation

The timing parameters provided in Figure 34.4 require that all Write operations must be com- pleted within 4µs. After completing a Write operation, the device must either enter standby (by transitioning CE# High), or else perform a second operation (Read or Write) using a new address. Figure 35.1 and Figure 35.2 demonstrate these constraints as they apply during an asynchronous (page-mode-disabled) operation. Either the CE# active period (t CEM in Figure 35.1) or the ad- dress valid period (t TM in Figure 35.2 ) must be less than 4µs during any Write operation, otherwise, the extended Write timings must be used. Figure 35.1 Extended Timing for t CEM Figure 35.2 Extended Timing for t TM T able 35.1 Extended Cycle Impact on Read and Write Cycles Page Mode Timing Constraint Read Cycle Write Cycle Asynchronous Page Mode Disabled tCEM and tTM > 4µs (See Figure 35.1 and Figure 35.2.) No impact. Must use extended Write timing. (See Figure 35.2) Asynchronous Page Mode Enabled tCEM > 4µs (See Figure 35.1.) All following intrapage Read access times are tAA (not tAPA). Must use extended Write timing. (See Figure 35.3) Burst t CEM > 4µs (See Figure 35.1.) Burst must cross a row boundary within 4µs. CE# ADDRESS tCEM 4 μs< CE# ADDRESS TM <t 4μs

February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 213 Advance Information

35.2.1 Extended Write Timing— Asynchronous Write Operation

Modified timings are required during extended Write operations (see Figure 35.3). An extended Write operation requires that both the Write pulse width (tWP) and the data valid period (tDW) be lengthened to at least the minimum Write cycle time (tWC [MIN]). These increased timings ensure that time is available for both a refresh operation and a successful completion of the Write operation.

35.3 Page Mode Read Operation

When a CellularRAM device is configured for page mode operation, the address inputs are used to accelerate Read accesses and cannot be used by the on-chip circuitry to schedule refresh. If CE# is Low longer than the tCEM maximum time of 4µs during a Read operation, the system must allow tAA (not tAPA, as would otherwise be expected) for all subsequent intrapage accesses until CE# goes High.

35.4 Burst-Mode Operation

When configured for burst-mode operation, it is necessary to allow the device to perform a refresh within any 4µs window. One of two conditions will enable the device to schedule a refresh within 4µs. The first condition is when all burst operations complete within 4µs. A burst completes when the CE# signal is registered High on a rising clock edge. The second condition that allows a refresh is when a burst access crosses a row boundary. The row-boundary crossing causes Wait to be asserted while the next row is accessed and enables the scheduling of refresh.

35.5 Summary

CellularRAM products are designed to ensure that any possible asynchronous timings do not cause data corruption due to lack of refresh. Slow bus timings on asynchronous Write operations require that tWP and tDW be lengthened. Slow bus timings during asynchronous page Read oper- ations cause the next intrapage Read data to be delayed to tAA. Burst mode timings must allow the device to perform a refresh within any 4µs period. A burst operation must either complete (CE# registered High) or cross a row boundary within 4µs to en- sure successful refresh scheduling. These timing requirements are likely to have little or no impact when interfacing a CellularRAM device with a low-speed memory bus. Figure 35.3 Extended Write Operation tCEM or t TM > 4 μs tWP > t WC (MIN) tDW > t WC (MIN) ADDRESS CE# LB#/UB# WE# DATA-IN

214 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005

36 Revisions

Revision A0 (February 17, 2005) Initial Release Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with above- mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on ex- port under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright ©2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.