S75NS-N SPANSION | Alldatasheet
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Publication Number S75NS-N_00 Revision 01E Issue Date May 3, 2006 S75NS-N S75NS-N Cover Sheet S29NS-N: MirrorBit
1.8 Volt-only Simultaneous Read/
Write, Burst-mode Multiplexed Flash (NOR Interface) S30MS-P: ORNAND Flash (NAND interface) Multiplexed Synchronous pSRAM Data Sheet (Advance Information) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
ii S75NS-N May 3, 2006 S75NS-N_00-01E Data Sheet (Advance Information) Notice On Data Sheet Designations Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or V IO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.
This document contains information on one or more products under development at Spansion LLC. The information is intended to he lp you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice. Publication Number S75NS-N_00 Revision 01E Issue Date May 3, 2006
Features
/G132Power supply voltage of 1.7 V to 1.95 V /G132Burst Speed: 66 MHz /G132Package - MCP BGA: 0.5 mm ball pitch – 11 x 13 x 1.4 mm, 112 ball /G132Operating Temperature – Wireless, –25°C to +85°C General Description The S75NS-N Series is a product line of stacked Multi-Chip Product (MCP) packages and consists of the following items: /G132S29NS-N /G132S30MS-P /G132Mux pSRAM The products covered by this document are listed in the tables below. Product Selector Guide For detailed specifications, please refer to the individual data sheets: S75NS-N S29NS-N: MirrorBit™ 1.8 Volt-only Simultaneous Read/ Write, Burst-mode Multiplexed Flash (NOR Interface) S30MS-P: ORNAND™ Flash (NAND interface) Multiplexed Synchronous pSRAM Data Sheet (Advance Information) S29NS128 + pSRAM 32 Mb S30MS512P S75NS128NBF S30MS01GP S75NS128NBG Device pSRAM Density pSRAM Type S75NS128NBF 32 Mb Multiplexed pSRAM Type 3 S75NS128NBG 32 Mb Multiplexed pSRAM Type 3 Document Publication Identification Number S29NS-N S29NS-N_00 S30MS-P S30MS-P_00
32 Mb Multiplexed pSRAM Type 3 muxpsram_04
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Data Sheet (Advance Information) 1. Ordering Information The ordering part number is formed by a valid combination of the following:
1.1 Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.Notes: 1. Type 0 is standard. Specify other options as required. 2. The package marking omits the leading S and packing type designator from the ordering part number. 3. Contact factory for availability of any of the OPNs listed because RAM type availability may vary over time. S75NS 128 N B G J W JZ 0 Packing Type 0 = Tray 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel Model Number Refer to the Valid Combinations table below Temperature Range W = Wireless (-25°C to +85°C) Package Type J = 1.4 mm height, 0.5mm ball size, Thin Fine-Pitch Ball Grid Array (FBGA) Lead (Pb)-free Package (LF35) ORNAND Data Density F = 512 Mb G = 01 Gb pSRAM Density B = 32 Mb C = 64 Mb Process Technology N = 110 nm MirrorBit Technology Flash Density 256 = 256 Mb 128 = 128 Mb Device Family S75NS = Multi-Chip Product 1.8 Volt-only Simultaneous Read/ Write Burst Mode Multiplexed Flash Memory + pSRAM + ORNAND Data Storage Table 1.1 MCP Configurations and Valid Combinations Base Ordering Part Number (Note 2) Package & Temperature Model Number Packing Type pSRAM Type Flash Speed Options pSRAM Speed Options S75NS128NBF UJW JZ 0, 2, 3 pSRAM Type 3 66 MHz 66 MHz S75NS128NBG JZ pSRAM Type 3 66 MHz 66 MHz
S75NS-N_00_01E May 3, 2006 S75NS-N 3 Data Sheet (Advance Information) 2. Input/Output Descriptions Table 2.1 identifies the input and output package connections provided on the device. Table 2.1 Input/Output Descriptions Symbol Signal Type Description NS (NOR) pSRAM MS (ORNAND) AMAX – A16 Input Address inputs X X ADQ15 – ADQ0 I/O Multiplexed Address/Data X X OE# Input Output Enable input. Asynchronous relative to CLK for the Burst mode. XX WE# Input Write Enable input. X X V SS Ground Ground X X F-RDY / R-WAIT Output Ready output. Indicates the status of the Burst read. The WAIT# pin of the pSRAM is tied to RDY . XX CLK Input Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Should be at V IL or VIH while in asynchronous mode XX AVD# Input Address Valid input. Indicates to device that the valid address is present on the address inputs. Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. High = device ignores address inputs XX F-RST# Input Hardware reset input. Low = device resets and returns to reading array data X F-WP# Input Hardware write protect input. At V IL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. X F-ACC Input Accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. X F-CE# Input Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode. X VCC Power Flash 1.8 Volt-only single power supply X X R-CE1# Input Chip-enable input for pSRAM X R-CRE Input Control Register Enable (pSRAM) X R-V CC Power pSRAM Power Supply X R-UB# Input Upper Byte Control (pSRAM) X R-LB# Input Lower Byte Control (pSRAM) X N-CLE Input Command Latch Enable X N-ALE Input Address Latch Enable X N-CE# Input Chip Enable input for ORNAND X N-WE# Input Write Enable input X N-RE# Input Read Enable input X N-IO0 - N-IO7 I/O Data Input/Output X N-WP# Input Hardware write protect input. At V IL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. X N-RY/BY# Input Ready/Busy output X N-PRE Input Power-On Read Enable X N-VSS Ground Ground X N-VCC Power ORNAND 1.8 Volt-only single power supply. X DNU — Do Not Use NC — No Connect; not connected internally
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Data Sheet (Advance Information) 3. MCP Block Diagram Figure 3.1 MCP Block Diagram 4. Connection Diagrams /Physical Dimensions This section contains the I/O designations and package specifications for the S71NS-N.
4.1 Special Handling Instru ctions for FBGA Packages
Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. A21-A22 A21-A22 F-RST# RST# A15-A0 ADQ15-ADQ0 DQ15-DQ0 F-ACC ACC CLK CL K F-WP# WP# RDY F-RDY/R-WAI T F-CE# CE# OE# OE# WE# WE# A16-A20 A16-A20 AVD# AVD# VCC VCC VSS VSS VCCQ VCCQ VSSQ VSSQ R-UB# UB# A15-A0 DQ15-DQ0 R-LB# LB# CLK WAIT R-CE1# CE# OE# WE# A16-A20 AVD# R-CRE CRE VCC VSS VCCQ VSSQ I/O0-I/O7 N-IO0 - N-IO7 N-RY/BY# RB# N-CLE CLE N-CE# CE# N-ALE ALE VSS N-VSS N-RE# RE# N-WP# WP# N-WE# WE# VCC N-VCC x8 ORNAND Flash Memory Mux FLASH MEMORY Mux Sync pSRAM MEMORY N-PRE PRE
S75NS-N_00_01E May 3, 2006 S75NS-N 5 Data Sheet (Advance Information)
4.2 Connection Diagrams
Note: Addresses are shared between Flash and RAM depending on the density of the pSRAM. MCP Flash-Only Addresses Shared Addresses Shared ADQ Pins S75NS128NBG A22-A21 A20-A16 ADQ15 – ADQ0 S75NS128NBF A22-A21 A20-A16 ADQ15 – ADQ0 329 1 0 547 681 1312 15 14 17 16 1811 NC NC B D E F G H J K L M N P A C NC NC NCNC NC NC NC NC NCNC DNU DNU DNUN-IO7 NC NC DNU R-LB# R-UB#DNUN-RDY DNU N-IO5 N-IO6DNU DNU N-CE# VCC WE# F-RDY/ R-WAIT N-RE# VSS A21 CLK A17 A19 N-IO4A22 DNUF-ACC N-VCC DNU F-RST#VCCQN-VCC A20 A16 AVD# F-CE#A18 DNU VSSQ N-PREF-WP# N-VSS A/DQ12 A/DQ3VSSN-VSS A/DQ6 A/DQ7 A/DQ13 A/DQ8 A/DQ9 N-VCCOE# N-VSSA/DQ2 N-CLE A/DQ4 A/DQ11A/DQ15N-ALE VSSQ A/DQ14 A/DQ5 A/DQ1 VCCQ DNU A/DQ0 N-IO3A/DQ18 DNU R-CE# R-CREN-WP#N-WE# DNU VSS DNU N-IO1 N-IO2 NCNC DNU DNU DNUN-IO8 NC NC NCNC NC NC NC NC NC NC NC NC Legend NOR Flash/pSRAM Shared Only No Connect Do Not Use NOR Flash 1 Only pSRAM Only ORNAND Flash Only
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Data Sheet (Advance Information)
4.2.1 Lookahead Connection Diagram
Figure 4.1 112-ball x16 MUX NOR FLASH (Bus 1) + x16 MUX pSRAM (Bus 1) + x8/x16 ORNAND (Bus2) 329 1 0 547 681 1312 15 14 17 16 1811 NC NC B D E F G H J K L M N P A C NC NC NCNC NC NC NC NC NCNC DNU DNU N-IO15N-IO7 NC NC DNU R-LB# R-UB#N2-CE#N-RDY F2-CE# N-IO5 N-IO6N-IO13 N-IO14 N1-CE# VCC WE#F-RDY/ R-WAIT N-RE# VSS A21 CLK A17 A19 N-IO4A22 N-IO12F-ACC N-VCC A23 F-RST#VCCQN-VCC A20 A16 AVD# F1-CE#A18 N-IO11VSSQ N-PREF-WP# N-VSS A/DQ12 A/DQ3VSSN-VSS A/DQ6 A/DQ7 A/DQ13 A/DQ8 A/DQ9 VCCOE# VSSA/DQ2 N-CLE A/DQ4 A/DQ11A/DQ15N-ALE VSSQ A/DQ14 A/DQ5 A/DQ1 VCCQ N-IO18A/DQ0 N-IO3A/DQ10 DNU R-CE# R-CREN-WP#N-WE# A24 VSS N-IO9N-IO1 N-IO2 NCNC DNU DNU N-IO8N-IO0 NC NC NCNC NC NC NC NC NC NC NC NC Legend NOR Flash/pSRAM Shared Only No Connect Do Not Use NOR Flash 1 Only pSRAM Only ORNAND Flash Only NOR Flash 2 Only NOR Flash Shared Only
S75NS-N_00_01E May 3, 2006 S75NS-N 7 Data Sheet (Advance Information)
4.3 Physical Dimensions
Figure 4.2 MMB112—11 x 13 mm, 112-ball VFBGA 3558 \\ 16-038.29 \\ 4.27.6 PACKAGE MMB 112 JEDEC N/A D x E 13.00 mm x 11.00 mm PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.40 PROFILE A1 0.20 --- --- BALL HEIGHT A2 0.94 --- 1.11 BODY THICKNESS D 13.00 BSC BODY SIZE E 11.00 BSC BODY SIZE D1 8.50 BSC MATRIX FOOTPRINT E1 6.50 BSC MATRIX FOOTPRINT MD 18 MATRIX SIZE D DIRECTION ME 14 MATRIX SIZE E DIRECTION n 112 BALL COUNT b 0.25 0.30 0.35 BALL DIAMETER eE 0.50 BSC BALL PITCH eD 0.50 BSC BALL PITCH SD / SE 0.25 BSC SOLDER BALL PLACEMENT 1C~1M,2A,2B,2E~2K,3A,3B,3N,3P,4A,4B,4N, DEPOPULATED SOLDER BALLS 4P,5A,5B, 5C,5M,5N,5P,6A~6D,6L~6P,7A~7E, 8A~8E,8K~8P,9A~9D,9L~9P,10A~10D, NOTES: 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO
DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. Ø 10L~10P,11A~11E,11K~11P,12A~12E, 12K~12P,13A~13D,13L~13P,14A~14C, 14M~14P,15A,15B,15N,15P,16A,16B, 16N,16P,17A,17B,17N,17P,18C~18M A B C D E F G H J K L M N P 18 17 16 15
0.08 M C
b
0.15 M C A B
0.08 7SE eE eD CORNER PIN A1 345678910111213 SD BOTTOM VIEW C AD E 0.15 (2X) C B C0.15 (2X) TOP VIEW PIN A1 CORNER A2A INDEX MARK 0.20 ABCDEFGHJKLMNPRTUVW
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Data Sheet (Advance Information) 5. Revision History
5.1 Revision A (May 3, 2006)
Initial release. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2006 Spansion LLC. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, and combinations thereof are trademarks of Spansion LLC. Other names are for informational purposes only and may be trademarks of their respective owners.