Memory

S71PL032JA0

SPANSION

STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM

Manufacturer: SPANSION

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S71PL254 SPANSION | Alldatasheet

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Publication Number S71PL254/127/064/032J_00 Revision A Amendment 6 Issue Date November 22, 2004 ADVANCE S71PL254/127/064/032J based MCPs Stacked Multi-Chip Product (MCP) Flash Memory and RAM 256M/128/64/32 Megabit (16/8/4/2M x 16-bit) CMOS 3.0 Volt-only Simultaneous Operation Page Mode Flash Memory and 64/32/16/8/4 Megabit (4M/2M/1M/512K/256K x 16-bit) Static RAM/Pseudo Static RAM Datasheet Distinctive Characteristics MCP Features Power supply voltage of 2.7 to 3.1 volt High performance —5 5 n s — 65 ns (65 ns Flash, 70ns pSRAM) Packages — 7 x 9 x 1.2mm 56 ball FBGA — 8 x 11.6 x 1.2mm 64 ball FBGA — 8 x 11.6 x 1.4mm 84 ball FBGA Operating Temperature — –25°C to +85°C — –40°C to +85°C General Description The S71PL series is a product line of stacked Multi-Chip Product (MCP) packages and consists of: One or more S29PL (Simultaneous Read/Write) Flash memory die pSRAM or SRAM The 256Mb Flash memory consists of two S29PL127J devices. In this case, CE#f2 is used to access the second Flash and no extra address lines are required. The products covered by this document are listed in the table below: Note: Not recommended for new designs; use pSRAM based MCPs instead. Flash Memory Density 32Mb 64Mb 128Mb 256Mb pSRAM Density 4Mb S71PL032J40 8Mb S71PL032J80 S71PL064J80 16Mb S71PL032JA0 S71PL064JA0 S71PL127JA0 32Mb S71PL064JB0 S71PL127JB0 S71PL254JB0 64Mb S71PL127JC0 S71PL254JC0 Flash Memory Density 32Mb 64Mb SRAM Density (Note) 4Mb S71PL032J04 8Mb S71PL032J08 S71PL064J08

2 S71PL254/127/064/032J based MCPs S71PL254/127/064/032J_00_A6 November 22, 2004

Device-Model# Flash Access time (ns) (p)SRAM density (p)SRAM Access time (ns) pSRAM type Package S71PL032J04-0B 65 4M SRAM 70 SRAM2 TSC056 S71PL032J04-0F 65 4M SRAM 70 SRAM3 TSC056 S71PL032J04-0K 65 4M SRAM 70 SRAM4 TSC056 S71PL032J40-0K 65 4M pSRAM 70 pSRAM4 TLC056 S71PL032J40-07 65 4M pSRAM 70 pSRAM1 TSC056 S71PL032J08-0B 65 8M SRAM 70 SRAM2 TSC056 S71PL032J80-0P 65 8M pSRAM 70 pSRAM5 TSC056 S71PL032J80-07 65 8M pSRAM 70 pSRAM1 TSC056 S71PL032JA0-0K 65 16Mb pSRAM 70 pSRAM1 TSC056 S71PL032JA0-0F 65 16Mb pSRAM 70 pSRAM3 TSC056 S71PL032JA0-0Z 65 32M pSRAM 70 pSRAM7 TLC056 Device-Model# Flash Access time (ns) (p)SRAM density (p)SRAM Access time (ns) (p)SRAM type Package S71PL064J08-0B 65 8M SRAM 70 SRAM2 TLC056 S71PL064J08-0U 65 8M SRAM 70 SRAM4 TLC056 S71PL064J80-0K 65 8M pSRAM 70 pSRAM1 TSC056 S71PL064J80-07 65 8M pSRAM 70 pSRAM1 TLC056 S71PL064J80-0P 65 8M pSRAM 70 pSRAM5 TSC056 S71PL064JA0-0Z 65 16M pSRAM 70 pSRAM7 TLC056 S71PL064JA0-0B 65 16M pSRAM 70 SRAM3 TLC056 S71PL064JA0-07 65 16M pSRAM 70 pSRAM1 TLC056 S71PL064JA0-0P 65 16M pSRAM 70 pSRAM7 TLC056 S71PL064JB0-07 65 32M pSRAM 70 pSRAM1 TLC056 S71PL064JB0-0B 65 32M pSRAM 70 pSRAM2 TLC056 S71PL064JB0-0U 65 32M pSRAM 70 pSRAM6 TLC056

November 22, 2004 S71PL254/127/064/032J_00_A6 S71PL254/127/064/032J based MCPs 3 Preliminary 128Mb Flash Memory 256Mb Flash Memory (2xS29PL127J) Device-Model# Flash Access time (ns) pSRAM density pSRAM Access time (ns) pSRAM type Package S71PL127JA0-9P 65 16M pSRAM 70 pSRAM7 TLA064 S71PL127JA0-9Z 65 16M pSRAM 70 pSRAM7 TLA064 S71PL127JA0-97 65 16M pSRAM 70 pSRAM1 TLA064 S71PL127JB0-97 65 32M pSRAM 70 pSRAM1 TLA064 S71PL127JB0-9Z 65 32M pSRAM 70 pSRAM7 TLA064 S71PL127JB0-9U 65 32M pSRAM 70 pSRAM6 TLA064 S71PL127JB0-9B 65 32M pSRAM 70 pSRAM2 TLA064 S71PL127JC0-97 65 64M pSRAM 70 pSRAM1 TLA064 S71PL127JC0-9Z 65 64M pSRAM 70 pSRAM7 TLA064 S71PL127JC0-9U 65 64M pSRAM 70 pSRAM6 TLA064 Device-Model# Flash Access time (ns) pSRAM density pSRAM Access time (ns) pSRAM type Package S71PL254JB0-T7 65 32M pSRAM 70 pSRAM1 FTA084 S71PL254JB0-TB 65 32M pSRAM 70 pSRAM2 FTA084 S71PL254JB0-TU 65 32M pSRAM 70 pSRAM6 FTA084 S71PL254JC0-TB 65 64M pSRAM 70 pSRAM2 FTA084 S71PL254JC0-TZ 65 64M pSRAM 70 pSRAM7 FTA084

4 S71PL254/127/064/032J_00_A6 November 22, 2004

Table 9. PL127J Boot Sector/Sector Block Addresses for Protection/ Table 10. PL064J Boot Sector/Sector Block Addresses for Table 11. PL032J Boot Sector/Sector Block Addresses for Figure 1. In-System Sector Protection/Sector Unprotection

6 S71PL254/127/064/032J_00_A6 November 22, 2004

Table 35. DC Electrical Characteristics Figure 49. Write Cycle 4 (BHE#/BLE# Controlled, OE# Low).. 123 Figure 63. Read Timing #4 (Page Address Access after CE1# Figure 64. Read Timing #5 (Random and Page Address Access for Figure 67. Write Timing #3-1(WE#/LB#/UB# Byte Figure 68. Write Timing #3-3 (WE#/LB#/UB# Byte Figure 69. Write Timing #3-4 (WE#/LB#/UB# Byte Figure 71. Read / Write Timing #1-2 Figure 73. Read / Write Timing #3 Figure 78. Power Down Program Timing (for 32M/64M Only). 151 Figure 80. Timing Waveform of Read Cycle(1) (Address Controlled, Figure 81. Timing Waveform of Read Cycle(2) (WE#=VIH, if BYTE#

8 S71PL254/127/064/032J_00_A6 November 22, 2004

Notes: 1. For 1 Flash + pSRAM, CE#f1=CE#. For 2 Flash + pSRAM, CE#=CE#f1 and CE#f2 is the chip-enable for the second Flash. 2. For 256Mb only, Flash 1 = Flash 2 = S29PL127J. VSS RESET# Flash 1 IO15-IO0 VCCf DQ15 to DQ0 RY/BY# WP#/ACC VCCVCC CE#f1 Flash-only Address Shared Address OE# WE# Flash 2 (Note 2)CE#f2 (Note 1) VCCS VCC CE#s UB#s LB#s CE# UB# LB# pSRAM/SRAM CE2

November 22, 2004 S71PL254/127/064/032J_00_A6 9 Advance Information Connection Diagram (S71PL032J) Notes: 1. May be shared depending on density. — A19 is shared for the 16M pSRAM configuration. — A18 is shared for the 8M (p)SRAM and above configurations. 2. Connecting all Vcc and Vss balls to Vcc and Vss is recommended. MCP Flash-only Addresses Shared Addresses S71PL032JA0 A20 A19-A0 S71PL032J80 A20-A19 A18-A0 S71PL032J08 A20-A19 A18-A0 S71PL032J40 A20-A18 A17-A0 S71PL032J04 A20-A18 A17-A0 UB# A18 A17 DQ1 DQ9 DQ10 DQ2 LB# CE2s A20 DQ4 VCCs RFU WE# A19 A10 DQ6 DQ13 DQ12 DQ5 RST#f RY/BY# DQ3 VCCf DQ11 WP/ACC A12 A13 A14 RFU DQ15 DQ7 DQ14 A11 A15 RFU RFU A16 RFU VSS VSS OE# DQ0CE1#s DQ8 CE1#f F5F4 B1 B8 A3 A5 A6A4 A7A2 RAM only Shared (Note 1) Flash only Legend Reserved for Future Use 56-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)

10 S71PL254/127/064/032J_00_A6 November 22, 2004

Connection Diagram (S71PL064J) Notes: 1. May be shared depending on density. — A20 is shared for the 32M pSRAM configuration. — A19 is shared for the 16M pSRAM and above configurations. — A18 is shared for the 8M (p)SRAM and above configurations. 2. Connecting all Vcc and Vss balls to Vcc and Vss is recommended. MCP Flash-only Addresses Shared Addresses S71PL064JB0 A21 A20-A0 S71PL064JA0 A21-A20 A19-A0 S71PL064J80 A21-A19 A18-A0 S71PL064J08 A21-A19 A18-A0 UB# A18 A17 DQ1 DQ9 DQ10 DQ2 LB# CE2s A20 DQ4 VCCs RFU WE# A19 A10 DQ6 DQ13 DQ12 DQ5 RST#f RY/BY# DQ3 VCCf DQ11 WP/ACC A12 A13 A14 RFU DQ15 DQ7 DQ14 A11 A15 A21 RFU A16 RFU VSS VSS OE# DQ0CE1#s DQ8 CE1#f F5F4 B1 B8 A3 A5 A6A4 A7A2 RAM only Shared (Note 1) Flash only Legend Reserved for Future Use 56-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)

November 22, 2004 S71PL254/127/064/032J_00_A6 11 Advance Information Connection Diagram (S71PL127J) Notes: 1. May be shared depending on density. — A21 is shared for the 64M pSRAM configuration. — A20 is shared for the 32M pSRAM and above configurations. 1. A19 is shared for the 16M pSRAM and above configurations. 2. Connecting all Vcc & Vss balls to Vcc & Vss is recommended. 3. Ball L5 will be Vccf in the 84-ball density upgrades. Do not connect to Vss or any other signal. MCP Flash-only Addresses Shared Addresses S71PL127JC0 A22 A21-A0 S71PL127JB0 A22-A21 A20-A0 S71PL127JA0 A22-A20 A19-A0 UB# A18 A17 DQ1 DQ9 DQ10 DQ2 CE2s A20 DQ4 VCCs RFU RFU A19 A10 DQ6 DQ13 DQ12 DQ5 RST#f RY/BY# DQ3 VCCf DQ11 RFU A12 A13 A14 RFU DQ15 DQ7 DQ14 A21 A22 A16 RFU VSS VSS OE# DQ0CE1#s DQ8 CE#f H6H5 B6B5 RAM only Shared (Note 1) Flash only Legend Reserved for Future Use RFURFU* L6L5 LB# WE# WP/ACC A11 A15 NC A10 NC M1 M10 NC NC *See notes below 64-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)

12 S71PL254/127/064/032J_00_A6 November 22, 2004

Connection Diagram (S71PL254J) Notes: 1. May be shared depending on density. — A21 is shared for the 64M pSRAM configuration. — A20 is shared for the 32M pSRAM configuration. 2. Connecting all Vcc & Vss balls to Vcc & Vss is recommended. Special Handling Instructions For FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultra- sonic cleaning methods. The package and/or data integrity may be compromised MCP Flash-only Addresses Shared Addresses S71PL254JC0 A22 A21-A0 S71PL254JB0 A22-A21 A20-A0 UB# A18 A17 DQ1 DQ9 DQ10 CE2s A20 DQ4 VCCs A19 A10 DQ6 DQ13 DQ12 RST#f RY/BY# DQ3 VCCf A12 A13 A14 RFU DQ15 DQ7 A21 A22 A16 RFU VSS VSS OE# DQ0CE1#s CE#f1 H6H5 RAM only Shared (Note 1) Flash only Legend Reserved for Future Use A15 NC A10 NC M1 M10 NC NC LB# WE# A8WP/ACC A11 RFU RFU C6C5 RFU RFU RFUCE#F2 RFU RFU RFU RFU B6B5 RFU RFU RFUVCCf RFU RFU RFU RFU L6L5 DQ2 RFU DQ5DQ11 DQ14 RFU DQ8 RFU K6K5 RFURFU H6H5 RFURFU H6H5 2nd Flash Only 84-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)

November 22, 2004 S71PL254/127/064/032J_00_A6 13 Advance Information if the package body is exposed to temperatures above 150°C for prolonged peri- ods of time. Pin Description A21–A0 = 22 Address Inputs (Common) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE1#f = Chip Enable 1 (Flash) CE#f2 = Chip Enable 2 (Flash) CE1#ps = Chip Enable 1 (pSRAM) CE2ps = Chip Enable 2 (pSRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output (Flash 1) UB# = Upper Byte Control (pSRAM) LB# = Lower Byte Control (pSRAM) RESET# = Hardware Reset Pin, Active Low (Flash 1) WP#/ACC = Hardware Write Protect/Acceleration Pin (Flash) V CCf = Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VCCps = pSRAM Power Supply VSS = Device Ground (Common) NC = Pin Not Connected Internally Logic Symbol DQ15–DQ0 A21–A0 CE1#f OE# WE# RESET# R Y/BY# WP#/ACC UB# CE2#f CE2ps CE1#ps LB#

14 S71PL254/127/064/032J_00_A6 November 22, 2004

Ordering Information

The order number is formed by a valid combinations of the following: S71PL 127 J B0 BA W 9 Z 0 PACKING TYPE 0= T r a y 2 = 7” Tape and Reel 3 = 13” Tape and Reel MODEL NUMBER See the Valid Combinations table. PACKAGE MODIFIER 0 = 7 x 9mm, 1.2mm height, 56 balls (TLC056 or TSC065) 9 = 8 x 11.6mm, 1.2mm height, 64 balls (TLA064 or TSB064) T = 8 x 11.6mm, 1.4mm height, 84 balls (FTA084) TEMPERATURE RANGE W = Wireless (-25 °C to +85°C) I= I n d u s t r i a l ( - 4 0°C to +85°C) PACKAGE TYPE BA = Fine-pitch BGA Lead (Pb)-free compliant package BF = Fine-pitch BGA Lead (Pb)-free package pSRAM DENSITY C0 = 64Mb pSRAM B0 = 32Mb pSRAM A0 = 16Mb pSRAM 80 = 8Mb pSRAM 40 = 4Mb pSRAM 08 = 8Mb SRAM 04 = 4Mb SRAM PROCESS TECHNOLOGY J = 110 nm, Floating Gate Technology FLASH DENSITY 254 = 256Mb 127 = 128Mb 064 = 64Mb 032 = 32Mb PRODUCT FAMILY S71PL Multi-chip Product (MCP) 3.0-volt Simultaneous Read/Write, Page Mode Flash Memory and RAM

November 22, 2004 S71PL254/127/064/032J_00_A6 15 Advance Information S71PL032J Valid Combinations Speed Options (ns) (p)SRAM Type/Access Time (ns) Package Marking Base Ordering Part Number Package & Temperature Package Modifier/ Model Number Packing Type S71PL032J04 BAW 0, 2, 3 (Note 1) SRAM2 / 70 (Note 2) S71PL032J04 0F SRAM3 / 70 S71PL032J04 0K SRAM4 / 70 S71PL032J40 0K pSRAM4 / 70 S71PL032J80 0P pSRAM5 / 70 S71PL032J08 0B SRAM2 / 70 S71PL032J40 07 pSRAM1 / 70 S71PL032J80 07 pSRAM1 / 70 S71PL032JA0 07 pSRAM1 / 70 S71PL032JA0 0F pSRAM3 / 70 S71PL032JA0 0Z pSRAM2 / 70 S71PL032J04 BFW 0, 2, 3 (Note 1) SRAM2 / 70 (Note 2) S71PL032J04 0F SRAM3 / 70 S71PL032J04 0K SRAM4 / 70 S71PL032J40 0K pSRAM4 / 70 S71PL032J80 0P pSRAM5 / 70 S71PL032J08 0B SRAM2 / 70 S71PL032J40 07 pSRAM1 / 70 S71PL032J80 07 pSRAM1 / 70 S71PL032JA0 07 pSRAM1 / 70 S71PL032JA0 0F pSRAM3 / 70 S71PL032JA0 0Z pSRAM2 / 70 S71PL032J04 BAI 0, 2, 3 (Note 1) SRAM2 / 70 (Note 2) S71PL032J04 0F SRAM3 / 70 S71PL032J04 0K SRAM4 / 70 S71PL032J40 0K pSRAM4 / 70 S71PL032J80 0P pSRAM5 / 70 S71PL032J08 0B SRAM2 / 70 S71PL032J40 07 pSRAM1 / 70 S71PL032J80 07 pSRAM1 / 70 S71PL032JA0 07 pSRAM1 / 70 S71PL032JA0 0F pSRAM3 / 70 S71PL032JA0 0Z pSRAM2 / 70 S71PL032J04 BFI 0, 2, 3 (Note 1) SRAM2 / 70 (Note 2) S71PL032J04 0F SRAM3 / 70 S71PL032J04 0K SRAM4 / 70 S71PL032J40 0K pSRAM4 / 70 S71PL032J80 0P pSRAM5 / 70 S71PL032J08 0B SRAM2 / 70 S71PL032J40 07 pSRAM1 / 70 S71PL032J80 07 pSRAM1 / 70 S71PL032JA0 07 pSRAM1 / 70 S71PL032JA0 0F pSRAM3 / 70 S71PL032JA0 0Z pSRAM2 / 70

16 S71PL254/127/064/032J_00_A6 November 22, 2004

S71PL064J Valid Combinations Speed Options (ns) (p)SRAM Type/Access Time (ns) Package Marking Base Ordering Part Number Package & Temperature Package Modifier/ Model Number Packing Type S71PL064J08 BAW 0, 2, 3 (Note 1) 65 SRAM1 / 70 (Note 2) S71PL064J08 0U SRAM3 / 70 S71PL064J80 0K pSRAM1 /70 S71PL064J80 07 pSRAM1 / 70 S71PL064J80 0P pSRAM5 / 70 S71PL064JA0 0Z pSRAM7 / 70 S71PL064JA0 0B pSRAM3 / 70 S71PL064JA0 07 pSRAM1 / 70 S71PL064JA0 0P pSRAM7 / 70 S71PL064JB0 07 pSRAM1 / 70 S71PL064JB0 0B pSRAM2 / 70 S71PL064JB0 0U pSRAM6 / 70 S71PL064J08 BFW 0, 2, 3 (Note 1) 65 SRAM1 / 70 (Note 2) S71PL064J08 0U SRAM3 / 70 S71PL064J80 0K pSRAM1 /70 S71PL064J80 07 pSRAM1 / 70 S71PL064J80 0P pSRAM5 / 70 S71PL064JA0 0Z pSRAM7 / 70 S71PL064JA0 0B pSRAM3 / 70 S71PL064JA0 07 pSRAM1 / 70 S71PL064JA0 0P pSRAM7 / 70 S71PL064JB0 07 pSRAM1 / 70 S71PL064JB0 0B pSRAM2 / 70 S71PL064JB0 0U pSRAM6 / 70 S71PL064J08 BAI 0, 2, 3 (Note 1) 65 SRAM1 / 70 (Note 2) S71PL064J08 0U SRAM3 / 70 S71PL064J80 0K pSRAM1 /70 S71PL064J80 07 pSRAM1 / 70 S71PL064J80 0P pSRAM5 / 70 S71PL064JA0 0Z pSRAM7 / 70 S71PL064JA0 0B pSRAM3 / 70 S71PL064JA0 07 pSRAM1 / 70 S71PL064JA0 0P pSRAM7 / 70 S71PL064JB0 07 pSRAM1 / 70 S71PL064JB0 0B pSRAM2 / 70 S71PL064JB0 0U pSRAM6 / 70 Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” and packing type designator from ordering part number. Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations. Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” and packing type designator from ordering part number. Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations. Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” and packing type designator from ordering part number. Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations.

November 22, 2004 S71PL254/127/064/032J_00_A6 17 Advance Information S71PL064J08 BFI 0, 2, 3 (Note 1) 65 SRAM1 / 70 (Note 2) S71PL064J08 0U SRAM3 / 70 S71PL064J80 0K pSRAM1 /70 S71PL064J80 07 pSRAM1 / 70 S71PL064J80 0P pSRAM5 / 70 S71PL064JA0 0Z pSRAM7 / 70 S71PL064JA0 0B pSRAM3 / 70 S71PL064JA0 07 pSRAM1 / 70 S71PL064JA0 0P pSRAM7 / 70 S71PL064JB0 07 pSRAM1 / 70 S71PL064JB0 0B pSRAM2 / 70 S71PL064JB0 0U pSRAM6 / 70 S71PL127J Valid Combinations Speed Options (ns) (p)SRAM Type/Access Time (ns) Package Marking Base Ordering Part Number Package & Temperature Package Modifier/Model Number Packing Type S71PL127JA0 BAW 0, 2, 3 (Note 1) 65 pSRAM7 / 70 (Note 2) S71PL127JA0 9Z pSRAM7 / 70 S71PL127JA0 97 pSRAM1 / 70 S71PL127JB0 97 pSRAM1 / 70 S71PL127JB0 9Z pSRAM7 / 70 S71PL127JB0 9U pSRAM6 /70 S71PL127JC0 97 pSRAM1 /70 S71PL127JC0 9Z pSRAM7 / 70 S71PL127JC0 9U pSRAM6 / 70 S71PL127JB0 9B pSRAM2 / 70 S71PL127JA0 BFW 0, 2, 3 (Note 1) 65 pSRAM7 / 70 (Note 2) S71PL127JA0 9Z pSRAM7 / 70 S71PL127JA0 97 pSRAM1 / 70 S71PL127JB0 97 pSRAM1 / 70 S71PL127JB0 9Z pSRAM7 / 70 S71PL127JB0 9U pSRAM6 / 70 S71PL127JC0 97 pSRAM1 /70 S71PL127JC0 9Z pSRAM7 / 70 S71PL127JC0 9U pSRAM6 / 70 S71PL127JB0 9B pSRAM2 / 70 S71PL064J Valid Combinations Speed Options (ns) (p)SRAM Type/Access Time (ns) Package Marking Base Ordering Part Number Package & Temperature Package Modifier/ Model Number Packing Type Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” and packing type designator from ordering part number. Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations.

18 S71PL254/127/064/032J_00_A6 November 22, 2004

0, 2, 3 (Note 1) 65 pSRAM7 / 70 (Note 2) S71PL127JA0 9Z pSRAM7 / 70 S71PL127JA0 97 pSRAM1 / 70 S71PL127JB0 97 pSRAM1 / 70 S71PL127JB0 9Z pSRAM7 / 70 S71PL127JB0 9U pSRAM6 / 70 S71PL127JC0 97 pSRAM1 /70 S71PL127JC0 9Z pSRAM7 / 70 S71PL127JC0 9U pSRAM6 / 70 S71PL127JB0 9B pSRAM2 / 70 S71PL127JA0 BFI 0, 2, 3 (Note 1) 65 pSRAM7 / 70 (Note 2) S71PL127JA0 9Z pSRAM7 / 70 S71PL127JA0 97 pSRAM1 / 70 S71PL127JB0 97 pSRAM1 / 70 S71PL127JB0 9Z pSRAM7 / 70 S71PL127JB0 9U pSRAM6 / 70 S71PL127JB0 9B pSRAM2 / 70 S71PL127JC0 97 pSRAM1 /70 S71PL127JC0 9Z pSRAM7 / 70 S71PL127JC0 9U pSRAM6 / 70 S71PL127J Valid Combinations Speed Options (ns) (p)SRAM Type/Access Time (ns) Package Marking Base Ordering Part Number Package & Temperature Package Modifier/Model Number Packing Type Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” and packing type designator from ordering part number. Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations.

November 22, 2004 S71PL254/127/064/032J_00_A6 19 Advance Information S71PL254J Valid Combinations Speed Options (ns) (p)SRAM Type/Access Time (ns) Package Marking Base Ordering Part Number Package & Temperature Model Number Packing Type S71PL254JB0 BAW 0, 2, 3 (Note 1) 65 pSRAM1 / 70 (Note 2) S71PL254JB0 TB pSRAM2 /70 S71PL254JB0 TU pSRAM6 / 70 S71PL254JC0 TB pSRAM2 / 70 S71PL254JC0 TZ pSRAM7 / 70 S71PL254JB0 BFW 0, 2, 3 (Note 1) 65 pSRAM1 / 70 (Note 2) S71PL254JB0 TB pSRAM2 /70 S71PL254JB0 TU pSRAM6 / 70 S71PL254JC0 TB pSRAM2 / 70 S71PL254JC0 TZ pSRAM7 / 70 S71PL254JB0 BAI 0, 2, 3 (Note 1) 65 pSRAM1 / 70 (Note 2) S71PL254JB0 TB pSRAM2 /70 S71PL254JB0 TU pSRAM6 / 70 S71PL254JC0 TB pSRAM2 / 70 S71PL254JC0 TZ pSRAM7 / 70 S71PL254JB0 BFI 0, 2, 3 (Note 1) 65 pSRAM1 / 70 (Note 2) S71PL254JB0 TB pSRAM2 /70 S71PL254JB0 TU pSRAM6 / 70 S71PL254JC0 TB pSRAM2 / 70 S71PL254JC0 TZ pSRAM7 / 70 Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” and packing type designator from ordering part number. Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations.

20 S71PL254/127/064/032J_00_A6 November 22, 2004

TLC056—56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7mm Package 3348 \\ 16-038.22a PACKAGE TLC 056 JEDEC N/A D x E 9.00 mm x 7.00 mm PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.20 PROFILE A1 0.20 --- --- BALL HEIGHT A2 0.81 --- 0.97 BODY THICKNESS D 9.00 BSC. BODY SIZE E 7.00 BSC. BODY SIZE D1 5.60 BSC. MATRIX FOOTPRINT E1 5.60 BSC. MATRIX FOOTPRINT MD 8 MATRIX SIZE D DIRECTION ME 8 MATRIX SIZE E DIRECTION n 56 BALL COUNT φb 0.35 0.40 0.45 BALL DIAMETER eE 0.80 BSC. BALL PITCH eD 0.80 BSC BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT A1,A8,D4,D5,E4,E5,H1,H8 DEPOPULATED SOLDER BALLS NOTES: 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 7SE A eD DCEFGH eE B PIN A1 CORNER7 SD BOTTOM VIEW C0.08 0.20 C A E B C0.15 (2X) C D C0.15 (2X) INDEX MARK b TOP VIEW SIDE VIEW CORNER 56X A2A 0.15 M M C C AB 0.08 PIN A1

November 22, 2004 S71PL254/127/064/032J_00_A6 21 Advance Information TSC056—56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7mm Package 3427 \\ 16-038.22 PACKAGE TSC 056 JEDEC N/A D x E 9.00 mm x 7.00 mm PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.20 PROFILE A1 0.17 --- --- BALL HEIGHT A2 0.81 --- 0.97 BODY THICKNESS D 9.00 BSC. BODY SIZE E 7.00 BSC. BODY SIZE D1 5.60 BSC. MATRIX FOOTPRINT E1 5.60 BSC. MATRIX FOOTPRINT MD 8 MATRIX SIZE D DIRECTION ME 8 MATRIX SIZE E DIRECTION n 56 BALL COUNT φb 0.35 0.40 0.45 BALL DIAMETER eE 0.80 BSC. BALL PITCH eD 0.80 BSC BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT A1,A8,D4,D5,E4,E5,H1,H8 DEPOPULATED SOLDER BALLS NOTES: 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIAMETER IN A PLANE PARALLEL TO DATUM C. AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 7SE A eD DCEFGH eE B PIN A1 CORNER7 SD BOTTOM VIEW C0.08 0.20 C A E B C0.15 (2X) C D C0.15 (2X) INDEX MARK b TOP VIEW SIDE VIEW CORNER 56X A2A 0.15 M M C C AB 0.08 PIN A1

22 S71PL254/127/064/032J_00_A6 November 22, 2004

TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6mm Package 3352 \\ 16-038.22a PACKAGE TLA 064 JEDEC N/A D x E 11.60 mm x 8.00 mm PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.20 PROFILE A1 0.17 --- --- BALL HEIGHT A2 0.81 --- 0.97 BODY THICKNESS D 11.60 BSC. BODY SIZE E 8.00 BSC. BODY SIZE D1 8.80 BSC. MATRIX FOOTPRINT E1 7.20 BSC. MATRIX FOOTPRINT MD 12 MATRIX SIZE D DIRECTION ME 10 MATRIX SIZE E DIRECTION n 64 BALL COUNT φb 0.35 0.40 0.45 BALL DIAMETER eE 0.80 BSC. BALL PITCH eD 0.80 BSC BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B2,B3,B4,B7,B8,B9,B10 C1,C2,C9,C10,D1,D10,E1,E10, F1,F5,F6,F10,G1,G5,G6,G10 H1,H10,J1,J10,K1,K2,K9,K10 L1,L2,L3,L4,L7,L8,L9,L10 M2,M3,M4,M5,M6,M7,M8,M9 NOTES: 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIAMETER IN A PLANE PARALLEL TO DATUM C. AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. C0.20 C0.08C b64X

0.08 M C

0.15 M C A B

C0.15 (2X) (2X) C0.15 B AD E PIN A1 TOP VIEW CORNER

November 22, 2004 S71PL254/127/064/032J_00_A6 23 Advance Information TSB064—64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package 3351 \\ 16-038.22a PACKAGE TSB 064 JEDEC N/A D x E 11.60 mm x 8.00 mm PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.20 PROFILE A1 017 --- --- BALL HEIGHT A2 0.81 --- 0.97 BODY THICKNESS D 11.60 BSC. BODY SIZE E 8.00 BSC. BODY SIZE D1 8.80 BSC. MATRIX FOOTPRINT E1 7.20 BSC. MATRIX FOOTPRINT MD 12 MATRIX SIZE D DIRECTION ME 10 MATRIX SIZE E DIRECTION n 64 BALL COUNT φb 0.35 0.40 0.45 BALL DIAMETER eE 0.80 BSC. BALL PITCH eD 0.80 BSC BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B2,B3,B4,B7,B8,B9,B10 C1,C2,C9,C10,D1,D10,E1,E10 F1,F5,F6,F10,G1,G5,G6,G10 H1,H10,J1,J10,K1,K2,K9,K10 L1,L2,L3,L4,L7,L8,L9,L10 M2,M3,M4,M5,M6,M7,M8,M9 NOTES: 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIAMETER IN A PLANE PARALLEL TO DATUM C. AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. CC 0.08A1 b64X

6 SIDE VIEW

E D 0.15 C (2X) GFEK JH SD M L C C0.15 B (2X) 0.20 PIN A1 CORNER INDEX MARK A2A TOP VIEW BOTTOM VIEW

24 S71PL254/127/064/032J_00_A6 November 22, 2004

FTA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6mm 3388 \\ 16-038.21a PACKAGE FTA 084 JEDEC N/A D x E 11.60 mm x 8.00 mm NOTE PACKAGE SYMBOL MIN NOM MAX A --- --- 1.40 PROFILE A1 0.17 --- --- BALL HEIGHT A2 1.02 --- 1.17 BODY THICKNESS D 11.60 BSC. BODY SIZE E 8.00 BSC. BODY SIZE D1 8.80 BSC. MATRIX FOOTPRINT E1 7.20 BSC. MATRIX FOOTPRINT MD 12 MATRIX SIZE D DIRECTION ME 10 MATRIX SIZE E DIRECTION n 84 BALL COUNT φb 0.35 0.40 0.45 BALL DIAMETER eE 0.80 BSC. BALL PITCH eD 0.80 BSC BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B10,C1,C10,D1,D10,E1,E10 F1,F10,G1,G10,H1,H10 J1,J10,K1,K10,L1,L10 M2,M3,M4,M5,M6,M7,M8,M9 NOTES: 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIAMETER IN A PLANE PARALLEL TO DATUM C. AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. (2X) C0.08 0.20 C C b SIDE VIEW 84X A2A

0.15 M C

0.08 BOTTOM VIEW ML 7SE A eD DCEFGHJK eE B PIN A1 CORNER7 SD A E B C0.15 D C0.15 (2X) INDEX MARK TOP VIEW CORNER PIN A1

Publication Number S29PL127J_064J_032J_MCP Revision A Amendment 3 Issue Date August 12, 2004 ADVANCE INFORMATION S29PL127J/S29PL064J/S29PL032J for MCP 128/64/32 Megabit (8/4/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO TM Control Distinctive Characteristics Architectural Advantages 128/64/32 Mbit Page Mode devices — Page size of 8 words: Fast page read access from random locations within the page Single power supply operation — Full Voltage range: 2.7 to 3.1 volt read, erase, and program operations for battery-powered applications Simultaneous Read/Write Operation — Data can be continuously read from one bank while executing erase/program functions in another bank — Zero latency switching from write to read operations FlexBank Architecture (PL127J/PL064J/PL032J) — 4 separate banks, with up to two simultaneous operations per device —B a n k A : PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31) PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15) PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7) —B a n k B : PL127J - 48 Mbit (32 Kw x 96) PL064J - 24 Mbit (32 Kw x 48) PL032J - 12 Mbit (32 Kw x 24) —B a n k C : PL127J - 48 Mbit (32 Kw x 96) PL064J - 24 Mbit (32 Kw x 48) PL032J - 12 Mbit (32 Kw x 24) —B a n k D : PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31) PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15) PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7) Enhanced VersatileI/O TM (VIO) Control — Output voltage generated and input voltages tolerated on all control inputs and I/Os is determined by the voltage on the VIO pin —V IO options at 1.8 V and 3 V I/O for PL127J devices —3 V V IO for PL064J and PL032J devices Secured Silicon Sector region — Up to 128 words accessible through a command sequence — Up to 64 factory-locked words — Up to 64 customer-lockable words Both top and bottom boot blocks in one device Manufactured on 110 nm process technology Data Retention: 20 years typical Cycling Endurance: 1 million cycles per sector typical Performance CharacteristicS High Performance — Page access times as fast as 20 ns — Random access times as fast as 55 ns Power consumption (typical values at 10 MHz) — 45 mA active read current — 17 mA program/erase current — 0.2 µA typical standby mode current Software Features Software command-set compatible with JEDEC 42.4 standard — Backward compatible with Am29F, Am29LV, Am29DL, and AM29PDL families and MBM29QM/RM, MBM29LV, MBM29DL, MBM29PDL families CFI (Common Flash Interface) compliant — Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices Erase Suspend / Erase Resume — Suspends an erase operation to allow read or program operations in other sectors of same bank Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences

26 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data WP#/ ACC (Write Protect/Acceleration) input —A t V IL, hardware level protection for the first and last two 4K word sectors. —A t V IH, allows removal of sector protection —A t V HH, provides accelerated programming in a factory setting Persistent Sector Protection — A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector — Sectors can be locked and unlocked in-system at V CC level Password Sector Protection — A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password Package options — Standard discrete pinouts 11 x 8 mm, 80-ball Fine-pitch BGA (PL127J) (VBG080) 8 x 6 mm, 48-ball Fine pitch BGA (PL064J/PL032J) (VBK048) — MCP-compatible pinout 8 x 11.6 mm, 64-ball Fine-pitch BGA (PL127J) 7 x 9 mm, 56-ball Fine-pitch BGA (PL064J and PL032J) Compatible with MCP pinout, allowing easy integration of RAM into existing designs

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 27 Advance Information General Description The PL127J/PL064J/PL032J is a 128/128/64/32 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8/8/4/2 Mwords. The devices are offered in the following packages: 11mm x 8mm, 64-ball Fine-pitch BGA standalone (all) 9mm x 8mm, 80-ball Fine-pitch BGA standalone (PL127J) 8mm x 11.6mm, 64-ball Fine pitch BGA multi-chip compatible (PL127J) The word-wide data (x16) appears on DQ15-DQ0. This device can be pro - grammed in-system or in standard EPROM programmers. A 12.0 V V PP is not required for write or erase operations. The device offers fast page access times of 20 to 30 ns, with corresponding ran- dom access times of 55 to 70 ns, respectively, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Simultaneous Read/Write Operation with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediatel y and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improving system performance. The device can be organized in both top and bottom sector configurations. The banks are organized as follows: Page Mode Features The page size is 8 words. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page. Standard Flash Memory Features The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both read and write functions. Internally ge nerated and regulated voltages are pro - vided for the program and erase operations. The device is entirely command set compatible with the JEDEC 42.4 single- power-supply Flash standard. Commands are written to the command regis- ter using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming Bank PL127J Sectors PL064J Sectors PL032J Sectors A 16 Mbit (4 Kw x 8 and 32 Kw x 31) 8 Mbit (4 Kw x 8 and 32 Kw x 15) 4 Mbit (4 Kw x 8 and 32 Kw x 7) B 48 Mbit (32 Kw x 96) 24 Mbit (32 Kw x 48) 12 Mbit (32 Kw x 24) C 48 Mbit (32 Kw x 96) 24 Mbit (32 Kw x 48) 12 Mbit (32 Kw x 24) D 16 Mbit (4 Kw x 8 and 32 Kw x 31) 8 Mbit (4 Kw x 8 and 32 Kw x 15) 4 Mbit (4 Kw x 8 and 32 Kw x 7)

28 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or ac cept another command. The sector erase architecture allows memory sectors to be erased and repro - grammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automat- ically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combina - tion of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the Secured Silicon Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. The device electrically erases all bits within a sector simultaneously via Fowler- Nordheim tunneling. The data is programmed using hot electron injection.

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 29 Advance Information Product Selector Guide Note: Contact factory for availability. Part Number S29PL032J/S29PL064J/S29PL127J Speed Option VCC,VIO = 2.7–3.6 V 55 (Note) 60 70 VCC = 2.7–3.6 V, VIO = 1.65–1.95 V (PL127J only) 65 70 Max Access Time, ns (tACC) 55 (Note) 60 65 70 70 Max CE# Access, ns (tCE) Max Page Access, ns (tPACC) 20 (Note) 25 30 30 30 Max OE# Access, ns (tOE)

30 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

Notes: 1. RY/BY# is an open drain output. 2. Amax = A22 (PL127J), A21 (PL064J), A20 (PL032J) VCC VSS State Control Command Register PGM Voltage Generator VCC Detector Timer Erase Voltage Generator Input/Output Buffers Sector Switches Chip Enable Output Enable Logic Y-Gating Cell Matrix Address Latch Y-Decoder X-Decoder Data Latch RESET# RY/BY# (See Note) Amax–A3 A2–A0 CE# WE# DQ15–DQ0 VIO OE#

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 31 Advance Information Simultaneous Read/Write Block Diagram Note: Amax = A22 (PL127J), A21 (PL064J), A20 (PL032J) Note: Pinout shown for PL127J. VCC VSS Bank A Address Bank B Address Amax–A0 RESET# WE# CE# DQ0–DQ15 STATE CONTROL COMMAND REGISTER RY/BY# Bank A X-Decoder OE# DQ15–DQ0 Status Control Amax–A0 Amax–A0 A22–A0A22–A0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 Mux Mux Mux Bank B X-Decoder Y-gate Bank C X-Decoder Bank D X-Decoder Y-gate Bank C Address Bank D Address WP#/ACC

32 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

Amax–A0 = Address bus DQ15–DQ0 = 16-bit data inputs/outputs/float CE# = Chip Enable Inputs OE# = Output Enable Input WE# = Write Enable VSS = Device Ground NC = Pin Not Connected Internally RY/BY# = Ready/Busy output and open drain. When RY/BY#= VIH, the device is ready to accept read operations and commands. When RY/BY#= VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset operation. WP#/ACC = Write Protect/Acceleration Input. When WP#/ACC= VIL, the highest and lowest two 4K-word sectors are write protected regardless of other sector protection configurations. When WP#/ ACC= VIH, these sector are unprotected unless the DYB or PPB is programmed. When WP#/ACC= 12V, program and erase operations are accelerated. VIO = Input/Output Buffer Power Supply (1.65 V to 1.95 V (for PL127J) or 2.7 V to 3.6 V (for all PLxxxJ devices) VCC = Chip Power Supply (2.7 V to 3.6 V or 2.7 to 3.3 V) RESET# = Hardware Reset Pin CE#1 = Chip Enable Inputs Notes: 1. Amax = A22 (PL127J), A21 (PL064J), A20 (PL032J) Logic Symbol max+1 DQ15–DQ0 Amax–A0 CE# OE# WE# RESET# RY/BY# WP#/ACC VIO (VCCQ)

these operations in further detail.

The sector protect and sector unprotect functions may also be implemented via programming equipment. See the

High Voltage Sector Protection section.

WP#/ACC must be high when writing to upper two and lower two sectors.

Refer to Table 23 for timing specifications and to Figure 11 for the timing diagram. Table 1. PL127J Device Bus Operations

0.3 V X X VIO ±

0.3 V X (Note 2) X High-Z

34 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

access time is the delay from the falling edge of the OE# to valid data at the out- put inputs (assuming the addresses have been stable for at least tACC–tOE time). Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. Address bits Amax–A3 select an 8 word page, and address bits A2–A0 select a specific word within that page. This is an asyn chronous operation with the microprocessor supplying the specific word location. The random or initial page access is t ACC or tCE and subsequent page read ac - cesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. Fast page mode accesses are obtained by keeping Amax–A3 constant and changing A2–A0 to select the specific word within that page. Simultaneous Read/Write Operation In addition to the conventional features (read, program, erase-suspend read, and erase-suspend program), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation). The bank can be selected by bank addresses (PL127J: A22–A20, L064J: A21–A19, PL032J: A20–A18) with zero latency. The simultaneous operation can execute multi-function mode in the same bank. Ta bl e 2 . Page Select Word A2 A1 A0 Word 0 0 0 0 Word 1 0 0 1 Word 2 0 1 0 Word 3 0 1 1 Word 4 1 0 0 Word 5 1 0 1 Word 6 1 1 0 Word 7 1 1 1 Ta b l e 3 . Bank Select Bank PL127J: A22–A20 PL064J: A21–A19 PL032J: A20–A18 Bank A 000 Bank B 001, 010, 011 Bank C 100, 101, 110 Bank D 111

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 35 Advance Information Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The “Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 4 indicates the set of address space that each sector occupies. A “bank ad- dress” is the set of address bits required to uniquely select a bank. Similarly, a “sector address” refers to the address bits required to uniquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. ICC2 in the DC Characteristics table represents the active current specification for the write mode. See the timing specification tables and timing diagrams in the Reset for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the afore- mentioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP#/ACC pin re- turns the device to normal operation. Note that V HH must not be asserted on WP#/ACC for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin should be raised to V CC when not in use. That is, the WP#/ACC pin should not be left floating or unconnected; incon- sistent behavior of the device may result. Autoselect Functions If the system writes the autoselect command sequence, the device enters the au- toselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Secured Silicon Sector Ad - dresses and Autoselect Command Sequence for more information. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V IO ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device

36 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws ac- tive current until the operation is completed. ICC3 in “DC Characteristics” represents the CMOS standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The de- vice automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con- trol signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Note that during automatic sleep mode, OE# must be at V IH before the device reduces current to the stated sleep mode specification. ICC5 in “DC Characteristics” represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driv en low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The op eration that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm ware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin re - mains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/ BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristic tables for RESET# parameters and to 13 for the timing diagOutput Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins (except for RY/BY#) are placed in the highest Impedance state.

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 37 Advance Information Ta bl e 4 . PL127J Sector Architecture Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16) Bank A SA0 00000000000 4 000000h–000FFFh SA1 00000000001 4 001000h–001FFFh SA2 00000000010 4 002000h–002FFFh SA3 00000000011 4 003000h–003FFFh SA4 00000000100 4 004000h–004FFFh SA5 00000000101 4 005000h–005FFFh SA6 00000000110 4 006000h–006FFFh SA7 00000000111 4 007000h–007FFFh SA8 00000001XXX 32 008000h–00FFFFh SA9 00000010XXX 32 010000h–017FFFh SA10 00000011XXX 32 018000h–01FFFFh SA11 00000100XXX 32 020000h–027FFFh SA12 00000101XXX 32 028000h–02FFFFh SA13 00000110XXX 32 030000h–037FFFh SA14 00000111XXX 32 038000h–03FFFFh SA15 00001000XXX 32 040000h–047FFFh SA16 00001001XXX 32 048000h–04FFFFh SA17 00001010XXX 32 050000h–057FFFh SA18 00001011XXX 32 058000h–05FFFFh SA19 00001100XXX 32 060000h–067FFFh SA20 00001101XXX 32 068000h–06FFFFh SA21 00001110XXX 32 070000h–077FFFh SA22 00001111XXX 32 078000h–07FFFFh SA23 00010000XXX 32 080000h–087FFFh SA24 00010001XXX 32 088000h–08FFFFh SA25 00010010XXX 32 090000h–097FFFh SA26 00010011XXX 32 098000h–09FFFFh SA27 00010100XXX 32 0A0000h–0A7FFFh SA28 00010101XXX 32 0A8000h–0AFFFFh SA29 00010110XXX 32 0B0000h–0B7FFFh SA30 00010111XXX 32 0B8000h–0BFFFFh SA31 00011000XXX 32 0C0000h–0C7FFFh SA32 00011001XXX 32 0C8000h–0CFFFFh SA33 00011010XXX 32 0D0000h–0D7FFFh SA34 00011011XXX 32 0D8000h–0DFFFFh SA35 00011100XXX 32 0E0000h–0E7FFFh SA36 00011101XXX 32 0E8000h–0EFFFFh SA37 00011110XXX 32 0F0000h–0F7FFFh SA38 00011111XXX 32 0F8000h–0FFFFFh

38 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

SA39 00100000XXX 32 100000h–107FFFh SA40 00100001XXX 32 108000h–10FFFFh SA41 00100010XXX 32 110000h–117FFFh SA42 00100011XXX 32 118000h–11FFFFh SA43 00100100XXX 32 120000h–127FFFh SA44 00100101XXX 32 128000h–12FFFFh SA45 00100110XXX 32 130000h–137FFFh SA46 00100111XXX 32 138000h–13FFFFh SA47 00101000XXX 32 140000h–147FFFh SA48 00101001XXX 32 148000h–14FFFFh SA49 00101010XXX 32 150000h–157FFFh SA50 00101011XXX 32 158000h–15FFFFh SA51 00101100XXX 32 160000h–167FFFh SA52 00101101XXX 32 168000h–16FFFFh SA53 00101110XXX 32 170000h–177FFFh SA54 00101111XXX 32 178000h–17FFFFh SA55 00110000XXX 32 180000h–187FFFh SA56 00110001XXX 32 188000h–18FFFFh SA57 00110010XXX 32 190000h–197FFFh SA58 00110011XXX 32 198000h–19FFFFh SA59 00110100XXX 32 1A0000h–1A7FFFh SA60 00110101XXX 32 1A8000h–1AFFFFh SA61 00110110XXX 32 1B0000h–1B7FFFh SA62 00110111XXX 32 1B8000h–1BFFFFh SA63 00111000XXX 32 1C0000h–1C7FFFh SA64 00111001XXX 32 1C8000h–1CFFFFh SA65 00111010XXX 32 1D0000h–1D7FFFh SA66 00111011XXX 32 1D8000h–1DFFFFh SA67 00111100XXX 32 1E0000h–1E7FFFh SA68 00111101XXX 32 1E8000h–1EFFFFh SA69 00111110XXX 32 1F0000h–1F7FFFh SA70 00111111XXX 32 1F8000h–1FFFFFh SA71 01000000XXX 32 200000h–207FFFh SA72 01000001XXX 32 208000h–20FFFFh SA73 01000010XXX 32 210000h–217FFFh SA74 01000011XXX 32 218000h–21FFFFh SA75 01000100XXX 32 220000h–227FFFh SA76 01000101XXX 32 228000h–22FFFFh SA77 01000110XXX 32 230000h–237FFFh SA78 01000111XXX 32 238000h–23FFFFh T able 4. PL127J Sector Architecture (Continued) Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16)

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 39 Advance Information Bank B SA79 01001000XXX 32 240000h–247FFFh SA80 01001001XXX 32 248000h–24FFFFh SA81 01001010XXX 32 250000h–257FFFh SA82 01001011XXX 32 258000h–25FFFFh SA83 01001100XXX 32 260000h–267FFFh SA84 01001101XXX 32 268000h–26FFFFh SA85 01001110XXX 32 270000h–277FFFh SA86 01001111XXX 32 278000h–27FFFFh SA87 01010000XXX 32 280000h–287FFFh SA88 01010001XXX 32 288000h–28FFFFh SA89 01010010XXX 32 290000h–297FFFh SA90 01010011XXX 32 298000h–29FFFFh SA91 01010100XXX 32 2A0000h–2A7FFFh SA92 01010101XXX 32 2A8000h–2AFFFFh SA93 01010110XXX 32 2B0000h–2B7FFFh SA94 01010111XXX 32 2B8000h–2BFFFFh SA95 01011000XXX 32 2C0000h–2C7FFFh SA96 01011001XXX 32 2C8000h–2CFFFFh SA97 01011010XXX 32 2D0000h–2D7FFFh SA98 01011011XXX 32 2D8000h–2DFFFFh SA99 01011100XXX 32 2E0000h–2E7FFFh SA100 01011101XXX 32 2E8000h–2EFFFFh SA101 01011110XXX 32 2F0000h–2F7FFFh SA102 01011111XXX 32 2F8000h–2FFFFFh SA103 01100000XXX 32 300000h–307FFFh SA104 01100001XXX 32 308000h–30FFFFh SA105 01100010XXX 32 310000h–317FFFh SA106 01100011XXX 32 318000h–31FFFFh SA107 01100100XXX 32 320000h–327FFFh SA108 01100101XXX 32 328000h–32FFFFh SA109 01100110XXX 32 330000h–337FFFh SA110 01100111XXX 32 338000h–33FFFFh SA111 01101000XXX 32 340000h–347FFFh SA112 01101001XXX 32 348000h–34FFFFh SA113 01101010XXX 32 350000h–357FFFh SA114 01101011XXX 32 358000h–35FFFFh SA115 01101100XXX 32 360000h–367FFFh SA116 01101101XXX 32 368000h–36FFFFh SA117 01101110XXX 32 370000h–377FFFh SA118 01101111XXX 32 378000h–37FFFFh T able 4. PL127J Sector Architecture (Continued) Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16)

40 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

SA119 01110000XXX 32 380000h–387FFFh SA120 01110001XXX 32 388000h–38FFFFh SA121 01110010XXX 32 390000h–397FFFh SA122 01110011XXX 32 398000h–39FFFFh SA123 01110100XXX 32 3A0000h–3A7FFFh SA124 01110101XXX 32 3A8000h–3AFFFFh SA125 01110110XXX 32 3B0000h–3B7FFFh SA126 01110111XXX 32 3B8000h–3BFFFFh SA127 01111000XXX 32 3C0000h–3C7FFFh SA128 01111001XXX 32 3C8000h–3CFFFFh SA129 01111010XXX 32 3D0000h–3D7FFFh SA130 01111011XXX 32 3D8000h–3DFFFFh SA131 01111100XXX 32 3E0000h–3E7FFFh SA132 01111101XXX 32 3E8000h–3EFFFFh SA133 01111110XXX 32 3F0000h–3F7FFFh SA134 01111111XXX 32 3F8000h–3FFFFFh Bank C SA135 10000000XXX 32 400000h–407FFFh SA136 10000001XXX 32 408000h–40FFFFh SA137 10000010XXX 32 410000h–417FFFh SA138 10000011XXX 32 418000h–41FFFFh SA139 10000100XXX 32 420000h–427FFFh SA140 10000101XXX 32 428000h–42FFFFh SA141 10000110XXX 32 430000h–437FFFh SA142 10000111XXX 32 438000h–43FFFFh SA143 10001000XXX 32 440000h–447FFFh SA144 10001001XXX 32 448000h–44FFFFh SA145 10001010XXX 32 450000h–457FFFh SA146 10001011XXX 32 458000h–45FFFFh SA147 10001100XXX 32 460000h–467FFFh SA148 10001101XXX 32 468000h–46FFFFh SA149 10001110XXX 32 470000h–477FFFh SA150 10001111XXX 32 478000h–47FFFFh SA151 10010000XXX 32 480000h–487FFFh SA152 10010001XXX 32 488000h–48FFFFh SA153 10010010XXX 32 490000h–497FFFh SA154 10010011XXX 32 498000h–49FFFFh SA155 10010100XXX 32 4A0000h–4A7FFFh SA156 10010101XXX 32 4A8000h–4AFFFFh SA157 10010110XXX 32 4B0000h–4B7FFFh SA158 10010111XXX 32 4B8000h–4BFFFFh T able 4. PL127J Sector Architecture (Continued) Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16)

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 41 Advance Information Bank C SA159 10011000XXX 32 4C0000h–4C7FFFh SA160 10011001XXX 32 4C8000h–4CFFFFh SA161 10011010XXX 32 4D0000h–4D7FFFh SA162 10011011XXX 32 4D8000h–4DFFFFh SA163 10011100XXX 32 4E0000h–4E7FFFh SA164 10011101XXX 32 4E8000h–4EFFFFh SA165 10011110XXX 32 4F0000h–4F7FFFh SA166 10011111XXX 32 4F8000h–4FFFFFh SA167 10100000XXX 32 500000h–507FFFh SA168 10100001XXX 32 508000h–50FFFFh SA169 10100010XXX 32 510000h–517FFFh SA170 10100011XXX 32 518000h–51FFFFh SA171 10100100XXX 32 520000h–527FFFh SA172 10100101XXX 32 528000h–52FFFFh SA173 10100110XXX 32 530000h–537FFFh SA174 10100111XXX 32 538000h–53FFFFh SA175 10101000XXX 32 540000h–547FFFh SA176 10101001XXX 32 548000h–54FFFFh SA177 10101010XXX 32 550000h–557FFFh SA178 10101011XXX 32 558000h–15FFFFh SA179 10101100XXX 32 560000h–567FFFh SA180 10101101XXX 32 568000h–56FFFFh SA181 10101110XXX 32 570000h–577FFFh SA182 10101111XXX 32 578000h–57FFFFh SA183 10110000XXX 32 580000h–587FFFh SA184 10110001XXX 32 588000h–58FFFFh SA185 10110010XXX 32 590000h–597FFFh SA186 10110011XXX 32 598000h–59FFFFh SA187 10110100XXX 32 5A0000h–5A7FFFh SA188 10110101XXX 32 5A8000h–5AFFFFh SA189 10110110XXX 32 5B0000h–5B7FFFh SA190 10110111XXX 32 5B8000h–5BFFFFh SA191 10111000XXX 32 5C0000h–5C7FFFh SA192 10111001XXX 32 5C8000h–5CFFFFh SA193 10111010XXX 32 5D0000h–5D7FFFh SA194 10111011XXX 32 5D8000h–5DFFFFh SA195 10111100XXX 32 5E0000h–5E7FFFh SA196 10111101XXX 32 5E8000h–5EFFFFh SA197 10111110XXX 32 5F0000h–5F7FFFh SA198 10111111XXX 32 5F8000h–5FFFFFh T able 4. PL127J Sector Architecture (Continued) Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16)

42 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

SA199 11000000XXX 32 600000h–607FFFh SA200 11000001XXX 32 608000h–60FFFFh SA201 11000010XXX 32 610000h–617FFFh SA202 11000011XXX 32 618000h–61FFFFh SA203 11000100XXX 32 620000h–627FFFh SA204 11000101XXX 32 628000h–62FFFFh SA205 11000110XXX 32 630000h–637FFFh SA206 11000111XXX 32 638000h–63FFFFh SA207 11001000XXX 32 640000h–647FFFh SA208 11001001XXX 32 648000h–64FFFFh SA209 11001010XXX 32 650000h–657FFFh SA210 11001011XXX 32 658000h–65FFFFh SA211 11001100XXX 32 660000h–667FFFh SA212 11001101XXX 32 668000h–66FFFFh SA213 11001110XXX 32 670000h–677FFFh SA214 11001111XXX 32 678000h–67FFFFh SA215 11010000XXX 32 680000h–687FFFh SA216 11010001XXX 32 688000h–68FFFFh SA217 11010010XXX 32 690000h–697FFFh SA218 11010011XXX 32 698000h–69FFFFh SA219 11010100XXX 32 6A0000h–6A7FFFh SA220 11010101XXX 32 6A8000h–6AFFFFh SA221 11010110XXX 32 6B0000h–6B7FFFh SA222 11010111XXX 32 6B8000h–6BFFFFh SA223 11011000XXX 32 6C0000h–6C7FFFh SA224 11011001XXX 32 6C8000h–6CFFFFh SA225 11011010XXX 32 6D0000h–6D7FFFh SA226 11011011XXX 32 6D8000h–6DFFFFh SA227 11011100XXX 32 6E0000h–6E7FFFh SA228 11011101XXX 32 6E8000h–6EFFFFh SA229 11011110XXX 32 6F0000h–6F7FFFh SA230 11011111XXX 32 6F8000h–6FFFFFh T able 4. PL127J Sector Architecture (Continued) Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16)

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 43 Advance Information Bank D SA231 11100000XXX 32 700000h–707FFFh SA232 11100001XXX 32 708000h–70FFFFh SA233 11100010XXX 32 710000h–717FFFh SA234 11100011XXX 32 718000h–71FFFFh SA235 11100100XXX 32 720000h–727FFFh SA236 11100101XXX 32 728000h–72FFFFh SA237 11100110XXX 32 730000h–737FFFh SA238 11100111XXX 32 738000h–73FFFFh SA239 11101000XXX 32 740000h–747FFFh SA240 11101001XXX 32 748000h–74FFFFh SA241 11101010XXX 32 750000h–757FFFh SA242 11101011XXX 32 758000h–75FFFFh SA243 11101100XXX 32 760000h–767FFFh SA244 11101101XXX 32 768000h–76FFFFh SA245 11101110XXX 32 770000h–777FFFh SA246 11101111XXX 32 778000h–77FFFFh SA247 11110000XXX 32 780000h–787FFFh SA248 11110001XXX 32 788000h–78FFFFh SA249 11110010XXX 32 790000h–797FFFh SA250 11110011XXX 32 798000h–79FFFFh SA251 11110100XXX 32 7A0000h–7A7FFFh SA252 11110101XXX 32 7A8000h–7AFFFFh SA253 11110110XXX 32 7B0000h–7B7FFFh SA254 11110111XXX 32 7B8000h–7BFFFFh SA255 11111000XXX 32 7C0000h–7C7FFFh SA256 11111001XXX 32 7C8000h–7CFFFFh SA257 11111010XXX 32 7D0000h–7D7FFFh SA258 11111011XXX 32 7D8000h–7DFFFFh SA259 11111100XXX 32 7E0000h–7E7FFFh SA260 11111101XXX 32 7E8000h–7EFFFFh SA261 11111110XXX 32 7F0000h–7F7FFFh SA262 11111111000 4 7F8000h–7F8FFFh SA263 11111111001 4 7F9000h–7F9FFFh SA264 11111111010 4 7FA000h–7FAFFFh SA265 11111111011 4 7FB000h–7FBFFFh SA266 11111111100 4 7FC000h–7FCFFFh SA267 11111111101 4 7FD000h–7FDFFFh SA268 11111111110 4 7FE000h–7FEFFFh SA269 11111111111 4 7FF000h–7FFFFFh T able 4. PL127J Sector Architecture (Continued) Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16)

44 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

Ta b l e 5 . PL064J Sector Architecture Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16) Bank A SA0 0000000000 4 000000h–000FFFh SA1 0000000001 4 001000h–001FFFh SA2 0000000010 4 002000h–002FFFh SA3 0000000011 4 003000h–003FFFh SA4 0000000100 4 004000h–004FFFh SA5 0000000101 4 005000h–005FFFh SA6 0000000110 4 006000h–006FFFh SA7 0000000111 4 007000h–007FFFh SA8 0000001XXX 32 008000h–00FFFFh SA9 0000010XXX 32 010000h–017FFFh SA10 0000011XXX 32 018000h–01FFFFh SA11 0000100XXX 32 020000h–027FFFh SA12 0000101XXX 32 028000h–02FFFFh SA13 0000110XXX 32 030000h–037FFFh SA14 0000111XXX 32 038000h–03FFFFh SA15 0001000XXX 32 040000h–047FFFh SA16 0001001XXX 32 048000h–04FFFFh SA17 0001010XXX 32 050000h–057FFFh SA18 0001011XXX 32 058000h–05FFFFh SA19 0001100XXX 32 060000h–067FFFh SA20 0001101XXX 32 068000h–06FFFFh SA21 0001110XXX 32 070000h–077FFFh SA22 0001111XXX 32 078000h–07FFFFh Bank B SA23 0010000XXX 32 080000h–087FFFh SA24 0010001XXX 32 088000h–08FFFFh SA25 0010010XXX 32 090000h–097FFFh SA26 0010011XXX 32 098000h–09FFFFh SA27 0010100XXX 32 0A0000h–0A7FFFh SA28 0010101XXX 32 0A8000h–0AFFFFh SA29 0010110XXX 32 0B0000h–0B7FFFh SA30 0010111XXX 32 0B8000h–0BFFFFh SA31 0011000XXX 32 0C0000h–0C7FFFh SA32 0011001XXX 32 0C8000h–0CFFFFh SA33 0011010XXX 32 0D0000h–0D7FFFh SA34 0011011XXX 32 0D8000h–0DFFFFh SA35 0011100XXX 32 0E0000h–0E7FFFh SA36 0011101XXX 32 0E8000h–0EFFFFh SA37 0011110XXX 32 0F0000h–0F7FFFh SA38 0011111XXX 32 0F8000h–0FFFFFh SA39 0100000XXX 32 100000h–107FFFh SA40 0100001XXX 32 108000h–10FFFFh SA41 0100010XXX 32 110000h–117FFFh SA42 0100011XXX 32 118000h–11FFFFh SA43 0100100XXX 32 120000h–127FFFh SA44 0100101XXX 32 128000h–12FFFFh SA45 0100110XXX 32 130000h–137FFFh SA46 0100111XXX 32 138000h–13FFFFh SA47 0101000XXX 32 140000h–147FFFh

Table 5. PL064J Sector Architecture (Continued)

46 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 47 Advance Information Ta b l e 6 . PL032J Sector Architecture Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16) Bank A SA0 000000000 4 000000h–000FFFh SA1 000000001 4 001000h–001FFFh SA2 000000010 4 002000h–002FFFh SA3 000000011 4 003000h–003FFFh SA4 000000100 4 004000h–004FFFh SA5 000000101 4 005000h–005FFFh SA6 000000110 4 006000h–006FFFh SA7 000000111 4 007000h–007FFFh SA8 000001XXX 32 008000h–00FFFFh SA9 000010XXX 32 010000h–017FFFh SA10 000011XXX 32 018000h–01FFFFh SA11 000100XXX 32 020000h–027FFFh SA12 000101XXX 32 028000h–02FFFFh SA13 000110XXX 32 030000h–037FFFh SA14 000111XXX 32 038000h–03FFFFh Bank B SA15 001000XXX 32 040000h–047FFFh SA16 001001XXX 32 048000h–04FFFFh SA17 001010XXX 32 050000h–057FFFh SA18 001011XXX 32 058000h–05FFFFh SA19 001100XXX 32 060000h–067FFFh SA20 001101XXX 32 068000h–06FFFFh SA21 001110XXX 32 070000h–077FFFh SA22 001111XXX 32 078000h–07FFFFh SA23 010000XXX 32 080000h–087FFFh SA24 010001XXX 32 088000h–08FFFFh SA25 010010XXX 32 090000h–097FFFh SA26 010011XXX 32 098000h–09FFFFh SA27 010100XXX 32 0A0000h–0A7FFFh SA28 010101XXX 32 0A8000h–0AFFFFh SA29 010110XXX 32 0B0000h–0B7FFFh SA30 010111XXX 32 0B8000h–0BFFFFh SA31 011000XXX 32 0C0000h–0C7FFFh SA32 011001XXX 32 0C8000h–0CFFFFh SA33 011010XXX 32 0D0000h–0D7FFFh SA34 011011XXX 32 0D8000h–0DFFFFh SA35 011100XXX 32 0E0000h–0E7FFFh SA36 011101XXX 32 0E8000h–0EFFFFh SA37 011110XXX 32 0F0000h–0F7FFFh SA38 011111XXX 32 0F8000h–0FFFFFh

48 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

Table 6. PL032J Sector Architecture (Continued)

autoselect codes can also be accessed in-system through the command register. Table 17. Note that if a Bank Address (BA) the other bank, without exiting the autoselect mode. Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care.

0 A9 A8 A7 A6

50 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

Ta bl e 9 . PL127J Boot Sector/Sector Block Addresses for Protection/Unprotection Sector A22-A12 Sector/ Sector Block Size Sector A22-A12 Sector/ Sector Block Size SA0 00000000000 4 Kwords SA131-SA134 011111XXXXX 128 (4x32) Kwords SA1 00000000001 4 Kwords SA135-SA138 100000XXXXX 128 (4x32) Kwords SA2 00000000010 4 Kwords SA139-SA142 100001XXXXX 128 (4x32) Kwords SA3 00000000011 4 Kwords SA143-SA146 100010XXXXX 128 (4x32) Kwords SA4 00000000100 4 Kwords SA147-SA150 100011XXXXX 128 (4x32) Kwords SA5 00000000101 4 Kwords SA151-SA154 100100XXXXX 128 (4x32) Kwords SA6 00000000110 4 Kwords SA155-SA158 100101XXXXX 128 (4x32) Kwords SA7 00000000111 4 Kwords SA159-SA162 100110XXXXX 128 (4x32) Kwords SA8 00000001XXX 32 Kwords SA163-SA166 100111XXXXX 128 (4x32) Kwords SA9 00000010XXX 32 Kwords SA167-SA170 101000XXXXX 128 (4x32) Kwords SA10 00000011XXX 32 Kwords SA171-SA174 101001XXXXX 128 (4x32) Kwords SA11-SA14 000001XXXXX 128 (4x32) Kwords SA175-SA178 101010XXXXX 128 (4x32) Kwords SA15-SA18 000010XXXXX 128 (4x32) Kwords SA179-SA182 101011XXXXX 128 (4x32) Kwords SA19-SA22 000011XXXXX 128 (4x32) Kwords SA183-SA186 101100XXXXX 128 (4x32) Kwords SA23-SA26 000100XXXXX 128 (4x32) Kwords SA187-SA190 101101XXXXX 128 (4x32) Kwords SA27-SA30 000101XXXXX 128 (4x32) Kwords SA191-SA194 101110XXXXX 128 (4x32) Kwords SA31-SA34 000110XXXXX 128 (4x32) Kwords SA195-SA198 101111XXXXX 128 (4x32) Kwords SA35-SA38 000111XXXXX 128 (4x32) Kwords SA199-SA202 110000XXXXX 128 (4x32) Kwords SA39-SA42 001000XXXXX 128 (4x32) Kwords SA203-SA206 110001XXXXX 128 (4x32) Kwords SA43-SA46 001001XXXXX 128 (4x32) Kwords SA207-SA210 110010XXXXX 128 (4x32) Kwords SA47-SA50 001010XXXXX 128 (4x32) Kwords SA211-SA214 110011XXXXX 128 (4x32) Kwords SA51-SA54 001011XXXXX 128 (4x32) Kwords SA215-SA218 110100XXXXX 128 (4x32) Kwords SA55-SA58 001100XXXXX 128 (4x32) Kwords SA219-SA222 110101XXXXX 128 (4x32) Kwords SA59-SA62 001101XXXXX 128 (4x32) Kwords SA223-SA226 110110XXXXX 128 (4x32) Kwords SA63-SA66 001110XXXXX 128 (4x32) Kwords SA227-SA230 110111XXXXX 128 (4x32) Kwords SA67-SA70 001111XXXXX 128 (4x32) Kwords SA231-SA234 111000XXXXX 128 (4x32) Kwords SA71-SA74 010000XXXXX 128 (4x32) Kwords SA235-SA238 111001XXXXX 128 (4x32) Kwords SA75-SA78 010001XXXXX 128 (4x32) Kwords SA239-SA242 111010XXXXX 128 (4x32) Kwords SA79-SA82 010010XXXXX 128 (4x32) Kwords SA243-SA246 111011XXXXX 128 (4x32) Kwords SA83-SA86 010011XXXXX 128 (4x32) Kwords SA247-SA250 111100XXXXX 128 (4x32) Kwords SA87-SA90 010100XXXXX 128 (4x32) Kwords SA251-SA254 111101XXXXX 128 (4x32) Kwords SA91-SA94 010101XXXXX 128 (4x32) Kwords SA255-SA258 111110XXXXX 128 (4x32) Kwords SA95-SA98 010110XXXXX 128 (4x32) Kwords SA259 11111100XXX 32 Kwords SA99-SA102 010111XXXXX 128 (4x32) Kwords SA260 11111101XXX 32 Kwords SA103-SA106 011000XXXXX 128 (4x32) Kwords SA261 11111110XXX 32 Kwords SA107-SA110 011001XXXXX 128 (4x32) Kwords SA262 11111111000 4 Kwords SA111-SA114 011010XXXXX 128 (4x32) Kwords SA263 11111111001 4 Kwords SA115-SA118 011011XXXXX 128 (4x32) Kwords SA264 11111111010 4 Kwords SA119-SA122 011100XXXXX 128 (4x32) Kwords SA265 11111111011 4 Kwords SA123-SA126 011101XXXXX 128 (4x32) Kwords SA127-SA130 011110XXXXX 128 (4x32) Kwords

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 51 Advance Information T able 10. PL064J Boot Sector/Sector Block Addresses for Protection/Unprotection Sector A21-A12 Sector/Sector Block Size SA0 0000000000 4 Kwords SA1 0000000001 4 Kwords SA2 0000000010 4 Kwords SA3 0000000011 4 Kwords SA4 0000000100 4 Kwords SA5 0000000101 4 Kwords SA6 0000000110 4 Kwords SA7 0000000111 4 Kwords SA8 0000001XXX 32 Kwords SA9 0000010XXX 32 Kwords SA10 0000011XXX 32 Kwords SA11-SA14 00001XXXXX 128 (4x32) Kwords SA15-SA18 00010XXXXX 128 (4x32) Kwords SA19-SA22 00011XXXXX 128 (4x32) Kwords SA23-SA26 00100XXXXX 128 (4x32) Kwords SA27-SA30 00101XXXXX 128 (4x32) Kwords SA31-SA34 00110XXXXX 128 (4x32) Kwords SA35-SA38 00111XXXXX 128 (4x32) Kwords SA39-SA42 01000XXXXX 128 (4x32) Kwords SA43-SA46 01001XXXXX 128 (4x32) Kwords SA47-SA50 01010XXXXX 128 (4x32) Kwords SA51-SA54 01011XXXXX 128 (4x32) Kwords SA55-SA58 01100XXXXX 128 (4x32) Kwords SA59-SA62 01101XXXXX 128 (4x32) Kwords SA63-SA66 01110XXXXX 128 (4x32) Kwords SA67-SA70 01111XXXXX 128 (4x32) Kwords SA71-SA74 10000XXXXX 128 (4x32) Kwords SA75-SA78 10001XXXXX 128 (4x32) Kwords SA79-SA82 10010XXXXX 128 (4x32) Kwords SA83-SA86 10011XXXXX 128 (4x32) Kwords SA87-SA90 10100XXXXX 128 (4x32) Kwords SA91-SA94 10101XXXXX 128 (4x32) Kwords SA95-SA98 10110XXXXX 128 (4x32) Kwords SA99-SA102 10111XXXXX 128 (4x32) Kwords SA103-SA106 11000XXXXX 128 (4x32) Kwords SA107-SA110 11001XXXXX 128 (4x32) Kwords SA111-SA114 11010XXXXX 128 (4x32) Kwords SA115-SA118 11011XXXXX 128 (4x32) Kwords SA119-SA122 11100XXXXX 128 (4x32) Kwords SA123-SA126 11101XXXXX 128 (4x32) Kwords SA127-SA130 11110XXXXX 128 (4x32) Kwords SA131 1111100XXX 32 Kwords SA132 1111101XXX 32 Kwords SA133 1111110XXX 32 Kwords SA134 1111111000 4 Kwords SA135 1111111001 4 Kwords SA136 1111111010 4 Kwords SA137 1111111011 4 Kwords SA138 1111111100 4 Kwords

52 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

Selecting a Sector Protection Mode The device is shipped with all sectors unprotected. Optional Spansion program - ming services enable programming and protecting sectors at the factory prior to shipping the device. Contact your local sales office for details. It is possible to determine whether a sector is protected or unprotected. See the Secured Silicon Sector Addresses for details. SA139 1111111101 4 Kwords SA140 1111111110 4 Kwords SA141 1111111111 4 Kwords T able 11. PL032J Boot Sector/Sector Block Addresses for Protection/Unprotection Sector A21-A12 Sector/Sector Block Size SA0 000000000 4 Kwords SA1 000000001 4 Kwords SA2 000000010 4 Kwords SA3 000000011 4 Kwords SA4 000000100 4 Kwords SA5 000000101 4 Kwords SA6 000000110 4 Kwords SA7 000000111 4 Kwords SA8 000001XXX 32 Kwords SA9 000010XXX 32 Kwords SA10 000011XXX 32 Kwords SA11-SA14 0001XXXXX 128 (4x32) Kwords SA15-SA18 0010XXXXX 128 (4x32) Kwords SA19-SA22 0011XXXXX 128 (4x32) Kwords SA23-SA26 0100XXXXX 128 (4x32) Kwords SA27-SA30 0101XXXXX 128 (4x32) Kwords SA31-SA34 0110XXXXX 128 (4x32) Kwords SA35-SA38 0111XXXXX 128 (4x32) Kwords SA39-SA42 1000XXXXX 128 (4x32) Kwords SA43-SA46 1001XXXXX 128 (4x32) Kwords SA47-SA50 1010XXXXX 128 (4x32) Kwords SA51-SA54 1011XXXXX 128 (4x32) Kwords SA55-SA58 1100XXXXX 128 (4x32) Kwords SA59-SA62 1101XXXXX 128 (4x32) Kwords SA63-SA66 1110XXXXX 128 (4x32) Kwords SA67 111100XXX 32 Kwords SA68 111101XXX 32 Kwords SA69 111110XXX 32 Kwords SA70 111111000 4 Kwords SA71 111111001 4 Kwords SA72 111111010 4 Kwords SA73 111111011 4 Kwords SA74 111111100 4 Kwords SA75 111111101 4 Kwords SA76 111111110 4 Kwords SA77 111111111 4 Kwords T able 10. PL064J Boot Sector/Sector Block Addresses for Protection/Unprotection Sector A21-A12 Sector/Sector Block Size

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 53 Advance Information Sector Protection The PL127J, PL064J, and PL032J features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups. Sector Protection Schemes Password Sector Protection A highly sophisticated protection meth od that requires a password before changes to certain sectors or sector groups are permitted WP# Hardware Protection A write protect pin that can prevent program or erase operations in sectors SA1- 133, SA1-134, SA2-0 and SA2-1. The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen. Selecting a Sector Protection Mode All parts default to operate in the Pers istent Sector Protection mode. The cus - tomer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method will be used. If the Persistent Sector Protection method is desired, programming the Persistent Sector Protection Mode Locking Bit permanently sets the device to the Persistent Sector Protection mode. If the Password Sector Protection method is desired, programming the Password Mode Locking Bit permanently sets the device to the Password Sector Protection mode. It is not possible to switch between the two protection modes once a locking bit has been set. One of the two modes must be selected when the device is first programmed. This prevents a program or virus from later setting the Password Mode Locking Bit, which would cause an unexpected shift from the default Per sistent Sector Protection Mode into the Password Protection Mode. The device is shipped with all sectors unprotected. Optional Spansion program - ming services enable programming and protecting sectors at the factory prior to shipping the device. Contact your local sales office for details. Ta bl e 1 2 . Sector Protection Schemes DYB PPB PPB Lock Sector State 0 0 0 Unprotected—PPB and DYB are changeable 0 0 1 Unprotected—PPB not changeable, DYB is changeable 0 1 0 Protected—PPB and DYB are changeable1 0 0 1 1 0 0 1 1 Protected—PPB not changeable, DYB is changeable1 0 1 1 1 1

54 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

It is possible to determine whether a sector is protected or unprotected. See Au- toselect Mode for details. Persistent Sector Protection The Persistent Sector Protection method replaces the 12 V controlled protection method in previous flash devices. This new method provides three different sec- tor protection states: Persistently Locked—The sector is protected and cannot be changed. Dynamically Locked—The sector is protected and can be changed by a simple command. Unlocked—The sector is unprotected and can be changed by a simple com - mand. To achieve these states, three types of “bits” are used: Persistent Protection Bit Persistent Protection Bit Lock Persistent Sector Protection Mode Locking Bit Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protecti on Bit is assigned to a maximum four sectors (see the sector address tables for specific sector protection groupings). All 4 Kword boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. The device erases all PPBs in parallel. If any PPB requires erasure, the device must be instructed to preprogram all of the sector PPBs prior to PPB erasure. Oth erwise, a previously erased sector PPBs can potentially be over-erased. The flash device does not have a built-in means of preventing sector PPBs over-erasure. Persistent Protection Bit Lock (PPB Lock) The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to “1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power- up or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through the DYB Write Command. When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared state – meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not pro- tected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the so- called Dynamic Locked or Unlocked states. They are called dynamic states be cause it is very easy to switch ba ck and forth betwee n the protected and unprotected conditions. This allows software to easily protect sectors against in-

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 55 Advance Information advertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are non-volatile. Indi - vidual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also lim- ited to 100 erase cycles. The PPB Lock bit adds an additional level of protection. Once all PPBs are pro - grammed to the desired settings, the PPB Lock may be set to “1”. Setting the PPB Lock disables all program and erase commands to the non-volatile PPBs. In ef fect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed; for ex ample, to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PPBs during system operation. The WP#/ACC write protect pin adds a final level of hardware protection to sec- tors SA1-133, SA1-134, SA2-0 and SA2-1. When this pin is low it is not possible to change the contents of these sectors. These sectors generally hold system boot code. The WP#/ACC pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. For customers who are concerned about malicious viruses there is another level of security - the persistently locked state. To persistently protect a given sector or sector group, the PPBs associated with that sector need to be set to “1”. Once all PPBs are programmed to the desired settings, the PPB Lock should be set to “1”. Setting the PPB Lock automatically disables all program and erase commands to the Non-Volatile PPBs. In effect, the PPB Lock “freezes” the PPBs into their cur rent state. The only way to clear the PPB Lock is to go through a power cycle. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write command se quence is all that is necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to re flect the desired settings. Setting the PPB lock bit once again will lock the PPBs, and the device operates normally again. The best protection is achieved by executing the PPB lock bit set command early in the boot code, and protect the boot code by holding WP#/ACC = VIL. Table 12 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the sector. In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PPB lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. If the user attempts to program or eras e a protected sector, the device ignores the command and returns to read mode. A program command to a protected sec- tor enables status polling for approximately 1 µs before the device returns to read

56 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 µs after which the device returns to read mode without having erased the protected sector. The programming of the DYB, PPB, and PPB lock for a given sector can be verified by writing a DYB/PPB/PPB lock verify command to the device. There is an alter native means of reading the protection status. Take RESET# to VIL and hold WE# at VIH.(The high voltage A9 Autoselect Mode also works for reading the status of the PPBs). Scanning the addresses (A18–A11) while (A6, A1, A0) = (0, 1, 0) will produce a logical ‘1” code at device output DQ0 for a protected sector or a “0” for an unprotected sector. In this mode, the other addresses are don’t cares. Address location with A1 = VIL are reserved for autoselect manufacturer and device codes. Persistent Sector Protection Mode Locking Bit Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode. Password Protection Mode The Password Sector Protection Mode method allows an even higher level of se- curity than the Persistent Sector Protection Mode. There are two main differences between the Persistent Sector Protection and the Password Sector Protection Mode: When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs delay for each “password check.” This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the password. The password may be correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations.

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 57 Advance Information Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: Permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. Disables all further commands to the password region. All program, and read op- erations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the passwo rd is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after set ting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persis tent Sector Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see “Password Verify Command”). The password function work s in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device. Write Protect (WP#) The Write Protect feature provides a hardware method of protecting the upper two and lower two sectors without using V ID. This function is provided by the WP# pin and overrides the previously discussed High Voltage Sector Protection method. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two outermost 4 Kword sectors on both ends of the flash array independent of whether it was previously protected or unprotected. If the system asserts VIH on the WP#/ACC pin, the device reverts the upper two and lower two sectors to whether they were last set to be protected or unpro - tected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in the High Voltage Sector Protection. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Assert ing RESET#, taking the device through a power-on reset, or issuing the PPB Lock

58 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

Bit Set command sets the PPB Lock Bit to a “1” when the Password Mode Lock Bit is not set. If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clear- ing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode. High Voltage Sector Protection Sector protection and unprotection may also be implemented using programming equipment. The procedure requires high voltage (V ID) to be placed on the RE - SET# pin. Refer to Figure 1 for details on this procedure. Note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle.

Figure 1. In-System Sector Protection/Sector Unprotection Algorithms

60 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

is set, the device cannot enter the Temporary Sector Unprotection Mode. tory-locked and customer-locked status of the part.

All protected sectors unprotected (If WP#/ACC = V IL, upper two and lower two

sectors will remain protected).

All previously protected sectors are protected once again

Figure 2. T emporary Sector Unprotect Operation

62 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

power-up and power-down transitions, or from system noise. when VCC is greater than VLKO. reset to the read mode on power-up. Figure 3. Secured Silicon Sector Protect Verify

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 63 Advance Information Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft - ware algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and back - ward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 13–16. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. The system can also write the CFI query command when the device is in the au- toselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 13–16. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100. Contact your local sales office for copies of these documents. Ta b l e 1 3 . CFI Query Identification String Addresses Data Description 10h 11h 12h 0051h 0052h 0059h Query Unique ASCII string “QRY” 13h 14h 0002h 0000h Primary OEM Command Set 15h 16h 0040h 0000h Address for Primary Extended Table 17h 18h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists)

64 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

Ta b l e 1 4 . System Interface String Addresses Data Description 1Bh 0027h VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 0036h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 0003h Typical timeout per single byte/word write 2 N µs 20h 0000h Typical timeout for Min. size buffer write 2 N µs (00h = not supported) 21h 0009h Typical timeout per individual block erase 2 N ms 22h 0000h Typical timeout for full chip erase 2 N ms (00h = not supported) 23h 0004h Max. timeout for byte/word write 2 N times typical 24h 0000h Max. timeout for buffer write 2 N times typical 25h 0004h Max. timeout per individual block erase 2 N times typical 26h 0000h Max. timeout for full chip erase 2 N times typical (00h = not supported) Ta b l e 1 5 . Device Geometry Definition Addresses Data Description 27h 0018h (PL127J) 0017h (PL064J) 0016h (PL032J) Device Size = 2 N byte 28h 29h 0001h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 0000h 0000h Max. number of byte in multi-byte write = 2 N (00h = not supported) 2Ch 0003h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 0007h 0000h 0020h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 00FDh (PL127J) 007Dh (PL064J) 003Dh (PL032J) Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100)32h 33h 34h 0000h 0000h 0001h 35h 36h 37h 38h 0007h 0000h 0020h 0000h Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) 39h 3Ah 3Bh 3Ch 0000h 0000h 0000h 0000h Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100)

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 65 Advance Information Ta b l e 1 6 . Primary Vendor-Specific Extended Query Addresses Data Description 40h 41h 42h 0050h 0052h 0049h Query-unique ASCII string “PRI” 43h 0031h Major version number, ASCII (reflects modifications to the silicon) 44h 0033h Minor version number, ASCII (reflects modifications to the CFI table) 45h TBD Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) 46h 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 0007h (PLxxxJ) Sector Protect/Unprotect scheme 07 = Advanced Sector Protection 4Ah 00E7h (PL127J) 0077h (PL064J) 003Fh (PL032J) Simultaneous Operation 00 = Not Supported, X = Number of Sectors excluding Bank 1 4Bh 0000h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 0002h (PLxxxJ) Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 0085h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Eh 0095h ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Fh 0001h Top/Bottom Boot Sector Flag 00h = Uniform device, 01h = Both top and bottom boot with write protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom 50h 0001h Program Suspend 0 = Not supported, 1 = Supported 57h 0004h Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks 58h 0027h (PL127J) 0017h (PL064J) 000Fh (PL032J) Bank 1 Region Information X = Number of Sectors in Bank 1 59h 0060h (PL127J) 0030h (PL064J) 0018h (PL032J) Bank 2 Region Information X = Number of Sectors in Bank 2 5Ah 0060h (PL127J) 0030h (PL064J) 0018h (PL032J) Bank 3 Region Information X = Number of Sectors in Bank 3

66 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

Writing specific address and data commands or sequences into the command register initiates device operations. Table 17 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset com - mand is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristic section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Re- sume Commands section for more information. The system must issue the reset command to return a bank to the read (or erase- suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations sec- tion for more information. The AC Characteristic table provides the read parameters, and Figure 12 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys tem was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. 5Bh 0027h (PL127J) 0017h (PL064J) 000Fh (PL032J) Bank 4 Region Information X = Number of Sectors in Bank 4 T able 16. Primary Vendor-Specific Extended Query (Continued) Addresses Data Description

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 67 Advance Information The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manu- facturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au toselect command. The bank then enters the autoselect mode. The system may read any number of autoselect codes without reinitiating the command sequence. Table 17 shows the address and data requirements. To determine sector protec- tion information, the system must write to the appropriate bank address (BA) and sector address (SA). Table 3 shows the address range and bank number associ- ated with each sector. The system must write the reset command to return to the read mode (or erase- suspend-read mode if the bank was previously in Erase Suspend). Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence The Secured Silicon Sector region provides a secured data area containing a ran- dom, eight word electronic serial number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues th e four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal operation. The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 17 shows the address and data requirements for both command sequences. See also “Secured Silicon Sector Flash Memory Region” for further information. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled. Word Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com- mand. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further con- trols or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 17 shows the address and data requirements for the program command sequence. Note that the Secured

68 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

Silicon Sector, autoselect, and CFI functi ons are unavailable when a [program/ erase] operation is in progress. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Note that the Secured Silicon Sector, autoselect and CFI functions are unavailable when the Secured Sil icon Sector is enabled. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to program data to a bank faster than using the standard program command sequence. The unlock bypass com mand sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this se quence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 17 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock By- pass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (See Table 18) The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V HH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH any operation other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or uncon - nected; inconsistent behavior of the device may result. 4 illustrates the algorithm for the program operation. Refer to the Erase/Program Operations table in the AC Characteristics section for parameters, and Figure 14 for timing diagrams.

for the chip erase command sequence. Operation Status section for information on these status bits. array data, to ensure data integrity. Note: See Table 17 for program command sequence. Figure 4. Program Operation

70 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

5 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the AC Characteristics section for parameters, and Figure 16 section for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two addi- tional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 17 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Em - bedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase com mands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time- out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any com mand other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system must rewrite the com mand sequence and any additional addresses and commands. Note that Secured Silicon Sector, autoselect, and CFI functi ons are unavailable when a [program/ erase] operation is in progress. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer). The time-out begins from the ris ing edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Sta- tus section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset im mediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. 5 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the AC Characteristics section for parameters, and Figure 16 section for timing diagrams.

to the Write Operation Status section for information on these status bits.

See Table 17 for erase command sequence.
See the section on DQ3 for information on the sector erase timer.

Figure 5. Erase Operation

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operation using the DQ7 or DQ6 status bits, just as in the standard Word Program operation. Refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the system can also issue the autoselect com- mand sequence. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. Refer to the Secured Silicon Sec- tor Addresses and the Autoselect Command Sequence sections for details. To resume the sector erase operation, the system must write the Erase Resume command (address bits are don’t care). The bank address of the erase-sus - pended bank is required when writin g this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector Protection Mode Locking Bit Program Com mand should be reissued to improve program margin. If the Secured Silicon Sector Protection Bit is verified as programmed without margin, the Secured Sil- icon Sector Protection Bit Program Command should be reissued to improve program margin. µµAfter programming a PPB, two additional cycles are needed to determine whether the PPB has been programmed with margin. If the PPB has been programmed without margin, the program command should be reissued to improve the program margin. Also note that the total number of PPB program/ erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been erased with margin. If the PPBs has been erased without mar gin, the erase command should be reissued to improve the program margin. The programming of either the PPB or DYB for a given sector or sector group can be verified by writing a Sector Protection Status command to the device. Note that there is no single command to independently verify the programming of a DYB for a given sector group. Command Definitions T ables Ta bl e 1 7 . Memory Array Command Definitions Command (Notes) Cycles Bus Cycles (Notes 1–4) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read (Note 5) 1 RA RD Reset (Note 6) 1 XXX F0 Autoselect (Note 7) Manufacturer ID 4 555 AA 2AA 55 (BA) 555 90 (BA) X00 01 Device ID (Note 10) 6 555 AA 2AA 55 (BA) 555 90 (BA) X01 227E (BA) X0E (Note 10) (BA) X0F (Note 10) Secured Silicon Sector Factory Protect (Note 8) 4 555 AA 2AA 55 (BA) 555 90 X03 (Note Sector Group Protect Verify (Note 9) 4 555 AAA 2AA 55 (BA) 555 90 (SA) X02 XX00/ XX01 Program 4 555 AA 2AA 55 555 A0 PA PD Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Program/Erase Suspend (Note 11) 1 BA B0

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 73 Advance Information Program/Erase Resume (Note 12) 1 BA 30 CFI Query (Note 13) 1 55 98 Accelerated Program (Note 15) 2 XX A0 PA PD Unlock Bypass Entry (Note 15) 3 555 AA 2AA 55 555 20 Unlock Bypass Program (Note 15) 2 XX A0 PA PD Unlock Bypass Erase (Note 15) 2 XX 80 XX 10 Unlock Bypass CFI (Notes 13, 15) 1 XX 98 Unlock Bypass Reset (Note 15) 2 XXX 90 XXX 00 Ta b l e 18 . Sector Protection Command Definitions Command (Notes) Cycles Bus Cycles (Notes 1-4) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Reset 1 XXX F0 Secured Silicon Sector Entry 3 555 AA 2AA 55 555 88 Secured Silicon Sector Exit 4 555 AA 2AA 55 555 90 XX 00 Secured Silicon Protection Bit Program (Notes 6 555 AA 2AA 55 555 60 OW 68 OW 48 OW RD(0) Secured Silicon Protection Bit Status 5 555 AA 2AA 55 555 60 OW 48 OW RD(0) Password Program (Notes 5, 7, 8) 4 555 AA 2AA 55 555 38 XX[0-3] PD[0-3] T able 17. Memory Array Command Definitions Command (Notes) Cycles Bus Cycles (Notes 1–4) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Legend: BA = Address of bank switching to autoselect mode, bypass mode, or erase operation. Determined by PL127J: Amax:A20, PL064J: Amax:A19, PL032J: Amax:A18. PA = Program Address (Amax:A0). Addresses latch on falling edge of WE# or CE# pulse, whichever happens later. PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of WE# or CE# pulse, whichever happens first. RA = Read Address (Amax:A0). RD = Read Data (DQ15:DQ0) from location RA. SA = Sector Address (Amax:A12) for verifying (in autoselect mode) or erasing. WD = Write Data. See “Configuration Register” definition for specific write data. Data latched on rising edge of WE#. X = Don’t care Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells in table denote read cycles. All other cycles are write operations. 4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 5. No unlock or command cycles required when bank is reading array data. 6. The Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend) when bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information). 7. Fourth cycle of autoselect command sequence is a read cycle. System must provide bank address to obtain manufacturer ID or device ID information. See Autoselect Command Sequence section for more information. 8. The data is C4h for factory and customer locked, 84h for factory locked and 04h for not locked. 9. The data is 00h for an unprotected sector group and 01h fo r a protected sector group. 10. Device ID must be read across cycles 4, 5, and 6. PL127J (X0Eh = 2220h, X0Fh = 2200h),PL064J (X0Eh = 2202h, X0Fh = 2201h), PL032J (X0Eh = 220Ah, X0Fh = 2201h). 11. System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode. Program/Erase Suspend command is valid only during a sector erase operation, and requires bank address. 12. Program/Erase Resume command is valid only during Erase Suspend mode, and requires bank address. 13. Command is valid when device is ready to read array data o r when device is in autoselect mode. 14. WP#/ACC must be at VID during the entire operation of command. 15. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required to return to the reading array.

74 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

The device provides several bits to determine the status of a program or erase opera- tion: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 19 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a Password Verify (Notes 6, 8, 9) 4 555 AA 2AA 55 555 C8 PWA[0-3] PWD[0-3] Password Unlock (Notes 7, 10, 11) 7 555 AA 2AA 55 555 28 PWA[0] PWD[0] PWA[1] PWD[1] PWA[2] PWD[2] PWA[3] PWD[3] PPB Program (Notes 5, 6, 12) 6 555 AA 2AA 55 555 60 (SA)WP 68 (SA)WP 48 (SA)WP RD(0) PPB Status 4 555 AA 2AA 55 555 90 (SA)WP RD(0) All PPB Erase (Notes 5, 6, 13, 14) 6 555 AA 2AA 55 555 60 WP 60 (SA) 40 (SA)WP RD(0) PPB Lock Bit Set 3 555 AA 2AA 55 555 78 PPB Lock Bit Status (Note 15) 4 555 AA 2AA 55 555 58 SA RD(1) DYB Write (Note 7) 4 555 AA 2AA 55 555 48 SA X1 DYB Erase (Note 7) 4 555 AA 2AA 55 555 48 SA X0 DYB Status (Note 6) 4 555 AA 2AA 55 555 58 SA RD(0) PPMLB Program (Notes 5, 6, 12) 6 555 AA 2AA 55 555 60 PL 68 PL 48 PL RD(0) PPMLB Status (Note 5) 5 555 AA 2AA 55 555 60 PL 48 PL RD(0) SPMLB Program (Notes 5, 6, 12) 6 555 AA 2AA 55 555 60 SL 68 SL 48 SL RD(0) SPMLB Status (Note 5) 5 555 AA 2AA 55 555 60 SL 48 SL RD(0) T able 18. Sector Protection Command Definitions Legend: DYB = Dynamic Protection Bit OW = Address (A7:A0) is (00011010) PD[3:0] = Password Data (1 of 4 portions) PPB = Persistent Protection Bit PWA = Password Address. A1:A0 selects portion of password. PWD = Password Data being verified. PL = Password Protection Mode Lock Address (A7:A0) is (00001010) RD(0) = Read Data DQ0 for protection indicator bit. RD(1) = Read Data DQ1 for PPB Lock status. SA = Sector Address where security command applies. Address bits Amax:A12 uniquely select any sector. SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010) WP = PPB Address (A7:A0) is (00000010) X = Don’t care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells in table denote read cycles. All other cycles are write operations. 4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 5. The reset command returns device to reading array. 6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle 6, program command must be issued and verified again. 7. Data is latched on the rising edge of WE#. 8. Entire command sequence must be entered for each portion of password. 9. Command sequence returns FFh if PPMLB is set. 10. The password is written over four consecutive cycles, at addresses 0-3. 11. A 2 µs timeout is required between any two portions of password. 12. A 100 µs timeout is required between cycles 4 and 5. 13. A 1.2 ms timeout is required between cycles 4 and 5. 14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB overerasure. 15. DQ1 = 1 if PPB locked, 0 if unlocked.

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 75 Advance Information hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Pro- gram or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the com mand sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device out puts the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status in formation on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 400 µs, then the bank returns to the read mode. If not all selected sectors are protected, the Em- bedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ15–DQ0 on the following read cycles. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asyn chronously with DQ15–DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid data on DQ15–DQ0 will appear on successive read cycles. Table 19 shows the outputs for Data# Polling on DQ7. 6 shows the Data# Polling algorithm. 18 in the AC Characteristic section shows the Data# Polling timing diagram.

76 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

Table 19 shows the outputs for RY/BY#.

VA = Valid address for programming. During a sector erase operation, a valid address is

any non-protected sector address.

DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously

Figure 6. Data# Polling Algorithm

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 77 Advance Information of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cy- cles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 400 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algo rithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is ac- tively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en ters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alter natively, the system can use DQ7 (see the DQ7: Data# Polling). If a program address falls within a pr otected sector, DQ6 toggles for approxi - mately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 19 shows the outputs for Toggle Bit I on DQ6. Figure 7 shows the toggle bit algorithm. Figure 19 in “Read Operation Timings” shows the toggle bit timing di- agrams. Figure 20 shows the differences between DQ2 and DQ6 in graphical form. See also the DQ2: Toggle Bit II.

78 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

edge of the final WE# pulse in the command sequence. for erasure. Thus, both status bits are required for sector and mode information. Table 19 to compare outputs for DQ2 and DQ6. Toggle Bit II for more information. Figure 7. T oggle Bit Algorithm

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 79 Advance Information store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc cessfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as de scribed in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algo rithm when it returns to determine the status of the operation (top of Figure 7). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified inter- nal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the opera tion, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to de- termine whether or not erasure has beg un. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” See also the Sector Erase Command Sequence. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept addi tional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each sub- sequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 19 shows the status of DQ3 relative to the other status bits.

80 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. Ta b l e 1 9 . Write Operation Status Status DQ7 (Note 2) DQ6 DQ5 (Note 1) DQ3 DQ2 (Note 2) RY/BY# Standard Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0 Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0 Erase Suspend Mode Erase-Suspend- Read Erase Suspended Sector 1 No toggle 0 N/A Toggle 1 Non-Erase Suspended Sector Data Data Data Data Data 1 Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions,

I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8.

Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is –0.5 V.

overshoot to +12.0 V for periods up to 20 ns.

No more than one output may be shorted to ground at a time. Duration of the

short circuit should not be greater than one second.

Stresses above those listed under “Absolute Maximum Ratings” may cause perma-

imum rating conditions for extended periods may affect device reliability. Figure 8. Maximum Overshoot Waveforms

82 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

Operating ranges define those limits between which the functionality of the de - vice is guaranteed. Industrial (I) Devices Wireless Devices Supply Voltages Notes: For all AC and DC specifications, VIO = VCC; contact your local sales office for other VIO options.

The I CC current listed is typically less than 5 mA/MHz, with OE# at VIH.
Maximum I CC specifications are tested with VCC = VCCmax.
I CC active while Embedded Erase or Embedded Program is in progress.
Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep
Valid CE1#/CE2# conditions: (CE1# = V IL, CE2# = VIH,) or (CE1# = VIH, CE2# = VIL) or (CE1# = VIH, CE2# = VIH)

Table 20. CMOS Compatible

5 MHz 15 25

10 MHz 45 55

5 MHz 21 45

10 MHz 46 70

84 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

Figure 9. Te s t S e t u p s

Figure 10. Input Waveforms and Measurement Levels

86 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

See Figure 9 and Table 21 for test specifications.
Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC /2. The time from OE#

high to the data bus driven to VCC /2 is taken as tDF.

For 70pF Output Load Capacitance, 2 ns will be added to the above t ACC,tCE,tPACC,tOE values for all speed grades.

Figure 11. Read Operation Timings

0 VRY/BY#

Figure 12. Page Read Operation Timings

88 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

Figure 13. Reset Timings

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 89 Advance Information Erase/Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Ta b l e 2 5 . Erase and Program Operations Parameter Speed Options JEDEC Std Description 55 60 65 70 Unit tAVAV tWC Write Cycle Time (Note 1) Min 55 60 65 70 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 30 35 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 25 30 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 10 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 40 ns tWHDL tWPH Write Pulse Width High Min 20 25 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 6 µs tWHWH1 tWHWH1 Accelerated Programming Operation (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns

90 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

PA = program address, PD = program data, D OUT is the true data at the program address

Figure 14. Program Operation Timings Figure 15. Accelerated Program Timing Diagram

92 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

Figure 18. Data# Polling Timings (During Embedded Algorithms)

VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last

Figure 19. T oggle Bit Timings (During Embedded Algorithms)

94 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

Figure 22. Sector/Sector Block Protect and Unprotect Timing Diagram

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 95 Advance Information Controlled Erase Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Ta bl e 2 7 . Alternate CE# Controlled Erase and Program Operations Parameter Speed Options JEDEC Std Description 55 60 65 70 Unit tAVAV tWC Write Cycle Time (Note 1) Min 55 60 65 70 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 30 35 ns tDVEH tDS Data Setup Time Min 25 30 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 35 40 ns tEHEL tCPH CE# Pulse Width High Min 20 25 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 6 µs tWHWH1 tWHWH1 Accelerated Programming Operation (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec

96 S29PL127J/S29PL064J/S29PL032J for MCP S29PL127J_064J_032J_MCP_00_A3 August 12, 2004

Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. D OUT is the data written to the device Ta b l e 2 8 . Alternate CE# Controlled Write (Erase/Program) Operation Timings tGHEL tWS OE# CE# WE# RESET# tDS Data tAH Addresses tDH tCP DQ7# D OUT tWC tAS tCPH PA Data# Polling A0 for program 55 for erase tRH tWHWH1 or 2 RY/BY# tWH PD for program 30 for sector erase 10 for chip erase 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase tBUSY

August 12, 2004 S29PL127J_064J_032J_MCP_00_A3 S29PL127J/S29PL064J/S29PL032J for MCP 97 Advance Information Notes: 1. Typical program and erase times assume the following conditions: 25 ×C, 3.0 V VCC, 100,000 cycles. Additionally, programming typicals assume checkerboard pattern. All values are subject to change. 2. Under worst case conditions of 90 ×C, VCC = 2.7 V, 100,000 cycles. All values are subject to change. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 17 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 100,000 cycles. BGA Pin Capacitance Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. Ta b l e 2 9 . Erase And Programming Performance Parameter Ty p (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.5 2 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time PL127J 135 216 sec PL064J 71 113.6 sec PL032J 39 62.4 sec Word Program Time 6 100 µs Excludes system level overhead (Note 5) Accelerated Word Program Time 4 60 µs Chip Program Time (Note 3) PL127J 50.4 200 sec PL064J 25.2 50.4 sec PL032J 12.6 25.2 sec Parameter Symbol Parameter Description Te s t S e t u p Ty p Max Unit CIN Input Capacitance VIN = 0 6.3 7 pF COUT Output Capacitance VOUT = 0 7.0 8 pF CIN2 Control Pin Capacitance VIN = 0 5.5 8 pF CIN3 WP#/ACC Pin Capacitance VIN = 0 11 12 pF

98 Type 2 pSRAM pSRAM_Type02_15A0 May 3, 2004

16Mb (1Mb Word x 16-bit) 32Mb (2Mb Word x 16-bit) 64Mb (4Mb Word x 16-bit)

Features

Process Technology: CMOS Organization: x16 bit Power Supply Voltage: 2.7~3.1V Three State Outputs Compatible with Low Power SRAM Product Information Pin Description Density VCC Range Standby (ISB1, Max.) Operating (ICC2, Max.) Mode 16Mb 2.7-3.1V 80 µA 30 mA Dual CS 16Mb 2.7-3.1V 80 µA 35 mA Dual CS and Page Mode 32Mb 2.7-3.1V 100 µA 35 mA Dual CS 32Mb 2.7-3.1V 100 µA 40 mA Dual CS and Page Mode 64Mb 2.7-3.1V TBD TBD Dual CS 64Mb 2.7-3.1V TBD TBD Dual CS and Page Mode Pin Name Description I/O CS1#, CS2 Chip Select I OE# Output Enable I WE# Write Enable I LB#, UB# Lower/Upper Byte Enable I A0-A19 (16M) A0-A20 (32M) A0-A21 (64M) Address Inputs I I/O0-I/O15 Data Inputs/Outputs I/O VCC/VCCQ Power Supply — VSS/VSSQ Ground — NC Not Connection — DNU Do Not Use —

100 Type 2 pSRAM pSRAM_Type02_15A0 May 3, 2004

Legend:X = Don’t care (must be low or high state). Absolute Maximum Ratings Notes: 1. Stresses greater than those listed under " Absolute Maximum Ratings" section may cause permanent damage to the device. Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability. DC Recommended Operating Conditions Notes: 1. TA=-40 to 85°C, otherwise specified. 2. Overshoot: V CC+1.0V in case of pulse width ≤ 20ns. 3. Undershoot: -1.0V in case of pulse width ≤ 20ns. 4. Overshoot and undershoot are sampled, not 100% tested. Mode CS1# CS2 OE# WE# LB# UB# I/O1-8 I/O9-16 Power Deselected H X X X X X High-Z High-Z Standby Deselected X L X X X X High-Z High-Z Standby Deselected X X X X H H High-Z High-Z Standby Output Disabled L H H H L X High-Z High-Z Active Outputs Disabled L H H H X L High-Z High-Z Active Lower Byte Read L H L H L H D OUT High-Z Active Upper Byte Read L H L H H L High-Z D OUT Active Word Read L H L H L L D OUT DOUT Active Lower Byte Write L H X L L H D IN High-Z Active Upper Byte Write L H X L H L High-Z D IN Active W o r d W r i t e L H X LLL D IN DIN Active Item Symbol Ratings Unit Voltage on any pin relative to VSS VIN , VOUT -0.2 to VCC+0.3V V Voltage on VCC supply relative to VSS VCC -0.2 to 3.6V V Power Dissipation PD 1.0 W Operating Temperature TA -40 to 85 °C Symbol Parameter Min Ty p Max Unit VCC Power Supply Voltage 2.7 2.9 3.1 V VSS Ground 0 0 0 VIH Input High Voltage 2.2 — VCC + 0.3 (Note 2) VIL Input Low Voltage -0.2 (Note 3) — 0.6

May 3, 2004 pSRAM_Type02_15A0 Type 2 pSRAM 101 Advance Information Capacitance (T a = 25°C, f = 1 MHz) Note: This parameter is sampled periodically and is not 100% tested. DC and Operating Characteristics Common Symbol Parameter T est Condition Min Max Unit CIN Input Capacitance VIN = 0V — 8 pF COIO Input/Output Capacitance VOUT = 0V — 10 pF Item Symbol T est Conditions Min Ty p Max Unit Input Leakage Current ILI VIN=VSS to VCC -1 — 1 µA Output Leakage Current ILO CS1#=VIH or CS2=VIL or OE#=VIH or WE#=VIL or LB#=UB#=VIH, VIO=VSS to VCC -1 — 1 µA Output Low Voltage VOL IOL=2.1mA — — 0.4 V Output High Voltage VOH IOH=-1.0mA 2.4 — — V

102 Type 2 pSRAM pSRAM_Type02_15A0 May 3, 2004

Notes: 1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from the time when standby mode is set up. 32M pSRAM Notes: 1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from the time when standby mode is set up. Item Symbol T est Conditions Min Ty p Max Unit Average Operating Current ICC1 Cycle time=1µs, 100% duty, IIO=0mA, CS1#≤0.2V, LB#≤0.2V and/or UB#≤0.2V, CS2≥VCC-0.2V, VIN≤0.2V or VIN≥VCC-0.2V — — 7 mA ICC2 Async Cycle time=Min, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN=VIH or VIL — — 30 mA Page Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN-VIH or VIL 35 mA Standby Current (CMOS) ISB1 (Note 1) Other inputs=0-VCC 1. CS1# ≥ VCC - 0.2, CS2 ≥ VCC - 0.2V (CS1# controlled) or 2. 0V ≤ CS2 ≤ 0.2V (CS2 controlled) — — 80 mA Item Symbol T est Conditions Min Ty p Max Unit Average Operating Current ICC1 Cycle time=1µs, 100% duty, IIO=0mA, CS1#≤0.2V, LB#≤0.2V and/or UB#≤0.2V, CS2≥VCC-0.2V, VIN≤0.2V or VIN≥VCC-0.2V — — 7 mA ICC2 Async Cycle time=Min, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN=VIH or VIL — — 35 mA Page Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN-VIH or VIL 40 mA Standby Current (CMOS) ISB1 (Note 1) Other inputs=0-VCC 1. CS1# ≥ VCC - 0.2, CS2 ≥ VCC - 0.2V (CS1# controlled) or 2. 0V ≤ CS2 ≤ 0.2V (CS2 controlled) — — 100 mA

Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from

the time when standby mode is set up. Note: Including scope and jig capacitance.

0V ≤ CS2 ≤ 0.2V (CS2 controlled)

Figure 25. Output Load

104 Type 2 pSRAM pSRAM_Type02_15A0 May 3, 2004

ACC Characteristics (T a = -40°C to 85°C, VCC = 2.7 to 3.1 V) Notes: 1. t WP (min)=70ns for continuous write operation over 50 times. Symbol Parameter Speed Bins Unit 70ns Min Max Read tRC Read Cycle Time 70 — ns tAA Address Access Time — 70 ns tCO Chip Select to Output — 70 ns tOE Output Enable to Valid Output — 35 ns tBA UB#, LB# Access Time — 70 ns tLZ Chip Select to Low-Z Output 10 — ns tBLZ UB#, LB# Enable to Low-Z Output 10 — ns tOLZ Output Enable to Low-Z Output 5 — ns tHZ Chip Disable to High-Z Output 0 25 ns tBHZ UB#, LB# Disable to High-Z Output 0 25 ns tOHZ Output Disable to High-Z Output 0 25 ns tOH Output Hold from Address Change 5 — ns tPC Page Cycle Time 25 — ns tPA Page Access Time — 20 ns Write tWC Write Cycle Time 70 — ns tCW Chip Select to End of Write 60 — ns tAS Address Set-up Time 0 — ns tAW Address Valid to End of Write 60 — ns tBW UB#, LB# Valid to End of Write 60 — ns tWP Write Pulse Width 55 (Note 1) — ns tWR Write Recovery Time 0 — ns tWHZ Write to Output High-Z 0 25 ns tDW Data to Write Time Overlap 30 — ns tDH Data Hold from Write Time 0 — ns tOW End Write to Output Low-Z 5 — ns

106 Type 2 pSRAM pSRAM_Type02_15A0 May 3, 2004

tOE(max) is met only when OE# becomes enabled after tAA(max). timing (tRC) or needs to sustain standby state for min. tRC at least once in every 4µs. Figure 29. Write Cycle #1 (WE# Controlled) Figure 30. Write Cycle #2 (CS1# Controlled)

108 pSRAM Type 3 pSRAM_Type03_06A0 February 25, 2004 Advance Information pSRAM T ype 3

16 Megabit (1M x 16) CMOS Pseudo SRAM

Organized as 1M words by 16 bits Fast Cycle Time: 70 ns Standby Current: 100 µA Deep power-down Current: 10 µA (Memory cell data invalid) Byte data control: LB# (DQ0 - 7), UB# (DQ8 - 15) Compatible with low-power SRAM Single Power Supply Voltage: 3.0V±0.3V

Description

pSRAM Type 3 currently includes only a 16M bit device, organized as 1M words by 16 bits. It is designed with advanced CMOS technology specified RAM featur- ing low-power static RAM-compatible function and pin configuration. This device operates from a single power supply. Advanced circuit technology provides both high speed and low power. It is automati cally placed in low-power mode when CS1# or both UB# and LB# are asserted high or CS2 is asserted low. There are three control inputs. CS1# and CS2 are used to select the device, and output en- able (OE#) provides fast memory acce ss. Data byte control pins (LB#,UB#) provide lower and upper byte access. This device is well suited to various micro- processor system applications where high speed, low power and battery backup are required. Pin Description A0 – A19 = Address Inputs DQ0 – DQ15 = Data Inputs/Outputs CE1# = Chip Enable CE2 = Deep Power Down OE# = Output Enable WE# = Write Control LB# = Lower Byte Control UB# = Upper Byte Control VCC = Power Supply VSS = Ground

February 25, 2004 pSRAM_Type03_06A0 pSRAM Type 3 109 Advance Information Operation Mode Note: X = don’t care. H = logic high. L = logic low. Absolute Maximum Ratings (see Note) Note: Absolute maximum DC requirements contains stress ratings only. Functional operation at the absolute maximum limits is not implied or guaranteed. Extended exposure to maximum ratings may affect device reliability. DC Characteristics Notes: 1. Overshoot: V CC + 2.0V in case of pulse width ≤ 20ns 2. Undershoot: -2.0V in case of pulse width ≤ 20ns 3. Overshoot and undershoot are sampled, not 100% tested. MODE CE1# CE2 OE# WE# LB# UB# DQ0 to DQ7 DQ8 to DQ15 POWER Deselect H H X X X X High-Z High-Z Standby Deselect X L X X X X High-Z High-Z Deep Power Down Deselect L H X X H H High-Z High-Z Standby Output Disabled L H H H L X High-Z High-Z Active Output Disabled L H H H X L High-Z High-Z Active Lower Byte Read L H L H L H D-out High-Z Active Upper Byte Read L H L H H L High-Z D-out Active Word Read L H L H L L D-out D-out Active Lower Byte Write L H X L L H D-in High-Z Active Upper Byte Write L H X L H L High-Z D-in Active Word Write L H X L L L D-in D-in Active SYMBOL RATING VALUE UNIT VCC Supply Voltage -0.2 to +3.6 V VIN Input Voltages -0.2 to VCC + 0.3 V VIN, VOUT Output and output Voltages -2.0 to +3.6 V ISH Output short circuit current 100 mA PD Power Dissipation 1 W Ta bl e 3 0 . DC Recommended Operating Conditions SYMBOL PARAMETER MIN TYP . MAX UNIT VDD Power Supply Voltage 2.7 3.0 3.3 V VSS Ground 0 - 0 VIH Input High Voltage 2.2 - VCC + 0.2 (Note 1) VIL Input Low Voltage -0.2 (Note 2) - +0.6

Table 31. DC Characteristics (TA = -25°C to 85°C, VDD = 2.6 to 3.3V)

Figure 33. AC Test Loads

116 pSRAM Type 4 pSRAM_Type04_18A0 August 30, 2004 Advance Information pSRAM T ype 4

4 Mbit (256K x 16)

Wide voltage range: 2.7V to 3.3V Typical active current: 3 mA @ f = 1 MHz Low standby power Automatic power-down when deselected Functional Description The Type 4 pSRAM is a high-performance CMOS pseudo static RAM (pSRAM) or- ganized as 256K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. The device can be put into standby mode reducing power consumption dramatically when deselected (CE1# Low, CE2 High or both BHE# and BLE# are High). The input/output pins (I/O0 through I/O15) are placed in a high-imped ance state when: deselected (CE1# High, CE2 Low, OE# is deasserted High), or during a write operation (Chip Enabled and Write Enable WE# Low). Reading from the device is accomplished by asserting the Chip Enables (CE1# Low and CE2 High) and Output Enable (OE#) Low while forcing the Write Enable (WE#) High. If Byte Low Enable (BLE#) is Low, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE#) is Low, then data from memory will appear on I/O8 to I/O15. See Table 37 for a complete description of read and write modes. Product Portfolio Notes: 1. Typical values are included for reference only and are no t guaranteed or tested. Typical values are measured at V CC = VCC (typ) and TA = 25°C. VCC Range (V) Speed (ns) Power Dissipation Operating, ICC (mA) Standby (ISB2) (µA)f = 1 MHz f = fmax Min Ty p Max Ty p . ( n o t e 1 )Max Ty p . ( n o t e 1 )Max Ty p. ( n o te 1 )Max 2.7V 3.0V 3.3V 70 ns 3 5 TBD 25 mA 15 40

August 30, 2004 pSRAM_Type04_18A0 pSRAM Type 4 117 Advance Information Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested) DC Voltage Applied to Outputs in High-Z Notes: 1. V IH(MAX) = VCC + 0.5V for pulse durations less than 20 ns. 2. V IL(MIN) = –0.5V for pulse durations less than 20 ns. 3. Overshoot and undershoot specifications are characterized and are not 100% tested. Operating Range Table 35 . DC Electrical Characteristics (Over the Operating Range) Notes: 1. Typical values are included for reference only and are no t guaranteed or tested. Typical values are measured at V CC = VCC(typ.), TA = 25°C. Ambient T emperature (TA) VCC -25°C to +85°C 2.7V to 3.3V Parameter Description Test Conditions Min. Typ. (note 1) Max Unit VCC Supply Voltage 2.7 3.3 V VOH Output High Voltage I OH = –1.0 mA V CC - 0.4 VOL Output Low Voltage I OL = 0.1 mA 0.4 VIH Input High Voltage 0.8 * V CC VCC + 0.4 VIL Input Low Voltage F = 0 -0.4 0.4 IIX Input Leakage Current GND ≤ VIN ≤ VCC -1 +1 µA IOZ Output Leakage Current GND ≤ VOUT ≤ VCC, Output Disabled -1 +1 ICC VCC Operating Supply Current f = fMAX = 1/tRC VCC = 3.3V IOUT = 0 mA CMOS Levels TBD 15 mA f = 1 MHz 3 ISB1 Automatic CE# Power-Down Current—CMOS Inputs CE# ≥ VCC – 0.2V, CE2 ≤ 0.2V VIN ≥ VCC – 0.2V, VIN ≤ 0.2V, f = fmax (Address and Data Only), f=0 (OE#, WE#, BHE# and BLE#) 250 µA ISB2 Automatic CE# Power-Down Current—CMOS Inputs CE# ≥ V CC – 0.2V, CE2 ≤ 0.2V VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, f = 0, VCC = 3.3V

Note: Tested initially and after any design or process changes that may affect these parameters. Note: Tested initially and after any design or process changes that may affect these parameters. impedance, per EIA / JESD51. Figure 43. AC T est Loads and Waveforms

August 30, 2004 pSRAM_Type04_18A0 pSRAM Type 4 119 Advance Information Ta b l e 3 6 . Switching Characteristics Notes: 1. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of V CC(typ.) /2, input pulse levels of 0 to VCC(typ.), and output loading of the specified I OL/IOH and 30 pF load capacitance. 2. t HZOE, tHZCE, tHZBE and tHZWE transitions are measured when the outputs enter a high-impedance state. 3. High-Z and Low-Z parameters are characterized and are not 100% tested. 4. To achieve 55-ns performance, the read access should be CE# controlled. In this case t ACE is the critical parameter and tSK is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle. 5. The internal write time of the memory is defined by the overlap of WE#, CE#1 = V IL, CE2 = VIH, BHE and/or BLE =VIL. All signals must be Active to initiate a write and any of these signals can terminate a write by going Inactive. The data input set- up and hold timing should be referenced to the edge of the signal that terminates write. Parameter Description Min Max Unit Read Cycle tRC Read Cycle Time 70 ns tAA Address to Data Valid 70 tOHA Data Hold from Address Change 10 tACE CE#1 Low and CE2 High to Data Valid 70 tDOE OE# Low to Data Valid 35 tLZOE OE# Low to Low Z (note 2, 3) 5 tHZOE OE# High to High Z (note 2, 3) 25 tLZCE CE#1 Low and CE2 High to Low Z (note 2, 3) 5 tHZCE CE#1 High and CE2 Low to High Z (note 2, 3) 25 tDBE BHE# / BLE# Low to Data Valid 70 tLZBE BHE# / BLE# Low to Low Z (note 2, 3) 5 tHZBE BHE# / BLE# High to High Z (note 2, 3) 25 tSK (note 4) Address Skew 10 Write Cycle (note 5) tWC Write Cycle Time 70 ns tSCE CE#1 Low an CE2 High to Write End 55 tAW Address Set-Up to Write End 55 tHA Address Hold from Write End 0 tSA Address Set-Up to Write Start 0 tPWE WE# Pulse Width 55 tBW BLE# / BHE# LOW to Write End 55 tSD Data Set-up to Write End 25 tHD Data Hold from Write End 0 tHZWE WE# Low to High Z (note 2, 3) 25 tLZWE WE# High to Low Z (note 2, 3) 5

High-Z and Low-Z parameters are characterized and are not 100% tested.
The internal write time of the memory is defined by the overlap of WE#, CE#1 = V IL, CE2 = VIH, BHE and/or BLE =VIL. All

up and hold timing should be referenced to the edge of the signal that terminates write.

Data I/O is high impedance if OE# ≥ VIH.
If Chip Enable goes Inactive simultaneously with WE# = High, the output remains in a high-impedance state.
During the Don’t Care period in the Data I/O waveform, the I/Os are in output state and input signals should not be applied.

Figure 46. Write Cycle 1 (WE# Controlled)

High-Z and Low-Z parameters are characterized and are not 100% tested.
The internal write time of the memory is defined by the overlap of WE#, CE#1 = V IL, CE2 = VIH, BHE and/or BLE =VIL. All

up and hold timing should be referenced to the edge of the signal that terminates write.

Data I/O is high impedance if OE# ≥ VIH.
If Chip Enable goes Inactive simultaneously with WE# = High, the output remains in a high-impedance state.
During the Don’t Care period in the Data I/O waveform, the I/Os are in output state and input signals should not be applied.

Figure 47. Write Cycle 2 (CE#1 or CE2 Controlled)

124 pSRAM Type 4 pSRAM_Type04_18A0 August 30, 2004 Advance Information Truth T able Ta b l e 3 7 . Truth T able CE#1 CE2 WE# OE# BHE# BLE# Inputs / Outputs Mode Power HXX X XX H i g h - Z Deselect/Power-Down Standby (I SB)XL X X XX H i g h - Z XX X X HH H i g h - Z L H H L L L Data Out (I/O0–I/O15) Read (Upper Byte and Lower Byte) Active (ICC) LH H L HL Data Out (I/O0 –I/O7); I/O8–I/O15 in High Z Read (Upper Byte only) LH H L LH Data Out (I/O8–I/O15); I/O0–I/O7 in High Z Read (Lower Byte only) L H H H L L High-Z Output Disabled L H H H H L High-Z Output Disabled LH H H LH H i g h - Z O u t p u t D i s a b l e d L H L X L L Data In (I/O0–I/O15) Write (Upper Byte and Lower Byte) LH L X HL Data In (I/O0–I/O7); I/O8–I/O15 in High Z Write (Lower Byte Only) LH L X LH Data In (I/O8–I/O15); I/O0 –I/O7 in High Z Write (Upper Byte Only)

April 26, 2004 pSRAM_Type06_14_A0 pSRAM Type 6 125 Advance Information pSRAM T ype 6 2M Word by 16-bit Cmos Pseudo Static RAM (32M Density) 4M Word by 16-bit Cmos Pseudo Static RAM (64M Density) Single power supply voltage of 2.6 to 3.3 V Direct TTL compatibility for all inputs and outputs Deep power-down mode: Memory cell data invalid Page operation mode: — Page read operation by 8 words Logic compatible with SRAM R/W () pin Standby current — Standby = 70 µA (32M) — Standby = 100 µA (64M) — Deep power-down Standby = 5 µA Access Times Pin Description 32M 64M Access Time 70 ns CE1# Access Time 70 ns OE# Access Time 25 ns Page Access Time 30 ns Pin Name Description A0 to A21 Address Inputs A0 to A2 Page Address Inputs I/O1 to I/O16 Data Inputs/Outputs CE1# Chip Enable Input CE2 Chip select Input WE# Write Enable Input OE# Output Enable Input LB#,UB# Data Byte Control Inputs VDD Power Supply GND Ground NC Not Connection

126 pSRAM Type 6 pSRAM_Type06_14_A0 April 26, 2004 Advance Information Functional Description Legend:L = Low-level Input (VIL), H = High-level Input (VIH), X = VIL or VIH, High-Z = High Impedance. Absolute Maximum Ratings DC Recommended Operating Conditions (T a = -40°C to 85°C) Note: VIH (Max) VDD = 1.0 V with 10 ns pulse width. VIL (Min) -1.0 V with 10 ns pulse width. Mode CE1# CE2 OE# WE# LB# UB# Address I/O1-8 I/O9-16 Power Read (Word) L H L H L L X D OUT DOUT IDDO Read (Lower Byte) L H L H L H X D OUT High-Z I DDO Read (Upper Byte) L H L H H L X High-Z D OUT IDDO Write (Word) L H X L L L X D IN DIN IDDO W r i t e ( L o w e r B y t e ) LHX L L HX D IN Invalid I DDO Write (Upper Byte) L H X L H L X Invalid D IN IDDO Outputs Disabled L H H H X X X High-Z High-Z I DDO Standby H H X X X X X High-Z High-Z I DDO Deep Power-down Standby H L X X X X X High-Z High-Z I DDSD Symbol Rating Value Unit VDD Power Supply Voltage -1.0 to 3.6 V VIN Input Voltage -1.0 to 3.6 V VOUT Output Voltage -1.0 to 3.6 V Topr Operating Temperature -40 to 85 °C Tstrg Storage Temperature -55 to 150 °C PD Power Dissipation 0.6 W IOUT Short Circuit Output Current 50 mA Symbol Parameter Min Ty p Max Unit VDD Power Supply Voltage 2.6 2.75 3.3 VVIH Input High Voltage 2.0 — VDD + 0.3 (Note) VIL Input Low Voltage -0.3 (Note) — 0.4

April 26, 2004 pSRAM_Type06_14_A0 pSRAM Type 6 127 Advance Information DC Characteristics (T a = -40°C to 85°C, VDD = 2.6 to 3.3 V) (See Note 3 to 4) Capacitance (T a = 25°C, f = 1 MHz) Note: This parameter is sampled periodically and is not 100% tested. AC Characteristics and Operating Conditions (T a = -40°C to 85°C, VDD = 2.6 to 3.3 V) (See Note 5 to 11) Symbol Parameter T est Condition Min Ty p. Max Unit IIL Input Leakage Current VIN = 0 V to VDD -1.0 — +1.0 µA ILO Output Leakage Current Output disable, VOUT = 0 V to VDD -1.0 — +1.0 µA VOH Output High Voltage IOH = - 0.5 mA 2.0 ¾ V V VOL Output Low Voltage IOL = 1.0 mA — — 0.4 V IDDO1 Operating Current CE1#= VIL, CE2 = VIH, IOUT = 0 mA, tRC = min ET5UZ8A-43DS — — 40 mA ET5VB5A-43DS — — 50 IDDO2 Page Access Operating Current CE1#= VIL, CE2 = VIH, IOUT = 0 mA Page add. cycling, tRC = min — — 25 mA IDDS Standby Current(MOS) CE1# = VDD - 0.2 V, CE2 = VDD - 0.2 V ET5UZ8A-43DS — — 70 mA ET5VB5A-43DS — — 100 µA IDDSD Deep Power-down Standby Current CE2 = 0.2 V — — 5 µA Symbol Parameter T est Condition Max Unit CIN Input Capacitance VIN = GND 10 pF COUT Output Capacitance VOUT = GND 10 pF Symbol Parameter Min Max Unit tRC Read Cycle Time 70 10000 ns tACC Address Access Time — 70 ns tCO Chip Enable (CE1#) Access Time — 70 ns tOE Output Enable Access Time — 25 ns tBA Data Byte Control Access Time — 25 ns tCOE Chip Enable Low to Output Active 10 — ns tOEE Output Enable Low to Output Active 0 — ns tBE Data Byte Control Low to Output Active 0 — ns tOD Chip Enable High to Output High-Z — 20 ns tODO Output Enable High to Output High-Z — 20 ns tBD Data Byte Control High to Output High-Z — 20 ns

128 pSRAM Type 6 pSRAM_Type06_14_A0 April 26, 2004 Advance Information AC T est Conditions tOH Output Data Hold Time 10 — ns tPM Page Mode Time 70 10000 ns tPC Page Mode Cycle Time 30 — ns tAA Page Mode Address Access Time — 30 ns tAOH Page Mode Output Data Hold Time 10 — ns tWC Write Cycle Time 70 10000 ns tWP Write Pulse Width 50 — ns tCW Chip Enable to End of Write 70 — ns tBW Data Byte Control to End of Write 60 — ns tAW Address Valid to End of Write 60 — ns tAS Address Set-up Time 0 — ns tWR Write Recovery Time 0 — ns tCEH Chip Enable High Pulse Width 10 — ns tWEH Write Enable High Pulse Width 6 — ns tODW WE# Low to Output High-Z — 20 ns tOEW WE# High to Output Active 0 ns tDS Data Set-up Time 30 — ns tDH Data Hold Time 0 — ns tCS CE2 Set-up Time 0 — ns tCH CE2 Hold Time 300 — µs tDPD CE2 Pulse Width 10 — ms tCHC CE2 Hold from CE1# 0 — ns tCHP CE2 Hold from Power On 30 — µs Parameter Condition Output load 30 pF + 1 TTL Gate Input pulse level VDD - 0.2 V, 0.2 V Timing measurements VDD x 0.5 Reference level VDD x 0.5 tR, tF 5 ns Symbol Parameter Min Max Unit

Figure 50. Read Cycle

Figure 51. Page Read Cycle (8 Words Access)

Figure 52. Write Cycle #1 (WE# Controlled) (See Note 8)

134 pSRAM Type 7 pSRAM_Type07_13_A1 November 2, 2004 Advance Information pSRAM T ype 7 CMOS 1M/2M/4M-Word x 16-bit Fast Cycle Random Access Memory with Low Power SRAM Interface 16Mb (1M word x 16-bit) 32Mb (2M word x 16-bit) 64Mb (4M word x 16-bit) Asynchronous SRAM Interface Fast Access Time — tCE = tAA = 60ns max (16M) — tCE = tAA = 65ns max (32M/64M) 8 words Page Access Capability — tPAA = 20ns max (32M/64M) Low Voltage Operating Condition — VDD = +2.7V to +3.1V Wide Operating Temperature — TA = -30°C to +85°C Byte Control by LB and UB Various Power Down modes — Sleep (16M) — Sleep, 4M-bit Partial, or 8M-bit Partial (32M) — Sleep, 8M-bit Partial, or 16M-bit Partial (64M) Pin Description Pin Name Description A21 to A0 Address Input: A19 to A0 for 16M, A20 to A0 for 32M, A21 to A0 for 64M CE1# Chip Enable (Low Active) CE2# Chip Enable (High Active) WE# Write Enable (Low Active) OE# Output Enable (Low Active) UB# Upper Byte Control (Low Active) LB# Lower Byte Control (Low Active) DQ16-9 Upper Byte Data Input/Output DQ8-1 Lower Byte Data Input/Output VDD Power Supply VSS Ground

November 2, 2004 pSRAM_Type07_13_A1 pSRAM Type 7 135 Advance information Functional Description Legend:L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance. Notes: 1. Should not be kept this logic condition longer than 1 ms. Please contact local Spansion representative for the relaxation of 1ms limitation. 2. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the selection of the Power-Down Program, 16M has data retentio n in all modes except Power Down. Refer to Power Down for details. 3. Can be either V IL or VIH but must be valid before Read or Write. Power Down (for 32M, 64M Only) Power Down The Power Down is a low-power idle state controlled by CE2. CE2 Low drives the device in power-down mode and maintain s the low-power idle state as long as CE2 is kept Low. CE2 High resumes the device from power-down mode. These devices have three power-down modes. These can be programmed by series of read/write operation. Each mode has following features. The default state is Sleep and it is the lowest power consumption but all data is lost once CE2 is brought to Low for Power Down. It is not required to program to Sleep mode after power-up. Mode CE2# CE1# WE# OE# LB# UB# A21-0 DQ8-1 DQ16-9 Standby (Deselect) H H X X X X X High-Z High-Z Output Disable (Note 1) HL H H X X Note 3 High-Z High-Z Output Disable (No Read) HL H H Valid High-Z High-Z Read (Upper Byte) H L Valid High-Z Output Valid Read (Lower Byte) L H Valid Output Valid High-Z Read (Word) L L Valid Output Valid Output Valid No Write LH H H Valid Invalid Invalid Write (Upper Byte) H L Valid Invalid Input Valid Write (Lower Byte) L H Valid Input Valid Invalid Write (Word) L L Valid Input Valid Input Valid P o w e r D o w n LXXXXX X H i g h - Z H i g h - Z 32M 64M Mode Retention Data Retention Address Mode Retention Data Retention Address Sleep (default) No N/A Sleep (default) No N/A 4M Partial 4M bit 00000h to 3FFFFh 8M Partial 8M bit 00000h to 7FFFFh 8M Partial 8M bit 00000h to 7FFFFh 16M Partial 16M bit 00000h to FFFFFh

136 pSRAM Type 7 pSRAM_Type07_13_A1 November 2, 2004 Advance Information Power Down Program Sequence The program requires 6 read/write operations with a unique address. Between each read/write operation requires that device be in standby mode. The following table shows the detail sequence. The first cycle reads from the most significant address (MSB). The second and third cycle are to write back the data (RDa) read by first cycle. If the second or third cycle is written in to the different address, the program is cancelled, and the data written by the second or third cycle is valid as a normal write operation. The fourth and fifth cycles write to MSB. The data from the fourth and fifth cycles is “don’t care.” If the fourth or fifth cycles are written into different address, the program is also cancelled but write data might not be written as normal write operation. The last cycle is to read from specific address key for mode selection. Once this program sequence is performed from a Partial mode to the other Partial mode, the written data stored in memory cell array can be lost. So, it should per form this program prior to regular read/write operation if Partial mode is used. Address Key The address key has following format. Cycle # Operation Address Data 1st Read 3FFFFFh (MSB) Read Data (RDa) 2nd Write 3FFFFFh RDa 3rd Write 3FFFFFh RDa 4th Write 3FFFFFh Don’t Care (X) 5th Write 3FFFFFh X 6th Read Address Key Read Data (RDb) Mode Address 32M 64M A21 A20 A19 A18 - A0 Binary Sleep (default) Sleep (default) 1 1 1 1 3FFFFFh 4M Partial N/A 1 1 0 1 37FFFFh 8M Partial 8M Partial 1 0 1 1 2FFFFFh N/A 16M Partial 1 0 0 1 27FFFFh

November 2, 2004 pSRAM_Type07_13_A1 pSRAM Type 7 137 Advance information Absolute Maximum Ratings WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions (See Warning Below) Notes: 1. Maximum DC voltage on input and I/O pins is V DD+0.2V. During voltage transitions, inputs can positive overshoot to VDD+1.0V for periods of up to 5 ns. 2. Minimum DC voltage on input or I/O pins is -0.3V. During voltage transitions, inputs can negative overshoot V SS to -1.0V for periods of up to 5ns. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the de- vice’s electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges can adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative before- hand. Package Capacitance Test conditions: TA = 25°C, f = 1.0 MHz Item Symbol Value Unit Voltage of VDD Supply Relative to VSS VDD -0.5 to +3.6 V Voltage at Any Pin Relative to VSS VIN, VOUT -0.5 to +3.6 V Short Circuit Output Current IOUT ±50 mA Storage temperature TSTG -55 to +125 °C Parameter Symbol Min Max Unit Supply Voltage VDD 2.7 3.1 V VSS 0 0 V High Level Input Voltage (Note 1) VIH VDD 0.8 VDD+0.2 V High Level Input Voltage (Note 1) VIL -0.3 VDD 0.2 V Ambient Temperature TA -30 85 °C Symbol Description Te s t S e t u p Ty p Max Unit CIN1 Address Input Capacitance VIN = 0V — 5 pF CIN2 Control Input Capacitance VIN = 0V — 5 pF CIO Data Input/Output Capacitance VIO = 0V — 8 pF

138 pSRAM Type 7 pSRAM_Type07_13_A1 November 2, 2004 Advance Information DC Characteristics (Under Recommended Conditions Unless Otherwise Noted) Notes: 1. All voltages are referenced to V SS. 2. DC Characteristics are measured after following POWER-UP timing. 3. I OUT depends on the output load conditions. Parameter Symbol T est Conditions 16M 32M 64M Input Leakage Output Leakage Output High Voltage Level VOH VDD = VDD(min), IOH = –0.5mA 2.2 — 2.4 — 2.4 — V Output Low Voltage Level VOL IOL = 1mA — 0.4 — 0.4 — 0.4 V VDD Power Down Current IDDPS VDD = VDD max., VIN = VIH or VIL, CE2 ≤ 0.2 V SLEEP 10 — 10 — 10 µA IDDP4 4M Partial N/A — 40 N/A µA IDDP8 8M Partial N/A — 50 — 80 µA IDDP16 16M Partial N/A N/A — 100 µA VDD Standby Current IDDS VDD = VDD max., VIN = VIH or VIL CE1 = CE2 = VIH — 1 — 1.5 — 1.5 mA IDDS1 VDD = VDD max., VIN ≤ 0.2V or VIN ≥ VDD – 0.2V, CE1 = CE2 ≥ VDD – 0.2V TA< +85°C — 100 — 80 — 170 µA TA< +40°C 90 µA VDD Active Current IDDA1 VDD = VDD max., VIN = VIH or VIL, CE1 = VIL and CE2= VIH, IOUT=0mA tRC / tWC = min. — 20 — 30 — 40 mA IDDA2 tRC / tWC = 1µs — 3 — 3 — 5 mA VDD Page Read Current IDDA3 VDD = VDD max., VIN = VIH or VIL, CE1 = VIL and CE2= VIH, IOUT=0mA, tPRC = min. N/A — 10 — 10 mA

November 2, 2004 pSRAM_Type07_13_A1 pSRAM Type 7 139 Advance information AC Characteristics (Under Recommended Operating Conditions Unless Otherwise Noted) Read Operation Notes: 1. Maximum value is applicable if CE#1 is kept at Low without change of address input of A3 to A21. If needed by system operation, please contact local Spansion representative for the relaxation of 1µs limitation. 2. Address should not be changed within minimum t RC. 3. The output load 50 pF with 50 ohm termination to V DD x 0.5 (16M), The output load 50 pF (32M and 64M). 4. The output load 5pF. 5. Applicable to A3 to A21 (32M and 64M) when CE1# is kept at Low. 6. Applicable only to A0, A1 and A2 (32M and 64M) when CE1# is kept at Low for the page address access. 7. In case Page Read Cycle is continued with keeping CE1# stays Low, CE1# must be brought to High within 4 µs. In other words, Page Read Cycle must be closed within 4 µs. 8. Applicable when at least two of address inputs among applicable are switched from previous state. 9. t RC(min) and tPRC(min) must be satisfied. 10. If actual value of tWHOL is shorter than specified minimum values, the actual tAA of following Read can become longer by the amount of subtracting the actual value from the specified minimum value. Parameter Symbol 16M 32M 64M Unit Notes Read Cycle Time t RC 70 1000 65 1000 65 1000 ns 1, 2 CE1# Access Time t CE —6 0—6 5—6 5 n s3 OE# Access Time t OE —4 0—4 0—4 0 n s3 Address Access Time t AA —6 0—6 5—6 5 n s 3 , 5 LB# / UB# Access Time t BA —3 0—3 0—3 0 n s3 Page Address Access Time t PAA N/A — 20 — 20 ns 3,6 Page Read Cycle Time t PRC N/A 20 1000 20 1000 ns 1, 6, 7 Output Data Hold Time t OH 5—5—5— n s 3 CE1# Low to Output Low-Z t CLZ 5—5—5— n s 4 OE# Low to Output Low-Z t OLZ 0—0—0— n s 4 LB# / UB# Low to Output Low-Z t BLZ 0—0—0— n s 4 CE1# High to Output High-Z t CHZ —2 0—2 0—2 0 n s3 OE# High to Output High-Z t OHZ —2 0—1 4—1 4 n s3 LB# / UB# High to Output High-Z t BHZ —2 0—2 0—2 0 n s3 Address Setup Time to CE1# Low t ASC −6—– 6—– 6— n s Address Setup Time to OE# Low t ASO 10 — 10 — 10 — ns Address Invalid Time t AX —1 0—1 0—1 0 n s 5 , 8 Address Hold Time from CE1# High t CHAH -6 — –6 — –6 — ns 9 Address Hold Time from OE# High t OHAH -6 — –6 — –6 — ns WE# High to OE# Low Time for Read t WHOL 10 1000 12 — 25 — ns 10 CE1# High Pulse Width t CP 10 — 12 — 12 — ns

140 pSRAM Type 7 pSRAM_Type07_13_A1 November 2, 2004 Advance Information AC Characteristics Write Operation Notes: 1. Maximum value is applicable if CE1# is kept at Low without any address change. If the relaxation is needed by system operation, please contact local Spansion representative for the relaxation of 1µs limitation. 2. Minimum value must be equal or greater than the sum of write pulse (t CW, tWP or tBW) and write recovery time (tWR). 3. Write pulse is defined from High to Low transition of CE1#, WE#, or LB#/UB#, whichever occurs last. 4. Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1# or WE# whichever occurs last. 5. Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1# or WE# whichever occurs first. 6. Write recovery is defined from Low to High transition of CE1#, WE#, or LB#/UB#, whichever occurs first. 7. t WPH minimum is absolute minimum value for device to detect High level. And it is defined at minimum V IH level. 8. If OE# is Low after minimum t OHCL, read cycle is initiated. In other words, OE# must be brought to High within 5ns after CE1# is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum t RC is met. 9. If OE# is Low after new address input, read cycle is initiated. In other word, OE# must be brought to High at the same time or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum tRC is met and data bus is in High-Z. Parameter Symbol 16M 32M 64M Unit Notes Write Cycle Time t WC 70 1000 65 1000 65 1000 ns 1,2 Address Setup Time t AS 0—0—0— n s3 CE1# Write Pulse Width t CW 45 — 40 — 40 — ns 3 WE# Write Pulse Width t WP 45 — 40 — 40 — ns 3 LB#/UB# Write Pulse Width t BW 45 — 40 — 40 — ns 3 LB#/UB# Byte Mask Setup Time t BS -5 — –5 — –5 — ns 4 LB#/UB# Byte Mask Hold Time t BH -5 — –5 — –5 — ns 5 Write Recovery Time t WR 0—0—0— n s6 CE1# High Pulse Width t CP 10 — 12 — 12 — ns WE# High Pulse Width t WHP 7.5 1000 7.5 1000 7.5 1000 ns 7 LB#/UB# High Pulse Width t BHP 10 1000 12 1000 12 1000 ns Data Setup Time t DS 15 — 12 — 12 — ns Data Hold Time t DH 0—0—0— n s OE# High to CE1# Low Setup Time for Write t OHCL -5 — –5 — –5 — ns 8 OE# High to Address Setup Time for Write t OES 0—0—0— n s9 LB# and UB# Write Pulse Overlap t BWO 30 — 30 — 30 — ns

November 2, 2004 pSRAM_Type07_13_A1 pSRAM Type 7 141 Advance information AC Characteristics Power Down Parameters Notes: 1. Applicable also to power-up. 2. Applicable when 4Mb and 8Mb Partial modes are programmed. Other Timing Parameters Notes: 1. Some data might be written into any address location if t CHWX(min) is not satisfied. 2. The Input Transition Time (t T) at AC testing is 5ns as shown in below. If actual tT is longer than 5ns, it can violate the AC specification of some of the timing parameters. Parameter Symbol 16M 32M 64M CE2 Low Setup Time for Power Down Entry tCSP 10 — 10 — 10 — ns CE2 Low Hold Time after Power Down Entry tC2LP 80 — 65 — 65 — ns CE1# High Hold Time following CE2 High after Power Down Exit [SLEEP mode only] tCHH 300 — 300 — 300 — µs 1 CE1# High Hold Time following CE2 High after Power Down Exit [not in SLEEP mode] tCHHP N/A 1 — 1 — µs 2 CE1# High Setup Time following CE2 High after Power Down Exit tCHS 0 — 0 — 0 — ns 1 Parameter Symbol 16M 32M 64M CE1# High to OE# Invalid Time for Standby Entry tCHOX 10 — 10 — 10 — ns CE1# High to WE# Invalid Time for Standby Entry tCHWX 10 — 10 — 10 — ns 1 CE2 Low Hold Time after Power-up tC2LH 50 — 50 — 50 — µs CE1# High Hold Time following CE2 High after Power-up tCHH 300 — 300 — 300 — µs Input Transition Time tT 1 25 1 25 1 25 ns 2

152 SRAM SRAM_Type01_02A0 June 15, 2004

Process Technology: Full CMOS Power Supply Voltage: 2.7~3.3V Three state outputs Notes: 1. UB#, LB# swapping is available only at x16. x8 or x16 select by BYTE# pin. Pin Description Version Density Organization (ISB1, Max.) Standby (ICC2, Max.) Operating Mode F 4Mb x8 or x16 (note 1) 10 µA 22 mA Dual CS, UB# / LB# (tCS) G 4Mb x8 or x16 (note 1) 10 µA 22 mA Dual CS, UB# / LB# (tCS) C 8Mb x8 or x16 (note 1) 15 µA 22 mA Dual CS, UB# / LB# (tCS) D 8Mb X16 TBD TBD Dual CS, UB# / LB# (tCS) Pin Name Description I/O CS1#, CS2 Chip Selects I OE# Output Enable I WE# Write Enable I BYTE# Word (VCC)/Byte (VSS) Select I A0~A17 (4M) A0~A18 (8M) Address Inputs I SA Address Input for Byte Mode I I/O0~I/O15 Data Inputs/Outputs I/O VCC Power Supply - VSS Ground - DNU Do Not Use - NC No Connection -

June 15, 2004 SRAM_Type01_02A0 SRAM 153 Advance Information Functional Description 4M Version F, 4M version G, 8M version C Note: X means don’t care (must be low or high state). Byte Mode CS1# CS2 OE# WE# BYTE# SA LB# UB# IO0~7 IO8~15 Mode Power H X X X X X X X High-Z High-Z Deselected Standby X L X X X X X X High-Z High-Z Deselected Standby X X X X X X H H High-Z High-Z Deselected Standby L H H H VCC X L X High-Z High-Z Output Disabled Active L H H H VCC X X L High-Z High-Z Output Disabled Active L H L H VCC X L H Dout High-Z Lower Byte Read Active L H L H VCC X H L High-Z Dout Upper Byte Read Active L H L H VCC X L L Dout Dout Word Read Active L H X L VCC X L H Din High-Z Lower Byte Write Active L H X L VCC X H L High-Z Din Upper Byte Write Active L H X L VCC X L L Din Din Word Write Active CS1# CS2 OE# WE# BYTE# SA LB# UB# IO0~7 IO8~15 Mode Power H X X X X X X X High-Z High-Z Deselected Standby X L X X X X X X High-Z High-Z Deselected Standby L H H H X X H H High-Z High-Z Deselected Standby L H L L VCC X L X High-Z High-Z Output Disabled Active L H X L VCC X X L High-Z High-Z Output Disabled Active

154 SRAM SRAM_Type01_02A0 June 15, 2004

Note: X means don’t care (must be low or high state). Absolute Maximum Ratings (4M Version F) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Absolute Maximum Ratings (4M Version G, 8M Version C, 8M Version D) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CS1# CS2 OE# WE# LB# UB# IO0~8 IO9~16 Mode Power H X X X X X High-Z High-Z Deselected Standby X L X X X X High-Z High-Z Deselected Standby X X X X H H High-Z High-Z Deselected Standby L H H H L X High-Z High-Z Output Disabled Active L H H H X L High-Z High-Z Output Disabled Active L H L H L H Dout High-Z Lower Byte Read Active L H L H H L High-Z Dout Upper Byte Read Active L H L H L L Dout Dout Word Read Active L H X L L H Din High-Z Lower Byte Write Active L H X L H L High-Z Din Upper Byte Write Active L H X L L L Din Din Word Write Active Item Symbol Ratings Unit Voltage on any pin relative to VSS VIN,VOUT -0.2 to VCC+0.3V V Voltage on VCC supply relative to VSS VCC -0.2 to 4.0V V Power Dissipation PD 1.0 W Operating Temperature TA -40 to 85 °C Item Symbol Ratings Unit Voltage on any pin relative to VSS VIN,VOUT -0.2 to VCC+0.3V (Max. 3.6V) V Voltage on VCC supply relative to VSS VCC -0.2 to 3.6V V Power Dissipation PD 1.0 W Operating Temperature TA -40 to 85 °C

June 15, 2004 SRAM_Type01_02A0 SRAM 155 Advance Information DC Characteristics Recommended DC Operating Conditions (Note 1) Notes: 1. T A = -40 to 85°C, unless otherwise specified. 2. Overshoot: Vcc+1.0V in case of pulse width ≤20ns. 3. Undershoot: -1.0V in case of pulse width ≤20ns. 4. Overshoot and undershoot are sampled, not 100% tested. Capacitance (f=1MHz, TA=25°C) Note: Capacitance is sampled, not 100% tested DC Operating Characteristics Common Item Symbol Min Ty p Max Unit Supply voltage VCC 2.7 3.0 3.3 V Ground VSS 0 0 0 V Input high voltage VIH 2.2 - VCC+0.2 (Note 2) V Input low voltage VIL -0.2 (Note 3) - 0.6 V Item Symbol T est Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF Item Symbol T est Conditions Min Ty p (Note) Max Unit Input leakage current ILI VIN=VSS to VCC -1 - 1 µA Output leakage current ILO CS1#=VIH or CS2=VIL or OE#=VIH or WE#=VIL or LB#=UB#=VIH, VIO=Vss to VCC -1 - 1 µA Output low voltage VOL IOL = 2.1mA - - 0.4 V Output high voltage VOH IOH = -1.0mA 2.4 - - V

156 SRAM SRAM_Type01_02A0 June 15, 2004

DC Operating Characteristics 4M Version F Note: Typical values are not 100% tested. DC Operating Characteristics 4M Version G Note: Typical values are not 100% tested. Item Symbol T est Conditions Min Ty p (Note) Max Unit Average operating current ICC1 Cycle time=1µs, 100% duty, IIO=0mA, CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V, BYTE#=VSS or VCC, VIN ≤ 0.2V or VIN ≥ VCC-0.2V, LB# ≤ 0.2V or/and UB# ≤ 0.2V - - 3 mA ICC2 Cycle time=Min, IIO=0mA, 100% duty, CS1# = VIL, CS2=VIH, BYTE# = VSS or VCC, VIN=VIL or VIH, LB# ≤ 0.2V or/ and UB# ≤ 0.2V - - 22 mA Standby Current (CMOS) ISB1 (Note) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V (CS1# controlled) or CS2 ≤ 0.2V (CS2 controlled), BYTE# = VSS or VCC, Other input =0~VCC - 1.0 (Note) 10 µA Item Symbol T est Conditions Min Ty p (Note) Max Unit Average operating current ICC1 Cycle time=1µs, 100% duty, IIO=0mA, CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V, BYTE#=VSS or VCC, VIN ≤ 0.2V or VIN ≥ VCC-0.2V, LB# ≤ 0.2V or/and UB# ≤ 0.2V - - 4 mA ICC2 Cycle time=Min, IIO=0mA, 100% duty, CS1# = VIL, CS2=VIH, BYTE# = VSS or VCC, VIN=VIL or VIH, LB# ≤ 0.2V or/ and UB# ≤ 0.2V - - 22 mA Standby Current (CMOS) ISB1 (Note) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V (CS1# controlled) or CS2 ≤ 0.2V (CS2 controlled), BYTE# = VSS or VCC, Other input = 0~VCC - 3.0 (Note) 10 µA

June 15, 2004 SRAM_Type01_02A0 SRAM 157 Advance Information DC Operating Characteristics 8M Version C Note: Typical values are not 100% tested. DC Operating Characteristics 8M Version D Note: Typical values are not 100% tested. Item Symbol T est Conditions Min Ty p (Note) Max Unit Average operating current ICC1 Cycle time=1µs, 100% duty, IIO=0mA, CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V, BYTE#=VSS or VCC, VIN ≤ 0.2V or VIN ≥ VCC-0.2V, LB# ≤ 0.2V or/and UB# ≤ 0.2V - - 3 mA ICC2 Cycle time=Min, IIO=0mA, 100% duty, CS1# = VIL, CS2=VIH, BYTE# = VSS or VCC, VIN=VIL or VIH, LB# ≤ 0.2V or/ and UB# ≤ 0.2V - - 22 mA Standby Current (CMOS) ISB1 (Note) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V (CS1# controlled) or CS2 ≤ 0.2V (CS2 controlled), BYTE# = VSS or VCC, Other input = 0~VCC - - 15 µA Item Symbol T est Conditions Min Ty p (Note) Max Unit Average operating current ICC1 Cycle time=1µs, 100% duty, IIO=0mA, CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V, BYTE#=VSS or VCC, VIN ≤ 0.2V or VIN ≥ VCC-0.2V, LB# ≤ 0.2V or/and UB# ≤ 0.2V - - TBD mA ICC2 Cycle time=Min, IIO=0mA, 100% duty, CS1# = VIL, CS2=VIH, BYTE# = VSS or VCC, VIN=VIL or VIH, LB# ≤ 0.2V or/ and UB# ≤ 0.2V - - TBD mA Standby Current (CMOS) ISB1 (Note) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V (CS1# controlled) or CS2 ≤ 0.2V (CS2 controlled), BYTE# = VSS or VCC, Other input = 0~VCC - - TBD µA

158 SRAM SRAM_Type01_02A0 June 15, 2004

Including scope and jig capacitance.

Figure 79. AC Output Load

June 15, 2004 SRAM_Type01_02A0 SRAM 159 Advance Information Data Retention Characteristics (4M Version F) Notes: 2. Typical values are not 100% tested. Write Write cycle time tWC 70 - ns Chip select to end of write tCW 60 - ns Address set-up time tAS 0 - ns Address valid to end of write tAW 60 - ns LB#, UB# valid to end of write tBW 60 - ns Write pulse width tWP 50 - ns Write recovery time tWR 0 - ns Write to output high-Z tWHZ 0 20 ns Data to write time overlap tDW 30 - ns Data hold from write time tDH 0 - ns End write to output low-Z tOW 5 - ns Item Symbol T est Condition Min Ty p Max Unit VCC for data retention VDR CS1# ≥ VCC-0.2V (Note 1), VIN ≥ 0V. BYTE# = VSS or VCC 1.5 - 3.3 V Data retention current IDR VCC=3.0V, CS1# ≥ VCC-0.2V (Note 1), VIN ≥ 0V - 1.0 (Note 2) 10 µA Data retention set-up time tSDR See data retention waveform 0 - - ns Recovery time tRDR tRC - - Parameter List Symbol Speed Bins Units 70ns Min Max

160 SRAM SRAM_Type01_02A0 June 15, 2004

Figure 80. Timing Waveform of Read Cycle(1) (Address Controlled, CS#1=OE#=VIL, CS2=WE#=VIH, UB#

162 SRAM SRAM_Type01_02A0 June 15, 2004

Figure 83. Timing Waveform of Write Cycle(2) (CS# controlled, if BYTE# is Low, Ignore UB#/LB# Timing)

A write occurs during the overlap (t WP) of low CS1# and low WE#. A write begins when CS1# goes low and WE#

measured from the beginning of write to the end of write.

t CW is measured from the CS1# going low to the end of write.
t AS is measured from the address valid to the beginning of write.
t WR is measured from the end of write to the address change. t WR applied in case a write ends as CS1# or WE#

Figure 84. Timing Waveform of Write Cycle(3) (UB#, LB# controlled)

Figure 85. Data Retention Waveform

164 pSRAM Type 1 pSRAM_Type01_12_A0 June 8, 2004 Advance Information pSRAM T ype 1 4Mbit (256K Word x 16-bit) 8Mbit (512K Word x 16-bit) 16Mbit (1M Word x 16-bit) 32Mbit (2M Word x 16-bit) 64Mbit (4M Word x 16-bit) Fast Cycle Times —T ACC < 70 nS —T ACC < 65 nS —T ACC < 60 nS —T ACC < 55 nS Very low standby current —I SB < 120 µA (64M and 32M) —I SB < 100 µA (16M) Very low operating current — Icc < 25mA Functional Description Absolute Maximum Ratings Mode CE# CE2/ZZ# OE# WE# UB# LB# Addresses I/O 1-8 I/O 9-16 Power Read (word) L H L H L L X Dout Dout I ACTIVE Read (lower byte) L H L H H L X Dout High-Z I ACTIVE Read (upper byte) L H L H L H X High-Z Dout I ACTIVE Write (word) L H X L L L X Din Din I ACTIVE Write (lower byte) L H X L H L X Din Invalid I ACTIVE Write (upper byte) L H X L L H X Invalid Din I ACTIVE Outputs disabled L H H H X X X High-Z High-Z I ACTIVE Standby H H X X X X X High-Z High-Z I STANDBY Deep power down H L X X X X X High-Z High-Z I DEEP SLEEP Item Symbol Ratings Units Voltage on any pin relative to VSS Vin, Vout -0.2 to VCC +0.3 V Voltage on VCC relative to VSS VCC -0.2 to 3.6 V Power dissipation PD 1 W Storage temperature TSTG -55 to 150 °C Operating temperature TA -25 to 85 °C

June 8, 2004 pSRAM_Type01_12_A0 pSRAM Type 1 165 Advance Information DC Characteristics (4Mb pSRAM Asynchronous) Asynchronous Performance Grade -70 Density 4Mb pSRAM Symbol Parameter Conditions Min Max Units VCC Power Supply 2.7 3.3 V VIH Input High Level 1.4 Vccq V CC + 0.3 V VIL Input Low Level -0.3 0.4 V IIL Input Leakage Current Vin = 0 to VCC 0.5 µA ILO Output Leakage Current OE = V IH or Chip Disabled 0.5 µA VOH Output High Voltage I OH = -1.0 mA VIOH = -0.2 mA 0.8 Vccq IOH = -0.5 mA VOL Output Low Voltage I OL = 2.0 mA VIOL = 0.2 mA 0.2 IOL = 0.5 mA IACTIVE Operating Current V CC = 3.3 V 25 mA ISTANDBY Standby Current VCC = 3.0 V 70 µA VCC = 3.3 V IDEEP SLEEP Deep Power Down Current xµ A IPAR 1/4 1/4 Array PAR Current xµ A IPAR 1/2 1/2 Array PAR Current xµ A

166 pSRAM Type 1 pSRAM_Type01_12_A0 June 8, 2004 Advance Information DC Characteristics (8Mb pSRAM Asynchronous) Asynchronous Version B C Performance Grade -55 -70 -70 Density 8Mb pSRAM 8Mb pSRAM 8Mb pSRAM Symbol Parameter Conditions Min Max Units Min Max Units Min Max Units IIL Input Leakage Current Vin = 0 to VCC 0.5 µA 0.5 µA 0.5 µA ILO Output Leakage Current OE = V IH or Chip Disabled 0.5 µA 0.5 µA 0.5 µA VOH Output High Voltage IOH = -1.0 mA V CC-0.4 V VCC-0.4 VVIOH = -0.2 mA 0.8 VCCQ IOH = -0.5 mA VOL Output Low Voltage IOL = 2.0 mA 0.4 V 0.4 VVIOL = 0.2 mA 0.2 IOL = 0.5 mA IACTIVE Operating Current V CC = 3.3 V 25 mA 23 mA 25 mA ISTANDBY Standby Current VCC = 3.0 V 60 µA µA µA VCC = 3.3 V IDEEP SLEEP Deep Power Down Current xµ A xµ A x µ A I PAR 1/4 1/4 Array PAR Current xµ A xµ A x µ A IPAR 1/2 1/2 Array PAR Current xµ A xµ A x µ A

June 8, 2004 pSRAM_Type01_12_A0 pSRAM Type 1 167 Advance Information DC Characteristics (16Mb pSRAM Asynchronous) Asynchronous Performance Grade -55 -70 Density 16Mb pSRAM 16Mb pSRAM Symbol Parameter Conditions Minimum Maximum Units Minimum Maximum Units VCC Power Supply 2.7 3.6 V 2.7 3.6 V VIH Input High Level 2.2 V CC + 0.3 V 2.2 V CC + 0.3 V VIL Input Low Level -0.3 0.6 V -0.3 0.6 V IIL Input Leakage Current Vin = 0 to V CC 0.5 µA 0.5 µA ILO Output Leakage Current OE = V IH or Chip Disabled 0.5 µA 0.5 µA VOH Output High Voltage IOH = -1.0 mA V CC-0.4 V VCC-0.4 VIOH = -0.2 mA IOH = -0.5 mA VOL Output Low Voltage IOL = 2.0 mA 0.4 V 0.4 VIOL = 0.2 mA IOL = 0.5 mA IACTIVE Operating Current V CC = 3.3 V 25 mA 23 mA ISTANDBY Standby Current VCC = 3.0 V 100 µA 100 µA VCC = 3.3 V IDEEP SLEEP Deep Power Down Current x µA x µA IPAR 1/4 1/4 Array PAR Current x µA x µA IPAR 1/2 1/2 Array PAR Current x µA x µA

168 pSRAM Type 1 pSRAM_Type01_12_A0 June 8, 2004 Advance Information DC Characteristics (16Mb pSRAM Page Mode) Page Mode Performance Grade -60 -65 -70 Density 16Mb pSRAM 16Mb pSRAM 16Mb pSRAM Symbol Parameter Conditions Min Max Units Min Max Units Min Max Units VIH Input High VIL Input Low I IL Input Leakage Current Vin = 0 to V CC 1µ A 1µ A 1µ A ILO Output Leakage Current OE = V IH or Chip Disabled 1µ A 1µ A 1µ A VOH Output High Voltage I OH = -1.0 mA VV VIOH = -0.2 mA IOH = -0.5 mA 0.8 Vccq 0.8 Vccq 0.8 Vccq VOL Output Low Voltage I OL = 2.0 mA VV VIOL = 0.2 mA IOL = 0.5 mA 0.2 Vccq 0.2 Vccq 0.2 Vccq IACTIVE Operating Current V CC = 3.3 V 25 mA 25 mA 25 mA ISTANDBY Standby Current VCC = 3.0 V µA µA µA VCC = 3.3 V 100 100 100 IDEEP SLEEP Deep Power Down Current 10 µA 10 µA 10 µA I PAR 1/4 1/4 Array PAR Current 65 µA 65 µA 65 µA I PAR 1/2 1/2 Array PAR Current 80 µA 80 µA 80 µA

June 8, 2004 pSRAM_Type01_12_A0 pSRAM Type 1 169 Advance Information DC Characteristics (32Mb pSRAM Page Mode) Page Mode Version C E Performance Grade -65 -60 -65 -70 Density 32Mb pSRAM 32Mb pSRAM 32Mb pSRAM 32Mb pSRAM Symbol Parameter Conditions Min Max Units Min Max Units Min Max Units Min Max Units VCC Power VIH Input High Level 1.4 V CC + 0.2 V0 . 8 V c c q VCC + 0.2 V 0.8 Vccq VCC + 0.2 V 0.8 Vccq VCC 0.2 V VIL Input Low Level -0.2 0.4 V -0.2 0.2 Vccq V- 0 . 2 0.2 Vccq V- 0 . 2 0.2 Vccq V IIL Input Leakage Current Vin = 0 to V CC 0.5 µA 1 µA 1 µA 1 µA ILO Output Leakage Current OE = V IH or Chip Disabled 0.5 µA 1 µA 1 µA 1 µA VOH Output High Voltage IOH = -1.0 mA VVV VIOH = -0.2 mA 0.8 Vccq IOH = -0.5 mA 0.8 Vccq 0.8 Vccq 0.8 Vccq VOL Output Low Voltage I OL = 2.0 mA VVV VIOL = 0.2 mA 0.2 IOL = 0.5 mA 0.2 Vccq 0.2 Vccq 0.2 Vccq IACTIVE Operating Current VCC = 3.3 V 25 mA 25 mA 25 mA 25 mA ISTANDBY Standby Current VCC = 3.0 V µA µA µA µA VCC = 3.3 V 100 120 120 100 IDEEP SLEEP Deep Power Down Current 10 µA 10 µA 10 µA 10 µA IPAR 1/4 1/4 Array PAR Current 65 µA 75 µA 75 µA 65 µA I PAR 1/2 1/2 Array PAR Current 80 µA 90 µA 90 µA 80 µA

170 pSRAM Type 1 pSRAM_Type01_12_A0 June 8, 2004 Advance Information DC Characteristics (64Mb pSRAM Page Mode) Timing T est Conditions Page Mode Performance Grade -70 Density 64Mb pSRAM Symbol Parameter Conditions Min Max Units VCC Power Supply 2.7 3.3 V VIH Input High Level 0.8 Vccq V CC + 0.2 V VIL Input Low Level -0.2 0.2 Vccq V IIL Input Leakage Current Vin = 0 to VCC 1µ A ILO Output Leakage Current OE = V IH or Chip Disabled 1µ A VOH Output High Voltage I OH = -1.0 mA VIOH = -0.2 mA IOH = -0.5 mA 0.8 Vccq VOL Output Low Voltage I OL = 2.0 mA VIOL = 0.2 mA IOL = 0.5 mA 0.2 Vccq IACTIVE Operating Current V CC = 3.3 V 25 mA ISTANDBY Standby Current VCC = 3.0 V µA VCC = 3.3 V 120 IDEEP SLEEP Deep Power Down Current 10 µA IPAR 1/4 1/4 Array PAR Current 65 µA IPAR 1/2 1/2 Array PAR Current 80 µA Item Input Pulse Level 0.1 VCC to 0.9 VCC Input Rise and Fall Time 5ns Input and Output Timing Reference Levels 0.5 VCC Operating Temperature -25°C to +85°C

Figure 86. Output Load Circuit

172 pSRAM Type 1 pSRAM_Type01_12_A0 June 8, 2004 Advance Information AC Characteristics (4Mb pSRAM Page Mode) Asynchronous Performance Grade -70 Density 4Mb pSRAM

3 Volt Symbol Parameter Min Max Units

tba UB#, LB# Access time 70 ns tlz Chip select to Low-z output 10 ns tblz UB#, LB# Enable to Low-Z output 10 ns tolz Output enable to Low-Z output 5n s thz Chip enable to High-Z output 02 0 n s tbhz UB#, LB# disable to High-Z output 02 0 n s tohz Output disable to High-Z output 02 0 n s toh Output hold from Address Change 10 ns

June 8, 2004 pSRAM_Type01_12_A0 pSRAM Type 1 173 Advance Information Write twc Write cycle time 70 ns tcw Chipselect to end of write 70 ns tas Address set up Time 0n s taw Address valid to end of write 70 ns tbw UB#, LB# valid to end of write 70 ns twp Write pulse width 55 ns twr Write recovery time 0n s twhz Write to output High-Z 20 ns tdw Data to write time overlap 25 ns tdh Data hold from write time 0n s tow End write to output Low-Z 5 tow Write high pulse width 7.5 ns Other tpc Page read cycle x tpa Page address access time x twpc Page write cycle x tcp Chip select high pulse width x Asynchronous Performance Grade -70 Density 4Mb pSRAM

174 pSRAM Type 1 pSRAM_Type01_12_A0 June 8, 2004 Advance Information AC Characteristics (8Mb pSRAM Asynchronous) Asynchronous Version B C Performance Grade -55 -70 -70 Density 8Mb pSRAM 8Mb pSRAM 8Mb pSRAM

3 Volt Symbol Parameter Min Max Units Min Max Units Min Max Units

trc Read cycle time 55 ns 70 ns 70 ns taa Address Access Time 55 ns 70 ns 70 ns tco Chip select to output 55 ns 70 ns 70 ns toe Output enable to valid output 30 ns 35 ns 20 ns tba UB#, LB# Access time 55 ns 70 ns 70 ns tlz Chip select to Low-z output 5 ns 5 ns 10 ns tblz UB#, LB# Enable to Low-Z output 5 ns 5 ns 10 ns tolz Output enable to Low-Z output 5n s 5n s 5n s thz Chip enable to High-Z output 02 0 n s02 5 n s02 0 n s tbhz UB#, LB# disable to High-Z output 02 0 n s02 5 n s02 0 n s tohz Output disable to High-Z output 02 0 n s02 5 n s02 0 n s toh Output hold from Address Change 10 ns 10 ns 10 ns

June 8, 2004 pSRAM_Type01_12_A0 pSRAM Type 1 175 Advance Information Write twc Write cycle time 55 ns 70 ns 70 ns tcw Chip select to end of write 45 ns 55 ns 70 ns tas Address set up Time 0n s 0n s 0n s taw Address valid to end of write 45 ns 55 ns 70 ns tbw UB#, LB# valid to end of write 45 ns 55 ns 70 ns t w p W r i t e p u l s e w i d t h 4 5n s 5 5n s 5 5n s twr Write recovery time 0n s 0n s 0n s twhz Write to output High-Z 25 ns 25 20 ns tdw Data to write time overlap 40 ns 40 ns 25 ns tdh Data hold from write time 0n s 0n s 0n s tow End write to output Low-Z 555 tow Write high pulse width x x ns x x ns x x ns Other tpc Page read cycle x x x tpa Page address access time xxx twpc Page write cycle x x x tcp Chip select high pulse width xxx Asynchronous Version B C Performance Grade -55 -70 -70 Density 8Mb pSRAM 8Mb pSRAM 8Mb pSRAM

176 pSRAM Type 1 pSRAM_Type01_12_A0 June 8, 2004 Advance Information AC Characteristics (16Mb pSRAM Asynchronous) Asynchronous Performance Grade -55 -70 Density 16Mb pSRAM 16Mb pSRAM

3 Volt Symbol Parameter Min Max Units Min Max Units

trc Read cycle time 55 ns 70 ns taa Address Access Time 55 ns 70 ns tco Chip select to output 55 ns 70 ns toe Output enable to valid output 30 ns 35 ns tba UB#, LB# Access time 55 ns 70 ns tlz Chip select to Low-z output 5n s 5n s tblz UB#, LB# Enable to Low-Z output 5n s 5n s tolz Output enable to Low-Z output 5n s 5n s thz Chip enable to High-Z output 02 5 n s02 5 n s tbhz UB#, LB# disable to High-Z output 02 5 n s02 5 n s tohz Output disable to High-Z output 02 5 n s02 5 n s toh Output hold from Address Change 10 ns 10 ns

June 8, 2004 pSRAM_Type01_12_A0 pSRAM Type 1 177 Advance Information Write twc Write cycle time 55 ns 70 ns tcw Chipselect to end of write 50 ns 55 ns tas Address set up Time 0n s 0n s taw Address valid to end of write 50 ns 55 ns tbw UB#, LB# valid to end of write 50 ns 55 ns twp Write pulse width 50 ns 55 ns twr Write recovery time 0n s 0n s twhz Write to output High-Z 25 ns 25 ns tdw Data to write time overlap 25 ns 25 ns tdh Data hold from write time 0n s 0n s tow End write to output Low-Z 55 tow Write high pulse width xx n s xx n s Other tpc Page read cycle x x tpa Page address access time xx twpc Page write cycle x x tcp Chip select high pulse width xx Asynchronous Performance Grade -55 -70 Density 16Mb pSRAM 16Mb pSRAM

178 pSRAM Type 1 pSRAM_Type01_12_A0 June 8, 2004 Advance Information AC Characteristics (16Mb pSRAM Page Mode) Page Mode Performance Grade -60 -65 -70 Density 16Mb pSRAM 16Mb pSRAM 16Mb pSRAM trc Read cycle time 60 20k ns 65 20k ns 70 20k ns taa Address Access Time 60 ns 65 ns 70 ns tco Chip select to output 60 ns 65 ns 70 ns toe Output enable to valid output 25 ns 25 ns 25 ns tba UB#, LB# Access time 60 ns 65 ns 70 ns tlz Chip select to Low-z output 10 ns 10 ns 10 ns tblz UB#, LB# Enable to Low-Z output 10 ns 10 ns 10 ns tolz Output enable to Low-Z output 5n s 5n s 5n s thz Chip enable to High-Z output 0 5 ns 0 5 ns 0 5 ns tbhz UB#, LB# disable to High-Z output 0 5 ns 0 5 ns 0 5 ns tohz Output disable to High-Z output 0 5 ns 0 5 ns 0 5 ns toh Output hold from Address Change 5n s 5n s 5n s

June 8, 2004 pSRAM_Type01_12_A0 pSRAM Type 1 179 Advance Information Write twc Write cycle time 60 20k ns 65 20k ns 70 20k ns tcw Chipselect to end of write 50 ns 60 ns 60 ns tas Address set up Time 0n s 0n s 0n s taw Address valid to end of write 50 ns 60 ns 60 ns tbw UB#, LB# valid to end of write 50 ns 60 ns 60 ns t w p W r i t e p u l s e w i d t h 5 0n s 5 0n s 5 0n s twr Write recovery time 0n s 0n s 0n s twhz Write to output High-Z 5n s 5n s 5n s tdw Data to write time overlap 20 ns 20 ns 20 ns tdh Data hold from write time 0n s 0n s 0n s tow End write to output Low-Z 555 tow Write high pulse width 7 . 5n s 7 . 5n s 7 . 5n s Other tpc Page read cycle 25 20k ns 25 20k ns 25 20k ns tpa Page address access time 25 ns 25 ns 25 ns twpc Page write cycle 25 20k ns 25 20k ns 25 20k ns tcp Chip select high pulse width 10 ns 10 ns 10 ns Page Mode Performance Grade -60 -65 -70 Density 16Mb pSRAM 16Mb pSRAM 16Mb pSRAM

180 pSRAM Type 1 pSRAM_Type01_12_A0 June 8, 2004 Advance Information AC Characteristics (32Mb pSRAM Page Mode) Page Mode Version C E Performance Grade -65 -60 -65 -70 Density 32Mb pSRAM 32Mb pSRAM 32Mb pSRAM 32Mb pSRAM

3 Volt Symbol Parameter Min Max Units Min Max Units Min Max Units Min Max Units

trc Read cycle time 65 20k ns 60 20k ns 65 20k ns 70 20k ns taa Address Access Time 65 ns 60 ns 65 ns 70 ns tco Chip select to output 65 ns 60 ns 65 ns 70 ns toe Output enable to valid output 20 ns 25 ns 25 ns 25 ns tba UB#, LB# Access time 65 ns 60 ns 65 ns 70 ns tlz Chip select to Low-z output 10 ns 10 ns 10 ns 10 ns tblz UB#, LB# Enable to Low-Z output 10 ns 10 ns 10 ns 10 ns tolz Output enable to Low-Z output 5 ns 5 ns 5 ns 5 ns thz Chip enable to High-Z output 02 0 n s0 5n s 0 5n s0 5 n s tbhz UB#, LB# disable to High-Z output 02 0 n s0 5n s 0 5n s0 5 n s tohz Output disable to High-Z output 02 0 n s0 5n s 0 5n s0 5 n s toh Output hold from Address Change 5 ns 5 ns 5 ns 5 ns

June 8, 2004 pSRAM_Type01_12_A0 pSRAM Type 1 181 Advance Information Write twc Write cycle time 65 20k ns 60 20k ns 65 20k ns 70 20k ns tcw Chipselect to end of write 55 ns 50 ns 60 ns 60 ns tas Address set up Time 0 ns 0 ns 0 ns 0 ns taw Address valid to end of write 55 ns 50 ns 60 ns 60 ns tbw UB#, LB# valid to end of write 55 ns 50 ns 60 ns 60 ns twp Write pulse width 55 20k ns 50 ns 50 ns 50 ns twr Write recovery time 0 ns 0 ns 0 ns 0 ns twhz Write to output High-Z 5 ns 5 ns 5 ns 5 ns tdw Data to write time overlap 25 ns 20 ns 20 ns 20 ns tdh Data hold from write time 0 ns 0 ns 0 ns 0 ns tow End write to output Low-Z 55 5 5 tow Write high pulse width 7.5 ns 7.5 ns 7.5 ns 7.5 ns Other tpc Page read cycle 25 20k ns 25 20k ns 25 20k ns 25 20k ns tpa Page address access time 25 ns 25 ns 25 ns 25 ns twpc Page write cycle 25 20k ns 25 20k ns 25 20k ns 25 20k ns tcp Chip select high pulse width 10 ns 10 ns 10 ns 10 ns Page Mode Version C E Performance Grade -65 -60 -65 -70 Density 32Mb pSRAM 32Mb pSRAM 32Mb pSRAM 32Mb pSRAM

182 pSRAM Type 1 pSRAM_Type01_12_A0 June 8, 2004 Advance Information AC Characteristics (64Mb pSRAM Page Mode) Page Mode Performance Grade -70 Density 64Mb pSRAM trc Read cycle time 70 20k ns taa Address Access Time 70 ns tco Chip select to output 70 ns toe Output enable to valid output 25 ns tba UB#, LB# Access time 70 ns tlz Chip select to Low-z output 10 ns tblz UB#, LB# Enable to Low-Z output 10 ns tolz Output enable to Low-Z output 5n s thz Chip enable to High-Z output 05 n s tbhz UB#, LB# disable to High-Z output 05 n s tohz Output disable to High-Z output 05 n s toh Output hold from Address Change 5n s

Figure 87. Timing of Read Cycle (CE# = OE# = VIL, WE# = ZZ# = VIH)

Figure 88. Timing Waveform of Read Cycle (WE# = ZZ# = VIH)

Figure 89. Timing Waveform of Page Mode Read Cycle (WE# = ZZ# = VIH)

Figure 92. Timing Waveform of Page Mode Write Cycle (ZZ# = VIH)

188 pSRAM Type 1 pSRAM_Type01_12_A0 June 8, 2004 Advance Information Power Savings Modes (For 16M Page Mode, 32M and 64M Only) There are several power savings modes. Partial Array Self Refresh Temperature Compensated Refresh (64M) Deep Sleep Mode Reduced Memory Size (32M, 16M) The operation of the power saving modes ins controlled by the settings of bits contained in the Mode Register. This definition of the Mode Register is shown in Figure 93 and the various bits are used to enable and disable the various low power modes as well as enabling Page Mode operation. The Mode Register is set by using the timings defined in Figure xxx. Partial Array Self Refresh (PAR) In this mode of operation, the internal refresh operation can be restricted to a 16Mb, 32Mb, or 48Mb portion of the array. The array partition to be refreshed is determined by the respective bit settings in the Mode Register. The register set tings for the PASR operation are defined in Table xxx. In this PASR mode, when ZZ# is active low, only the portion of the array that is set in the register is re freshed. The data in the remainder of the array will be lost. The PASR operation mode is only available during standby time (ZZ# low) and once ZZ# is returned high, the device resumes full array refresh. All future PASR cycles will use the contents of the Mode Register that has been previously set. To change the ad dress space of the PASR mode, the Mode Register must be reset using the previously defined procedures. For PASR to be activated, the register bit, A4Must be set to a one (1) value, “PASR Enabled”. If this is the case, PASR will be acti- vated 10 µs after ZZ# is brought low. If the A4 register bit is set equal to zero (0), PASR will not be activated. T emperature Compensated Refresh (for 64Mb) In this mode of operation, the internal refresh rate can be optimized for the op- eration temperature used and this can then lower standby current. The DRAM array in the PSRAM must be refreshed internally on a regular basis. At higher temperatures, the DRAM cell must be refreshed more often than at lower tem - peratures. By setting the temperature of operation in the Mode Register, this refresh rate can be optimized to yield the lowest standby current at the given op erating temperature. There are four diff erent temperature settings that can be programmed in to the PSRAM. These are defined in Figure 93. Deep Sleep Mode In this mode of operation, the internal refresh is turned off and all data integrity of the array is lost. Deep Sleep is entered by bringing ZZ# low with the A4 reg- ister bit set to a zero (0), “Deep Sleep Enabled”. If this is the case, Deep Sleep will be entered 10 µs after ZZ# is brought low. The device will remain in this mode as long as ZZ# remains low. If the A4 register bit is set equal to one (1), Deep Sleep will not be activated. Reduced Memory Size (for 32M and 16M) In this mode of operation, the 32Mb PSRAM can be operated as a 8Mb or 16Mb device. The mode and array size are determined by the settings in the VA register. The VA register is set according to the fo llowing timings and the bit settings in the table “Address Patterns for RMS”. The RMS mode is enabled at the time of ZZ

portion of the array may not be used. Figure 93. Mode Register

64 Mb 32 Mb / 16 Mb

June 8, 2004 pSRAM_Type01_12_A0 pSRAM Type 1 191 Advance Information Mode Register Update and Deep Sleep Timings Notes: 1. Minimum cycle time for writing register is equal to speed grade of product. Address Patterns for PASR (A4=1) (64M) Item Symbol Min Max Unit Note Chip deselect to ZZ# low tCDZZ 5 ns ZZ# low to WE# low tZZWE 10 500 ns Write register cycle time tWC 70/85 ns 1 Chip enable to end of write tCW 70/85 ns 1 Address valid to end of write tAW 70/85 ns 1 Write recovery time tWR 0 ns Address setup time tAS 0 ns Write pulse width tWR 40 ns Deep Sleep Pulse Width tZZMIN 10 µs Deep Sleep Recovery tR 150 µs A2 A1 A0 Active Section Address Space Size Density 1 1 1 Top quarter of die 300000h-3FFFFFh 1Mb x 16 16Mb 1 1 0 Top half of die 200000h-3FFFFFh 2Mb x 16 32Mb 1 0 1 Reserved 1 0 0 No PASR None 0 0 0 1 1 Bottom quarter of die 000000h-0FFFFFh 1Mb x 16 16Mb 0 1 0 Bottom half of die 000000h-1FFFFFh 2Mb x 16 32Mb 0 0 1 Reserved 0 0 0 Full array 000000h-3FFFFFh 4Mb x 16 64Mb

192 pSRAM Type 1 pSRAM_Type01_12_A0 June 8, 2004 Advance Information Deep ICC Characteristics (for 64Mb) Address Patterns for PAR (A3= 0, A4=1) (32M) Address Patterns for RMS (A3 = 1, A4 = 1) (32M) Item Symbol Te s t Array Partition Ty p Max Unit PASR Mode Standby Current IPASR VIN = VCC or 0V, Chip Disabled, tA = 85°C None 10 µA 1/4 Array 75 1/2 Array 90 Full Array 120 Item Symbol Max T emperature Ty p Max Unit Temperature Compensated Refresh Current ITCR 15°C 50 µA 45°C 60 70°C 80 85°C 120 Item Symbol Te s t Ty p Max Unit Deep Sleep Current IZZ VIN = VCC or 0V, Chip in ZZ# mode, tA = 25°C 10 µA A2 A1 A0 Active Section Address Space Size Density 0 1 1 One-quarter of die 000000h - 07FFFFh 512Kb x 16 8Mb 0 1 0 One-half of die 000000h - 0FFFFFh 1Mb x 16 16Mb x 0 0 Full die 000000h - 1FFFFFh 2Mb x 16 32Mb 1 1 1 One-quarter of die 180000h - 1FFFFFh 512Kb x 16 8Mb 1 1 0 One-half of die 100000h - 1FFFFFh 1Mb x 16 16Mb A2 A1 A0 Active Section Address Space Size Density 0 1 1 One-quarter of die 000000h - 07FFFFh 512Kb x 16 8Mb 0 1 0 One-half of die 000000h - 0FFFFFh 1Mb x 16 16Mb 1 1 1 One-quarter of die 180000h - 1FFFFFh 512Kb x 16 8Mb 1 1 0 One-half of die 100000h - 1FFFFFh 1Mb x 16 16Mb

June 8, 2004 pSRAM_Type01_12_A0 pSRAM Type 1 193 Advance Information Low Power ICC Characteristics (32M) Address Patterns for PAR (A3= 0, A4=1) (16M) Address Patterns for RMS (A3 = 1, A4 = 1) (16M) Low Power ICC Characteristics (16M) Item Symbol Te s t Array Partition Ty p Max Unit PAR Mode Standby Current IPAR VIN = VCC or 0V, Chip Disabled, tA= 85 o C 1/4 Array 65 µA 1/2 Array 80 µA RMS Mode Standby Current IRMSSB VIN = VCC or 0V, Chip Disabled, tA= 85 o C 4Mb Device 40 µA 8Mb Device 50 µA Deep Sleep Current IZZ VIN = VCC or 0V, Chip in ZZ mode, tA= 85 o C 10 µA A2 A1 A0 Active Section Address Space Size Density 0 1 1 One-quarter of die 00000h - 0FFFFh 256Kb x 16 4Mb 0 1 0 One-half of die 00000h - 7FFFFh 512Kb x 16 8Mb x 0 0 Full die 00000h - FFFFFh 1Mb x 16 162Mb 1 1 1 One-quarter of die C0000h - FFFFh 256Kb x 16 4Mb 1 1 0 One-half of die 80000h - 1FFFFFh 512Kb x 16 8Mb A2 A1 A0 Active Section Address Space Size Density 0 1 1 One-quarter of die 00000h - 0FFFFh 256Kb x 16 4Mb 0 1 0 One-half of die 00000h - 7FFFFh 512Kb x 16 8Mb 1 1 1 One-quarter of die C0000h - FFFFFh 256Kb x 16 4Mb 1 1 0 One-half of die 80000h - FFFFFh 512Kb x 16 8Mb Item Symbol Te s t Array Partition Ty p Max Unit PAR Mode Standby Current IPAR VIN = VCC or 0V, Chip Disabled, tA= 85 o C 1/4 Array 65 µA 1/2 Array 80 RMS Mode Standby Current IRMSSB VIN = VCC or 0V, Chip Disabled, tA= 85 o C 4Mb Device 40 µA 8Mb Device 50 Deep Sleep Current IZZ VIN = VCC or 0V, Chip in ZZ# mode, tA= 85 o C 10 µA

Revision A (May 3, 2004) Initial release. Revision A1 (May 6, 2004) MCP Features Corrected the high performance access times. Connection Diagrams Added reference points on all diagrams. Corrected package types. Corrected the description of product family to Page Mode Flash memory. pSRAM Type 1 Corrected the description of the 8Mb device to 512Kb Word x 16-bit. pSRAM Type 6 Corrected the description of the 2Mb device to 128Kb Word x 16-bit. Corrected the description of the 4Mb device to 256Kb Word x 16-bit. Revision A2 (May 11, 2004) General Description Corrected the tables to reflect accurate device configurations. Revision A3 (June 16, 2004) Corrected the Valid Combinations tables to reflect accurate device configurations. SRAM New section added. Revision A4 (July 16, 2004) Global Changes Global Change of FASL to Spansion. Global change to remove space between M and Mb callouts. “32Mb Flash Memory” on page 2 Replaced “S71PL032J08-07” with “S71PL032J08-0B”. Replaced “S71PL032JA0” with “S71PL032JA0-07”. Added row with the following content: S71PL032JA0-08; 65; 16Mb pSRAM; 70; pSRAM3; TLC056. “64Mb Flash Memory” on page 2 Replaced “S71PL064J08-0K” with “S71PL064J08-0B”. Replaced “S71PL064J08-0P” with “S71PL064J08-0U”. Deleted “S71PL064J80-05” row. Replaced “S71PL064JA0-07” with “S71PL064JA0-0K”.

November 22, 2004 S71PL254/127/064/032J_00_A6 Revision Summary 195 Advance Information Replaced “S71PL064JA0-0Z” with Added row with the following content:S71PL064JB0-07; 65; 32M pSRAM; 70; Psram 1; TLC056. “32Mb Flash Memory” on page 2 Replaced “S71PL032JA0-08” with “S71PL032JA0-0F”. “64Mb Flash Memory” on page 2 Replaced “S71PL032JA0-07” with “S71PL032JA0-0K”. “128Mb Flash Memory” on page 3 Added row with the following content: S71PL127JB0-9; 65; 32M pSRAM; 70; pSRAM; TLA064. Replaced “S71PL127JB0-97” with “S71PL127JB0-9Z”. Added row with the following content: S71PL127JC0-97; 65; 64M pSRAM; 70; pSRAM1; TLA064. Replaced “S71PL127JC0-9P” with “S71PL127JC0-9Z”. In the S71Pl254JB0-TB row changed pSRAM type from “pSRAM3” to “pSRAM2”. “256Mb Flash Memory (2xS29PL127J)” on page 3 Added row with the following content: S71PL254JB0-TB; 65; 32M pSRAM; 70; pSRAM3; FTA084. Added row with the following content: S71PL254JC0-TB; 65; 64M pSRAM; 70; pSRAM2; FTA084. “Connection Diagram (S71PL127J)” on page 11 Updated pins D8, D9, and L5. Added notes 2 and 3 to drawing. “Connection Diagram (S71PL254J)” on page 12 Updated pins D8 and D9. Added Note 2 to drawing. “S71PL032J Valid Combinations” on page 15 Changed S71PL032J08 (p)SRAM Type Access Time (ns) from “SRAM1” to “SRAM2” (4 changes made in table). Changed S71PL032JA0 (p)SRAM Type Access Time (ns) from “SRAM3 / 70” to pSRAM3 /70”. Deleted all cells with the following collaborated text: “BAW,BFW, BAI. BFI”. Merged previous place holder with cell above. “S71PL064J Valid Combinations” on page 16 In (p)SRAM Type/Access Time (ns) changed all instances of “stet” to “pSRAM1/ 70”. In Package Modifier/Model Number changed all instances of “stet” to “07”. Added row to BAW Package and Temperature sections with the following content: S71PL064JB0; 07; 65 (previously inclusive); pSRAM1/70. “S71PL127J Valid Combinations” on page 17 Changed the S71PL127JA0 Package Modifier/Model Number from “9Z” to “9P” (4 instances).

Added 4 rows with the following content: S71PL127JC0; 97; pSRAM1/70. “S71PL254J Valid Combinations” on page 18 Added 4 rows with the following content: S71PL254JC0; TB; pSRAM2/70. Added 4 rows with the following content: S71PL254JB0; TB; pSRAM2/70. “S71PL254/127/064/032J based MCPs” on page 1 Added 254M to Megabit indicator. Added 16 to CMOS indicator. Revision A5 (September 14, 2004) Product Selector Guide Updated the 128Mb Flash Memory table. Valid Combinations Table Updated the S71PL127J Valid Combinations table. Revision A6 (November 22, 2004) Product Selector Guide Updated the 32Mb and 64Mb tables. Valid Combinations Tables Updated the 32Mb and 64Mb combinations. Physical Dimensions Added the TSB064 package. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men- tioned uses of the products. Any semiconductor devices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign T rade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2004 Spansion LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Span- sion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective compa- nies.

Product Information

S71PL032JA0 specifications and overview.

Summary

STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM

Description

STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM

Source title S71PL032JA0 Datasheet(PDF) - SPANSION

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