S71NS064NC0BJWRN3

S71NS-N-MCP SPANSION | Alldatasheet

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Publication Number S71NS-N_00 Revision A Amendment 3 Issue Date October 10, 2006 S71NS-N MCP Products MirrorBit TM

1.8 Volt-only Simultaneous Read/Write,

Burst-mode Multiplexed Flash Memory:

256 Mb (16 Mb x 16-bit), 128 Mb (8 Mb x 16-bit) and

64 Mb (4 Mb x 16-bit) with Burst-mode Multiplexed

pSRAM: 64 Mb (4 Mb x 16-bit), 32 Mb (2 Mb x 16-bit) and 16 Mb (1 Mb x 16-bit) Data Sheet ADVANCE INFORMATION Notice to Readers: The Advance Information status indicates that this document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the fact ory. Spansion Inc. reserves the right to change or discon tinue work on this proposed product without notice.

ii S71NS-N_00_A3 October 10, 2006 Advance Information Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specif ications throughout the product life cycle, in- cluding development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their de- sign. The following descriptions of Spansion data sheet designations are presented here to high- light their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any desi gn to production. Information presented in a document with this designation is likely to change, and in some cases, development on the prod- uct may discontinue. Spansion Inc. therefore places the following conditions upon Advance Infor- mation content: “This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without con- tacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the prod- uct life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary docume nt should be expected while keeping these as- pects of production under consid eration. Spansion places the following conditions upon Prelimi- nary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifica- tions due to changes in technical specifications.” Combination Some data sheets will contain a combination of products with different designations (Advance In- formation, Preliminary, or Full Production). This type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with DC Charac teristics table and AC Erase an d Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designatio n is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incor- rect specification. Spansion Inc. applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that sub- sequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.

Publication Number S71NS-N_00 Revision A Amendment 3 Issue Date October 10, 2006 General Description The S71NS-N Series is a product line of stacked Multi-Chip Product (MCP) packages and consists of the following items: „ One or more S29NS-N flash memory die „ Mux burst-mode pSRAM The products covered by this document are listed in the table below. For details about their spec- ifications, please refer to their individual datasheet for further details. Distinctive Characteristics MCP Features „ Power supply voltage of 1.7 V to 1.95 V „ Burst Speed: 66 MHz „ Package - MCP BGA: 0.5 mm ball pitch — 8.0 x 9.2 mm, 56 ball for NS064N and NS128N based MCPs — 10.0 x 11.0 mm, 60 ball for NS256N based MCPs „ Operating Temperature — Wireless, –25°C to +85°C For detailed specifications, please refer to the individual data sheets: S71NS-N MCP Products MirrorBit TM Burst-mode Multiplexed Flash Memory: pSRAM: 64 Mb (4 Mb x 16-bit), 32 Mb (2 Mb x 16-bit) and 16 Mb (1 Mb x 16-bit) ADVANCE INFORMATION pSRAM Density 16 Mb 32 Mb 64 Mb Flash

64 Mb S71NS064NA0

128 Mb S71NS128NA0 S71NS128NB0 S71NS128NC0

256 Mb S71NS256NB0 S71NS256NC0

Document Publication Identification Number S29NS-N S29NS-N_00

16 M Multiplexed pSRAM Type 2 muxpsram_05

16 M Multiplexed pSRAM Type 3 muxpsram_03

32 M Multiplexed pSRAM Type 3 muxpsram_04

64 M Multiplexed pSRAM Type 3 muxpsram_01

2 S71NS-N MCP Products S71NS-N_00_A3 October 10, 2006

1 Ordering Information

The ordering part number is formed by a valid combination of the following: Package Marking Note: The package marking omits the leading S from the ordering part number. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S71NS 128 N C 0 BJ W R N 0 Packing Type 0= T r a y 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel RAM Supplier and Speed Combinations N = pSRAM Type 3, 70 ns, 66 MHz T = pSRAM Type 2, 70 ns, 66 MHz Package Modifier R = 1.2 mm, 8.0 x 9.2, 56-ball VFBGA V = 1.2 mm, 11 x 10 mm, 60-ball VFBGA Temperature Range W = Wireless (-25°C to +85°C) Package Type BJ = Very Thin Fine-Pitch Ball Grid Array (VFBGA) Lead (Pb)-free Package (LF35) Chip Contents—2 No content pSRAM Density C = 64 Mb B = 32 Mb A = 16 Mb Process Technology N = 110 nm MirrorBit Technology Flash Density 256 = 256 Mb 128 = 128 Mb 064 = 64 Mb Device Family S71NS = Multi-Chip Product

1.8 Volt-only Simultaneous Read/Write Burst Mode

Multiplexed Flash Memory + pSRAM T able 1.1 MCP Configurations and Valid Combinations Base Ordering Part Number (Note 2) Package & T emperature Model Number Packing Ty p e pSRAM T ype Flash Speed Options pSRAM Speed Options S71NS064NA0 BJW RT 0, 1, 2 pSRAM Type 2 66 MHz 66 MHz RN pSRAM Type 3 66 MHz 66 MHz S71NS128NA0 RN pSRAM Type 3 66 MHz 66 MHz S71NS128NB0 RN pSRAM Type 3 66 MHz 66 MHz S71NS128NC0 RN pSRAM Type 3 66 MHz 66 MHz S71NS256NB0 VN pSRAM Type 3 66 MHz 66 MHz S71NS256NC0 VN pSRAM Type 3 66 MHz 66 MHz

October 10, 2006 S71NS-N_00_A3 S71NS-N MCP Products 3 Advance Information

2 Input/Output Descriptions

Table 2.1 identifies the input and output package connections provided on the device. T able 2.1 Input/Output Descriptions Symbol Description Flash RAM AMAX – A16 Address inputs XX ADQ15 – ADQ0 Multiplexed Address/Data X X OE# Output Enable input. Asynchronous relative to CLK for the Burst mode. X X WE# Write Enable input. X X VSS Ground XX NC No Connect; not connected internally X X RDY Ready output. Indicates the status of the Burst read. The WAIT# pin of the pSRAM is tied to RDY. XX CLK Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Should be at VIL or VIH while in asynchronous mode XX AVD# Address Valid input. Indicates to device that the valid address is present on the address inputs. Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. High = device ignores address inputs XX F-RST# Hardware reset input. Low = device resets and returns to reading array data X F-WP# Hardware write protect input. At VIL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. X F-ACC Accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. X R-CE1# Chip-enable input for pSRAM. X F-CE# Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode. X R-CRE Control Register Enable (pSRAM). X F-VCC Flash 1.8 Volt-only single power supply. X R-VCC pSRAM Power Supply. X R-UB# Upper Byte Control (pSRAM). X R-LB# Lower Byte Control (pSRAM) X DNU Do Not Use

4 S71NS-N MCP Products S71NS-N_00_A3 October 10, 2006

3 MCP Block Diagram

Figure 3.1 MCP Block Diagram Note: The CLK and WAIT signals on the pSRAM are not present on the pSRAM Type 2; therefore, for those MCP's, those signals will only be connected to the NS flash, but not to the pSRAM. Also, on this pSRAM, the CRE signal will not be present at all. F-RST# RST# F-ACC ACC F-WP# WP# RDY RDY/ WAIT F-CE# CE# OE# OE# WE# WE# AD15-AD0 AD15-AD0 AVD# AVD# CLK CLK Amax-A16 Amax-A16 CRE UB# LB# WAIT R-CE# CE# OE# WE# AD15-AD0 AVD# CLK Amax-A16 NS pSRAM R-CRE R-UB# R-LB#

October 10, 2006 S71NS-N_00_A3 S71NS-N MCP Products 5 Advance Information

4 Connection Diagrams/Physical Dimensions

This section contains the I/O designations and package specifications for the S71NS-N.

4.1 Special Handling Instructions for FBGA Packages

Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning meth- ods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.

4.2 Connection Diagrams

4.2.1 pSRAM Based Pinout, 56-Ball, VFBGA Notes: 1. Addresses are shared between Flash and RAM depending on the density of the pSRAM. 2. CLK and WAIT signals are Flash only for the S71NS064N A0-RT, while on that MCP, the CRE signal won't exist. Figure 4.1 pSRAM Based Pinout, 56-Ball, VFBGA MCP Flash-Only Addresses Shared Addresses Shared ADQ Pins S71NS128NC0 A22 A21-A16 ADQ15 – ADQ0 S71NS128NB0 A22-A21 A20-A16 ADQ15 – ADQ0 S71NS128NA0 A22-A20 A19-A16 ADQ15 – ADQ0 S71NS064NA0 A21-A20 A19-A16 ADQ15 – ADQ0 Flash/RAM Shared Only Flash Only Legend RAM Only No Connect (Distance between outer NC balls is 2x pitch) Reserved for Future Use NC K14 NC A14 NC NC D3 D6D5 D7 D8 D9 D10D4 E3 E6E5 E7 E8 E9 E10E4 E11 E12 F3 F6F5 F7 F8 F9 F10F4 F11 F12 G3 G6G5 G7 G8 G9 G10G4 G11 G12 H3 H4 H11 H12 C3 C7 C11 NC RFU R-LB# R-UB# RFU NC F-RDY/ R-WAIT A21 V SS CLK V CC F-ACC A19 D11 A17 A22WE# VCCQ A16 A20 AVD# DNU F-RST# F-WP# A18 F-CE# V SSQ VSS A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE# A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0 NC RFU R-CE# R-CRE RFU NC C4 C8 C12 D12 H7 H8 56-ball Fine-Pitch Ball Grid Array pSRAM-Based Pinout (Top View, Balls Facing Down)

6 S71NS-N MCP Products S71NS-N_00_A3 October 10, 2006

4.2.2 pSRAM Based Pinout, 60-Ball, VFBGA Note: Addresses are shared between Flash and RAM depending on the density of the pSRAM. Figure 4.2 pSRAM Based Pinout, 60-Ball, VFBGA MCP Flash-Only Addresses Shared Addresses Shared ADQ Pins S71NS256NC0 A23-A22 A21–A16 ADQ15 – ADQ0 S71NS256NB0 A23-A21 A20-A16 ADQ15 – ADQ0 NC Flash/RAM Shared Only Flash Only Legend RAM Only No Connect (Distance between outer NC balls is 2x pitch) Reserved for Future Use NC M16 NC P18 NC C16 NC A18 NC NC NC F5 F8F7 F9 F10 F11 F12F6 G5 G8G7 G9 G10 G11 G12G6 G13 G14 H5 H8H7 H9 H10 H11 H12H6 H13 H14 J5 J8J7 J9 J10 J11 J12J6 J13 J14 K5 K6 K13 K14 E5 E9 E13 NC RFU R-LB# R-UB# RFU NC F-RDY/ R-WAIT A21 V SS CLK V CC F-ACC A19 F13 A17 A22WE# VCCQ A16 A20 AVD# A23 F-RST# F-WP# A18 F-CE# V SSQ VSS A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE# A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0 NC RFU R-CE# R-CRE RFU NC E6 E10 E14 F14 K9 K10

October 10, 2006 S71NS-N_00_A3 S71NS-N MCP Products 7 Advance Information

4.2.3 Look Ahead Connection Diagram

112-ball x16 MUX NOR Flash + x16 MUX pSRAM on Shared Bus and x16 NAND Interface ORNAND on Bus 2 Figure 4.3 Look Ahead Connection Diagram 112-ball x16 MUX NOR Flash + x16 MUX pSRAM on Shared Bus and x16 NAND Interface ORNAND on Bus 2 329 1 0 547 681 1312 15 14 17 16 1811 NC NC B D E F G H J K L M N P A C NC NC NCNC NC NC NC NC NCNC DNU DNU N-IO15N-IO7 NC NC DNU R-LB# R-UB#N2-CE#N-RDY F2-CE# N-IO5 N-IO6N-IO13 N-IO14 N1-CE# VCC WE#F-RDY/ R-WAIT N-RE# VSS A21 CLK A17 A19 N-IO4A22 N-IO12F-ACC N-VCC A23 F-RST#VCCQN-VCC A20 A16 AVD# F1-CE#A18 N-IO11VSSQ N-PREF-WP# N-VSS A/DQ12 A/DQ3VSSN-VSS A/DQ6 A/DQ7 A/DQ13 A/DQ8 A/DQ9 VCCOE# VSSA/DQ2 N-CLE A/DQ4 A/DQ11A/DQ15N-ALE VSSQ A/DQ14 A/DQ5 A/DQ1 VCCQ N-IO18A/DQ0 N-IO3A/DQ10 DNU R-CE# R-CREN-WP#N-WE# A24 VSS N-IO9N-IO1 N-IO2 NCNC DNU DNU N-IO8N-IO0 NC NC NCNC NC NC NC NC NC NC NC NC Legend NOR Flash/pSRAM Shared Only No Connect Do Not Use NOR Flash 1 Only pSRAM Only ORNAND Flash Only NOR Flash 2 Only NOR Flash Shared Only

8 S71NS-N MCP Products S71NS-N_00_A3 October 10, 2006

4.3 Physical Dimensions

4.3.1 NLB056—9.2 x 8.0 mm, 56-ball VFBGA Figure 4.4 Physical Dimensions, NLB056—56-ball VFBGA 3507\\ 16-038.22 \\ 7.14.5 PACKAGE NLB 056 JEDEC N/A D x E 9.20 mm x 8.00 mm PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.20 PROFILE A1 0.20 --- --- BALL HEIGHT A2 0.85 --- 0.97 BODY THICKNESS D 9.20 BSC. BODY SIZE E 8.00 BSC. BODY SIZE D1 4.50 BSC. MATRIX FOOTPRINT E1 6.50 BSC. MATRIX FOOTPRINT MD 10 MATRIX SIZE D DIRECTION ME 14 MATRIX SIZE E DIRECTION n 56 BALL COUNT Øb 0.25 0.30 0.35 BALL DIAMETER eE 0.50 BSC. BALL PITCH eD 0.50 BSC BALL PITCH SD / SE 0.25 BSC. SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS NOTES: 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.

9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT. A2 ~ A13,B1 ~ B14 J1 ~ J14, K2 ~ K13 G1,G2,G13,G14,H1,H2,H5,H6,H9,H10,H13,H14 D1,D2,D13,D14,E1,E2,E13,E14,F1,F2,F13,F14 C1,C2,C5,C6,C9,C10,C13,C14 0.20 0.08C SIDE VIEW A A2 56X

0.15 M A C

0.08 M C

B b C C BOTTOM VIEW 7SE eD ABCDEFHGJK eE CORNER PIN A17 SD AD E (2X) 0.10 C C B (2X) 0.10 TOP VIEW CORNER PIN A1 INDEX MARK

October 10, 2006 S71NS-N_00_A3 S71NS-N MCP Products 9 Advance Information 4.3.1 NLA060—11.0 x 10.0 mm, 60-ball VFBGA Figure 4.5 Physical Dimensions, NLA060—60-ball VFBGA 3483 \\ 16-038.22 \\ 3.11.5 PACKAGE NLA 060 JEDEC N/A D x E 10.95 mm x 9.95 mm PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.20 PROFILE A1 0.20 --- --- BALL HEIGHT A2 0.85 --- 0.97 BODY THICKNESS D 10.95 BSC. BODY SIZE E 9.95 BSC. BODY SIZE D1 6.50 BSC. MATRIX FOOTPRINT E1 8.50 BSC. MATRIX FOOTPRINT MD 14 MATRIX SIZE D DIRECTION ME 18 MATRIX SIZE E DIRECTION n 60 BALL COUNT Øb 0.25 0.30 0.35 BALL DIAMETER eE 0.50 BSC. BALL PITCH eD 0.50 BSC BALL PITCH SD / SE 0.25 BSC. SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS NOTES: 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIAMETER IN A PLANE PARALLEL TO DATUM C. AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT. AD E (2X) 0.15 C INDEX MARK C B 0.15 (2X) TOP VIEW CORNER PIN A1 b60X

0.15 M C

C C C

6 SIDE VIEW

A A2 0.20 0.08 PNML KJ HGFEDCB SE A eD eE CORNER PIN A17 SD BOTTOM VIEW A2~A17,B1~B18,C1,C2,C4~C15,C17,C18 D1~D18,E1,E2,E3,E4,E7,E8,E11,E12,E15,E16,E17,E18 K1,K2,K3,K4,K7,K8,K11,K12,K15,K16,K17,K18 L1 ~L18,M1,M2,M4~M15,M17,M18,N1~N18,P2~P17 F1,F2,F3,F4,F15,F16,F17,F18,G1,G2,G3,G4,G15,G16,G17,G18 H1,H2,H3,H4,H15,H16,H17,H18,J1,J2,J3,J4,J15,J16,J17,J18

10 S71NS-N MCP Products S71NS-N_00_A3 October 10, 2006

5 Revisions

Revision A0 (January 3, 2006) Initial Release under Publication Identification Number S71NS128NC0_01 Revision A1 (March 1, 2006) Changed the Publication Identification Number from S71NS128NC0_01 to S71NS-N_00 Added the MCP S71NS064NA0 Revision A2 (June 13, 2006) Corrected the grid reference for 56-ball connection diagram Revision A3 (October 10, 2006) Added the S71NS064NA0-RT - the one using pSRAM Type 2 Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable to you and/or any third party for any claims or damages arising in connection with above- mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on ex- port under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion Inc. product under development by Spansion Inc. Spansion Inc. reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion Inc. assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.