S40FC004 ETC | Alldatasheet
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Features
e.MMC 5.1 Specification Compatible Backward compatible with previous e.MMC specifications Operating Voltage V : 1.7V - 1.95V or 2.7V - 3.6V CCQ V : 2.7V - 3.6V CC Density: 4 GB of Data Storage Data Bus Width: SDR Mode: 1 bit, 4 bit, 8 bit DDR Mode: 4 bit, 8 bit HS200 Mode: 4 bit, 8 bit HS400 Mode: 8 bit Clock Frequency: 52 MHz, 200 MHz SDR Mode: up to 52 MHz DDR Mode: up to 52 MHz HS200 Mode: up to 200 MHz HS400 Mode: up to 200 MHz BGA Packages 153-ball VFBGA — 11.5 mm x 13 mm x 0.8 mm Operating Temperature Range Industrial (–40°C to + 85°C) Key Supported Features HS400, HS200 Boot Feature/ Boot Partition Partitioning, RPMB, RPMB Throughput Improve HPI, BKOPS, BKOP Operation Control Sanitize, Discard, Trim, Erase Lock/Unlock High Priority Interrupt Secure Removal Type Configurable Drive Strength Cache, Cache Barrier, Cache Flushing Report Reliable Write Hardware/ Software Reset Health Monitoring Field Firmware Update PON, Sleep/Awake Packed CMD, CMD Queuing Data Strobe Pin, Enhanced Data Strobe Production State Awareness Write protect, Secure Write Protection 4GB , 3.3 V, e.MMC Flash Embedded Wireless (-25°C to + 85°C) Industrial Extended (–40°C to + 105°C) Automotive (–40°C to + 85°C) Automotive Extended (–40°C to + 105°C) SkyHigh Memory Limited Document Number: 002-01111 Rev. J Suite 4401-02, 44/F One Island East,
18 Westlands Road Hong Kong
www.skyhighmemory.com Revised Feb. 03, 2021
Performance and Power Consumption (Temperature = 25°C) Table 3 Power Consumption S40FC004 Table 1 MLC Partition Sequential Performance Write Read 1. Bus in x8 I/O, HS400 mode. Sequential Access of 1MB chunk (Clean) Table 2 MLC Partition Random Performance Write (Cache On) Write (Cache Off) Read 2: Bus in x8 I/O, HS400 mode. Random Access of 4KB chunk over 1GB span Typ. Values (IOPS) 4GB Condition Condition 4GB 200 Typ. Values (MB/s) Burst Sustained 3550 800 1100 555 N/A 5870 [ 1 [ 2 Note: Note: Density Speed VCC/VCCQ Operation ICC(mA) ICCQ(mA) ICC(uA) ICCQ(uA) ICC(uA) ICCQ(uA) Read Write Read Write Read Write Read 145 Write Read Write Read 105 Write HS200 3.6/1.95 HS400 3.6/1.95 eMMC RMS Idle Sleep 4GB SDR52 3.6/1.95 110 170 100 160 DDR52 3.6/1.95 SDR52 3.6/3.6 DDR52 3.6/3.6 Document Number: 002-01111 Rev. *J Page 2 of 33
Key Supported e.MMC Features 5.1 5.2 5.3 Sleep (CMD5) 5.4 5.5 Background Operations 5.6 5.7 5.8 Sanitize 5.9 Hardware Reset 5.10 5.11 Register Values 6.1 6.2 CID Register 6.4 CSD Register 6.5 AC Parameter 7.1 Bus Timing 7.2 High Speed Timing 7.3 Backward Compatible Timing 7.4 DDR Interface Timing 7.5 Timing Specifications for HS200 Clock Timing 21 HS200 Input Timing 22 HS200 Output Timing 23 7.6 HS400 Device Input Timing 23 HS400 Device Output Timing 24 HS400 Device Command Output Timing 27 7.7 7.8 7.9 Push-Pull Mode Bus Signal Level — High Voltage e.MMC 7.10 Push-Pull Bus Signal Level — Dual Voltage e.MMC ... 29 DC Parameter 8.1 8.2
Ordering Information
- 10.1 VFBGA 153 — Package Dimensions 11.5 x 13 x 0.8 mm 11. Document History Page 6.3 Product Table S40FC004 ... 29 Performance and Power Consumption Document Number: 002-01111 Rev. *J Page 3 of 33
e.MMC is a managed NAND memory solution designed for embedded applications. SkyHigh e.MMC includes a flash controller and a standard MLC NAND flash memory, and is compatible with the JEDEC JESD84-B51 with backwards compatibility to previous e.MMC specifications. Designed for faster throughput and large data transfer, SkyHigh e.MMC offers high performance, great reliability, and minimal latency. In addition to higher performance, SkyHigh's e.MMC offers optimum power management features resulting in reduced power consumption, making it an ideal solution for mobile applications. In addition, highly optimized SkyHigh firmware fully utilizes the MLC NAND capabilities leveraging wear-leveling, defect management, garbage collection, and ECC to enhance product life. The SkyHigh e.MMC product family offers a vast array of the JEDEC e.MMC features including HS200, HS400, high priority interrupt (HPI), boot partitions, RPMB partitions, background operations, hardware reset, and power off notification. Combined with an advanced e.MMC feature set and SkyHigh's commitment to quality, SkyHigh e.MMC is ideal for industrial applications as well as set top boxes, gaming consoles, and consumer electronic devices. SkyHigh Product Offering The SkyHigh e.MMC product offering includes:
4 GB: S40FC004
153 VFBGA (11.5 x 13 x 0.8, 0.5 mm ball pitch) S40FC004 Document Number: 002-01111 Rev. *J Page 4 of 33
Figure 3.1 FBGA 153 (Top View, Balls Down) B D E F G H J K L M N P A C DAT0 DAT2 DAT1 DAT4 DAT3 DAT6 DAT5 DAT7 VDDI VSSQ VCCQ VSS VCC VCC VSS VSS VCC VSS RST_N VCC CMD VCCQ CLK VSSQ VSSQ VCCQ VCCQ VSSQ VSSQ VCCQ NC NC NC NC NC NC NC VSS RFU NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC RFU NC NC RFU NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC RFU RFU RFU NC NC NC NC NC NC RFU NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC RFU RFU NC NC RFU RFU RFU RFU DS VSS NC NC NC S40FC004 Document Number: 002-01111 Rev. *J Page 5 of 33
Table 3.1 Pin Description
Description
Bidirectional data channels used for data transfers. I/O DAT0 - DAT7 Bidirectional command channel used for I/O CMD device initialization and command transfers. Clock input. Input CLK Hardware reset. Input RST_N Supply voltage for the flash memory. Power VCC Supply voltage for the memory controller and MMC interface. Power VCCQ Internal power node. Connect capacitor to ground. Power VDDI Ground pin for the flash memory. Power VSS Ground pin for the memory controller and MMC interface. Power VSSQ Data strobe. Output DS Not connected. NC Reserved for future use. Do not connect. RFU S40FC004 Document Number: 002-01111 Rev. *J Page 6 of 33
5.3 Sleep (CMD5) Sleep/Awake (CMD5) is used to switch the device between Sleep and Standby mode. During the Sleep state, V CC can be switched off for maximum power savings. While a device is in Sleep mode it can only respond to the Reset (CMD0) and Sleep/Awake (CMD5) commands. 5.4 High Priority Interrupt (HPI) High Priority Interrupt (HPI) is intended to suspend an ongoing operation while allowing for a high priority read operation to be performed. 5.5 Background Operations e.MMC devices are equipped with a Background Operations feature. When enabled, Background Operations allow the e.MMC device to perform a number of routine data maintenance operations such as wear leveling, garbage collection, erase, and compaction while the host CPU is not being serviced. 5.6 Auto Background Operations Auto Background Operations is a feature that allows the e.MMC device to fully manage background operations without any requirements from the Host. The e.MMC device will check if background operations are required at specified intervals and initiate background operations if needed. This frees the host from having to develop software to manage these maintenance tasks and ensure that the e.MMC device is operating at the optimum performance levels. Issuing any command while auto background operations are occurring will stop the current background operation activities. There will be a maximum latency of 40 ms if auto background operations are interrupted by any read or write command from the host. 5.7 Trim Similar to the Erase operation, the Trim function performs a targeted erase on specific write blocks. Data that is no longer needed, designated by the host, will be erased during background erase events. 5.8 Sanitize Sanitize is intended for applications with high security requirements that can afford the performance impact. This command is used in conjunction with standard Erase or Trim operations and requires the device to physically remove data from the unmapped user address space. The busy line will be asserted once the Sanitize operations begin and will remain busy until the operation has been completed or interrupted. 5.9 Hardware Reset Used by the host to reset the device, hardware reset moves the device into a pre-idle state and disables the power-on period write protection on blocks that were set at power-on as write protected. S40FC004 Document Number: 002-01111 Rev. *J Page 9 of 33
Notes: 1. Bit 31 is set to LOW if device is not finished with the power up routine. 2. The voltage for internal flash memory (V CC ) should be 2.7V - 3.6V regardless of OCR Register value. 5.10 Health Monitoring Health Monitoring is a proprietary feature of the SkyHigh e.MMC product that provides useful information about the life span of the NAND flash component. The host can query for the device’s health by using the CMD60 command to get information such as the number of bad blocks and the number of erase cycles for each block. EXT_CSD registers [269:254] also contain valuable device health information. A separate application note is available with the full details of the CMD60 command and EXT_CSD registers [269:254]. A non-disclosure agreement (NDA) is required to view this application note. Contact your nearest SkyHigh sales office for more information. 5.11 Field Firmware Update Field Firmware Update is a feature that allows the host to upload a new version of the firmware to the e.MMC. This can be done by setting the device into FFU mode and performing writes with the arguments defined in the FFU_ARG register. A separate application note is available with the full details of this feature. A non-disclosure agreement (NDA) is required to view this application note. Contact your nearest SkyHigh sales office for more information. Register Values 6.1 OCR Register Operation Conditions Register (OCR) stores the e.MMC voltage profile. In addition, it contains the status bit (31) which is set when the device power up has been completed. Table 6.1 OCR Register Value OCR Slice Field Description 00 00000b [6:0] Reserved V CCQ Dual Voltage: 1b [7] : 1.7 - 1.95 range V CCQ 000 0000b [14:8] : 2.0 - 2.6 range V CCQ 1 1111 1111b [23:15] : 2.7 - 3.6 range 0 0000b [28:24] Reserved Sector Mode: 10b [30:29] Access Mode e.MMC power up status bit (busy) (1) [31] S40FC004 Document Number: 002-01111 Rev. *J Page 10 of 33
6.2 CID Register
The Card Identification Register (CID) contains the card iden tification information used during the card identification phase. Table 6.2 CID Register CID Value CID slice Width Field ID Field Name 01h [127:120] MID Manufacturer ID 01b [113:112] CBX Card BGA 00h [111:104] OID OEM/Application ID See product table [103:56] PNM Product Name [55:48] PRV Product Revision 32-bit unsigned binary integer assigned at random [47:16] PSN Product Serial Number [15:8] MDT Manufacturing Date (Note 1) [7:1] CRC CRC7 Checksum (Note Always 1 [0] Not Used Notes: 1. Descriptions follow JEDEC e.MMC Standard Specifications. 2. The CRC7 checksum (7 bits). This is the checksum of the CID contents computed according to 0. 3. Product Revision is a combination of Controller and Firmware Revisions.
6.3 Product Table
Table 6.3 Product Table SkyHigh Part Number Density Product Name in CID Register (PNM) S40FC004 4 GB S 40004” – 533430303034h S40FC004 (Note 3) Document Number: 002-01111 Rev. *J Page 11 of 33
6.4 Card Specific Data Register
Table 6. CSD Register
- The CRC field carries the check sum for the CSD contents. It is computed according to 0. The checksum has to be recalculated by the host for any CSD
modification. The default corresponds to the initial CSD contents. Table 7. Extended CSD Register ( R/W = One time programmable and readable. assertion and any CMD0 reset and readable. R/W/C_P = Writable after value cleared by power failure and hardware reset assertion (the value not cleared by CMD0 reset) and readable. reset assertion and any CMD0 reset and readable. W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and not readable. Table 7. Extended CSD Register (EXT_CSD)
R/W = One time programmable and readable. R/W/E = Multiple writable with value kept after power failure, hardware reset assertion and any CMD0 reset and readable. R/W/C_P = Writable after value cleared by power failure and hardware reset assertion (the value not cleared by CMD0 reset) and readable. R/W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and readable. power failure, hardware reset assertion and any CMD0 reset and not readable.
- This Fields reserved for vendor proprietary health report.
R/W = One time programmable and readable. hardware reset assertion and any CMD0 reset and readable. R/W/C_P = Writable after value cleared by power failure and hardware reset assertion (the value not cleared by CMD0 reset) and readable. R/W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and readable. W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and not readable.
R/W = One time programmable and readable. R/W/E = Multiple writable with value kept after power failure, hardware reset assertion and any CMD0 reset and readable. R/W/C_P = Writable after value cleared by power failure and hardware reset assertion (the value not cleared by CMD0 reset) and readable. R/W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and readable. = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and not readable.
R/W = One time programmable and readable. R/W/E = Multiple writable with value kept after power failure, hardware reset assertion and any CMD0 reset and readable. R/W/C_P = Writable after value cleared by power failure and hardware reset assertion (the value not cleared by CMD0 reset) and readable. R/W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and readable. W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and not readable.
R/W = One time programmable and readable. R/W/E = Multiple writable with value kept after power failure, hardware reset assertion and any CMD0 reset and readable. R/W/C_P = Writable after value cleared by power failure and hardware reset assertion (the value not cleared by CMD0 reset) and readable. R/W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and readable. assertion and any CMD0 reset and not readable.
- These fields are reserved for definition by the device manufacturer
- AC Parameter
7.1 Bus Timing
Figure 7.1 Bus Timing Diagram Note: 1. Data must always be sampled on the rising edge of the clock. D a t a D a t a D a t a D a t a Inv a lid Inv a lid t PP t WH t WL t ISU t IH t THL t TLH t OH CLK Inp u t O u tp u t t OSU t ODLY 50% V DD 50% V DD min (V IH min (V OH m a x (V IL min (V IH m a x (V IL m a x (V OL S40FC004 Document Number: 002-01111 Rev. *J Page 19 of 33
7.2 Backward Compatible Timing 7.3 Table 7.1 High Speed Timing Remark Unit Max Min Symbol Parameter Clock CLK f Clock Frequency Data Transfer Mode PP MHz CL 30 pF Tolerance: +100 kHz f Clock Frequency Identification Mode OD Tolerance: +20 kHz kHz 400 t Clock Low Time WL CL ns 6.5 30 pF t Clock High Time WH CL ns 6.5 30 pF t Clock Rise Time TLH CL ns 30 pF t Clock Fall Time THL CL ns 30 pF Inputs CMD, DAT (referenced to CLK) t Input Set-up Time ISU CL ns 30 pF t Input Hold Time IH CL ns 30 pF Outputs CMD, DAT (referenced to CLK) t Output Delay Time During Data Transfer Mode ODL Y CL ns 13.7 30 pF t Output Hold Time OH CL 2.5 30 pF t Signal Rise Time RISE CL ns 30 pF t Signal Fall Time FALL CL ns 30 pF Table 7.2 Backward Compatible Timing Remark Unit Max Min Symbol Parameter Clock CLK f Clock Frequency Data Transfer Mode PP CL MHz 30 pF f Clock Frequency Identification Mode OD kHz 400 t Clock Low Time WL CL ns 30 pF t Clock High Time WH t Clock Rise Time TLH CL ns 30 pF t Clock Fall Time THL CL ns 30 pF Inputs CMD, DAT (referenced to CLK) t Input Set-Up Time ISU CL ns 30 pF t Input Hold Time IH CL ns 30 pF Outputs CMD, DAT (referenced to CLK) t Output Hold Time OH CL ns 8.3 30 pF t Output Set-up Time OSU CL ns 11.7 30 pF S40FC004 Document Number: 002-01111 Rev. *J Page 20 of 33
7.4 Figure 7.2 DDR Interface Timing
7.5 Timing Specifications for HS200 Mode
7.5.1 HS200 Clock Timing
HS200 mode is available when V CCQ is 1.7V to 1.95V, and the clock timing sh ould conform with the timing diagram shown in Figure 7.3 . CLK input timings need to m eet the clock timing across the entire range of operating environment. CLK timings must be measured while CMD and DAT signals are either high or low. HS200 supports clock frequencies of up to 200 MHz. Table 7.3 DDR Interface Timing Remark Unit Max. Min Symbol Parameter Input CLK1 Includes jitter, phase noise Clock Duty Cycle Input DAT (referenced to CLK-DDR mode) t Input Set-up Time ISUddr CL ns 2.5 20 pF t Input Hold Time IHddr CL ns 2.5 20 pF Output DAT (referenced to CLK-DDR mode) t Output Delay Time During Data Transfer ODL Yddr CL ns 1.5 20 pF t Signal Rise Time (All Signals) RISE CL ns 20 pF t Signal Fall Time (All Signals) FALL CL ns 20 pF D a t a t PP t I S Uddr Inp u t O u tp u t t ODLYddr(m a min (V IH min (V OH m a x (V IL min (V IH m a x (V IL m a x (V OL CLK t IHddr t I S Uddr t IHddr I t ODLYddr(min) t ODLYddr(m a t ODLYddr(min) D a t a D a t a Inv a lid D a t a D a t a D a t a S40FC004 Document Number: 002-01111 Rev. *J Page 21 of 33
7.5.3 HS200 Output Timing
parameter is defined to allow device output delay to be longer than t PERIOD . t PH may have random phase relation to the clock upon initialization. The Host is ulti mately responsible to find the optimal sa mpling point for the Device outputs, while switching to the HS200 mode. The impact of a temperature drift ( TPH ) has to be taken into account when settin g the sampling point. Output valid data window VW ) is available regardless of the drift ( TPH ) while the position of data window varies by the drift. Figure 7.5 HS200 Device Output Timing Note: 1. V OH denotes V OH(min.) , and V OL denotes V OL(max.) Note: 1. Unit Interval (UI) is one-bit nominal time (i.e. UI = 5 ns at 200 MHz). Table 7.6 HS200 Device Output Timing Notes Unit Max. Min. Symbol t PH U I Device output momentary phase from CLK input to CMD or DAT lines output. Does not include a long term temperature drift. TPH -350 T = -20°C) +1550 T = 90°C) ps Delay variation due to temperature change after tuning. Total allowable shift of output valid window (t VW ) from last system Tuning procedure. TPH is 2600 ps for T from -25°C to 125°C during operation. t VW UI 0.575 t VW = 2.88 ns at 200 MHz. Host path may add Signal Integrity induced noise, skews, etc. Expected t VW at Host input is la rger than 0.475 UI. VCCQ Clock Inp u t V SS V T t PERIOD V OL t VW CMD.DAT[7-0] Inp u t V OH V a lid Window V OH V OL t PH VCCQ V SS S40FC004 Document Number: 002-01111 Rev. *J Page 23 of 33
Figure 7.6 TPH Consideration Implementation Guide: The host should avoid sampling errors that are caused by the TPH drift. Tuning should be performed while the device wakes up after sleep. Reducing operating frequency can help overcome the TPH drift.
7.6 Bus Timing Specification in HS400 Mode
7.6.1 HS400 Device Input Timing
The CMD input timing for HS400 mode is the same as CMD input timing for HS200 mode. Figure 7.7 and Table 7.4 show Device input timing. Sa mpling point a fter j u nction cooled to -20°C Sa mpling point a fter j u nction he a ted to +90°C Sa t mpling poin a fter t u rning Sa mpling point = 1550 p s Δ TPH = - 50 p s Δ TPH V a lid ndow Wi V a lid Window V a lid w indo W S40FC004 Document Number: 002-01111 Rev. *J Page 24 of 33
Figure 7.7 HS400 Device Data Input Timing Note: 1. V T = 50% of V CCQ , indicates clock reference point for timing measurements.
7.6.2 HS400 Device Output Timing
The Data Strobe is used to read data in HS400 mode. The Data St robe is toggled only during dat a read or CRC status response. Table 7.7 HS400 Device Input Timing Remark Unit Max Min Symbol Parameter Input CLK Cycle time data transfer mode t PERIOD
200 MHz (max), between rising edges With
T With respect to V V/ns 1.125 SR Slew rate IH IL t Duty cycle distortion CKDCD ns 0.3 0.0 Allowable deviation from an ideal 50% duty cycle. With respect to V T Includes jitter, phase noise t Minimum pulse width CKMPW With respect to V ns 2.2 T Input DAT (referenced to CLK) t Input set-up time ISUddr ns 0.4 C Device 6 pF With respect to V IH IL t Input hold time IHddr ns 0.4 C Device 6 pF With respect to V IH IL With respect to V V/ns 1.125 SR Slew rate IH IL S40FC004 Document Number: 002-01111 Rev. *J Page 25 of 33
Figure 7.8 HS400 Device Output Timing Note: V T = 50% of V CCQ , indicates clock reference point for timing measurements. Table 7.8 HS400 Device Output Timing Remark Unit Max Min Symbol Parameter Data Strobe Cycle time data transfer mode t PERIOD T V/ns 1.125 SR Slew rate With respect to V OH OL and HS400 reference load Duty cycle distortion t DSDCD ns 0.2 0.0 Allowable deviation from the input CLKduty cycle distortion (t CKDCD ) With respect to V T Includes jitter, phase noise Minimum pulse width t DSMPW With respect to V ns 2.0 T t Read pre-amble RPRE t 0.4 PERIOD Max value is specified by manufacturer. Value up to infinite is valid t Read post-amble RPST t 0.4 PERIOD Max value is specified by manufacturer. Value up to infinite is valid Output DAT (referenced to Data Strobe) t Output skew RQ ns 0.4 With respect to V OH OL and HS400 reference load t Output hold skew RQH ns 0.4 With respect to V OH OL and HS400 reference load. V/ns 1.125 SR Slew rate With respect to V OH OL and HS400 reference load S40FC004 Document Number: 002-01111 Rev. *J Page 26 of 33
Note: 1. Recommended maximum value is 30 k for 1.2V and 50 k for 1.8V interface supply voltages. Table 7.9 HS400 Capacitance and Resistors Unit Max Min Symbol Parameter R Pull-up resistance for CMD CMD k 100 4.7 R Pull-up resistance for DAT0-7 DAT k 100 R Pull-down resistance for Data Strobe DS k 100 R Internal pull up resistance DAT1-DAT7 int k 150 C Single Device capacitance Device pF S40FC004 Document Number: 002-01111 Rev. *J Page 27 of 33
7.6.3 HS400 Device Command Output Timing
The Data Strobe is used to response of any command in HS400 mode. Figure 7.9 HS400 CMD Response Timing Note: V T = 50% of V CCQ , indicates clock reference point for timing measurements. Remark Unit Max Min Symbol Parameter Data Strobe Cycle time data transfer mode t PERIOD T SR Slew rate V/ns 1.125 With respect to V OH OL and HS400 reference load t Duty cycle distortion DSDCD ns 0.2 0.0 Allowable deviation from the input CLK duty cycle distortion (t CKDCD With respect to V T Includes jitter, phase noise t Minimum pulse width DSMPW ns 2.0 With respect to V T t Read pre-amble RPRE tPERIOD 0.4 Max value is specified by manufacturer. Value up to infinite is valid t Read post-amble RPST tPERIOD 0.4 Max value is specified by manufacturer. Value up to infinite is valid CMD Response (referenced to Data Strobe) t Output skew(CMD) RQ_CMD ns 0.4 With respect to V OH OL and HS400 reference load Output hold skew(CMD) t RQH_CMD ns 0.4 With respect to V OH OL and HS400 reference load Slew rate V/ns 1.125 SR With respect to V OH OL and HS400 reference load CMD OUTPUT VALID WINDOW t RQ_CMD t RQH_CMD V T t DSMPW t DSMPW t DSDCD t DSDCD Data Strobe t PERIOD VCCQ VSS VCCQ VSS V OH V OL S40FC004 Document Number: 002-01111 Rev. *J Page 28 of 33
7.7 Figure 7.10 Signal Levels Open-Drain Mode Bus Signal Level 7.8 Push-Pull Mode Bus Signal 7.9 Level — High Voltage e.MMC Push-Pull Bus Signal Level — Dual Voltage e.MMC 7.10 Table 7.10 Open-Drain Mode Bus Signal Level Conditions Unit Max. Min. Symbol Parameter V Output High Voltage OH V CCQ I V -0.2 OH = -100 µA V Output Low Voltage OL I V 0.3 OLL = 2 mA Table 7.11 Push-Pull Mode Bus Signal Level — Hi gh Voltage e.MMC Conditions Unit Max. Min. Symbol Parameter V Output High Voltage OH 0.75 * V CCQ I V OH = -100 µA at V CCQ min V Output Low Voltage OL 0.125 * V CCQ I V OL = 100 µA at V CCQ min V Input High Voltage IH 0.625 * V CCQ V CCQ V + 0.3 V Input Low Voltage IL V SS 0.25 * V -0.3 CCQ V Table 7.12 Push-Pull Bus Signal Level — Dual Voltage e.MMC Conditions Unit Max. Min. Symbol Parameter V Output High Voltage OH V CCQ I V -0.45V OH = -2 mA V Output Low Voltage OL I V 0.45V OL = 2 mA V Input High Voltage IH 0.65 * V CCQ V CCQ V + 0.3 V Input Low Voltage IL V SS 0.35 * V -0.3 CCQ V V CCQ Inp u t Inp u t u ndefined V t O u tp u t O u tp u t High Level Low Level High Level Low Level V OH V IH V IL V OL V SS S40FC004 Document Number: 002-01111 Rev. *J Page 29 of 33
- DC Parameter
8.1 Supply Voltage
8.2 Table 8.1 Supply Voltage Unit Max. Min. Symbol V CC V 3.6 2.7 V CCQ V 3.6 2.7 V 1.95 1.7 V SS V 0.5 -0.5 Table 8.2 Bus Operating Condition Unit Max. Min. Parameter V -0.5 Peak Voltage on all lines CCQ V +0.5 Input Leakage Current (after changing the bus width and disconnecting the internal pull-up resistors) µA Output Leakage Current (after changing the bus width and disconnecting the internal pull-up resistors) µA S40FC004 Document Number: 002-01111 Rev. *J Page 30 of 33
- Ordering Information The ordering part number is formed by a valid combination of the following: Valid Combinations Valid Combinations list configurations planne d to be supported in volume for this device. Consult your local sales office to co nfirm availability of specific valid combinations and to check on newly released combinations. I 004 FC S40 Valid Combinations Device Family Controller Density Package Type Temperature Range Model Number Packing Type Package
C, I BGA 0, 3 Packing Type Tray 13” Tape and Reel Model Number
1 NAND Die
I Industrial (-40°C to + 85°C) Package FBGA 153, 11.5 x 13 mm Controller e.MMC 5.1 Density 004 = 4GB Product Family FC Flash + Controller Device Family S40 = SkyHigh e.MMC Family Product Family FC S40FC004 C Embedded Wireless (-25°C to + 85°C) Firmware Version 00 (Default) Firmware Version V Industrial Plus (-40°C to + 105°C) A Industrial with AECQ-100 and GT Grade (-40°C to + 85°C) B Industrial Plus with AECQ-100 and GT Grade (-40°C to + 105°C) Document Number: 002-01111 Rev. *J Page 31 of 33
VFBGA 153 — Package Dimensions 11.5 x 13 x 0.8 mm S40FC004 PACKAGE JEDEC D X E SYMBOL A D E MD ME n O b eE eD SE SD / MIN. 0.70 0.17 0.25 D5-D11,E11-K11,L4-L11,E4-K4 F6-F9,G6-G9,H6-H9,J6-J9 TBD 153 MO-276 13.00mm X 11.50mm PACKAGE NOM. --- ---
13.00 BSC
11.50 BSC
6.50 BSC
0.30
0.50 BSC
0.25 BSC
MAX. 0.80 --- 0.35 NOTE PROFILE BALL HEIGHT BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS TBD153-0.8/4.16.15 NOTES: DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5-2009. THIS OUTLINE CONFORMS TO JEP 95, SECTION 4.6. ALL DIMENSIONS ARE IN MILLIMETERS. BALL P OSITION DESIGNATION PER JEP 95, SECTION 3, SPP-020. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL “MD” IS THE BALL MATRIX SIZE IN THE “D” DIRECTION. SYMBOL “ME” IS THE BALL MATRIX SIZE IN THE “E” DIRECTION. n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION “b” IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW D OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = e/2 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. TEST PADS MAY BE PRESENT BUT ARE NOT SHOWN. THEY ARE FOR INTERNAL USE ONLY AND ARE NOT SOLDER BALLS. 10. Physical Diagram 10.1 Document Number: 002-01111 Rev. *J Page 32 of 33
- Document History Page Document Title: S40FC004 Document Number: 002-01111 Rev. ECN No. Orig. of Change Submission Date Description of Change Initial release 06/26/2019 MNADA Updated CSD, CID, valid combinations 10/03/2019 MNADA A S40FC004 S40FC008 S40FC016 Updated CSD [14], [36:32], EXT_CSD[229] Changed pacakge height to 0.8mm for 4GB and 8GB- added package drawing 11/15/2019 MNADA B C MNADA 11/22/2019 Update ICC data and added performance data. Added Commercial Grade D MNADA 01/21/2020 Removed firmware revision from Ordering Information E MNADA 01/29/2020 Changed Commercial to Embedded Wireless F MNADA 03/10/2020 Changed the package dimension to 11.5 x 13 G MNADA 04/15/2020 Updated Power Consumption section H MNADA 07/08/2020 I MNADA 10/27/2020 Updated Model Number and Valid Combinations Remove storage temperature from the first page Added Industrial Extended and Automotive option to the ordering Information Updated Performance, Power Consumption, removed 8GB, 16GB J MNADA 02/03/2021 Document Number: 002-01111 Rev. *J Page 33 of 33