S3A6

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www.renesas.com S3A6 Group Microcontrollers Datasheet Renesas Synergy™ Platform Synergy Microcontrollers S3 Series Apr 2017Rev.1.00 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com). Cover

1. Descriptions of circuits, software and other related inform ation in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics hereby expressly disclaims any warran ties against and liability for infringement or any other disputes involving patents, copyrights, or other intellectual property rights of third parties, by or arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawing, chart, program, algorithm, application examples. 3. No license, express, implied or otherwise, is granted here by under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 4. You shall not alter, modify, copy, or otherwise misappropria te any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics products. 5. Renesas Electronics products are cl assified according to the following two quality grades: "Standard" and "High Quality". The intended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc. Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (space and undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). 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(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. (Rev.3.0-1 November 2016)

1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. V oltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-evaluation test for the given product.

R01DS0308EU0100 Rev.1.00 Page 4 of 129 Apr 4, 2017

Features

■ ARM Cortex-M4 Core with Floating Point Unit (FPU)  ARMv7E-M architecture with DSP instruction set  Maximum operating frequency: 48 MHz  Support for 4-GB address space  ARM Memory Protection Unit (MPU) with 8 regions  Debug and Trace: ITM, DWT, FPB, TPIU, ETB  CoreSight debug port: JTAG-DP and SW-DP ■ Memory  256-KB code flash memory  8-KB data flash memory (up to 100,000 erase/write cycles)  32-KB SRAM  Flash Cache (FCACHE)  Memory Protection Units  128-bit unique ID ■ Connectivity  USB 2.0 Full-Speed Module (USBFS) - On-chip transceiver with voltage regulator - Compliant with USB Battery Charging Specification 1.2  Serial Communications Interface (SCI) × 4 - UART - Simple I - Simple SPI  Serial Peripheral Interface (SPI) × 2  I2C bus interface (IIC) × 2  CAN module (CAN)  Serial Sound Interface Enhanced (SSIE) ■ Analog  14-Bit A/D Converter (ADC14)  12-Bit D/A Converter (DAC12)  8-Bit D/A Converter (DAC8) ×2 (for ACMPLP)  Low-Power Analog Comparator (ACMPLP) × 2  Operational Amplifier (OPAMP) × 4  Temperature Sensor (TSN) ■ Timers  General PWM Timer 32-Bit (GPT32) × 2  General PWM Timer 16-Bit (GPT16) × 6  Asynchronous General-Purpose Timer (AGT) × 2  Watchdog Timer (WDT) ■ Safety  ECC in SRAM  SRAM parity error check  Flash area protection  ADC self-diagnosis function  Clock Frequency Accuracy Measurement Circuit (CAC)  Cyclic Redundancy Check (CRC) calculator  Data Operation Circuit (DOC)  Port Output Enable for GPT (POEG)  Independent Watchdog Timer (IWDT)  GPIO readback level detection  Register write protection  Main oscillator stop detection  Illegal memory access ■ System and Power Management  Low power modes  Realtime Clock (RTC) with calendar and Battery Backup support  Event Link Controller (ELC)  DMA Controller (DMAC) × 4  Data Transfer Controller (DTC)  Key Interrupt Function (KINT)  Power-on reset  Low voltage detection with voltage settings ■ Security and Encryption  AES128/256  GHASH  True Random Number Generator (TRNG) ■ Human Machine Interface (HMI)  Segment LCD Controller (SLCDC) - Up to 38 segments × 4 commons - Up to 34 segments × 8 commons  Capacitive Touch Sensing Unit (CTSU) ■ Multiple Clock Sources  Main clock oscillator (MOSC) (1 to 20 MHz when VCC = 2.4 to 5.5 V) (1 to 8 MHz when VCC = 1.8 to 2.4 V) (1 to 4 MHz when VCC = 1.6 to 1.8 V)  Sub-clock oscillator (SOSC) (32.768 kHz)  High-speed on-chip oscillator (HOCO) (24, 32, 48, 64 MHz when VCC = 2.4 to 5.5 V) (24, 32, 48 MHz when VCC = 1.8 to 5.5 V) (24, 32 MHz when VCC = 1.6 to 5.5 V)  Middle-speed on-chip oscillator (MOCO) (8 MHz)  Low-speed on-chip oscillator (LOCO) (32.768 kHz)  Independent watchdog timer OCO (15 kHz)  Clock trim function for HOCO/MOCO/LOCO  Clock out support ■ General Purpose I/O Ports  Up to 84 input/output pins - Up to 3 CMOS input - Up to 81 CMOS input/output - Up to 9 input/output 5 V tolerant - Up to 2 pins high current (20 mA) ■ Operating Voltage  VCC: 1.6 to 5.5 V ■ Operating Temperature and Packages  Ta = –40°C to +85°C - 100-pin LGA (7mm × 7mm, 0.65mm pitch)  Ta = –40°C to +105°C - 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch) - 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch) - 64-pin QFN (8 mm × 8 mm, 0.4 mm pitch) - 48-pin LQFP (7mm × 7mm, 0.5mm pitch) - 48-pin QFN (7mm × 7mm, 0.5mm pitch) - 40-pin QFN (6mm × 6mm, 0.5mm pitch) High efficiency 48-MHz ARM Cortex-M4 microcontroller, 256-KB code flash memory, 32-KB SRAM, Segment LCD Controller, Capacitive Touch Sensing Unit, USB 2.0 Full-Speed, 14-Bit A/D Converter, 12-Bit D/A Converter, security and safety features. S3A6 Group MCUs (High Efficiency MCUs) 32-bit ARM® Cortex®-M4 Microcontroller

R01DS0308EU0100 Rev.1.00 Page 5 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview 1. Overview The S3A6 Group MCUs integrate multiple series of software- and pin-compatible ARM®-based 32-bit MCUs that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development. The MCU provides an optimal combination of low-power, high-performance ARM Cortex®-M4 core running up to

48 MHz with the following features:

 256-KB code flash memory  32-KB SRAM  Segment LCD Controller (SLCDC)  Capacitive Touch Sensing Unit (CTSU)  USB 2.0 Full-Speed Module (USBFS)  14-bit A/D Converter (ADC14)  12-bit D/A Converter (DAC12)  Security features.

1.1 Function Outline

Table 1.1 ARM core Feature Functional description ARM Cortex-M4  Maximum operating frequency: up to 48 MHz  ARM Cortex-M4: - Revision: r0p1-01rel0 - ARMv7E-M architecture profile - Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008  ARM Memory Protection Unit (MPU): - ARMv7 Protected Memory System Architecture - 8 protect regions  SysTick timer: - Driven by LOCO clock Table 1.2 Memory Feature Functional description Code flash memory Maximum 256 KB code flash memory. See section 44, Flash Memory in User’s Manual. Data flash memory 8 KB data flash memory. See section 44, Flash Memory in User’s Manual. Option-setting memory The option-setting memory deter mines the state of the MCU after a reset. See section 6, Option-Setting Memory in User’s Manual. SRAM On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC). An area in SRAM0 provides error correction capability using ECC. See section 43, SRAM in User’s Manual.

R01DS0308EU0100 Rev.1.00 Page 6 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview Table 1.3 System (1 of 2) Feature Functional description Operating mode Two operating modes: - Single-chip mode - SCI/USB boot mode. See section 3, Operating Modes in User’s Manual. Reset 14 types of resets:  RES pin reset  Power-on reset  VBATT selected voltage power on reset  Independent watchdog timer reset  Watchdog timer reset  Voltage monitor 0 reset  Voltage monitor 1 reset  Voltage monitor 2 reset  SRAM parity error reset  SRAM ECC error reset  Bus master MPU error reset  Bus slave MPU error reset  Stack pointer error reset  Software reset. See section 5, Resets in User’s Manual. Low Voltage Detection (LVD) The Low Voltage Detection (LVD) monitors the voltage level input to the VCC pin, and the detection level can be selected using a software program. See section 7, Low Voltage Detection (LVD) in User’s Manual. Clock  Main clock oscillator (MOSC)  Sub-clock oscillator (SOSC)  High-speed on-chip oscillator (HOCO)  Middle-speed on-chip oscillator (MOCO)  Low-speed on-chip oscillator (LOCO)  PLL frequency synthesizer  Independent watchdog timer on-chip oscillator  Clock out support. See section 8, Clock Generation Circuit in User’s Manual. Clock Frequency Accuracy Measurement Circuit (CAC) The Clock Frequency Accuracy Measurement Circuit (CAC) is used to check the system clock frequency with a reference clock signal by counting the number of pulses of the system clock to be measured. The reference clock can be provided externally through a CACREF pin or internally from various on-chip oscillators. Event signals can be generated when the clock does not match or measurement ends. This feature is particularly useful in implementing a fail-safe mechanism for home and industrial automation applications. See section 9, Clock Frequency Accuracy Measurement Circuit (CAC) in User’s Manual. Interrupt Controller Unit (ICU) The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC module and DMAC module. The ICU also controls NMI interrupts. See section 13, Interrupt Controller Unit (ICU) in User's Manual. Key Interrupt Function (KINT) A key interrupt can be generated by setting the Key Return Mode register (KRM) and inputting a rising or falling edge to the key interrupt input pins. See section 20, Key Interrupt Function (KINT) in User's Manual. Low Power Mode Power consumption can be reduced in mult iple ways, including setting clock dividers, stopping modules, selecting power control mode in normal operation, and transitioning to low power modes. See section 10, Low Power Modes in User's Manual. Battery Backup Function A battery backup function is prov ided for partial powering by a battery. The battery powered area includes RTC, SOSC, LOCO, Wakeup Control, Backup Memory, VBATT_R Low Voltage Detection, and switch between VCC and VBATT. During normal operation, the battery powered area is powered by the main power supply, the VCC pin. When a VCC voltage drop is detected, the power source is switched to the dedicated battery backup power pin, the VBATT pin. When the voltage rises again, the power source is switched from the VBATT pin to the VCC pin. See section 11, Battery Backup Function in User's Manual. Register Write Protection The register wr ite protection function protects important registers from being overwritten due to software errors. See section 12, Register Write Protection in User's Manual.

R01DS0308EU0100 Rev.1.00 Page 7 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview Memory Protection Unit (MPU) Four MPUs and a CPU stack point er monitor function are provided. See section 15, Memory Protection Unit (MPU) in User's Manual. Watchdog Timer (WDT) The Watchdog Timer (WDT) is a 14-bi t down-counter. It can be used to reset the MCU when the counter underflows because the system has run out of control and is unable to refresh the WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. A refresh-permitted period can be set to refresh the counter and used as the condition to detect when the system runs out of control. See section 25, Watchdog Timer (WDT) in User's Manual. Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the MCU or to generate a non-maskable interrupt/interrupt for a timer underflow. Because the timer operates with an independent, dedicated clock source, it is particularly useful in returning the MCU to a known state as a fail safe mechanism when the system runs out of control. The IWDT can be triggered automatically on a reset, underflow, or refresh error, or by a refresh of the count value in the registers. See section 26, Independent Watchdog Timer (IWDT) in User's Manual. Table 1.4 Event link Feature Functional description Event Link Controller (ELC) The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral modules as event signals to connect them to different modules, enabling direct interaction between the modules without CPU intervention. See section 18, Event Link Controller (ELC) in User's Manual. Table 1.5 Direct memory access Feature Functional description Data Transfer Controller (DTC) A Data Transfer Controller (D TC) module is provided for transferring data when activated by an interrupt request. See section 17, Data Transfer Controller (DTC) in User's Manual. DMA Controller (DMAC) A 4-channel DMA Controller (DMAC) m odule is provided for transferring data without the CPU. When a DMA transfer request is generated, the DMAC transfers data stored at the transfer source address to the transfer destination address. See section 16, DMA Controller (DMAC) in User's Manual. Table 1.3 System (2 of 2) Feature Functional description

R01DS0308EU0100 Rev.1.00 Page 8 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview Table 1.6 Timers Feature Functional description General PWM Timer (GPT) The General PWM Timer (GPT) is a 32-bit timer with 2 channels and a 16-bit timer with 6 channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or the up- and down-counter. In addition, PWM waveforms can be generated for controlling brushless DC motors. The GPT can also be used as a general-purpose timer. See section 22, General PWM Timer (GPT) in User's Manual. Port Output Enable for GPT (POEG) Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT) output pins in the output disable state. See section 21, Port Output Enable for GPT (POEG) in User's Manual. Asynchronous General Purpose Timer (AGT) The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse output, external pulse width or period measurement, and counting of external events. This 16-bit timer consists of a reload register and a down-counter. The reload register and the down-counter are allocated to the same address, and they can be accessed with the AGT register. See section 23, Asynchronous General Purpose Timer (AGT) in User's Manual. Realtime Clock (RTC) The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count mode, that are controlled by the register settings. For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and automatically adjusts dates for leap years. For binary count mode, the RTC counts seconds and retains the information as a serial value. Binary count mode can be used for calendars other than the Gregorian (Western) calendar. See section 24, Realtime Clock (RTC) in User's Manual. Table 1.7 Communication interfaces (1 of 2) Feature Functional description Serial Communications Interface (SCI) The Serial Communications Interface (SCI) is configurable to five asynchronous and synchronous serial interfaces:  Asynchronous interfaces (UART and asynchronous communications interface adapter (ACIA))  8-bit clock synchronous interface  Simple IIC (master-only)  Simple SPI  Smart card interface. The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and transmission protocol. SCI0 and SCI1 have FIFO buffers to enable continuous and full-duplex communication, and the data transfer speed can be configured independently using an on-chip baud rate generator. See section 28, Serial Communications Interface (SCI) in User's Manual. I 2C Bus Interface (IIC) The 3-channel IIC module conf orms with and provides a subset of the NXP I2C bus (Inter- Integrated Circuit bus) interface functions. See section 29, I2C Bus Interface (IIC) in User's Manual. Serial Peripheral Interface (SPI) Two independent Serial Periph eral Interface (SPI) channels are capable of high-speed, full- duplex synchronous serial communications with multiple processors and peripheral devices. See section 31, Serial Peripheral Interface (SPI) in User's Manual. Serial Sound Interface Enhanced (SSIE) The Serial Sound Interface Enhanced (SSIE) peripheral provides functionality to interface with digital audio devices for transmitting PCM audio data over a serial bus with this MCU. The SSIE supports an audio clock frequency of up to 50 MHz, and can be operated as a slave or master receiver, transmitter, or transceiver to suit various applications. The SSIE includes 8- stage FIFO buffers in the receiver and transmitter, and supports interrupts and DMA-driven data reception and transmission. See section 33, Serial Sound Interface Enhanced (SSIE) in User's Manual. Controller Area Network (CAN) Module The Controller Area Network (CAN) module provides functionality to receive and transmit data using a message-based protocol between multiple slaves and masters in electromagnetically noisy applications. The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are supported. See section 30, Quad Serial Peripheral Interface (QSPI) in User's Manual.

R01DS0308EU0100 Rev.1.00 Page 9 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview USB 2.0 Full-Speed Module (USBFS) The full-speed USB controller can operate as a host controller or device controller. The module supports full-speed and low-speed (host controller only) transfer as defined in the Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and supports all of the transfer types defined in the Universal Serial Bus Specification 2.0. The USB has buffer memory for data transfer, providing a maximum of 10 pipes. PIPE1 to PIPE9 can be assigned any endpoint number based on the peripheral devices used for communication or based on the user system. The MCU supports version 1.2 of the battery charging specification. Because the MCU can be powered at 5 V, the USB LDO regulator provides the internal USB transceiver power supply 3.3 V. See section 27, USB 2.0 Full-Speed Module (USBFS) in User's Manual. Table 1.8 Analog Feature Functional description 14-bit A/D Converter (ADC14) A 14-bit succ essive approximation A/D Converter is provided. Up to 25 analog input channels are selectable. Temperature sensor output and internal reference voltage are selectable for conversion. The A/D conversion accuracy is selectable from 12-bit and 14-bit conversion making it possible to optimize the tradeoff between speed and resolution in generating a digital value. See section 35, 14-Bit A/D Converter (ADC14) in User's Manual. 12-bit D/A Converter (DAC12) The DAC12 converts data and includes an output amplifier. See section 36, 12-Bit D/A Converter (DAC12) in User's Manual. 8-bit D/A Converter (DAC8) (for ACMPLP) This MCU includes a 8-bit D/A converter without an output amplifier (DAC8). The DAC8 is used only the reference voltage for ACMPLP. See section 40, 8-Bit D/A Converter (DAC8) in User's Manual. Temperature Sensor (TSN) The on-chip temperature sensor can be used to determine and monitor the die temperature for reliable operation of the device. The sensor outputs a voltage directly proportional to the die temperature, and the relationship between the die temperature and the output voltage is linear. The output voltage is provided to the ADC for conversion and can be further used by the end application. See section 37, Temperature Sensor (TSN) in User's Manual. Low-Power Analog Comparator (ACMPLP) Analog comparators can be used to compare a reference input voltage and analog input voltage. The comparison result can be read by software and also be output externally. The reference input voltage can be selected from an input to the CMPREFi(i = 0,1) pin, internal 8- bit D/A converter output, or the internal reference voltage (Vref) generated internally in the MCU. The ACMPLP response speed can be set before starting an operation. Setting high-speed mode decreases the response delay time, but increases current consumption. Setting low- speed mode increases the response delay time, but decreases current consumption. See section 39, Low Power Analog Comparator (ACMPLP) in User's Manual. Operational Amplifier (OPAMP) Operational amplifiers can be used to amplify small analog input voltages and output the amplified voltages. A total of four differential operational amplifier units with two input pins and one output pin are provided. See section 38, Operational Amplifier (OPAMP) in User's Manual. Table 1.9 Human machine interfaces Feature Functional description Segment LCD Controller (SLCDC) The SLC DC provides the following functions:  Waveform A or B selectable  The LCD driver voltage generator can switch between internal voltage boosting method, capacitor split method, and external resistance division method  Automatic output of segment and common signals based on automatic display data register read  The reference voltage generated when operating the voltage boost circuit can be selected in 16 steps (contrast adjustment)  The LCD can be made to blink. See section 45, Segment LCD Controller (SLCDC) in User's Manual. Capacitive Touch Sensing Unit (CTSU) The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the touch sensor. Changes in the electrostatic capacitance are determined by software, which enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode surface of the touch sensor is usually enclosed with an electrical conductor so that a finger does not come into direct contact with the electrode. See section 41, Capacitive Touch Sensing Unit (CTSU) in User's Manual. Table 1.7 Communication interfaces (2 of 2) Feature Functional description

R01DS0308EU0100 Rev.1.00 Page 10 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview Table 1.10 Data processing Feature Functional description Cyclic Redundancy Check (CRC) Calculator The Cyclic Redundancy Check (CRC) generates CRC codes to detect errors in the data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first communication. Additionally, various CRC generation polynomials are available. The snoop function allows monitoring reads from and writes to specific addresses. This function is useful in applications that require CRC code to be generated automatically in certain events, such as monitoring writes to the serial transmit buffer and reads from the serial receive buffer. See section 32, Cyclic Redundancy Check (CRC) Calculator in User's Manual. Data Operation Circuit (DOC) The Data Op eration Circuit (DOC) compares, adds, and subtracts 16-bit data. See section 42, Data Operation Circuit (DOC) in User's Manual. Table 1.11 Security Feature Functional description Secure Crypto Engine 5 (SCE5)  Security algorithm: - Symmetric algorithm: AES  Other support features: - TRNG (True Random Number Generator) - Hash-value generation: GHASH

R01DS0308EU0100 Rev.1.00 Page 11 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview

1.2 Block Diagram

Figure 1.1 shows the block diagram of the MCU superset. Individual devices within the group might have a subset of the features. Figure 1.1 Block diagram Memories

256 KB Code Flash

8 KB Data Flash

32 KB SRAM

DMAC × 4 System Mode Control Power Control ICU MOSC/SOSC Clocks (H/M/L) OCO PLL Battery Backup GPT32 × 2 Timers AGT × 2 Realtime Clock CTSU ARM Cortex-M4 DSP FPU MPU NVIC System Timer Test and DBG I/F Bus MPU DTC WDT/IWDT CAC POR/LVD Reset Human Machine Interfaces SLCDC ELC Event Link SCE5 Security Analogs CRC Data Processing DOC Communication Interfaces IIC × 2 SPI × 2 CAN × 1 SSIE × 1 USBFS with Battery Charging version1.2 SCI × 4 TSN DAC12 ACMPLP × 2 ADC14 OPAMP × 4 GPT16 × 6 DAC8 KINT Register Write Protection

R01DS0308EU0100 Rev.1.00 Page 12 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview

1.3 Part Numbering

Figure 1.2 shows how to read the product part number, memory capacity, and package type. Table 1.12 shows a list of products. Figure 1.2 Part numbering scheme Table 1.12 Product list Product part number Orderable part number Package code Code flash Data flash SRAM Operating Temperature R7FS3A6783A01CFP R7FS3A6783A01CFP#AA0 PLQP0100KB-B 256 KB 8 KB 32 KB -40 to +105°C R7FS3A6782A01CLJ R7FS3A6782A01CLJ#AC0 PTLG0100JA-A -40 to +85°C R7FS3A6783A01CFM R7FS3A6783A01CFM#AA0 PLQP0064KB-C -40 to +105°C R7FS3A6783A01CNB R7FS3A6783A01CNB#AC0 PWQN0064LA-A -40 to +105°C R7FS3A6783A01CFL R7FS3A6783A01CFL#AA0 PLQP0048KB-B -40 to +105°C R7FS3A6783A01CNE R7FS3A6783A01CNE#AC0 PWQN0048KB-A -40 to +105°C R7FS3A6783A01CNF R7FS3A6783A01CNF#AC0 PWQN0040KC-A -40 to +105°C R 7 F S 3 A 6 7 Package type FP: LQFP 100 pins FM: LQFP 64 pins FL: LQFP 48 pins LJ: LGA 100 pins NB: QFN 64 pins NE: QFN 48 pins NF: QFN 40 pins Quality ID Software ID Operating temperature 2: -40° C to 85° C 3: -40° C to 105° C Code flash memory size 8: 256 KB Feature set 7: Superset Group name 6: S3A6 Core A: ARM ® Cortex®-M4 Series name 3: High efficiency Renesas Synergy™ family Flash memory Renesas microcontroller Renesas 8 3 A 0 1 C F P #AA 0 Production identification code Packing, Terminal material (Pb-free) #AA: Tray/Sn(Tin) only #AC: Tray/others

R01DS0308EU0100 Rev.1.00 Page 13 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview

1.4 Function Comparison

Table 1.13 Function comparison Parts number R7FS3A6783A01CFP R7FS3A6782A01CLJ R7FS3A6783A01CFM/ R7FS3A6783A01CNB R7FS3A6783A01CFL/ R7FS3A6783A01CNE R7FS3A6783A01CNF Pin count 100 100 64 48 40 Package LQFP LGA LQFP/QFN LQFP/QFN QFN Code flash memory 256 KB Data flash memory 8 KB SRAM 32 KB Parity 16 KB ECC 16 KB System CPU clock 48 MHz Backup registers 512 bytes ICU Yes KINT 85 3 Event control ELC Yes DMA DTC Yes DMAC 4 BUS External bus No Timers GPT32 2 GPT16 64 2 AGT 2N o RTC Yes WDT/IWDT Yes Communication SCI 4 IIC 2 SPI 21 SSIE 1N o QSPI No SDHI No CAN 1 USBFS Yes Analog ADC14 25 18 14 11 DAC12 1 DAC8 2 ACMPLP 21 TSN Yes HMI SLCDC 4 com × 34 seg and 4 com/seg 4 com × 17 seg and 4 com/seg No CTSU 27 24 15 10 Data processing CRC Yes DOC Yes Security SCE5

R01DS0308EU0100 Rev.1.00 Page 14 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview

1.5 Pin Functions

Table 1.14 Pin functions (1 of 4) Function Signal I/O Description Power supply VCC Input Power supply pin. Connect it to the system power supply. Connect this pin to VSS by a 0.1-μF capacitor. The capacitor should be placed close to the pin. VCL I/O Connect this pin to the VSS pin by t he smoothing capacitor used to stabilize the internal power supply. Place the capacitor close to the pin. VSS Input Ground pin. Connect it to the system power supply (0 V). VBATT Input Backup power pin Clock XTAL Output Pins for a crystal resonator. An external clock signal can be input through the EXTAL pinEXTAL Input XCIN Input Input/output pins for the sub-cloc k oscillator. Connect a crystal resonator between XCOUT and XCIN.XCOUT Output CLKOUT Output Clock output pin Operating mode control MD Input Pins for setting the operating mode. The signal levels on these pins must not be changed during operation mode transition at the time of release from the reset state. System control RES Input Reset signal input pin. The MCU enters the reset state when this signal goes low. CAC CACREF Input Measurement reference clock input pin Interrupt NMI Input Non-maskable interrupt request pin IRQ0 to IRQ12, IRQ14, IRQ15 Input Maskable interrupt request pins KINT KR00 to KR07 Input A key interrupt can be generated by inputting a falling edge to the key interrupt input pins On-chip debug TMS I/O On-chip emulator or boundary scan pins TDI Input TCK Input TDO Output SWDIO I/O Serial wire debug data input/output pin SWCLK Input Serial wire clock pin SWO Output Serial wire trace output pin Battery Backup VBATWIO0 to VBATWIO2 I/O Output wakeup signal for the VBATT wakeup control function. External event input for the VBATT wakeup control function. GPT GTETRGA, GTETRGB Input External trigger input pin GTIOC0A to GTIOC7A, GTIOC0B to GTIOC7B I/O Input capture, output capture, or PWM output pin GTIU Input Hall sensor input pin U GTIV Input Hall sensor input pin V GTIW Input Hall sensor input pin W GTOUUP Output 3-phase PWM output for BLDC motor control (positive U phase) GTOULO Output 3-phase PWM output for BLDC motor control (negative U phase) GTOVUP Output 3-phase PWM output for BLDC motor control (positive V phase) GTOVLO Output 3-phase PWM output for BLDC motor control (negative V phase) GTOWUP Output 3-phase PWM output for BLDC motor control (positive W phase) GTOWLO Output 3-phase PWM output for BLDC motor control (negative W phase)

R01DS0308EU0100 Rev.1.00 Page 15 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview AGT AGTEE0, AGTEE1 Input External event input enable AGTIO0, AGTIO1 I/O External event input and pulse output AGTO0, AGTO1 Output Pulse output AGTOA0, AGTOA1 Output Output compare match A output AGTOB0, AGTOB1 Output Output compare match B output RTC RTCOUT Output Output pin for 1-Hz/64-Hz clock RTCIC0 to RTCIC2 Input Time capture event input pins SCI SCK0 to SCK2, SCK9 I/O Input/output pins for the clock (clock synchronous mode) RXD0 to RXD2, RXD9 Input Input pins for received data (async hronous mode/clock synchronous mode) TXD0 to TXD2, TXD9 Output Output pins for transmitted data (asynchronous mode/clock synchronous mode) CTS0_RTS0 to CTS2_RTS2, CTS9_RTS9 I/O Input/output pins for controlling t he start of transmission and reception (asynchronous mode/clock synchronous mode), active-low SCL0 to SCL2, SCL9 I/O Input/output pins for the IIC clock (simple IIC) SDA0 to SDA2, SDA9 I/O Input/output pins for the IIC data (simple IIC) SCK0 to SCK2, SCK9 I/O Input/output pins for the clock (simple SPI) MISO0 to MISO2, MISO9 I/O Input/output pins for slave tr ansmission of data (simple SPI) MOSI0 to MOSI2, MOSI9 I/O Input/output pins for master transmission of data (simple SPI) SS0 to SS2, SS9 Input Slave-select i nput pins (simple SPI), active-low IIC SCL0, SCL1 I/O Input/output pins for clock SDA0, SDA1 I/O Input/output pins for data SSIE SSIBCK0 I/O SSIE serial bit clock pin SSILRCK0/SSIFS0 I/O Word select pins SSITXD0 Output Serial data output pins SSIRXD0 Input Serial data input pins AUDIO_CLK Input External clock pin for audio (input oversampling clock) SPI RSPCKA, RSPCKB I/O Clock input/output pin MOSIA, MOSIB I/O Inputs or outputs data output from the master MISOA, MISOB I/O Inputs or outputs data output from the slave SSLA0, SSLB0 I/O Input or output pin for slave selection SSLA1, SSLA2, SSLA3, SSLB1, SSLB2, SSLB3 Output Output pin for slave selection CAN CRX0 Input Receive data CTX0 Output Transmit data Table 1.14 Pin functions (2 of 4) Function Signal I/O Description

R01DS0308EU0100 Rev.1.00 Page 16 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview USBFS VSS_USB Input Ground pins VCC_USB_LDO Input Power supply pin for USB LDO regulator VCC_USB I/O Input: Power supply pin for USB transceiver. Output: USB LDO regulator output pin. This pin should be connected to an external capacitor. USB_DP I/O D+ I/O pin of the USB on-chip tr ansceiver. This pin should be connected to the D+ pin of the USB bus. USB_DM I/O D– I/O pin of the USB on-chip tr ansceiver. This pin should be connected to the D– pin of the USB bus. USB_VBUS Input USB cable connection monitor pin. This pin should be connected to VBUS of the USB bus. The VBUS pin status (connected or disconnected) can be detected when the USB module is operating as a device controller. USB_EXICEN Output Low-power control signal for external power supply (OTG) chip USB_VBUSEN Output VBUS (5 V) supply enable signal for external power supply chip USB_OVRCURA, USB_OVRCURB Input External overcurrent detection si gnals should be connected to these pins. VBUS comparator signals should be connected to these pins when the OTG power supply chip is connected. USB_ID Input MicroAB connector ID input signal should be connected to this pin during operation in OTG mode. Analog power supply AVCC0 Input Analog block power supply pin AVSS0 Input Analog block pow er supply ground pin VREFH0 Input Reference power supply pin VREFL0 Input Reference power supply ground pin VREFH Input Analog reference voltage supply pin for D/A converter VREFL Input Analog reference ground pin for D/A converter ADC14 AN000 to AN014, AN016 to AN025 Input Input pins for the analog signals to be processed by the A/D converter ADTRG0 Input Input pins for the external tri gger signals that start the A/D conversion, active-low DAC12 DA0 Output Output pins for the analog si gnals to be processed by the D/A converter Comparator output VCOUT Output Comparator output pin ACMPLP CMPREF0, CMPREF1 Input Reference voltage input pin CMPIN0, CMPIN1 Input Analog voltage input pins OPAMP AMP0+ to AMP3+ Input Analog voltage input pins AMP0- to AMP3- Input Analog voltage input pins AMP0O to AMP3O Output Analog voltage output pins CTSU TS00 to TS13, TS17 to TS22, TS27 to TS31, TS34, TS35 Input Capacitive touch detec tion pins (touch pins) TSCAP — Secondary power supply pin for the touch driver Table 1.14 Pin functions (3 of 4) Function Signal I/O Description

R01DS0308EU0100 Rev.1.00 Page 17 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview I/O ports P000 to P008, P010 to P015 I/O General-purpose input/output pins P100 to P115 I/O General-purpose input/output pins P200 Input General-purpose input pin P201 to P206, P212, P213 I/O General-purpose input/output pins P214, P215 Input General-purpose input pins P300 to P307 I/O General-purpose input/output pins P400 to P415 I/O General-purpose input/output pins P500 to P505 I/O General-purpose input/output pins P600 to P603 P608 to P610 I/O General-purpose input/output pins P708 I/O General-purpose input/output pins P808, P809 I/O General-purpose input/output pins P914, P915 I/O General-purpose input/output pins SLCDC VL1, VL2, VL3, VL4 I/O Voltage pin for driving the LCD CAPH, CAPL I/O Capacitor connection pi n for the LCD controller/driver COM0 to COM7 Output Common signal output pins for the LCD controller/driver SEG00 to SEG37 Output Segment signal output pins for the LCD controller/driver Table 1.14 Pin functions (4 of 4) Function Signal I/O Description

R01DS0308EU0100 Rev.1.00 Page 18 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview

1.6 Pin Assignments

Figure 1.3 to Figure 1.6 show the pin assignments. Figure 1.3 Pin assignment for LQFP 100-pin (top view) 100 P502 P503 P504 P505 VCC VSS P015 P014 P013/VREFL P012/VREFH AVCC0 AVSS0 P010/VREFH0 P008 P007 P006 P005 P004 P003 P002 P001 P501 P011/VREFL0 P300/TCK/SWCLK P302 P303 P809 P808 P304 P305 P306 P307 P200 P201/MD RES VCC P202 P203 P204 P205 P206 VCC_USB_LDO VCC_USB P914/USB_DP P915/USB_DM VSS_USB P301 VSS P100 P102 P103 P104 P105 P106 P107 P600 P601 P602 P603 VSS VCC P609 P608 P115 P114 P113 P112 P111 P110/TDI P109/TDO/SWO P108/TMS/SWDIO P101 P610 P400 P402 P403 P404 P405 P406 VBATT VCL P215/XCIN P214/XCOUT VSS P213/XTAL VCC P708 P415 P414 P413 P412 P411 P410 P409 P407 P401 P212/EXTAL P500 P000 P408 R7FS3A6783A01CFP

R01DS0308EU0100 Rev.1.00 Page 19 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview Figure 1.4 Pin assignment for LGA 100-pin (upper perspective view) R7FS3A6782A01CLJ P407 P915/ USB_DM VCC_ USB P205 VSS P200 P305 P809 P300/ TCK/ SWCLK P108/ TMS/ SWDIO P409 P412 VCC P212/ EXTAL P215/ XCIN VCL P403 P400 P000 P914/ USB_DP P413 VSS P213/ XTAL P214/ XCOUT VBATT P405 P401 P001 VSS_ USB VCC_US B_LDO P411 P415 P708 P404 P003 P004 P002 P204 P206 P408 P414 P406 P006 P007 P008 P005 P201/MD P307 RES P113 P600 P504 AVCC0 P013/ VREFL P012/ VREFH P304 P808 P306 P115 P601 P503 P100 P015 P014 P303 P110/TDI P111 P609 P602 P107 P103 VSS VCC P302 P301 P114 P610 P603 P106 P101 P501 P502 P109/ TDO/ SWO P112 P608 VCC VSS P105 P104 P102 P500 VCC P202 P203 P410 P402 P505 AVSS0 P011/ VREFL0 P010/ VREFH0 ABCDEFGHJK ABCDEFGHJK

R01DS0308EU0100 Rev.1.00 Page 20 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview Figure 1.5 Pin assignment for LQFP 64-pin (top view) P501 P502 P015 P014 P012/VREFH AVCC0 AVSS0 P011/VREFL0 P010/VREFH0 P004 P003 P002 P001 P013/VREFL P300/TCK/SWCLK P301 P302 P303 P304 P201/MD RES P204 P205 P206 VCC_USB_LDO VCC_USB P914/USB_DP P915/USB_DM VSS_USB P200 P100 P102 P103 P104 P105 P106 P107 VSS VCC P113 P112 P111 P110/TDI P108/TMS/SWDIO P101 P109/TDO/SWO P400 P402 VBATT VCL P215/XCIN P214/XCOUT VSS P213/XTAL P212/EXTAL VCC P411 P410 P408 P407 P401 P409 P000 R7FS3A6783A01CFM P500

R01DS0308EU0100 Rev.1.00 Page 21 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview Figure 1.6 Pin assignment for QFN 64-pin (upper perspective view) P300/TCK/SWCLK P301 P302 P303 P304 P201/MD RES P204 P205 P206 VCC_USB_LDO VCC_USB P914/USB_DP P915/USB_DM VSS_USB P200 P100 P102 P103 P104 P105 P106 P107 VSS VCC P113 P112 P111 P110/TDI P108/TMS/SWDIO P101 P109/TDO/SWO P400 P402 VBATT VCL P215/XCIN P214/XCOUT VSS P213/XTAL P212/EXTAL VCC P411 P410 P408 P407 P401 P409 R7FS3A6783A01CNB 49P500 P501 P502 P015 P014 P012/VREFH AVCC0 AVSS0 P011/VREFL0 P010/VREFH0 P004 P003 P002 P001 P000 P013/VREFL

R01DS0308EU0100 Rev.1.00 Page 22 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview Figure 1.7 Pin assignment for LQFP 48-pin (top view) P500 P014 P013/VREFL P012/VREFH AVCC0 AVSS0 P011/VREFL0 P010/VREFH0 P002 P001 P015 P300/TCK/SWCLK P302 P200 P201/MD RES P206 VCC_USB_LDO VCC_USB P914/USB_DP P915/USB_DM VSS_USB P301 P100 P101 P102 P103 P104 VSS VCC P112 P111 P110/TDI P108/TMS/SWDIO P109/TDO/SWO P400 VCL P215/XCIN P214/XCOUT VSS P213/XTAL P212/EXTAL VCC P408 P407 VBATT P409 P000 R7FS3A6783A01CFL

R01DS0308EU0100 Rev.1.00 Page 23 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview Figure 1.8 Pin assignment for QFN 48-pin (top view) P300/TCK/SWCLK P302 P200 P201/MD RES P206 VCC_USB_LDO VCC_USB P914/USB_DP P915/USB_DM VSS_USB P301 P100 P102 P103 P104 VSS VCC P112 P111 P110/TDI P109/TDO/SWO P108/TMS/SWDIO P101 P400 VCL P215/XCIN P214/XCOUT VSS P213/XTAL P212/EXTAL VCC P409 P408 P407 VBATT R7FS3A6783A01CNE 37P500 P014 P013/VREFL P012/VREFH AVCC0 AVSS0 P011/VREFL0 P010/VREFH0 P002 P001 P000 P015

R01DS0308EU0100 Rev.1.00 Page 24 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview Figure 1.9 Pin assignment for QFN 40-pin (top view) P300/TCK/SWCLK P301 P200 P201/MD RES VCC_USB_LDO VCC_USB P914/USB_DP P915/USB_DM VSS_USB P100 P102 VSS VCC P112 P111 P110/TDI P109/TDO/SWO P108/TMS/SWDIO P101 VBATT P215/XCIN P214/XCOUT VSS P213/XTAL P212/EXTAL VCC P408 P407 VCL R7FS3A6783A01CNF 31P015 P014 P013/VREFL P012/VREFH AVCC0 AVSS0 P011/VREFL0 P010/VREFH0 P001 P000

R01DS0308EU0100 Rev.1.00 Page 25 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview

1.7 Pin Lists

Power, System, Clock, Debug, CAC, VBATT Interrupt I/O ports Timers Communication interfaces Analogs HMI LQFP100 LGA100 LQFP64 QFN64 LQFP48 QFN48 QFN40 AGT GPT_OPS, POEG GPT RTC USBFS,CAN SCI IIC SPI SSIE ADC14 DAC12, OPAMP ACMPLP SLCDC CTSU

1 J10 1 1 1 1 CACRE

F IRQ0 P400 AGTIO GTIOC SCK0 SCK1 SCL0 AUDIO _CLK SEG04 TS20

2 J9 2 2 IRQ5 P401 GTETR

CTX0 CTS0_ RTS0/ SS0 TXD1/ MOSI1/ SDA1 SDA0 SEG05 TS19 3F 6 33 V B A T W IO0 IRQ4 P402 AGTIO AGTIO RTCIC0 CRX0 RXD1/ MISO1/ SCL1 SEG06 TS18 4H 1 0 V B A T W IO1 P403 AGTIO AGTIO GTIOC RTCIC1 CTS1_ RTS1/ SS1 SSIBC TS17 5G 8 V B A T W IO2 P404 GTIOC RTCIC2 SSILRC K0/ SSIFS0 6H 9 P 4 0 5 G T I O C SSITXD 7F 7 P 4 0 6 G T I O C SSIRX 8G 9 44221V B A T T 9G 1 0 55332V C L 1 0 F 1 0 66443X C I N P 2 1 5 1 1 F 9 77554X C O U T P 2 1 4 1 2 D 9 88665V S S 1 3 E 9 99776X T A L I R Q 2 P 2 1 3 G T E T R GA GTIOC TXD1/ MOSI1/ SDA1

14 E10 10 10 8 8 7 EXTAL IRQ3 P212 AGTEE

15 D10 11 11 9 9 8 VCC

16 F8 P708 RXD1/

17 E8 IRQ8 P415 GTIOC

18 E7 IRQ9 P414 GTIOC

19 C9 P413 CTS0_

20 C10 P412 SCK0 RSPCK

A

21 D8 12 12 IRQ4 P411 AGTOA

P GTIOC TXD0/ MOSI0/ SDA0 MOSIA SEG07 TS07

22 E6 13 13 IRQ5 P410 AGTOB

O GTIOC RXD0/ MISO0/ SCL0 MISOA SEG08 TS06 2 3B 1 0 1 41 41 01 0 I R Q 6 P 4 0 9 G T O W UP GTIOC USB_E XICEN TXD9/ MOSI9/ SDA9 SEG09 TS05

24 D7 15 15 11 11 9 IRQ7 P408 GTOW

USB_ID CTS1_ RTS1/ SS1 RXD9/ MISO9/ SCL9 SCL0 SEG10 TS04 2 5A 1 0 1 61 61 21 21 0 P 4 0 7 A G T I O RTCOU T USB_V BUS CTS0_ RTS0/ SS0 SDA0 SSLB3 ADTRG SEG11 TS03

26 B8 17 17 13 13 11 VSS_U

27 A9 18 18 14 14 12 P915 USB_D

M

R01DS0308EU0100 Rev.1.00 Page 26 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview

28 B9 19 19 15 15 13 P914 USB_D

P

29 A8 20 20 16 16 14 VCC_U

30 C8 21 21 17 17 15 VCC_U

SB_LD O

31 C7 22 22 18 18 IRQ0 P206 GTIU USB_V

32 A7 23 23 CLKOU

T IRQ1 P205 AGTO1 GTIV GTIOC USB_O VRCUR A TXD0/ MOSI0/ SDA0 CTS9_ RTS9/ SS9 SCL1 SSLB0 SEG13 TSCAP

33 B7 24 24 CACRE

F P204 AGTIO GTIW GTIOC USB_O VRCUR B SCK0 SCK9 SCL0 RSPCK B SEG14 TS00

34 D6 P203 GTIOC

CTS2_ RTS2/ SS2 TXD9/ MOSI9/ SDA9 MOSIB SEG15 TSCAP

35 C6 P202 GTIOC

36 A6 VSS

37 B6 VCC

38 D5 25 25 19 19 16 RES

39 B5 26 26 20 20 17 MD P201

40 A5 27 27 21 21 18 NMI P200

41 C5 P307 SEG17

42 D4 P306 SEG18

43 A4 IRQ8 P305 SEG19

44 B4 28 28 IRQ9 P304 GTIOC

45 C4 P808 SEG21

46 A3 P809 SEG22

47 B3 29 29 P303 GTIOC

48 B2 30 30 22 22 IRQ5 P302 GTOUU

P GTIOC TXD2/ MOSI2/ SDA2 SSLB3 SEG02/ COM6 TS08

49 C2 31 31 23 23 19 IRQ6 P301 AGTIO

O GTIOC RXD2/ MISO2/ SCL2 CTS9_ RTS9/ SS9 SSLB2 SEG01/ COM5 TS09

50 A2 32 32 24 24 20 TCK/

P GTIOC SSLB1

51 A1 33 33 25 25 21 TMS/

O GTIOC CTS9_ RTS9/ SS9 SSLB0

52 B1 34 34 26 26 22 TDO/

T P109 GTOVU P GTIOC CTX0 SCK1 TXD9/ MOSI9/ SDA9 MOSIB SEG23 TS10

53 C3 35 35 27 27 23 TDI IRQ3 P110 GTOVL

O GTIOC CRX0 CTS2_ RTS2/ SS2 RXD9/ MISO9/ SCL9 MISOB VCOUT SEG24 Pin number Power, System, Clock, Debug, CAC, VBATT Interrupt I/O ports Timers Communication interfaces Analogs HMI LQFP100 LGA100 LQFP64 QFN64 LQFP48 QFN48 QFN40 AGT GPT_OPS, POEG GPT RTC USBFS,CAN SCI IIC SPI SSIE ADC14 DAC12, OPAMP ACMPLP SLCDC CTSU

R01DS0308EU0100 Rev.1.00 Page 27 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview

54 D3 36 36 28 28 24 IRQ4 P111 GTIOC

B CAPH TS12

55 C1 37 37 29 29 25 P112 GTIOC

56 E5 38 38 P113 GTIOC

57 D2 P114 GTIOC

58 E4 P115 GTIOC

59 D1 P608 GTIOC

60 E3 P609 GTIOC

61 E2 P610 GTIOC

62 E1 39 39 30 30 26 VCC

63 F1 40 40 31 31 27 VSS

64 F2 P603 GTIOC

CTS9_ RTS9/ SS9 SEG30

65 F3 P602 GTIOC

66 F4 P601 GTIOC

67 F5 P600 GTIOC

68 G3 41 41 KR07 P107 GTIOC

69 G2 42 42 KR06 P106 GTIOC

70 G1 43 43 KR05/

71 H1 44 44 32 32 KR04/

72 H3 45 45 33 33 KR03 P103 GTOW

CTX0 CTS0_ RTS0/ SS0 SSLA0 AN019 CMPRE VL4

73 J1 46 46 34 34 28 KR02 P102 AGTO0 GTOW

A AN020/ ADTRG CMPIN VL3

74 H2 47 47 35 35 29 KR01/

CTS1_ RTS1/ SS1 SDA1 MOSIA AN021 CMPRE VL2

75 H4 48 48 36 36 30 KR00/

76 K1 49 49 37 37 P500 AGTOA

USB_V BUSEN AN016 CMPRE SEG34

77 J2 50 50 IRQ11 P501 AGTOB

USB_O VRCUR A TXD1/ MOSI1/ SDA1 AN017 CMPIN SEG35

78 K2 51 51 IRQ12 P502 GTIW GTIOC

USB_O VRCUR B RXD1/ MISO1/ SCL1 AN018 CMPRE SEG36

79 G4 P503 USB_E

80 G5 P504 USB_ID CTS1_

81 G6 IRQ14 P505 AN025

Power, System, Clock, Debug, CAC, VBATT Interrupt I/O ports Timers Communication interfaces Analogs HMI LQFP100 LGA100 LQFP64 QFN64 LQFP48 QFN48 QFN40 AGT GPT_OPS, POEG GPT RTC USBFS,CAN SCI IIC SPI SSIE ADC14 DAC12, OPAMP ACMPLP SLCDC CTSU

R01DS0308EU0100 Rev.1.00 Page 28 of 129 Apr 4, 2017 S3A6 Group MCUs 1. Overview

82 K3 VCC

83 J3 VSS

84 J4 52 52 38 38 31 IRQ7 P015 AN010 TS28

85 K4 53 53 39 39 32 P014 AN009 DA0

86 J5 54 54 40 40 33 VREFL P013 AN008 AMP1+

87 K5 55 55 41 41 34 VREFH P012 AN007 AMP1-

88 H5 56 56 42 42 35 AVCC0

89 H6 57 57 43 43 36 AVSS0

90 J6 58 58 44 44 37 VREFL

IRQ15 P011 AN006 AMP2+ TS31

91 K6 59 59 45 45 38 VREFH

92 J7 P008 AN014

93 H7 P007 AN013 AMP3O

94 G7 P006 AN012 AMP3-

95 K7 IRQ10 P005 AN011 AMP3+

96 J8 60 60 IRQ3 P004 AN004 AMP2O

97 H8 61 61 P003 AN003 AMP1O

98 K8 62 62 46 46 IRQ2 P002 AN002 AMP0O

99 K9 63 63 47 47 39 IRQ7 P001 AN001 AMP0- TS22

100 K10 64 64 48 48 40 IRQ6 P000 AN000 AMP0+ TS21

Power, System, Clock, Debug, CAC, VBATT Interrupt I/O ports Timers Communication interfaces Analogs HMI LQFP100 LGA100 LQFP64 QFN64 LQFP48 QFN48 QFN40 AGT GPT_OPS, POEG GPT RTC USBFS,CAN SCI IIC SPI SSIE ADC14 DAC12, OPAMP ACMPLP SLCDC CTSU

R01DS0308EU0100 Rev.1.00 Page 30 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics

2.1 Absolute Maximum Ratings

Note 1. Ports P205, P206, P400 to P404, P407, P408 are 5V-tolerant. Note 2. See section 2.2.1, Tj/Ta Definition. Note 3. Contact Renesas Electronics sales office for informati on on derating operation under Ta = +85°C to +105°C. Derating is the systematic reduction of load for improved reliability. Note 4. The upper limit of operating temperature is 85°C or 105°C, depending on the product. For details, see section 1.3, Part Numbering. Caution: Permanent damage to the MCU may result if absolute maximum ratings are exceeded. To preclude any malfunctions due to noise interference, insert capacitors of high frequency characteristics between the VCC and VSS pins, between the AVCC0 and AVSS0 pins, between the VCC_USB and VSS_USB pins, between the VREFH0 and VREFL0 pins, and between the VREFH and VREFL pins. Place capacitors of about 0.1 μF as close as possible to every power supply pin and use the shortest and heaviest possible traces. Also, connect capacitors as stabilization capacitance. Connect the VCL pin to a VSS pin by a 4.7 µF capacitor. The capacitor must be placed close to the pin. Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up might cause malfunction and the abnormal current that passes in the device at this time might cause degradation of internal elements. Table 2.1 Absolute maximum ratings Parameter Symbol Value Unit Power supply voltage VCC –0.5 to +6.5 V Input voltage 5V-tolerant ports* 1 Vin –0.3 to +6.5 V P000 to P008, P010 to P015 V in –0.3 to AVCC0 + 0.3 V Others V in –0.3 to VCC + 0.3 V Reference power supply voltage VREFH0 –0.3 to +6.5 V VREFH V VBATT power supply voltage VBATT –0.5 to +6.5 V Analog power supply voltage AVCC0 –0.5 to +6.5 V USB power supply voltage VCC_USB –0.5 to +6.5 V VCC_USB_LDO –0.5 to +6.5 V Analog input voltage When AN000 to AN014 are used V AN –0.3 to AVCC0 + 0.3 V When AN016 to AN025 are used –0.3 to VCC + 0.3 V LCD voltage VL1 voltage V L1 –0.3 to +2.8 V VL2 voltage V L2 –0.3 to +6.5 V VL3 voltage V L3 –0.3 to +6.5 V VL4 voltage V L4 –0.3 to +6.5 V Operating temperature*2,*3,*4 Topr –40 to +105 °C –40 to +85 Storage temperature T stg –55 to +125 °C

R01DS0308EU0100 Rev.1.00 Page 31 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note 1. Use AVCC0 and VCC under the following conditions: AVCC0 and VCC can be set individually within the operating range when VCC ≥ 2.2 V and AVCC0 ≥ 2.2 V. AVCC0 = VCC when VCC < 2.2 V or AVCC < 2.2 V. Note 2. When powering on the VCC and AVCC0 pins, power them on at the same time or the VCC pin first and then the AVCC0 pin. Table 2.2 Recommended operating conditions Parameter Symbol Value Min Typ Max Unit Power supply voltages VCC *1, *2 When USBFS is not used 1.6 - 5.5 V When USBFS is used USB Regulator Disable VCC_USB - 3.6 V When USBFS is used USB Regulator Enable VCC_USB _LDO -5 . 5 V V S S -0 -V USB power supply voltages VCC_USB When USBFS is not used -V C C -V When USBFS is used USB Regulator Disable (Input) 3.0 3.3 3.6 V VCC_USB_LDO When USBFS is not used -V C C -V When USBFS is used USB Regulator Disable -V C C -V When USBFS is used USB Regulator Enable 3.8 - 5.5 V V S S _ U S B -0 -V VBATT power supply voltage VBATT When the battery backup function is not used -V C C -V When the battery backup function is used 1.6 - 3.6 V Analog power supply voltages AVCC0 *1, *2 1.6 - 5.5 V AVSS0 - 0 - V VREFH0 When used as ADC14 Reference 1.6 - AVCC0 V VREFL0 - 0 - V VREFH When used as DAC12 Reference 1.6 - AVCC0 V VREFL - 0 - V

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2.2 DC Characteristics

2.2.1 Tj/Ta Definition

Note: Make sure that Tj = T a + θja × total power consumption (W), where total power consumption = (VCC – VOH) × ΣIOH + VOL × ΣIOL + ICCmax × VCC. Note 1. The upper limit of operating temperature is 85° C or 105°C, depending on the product. For details, see section 1.3, Part Numbering. If the part number shows the operation temperature at 85°C, then the maximum value of Tj is 105°C, otherwise, it is 125°C.

2.2.2 I/O V IH, VIL

Note 1. P205, P206, P400, P401, P407, P408 (total 6 pins). Note 2. P100, P101, P204, P205, P206, P400, P401, P407, P408 (total 9 pins). Note 3. P205, P206, P400 to P404, P407, P408 (total 9 pins). Table 2.3 DC Characteristics Conditions: Products with operating temperature (Ta) –40 to +105°C Parameter Symbol Typ Max Unit Test conditions Permissible junction temperature Tj - 125 °C High-speed mode Middle-speed mode Low-voltage mode Low-speed mode Subosc-speed mode 105* Table 2.4 I/O V IH, VIL (1) Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LDO = 2.7 to 5.5V, VBATT = 1.6 to 3.6 V, VSS = AVSS0 = 0 V Parameter Symbol Min Typ Max Unit Test conditions Schmitt trigger input voltage IIC*1 (except for SMBus) V IH VCC × 0.7 - 5.8 V - VIL -- V C C × 0 . 3 ∆VT VCC × 0.05 - - RES, NMI Other peripheral input pins excluding IIC VIH VCC × 0.8 - - VIL - - VCC × 0.2 ∆VT VCC × 0.1 - - Input voltage (except for Schmitt trigger input pin) IIC (SMBus)*2 VIH 2.2 - - VCC = 3.6 to 5.5 V VIH 2.0 - - VCC = 2.7 to 3.6 V VIL -- 0 . 8 - 5V-tolerant ports*3 VIH VCC × 0.8 - 5.8 VIL - - VCC × 0.2 P914, P915 V IH VCC_USB × 0.8 - VCC_USB + 0.3 VIL -- V C C _ U S B × 0 . 2 P000 to P008, P010 to P015 V IH AVCC0 × 0.8 - - VIL -- A V C C 0 × 0 . 2 EXTAL Input ports pins except for P000 to P008, P010 to P015, P914, P915 VIH VCC × 0.8 - - VIL - - VCC × 0.2 When VBATT power supply is selected P402, P403, P404 V IH VBATT × 0.8 - V BATT + 0.3 VIL -- V BATT × 0.2 ∆VT VBATT × 0.05 - -

R01DS0308EU0100 Rev.1.00 Page 33 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note 1. P205, P206, P400 to P404, P407, P408 (total 9 pins) Table 2.5 I/O V IH, VIL (2) Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LDO = 1.6 to 2.7 V, VBATT = 1.6 to 3.6 V, VSS = AVSS0 = 0 V Parameter Symbol Min Typ Max Unit Test conditions Schmitt trigger input voltage RES, NMI Peripheral input pins VIH VCC × 0.8 - - V - VIL - - VCC × 0.2 ∆VT VCC × 0.01 - - Input voltage (except for Schmitt trigger input pin) 5V-tolerant ports* 1 VIH VCC × 0.8 - 5.8 VIL - - VCC × 0.2 P914, P915 V IH VCC_USB × 0.8 - VCC_USB + 0.3 VIL - - VCC_USB × 0.2 P000 to P008, P010 to P015 V IH AVCC0 × 0.8 - - VIL - - AVCC0 × 0.2 EXTAL Input ports pins except for P000 to P008, P010 to P015, P914, P915 VIH VCC × 0.8 - - VIL - - VCC × 0.2 When VBATT power supply is selected P402, P403, P404 V IH VBATT × 0.8 - V BATT + 0.3 VIL -- V BATT × 0.2 ∆VT VBATT × 0.01 - -

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2.2.3 I/O I OH, IOL

Table 2.6 I/O I OH, IOL (1 of 2) Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LCO = 1.6 to 5.5 V Parameter Symbol Min Typ Max Unit Permissible output current (average value per pin) Ports P212, P213 - IOH --– 4 . 0 m A IOL - - 4.0 mA Port P408 Low drive* 1 IOH --– 4 . 0 m A IOL - - 4.0 mA Middle drive for IIC Fast-mode*4 VCC = 2.7 to 5.5 V IOH --– 8 . 0 m A IOL - - 8.0 mA Middle drive*2 VCC = 3.0 to 5.5 V IOH - - –20.0 mA IOL --2 0 . 0 m A Port P409 Low drive *1 IOH --– 4 . 0 m A IOL - - 4.0 mA Middle drive*2 VCC = 2.7 to 3.0 V IOH --– 8 . 0 m A IOL - - 8.0 mA Middle drive*2 VCC = 3.0 to 5.5 V IOH - - –20.0 mA IOL --2 0 . 0 m A Ports P100 to P115, P201 to P204, P300 to P307, P500 to P503, P600 to P603, P608 to P610, P808, P809 (total 41 pins) Low drive *1 IOH --– 4 . 0 m A IOL - - 4.0 mA Middle drive*2 IOH --– 4 . 0 m A IOL - - 8.0 mA Ports P914, P915 - IOH - - –4.0 mA IOL - - 4.0 mA Other output pin*3 Low drive*1 IOH --– 4 . 0 m A IOL - - 4.0 mA Middle drive*2 IOH --– 8 . 0 m A IOL - - 8.0 mA

R01DS0308EU0100 Rev.1.00 Page 35 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Caution: To protect the reliability of the MCU, the output cu rrent values should not exceed the values in this table. The average output current indicates the average value of current measured during 100 μs. Note 1. This is the value when low drivi ng ability is selected with the Port Drive Capability bit in PmnPFS register. Note 2. This is the value when middle driv ing ability is selected with the Port Drive Capability bit in PmnPFS register. Note 3. Except for ports P200, P214, P215, which are input ports. Note 4. This is the value when middle driv ing ability for IIC Fast-mode is selected with the Port Drive Capability bit in PmnPFS register. Note 5. For details on the permissible output current used with CTSU, see section 2.11, CTSU Characteristics. Permissible output current (Max value per pin) Ports P212, P213 - IOH --– 4 . 0 m A IOL - - 4.0 mA Port P408 Low drive* 1 IOH --– 4 . 0 m A IOL - - 4.0 mA Middle drive for IIC Fast-mode*4 VCC = 2.7 to 5.5 V IOH --– 8 . 0 m A IOL - - 8.0 mA Middle drive*2 VCC = 3.0 to 5.5 V IOH - - –20.0 mA IOL --2 0 . 0 m A Port P409 Low drive *1 IOH --– 4 . 0 m A IOL - - 4.0 mA Middle drive*2 VCC = 2.7 to 3.0 V IOH --– 8 . 0 m A IOL - - 8.0 mA Middle drive*2 VCC = 3.0 to 5.5 V IOH - - –20.0 mA IOL --2 0 . 0 m A Ports P100 to P115, P201 to P204, P300 to P307, P500 to P503, P600 to P603, P608 to P610, P808, P809 (total 41 pins) Low drive*1 IOH --– 4 . 0 m A IOL - - 4.0 mA Middle drive*2 IOH --– 4 . 0 m A IOL - - 8.0 mA Ports P914, P915 - IOH - - –4.0 mA IOL - - 4.0 mA Other output pin*3 Low drive*1 IOH --– 4 . 0 m A IOL - - 4.0 mA Middle drive*2 IOH --– 8 . 0 m A IOL - - 8.0 mA Permissible output current (max value total pins) Total of ports P000 to P008, P010 to P015 ΣIOH (max) --– 3 0 m A ΣIOL (max) --3 0m A Ports P914, P915 ΣIOH (max) --– 2 . 0 m A ΣIOL (min) - - 2.0 mA Total of all output pin*5 ΣIOH (max) --– 6 0 m A ΣIOL (max) --6 0m A Table 2.6 I/O I OH, IOL (2 of 2) Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LCO = 1.6 to 5.5 V Parameter Symbol Min Typ Max Unit

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2.2.4 I/O V OH, VOL, and Other Characteristics

Note 1. P100, P101, P204, P205, P206, P400, P401, P407, P408 (total 9 pins). Note 2. This is the value when middle driv ing ability is selected with the Port Drive Capability bit in PmnPFS register. Note 3. Based on characterization data, not tested in production. Note 4. Except for ports P200, P214, P215, which are input ports. Note 5. This is the value when mi ddle driving ability for IIC is selected with the Port Drive Capability bit in PmnPFS register for P408. Note 6. Except for P212, P213. Note 1. P100, P101, P204, P205, P206, P400, P401, P407, P408 (total 9 pins). Note 2. This is the value when middle driv ing ability is selected with the Port Drive Capability bit in PmnPFS register. Note 3. Based on characterization data, not tested in production. Note 4. Except for ports P200, P214, P215, which are input ports. Note 5. This is the value when mi ddle driving ability for IIC is selected with the Port Drive Capability bit in PmnPFS register for P408. Note 6. Except for P212, P213. Table 2.7 I/O V OH, VOL (1) Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LCO = 4.0 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions Output voltage IIC* 1 VOL -- 0 . 4 V I OL = 3.0 mA VOL*2,*5 -- 0 . 6 I OL = 6.0 mA Ports P408, P409*2, *3 VOH VCC – 1.0 - - I OH = –20 mA VOL -- 1 . 0 I OL = 20 mA Ports P000 to P008, P010 to P015 Low drive V OH AVCC0 – 0.8 - - I OH = –2.0 mA VOL -- 0 . 8 I OL = 2.0 mA Middle drive V OH AVCC0 – 0.8 - - I OH = –4.0 mA VOL -- 0 . 8 I OL = 4.0 mA Ports P914, P915 V OH VCC_USB – 0.8 - - I OH = –2.0 mA VOL -- 0 . 8 I OL = 2.0 mA Other output pins*4 Low drive V OH VCC – 0.8 - - I OH = –2.0 mA VOL -- 0 . 8 I OL = 2.0 mA Middle drive*6 VOH VCC – 0.8 - - I OH = –4.0 mA VOL -- 0 . 8 I OL = 4.0 mA Table 2.8 I/O V OH, VOL (2) Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LCO = 2.7 to 4.0 V Parameter Symbol Min Typ Max Unit Test conditions Output voltage IIC* 1 VOL -- 0 . 4 V I OL = 3.0 mA VOL*2,*5 -- 0 . 6 I OL = 6.0 mA Ports P408, P409*2, *3 VOH VCC – 1.0 - - I OH = –20 mA VCC = 3.3 V VOL -- 1 . 0 I OL = 20 mA VCC = 3.3 V Ports P000 to P008, P010 to P015 Low drive V OH AVCC0 – 0.5 - - I OH = –1.0 mA VOL -- 0 . 5 I OL = 1.0 mA Middle drive V OH AVCC0 – 0.5 - - I OH = –2.0 mA VOL -- 0 . 5 I OL = 2.0 mA Ports P914, P915 V OH VCC_USB – 0.5 - - I OH = –1.0 mA VOL -- 0 . 5 I OL = 1.0 mA Other output pins*4 Low drive V OH VCC – 0.5 - - I OH = –1.0 mA VOL -- 0 . 5 I OL = 1.0 mA Middle drive*6 VOH VCC – 0.5 - - I OH = –2.0 mA VOL -- 0 . 5 I OL = 2.0 mA

R01DS0308EU0100 Rev.1.00 Page 37 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note 1. Except for ports P200, P214, P215, which are input ports. Note 2. Except for P212, P213. Table 2.9 I/O V OH, VOL (3) Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LCO = 1.6 to 2.7 V Parameter Symbol Min Typ Max Unit Test conditions Output voltage Ports P000 to P015 Low drive V OH AVCC0 – 0.3 - - V I OH = –0.5 mA VOL -- 0 . 3 I OL = 0.5 mA Middle drive V OH AVCC0 – 0.3 - - I OH = –1.0 mA VOL -- 0 . 3 I OL = 1.0 mA Ports P914, P915 V OH VCC_USB – 0.3 - - I OH = –0.5 mA VOL -- 0 . 3 I OL = 0.5 mA Other output pins*1 Low drive V OH VCC – 0.3 - - I OH = –0.5 mA VOL -- 0 . 3 I OL = 0.5 mA Middle drive*2 VOH VCC – 0.3 - - I OH = –1.0 mA VOL -- 0 . 3 I OL = 1.0 mA Table 2.10 I/O other characteristics Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions Input leakage current RES, P200, P214, P215 | I in | - - 1.0 μAV in = 0 V Vin = VCC Three-state leakage current (off state) 5V-tolerant ports | I TSI | - - 1.0 μAV in = 0 V Vin = 5.8 V Other ports (except for ports P200, P214, P215 and 5 V tolerant) -- 1 . 0 V in = 0 V Vin = VCC Input pull-up resistor All ports (except for ports P200, P214, P215, P914, P915) RU 10 20 50 k Ω Vin = 0 V Input capacitance P914, P915, P100 to P103, P111, P112, P200 Cin - - 30 pF V in = 0 V f = 1 MHz Ta = 25°C Other input pins - - 15

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2.2.5 I/O Pin Output Characte ristics of Low Drive Capacity

Figure 2.2 V OH/VOL and IOH/IOL Voltage Characteristics at Ta = 25°C when low drive output is selected (reference data) Figure 2.3 V OH/VOL and IOH/IOL temperature characteristics at VCC = 1.6 V when low drive output is selected (reference data) 0123456 -60 -50 -40 -30 -20 -10 I OH/IOL vs VOH/VOL VOH/VOL [V] IOH/IOL [mA] VCC = 5.5 V VCC = 3.3 V VCC = 2.7 V VCC = 1.6 V VCC = 1.6 V VCC = 2.7 V VCC = 3.3 V VCC = 5.5 V IOH/IOL vs VOH/VOL VOH/VOL [V] IOH/IOL [mA] Ta = -40°C Ta = 105°C Ta = 25°C Ta = 105°C Ta = -40°C Ta = 25°C

R01DS0308EU0100 Rev.1.00 Page 40 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Figure 2.6 V OH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when low drive output is selected (reference data)

2.2.6 I/O Pin Output Characteri stics of Middle Drive Capacity

Figure 2.7 V OH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when middle drive output is selected (reference data) 0123456 -60 -40 -20 I OH/IOL vs VOH/VOL VOH/VOL [V] IOH/IOL [mA] Ta = -40°C Ta = 105°C Ta = 25°C Ta = 105°C Ta = -40°C Ta = 25°C 0123456 -140 -120 -100 -80 -60 -40 -20 100 120 140 I OH/IOL vs VOH/VOL VOH/VOL [V] IOH/IOL [mA] VCC = 5.5 V VCC = 3.3 V VCC = 2.7 V VCC = 1.6 V VCC = 1.6 V VCC = 2.7 V VCC = 3.3 V VCC = 5.5 V

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2.2.7 P408, P409 I/O Pin Ou tput Characteristics of Middle Drive Capacity

Figure 2.12 V OH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when middle drive output is selected (reference data) Figure 2.13 V OH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when middle drive output is selected (reference data) 0123456 IOH/IOL vs VOH/VOL VOH/VOL [V] IOH/IOL [mA] VCC = 5.5 V VCC = 3.3 V VCC = 2.7 V VCC = 2.7 V VCC = 3.3 V VCC = 5.5 V -140 -120 -100 -80 -60 -40 -20 100 120 140 200 180 160 -160 -180 -200 0 0.5 1 1.5 2 2.5 3 -60 -40 -20 IOH/IOL vs VOH/VOL VOH/VOL [V] IOH/IOL [mA] Ta = -40°C Ta = 105°C Ta = 25°C Ta = 105°C Ta = -40°C Ta = 25°C

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2.2.8 IIC I/O Pin Out put Characteristics

Figure 2.16 V OH/VOL and IOH/IOL voltage characteristics at Ta = 25°C 0123456 100 110 120 I OL vs VOL VOL [V] IOL [mA] VCC = 2.7V (Low drive) VCC = 3.3V (Low drive) VCC = 5.5V (Low drive) VCC = 5.5 V (Middle drive) VCC = 3.3V (Middle drive) VCC = 2.7V (Middle drive)

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2.2.9 Operating and Standby Current

Table 2.11 Operating and standby current (1) (1 of 2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter Symbol Typ* 10 Max Unit Test conditions Supply current*1 High-speed mode Normal mode All peripheral clock disabled, while (1) code executing from flash*5 ICLK = 48 MHz I CC 8.3 - mA *7 ICLK = 32 MHz 5.8 - ICLK = 16 MHz 3.5 - ICLK = 8 MHz 2.2 - All peripheral clock disabled, CoreMark code executing from flash*5 ICLK = 48 MHz 16.4 - ICLK = 32 MHz 11.3 - ICLK = 16 MHz 6.4 - ICLK = 8 MHz 4.0 - All peripheral clock enabled, while (1) code executing from flash ICLK = 48 MHz 18.5 - *9 ICLK = 32 MHz 13.8 - *8 ICLK = 16 MHz 7.7 - ICLK = 8 MHz 4.5 - All peripheral clock enabled, code executing from SRAM ICLK = 48 MHz - 50.0 *9 Sleep mode All peripheral clock disabled*5 ICLK = 48 MHz 3.3 - *7 ICLK = 32 MHz 2.4 - ICLK = 16 MHz 1.8 - ICLK = 8 MHz 1.4 - All peripheral clock enabled*5 ICLK = 48 MHz 13.4 - *9 ICLK = 32 MHz 10.4 - *8 ICLK = 16 MHz 6.0 - ICLK = 8 MHz 3.6 - Increase during BGO operation*6 2.5 - - Middle-speed mode*2 Normal mode All peripheral clock disabled, while (1) code executing from flash ICLK = 12 MHz I CC 2.5 - mA *7 ICLK = 8 MHz 2.0 - ICLK = 1 MHz 0.9 - All peripheral clock disabled, CoreMark code executing from flash ICLK = 12 MHz 4.7 - ICLK = 8 MHz 3.7 - ICLK = 1 MHz 1.2 - All peripheral clock enabled, while (1) code executing from flash ICLK = 12 MHz 5.7 - *8 ICLK = 8 MHz 4.3 - ICLK = 1 MHz 1.5 - All peripheral clock enabled, code executing from SRAM ICLK = 12 MHz - 20.0 Sleep mode All peripheral clock disabled*5 ICLK = 12 MHz 1.2 - *7 ICLK = 8 MHz 1.2 - ICLK = 1 MHz 0.8 - All peripheral clock enabled*5 ICLK = 12 MHz 4.4 - *8 ICLK = 8 MHz 3.4 - ICLK = 1 MHz 1.4 - Increase during BGO operation*6 2.5 - -

R01DS0308EU0100 Rev.1.00 Page 47 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note 1. Supply current values do not include output charge/dischar ge current from all pins. The values apply when internal pull-up MOSs are in the off state. Note 2. The clock source is HOCO. Note 3. The clock source is MOCO. Note 4. The clock source is the sub-clock oscillator. Note 5. This does not include BGO operation. Note 6. This is the increase for programming or erasure of the ROM or flash memory for data storage during program execution. Note 7. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64. Note 8. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are the same frequency as that of ICLK. Note 9. FCLK and PCLKB are set to divided by 2 and PCLKA, PCLKC, and PCLKD are the same frequency as that of ICLK. Note 10. VCC = 3.3 V. Supply current*1 Low-speed mode Normal mode All peripheral clock disabled, while (1) code executing from flash*5 ICLK = 1 MHz I CC 0.4 - mA *7 All peripheral clock disabled, CoreMark code executing from flash*5 ICLK = 1 MHz 0.6 - All peripheral clock enabled, while (1) code executing from flash*5 ICLK = 1 MHz 1.0 - *8 All peripheral clock enabled, code executing from SRAM*5 ICLK = 1 MHz - 2.2 Sleep mode All peripheral clock disabled*5 ICLK = 1 MHz 0.3 - *7 All peripheral clock enabled*5 ICLK = 1 MHz 0.9 - *8 Low-voltage mode Normal mode All peripheral clock disabled, while (1) code executing from flash ICLK = 4 MHz I CC 1.7 - mA *7 All peripheral clock disabled, CoreMark code executing from flash ICLK = 4 MHz 2.8 - All peripheral clock enabled, while (1) code executing from flash ICLK = 4 MHz 3.0 - *8 All peripheral clock enabled, code executing from SRAM ICLK = 4 MHz - 8.0 Sleep mode All peripheral clock disabled*5 ICLK = 4 MHz 1.3 - *7 All peripheral clock enabled ICLK = 4 MHz 2.5 - *8 Subosc- speed mode*4 Normal mode All peripheral clock disabled, while (1) code executing from flash*5 ICLK = 32.768 kHz I CC 8.5 - μA *8 All peripheral clock enabled, while (1) code executing from flash*5 ICLK = 32.768 kHz 14.9 - All peripheral clock enabled, code executing from SRAM*5 ICLK = 32.768 kHz - 83.0 Sleep mode All peripheral clock disabled*5 ICLK = 32.768 kHz 5.0 - All peripheral clock enabled*5 ICLK = 32.768 kHz 11.4 - Table 2.11 Operating and standby current (1) (2 of 2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter Symbol Typ* 10 Max Unit Test conditions

R01DS0308EU0100 Rev.1.00 Page 48 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Figure 2.17 Voltage dependency in high-speed operating mode (reference data) ICC (mA) VCC (V) Ta = 105 C Ta = 105 C Ta = 105 C Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the actual measurements of the sample cores during product evaluation . Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the actual measurements for the upper- limit samples during product evaluation. , ICLK = 48 MHz , ICLK = 8 MHz , ICLK = 48 MHz *1 Ta = 25 C , ICLK = 32 MHz *1 Ta = 25 C, ICLK = 16 MHz *1 Ta = 25 C Ta = 25 C, ICLK = 4 MHz *1 Ta = 25 C Ta = 25 C *1 , ICLK = 32 MHzTa = 25 C Ta = 105 C , ICLK = 16 MHz*2 , ICLK = 48 MHz*2Ta = 105 C , ICLK = 32 MHz*2Ta = 105 C Ta = 105 C *2 Ta = 105 C , ICLK = 16 MHz*1Ta = 25 C , ICLK = 4 MHz*2 , ICLK = 8 MHz*1Ta = 25 C , ICLK = 4 MHz*1Ta = 25 C , ICLK = 48 MHz *2 , ICLK = 32 MHz *2 , ICLK = 16 MHz *2 , ICLK = 8 MHz *2 , ICLK = 4 MHz *2 Ta = 105 C Ta = 105 C, ICLK = 8 MHz *1

R01DS0308EU0100 Rev.1.00 Page 49 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Figure 2.18 Voltage dependency in middle-speed operating mode (reference data) ICC (mA) VCC (V) Note 1. All peripheral operations except any BGO operation are operating normally . This is the average of the actual measurements of the sample cores during product evaluation . Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the actual measurements for the upper- limit samples during product evaluation. , ICLK = 12 MHz*2Ta = 105 C , ICLK = 8 MHz*2Ta = 105 C , ICLK = 12 MHzTa = 25 C *1 Ta = 105 C , ICLK = 4 MHz*2 , ICLK = 8 MHz*1Ta = 25 C , ICLK = 4 MHz*1Ta = 25 C , ICLK = 1 MHz*2Ta = 105 C Ta = 25 C, ICLK = 1 MHz*1 Ta = 105 C Ta = 105 C Ta = 25 C Ta = 25 C Ta = 25 C, ICLK = 4 MHz *1 Ta = 25 C, ICLK = 1 MHz *1  , ICLK = 12 MHz *2 , ICLK = 8 MHz *2 , ICLK = 4 MHz *2 , ICLK = 1 MHz *2 Ta = 105 C Ta = 105 C , ICLK = 12 MHz *1 , ICLK = 8 MHz *1

R01DS0308EU0100 Rev.1.00 Page 51 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Figure 2.21 Voltage dependency in subosc-speed mode (reference data) Note 1. Supply current values do not include output charge/dischar ge current from all pins. The values apply when internal pull-up MOSs are in the off state. Note 2. The IWDT and LVD are not operating. Note 3. Includes the current of sub-oscillat ion circuit or low-speed on-chip oscillator. Note 4. VCC = 3.3 V. Table 2.12 Operating and standby current (2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter Symbol Typ* 4 Max Unit Test conditions Supply current*1 Software Standby mode* Ta = 25°C I CC 0.8 4.5 μA- Ta = 55°C 1.3 7.1 Ta = 85°C 3.5 20.2 Ta = 105°C 8.7 53.7 Increment for RTC operation with low-speed on-chip oscillator*3 0.5 - - Increment for RTC operation with sub-clock oscillator*3 0.4 - SOMCR.SODRV[1:0] are 11b (Low power mode 3) 1.2 - SOMCR.SODRV[1:0] are 00b (Normal mode) 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0 55.0 ICC (uA) VCC (V) Note 1. All peripheral operations except any BGO operatio n are operating normally . This is the average of the actual measurements of the sample cores during product evaluation . Note 2. All peripheral operations except any BGO operatio n are operating at maximum . This is the average of the actual measurements for the upper- limit samples during product evaluation. , ICLK = 32 MHz *2Ta = 105 C Ta = 25 C, ICLK = 32 MHz *1 Ta = 25 C , ICLK = 32 MHz *1 Ta = 105 C , ICLK = 32 MHz *2

R01DS0308EU0100 Rev.1.00 Page 52 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Figure 2.22 Temperature dependency in Softwar e Standby mode all SRAM (reference data) Note 1. Supply current values do not include output charge/dischar ge current from all pins. The values apply when internal pull-up MOSs are in the off state. Table 2.13 Operating and standby current (3) Conditions: VCC = AVCC0 = 0V, VBATT = 1.6 to 3.6 V, VSS = AVSS0 = 0V Parameter Symbol Typ Max Unit Test conditions Supply current* RTC operation when VCC is off T a = 25°C I CC 0.8 - μA VBATT = 2.0 V SOMCR.SORDRV[1:0] = 11b (Low power mode 3)Ta = 55°C 0.9 - Ta = 85°C 1.0 - Ta = 105°C 1.1 - Ta = 25°C 0.9 - VBATT = 3.3 V SOMCR.SORDRV[1:0] = 11b (Low power mode 3)T a = 55°C 1.0 - Ta = 85°C 1.1 - Ta = 105°C 1.2 - Ta = 25°C 1.5 - VBATT = 2.0 V SOMCR.SORDRV[1:0] = 00b (Normal mode)Ta = 55°C 1.7 - Ta = 85°C 2.0 - Ta = 105°C 2.2 - Ta = 25°C 1.6 - VBATT = 3.3 V SOMCR.SORDRV[1:0] = 00b (Normal mode)Ta = 55°C 1.8 - Ta = 85°C 2.1 - Ta = 105°C 2.3 - ICC (mA) 0.1 100 -40 -20 0 20 40 60 80 100 Ta ( C) Average value of the tested middle samples during product evaluation. Average value of the tested upper-limit samples during product evaluation. ICC (uA)

R01DS0308EU0100 Rev.1.00 Page 53 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Figure 2.23 Temperature dependency of RTC operation with VCC off (reference data)

R01DS0308EU0100 Rev.1.00 Page 54 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note 1. The reference power supply current is included in the power supply current value for D/A conversion. Note 2. Current consumed only by the USBFS. Note 3. Includes the current supplied from the pull-up resistor of the USB_DP pin to the pull-down resistor of the host device, in addition to the current consumed by the MCU during the suspended state. Note 4. When VCC = VCC_USB = 3.3 V. Note 5. Current flowing only to the LCD controller. Not including the current that flows through the LCD panel. Note 6. When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (ADC140 module stop bit) is in the module-stop state. Table 2.14 Operating and standby current (4) Conditions: VCC = AVCC0 = 1.6 to 5.5 V, VREFH0 = 2.7 V to AVCC0 Parameter Symbol Min Typ Max Unit Test conditions Analog power supply current During A/D conversion (at high-speed conversion) I AVCC -- 3 . 0 m A - During A/D conversion (at low-power conversion) - - 1.0 mA - During D/A conversion (per channel)* 1 -0 . 4 0 . 8 m A - Waiting for A/D and D/A conversion (all units)*6 -- 1 . 0 μA- Reference power supply current During A/D conversion I REFH0 -- 1 5 0 μA- Waiting for A/D conversion (all units) - - 60 nA - During D/A conversion I REFH -5 0 1 0 0 μA- Waiting for D/A conversion (all units) - - 100 μA- Temperature sensor I TNS -7 5 - μA- Low-Power Analog Comparator operating current Window mode I CMPLP -1 5 - μA- Comparator high-speed mode - 10 - μA- Comparator low-speed mode - 2 - μA- Comparator low-speed mode using DAC8 - 820 - μA- Operational Amplifier operating current Low power mode 1 unit operating I AMP -2 . 5 4 . 0 μA- 2 units operating - 4.5 8.0 μA- 3 units operating - 6.5 11.0 μA- 4 units operating - 8.5 14.0 μA- High speed mode 1 unit operating - 140 220 μA- 2 units operating - 280 410 μA- 3 units operating - 420 600 μA- 4 units operating - 560 780 μA- LCD operating current External resistance division method fLCD = fSUB = 128 Hz, 1/3 bias, and 4-time slice ILCD1*5 -0 . 3 4 - μA- Internal voltage boosting method (VLCD.VLCD = 04) fLCD = fSUB = 128 Hz, 1/3 bias, and 4-time slice ILCD2*5 -0 . 9 2 - μA- Capacitor split method fLCD = fSUB = 128 Hz, 1/3 bias, and 4-time slice ILCD3*5 -0 . 1 9 - μA- USB operating current During USB communication operation under the following settings and conditions:  Host controller operation is set to full-speed mode Bulk OUT transfer (64 bytes) × 1, bulk IN transfer (64 bytes) × 1  Connect peripheral devices via a 1-meter USB cable from the USB port. I USBH*2 -4 . 3 ( V C C ) 0.9 (VCC_USB)*4 -m A - During USB communication operation under the following settings and conditions:  Device controller operation is set to full-speed mode Bulk OUT transfer (64 bytes) × 1, bulk IN transfer (64 bytes) × 1  Connect the host device via a 1-meter USB cable from the USB port. I USBF*2 -3 . 6 ( V C C ) 1.1 (VCC_USB)*4 -m A - During suspended state under the following setting and conditions:  Device controller operation is set to full-speed mode (pull up the USB_DP pin)  Software standby mode  Connect the host device via a 1-meter USB cable from the USB port. I SUSP*3 - 0.35 (VCC) 170 (VCC_USB)*4 - μA-

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2.2.10 VCC Rise and Fall Gr adient and Ripple Frequency

Note 1. When OFS1.LVDAS = 0. Note 2. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of OFS1.LVDAS bit. Figure 2.24 Ripple waveform Table 2.15 Rise and fall gradient characteristics Conditions: VCC = AVCC0 = 0 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions Power-on VCC rising gradient Voltage monitor 0 reset disabled at startup (normal startup) SrVCC 0.02 - 2 ms/V - Voltage monitor 0 reset enabled at startup*1 0.02 - - SCI/USB boot mode*2 0.02 - 2 Table 2.16 Rising and falling gradient and ripple frequency characteristics Conditions: VCC = AVCC0 = VCC_USB = 1.6 to 5.5 V The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (5.5 V) and lower limit (1.6 V). When VCC change exceeds VCC ±10%, the allowable voltage change rising/falling gradient dt/dVCC must be met. Parameter Symbol Min Typ Max Unit Test conditions Allowable ripple frequency f r (VCC) --1 0 k H z Figure 2.24 Vr (VCC) ≤ VCC × 0.2 --1 M H z Figure 2.24 Vr (VCC) ≤ VCC × 0.08 --1 0 M H z Figure 2.24 Vr (VCC) ≤ VCC × 0.06 Allowable voltage change rising and falling gradient dt/dVCC 1.0 - - ms/V When VCC change exceeds VCC ±10% Vr(VCC)VCC 1/fr(VCC)

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2.3 AC Characteristics

2.3.1 Frequency

Note 1. The lower-limit frequency of FCLK is 1 MHz while pr ogramming or erasing the flash memory. When using FCLK for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 2. The frequency accuracy of FCLK must be ±3.5% while pr ogramming or erasing the flash memory. Confirm the frequency accuracy of the clock source. Note 3. The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or abo ve and 1 MHz at below 2.4 V when the 14-bit A/D converter is in use. Note 4. See section 8, Clock Generation Ci rcuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB, PCLKC, PCLKD, and FCLK. Note 5. The maximum value of operation frequency does not include in ternal oscillator errors. For details on the range of guaranteed operation, see Table 2.22, Clock timing. Table 2.17 Operation frequency value in high-speed operating mode Conditions: VCC = AVCC0 = 2.4 to 5.5 V Parameter Symbol Min Typ Max* 5 Unit Operation frequency System clock (ICLK)*4 2.7 to 5.5 V f 0.032768 - 48 MHz 2.4 to 2.7 V 0.032768 - 16 FlashIF clock (FCLK)*1, *2, *4 2.7 to 5.5 V 0.032768 - 32 2.4 to 2.7 V 0.032768 - 16 Peripheral module clock (PCLKA)* 4 2.7 to 5.5 V - - 48 2.4 to 2.7 V - - 16 Peripheral module clock (PCLKB)* 4 2.7 to 5.5 V - - 32 2.4 to 2.7 V - - 16 Peripheral module clock (PCLKC)* 3, *4 2.7 to 5.5 V - - 64 2.4 to 2.7 V - - 16 Peripheral module clock (PCLKD)* 4 2.7 to 5.5 V - - 64 2.4 to 2.7 V - - 16 Table 2.18 Operation frequency value in middle-speed mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V Parameter Symbol Min Typ Max* 5 Unit Operation frequency System clock (ICLK)*4 2.7 to 5.5 V f 0.032768 - 12 MHz 2.4 to 2.7 V 0.032768 - 12 1.8 to 2.4 V 0.032768 - 8 FlashIF clock (FCLK)* 1, *2, *4 2.7 to 5.5 V 0.032768 - 12 2.4 to 2.7 V 0.032768 - 12 1.8 to 2.4 V 0.032768 - 8 Peripheral module clock (PCLKA)* 4 2.7 to 5.5 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8 Peripheral module clock (PCLKB)* 4 2.7 to 5.5 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8 Peripheral module clock (PCLKC)* 3, *4 2.7 to 5.5 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8 Peripheral module clock (PCLKD)* 4 2.7 to 5.5 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8

R01DS0308EU0100 Rev.1.00 Page 57 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note 1. The lower-limit frequency of FCLK is 1 MHz while pr ogramming or erasing the flash memory. When using FCLK for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 2. The frequency accuracy of FCLK must be ±3.5% while pr ogramming or erasing the flash memory. Confirm the frequency accuracy of the clock source. Note 3. The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in use. Note 4. See section 8, Clock Generation Ci rcuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB, PCLKC, PCLKD, FCLK. Note 5. The maximum value of operation frequency does not include in ternal oscillator errors. For details on the range of guaranteed operation, see Table 2.22, Clock timing. Note 1. The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. Note 2. The lower-limit frequency of PCLKC is 1 MHz when the A/D converter is in use. Note 3. See section 8, Clock Generation Ci rcuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB, PCLKC, PCLKD, FCLK. Note 4. The maximum value of operation frequency does not include in ternal oscillator errors. For details on the range of guaranteed operation, see Table 2.22, Clock timing. Note 1. The lower-limit frequency of FCLK is 1 MHz while pr ogramming or erasing the flash memory. When using FCLK for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 2. The frequency accuracy of FCLK must be ±3.5% while pr ogramming or erasing the flash memory. Confirm the frequency accuracy of the clock source. Note 3. The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or abo ve and 1 MHz at below 2.4 V when the 14-Bit A/D converter is in use. Note 4. See section 8, Clock Generation Ci rcuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB, PCLKC, PCLKD, FCLK. Note 5. The maximum value of operation frequency does not include in ternal oscillator errors. For details on the range of guaranteed operation, see Table 2.22, Clock timing. Table 2.19 Operation frequency value in low-speed mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V Parameter Symbol Min Typ Max* 4 Unit Operation frequency System clock (ICLK)*3 1.8 to 5.5 V f 0.032768 - 1 MHz FlashIF clock (FCLK)*1, *3 1.8 to 5.5 V 0.032768 - 1 Peripheral module clock (PCLKA)*3 1.8 to 5.5 V - - 1 Peripheral module clock (PCLKB)*3 1.8 to 5.5 V - - 1 Peripheral module clock (PCLKC)*2, *3 1.8 to 5.5 V - - 1 Peripheral module clock (PCLKD)*3 1.8 to 5.5 V - - 1 Table 2.20 Operation frequency value in low-voltage mode Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter Symbol Min Typ Max* 5 Unit Operation frequency System clock (ICLK)*4 1.6 to 5.5 V f 0.032768 - 4 MHz FlashIF clock (FCLK)*1, *2, *4 1.6 to 5.5 V 0.032768 - 4 Peripheral module clock (PCLKA)*4 1.6 to 5.5 V - - 4 Peripheral module clock (PCLKB)*4 1.6 to 5.5 V - - 4 Peripheral module clock (PCLKC)*3, *4 1.6 to 5.5 V - - 4 Peripheral module clock (PCLKD)*4 1.6 to 5.5 V - - 4

R01DS0308EU0100 Rev.1.00 Page 58 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note 1. Programming and erasing the flash memory is not possible. Note 2. The 14-bit A/D converter cannot be used. Note 3. See section 8, Clock Generation Ci rcuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB, PCLKC, PCLKD, FCLK.

2.3.2 Clock Timing

Table 2.21 Operation frequency value in subosc-speed mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V Parameter Symbol Min Typ Max Unit Operation frequency Peripheral module clock (PCLKA)*3 1.8 to 5.5 V - - 37.6832 Peripheral module clock (PCLKB)*3 1.8 to 5.5 V - - 37.6832 Peripheral module clock (PCLKC)*2, *3 1.8 to 5.5 V - - 37.6832 Peripheral module clock (PCLKD)*3 1.8 to 5.5 V - - 37.6832 Table 2.22 Clock timing (1 of 2) Parameter Symbol Min Typ Max Unit Test conditions EXTAL external clock input cycle time t Xcyc 50 - - ns Figure 2.25 EXTAL external clock input high pulse width t XH 20 - - ns EXTAL external clock input low pulse width t XL 20 - - ns EXTAL external clock rising time t Xr --5 n s EXTAL external clock falling time t Xf --5 n s EXTAL external clock input wait time*1 tEXWT 0.3 - - μs- EXTAL external clock input frequency f EXTAL --2 0 M H z 2 . 4 ≤ VCC ≤ 5.5 Main clock oscillator oscillation frequency f MAIN 1- 2 0 M H z 2 . 4 ≤ VCC ≤ 5.5 1- 8 1 . 8 ≤ VCC < 2.4 1- 4 1 . 6 ≤ VCC < 1.8 Main clock oscillation stabilization wait time (crystal)*9 tMAINOSCWT --- * 9 ms - LOCO clock oscillation frequency f LOCO 27.8528 32.768 37.6832 kHz - LOCO clock oscillation stabilization time t LOCO --1 0 0 μs Figure 2.26 IWDT-dedicated clock oscillation frequency f ILOCO 12.75 15 17.25 kHz - MOCO clock oscillation frequency f MOCO 6 . 88 9 . 2M H z - MOCO clock oscillation stabilization time t MOCO --1 μs-

R01DS0308EU0100 Rev.1.00 Page 59 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note 1. Time until the clock can be used after the Main Clock O scillator Stop bit (MOSCCR.MOSTP) is set to 0 (operating) when the external clock is stable. Note 2. The VCC range that the PLL can be used is 2.4 to 5.5 V. Note 3. After changing the setting of the SOSCCR.SOSTP bit so th at the sub-clock oscillator operates, only start using the sub-clock after the sub-clock oscillation stabilization wait time elapses, that is greater than or equal to the value recommended by the oscillator manufacturer. Note 4. The 48-MHz HOCO can be used within a VCC range of 1.8 V to 5.5 V. Note 5. The 64-MHz HOCO can be used within a VCC range of 2.4 V to 5.5 V. Note 6. This is a characteristic when HOCOCR.HCSTP bit is set to 0 (oscillation) in MOCO stop state. When HOCOCR.HCSTP bit is set to 0 (oscillation) during MOCO oscillation, this specification is shortened by 1 μs. Note 7. Whether stabilization time has elapsed can be confirmed by OSCSF.HOCOSF. Note 8. This is a characteristic when PLLCR.PLLSTP bit is set to 0 (operation) in MOCO stop state. When PLLCR.PLLSTP bit is set to 0 (operation) during MOCO oscillation, this specification is shortened by 1 μs. Note 9. When setting up the main clock, ask the oscillator manufa cturer for an oscillation evaluation and use the results as the recommended oscillation stabilization time. Set the MOSCWTCR register to a value equal to or greater than the recommended stabilization time. After changing the setting of the MOSCCR.MOSTP bit so that the main clock oscillator operates, read the OSCSF.MOSCSF flag to confirm that it is 1, then start using the main clock. HOCO clock oscillation frequency f HOCO24 23.64 24 24.36 MHz Ta = –40 to –20°C 1.8 ≤ VCC ≤ 5.5 22.68 24 25.32 Ta = –40 to 85°C 1.6 ≤ VCC < 1.8 23.76 24 24.24 Ta = –20 to 85°C 1.8 ≤ VCC ≤ 5.5 23.52 24 24.48 Ta = 85 to 105°C 2.4 ≤ VCC ≤ 5.5 fHOCO32 31.52 32 32.48 Ta = –40 to -20°C 1.8 ≤ VCC ≤ 5.5 30.24 32 33.76 Ta = –40 to 85°C 1.6 ≤ VCC < 1.8 31.68 32 32.32 Ta = –20 to 85°C 1.8 ≤ VCC ≤ 5.5 31.36 32 32.64 Ta = 85 to 105°C 2.4 ≤ VCC ≤ 5.5 fHOCO48*4 47.28 48 48.72 Ta = –40 to –20°C 1.8 ≤ VCC ≤ 5.5 47.52 48 48.48 Ta = –20 to 85°C 1.8 ≤ VCC ≤ 5.5 47.04 48 48.96 Ta = –40 to 105°C 2.4 ≤ VCC ≤ 5.5 fHOCO64*5 63.04 64 64.96 Ta = –40 to –20°C 2.4 ≤ VCC ≤ 5.5 63.36 64 64.64 Ta = –20 to 85°C 2.4 ≤ VCC ≤ 5.5 62.72 64 65.28 Ta = 85 to 105°C 2.4 ≤ VCC ≤ 5.5 HOCO clock oscillation stabilization time*6, *7 Except Low-Voltage mode tHOCO24 tHOCO32 --3 7 . 1 μs Figure 2.27 tHOCO48 --4 3 . 3 tHOCO64 --8 0 . 6 Low-Voltage mode t HOCO24 tHOCO32 tHOCO48 tHOCO64 - - 100.9 PLL input frequency*2 fPLLIN 4- 1 2 . 5 M H z - PLL circuit oscillation frequency*2 fPLL 24 - 64 MHz - PLL clock oscillation stabilization time*8 tPLL --5 5 . 5 μs Figure 2.29 PLL free-running oscillation frequency f PLLFR -8 -M H z - Sub-clock oscillator oscillation frequency f SUB - 32.768 - kHz - Sub-clock oscillation stabilization time*3 t SUBOSC --- * 3 s Figure 2.30 Table 2.22 Clock timing (2 of 2) Parameter Symbol Min Typ Max Unit Test conditions

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2.3.3 Reset Timing

Note 1. When OFS1.LVDAS = 0. Note 2. When OFS1.LVDAS = 1. Figure 2.32 Reset input timing at power-on Figure 2.33 Reset input timing Table 2.23 Reset timing Parameter Symbol Min Typ Max Unit Test conditions RES pulse width At power-on t RESWP 3 - - ms Figure 2.32 Other than above t RESW 30 - - μs Figure 2.33 Wait time after RES cancellation (at power-on) LVD0: enable*1 tRESWT - 0.7 -m s Figure 2.32 LVD0: disable*2 - 0.3 - Wait time after RES cancellation (during powered-on state) LVD0: enable*1 tRESWT2 - 0.5 -m s Figure 2.33 LVD0: disable*2 - 0.05 - Internal reset cancellation time (Watchdog timer reset, SRAM parity error reset, SRAM ECC error reset, Bus master MPU error reset, Bus slave MPU error reset, Stack pointer error reset, Software reset) LVD0: enable* 1 tRESWT3 - 0.6 -m s - LVD0: disable*2 - 0.15 - VCC RES tRESWP Internal reset tRESWT RES Internal reset tRESWT2 tRESW

R01DS0308EU0100 Rev.1.00 Page 63 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics

2.3.4 Wakeup Time

Note 1. The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. Note 2. The Main Clock Oscillator Wait C ontrol Register (MOSCWTCR) is set to 05h. Note 3. The Main Clock Oscillator Wait C ontrol Register (MOSCWTCR) is set to 00h. Note 4. The HOCO Clock Wait Control Register (HOCOWTCR) is set to 05h. Note 5. The HOCO Clock Wait Control Register (HOCOWTCR) is set to 06h. Note 1. The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. Note 2. The Main Clock Oscillator Wait C ontrol Register (MOSCWTCR) is set to 05h. Note 3. The Main Clock Oscillator Wait C ontrol Register (MOSCWTCR) is set to 00h. Table 2.24 Timing of recovery from low power modes (1) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode*1 High-speed mode Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (20 MHz) tSBYMC -2 3m s Figure 2.34 System clock source is PLL (48 MHz) with main clock oscillator*2 tSBYPC -2 3m s External clock input to main clock oscillator System clock source is main clock oscillator (20 MHz) tSBYEX -1 4 2 5 μs System clock source is PLL (48 MHz) with main clock oscillator tSBYPE -5 3 7 6 μs System clock source is HOCO*4 (HOCO clock is 32 MHz) tSBYHO -4 3 5 2 μs System clock source is HOCO*4 (HOCO clock is 48 MHz) tSBYHO -4 4 5 2 μs System clock source is HOCO*5 (HOCO clock is 64 MHz) tSBYHO -8 2 1 1 0 μs System clock source is MOCO t SBYMO -1 6 2 5 μs Table 2.25 Timing of recovery from low power modes (2) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode*1 Middle-speed mode Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (12 MHz) tSBYMC -2 3m s Figure 2.34 System clock source is PLL (24 MHz) with main clock oscillator*2 tSBYPC -2 3m s External clock input to main clock oscillator System clock source is main clock oscillator (12 MHz) tSBYEX -2 . 9 1 0 μs System clock source is PLL (24 MHz) with main clock oscillator*3 tSBYPE -4 9 7 6 μs System clock source is HOCO (24 MHz) t SBYHO -3 8 5 0 μs System clock source is MOCO t SBYMO -3 . 5 5 . 5 μs

R01DS0308EU0100 Rev.1.00 Page 64 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note 1. The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. Note 2. The Main Clock Oscillator Wait C ontrol Register (MOSCWTCR) is set to 05h. Note 3. The Main Clock Oscillator Wait C ontrol Register (MOSCWTCR) is set to 00h. Note 1. The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. When multiple oscillators are active, the recovery time can be determined by the following expression. Note 2. The Main Clock Oscillator Wait C ontrol Register (MOSCWTCR) is set to 05h. Note 3. The Main Clock Oscillator Wait C ontrol Register (MOSCWTCR) is set to 00h. Note 1. The sub-clock oscillator or LOCO itself continues to oscillate in Software Standby mode during subosc-speed mode. Table 2.26 Timing of recovery from low power modes (3) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode*1 Low-speed mode Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (1 MHz) tSBYMC -2 3 m s Figure 2.34 External clock input to main clock oscillator System clock source is main clock oscillator (1 MHz)*3 tSBYEX -2 8 5 0 μs System clock source is MOCO t SBYMO -2 5 3 5 μs Table 2.27 Timing of recovery from low power modes (4) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode Low-voltage mode Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (4 MHz)*2 tSBYMC -2 3m s Figure 2.34 External clock input to main clock oscillator System clock source is main clock oscillator (4 MHz)*3 tSBYEX - 108 130 μs System clock source is HOCO tSBYHO - 108 130 μs Table 2.28 Timing of recovery from low power modes (5) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode* Subosc-speed mode System cloc k source is sub-clock oscillator (32.768 kHz) tSBYSC -0 . 8 5 1m s Figure 2.34 System clock source is LOCO (32.768 kHz) tSBYLO - 0.85 1.2 ms

R01DS0308EU0100 Rev.1.00 Page 65 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Figure 2.34 Software Standby mode cancellation timing Table 2.29 Timing of recovery from low power modes (6) Parameter Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode to Snooze mode High-speed mode System clock source is HOCO tSNZ -3 6 4 5 μs Figure 2.35 Middle-speed mode System clock source is MOCO tSNZ -1 . 3 3 . 6 μs Low-speed mode System clock source is MOCO tSNZ -1 0 1 3 μs Low-voltage mode System clock source is HOCO tSNZ -8 7 1 1 0 μs Oscillator ICLK IRQ Software Standby mode tSBYSC, tSBYLO Oscillator ICLK IRQ Software Standby mode tSBYMC, tSBYPC, tSBYEX, tSBYPE, tSBYMO, tSBYHO

R01DS0308EU0100 Rev.1.00 Page 66 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Figure 2.35 Software Standby mode to Snooze mode recovery timing tSNZ IRQ ICLK (to DTC, SRAM)*1 PCLK ICLK (except DTC, SRAM) Oscillator Software Standby mode Snooze mode Note 1. When SNZCR.SNZDTCEN is set to 1, ICLK is supplied to DTC and SRAM.

R01DS0308EU0100 Rev.1.00 Page 67 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics

2.3.5 NMI and IRQ Noise Filter

Note: 200 ns minimum in Software Standby mode. Note 1. t Pcyc indicates the cycle of PCLKB. Note 2. t NMICK indicates the cycle of the NMI digital filter sampling clock. Note 3. t IRQCK indicates the cycle of the IRQi digital filter sampling clock (i = 0 to 12, 14, 15). Figure 2.36 NMI interrupt input timing Figure 2.37 IRQ interrupt input timing Table 2.30 NMI and IRQ noise filter Parameter Symbol Min Typ Max Unit Test conditions NMI pulse width t NMIW 200 -- ns NMI digital filter disabled t Pcyc × 2 ≤ 200 ns tPcyc × 2*1 -- tPcyc × 2 > 200 ns 200 -- NMI digital filter enabled t NMICK × 3 ≤ 200 ns tNMICK × 3.5*2 -- tNMICK × 3 > 200 ns IRQ pulse width t IRQW 200 -- ns IRQ digital filter disabled t Pcyc × 2 ≤ 200 ns tPcyc × 2*1 -- tPcyc × 2 > 200 ns 200 -- IRQ digital filter enabled t IRQCK × 3 ≤ 200 ns tIRQCK × 3.5*3 -- tIRQCK × 3 > 200 ns tNMIW NMI tIRQW IRQ

R01DS0308EU0100 Rev.1.00 Page 68 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics

2.3.6 I/O Ports, POEG , GPT, AGT, KINT, and ADC14 Trigger Timing

Note 1. Constraints on AGTIO input: t Pcyc × 2 < tACYC Note: t Pcyc: PCLKB cycle, tPDcyc: PCLKD cycle Figure 2.38 I/O ports input timing Figure 2.39 POEG in put trigger timing Table 2.31 I/O Ports, PO EG, GPT, AGT, KINT, and ADC14 trigger timing Parameter Symbol Min Max Unit Test conditions I/O ports Input data pulse width t PRW 1.5 - t Pcyc Figure 2.38 Input/output data cycle (P002, P003, P004, P007) t POcyc 10 - us POEG POEG input trigger pulse width t POEW 3- t Pcyc Figure 2.39 GPT Input capture pulse width Single edge t GTICW 1.5 - t PDcyc Figure 2.40 Dual edge 2.5 - AGT AGTIO, AGTEE input cycle 2.7 V ≤ VCC ≤ 5.5 V t ACYC*1 250 - ns Figure 2.41 2.4 V ≤ VCC < 2.7 V 500 - ns 1.8 V ≤ VCC < 2.4 V 1000 - ns 1.6 V ≤ VCC < 1.8 V 2000 - ns AGTIO, AGTEE input high level width, low-level width 2.7 V ≤ VCC ≤ 5.5 V t ACKWH, tACKWL 100 - ns 2.4 V ≤ VCC < 2.7 V 200 - ns 1.8 V ≤ VCC < 2.4 V 400 - ns 1.6 V ≤ VCC < 1.8 V 800 - ns AGTIO, AGTO, AGTOA, AGTOB output frequency 2.7 V ≤ VCC ≤ 5.5 V t ACYC2 62.5 - ns Figure 2.41 2.4 V ≤ VCC < 2.7 V 125 - ns 1.8 V ≤ VCC < 2.4 V 250 - ns 1.6 V ≤ VCC < 1.8 V 500 - ns ADC14 14-bit A/D converter trigger input pulse width t TRGW 1.5 - t Pcyc Figure 2.42 KINT Key interrupt input low-level width t KR 250 - ns Figure 2.43 Port tPRW POEG input trigger tPOEW

R01DS0308EU0100 Rev.1.00 Page 69 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Figure 2.40 GPT input capture timing Figure 2.41 AGT I/O timing Figure 2.42 ADC14 trigger input timing Figure 2.43 Key inte rrupt input timing

2.3.7 CAC Timing

Table 2.32 CAC timing Parameter Symbol Min Typ Max Unit Test conditions CAC CACREF input pulse width t PBcyc*1 ≤ tcac*2 tCACREF 4.5 × tcac + 3 × tPBcyc*1 --n s - tPBcyc*1 > tcac*2 5 × tcac + 6.5 × tPBcyc*1 --n s Input capture tGTICW tACYC2 AGTIO, AGTEE (input) tACYC tACKWL tACKWH AGTIO, AGTO, AGTOA, AGTOB (output) ADTRG0 tTRGW KR00 to KR07 tKR

R01DS0308EU0100 Rev.1.00 Page 70 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note 1. t PBcyc: PCLKB cycle. Note 2. t cac: CAC count clock source cycle.

2.3.8 SCI Timing

Note 1. t Pcyc: PCLKA cycle. Figure 2.44 SCK clock input timing Table 2.33 SCI timing (1) Parameter Symbol Min Max Unit *1 Test conditions SCI Input clock cycle Asynchronous t Scyc 4- t Pcyc Figure 2.44 Clock synchronous 6 - Input clock pulse width t SCKW 0.4 0.6 t Scyc Input clock rise time t SCKr -2 0 n s Input clock fall time t SCKf -2 0 n s Output clock cycle Asynchronous t Scyc 6- t Pcyc Clock synchronous 4 - Output clock pulse width t SCKW 0.4 0.6 t Scyc Output clock rise time 1.8 V or above t SCKr -2 0 n s

1.6 V or above - 30

Output clock fall time 1.8 V or above t SCKf -2 0 n s (master) Clock synchronous 1.8 V or above t TXD -4 0 n s Figure 2.45

1.6 V or above - 45

(slave) Clock synchronous

2.7 V or above - 55 ns

2.4 V or above - 60

1.8 V or above - 100

1.6 V or above - 125

time (master) Clock synchronous

2.7 V or above t RXS 45 - ns

2.4 V or above 55 -

1.8 V or above 90 -

1.6 V or above 110 -

time (slave) Clock synchronous

2.7 V or above 40 - ns

1.6 V or above 45 -

time (master) Clock synchronous t RXH 5- n s Receive data hold time (slave) Clock synchronous t RXH 40 - ns tSCKW tSCKr tSCKf tScyc SCKn (n = 0 to 2, 9)

R01DS0308EU0100 Rev.1.00 Page 71 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Figure 2.45 SCI input/output timing in clock synchronous mode Table 2.34 SCI timing (2) (1 of 2) Parameter Symbol Min Max Unit Test conditions Simple SPI SCK clock cycle output (master) t SPcyc 4 65536 t Pcyc Figure 2.46 SCK clock cycle input (slave) 6 65536 SCK clock high pulse width t SPCKWH 0.4 0.6 t SPcyc SCK clock low pulse width t SPCKWL 0.4 0.6 t SPcyc SCK clock rise and fall time 1.8 V or above t SPCKr, tSPCKf -2 0 n s Master 2.7 V or above t SU 45 - ns Figure 2.47 to Figure 2.502.4 V or above 55 -

1.8 V or above 80 -

Slave 2.7 V or above 40 - Data input hold time Master t H 33.3 - ns Slave 40 - SS input setup time t LEAD 1- t SPcyc SS input hold time t LAG 1- t SPcyc Data output delay Master 1.8 V or above t OD -4 0 n s

1.6 V or above - 50

Slave 2.4 V or above - 65 Master 2.7 V or above t OH -10 - ns

2.4 V or above -20 -

1.8 V or above -30 -

1.6 V or above -40 -

Master 1.8 V or above t Dr, tDf -2 0 n s Slave 1.8 V or above - 20 (n = 0 to 2, 9)

R01DS0308EU0100 Rev.1.00 Page 72 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Figure 2.46 SCI simple SPI mode clock timing Figure 2.47 SCI simple SPI mo de timing (master, CKPH = 1) Simple SPI Slave access time t SA - 10 (PCLKA >

32 MHz),

6 (PCLKA ≤

32 MHz)

tPcyc Figure 2.49 and Figure 2.50 Slave output release time t REL - 10 (PCLKA > 6 (PCLKA ≤ Table 2.34 SCI timing (2) (2 of 2) Parameter Symbol Min Max Unit Test conditions tSPCKWH VOH VOH VOL VOL VOH VOH tSPCKWL tSPCKr tSPCKf VOL tSPcyc tSPCKWH VIH VIH VIL VIL VIH VIH tSPCKWL tSPCKr tSPCKf VIL tSPcyc VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC (n = 0 to 2, 9) SCKn master select output SCKn slave select input tDr, tDf tSU tH tOH tOD MSB IN DATA LSB IN MSB IN MSB OUT DATA LSB OUT IDLE MSB OUT SCKn CKPOL = 0 output SCKn CKPOL = 1 output SMISOn input SMOSIn output (n = 0 to 2, 9)

R01DS0308EU0100 Rev.1.00 Page 74 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Figure 2.50 SCI simple SPI mode timing (slave, CKPH = 0) Note 1. tIICcyc: Clock cycle selected by the SMR.CKS[1:0] bits. tPcyc: PCLKB cycle. Note 2. Cb indicates the to tal capacity of the bus line. Table 2.35 SCI timing (3) Conditions: VCC = 2.7 to 5.5 V Parameter Symbol Min Max Unit Test conditions Simple I2C (Standard mode) SDA input rise time t Sr - 1000 ns Figure 2.51 SDA input fall time t Sf - 300 ns SDA input spike pulse removal time t SP 04 × t IICcyc*1 ns Data input setup time t SDAS 250 - ns Data input hold time t SDAH 0- n s SCL, SDA capacitive load C b*2 - 400 pF Simple I2C (Fast mode) SDA input rise time t Sr - 300 ns Figure 2.51 For all ports except P408, use PmnPFS.DSCR of middle drive. For port P408, use PmnPFS.DSCR1 /DSCR of middle drive for IIC fast-mode. SDA input fall time t Sf - 300 ns SDA input spike pulse removal time t SP 04 × t IICcyc*1 ns Data input setup time t SDAS 100 - ns Data input hold time t SDAH 0- n s SCL, SDA capacitive load C b*1 - 400 pF tDr, tDf tSA tOH tLEAD tTD tLAG tH LSB OUT (Last data) DATA MSB OUT MSB IN DATA LSB IN MSB IN LSB OUT tSU tOD tREL MSB OUT SSn input SCKn CKPOL = 1 input SCKn CKPOL = 0 input MISOn output MOSIn input (n = 0 to 2, 9)

R01DS0308EU0100 Rev.1.00 Page 75 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Figure 2.51 SCI simple IIC mode timing SDAn SCLn VIH VIL P*1 S*1 tSftSr tSDAH tSDAS tSP P*1 Test conditions: VIH = VCC × 0.7, VIL = VCC × 0.3 VOL = 0.6 V, IOL = 6 mA Sr*1 Note 1. S, P, and Sr indicate the following: S: Start condition P: Stop condition Sr: Restart condition (n = 0 to 2, 9)

R01DS0308EU0100 Rev.1.00 Page 76 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics

2.3.9 SPI Timing

Table 2.36 SPI timing (1 of 2) Conditions: Middle drive output is selected in the Port Drive Capability bit in PmnPFS register Parameter Symbol Min Max Unit *1 Test conditions SPI RSPCK clock cycle Master t SPcyc 2*4 4096 t Pcyc Figure 2.52 Slave 6 4096 RSPCK clock high pulse width Master t SPCKWH (tSPcyc – tSPCKR – tSPCKF) / 2 – 3 -n s Slave 3 × t Pcyc - RSPCK clock low pulse width Master t SPCKWL (tSPcyc – tSPCKR – tSPCKF) / 2 – 3 -n s Slave 3 × t Pcyc - RSPCK clock rise and fall time Output 2.7 V or above t SPCKr, tSPCKf -1 0 n s

2.4 V or above - 15

1.8 V or above - 20

Input - 1 µs Data input setup time Master t SU 10 - ns Figure 2.53 to Figure 2.58Slave 2.4 V or above 10 -

1.8 V or above 15 -

1.6 V or above 20 -

Data input hold time Master (RSPCK is PCLKA/2) t HF 0- n s Master (RSPCK is other than above.) tH tPcyc - Slave t H 20 - SSL setup time Master 1.8 V or above t LEAD -30 + N × tSpcyc*2 -n s

1.6 V or above -50 + N ×

tSpcyc*2 Slave 6 × t Pcyc - SSL hold time Master t LAG -30 + N × tSpcyc*3 Slave 6 × t Pcyc -

R01DS0308EU0100 Rev.1.00 Page 77 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note 1. t Pcyc: PCLKA cycle. Note 2. N is set as an integer from 1 to 8 by the SPCKD register. Note 3. N is set as an integer from 1 to 8 by the SSLND register. Note 4. The upper limit of RSPCK is 16 MHz. SPI Data output delay Master 2.7 V or above t OD -1 4 n s Figure 2.53 to Figure 2.58 2.4 V or above - 20

1.8 V or above - 25

Slave 2.7 V or above - 50

1.8 V or above - 85

1.6 V or above - 110

Data output hold time Master t OH 0- n s Slave 0 - Successive transmission delay Master t TD tSPcyc + 2 × tPcyc 8 × tSPcyc + 2 × tPcyc ns Slave 6 × t Pcyc - MOSI and MISO rise and fall time Output 2.7 V or above t Dr, tDf -1 0 n s Input - 1 µs SSL rise and fall time Output 2.7 V or above t SSLr, tSSLf -1 0 n s Input - 1 µs Slave access time 2.4 V or above t SA -2 × t Pcyc + 100 ns Figure 2.57 and Figure 2.581.8 V or above - 2 × t Pcyc + 140

1.6 V or above - 2 × t Pcyc + 180

Slave output release time 2.4 V or above t REL -2 × t Pcyc + 100 ns

1.8 V or above - 2 × t Pcyc + 140

Table 2.36 SPI timing (2 of 2) Conditions: Middle drive output is selected in the Port Drive Capability bit in PmnPFS register Parameter Symbol Min Max Unit *1 Test conditions

R01DS0308EU0100 Rev.1.00 Page 81 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Figure 2.58 SPI timing (slave, CPHA = 1)

2.3.10 IIC Timing

Table 2.37 IIC timing (1 of 2) Conditions: VCC = 2.7 to 5.5 V Parameter Symbol Min* 1 Max Unit Test conditions IIC (standard mode, SMBus) SCL input cycle time t SCL 6 (12) × tIICcyc + 1300 -n s Figure 2.59 SCL input high pulse width t SCLH 3 (6) × tIICcyc + 300 -n s SCL input low pulse width t SCLL 3 (6) × tIICcyc + 300 -n s SCL, SDA input rise time t Sr -1 0 0 0 n s SCL, SDA input fall time t Sf -3 0 0 n s SCL, SDA input spike pulse removal time tSP 01 ( 4 ) × t IICcyc ns SDA input bus free time (When wakeup function is disabled) tBUF 3 (6) × tIICcyc + 300 -n s SDA input bus free time (When wakeup function is enabled) tBUF 3 (6) × tIICcyc + 4 × tPcyc + 300 -n s START condition input hold time (When wakeup function is disabled) tSTAH tIICcyc + 300 - ns START condition input hold time (When wakeup function is enabled) tSTAH 1 (5) × tIICcyc + tPcyc + 300 -n s Repeated START condition input setup time tSTAS 1000 - ns STOP condition input setup time t STOS 1000 - ns Data input setup time t SDAS tIICcyc + 50 - ns Data input hold time t SDAH 0- n s SCL, SDA capacitive load C b -4 0 0 p F SSLn0 input RSPCKn CPOL = 0 input RSPCKn CPOL = 1 input MISOn output MOSIn input t Dr, tDf tSA tOH tLEAD tTD tLAG tH LSB OUT (Last data) DATA MSB OUT MSB IN DATA LSB IN MSB IN LSB OUT tSU tOD tREL MSB OUT n = A or B

R01DS0308EU0100 Rev.1.00 Page 82 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note: t IICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle Note 1. The value in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1. Figure 2.59 IIC bus interface input/output timing IIC (Fast mode) SCL input cycle time t SCL 6 (12) × tIICcyc + 600 -n s Figure 2.59 For all ports except P408, use PmnPFS.DSC R of middle drive. For port P408, use PmnPFS.DSC R1/DSCR of middle drive for IIC fast- mode. SCL input high pulse width t SCLH 3 (6) × tIICcyc + 300 -n s SCL input low pulse width t SCLL 3 (6) × tIICcyc + 300 -n s SCL, SDA input rise time t Sr -3 0 0 n s SCL, SDA input fall time t Sf -3 0 0 n s SCL, SDA input spike pulse removal time tSP 01 ( 4 ) × t IICcyc ns SDA input bus free time (When wakeup function is disabled) tBUF 3 (6) × tIICcyc + 300 -n s SDA input bus free time (When wakeup function is enabled) tBUF 3 (6) × tIICcyc + 4 × tPcyc + 300 -n s START condition input hold time (When wakeup function is disabled) tSTAH tIICcyc + 300 - ns START condition input hold time (When wakeup function is enabled) tSTAH 1(5) × tIICcyc + tPcyc + 300 -n s Repeated START condition input setup time tSTAS 300 - ns STOP condition input setup time t STOS 300 - ns Data input setup time t SDAS tIICcyc + 50 - ns Data input hold time t SDAH 0- n s SCL, SDA capacitive load C b -4 0 0 p F Table 2.37 IIC timing (2 of 2) Conditions: VCC = 2.7 to 5.5 V Parameter Symbol Min* 1 Max Unit Test conditions SDA0 to SDA1 SCL0 to SCL1 VIH VIL tSTAH tSCLH tSCLL P*1 S*1 tSf tSr tSCL tSDAH tSDAS tSTAS tSP tSTOS P*1 tBUF Sr*1 Note 1. S, P, and Sr indica te the following conditions. S: Start condition P: Stop condition Sr: Restart condition.

R01DS0308EU0100 Rev.1.00 Page 83 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics

2.3.11 SSIE Timing

Figure 2.60 SSIE clock input/output timing Table 2.38 SSIE timing Conditions: VCC = 1.6 to 5.5 V Parameter Symbol Min Max Unit Test conditions SSIE AUDIO_CLK input frequency

2.7 V or above t AUDIO -2 5 M H z -

1.6 V or above - 4

Output clock period t O 250 - ns Figure 2.60 Input clock period t I 250 - ns Clock high pulse width

1.8 V or above t HC 100 - ns

1.6 V or above 200 -

1.8 V or above t LC 100 - ns

Clock rise time t RC -2 5 n s Data delay 2.7 V or above t DTR -6 5 n s Figure 2.61, Figure 2.621.8 V or above - 105

1.6 V or above - 140

Set-up time 2.7 V or above t SR 65 - ns

1.6 V or above 140 -

1.8 V or above T DTRW - 105 ns Figure 2.63 tI, tO

R01DS0308EU0100 Rev.1.00 Page 85 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Figure 2.63 SSIE data output dela y from SSILRCK0/SSIFS0 change time

2.3.12 CLKOUT Timing

Note 1. When the EXTAL external clock input or an oscillator is used with division by 1 (the CKOCR.CKOSEL[2:0] bits are 011b and the CKOCR.CKODIV[2:0] bits are 000b) to output from CLKOUT, the above should be satisfied with an input duty cycle of 45 to 55%. Note 2. When the MOCO is selected as the clock output source (t he CKOCR.CKOSEL[2:0] bits are 001b), set the clock output division ratio selection to be divided by 2 (the CKOCR.CKODIV[2:0] bits are 001b). Figure 2.64 CLKOUT output timing Table 2.39 CLKOUT timing Parameter Symbol Min Max Unit* 1 Test conditions CLKOUT CLKOUT pin output cycle* 1 VCC = 2.7 V or above t Ccyc 62.5 - ns Figure 2.64 VCC = 1.8 V or above 125 - VCC = 1.6 V or above 250 - CLKOUT pin high pulse width* 2 VCC = 2.7 V or above t CH 15 - ns VCC = 1.8 V or above 30 - VCC = 1.6 V or above 150 - CLKOUT pin low pulse width* 2 VCC = 2.7 V or above t CL 15 - ns VCC = 1.8 V or above 30 - VCC = 1.6 V or above 150 - CLKOUT pin output rise time VCC = 2.7 V or above t Cr -1 2 n s VCC = 1.8 V or above - 25 VCC = 1.6 V or above - 50 CLKOUT pin output fall time VCC = 2.7 V or above t Cf -1 2 n s VCC = 1.8 V or above - 25 VCC = 1.6 V or above - 50 tDTRW SSILRCK0/SSIFS0 (Input) SSITXD0 (Output) MSB bit output delay from SSILRCK0/SSIFS0 change time for Slave transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0] tCf tCH tCcyc tCr tCL CLKOUT pin output Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF

R01DS0308EU0100 Rev.1.00 Page 86 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics

2.4 USB Characteristics

2.4.1 USBFS Timing

Figure 2.65 USB_DP and USB_DM output timing Table 2.40 USB characteristics Conditions: VCC = VCC_USB = 3.0 to 3.6 V, Ta = -20 to +85°C (USBCLKSEL = 1), Ta = -40 to +105°C (USBCLKSEL = 0) Parameter Symbol Min Max Unit Test conditions Input characteristics Input high level voltage V IH 2.0 - V - Input low level voltage V IL -0 . 8 V - Differential input sensitivity V DI 0.2 - V | USB_DP - USB_DM | Differential common mode range VCM 0.8 2.5 V - Output characteristics Output high level voltage V OH 2.8 VCC_USB V I OH = –200 μA Output low level voltage V OL 0.0 0.3 V I OL = 2 mA Cross-over voltage V CRS 1.3 2.0 V Figure 2.65, Figure 2.66, Figure 2.67Rise time FS t r 42 0 n s LS 75 300 Fall time FS t f 42 0 n s LS 75 300 Rise/fall time ratio FS t r/tf 90 111.11 % LS 80 125 Output resistance Z DRV 28 44 Ω (Adjusting the resistance of external elements is not necessary.) VBUS characteristics VBUS input voltage V IH VCC × 0.8 - V - VIL -V C C × 0 . 2 V - Pull-up, pull-down Pull-down resistor R PD 14.25 24.80 k Ω - Pull-up resistor R PUI 0.9 1.575 k Ω During idle state RPUA 1.425 3.09 k Ω During reception Battery Charging Specification Ver 1.2 D + sink current I DP_SINK 25 175 μA- D – sink current I DM_SINK 25 175 μA- DCD source current I DP_SRC 71 3 μA- Data detection voltage V DAT_REF 0.25 0.4 V - D + source voltage V DP_SRC 0.5 0.7 V Output current = 250 μA D – source voltage V DM_SRC 0.5 0.7 V Output current = 250 μA USB_DP, USB_DM tftr 90% 10%10% 90%VCRS

R01DS0308EU0100 Rev.1.00 Page 87 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Figure 2.66 Test circuit for Full-Speed (FS) connection Figure 2.67 Test circuit for Low-Speed (LS) connection

2.4.2 USB External Supply

Table 2.41 USB regulator Parameter Min Typ Max Unit Test conditions VCC_USB supply current VCC_USB_LDO ≥ 3.8V - - 50 mA - VCC_USB_LDO ≥ 4.5V - - 100 mA - VCC_USB supply voltage 3.0 - 3.6 V - Observation point 50 pF DP DM 50 pF Observation point 200 pF to 600 pF DP DM 200 pF to 600 pF 1.5 K 3.6 V Observation point

R01DS0308EU0100 Rev.1.00 Page 88 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics

2.5 ADC14 Characteristics

Figure 2.68 AVCC0 to VREFH0 voltage range Table 2.42 A/D conversion characteristics (1) in high-speed A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 4.5 to 5.5 V, VREFH0 = 4.5 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 64 MHz - Analog input capacitance Cs - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input resistance Rs - - 2.5 k Ω - Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution - - 12 Bit - Conversion time* (Operation at PCLKC = 64 MHz) Permissible signal source impedance Max. = 0.3 kΩ 0.70 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.13 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Offset error - ±0.5 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Full-scale error - ±0.75 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel ±8.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - 14-bit mode Resolution - - 14 Bit - VREFH0 5.0 4.0 3.0 2.0 1.0 A/D Conversion Characteristics (2) ADCSR.ADHSC = 0 5.5 2.7 2.4 2.42.7 5.5 AVCC0 VREFH0 5.0 4.0 3.0 2.0 1.0 ADCSR.ADHSC = 1 5.5 2.7 2.4 2.4 2.7 5.5 AVCC0 1.8 1.8 A/D Conversion Characteristics (1) A/D Conversion Characteristics (3) A/D Conversion Characteristics (4) A/D Conversion Characteristics (5) A/D Conversion Characteristics (6) A/D Conversion Characteristics (7) 1.6 1.6

R01DS0308EU0100 Rev.1.00 Page 89 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Conversion time*1 (Operation at PCLKC = 64 MHz) Permissible signal source impedance Max. = 0.3 kΩ 0.80 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.22 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Offset error - ±2.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Full-scale error - ±3.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±5.0 ±20 LSB High-precision channel ±32.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Table 2.43 A/D conversion characteristics (2) in high-speed A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 48 MHz - Analog input capacitance Cs - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input resistance Rs - - 2.5 k Ω - Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution - - 12 Bit - Conversion time* (Operation at PCLKC = 48 MHz) Permissible signal source impedance Max. = 0.3 kΩ 0.94 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.50 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Offset error - ±0.5 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Full-scale error - ±0.75 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel ±8.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - 14-bit mode Resolution - - 14 Bit - Table 2.42 A/D conversion characteristics (1) in high-speed A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 4.5 to 5.5 V, VREFH0 = 4.5 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions

R01DS0308EU0100 Rev.1.00 Page 90 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Conversion time*1 (Operation at PCLKC = 48 MHz) Permissible signal source impedance Max. = 0.3 kΩ 1.06 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.63 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Offset error - ±2.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Full-scale error - ±3.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±5.0 ±20 LSB High-precision channel ±32.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Table 2.44 A/D conversion characteristics (3) in high-speed A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 32 MHz - Analog input capacitance Cs - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input resistance Rs - - 2.5 k Ω - Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution - - 12 Bit - Conversion time* (Operation at PCLKC = 32 MHz) Permissible signal source impedance Max. = 1.3 kΩ 1.41 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 2.25 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Offset error - ±0.5 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Full-scale error - ±0.75 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel ±8.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - 14-bit mode Resolution - - 14 Bit - Table 2.43 A/D conversion characteristics (2) in high-speed A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions

R01DS0308EU0100 Rev.1.00 Page 91 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Conversion time*1 (Operation at PCLKC = 32 MHz) Permissible signal source impedance Max. = 1.3 kΩ 1.59 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 2.44 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Offset error - ±2.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Full-scale error - ±3.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±5.0 ±20 LSB High-precision channel ±32.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Table 2.45 A/D conversion characteristics (4) in low power A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 24 MHz - Analog input capacitance Cs - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input resistance Rs - - 2.5 k Ω - Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution - - 12 Bit - Conversion time* (Operation at PCLKC = 24 MHz) Permissible signal source impedance Max. = 1.1 kΩ 2.25 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 3.38 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Offset error - ±0.5 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Full-scale error - ±0.75 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel ±8.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - 14-bit mode Resolution - - 14 Bit - Table 2.44 A/D conversion characteristics (3) in high-speed A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions

R01DS0308EU0100 Rev.1.00 Page 92 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Conversion time*1 (Operation at PCLKC = 24 MHz) Permissible signal source impedance Max. = 1.1 kΩ 2.50 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 3.63 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Offset error - ±2.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Full-scale error - ±3.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±5.0 ±20 LSB High-precision channel ±32.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Table 2.46 A/D conversion characteristics (5) in low power A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 16 MHz - Analog input capacitance Cs - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input resistance Rs - - 2.5 k Ω - Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution - - 12 Bit - Conversion time* (Operation at PCLKC = 16 MHz) Permissible signal source impedance Max. = 2.2 kΩ 3.38 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 5.06 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Offset error - ±0.5 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Full-scale error - ±0.75 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel ±8.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - 14-bit mode Resolution - - 14 Bit - Table 2.45 A/D conversion characteristics (4) in low power A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions

R01DS0308EU0100 Rev.1.00 Page 93 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Conversion time*1 (Operation at PCLKC = 16 MHz) Permissible signal source impedance Max. = 2.2 kΩ 3.75 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 5.44 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Offset error - ±2.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Full-scale error - ±3.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±5.0 ±20 LSB High-precision channel ±32.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Table 2.47 A/D conversion characteristics (6) in low power A/D conversion mode (1 of 2) Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 8 MHz - Analog input capacitance Cs - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input resistance Rs - - 2.5 k Ω - Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution - - 12 Bit - Conversion time* (Operation at PCLKC = 8 MHz) Permissible signal source impedance Max. = 5 kΩ 6.75 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 10.13 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Offset error - ±1.0 ±7.5 LSB High-precision channel ±10.0 LSB Other than above Full-scale error - ±1.5 ±7.5 LSB High-precision channel ±10.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±3.0 ±8.0 LSB High-precision channel ±12.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - 14-bit mode Resolution - - 14 Bit - Table 2.46 A/D conversion characteristics (5) in low power A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions

R01DS0308EU0100 Rev.1.00 Page 94 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Conversion time*1 (Operation at PCLKC = 8 MHz) Permissible signal source impedance Max. = 5 kΩ 7.50 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 10.88 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Offset error - ±4.0 ±30.0 LSB High-precision channel ±40.0 LSB Other than above Full-scale error - ±6.0 ±30.0 LSB High-precision channel ±40.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±12.0 ±32.0 LSB High-precision channel ±48.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Table 2.48 A/D conversion characteristics (7) in low power A/D conversion mode (1 of 2) Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 4 MHz - Analog input capacitance Cs - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input resistance Rs - - 2.5 k Ω - Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution - - 12 Bit - Conversion time* (Operation at PCLKC = 4 MHz) Permissible signal source impedance Max. = 9.9 kΩ 13.5 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 20.25 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Offset error - ±1.0 ±7.5 LSB High-precision channel ±10.0 LSB Other than above Full-scale error - ±1.5 ±7.5 LSB High-precision channel ±10.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±3.0 ±8.0 LSB High-precision channel ±12.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - 14-bit mode Resolution - - 14 Bit - Table 2.47 A/D conversion characteristics (6) in low power A/D conversion mode (2 of 2) Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions

R01DS0308EU0100 Rev.1.00 Page 95 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Note 1. The internal reference voltage cannot be selected for input channels when AVCC0 < 2.0 V. Note 2. The 14-bit A/D internal reference voltage indicates the vo ltage when the internal reference voltage is input to the 14-bit A/D converter. Conversion time*1 (Operation at PCLKC = 4 MHz) Permissible signal source impedance Max. = 9.9 kΩ 15.0 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 21.75 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Offset error - ±4.0 ±30.0 LSB High-precision channel ±40.0 LSB Other than above Full-scale error - ±6.0 ±30.0 LSB High-precision channel ±40.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±12.0 ±32.0 LSB High-precision channel ±48.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Table 2.49 14-Bit A/D converter channel classification Classification Channel Conditions Remarks High-precision channel AN000 to AN014 AVCC0 = 1.6 to 5.5 V Pins AN000 to AN014 cannot be used as general I/O, IRQ2, IRQ3 inputs, and TS transmission, when the A/D converter is in use Normal-precision channel AN016 to AN025 Internal reference voltage input channel Internal reference voltage AVCC0 = 2.0 to 5.5 V - Temperature sensor input channel Temperature sensor output AVCC0 = 2.0 to 5.5 V - Table 2.50 A/D internal reference voltage characteristics Conditions: VCC = AVCC0 = VREFH0 = 2.0 to 5.5 V*1 Parameter Min Typ Max Unit Test conditions Internal reference voltage input channel*2 1.36 1.43 1.50 V - Sampling time 5.0 - - μs- Table 2.48 A/D conversion characteristics (7) in low power A/D conversion mode (2 of 2) Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions

R01DS0308EU0100 Rev.1.00 Page 96 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Figure 2.69 Illustration of 14-bit A/D converter characteristic terms Absolute accuracy Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of analog input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D conversion characteristics, is used as the analog input voltage. For example, if 12-bit resolution is used and the reference voltage VREFH0 = 3.072 V , then 1-LSB width becomes 0.75 mV, and 0 mV , 0.75 mV , and 1.5 mV are used as the analog input voltages. If analog input voltage is 6 mV , an absolute accuracy of ±5 LSB means that the actual A/D conversion result is in the range of 003h to 00Dh, though an output code of 008h can be expected from the theoretical A/D conversion characteristics. Integral nonlinearity error (INL) Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale errors are zeroed, and the actual output code. Differential nonlinearity error (DNL) Differential nonlinearity error is the difference between 1-LSB width based on the ideal A/D conversion characteristics and the width of the actually output code. Offset error Offset error is the difference between the transition point of the ideal first output code and the actual first output code. Full-scale error Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code. Integral nonlinearity error (INL) Actual A/D conversion characteristic Ideal A/D conversion characteristic Analog input voltage Offset error Absolute accuracy Differential nonlinearity error (DNL) Full-scale error FFFh 000h Ideal line of actual A/D conversion characteristic 1-LSB width for ideal A/D conversion characteristic Differential nonlinearity error (DNL) 1-LSB width for ideal A/D conversion characteristic VREFH0 (full-scale) A/D converter output code

R01DS0308EU0100 Rev.1.00 Page 97 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics

2.6 DAC12 Characteristics

Table 2.51 D/A conversion characteristics (1) Conditions: VCC = AVCC0 = 1.8 to 5.5 V Reference voltage = VREFH or VREFL selected Parameter Min Typ Max Unit Test conditions Resolution - - 12 bit - Resistive load 30 - - k Ω - Load capacitance - - 50 pF - Output voltage range 0.35 - AVCC0 – 0.47 V - DNL differential nonlinearity error - ±0.5 ±1.0 LSB - INL integral nonlinearity error - ±2.0 ±8.0 LSB - Offset error - - ±20 mV - Full-scale error - - ±20 mV - Output impedance - 5 - Ω - Conversion time - - 30 μs- Table 2.52 D/A conversion characteristics (2) Conditions: VCC = AVCC0 = 1.8 to 5.5 V Reference voltage = AVCC0 or AVSS0 selected Parameter Min Typ Max Unit Test conditions Resolution - - 12 bit - Resistive load 30 - - k Ω - Load capacitance - - 50 pF - Output voltage range 0.35 - AVCC0 – 0.47 V - DNL differential nonlinearity error - ±0.5 ±2.0 LSB - INL integral nonlinearity error - ±2.0 ±8.0 LSB - Offset error - - ±30 mV - Full-scale error - - ±30 mV - Output impedance - 5 - Ω - Conversion time - - 30 μs- Table 2.53 D/A conversion characteristics (3) Conditions: VCC = AVCC0 = 1.8 to 5.5 V Reference voltage = internal reference voltage selected Parameter Min Typ Max Unit Test conditions Resolution - - 12 bit - Internal reference voltage (Vbgr) 1.36 1.43 1.50 V - Resistive load 30 - - k Ω - Load capacitance - - 50 pF - Output voltage range 0.35 - Vbgr V - DNL differential nonlinearity error - ±2.0 ±16.0 LSB - INL integral nonlinearity error - ±8.0 ±16.0 LSB - Offset error - - ±30 mV - Output impedance - 5 - Ω - Conversion time - - 30 μs-

R01DS0308EU0100 Rev.1.00 Page 98 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Figure 2.70 Illustration of D/A converter characteristic terms Integral nonlinearity error (INL) Integral nonlinearity error is the maximum deviation between the ideal output voltage based on the ideal conversion characteristic when the measured offset and full-scale errors are zeroed, and the actual output voltage. Differential nonlinearity error (DNL) Differential nonlinearity error is the difference between 1-LSB voltage width based on the ideal D/A conversion characteristics and the width of the actual output voltage. Offset error Offset error is the difference between the highest actual output voltage that falls below the lower output limit and the ideal output voltage based on the input code. Full-scale error Full-scale error is the difference between the lowest actual output voltage that exceeds the upper output limit and the ideal output voltage based on the input code. 000h D/A converter input code FFFh Output analog voltage Upper output limit Lower output limit Offset error Ideal output voltage 1-LSB width for ideal D/A conversion characteristic Differential nonlinearity error (DNL) Actual D/A conversion characteristic Integral nonlinearity error (INL) Full-scale error Gain error Offset error Ideal output voltage Note 1. Ideal D/A conversion output voltage that is adjus ted so that offset and full scale errors are zeroed.

R01DS0308EU0100 Rev.1.00 Page 99 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics

2.7 TSN Characteristics

2.8 OSC Stop Detect Characteristics

Figure 2.71 Oscillation stop detection timing Table 2.54 TSN characteristics Conditions: VCC = AVCC0 = 2.0 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions Relative accuracy - - ±1.5 - °C 2.4 V or above - - ±2.0 - °C Below 2.4 V Temperature slope - - –3.65 - mV/°C - Output voltage (at 25°C) - - 1.05 - V VCC = 3.3 V Temperature sensor start time t START --5 μs- Sampling time - 5 - - μs- Table 2.55 Oscillation stop detection circuit characteristics Parameter Symbol Min Typ Max Unit Test conditions Detection time t dr --1 m s Figure 2.71 tdr Main clock OSTDSR.OSTDF MOCO clock ICLK PLL clock tdr Main clock OSTDSR.OSTDF MOCO clock ICLK When the main clock is selected When the PLL clock is selected

R01DS0308EU0100 Rev.1.00 Page 100 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics

2.9 POR and LVD Characteristics

Note 1. These characteristics apply when noise is not superimposed on the power supply. When a setting causes this voltage detection level to overlap with that of the voltage detection circuit, it cannot be specified whether LVD1 or LVD2 is used for voltage detection. Note 2. # in the symbol Vdet0_# denotes the value of the OFS1.VDSEL1[2:0] bits. Note 3. # in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[4:0] bits. Note 4. # in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[2:0] bits. Table 2.56 Power-on reset circuit and voltag e detection circuit characteristics (1) Parameter Symbol Min Typ Max Unit Test conditions Voltage detection level*1 Power-on reset (POR) V POR 1.27 1.42 1.57 V Figure 2.72, Figure 2.73 Voltage detection circuit (LVD0)*2 Vdet0_0 3.68 3.85 4.00 V Figure 2.74 At falling edge VCCV det0_1 2.68 2.85 2.96 Vdet0_2 2.38 2.53 2.64 Vdet0_3 1.78 1.90 2.02 Vdet0_4 1.60 1.69 1.82 Voltage detection circuit (LVD1)*3 Vdet1_0 4.13 4.29 4.45 V Figure 2.75 At falling edge VCCV det1_1 3.98 4.16 4.30 Vdet1_2 3.86 4.03 4.18 Vdet1_3 3.68 3.86 4.00 Vdet1_4 2.98 3.10 3.22 Vdet1_5 2.89 3.00 3.11 Vdet1_6 2.79 2.90 3.01 Vdet1_7 2.68 2.79 2.90 Vdet1_8 2.58 2.68 2.78 Vdet1_9 2.48 2.58 2.68 Vdet1_A 2.38 2.48 2.58 Vdet1_B 2.10 2.20 2.30 Vdet1_C 1.84 1.96 2.05 Vdet1_D 1.74 1.86 1.95 Vdet1_E 1.63 1.75 1.84 Vdet1_F 1.60 1.65 1.73 Voltage detection circuit (LVD2)*4 Vdet2_0 4.11 4.31 4.48 V Figure 2.76 At falling edge VCCVdet2_1 3.97 4.17 4.34 Vdet2_2 3.83 4.03 4.20 Vdet2_3 3.64 3.84 4.01

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2.10 VBATT Characteristics

Note: The VCC-off period for starting power supply switching indica tes the period in which VCC is below the minimum value of the voltage level for switching to battery backup (VDETBATT). Figure 2.77 Power supply switching and LVD0 reset timing Table 2.58 Battery backup function characteristics Conditions: VCC = AVCC0 = 1.6V to 5.5V, VBATT = 1.6 to 3.6 V Parameter Symbol Min Typ Max Unit Test conditions Voltage level for switching to battery backup (falling) V DETBATT 1.99 2.09 2.19 V Figure 2.77, Figure 2.78Hysteresis width for switching to battery back up V VBATTH - 100 - mV VCC-off period for starting power supply switching t VOFFBATT 300 - - μs- Voltage detection level VBATT_Power-on reset (VBATT_POR) VVBATPOR 1.30 1.40 1.50 V Figure 2.77, Figure 2.78 Wait time after VBATT_POR reset time cancellation t VBATPOR - - 3 mS - Level for detection of voltage drop on the VBATT pin (falling) VBTLVDLVL[1:0] = 10b V DETBATLVD 2.11 2.2 2.29 V Figure 2.79 VBTLVDLVL[1:0] = 11b 1.92 2 2.08 V Hysteresis width for VBATT pin LVD V VBATLVDTH - 50 - mV VBATT pin LVD operation stabilization time t d_vbat - - 300 μs Figure 2.79 VBATT pin LVD response delay time t det_vbat - - 350 μs Allowable voltage change rising/falling gradient dt/dVCC 1.0 - - ms/V - VCC voltage level for access to the VBATT backup registers V _BKBATT 1.8 - - V - VDETBATT VVBATH VCC supplied VBATT VCC VVBATPOR VBATT supplied VCC supplied Backup power area Internal reset signal (active-low) tLVD0 Vdet0 VLVH tdettdet VPOR

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2.11 CTSU Characteristics

Table 2.59 VBATT-I/O characteristics Parameter Symbol Min Typ Max Unit Test conditions VBATWIOn I/O output characteristics (n = 0 to 2) VCC > VDETBATT VCC = 4.0 to 5.5 V V OH VCC - 0.8 - - V I OH = -200 µA VOL -- 0 . 8 I OL = 200 µA VCC = 2.7 to 4.0 V V OH VCC - 0.5 - - I OH = -100 µA VOL -- 0 . 5 I OL = 100 µA VCC = VDETBATT to 2.7 V V OH VCC - 0.3 - - I OH = -50 µA VOL -- 0 . 3 I OL = 50 µA VCC < VDETBATT VBATT = 2.7 to 3.6 V V OH VBATT - 0.5 - - I OH = -100 µA VOL -- 0 . 5 I OL = 100 µA VBATT = 1.6 to 2.7 V V OH VBATT - 0.3 - - I OH = -50 µA VOL -- 0 . 3 I OL = 50 µA Table 2.60 CTSU characteristics Conditions: VCC = AVCC0 = 1.8 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions External capacitance connected to TSCAP pin C tscap 91 0 1 1 n F - TS pin capacitive load C base --5 0 p F - Permissible output high current ΣIoH - - -24 mA When the mutual capacitance method is applied

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2.12 Segment LCD Contro ller Characteristics

2.12.1 Resistance Division Method

[Static Display Mode] [1/2 Bias Method, 1/4 Bias Method] [1/3 Bias Method]

2.12.2 Internal Volt age Boosting Method

[1/3 Bias Method] Note 1. This is a capacitor that is conne cted between voltage pins used to drive the LCD. Table 2.61 Resistance division method LCD characteristics (1) Conditions: VL4 ≤ VCC ≤ 5.5 V Parameter Symbol Min Typ Max Unit Test conditions LCD drive voltage V L4 2.0 - VCC V - Table 2.62 Resistance division method LCD characteristics (2) Conditions: VL4 ≤ VCC ≤ 5.5 V Parameter Symbol Min Typ Max Unit Test conditions LCD drive voltage V L4 2.7 - VCC V - Table 2.63 Resistance division method LCD characteristics (3) Conditions: VL4 ≤ VCC ≤ 5.5 V Parameter Symbol Min Typ Max Unit Test conditions LCD drive voltage V L4 2.5 - VCC V - Table 2.64 Internal voltage boosting method LCD characteristics Conditions: VCC = 1.8 V to 5.5 V Parameter Symbol Conditions Min Typ Max Unit Test conditions LCD output voltage variation range VL1 C1 to C4*1 = 0.47 μF VLCD = 04h 0.90 1.0 1.08 V - VLCD = 05h 0.95 1.05 1.13 V - VLCD = 06h 1.00 1.10 1.18 V - VLCD = 07h 1.05 1.15 1.23 V - VLCD = 08h 1.10 1.20 1.28 V - VLCD = 09h 1.15 1.25 1.33 V - VLCD = 0Ah 1.20 1.30 1.38 V - VLCD = 0Bh 1.25 1.35 1.43 V - VLCD = 0Ch 1.30 1.40 1.48 V - VLCD = 0Dh 1.35 1.45 1.53 V - VLCD = 0Eh 1.40 1.50 1.58 V - VLCD = 0Fh 1.45 1.55 1.63 V - VLCD = 10h 1.50 1.60 1.68 V - VLCD = 11h 1.55 1.65 1.73 V - VLCD = 12h 1.60 1.70 1.78 V - VLCD = 13h 1.65 1.75 1.83 V - Doubler output voltage V L2 C1 to C4*1 = 0.47 μF2 × V L1 - 0.1 2 × V L1 2 × VL1 V- Tripler output voltage V L4 C1 to C4*1 = 0.47 μF3 × V L1 - 0.15 3 × V L1 3 × VL1 V- Reference voltage setup time*2 tVL1S 5 --m s Figure 2.80 LCD output voltage variation range*3 tVLWT C1 to C4*1 = 0.47 μF 500 - - ms

R01DS0308EU0100 Rev.1.00 Page 108 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = 0.47 μF ±30%. Note 2. This is the time required to wait from when the refer ence voltage is specified using the VLCD register (or when the internal voltage boosting method is selected (by setting the MDSET[1:0] bits in the LCDM0 register to 01b) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). Note 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). [1/4 Bias Method] Note 1. This is a capacitor that is connect ed between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL3 and GND C5: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = C5 = 0.47 μF ± 30% Note 2. This is the time required to wait from when the refer ence voltage is specified by using the VLCD register (or when the internal voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits in the LCDM0 register to 01b) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). Note 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). Note 4. V L4 must be 5.5 V or lower. Table 2.65 Internal voltage boosting method LCD characteristics Conditions: VCC = 1.8 V to 5.5 V Parameter Symbol Conditions Min Typ Max Unit Test conditions LCD output voltage variation range VL1 C1 to C5*1 = 0.47 μF VLCD = 04h 0.90 1.0 1.08 V - VLCD = 05h 0.95 1.05 1.13 V - VLCD = 06h 1.00 1.10 1.18 V - VLCD = 07h 1.05 1.15 1.23 V - VLCD = 08h 1.10 1.20 1.28 V - VLCD = 09h 1.15 1.25 1.33 V - VLCD = 0Ah 1.20 1.30 1.38 V - VLCD = 0Bh 1.25 1.35 1.43 V - VLCD = 0Ch 1.30 1.40 1.48 V - Doubler output voltage V L2 C1 to C5*1 = 0.47 μF2 V L1 - 0.08 2V L1 2VL1 V- Tripler output voltage V L3 C1 to C5*1 = 0.47 μF3 V L1 - 0.12 3V L1 3VL1 V- Quadruply output voltage VL4*4 C1 to C5*1 = 0.47 μF4 V L1 - 0.16 4V L1 4VL1 V- Reference voltage setup time*2 tVL1S 5 --m s Figure 2.80 LCD output voltage variation range*3 tVLWT C1 to C5*1 = 0.47 μF 500 - - ms

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2.12.3 Capacitor Split Method

[1/3 Bias Method] Note 1. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1). Note 2. This is a capacitor that is connect ed between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = 0.47 μF ± 30%. Figure 2.80 LCD reference voltage setup time, voltag e boosting wait time, and capacitor split wait time Table 2.66 Internal voltage boosting method LCD characteristics Conditions: VCC = 2.2 V to 5.5 V Parameter Symbol Conditions Min Typ Max Unit Test conditions VL4 voltage*1 VL4 C1 to C4 = 0.47 μF*2 -V C C - V - VL2 voltage*1 VL2 C1 to C4 = 0.47 μF*2 2/3 × VL4 - 0.07 2/3 × V L4 2/3 × VL4 + 0.07 V - VL1 voltage*1 VL1 C1 to C4 = 0.47 μF*2 1/3 × VL4 - 0.08 1/3 × V L4 1/3 × VL4 + 0.08 V - Capacitor split wait time*1 tWAIT 100 - - ms Figure 2.80 MDSET0, MDSET1 VLCON LCDON 01b or 10b00b tVL1S tVLWT, tWAIT

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2.13 Comparator Characteristics

Note: When 8-bit DAC output is used as the reference volt age, the offset voltage increases up to 2.5 x VCC/256. Note: In window mode, be sure to satisfy the following condition: VREFH - VREFL ≥ 0.2 V. Table 2.67 ACMPLP characteristics Conditions: VCC = 1.8 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions Reference voltage range Standard mode VREF 0 - VCC–1.4 V - Window mode CMPREF1 VREFH 1.4 - VCC V - CMPREF0 VREFL 0 - VCC–1.4 V - Input voltage range VI 0 - VCC V - Internal reference voltage - 1.36 1.44 1.50 V - Output delay High-speed mode Td - - 1.2 μs VCC = 3.0 Slew rate of input signal > 50 mV/μsLow-speed mode - - 5 μs Window mode - - 2 μs Offset voltage* Note: High-speed mode - - - 50 mV - Low-speed mode - - - 40 mV - Window mode - - - 60 mV - Operation stabilization wait time T cmp 100 - - μs-

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2.14 OPAMP Characteristics

Note 1. When the operational amplifier referenc e current circuit is activated in advance. Table 2.68 OPAMP characteristics Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V) Parameter Symbol Conditions Min Typ Max Unit Common mode input range Vicm1 Low-power consumption mode 0.2 - AVCC0 – 0.5 V Vicm2 High-speed mode 0.3 - AVCC0 – 0.6 V Output voltage range Vo1 Low-power consumption mode 0.1 - AVCC0 – 0.1 V Vo2 High-speed mode 0.1 - AVCC0 – 0.1 V Input offset voltage Vioff 3 σ –10 - 10 mV Open gain Av 60 120 - dB Gain-bandwidth (GB) product GBW1 Low-power consumption mode - 0.04 - MHz GBW2 High-speed mode - 1.7 - MHz Phase margin PM CL = 20 pF 50 - - deg Gain margin GM CL = 20 pF 10 - - dB Equivalent input noise Vnoise1 f = 1 kHz Low-power consumption mode - 230 - nV/ √Hz Vnoise2 f = 10 kHz - 200 - nV/ √Hz Vnoise3 f = 1 kHz High-speed mode - 90 - nV/ √Hz Vnoise4 f = 2 kHz - 70 - nV/ √Hz Power supply reduction ratio PSRR -9 0 - d B Common mode signal reduction ratio CMRR - 90 - dB Stabilization wait time Tstd1 CL = 20 pF Only operational amplifier is activated * Low-power consumption mode 650 - - μs Tstd2 High-speed mode 13 - - μs Tstd3 CL = 20 pF Operational amplifier and reference current circuit are activated simultaneously Low-power consumption mode 650 - - μs Tstd4 High-speed mode 13 - - μs Settling time Tset1 CL = 20 pF Low-power consumption mode - - 750 μs Tset2 High-speed mode - - 13 μs Slew rate Tslew1 CL = 20 pF Low-power consumption mode -0 . 0 2 - V / μs Tslew2 High-speed mode - 1.1 - V/ μs Load current Iload1 Low-power mode –100 - 100 μA Iload2 High-speed mode –100 - 100 μA Load capacitance CL --2 0 p F

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2.15 Flash Memory Characteristics

2.15.1 Code Flash Memory Characteristics

Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 1,000), erasing can be done n times for each block. For instance, when 8-byte programming is performed 256 times for different addresses in 2-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming the same address for several times as one erasure is not enabled (overwriting is prohibited). Note 2. Characteristic when using the flash memory programmer and the self-programming library provided by Renesas Electronics. Note 3. This result is obtained from reliability testing. Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software. Note: The lower-limit frequency of FCLK is 1 MHz during progra mming or erasing the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note: The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source. Table 2.69 Code flash characteristics (1) Parameter Symbol Min Typ Max Unit Test conditions Reprogramming/erasure cycle*1 NPEC 1000 - - Times - Data hold time After 1000 times of N PEC tDRP 20*2, *3 --Y e a r T a = +85°C Table 2.70 Code flash characteristics (2) High-speed operating mode Conditions: VCC = 2.7 to 5.5 V Parameter Symbol FCLK = 1 MHz FCLK = 32 MHz UnitMin Typ Max Min Typ Max Programming time 8-byte t P8 - 116 998 - 54 506 μs Erasure time 2-KB t E2K - 9.03 287 - 5.67 222 ms Blank check time 8-byte t BC8 - - 56.8 - - 16.6 μs 2-KB t BC2K - - 1899 - - 140 μs Erase suspended time t SED - - 22.5 - - 10.7 μs Startup area switching setting time t SAS - 21.7 585 - 12.1 447 ms Access window time t AWS - 21.7 585 - 12.1 447 ms OCD/serial programmer ID setting time t OSIS - 21.7 585 - 12.1 447 ms ROM mode transition wait time 1 t DIS 2- - 2- - μs ROM mode transition wait time 2 t MS 5- - 5- - μs

R01DS0308EU0100 Rev.1.00 Page 113 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software. Note: The lower-limit frequency of FCLK is 1 MHz during progra mming or erasing the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note: The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source.

2.15.2 Data Flash Memory Characteristics

Note 1. The reprogram/erase cycle is the number of erasure for ea ch block. When the reprogram/erase cycle is n times (n = 100,000), erasing can be performed n times for each block. For instance, when 1-byte programming is performed 1,000 times for different addresses in 1-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming the same address for several times as one erasure is not enabled. (overwriting is prohibited). Note 2. Characteristics when using the flash memory programmer and the self-programming library provided by Renesas Electronics. Note 3. These results are obtained from reliability testing. Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software. Note: The lower-limit frequency of FCLK is 1 MHz during progra mming or erasing the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note: The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source. Table 2.71 Code flash characteristics (3) Middle-speed operating mode Conditions: VCC = 1.8 to 5.5 V, Ta = –40 to +85°C Parameter Symbol FCLK = 1 MHz FCLK = 8 MHz UnitMin Typ Max Min Typ Max Programming time 8-byte t P8 - 157 1411 - 101 966 μs Erasure time 2-KB t E2K - 9.10 289 - 6.10 228 ms Blank check time 8-byte t BC8 - - 87.7 - - 52.5 μs 2-KB t BC2K - - 1930 - - 414 μs Erase suspended time t SED - - 32.7 - - 21.6 μs Startup area switching setting time t SAS - 22.5 592 - 14.0 464 ms Access window time t AWS - 22.5 592 - 14.0 464 ms OCD/serial programmer ID setting time t OSIS - 22.5 592 - 14.0 464 ms Flash memory mode transition wait time 1 t DIS 2 --2 -- μs Flash memory mode transition wait time 2 t MS 720 - - 720 - - ns Table 2.72 Data flash characteristics (1) Parameter Symbol Min Typ Max Unit Test conditions Reprogramming/erasure cycle*1 NDPEC 100000 1000000 - Times - Data hold time After 10000 times of N DPEC tDDRP 20*2, *3 - - Year Ta = +85°C After 100000 times of NDPEC 5*2, *3 - - Year After 1000000 times of NDPEC -1 * 2, *3 - Year Ta = +25°C Table 2.73 Data flash characteristics (2) High-speed operating mode Conditions: VCC = 2.7 to 5.5 V Parameter Symbol FCLK = 4 MHz FCLK = 32 MHz UnitMin Typ Max Min Typ Max Programming time 1-byte t DP1 - 52.4 463 - 42.1 387 μs Erasure time 1-KB t DE1K - 8.98 286 - 6.42 237 ms Blank check time 1-byte t DBC1 - - 24.3 - - 16.6 μs 1-KB t DBC1K - - 1872 - - 512 μs Suspended time during erasing t DSED - - 13.0 - - 10.7 μs Data flash STOP recovery time t DSTOP 5- - 5- - μs

R01DS0308EU0100 Rev.1.00 Page 114 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software. Note: The lower-limit frequency of FCLK is 1 MHz during progra mming or erasing the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note: The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source.

2.16 Boundary Scan

Note 1. Boundary scan does not function unt il power-on-reset becomes negative. Figure 2.81 Boundary scan TCK timing Table 2.74 Data flash characteristics (3) Middle-speed operating mode Conditions: VCC = 1.8 to 5.5 V, Ta = –40 to +85°C Parameter Symbol FCLK = 4 MHz FCLK = 8 MHz UnitMin Typ Max Min Typ Max Programming time 1-byte t DP1 - 94.7 886 - 89.3 849 μs Erasure time 1-KB t DE1K - 9.59 299 - 8.29 273 ms Blank check time 1-byte t DBC1 - - 56.2 - - 52.5 μs 1-KB t DBC1K - - 2.17 - - 1.51 ms Suspended time during erasing t DSED - - 23.0 - - 21.7 μs Data flash STOP recovery time t DSTOP 720 - - 720 - - ns Table 2.75 Boundary scan Conditions: VCC = AVCC0 = 2.4 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions TCK clock cycle time t TCKcyc 100 - - ns Figure 2.81 TCK clock high pulse width t TCKH 45 - - ns TCK clock low pulse width t TCKL 45 - - ns TCK clock rise time t TCKr -- 5 n s TCK clock fall time t TCKf -- 5 n s TMS setup time t TMSS 20 - - ns Figure 2.82 TMS hold time t TMSH 20 - - ns TDI setup time t TDIS 20 - - ns TDI hold time t TDIH 20 - - ns TDO data delay t TDOD - - 70 ns Boundary Scan circuit start up time*1 tBSSTUP tRESWP --- Figure 2.83 tTCKcyc tTCKH tTCKf tTCKL tTCKr TCK

R01DS0308EU0100 Rev.1.00 Page 115 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Figure 2.82 Boundary scan input/output timing Figure 2.83 Boundary scan circuit start up timing

2.17 Joint European Test Action Group (JTAG)

Table 2.76 JTAG (debug) characteristics (1) Conditions: VCC = 2.4 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions TCK clock cycle time t TCKcyc 80 - - ns Figure 2.84 TCK clock high pulse width t TCKH 35 - - ns TCK clock low pulse width t TCKL 35 - - ns TCK clock rise time t TCKr -- 5 n s TCK clock fall time t TCKf -- 5 n s TMS setup time t TMSS 16 - - ns Figure 2.85 TMS hold time t TMSH 16 - - ns TDI setup time t TDIS 16 - - ns TDI hold time t TDIH 16 - - ns TDO data delay time t TDOD - - 70 ns tTMSS tTMSH tTDIS tTDIH tTDOD TCK TMS TDI TDO tBSSTUP (= tRESWP) VCC RES Boundary scan execute

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2.17.1 Serial Wire Debug (SWD)

Figure 2.86 SWD SWCLK timing Table 2.78 SWD characteristics (1) Conditions: VCC = 2.4 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time t SWCKcyc 80 - - ns Figure 2.86 SWCLK clock high pulse width t SWCKH 35 - - ns SWCLK clock low pulse width t SWCKL 35 - - ns SWCLK clock rise time t SWCKr -- 5 n s SWCLK clock fall time t SWCKf -- 5 n s SWDIO setup time t SWDS 16 - - ns Figure 2.87 SWDIO hold time t SWDH 16 - - ns SWDIO data delay time t SWDD 2 - 70 ns Table 2.79 SWD characteristics (2) Conditions: VCC = 1.6 to 2.4 V Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time t SWCKcyc 250 - - ns Figure 2.86 SWCLK clock high pulse width t SWCKH 120 - - ns SWCLK clock low pulse width t SWCKL 120 - - ns SWCLK clock rise time t SWCKr -- 5 n s SWCLK clock fall time t SWCKf -- 5 n s SWDIO setup time t SWDS 50 - - ns Figure 2.87 SWDIO hold time t SWDH 50 - - ns SWDIO data delay time t SWDD 2 - 150 ns SWCLK tSWCKcyc tSWCKH tSWCKf tSWCKr tSWCKL

R01DS0308EU0100 Rev.1.00 Page 118 of 129 Apr 4, 2017 S3A6 Group MCUs 2. Electrical Characteristics Figure 2.87 SWD input/output timing SWDIO (Output) SWDIO (Output) SWDIO (Output) tSWDD tSWDD tSWDD SWCLK SWDIO (Input) tSWDS tSWDH

R01DS0308EU0100 Rev.1.00 Page 119 of 129 Apr 4, 2017 S3A6 Group MCUs Appendix 1. Package Dimensions Appendix 1.Package Dimensions Information on the latest version of the package dimensions or mountings is displayed in “Packages” on the Renesas Electronics Corporation website. Figure 1.1 LGA 100-pin P-TFLGA100-7x7-0.65 0.1g MASS[Typ.] 100F0GPTLG0100JA-A RENESAS CodeJEITA Package Code Previous Code 0.15v 0.20w 0.08 0.4850.4350.385 MaxNomMin Dimension in Millimeters Symbol Reference 7.0D 7.0E 1.05A x 0.65e 0.10y b 0.31 0.35 0.39 0.575ZD ZE 0.575 Index mark Bw Sw A S A H G F E D C B 12345678yS S A v (Laser mark) Index mark J K 91 0 D E e e A ZD ZE B φ b φ b1 φ× MS A B φ× MS A B

R01DS0308EU0100 Rev.1.00 Page 120 of 129 Apr 4, 2017 S3A6 Group MCUs Appendix 1. Package Dimensions Figure 1.2 LQFP 100-pin MASS (Typ) [g] 0.6 Unit: mm Previous CodeRENESAS Code PLQP0100KB-B — P-LFQFP100-14x14-0.50 © 2015 Renesas Electronics Corporation. All rights reserved. D E HD HE A bp c T e x y L p 13.9 13.9 15.8 15.8 0.05 0.15 0.09 0.45 Min Nom Dimensions in millimetersReference Symbol Max 14.0 14.0 1.4 16.0 16.0 0.20 3.5q 0.5 0.6 1.0 14.1 14.1 16.2 16.2 1.7 0.15 0.27 0.20 0.08 0.08 0.75 NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. T HD A2A1 Lp Detail F A c 0.25 D 100 26 251 F NOTE 4 NOTE 3 Index area HE E*2 *3 bpe yS S M

R01DS0308EU0100 Rev.1.00 Page 121 of 129 Apr 4, 2017 S3A6 Group MCUs Appendix 1. Package Dimensions Figure 1.3 LQFP 64-pin MASS (Typ) [g] 0.3 Unit: mm Previous CodeRENESAS Code PLQP0064KB-C — P-LFQFP64-10x10-0.50 © 2015 Renesas Electronics Corporation. All rights reserved. D E HD HE A bp c T e x y L p 9.9 9.9 11.8 11.8 0.05 0.15 0.09 0.45 Min Nom Dimensions in millimetersReference Symbol Max 10.0 10.0 1.4 12.0 12.0 0.20 3.5q 0.5 0.6 1.0 10.1 10.1 12.2 12.2 1.7 0.15 0.27 0.20 0.08 0.08 0.75 NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. HD A2A1 Lp Detail F A c 0.25 D 48 33 3249 161 F NOTE 4 NOTE 3 Index area HE E*2 bpe yS S M T

R01DS0308EU0100 Rev.1.00 Page 122 of 129 Apr 4, 2017 S3A6 Group MCUs Appendix 1. Package Dimensions Figure 1.4 QFN 64-pin 2013 Renesas Electronics Corporation. All rights reserved. Sy e Lp SxbA B M A D E A S B A D E DETAIL OF A PART EXPOSED DIE PAD P-HWQFN64-8x8-0.40 PWQN0064LA-A 0.16 161 3249 INDEX AREA D A Lp 0.20 6.50 0.40 8.00 8.00 6.50 Referance Symbol Min Nom Max Dimension in Millimeters 0.23 0.30 0.50 b 0.17 x A 0.80 y 0.05 0.00 0.20 e Z Z c D E D E E 0.40 0.05 1.00 1.00 0.15 0.25 A1 c 2 8.057.95 8.057.95 Z Z D E 3348 P64K8-40-9B5-3

R01DS0308EU0100 Rev.1.00 Page 123 of 129 Apr 4, 2017 S3A6 Group MCUs Appendix 1. Package Dimensions Figure 1.5 LQFP 48-pin MASS (Typ) [g] 0.2 Unit: mm Previous CodeRENESAS Code PLQP0048KB-B — P-LFQFP48-7x7-0.50 D E HD HE A bp c T e x y L p 6.9 6.9 8.8 8.8 0.05 0.17 0.09 0.45 Min Nom Dimensions in millimetersReference Symbol Max 7.0 7.0 1.4 9.0 9.0 0.20 3.5q 0.5 0.6 1.0 7.1 7.1 9.2 9.2 1.7 0.15 0.27 0.20 0.08 0.08 0.75 NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. HD A2A1 Lp Detail F A c 0.25 HE D E 36 25 25 11 2 F NOTE 4 NOTE 3 Index area bpe yS S M T

R01DS0308EU0100 Rev.1.00 Page 124 of 129 Apr 4, 2017 S3A6 Group MCUs Appendix 1. Package Dimensions Figure 1.6 QFN 48-pin 2013 Renesas Electronics Corporation. All rights reserved. Sy e Lp SxbA B M A D E A S B A D E DETAIL OF A PART EXPOSED DIE PAD P-HWQFN48-7x7-0.50 PWQN0048KB-A 48PJN-A 0.13 121 2437 INDEX AREA D A Lp 0.20 5.50 0.40 7.00 7.00 5.50 Referance Symbol Min Nom Max Dimension in Millimeters 0.30 0.30 0.50 b 0.18 x A 0.80 y 0.05 0.00 0.25 e Z Z c D E D E E 0.50 0.05 0.75 0.75 0.15 0.25 A1 c 2 7.056.95 7.056.95 Z Z D E 2536 P48K8-50-5B4-6

R01DS0308EU0100 Rev.1.00 Page 125 of 129 Apr 4, 2017 S3A6 Group MCUs Appendix 1. Package Dimensions Figure 1.7 QFN 40-pin Sy e Lp SxbA B M A D E A S B A D E DETAIL OF A PART EXPOSED DIE PAD P-HWQFN40-6x6-0.50 PWQN0040KC-A P40K8-50-4B4-5 0.09 101 2031 INDEX AREA D A Lp 0.20 4.50 0.40 6.00 6.00 4.50 Referance Symbol Min Nom Max Dimension in Millimeters 0.30 0.30 0.50 b 0.18 x A 0.80 y 0.05 0.00 0.25 e Z Z c D E D E E 0.50 0.05 0.75 0.75 0.15 0.25 A1 c 2 6.055.95 6.055.95 Z Z D E 2130

Revision History S3A6 Group Microcontrollers Datasheet Proprietary Notice All text, graphics, photographs, trademarks, logos, artwork and computer code, collectively known as content, contained in this document is owned, controlled or licensed by or to Renesas, and is protected by trade dress, copyright, patent and trademark laws, and other intellectual property rights and unfair competition laws. Except as expressly provided herein, no part of this document or content may be copied, reproduced, republished, posted, publicly displayed, encoded, translated, transmitted or distributed in any other medium for publication or distribution or for any commercial enterprise, without prior written consent from Renesas. ARM® and Cortex® are registered trademarks of ARM Limited. CoreSight™ is a trademark of ARM Limited. CoreMark® is a registered trademark of the Embedded Microprocessor Benchmark Consortium. Magic Packet™ is a trademark of Advanced Micro Devices, Inc. SuperFlash® is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Other brands and names mentioned in this document may be the trademarks or registered trademarks of their respective holders. Rev. Date Summary

1.00 Apr 4, 2017 First release

Revision History

S3A6 Group Microcontrollers Datasheet Publication Date: Rev.1.00 Apr 4, 2017 Published by: Renesas Electronics Corporation Colophon

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