S32V232

S32V234 NXP | Alldatasheet

Document overview

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Technical content

Features

• ARM® Cortex®-A53, 64-bit CPU – Up to 1000 MHz Quad ARM Cortex-A53 – 32 KB/32 KB I-/D- L1 Cache – NEON MPE co-processor – Dual precision FPU – 2 clusters with 2 CPUs and 256 KB L2 cache each – Memory Management Unit – GIC Interrupt Controller – ECC/parity error support for its memories – Generic timers – Fault encapsulation by hardware for redundant executed application software on multiple core cluster
• ARM Cortex-M4, 32-bit CPU – Up to 133 MHz – 16 KB/16 KB I-/D- L1 Cache – 32+32 KB tightly coupled memory (TCM) – ECC/parity support for its memories
• Clocks – Phase Locked Loops (PLLs) – 1 external crystal oscillator (FXOSC) – 1 FIRC oscillator
• System protection and power management features – Flexible run modes to consume low power based on application needs – Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents – Power gating of unused A53 cores and GPU – Low and high voltage warning and detect – Hardware CRC module to support fast cyclic redundancy checks (CRC) – 120-bit unique chip identifier – Hardware watchdog – eDMA controller with 32 channels (with DMAMUX) – Extended Resource Domain Controller
• Safety concept – ISO 26262, ASIL level target – Measures to detect faults in memory and logic – Measures to detect single point and latent faults – Quantitative out of context analysis of functional safety (FMEDA) tailored to application specifics – Safety manual and FMEDA report available
• Security – CSE with 16 KB of on-chip Secure RAM and ROM. – ARM TrustZone (TZ) architecture support – Boot from NOR flash with AES-128 (CTR) – On-Chip One-Time Programmable element Controller (OCOTP_CTRL) with on chip electrical fuse array. – System JTAG Controller (SJC)
• Debug functionality – Standard JTAG and Compact JTAG – 16-bit Trace port, Serial Wire Output port
• Timers – General purpose timers (FTM) – Two Periodic Interrupt Timer (PIT) – IEEE 1588 Timers (part of Ethernet Subsystem)
• Analog – 1x 12-bit 1.8 V SAR ADC with self-test
• Communications – UART(w/ LIN2.1l) – Serial peripheral interface (SPI) – I2C blocks – PCI express 2.0 with endpoint and root complex support – LFAST serial link – 1 GBit Ethernet with PTP IEEE 1588 – FD-CAN – FlexRay Dual Channel, Version 2.1 RevA NXP Semiconductors Document Number S32V234 Data Sheet: Technical Data Rev. 9, 03/2020 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

• Memory interfaces – 32-bit DRAM Controller with support for LPDDR2/DDR3/DDR3L - Data rate of up to 1066 MT/s at 533 MHz clock frequency with ECC (SEC-DED-TED) triple error detection support for subregion – QuadSPI supporting Execute-In-Place (XIP) – Boot flash fault detection and correction using two-dimensional parity. – Triple fault detection and single fault correction scheme for external DDR-RAM including address/page fault detection.
• Video input interfaces, Image processing, graphics processing, display – Display Control Unit (2D-ACE) with 24-bit RGB, GPU frame buffer decoding – GPU GC3000 with frame buffer compression – 2x VIU (Video interface unit) for camera input – 2x MIPICSI2 with four lanes for camera input (support 1080 pixel @ 30 fps) – Image signal processor (ISP), supporting 2x1 or 1x2 megapixel @ 30 fps and 4x2 megapixel for subset of functions (exposure control, gamma correction) – 2x APEX2-CL Image cognition processor. APEX-642CL comprises two Array Processing Unit (APU) cores configurable as single SIMD engine with 64 16-bit Computational Units (CU), or configurable as two core MIMD engines with 32 16-bit CUs each. – CUs are comprised of four Functional Units: 16-bit Multiplier, Load Store Unit, ALU, and Shifter – JPEG video decoder (8/12-bit) – H.264 video decoder (8/10/12-bit), High-intra and constrained baseline formats – H.264 video encode (8/10/12-bit), High-intra only – Fast DMA for data transfers between DRAM and System RAM with CRC
• Human-Machine Interface (HMI) – GPIO pins with interrupt support, DMA request capability, digital glitch filter – Configurable slew rate and drive strength on all output pins
• System RAM – 4 MB On-Chip System RAM with ECC S32V234 Data Sheet, Rev. 9, 03/2020

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4.3 Power Management Controller (PMC) electrical

5.2.1.1 DDR3 mode DC electrical

5.2.2.1 DDR3L mode DC electrical

5.2.3.1 LPDDR2 mode DC electrical

6.4 DDR SDRAM Specific Parameters (DDR3, DDR3L, and

6.5.2 Ultra High Speed SD/SDIO/MMC Host Interface

6.5.3.2 LFAST Interface electrical

6.5.5.2 Receive and Transmit signal timing

6.5.5.3 Receive and Transmit signal timing

6.5.5.4 Receive and Transmit signal timing

6.5.5.5 MII/RMII Serial Management channel

S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 3

6.6.1.2 Interface to TFT LCD Panels—Pixel

6.6.1.3 Interface to TFT LCD panels—access

6.6.3 MIPICSI2 D-PHY electrical and timing parameters.65 S32V234 Data Sheet, Rev. 9, 03/2020

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1 Block diagram

10 Mbps

1 Gbps

5 Gbps

4 Lanes

• • • OCOTP_CTRL Wake Up SIUL SARADC_0 FlexTimer_0 IIC_0 Linflex_0 CAN_FD_0 DSPI_0 DSPI_2 CRC_0 FCCU CRC_1 DSPI_3 DSPI_1 CAN_FD_1 Linflex_1 IIC_2 IIC_1 FlexTimer_1 SWT_4 SWT_3 SWT_2 STM_1 INTC_MON CGM-CMUs PIT_1 SSE TSENS PMC ERM + EIM MSCM SEMA4 MEMU 32-bits MC MPU Debug Debug Debug Debug Debug Debug Debug Debug Debug 16-bit VIU Seq GIC-400

533 MHz

1066 MT/s

Figure 1. Block diagram

2 Family comparison

2.1 Feature Set

Table 1. Feature Set

• 32 KB/32 KB I-/D- L1 Cache
• NEON MPE co-processor
• Dual precision FPU
• 256 KB L2 Cache per cluster
• MMU
• GIC interrupt controller
• Up to 1000 MHz Dual ARM Cortex-A53 (single cluster)
• The remaining features are same as S32V234 Table continues on the next page... Block diagram S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 5

Table 1. Feature Set (continued)

• ECC/parity error support for its memories
• Generic timers ARM Cortex-M4 Core • Up to 133 MHz
• 16 KB/16 KB I-/D- L1 Cache
• 32+32 KB tightly coupled memory (TCM)
• ECC/parity support for its memories
• Same as S32V234 Clocks • Phase Locked Loops (PLLs)
• 1 external crystal ocillators (FXOSC)
• 1 FIRC
• Same as S32V234 System, protection and power management features
• Flexible run modes to consume lower power based on application needs.
• Peripheral clock enable registers can disable clocks to unused modules, thereby reducing currents
• Low and high voltage warning and detect
• Hardware CRC module to support fast cyclic redundancy checks (CRC)
• 120-bit unique chip identifier
• Hardware watchdog
• Safe eDMA controller with 32 channels (with DMAMUX)
• Extended Resource Domain Controller
• Same as S32V234 Safety concept • ISO 26262, ASIL level target as per safety concept
• Measures detecting faults in memory and logic
• Measures to detect single point and latent faults
• Quantitative out of context analysis of functional safety (FMEDA) tailored to application specifics
• Safety manual and FMEDA report available
• Boot flash authentication and fault detection and correction using AES-128 and two-dimensional parity.
• Double and triple fault detection and single fault correction scheme for external DDR-RAM including address/ page fault detection.
• Fault encapsulation by hardware for redundant executed application software on multiple core cluster.
• Structural software based self test routines providing high diagnostic coverage.
• Same as S32V234 Debug • Standard JTAG
• 16-bit Trace port, Serial Wire Output port
• Same as S32V234 Timers • General purpose timers (FTM) • Same as S32V234 Table continues on the next page... Family comparison S32V234 Data Sheet, Rev. 9, 03/2020

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• Two Periodic Interrupt Timer (PIT)
• IEEE 1588 Timers (part of Ethernet Subsystem) Communications • UART(w/ LIN2.1l)
• Serial peripheral interface (SPI)
• I2C blocks
• PCI express 2.0 with endpoint and root complex support
• LFAST serial link
• 1 GBit Ethernet with PTP IEEE 1588
• FD-CAN
• Flexray Dual Channel, Version 2.1 RevA
• Same as S32V234 Memory Interfaces • 32-bit DRAM Controller with support for LPDDR2/DDR3/DDR3L - Data rate of up to 1066 MT/s at 533 MHz clock frequency with ECC (SEC-DED-TED) single error correction, double error detection, and triple error detection support for subregion
• Dual QuadSPI supporting Execute-In- Place (XIP)
• Same as S32V234 Video input interfaces, Image processing, graphics processing, display
• Display Control Unit (2D-ACE) with 24- bit RGB, GPU framebuffer decoding
• GPU GC3000 with frame buffer compression
• 2x Video interface unit (VIU) for camera input
• 2x CSI with 4 lanes for camera input (support 1080p @ 30fps)
• Image signal processor (ISP), supporting 2x1 or 1x2 MPixel @ 30fps and 4x1 MPixel for subset of functions (exposure control, gamma correction)
• 2x APEX2-CL Image cognition processor (dual 32-bit array processor)
• JPEG video decoder (8/12-bit)
• H.264 video decoder (8/10/12-bit), High- intra and constrained baseline formats
• H.264 video encoder (8/10/12-bit), I- frames only
• Safe Fast DMA for data transfers between DRAM and System RAM with CRC
• Same as S32V234 Analog • 1x 12-bit SAR ADC with self-test • Same as S32V234 Human-Machine Interface (HMI)
• SIUL, GPIO pins with interrupt support, DMA request capability, digital glitch filter.
• Configurable slew rate and drive strength on all output pins
• Same as S32V234 System RAM • 4 MB On-Chip System RAM with ECC • 3 MB On-Chip System RAM with ECC Power Consumption • Run modes: • Same as S32V234 Family comparison S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 7

• Frequency scaling and clock gating for processing blocks and peripherals in run mode Ordering parts

3.1 Ordering information

4 B K N1 V UB R

4.1 Operation above maximum operating conditions

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Table 2. Operation above maximum operating conditions

1.8 V DGO Voltage Domain

3.0 V < 60 s 25 °C

2.3 V < 10 hr 25 °C

1.29 V < 60 s 25 °C

1.1 V < 10 hr 25 °C

3.3 V DGO Voltage Domain

4.95 V < 60 s 25 °C

4.29 V < 10 hr 25 °C

4.2 Recommended operating conditions

Table 3. Recommended operating conditions Table continues on the next page...

Table 3. Recommended operating conditions (continued)

1. All the grounds viz. VSS, VSS_FXOSC, and VSS_HV_ADV are tied together at the package level.
2. VDD_LV_CORE_SOC, VDD_LV_CORE_ARM, and VDD_LV_CORE_GPU supply balls should all be connected together to one power

power gated as they are not used, the VDD_LV_CORE_ARM supply balls have to be statically connected to the ground plane.

1. Maximum ambient temperature requires management of the heat dissipation to ensure the device junction temperature

does not exceed the maximum.

4.3 Power Management Controller (PMC) electrical specifications

• Low voltage detector (LVD_33_PMC) for 3.3 V VDD_GPIO0 supply (GPIO segment and PMC) and Low Voltage Detector for FIRC (VDD_HV_FXOSC)
• Low voltage detector (LVD_18) for VDD_HV_PMC
• Low voltage detector (LVD_18) for VDD_HV_FXOSC
• High voltage detector (HVD_18) for VDD_HV_PMC
• Low voltage detector (LVD_CORE) for VDD_LV_CORE_SOC
• High voltage detector (HVD_CORE) for VDD_LV_CORE_SOC
• Power on Reset (POR) General S32V234 Data Sheet, Rev. 9, 03/2020

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Table 4. PMC electrical specifications

1. Lower threshold/assert point
2. Upper threshold/release point

4.4 Power consumption

to change per device characterization. Table 5. Power consumption Table continues on the next page...

Table 5. Power consumption (continued) Table continues on the next page...

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1. Data represented is at 125 °C Tj and 1.01 V vdd conditions
2. Includes SoC, GPU, and ARM supply combinations depending on use case description.
3. Adder to the static idd current component. 4xCortex A53 executing Dhrystone MIPS in AArch64 and the interconnect,

4.5 Electrostatic discharge (ESD) specifications

Q100-002/-011 to meet the HBM and CDM ratings described below. Table 6. ESD ratings 1

1. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification

room temperature followed by hot temperature, unless specified otherwise in the device specification.

1. Data based on characterization results, not tested in production.

4.6 Electromagnetic Compatibility (EMC) specifications

EMC measurements to IC-level IEC standards are available from NXP on request.

4.7 PCB routing guidelines

• CLK/Addess/Commands
• Route with 50 ohm controlled impedance and differential pair (CLK) with 100 ohm controlled impedance
• Use Fly by topology in case of multiple memory components
• Address and command lines Terminated to VTT with 50 ohm
• To be referenced with Power, not Ground General S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 13

• Address/Cmd to be routed within 66 mils with respect to CLK and to be matched from controller to memory; memory to memory as well
• All traces to be routed in internal layers
• Preference is to use only two layers for routing this group
• Limit the via number to less than three NOTE The differential clock lines on the DDR3 interface should use AC termination scheme, with a 0.1 µF series capacitor and referenced to DDR IO supply (VDD_DDR_IO).
• Data/Strobe
• Route with 50 ohm controlled impedance and differential pair (DQS strobe) with 100 ohm controlled impedance
• Data to be routed within 33 mils with respect to respective strobe
• To be referenced with Ground
• All traces to be routed in internal layers
• Strictly to be routed in only two layers
• Avoid more than two vias LPDDR2 PCB design
• CLK/Addess/Commands
• Route with 50 ohm controlled impedance and differential pair (CLK) with 100 ohm controlled impedance
• To be referenced with Power, not Ground
• Address/Cmd to be routed within 66 mils with respect to CLK and to be matched from controller to memory
• All traces to be routed in internal layers and delay should be less than 150 ps
• Preference is to use only two layers for routing this group
• Limit the via number to less than three
• Data/Strobe
• Route with 50 ohm controlled impedance and differential pair (DQS strobe) with 100 ohm controlled impedance
• Data to be routed within 33 mils with respect to respective strobe
• To be referenced with Ground
• All traces to be routed in internal layers and delay should be less than 150 ps
• Strictly to be routed in only two layers
• Avoid more than two vias GPIO Interfaces
• QuadSPI
• Put 22 ohm series termination on board when operating with SIUL2_MSCRn[DSE] 111 General S32V234 Data Sheet, Rev. 9, 03/2020

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• TRACE
• Put 22 ohm series termination on board when operating with SIUL2_MSCRn[DSE] 111
• ENET
• Put 22 ohm series termination on board when operating with SIUL2_MSCRn[DSE] 111 I/O parameters General purpose I/O parameters

5.1.1 GPIO speed at various voltage levels

packages and boards, use appropriate I/O IBIS model. Table 7. GPIO rise/fall times (1.8 V range)

Table 8. GPIO rise/fall times (2.5 V range) Table 9. GPIO rise/fall times (3.3 V range)

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low to logic high or vice versa.

5.1.2 DC electrical specifications

Table 10. DC electrical specifications

1. ovdd is the IO supply for the pads.
2. Max condition: bcs model, 3.6 V, and 125 °C. These values are for I/O buffers.

register to ensure optimum performance of the GPIO pads. Table 11. Current-draw Characteristics for DDR_VREF

5.2 DDR pads

5.2.1 DDR3 mode

5.2.1.1 DDR3 mode DC electrical specifications

Table 12. DDR3 mode DC electrical specifications

1. Vtt is expected to track ovdd/2.
2. Vtt is not applied directly to the device. Minimum and Maximum values are system dependant.
3. Typ condition: typ model, 1.5 V, and 25 °C, max condition: wcs model, 1.425 V, and 125 °C, min condition: bcs model,

5.2.2 DDR3L mode

5.2.2.1 DDR3L mode DC electrical specifications

Table 13. DDR3L mode DC electrical specifications Table continues on the next page...

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Table 13. DDR3L mode DC electrical specifications (continued)

1. Vtt is not applied directly to the device. Minimum and Maximum values are system dependant.

5.2.3.1 LPDDR2 mode DC electrical specifications

Table 14. LPDDR2 mode DC electrical specifications

1. Typ condition: typ model, 1.2 V, and 25 °C, max condition: wcs model, 1.14 V, and 125 °C, min condition: bcs model, 1.32

5.3 Boot Configuration Pins Specification

Value driven on RCON and BOOTMOD pins should be stable for at least 1 µs after RESET pin is deasserted. NOTE External pull up/down resistors must be used on the BOOTMOD pins in order to ensure latching at the correct state. NOTE NXP would anticipate that most customers would use the boot from fuses option in a production environment. However, there is no reliability impact if the device is configured by RCON rather than fuses. Peripheral operating requirements and behaviors Analog modules

6.1.1 ADC electrical specifications

The device provides a 12-bit Successive Approximation Register (SAR) Analog-to- Digital Converter. 6.1 Peripheral operating requirements and behaviors S32V234 Data Sheet, Rev. 9, 03/2020

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1 LSB (ideal)

Figure 2. ADC characteristics and error definitions Maximum (+5/-10%) variation can be expected .

6.1.1.1 Input equivalent circuit

Figure 3. Input equivalent circuit Table 15. ADC conversion characteristics

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1. Please see description of Clock & reset section in ADC chapter in Reference Manual for details. User need to generate

MCR[4].ADCLKDIV = 0 (default).

1. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal

clock tsample depend on programming. For internal ADC channels, the minimum sampling time required is 3 microsecond.

1. This parameter does not include the sample time tsample, but only the time for determining the digital result and the time to

load the result register with the conversion result.

1. Specifications are quoted here for input signal ranging from 150 mV to VDD_HV_ADC - 150 mV. For signals outside this

range, the Specifications may degrade beyond limits specified in this table.

6.1.2 Thermal Monitoring Unit (TMU)

The following table describes TMU electrical characteristics. Table 16. TMU electrical characteristics

6.2.1 Main oscillator electrical characteristics

The device provides an oscillator/resonator driver of a Pierce-type structure. Table 17. Main oscillator electrical characteristics

1. The start-up time is dependent upon crystal characteristics, board leakage, etc, high ESR and excessive capacitive loads

• NX3225 – 40 MHz; Load capacitance = 8 pF
• NX5032 – 40 MHz; Load capacitance = 8 pF 6.2.2 48 MHz FIRC electrical characteristics

Table 18. FIRC electrical specifications

6.2.3 PLL electrical specifications

Table 19. PLL electrical characteristics 1

1. The jitter values are gauranteed for following conditions:
2. Measurement being done on LFAST TX pad with observed frequency greater than 250 M and less than 320 M
3. Minimum SOC activity - Operations required to observe clock must be functional.
4. Maximum frequency change in SSCG modulation is limited by following relation: Modulation Depth * VCO Frequency
5. PLL0IN clock retrieved from either internal RCOSC or external FXOSC clock. Input characteristics are granted when using

internal RCOSC or external oscillator is used in functional mode.

1. The PLLIN clock is the frequency after the PREDIV(Pre-divider) value division, and before the Phase detector block.

Please refer to the PLLs section of clocking chapter in the Reference Manual.

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1. STEPSIZE x STEPNO < 18432

in the "Clocking" chapter of the Reference Manual.

6.2.4 DFS electrical specifications

Table 20. DFS electrical specification 1

1. DFSes mfi, mfn and frequencies are defined and restricted as per Reference Manual. See the table "DFS (mfi, mfn)

settings" in the "Clocking" chapter of the Reference Manual for the supported mfi and mfn combinations.

6.2.5 LFAST PLL Electrical Specifications

The following table lists AC specification of the LFAST PLL block. Table 21. LFAST PLL Interface AC

1. VCO clock measured over 100 µs acquisition at ZipWire TX LVDS across 100 ohm load
2. Only Total Jitter is given a maximum specification as variation of Random and Deterministic jitter is not critical. Any

6.3.1 QuadSPI AC specifications

• Measurements are with a load of 35 pF on output pins. Input slew: 1 ns, SIUL2_MSCRn[DSE] = 111, and SIUL2_MSCRn[SRE] = 11
• QuadSPI input timing is with 15 pF load on flash output.
• QuadSPI_MCR[DQS_EN] must be set as 1 for SDR READ NOTE These are not necessarily the default configuration after chip resets. You must ensure the above chip configuration to match the measurements in this section. The following table lists various QuadSPI modes and their corresponding configurations. Please refer to the device Reference Manual for register and bit descriptions.

Table 22. QuadSPI read/write settings For SDR mode, QuadSPI_MCR[DQS_EN] must be set as '1'.

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Figure 4. QuadSPI input timing (SDR mode) diagram

• A negative time indicates the actual capture edge inside the device is earlier than clock appearing at pad.
• All board delays need to be added appropriately
• Input hold time being negative does not have any implication or max achievable frequency

Table 23. QuadSPI input timing (SDR mode) specifications

Figure 5. QuadSPI output timing (SDR mode) diagram Table 24. QuadSPI output timing (SDR mode) specifications Figure 6. QuadSPI input timing (DDR mode) diagram

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Table 25. QuadSPI input timing (DDR mode) specifications Figure 7. QuadSPI output timing (DDR mode) diagram Table 26. QuadSPI output timing (DDR mode) specifications Maximum clock frequency = 100 MHz.

Figure 8. QuadSPI input timing (HyperFlash mode) diagram Table 27. QuadSPI input timing (HyperFlash mode) specifications Figure 9. QuadSPI output timing (HyperFlash mode) diagram Table 28. QuadSPI output timing (HyperFlash mode) specifications Table continues on the next page...

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Table 28. QuadSPI output timing (HyperFlash mode) specifications (continued)

6.4.1 DDR3 and DDR3L timing parameters

Operating voltages of DDR3 and DDR3L are different.

Figure 10. DDR3 and DDR3L command and address timing parameters CKE pin has an external weak pull down requirement.

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JESD79-3F and JESD79-3-1A.01 specifications respectively. Table 29. DDR3 and DDR3L timing parameter All measurements are in reference to Vref level. resistor from outputs to VDD_REF.

6.4.2 DDR3 and DDR3L read cycle

Figure 11. DDR3 and DDR3L read cycle Table 30. DDR3 and DDR3L read cycle All measurements are in reference to Vref level.

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6.4.3 DDR3 and DDR3L write cycle

Figure 12. DDR3 and DDR3L write cycle Table 31. DDR3 and DDR3L write cycle All measurements are in reference to Vref level. resistor from outputs to VDD_REF.

6.4.4 LPDDR2 timing parameter

Figure 13. LPDDR2 command and address timing parameter CKE pin has a external weak pull down requirement. Table 32. LPDDR2 timing parameter

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All measurements are in reference to Vref level. resistor from outputs to VDD_REF.

6.4.5 LPDDR2 read cycle

Figure 14. LPDDR2 read cycle Table 33. LPDDR2 read cycle All measurements are in reference to Vref level.

6.4.6 LPDDR2 write cycle

Figure 15. LPDDR2 write cycle Table 34. LPDDR2 write cycle All measurements are in reference to Vref level. resistor from outputs to VDD_REF.

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6.5.1 DSPI timing

SIUL2_MSCRn[DSE] = 101, and SIUL2_MSCRn[SRE] = 11. the measurements in this section. Table 35. DSPI timing

1. SMPL_PTR should be set to 1. For SPI_CTARn[BR] - 'Baud Rate Scaler' configuration is >= 3.
2. Slave Receive Only Mode can operate at a maximum frequency of 60 MHz. In this mode, the DSPI can receive data on

SIN, but no valid data is transmitted on SOUT.

1. This value of 16 ns is with the configuration prescaler values: SPI_CTARn[PCSSCK] - "PCS to SCK Delay Prescaler"

configuration is "3" (01h) and SPI_CTARn[CSSCK] - "PCS to SCK Delay Scaler" configuration is "2" (0000h).

1. This value of 16 ns is with the configuration prescaler values: SPI_CTARn[PASC] - "After SCK Delay Prescaler"

configuration is "3" (01h) and SPI_CTARn[ASC] - "After SCK Delay Scaler" configuration is "2" (0000h). Figure 16. DSPI classic SPI timing — master, CPHA = 0

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Figure 19. DSPI classic SPI timing — slave, CPHA = 1 Figure 20. DSPI modified transfer format timing — master, CPHA = 0

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Figure 21. DSPI modified transfer format timing — master, CPHA = 1 Figure 22. DSPI PCS strobe (PCSS) timing

6.5.2 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC)

booting does not apply to SD/SDIO/SDHC/SDXC modes. SIUL2_MSCRn[DSE] = 101, and SIUL2_MSCRn[SRE] = 11. functioning of uSDHC external interface. the measurements in this section.

6.5.2.1 SDR mode timing specifications

Figure 23. SDR CMD-DATx Read Timing Figure 24. SDR CMD-DATx Write Timing Table 36. SDR mode timing specification Table continues on the next page...

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Table 36. SDR mode timing specification (continued)

1. In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
2. In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,

clock frequency can be any value between 0–50 MHz.

1. In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode,

clock frequency can be any value between 0–52 MHz.

6.5.2.2 DDR mode timing specifications

Figure 25. DDR Data Read timing

Figure 26. DDR DATA Write timing Figure 27. DDR CMD Read Timing Figure 28. DDR CMD Write Timing

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Table 37. DDR mode timing specification

6.5.3.1 LFAST interface timing diagrams

Figure 29. LFAST timing definition

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Figure 30. Rise/fall time

6.5.3.2 LFAST Interface electrical characteristics

Table 38. LFAST electrical characteristics

1. All values need to be confirmed during device characterization.
2. Startup time is defined as the time taken by LFAST current reference block for settling bias current after its pwr_down

(power down) has been deasserted. LFAST functionality is guaranteed only after the startup time.

1. Rise/fall time is defined for 20 to 80% signal voltage levels, at 2pF Cload and 100 Ohm termination resistor load.
2. Total lumped capacitance including silicon, package pin and bond wire. Application board simulation needed to verify

1. Total capacitance including silicon, package pin and bond wire
2. Total inductance including silicon, package pin and bond wire

6.5.4.1 FlexRay timing parameters

6.5.4.2 TxEN

Figure 31. TxEN signal Table 39. TxEN output characteristics 1

1. TxEN pin load maximum 25 pF.

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Figure 32. TxEN signal propagation delays

6.5.4.3 TxD

Figure 33. TxD signal Table 40. TxD output characteristics Table continues on the next page...

Table 40. TxD output characteristics (continued)

1. TxD pin load maximum 25 pF.

Figure 34. TxD signal propagation delays

6.5.4.4 RxD

Table 41. RxD input characteristics

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6.5.5.1 Ethernet Switching Specifications

SIUL2_MSCRn[DSE] = 111 and SIUL2_MSCRn[SRE] = 11. the measurements in this section.

6.5.5.2 Receive and Transmit signal timing specifications for RMII

interfaces for a range of transceiver devices. Table 42. Receive signal timing for RMII interfaces

Figure 35. RMII receive signal timing diagram Figure 36. RMII transmit signal timing diagram

6.5.5.3 Receive and Transmit signal timing specifications for MII

for a range of transceiver devices.

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6.5.5.4 Receive and Transmit signal timing specifications for RGMII

range of transceiver devices. Table 45. Receive signal timing for RGMII interfaces

1. For 10 Mbps and 100 Mbps, Tcyc will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively.
2. For all versions of RGMII prior to 2.0; This implies that PC board design will require clocks to be routed such that an
3. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as

Figure 39. RGMII Transmit signal timing diagram original Figure 40. RGMII Receive signal timing diagram original

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6.5.5.5 MII/RMII Serial Management channel timing (MDC/MDIO)

the measurements in this section. Figure 41. MDIO input timing Figure 42. MDIO output timing Table 46. MDIO interface timing specification Table continues on the next page...

Table 46. MDIO interface timing specification (continued)

6.5.6 PCI Express specifications

the Base Specification. Consult the Base Specification for additional details. Table 47. PCI Express transmitter specifications 1

1.5 MHz

58 NXP Semiconductors

1. See Table 4-9 2.5 and 5.0 GT/s Transmitter Specifications in PCI Express Base Specification for further details.

Table 48. PCI Express receiver specifications 1

1. See Table 4-12 2.5 and 5.0 GT/s Receiver Specifications in PCI Express Base Specification for further details.

6.5.7 IIC timing

Table 49. IIC SCL and SDA input timing specifications

1. Inter Peripheral Clock is the clock at which the IIC peripheral is working in the device

1. pg_clk frequency should be greater than 5 MHz for standard mode and 20 MHz for fast mode.

Table 50. IIC SCL and SDA output timing specifications

1. Programming IBFD (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings listed.

position is affected by the prescale and division values programmed in IFDR.

1. Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device.
2. Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL or SDA

takes to reach a high level depends on external signal capacitance and pullup resistor values. Figure 43. IIC input/output timing

6.5.8 LINFlex timing

The maximum bit rate is 1.875 MBit/s.

60 NXP Semiconductors

6.6.1 Display Control Unit (2D-ACE) Parameters

6.6.1.1 Interface to TFT panels

This section provides the LCD interface timing for a generic active matrix color TFT panel. Measurements are with a load of 20 pF on output pins. Input slew = 1 ns, SIUL2_MSCRn[DSE] = 111, and SIUL2_MSCRn[SRE] = 11. NOTE These are not necessarily the default configuration after chip resets. You must ensure the above chip configuration to match the measurements in this section. In the figure below1, signals are shown with positive polarity. The sequence of events for active matrix interface timing:

• PCLK latches data into the panel on its positive edge (when positive polarity is selected). In active mode, PCLK runs continuously. This signal frequency could be from 5 to 150 MHz depending on the panel type.
• HSYNC causes the panel to start a new line. It always encompasses at least one PCLK pulse.
• VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
• DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off. 6.6 1. LD[23:0]” signal is “line data,” an aggregation of the 2D-ACE’s RGB signals—R[0:7], G[0:7] and B[0:7]. Display modules S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 61

Figure 44. TFT LCD interface timing overview

6.6.1.2 Interface to TFT LCD Panels—Pixel Level Timings

Table 51. LCD interface timing parameters—horizontal and vertical Table continues on the next page...

62 NXP Semiconductors

Table 51. LCD interface timing parameters—horizontal and vertical (continued) Figure 45. Horizontal sync timing Figure 46. Vertical sync pulse

6.6.1.3 Interface to TFT LCD panels—access level

This section provides the access level timing parameters of the LCD interface. Table 52. LCD Interface Timing Parameters—Access Level Table continues on the next page...

Table 52. LCD Interface Timing Parameters—Access Level (continued) Figure 47. LCD Interface Timing Parameters—Access Level

6.6.2 Video input unit (VIU) timing specifications

Figure 48. VIU timing diagram Table 53. VIU timing parameters

64 NXP Semiconductors

6.6.3 MIPICSI2 D-PHY electrical and timing parameters

6.6.3.1 Electrical and timing Information

Table 54. Electrical and timing Information

1. All rights reserved. This material is reprinted with the permission of the MIPI Alliance, Inc. No part(s) of this document may

be disclosed, reproduced or used for any purpose other than as needed to support the use of the products of NXP Inc.

6.6.3.2 D-PHY signaling levels

that LP receiver always detects low on HS signals. Table 55. D-PHY RX calibrator specifications Figure 49. D-PHY signaling levels

6.6.3.3 D-PHY switching characteristics

Table 56. D-PHY switching characteristics Table continues on the next page...

66 NXP Semiconductors

Table 56. D-PHY switching characteristics (continued)

6.6.3.4 Low-Power Receiver timing

Figure 50. Input Glitch Rejection of Low-Power Receivers

6.6.3.5 Data to Clock timing

Figure 51. Data to Clock timing definition Table 57. Data to Clock timing specifications

1. when D-PHY is supporting maximum data rate > 1 Gbps.
2. when D-PHY is supporting maximum data rate = 1 Gbps.

6.6.3.6 NOTICE OF DISCLAIMER

effort, of lack of viruses, and of lack of negligence.

68 NXP Semiconductors

All materials contained herein are protected by copyright laws, and may not be reproduced, republished, distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related trademarks, trade names, and other intellectual property are the exclusive property of MIPI Alliance and cannot be used without its express prior written permission. ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL, CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL, WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document; and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance with the contents of this Document. The use or implementation of the contents of this Document may involve or require the use of intellectual property rights ("IPR") including (but not limited to) patents, patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any IPR or claims of IPR as respects the contents of this Document or otherwise. Debug specifications

6.7.1 JTAG interface timing

Measurements are with a load of 45 pF on output pins. Input slew = 1 ns, SIUL2_MSCRn[DSE] = 101, and SIUL2_MSCRn[SRE] = 11. 6.7 Debug specifications S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 69

the measurements in this section. Table 58. JTAG pin AC electrical characteristics 1

1. These specifications apply to boundary scan, JTAG and CJTAG, and serial wire debug modes.
2. This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions.
3. Cycle time is 25 ns assuming full cycle timing. Cycle time is 50 ns assuming half cycle timing
4. Cycle time is 50 ns assuming full cycle timing. Cycle time is 100 ns assuming half cycle timing
5. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
6. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

Table 59. PCIe JTAG AC electrical characteristics 1 Table continues on the next page...

70 NXP Semiconductors

Table 59. PCIe JTAG AC electrical characteristics 1 (continued)

1. These specifications apply to boundary scan, JTAG and CJTAG, and serial wire debug modes.
2. This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions.
3. Cycle time is 25 ns assuming full cycle timing. Cycle time is 50 ns assuming half cycle timing.
4. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
5. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

Figure 52. JTAG test clock input timing

Figure 53. JTAG test access port timing Figure 54. JTAG JCOMP timing

72 NXP Semiconductors

Figure 55. JTAG boundary scan timing

6.7.2 Debug trace timing specifications

SIUL2_MSCRn[DSE] = 111, and SIUL2_MSCRn[SRE] = 11. the measurements in this section. Table 60. Debug trace operating behaviors Table continues on the next page...

Table 60. Debug trace operating behaviors (continued) Figure 56. TRACE_CLKOUT specifications

6.8 Wakeup Unit (WKPU) AC specifications

Table 61. WKPU glitch filter specifications

6.9 RESET pin glitch filter specifications

Table 62. RESET pin glitch filter specifications

6.10 External interrupt timing (IRQ pin)

Table 63. External interrupt timing Table continues on the next page...

74 NXP Semiconductors

Table 63. External interrupt timing (continued)

1. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

Figure 57. External interrupt timing

7.1 Thermal attributes

Table 64. Thermal Resistance Data

1. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets

JEDEC specification for this package.

1. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is

used for the case temperature. Reported value includes the thermal resistance of the interface layer.

1. Junction-to-Lid-Top thermal resistance determined using the using MIL-STD 883 Method 1012.1. However, instead of the

thermal resistance of the interface layer between the package and cold plate.

8.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

9.1 Package pinouts and signal descriptions

For package pinouts and signal descriptions, refer to the Reference Manual.

10 Reset sequence

device remains in reset condition in each of those conditions.

10.1 Reset sequence duration

different reset sequences described in Reset sequence description. Table 65. RESET sequences 1

1 TDRB Destructive Reset Sequence, All LBIST/MBIST enabled 25 — ~50 ms

2 TDR Destructive Reset Sequence, BIST disabled 50 — 90 µs

3 TERLB External Reset Sequence Long, Unsecure Boot, BIST enabled 25 — ~50 ms

Table continues on the next page...

76 NXP Semiconductors

Table 65. RESET sequences 1 (continued)

4 TFRL Functional Reset Sequence Long, Unsecure Boot, BIST disabled 50 — 90 µs

5 TFRS Functional Reset Sequence Short, Unsecure Boot, BIST disabled 2 — 7 µs

1. All the Reset durations assume boot code execution time for Execute-in-place for QuadSPI booting, Unsecure mode with

authentication times will be over and above these durations.

10.2 Boot performance matrix

and application image download time. Table 66. Boot execution time

4 MB 256 kB 128 kB 32kB

Figure 58. Boot diagram

10.3 Reset sequence description

for which the duration is specified in Table 65. will vary as per Application code image size. became stable. Deassertion of EXT_POR pin triggers the start of reset sequence. reset sequence and the possible states of the RESET (Active-low) signal pin.

78 NXP Semiconductors

Figure 62. Functional reset sequence long Figure 63. Functional reset sequence short RGM_FBRE register in the device reference manual for more information.

11 Power sequencing requirements

• P CIE_VP and PCIE_VPH supplies should be powered up within 50 ms of each other.
• V DD_HV_CSI and VDD_LV_CSI supplies should be powered up within 50 ms of each other.
• V REFH_ADC should never differ from VDD_HV_ADV by more than 100 mV at any time including during power-up or power-down. Power sequencing requirements S32V234 Data Sheet, Rev. 9, 03/2020

80 NXP Semiconductors

• DDR0_VREF0 and DDR1_VREF0 supplies are expected to be 0.5 of V DD_DDR0_IO and VDD_DDR1_IO supplies and are to track VDD_HV_DDR0 and VDD_HV_DDR1 supply variations as measured at the receiver. Peak-to-Peak noise on DDR0_VREF0 and DDR1_VREF0 supplies should be between +/- 15 mV.
• The maximum rise time for the POR and RESET signal is 1 ms. Very slow ramps can induce bounces in the input read state during the transition from logic low to logic high, which causes the part getting locked in a self-reset loop. Any external noise on this pin can increase the problem. NOTE VDD_HV_ADV must be powered for using LFAST interface. Each supply group mentioned in the table below can be independently powered up/down from the other supply groups. Power supplies in the same group must be powered up/ down together. Supply groups belonging to the same supply domain can be ganged together on board level (with appropriate noise isolation) to allow these groups to power up/down together. Following supply groups have been tested for power sequencing tests:

Table 67. Supply groups tested for power sequencing Table 68. Revision history Table continues on the next page...

Revision history

S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 81

Table 68. Revision history (continued)

• Editorial changes. Added topic PCB routing guideliness. Added topic RESET pin glitch filter specifications. In Table 15, added the sentence "For internal ADC channels, the minimum sampling time required is 3 microsecond" in the foot note on "Sample time". In Power Management Controller (PMC) electrical specifications, changed the introductory paragraph. Added Low Voltage Detector for IRC (VDD_HV_OSC). In Table 3, modified minimum value of 3.3 V input/output supply voltage. In Reset sequence description, updated both "External reset sequence long, BIST enabled" and "Destructive reset sequence, BIST enabled" images. In Table 17, updated the condition of Oscillator start-up time from fOSC = 24,40 MHz to fFXOSCHS = 24,40 MHz. In Power sequencing requirements, changed VREFL_ADC to VREFH_ADC, VDD_HV_CSI1/2 to VDD_HV_CSI, and VDD_LV_CSI1/2 to VDD_LV_CSI. In Table 10, added footnote in ovdd. In Table 5, changed VS4 to S32V234 and VS2 to S32V232. Made extensive changes in QuadSPI AC specifications. In Table 3, added Supply ramp rate specifications. In Table 5, changed maximum value of vdd_hv_pll from 30 mA to 35 mA and maximum value of vdd_lv_pll from 55 mA to 80 mA. In DDR3 and DDR3L timing parameters , added a note. In Table 29, updated the table title to include DDR3L. Also updated minimum value of DDR4. DDR5, DDR6, and DDR7 and changed units of DDR1 and DDR2. In Table 30, updated the table title to include DDR3L. Also updated minimum value of DDR26. In Table 31, updated the table title to include DDR3L. Updated minimum values of DDR17 and DDR18, and units of DDR21 and DDR22. In Table 32, updated LP1 and LP2 symbols and units. In Figure 15, changed figure title from “LPDDR3 write cycle” to “LPDDR2 write cycle”. In Table 34, updated minimum value of LP18, and minimum and maximum value of LP21. Also updated units of LP21, LP22, and LP23. Updated topic titles DDR SDRAM Specific Parameters (DDR3, DDR3L, and LPDDR2), DDR3 and DDR3L timing parameters , DDR3 and DDR3L read cycle, and DDR3 and DDR3L write cycle. Updated figure titles Figure 10, Figure 11, and Figure 12. In Reset sequence description, added value of external pull up resistor as 10-15 kiloohm. In Table 18, modified the parameter "IRCOSC frequency variation afterprocess trimming" to "IRCOSC frequency variation with respect to supply and temperature after process trimming". Updated Table 16. In Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC), added the sentence "uSDHC_VEND_SPEC[CMD_OE_PRE_EN] field should be programmed to 1 for proper functioning of uSDHC external interface". In Table 59, updated maximum value of TCK Rise and Fall Times. Table continues on the next page...

S32V234 Data Sheet, Rev. 9, 03/2020

82 NXP Semiconductors

Cycle Time and updated maximum value of TCK Rise and Fall Times. Added DDR3L mode and DDR3L mode DC electrical specifications. Removed LPDDR2 I/O AC specifications. section as there is only one QuadSPI. Changed all instances of XOSC to FXOSC throughout the document. Changed all instances of MIPI-CSI2, MIPI, and CSI2 to MIPICSI2 throughout the document.

• Editorial changes. 3 04/2017 • Editorial changes.
• Updated Figure 1.
• Modified Figure 4.
• Modified Figure 6.
• Modified Figure 7.
• Updated Figure 29.
• Updated Figure 38.
• Updated Figure 43.
• Updated Figure 48.
• Removed Figure "DSPI modified transfer format timing – slave, CPHA = 0" and Figure "DSPI modified transfer format timing — slave, CPHA = 1".
• In Table 1, updated ARM Cortex-A53 Core feature for S32V232 from “Up to 600 MHz Quad ARM Cortex-A53” to “Up to 800 MHz Dual ARM Cortex-A53 (single cluster)”.
• In Table 3 :
• added the footnote "All the grounds viz. VSS, VSS_XOSC,VSS_PMC and VSS_HV_ADV are tied together at the package level” in Common ground voltage.
• minimum operating voltage of V DD_HV_IO_ETH has been changed from 1.71 V to 1.5 V, and maximum value of DDR I/O supply voltage LPDDR2 changed from 1.26 V to 1.30
• parameter “Supply ramp rate” has been changed to “Supply ramp rate for all supplies on the device”
• added LFAST IO bank supply (V DDIO_LFAST) in the list of symbols for "1.8 V supply voltage (for analog circuits, PLLs)"
• In Table 4 :
• added Band Gap Reference value of PMC.
• maximum value of trimmed VTH threshold of VDD_LV_CORE_SOC (low voltage monitoring) has been changed from 939 to 946 mV, and maximum values of trimmed VTL and VTH threshold of VDD_LV_CORE_SOC (high voltage monitoring) have been changed from 1081 to 1093, and 1096 to 1093 mV, respectively.
• In Table 5 :
• modified table footnotes to clarify that power numbers are estimated for 1.01 V and 125 °C.
• VDD_HV_LFASTPLL Simulation values (Maximum) and Maximum Values of Use cases "PLL operating with 320 MHz (LFAST used)” and "PLL not operational (LFAST not used)” have been modified.
• use case “eFuse reading happening” of VDD_HV_EFUSE and its specifications are removed.
• max simulation values of MIPICSI2 interface operating as per MIPICSI not used (not powered?) in VDD_HV_CSI and VDD_LV_CSI have been changed from .1 mA to 1.6 mA and 11 mA to 15 mA.
• for PCIE_VP and PCIE_VPH, Powered down (leakage only) use case has been changed to Reset/idle. Max simulation values for PCIE_VP and PCIE_VPH (Reset/idle) Table continues on the next page...

S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 83

• modified the table heading. Removed Front Camera (w power binning) from VDD_LV_CORE and updated max values for “Adder 4x A53 CPU with Dhrystone MIPS running on each CPU @1 GHz” from 1.0 A to 1.4 A.
• removed "Simulation values" column.
• PCIE_VPH limits changed for “5 GHz operation (PCIe 2.0)” from 40 mA to 50 mA and “Reset/Idle” from 11 mA to 20 mA.
• minimum and maximum values of PMC Band Gap Reference value have been changed from 1185 to 1176 mV, and 1215 to 1224 mV respectively.
• In Table 10 :
• added the note ”After bootup, application software should switch to manual voltage detect mode using VSEL_x settings of SRC_GPR14 register to ensure optimum performance of the GPIO pads. Please refer to SRC chapter in the Reference Manual for the register details.”
• changed the maximum value of Input current (no pull-up/down) from 1 to 8 μA.
• removed “Input Hysteresis”
• maximum value of parameter “Input current (50 kilohm PU)” has been changed from 100 to 150 μA.
• maximum value of parameter “Input current (100 kilohm PU)” has been changed from 50 to 60 μA.
• removed parameter “pad keeeper resistance” and "maximum external resistor value that is guaranteed to overdrive the pad keeper".
• maximum value of parameter “Input current (50 kilohm PD)” with test condition Vin=0 has been changed from 1 to 8 μA. Also, when Vin = Vdd, maximum value of Input current (33 kilohm PU), Input current (50 kilohm PU), and Input current (100 kilohm PU) have been changed from 1 to 6 μA.
• test conditions "Ioh=-1 mA" changed to "Ioh=-100 μA" and "Ioh= 1 mA" changed to "Ioh=-100 μA".
• In Table 12, Table 13, and Table 14,
• Added Vih (DC) and Vil (DC) specifications .
• All tri-state supply current items are removed and updated test conditions of "High-level output voltage" and "Low-level output voltage".
• Maximum value of parameter “ Input current (no pullup/pulldown)” has been changed from 3 to 5 μA, 3 to 5 μA, and 2.5 to 5 μA, respectively.
• In Table 12, removed parameter “Rod_keep”. Updated minimum, typical, and maximum value of parameter Rkeep.
• In Table 13, removed parameter “Rod_keep”.
• In Table 14, removed parameter “Rod_keep” and deleted footnote “Note that the Jedec LPDDR2 specification (JESD209-2B) supersedes any specification in this document”.
• In Table 15
• updated ADC Input Clock frequency
• added ADC Conversion clock frequency
• removed conditions of Sample time and Conversion time
• removed all information about parameter “Max positive/negative injection” and modified “Total unadjusted error” in “TUE”.
• In Table 17, modified the minimum and maximum values of VIH and VIL.
• In Table 19 :
• Changed maximum value of SSCG modulation depth from -6% to -5.4%, and added condition STEPSIZE x STEPNO < 18432.
• Removed “PLL VCO frequency” and “PLL output clock PHI0”, and deleted footnote "All PLLs have same specifications. PLL programming should take maximum clock frequencies as per Reference Manual recommendation”.
• Added Table 19. Table continues on the next page...

S32V234 Data Sheet, Rev. 9, 03/2020

84 NXP Semiconductors

• In Table 21 :
• unit for Total Jitter has been changed from ps to ns.
• removed max Deterministic and max Random jitter specifications; added footnote in max Total Jitter.
• In Table 22 :
• Made modification in DDR mode.
• Updated values of QuadSPI_SOCCR[FDCC_FB] and QuadSPI_SOCCR[FDCC_FA] for SDR and DDR mode (internal DQS Mode) and added footnote “Device qualification is not complete.”
• Deleted Table "QuadSPI input timing (DDR mode) specifications with learning"
• In Table 24 changed Minimum value of Chip select output setup time and Chip select output hold time.
• In Table 25
• changed maximum value of SCK Clock Frequency and updated configuration. Also, changed table caption
• changed the minimum value of "Setup time for incoming data".
• In Table 26 :
• deleted "Chip select output setup time" and "Chip select output hold time".
• changed the maximum value of "Output Data Valid" and minimum value of "Output Data Hold".
• In Table 27, updated minimum value of parameters “Setup time for incoming data” and “Hold time for incoming data”.
• In Table 28, updated maximum value of “Ck to Ck2 skew max” and minimum value of “Ck to Ck2 skew min”.
• In Table 29 changed symbol and minimum value of DDR4, DDR5, DDR6, and DDR7.
• In Table 30 modified minimum value of DDR26 from 540 to 563 ps.
• In Table 31 changed the symbol and minimum value of DDR17 and DDR18.
• In Table 32 changed the symbol and minimum value of parameters CKE setup time, CKE hold time, CA setup time, and CA hold time.
• In Table 33 changed the minimum value of LP26.
• In Table 34 changed the symbol and minimum value of LP17 and LP18.
• In Table 35 :
• Updated footnotes to include changes in PCSSCK, CSSCK, PASC, ASC values.
• Updated footnotes in minimum timing of parameter DSPI cycle time, PCS to SCK delay, and After SCK delay.
• In Table 36 changed the heading of table from "SD/eMMC4.3 interface timing specification" to "SDR mode timing specification".
• In Table 37 changed the heading of table from "SD3.0/eMMC4.5 interface timing specification" to "DDR mode timing specification" and updated parameter "Clock Frequency (eMMC4.5 DDR)" to "Clock Frequency (eMMC4.4 DDR)".
• In Table 38 :
• updated min, typ, and max values of V OS_DRF and |ΔVOD_DRF|
• deleted R OUT_DRF and VHYS_DRF
• modified R IN_DRF
• added LFAST Clock characteristics
• parameter Rise/Fall time (10% - 90% of swing) is changed to Rise/Fall time (20% - 80% of swing) and minimum and maximum values of the parameter have been changed from
• added footnote “Rise/fall time is defined for 20 to 80% signal voltage levels, at 2pF Cload and 100 Ohm termination resistor load”.
• Updated minimum and maximum value of “Common mode voltage” (Transmitter) from
• Updated maximum value of “Common mode voltage” (Receiver) from 1.6 to 1.5 V. Table continues on the next page...

S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 85

• Updated the footnote in minimum and maximum values of “Common mode voltage” (Receiver).
• Changed minimum value of “Differential input voltage” (Receiver) from 100 to 150 mV.
• In Table 43 changed minimum and maximum value of RX_CLK duty cycle.
• In Table 44 :
• changed minimum and maximum value of TX_CLK duty cycle and minimum value of Out delay from TX_CLK.
• included "TX_CLK to Output Valid" and "TX_CLK to Output Invalid".
• In Table 45 removed the foot note from "Characteristic".
• In Table 49 :
• Changed minimum value of “Data hold time0” and “Data setup time” from 0 to 25 ns, and 0 to 250 (standard mode); 100 (fast mode) respectively
• Added note "ipg_clk frequency should be greater than 5 MHz for standard mode and 20 MHz for fast mode" to minimum value of “Data setup time”
• Updated the column "Number"
• In Table 50, minimum value of “Stop condition setup time” has been changed from 10 to 11 IPS bus cycle.
• In Table 51, changed Display pixel clock period from 6.4 to 6.66 ns.
• In Table 52, changed pixel clock period from 6.36 to 6.66 ns.
• In Table 53, changed description "VIU data setup time" to "VIU Data/Hsync/Vsync setup time" and "VIU data hold time" to "VIU Data/Hsync/Vsync hold time".
• In Table 54, removed "Contention Line Receiver DC Specifications".
• In Table 57, Data to Clock Setup Time and Clock to Data Hold Time are updated to include condition where the PHY is used to a maximum data rate of 1.0Gbps and data rates greater than 1.0Gbps.
• In Table 60, updated Clock frequency.
• In Table 65 :
• changed minimum and maximum values of “Destructive Reset Sequence, BIST disabled” from 5 ms to 50 µs and 10 ms to 90 µs
• changed minimum and maximum values of “Functional Reset Sequence Long, Unsecure Boot, BIST disabled” from 5 ms to 50 µs and 10 ms to 90 µs
• changed minimum and maximum values of ”Functional Reset Sequence Short, Unsecure Boot, BIST disabled” from 5 ms to 2 µs and 6 ms to 7 µs.
• Added Table 67 and a paragraph preceding it “Each supply group mentioned in the table below can be independently powered up/down from the other supply groups. Supply domains belonging to the same supply group are supposed to be ganged together on board level (with appropriate noise isolation) to allow this group to power up/down together”.
• All IRC and IRCOSC in the document changed to FIRC.
• In Features, modified JPEG and H.264 information.
• Removed hysteresis information from Features, Table 1, and from Table 10.
• Modified content in Family comparison.
• Added topic Operation above maximum operating conditions.
• Updated Ordering information
• In Power consumption, modified the statement “These specifications are design targets and are subject to change per device characterization” to “These specifications are subject to change per device characterization.”
• In PCB routing guidelines changed the subheading from "DDR3 PCB design" to "DDR3/ DDR3L PCB design".
• Added topic GPIO speed at various voltage levels.
• In DDR pads, deleted table "DDR operating conditions".
• In ADC electrical specifications, Updated the note to “While measuring scaled supply voltages on ADC Channels, Maximum (+5/-10%) variation can be expected .”
• In Main oscillator electrical characteristics, added crystal information.
• In ADC electrical specifications added the note “While measuring scaled supply voltages on ADC Channels, Maximum 10% variation can be expected”. Table continues on the next page...

S32V234 Data Sheet, Rev. 9, 03/2020

86 NXP Semiconductors

• In Thermal Monitoring Unit (TMU), changed all occurrences of “Temperature Sensor” to “Thermal Monitoring Unit”.
• In 48 MHz FIRC electrical characteristics, min and max value of “IRCOSC frequency variation with respect to supply and temperature after process trimming” has been changed from -5 to -10 and +5 to +10 %.
• In QuadSPI AC specifications deleted sentence "DDR configurations are applicable when used without learning enabled."
• Added a note in DSPI timing.
• In Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) changed the introductory paragraph.
• Renamed topic "SD/eMMC4.3 (Single Data Rate) AC Timing" to "SDR Mode Timing Specifications". In this topic SDR mode timing specifications deleted the introductory paragraph and deleted the existing figure. Two new figures Figure 23 and Figure 24 are added. Modified Table 36.
• Renamed topic "SD/eMMC4.4/5.0 (Dual Data Rate) eSDHCv3 AC Timing" to "DDR Mode Timing Specifications". In this topic DDR mode timing specifications, deleted the introductory paragraph and replaced the existing figure with four new figures (Figure 25, Figure 26, Figure 27, Figure 28).
• In DSPI timing changed the note from "DSPI on this chip neither supports interaction with a Slave in MTFE mode nor acts as one" to "DSPI Timing specs on this chip are valid with Slave in Classic Mode only."
• In Ethernet Switching Specifications, ” statement "For RGMI, output load is 15 pF and pad settings are DSE[2:0] = 111 and FSEL[1:0] = 11" is changed to "For RGMII, output load is 5 pF and pad settings are DSE[2:0] = 111 and FSEL[1:0] = 11."
• Added topic MII/RMII Serial Management channel timing (MDC/MDIO).
• In Video input unit (VIU) timing specifications heading "Video input unit (VIU) electrical specifications" changed to "Video input unit (VIU) timing specifications".
• Added topic Boot performance matrix.
• In Power sequencing requirements :
• added note "VDD_HV_ADV must be powered for using LFAST interface". Changed “VREFH_ADC should never be more than 100 mV above VDD_HV_ADV” to “VREFH_ADC should never differ from VDD_HV_ADV by more than 100 mV at any time including during power-up or power-down”.
• Changed the sentence from "DDR0_VREF0 and DDR1_VREF0 supplies are expected to be 0.5 of VDD_HV_DDR0 and VDD_HV_DDR1 I/O supplies and are to track VDD_HV_DDR0 and VDD_HV_DDR1 supply variations as measured at the receiver” to "DDR0_VREF0 and DDR1_VREF0 supplies are expected to be 0.5 of VDD_DDR0_IO and VDD_DDR1_IO supplies and are to track VDD_HV_DDR0 and VDD_HV_DDR1 supply variations as measured at the receiver”.
• Updated the statement "VDD_HV_CSI and VDD_LV_CSI should be powered up together on board to prevent any electrical crossover currents" to "VDD_HV_CSI and VDD_LV_CSI supplies should be powered up within 50 ms of each other". 3.1 07/2017 • The only changes between S32V234 Rev 3.1 and Rev 3 is the removal of "Confidential Proprietary" from the footer. 4 11/2017 • In Ordering information, added a table mentioning the production part numbers with respective feature configurations.
• In Table 19, updated SSCG modulation depth values.
• In Features, updated the statement for "APEX2-CL Image cognition processor" to remove the mention of OpenCL 1.2 support.
• In Features, updated the first statement under "Memory interfaces" with the correct LPDDR2/ DDR3/DDR3L operating specs.
• Updated LPDDR2 and DDR3 operating clock rate and data rate in Figure 1.
• In Feature Set, updated the "Memory Interfaces" entry for the correct operating data rate and clock rate of LPDD2 and DDR3. Table continues on the next page...

S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 87

• In PCB routing guidelines, added a note under the "CLK/Addess/Commands" section. And updated the third point under the section for clarification.
• In Table 3, row 2 and 3 has been split into sub-sections for different I/O voltages.
• In Table 5, updated max value for VDD_HV_LFASTPLL when "PLL operating with 320 MHz (LFAST used)". Value is changed from 24 mA to 26 mA.
• In Table 16, updated TADC at TJ = 40 °C to 125 °C, from +/- 5 °C to +/- 6 °C.
• In Table 5, updated descriptions for VDD_HV_CSI and VDD_LV_CSI. The string "not powered?" is changed to "IP Powered and Disabled".
• In Main oscillator electrical characteristics, updated the section to remove references of 24 MHz FXOSC support.
• In Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC), updated the topic title and added a paragraph describing voltage restriction with eMMC booting.
• In Table 5, removed the footnotes from the "Max Values" column, and added one to the VDD_LV_CORE entry.
• In Table 19, updated the frequency values for "PLL input clock".
• In Table 20, updated the "Input Frequency" values.
• Updated the specs in following tables:
• Table 29
• Table 31
• Table 32
• Table 34
• Removed the table "PLL maximum frequencies" from the section PLL electrical specifications.
• In DFS electrical specifications, updated mfn division factor from [0:255] to [1:255], and updated the footnote from the Table 20. 5 03/2018 • This device is qualified now, so removed the footnote from Table 22 that said "Device qualification is not complete.".
• Corrected "Operating Max Supply Voltage" for "3.3 V DGO Voltage Domain" in Table 2 to 3.6
• Corrected Block diagram to add DRAM-ECC to MMDC_1 block, similar to it was with MMDC_0.
• Updated the specs for VDD_LV_CORE in Table 5.
• Updated max values for T DRB and TERLB in Table 65. 6 08/2018 • GPIO speed at various voltage levels - Added a note at the end of the section.
• Power sequencing requirements - Added one new point to the bullet list mentioning the maximum rise time for POR signal.
• Boot Configuration Pins Specification - Added two notes in this section.
• Table 56 - Updated "Maximum serial data rate" spec from "80 to 1.5 Gbps" to "80 to 1500 Mbps".
• Following changes are made throughout the document for better clarification:
• DSE[2:0] changed to SIUL2_MSCR n[DSE].
• ipp_dse<1:0> changed to SIUL2_MSCR n[DSE].
• FSEL[1:0] changed to SIUL2_MSCR n[SRE].
• ipp_fsel changed to SIUL2_MSCR n[SRE].
• Deleted the test condition about ipp_do.
• Added a note to the following sections to clarify that to match with the measurements given in the section you must ensure the configuration mentioned. That may not be the default configuration of the chip after reset.
• QuadSPI AC specifications
• DSPI timing
• Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC)
• Ethernet Switching Specifications
• MII/RMII Serial Management channel timing (MDC/MDIO)
• Interface to TFT panels Table continues on the next page...

S32V234 Data Sheet, Rev. 9, 03/2020

88 NXP Semiconductors

• JTAG interface timing
• Debug trace timing specifications
• Electrostatic discharge (ESD) specifications - Removed the VESD(CDM) specs for corner pins. 7 08/2018 • GPIO speed at various voltage levels - Added the text "The maximum rise time for all GPIO pins is 1 ms" to the existing note.
• Power sequencing requirements - Updated the last bullet to "The maximum rise time for the 8 12/2018 • Changed all instances of XOSC to FXOSC throughout the document.
• In Table 1 - For S32V232 changed "Up to 800 MHz Dual ARM Cortex-A53 (single cluster)" to "Up to 1000 MHz Dual ARM Cortex-A53 (single cluster)" and in communications row removed all the text and added text "Same as S32V234" for S32V232.
• In Ordering information - Changed text from "The orderable part numbers of this chip are in the table below" to "An example of orderable part numbers of this chip are in the table below".
• In GPIO speed at various voltage levels - Added the Drive Strength "001" and "010" in the "GPIO rise/fall times (1.8 V range)", "GPIO rise/fall times (2.5 V range)" and "GPIO rise/fall times (3.3 V range)" tables.
• In Features - Removed the text "ARM TrustZone (TZ) architecture support" and added text "Secure vs non-secure applications separation supported via ARM v8 exception level support in the ARM Cortex A53 clusters and its extension via XRDC on SoC level".
• In Table 5 updated the following:
• Replaced descriptive text with orderable part number.
• Removed @ 125 C from each row.
• Split the row "DD_LV_CORE" into "DD_LV_CORE (static)" and "DD_LV_CORE (dynamic)" into separate rows.
• Added "T j" as the temperature in the footnote.
• Added further static power entries. Added values for 125 T j and 105 Tj for VDD_LV_CORE (Static).
• Added parameters "VDD_HV_ADV" and "VDD_REFH_ADC".
• In DDR3 and DDR3L timing parameters added Note "DDR3 and DDR3L timing parameters are compliant with JESD79-3F and JESD79-3-1A.01 specifications respectively".
• In LPDDR2 timing parameter added Note "LPDDR2 timing parameters are compliant with JESD209-2B specification". 9 01/2020 • In Ordering information :
• Added Figure 1.
• Added a note "For the latest information on orderable parts please check https:// www.nxp.com/s32v234 Buy/Parametrics section".
• In Features changed the text from "Secure vs non-secure applications separation supported via ARM v8 exception level support in the ARM Cortex A53 clusters and its extension via XRDC on chip level" to "ARM TrustZone (TZ) architecture support".
• In Table 2 removed the "Operating Max Supply Voltage" rows.
• Removed the Maximum and Minimum values of Vtt and added a footnote in Table 13 and Table 12.
• Updated the text from "Supply domains belonging to the same supply group are supposed to be ganged together on board level (with appropriate noise isolation) to allow this group to power up/down together" to "Power supplies in the same group must be powered up/down together. Supply groups belonging to the same supply domain can be ganged together on board level (with appropriate noise isolation) to allow these groups to power up/down together" in Power sequencing requirements.
• In Table 38 for |ΔVI_DRF|added the conditions "VICOM_DRF>1.4 V" and "VICOM_DRF<= 1.4 V".

S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 89

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