S32R274 NXP | Alldatasheet
Document overview
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Technical content
Features
- On-chip modules available within the device include the following features: Safety core: Power Architecture® e200Z4 32-bit CPU with checker core
- Dual issue computation cores: Power Architecture® e200Z7 32-bit CPU
- 2 MB on-chip code flash (FMC flash) with ECC
- 1.5 MB on-chip SRAM with ECC
- RADAR processing – Signal Processing Toolbox (SPT) for RADAR signal processing acceleration – Cross Timing Engine (CTE) for precise timing generation and triggering – Waveform generation module (WGM) for chirp ramp generation – 4x 12-bit ΣΔ-ADC with 10 MSps – One DAC with 10 MSps – MIPICSI2 interface to connect external ADCs
- Memory Protection – Each core memory protection unit provides 24 entries – Data and instruction bus system memory protection unit (SMPU) with 16 region descriptors each – Register protection
- Clock Generation – 40 MHz external crystal (XOSC) – 16 MHz Internal oscillator (IRCOSC) – Dual system PLL with one frequency modulated phase-locked loop (FMPLL) – Low-jitter PLL to ΣΔ-ADC and DAC clock generation (not supported on SC66760x devices)
- Functional Safety – Enables up to ASIL-D applications FCCU for fault collection and fault handling – MEMU for memory error management – Safe eDMA controller – Self-Test Control Unit (STCU2) – Error Injection Module (EIM) – On-chip voltage monitoring – Clock Monitor Unit (CMU)
- Security – Cryptographic Security Engine (CSE2) – Supports censorship and life-cycle management
- Timers – Two Periodic Interval Timers (PIT) with 32-bit counter resolution – Three System Timer Module (STM) – Three Software Watchdog Timers (SWT) – Two eTimer modules with 6 channels each – One FlexPWM module for 12 PWM signals
- Communication Interfaces – Two Serial Peripheral interface (SPI) modules – One LINFlexD module – Two inter-IC communication interface (I2C) modules – One dual-channel FlexRay module with 128 message buffers – Three FlexCAN modules with configurable buffers - CAN FD optionally supported on 2 FlexCAN modules – One ENET MAC supporting MII/RMII/RGMII interface – ZipWire high-speed serial communication
- Debug Functionality – 4-pin JTAG interface and Nexus/Aurora interface for serial high-speed tracing – e200Z7 core and e200Z4 core: Nexus development interface (NDI) per IEEE-ISTO 5001-2012 Class 3+ NXP Semiconductors Document Number S32R274 Data Sheet: Technical Data Rev. 5, 04/2019 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.
- Two analog-to-digital converters (SAR ADC) – Each ADC supports up to 16 input channels Cross Trigger Unit (CTU)
- On-chip voltage DC/DC regulator for core clock (VREG)
- Two Temperature Sensors (TSENS) S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019
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8.2 Flash memory Array Integrity and Margin Read
8.6 Flash memory read wait-state and address-pipeline control
9.3 LVDS Fast Asynchronous Transmission (LFAST) electrical
S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019 NXP Semiconductors 3
1.1 Family comparison
contact your marketing representative. Table 1. S32R274 and S32R264 Family Comparison
240 MHz (z7
266 MHz (z7
Table continues on the next page...
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Table 1. S32R274 and S32R264 Family Comparison (continued)
- DAC is not supported in S32R264x devices. Hence, ignore its occurrences in this document for S32R264K and S32R264J.
1.2 Feature list
- Safety core: Power Architecture ® e200Z4 32-bit CPU with checker core Introduction S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019 NXP Semiconductors 5
- 2 cycle delayed lockstep
- Harvard architecture with 64-bit bus for data and instructions Dual issue: up to two instructions per clock cycle
- 8 KB instruction cache and 4 KB data cache
- 64 KB data local memory
- with background load/store: backdoor access
- 0-wait state for all read and 32/64-bit write accesses
- Low number of wait states for backdoor accesses
- Support for decorated storage
- Variable Length Encoding (VLE) compliant for higher code density
- Single precision floating point operations
- Computation cores: Power Architecture ® e200Z7 32-bit CPU
- Dual issue: up to two instructions per clock cycle
- Harvard architecture with 64-bit bus for data instructions
- 16 KB instruction cache and 16 KB data cache
- 64 KB data local memory
- with background load/store: backdoor access
- 0-wait state for all read and 32/64-bit write accesses
- Low number of wait states for backdoor accesses
- Support for decorated storage
- Using variable length encoding (VLE) for higher code density
- 4-way integer processing unit (SPE2)
- 2-way single-precision Floating Point Unit (EFPU2)
- 2 MB on-chip code flash (FMC flash) with ECC
- Three ports (one per CPU) shared between code and data flash with 4 × 256 bit buffer for code and data flash including prefetch functions
- Data flash is part of the code flash module
- Including 64 KB EEPROM emulation
- 1.5 MB on-chip SRAM with ECC
- Decorated memory controller to support atomic read-modify-write operations
- Single- and double-bit error visibility is supported
- Up to four ports (one per CPU and SPT) and up to 8 banks allow simultaneous accesses from different masters to different banks
- RADAR processing
- Signal Processing Toolbox (SPT) for RADAR signal processing acceleration
- Cross Timing Engine (CTE) for precise timing generation and triggering
- Waveform generation module (WGM) for chirp ramp generation
- 4x 12-bit ΣΔ-ADC with 10 MSps (not supported on S32R264 devices)
- One DAC with 10 MSps (not supported on S32R264 devices)
- MIPICSI2 interface to connect external ADCs Introduction S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019
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- Four data lanes, with up to 1 Gbps per lane and in total
- One clock lane Memory Protection
- Each core memory protection unit provides 24 entries
- Data and instruction bus system memory protection Unit (SMPU) with 16 region descriptors each
- Register protection
- Clock Generation
- 40 MHz external crystal (XOSC)
- 16 MHz Internal oscillator (IRCOSC)
- Dual system PLL with one frequency modulated phase-locked loop (FMPLL)
- Low-jitter PLL to ΣΔ-ADC and DAC clock generation
- Functional Safety
- Enables up to ASIL-D applications
- End to end ECC ensuring full protection of all data accesses throughout the system, from each of the systems masters through the crossbar and into the memories and peripherals
- FCCU for fault collection and fault handling
- MEMU for memory error management
- Safe eDMA controller
- User selectable Memory BIST (MBIST) can be enabled to run out of various reset conditions or during runtime
- Self-Test Control Unit (STCU2)
- Error Injection Module (EIM)
- On-chip voltage monitoring
- Clock Monitor Unit (CMU) to support monitoring of critical clocks
- Security
- Cryptographic Security Engine (CSE2) enabling advanced security management
- Supports censorship and life-cycle management via Password and Device Security (PASS) module
- Diary control for tamper detection (TDM)
- Support Modules
- Global Interrupt controller (INTC) capable of routing interrupts to any CPU
- Semaphore unit to manage access to shared resources
- Two CRC computation units with four polynomials
- 32-channel eDMA controller with multiple transfer request sources using DMAMUX
- Boot Assist Module (BAM) supports internal flash programming via a serial link (LIN / CAN)
- Timers
- Two Periodic Interval Timers (PIT) with 32-bit counter resolution Introduction S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019 NXP Semiconductors 7
- Three System Timer Module (STM)
- Three Software Watchdog Timers (SWT) Two eTimer modules with 6 channels each
- One FlexPWM module for 12 PWM signals
- Communication Interfaces
- Two Serial Peripheral interface (SPI) module
- Two inter-IC communication interface (I2C) modules
- One LINFlexD module
- One dual-channel FlexRay module with 128 message buffers
- Three FlexCAN modules with configurable buffers
- CAN FD optionally supported on 2 FlexCAN modules
- One ENET MAC supporting MII/RMII/RGMII interface
- Supports 10/100 Mbps (MII/RMII/RGMII) and >100 Mbps (RGMII)
- Supports IEEE1588 timestamps and PTP
- Zipwire high-speed serial communication
- Supports LFAST and SIPI protocol
- Fast interprocessor communication with 320 Mbps gross data rate
- DMA based access to memory resources
- Debug Functionality
- 4-pin JTAG interface and Nexus/Aurora interface for serial high-speed tracing
- e200Z7 core and e200Z4 core: Nexus development interface (NDI) per IEEE- ISTO 5001-2012 Class 3+
- All platform bus masters except CSE can be monitored via Nexus/Aurora
- Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) (IEEE 1149.1) and 1149.7 (cJTAG)
- On-chip control for Nexus development interface by JTAGM module
- Two analog-to-digital converters (SAR ADC)
- Each ADC supports up to 16 input channels
- Cross Trigger Unit to enable synchronization of ADC conversions with eTimer
- On-chip voltage DC/DC regulator for core clock (VREG)
- Two Temperature Sensors (TSENS) S32R264 feature changes with respect to S32R274 are as follows:
- SD-ADC’s removed
- DAC removed
- SDPLL replaced with AFEPLL
- Improved radiated emissions in the GLONASS band. Full EMC reports are available from NXP on request for both S32R264, and S32R274 to allow the customer to select the most suitable part for their usecase. Introduction S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019
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1.3 Block diagram
2 MB Flash memory
8 Banks
Figure 1. S32R274 block diagram
2.1 Determining valid orderable parts
3.1 Description
values of these fields to determine the specific part you have received.
3.2 Fields
Table 2. Configuration Table 3. Configuration Table 4. Performance Table continues on the next page...
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Table 4. Performance (continued) Table 5. Temperature values
4.1 Absolute maximum ratings
reliability or cause permanent damage to the device. Table 6. Absolute maximum ratings Table continues on the next page...
Table 6. Absolute maximum ratings (continued)
- 5.3 V for 10 hours cumulative over lifetime of device; 3.3 V +10% for time remaining.
- Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
- 1.45 V to 1.5 V allowed for 60 seconds cumulative time at maximum T J = 150°C; remaining time as defined in note 5 and
- 1.375 V to 1.45 V allowed for 10 hours cumulative time at maximum T J = 150°C; remaining time as defined in note 6.
- 1.32 V to 1.375 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.275 V at
- TV DD is relevant for all external supplies.
- ADC inputs include an overvoltage detect function that detects any voltage higher than 1.2 V with respect to ground on
input remains disconnected until the inputs return to the normal operating range.
- SDADC is powered up and overvoltage protection is ON.
- SDADC is powered up and overvoltage protection is OFF.
- Only when V DD_HV_IOx < 3.63 V.
- No input current injection circuitry on AFE pins.
- The maximum value of 10 mA applies to pulse injection only. DC current injection is limited to a maximum of 5 mA.
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4.2 Operating conditions
Table 7. Device operating conditions Table continues on the next page...
Table 7. Device operating conditions (continued)
40 MHz
- Full functionality cannot be guaranteed when voltages are out of the recommended operating conditions.
- Min voltage takes into account the LVD variation.
- Max voltage takes into account HVD variation.
- Aurora supply must connect to core supply voltage at board level.
- The ground connection for the V DD_HV_FLA is shared with VSS.
- Supply range does not take into account HVD levels. Full range can be achieved after power-up, if HVD is disabled. See
Voltage regulator electrical characteristics section for details.
- Around common mode voltage of 0.7 V. Input voltage cannot exceed 1.4 V prior to AFE start-up completion (VREF and
- SDADC input voltage full scale is 1.2 Vpp
- On channels shared between ADC0 and 1, V DD_HV_ADCREFx is the lower of VDD_HV_ADCREF0/1.
- V DD_LV_DPHY supply should be shorted to core supply voltage VDD on board. Refer to AN5251. Contact your NXP sales
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- While determining if the operating temperature specifications are met, either the ambient temperature or junction
- Full performance means full frequency.
- Recommended Crystal 40 MHz (ESR≤30 Ω), 8 pF load capacitance.
- External mode can be used as differential input with EXTAL and XTAL
- The number is 3.5 ps when SD-ADC and/or DAC is not used in the device.
4.3 Supply current characteristics
targets and are subject to change per device characterization. Table 8. Current consumption characteristics regulators and 4 SD enabled.
- Strong dependence on use case, cache usage.
- Measured during flash read.
- Peak Flash current measured during read while write (RWW) operation.
- Temp sensor current when PMC_CTL_TD[TSx_AOUT_EN] = 1. TS0 on ADCREF0/1.
- Typical number is approximately 10 mA per each SD-ADC enabled, 12 mA for SD-PLL and 15 mA for the AFE regulators.
4.4 Voltage regulator electrical characteristics
Table 9. Voltage regulator electrical specifications
3.3 V PMU supply voltage POR release
3.3 V PMU supply voltage POR engage
Table continues on the next page...
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Table 9. Voltage regulator electrical specifications (continued)
- Min/Max includes transient load conditions. Steady state voltage is within the core supply operating specifications.
- There is a strong pull up from VREG_SWP to VDD_HV_REG3V8 which is connected when SMPS is disabled. The pullup
has resistance less than 1 Kohm, therefore VREG_SWP should not be connected to ground if unused.
Figure 2. SMPS External Components Configuration Table 10. SMPS External Components
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Figure 3. Radar AFE External Components Configuration Table 11. Radar AFE External Components Table continues on the next page...
Table 11. Radar AFE External Components (continued)
- All Radar AFE external bypass capacitors should be placed as close as possible to the associated package pin. As shown
μF is referred to as the larger cap. 0.1 μF is referred to as the smaller cap.
4.5 Electromagnetic Compatibility (EMC) specifications
EMC measurements to IC-level IEC standards are available from NXP on request.
4.6 Electrostatic discharge (ESD) characteristics
test conforms to the AEC-Q100-002/-003/-011 standard. otherwise in the device specification. Table 12. ESD ratings
1 VESD(HBM) Electrostatic discharge
Table continues on the next page...
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Table 12. ESD ratings (continued)
2 VESD(CDM) Electrostatic discharge
- All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
- Data based on characterization results, not tested in production.
- 500 V for non-AFE pins, 250 V for AFE pins.
5.1 I/O pad DC electrical characteristics
NMI, TCK, TMS, JCOMP are treated as GPIO. Table 13. I/O pad DC electrical specifications
- Measured when pad = V DD_HV_IO
- Measured when pad is sourcing 2 mA
- Measured when pad is sinking 2 mA
- Ioh/Iol is derived from spice simulations. These values are NOT guaranteed by test.
5.1.1 RGMII pad DC electrical characteristics
Table 14. RGMII pad DC electrical specifications
- Measured when pad = V DD_HV_IO
- Measured when pad is sourcing 2 mA
- Measured when pad is sinking 2 mA
- Ioh_f value is measured with 0.8*VDDE applied to the pad.
- Iol_f is measured when 0.2*VDDE is applied to the pad.
5.2 I/O pad AC specifications
to +150°C and for the full operating range of the VDD_HV_IO supply defined in Table 7. Table 15. Functional Pad electrical characteristics Table continues on the next page...
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Table 15. Functional Pad electrical characteristics (continued)
- As measured from 50% of core side input to Voh/Vol of the output
- Measured from 20% - 80% of output voltage swing
Data based on characterization results, not tested in production. Table 16. Functional Pad AC Specifications
5.3 Aurora LVDS driver electrical characteristics
Table 17. Aurora LVDS driver electrical characteristics Table continues on the next page...
Table 17. Aurora LVDS driver electrical characteristics (continued)
- Conditions for these values are V DD_LV_IO_AURORA = 1.19V to 1.32V, TJ = –40 / 150 °C
- Startup time is defined as the time taken by LVDS current reference block for settling bias current after its pwr_down
(power down) has been deasserted. LVDS functionality is guaranteed only after the startup time.
- Receiver o/p duty cycle is measured with 1.25 Gbps, 50% duty cycle, max 1 ns rise/fall time, 100 mV voltage swing signal
applied at the receiver input.
5.4 Reset pad electrical characteristics
The device implements a dedicated bidirectional RESET_B pin. Figure 4. Start-up reset requirements
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Figure 5. Noise filtering on reset signal Table 18. RESET_B electrical characteristics
- V DD_HV_IOx = 3.3 V -5%,+10%, TJ = –40 / 150°C, unless otherwise specified.
- Data based on characterization results, not tested in production.
The device provides an oscillator/resonator driver. Table 19. XOSC electrical characteristics
- The number is 3.5 ps when SD-ADC and/or DAC is not used in the device.
- When using a 40 MHz crystal, the recommended load capacitance is 8 pF. Need quiet ground connection on the board
- The termination resistance is only active when the AFE is powered (VDD_HV_RAW, VDD_HV_DAC and the AFE
configured in differential bypass mode.
6.1.2 FMPLL electrical characteristics
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Figure 6. PLL integration Table 20. PLL0 electrical characteristics
- V DD_LV_PLL0 =1.25 V ± 5%, TJ = -40 / 150 °C unless otherwise specified.
- PLL0IN clock retrieved directly from either IRCOSC or external XOSC clock.
- f PLL0IN frequency must be scaled down using PLLDIG_PLL0DV[PREDIV] to ensure the reference clock to the PLL analog
- The maximum clock outputs are limited by the design clock frequency requirements as per recommended operating
- V DD_LV_PLL0 noise due to application in the range VDD_LV_PLL0 = 1.25 V±5%, with frequency below PLL bandwidth (40 KHz)
Table 21. FMPLL1 electrical characteristics
- V DD_LV_PLL0 = 1.25 V ± 5%, TJ = -40 / 150°C unless otherwise specified.
- PLL1IN clock retrieved directly from either internal PLL0 or external XOSC clock.
Table 22. Internal RC Oscillator electrical specifications
- The typical user trim step size (δf TRIM) is 0.3% of current frequency for application of positive trim and 0.26% of current
frequency for application of negative trim, based on characterization results. Table 23. 320 MHz AFE PLL parameters
- The LW64 bit sets the wait time before the PLL frequency is measured after each calibration step to allow for stabilization.
If LW64 is '0', wait time of 256 reference clock cycles is used. If LW64 is'1', wait time of 64 reference clock cycles is used.
6.1.5 LFAST PLL electrical characteristics
The specifications in the following table apply to the interprocessor bus LFAST interface. Table 24. LFAST PLL electrical characteristics
10 MHz
Table continues on the next page...
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- The 640 MHz frequency is achieved with a 10 MHz or 20 MHz reference clock. With a 26 MHz reference, the VCO
- The time from the PLL enable bit register write to the start of phase locks is maximum 2 clock cycles of the peripheral
bridge clock that is connected to the PLL on the device.
- Measured at the transmitter output across a 100 Ω termination resistor on a device evaluation board.
7.1 ADC electrical characteristics
1 LSB (ideal)
1 LSB ideal =(VrefH-VrefL)/ 4096 =
Figure 7. ADC characteristics and error definitions
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7.1.1 Input equivalent circuit
Figure 8. Input equivalent circuit Table 25. ADC conversion characteristics Table continues on the next page...
Table 25. ADC conversion characteristics (continued)
- V DD_HV_ADC = 3.3 V -5%,+10%, TJ = –40 to +150°C, unless otherwise specified and analog input voltage from VAGND to
- AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
- During the sample time the input capacitance C S can be charged/discharged by the external source. The internal
clock tsample depend on programming.
- This parameter does not include the sample time t sample, but only the time for determining the digital result and the time to
load the result register with the conversion result.
- SeeInput equivalent circuit figure.
- ADC specifications are met only if injection is within these specified limits
- Max injection current for all ADC IOs is ± 10 mA
32 NXP Semiconductors
7.2 Sigma Delta ADC electrical characteristics
Figure 9. ADC input equivalent circuit Table 26. Sigma Delta ADC Parameters LSDA Latency @ 10 MS/s, full step input to 50% output. full-bandwidth decimation filter coefficients). Table continues on the next page...
Table 26. Sigma Delta ADC Parameters (continued)
- 0.6 Vpp (i.e. -6 dBFS) input signals applied at the following frequencies one at a time: 20.77 KHz, 317.7 KHz, 857.7 KHz, 1.411 MHz, 2.95 MHz, 3.897 MHz, and 4.997 MHz and the SNR in dBFS is then calculated. SNR at 5 MHz will be reduced by 5 dB due to decimation filter roll off.
- The SNR is specified to be 67 dBFS typical for input frequencies between 20 KHz and 4 MHz. Mismatch shaper on. SNRSDA_MM_OFF1 Signal-to-Noise Ratio Mismatch Shaper off Input Frequency Range and integration bandwidth are from 20 KHz to 5 MHz. (using full-bandwidth decimation filter coefficients). Production test frequencies 449 KHz and 4 MHz. Production test amplitude is -6 dBFS = 0.6 Vpp. Characterized under the following conditions:
- 0.6 Vpp (i.e. -6dBFS) input signals applied at the following frequencies one at a time: 20.77 KHz, 317.7 KHz, 857.7 KHz, 1.411 MHz, 2.95 MHz, 3.897 MHz, and 4.997 MHz and the SNR in dBFS is then calculated. SNR at 5 MHz will be reduced by 5 dB due to decimation filter roll off.
- The SNR is specified to be 67 dBFS typical for input frequencies between 20 KHz and 4 MHz. Mismatch shaper off. 65 67 — dBFS SNDRSDA_MM_ON1 Signal-to-Noise-and- Distortion Ratio Mismatch Shaper on Input Frequency Range and integration bandwidth are from 20 KHz to 5 MHz. (using full-bandwidth decimation filter coefficients). Production test frequencies 449 KHz and 4 MHz. Production test amplitude is -6 dBFS = 0.6 Vpp. Characterized under the following conditions:
- 0.6 Vpp (i.e. -6 dBFS) input signals applied at the following frequencies one at a time: 20.77 KHz, 317.7 KHz, 857.7 KHz, 1.411 MHz, 2.95 MHz, 3.897 MHz, and 4.997 MHz and the SNDR in dBFS is then calculated. SNR at 5 MHz will be reduced by 5 dB due to decimation filter roll off.
- The SNR is specified to be 64 dBFS typical for input frequencies between 20 KHz and 4 MHz. Mismatch shaper on. 62 64 — dBFS SNDRSDA_MM_OFF1 Signal-to-Noise-and- Distortion Ratio Mismatch Shaper off Input Frequency Range and integration bandwidth are from 20 KHz to 5 MHz. (using full-bandwidth decimation filter coefficients) 60 62 — dBFS Table continues on the next page... Analog modules S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019
34 NXP Semiconductors
- 0.6 Vpp (i.e. -6 dBFS) input signals applied at the following frequencies applied one at a time: 20.77 KHz, 317.7 KHz, 857.7 KHz, 1.411 MHz, 2.95 MHz, 3.897 MHz, and 4.997 MHz and the SNDR in dBFS is then calculated. SNR at 5 MHz will be reduced by 5 dB due to decimation filter roll off.
- The SNR is specified to be 62 dBFS typical for input frequencies between 20 KHz and 4 MHz. Mismatch shaper off. IFDRSDA Interference Free Dynamic Range 20 ms integration, ADC inputs tied together at the package pin. One side of the AC coupling capacitors associated with each input should remain connected to the ADC input and the other side of the capacitor should connected to ground. 90 — — dBFS IMDSDA_MM_ON Intermodulation Distortion Mismatch Shaper on Input Frequency Range and integration bandwidth are from 20 KHz to 5 MHz (using full-bandwidth decimation filter coefficients). Characterized under the following conditions:
- Two distinct sets of signal pairs at the specified frequencies and at an amplitude of -8 dBFs (i.e. 0.23886 Vpeak = 0.47772 Vpp differential) are applied one signal pair at a time. Signal pair #1 is f1 = 1 MHz and f2 =
1.1 MHz and signal pair #2 is f1 =
- All inter modulation products are checked. Mismatch Shaper on. 62 — — dBc IMDSDA_MM_OFF Intermodulation Distortion Mismatch Shaper off Input Frequency Range and integration bandwidth are from 20 KHz to 5 MHz (using full-bandwidth decimation filter coefficients). Characterized under the following conditions:
- Two distinct sets of signal pairs at the specified frequencies and at an amplitude of -8 dBFs (i.e. 0.23886 Vpeak = 0.47772 Vpp differential) are applied one signal pair at a time. Signal pair #1 is f1 = 1 MHz and f2 =
- All inter modulation products are checked. Mismatch Shaper off. 55 — — dBc GM Gain Mismatching (ADCx to ADCy) -3.5 — 3.5 % OE Input Offset Error — -25 — 25 mV Table continues on the next page... Analog modules S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019 NXP Semiconductors 35
5 MHz
6 MHz
7 MHz
15 MHz
- Derate specification by 2 dBFS for T j less than 0°C.
- vdda is an internally regulated and trimmed 1.45V ± 10mV voltage.
- The input structure of the ADC is an active RC integrator which has a frequency dependent input impedance as indicated
in ADC input equivalent circuit.
- All attenuation values are relative to 0 dB in the ADC passband.
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7.3 DAC electrical specifications
- All data is measured in single ended mode. Differential mode is guaranteed by design. Specifications guaranteed only if factory trims are not overridden.
Table 27. DAC parameters TOE and Tdv may be degraded.
- DAC linearity, output swing, noise, TOE, and Tdv specifications are all based upon a 300 Ω DAC output load resistor and
- Once all of the LVDs have cleared and the DAC is powered on, a one-time wait time of 300 ms is required before the DAC
- The full-scale DAC output is trimmed to 1.30 V ±10 mV with all DAC inputs set to 1 including both full-scale adjust bits.
- Rl = 300 Ω, 10uF capacitor between Vdd_HV_DAC and DAC_C, ideal supply
- Difference between ideal and real (Va+Vb/2), for all base and PWM LSBs
- Falling edge to falling edge or rising edge to rising edge. Any transition DACn -> DACn + 1
- DAC PSRR is 30 dB minimum for DAC output levels of 1/3 of full-scale or less. DAC PSRR is 24 dB minimum with the
8.1 Flash memory program and erase specifications
Table 28 shows the estimated Program/Erase times. Table 28. Flash memory program and erase specifications
- Program times are actual hardware programming times and do not include software overhead. Block program times
assume quad-page programming.
- Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 °C. Typical program and erase times may be used for throughput calculations.
- Conditions: ≤ 150 cycles, nominal voltage.
- Plant Programing times provide guidance for timeout limits used in the factory.
- Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations.
- Conditions: -40°C ≤ T J ≤ 150°C, full spec voltage.
38 NXP Semiconductors
8.2 Flash memory Array Integrity and Margin Read specifications
Table 29. Flash memory Array Integrity and Margin Read specifications
- Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The
- The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the
equation, the results of the equation are also unit accurate.
8.3 Flash memory module life specifications
Table 30. Flash memory module life specifications
- Program and erase supported across standard temperature specs.
- Program and erase supported across standard temperature specs.
8.4 Data retention vs program/erase cycles
line demonstrates technology capability, however is beyond the qualification limits.
8.5 Flash memory AC timing specifications
Table 31. Flash memory AC timing specifications Table continues on the next page...
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Table 31. Flash memory AC timing specifications (continued) program/erase until the MCR-DONE bit is cleared. program/erase until the MCR-DONE bit is set to a 1. frequencies, based on specified intrinsic flash memory access timed of the Flash memory. Table 32. Flash read wait state and address pipeline control guidelines
0 MHz < fsys <= 33 MHz 0 0 3 1
Table continues on the next page...
Table 32. Flash read wait state and address pipeline control guidelines (continued)
33 MHz < fsys <= 100 MHz 2 1 5 1
100 MHz < fsys <= 120 MHz 3 1 6 1
9.1 Ethernet switching specifications
appropriately to arrive at timing specs/constraints for the physical interface.
9.1.1 MII signal switching specifications
- Measurements are with input transition of 1 ns and output load of 25 pF.
Table 33. MII signal switching specifications
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Figure 10. MII transmit signal timing diagram Figure 11. MII receive signal timing diagram
9.1.2 RMII signal switching specifications
- Measurements are with input transition of 1 ns and output load of 25 pF.
Table 34. RMII signal switching specifications Table continues on the next page...
Figure 12. RMII transmit signal timing diagram Figure 13. RMII receive signal timing diagram
9.1.3 RGMII signal switching specifications
- Measurements are with input transition of 0.750 ns and output load of 10 pF.
Table 35. RGMII signal switching specifications Table continues on the next page...
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9.1.4 MII/RMII Serial Management channel timing (MDC/MDIO)
(vih/vil/voh/vol/)values in I/O pad DC electrical characteristics . transition of 1.0 ns and output load of 50 pF. Table 36. Ethernet MDIO timing table Figure 16. RMII/MII serial management channel timing diagram
46 NXP Semiconductors
9.2 FlexRay timing parameters
9.2.1 TxEN
Figure 17. FlexRay TxEN signal Table 37. TxEN output characteristics 1
- All parameters specified for V DD_HV_IOx = 3.3 V -5%, +10%, TJ = –40 °C / 150 °C, TxEN pin load maximum 25 pF.
Figure 18. FlexRay TxEN signal propagation delays
9.2.2 TxD
Figure 19. FlexRay TxD signal
- Measurements are with output load of 25 pF and pad configured as SRE =11.
Table 38. TxD output characteristics Table continues on the next page...
48 NXP Semiconductors
Table 38. TxD output characteristics (continued)
- All parameters specified for V DD_HV_IOx = 3.3 V -5%, +10%, TJ = –40 °C / 150°C, TxD pin load maximum 25 pF
Figure 20. FlexRay TxD signal propagation delays
9.2.3 RxD
Table 39. RxD input characteristic
- All parameters specified for V DD_HV_IOx = 3.3 V -5%, +10%, TJ = –40 / 150 °C
9.2.4 Receiver asymmetry
Table 40. Receiver asymmetry The following table provides output driver characteristics for LFAST I/Os. Table 41. LFAST output buffer electrical characteristics current). See GPIO DC electrical specification.
50 NXP Semiconductors
9.3.1 LFAST interface timing diagrams
Figure 21. LFAST timing definition
Figure 22. Power-down exit time Figure 23. Rise/fall time
9.3.2 LFAST interface electrical characteristics
frequency (preferably less than 10 MHz). Table 42. LFAST electrical characteristics Table continues on the next page...
52 NXP Semiconductors
- V DD_VH_IOx = 3.3 V -5%,+10%, TJ = –40 / 150 °C, unless otherwise specified
- Startup time is defined as the time taken by LFAST current reference block for settling bias current after its pwr_down
(power down) has been deasserted. LFAST functionality is guaranteed only after the startup time.
- Startup time is defined as the time taken by LFAST transmitter for settling after its pwr_down (power down) has been
- Startup time is defined as the time taken by LFAST transmitter for settling after its pwr_down (power down) has been
- Startup time is defined as the time taken by LFAST receiver for settling after its pwr_down (power down) has been
- Total lumped capacitance including silicon, package pin and bond wire. Application board simulation is needed to verify
- Total capacitance including silicon, package pin and bond wire
- Total inductance including silicon, package pin and bond wire
9.4 Serial Peripheral Interface (SPI) timing specifications
The following table describes the SPI electrical characteristics.
- Measurements are with maximum output load of 50 pF, input transition of 1 ns and pad configured as SRE = 11.
Table 43. SPI timing Table continues on the next page...
54 NXP Semiconductors
Table 43. SPI timing (continued)
- Slave Receive Only mode can operate at a maximum frequency of 60 MHz. In this mode, the SPI can receive data on SIN,
but no valid data is transmitted on SOUT.
- For SPI_CTARn[PCSSCK] - 'PCS to SCK Delay Prescaler' configuration is '3' (01h) and SPI_CTARn[CSSCK] - 'PCS to
SCK Delay Scaler' configuration is '2' (0000h).
- For SPI_CTARn[PASC] - 'After SCK Delay Prescaler' configuration is '3' (01h) and SPI_CTARn[ASC] - 'After SCK Delay
Scaler' configuration is '2' (0000h).
- The numbers are valid when SPI is configured for 50/50. Refer the Reference manual for the mapping of the duty cycle to
of 33/66 at SPI translates to min tSCK/3 - 1.5 ns and max tSCK/3 + 1.5 ns.
- The slave mode parameters (t SUI, tHI, tSUO and tHO) assume 50% duty cycle on SCK input. Any change in SCK duty cycle
input must be taken care during the board design or by the master timing.
- The slave receive only mode parameters (t SUI and tHI) assume 50% duty cycle on SCK input. Any change in SCK duty
tsdc(min) for the slave receive mode.
- In the master mode, this is governed by t PCSSCK. Refer the SPI chapter in the Reference Manual for details. The minimum
spec is valid only for SPI_CTARn[PCSSCK]= '0b01' (PCS to SCK delay prescalar of 3) or higher.
- In the master mode, this is governed by t PASC. Refer the SPI chapter in the Reference Manual for details. The minimum
spec is valid only for SPI_CTARn[PASC]= '0b01' (after SCK delay prescalar of 3) or higher.
- For SPI_CTARn[BR] - 'Baud Rate Scaler' configuration is >= 4.
- N = Configured sampling point value in MTFE=1 Mode.
- Same value is applicable for PCS timing in continuous SCK mode.
- SPI_MCR[SMPL_PT] should be set to 1.
For numbers shown in the following figures, see Table 43.
Figure 24. SPI classic SPI timing — master, CPHA = 0 Figure 25. SPI classic SPI timing — master, CPHA = 1
56 NXP Semiconductors
Figure 28. SPI modified transfer format timing — master, CPHA = 0 Figure 29. SPI modified transfer format timing — master, CPHA = 1 Figure 30. SPI PCS strobe (PCSS) timing
58 NXP Semiconductors
9.5 LINFlexD timing specifications
The maximum bit rate is 1.875 MBit/s.
9.6 I 2C timing
Table 44. I 2C SCL and SDA input timing specifications
1 I_tHD:STA Start Condition hold time 2 -
3 I_tHD:DAT Data hold time 2 -
4 I_tHIGH Clock high time 4 -
5 I_tSU:DAT Data setup time 4 -
6 I_tSU:STA Start condition setup time (for repeated
7 I_tSU:STOP Stop condition setup time 2 -
Table 45. I 2C SCL and SDA output timing specifications
1 O_tHD:STA Start condition hold time1 6 -
2 O_t_LOW Clock low time1 10 -
3 O_tHD:DAT Data hold time1 7 -
4 O_t_HIGH Clock high time1 10 -
5 O_tSU:DAT Data setup time1 2 -
6 O_tSU:STA Start condition setup time (for
7 O_tSU:STOP Stop condition setup time1 10 -
- Programming IBFD (I 2C Bus Frequency Divider Register) with the maximum frequency results in the minimum output
timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed in IBDR (I2C Bus Data I/O Register).
- Serial data (SDA) and Serial clock (SCL) reaches peak level depending upon the external signal capacitance and pull up
resistor values as SDA and SCL are open-drain type outputs which are only actively driven low by the I2C module.
Figure 31. I2C input/output timing
10.1 JTAG/CJTAG interface timing
The following table lists JTAGC/CJTAG electrical characteristics.
- Measurements are with input transition of 1 ns, output load of 50 pF and pads configured with SRE=11.
Table 46. JTAG/CJTAG pin AC electrical characteristics 1 Table continues on the next page...
60 NXP Semiconductors
Table 46. JTAG/CJTAG pin AC electrical characteristics 1 (continued)
- These specifications apply to JTAG boundary scan only.
- This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions.
Refer to pad specification for allowed transition frequency.
- TMS timing is applicable only in CJTAG mode
- Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
- Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.
Figure 32. JTAG test clock input timing
Figure 33. JTAG test access port timing Figure 34. JTAG JCOMP timing
62 NXP Semiconductors
Figure 35. JTAG boundary scan timing
10.2 Nexus Aurora debug port timing
Table 47. Nexus Aurora debug port timing
3 JRC Reference Clock jitter — 40 ps
5 BER Bit Error Rate — 10-12 —
Table continues on the next page...
Table 47. Nexus Aurora debug port timing (continued)
9 SO Differential output skew — 20 ps
10 SMO Lane to lane output skew — 1000 ps
11 OUI Aurora lane Unit Interval 800 800 ps
Figure 36. Nexus Aurora timings
11 WKUP/NMI timing specifications
Table 48. WKUP/NMI glitch filter
64 NXP Semiconductors
12 External interrupt timing (IRQ pin)
Table 49. External interrupt timing
- Applies when IRQ pins are configured for rising edge or falling edge events, but not both
the device reference manual for details. Figure 37. External interrupt timing
13 Temperature sensor electrical characteristics
The following table describes the temperature sensor electrical characteristics. Table 50. Temperature sensor electrical characteristics
14.1 MIPICSI2 D-PHY electrical and timing specifications
MIPICSI2 version 1.1, D-PHY specification Rev. 1.0 (for MIPI sensor port x4 lanes). Figure 38. MIPICSI2 circuit Table 51. Calibrator specifications
14.1.1 Electrical and timing information
Table 52. Electrical and timing information Table continues on the next page...
- All rights reserved. This material is reprinted with the permission of the MIPI Alliance, Inc. No part(s) of this document may
66 NXP Semiconductors
Table 52. Electrical and timing information (continued)
14.1.2 D-PHY signaling levels
that LP receiver always detects low on HS signals. Figure 39. D-PHY signaling levels
14.1.3 D-PHY switching characteristics
Table 53. D-PHY switching characteristics Table continues on the next page...
Table 53. D-PHY switching characteristics (continued)
450 MHz
50 MHz and 450 MHz
14.1.4 Low-power receiver timing
Figure 40. Input Glitch Rejection of Low-Power Receivers
68 NXP Semiconductors
14.1.5 Data to clock timing
Figure 41. Definition Table 54. Data to clock timing specifications
14.2 MIPICSI2 Disclaimer
effort, of lack of viruses, and of lack of negligence.
All materials contained herein are protected by copyright laws, and may not be reproduced, republished, distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related trademarks, trade names, and other intellectual property are the exclusive property of MIPI Alliance and cannot be used without its express prior written permission. ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL, CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL, WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document; and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance with the contents of this Document. The use or implementation of the contents of this Document may involve or require the use of intellectual property rights ("IPR") including (but not limited to) patents, patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any IPR or claims of IPR as respects the contents of this Document or otherwise. Radar module S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019
70 NXP Semiconductors
15.1 Thermal characteristics
Table 55. 257MAPBGA package thermal characteristics
- Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
- Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
- Per JEDEC JESD51-6 with the board horizontal.
- Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
for the specified package. Board temperature is measured on the top surface of the board near the package.
- Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
- Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2.
15.1.1 General notes for specifications at maximum junction
- T A = ambient temperature for the package (°C) RθJA = junction to ambient thermal resistance (°C/W)
- R θJB = junction to board thermal resistance (°C/W)
- T θBRD = average board temperature just outside the package periphery (°C)
- P D = power dissipation in the package (W) Thermal Specifications S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019 NXP Semiconductors 71
The junction to ambient thermal resistance is an industry standard parameter that provides a quick and easy estimation of thermal performance. However, junction to board thermal resistance is more appropriate for tight enclosure spaces where board temperature should be used as reference temperature. Using 2s2p board with natural convection conditions, junction temperature is found to be less than 150°C . There are two parameters in common usage: the value determined on a single layer board and the value obtained on a board with two inner planes. For packages such as PBGA, these values can significantly differ. For customer board design with different number of layers and copper percentage content, these values must be appropriately interpolated in order to evaluate junction temperature. In general, the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed in the following equation as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RθJA = RθJC + RθCA where:
- R θJA = junction to ambient thermal resistance (°C/W) RθJC = junction to case thermal resistance (°C/W)
- R θCA = case to ambient thermal resistance (°C/W) RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using this equation: TJ = TT + (ΨJT × PD) where:
- T T = thermocouple temperature on top of the package (°C)
- ΨJT = thermal characterization parameter (°C/W)
- P D = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the Thermal Specifications S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019
72 NXP Semiconductors
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
15.1.2 References
Semiconductor Equipment and Materials International; 3081 Zanker Road; San Jose, CA
95134 USA; (408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the Web at http://www.jedec.org. 1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air- Cooled Applications,” Electronic Packaging and Production, pp. 53–58, March 1998. 3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.
16 Packaging
The S32R274 is offered in the following package types. If you want the drawing for this package Then use this document number 257-ball MAPBGA 98ASA00081D NOTE For detailed information regarding package drawings, refer to www.nxp.com.
17 Reset sequence
This section describes different reset sequences and details the duration for which the device remains in reset condition in each of those conditions. Packaging S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019 NXP Semiconductors 73
17.1 Reset sequence duration
different reset sequences described in Reset sequence description. Table 57. RESET sequences
1 TDRB Destructive Reset Sequence, BIST enabled 15 502 ms
2 TDR Destructive Reset Sequence, BIST disabled 400 2000 µs
3 TERLB External Reset Sequence Long, BIST enabled 15 50 ms
4 TFRL Functional Reset Sequence Long, BIST disabled 400 2000 µs
5 TFRS Functional Reset Sequence Short3 1 500 µs
- The maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET
by an external reset generator.
- Max time is based on STCU BIST configuration execution time + max RESET time (TDR). For default STCU BIST
configuration execution time, refer to EB834. Contact your NXP sales representative for details.
- BIST is not executed on short functional reset
17.2 Reset sequence description
for which the duration is specified in Table 57. point, application execution starts and the internal reset sequence is finished. duration is included into Phase3 below. start of reset sequence in internal as well as external regulation modes. reset sequence and the possible states of the RESET_B signal pin.
74 NXP Semiconductors
Figure 45. Functional reset sequence long Figure 46. Functional reset sequence short register in the device reference manual for more information.
18 Power sequencing requirements
recommendations in this section. supplies should be treated as a single supply from board perspective. power supplies to the design are in operating range.
76 NXP Semiconductors
they can be enabled by software once design is powered up. before data is sent on its input pads.
19.1 Package pinouts and signal descriptions
For package pinouts and signal descriptions, refer to the Reference Manual. Table 58. Revision History Rev 4 May, 2018 • Removed section "4.1 Introduction".
- Removed section "3.2 Format". In Fields, removed figure "Commercial product code structure".
- In Nexus Aurora debug port timing, added t EVTIPW row.
- In Ethernet switching specifications changed the following:
- Updated the figure RMII/MII serial management channel timing diagram.
- In Ethernet MDIO timing table changed MDC10 Min value and MDC11 Max value.
- Extensively updated Table 32.
- In Table 7, changed V inxoscclkvih Max value from 1.2 to 1.23.
- In Table 25, added rows for the symbols t sampleC, tsampleS,tsampleBG, and tsampleTS.
- In Table 6, changed V INA maximum value to 6.0.
- Added the following footnotes in Absolute maximum ratings :
- The maximum value limits of injection current and input voltage both must be followed together for proper device operation.
- The maximum value of 10 mA applies to pulse injection only. DC current injection is limited to a maximum of 5 mA.
- In Table 7, changed V INA maximum value to VDD_HV_ADCREFx.
- In Table 2 :
- Changed part from FS32R274KBK2MMM to FS32R274KSK2MMM and changed configuration from "B" to "S"
- Changed part from FS32R274KBK2VMM to FS32R274KSK2VMM and changed configuration from "B" to "S"
- Added "B or S" to Table 3 Rev 5 July 03, 2018
- In Table 6, Removed footnote on I INJPAD. Rev 5 April 30, 2019
- In Table 1, added information for 266 MHz frequency parts .
- In Table 2, added the rows for "FS32R274JSK2MMM", "FS32R264KBK0MMM", "FS32R264KCK0MMM", "FS32R264JBK0MMM" and "FS32R264JCK0MMM".
- Added the feature changes for S32R264 with respect to S32R274 in Feature list. Pinouts S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019 NXP Semiconductors 77
- In Table 4, added the row for 266MHz frequency performance.
- In Table 8, added the Conditions and Max value in IDD_CORE for 266 MHz frequency.
- Added note "S32R264 devices support AFE PLL while S32R274 devices support SDPLL", in Block diagram.
- In Operating conditions, changed the footnote from "Full performance means Core0 running @ 120 MHz, Core1/2 running @ 240 MHz, SPT running @ 200 MHz, rich set of peripherals used" to "Full performance means full frequency".
Revision History
S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019
78 NXP Semiconductors
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