S32M2XX NXP | Alldatasheet
Document overview
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- PDF pages: 135
Technical content
Datasheet sections
- 1 About the document
- 2 Introduction
- 3 Block diagram
- 4 Feature comparison
- 5 Ordering information
- 6 General
- 6.1 Absolute maximum ratings
- 6.3 Thermal operating characteristics
- 6.4 ESD and Latch-up Protection Characteristics
- 7 IDD current consumption and modes
- 8.1 Power management
- 8.1.1 PMC Electrical Specifications
- 8.1.2 Voltage Monitors in Application Extension PMC
- 8.2 I/O Parameters
- 8.2.1 Application Extension IO DC electrical
- 8.2.2 High Voltage Input
- 8.4 CANPHY Electrical Specifications
- 8.5 LINPHY Electrical Specifications
- 8.6 DPGA Electrical Specifications
- 8.7 GDU Electrical Specifications
- 8.8 Temperature Monitor Electrical Specifications
- 9 S32M27x MCU electrical specifications
- 9.1 Glitch Filter
- 9.2 Power management
- 9.2.1 Supply Monitoring
- 9.3 I/O parameters
- 9.4 Flash memory specification
- 9.4.1 Flash memory program and erase
- 9.4.2 Flash memory Array Integrity and Margin Read
- 9.4.3 Flash memory module life specifications
- 9.4.3.1 Data retention vs program/erase cycles
- 9.4.4 Flash memory AC timing specifications
- 9.4.5 Flash memory read timing parameters
- 9.5 Analog modules
- 9.5.1 SAR ADC
- 9.5.2 Low Power Comparator (LPCMP)
- 9.5.3 Temperature Sensor
- 9.5.4 Supply Diagnosis
- 9.6 Clocking modules
- 9.6.1 FIRC
- 9.6.2 SIRC
- 9.6.3 Fast External Oscillator (FXOSC)
- 9.6.4 PLL
- 9.7 Communication modules
- 9.7.1 LPSPI
- 9.7.2 I2C
- 9.7.3 FlexCAN characteristics
- 9.7.4 LPUART specifications
- 9.8 Debug modules
- 9.8.1 JTAG electrical specifications
- 9.8.2 SWD electrical specifications
- 10 S32M24x MCU electrical specifications
- 10.1 General
- 10.1.1 LVR, LVD and POR operating requirements
- 10.2 I/O parameters
- 10.2.1 AC electrical characteristics
- 10.2.2 General AC specifications
- 10.2.6 AC electrical specifications at 5 V range
- 10.2.7 Standard input pin capacitance
- 10.2.8 Device clock specifications
- 10.3 Peripheral operating requirements and
- 10.3.1 System modules
- 10.3.2 Clock interface modules
- 10.3.2.1 External System Oscillator electrical
- 10.3.2.2 External System Oscillator frequency
- 10.3.2.3 System Clock Generation (SCG) specifications
- 10.3.2.4 Low Power Oscillator (LPO) electrical
- 10.3.2.5 SPLL electrical specifications
- 10.3.3 Memory and memory interfaces
- 10.3.3.1 Flash memory module (FTFC/FTFM) electrical
- 10.3.4 Analog modules
- 10.3.4.1 ADC electrical specifications
- This document provides electrical specifications for S32M2xx.
- For functional characteristics and the programming model, see S32M24x and S32M27x Reference Manuals. S32M241 S32M242 S32M243 S32M244 S32M274 S32M276 S32M2xx S32M2xx Data Sheet Supports S32M24x and S32M27x Rev. 3 — 10/2023 Data Sheet: Advance Information This document contains information on a new product. Specifications and information herein are subject to change without notice.
10.3.4.2 CMP with 8-bit DAC electrical specifications102
10.4.1 General notes for specifications at maximum
1 About the document
This document is divided into four main parts: 1. Sections in the first set contain information that applies to the S32M27x and S32M24x System in Package (SIP) devices. These includes from section 2 to section 7 and section 11 and 12. 2. Sections in the second set are applicable to “Application extension” Subsytem, hence applies to both S32M24x and S32M27x, this includes section 8 and its sub-sections. 3. Sections in the third set are applicable to S32M27x MCU, this includes section 9 and its sub-sections. 4. Sections in the fourth set are applicable to S32M24x MCU, this includes section 10 and its sub-sections.
2 Introduction
S32M2 is a family of integrated solutions based on ARM Cortex M microcontroller cores that closely resemble NXP’s S32K MCU products with the addition of high voltage analog features. The commonality between S32M2 and S32K, be that hardware or supporting software and firmware, results in a combined portfolio with scalability between general purpose MCUs and integrated solutions. Building on S32K System on Chip (SoC) microcontrollers, S32M2's System in Package (SiP) integrates automotive qualified and application-focused capabilities like voltage-regulators operating directly from a car battery, physical communications interfaces (LIN, CXPI, or CAN FD), and MOSFET Gate pre-drivers for motor control. With attention to cost at the system level, S32M2 integrates voltage regulators, pulse-width modulators, analog to digital converters, timers, non-volatile memory and more to reduce overall component count and reduce board space. This document covers, S32M24x and S32M27x families, both targeting motor control for a single BLDC/PMSM motor or up to three Brushed DC motors. Communication is over LIN, CXPI, or CAN FD directly with the included physical interfaces. The main attributes of devices within the sub-family are:
- Built-in voltage regulation and protection to run directly from a reverse-battery protected 12V car battery supply.
- 5V voltage output to supply power to an external component like hall sensor.
- LIN, CXPI or CAN-FD physical interface for direct connection to the communications bus without an external phy.
- Arm Cortex M4 processors with Floating Point running up to 80MHz or Arm Cortex M7 processors with Floating Point running up to 120 MHz.
- Non-volatile program memory from 128KB to 1MB.
- Integrated gate driver for up to 6 external power MOSFETs for BLDC or PMSM motor drive applications.
- 64-pin LQFP-EP Package.
3 Block diagram
The following figures shows block diagram of the S32M24x and S32M27x family. On the left side is the MCU and on the right side is the AE. The SiP boundary is the bold dashed line. The diagram shows typical external components required for a 3-phase motor control application with single-shunt current sensing. NXP Semiconductors About the document S32M2xx Data Sheet, Rev. 3, 10/2023 Data Sheet: Advance Information Preliminary Information 4 / 135
1 . The pins PTA5 and RESET_B must be connected at board level.
- The VPRE voltage can be regulated using an external p-channel power FET (gate controlled via the GCTL pin), to reduce the on chip power dissipation and assure that the maximum operating junction temperature is not exceeded. Depending on the operating conditions of the application (ambient temperature, MCU load), the external FET could be required.
10 Kohm
1 Kohm 1 (See footnote)PTA5
Figure 1. S32M24x Block diagram
- The VPRE voltage can be regulated using an external p-channel power FET (gate controlled via the GCTL pin), to reduce the on chip power dissipation and assure that the maximum operating junction temperature is not exceeded. Depending on the operating conditions of the application (ambient temperature, MCU load), the external FET could be required.
Figure 2. S32M27x Block diagram
4 Feature comparison
“CAN” or “LIN”. See the Ordering Information section. Table 1. S32M24x Feature comparison Table continues on the next page...
Table 1. S32M24x Feature comparison (continued) Table continues on the next page...
- Six channels of the FTM3 are internally connected for the PWM signals on GDU.
- The number of timer channels available on external pins depends on the package option (CAN or LIN). For the actual IO
mapping, see the IOMUX file attached to the S32M24x Reference Manual.
- The number of ADC channels available on external pins depends on the package option (CAN or LIN). For the actual ADC
connections (high voltage Input, VSUP sense, temperature sensor).
- There are two UART/LIN modules in S32M24x. On LIN variants, LPUART1 is internally connected to LIN/CXPI PHY.
- There are two SPI modules in S32M242 and S32M241, and three SPI modules in S32M244 and S32M243. LPSPI1 is
dedicated to internal configuration and communication.
- There is one CAN module in S32M24x. On CAN variant, CAN0 is internally connected to CAN FD PHY for CAN
Table 2. S32M27x Feature comparison Table continues on the next page...
Table 2. S32M27x Feature comparison (continued)
- Six outputs of the LCU are internally connected for the PWM signals on GDU.
- Additionally, there are six ADC channels that are internally connected for: current sense from DPGA, DC link voltage
monitoring, phase voltage measurement, and HVM connections (high voltage Input, VSUP sense, temperature sensor).
- There are four UART/LIN modules in S32M27x. On LIN variants, LPUART1 is internally connected to LIN/CXPI PHY.
- There are four LPSPI modules in S32M27x, listing only modules with external pins available. LPSPI1 is dedicated to internal
configuration and communication.
- There are three CAN modules in S32M27x. On CAN variant, CAN0 is internally connected to CAN FD PHY for CAN
5 Ordering information
P/S 32 M 2 4 X X X AB M PA S R Product status Product type/brand Product line Family Core Memory size Communications options Security Fab and mask rev letter Temperature suffix Package suffix Software configuration Tape and reel indicator M24x M27x * 3 is used only for S32M243, a special grade zero capable version for 256 KB Product status P: Prototype S: Qualified ordering P/N Product type/brand 32: Automotive 32-bit MCU/MPU Product line and family M2 = 12 V motor control Core platform 4 = Arm cortex M4 7 = Arm cortex M7, single core Memory size - 128 K 256 K 512 K 1 MB 0 1 2, 3* 4 6 8 MB
Features
L: LIN phy C: CAN FD phy X: CXPI phy Security C: CSEc security (S32M24x) H: HSE security (S32M27x) x: OEM specific security firmware Fab and mask rev letter See table 3 below Temperature suffix V: -40ºC to 105ºC M: -40ºC to 125ºC W: -40ºC to 150ºC (S32M243/244 only) Package suffix Software configuration S = Family SW package, including:
- SDK
- AUTOSAR MCAL(ISO26262, crypto driver included)
- Core self test SW
- Standard security firmware Additional solution specific SW Tape and reel indicator T: Trays/tubes R: Tape and reel 64 KH Pins LQFP-EP
Figure 3. Ordering information Table 3. Part number information
Ordering information
S32M2xx Data Sheet, Rev. 3, 10/2023 Data Sheet: Advance Information Preliminary Information 10 / 135
6 General
6.1 Absolute maximum ratings
and minimum values in the datasheet are across process, voltage, and temperature. maximum ratings is not implied. Table 4. Absolute maximum ratings Table continues on the next page...
Table 4. Absolute maximum ratings (continued) Table continues on the next page...
Table continues on the next page...
- Negative range is applicable only with external 10Kohm series resistor. Otherwise, the HVI input pin voltage range is
limited to -0.3V < VHVI < 42V.
- Negative DC voltages on the High-Side Gate (HGx) pins and Low-Side Gate (LGx) pins are only possible when the
Low-side drivers: 12V ≥ (LGx - LSx) ≥ -0.3V.
- Negative limit is applicable only for pulsed operation.
- Negative range is applicable only with external series resistor populated, R ≥ 2.34KOhm.
- If the GCTL pin is not used, it must be left unconnected.
- For S32M24x devices, VDD_AE10, VDD and VDDA must be shorted to a common source on PCB.
- The supply should be kept in operating conditions and once out of operating conditions, the device should be either
held in reset condition by external circuit is allowed for 10 hours cumulative over lifetime.
- While respecting the maximum current injection limit.
- 60 seconds lifetime; device in reset (no outputs enabled/toggling)
- 6.0 V maximum for 10 hours over lifetime; 7.0 V maximum for 60 seconds over lifetime.
- For S32M27x devices, VDD_AE10 and VDD_HV_A must be shorted to a common source on PCB.
- Absolute max rating must be honored under all conditions, including current injection.
- When input pad voltage levels are close to the supply (VDD or VDD_HV_A) or VSS, practically no current injection is
- All MCU digital I/O pins are internally clamped to VSS and VDD or VDDA (S32M24x devices), or VSS and VDD_HV_A
All VSS or ground pins and the exposed pad must be connected in a common and single reference in the PCB.
6.2 Voltage and current operating requirements
This section describes the operating conditions of the device. All voltages are referred to VSS unless otherwise specified. the ADC reference high voltage (VREFH) at 5 V, temperature = 25 °C and typical silicon process unless otherwise stated. degraded when voltage drops below the minimum supply voltage. Table 5. Voltage and current operating requirements Table continues on the next page...
Table 5. Voltage and current operating requirements (continued) Table continues on the next page...
- Normal operating range is 5.5V - 18V. Continuous operation at 40V is not allowed. Only Transient Conditions (Load Dump)
the device due to the over-voltage protection based on the HD pin voltage level.
- VDD and VDDA must be shorted to a common source on PCB. The differential voltage between VDD and VDDA is for
reference supply design for SAR ADC.
- VREFH should always be equal to or less than the supply rail + 0.1 V (VDDA + 0.1V and VDD + 0.1 V, or VDD_HV_A +
- Open-drain outputs must be pulled respectively to their supply rail (VDD or VDD_HV_A).
- When input pad voltage levels are close to the supply rails (VDD or VDD_HV_A) or VSS, practically no current injection is
- This is the device supply ramp rate, applicable to the main supply (VSUP).
6.3 Thermal operating characteristics
Table 6. Thermal operating characteristics Table continues on the next page...
Table 6. Thermal operating characteristics (continued)
6.4 ESD and Latch-up Protection Characteristics
Table 7. ESD and Latch-up Protection Characteristics Table continues on the next page...
Table 7. ESD and Latch-up Protection Characteristics (continued)
- This parameter is tested in conformity with AEC-Q100-002.
- Device failure is defined as: "If after exposure to ESD pulses, the device does not meet specification requirements."
- Pins stressed to reference group containing all ground pins.
- Pins stressed to reference group containing all ground and supply pins.
- This parameter is tested in conformity with AEC-Q100-011.
- To further improve ESD/EMI robustness in case the signal to the HVI pin comes from an off-board (global) source, a 10nF
- This parameter is tested in conformity with AEC-Q100-004.
- Positive current injection is not possible for the following pins: BST, LSx, HSx.
All ESD testing conforms with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
7 IDD current consumption and modes
See next page for IDD current consumption and modes.
Table 8. IDD current consumption
- VPRE using external ballast transistor
Table 9. IDD modes
8 Application extension electrical specifications
8.1 Power management
8.1.1 PMC Electrical Specifications
Table 10. PMC Electrical Specifications Table continues on the next page...
Table 10. PMC Electrical Specifications (continued) Table continues on the next page...
- All capacitors must be low ESR ceramic capacitors (for example, X7R) with 20% maximum deviation allowed.
8.1.2 Voltage Monitors in Application Extension PMC
Table 11. Voltage Monitors in Application Extension PMC
8.2 I/O Parameters
8.2.1 Application Extension IO DC electrical specifications
The following table includes the specifications for the I/O pads of the Application Extension.
Table 12. Application Extension IO DC electrical specifications Table continues on the next page...
Table 12. Application Extension IO DC electrical specifications (continued)
- A positive value is leakage flowing into pin with pin at the GPIO supply level; a negative value is leakage flowing out the pin
8.2.2 High Voltage Input
The table below gives the specification for the High Voltage Input (HVI) and the Voltage Monitor (VM). Table 13. High Voltage Input Table continues on the next page...
Table 13. High Voltage Input (continued) Table continues on the next page...
Table continues on the next page...
Table continues on the next page...
- Analog supply currents consumed by pull up or pull down function can be calculated out of selected impedance values.
- A resistor with value of HVI_R is required to be placed externally at HVI pin. If the signal connected to HVI_R resistor is
resistor type "0805" is large enough to avoid arching during GUN.
- HVM_RATIO = V(HVI_R) / V(SENSE_INT). V(HVI_R) is the voltage at the resistor HVI_R. V(SENSE_INT) is the down
- Value includes resistor HVI_R.
and chose the highest ADC resolution.
- Any enable/disable of a function has the effect, for this function and also other functions, to wait for the signal to stabilize.
Same applies also in case of switching the input sources. Table 14. 42 MHz RC Oscillator electrical specifications
8.4 CANPHY Electrical Specifications
Table 15. CANPHY Electrical Specifications Table continues on the next page...
Table 15. CANPHY Electrical Specifications (continued)
2.5 MHz
Table continues on the next page...
- CRXD is applied onto the AMPOUT pin with CAN-PHY configuring in certification mode (AE
IO_FUNCMUX_CFG[AMPOUT_SEL]=001b, and VDD_AE10 is in 5V mode (PMC_AE CONFIG[VDD_SEL5V]=1).
8.5 LINPHY Electrical Specifications
Table 16. LINPHY Electrical Specifications
18 V; LIN Active mode;
12 V; 0 V < VLIN < 18
28 V; LIN Active mode
Table continues on the next page...
Table 16. LINPHY Electrical Specifications (continued)
7 V to 18 V
4.8 V to 7 V
7.6 V to 18 V
Table continues on the next page...
- The device is compliant with LIN 2.2a.
8.6 DPGA Electrical Specifications
Table 17. DPGA Electrical Specifications Vout Output voltage range 0.25 — Vvdda-0. Table continues on the next page...
Table 17. DPGA Electrical Specifications (continued) Table continues on the next page...
Table continues on the next page...
Table continues on the next page...
- VIN spec is the voltage range of each individual pin (AMPP,AMPM)
- This is the initial value after production; aging drift is not included.
- The step can be further reduced by utilizing level shifting current source trimming.
8.7 GDU Electrical Specifications
Table 18. GDU Electrical Specifications
10 V, 40 KHz 1
Table continues on the next page...
Table 18. GDU Electrical Specifications (continued) Table continues on the next page...
Table continues on the next page...
Table continues on the next page...
Table continues on the next page...
- Total gate charge spec is only a recommendation. FETs with higher gate charge can be used when resulting slew rates
are tolerable by the application and resulting power dissipation does not lead to thermal overload.
- max VHSx | VHD =20V, ADC supply=3.3V
- max VHSx | VHD =20V, ADC supply=5V
- max VHSx | VHD =30.65V, ADC supply=3.3V
- max VHSx | VHD =30.65V, ADC supply=5V
- (VBSx - HSx) = 10V respectively VLSx=10V, measured from 1V to 9V HGx/LGx vs HSx/LSx
- (VBSx - HSx) = 10V respectively VLSx=10V, measured from 9V to 1V HGx/LGx vs HSx/LSx
- The delay is dependent on slew rate configuration. The variation on a given device for a given slew setting is much less
- ROSD_pu =~ROSD_pd, VSUP>=7V
8.8 Temperature Monitor Electrical Specifications
Table 19. Temperature Monitor Electrical Specifications Table continues on the next page...
Table 19. Temperature Monitor Electrical Specifications (continued)
- The error caused by ADC conversion and provided temperature calculation formula is not included.
- TMON_PHY measurements can deviate by TTSENS_acc_offset from the accuracy achievable by TMON_PMC.
- In the lowest temperature quadrant (up to 85°C) the temperature sensor accuracy is relaxed to +/- 10°C. This includes
9 S32M27x MCU electrical specifications
9.1 Glitch Filter
The glitch filter parameters in the following table apply to the filters of WKPU pins and TRGMUX inputs 60-63. Table 20. Glitch Filter
- An input signal pulse is defined by the duration between the input signal's crossing of a Vil/Vih threshold voltage level, and
the next crossing of the opposite level.
- Pulses shorter than defined by the maximum value are guaranteed to be filtered (not passed).
- Pulses in between the max filtered and min unfiltered may or may not be passed through.
- Pulses larger than defined by the minimum value are guaranteed to not be filtered (passed).
9.2 Power management
9.2.1 Supply Monitoring
Table 21. Supply Monitoring
9.3 I/O parameters
Table 22. GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V) Table continues on the next page...
Table 22. GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V) (continued) Table continues on the next page...
Table continues on the next page...
- Maximum length of RESET pulse will be filtered by an internal filter on this pin.
- Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter.
- A positive value is leakage flowing into pin with pin at VDD_HV_A/B (the GPIO supply level); a negative value is leakage
flowing out the pin with the pin at ground.
- GPIO output transition time information can be obtained from the device IBIS model. IBIS models are recommended for
connected to an actual transmission line load.
- I/O output current specifications are valid for the given reference load figure, and the constraints given in the Operating
Conditions of this document.
- I/O timing specifications are valid for the un-terminated transmission line reference load given in the figure below. A
total with margin). For signals with frequency greater than 63MHz, a maximum 2 inch PCB trace is assumed.
- See IBIS models for further details.
Figure 4. Reference Load Diagram
Table 23. GPIO DC electrical specifications, 5.0V (4.5V - 5.5V) Table continues on the next page...
Table 23. GPIO DC electrical specifications, 5.0V (4.5V - 5.5V) (continued) Table continues on the next page...
- Maximum length of RESET pulse will be filtered by an internal filter on this pin.
- Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter.
- A positive value is leakage flowing into pin with pin at VDD_HV_A/B (the GPIO supply level); a negative value is leakage
flowing out the pin with the pin at ground.
- GPIO output transition time information can be obtained from the device IBIS model. IBIS models are recommended for
connected to an actual transmission line load.
- I/O output current specifications are valid for the given reference load figure, and the constraints given in the Operating
Conditions of this document.
- I/O timing specifications are valid for the un-terminated transmission line reference load given in the figure below. A
- See IBIS models for further details.
Figure 5. Reference Load Diagram
Table 24. 3.3V (2.97V - 3.63V) GPIO Output AC Specification Table 25. 5.0V (4.5V - 5.5V) GPIO Output AC Specification Table continues on the next page...
Table 25. 5.0V (4.5V - 5.5V) GPIO Output AC Specification (continued)
9.4 Flash memory specification
9.4.1 Flash memory program and erase specifications
Table 26. Flash memory program and erase specifications
- Program times are actual hardware programming times and do not include software overhead. Sector program times
assume quad-page programming.
- Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 °C. Typical program and erase times may be used for throughput calculations.
- Conditions: ≤ 25 cycles, nominal voltage.
- Plant Programing times provide guidance for timeout limits used in the factory.
- Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations.
- Conditions: -40°C ≤TJ ≤150°C, full spec voltage.
9.4.2 Flash memory Array Integrity and Margin Read specifications
Table 27. Flash memory Array Integrity and Margin Read specifications Table continues on the next page...
Table 27. Flash memory Array Integrity and Margin Read specifications (continued)
- Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The
read setup that requires 6 clocks to read Nread would equal 6.
- Array Integrity times are actual hardware execution times and do not include software overhead or system code execution
- The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the
equation, the results of the equation are also unit accurate.
9.4.3 Flash memory module life specifications
Table 28. Flash memory module life specifications 1 MB and 2 MB blocks using Sector Erase. Table continues on the next page...
Table 28. Flash memory module life specifications (continued)
- Program and erase supported for factory conditions. Nominal supply values and operation at 25°C.
9.4.3.1 Data retention vs program/erase cycles
Graphically, Data Retention versus Program/Erase Cycles can be represented by the following figure. The spec window represents qualified limits. Figure 6. Data retention vs program/erase cycles
9.4.4 Flash memory AC timing specifications
Table 29. Flash memory AC timing specifications Table continues on the next page...
Table 29. Flash memory AC timing specifications (continued)
- For Block Erase, Tdones times may be 3x max spec.
- In extreme cases (1 block configurations) Tdrcv min may be faster (12uS plus seven system clocks)
9.4.5 Flash memory read timing parameters
Table 30. Flash Read Wait State Settings (S32M27x)
250 KHz < Freq ≤ 66 MHz 1
66 MHz < Freq ≤ 100 MHz 2
100 MHz < Freq ≤ 133 MHz 3
133 MHz < Freq ≤ 167 MHz 4
167 MHz < Freq ≤ 200 MHz 5
200 MHz < Freq ≤ 233 MHz 6
233 MHz < Freq ≤ 250 MHz 7
9.5 Analog modules
9.5.1 SAR ADC
Table 31. SAR ADC Table continues on the next page...
Table 31. SAR ADC (continued)
- Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for reference
- VSS and VREFL should be shorted on PCB. 100mV difference between VSS and VREFL is for transient only (not for DC).
- This is ADC Input range for ADC accuracy guaranteed in this input range only. For SoC Pin capability, see Operation
- TUE spec for precision and standard channels is based on 12-bit level resolution.
- Spec valid if potential difference between VDD_HV_A and VREFH should follow VDD_HV_A +0.1V >=VREFH >=
Figure 7. SAR ADC Input Circuit
9.5.2 Low Power Comparator (LPCMP)
Table 32. Low Power Comparator (LPCMP) Table continues on the next page...
Table 32. Low Power Comparator (LPCMP) (continued)
- vdda is comparator HV supply and internally shorted to VDD_HV_A pin. vss is comparator ground
- Difference at input > 200mV
- Applied +/- (100 mV + VAHYST0/1/2/3 + max. of VAIO) around switch point
- Applied +/- (30 mV + VAHYST0/1/2/3 + max. of VAIO) around switch point
- 1 LSB = (vrefh_cmp - vrefl_cmp) /256. vrefh_cmp and vrefl_cmp are comparator reference high and low
- Calculation method used: Linear Regression Least Square Method
pull up/down is recommended). VDD_HV_B. These channels must be disabled when VDD_HV_A goes below VDD_HV_B.
Figure 11. Typical Hysteresis vs VAIN (VDD_HV_A = 5 V, Low Speed Mode).png
9.5.3 Temperature Sensor
The table below gives the specification for the MCU on-die temperature sensor. Table 33. Temperature Sensor
- Required ADC sampling time specified by parameter TS_TADCSA needs to be used at the ADC conversion to guarantee
the specified accuracy. A smaller sampling time leads to a less accurate result.
- Note: The temperature sensor measures the junction temperature Tj at the location where it is placed on die. The local Tj
is modulated by current and previous active state of the circuit elements on die.
- The error caused by ADC conversion and provided temperature calculation formula is not included.
9.5.4 Supply Diagnosis
The table below gives the specification for the on die supply diagnosis.
Table 34. Supply Diagnosis
- Required ADC sampling time specified by parameter AN_TADCSA needs to be used at the ADC conversion to guarantee
the specified accuracy. A smaller sampling time leads to a less accurate result.
- If V15 > VDD_HV_A +100mV then the V15 measurement via anamux may be imprecise.
- These specs will have degraded performance when used in extended supply voltage operation range, i.e. normal supply
voltage range specification is exceeded.
9.6 Clocking modules
9.6.1 FIRC
Table 35. FIRC
- Startup time is for reference only.
9.6.2 SIRC
Table 36. SIRC Table continues on the next page...
Table 36. SIRC (continued)
- Startup time is for information only.
9.6.3 Fast External Oscillator (FXOSC)
Table 37. Fast External Oscillator (FXOSC) Table continues on the next page...
Table 37. Fast External Oscillator (FXOSC) (continued)
- For bypass mode applications, the EXTAL pin should be driven low when FXOSC is in off/disabled state.
- The startup time specification is valid only when the recommended crystal and load capacitors are used. For higher load
capacitances, the actual startup time might be higher.
- The recommended gm setting to ensure extal swing < 2.75V at 8MHz in ALC-disabled mode is gm=4'b0010.
Recommended gm settings in ALC-disabled mode for all other supported frequencies and crystals remain the same. To ensure stable oscillations, FXOSC incorporates the feedback resistance internally. the crystal drive level rating. In such cases, contact NXP sales representative for selecting the correct crystal.
- gmXOSC is the transconductance of the internal oscillator circuit
- ESR is the equivalent series resistance of the external crystal
- RS is the series resistance connected between XTAL pin and external crystal for current limitation
- F is the external crystal oscillation frequency
- C0 is the shunt capacitance of the external crystal
- CL is the external crystal total load capacitance. CL = Cs+ [C1*C2/(C1+C2)]
- Cs is stray or parasitic capacitance on the pin due to any PCB traces
- C1, C2 external load capacitances on EXTAL and XTAL pins See manufacture datasheet for external crystal component values
Figure 12. Oscillation build-up equation
Figure 13. Block diagram
9.6.4 PLL
Jitter values specified in this table are applicable for FXOSC reference clock input only. Table 38. PLL Table continues on the next page...
Table 38. PLL (continued)
- Jitter numbers are valid only at IP boundary and does not include any degradation due to IO pad for clock measurement.
- Jitter numbers calculated by extrapolating RMS jitter numbers to +/- 7 sigma .
- For SSCG, jitter due to systematic modulation needs to be added as per applied modulation. Accumulated jitter
9.7 Communication modules
9.7.1 LPSPI
of the transfer attributes are programmable. The following table provides timing characteristics for classic LPSPI timing modes.
- All timing is shown with respect to 50% VDD_HV_A/B thresholds.
- All measurements are with maximum output load of 30 pF, input transition of 1 ns and pad configured with fastest slew setting
Table 39. LPSPI Table continues on the next page...
Table 39. LPSPI (continued) Table continues on the next page...
Table continues on the next page...
- For LPSPI0 instance, max. peripheral frequency is equal to AIPS_PLAT_CLK.
- fperiph = LPSPI peripheral clock
- Master Loopback mode: In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting
LPSPI_CFGR1[SAMPLE] bit as 1.
- These specifications apply to the SPI operation, as master or slave, at up to 10 Mbps for the combinations not indicated
configurations. See table "LPSPI 20 MHz and 15 MHz Combinations.
- LPSPI0 support up to 20MHz on fast pin.
- Minimum configuration value for CR[PCSSCK] field is 3(0x00000011).
- Minimum configuration value for CCR[SCKPCS] field is 3(0x00000011).
- While selecting odd dividers, ensure Duty Cycle is meeting this parameter.
- Output rise/fall time is determined by the output load and GPIO pad drive strength setting. See the GPIO specifications for
- The input rise/fall time specification applies to both clock and data, and is required to guarantee related timing parameters.
Figure 14. LPSPI Slave Mode Timing (CPHA=1)
Figure 15. LPSPI Slave Mode Timing (CPHA=0) Figure 16. LPSPI Master Mode Timing (CPHA=0) Figure 17. LPSPI Master Mode Timing (CPHA=1)
9.7.2 I2C
See I/O parameters for I2C specification.
For supported baud rate see section 'Chip-specific LPI2C information' of the Reference Manual.
9.7.3 FlexCAN characteristics
See I/O parameters for FlexCAN specification. For supported baud rate, see section 'Protocol timing' of the Reference Manual.
9.7.4 LPUART specifications
See I/O parameters for LPUART specifications.
9.8 Debug modules
9.8.1 JTAG electrical specifications
The following table describes the JTAG electrical characteristics. These specifications apply to JTAG and boundary scan. Measurements are with maximum output load of 30pF, input transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0. Table 40. JTAG electrical specifications Table continues on the next page...
Figure 20. Boundary Scan Timing
9.8.2 SWD electrical specifications
transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0. Table 41. SWD electrical specifications Table continues on the next page...
Table 41. SWD electrical specifications (continued) Figure 21. SWD Input Clock Timing Figure 22. SWD Output Data Timing
10 S32M24x MCU electrical specifications
10.1 General
10.1.1 LVR, LVD and POR operating requirements
Table 42. VDD supply LVR, LVD and POR operating requirements for S32M241 and S32M242 series1 Table continues on the next page...
Table 42. VDD supply LVR, LVD and POR operating requirements for S32M241 and S32M242 series1 (continued)
- In 3.3 V range, the VLVW is always set since supply remains below VLVW range. Hence PMC.LVDSC2[LVWIE] should
remain cleared while device operates in 3.3 V range.
- Rising threshold is the sum of falling threshold and hysteresis voltage.
Table 43. VDD supply LVR and POR operating requirements for S32M243 and S32M244 series1
- In 3.3 V range, the VLVW is always set since supply remains below VLVW range. Hence PMC.LVDSC2[LVWIE] should
remain cleared while device operates in 3.3 V range.
- Rising threshold is the sum of falling threshold and hysteresis voltage.
- An internal monitor could reset the chip at a higher supply level, but 3.13 V onward the chip is fully functional.
10.1.2 Power mode transition operating behaviors
Table 44. Clock configuration Table continues on the next page...
Table 44. Clock configuration (continued) Table 45. Power mode transition operating behaviors for S32M241 and S32M242 series across the operating temperature range of the chip. Table continues on the next page...
Table 45. Power mode transition operating behaviors for S32M241 and S32M242 series (continued) Table 46. Power mode transition operating behaviors for S32M243 and S32M244 series across the operating temperature range of the chip.
10.2 I/O parameters
10.2.1 AC electrical characteristics
at the 20% and 80% points, as shown in the following figure.
Figure 23. Input signal measurement reference
10.2.2 General AC specifications
These general purpose specifications apply to all signals configured for GPIO, UART, and timers. Table 47. General switching specifications
- This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may
- The greater of synchronous and asynchronous timing must be met.
- These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be recognized.
- Maximum length of RESET pulse which will be the filtered by internal filter only if PCR_PTA5[PFE] is at its reset value of
- Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter only if PCR_PTA5[PFE] is at its reset
of PCM_RPC register and/or PORT_DFER register for PTA5. IO Signal Description Input Multiplexing sheet(s) attached with Reference Manual.
Table 48. DC electrical specifications at 3.3 V Range for S32M242 series
- For reset pads, same Vih levels are applicable
- For reset pads, same Vil levels are applicable
- The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_Standard value
- For refernce only. Run simulations with the IBIS model and custom board for accurate results.
- Typical leakage is given at room temperature. Maximum is given for 125°C. Leakage numbers increase with temperature,
to charge the sample and hold capacitances and internal analog busses. These are difficult to predict.
- Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All
- Measured at input V = VSS
- Measured at input V = VDD
Table 49. DC electrical specifications at 3.3 V Range for S32M244 series
- For reset pads, same Vih levels are applicable
- For reset pads, same Vil levels are applicable
- The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_Standard value
- Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All
- Measured at input V = VSS
- Measured at input V = VDD
Table 50. DC electrical specifications at 5.0 V Range for S32M242 series
- For reset pads, same Vih levels are applicable
- For reset pads, same Vil levels are applicable
- The strong pad I/O pin is capable of switching a 50 pF load up to 40 MHz.
- For refernce only. Run simulations with the IBIS model and custom board for accurate results.
- Typical leakage is given at room temperature. Maximum is given for 125°C. Leakage numbers increase with temperature,
to charge the sample and hold capacitances and internal analog busses. These are difficult to predict.
- Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All
- Measured at input V = VSS
- Measured at input V = VDD
Table 51. DC electrical specifications at 5.0 V Range for S32M244 series
- For reset pads, same Vih levels are applicable
- For reset pads, same Vil levels are applicable
- The strong pad I/O pin is capable of switching a 50 pF load up to 40 MHz.
- Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All
- Measured at input V = VSS
- Measured at input V = VDD
Table 52. AC electrical specifications at 3.3 V Range for S32M242 series
- For reference only. Run simulations with the IBIS model and your custom board for accurate results.
- Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be different,
for example for ENET, QSPI etc. . For protocol specific AC specifications, see respective sections. Table 53. AC electrical specifications at 3.3 V Range for S32M244 series
- For reference only. Run simulations with the IBIS model and your custom board for accurate results.
- Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be different.
For protocol specific AC specifications, see respective sections.
10.2.6 AC electrical specifications at 5 V range
Table 54. AC electrical specifications at 5 V Range for S32M242 series
- For reference only. Run simulations with the IBIS model and your custom board for accurate results.
- Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be different,
for example for ENET, QSPI etc. . For protocol specific AC specifications, see respective sections. Table 55. AC electrical specifications at 5 V Range for S32M244 series
- For reference only. Run simulations with the IBIS model and your custom board for accurate results.
- Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be different.
For protocol specific AC specifications, see respective sections.
10.2.7 Standard input pin capacitance
Table 56. Standard input pin capacitance Please refer to External System Oscillator electrical specifications for EXTAL/XTAL pins.
10.2.8 Device clock specifications
Table 57. Device clock specifications 1
- Refer to the section Feature comparison for the availability of modes and other specifications.
- With SPLL as system clock source.
- 48 MHz when fSYS is 48 MHz
- The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
10.3 Peripheral operating requirements and behaviors
10.3.1 System modules
There are no electrical specifications necessary for the device's system modules.
10.3.2 Clock interface modules
10.3.2.1 External System Oscillator electrical specifications
Figure 24. Oscillator connections scheme Table 58. External System Oscillator electrical specifications Table continues on the next page...
Table 58. External System Oscillator electrical specifications (continued)
- Crystal oscillator circuit provides stable oscillations when gmXOSC > 5 * gm_crit. The gm_crit is defined as:
- gmXOSC is the transconductance of the internal oscillator circuit
- ESR is the equivalent series resistance of the external crystal
- RS is the series resistance connected between XTAL pin and external crystal for current limitation
- F is the external crystal oscillation frequency
- C0 is the shunt capacitance of the external crystal
- CL is the external crystal total load capacitance. CL = Cs+ [C1*C2/(C1+C2)]
- Cs is stray or parasitic capacitance on the pin due to any PCB traces
- C1, C2 external load capacitances on EXTAL and XTAL pins See manufacture datasheet for external crystal component values 2. • When low-gain is selected, internal RF will be selected and external RF should not be attached.
- When high-gain is selected, external RF (1 M Ohm) needs to be connected for proper operation of the crystal. For external resistor, up to 5% tolerance is allowed. 3. RS should be selected carefully to have appropriate oscillation amplitude for both protecting crystal or resonator device and satisfying proper oscillation startup condition. 4. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 5. Minimum value is shown as a reference only, however the HW design needs to ensure it reaches the maximum value by following the guidelines given in above notes (notes 1, 2, and 3) and performs the required robustness testing at the application level. During testing, a low capacitance probe (< 5 pF ) must be used to avoid any decrease in the Vpp_EXTAL value. NXP Semiconductors S32M24x MCU electrical specifications S32M2xx Data Sheet, Rev. 3, 10/2023 Data Sheet: Advance Information Preliminary Information 89 / 135
10.3.2.2 External System Oscillator frequency specifications
Table 59. External System Oscillator frequency specifications
40 MHz low-gain mode (HGO=0) — 2 —
40 MHz high-gain mode (HGO=1) — 2 —
- For an ideal clock of 40 MHz, if permitted by application requirements, an error of +/- 5% is supported with 50% duty cycle.
- (S32M244) At 40 MHz to 36 MHz when sourcing for ADC clock please use divider ADCn.ADC_CFG1[ADICLK] to ½ or
better duty cycle to be maintained. For frequencies lower than 32 MHz, please maintain duty cycle of 40-50% or better.
- Frequencies below 40 MHz can be used for degraded duty cycle upto 40-60%. When using for ADC clock further
higher duty cycle should be maintained.
- (S32M244) The limits to source ADC clock are 40 MHz, so in cases the input clock is higher than 40 MHz, it cannot be
used as a source of ADC clock.
- Proper PC board layout procedures must be followed to achieve specifications.
10.3.2.3 System Clock Generation (SCG) specifications
10.3.2.3.1 Fast internal RC Oscillator (FIRC) electrical specifications
Table 60. Fast internal RC Oscillator electrical specifications for S32M242 series
- With FIRC regulator enable
- Startup time is defined as the time between clock enablement and clock availability for system use.
Table 61. Fast internal RC Oscillator electrical specifications for S32M244 series
- With FIRC regulator enable
- Startup time is defined as the time between clock enablement and clock availability for system use.
Fast internal RC oscillator is compliant with LIN when device is used as a slave node.
10.3.2.3.2 Slow internal RC oscillator (SIRC) electrical specifications
Table 62. Slow internal RC oscillator (SIRC) electrical specifications for S32M242 series
- Startup time is defined as the time between clock enablement and clock availability for system use.
Table 63. Slow internal RC oscillator (SIRC) electrical specifications for S32M244 series
- Startup time is defined as the time between clock enablement and clock availability for system use.
10.3.2.4 Low Power Oscillator (LPO) electrical specifications
Table 64. Low Power Oscillator (LPO) electrical specifications
10.3.2.5 SPLL electrical specifications
Table 65. SPLL electrical specifications
- FSPLL_REF is PLL reference frequency range after the PREDIV. For PREDIV and MULT settings refer SCG_SPLLCFG
register of Reference Manual.
- FSPLL_Input is PLL input frequency range before the PREDIV must be limited to the range 8 MHz to 40 MHz. This input
mode. For external clock source settings refer SCG_SOSCCFG register of Reference Manual.
- This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each
- The behavior of the accumulated PLL jitter saturates over 1us.
- Lock detector detection time is defined as the time between PLL enablement and clock availability for system use.
10.3.3 Memory and memory interfaces
10.3.3.1 Flash memory module (FTFC/FTFM) electrical specifications
This section describes the electrical characteristics of the flash memory module.
10.3.3.1.1 Flash timing specifications — commands
Table 66. Flash command timing specifications for S32M242 series
128 KB flash — —
256 KB flash — 2
512 KB flash — —
2 KB flash — 75 µs
4 KB flash — 100
32 KB flash — — ms 2
64 KB flash 30 550
256 KB flash 250 2125
Table continues on the next page...
Table 66. Flash command timing specifications for S32M242 series (continued)
- All command times assumes 25 MHz or greater flash clock frequency (for synchronization time between internal/
- Maximum times for erase parameters based on expectations at cycling end-of-life.
- For all EEPROM Emulation terms, the specified timing shown assumes previous record cleanup has occurred. This may
- 1st time EERAM writes after a Reset or SETRAM may incur additional overhead for EEE cleanup, resulting in up to 2× the
- Only after the Nth write completes will any data be valid. Emulated EEPROM record scheme cleanup overhead may occur
set will still be valid and the new records will be discarded.
- Quick Write times may take up to 550 µs, as additional cleanup may occur when crossing sector boundaries.
- Time for emulated EEPROM record scheme overhead cleanup. Automatically done after last (Nth) write completes, assuming
still powered. Or via SETRAM cleanup execution command is requested at a later point. Table 67. Flash command timing specifications for S32M244 series
256 KB flash — —
2 KB flash — 200 µs
4 KB flash — 220
64 KB flash 100 1000 ms 2
512 KB flash 700 8000
1 KB flash 7 — ms
Table continues on the next page...
Table 67. Flash command timing specifications for S32M244 series (continued)
- All command times assume 20 MHz flash clock frequency.
- Maximum times for erase parameters based on expectations at cycling end-of-life.
- For all EEPROM Emulation terms, the specified timing shown assumes previous record cleanup has occurred (tquickwrClnup).
- 1st time FlexRAM writes after a Reset or SETRAM may incur additional overhead for emulated EEPROM cleanup, resulting
in up to 2× the times shown.
- Only after the Nth write completes will any data be valid. Emulated EEPROM record scheme cleanup overhead may occur
set will still be valid and the new records will be discarded.
- Quick Write times may take up to 1200 µs, as additional cleanup may occur when crossing sector boundaries.
- Time for emulated EEPROM record scheme overhead cleanup. Automatically done after last (Nth) write completes, assuming
still powered. Or via SETRAM cleanup execution if command is requested at a later point.
10.3.3.1.2 Reliability specifications
Table 68. NVM reliability specifications
- EEPROM backup to FlexRAM ratio = 16
- EEPROM backup to FlexRAM ratio = 256 100 K 1.6 M writes writes 5 6 7 1. Data retention period per block begins upon initial user factory programming or after each subsequent erase. 2. Program and Erase for PFlash and DFlash are supported across product temperature specification. 3. Cycling endurance is per DFlash or PFlash Sector. 4. Background maintenance operations during normal FlexRAM usage extend effective data retention life beyond 5 years. 5. FlexMemory write endurance specified for 32-bit writes to FlexRAM and is supported across product temperature specification. Greater write endurance may be achieved with larger ratios of EEPROM backup to FlexRAM. 6. For usage of any emulated EEPROM driver other than the FlexMemory feature, the endurance spec will fall back to the specified endurance value of the DFlash specification (1K). 7. FlexMemory calculator tool is available at NXP web site for help in estimation of the maximum write endurance achievable at specific EEPROM/FlexRAM ratios. The "In Spec" portions of the online calculator refer to the NVM reliability specifications section of data sheet. This calculator only applies to the FlexMemory feature.
10.3.4 Analog modules
10.3.4.1 ADC electrical specifications
All the data mention in this table is only validated in a simulation and granted by NXP design team.
Table 69. 12-bit ADC operating conditions
0 See voltage and current
Table continues on the next page...
Table 69. 12-bit ADC operating conditions (continued)
- Typical values assume VDDA = 5 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF unless otherwise stated. Typical values are for reference only, and
are not tested in production.
- For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSS. To get maximum performance,
reference supply quality should be better than SAR ADC. See application note AN5032 for details.
- Clock and compare cycle need to be set according to the guidelines mentioned in the
- ADC conversion will become less reliable above maximum frequency.
- When using ADC hardware averaging, see the
Reference Manual to determine the most appropriate setting for AVGS.
- Numbers based on the minimum sampling time of 275 ns.
- For guidelines and examples of conversion rate calculation, see the
- Configuration used during the test to obtain this value is:
- VDD=VDDA=VREFH=2.5 V, 2.7 V, 3 V ,5.5 V, (externally forced)
- BUS CLK=48 MHz, ADC CLK=48MHz (FIRC Used), Calibration CLK=24MHz, Sample Time =14 Cyc, Averaging=32
- Resolution= 12 bit
- Conversion Mode: Continuous Conversion
- Channel: ADC0_SE1
- Temperatures: -40C, 25C, 135C NXP Semiconductors S32M24x MCU electrical specifications S32M2xx Data Sheet, Rev. 3, 10/2023 Data Sheet: Advance Information Preliminary Information 99 / 135
Figure 25. ADC input impedance equivalency diagram
- ADC performance specifications are documented using a single ADC. For parallel/simultaneous operation of both ADCs, either for sampling the same channel by both ADCs or for sampling different channels by each ADC, some amount of decrease in performance can be expected. Care must be taken to stagger the two ADC conversions, in particular the sample phase, to minimize the impact of simultaneous conversions.
- On reduced pin packages where ADC reference pins are shared with supply pins, ADC analog performance characteristics may be impacted. The amount of variation will be directly impacted by the external PCB layout and hence care must be taken with PCB routing. See AN5426 for details
- All accuracy numbers assume the ADC is calibrated with VREFH=VDDA=VDD, with the calibration frequency set to less than or equal to half of the maximum specified ADC clock frequency. NOTE
Table 70. 12-bit ADC characteristics (2.7 V to 3 V) (VREFH = VDDA, VREFL = VSS) 1
- This table is not applicable to S32M244.
- Typical values assume VDDA = 3 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF.
- The ADC supply current depends on the ADC conversion rate.
- Represents total static error, which includes offset and full scale error.
- 1 LSB = (VREFH - VREFL)/2N
- The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device
- For ADC signals adjacent to VDD/VSS or XTAL/EXTAL or high frequency switching pins, some degradation in the ADC
performance may be observed.
- All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the
internal analog parameters, assume minor degradation.
- All the parameters in the table are given assuming system clock as the clocking source for ADC.
Table 71. 12-bit ADC characteristics (3 V to 5.5 V)(VREFH = VDDA, VREFL = VSS)
- Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF unless otherwise stated.
- The ADC supply current depends on the ADC conversion rate.
- Represents total static error, which includes offset and full scale error.
- 1 LSB = (VREFH - VREFL)/2N
- The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device
- For ADC signals adjacent to VDD/VSS or XTAL/EXTAL or high frequency switching pins, some degradation in the ADC
performance may be observed.
- All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the
internal analog parameters, assume minor degradation.
- All the parameters in the table are given assuming system clock as the clocking source for ADC.
- Due to triple bonding in lower pin packages like 64-LQFP degradation might be seen in ADC parameters. NOTE
Table 72. Pin mapping Table continues on the next page...
Table 72. Pin mapping (continued)
10.3.4.2 CMP with 8-bit DAC electrical specifications
Table 73. Comparator with 8-bit DAC electrical specifications for S32M242 series Table continues on the next page...
Table 73. Comparator with 8-bit DAC electrical specifications for S32M242 series (continued)
- Difference at input > 200mV
- Applied ± (100 mV + VHYST0/1/2/3+ max. of VAIO) around switch point.
- Applied ± (30 mV + 2 × VHYST0/1/2/3+ max. of VAIO) around switch point.
- Calculation method used: Linear Regression Least Square Method
Table 74. Comparator with 8-bit DAC electrical specifications for S32M244 series Table continues on the next page...
Table 74. Comparator with 8-bit DAC electrical specifications for S32M244 series (continued) Table continues on the next page...
- Difference at input > 200mV
- Applied ± (100 mV + VHYST0/1/2/3+ max. of VAIO) around switch point.
- Applied ± (30 mV + 2 × VHYST0/1/2/3+ max. of VAIO) around switch point.
- Calculation method used: Linear Regression Least Square Method
50 K pull up/down is recommended). Figure 26. Typical hysteresis vs. VAIN (VDDA = 3.3 V, PMODE = 0)
Figure 29. Typical hysteresis vs. VAIN (VDDA = 5 V, PMODE = 1)
10.3.5 Communication modules
10.3.5.1 LPUART electrical specifications
Refer to General AC specifications for LPUART specifications. Baud rate = Baud clock / ((OSR+1) * SBR). For details, see LPUART chapter of the Reference Manual.
10.3.5.2 LPSPI electrical specifications
of the transfer attributes are programmable. The following tables provide timing characteristics for classic LPSPI timing modes.
- All timing is shown with respect to 20% VDD and 80% VDD thresholds.
- All measurements are with maximum output load of 50 pF, input transition of 1 ns and pad configured with fastest slew setting (DSE = 1). NXP Semiconductors S32M24x MCU electrical specifications S32M2xx Data Sheet, Rev. 3, 10/2023 Data Sheet: Advance Information Preliminary Information 108 / 135
Table 75. LPSPI electrical specifications1 Table continues on the next page...
Table 75. LPSPI electrical specifications1 (continued) Table continues on the next page...
Table continues on the next page...
- Trace length should not exceed 11 inches for SCK pad when used in Master loopback mode.
- While transitioning from HSRUN mode to RUN mode, LPSPI output clock should not be more than 14 MHz.
- fperiph = LPSPI peripheral clock
- Master Loopback mode - In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting LPSPI_CFGR1[SAMPLE] bit as 1. Clock
pads used are PTD15 and PTE0. Applicable only for LPSPI0.
- Master Loopback (slow) - In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting LPSPI_CFGR1[SAMPLE] bit as 1. Clock
pad used is PTB2. Applicable only for LPSPI0.
- Set the PCSSCK configuration bit as 0, for a minimum of 1 delay cycle of LPSPI baud rate clock, where PCSSCK ranges from 0 to 255.
- Set the SCKPCS configuration bit as 0, for a minimum of 1 delay cycle of LPSPI baud rate clock, where SCKPCS ranges from 0 to 255.
- While selecting odd dividers, ensure Duty Cycle is meeting this parameter.
1.The bus is driven but may not be equal to the valid serial data being sent. Figure 32. LPSPI slave mode timing (CPHA = 0) Figure 33. LPSPI slave mode timing (CPHA = 1)
10.3.5.3 LPI2C electrical specifications
See General AC specifications for LPI2C specifications. For supported baud rate see section 'Chip-specific LPI2C information' of the Reference Manual.
10.3.5.4 FlexCAN electical specifications
For supported baud rate, see section 'Protocol timing' of the Reference Manual.
10.3.5.5 Clockout frequency
Maximum supported clock out frequency for this device is 20 MHz
10.3.6 Debug modules
10.3.6.1 SWD electrical specofications
S32M24x MCU electrical specifications S32M2xx Data Sheet, Rev. 3, 10/2023 Data Sheet: Advance Information Preliminary Information 115 / 135
Table 76. SWD electrical specifications
5.0 V IO
3.3 V IO
Figure 34. Serial wire clock input timing Figure 35. Serial wire data timing
10.3.6.2 JTAG electrical specifications
Table 77. JTAG electrical specifications
Figure 38. Test Access Port timing
10.4 Thermal attributes
10.4.1 General notes for specifications at maximum junction temperature
- TA = ambient temperature for the package (°C)
- RθJA = junction to ambient thermal resistance (°C/W)
- PD = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on a board with internal plane (2s2p) is usually appropriate if the board has low power dissipation and the components are well separated. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using this equation: TJ = TT + (ΨJT × PD) where:
- TT = thermocouple temperature on top of the package (°C)
- ΨJT = thermal characterization parameter (°C/W)
- PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the NXP Semiconductors S32M24x MCU electrical specifications S32M2xx Data Sheet, Rev. 3, 10/2023 Data Sheet: Advance Information Preliminary Information 120 / 135
11 Thermal Characteristics
Table 78. Thermal characteristics
- Thermal test board meets JEDEC specification for this package (JESD51-7).
- Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is
meant to predict the performance of a package in an application-specific environment. The S32M is offered in the following package types. Table 79. Packaging number or see below figures.
Figure 39. Package outline 1 of 3
Figure 40. Package outline 2 of 3
Figure 41. Package outline 3 of 3
Figure 42. PCB design guidelines - solder mask opening pattern
Figure 43. PCB design guidelines - I/O pads and solderable area
Figure 44. PCB design guidelines - solder paste stencil
Figure 45. Package drawing notes
The following table lists the changes in this document. Rev 3, Oct 2023
- Updated S32M27x block diagram.
- Updated ordering information.
- In section "Absolute maximum ratings", updated footnote "For S32M24x devices, VDD_AE10, VDD...".
- In section "Thermal operating characteristics" deleted storage temperature range.
- In section "PMC Electrical Specifications": — Limits and condition updated for V_VDD_5Vmode, VDD_REG_DYN, and VDDC. — Condition updated for V_VDD_3Vmode, IVDD_LD_FP, and IVDD_LD_LP.
- In section "Voltage Monitors in Application Extension PMC" updated VDD_OV1 max to 5.55V and VDDC_UV max to 4.9V.
- In section "Application Extension IO DC electrical specifications", updated max IO_VDDE_IOCD from 100 to 175 mA
- In section "42 MHz RC Oscillator electrical specifications" updated fosc.
- In section "CANPHY Electrical Specifications" added tbit(bus) and delta-trec parameters.
- Updated "DPGA Electrical Specifications".
- In section "Temperature Monitor Electrical Specifications" — added TTSENSE_* parameters for different temperature ranges and updated TOT_1. — updated TTSENS_acc_offset limit to +/-2 C and added clarification about different instances of temp monitor "There are two temperature sensors, one instance located in vicinity of...".
- Added section "Supply Diagnosis".
- In section "LPSPI" updated specification and diagrams to represent voltage measurment at 50% and updated symbol for "Data hold time (inputs)" from tHO to tHI.
- In section "DPGA Electrical Specifications" clarified VIN in the footnote.
- In section "GDU", clarified VIN and updated respective footnotes.
- In comparator sections of both S32M24x and S32M27x, changed VIN level to corresponding parameter, VAIN.
- In section LPUART section of S32M24x, reffered to LPUART chapter.
- Added package drawings. Rev 3 DraftA, May 2023
- In "Block diagram" added introduction to explain the diagram.
- In feature comparison changed "Flash with ECC protection" to "Program flash memory" and "Data flash" to "Flash memory".
- Updated Ordering information to remove TBDs.
- In section "Absolute maximum ratings", Table continues on the next page... NXP Semiconductors
Revision history
S32M2xx Data Sheet, Rev. 3, 10/2023 Data Sheet: Advance Information Preliminary Information 129 / 135
Rev 3 DraftA, May 2023 — changed the description of VHSx and VLSx from 1us to 100ns. — updated footnote attached to VHGx and VLGx.
- In section "Application Extension IO DC electrical specifications" changed CJTAG to AMPOUT and updated IO_VDDE_IOCD from 100 to 175 mA.
- In section "High Voltage Module (HVM)": — updated HVM_AIM limit from +/-4 to +/-5% for ratio 2, 7, 11, 16 as mentioned in the condition which is also updated (was 40°C <= Tj<=125°C) — updated HVM_AIM condition from 125°C < Tj to Ratio 1. — updated VM_LBI1H, VM_LBI2H and VM_LBI3H from 0.6 to 0.8V — updated VM_HBI1H and VM_HBI2H from 1 to 1.35V. — updated VM_HBI2A min from 24 to 23.5 V.
- In section "CANPHY Electrical Specifications", tdom,TXD symbol updated to tCPTXDDT.
- In section "GDU Electrical Specifications", is updated thouroghly.
- In section "Temperature Monitor Electrical Specifications" mentioned it is AE on-die temperature sensor.
- In section "SAR ADC" updated leading sentence and added footnote to TUE with condition "without adjacent pincurrent injection".
- In section "SAR ADC" updated figure "SAR ADC Input Circuit" to update ADC supply from VREFH to VDD_HV_A.
- In section "Low Power Comparator (LPCMP)": — updated description of tDDAC from "DAC Initializationand switchingsettling time" to "DAC Initialization time" — updated footnote attached to TDHSS. — changed ACMP0 to LPCMP0.
- In section "Temperature Sensor" mentioned it is MCU on -die temperature sensor.
- In section "Fast External Oscillator (FXOSC)", — added Oscillator Analog circuit supply current for ALC disabled and added specifications related to Input clock low/high level in bypass mode. — removed a note "To improve the FXOSC jitter & duty...".
- In section "PLL" added sentence "Jitter values specified in this table are applicable for FXOSC reference clock input only" and updated footnote to cyclic jitter specification to mention "Accumulated jitter specification is not valid with SSCG".
- Updated "Thermal attributes" section thoroughly. Rev 2.1, Jan 2023
- Updated S32M27x block diagram. NXP Semiconductors
S32M2xx Data Sheet, Rev. 3, 10/2023 Data Sheet: Advance Information Preliminary Information 130 / 135
Rev 2, Jan 2023
- Updated block diagrams and feature comparison.
- Added "ordering information".
- In section “Voltage and current operating requirements”, changed Vramp_fast from 32 to 100V/ms.
- In section "ESD and Latch-up Protection Characteristics", added new footnote and added it to VHBM (CANH and CANL pins). Also attached footnote 3 to VHBM (LIN and HVI0 pins).
- In table "IDD modes" removed VLPR mode column and PDB row and updated FlexTimer to PWM (FTM/eMIOS).
- In section "PMC Electrical Specifications", for CVLS, CVDD and CVDDC added typical value as 2.2 or 4.7 uF and removed LIN specifications.
- Updated section name from "High Voltage Input" to "High Voltage Module (HVM) electrical specifications".
- In section "Application Extension IO DC electrical specifications", updated supply names and added specification "IO_RESET_NOT_FILTERED_PULSE".
- In section "High Voltage Input", updated symbols HVM_AIM and deleted HVM_VTHT33.
- In section "CANPHY Electrical Specifications", — deleted I(VSUP)_CANPHY_wakeup, "tdom,bus" and VO(diff)_dom with RL=50 to 60 ohm. — Updated min from 1.4 to 1.5 V and max from 3.3 to 3 V for VO(diff)_dom with condition RL=45 to 70 ohm. — Updated min from -50 to -500 mV for VO(diff)_rec (Normal mode). — For "|IO(sc)|", updated condition.
- In "LINPHY Electrical Specifications" deleted ΔIVSUP_LIN_wup".
- Updated symbols, conditions and footnotes in "GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)" and "GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)" sections.
- In section "Fast External Oscillator (FXOSC)" added EXTAL_SWING_PP and VSB specifications. Rev 1, Aug 2022
- Initial release. NXP Semiconductors
S32M2xx Data Sheet, Rev. 3, 10/2023 Data Sheet: Advance Information Preliminary Information 131 / 135
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Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2023. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10/2023 Document identifier: S32M2xx