Power Management

S32K376

NXP Semiconductors

This document provides electrical specifications for S32K396. For functional characteristics and the programming model, see S32K396 Reference Manual. Rev. 3 - 03/2024

Manufacturer: NXP Semiconductors

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PDF pages: 119

Technical content

Datasheet sections

1 S32K396 product series
2 Block diagrams
3 Features
3.1 Feature comparison
3.2 Feature summary
4 Ordering information
5 General
5.1 Absolute maximum ratings
5.2.1 Supported voltage supply use-cases
5.3 Thermal operating characteristics
5.4 ESD and Latch-up Protection Characteristics
6 Power management
6.1 Supply Monitoring
6.2 Recommended Decoupling Capacitors
6.3 V15 regulator (SMPS option) electrical
6.4 V11 regulator (NMOS ballast transistor control)
6.5 Supply currents
6.6 Operating mode
6.7 Cyclic wake-up current
7 I/O parameters
8 Real-time control
8.4 LCU
8.5 LCU skew characteristics
9 Glitch Filter
10 LVDS specifications
10.3 LVDS 5V Transmitter Electrical Specifications
12 Flash memory specification
12.1 Flash memory program and erase
12.2 Flash memory Array Integrity and Margin Read
12.3 Flash memory module life specifications
12.3.1 Data retention vs program/erase cycles
12.4 Flash memory AC timing specifications
12.5 Flash memory read timing parameters
13 Analog modules
13.1 SAR_ADC
13.2 Sigma Delta Analog to Digital Converter
13.3 Low Power Comparator (LPCMP)
13.4 Sine wave generator
13.5 Supply Diagnosis
13.6 Temperature Sensor
14 Clocking modules
14.1 Fast External Oscillator (FXOSC)
14.2 FIRC
14.3 SIRC
14.4 PLL
15 Communication interfaces
15.1 LPSPI
15.1.1 LPSPI
15.1.3 LPSPI Pad Type
15.2 MDIO timing specifications
15.3 Ethernet MII (10/100 Mbps)
15.4 Ethernet MII (200 Mbps)
15.5 Ethernet RMII (10/100 Mbps)
15.6 I2C
15.7 FlexCAN characteristics
15.8 LPUART characteristics
15.9 SPI
15.10 Microsecond channel (MSC)
15.11 Zipwire
15.12 LFAST PLL
16 Memory interfaces
16.3 QuadSPI configurations
17 Debug modules
17.1 Debug trace timing specifications
17.2 JTAG electrical specifications
17.3 SWD electrical specifications
18 Thermal Attributes
18.1 Description
18.2 Thermal Characteristics
19 Dimensions
19.1 Obtaining package dimensions
20 Revision history

This document provides electrical specifications for S32K396. For functional characteristics and the programming model, see S32K396 Reference Manual. S32K396 S32K39 and S32K37 Data Sheet Supports S32K396, S32K394, S32K376 and S32K374. Rev. 3 — 03/2024 Data Sheet: Technical Data NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

1 S32K396 product series

The Cortex-M7 core at a higher frequency.
Advanced motor control coprocessors.
An extended analog, including a high-resolution PWM. S32K396 is developed to meet the next generation SiC traction inverter requirements and to enable high efficiency, low latency, and system-level BOM cost savings. Because of its versatile architecture, S32K396 is also well suited to address a wide range of xEV applications. This document represents S32K396 which is the superset device of the S32K39 and S32K37 family. The S32K39x MCUs extend the high-performance capabilities of S32K37x with two programmable motor control coprocessors. The last digit denotes the size of Flash memory size. See the Feature comparison for a detailed overview of the differences between variants. When the S32K396 is referenced in the RM it means the conditions, configurations or features are valid for all the variants of the device. S32K396 can also be used in combination with powerful 16 nm NXP MCUs or MPUs (S32Z2 and S3E2), in these ways:
As a companion die: connected locally (same ECU) to S32Z2 and S3E2 through the Zipwire interface to extend 5V I/O and analog capabilities
As a smart actuator: connected remotely via Ethernet or FlexCAN

2 Block diagrams

Figure 1. S32K39x (x=4 or 6)

A Figure 2. S32K37x (x=4 or 6)

3 Features

3.1 Feature comparison

The following table compares some of the prominent features of the S32K396 product series. Table 1. Feature comparison

20541 Mixed ASIL

Table continues on the next page...

Features

S32K39 and S32K37 Data Sheet, Rev. 3, 03/2024 Data Sheet: Technical Data 5 / 119

Table 1. Feature comparison (continued) Table continues on the next page... S32K39 and S32K37 Data Sheet, Rev. 3, 03/2024 Data Sheet: Technical Data 6 / 119

176 LQFP-

Cortex-M7 core DMIPS/MHz 2.14-3.23.
This feature is available for 289 MAPBGA.
You can increase the number of channels by using FlexIO emulation.
LVDS and single-ended in 289 MAPBGA; single-ended only in 176 LQFP-EP.

3.2 Feature summary

The following table provides a list of Cortex-M7 core features that the S32K396 product family supports. Table 2. Feature summary

Arm core based on the Armv7 architecture and ThumbR-2 ISA
16 KB data and 16 KB I-cache for optimizing wait state execution from memories
96 KB TCM associated with each core
On-core MPU for dynamic task protection (16 regions)
IEEE 754-compliant SPFPU
Harvard bus architecture implementing dedicated instruction and data path
5-stage pipeline with branch speculation
XRDC integrated with a crossbar switch to provide memory and peripheral protection
DSP and SIMD extension
I/O protection (VIRT_WRAPPER)
embedded trace macrocell (ETM) supporting instruction trace
Arm third-party ecosystem support: software and tools to help minimize development time and cost DSP and coprocessors • CoolFlux DSP16L with: — A frequency of 160 MHz — One core and four threads — 32 KB Instruction RAM and 24 KB Data RAM
Two coprocessor cores at a frequency of 320 MHz each that help with: — Software running independently of the Cortex-M7 CPUs — 32 KB code RAM and 8 KB data RAM Table continues on the next page... NXP Semiconductors

S32K39 and S32K37 Data Sheet, Rev. 3, 03/2024 Data Sheet: Technical Data 7 / 119

Table 2. Feature summary (continued)

Extra safety features such as ECC, watchdog, latency monitor, and idle counter DMA • 2 x 64-channel DMAMUX per eDMA
2 x 32-channel eDMAs (1 eDMA implemented as a lock-step pair)
Complex data transfers performed with minimal intervention from a host processor
Programmable support for scatter-gather DMA processing System and power management • Support for simplified power modes (Run and Standby)
Support for clock gating of unused modules; specific peripherals continue to work in low-power modes
Support for an external ballast transistor to generate core supply
Fully independent CPU and peripheral clocking scheme
Rapid start-up from a 48 MHz FIRC
Low-power oscillator such as the 32 kHz SIRC
PMC with LVD and selectable trip points
Support for multiple power modes
NMI Memory and memory interfaces • Up to 6 MB program flash memory with an ECC
Up to 128 KB data flash memory with an ECC
Up to 800 KB SRAM with an ECC
8-bit QuadSPI
120 MHz DTR Clocks • External 8–40 MHz crystal oscillator or resonator
Internal clock references: — 48 MHz FIRC ± 5% — 32 kHz SIRC ± 10%
Up to 640 MHz PLL for divided system clock operation Security and integrity • HSE_B: Upgradable firmware that NXP delivers and you can program
Security ciphers: — Symmetric: AES with 128, 192, or 256 bits — Cipher modes: ECB, CBC, cipher-based message authentication code (CMAC), GMAC, Counter-Based Block Cipher mode Table continues on the next page... NXP Semiconductors

S32K39 and S32K37 Data Sheet, Rev. 3, 03/2024 Data Sheet: Technical Data 8 / 119

Security use cases supported: — OTA update — Secure boot — Secure communication — Component protection — Secure storage — Key exchange Safety ISO26262 • Classification up to ASIL D
ERM and EIM support
Watchdog timers with an independent clock source
Voltage monitors
Bandgap voltage available as ADC input
External clock source monitoring using an independent reference
PLL lock and loss-of-lock protection
XRDC
Access control, memory protection, and peripheral isolation
ECC on code flash memory, data flash memory, and system RAM
ADC self-test feature
Internal analog monitoring of all supplies available
CRC generation module
FCCU failure output Analog • 12-bit ADC: — Up to 69 external analog inputs — 1 μs conversion time — Internal bandgap voltage reference channel, supporting automatic compare and an optional hardware trigger Table continues on the next page... NXP Semiconductors

S32K39 and S32K37 Data Sheet, Rev. 3, 03/2024 Data Sheet: Technical Data 9 / 119

SDADC: — Integrated digital filtering (CoolFlux DSP)
SGEN (Sine Wave Generator) — Input clock frequency range: 12 MHz–20 MHz — Output sinusoidal signal frequency range: 1 kHz–50 kHz
LPCMP with an internal 8-bit DAC as a reference: — LPCMP with both positive and negative inputs, with separately selectable interrupts on rising and falling comparator outputs — Ability to cross-trigger the timers from both the ADC and LPCMP outputs
Temperature sensor (TempSense) with an output that ADC measures I/O timers • eFlexPWM with NanoEdge (high-resolution PWM): — 16 bits (+5 with NanoEdge) of resolution for center-aligned, edge- aligned, and asymmetrical PWMs — Support for double switching PWM outputs — Fault inputs that can be assigned to control multiple PWM outputs — Independent top and bottom hardware deadtime insertion — Multiple output trigger events that can be generated per PWM cycle via hardware
24-bit eMIOS timer, offering up to 24 standard channels: — Input Capture, Output Compare, and PWM modes — Fault input support with global fault control — Multiple features such as deadtime insertion, configurable polarity, quadrature decoding, and so on
Motor control and power conversion using a combination of eTPU, eFlexPWM, eMIOS, LCU, BCTU, and SWG
3 x STMs, with four channels each
32-bit RTC
3 x 32-bit PITs, with four channels for raising interrupts and triggering DMA channels Communications • LPSPI supporting DMA with full-duplex or single-wire bidirectional communication in Master or Slave mode Table continues on the next page... NXP Semiconductors

S32K39 and S32K37 Data Sheet, Rev. 3, 03/2024 Data Sheet: Technical Data 10 / 119

LPI2C modules with: — DMA support — Low-power availability — Master or slave support — System management bus
FlexIO, with an option to configure as different communication peripherals, offering support for SENT
LPUART with DMA support, having: — An optional 13-bit break — Full-duplex NRZ — LIN 2.1 extension support — Low-power availability
FlexCAN modules with ISOCAN-FD and DMA support
EMAC complex (10/100 Ethernet) that supports 1588 timers, MII/RMII interface, and AVB and TSN support
Microsecond channel (MSC)
Zipwire (high-speed SIPI and LFAST) Debug • Debug watchpoint and trace (DWT), with four configurable comparators as hardware watch points
SWO-synchronous trace data support
Instrumentation trace macrocell (ITM) with software and hardware trace plus timestamping
FPB with an ability to patch code and data from code space to system space
All execution units and bus masters made traceable through TPIU over GPIO pins; a very-low-bandwidth trace option also available via the SWO
embedded trace FIFO (ETF): a dedicated trace buffer available for each of the core masters, allowing data to be captured internally before being optionally routed to external trace pins
Serial wire viewer (SWV): trace capability providing displays of: — Reads — Writes — Exceptions — PC samples — Print Table continues on the next page... NXP Semiconductors

S32K39 and S32K37 Data Sheet, Rev. 3, 03/2024 Data Sheet: Technical Data 11 / 119

Up to 144 GPIO pins with interrupt functionality
Up to 77 GPIO pins with wakeup capability
Pseudo open-drain support on LPUART, FlexIO, and LPI2C
Package options of 289 MAPBGA and 176 LQFP-EP

4 Ordering information

13th& 14thCharacter Package Suffix 12thCharacter Ambient Temperature (Ta) V= -40°C to 105°C M= -40°C to 125°C 1stCharacter Product Status for ordering and marking Pfor prototype and Sfor qualified ordering P/N Series/Family 8thCharacter Extra Feature 9thCharacter Security Product statusP/S 4thCharacter Product Line K= General Purpose MCU 5thCharacter Series / Family 3= K3 product family / arm Cortex M7 based 16thCharacter Tape & Reel T= Trays/Tubes R= Tape & Reel 10th& 11thCharacter Fab and Mask rev Tx = Global Foundry x0= 1stfab revision x1= 2ndfab revision 2nd& 3rdCharacter Product Type / Brand 32for Automotive 32Bit MCU/MPU 6thCharacter Core platform 7thCharacter Memory Size 4 6 P-Flash 4MB 6M 2-3 10-11 13-14 KU

289 JB -

S= Standard Family SW Package, including:

Real Time Driver including Autosar MCAL and Non Autosar driver package (ISO26262 compliant, crypto driver included)
Standard Security Firmware T Tape and Reel Indicator16 HSE B H No Ethernet MAC 100Mbps Ethernet MAC N E pins MAPBGALQFP-EP 176 7 = 1x M7 LS core + 2x M7 split-lock cores + DSP 9 = 1x M7 LS core + 2x M7 split-lock cores + DSP + dual eTPU

Figure 3. Ordering information

5 General

5.1 Absolute maximum ratings

as absolute maximum ratings - is not implied.

Ordering information

S32K39 and S32K37 Data Sheet, Rev. 3, 03/2024 Data Sheet: Technical Data 12 / 119

minimum values in the datasheet are across process, voltage, and temperature. Table 3. Absolute maximum ratings Table continues on the next page...

Table 3. Absolute maximum ratings (continued)

All voltages are referred to VSS unless otherwise specified.
6.0 V maximum for 10 hours over lifetime; 7.0 V maximum for 60 seconds over lifetime.
Voltage at VDD_DCDC cannot be higher than VDD_HV_A.
Absolute max rating must be honored under all conditions, including current injection.
When input pad voltage levels are close to VDD_HV_A (respectively to VDD_HV_B) or VSS, practically no current injection

is possible. See application note AN4731 for a description of injection current on NXP automotive microcontrollers.

TSTG specifies the storage temperature range. It is not the operating temperature range. Please refer to the Thermal

operating characteristics table.

5.2 Voltage and current operating requirements

degraded when voltage drops below 2.97 V. DSPI/MSC interface is supported only at VDD_HV_A = 5V. Table 4. Voltage and current operating requirements Table continues on the next page...

Table 4. Voltage and current operating requirements (continued) Table continues on the next page...

All voltages are referred to VSS unless otherwise specified.
Voltage at VDD_DCDC cannot be higher than VDD_HV_A
Min and Max values are applicable only for non-SMPS mode where V15 is sourced externally.
Must be shorted to VDD_HV_A at the PCB level
Ensure that VDD_HV_A ramps before VDD_LVDS.
SDADC is intended to be used only when VDD_HV_A is supplied with 5V. In case of VDD_HV_A is supplied with 3.3V it is
VREFH should always be equal to or less than VDD_HV_A +0.1. Any positive differential voltage between VREFH and
All the VREFH_xx except of VREFH_R2R must be shorted to single supply source at the PCB level, either isolated

voltage reference or shorted to VDD_HV_A. Isolated VREFH_R2R is required to avoid SDADC performance degradation.

Open-drain outputs must be pulled respectively to their supply rail (VDD_HV_A or VDD_HV_B).
When input pad voltage levels are close to VDD_HV_A (respectively to VDD_HV_B) or VSS, practically no current injection
The MCU supply ramp rate parameter must be applicable to the MCU input/external supplies. The ramp rate assumes that

the S32K396 Hardware design guidelines document available on http://www.nxp.comare followed. power dissipation allowed for a given package. Voltage at VDD_DCDC cannot be higher than VDD_HV_A.

5.2.1 Supported voltage supply use-cases

Table 5. Supported voltage supply use-cases

5.3 Thermal operating characteristics

Table 6. Thermal operating characteristics

5.4 ESD and Latch-up Protection Characteristics

Table 7. ESD and Latch-up Protection Characteristics

Device failure is defined as: "If after exposure to ESD pulses, the device does not meet specification requirements."
This parameter is tested in conformity with AEC-Q100-002.
All ESD testing conforms with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
This parameter is tested in conformity with AEC-Q100-011.
This parameter is tested in conformity with AEC-Q100-004.

6 Power management

6.1 Supply Monitoring

Table 8. Supply Monitoring Table continues on the next page...

Table 8. Supply Monitoring (continued)

The HVD_V15 monitor is provided to indicate if the V15 rail is far above the standard V15 operating range , to ensure

6.2 Recommended Decoupling Capacitors

Table 9. Recommended Decoupling Capacitors

Optionally, 10 nF capacitors can be added in parallel to the decoupling capacitors.
These capacitors must be placed as close as possible to the corresponding supply and ground pins. For BGA

packages, the capacitors must be placed on the other side of the PCB to minimize the trace lengths.

All capacitors must be low ESR ceramic capacitors (for example, X7R). The minimum recommendation is after

considering component aging and tolerance.

For devices where the VDD_HV_B domain is present, if the VDD_HV_B supply is different supply from VDD_HV_A, a

dedicated bulk capacitor is needed.

It is also possible to use higher capacitance values (for example, 10 μF) in place of the 4.7 μF capacitor.
These capacitors must be placed close to the source.

recommendations can be followed in addition to the capacitance requirements of the external voltage regulator.

21 V15

Figure 4. 176LQFP decoupling capacitor pinout diagram

Figure 5. 176LQFP decoupling capacitor pinout diagram (SMPS)

Figure 6. 289BGA decoupling capacitor pinout diagram

Figure 7. 289BGA decoupling capacitor pinout diagram (SMPS)

6.3 V15 regulator (SMPS option) electrical specifications

The chip hardware design guidelines document lists the recommended part numbers for PMOS, Schottky diode and inductor.

Table 10. V15 regulator (SMPS option) electrical specifications

Only needed when internal SMPS is used to generate V15 and VDD_DCDC is supplied with isolated source from

6.4 V11 regulator (NMOS ballast transistor control) electrical specifications

The chip hardware design guidelines document lists the recommended part number for NMOS. Table 11. V11 regulator (NMOS ballast transistor control) electrical specifications Table continues on the next page...

Table 11. V11 regulator (NMOS ballast transistor control) electrical specifications (continued)

6.5 Supply currents

All data in this table is preliminary and based on first samples. Table 12. STANDBY mode supply currents

See the configurations in Table 15.
IO load current is not included. The actual current requirements for IOs will depend on the I/O configuration in the
“typ” is indicative of the average current numbers at the nominal internally regulated V11 supply voltage, VDD_HV_A =

5.0V, VDD_HV_B = 5.0V, for the typical silicon process..

“max” is indicative of the maximum current numbers at the maximum internally regulated V11 supply voltage (1.16 V),

VDD_HV_A = 5.5V, VDD_HV_B = 5.5V, for the fast silicon process. All data in this table is preliminary and based on first samples. Table 13. Low speed RUN mode supply currents

24 MHz

Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation.
See the example configurations in Table 15.
IO load current is not included. The actual current requirements for IOs will depend on the I/O configuration in the
RUN IDD @ VDD_HV_A includes Flash memory read current from the V25 voltage rail.
V11 is generated by V15 using external NMOS.
“typ” is indicative of the average current numbers at the nominal internally regulated V11 supply voltage, VDD_HV_A =

5.0V, VDD_HV_B = 5.0V, V15 = 1.5V, for the typical silicon process.

“max” is indicative of the maximum current numbers at the maximum internally regulated V11 supply voltage (1.16 V),

VDD_HV_A = 5.5V, VDD_HV_B = 5.5V, V15 = 1.65V, for the fast silicon process.

For the maximum allowable RUN current in an application, the junction temperature must be kept below the maximum

specification, TJ < 150°C, to avoid self-heating. All data in this table is preliminary and based on first samples. process unless otherwise stated.

The data in this table is preliminary and based on first samples. process unless otherwise stated. Table 14. Example RUN mode configuration supply currents

Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation.
See the configurations in Table 15.
VDD_HV_A current will increase/decrease with analog modules as per the use case.
IO current is not included. The actual current requirements for IOs will depend on the I/O configuration in the application.
RUN IDD @ VDD_HV_A includes Flash memory read current from the V25 voltage rail.
V11 is generated by V15 using external NMOS.
“typ” is indicative of the average current numbers at the nominal internally regulated V11 supply voltage, VDD_HV_A =

5.0V, VDD_HV_B = 5.0V, V15 = 1.5V, for the typical silicon process.

“max” is indicative of the maximum current numbers at the maximum internally regulated V11 supply voltage (1.16 V),

VDD_HV_A = 5.5V, VDD_HV_B = 5.5V, V15 = 1.65V, for the fast silicon process.

For the maximum allowable RUN current in an application, the junction temperature must be kept below the maximum

specification, TJ < 150°C, to avoid self-heating.

6.6 Operating mode

Table 15. STANDBY and low speed RUN configuration options Table continues on the next page...

Table 15. STANDBY and low speed RUN configuration options (continued)

See clocking use case examples in the Clocking chapter of the S32K396 Reference Manual.

Table 16. RUN mode configuration options Table continues on the next page...

Table 16. RUN mode configuration options (continued)

289 MAPBGA Yes

HSE: After start-up, the HSE core is in WFI.
eFLEXPWM channels assumed evenly split between 2 instances
eMIOS0: 6 channels in PWM mode @ 20 KHz.
SAR and SD-ADC represents number of active instances.

6.7 Cyclic wake-up current

The supply current is obtained through the measurements of the current during the corresponding operating mode.
The duration is defined by the application (how much time will the device spend in the according operating mode).
The ratio of duration is obtained by dividing the duration of the corresponding operating mode by the total duration of the
The current according to ratio is obtained by multiplying the supply current and the ratio of duration related to the proper
The average current is calculated by the addition of each device operating mode’s current according to ratio.

7 I/O parameters

and the number of Analog functions (CMP and ADC channels) multiplexed per pin. Count" is shown in the Condition column of the following table.

Table 17. GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V) Table continues on the next page...

Table 17. GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V) (continued) Table continues on the next page...

Maximum length of RESET pulse will be filtered by an internal filter on this pin.
Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter.

A positive value is leakage flowing into pin with pin at VDD_HV_A/B (the GPIO supply level); a negative value is leakage

flowing out the pin with the pin at ground.

Hysteresis spec does not apply to fast pad
GPIO output transition time information can be obtained from the device IBIS model. IBIS models are recommended for

connected to an actual transmission line load.

I/O output current specifications are valid for the given reference load figure, and the constraints given in the Operating

Conditions of this document.

I/O timing specifications are valid for the un-terminated 50ohm transmission line reference load given in the figure below.

resistance in the transmission line should be matched closely to the selected output resistance (ROUT_*) of the I/O pad.

To determine total switching current on any I/O supply, current values per output pin should not be incrementally summed.
See IBIS models for further details.

Figure 8. Reference Load Diagram and the number of Analog functions (CMP and ADC channels) multiplexed per pin. Count" is shown in the Condition column of the following table. Table 18. GPIO DC electrical specifications, 5.0V (4.5V - 5.5V) Table continues on the next page...

Table 18. GPIO DC electrical specifications, 5.0V (4.5V - 5.5V) (continued) Table continues on the next page...

Table continues on the next page...

Maximum length of RESET pulse will be filtered by an internal filter on this pin.
Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter.
A positive value is leakage flowing into pin with pin at VDD_HV_A/B (the GPIO supply level); a negative value is leakage

flowing out the pin with the pin at ground.

Hysteresis spec does not apply to fast pad
GPIO output transition time information can be obtained from the device IBIS model. IBIS models are recommended for

connected to an actual transmission line load.

I/O output current specifications are valid for the given reference load figure, and the constraints given in the Operating

Conditions of this document.

I/O timing specifications are valid for the un-terminated 50ohm transmission line reference load given in the figure below.

A lumped 8pF load is assumed in addition to a 5 inch microstrip trace on standard FR4 with approximately 3.3pF/inch.. resistance (ROUT_*) of the I/O pad.

To determine total switching current on any I/O supply, current values per output pin should not be incrementally summed.

See IBIS models for further details.

Figure 9. Reference Load Diagram Table 19. 3.3V (2.97V - 3.63V) GPIO Output AC Specification Table continues on the next page...

Table 19. 3.3V (2.97V - 3.63V) GPIO Output AC Specification (continued)

I/O timing specifications are valid for the un-terminated 50ohm transmission line reference load given in the figure below.
GPIO rise/fall time specifications are derived from simulation model for the defined operating points (between 20% and

microcontroller models and application PCB.

GPIO output transistion time information can be obtained from the device IBIS model. IBIS models are recommended for

connected to an actual transmission line load.

Output timing valid for maximum external load C L = 50pF (includes PCB trace, package trace, and external device input

See IBIS models for further details.

Figure 10. Reference Load Diagram Table 20. 5.0V (4.5V - 5.5V) GPIO Output AC Specification Table continues on the next page...

Table 20. 5.0V (4.5V - 5.5V) GPIO Output AC Specification (continued)

I/O timing specifications are valid for the un-terminated 50ohm transmission line reference load given in the figure below.

output resistance (ROUT_*) of the I/O pad.

GPIO output transistion time information can be obtained from the device IBIS model. IBIS models are recommended for

connected to an actual transmission line load.

GPIO rise/fall time specifications are derived from simulation model for the defined operating points (between 20% and

microcontroller models and application PCB.

Output timing valid for maximum external load C L = 50pF (includes PCB trace, package trace, and external device input

See IBIS models for further details.

Figure 11. Reference Load Diagram

8 Real-time control

Table 21. eTPU timing

tPER_CLK is the period of the peripheral clock (PER_CLK) on the device.
Value in the table represent the minimum pulse which is the module capable to process. When the input signal is going

Figure 12. eTPU timing

Table 22. eTPU skew characteristics

etpu_A channels only PTC8/PTC29 , PTA7/PTC30 , PTA6/PTC31 , PTD20/PTB16, PTB15/PTB14 , PTD21/PTB13 , PTD3/
etpu_A channels only Group1 (PTC8/PTC29, PTA7/PTC30, PTA6/PTC31), Group2(PTD20/PTB16, PTB15/PTB14,

Table 23. eMIOS

tPER_CLK is the period of the peripheral clock (PER_CLK) on the device.
Value in the table represent the minimum pulse which is the module capable to process. When the input signal is going
Actual output pulse may be larger when considering a slow transitioning output.

Figure 13. EMIOS Timing

8.4 LCU

Table 24. LCU

tPER_CLK is the period of the peripheral clock (PER_CLK) on the device.
Value in the table represent the minimum pulse which is the module capable to process. When the input signal is going
Actual output pulse may be larger when considering a slow transitioning output.

Figure 14. LCU timing

8.5 LCU skew characteristics

Table 25. LCU skew characteristics

Pairs (For LCU_0 (PTD20/PTB16, PTB15/PTB14, PTD21/PTB13)), For LCU_1 (PTC28/PTC9 , PTC8 /PTC29, PTA7/
LCU_0 group:(PTD20/PTB16, PTB15/PTB14, PTD21/PTB13), LCU_1 group: (PTC28 /PTC9 , PTC8/ PTC29, PTA7/

9 Glitch Filter

Table 26. Glitch Filter

Pulses shorter than defined by the maximum value are guaranteed to be filtered (not passed).
An input signal pulse is defined by the duration between the input signal's crossing of a Vil/Vih threshold voltage level, and

the next crossing of the opposite level.

Pulses in between the max filtered and min unfiltered may or may not be passed through.
Pulses larger than defined by the minimum value are guaranteed to not be filtered (passed).

10 LVDS specifications

These specifications are related to LVDS pads dedicated to Zipwire. Table 27. LVDS 3.3V Receiver Electrical Specifications Table continues on the next page...

Table 27. LVDS 3.3V Receiver Electrical Specifications (continued) These specifications are related to LVDS pads dedicated to Zipwire. Table 28. LVDS 3.3V Transmitter Electrical Specifications

10.3 LVDS 5V Transmitter Electrical Specifications

These specifications are related to LVDS pads dedicated to MSC. Table 29. LVDS 5V Transmitter Electrical Specifications Table 30. eFlexPWM

Table 31. eFlexPWM skew characteristics

Pairs(For PWM_0:( PTD4/PTD22, PTD2/PTD3 , PTA3/PTD23, PTD24/PTA2 ), For PWM_1:(PTC9/PTC28, PTC29/PTC8,
PWM_0 group:( PTD4/PTD22, PTD2/PTD3 , PTA3/PTD23, PTD24/PTA2 ), For PWM_1 group: (PTC9/PTC28, PTC29/

12 Flash memory specification

12.1 Flash memory program and erase specifications

Table 32. Flash memory program and erase specifications

Program times are actual hardware programming times and do not include software overhead. Sector program times

assume quad-page programming.

Typical program and erase times represent the median performance and assume nominal supply values and operation at

25 °C. Typical program and erase times may be used for throughput calculations.

Conditions: ≤ 25 cycles, nominal voltage.

Plant Programing times provide guidance for timeout limits used in the factory.
Typical End of Life program and erase times represent the median performance and assume nominal supply values.

Typical End of Life program and erase values may be used for throughput calculations.

Conditions: -40°C ≤TJ ≤150°C, full spec voltage.

12.2 Flash memory Array Integrity and Margin Read specifications

Table 33. Flash memory Array Integrity and Margin Read specifications

Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The

read setup that requires 6 clocks to read Nread would equal 6.

Array Integrity times are actual hardware execution times and do not include software overhead or system code execution
The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the

equation, the results of the equation are also unit accurate.

12.3 Flash memory module life specifications

Table 34. Flash memory module life specifications 1 MB and 2 MB blocks using Sector Erase.

Program and erase supported for factory conditions. Nominal supply values and operation at 25°C.

12.3.1 Data retention vs program/erase cycles

Graphically, Data Retention versus Program/Erase Cycles can be represented by the following figure. The spec window represents qualified limits. Figure 15. Data retention vs program/erase cycles

12.4 Flash memory AC timing specifications

Table 35. Flash memory AC timing specifications

For Block Erase, Tdones times may be 3x max spec.
In extreme cases (1 block configurations) Tdrcv min may be faster (12uS plus seven system clocks)

12.5 Flash memory read timing parameters

Table 36. Flash Read Wait State Settings (S32K396, S32K394, S32K376, and S32K374)

250 KHz < Freq ≤ 60 MHz 1

60 MHz < Freq ≤ 90 MHz 2

90 MHz < Freq ≤ 120 MHz 3

120 MHz < Freq ≤ 150 MHz 4

150 MHz < Freq ≤ 180 MHz 5

180 MHz < Freq ≤ 210 MHz 6

Table continues on the next page...

Table 36. Flash Read Wait State Settings (S32K396, S32K394, S32K376, and S32K374) (continued)

210 MHz < Freq ≤ 240 MHz 7

240 MHz < Freq ≤ 250 MHz 8

13 Analog modules

13.1 SAR_ADC

Table 37. SAR_ADC Table continues on the next page...

Table 37. SAR_ADC (continued)

Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for reference supply design for
VSS and VREFL should be shorted on PCB. 100mV difference between VSS and VREFL is for transient only (not for DC).
This is ADC Input range for ADC accuracy guaranteed in this input range only. For SoC Pin capability, see Operation Condition Section.
Spec valid if potential difference between VDD_HV_A and VREFH should follow VDD_HV_A +0.1V >=VREFH >= VDD_HV_A -1.5V
TUE spec for precision and standard channels is based on 12-bit level resolution.

Figure 16. SAR ADC Input Circuit

13.2 Sigma Delta Analog to Digital Converter

Table 38. Sigma Delta Analog to Digital Converter Table continues on the next page...

Table 38. Sigma Delta Analog to Digital Converter (continued) &RIPPLE Passband ripple -1 — 1 % From 10Hz to 0.33*Fd. Table continues on the next page...

Table continues on the next page...

When using a GAIN setting of 16, the conversion result will always have a value of zero in the least significant bit. The

gives an effective resolution of 15 bits.

Fs=40MHz is preferred mode except for applications requiring high input impedance. Fs=20MHz mode provides higher
Offset and gain error due to temperature drift can occur in either direction (+/-) for each of the SDADCs on the dev
Conversion offset error must be divided by the applied gain factor (1, 2, 4, 8, or 16) to obtain the actual input referred offset
Calibration of gain is possible when gain = 1. Offset Calibration should be done with respect to 0.5*VDD_HV_SDADC for
Applicable for half sampling rate mode(Fs=20MHz).
Guaranteed only when input signal is between VREFP-0.15 and VREFN+0.15. Parameter observed should be normalized

13.3 Low Power Comparator (LPCMP)

Table 39. Low Power Comparator (LPCMP) Table continues on the next page...

Table 39. Low Power Comparator (LPCMP) (continued) Table continues on the next page...

Difference at input > 200mV
vdda is comparator HV supply and internally shorted to VDD_HV_A pin. vss is comparator ground
Applied +/- (100 mV + VAHYST0/1/2/3 + max. of VAIO) around switch point
Applied +/- (30 mV + VAHYST0/1/2/3 + max. of VAIO) around switch point
1 LSB = (vrefh_cmp - vrefl_cmp) /256. vrefh_cmp and vrefl_cmp are comparator reference high and low
Calculation method used: Linear Regression Least Square Method

VDD_HV_A goes below VDD_HV_B.

Figure 20. Typical Hysteresis vs Vin level (VDD_HV_A = 5 V, Low Speed Mode).png

13.4 Sine wave generator

Table 40. Sine wave generator

Peak to peak value is measured with no R or I load and its range is for room temperature
Peak-to-peak value is measured with no R or I load
Peak to peak excludes noise, SINAD must be considered.
Common mode value is measured with no R or I load
SINAD is measured at Max Peak-to-Peak voltage. SINAD may not be met with FIRC clock source.
Internal device routing resistance. ESD pad resistance is in series and must be considered for Max peak to peak voltages,

13.5 Supply Diagnosis

The table below gives the specification for the on die supply diagnosis. Table 41. Supply Diagnosis

These specs will have degraded performance when used in extended supply voltage operation range, i.e. normal supply

voltage range specification is exceeded.

Required ADC sampling time specified by parameter AN_TADCSA needs to be used at the ADC conversion to guarantee

the specified accuracy. A smaller sampling time leads to a less accurate result.

If V15 > VDD_HV_A +100mV then the V15 measurement via anamux may be imprecise.

13.6 Temperature Sensor

The table below gives the specification for the MCU on-die temperature sensor. Table 42. Temperature Sensor

Required ADC sampling time specified by parameter TS_TADCSA needs to be used at the ADC conversion to guarantee

the specified accuracy. A smaller sampling time leads to a less accurate result.

Note: The temperature sensor measures the junction temperature Tj at the location where it is placed on die. The local Tj

is modulated by current and previous active state of the circuit elements on die.

The error caused by ADC conversion and provided temperature calculation formula is not included.

14 Clocking modules

14.1 Fast External Oscillator (FXOSC)

Table 43. Fast External Oscillator (FXOSC) Table continues on the next page...

Table 43. Fast External Oscillator (FXOSC) (continued)

For bypass mode applications, the EXTAL pin should be driven low when FXOSC is in off/disabled state.
The startup time specification is valid only when the recommended crystal and load capacitors are used. For higher load

capacitances, the actual startup time might be higher.

The recommended gm setting to ensure extal swing < 2.75V at 8MHz in ALC-disabled mode is gm=4'b0010.

Recommended gm settings in ALC-disabled mode for all other supported frequencies and crystals remain the same. To ensure stable oscillations, FXOSC incorporates the feedback resistance internally. the crystal drive level rating. In such cases, contact NXP sales representative for selecting the correct crystal.

gmXOSC is the transconductance of the internal oscillator circuit
ESR is the equivalent series resistance of the external crystal
RS is the series resistance connected between XTAL pin and external crystal for current limitation
F is the external crystal oscillation frequency
C0 is the shunt capacitance of the external crystal
CL is the external crystal total load capacitance. CL = Cs+ [C1*C2/(C1+C2)]
Cs is stray or parasitic capacitance on the pin due to any PCB traces
C1, C2 external load capacitances on EXTAL and XTAL pins See manufacture datasheet for external crystal component values

Figure 21. Oscillation build-up equation in BGA289 package) cannot be toggling edge-aligned. For 176LQFP, To improve FXOSC jitter with SMPS ON use VDD_DCDC=3.3 V.

Figure 22. Block diagram

14.2 FIRC

Table 44. FIRC

Startup time is for reference only.

14.3 SIRC

Table 45. SIRC

Startup time is for information only.

14.4 PLL

Jitter values specified in this table are applicable for FXOSC reference clock input only. Table 46. PLL Table continues on the next page...

Table 46. PLL (continued)

For SSCG, jitter due to systematic modulation needs to be added as per applied modulation. Accumulated jitter
Jitter numbers are valid only at IP boundary and does not include any degradation due to IO pad for clock measurement.
Jitter numbers calculated by extrapolating RMS jitter numbers to +/- 7 sigma .

15 Communication interfaces

15.1 LPSPI

15.1.1 LPSPI

of the transfer attributes are programmable. The following table provides timing characteristics for classic LPSPI timing modes. 1.All timing is shown with respect to 50% VDD_HV_A/B thresholds.

All measurements are with maximum output load of 30pF, input transition of 1 ns and pad configured DSE = 1, SRC = 0

Table 47. LPSPI Table continues on the next page...

Table 47. LPSPI (continued) Table continues on the next page...

For LPSPI0 instance, max. peripheral frequency is equal to AIPS_PLAT_CLK.
fperiph = LPSPI peripheral clock
Master Loopback mode: In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting

LPSPI_CFGR1[SAMPLE] bit as 1.

These specifications apply to the SPI operation, as master or slave, at up to 10 Mbps for the combinations not indicated

configurations. See table "LPSPI 20 MHz and 15 MHz Combinations.

LPSPI0 support up to 20MHz on fast pin.
Minimum configuration value for CCR[PCSSCK] field is 3(0x00000011).
Minimum configuration value for CCR[SCKPCS] field is 3(0x00000011).
While selecting odd dividers, ensure Duty Cycle is meeting this parameter.
Output rise/fall time is determined by the output load and GPIO pad drive strength setting. See the GPIO specifications for
The input rise/fall time specification applies to both clock and data, and is required to guarantee related timing parameters.

Figure 26. LPSPI Master Mode Timing (CPHA=1)

15.1.2 LPSPI0 20 MHz and 15 MHz Combinations

Table 48. LPSPI0 20 MHz and 15 MHz Combinations

15 Mbps

Trace length should not exceed 11 inches for SCK pad when used in Master loopback mode.

15.1.3 LPSPI Pad Type

Table 49. LPSPI Pad Type Table continues on the next page...

Table 49. LPSPI Pad Type (continued) Table continues on the next page...

15.2 MDIO timing specifications

2.97 V to 3.63 V. MDIO pin must have external Pull-up. Table 50. MDIO timing specifications

Figure 27. MII/RMII serial management channel timing

15.3 Ethernet MII (10/100 Mbps)

configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97 V to 3.63 V. QuadSPI cannot be used along with Ethernet in 176LQFP-EP. Table 51. Ethernet MII (10/100 Mbps)

15.4 Ethernet MII (200 Mbps)

configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97 V to 3.63 V. Table 52. Ethernet MII (200 Mbps)

15.5 Ethernet RMII (10/100 Mbps)

configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97 V to 3.63 V. Table 53. Ethernet RMII (10/100 Mbps)

Figure 32. RMII receive diagram Figure 33. RMII transmit diagram

15.6 I2C

See I/O parameters for I2C specification.

15.7 FlexCAN characteristics

See I/O parameters for FlexCAN specification.

15.8 LPUART characteristics

See I/O parameters for LPUART specification.

15.9 SPI

DRE=1 & SRE=0 is the required drive setting to meet the timing. Table 54. SPI

SMPL_PTR should be set to 1. For SPI_CTARn[BR] - 'Baud Rate Scaler' configuration is >= 3
The maximum SPI baud rate that is achievable in a dedicated master-slave connection depends on several parameters
This value of 20 ns is with the configuration prescaler values: SPI_CTARn[PCSSCK] - "PCS to SCK Delay Prescaler"
This value of 20 ns is with the configuration prescaler values: SPI_CTARn[PASC] - "After SCK Delay Prescaler"
Input timing assumes an input signal slew rate of 2ns (20%/80%).
For the case of both master and slave being NXP S32x devices, frequency of operation will be reduced to

[1000 /2* {tSUI_master + tSUO_slave + PCB delay}] in ns.

Output timing valid for maximum external load CL = 25 pF (includes PCB trace, package trace (around 1-2pF) and flash

Figure 36. SPI PCS Strobe (PCSS) Timing

15.10 Microsecond channel (MSC)

These specs apply to both LVDS and GPIO. This module corresponds with DSPI in RM. Table 55. Microsecond channel (MSC)

If MSC functionality is not used it can be used as SPI interface
With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of SPI_CLKn. This

timing value is due to pad delays and signal propagation delays.

Figure 37. SPI ,aster timing, output only

15.11 Zipwire

See LVDS 3.3V Receiver/Transmitter Electrical Specifications for Zipwire specification.

15.12 LFAST PLL

Table 56. LFAST PLL Table continues on the next page...

Table 56. LFAST PLL (continued)

DJ max jitter includes influence of edge aligned IO activity

16 Memory interfaces

Reference Manual for register and bit descriptions. Table 57. QuadSPI Octal 3.3V DDR 120MHz Table continues on the next page...

Table 57. QuadSPI Octal 3.3V DDR 120MHz (continued) tIH_DQS Input hold time (w.r.t.

Input timing assumes an input signal transition of 1 ns (20%/80%). DQS denotes external strobe provided by the Flash.

Reference Manual for register and bit descriptions. Program register value QuadSPI_FLSHCR[TCSS] = 4\`h3. Program register value QuadSPI_FLSHCR[TCSH] = 4\`h3. transitions measured at mid-supply. Table 58. QuadSPI Quad 3.3V SDR 120MHz

This frequency specification is valid only if output valid time of external flash is ≤ 5.5ns, and if output valid time of

external flash is more than 5.5ns but ≤ 6.5ns, then maximum fSCK is 104MHz.

Figure 38. QuadSPI input timing (SDR mode) Figure 39. QuadSPI output timing (SDR mode)

16.3 QuadSPI configurations

Table 59. QuadSPI configurations (120 DDR) Table continues on the next page...

Table 59. QuadSPI configurations (120 DDR) (continued)

See Chapter "DLL and delay chain usage" for the DLLCR programming sequence

Table 60. QuadSPI configurations (120 SDR) Table continues on the next page...

Table 60. QuadSPI configurations (120 SDR) (continued)

17 Debug modules

17.1 Debug trace timing specifications

input transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0. Table 61. Debug trace timing specifications Figure 40. Trace CLKOUT specifications

17.2 JTAG electrical specifications

The following table describes the JTAG electrical characteristics. These specifications apply to JTAG and boundary scan. Measurements are with maximum output load of 30pF, input transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0.

Table 62. JTAG electrical specifications

Cycle time is 30ns assuming full cycle timing. Cycle time is 60ns assuming half cycle timing.
This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions.
Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

Figure 43. Boundary Scan Timing

17.3 SWD electrical specifications

transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0. Table 63. SWD electrical specifications Table continues on the next page...

Table 63. SWD electrical specifications (continued) Figure 44. SWD Input Clock Timing Figure 45. SWD Output Data Timing

18 Thermal Attributes

18.1 Description

The tables in the following sections describe the thermal characteristics of the device.

18.2 Thermal Characteristics

Junction temperature of the device does not solely depend on package thermal resistance but is also a function of chip power dissipation, PCB attributes, environmental conditions (ambient temperature & air flow) and cumulative effects of other heat generating ICs on the PCB. NXP Semiconductors Thermal Attributes S32K39 and S32K37 Data Sheet, Rev. 3, 03/2024 Data Sheet: Technical Data 109 / 119

The appropriate thermal design must be carried out on package so that it can safely dissipate the necessary amount of power needed for it to function properly. This may involve adding a cooling solution on the package, creating thermal enhancements on the PCB and improving environmental conditions.
The customer is encouraged to use the package model to perform design and risk assessment through simulations. Package models in FloTHERM or Icepak formats can be obtained under NDA from the sales team. Thermal Ratings
The table below is the S32K396 package thermal ratings for both MAPBGA and LQFP-EP package variants. These numbers are derived through simulations based on standardized tests as described in the footnotes.
Thermal resistance data in this report is solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not meant to predict the performance of a package in an application-specific environment :

Table 64. Thermal Characteristics

Thermal test board meets JEDEC specification for this package (JESD51-9 for MAPBGA and 51-7 for LQFP-EP). Test board

has 7x7 via array under the package.

Determined in accordance with JEDEC JESD51-2A natural convection environment.
Junction-to-Case (top) thermal resistance determined using an isothermal cold plate. Case temperature refers to the

MAPBGA’s mold surface temperature.

Junction-to-Case (bottom) thermal resistance determined using an isothermal cold plate. Case temperature refers to the

exposed pad surface temperature of LQFP-EP.

19 Dimensions

19.1 Obtaining package dimensions

The following table lists the changes in this document.

Rev 3, Mar 2024

Updated the 6th character in Ordering Information
Updated the footnote attached to HVD_V15 symbol in Supply monitoring section
ADded L_SMPS and D_SMPS in V15 regulator (SMPS option) electrical specifications table
Updated Supply Currents section
Added ILKG_33_TWINANAMUX and ILKG_50_TWINANAMUX and removed ILKG_GPI, ILKG_50_I and ILKG_33_I from 3.3 V GPIO DC electrical specifications section and 5.0 V GPIO DC electrical specifications
Added footnotes to 3.3 V GPIO AC electrical specifications and 5.0 V GPIO AC electrical specifications table
Added Reference load diagram in 3.3 V GPIO AC electrical specifications section and 5.0 V GPIO AC electrical specifications section and LCU timing
Updated existing values and added parameters at 20 MHz frequency in Sigma Delta Analogto Digital Converter table
Updated CMRR value from 55 dB to 34 dB
Updated maximum frequency of FPLL_out and FPLL_vcoRange in PLL table
In LPSPI section — Updated the first point above table to "All timing is shown with respect to 50% VDD_HV_A/B thresholds" — Updated second point above table to "All measurements are with maximum output load of 30pF, input transition of 1 ns and pad configured DSE = 1, SRC = 0" — Updated min values of tLEAD/tLAG to ""tSPCK/2" for LPSPI Slave mode — For "tWPSCK", removed "high or low" from description — Removed Rise/Fall time output specs — Added footnotes "Output rise/fall time is determined by the output load and GPIO pad drive strength setting..." and "The input rise/fall time specification applies to both clock and data..." — Updated LPSPI Master Mode Timing (CPHA=0) and LPSPI Master Mode Timing (CPHA=1) figure
In LPSPI0 20 MHz and 15 MHz Combinations section, added note "LPSPI0 20 MHz and 15 MHz Combinations"
IN LPSPI Pad type table, removed PTF25 and updated PTA16 to PTA6
Added note "QuadSPI cannot be used along with ENET in 176LQFP" in Ethernet MII (10/100 Mbps) section, Ethernet MII (200 Mbps) section and Ethernet RMII (10/100 Mbps) section
Added t2 and t3 in Microsecond channel
Updated 176 LQFP_EP package to "Yes" in Run Mode configuration
Updated ILKG_50_M0 LSL from -1614.4nA to -1615nA in 5.0 V GPIO DC Electrical specifications section
Updated the footnotes of LCU skew characteristics, eTPU skew charactteristics and eFlexPWM skew characteristics Rev 2, Aug 2023
Updated the title of datasheet to "S32K39 and S32K37 datasheet" Table continues on the next page... NXP Semiconductors

Revision history

S32K39 and S32K37 Data Sheet, Rev. 3, 03/2024 Data Sheet: Technical Data 111 / 119

Rev 2, Aug 2023

Updated the S32K38 part to S32K37 part all over the datasheet
Removed I3C feature all over the datasheet
Updated the S32K396 product series section
Updated mention of "GHzPWM configuration" to "eFlexPWM configuration" in Feature Comparison and Feature Summary
Added Clocks section in Feature Summary
Updated Feature Summary table
Updated "4x arm Cortex" to "3x arm Cortex" in both block diagrams and Feature Comparison section
Updated "arm" to "Arm" in both block diagrams
Updated 100 Mbps Ethernet to 10/100 Mbps Ethernet
Added Supported voltage supply use-cases, LPSPI Pad Type, and eMIOS
Added LCU skew characteristics, eTPU skew characteristics and eFlexPWM skew characteristics
Updated the maximum value of V15, description of V11 and added footnote ""Voltage at VDD_DCDC cannot be higher than VDD_HV_A" in Absolute maximum ratings to VDD_DCDC
In Voltage and current operating requirements — Added footnote to V15 as "Min and Max values are applicable only for non-SMPS mode where V15 is sourced externally". — Updated footnote from “VDDA_SWG must be shorted to VDD_HV_A at the PCB level” to “Must be shorted to VDD_HV_A at the PCB level” and add it to VDD_SDADC — Updated footnote from “SDADC can be only used when VDD_HV_A is 5V, otherwise SDADC cannot be used” to "SDADC is intended to be used only when VDD_HV_A is supplied with 5V. In case of VDD_HV_A is supplied with 3.3V it is recommended to disable SDADC in MC_ME module" and added to VREH_SDADC_xx — Added footnote "All the VREFH_xx except of VREFH_R2R must be shorted to single supply source at the PCB level, either isolated voltage reference or shorted to VDD_HV_A. Isolated VREFH_R2R is required to avoid SDADC performance degradation. If isolated supply cannot be used, then appropriate filtration is needed to isolate the VREFH_R2R noise." and attached to VREFH_R2R, VREFH_SDADC_xx and VREFH_SAR_xx. — Updated the footnote attached to VREFH specs to "VREFH should always be equal to or less than VDD_HV_A +0.1.." — Added IINJ_LVDS parameter specs with 100 µA as typical — Added footnote "Voltage at VDD_DCDC cannot be higher than VDD_HV_A" to VDD_DCDC
Added footnote to HVD_V15 in Supply Monitoring
In Recommended Decoupling Capacitors — Added "Only needed when internal SMPS is used to generate V15 and VDD_DCDC is supplied with isolated source from VDD_HV_A or VDD_HV_B" — Removed COUT_V15 parameter from Recommended Decoupling Capacitors and added in V15 regulator (SMPS option) electrical specifications as COUT_V15_SMPS — Added CBULK_SMPS with 22 µF as typical value Table continues on the next page... NXP Semiconductors

S32K39 and S32K37 Data Sheet, Rev. 3, 03/2024 Data Sheet: Technical Data 112 / 119

Rev 2, Aug 2023 — Updated the figures

Updated the title name of V15 regulator (SMPS option) electrical specifications and V11 regulator (NMOS ballast transistor control) electrical specifications
In V11 regulator (NMOS ballast transistor control) electrical specifications. split VTH_NMOS for 3.3 V supply and 5 Vsupply
Updated the typical value of V15 Output from 1.51 to 1.5 in V15 regulator (SMPS option) electrical specifications
Updated the description of V15 to "V15 Input" and typical value to 1.5 in V11 regulator (NMOS ballast transistor control) electrical specifications
Added V11 output with 1.14 typical value in V11 regulator (NMOS ballast transistor control) electrical specifications
In Supply currents section — Added column for VDD_HV_B in Example RUN mode configuration supply currents table — Removed Clock Option E column from Low speed RUN mode supply currents table — Removed "RUN mode supply currents (peripherals disabled)" table
Updated eFLEXPWM to 12 channels and eMIOS to 6 channels in RUN mode configuration options table in Operating mode
Updated GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V) and in GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)
Added eTPU timing diagram in eTPU timing
In LVDS 3.3V Transmitter Electrical Specifications and LVDS 5V Transmitter Electrical Specifications, updated the symbol of Deterministic Jitter from Eye_Jitter to Dj
In LVDS 5V Transmitter Electrical Specifications, updated min of Ipin_leakage to -5.6 and max to 5.6 and updated the unit of Dmax from MHz to Mbps
In SAR_ADC section, updated paragraph "All below specs are applicable...". and added footnote to TUE as "Spec valid if potential difference between VDD_HV_A.." and figure updated to show VDD_HV_A instead of VREF
In eFlexPWM, added "only for single instance" in Condition column of IVDD current consumption
Updated the values of Sigma Delta Analog to Digital Converter
In LPCMP section changed ACMP0 to LPCMP0 and updated the information after the table
In Sine wave generator, updated the footnotes and updated the minimum value of APP to 0.394 to be similar to minimum value of MINAPP
In Fast External Oscillator (FXOSC) — Updated IFOSXC, added EXTAL_SWING_PP, added CLKIN_VIL_EXTAL_BYPASS, CLKIN_VIH_EXTAL_BYPASS specifications and VSB specs and related footnote — Added two notes after the table
Updated section and table name from "Ethernet MII (100 Mbps)" to "Ethernet MII (10/100 Mbps)" and "Ethernet RMII" to "Ethernet RMII (10/100 Mbps)"
In Ethernet MII (10/100 Mbps) Table continues on the next page... NXP Semiconductors

S32K39 and S32K37 Data Sheet, Rev. 3, 03/2024 Data Sheet: Technical Data 113 / 119

Rev 2, Aug 2023 — Added 10/100 Mbps as Condition for RXCLK frequency, MII3, MII4 and TXCLK frequency — Updated the typical value of RXCLK frequency and TXCLK frequency to 2.5/25 — Added 10/100 Mbps as Condition for RMII input clock frequency

Updated SPIsection — Added "DRE=1 and SRE=0....timing" before table — Added Note "This modules corresponds with DSPI in RM" — Removed tA and tDIS and updated load capacitance from 25 pF to 30 pF
In Microsecond channel (MSC) — ADded footnote to MSC_GPIO stating "if MSC functionality is not used it can be used as SPI interface" — Added Note "This modules corresponds with DSPI in RM" — Added t1 with min as -1 and max as 1 ns — Updated the minimum values of tSCK (LVDS) to 25 and tSCK (GPIO) to 40 — Removed the parameter tCSC and tASC and added parameter tCSV and tCSH in — Updated the maximum value of tSCV to 26 ns(GPIO) and minimum value tSCH to -4 ns
Removed auto-learning mode from QuadSPI Octal 3.3V DDR 120MHz table
In PLL, updated the footnote to "For SSCG, jitter due to systematic modulation needs to be added as per applied modulation. Accumulated jitter specification is not valid with SSCG."
Added sentence before the table in PLL
Added accumulated and period jitter specifications in PLL table
In LFAST PLL table, updated the typical value of Rj to 50 ps. Updated the typical value of Dj to 80 ps and maximum value to 500 ps and added footnote "DJ max jitter includes influence of edge aligned IO activity" 120MHz Rev 1.1, Aug 2022
In section "Voltage and current operating requirements", added "contact NXP sales representative for Hardware design guidelines document/package".
Updated section "Sigma Delta Analog to Digital Converter" to remove TBDs and other updates.
In section "SAR ADC", removed TBD from RS (max) specification. Rev 1, Aug 2022
Updated data sheet classification to "Advance Information".
Updated sections S32K396 product series, feature comparison and feature summary.
In section "Absolute maximum ratings": Table continues on the next page... NXP Semiconductors

S32K39 and S32K37 Data Sheet, Rev. 3, 03/2024 Data Sheet: Technical Data 114 / 119

Rev 1, Aug 2022 — Updated V15 description as "Voltage sensing input". — Added voltage range for VDD_LVDS.

In section "Voltage and current operating requirements": — Added a note as "DSPI/MSC interface is supported only at VDD_HV_A = 5V." — Updated V15 description as "Voltage sensing input". — Added footnote to VDDA_SWG as "VDDA_SWG must be shorted to VDD_HV_A at the PCB level." — Added voltage range for VDD_LVDS and footnote "Ensure that VDD_HV_A ramps before VDD_LVD.". — Added VDD_SDADC supply. — ADC reference voltage symbol and description updated. — Removed 3.3 V from SD ADC reference voltage typical, updated minimum and added a footnote as "VREFH_SDADC_xx must be shorted to single supply source...". — Added R2R high/low voltage reference specifications.
Deleted LVD_V15 from "Supply monitoring""
In section "Recommended Decoupling Capacitors": — Updated description of CDEC and a related footnote updated to mention 10nF instead of 1 nF Optionally, 10 nF capacitors can be added...". — Decoupling capacitors pinout diagrams updated.
In section "SMPS regulator electrical specifications": — Added "External schottky diode average forward current". — Added 2V as "External P-channel MOSFET threshold voltage".
In section "NMOS Ballast Transistor Control Specification" added CNMOS (NMOS gate stability capacitor)
Updated IDD tables in "Supply currents".
In section "Operating mode" changed I3C to I2C.
Added section "Cyclic wake-up current"
In section "GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)" deleted ILKG_33_S_PTE13.
In section "GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)" deleted ILKG_50_S_PTE13.
In section "LVDS 3.3V Receiver Electrical Specifications", added sentence "These specifications are related to LVDS pads dedicated to Zipwire."
Added "LCU"and "eTPU timing".
Changed "AE Nano Edge" to eFlexPWM.
In section "SAR SDC" — CP2 (all/standard channels) updated from 4.18 to 5 pF. — CP2 (precision channels) updated from 1.42 to 2.2 pF. — In footnote attached to TUE updated to mention 12-bit level resolution for both precision and standard channels.
In section "FXOSC" removed crystal recommendations and updated a paragraph as "To ensure stable oscillations, FXOSC...". Table continues on the next page... NXP Semiconductors

S32K39 and S32K37 Data Sheet, Rev. 3, 03/2024 Data Sheet: Technical Data 115 / 119

Rev 1, Aug 2022

In section "LPSPI", updated part of sentence as "All measurements are with maximum output load of 30 pF...." and updated tV for Slave_10Mbps from 36 to 41 ns.
In section "MDIO timing specifications" updated MDC3 from 25 to 28 ns.
In section "I3C Push-Pull Timing Parameters for SDR Mode" added tDVO specs and updated tSU_PP from 3 to 5 ns.
Added sections "SPI" and "Microsecond channel (MSC)".
In section "QuadSPI Octal 3.3V DDR 120MHz": — Updated part of sentence as "QuadSPI trace length should be less than or equal to 2 inches.". — Updated tOD_DATA, tOD_CS, IH_DQS and deleted tDVW.
In section "QuadSPI Quad 3.3V SDR 120MHz": — Updated part of sentence as "QuadSPI trace length should be less than or equal to 2 inches.". — deleted specs related to internal loopback, updated tIS and tDVW
Added QuadSPI configurations. NXP Semiconductors

S32K39 and S32K37 Data Sheet, Rev. 3, 03/2024 Data Sheet: Technical Data 116 / 119

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Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2024. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 03/2024 Document identifier: S32K396

Product Information

S32K376 specifications and overview.

Summary

This document provides electrical specifications for S32K396. For functional characteristics and the programming model, see S32K396 Reference Manual. Rev. 3 - 03/2024

Description

This document provides electrical specifications for S32K396. For functional characteristics and the programming model, see S32K396 Reference Manual. Rev. 3 - 03/2024

Source title S32K376 Datasheet(PDF) - NXP Semiconductors

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