S32K324

S32K3XX_V02 NXP | Alldatasheet

Document overview

• Manufacturer or author: NXP Semiconductors
• PDF pages: 146

Technical content

Datasheet sections

• 1 Overview
• 2 Block diagram
• 3 Feature comparison
• 4 Ordering information
• 4.1 Determining valid orderable parts
• 5 General
• 5.1 Absolute maximum ratings
• 5.3 Thermal operating characteristics
• 5.4 ESD and Latch-up Protection Characteristics
• 6 Power management
• 6.1 Power management system - S32K344,
• 6.2 Power management system - S32K312,
• 6.3 Power management system - S32K358,
• 6.4 Power management system - S32K388
• 6.5.1 Power mode transition operating behavior
• 6.5.2 Boot time, HSE firmware not installed
• 6.5.3 Boot time, HSE firmware installed
• 6.5.4 HSE firmware memory verification time
• 6.6 Supply Monitoring
• 6.7 Recommended Decoupling Capacitors
• 6.8 V15 regulator (SMPS option) electrical
• 6.9 V15 regulator (BJT option, NPN ballast
• 6.10 V11 regulator (NMOS ballast transistor control)
• 6.11 Supply currents
• 6.12 Operating mode
• 6.13 Cyclic wake-up current
• 7 I/O parameters
• 8 Glitch Filter
• 9 Flash memory specification
• 9.1 Flash memory program and erase
• 9.2 Flash memory Array Integrity and Margin Read
• 9.3 Flash memory module life specifications
• 9.3.1 Data retention vs program/erase cycles
• 9.4 Flash memory AC timing specifications
• 9.5 Flash memory read timing parameters
• 10 Analog modules
• 10.1 SAR ADC
• 10.2 Supply Diagnosis
• 10.3 Low Power Comparator (LPCMP)
• 10.4 Temperature Sensor
• 11 Clocking modules
• 11.1 FIRC
• 11.2 SIRC
• 11.3 PLL
• 11.4 Fast External Oscillator (FXOSC)
• 11.5 Slow Crystal Oscillator (SXOSC)
• 12 Communication interfaces
• 12.1 LPSPI
• 12.2 LPSPI0 20 MHz and 15 MHz Combinations102
• 12.3 Communication between two S32K388
• 12.3.1 Timing specification for S32K388 to S32K388
• 12.4 I2C
• 12.5 FlexCAN characteristics
• 12.6 SAI electrical specifications
• 12.6.2 SAI Electrical Characteristics, Master Mode106
• 12.7 Ethernet characteristics
• 12.7.1 Ethernet MII (100 Mbps)
• 12.7.2 Ethernet MII (200 Mbps)
• 12.7.3 Ethernet RMII
• 12.7.4 Ethernet RGMII
• 12.7.5 MDIO timing specifications
• 12.8 QuadSPI
• 12.10 LPUART specifications
• 13 Debug modules
• 13.1 Debug trace timing specifications
• 13.2 SWD electrical specifications
• 13.3 JTAG electrical specifications
• 14 Thermal Attributes

• Operating characteristics — Voltage range: 2.97 V to 5.5 V — Ambient temperature range: -40 °C to 125 °C for all power modes
• Arm™ Cortex-M7 core, 32-bit CPU — M7 supports up to 300 MHz frequency with 2.14 DMIPS / MHz — Arm Core based on the Armv7 and Thumb®-2 ISA — Integrated Digital Signal Processor (DSP) — Configurable Nested Vectored Interrupt Controller (NVIC) — Single Precision Floating Point Unit (FPU)
• Clock interfaces — 8 - 40 MHz Fast External Oscillator (FXOSC) — 48 MHz Fast Internal RC oscillator (FIRC) — 32 kHz Low Power Oscillator (SIRC) — 32 kHz Slow External Oscillator (SXOSC) — System Phased Lock Loop (SPLL)
• I/O and package — LQFP48, HDQFP100, HDQFP172, MAPBGA257, MAPBGA289, HDQFP172 with Exposed pad (EP) package options
• Up to 32-channel DMA with up to 128 request sources using DMAMUX
• Memory and memory interfaces — Up to 8 MB program flash memory with ECC — Up to 128 K of flexible program or data flash memory — Up to 512 KB SRAM with ECC, includes 192 KB of TCM RAM ensuring maximum CPU performance of fast control loops with minimal latency — Data and instruction cache for each core to minimize performance impact of memory access latencies — QuadSPI support
• Mixed-signal analog — Up to three 12-bit Analog-to-Digital Converters (ADC) with up to 24 channel analog inputs per module — One Temperature Sensor (TempSense) — Up to three Analog Comparators (CMP), with each comparator having an internal 8-bit DAC
• Human-Machine Interface (HMI) — Up to 235 GPIO pins — Non-Maskable Interrupt (NMI) — Up to 60 pins with wakeup capability — Up to 32 pins with interrupt support S32K3XX S32K3xx Data Sheet Supports S32K344, S32K324, S32K314, S32K312, S32K341 and S32K342. Data is preliminary for S32K311, S32K310, S32K328, S32K338, S32K348, S32K358 and S32K388 Rev. 7 — 04/2023 Data Sheet: Technical Data NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

• Power management — Low-power Arm Cortex-M7 core with excellent energy efficiency, balanced with performance — Power Management Controller (PMC) with simplified mode management (RUN and STANDBY) — Supports peripheral specific clock gating. Only specific peripherals remain working in low power modes.
• Communications interfaces — Up to 16 serial communication interface (LPUART) modules, with LIN, UART and DMA support — Up to six Low Power Serial Peripheral Interface (LPSPI) modules with DMA support — Up to two Low Power Inter-Integrated Circuit (LPI2C) modules with DMA support — Up to six FlexCAN modules (with optional CAN-FD support) — FlexIO module for flexible and high performance serial interfaces — Up to two Ethernet module — Up to two Synchronous Audio Interface (SAI) modules
• Reliability, safety and security — Hardware Security Engine (HSE_B) - Supports AES accelerator(for K388 only) — Up to two Internal Software Watchdog Timers (SWT) — Error-Correcting Code (ECC) on all memories — Error Detection Code (EDC) on data path — Cyclic Redundancy Check (CRC) module — 120-bit Unique Identification (ID) number — Extended Cross domain Domain Controller (XRDC), providing protection for master core access rights — Virtualization Wrapper (VIRT_WRAPPER), providing I/O protection
• Debug functionality — Serial Wire JTAG debug Port (SWJ-DP), with 2 pin Serial Wire Debug (SWD) for external debugger — Debug Watchpoint and Trace (DWT), with four configurable comparators as hardware watchpoints — Serial Wire Output (SWO)-synchronous trace data support — Instrumentation Trace Macrocell (ITM) with software and hardware trace, plus time stamping — CoreSight AHB Trace Macrocell (HTM) — Flash Patch and Breakpoints (FPB) with ability to patch code and data from code space to system space — Serial Wire Viewer (SWV): A trace capability providing displays of reads, writes, exceptions, PC Samples and print — Full data trace for up to 16 output wide — Embedded Cross Trigger (ECT) is used for multicore run-control and trace cross triggering, using CoreSight Cross Trigger Interface (CTI)
• Timing and control — Up to three enhanced modular I/O system (eMIOS), offering up to 72 timer channels (IC/OC/PWM) — Up to two System Timer Modules (STM) — Up to two Logic Control Units (LCU) — Full cross triggering support for ADC / timer (BCTU) — One Trigger MUX Control (TRGMUX) module — Up to three Periodic Interrupt Timer (PIT) modules — 32-bit Real Time Counter (RTC) with autonomous periodic interrupt (API) function NXP Semiconductors S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 2 / 146

1 Overview

to take advantage of more memory or feature integration.

2 Block diagram

512 KB Pflashwith ECC

112 KB RAM with ECCinclude96KB TCM

• OTA ready-RWW, A/B swap CPU Platform
• Scalable ARM M7 core inlockstep• Optimized for Real-time with zero wait I/D-TCM c Network/ Communication
• CAN/ CAN FD, LIN• Flexible IO emulation Motor Control
• On-chip motor control sub-system• Offloading CPU
• Future Proof Security/OTA• ISO26262 Compliant Safety System• ScalableARM platform• Optimized for Low power• Rich Network/Communication Interface Safety
• HW redundancy• MBIST/LBIST/Self Test• Clock/Voltage monitor• Centralized error detection• ASIL B compliant Security
• HW acclfor AES 256, RSA 4096, ECC 521• Firmware included, upgradable• Side-channel physical protection• Meet Evita Full function goal

Figure 1. S32K310: ASIL B Single Core 1MB General Purpose MCU

1 MB Pflash with ECC

120 MHz

Figure 2. S32K311: ASIL B Single Core 1MB General Purpose MCU

2 MB Pflash with ECC

• • • • Security HW accl for AES 256, RSA 4096, ECC 521 Firmware included, upgradable Side-channel physical protection Meet Evita Full function goal Network/ Communication CAN/CAN FD, LIN Flexible IO emulation• • System FIRC (48 MHz) CPU Platform Cortex-M7

Figure 3. S32K312: ASIL B Single Core 2MB General Purpose MCU

160 MHz

Figure 4. S32K322: ASIL B Dual Core 2MB General Purpose MCU

• ••• Security HW accl for AES 256,RSA 4096, ECC 521Firmware included,upgradableSide-channel physicalprotectionMeet Evita Fullfunction goal Network/Communication Ethernet (TSN), CAN/CAN FD, LINSAI for AudioFlexible IO emulation System FIRC (48 MHz) CPU Platform Cortex-M7

Figure 5. S32K341: ASIL D Lockstep Core 1MB General Purpose MCU

Figure 6. S32K342: ASIL D Lockstep Core 2MB General Purpose MCU

4 MB Pflash with ECC

Figure 7. S32K314: ASIL B Single Core 4MB General Purpose MCU

• • • • Security HW accl for AES 256, RSA 4096, ECC 521 Firmware included, upgradable Side-channel physical protection Meet Evita Full function goal Network/ Communication Ethernet (TSN), CAN/ CAN FD, LIN SAI for Audio Flexible IO emulation
• • System FIRC (48 MHz) CPU Platform Cortex-M7

Figure 8. S32K324: ASIL B Dual Core 4MB General Purpose MCU Figure 9. S32K344: ASIL D Lockstep Core 4MB General Purpose MCU

8 MB Pflash with ECC

240 MHz

Figure 10. S32K328: ASIL B Dual Core 8MB General Purpose MCU Figure 11. S32K338: ASIL B Three Core 8MB General Purpose MCU

Figure 12. S32K348: ASIL D Lockstep Core 8MB General Purpose MCU Figure 13. S32K358: ASIL D Lockstep Core + One, 8MB General Purpose MCU

128 KB Dflash with ECC

1152 KB RAM with ECCIncl 384 KB TCM

300 MHz

Figure 14. S32K388: ASIL D 8MB MCU

3 Feature comparison

• S32K310
• S32K311
• S32K312
• S32K322
• S32K341
• S32K342
• S32K314
• S32K324
• S32K344
• S32K328
• S32K338
• S32K348
• S32K358
• S32K388 NXP Semiconductors Feature comparison S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 12 / 146

Table 1. S32K3xx chip's feature comparison

512 KB 1 MB 2 MB 1 MB 2 MB 4 MB 8 MB 8 MB

16 KB 32 KB 64 KB 64 KB

Table continues on the next page...

Table 1. S32K3xx chip's feature comparison (continued) Table continues on the next page...

Table continues on the next page...

1. This feature set is under evaluation and subject to change.
2. Final DMIPS is in range based on compiler setting. Low number is using "ground rules" laid out in the Dhrystone documentation. High number is using inlining of
3. ASIL-B and ASIL-D performance is available simultaneously.
4. Core configuration is 2xLS + 1 independent core
5. Core configuration is 1xLS + 3 independent cores
6. Result depends on specific compiler version, contact NXP sales representative for more details.
7. 4-bit data width, SDR mode only
8. 8-bit data width, SDR and DDR mode

4 Ordering information

Figure 15. Ordering information

Features

32: Automotive 32-bit MCU/MPU Tx: Global Foundry x0: 1st mask revision x1: 2nd mask revision Product Line K: General purpose MCU S: Standard Family SW Package, including: I: ISELED SW licensed + Standard Family SW Package Additional solution specific SW TBD Real time driver including combined SDK & Autosar MCAL (ISO26262, crypto driver included) Standard Security Firmware Safety Peripheral Driver (SPD) Inter-core communication framework(IPCF) Memory Size Series/Family 3: K3 product family/ARM CortexM7 based Core platform 1: 1 x M7 Core 2: 2 x M7 Cores 3: 3 x M7 Cores 4: 1 x M7 lockstep core 5: 1 x M7 lockstep core plus 1 x M7 core P/S 32 K 3 4 4 X X T0 M PA S R Product Type/Brand Product Line Series/Family Core platform Memory size V: -40 °C to 105 °C M: -40 °C to 125 °C Temperature Suffix Temperature Suffix Package Suffix Software configuration Tape and Reel Indicator Package Suffix Software Configuration T: Trays/Tubes R: Tape & Reel Tape and Reel Indicator 100 172 257 289 MM JB PA PB LF PC pins HDQFPBGA LQFPHDQFP-EP 0 1 2 4 6 8 P-FLASH 512KB 1MB 2MB 4MB 6MB 8MB No Ethernet MAC 100Mbps Ethernet MAC 1Gbps Ethernet MAC 2x1 Gbps Ethernet MAC N E G H HSE B Standard Security Customized Security H ∙ ∙∙∙ G= customized firmware for GM HSE 8: 2 x M7 lockstep + 1xM7 core or 1xM7 lockstep + 3xM7 Cores V= customized firmware for VW

4.1 Determining valid orderable parts

To determine the orderable part numbers for this device, please contact NXP sales representative.

5 General

Ordering information

S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 17 / 146

5.1 Absolute maximum ratings

as absolute maximum ratings - is not implied. minimum values in the datasheet are across process, voltage, and temperature. The VDD_DCDC supply voltage is only present in certain devices and packages (S32K358, S32K348, S32K338, S32K328). Table 2. Absolute maximum ratings Table continues on the next page...

Table 2. Absolute maximum ratings (continued)

1. All voltages are referred to VSS unless otherwise specified.
2. 6.0 V maximum for 10 hours over lifetime; 7.0 V maximum for 60 seconds over lifetime.
3. Voltage at VDD_DCDC cannot be higher than VDD_HV_A.
4. Absolute max rating must be honored under all conditions, including current injection.
5. When input pad voltage levels are close to VDD_HV_A (respectively to VDD_HV_B) or VSS, practically no current injection

is possible. See application note AN4731 for a description of injection current on NXP automotive microcontrollers.

1. TSTG specifies the storage temperature range. It is not the operating temperature range. Please refer to the Thermal

operating characteristics table.

5.2 Voltage and current operating requirements

degraded when voltage drops below 2.97 V. The VDD_DCDC supply voltage is only present in certain devices and packages (S32K358, S32K348, S32K338, S32K328).

Table 3. Voltage and current operating requirements Table continues on the next page...

Table 3. Voltage and current operating requirements (continued)

1. All voltages are referred to VSS unless otherwise specified.
2. Voltage at VDD_DCDC cannot be higher than VDD_HV_A.
3. Min and Max values are applicable only for non-SMPS mode where V15 is sourced externally.
4. If total power dissipation and maximum junction temperature allows. Please refer to Thermal operating characteristics

the maximum power dissipation allowed for a given package.

1. You must ensure that the junction temperature in the application must not exceed the maximum specified Tj.
2. VREFH should always be equal to or less than VDD_HV_A +0.1. Any positive differential voltage between VREFH and
3. Open-drain outputs must be pulled respectively to their supply rail (VDD_HV_A or VDD_HV_B).
4. When input pad voltage levels are close to VDD_HV_A (respectively to VDD_HV_B) or VSS, practically no current injection
5. The MCU supply ramp rate parameter must be applicable to the MCU input/external supplies. The ramp rate assumes that

the S32K3xx HW design guidelines available on www.nxp.com are followed.

5.3 Thermal operating characteristics

Table 4. Thermal operating characteristics

5.4 ESD and Latch-up Protection Characteristics

Table 5. ESD and Latch-up Protection Characteristics

1. Device failure is defined as: "If after exposure to ESD pulses, the device does not meet specification requirements."
2. This parameter is tested in conformity with AEC-Q100-002.
3. All ESD testing conforms with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
4. This parameter is tested in conformity with AEC-Q100-011.
5. This parameter is tested in conformity with AEC-Q100-004.

6 Power management

6.1 Power management system - S32K344, S32K324, S32K341, S32K314, S32K342, and

S32K322. VDD_HV_A V25 V11_RUN VSS ADC_n VREFH VREFL Flash memory PMC V25 (Double bond) GPIO Pads VDD_HV_A VSS SW* V11 (Double bond) V11_STANDBY V11_STANDBYRegisters SOG (Standby) WKPU MC_PCU MC_RGM 32 K SRAM PIT_0 (RTI) DCM SOG (Run) LPCMP_n FXOSC SIRC FIRC SXOSC PLLDIG TempSense RTC - Standby domain - Standby domain (optional) - On during FPM (Run mode) onlySW* B VDD_HV_B Optional V15 VRC_CTRL VC_BJT Last Mile distributed regulatorFPMBoot GPIO Pads VDD_HV_B VSS LPM V11_STANDBY COUT_V15 NXP Semiconductors Power management S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 23 / 146

6.2 Power management system - S32K312, S32K311, S32K310

VDD_HV_A V25 V11_RUN VSS ADC_n VREFH VREFL Flash memory PMC V25 (Double bond) GPIO Pads VDD_HV_A VSS SW* V11 (Double bond) V11_STANDBY V11_STANDBYRegisters SOG (Standby) WKPU MC_PCU MC_RGM 32 K SRAM PIT_0 (RTI) DCM SOG (Run) LPCMP_n FXOSC SIRC FIRC SXOSC PLLDIG TempSense RTC - Standby domain - Standby domain (optional) - On during FPM (Run mode) onlySW* B NXP Semiconductors Power management S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 24 / 146

6.3 Power management system - S32K358, S32K348, S32K338, S32K328

LPCMP_n FXOSC SIRC FIRC SXOSC Registers - Standby domain - Standby domain (optional) - On during FPM (Run mode) only PLLDIG0 MC_RGM WKPU MC_PCU PIT_0 (RTI) SOG (Run) SRAM 64 kB RTC DCMPLLDIG1 TempSense SOG (Standby) ADC_n LPMPMC LPM (V15) V11_STANDBY V25 V11_RUN V11_STANDBY V11_STANDBY (Triple bond) Last Mile distributed regulator FPM SW* SW* optional optional [See footnotes] VIN VC_BJT VDD_HV_A VREFH VREFL V11 V25 VSS VSS_DCDC PGATE_CTRL VDD_DCDC VDD_HV_B VRC_CTRL Pads GPIO VDD_HV_A VSS Pads GPIO VDD_HV_B VSS (Triple bond) V15[See footnotes] The V15 input voltage can be supplied directly by an SBC or Voltage regulator. The S32K3x8 devices provide two options to derive the V15 regulator from the 5V or 3.3V supply. Option 1: A DC/DC converter (SMPS) regulator can be implemented by connecting the external components (PMOS, inductor, diode) shown in the figure above, at pins VDD_DCDC, PMOS_CTRL, and VSS_DCDC. In this case, VRC_CTRL must not be connected. VDD_DCDC must be connected to the VDD_HV_A or VDD_HV_B, supply voltage. In this VRC_CTRL pin must be connected to the base of the transistor. In this case, VDD_DCDC, PMOS_CTRL must not be connected. VSS_DCDC must be connected to MCU GND. Option 2: A linear regulator can be implemented by connecting a bipolar NPN transistor from the VDD_HV_A or VDD_HV_B, supply voltage shown as VC_BJT in the figure above. The COUT_V15 In this option, COUT_V15 is specified in Recommended decoupling capacitors. option, COUT_V15 is specified in SMPS regulator electrical specifications. NXP Semiconductors Power management S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 25 / 146

6.4 Power management system - S32K388

6.5 Power mode transition operating behaviors

6.5.1 Power mode transition operating behavior

The values in the table below are provided for reference only. Table 6. Power mode transition operating behavior Table continues on the next page...

Table 6. Power mode transition operating behavior (continued)

6.5.2 Boot time, HSE firmware not installed

Table 7. Boot time, HSE firmware not installed

6.5.3 Boot time, HSE firmware installed

corresponding user code verification time must be added. Table 8. Boot time, HSE firmware installed Table continues on the next page...

Table 8. Boot time, HSE firmware installed (continued)

6.5.4 HSE firmware memory verification time examples

Table 9. HSE firmware memory verification time examples Table continues on the next page...

Table 9. HSE firmware memory verification time examples (continued) Table continues on the next page...

Table continues on the next page...

Table continues on the next page...

6.6 Supply Monitoring

Certain monitors are present on certain devices. See Power Management chapter in reference manual. Table 10. Supply Monitoring Table continues on the next page...

Table 10. Supply Monitoring (continued)

6.7 Recommended Decoupling Capacitors

Table 11. Recommended Decoupling Capacitors

1. Optionally, 1 nF capacitors can be added in parallel to the decoupling capacitors.
2. All capacitors must be low ESR ceramic capacitors (for example, X7R). The minimum recommendation is after

considering component aging and tolerance.

1. These capacitors must be placed as close as possible to the corresponding supply and ground pins. For BGA

packages, the capacitors must be placed on the other side of the PCB to minimize the trace lengths.

1. For devices where the VDD_HV_B domain is present, if the VDD_HV_B supply is different supply from VDD_HV_A, a

dedicated bulk capacitor is needed.

1. It is also possible to use higher capacitance values (for example, 10 μF) in place of the 4.7 μF capacitor.
2. These capacitors must be placed close to the source.
3. For devices where V15 is present, the V15 regulator output capacitor and the filter capacitors are required when using an

recommendations can be followed in addition to the capacitance requirements of the external voltage regulator.

Figure 16. 48-pin LQFP decoupling capacitor pinout diagram (S32K311, S32K310)

Figure 17. 100-pin HDQFP decoupling capacitor pinout diagram (S32K312, S32K311, S32K310)

Figure 18. 100-pin HDQFP decoupling capacitor pinout diagram (S32K342, S32K341, S32K322)

Figure 19. 172-pin HDQFP decoupling capacitor pinout diagram (S32K312)

Figure 20. 172-pin HDQFP decoupling capacitor pinout diagram (S32K344, S32K324, S32K314, S32K342, S32K341

Figure 21. 257BGA package decoupling capacitor pinout diagram (S32K344, S32K324 and S32K314)

Figure 22. 172-pin HDQFP decoupling capacitor pinout diagram (S32K358, S32K348, S32K338 and S32K328)

Figure 23. 172-pin HDQFP decoupling capacitor pinout diagram, SMPS (S32K358, S32K348, S32K338 and S32K328)

Figure 24. 289BGA package decoupling capacitor pinout diagram (S32K358, S32K348, S32K338 and S32K328)

Figure 25. 289BGA package decoupling capacitor pinout diagram, SMPS (S32K358, S32K348, S32K338 and S32K328)

Figure 26. 289BGA package decoupling capacitor pinout diagram, (S32K388)

Figure 27. 289BGA package decoupling capacitor pinout diagram, SMPS (S32K388)

6.8 V15 regulator (SMPS option) electrical specifications

to control an external Power P-channel MOSFET. In addition to the PMOS, an external inductor and a Schottky diode are required. See related figures in section "Recommended decoupling capacitors". The chip hardware design guidelines document lists the recommended part numbers for PMOS, Schottky diode and inductor.

Table 12. V15 regulator (SMPS option) electrical specifications

1. Only needed when internal SMPS is used to generate V15 and VDD_DCDC is supplied with isolated source from

Figure 28. SMPS circuit

6.9 V15 regulator (BJT option, NPN ballast transistor control) electrical specifications

document lists the recommended part numbers for the external devices.

Table 13. V15 regulator (BJT option, NPN ballast transistor control) electrical specifications Figure 29. Ballast circuit

6.10 V11 regulator (NMOS ballast transistor control) electrical specifications

The S32K388 supports a linear regulator stage for the V11 supply, with a dedicated pin to control an external NMOS transistor. The chip hardware design guidelines document lists the recommended part number for NMOS. Table 14. V11 regulator (NMOS ballast transistor control) electrical specifications Table continues on the next page...

Table 14. V11 regulator (NMOS ballast transistor control) electrical specifications (continued)

6.11 Supply currents

All data in this table is preliminary and based on first samples.

Table 15. STANDBY mode supply currents Table continues on the next page...

Table 15. STANDBY mode supply currents (continued) Table continues on the next page...

1. See the configurations in Table 19.
2. IO load current is not included. The actual current requirements for IOs will depend on the I/O configuration in the application.
3. “typ” is indicative of the average current numbers at the nominal internally regulated V11 supply voltage, VDD_HV_A = 5.0V, VDD_HV_B = 5.0V, for the typical
4. “max” is indicative of the maximum current numbers at the maximum internally regulated V11 supply voltage (1.16 V), VDD_HV_A = 5.5V, VDD_HV_B = 5.5V, for

All data in this table is preliminary and based on first samples. NOTE Typical current numbers are indicative for typical silicon process and may vary based on the silicon distribution and user configuration. Typical conditions assumes VDD_HV_A = VREFH = 5 V, VDD_HV_B = 5V (if the VDD_HV_B domain present in the device), temperature = 25 °C, and typical silicon process unless otherwise stated. NXP Semiconductors Power management S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 53 / 146

Table 16. Low speed RUN mode supply currents Table continues on the next page...

Table 16. Low speed RUN mode supply currents (continued) Table continues on the next page...

1. Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation.
2. See the example configurations in Table 19.
3. IO load current is not included. The actual current requirements for IOs will depend on the I/O configuration in the application.
4. RUN IDD @ VDD_HV_A includes Flash memory read current from the V25 voltage rail.
5. RUN IDD @ V15 includes Flash memory read current from the V11 voltage rail
6. For S32K388, the current from a V15 supply will flow through the external NMOS for the V11 regulation stage, and into the V11 pins of the device.

1. “typ” is indicative of the average current numbers at the nominal internally regulated V11 supply voltage, VDD_HV_A = 5.0V, VDD_HV_B = 5.0V, V15 = 1.5V, for the typical silicon process. 8. “max” is indicative of the maximum current numbers at the maximum internally regulated V11 supply voltage (1.16 V), VDD_HV_A = 5.5V, VDD_HV_B = 5.5V, V15 = 1.65V, for the fast silicon process. 9. For the maximum allowable RUN current in an application, the junction temperature must be kept below the maximum specification, TJ < 150°C, to avoid self-heating. 10. If the total power dissipation would cause the junction temperature to be exceeded when VDD_HV_A is at 5V, then VDD_HV_A should be limited to operate at 3.3V. NXP Semiconductors Power management S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 57 / 146

All data in this table is preliminary and based on first samples. NOTE Typical current numbers are indicative for typical silicon process and may vary based on the silicon distribution and user configuration. Typical conditions assumes VDD_HV_A = VREFH = 5 V, VDD_HV_B = 5V (if the VDD_HV_B domain present in the device), temperature = 25 °C and typical silicon process unless otherwise stated. NXP Semiconductors Power management S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 58 / 146

Table 17. RUN mode supply currents (peripherals disabled) Table continues on the next page...

Table 17. RUN mode supply currents (peripherals disabled) (continued) Table continues on the next page...

1. Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation.
2. See the configurations in Table 20.
3. IO load current is not included. The actual current requirements for IOs will depend on the I/O configuration in the application.
4. RUN IDD @ VDD_HV_A includes Flash memory read current from the V25 voltage rail.
5. RUN IDD @ V15 includes Flash memory read current from the V11 voltage rail.
6. For S32K388, the current from a V15 supply will flow through the external NMOS for the V11 regulation stage, and into the V11 pins of the device.
7. “typ” is indicative of the average current numbers at the nominal internally regulated V11 supply voltage, VDD_HV_A = 5.0V, VDD_HV_B = 5.0V, V15 = 1.5V, for

the typical silicon process.

1. “max” is indicative of the maximum current numbers at the maximum internally regulated V11 supply voltage (1.16 V), VDD_HV_A = 5.5V, VDD_HV_B = 5.5V, V15 = 1.65V, for the fast silicon process. 9. For the maximum allowable RUN current in an application, the junction temperature must be kept below the maximum specification, TJ < 150°C, to avoid self-heating. 10. “typ” is indicative of the average current numbers at the nominal internally regulated V11 supply voltage, VDD_HV_A = 5.0V, VDD_HV_B = 5.0V, V15 = 1.5V, for the typical silicon process. 11. “max” is indicative of the maximum current numbers at the maximum internally regulated V11 supply voltage (1.16 V), VDD_HV_A = 5.5V, VDD_HV_B = 5.5V, V15 = 1.65V, for the fast silicon process. 12. For the maximum allowable RUN current in an application, the junction temperature must be kept below the maximum specification, TJ < 150°C, to avoid self-heating. 13. If the total power dissipation would cause the junction temperature to be exceeded when VDD_HV_A is at 5V, then VDD_HV_A should be limited to operate at 3.3V. NXP Semiconductors Power management S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 62 / 146

The data in this table is preliminary and based on first samples. NOTE Typical current numbers are indicative for typical silicon process and may vary based on the silicon distribution and user configuration. Typical conditions assumes VDD_HV_A = VREFH = 5 V, VDD_HV_B = 5V (if the VDD_HV_B domain present in the device), temperature = 25 °C and typical silicon process unless otherwise stated. NXP Semiconductors Power management S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 63 / 146

Table 18. Example RUN mode configuration supply currents Table continues on the next page...

Table 18. Example RUN mode configuration supply currents (continued) Table continues on the next page...

1. Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation.
2. See the configurations in Table 20.
3. IO current is not included. The actual current requirements for IOs will depend on the I/O configuration in the application.
4. RUN IDD @ VDD_HV_A includes Flash memory read current from the V25 voltage rail.
5. RUN IDD @ V15 includes Flash memory read current from the V11 voltage rail.
6. For S32K388, the current from a V15 supply will flow through the external NMOS for the V11 regulation stage, and into the V11 pins of the device.
7. “typ” is indicative of the average current numbers at the nominal internally regulated V11 supply voltage, VDD_HV_A = 5.0V, VDD_HV_B = 5.0V, V15 = 1.5V, for

the typical silicon process.

1. “max” is indicative of the maximum current numbers at the maximum internally regulated V11 supply voltage (1.16 V), VDD_HV_A = 5.5V, VDD_HV_B = 5.5V, V15

= 1.65V, for the fast silicon process.

1. For the maximum allowable RUN current in an application, the junction temperature must be kept below the maximum specification, TJ < 150°C, to avoid

1. If the total power dissipation would cause the junction temperature to be exceeded when VDD_HV_A is at 5V, then VDD_HV_A should be limited to operate at 3.3V. NXP Semiconductors Power management S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 67 / 146

6.12 Operating mode

Table 19. STANDBY and low speed RUN configuration options

1. See clocking use case examples in the Clocking chapter of the S32K3xx Reference Manual.

Table 20. RUN mode configuration options Table continues on the next page...

Table 20. RUN mode configuration options (continued)

1. See clocking use case examples in the Clocking chapter of the S32K3xx Reference Manual.
2. HSE_B: After start-up, the HSE core is in WFI.
3. • FlexCAN0: Transmitting an 8-byte CAN-FD data frame at 5 Mbps, every 10 ms.

• FlexCAN1: Transmitting a 64-byte CAN-FD data frame at 2 Mbps, every 20 ms.
• FlexCAN2-5: Transmitting an 8-byte CAN data frame at 500 Kbps, every 20 ms. 4. LPUART0-15: Transmitting at 19200 bps, every 100ms. 5. • LPSPI0: Transmitting 32 bits at 20 Mbps (GPIO Fast pads), every 5 ms.
• LPSPI1-5: Transmitting 32 bits at 1 Mbps, every 5 ms. 6. LPI2C0-1: Transmitting 3 bytes at 400 Kbps, every 100ms. 7. EMAC: ON for MII interface. 8. • eMIOS0: 6 channels in PWM mode @ 20 KHz.
• eMIOS1-2: 8 channels in PWM mode @ 400 Hz. 9. • SAR_ADC0: 16 channels at 400 Hz rate, BCTU triggered.
• SAR_ADC1-2: 4 channels at 20 KHz rate, BCTU triggered. 10. LPCMP0: 8 channels enabled; LPCMP1-2: 4 channels enabled. NXP Semiconductors Power management S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 69 / 146

6.13 Cyclic wake-up current

for approximately 200μs to scan several GPIO inputs (51 GPIOS), and spends the rest of the time in STANDBY mode.

1. The supply current is obtained through the measurements of the current during the corresponding operating mode.
2. The duration is defined by the application (how much time will the device spend in the according operating mode).
3. The ratio of duration is obtained by dividing the duration of the corresponding operating mode by the total duration of the
4. The current according to ratio is obtained by multiplying the supply current and the ratio of duration related to the proper
5. The average current is calculated by the addition of each device operating mode’s current according to ratio.

7 I/O parameters

and the number of Analog functions (CMP and ADC channels) multiplexed per pin. For S32K388, see the ILKG column in the Pinout section of the IOMUX file attached to the Reference Manual. "Analog Function Count" is shown in the Condition column of the following table. Table 21. GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V) Table continues on the next page...

Table 21. GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V) (continued) Table continues on the next page...

Table continues on the next page...

1. Maximum length of RESET pulse will be filtered by an internal filter on this pin.
2. Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter.
3. A positive value is leakage flowing into pin with pin at VDD_HV_A/B (the GPIO supply level); a negative value is leakage

flowing out the pin with the pin at ground.

1. GPIO output transition time information can be obtained from the device IBIS model. IBIS models are recommended for

connected to an actual transmission line load.

1. I/O output current specifications are valid for the given reference load figure, and the constraints given in the Operating

Conditions of this document.

1. I/O timing specifications are valid for the un-terminated transmission line reference load given in the figure below. A

total with margin). For signals with frequency greater than 63MHz, a maximum 2 inch PCB trace is assumed.

1. To determine total switching current on any I/O supply, current values per output pin should not be incrementally summed.
2. See IBIS models for further details.

Figure 30. Reference Load Diagram and the number of Analog functions (CMP and ADC channels) multiplexed per pin. For S32K388, see the ILKG column in the Pinout section of the IOMUX file attached to the Reference Manual. "Analog Function Count" is shown in the Condition column of the following table. Table 22. GPIO DC electrical specifications, 5.0V (4.5V - 5.5V) Table continues on the next page...

Table 22. GPIO DC electrical specifications, 5.0V (4.5V - 5.5V) (continued) Table continues on the next page...

Table continues on the next page...

1. Maximum length of RESET pulse will be filtered by an internal filter on this pin.
2. Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter.
3. A positive value is leakage flowing into pin with pin at VDD_HV_A/B (the GPIO supply level); a negative value is leakage

flowing out the pin with the pin at ground.

1. GPIO output transition time information can be obtained from the device IBIS model. IBIS models are recommended for

connected to an actual transmission line load.

1. I/O output current specifications are valid for the given reference load figure, and the constraints given in the Operating

Conditions of this document.

1. I/O timing specifications are valid for the un-terminated transmission line reference load given in the figure below. A
2. To determine total switching current on any I/O supply, current values per output pin should not be incrementally summed.

1. See IBIS models for further details.

Figure 31. Reference Load Diagram Table 23. 5.0V (4.5V - 5.5V) GPIO Output AC Specification Table continues on the next page...

Table 23. 5.0V (4.5V - 5.5V) GPIO Output AC Specification (continued) Table 24. 3.3V (2.97V - 3.63V) GPIO Output AC Specification Table continues on the next page...

Table 24. 3.3V (2.97V - 3.63V) GPIO Output AC Specification (continued)

8 Glitch Filter

The glitch filter parameters in the following table apply to the filters of WKPU pins and TRGMUX inputs 60-63.

Table 25. Glitch Filter

1. An input signal pulse is defined by the duration between the input signal's crossing of a Vil/Vih threshold voltage level, and

the next crossing of the opposite level.

1. Pulses shorter than defined by the maximum value are guaranteed to be filtered (not passed).
2. Pulses in between the max filtered and min unfiltered may or may not be passed through.
3. Pulses larger than defined by the minimum value are guaranteed to not be filtered (passed).

9 Flash memory specification

9.1 Flash memory program and erase specifications

Table 26. Flash memory program and erase specifications

1. Program times are actual hardware programming times and do not include software overhead. Sector program times

assume quad-page programming.

1. Typical program and erase times represent the median performance and assume nominal supply values and operation at

25 °C. Typical program and erase times may be used for throughput calculations.

1. Conditions: ≤ 25 cycles, nominal voltage.
2. Plant Programing times provide guidance for timeout limits used in the factory.
3. Typical End of Life program and erase times represent the median performance and assume nominal supply values.

Typical End of Life program and erase values may be used for throughput calculations.

1. Conditions: -40°C ≤TJ ≤150°C, full spec voltage.

9.2 Flash memory Array Integrity and Margin Read specifications

Table 27. Flash memory Array Integrity and Margin Read specifications

1. Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The

read setup that requires 6 clocks to read Nread would equal 6.

1. Array Integrity times are actual hardware execution times and do not include software overhead or system code execution
2. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the

equation, the results of the equation are also unit accurate.

9.3 Flash memory module life specifications

Table 28. Flash memory module life specifications 1 MB and 2 MB blocks using Sector Erase.

1. Program and erase supported for factory conditions. Nominal supply values and operation at 25°C.

9.3.1 Data retention vs program/erase cycles

Graphically, Data Retention versus Program/Erase Cycles can be represented by the following figure. The spec window represents qualified limits. Figure 32. Data retention vs program/erase cycles

9.4 Flash memory AC timing specifications

Table 29. Flash memory AC timing specifications

1. For Block Erase, Tdones times may be 3x max spec.
2. In extreme cases (1 block configurations) Tdrcv min may be faster (12uS plus seven system clocks)

9.5 Flash memory read timing parameters

Table 30. Flash Read Wait State Settings (S32K344, S32K324, S32K314, S32K342, S32K322, S32K341, S32K312,

250 KHz < Freq ≤ 66 MHz 1

66 MHz < Freq ≤ 100 MHz 2

100 MHz < Freq ≤ 133 MHz 3

133 MHz < Freq ≤ 167 MHz 4

167 MHz < Freq ≤ 200 MHz 5

Table continues on the next page...

200 MHz < Freq ≤ 233 MHz 6

233 MHz < Freq ≤ 250 MHz 7

Table 31. Flash Read Wait State Settings (S32K358, S32K348, S32K338, S32K328 and S32K388)

250 KHz < Freq ≤ 60 MHz 1

60 MHz < Freq ≤ 90 MHz 2

90 MHz < Freq ≤ 120 MHz 3

120 MHz < Freq ≤ 150 MHz 4

150 MHz < Freq ≤ 180 MHz 5

180 MHz < Freq ≤ 210 MHz 6

210 MHz < Freq ≤ 240 MHz 7

240 MHz < Freq ≤ 250 MHz 8

10 Analog modules

10.1 SAR ADC

Table 32. SAR ADC Table continues on the next page...

Table 32. SAR ADC (continued) Table continues on the next page...

1. Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for reference
2. VSS and VREFL should be shorted on PCB. 100mV difference between VSS and VREFL is for transient only (not for DC).
3. This is ADC Input range for ADC accuracy guaranteed in this input range only. For SoC Pin capability, see Operation
4. TUE spec for precision and standard channels is based on 12-bit level resolution.
5. Spec valid if potential difference between VDD_HV_A and VREFH should follow VDD_HV_A +0.1V >=VREFH >=

Figure 33. SAR ADC Input Circuit

10.2 Supply Diagnosis

The table below gives the specification for the on die supply diagnosis. Table 33. Supply Diagnosis

1. Required ADC sampling time specified by parameter AN_TADCSA needs to be used at the ADC conversion to guarantee

the specified accuracy. A smaller sampling time leads to a less accurate result.

1. If V15 > VDD_HV_A +100mV then the V15 measurement via anamux may be imprecise.
2. These specs will have degraded performance when used in extended supply voltage operation range, i.e. normal supply

voltage range specification is exceeded.

10.3 Low Power Comparator (LPCMP)

Table 34. Low Power Comparator (LPCMP) Table continues on the next page...

Table 34. Low Power Comparator (LPCMP) (continued) Table continues on the next page...

1. vdda is comparator HV supply and internally shorted to VDD_HV_A pin. vss is comparator ground
2. Difference at input > 200mV
3. Applied +/- (100 mV + VAHYST0/1/2/3 + max. of VAIO) around switch point
4. Applied +/- (30 mV + 2 x VAHYST0/1/2/3 + max. of VAIO) around switch point
5. 1 LSB = (vrefh_cmp - vrefl_cmp) /256. vrefh_cmp and vrefl_cmp are comparator reference high and low
6. Calculation method used: Linear Regression Least Square Method

pull up/down is recommended). VDD_HV_B. These channels must be disabled when VDD_HV_A goes below VDD_HV_B. Figure 34. Typical Hysteresis vs Vin level (VDD_HV_A = 3.3 V, High Speed Mode)

10.4 Temperature Sensor

The table below gives the specification for the on die temperature sensor. Table 35. Temperature Sensor

1. Required ADC sampling time specified by parameter TS_TADCSA needs to be used at the ADC conversion to guarantee

the specified accuracy. A smaller sampling time leads to a less accurate result.

1. Note: The temperature sensor measures the junction temperature Tj at the location where it is placed on die. The local Tj

is modulated by current and previous active state of the circuit elements on die.

1. The error caused by ADC conversion and provided temperature calculation formula is not included.

11 Clocking modules

11.1 FIRC

Table 36. FIRC

1. Startup time is for reference only.

11.2 SIRC

Table 37. SIRC

1. Startup time is for information only.

11.3 PLL

Table 38. PLL Table continues on the next page...

Table 38. PLL (continued)

1. For SSCG, jitter due to systematic modulation needs to be added as per applied modulation. Accumulated jitter
2. Jitter numbers are valid only at IP boundary and does not include any degradation due to IO pad for clock measurement.
3. Jitter numbers calculated by extrapolating RMS jitter numbers to +/- 7 sigma .

11.4 Fast External Oscillator (FXOSC)

Table 39. Fast External Oscillator (FXOSC) Table continues on the next page...

Table 39. Fast External Oscillator (FXOSC) (continued)

1. For bypass mode applications, the EXTAL pin should be driven low when FXOSC is in off/disabled state.
2. The startup time specification is valid only when the recommended crystal and load capacitors are used. For higher load

capacitances, the actual startup time might be higher.

1. The recommended gm setting to ensure extal swing < 2.75V at 8MHz in ALC-disabled mode is gm=4'b0010.

Recommended gm settings in ALC-disabled mode for all other supported frequencies and crystals remain the same. To ensure stable oscillations, FXOSC incorporates the feedback resistance internally. the crystal drive level rating. In such cases, contact NXP sales representative for selecting the correct crystal.

11.5 Slow Crystal Oscillator (SXOSC)

Table 40. Slow Crystal Oscillator (SXOSC)

1. Supports single frequency

12 Communication interfaces

12.1 LPSPI

of the transfer attributes are programmable. The following table provides timing characteristics for classic LPSPI timing modes.

1. All timing is shown with respect to 20% VDD_HV_A/B and 80% VDD_HV_A/B thresholds.
2. All measurements are with maximum output load of 30 pF, input transition of 1 ns and pad configured with fastest slew setting

Table 41. LPSPI Table continues on the next page...

Table 41. LPSPI (continued) Table continues on the next page...

Table continues on the next page...

1. For LPSPI0 instance, max. peripheral frequency is equal to AIPS_PLAT_CLK.
2. fperiph = LPSPI peripheral clock
3. Master Loopback mode: In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting

LPSPI_CFGR1[SAMPLE] bit as 1.

1. These specifications apply to the SPI operation, as master or slave, at up to 10 Mbps for the combinations not indicated

configurations. See table "LPSPI 20 MHz and 15 MHz Combinations.

1. LPSPI0 support up to 20MHz on fast pin.
2. Minimum configuration value for CR[PCSSCK] field is 3(0x00000011).
3. Minimum configuration value for CCR[SCKPCS] field is 3(0x00000011).
4. While selecting odd dividers, ensure Duty Cycle is meeting this parameter.

Figure 40. LPSPI Master Mode Timing (CPHA=0)

12.2 LPSPI0 20 MHz and 15 MHz Combinations

15 and 20 Mbps is supported on LPSPI0 only. Table 42. LPSPI0 20 MHz and 15 MHz Combinations

15 Mbps

Trace length should not exceed 11 inches for SCK pad when used in Master loopback mode.

12.3 Communication between two S32K388 devices

LPSPI2 in Slave 4x dataline half duplex mode on second device. Similarly LPSPI5, but for in opposite direction than LPSPI2 do.

Figure 44. Connection between two S32K388 devices Table 43. Pins and signals assignment for this communication.

12.3.1 Timing specification for S32K388 to S32K388 communication

Table 44. Timing specification for S32K388 to S32K388 communication

12.4 I2C

See I/O parameters for I2C specification.

12.5 FlexCAN characteristics

See I/O parameters for FlexCAN specification.

12.6 SAI electrical specifications

12.6.1 SAI Electrical Characteristics, Slave Mode

input transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97 V to 3.63 V. Table 45. SAI Electrical Characteristics, Slave Mode

1. The slave mode parameters (S15 - S22) assume 50% duty cycle on SAI_BCLK input. Any change in SAI_BCLK duty cycle

input must be taken care during the board design or by the master timing.

Figure 45. SAI slave mode

12.6.2 SAI Electrical Characteristics, Master Mode

input transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b 0. I/O operating voltage ranges from 2.97 V to 3.63 V. Table 46. SAI Electrical Characteristics, Master Mode Table continues on the next page...

Table 46. SAI Electrical Characteristics, Master Mode (continued) Figure 46. SAI master mode

12.7 Ethernet characteristics

12.7.1 Ethernet MII (100 Mbps)

configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97 V to 3.63 V. Table 47. Ethernet MII (100 Mbps) Table continues on the next page...

Table 47. Ethernet MII (100 Mbps) (continued) Figure 47. MII receive diagram

Figure 48. MII transmit diagram

12.7.2 Ethernet MII (200 Mbps)

configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97 V to 3.63 V. Table 48. Ethernet MII (200 Mbps) Table continues on the next page...

Table 48. Ethernet MII (200 Mbps) (continued) Figure 49. MII receive diagram

Figure 50. MII transmit diagram

12.7.3 Ethernet RMII

configured with DSE = 1'b1 and SRE = 1'b0. I/O operating voltage ranges from 2.97 V to 3.63 V. Table 49. Ethernet RMII Table continues on the next page...

Table 49. Ethernet RMII (continued) Figure 51. RMII receive diagram

Figure 52. RMII transmit diagram

12.7.4 Ethernet RGMII

configured with DSE = 1'b1 and SRE = 1'b0. Table 50. Ethernet RGMII

1. For 10 Mbps and 100 Mbps, Tcyc will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively.
2. RGMII timing specifications is valid for 3.3V nominal I/O pad supply voltage.

1. Output timing valid for maximum external load CL = 13.5pF, which is assumed to be a 5pF load at the end of a 50ohm, un-

Figure 53. RGMII Receive Timing Figure 54. RGMII Transmit Timing

12.7.5 MDIO timing specifications

2.97 V to 3.63 V. MDIO pin must have external Pull-up. Table 51. MDIO timing specifications Table continues on the next page...

Table 51. MDIO timing specifications (continued) Figure 55. MII/RMII serial management channel timing

12.8 QuadSPI

Reference Manual for register and bit descriptions. Program register value QuadSPI_FLSHCR[TCSS] = 4\`h3. Program register value QuadSPI_FLSHCR[TCSH] = 4\`h3.

Program register value QuadSPI_DLLCRA[SLV_FINE_OFFSET] to 4'b0001. Table 52. QuadSPI Quad 3.3V SDR 120MHz

1. This frequency specification is valid only if output valid time of external flash is ≤ 5.5ns, and if output valid time of

external flash is more than 5.5ns but ≤ 6.5ns, then maximum fSCK is 104MHz.

1. For S32K342 100HDQFP, tSDC spec would be 44%-56% when ENET and SAI active along with QuadSPI at

Table 53. QuadSPI Octal 3.3V DDR 100MHz tIH_DQS Input hold time (w.r.t.

1. Input timing assumes maximum input signal transition of 1 ns (20%/80%). DQS denotes external strobe provided by the
2. Where m=TCSS and n=TCSH-1.

The following table applies only to S32K388. Reference Manual for register and bit descriptions. Table 54. QuadSPI Quad 3.3V SDR 103.33MHz Table continues on the next page...

Table 54. QuadSPI Quad 3.3V SDR 103.33MHz (continued) tIH_SCK Input hold time (w.r.t.

1. Input timing assumes maximum input signal transition of 1ns (20%/80%).
2. Where m=TCSS and n=TCSH-1.

The following table applies to S32K328, S32K338, S32K348, S32K358. Reference Manual for register and bit descriptions. Set FLSHCR[TCSS]=2 and FLSHCR[TCSH]=5. Table 55. QuadSPI Octal 3.3V DDR 120MHz Table continues on the next page...

Table 55. QuadSPI Octal 3.3V DDR 120MHz (continued) tIH_DQS Input hold time (w.r.t.

1. Input timing assumes an input signal transition of 1 ns (20%/80%). DQS denotes external strobe provided by the Flash.

The following table applies only to S32K388. Reference Manual for register and bit descriptions. Table 56. QuadSPI Quad 3.3V SDR 125MHz tIH_SCK Input hold time (w.r.t.

1. Input timing assumes maximum input signal transition of 1ns (20%/80%).
2. Where m=TCSS and n=TCSH-1.

Table 57. uSDHC SDR electrical specifications

1. In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7V to 3.6V.
2. Output timing valid for maximum external load CL = 25pF, which is assumed to be a 10pF load at the end of a 50Ohm,

un-terminated, 3.5 inch microstrip trace on standard FR4 (1.5pF/inch), (25pF total with margin).

1. In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed

mode, clock frequency can be any value between 0–50 MHz.

1. In normal (full) speed mode for MMC card, clock frequency can be any value between 0–25 MHz. In high-speed mode,

clock frequency can be any value between 0–50 MHz.

1. The SDHC_CLK rise/fall time specification applies to the input clock transition required in order to meet the output delay

pad specifications for detail.

1. Input timing assumes an input signal slew rate of 3ns (20%/80%).

Figure 58. SD/eMMC4.3 High Speed Mode Interface Timing Table 58. uSDHC DDR electrical specifications Table continues on the next page...

Table 58. uSDHC DDR electrical specifications (continued)

1. Output timing valid for maximum external load CL = 25pF, which is assumed to be a 10pF load at the end of a 50Ohm,

un-terminated, 3.5 inch microstrip trace on standard FR4 (1.5pF/inch), (25pF total with margin).

1. The SDHC_CLK rise/fall time specification applies to the input clock transition required in order to meet the output delay

pad specifications for detail.

1. Input timing assumes an input signal slew rate of 3ns (20%/80%).

Figure 59. SD/eMMC4.4/4.41 DDR50 Mode Interface Timing

12.10 LPUART specifications

See I/O parameters for LPUART specifications.

13 Debug modules

13.1 Debug trace timing specifications

input transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0. Table 59. Debug trace timing specifications Figure 60. Trace CLKOUT specifications

13.2 SWD electrical specifications

transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0. Table 60. SWD electrical specifications Table continues on the next page...

13.3 JTAG electrical specifications

The following table describes the JTAG electrical characteristics. These specifications apply to JTAG and boundary scan. Measurements are with maximum output load of 30pF, input transition of 1ns and pad configured with DSE = 1'b1 and SRE = 1'b0. Table 61. JTAG electrical specifications

1. Cycle time is 30ns assuming full cycle timing. Cycle time is 60ns assuming half cycle timing.
2. This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions.
3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

Figure 65. Boundary Scan Timing

14 Thermal Attributes

14.1 Description

The tables in the following sections describe the thermal characteristics of the device.

14.2 Thermal characteristics

• Junction temperature of the device does not solely depend on package thermal resistance but is also a function of chip power dissipation, PCB attributes, environmental conditions (ambient temperature & air flow) and cumulative effects of other heat generating ICs on the PCB.
• The appropriate thermal design must be carried out on package so that it can safely dissipate the necessary amount of power needed for it to function properly without exceeding the maximum junction temperature. This may involve adding a cooling solution on the package, creating thermal enhancements on the PCB and improving environmental conditions.
• The customer is encouraged to use the package model to perform design and risk assessment through simulations. Package models in FloTHERM or Icepak formats can be obtained under NDA from the sales team. Thermal Ratings
• The table below is the package thermal ratings for LQFP, HDQFP & MAPBGA package variants. These numbers are derived through simulations based on standardized tests as described in the footnotes. NXP Semiconductors Thermal Attributes S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 128 / 146

• Thermal resistance data in this report is solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not meant to predict the performance of a package in an application-specific environment : NXP Semiconductors Thermal Attributes S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 129 / 146

Table 62. Thermal characteristics

1. Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is solely for a thermal performance
2. Thermal test board meets JEDEC specification for this package (JESD51-9).

15 Dimensions

15.1 Obtaining package dimensions

Package dimensions are provided in the package drawings. To find a package drawing, go to nxp.com and perform a keyword search for the drawing’s document number: Package option Document Number 48-pin LQFP 98ASH00962A 257-ball MAPBGA 98ASA01483D 172-pin HDQFP 98ASA01107D 100-pin HDQFP 98ASA01570D 172-pin HDQFP_EP 98ASA01667D 289-ball MAPBGA 98ASA01216D The following table lists the changes in this document. Rev 7, Apr 2023

• Updated caution in overview and updated feature comparision.
• In "S32K3xx chip's feature comparison" section clarified via footnote that S32K388 supports QuadSPI SDR modes only.
• Updated S32K312 and S32K388 block diagram.
• QFP package references updated to HDQFP.
• In section "Absolute maximum ratings" added footnote to VDD_DCDC as "Voltage at VDD_DCDC cannot be higher than VDD_HV_A".
• In section "Voltage and current operating requirements" added footnote to V15 as "Min and Max values are applicable only for non-SMPS mode where V15 is sourced externally".
• Updated descriptions and condition in following sections: — Boot time, HSE firmware not installed — Boot time, HSE firmware installed — HSE firmware memory verification time examples
• In section "Recommended Decoupling Capacitors" updated variants for COUT V11.
• In section "V15 regulator (SMPS option) electrical specifications" added CBULK_SMPS.
• In section "V15 regulator (BJT option, NPN ballast transistor control) electrical specifications" added V15 input.
• In section "SAR ADC" updated paragraph "All below specs are applicable...". and added footnote to TUE as "Spec valid if potential difference between VDD_HV_A.." amd figure updated to show VDD_HV_A instead of VREFH.
• In LPCMP section changed ACMP0 to LPCMP0.
• In PLL added paragraph to mention Auxilliary PLL applicability and footnote updated to mention "Accumulated jitter specification is not valid with SSCG". NXP Semiconductors Dimensions S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 131 / 146

Rev 7, Apr 2023

• In PLL added CLKIN_VIL_EXTAL_BYPASS and CLKIN_VIH_EXTAL_BYPASS specifications.
• Added section "Communication between two S32K388 devices".
• In section "Ethernet MII (100 Mbps)" updated specification for 10 and 100 Mbps.
• In section "Ethernet RGMII" added paragraph "The following timing specs are defined at the device".
• In section "MDIO timing specifications" updated MDC3 for GPIO[113]pad of S32K388.
• Added following QuadSPI modes for S32K388: — QuadSPI Quad 3.3V SDR 103.33MHz — QuadSPI Quad 3.3V SDR 125MHz
• In QuadSPI modes, mentioned the applicability to the devices in K3 family.
• In "Debug trace timing specifications" section added row for 125 MHz for S32K388.
• Updated "Thermal characteristics" to add information on Thermal design and characterstics. Rev 6, Nov 2022
• Added S32K388 decoupling capacitor diagrams.
• In section "Power mode transition operating behavior" tMODE_STDBYEXIT time is added as 80 us.
• In "V15 regulator (SMPS option) electrical specifications" section changed V15 output supply from 1.51V to 1.5V.
• In "5.0V (4.5V - 5.5V) GPIO Output AC Specification" — TR_TF_50_F with condition DSE=1, SRE=0, Capacitance=25pF changed from 0.9 to 1.9 ns. — TR_TF_50_F with condition DSE=0, SRE=0, Capacitance=50pF changed from 5.3 to 6.0 ns. — TR_TF_50_F with condition DSE=0, SRE=1, Capacitance=50pF changed from 7.7 to 9.0 ns. — TR_TF_50_F with condition DSE=1, SRE=1, Capacitance=50pF changed from 5.1 to 6.5 ns.
• In "3.3V (2.97V - 3.63V) GPIO Output AC Specification" — TR_TF_33_F with condition DSE=0, SRE=0, Capacitance=25pF changed from 4 to 4.5 ns. — TR_TF_33_F with condition DSE=1, SRE=0, Capacitance=25pF changed from 2 to 2.5 ns. — TR_TF_33_F with condition DSE=0, SRE=0, Capacitance=50pF changed from 7 to 8 ns.
• In sectioon "Fast External Oscillator (FXOSC)" added EXTAL_SWING_PP and VSB specs and related footnote. Rev 5.2, Oct 2022
• Added S32K310 and S32K388 where applicable.
• Updated "overview".
• In "features": — Updated M7 support upto 300 MHz. — Updated Ethernet instance from one to two. — Added Support to AES accelerator(for K388 only) NXP Semiconductors

Revision history

S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 132 / 146

Rev 5.2, Oct 2022 — Removed I3C instances.

• Added S32K310 and S32K388 block diagram and updated others to remove I3C.
• Updated "Feature comparison".
• Updated "Ordering information".
• In "Absolute maximum ratings": — Added symbol "V15" as "Voltage sensing input" for S32K388 and changed max value to 2.75V for S32K358. — Added symbol "V11" for S32K388.
• In "Voltage and current operating requirements": — Added symbol "V15" as "Voltage sensing input" for S32K388 and updated conditions for V15 and V15_extended. Also added a footnote to V15_extended as You must ensure that the junction temperature"...". — Added symbol "V11" for S32K388. — Updated link to download hardware design guidelines document.
• In section "Thermal operating characteristics" added sentence as "For S32K388, applications running at 125°C
• Added S32K388 power management diagram and added other variants to diagrams as applicable.
• In section "Power mode transition operating behavior, added condition for tMODE_STDBYEXIT_FAST as "FIRC ON @48MHz in Standby mode".
• In section "Supply monitoring" added sentence as "Certain monitors are present on certain...".
• In section "Recommended Decoupling Capacitors" added COUT_V11 for S32K388 and updated decouling capacitor diagrams.
• Section "SMPS regulator electrical specifications" changed to "V15 regulator (SMPS option) electrical specifications" and following changes done: — Added paragraphs at the begining of table as: ◦ "Some devices (S32K358, S32K348, S32K338, and S32K328)...." ◦ "The table below describes the electrical parameters for the components needed to implement an SMPS...." ◦ Updated existing to include inductor "The chip hardware design guidelines document lists the recommended...". ◦ Added figure, removed redundant sentence "The table below describes the electrical parameters.." and updated part numbers. — Added "External Schottky diode average forward current" as 2A. — Added "External P-channel MOSFET threshold voltage" as 2V.
• Section "NPN Ballast Transistor Control Specification" renamed to "V15 regulator (BJT option, NPN ballast transistor control) electrical specifications" and updated the following: — added paragraph "Some devices (S32K358, S32K348, S32K338, S32K328, S32K344, S32K324, S32K314, S32K342, S32K322, S32K341) support ...." — Updated ballast circuit figure.
• Added section "V11 regulator (NMOS ballast transistor control) electrical specifications".
• In section "Supply currents": NXP Semiconductors

S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 133 / 146

Rev 5.2, Oct 2022 — added template for S32K388. — added values for S32K342. — added S32K310 along with S32K311.

• GMAC term is added along with EMAC in "Operating mode" section.
• Updated GPIO specs to clarify leakage specifications.
• In SAR ADC section, removed TBD from RS max specification.
• In section "SXOSC", Oscillator Analog circuit supply current max updated to 4 uA.
• In section "LPSPI", updated tV and tHO for S32K358 and a note is added as "15 and 20 Mbps is supported on LPSPI0 only.".
• In section "uSDHC SDR electrical specifications" relaxed tISU for 25 MHz and 400 KHz from 4.8 to 6.3 ns.
• Deleted I3C specifications
• Updated "Thermal characteristics"
• Added 48-pin LQFP package drawing number in "Obtaining package dimensions" section.
• Editorial updates. Rev 4, April 2022
• Removed S32K312 from preliminary list from the title of the document and "Overview".
• In features on first page added MAPBGA289 to the package list and updated GPIO pins upto 235.
• Removed "NDA required" term from all block diagrams.
• In "Ordering information", added HDQFP-EP package suffix.
• In section "Absolute maximum ratings", and "Voltage and current operating requirements", added S32K341 variant to
• In section “Voltage and current operation requirement”, the footnote attached to supply ramp rate is updated as “ The MCU Supply ramp applicable to the MCU input/external supplies...".
• Updated capacitor symbol to non-polarity in following figures at V25 and V11: — Power management system - S32K344, S32K324, S32K341, S32K314, S32K342, and S32K322. — Power management system - S32K312, S32K311
• In "Power management system - S32K358" figure, updated connections to optional circuit with dashed lines for PGATE_CTRL and VSS_DCDC.
• In section “SMPS regulator electrical specifications”, added a sentence “The chip hardware design guidelines documents lists the recommended part numbers of PMOS & Schottky diode."
• In table "SMPS regulator electrical specifications" : — The typ. value of "External coil inductance" changed from 5 to 4.7uH. — Added “Schottky diode reverse voltage” with Min value 5.0 V. — Added “Schottky diode forward current” with Min value 1.0 A.
• In section "SMPS regulator electrical specifications" changed "COUT_V15" to "COUT_V15_SMPS" to match it with corresponding figure. NXP Semiconductors

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Rev 4, April 2022

• In section "Recommended Decoupling Capacitors" changed "COUT_V15" to "COUT_V15_NPN" to match it with corresponding figure.
• In section "Recommended Decoupling Capacitors", following footnotes updated: — Footnote attached to CDEC "Optionally, 1 nF capacitors can be added...". — Footnote attached to CBULK "For devices where the VDD_HV_B domain is present, if the VDD_HV_B...". — Added footnote to CBULK "These capacitors must be placed close to the source."
• In section "Recommended Decoupling Capacitors", updated and added decoupling capacitors diagrams.
• In section "NPN Ballast Transistor Control Specification" added specification for VDD_HV_NPN.
• Updated "Ballast circuit" figure under section " NPN Ballast Transistor Control Specification".
• Current IDD specs are updated for S32K12 for following : — Table “STANDBY mode supply currents” — Table “Low speed RUN mode supply currents” — Table “RUN mode supply currents (peripherals disabled)” — Table “Example RUN mode configuration supply current”
• In section “supply current”, Removed table “Recommended current limits in board design” and related sentence “The power supplies for the voltage ...."
• In section “Power management”, added section ”Cyclic wake-up current” and removed table "Low-power, cyclic operation mode" from supply currents.
• In section "GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)",with symbol "ILKG_33_S", the condition has been changed from PTC0 to PTD0.
• In section "5.0V (4.5V - 5.5V) GPIO Output AC Specification": — for Symbol "TR_TF_50_F" with condition "DSE=0, SRE=1, Capacitance=50pF" Min changed from "2.8" to "1.9". — for Symbol "TR_TF_50_F" with condition "DSE=0, SRE=1, Capacitance=50pF" Max changed from "10.2" to "7.7". — for Symbol "TR_TF_50_F" with condition "DSE=1, SRE=1, Capacitance=50pF" Min changed from "1.9" to "1.3". — for Symbol "TR_TF_50_F" with condition "DSE=1, SRE=1, Capacitance=50pF" Max changed from "6.7" to "5.1". — for Symbol "TR_TF_50_F" with condition "DSE=0, SRE=0, Capacitance=50pF" Min changed from "2.0" to "1.0". — for Symbol "TR_TF_50_F" with condition "DSE=0, SRE=0, Capacitance=50pF" Max changed from "7.4" to "5.3". — for Symbol "TR_TF_50_F" with condition "DSE=1, SRE=0, Capacitance=25pF" Min changed from "0.9" to "0.3". — for Symbol "TR_TF_50_F" with condition "DSE=1, SRE=0, Capacitance=25pF" Max changed from "3.0" to "0.9". — for Symbol "TR_TF_50_F" with condition "DSE=1, SRE=1, Capacitance=25pF" Min changed from "1.3" to "0.9". — for Symbol "TR_TF_50_F" with condition "DSE=1, SRE=1, Capacitance=25pF" Max changed from "5.1" to "4.1". — for Symbol "TR_TF_50_F" with condition "DSE=1, SRE=0, Capacitance=50pF" Min changed from "1.6" to "0.9". — for Symbol "TR_TF_50_F" with condition "DSE=1, SRE=0, Capacitance=50pF" Max changed from "3.6" to "3.0". — for Symbol "TR_TF_50_F" with condition "DSE=0, SRE=0, Capacitance=25pF" Min changed from "1.0" to "0.4". — for Symbol "TR_TF_50_F" with condition "DSE=0, SRE=0, Capacitance=25pF" Max changed from "5.3" to "3.1". — for Symbol "TR_TF_50_F" with condition "DSE=0, SRE=1, Capacitance=25pF" Min changed from "1.9" to "1.5". NXP Semiconductors

S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 135 / 146

Rev 4, April 2022 — for Symbol "TR_TF_50_F" with condition "DSE=0, SRE=1, Capacitance=25pF" Max changed from "7.7" to "6.1".

• In section “SAR ADC“, the footnote attached to “ADC Total Unadjusted Error” is updated as “TUE spec for precision and standard channels is based on 12-bit level resolution”.
• In section "Supply Diagnosis", for Symbol "AN_ACC" and "AN_T_on" footnote added "These specs will have degraded performan..."
• In section "Fast External Oscillator (FXOSC)", for Symbol "TFXOSC" description changed from "Fxosc start up time" to "Fxosc start up time (ALC enabled)".
• In section "Fast External Oscillator (FXOSC)", removed the crystal part numbers and related information which includes sentence "To ensure stable oscillations, FXOSC incorporates the feedback resistance internally.".
• In section "LPSPI", updated the sentence updated maximum output load of 50pF to 30pF.
• In section "LPSPI", footnote attached to "fperiph" is udated to mention clock name instead of frequency. "For LPSPI0
• In section "I3C Push-Pull Timing Parameters for SDR Mode", Symbol "tV" and tHI are deleted.
• Added section "Ethernet RGMII".
• In all QuadSPI modes updated trace length from 3 inches to 2 inches.
• Added "QuadSPI Octal 3.3V DDR 100MHz" mode.
• Deleted "QuadSPI Quad 3.3V DDR 80MHz" mode.
• In section "QuadSPI Octal 3.3V DDR 120MHz" : — For symbol “tOD_DATA”, Max. value changed from “2.567” to “ 2.934”. — For symbol “tOD_CS”, Min value has been changed from “3.015” to “3.016” and Max. value changed from “-1.33” to “-0.766”. — For symbol “tDVW”, Min value has been changed from “2.314” to “2.518”. — For symbol “tIH_DQS”, Min value has been changed from “2.767” to “3.134”.
• uSDHC specifications are updated thoroughly.
• In "Thermal characteristics": — Updated table header to include all variants. — For S32K312 100-HDQFP updated RϴJA from 34.8 to 38 °C/W and RϴJT from 0.6 to 0.8 °C/W. — For S32K3x4, 257MAPBGA updated RϴJA from 27 to 26.8 °C/W.
• Updated Legal information. Rev 3, Oct 2021
• Datasheet classification is updated to "Technical data" for S32K344.
• In section "Supply currents" added values for 85C (typ and max) and updated 105 (max) and 125 (max) values for S32K344.
• In front page features, added HDQFP172 with Exposed pad (EP) option and information on I3C. NXP Semiconductors

S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 136 / 146

Rev 3, Oct 2021

• In "Feature comparision" section added footnote to add information about HDQFP172 with Exposed pad (EP) package for S32K3x8 devices.
• VDD_HV_SMPS is changed to VDD_DCDC throughout.
• In section "Absolute maximum ratings", footnote attached to "I_INJSUM_DC_ABS" is exteded to add information "See application note AN4731 for...".
• Figure "Power management system - S32K344, S32K324, S32K341, S32K314, S32K342, and S32K322." is updated to add COUT_V15 capacitor.
• Figure "Power management system - S32K358" is updated to add COUT_V15 capacitor and optional circuit explained in the notes.
• In section "SMPS regulator electrical specifications", COUT_V15 is added to "External bypass capacitor".
• Figure "Package decoupling capacitor pinout diagram" is updated to show HDQFP172-EP package.
• Table title "Current limit requirements for board design" is changed to "Recommended current limits in board design" and added a note as "The power supplies for the voltage rails must be...".
• In section "GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)": — for ILKG_33_S updated condition to update pins which has Analog Function Count=2/3 — for ILKG_33_M updated condition to update pins which has Analog Function Count=1 — added ILKG_33_M with condition "PTE8 and PTD6" — udpdated ILKG_33, -120 nA (min) and 120 nA (max). — updated condition of IOH_*, IOL_* to add < and > symbols. — added IOHT specification.
• In section "GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)": — for ILKG_50_S updated condition to update pins which has Analog Function Count=2/3 — for ILKG_50_M updated condition to update pins which has Analog Function Count=1 — added ILKG_50_M with condition "PTE8 and PTD6" — udpdated ILKG_50, -150 nA (min) and 150 nA (max). — updated condition of IOH_*, IOL_* to add < and > symbols. — added IOHT specification.
• In section "5.0V (4.5V - 5.5V) GPIO Output AC Specification": — for Symbol "TR_TF_50_S" with condition "Capacitance=25pF" Min changed from "TBD" to "5" — for Symbol "TR_TF_50_S" with condition "Capacitance=25pF" Max changed from "TBD" to "21" — for Symbol "TR_TF_50_S" with condition "Capacitance=50pF" Min changed from "TBD" to "10" — for Symbol "TR_TF_50_S" with condition "Capacitance=50pF" Max changed from "TBD" to "31" — for Symbol "TR_TF_50_SP" with condition "DSE=0, Capacitance=25pF" Min changed from "5" to "3.5" — for Symbol "TR_TF_50_SP" with condition "DSE=1, Capacitance=25pF" Min changed from "2.4" to "1.2" NXP Semiconductors

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Rev 3, Oct 2021 — for Symbol "TR_TF_50_SP" with condition "DSE=0, Capacitance=50pF" Min changed from "8.9" to "7.1" — for Symbol "TR_TF_50_SP" with condition "DSE=1, Capacitance=50pF" Min changed from "4.1" to "3.4" — for Symbol "TR_TF_50_M" with condition "DSE=0, SRE=0, Capacitance=25pF" Min changed from "2.5" to "1.8" — for Symbol "TR_TF_50_M" with condition "DSE=0, SRE=1, Capacitance=25pF" Min changed from "3" to "2.5" — for Symbol "TR_TF_50_M" with condition "DSE=1, SRE=0, Capacitance=25pF" Min changed from "1" to "0.8" — for Symbol "TR_TF_50_F" with condition "DSE=0, SRE=0, Capacitance=25pF" Max changed from "4.3" to "5.3" — for Symbol "TR_TF_50_F" with condition "DSE=1, SRE=0, Capacitance=25pF" Max changed from "1.6" to "3.0"

• In section "3.3V (2.97V - 3.63V) GPIO Output AC Specification": — for Symbol "TR_TF_33_S" with condition "Capacitance=25pF" Min changed from "TBD" to "6.5" — for Symbol "TR_TF_33_S" with condition "Capacitance=25pF" Max changed from "TBD" to "28" — for Symbol "TR_TF_33_S" with condition "Capacitance=50pF" Min changed from "TBD" to "11" — for Symbol "TR_TF_33_S" with condition "Capacitance=50pF" Max changed from "TBD" to "43" — for Symbol "TR_TF_33_SP" with condition "DSE=0, Capacitance=25pF" Min changed from "5" to "4" — for Symbol "TR_TF_33_SP" with condition "DSE=1, Capacitance=25pF" Min changed from "2.4" to "2.0" — for Symbol "TR_TF_33_M" with condition "DSE=0, SRE=0, Capacitance=25pF" Min changed from "3.2" to "2.2" — for Symbol "TR_TF_33_M" with condition "DSE=0, SRE=1, Capacitance=25pF" Min changed from "3.8" to "3.0" — for Symbol "TR_TF_33_M" with condition "DSE=1, SRE=0, Capacitance=25pF" Min changed from "1" to "0.8" — for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=0, Capacitance=25pF" Min changed from "1.1" to "0.5" — for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=0, Capacitance=25pF" Max changed from "7.0" to "4" — for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=1, Capacitance=25pF" Min changed from "2.6" to "2.1" — for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=1, Capacitance=25pF" Max changed from "11.0" to "9" — for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=0, Capacitance=25pF" Min changed from "0.8" to "0.4" — for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=0, Capacitance=25pF" Max changed from "3.4" to "2" — for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=1, Capacitance=25pF" Min changed from "1.5" to "1.2" — for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=1, Capacitance=25pF" Max changed from "7.8" to "6.4" — for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=0, Capacitance=50pF" Min changed from "2.5" to "1.1" — for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=0, Capacitance=50pF" Max changed from "10.8" to "7" — for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=1, Capacitance=50pF" Min changed from "3.6" to "2.6" — for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=1, Capacitance=50pF" Max changed from "15.0" to "11" — for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=0, Capacitance=50pF" Min changed from "1.5" to "0.8" — for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=0, Capacitance=50pF" Max changed from "5.5" to "4.2" — for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=1, Capacitance=50pF" Min changed from "2.2" to "1.5" — for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=1, Capacitance=50pF" Max changed from "10.0" to "7.8" to determine the most appropriate settings for AVGS." and removed footnote from RS specification. NXP Semiconductors

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Rev 3, Oct 2021

• In section "SAR ADC", added specifications for CP1, CP2 and RSW1 corresponding to all channels, shared channels and precision channels. Also added the related figure.
• In section "PLL", removed some non-applicable footnotes.
• In section "LPSPI", added information before the table The Low Power Serial Peripheral Interface (LPSPI) provides a
• In section "LPSPI0 20 MHz and 15 MHz Combinations", added note as "Trace length should not exceed 11 inches for SCK pad when used in Master loopback mode."
• Added "I3C" specifications.
• In section "Ethernet MII (100 Mbps)", for "RXCLK frequency" typ value moved to max.
• In section "Ethernet RMII", added paragraph "The following timing specs are defined at the device I/O pin and must
• In section "QuadSPI Quad 3.3V SDR 120MHz", for Symbol "tSDC" footnote added "For S32K342 100HDQFP, tSDC spec would be ..."
• In section "QuadSPI Quad 3.3V SDR 120MHz" added sentence "Program register value QuadSPI_DLLCRA[SLV_FINE_OFFSET] to 4'b0001.".
• In section "QuadSPI Octal 3.3V DDR 120MHz", Symbol "tSCK" min is calrified, condition updated to External DQS and "tSCK" with condition Internal Loopback is deleted.
• In section "QuadSPI Octal 3.3V DDR 120MHz", Symbol "tSDC" condition updated to External DQS and "tSDC" with condition Internal Loopback is deleted..
• In section "QuadSPI Octal 3.3V DDR 120MHz", specifications tISU_PCS, tIH_PCS, tCK2CKmin and tCK2CKmax are deleted. Rev 2, Aug 2021
• Added section "Overview".
• In block diagrams: — S32K311/S32K312/S32K314 removed "Scalable ARM M7 core in Lock step" and added "Single ARM M7 core". — S32K322/S32K324 removed "Scalable ARM M7 core in Lock step" and added "Two independent ARM M7 cores".
• In "Absolute maximum ratings" and "Voltage and current operating requirements": — Some general footnotes are moved to top of table — VDD_HV_SMPS added footnotes
• In "Voltage and current operating requirements" for VREFH extended footnote "VREFH should always be equal to...".
• Updated title - Power management system - S32K344, S32K324, S32K341, S32K314, S32K342, and S32K322.
• In figure "Power management system - S32K358" updated double bond to triple bond.
• In section "Recommended Decoupling Capacitors" added COUT_V11 with typ as 1 uF.
• Added section "Power mode transition operating behaviors" and its subsections: — Power mode transition operating behaviour — Boot time, HSE firmware not installed NXP Semiconductors

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Rev 2, Aug 2021 — Boot time, HSE firmware installed — HSE firmware memory verification time examples

• Moved information from "Supply monitoring" to "Supply diagnosos" and attached it to "AN_ACC". The information is "If V15 > VDD_HV_A +100mV then..."
• Updated figure "Package decoupling capacitor pinout diagram" to add 289 MapBGA
• Section "Flash memory program and erase specifications" updated thoroughly.
• In section "Flash memory module life specifications" removed footnotes 1 and 2.
• In section "Data retention vs program/erase cycles" added sentence before related to figure "The spec window represents qualified limits.".
• In section "Flash memory AC timing specifications": — Updated register naming representation — Added footnote to tdrcv min as " In extreme cases (1 block configurations)...". — Max updated to "50 system clock periods" for taistop
• Ins ection "Flash memory read timing parameters" mantioned part numbers for each table as applicable.
• >In section "SAR ADC", for Symbol "fAD_CK" added new spec and max updated to 120.
• In section "FIRC", Symbol "IFIRC" is deleted.
• In section "SIRC", Symbol "Ivdda" with condition "On state" is deleted.
• In section "PLL", clarification added in condition column for jitter specifications.
• In section "Fast External Oscillator (FXOSC)", for Symbol "FREQ_BYPASS", "TRF_BYPASS" and "CLKIN_DUTY_BYPASS" footnote added "For bypass mode applications, the EXTAL ...".
• In section "Fast External Oscillator (FXOSC)", for Symbol "TFXOSC" footnote added "The startup time specification is valid ...".
• In section "Fast External Oscillator (FXOSC)", Symbol "IFXOSC" specs are merged into one and description and condition updated.
• In section "LPSPI", Symbol "tSPSCK" with condition "Slave_10Mbps" is added.
• In section "LPSPI", Symbol "tSPSCK" with condition "Master_10Mbps" is added.
• Updated title to mention LPSPI0 of "LPSPI0 20 MHz and 15 MHz Combinations", and updated header "20Mbps" to "20Mbps (In loopback mode only)".
• In "I3C" section, added two sentences.
• Updated "QuadSPI" sections.
• Editorial updates. Rev 2 Draft B, Mar 2021
• Updated "block diagrams" and "Feature comparison"
• Updated "Ordering information" to add 289 pagkage and removed one. NXP Semiconductors

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Rev 2 Draft B, Mar 2021

• In section "Absolute maximum ratings", Symbol "VDD_HV_SMPS" is added.
• In section "Absolute maximum ratings", for Symbol "I_INJPAD_DC_ABS" and "I_INJSUM_DC_ABS" footnote updated "When input pad voltage levels are close ...".
• In section "Voltage and current operating requirements", Symbol "IINJSUM_DC_OP" and "IINJPAD_DC_OP" condition is updated
• In section "Voltage and current operating requirements", Symbol "VDD_HV_SMPS" is added.
• In section "Voltage and current operating requirements", for Symbol "I_INJPAD_DC_ABS" and "I_INJSUM_DC_ABS" footnote updated "When input pad voltage levels are close ...".
• In section "Power management": — "Power management system - S32K344, S32K324, S32K314" figure updated. — "Power management system - S32K312, S32K311" figure updated. — "Power management system - S32K358" figure added.
• In section "Supply Monitoring", Symbol "HVD_V15" is added.
• In section "Supply Monitoring", for "LVD_VDD_HV_A", symbol and description updated.
• Added section "SMPS regulator electrical specifications"
• In section "NPN Ballast Transistor Control Specification", fig with title "Ballast circuit" is changed.
• In section "Supply currents" and "operating mode" tables are updated.
• In section "GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)", fig with title "Reference Load Diagram" is changed.
• In section "GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)", footnote updated "A positive value is leakage flowing into...".
• In section "GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)", Symbol "ILKG_50_S_PTE13" with condition "PMC VRC_CTRL pin" is added.
• In section "GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)", footnote updated "A positive value is leakage flowing into...".
• In section "GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)", fig with title "Reference Load Diagram" is changed.
• In section "Flash memory specification", added specs for 512KB and 2MB specifications.
• In table "Flash memory AC timing specifications", taistop max updated.
• Updated "Flash Read Wait State Settings"
• In section "Low Power Comparator (LPCMP)", updated IDLSS typ to 17uA.
• In section "Low Power Comparator (LPCMP)", updated INL and DNL.
• In section "Low Power Comparator (LPCMP)", updated paragraph "For devices where the VDD_HV_B domain is present..."
• In "Low Power Comparator (LPCMP)" added hysterisis plots.
• In section "PLL", symbol "FPLL_out" description updated to add (PLL_PHIn_CLK)
• In section "PLL", "IPLL_V25" deleted.
• In section "PLL", updated jitter specifications.
• In section "FXOSC", updated paragraph "To improve the FXOSC jitter and duty cycle performance...". NXP Semiconductors

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Rev 2 Draft B, Mar 2021

• In section "SXOSC", updated description of "ISXOSC" to Oscillator Analog circuit supply current.
• Added section "I3C".
• Added QuadSPI DDR electrical specifications for Octal and Quad.
• Added uSDHC specifications.
• Updated "Thermal characteristics" and "Obtaining package dimensions" Rev 2 Draft A, Nov 2020
• Updated features to show maximum memory support up to 8 MB.
• Added information for S32K341.
• Updated "Block diagrams".
• Updated "Feature comparision"
• Updated "Thermal characterstics" to add data for S32K312 and S32K342.
• Added document number for 172-pin HDQFP package in section "Obtaining package dimensions" NXP Semiconductors

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Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. NXP Semiconductors Legal information S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 143 / 146

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AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, μVision, Versatile — are trademarks and/or registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere. The related technology may be protected by any or all of patents, copyrights, designs and trade secrets. All rights reserved. Bluetooth — the Bluetooth wordmark and logos are registered trademarks owned by Bluetooth SIG, Inc. and any use of such marks by NXP Semiconductors is under license. EdgeLock — is a trademark of NXP B.V. elQ — is a trademark of NXP B.V. I2C-bus — logo is a trademark of NXP B.V. NXP SECURE CONNECTIONS FOR A SMARTER WORLD — is a trademark of NXP B.V. SafeAssure — is a trademark of NXP B.V. SafeAssure — logo is a trademark of NXP B.V. SuperFlash This product uses SuperFlash®technology. SuperFlash® is a registered trademark of Silicon Storage Technology, Inc. Synopsys & Designware — are registered trademarks of Synopsys, Inc. Synopsys — Portions Copyright © 2021 Synopsys, Inc. Used with permission. All rights reserved. NXP Semiconductors Legal information S32K3xx Data Sheet, Rev. 7, 04/2023 Data Sheet: Technical Data Preliminary Information 145 / 146

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2023. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 04/2023 Document identifier: S32K3XX