S32K116

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Document overview

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Technical content

• Supports S32K116, S32K118, S32K142, S32K142W, S32K144, S32K144W, S32K146, and S32K148 – Technical information for S32K142W and S32K144W device families is preliminary until these devices achieve qualification
• The following two attachments are available with the Datasheet: – S32K1xx_Orderable_Part_Number_ List.xlsx – S32K1xx_Power_Modes_Configuration.xlsx Key Features
• Operating characteristics – Voltage range: 2.7 V to 5.5 V – Ambient temperature range: -40 °C to 105 °C for HSRUN mode, -40 °C to 150 °C for RUN mode
• Arm™ Cortex-M4F/M0+ core, 32-bit CPU – Supports up to 112 MHz frequency (HSRUN mode) with 1.25 Dhrystone MIPS per MHz – Arm Core based on the Armv7 Architecture and Thumb®-2 ISA – Integrated Digital Signal Processor (DSP) – Configurable Nested Vectored Interrupt Controller (NVIC) – Single Precision Floating Point Unit (FPU)
• Clock interfaces – 4 - 40 MHz fast external oscillator (SOSC) with up to 50 MHz DC external square input clock in external clock mode – 48 MHz Fast Internal RC oscillator (FIRC) – 8 MHz Slow Internal RC oscillator (SIRC) – 128 kHz Low Power Oscillator (LPO) – Up to 112 MHz (HSRUN) System Phased Lock Loop (SPLL) – Up to 20 MHz TCLK and 25 MHz SWD_CLK – 32 kHz Real Time Counter external clock (RTC_CLKIN)
• Power management – Low-power Arm Cortex-M4F/M0+ core with excellent energy efficiency – Power Management Controller (PMC) with multiple power modes: HSRUN, RUN, STOP, VLPR, and VLPS. Note: CSEc (Security) or EEPROM writes/ erase will trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to execute simultaneously. The device will need to switch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase. – Clock gating and low power operation supported on specific peripherals.
• Memory and memory interfaces – Up to 2 MB program flash memory with ECC – 64 KB FlexNVM for data flash memory with ECC and EEPROM emulation. Note: CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to execute simultaneously. The device will need to switch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase. – Up to 256 KB SRAM with ECC – Up to 4 KB of FlexRAM for use as SRAM or EEPROM emulation – Up to 4 KB Code cache to minimize performance impact of memory access latencies – QuadSPI with HyperBus™ support
• Mixed-signal analog – Up to two 12-bit Analog-to-Digital Converter (ADC) with up to 32 channel analog inputs per module – One Analog Comparator (CMP) with internal 8-bit Digital to Analog Converter (DAC)
• Debug functionality – Serial Wire JTAG Debug Port (SWJ-DP) combines – Debug Watchpoint and Trace (DWT) – Instrumentation Trace Macrocell (ITM) – Test Port Interface Unit (TPIU) – Flash Patch and Breakpoint (FPB) Unit
• Human-machine interface (HMI) – Up to 156 GPIO pins with interrupt functionality – Non-Maskable Interrupt (NMI) NXP Semiconductors Document Number S32K1XX Data Sheet: Technical Data Rev. 14, 08/2021 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

• Communications interfaces – Up to three Low Power Universal Asynchronous Receiver/Transmitter (LPUART/LIN) modules with DMA support and low power availability – Up to three Low Power Serial Peripheral Interface (LPSPI) modules with DMA support and low power availability – Up to two Low Power Inter-Integrated Circuit (LPI2C) modules with DMA support and low power availability – Up to three FlexCAN modules (with optional CAN-FD support) – FlexIO module for emulation of communication protocols and peripherals (UART, I2C, SPI, I2S, LIN, PWM, etc). – Up to one 10/100Mbps Ethernet with IEEE1588 support and two Synchronous Audio Interface (SAI) modules.
• Safety and Security – Cryptographic Services Engine (CSEc) implements a comprehensive set of cryptographic functions as described in the SHE (Secure Hardware Extension) Functional Specification. Note: CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to execute simultaneously. The device will need to switch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase. – 128-bit Unique Identification (ID) number – Error-Correcting Code (ECC) on flash and SRAM memories – System Memory Protection Unit (System MPU) – Cyclic Redundancy Check (CRC) module – Internal watchdog (WDOG) – External Watchdog monitor (EWM) module
• Timing and control – Up to eight independent 16-bit FlexTimers (FTM) modules, offering up to 64 standard channels (IC/OC/PWM) – One 16-bit Low Power Timer (LPTMR) with flexible wake up control – Two Programmable Delay Blocks (PDB) with flexible trigger system – One 32-bit Low Power Interrupt Timer (LPIT) with 4 channels – 32-bit Real Time Counter (RTC)
• Package – 32-pin QFN, 48-pin LQFP, 64-pin LQFP, 100-pin LQFP, 100-pin MAPBGA, 144-pin LQFP, 176-pin LQFP package options
• 16 channel DMA with up to 63 request sources using DMAMUX S32K1xx Data Sheet, Rev. 14, 08/2021

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6.2.2 External System Oscillator frequency specifications . 38

6.2.3.1 Fast internal RC Oscillator (FIRC)

6.2.3.2 Slow internal RC oscillator (SIRC)

6.2.4 Low Power Oscillator (LPO) electrical specifications

6.3.1 Flash memory module (FTFC/FTFM) electrical

6.3.1.1 Flash timing specifications —

7.3 General notes for specifications at maximum junction

S32K1xx Data Sheet, Rev. 14, 08/2021 NXP Semiconductors 3

1 Block diagram

subset of the features. See Feature comparison for chip specific values.

48 MHz

8 MHz

accesses. In this document, the term MPU refers to NXP’s system MPU. chapter of the S32K1xx Series Reference Manual. execute CSEc (Security) or EEPROM writes/erase. Figure 1. High-level architecture diagram for the S32K14x and S32K14xW family

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accesses. In this document, the term MPU refers to NXP’s system MPU. chapter of the S32K1xx Series Reference Manual. Figure 2. High-level architecture diagram for the S32K11x family

2 Feature comparison

2 KB (up to 32 KB D-Flash)EEPROM emulated by FlexRAM1

2 KBFlexRAM (also available as system RAM)

25 KBSystem RAM (including FlexRAM and MTB) 17 KB

48 MHzFrequency

device is running at HSRUN mode (112MHz) or VLPR mode. 2 Available when EEEPROM, CSEc and Data Flash are not used. Else only up to 1,984 KB is available for Program Flash. of the last 512 KB block can be used as Data flash or Program flash. See chapter FTFC for details.

4 Only for Boundary Scan Register

5 See Dimensions section for package drawings

6 QuadSPI is not supported for S32K148 in 100-pin LQFP

80 MHz (RUN mode) or 112 MHz (HSRUN mode)1

4 KB (up to 64 KB D-Flash)

32 KB 64 KB 128 KB 256 KB

256 KB 512 KB 1 MB 2 MB2

Figure 3. S32K1xx product series comparison

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1 See Dimensions section of Datasheet for package drawings

Figure 4. S32K14xW product series comparison

Ordering information

3.1 Selecting orderable part number

Not all part number combinations are available. See the attachment S32K1xx_Orderable_Part_Number_ List.xlsx attached with the Datasheet for a list of standard orderable part numbers. S32K1xx Data Sheet, Rev. 14, 08/2021

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3.2 Ordering information

F/P S32 K 1 0 0 X Y T0 M LH R Product status Product type/brand Product line Series/Family(including generation) Core platform/ Performance Memory size Ordering option 1: Letter Ordering option 2: Letter Wafer Fab and revision Temperature Package Tape and Reel Product statusP: PrototypeF: Qualified Product type/brandS32: Automotive 32-bit MCU Product lineK: Arm Cortex MCUs Series/Family1: 1st product series2: 2nd product series Core platform/Performance1: Arm Cortex M0+4: Arm Cortex M4F Memory size S32K11x 2 4 6 8 S32K14x/S32K14xW256K512K 128K 256K Ordering optionX: Speed L: 48 MHz with DMA (S32K11x only) H: 80 MHz U1: 112 MHz (Not valid with M temperature/125C) W: 80 MHz (S32K14xW only) Y: Optional feature F: CAN FD, FlexIO A1: CAN FD, FlexIO, Security E: Ethernet, Serial Audio Interface (S32K148 only) J1: Ethernet, Serial Audio Interface, CAN FD, FlexIO, Security (S32K148 only) I: ISELED, FlexIO L1: ISELED, CAN FD, FlexIO, Security G1: ISELED, Ethernet, Serial Audio Interface, CAN FD, FlexIO, Security (S32K148 only) Wafer Fab and Mask revision identifier Tx: Wafer Fab identifier x0: Mask Revision identifier Temperature V: -40C to 105C M: -40C to 125C W: -40 to 150C Tape and Reel T: Trays/Tubes R: Tape and Reel Package LQFP 32 FM Pins QFNBGA 100 144 176 LL LF LH LQ LU MH - - 1 . CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to execute simultaneously. The device will need to switch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase. 2. Part numbers no longer offered as standard include: Ordering Option X M: 64MHz B: 48 MHz without DMA (S32K11x only) Ordering Option Y N: limited RAM. 16KB for K142, 48KB for K144, 96KB for K146, 192KB for K148 R: Basic feature set S: Security B: CAN FD, FlexIO, limited RAM (S32K14x only) C: CAN FD, FlexIO, Security, limited RAM (S32K14x only) V: NFC Stack License X1: CAN FD, FlexIO, Security with NFC Stack License Temperature C: -40C to 85 Not all part number combinations are available. See S32K1xx_Orderable_Part_Number_List.xlsx attached with the Datasheet for list of standard orderable parts. NOTE Figure 5. Ordering information S32K1xx Data Sheet, Rev. 14, 08/2021 NXP Semiconductors 9

4.1 Absolute maximum ratings

• Functional operating conditions appear in the DC electrical characteristics. Absolute maximum ratings are stress ratings only, and functional operation at the maximum values is not guaranteed. See footnotes in the following table for specific conditions.
• Stress beyond the listed maximum values may affect device reliability or cause permanent damage to the device.
• All the limits defined in the datasheet specification must be honored together and any violation to any one or more will not guarantee desired operation.
• Unless otherwise specified, all maximum and minimum values in the datasheet are across process, voltage, and temperature.

Table 1. Absolute maximum ratings for S32K1xx series

1. All voltages are referred to VSS unless otherwise specified.
2. As VDD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the

ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details.

1. 60 seconds lifetime – No restrictions i.e. the part is not held in reset and can switch.

10 hours lifetime – The part is held in reset by an external circuit i.e. the part cannot switch.

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the part will operate with reduced functionality. If the given time limits or supply levels are exceeded, the device may get damaged.

1. When input pad voltage levels are close to VDD or VSS, practically no current injection is possible.
2. While respecting the maximum current injection limit
3. This is the Electronic Control Unit (ECU) supply ramp rate and not directly the MCU ramp rate. Limit applies to both

maximum absolute maximum ramp rate and typical operating conditions.

1. This is the MCU supply ramp rate and the ramp rate assumes that the S32K1xx HW design guidelines in AN5426 are

followed. Limit applies to both maximum absolute maximum ramp rate and typical operating conditions.

1. TJ (Junction temperature)=135 °C. Assumes TA=125 °C for RUN mode

• Assumes maximum θJA for 2s2p board. See Thermal characteristics 9. 60 seconds lifetime; device in reset (no outputs enabled/toggling)

Table 2. Absolute maximum ratings for S32K14xW series

1. All voltages are referred to VSS unless otherwise specified.
2. As VDD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the

ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details.

1. 60 seconds lifetime – No restrictions i.e. the part is not held in reset and can switch.

10 hours lifetime – The part is held in reset by an external circuit i.e. the part cannot switch. the part will operate with reduced functionality. If the given time limits or supply levels are exceeded, the device may get damaged.

1. When input pad voltage levels are close to VDD or VSS, practically no current injection is possible.
2. While respecting the maximum current injection limit

1. This is the Electronic Control Unit (ECU) supply ramp rate and not directly the MCU ramp rate. Limit applies to both

maximum absolute maximum ramp rate and typical operating conditions.

1. This is the MCU supply ramp rate and the ramp rate assumes that the S32K1xx HW design guidelines in AN5426 are

followed. Limit applies to both maximum absolute maximum ramp rate and typical operating conditions.

1. TJ (Junction temperature)=170 °C. Assumes TA=150 °C for RUN mode

• T J is the absolute maximum rating temperature at which the product will not be damaged, guaranteed by intrinsic reliability.
• Assumes maximum θJA for 2s2p board. See Thermal characteristics 9. 60 seconds lifetime; device in reset (no outputs enabled/toggling)

4.2 Voltage and current operating requirements

Table 3. Voltage and current operating requirements for S32K1xx series 1 external power supply source.

1. Typical conditions assumes VDD = VDDA = VREFH = 5 V, temperature = 25 °C and typical silicon process unless otherwise
2. As VDD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the

ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details.

1. S32K148 will operate from 2.7 V when executing from internal FIRC. When the PLL is engaged S32K148 is guaranteed to

operate from 2.97 V. All other S32K family devices operate from 2.7 V in all modes.

1. VDD and VDDA must be shorted to a common source on PCB. The differential voltage between VDD and VDDA is for RF-AC

reference supply design for SAR ADC.

1. VREFH should always be equal to or less than VDDA + 0.1 V and VDD + 0.1 V

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1. Open drain outputs must be pulled to VDD.
2. When input pad voltage levels are close to VDD or VSS, practically no current injection is possible.

Table 4. Voltage and current operating requirements for S32K14xW series 1 external power supply source.

1. Typical conditions assumes VDD = VDDA = VREFH = 5 V, temperature = 25 °C and typical silicon process unless otherwise
2. As VDD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the

ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details.

1. VDD and VDDA must be shorted to a common source on PCB. The differential voltage between VDD and VDDA is for RF-AC

reference supply design for SAR ADC.

1. VREFH should always be equal to or less than VDDA + 0.1 V and VDD + 0.1 V
2. Open drain outputs must be pulled to VDD.
3. When input pad voltage levels are close to VDD or VSS, practically no current injection is possible.

4.3 Thermal operating characteristics

Table 5. Thermal operating characteristics for S32K1xx series

1. Values mentioned are measured at ≤ 112 MHz in HSRUN mode.
2. Values mentioned are measured at ≤ 80 MHz in RUN mode.

Table 6. Thermal operating characteristics for S32K14xW series

1. Values mentioned are measured at ≤ 80 MHz in RUN mode.

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4.4 Power and ground pins

100 LQFP

32 QFN

144 LQFP

176 LQFP

64 LQFP

48 LQFP

Figure 6. Pinout decoupling

Table 7. Supplies decoupling capacitors 1, 2

1. VDD and VDDA must be shorted to a common source on PCB. The differential voltage between VDD and VDDA is for RF-AC

reference supply design for SAR ADC. All VSS pins should be connected to common ground at the PCB level.

1. All decoupling capacitors must be low ESR ceramic capacitors (for example X7R type).
2. Minimum recommendation is after considering component aging and tolerance.
3. For improved performance, it is recommended to use 10 μF, 0.1 μF and 1 nF capacitors in parallel.
4. All decoupling capacitors should be placed as close as possible to the corresponding supply and ground pins.
5. Contact your local Field Applications Engineer for details on best analog routing practices.
6. The filtering used for decoupling the device supplies must comply with the following best practices rules:

• The protection/decoupling capacitors must be on the path of the trace connected to that component.
• No trace exceeding 1 mm from the protection to the trace or to the ground.
• The protection/decoupling capacitors must be as close as possible to the input pin of the device (maximum 2 mm).
• The ground of the protection is connected as short as possible to the ground plane under the integrated circuit. General S32K1xx Data Sheet, Rev. 14, 08/2021

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Figure 7. Power diagram

4.5 LVR, LVD and POR operating requirements

Table 8. V DD supply LVR, LVD and POR operating requirements for S32K1xx series1 Table continues on the next page...

1. In 3.3 V range, the VLVW is always set since supply remains below VLVW range. Hence PMC.LVDSC2[LVWIE] should

remain cleared while device operates in 3.3 V range.

1. Rising threshold is the sum of falling threshold and hysteresis voltage.

Table 9. V DD supply LVR and POR operating requirements for S32K14xW series1

1. In 3.3 V range, the VLVW is always set since supply remains below VLVW range. Hence PMC.LVDSC2[LVWIE] should

remain cleared while device operates in 3.3 V range.

1. Rising threshold is the sum of falling threshold and hysteresis voltage.
2. An internal monitor could reset the chip at a higher supply level, but 3.13 V onward the chip is fully functional.

4.6 Power mode transition operating behaviors

Table 10. Clock configuration Table continues on the next page...

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Table 10. Clock configuration (continued)

1. • For S32K11x – FIRC/SOSC

• For S32K14x, S32K14xW – FIRC/SOSC/SPLL

Table 11. Power mode transition operating behaviors for S32K1xx series across the operating temperature range of the chip.

is the recommended operating mode. Table 12. Power mode transition operating behaviors for S32K14xW series across the operating temperature range of the chip.

4.7 Power consumption

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Table 13. Power consumption (Typicals unless stated otherwise) 1 Table continues on the next page...

Table 13. Power consumption (Typicals unless stated otherwise) 1 (continued)

85 Typ N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A

Table continues on the next page...

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1. Typical current numbers are indicative for typical silicon process and may vary based on the silicon distribution and user configuration. Typical conditions assumes VDD = VDDA = VREFH = 5 V, temperature = 25 °C and typical silicon process unless otherwise stated. All output pins are floating and On-chip pulldown is enabled for all unused input pins. 2. Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation. 3. HSRUN mode must not be used at 125°C. Max ambient temperature for HSRUN mode is 105°C. 4. Values mentioned for S32K14x devices are measured at RUN@80 MHz with peripherals disabled and values mentioned for S32K11x devices are measured at RUN@48 MHz with peripherals disabled. 5. With PMC_REGSC[CLKBIASDIS] set to 1. See Reference Manual for details. 6. Data collected using RAM 7. Numbers on limited samples size and data collected with Flash 8. The S32K148 data points assume that ENET/QuadSPI/SAI etc. are inactive. General S32K1xx Data Sheet, Rev. 14, 08/2021

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Table 14. VLPS additional use-case power consumption at typical conditions 1, 2, 3

• Clock source: SIRC
• Transmiting or receiving continuously using DMA
• Baudrate: 19.2 kbps 25 179 187 230 230 248 250 250 μA 85 235 244 320 400 – 410 490 μA 105 304 325 490 550 563 600 850 μA 125 499 551 890 1070 1102 1250 1960 μA VLPS and LPUART wake-up
• Clock source: SIRC
• Wake-up address feature enabled
• Baudrate: 19.2 kbps 25 107 107 135 138 140 146 146 μA 85 149 157 170 240 – 280 350 μA 105 199 223 260 400 424 480 600 μA 125 347 405 530 580 703 1000 1280 μA VLPS and LPI2C master
• Clock Source: SIRC
• Transmit/receive using DMA
• Baudrate: 100 kHz 25 600 600 670 690 691 820 900 μA 85 696 712 880 960 – 1220 1370 μA 105 815 852 1080 1250 1320 1660 2060 μA 125 1152 1251 1970 1980 2001 2860 3690 μA VLPS and LPI2C slave wake-up
• Clock source: SIRC
• Wake-up address feature enabled
• Baudrate: 100 kHz 25 260 260 260 260 260 270 280 μA 85 293 308 340 340 – 410 510 μA 105 339 367 430 430 458 610 810 μA 125 478 543 740 760 774 1170 1540 μA VLPS and LPSPI master 4
• Clock source: SIRC
• Transmit/receive using DMA
• Baudrate: 500 kHz Table continues on the next page... General S32K1xx Data Sheet, Rev. 14, 08/2021 NXP Semiconductors 25

• 1 channel enable
• Mode: 32-bit periodic counter 25 114 114 114 114 116 120 130 μA 85 158 164 190 250 – 260 320 μA 105 210 223 310 410 425 440 570 μA 125 371 408 640 750 780 910 1280 μA 1. All power numbers listed in this table are typical power numbers 2. Current numbers are quoted for a certain application code and may vary on user configuration and silicon process variation. 3. The power numbers are not strictly for the VLPS mode operation alone, but also includes power due to periodic wakeup. The power therefore includes wakeup plus VLPS mode activity. This leads to greater dependence of power numbers on application code. 4. The single LPSPI used is LPSPI1 in S32K14X devices but LPSPI0 in S32K11x devices. General S32K1xx Data Sheet, Rev. 14, 08/2021

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of operations measure at 3.3 V. Table 15. Power consumption at 3.3 V

1. HSRUN mode must not be used at 125°C. Max ambient temperature for HSRUN mode is 105°C.

4.8 ESD and latch-up protection characteristics

1. Device failure is defined as: "If after exposure to ESD pulses, the device does not meet specification requirements."
2. All ESD testing conforms with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
3. This parameter is tested in conformity with AEC-Q100-002.
4. This parameter is tested in conformity with AEC-Q100-011.
5. This parameter is tested in conformity with AEC-Q100-004.

4.9 EMC radiated emissions operating behaviors

EMC measurements to IC-level IEC standards are available from NXP on request.

5.1 AC electrical characteristics

Figure 8. Input signal measurement reference

5.2 General AC specifications

Table 16. General switching specifications

1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
2. The greater of synchronous and asynchronous timing must be met.
3. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be recognized.
4. Maximum length of RESET pulse which will be the filtered by internal filter only if PCR_PTA5[PFE] is at its reset value of
5. Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter only if PCR_PTA5[PFE] is at its reset

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of PCM_RPC register and/or PORT_DFER register for PTA5. Table 17. DC electrical specifications at 3.3 V Range for S32K1xx series

1. S32K148 will operate from 2.7 V when executing from internal FIRC. When the PLL is engaged S32K148 is guaranteed to

operate from 2.97 V. All other S32K family devices operate from 2.7 V in all modes.

1. For reset pads, same Vih levels are applicable

1. For reset pads, same Vil levels are applicable
2. The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_Standard
3. For refernce only. Run simulations with the IBIS model and custom board for accurate results.
4. Typical leakage is given at room temperature. Maximum is given for 125°C. Leakage numbers increase with temperature,
5. Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All
6. When using ENET and SAI on S32K148, the overall device limits associated with high drive pin configurations must be

respected i.e. On 144-pin LQFP the general purpose pins: PTA10, PTD0, and PTE4 must be set to low drive.

1. Measured at input V = VSS
2. Measured at input V = VDD

Table 18. DC electrical specifications at 3.3 V Range for S32K14xW series

1. For reset pads, same Vih levels are applicable
2. For reset pads, same Vil levels are applicable
3. The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_Standard
4. Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All
5. Measured at input V = VSS
6. Measured at input V = VDD

30 NXP Semiconductors

Table 19. DC electrical specifications at 5.0 V Range for S32K1xx series

1. For reset pads, same Vih levels are applicable
2. For reset pads, same Vil levels are applicable
3. The strong pad I/O pin is capable of switching a 50 pF load up to 40 MHz.
4. For refernce only. Run simulations with the IBIS model and custom board for accurate results.
5. Typical leakage is given at room temperature. Maximum is given for 125°C. Leakage numbers increase with temperature,
6. Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All

1. Measured at input V = VSS
2. Measured at input V = VDD

Table 20. DC electrical specifications at 5.0 V Range for S32K14xW series

1. For reset pads, same Vil levels are applicable
2. The strong pad I/O pin is capable of switching a 50 pF load up to 40 MHz.
3. Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All
4. Measured at input V = VSS
5. Measured at input V = VDD

Table 21. AC electrical specifications at 3.3 V Range for S32K1xx series Table continues on the next page...

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Table 21. AC electrical specifications at 3.3 V Range for S32K1xx series (continued)

1. For reference only. Run simulations with the IBIS model and your custom board for accurate results.
2. Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be

different, for example for ENET, QSPI etc. . For protocol specific AC specifications, see respective sections. Table 22. AC electrical specifications at 3.3 V Range for S32K14xW series

1. For reference only. Run simulations with the IBIS model and your custom board for accurate results.
2. Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be

different. For protocol specific AC specifications, see respective sections.

5.6 AC electrical specifications at 5 V range

Table 23. AC electrical specifications at 5 V Range for S32K1xx series

1. For reference only. Run simulations with the IBIS model and your custom board for accurate results.
2. Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be

different, for example for ENET, QSPI etc. . For protocol specific AC specifications, see respective sections. Table 24. AC electrical specifications at 5 V Range for S32K14xW series

1. For reference only. Run simulations with the IBIS model and your custom board for accurate results.
2. Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be

different. For protocol specific AC specifications, see respective sections.

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5.7 Standard input pin capacitance

Table 25. Standard input pin capacitance specifications for EXTAL/XTAL pins.

5.8 Device clock specifications

Table 26. Device clock specifications 1

1. Refer to the section Feature comparison for the availability of modes and other specifications.

1. Only available on some devices. See section Feature comparison. 3. With SPLL as system clock source. 4. 48 MHz when fSYS is 48 MHz 5. With SPLL as system clock source. 6. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module. Peripheral operating requirements and behaviors

6.1 System modules

There are no electrical specifications necessary for the device's system modules. Clock interface modules

6.2.1 External System Oscillator electrical specifications

6.2 Peripheral operating requirements and behaviors S32K1xx Data Sheet, Rev. 14, 08/2021

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Figure 9. Oscillator connections scheme Table 27. External System Oscillator electrical specifications Table continues on the next page...

1. Crystal oscillator circuit provides stable oscillations when gmXOSC > 5 * gm_crit. The gm_crit is defined as:

• g mXOSC is the transconductance of the internal oscillator circuit
• ESR is the equivalent series resistance of the external crystal
• R S is the series resistance connected between XTAL pin and external crystal for current limitation
• F is the external crystal oscillation frequency
• C 0 is the shunt capacitance of the external crystal
• C L is the external crystal total load capacitance. CL = Cs+ [C1*C2/(C1+C2)]
• C s is stray or parasitic capacitance on the pin due to any PCB traces
• C 1, C2 external load capacitances on EXTAL and XTAL pins See manufacture datasheet for external crystal component values 2. • When low-gain is selected, internal R F will be selected and external RF should not be attached.
• When high-gain is selected, external R F (1 M Ohm) needs to be connected for proper operation of the crystal. For external resistor, up to 5% tolerance is allowed. 3. RS should be selected carefully to have appropriate oscillation amplitude for both protecting crystal or resonator device and satisfying proper oscillation startup condition. 4. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 5. Minimum value is shown as a reference only, however the HW design needs to ensure it reaches the maximum value by following the guidelines given in above notes (notes 1, 2, and 3) and performs the required robustness testing at the application level. During testing, a low capacitance probe (< 5 pF ) must be used to avoid any decrease in the Vpp_EXTAL value.

6.2.2 External System Oscillator frequency specifications

38 NXP Semiconductors

Table 28. External System Oscillator frequency specifications

40 MHz low-gain mode (HGO=0) — 2 —

40 MHz high-gain mode (HGO=1) — 2 —

1. For an ideal clock of 40 MHz, if permitted by application requirements, an error of +/- 5% is supported with 50% duty cycle.
2. (S32K14xW) At 40 MHz to 36 MHz when sourcing for ADC clock please use divider ADCn.ADC_CFG1[ADICLK] to ½ or lower for the specific ADC instance. This

maintain duty cycle of 40-50% or better.

1. S32K1xx : Frequencies below 40 MHz can be used for degraded duty cycle upto 40-60%. When using for ADC clock further restrictions apply. At 50 MHz to 45

requirement. for 45 MHz and 41 MHz 45-55% or higher duty cycle should be maintained.

1. (S32K14xW) The limits to source ADC clock are 40 MHz, so in cases the input clock is higher than 40 MHz, it cannot be used as a source of ADC clock.
2. Proper PC board layout procedures must be followed to achieve specifications.

6.2.3.1 Fast internal RC Oscillator (FIRC) electrical specifications

Table 29. Fast internal RC Oscillator electrical specifications for S32K1xx series

1. With FIRC regulator enable
2. Startup time is defined as the time between clock enablement and clock availability for system use.

Table 30. Fast internal RC Oscillator electrical specifications for S32K14xW series

1. With FIRC regulator enable
2. Startup time is defined as the time between clock enablement and clock availability for system use.

40 NXP Semiconductors

6.2.3.2 Slow internal RC oscillator (SIRC) electrical specifications

Table 31. Slow internal RC oscillator (SIRC) electrical specifications for S32K1xx series

1. Startup time is defined as the time between clock enablement and clock availability for system use.

Table 32. Slow internal RC oscillator (SIRC) electrical specifications for S32K14xW series

1. Startup time is defined as the time between clock enablement and clock availability for system use.

Table 33. Low Power Oscillator (LPO) electrical specifications

6.2.5 SPLL electrical specifications

Table 34. SPLL electrical specifications

1. FSPLL_REF is PLL reference frequency range after the PREDIV. For PREDIV and MULT settings refer SCG_SPLLCFG

register of Reference Manual.

1. FSPLL_Input is PLL input frequency range before the PREDIV must be limited to the range 8 MHz to 40 MHz. This input

mode. For external clock source settings refer SCG_SOSCCFG register of Reference Manual.

1. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each
2. The behavior of the accumulated PLL jitter saturates over 1us.
3. Lock detector detection time is defined as the time between PLL enablement and clock availability for system use.

6.3.1 Flash memory module (FTFC/FTFM) electrical specifications

This section describes the electrical characteristics of the flash memory module.

6.3.1.1 Flash timing specifications — commands

Table 35. Flash command timing specifications for S32K14x series Table continues on the next page...

42 NXP Semiconductors

Table 35. Flash command timing specifications for S32K14x series (continued)

2 KB flash — 75 — 75 — 75 — 75 µs

4 KB flash — 100 — 100 — 100 — 100

64 KB flash 30 550 30 550 30 550 — —

256 KB flash 250 2125 — — — — — —

512 KB flash — — 250 4250 250 4250 250 4250

Table continues on the next page...

Table continues on the next page...

44 NXP Semiconductors

1. All command times assumes 25 MHz or greater flash clock frequency (for synchronization time between internal/external
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For all EEPROM Emulation terms, the specified timing shown assumes previous record cleanup has occurred

0x00 - No EEPROM issues detected.

1. 1st time EERAM writes after a Reset or SETRAM may incur additional overhead for EEE cleanup, resulting in up to 2× the
2. Only after the Nth write completes will any data be valid. Emulated EEPROM record scheme cleanup overhead may occur

set will still be valid and the new records will be discarded.

1. Quick Write times may take up to 550 µs, as additional cleanup may occur when crossing sector boundaries.
2. Time for emulated EEPROM record scheme overhead cleanup. Automatically done after last (Nth) write completes,

assuming still powered. Or via SETRAM cleanup execution command is requested at a later point. Table 36. Flash command timing specifications

2 KB flash — 200 — 200 µs

4 KB flash — 220 — 220

64 KB flash 100 1100 100 1100 ms -1

256 KB flash 350 4400 — —

512 KB flash — — 700 8600

1 KB flash 7 — 7 — ms

Table continues on the next page...

Table 36. Flash command timing specifications (continued)

32 KB EEPROM

64 KB EEPROM

48 KB EEPROM

46 NXP Semiconductors

Table 37. Flash command timing specifications for S32K11x series

64 KB flash — — — —

256 KB flash — — — 2

512 KB flash — — — —

2 KB flash — 75 — 75 µs

4 KB flash — 100 — 100

32 KB flash 15 300 15 300 ms 2

128 KB flash 120 1100 — —

256 KB flash — — 250 2125

Table continues on the next page...

Table 37. Flash command timing specifications for S32K11x series (continued)

1. All command times assume 25 MHz or greater flash clock frequency (for synchronization time between internal/external
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For all EEPROM Emulation terms, the specified timing shown assumes previous record cleanup has occurred. This may
4. 1st time EERAM writes after a Reset or SETRAM may incur additional overhead for EEE cleanup, resulting in up to 2x the
5. Only after the Nth write completes will any data be valid. Emulated EEPROM record scheme cleanup overhead may occur

set will still be valid and the new records will be discarded.

48 NXP Semiconductors

1. Quick Write times may take up to 550 µs, as additional cleanup may occur when crossing sector boundaries.
2. Time for emulated EEPROM record scheme overhead cleanup. Automatically done after last (Nth) write completes,

assuming still powered. Or via SETRAM cleanup execution command is requested at a later point. reset to the FTFC/FTFM macro to stop the operation.

6.3.1.2 Reliability specifications

Table 38. NVM reliability specifications

• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 256 100 K 1.6 M writes writes 5, 6, 7 1. Data retention period per block begins upon initial user factory programming or after each subsequent erase. 2. Program and Erase for PFlash and DFlash are supported across product temperature specification. 3. Cycling endurance is per DFlash or PFlash Sector. 4. Background maintenance operations during normal FlexRAM usage extend effective data retention life beyond 5 years. 5. FlexMemory write endurance specified for 32-bit writes to FlexRAM and is supported across product temperature specification. Greater write endurance may be achieved with larger ratios of EEPROM backup to FlexRAM. 6. For usage of any emulated EEPROM driver other than the FlexMemory feature, the endurance spec will fall back to the specified endurance value of the DFlash specification (1K). 7. FlexMemory calculator tool is available at NXP web site for help in estimation of the maximum write endurance achievable at specific EEPROM/FlexRAM ratios. The "In Spec" portions of the online calculator refer to the NVM reliability specifications section of data sheet. This calculator only applies to the FlexMemory feature.

6.3.2 QuadSPI AC specifications

The following table describes the QuadSPI electrical characteristics.

• Measurements are with maximum output load of 25 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1).
• I/O operating voltage ranges from 2.97 V to 3.6 V
• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the interface should be OFF.
• Add 50 ohm series termination on board in QuadSPI SCK for Flash A to avoid loop back reflection when using in Internal DQS (PAD Loopback) mode.
• QuadSPI trace length should be 3 inches. Memory and memory interfaces S32K1xx Data Sheet, Rev. 14, 08/2021 NXP Semiconductors 49

• For non-Quad mode of operation if external device doesn’t have pull-up feature, external pull-up needs to be added at board level for non-used pads.
• With external pull-up, performance of the interface may degrade based on load associated with external pull-up. Memory and memory interfaces S32K1xx Data Sheet, Rev. 14, 08/2021

50 NXP Semiconductors

Table 39. QuadSPI electrical specifications Table continues on the next page...

Table 39. QuadSPI electrical specifications (continued)

1. See Reference Manual for details on mode settings
2. See Reference Manual for details on mode settings
3. RWDS(External DQS CLK) frequency
4. For operating frequency ≤ 64 Mhz,Output invalid time is 5 ns.
5. Program register value QuadSPI_FLSHCR[TCSS] = 4\`h2
6. Program register value QuadSPI_FLSHCR[TCSH] = 4\`h1

52 NXP Semiconductors

Figure 13. QuadSPI output timing (HyperRAM mode) diagram

54 NXP Semiconductors

Table 40. 12-bit ADC operating conditions 1

0 See Voltage and current

1. 6 Continuous conversions
2. All the data mention in this table is only validated in a simulation and granted by NXP design team.

1. Typical values assume VDDA = 5 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF unless otherwise stated. Typical values are for reference only, and are not tested in production. 3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSS. To get maximum performance, reference supply quality should be better than SAR ADC. See application note AN5032 for details. 4. Clock and compare cycle need to be set according to the guidelines mentioned in the Reference Manual . 5. ADC conversion will become less reliable above maximum frequency. 6. When using ADC hardware averaging, see the Reference Manual to determine the most appropriate setting for AVGS. 7. Numbers based on the minimum sampling time of 275 ns. 8. For guidelines and examples of conversion rate calculation, see the Reference Manual section 'Calibration function' 9. Configuration used during the test to obtain this value is:

• VDD=VDDA=VREFH=2.5 V, 2.7 V, 3 V ,5.5 V, (externally forced)
• BUS CLK=48 MHz, ADC CLK=48MHz (FIRC Used), Calibration CLK=24MHz, Sample Time =14 Cyc, Averaging=32
• Resolution= 12 bit
• Conversion Mode: Continuous Conversion
• Channel: ADC0_SE1
• Temperatures: -40C, 25C, 135C ADC electrical specifications S32K1xx Data Sheet, Rev. 14, 08/2021

56 NXP Semiconductors

Figure 14. ADC input impedance equivalency diagram

• ADC performance specifications are documented using a single ADC. For parallel/simultaneous operation of both ADCs, either for sampling the same channel by both ADCs or for sampling different channels by each ADC, some amount of decrease in performance can be expected. Care must be taken to stagger the two ADC conversions, in particular the sample phase, to minimize the impact of simultaneous conversions.
• On reduced pin packages where ADC reference pins are shared with supply pins, ADC analog performance characteristics may be impacted. The amount of variation will be directly impacted by the external PCB layout and hence care must be taken with PCB routing. See AN5426 for details
• All accuracy numbers assume the ADC is calibrated with VREFH=VDDA=VDD, with the calibration frequency set to less than or equal to half of the maximum specified ADC clock frequency. ADC electrical specifications S32K1xx Data Sheet, Rev. 14, 08/2021 NXP Semiconductors 57

Table 41. 12-bit ADC characteristics (2.7 V to 3 V) (V REFH = VDDA, VREFL = VSS) 1

1. This table is not applicable to S32K14xW.
2. Typical values assume VDDA = 3 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF.
3. The ADC supply current depends on the ADC conversion rate.
4. Represents total static error, which includes offset and full scale error.
5. 1 LSB = (VREFH - VREFL)/2N
6. The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device
7. For ADC signals adjacent to VDD/VSS or XTAL/EXTAL or high frequency switching pins, some degradation in the ADC

performance may be observed.

1. All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the

internal analog parameters, assume minor degradation.

1. All the parameters in the table are given assuming system clock as the clocking source for ADC.

Table 42. 12-bit ADC characteristics (3 V to 5.5 V)(V REFH = VDDA, VREFL = VSS)

1. Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF unless otherwise stated.
2. The ADC supply current depends on the ADC conversion rate.
3. Represents total static error, which includes offset and full scale error.
4. 1 LSB = (VREFH - VREFL)/2N
5. The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device
6. For ADC signals adjacent to VDD/VSS or XTAL/EXTAL or high frequency switching pins, some degradation in the ADC

performance may be observed.

1. All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the

internal analog parameters, assume minor degradation.

1. All the parameters in the table are given assuming system clock as the clocking source for ADC.

58 NXP Semiconductors

• Due to triple bonding in lower pin packages like 32-QFN, 48-LQFP, and 64-LQFP degradation might be seen in ADC parameters.
• When using high speed interfaces such as the QuadSPI, SAI0, SAI1 or ENET there may be some ADC degradation on the adjacent analog input paths. See following table for details. Pin name TGATE purpose PTE8 CMP0_IN3 PTC3 ADC0_SE11/CMP0_IN4 PTC2 ADC0_SE10/CMP0_IN5 PTD7 CMP0_IN6 PTD6 CMP0_IN7 PTD28 ADC1_SE22 PTD27 ADC1_SE21

6.4.2 CMP with 8-bit DAC electrical specifications

Table 44. Comparator with 8-bit DAC electrical specifications for S32K1xx series Table continues on the next page...

1. Difference at input > 200mV
2. Applied ± (100 mV + VHYST0/1/2/3+ max. of VAIO) around switch point.
3. Applied ± (30 mV + 2 × VHYST0/1/2/3+ max. of VAIO) around switch point.
4. Calculation method used: Linear Regression Least Square Method

60 NXP Semiconductors

Table 45. Comparator with 8-bit DAC electrical specifications for S32K14xW series Table continues on the next page...

1. Difference at input > 200mV
2. Applied ± (100 mV + VHYST0/1/2/3+ max. of VAIO) around switch point.
3. Applied ± (30 mV + 2 × VHYST0/1/2/3+ max. of VAIO) around switch point.
4. Calculation method used: Linear Regression Least Square Method

62 NXP Semiconductors

Figure 17. Typical hysteresis vs. Vin level (VDDA = 5 V, PMODE = 0) Figure 18. Typical hysteresis vs. Vin level (VDDA = 5 V, PMODE = 1)

64 NXP Semiconductors

6.5.1 LPUART electrical specifications

Refer to General AC specifications for LPUART specifications.

6.5.1.1 Supported baud rate

Baud rate = Baud clock / ((OSR+1) * SBR). For details, see section: 'Baud rate generation' of the Reference Manual.

6.5.2 LPSPI electrical specifications

The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic LPSPI timing modes.

• All timing is shown with respect to 20% V DD and 80% VDD thresholds.
• All measurements are with maximum output load of 50 pF, input transition of 1 ns and pad configured with fastest slew setting (DSE = 1). 6.5 Communication modules S32K1xx Data Sheet, Rev. 14, 08/2021 NXP Semiconductors 65

Table 46. LPSPI electrical specifications 1 Table continues on the next page...

66 NXP Semiconductors

Table 46. LPSPI electrical specifications 1 (continued) Table continues on the next page...

Table continues on the next page...

68 NXP Semiconductors

1. Trace length should not exceed 11 inches for SCK pad when used in Master loopback mode.
2. While transitioning from HSRUN mode to RUN mode, LPSPI output clock should not be more than 14 MHz.
3. fperiph = LPSPI peripheral clock
4. Master Loopback mode - In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting LPSPI_CFGR1[SAMPLE] bit as 1.

Clock pads used are PTD15 and PTE0. Applicable only for LPSPI0.

1. Master Loopback (slow) - In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting LPSPI_CFGR1[SAMPLE] bit as 1.

Clock pad used is PTB2. Applicable only for LPSPI0.

1. This is the maximum operating frequency (fop) for LPSPI0 with GPIO-HD PAD type only. Otherwise, the maximum operating frequency (fop) is 12 Mhz.
2. Set the PCSSCK configuration bit as 0, for a minimum of 1 delay cycle of LPSPI baud rate clock, where PCSSCK ranges from 0 to 255.
3. Set the SCKPCS configuration bit as 0, for a minimum of 1 delay cycle of LPSPI baud rate clock, where SCKPCS ranges from 0 to 255.
4. While selecting odd dividers, ensure Duty Cycle is meeting this parameter.
5. Maximum operating frequency (fop ) is 12 MHz irrespective of PAD type and LPSPI instance.
6. Applicable for LPSPI0 only with GPIO-HD PAD type, with maximum operating frequency (fop) as 14 MHz.

1. If configured as an output.

Figure 19. LPSPI master mode timing (CPHA = 0) Figure 20. LPSPI master mode timing (CPHA = 1)

70 NXP Semiconductors

1.The bus is driven but may not be equal to the valid serial data being sent. Figure 21. LPSPI slave mode timing (CPHA = 0) Figure 22. LPSPI slave mode timing (CPHA = 1)

6.5.3 LPI2C electrical specifications

See General AC specifications for LPI2C specifications.

6.5.4 FlexCAN electical specifications

For supported baud rate, see section 'Protocol timing' of the Reference Manual.

6.5.5 SAI electrical specifications

The following table describes the SAI electrical characteristics.

• Measurements are with maximum output load of 50 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1).
• I/O operating voltage ranges from 2.97 V to 3.6 V
• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the interface should be OFF.

Table 47. Master mode timing specifications

72 NXP Semiconductors

Figure 23. SAI Timing — Master modes Table 48. Slave mode timing specifications

1. The slave mode parameters (S15 - S22) assume 50% duty cycle on SAI_BCLK input. Any change in SAI_BCLK duty cycle

input must be taken care during the board design or by the master timing.

Figure 24. SAI Timing — Slave modes

6.5.6 Ethernet AC specifications

appropriately to arrive at timing specs/constraints for the physical interface. The following table describes the MII electrical characteristics.

• Measurements are with maximum output load of 25 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1).
• I/O operating voltage ranges from 2.97 V to 3.6 V
• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the interface should be OFF.

Table 49. MII signal switching specifications

74 NXP Semiconductors

Table 50. RMII signal switching specifications Figure 27. RMII receive diagram Figure 28. RMII transmit diagram The following table describes the MDIO electrical characteristics.

• Measurements are with maximum output load of 25 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1).
• I/O operating voltage ranges from 2.97 V to 3.6 V
• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the interface should be OFF.
• MDIO pin must have external Pull-up.

Table 51. MDIO timing specifications Table continues on the next page...

76 NXP Semiconductors

Table 51. MDIO timing specifications (continued) Figure 29. MII/RMII serial management channel timing diagram

6.5.7 Clockout frequency

6.6.1 SWD electrical specofications

Table 52. SWD electrical specifications

78 NXP Semiconductors

Figure 30. Serial wire clock input timing Figure 31. Serial wire data timing

6.6.2 Trace electrical specifications

The following table describes the ETM Trace electrical characteristics.

• Measurements are with maximum output load of 50 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1).
• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the interface should be OFF. NOTE ETM trace is supported only on S32K148. Debug modules S32K1xx Data Sheet, Rev. 14, 08/2021 NXP Semiconductors 79

Table 53. ETM Trace specifications Figure 32. TRACE CLKOUT specifications

6.6.3 JTAG electrical specifications

80 NXP Semiconductors

Table 54. JTAG electrical specifications Table continues on the next page...

Table 54. JTAG electrical specifications (continued)

82 NXP Semiconductors

Figure 35. Test Access Port timing

7.1 Description

The tables in the following sections describe the thermal characteristics of the device. or other components on the board, and board thermal resistance.

7.2 Thermal characteristics

84 NXP Semiconductors

Table 55. Thermal characteristics for 32-pin QFN and 48/64/100/144/176-pin LQFP package

64 NA 62 61 60 61 60 59 NA

100 NA NA 53 NA 52 NA 51 46

144 NA NA NA NA NA NA 51 44

176 NA NA NA NA NA NA NA 42

64 NA 46 45 45 45 45 44 NA

100 NA NA 42 NA 42 NA 40 36

144 NA NA NA NA NA NA 44 37

176 NA NA NA NA NA NA NA 36

64 NA 44 43 42 43 42 41 NA

100 NA NA 40 NA 40 NA 39 34

144 NA NA NA NA NA NA 42 36

176 NA NA NA NA NA NA NA 35

64 NA 50 49 49 49 49 48 NA

100 NA NA 43 NA 42 NA 41 37

176 NA NA NA NA NA NA NA 34

64 NA 39 38 38 38 38 37 NA

Table continues on the next page...

100 NA NA 35 NA 35 NA 34 30

144 NA NA NA NA NA NA 37 31

176 NA NA NA NA NA NA NA 30

64 NA 37 36 36 36 36 35 NA

100 NA NA 34 NA 34 NA 33 28

144 NA NA NA NA NA NA 36 30

176 NA NA NA NA NA NA NA 29

64 NA 26 25 24 25 24 23 NA

100 NA NA 25 NA 25 NA 24 19

144 NA NA NA NA NA NA 30 24

176 NA NA NA NA NA NA NA 24

64 NA 14 13 12 12 12 11 NA

100 NA NA 13 NA 12 NA 11 9

144 NA NA NA NA NA NA 12 9

176 NA NA NA NA NA NA NA 9

Table continues on the next page...

86 NXP Semiconductors

64 NA 2 2 2 2 2 2 NA

100 NA NA 2 NA 2 NA 2 1

144 NA NA NA NA NA NA 2 1

176 NA NA NA NA NA NA NA 1

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air

flow, power dissipation of other components on the board, and board thermal resistance.

1. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively.
2. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek

letters are not available, the thermal characterization parameter is written as Psi-JT.

Table 56. Thermal characteristics for the 100 MAPBGA package

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air

flow, power dissipation of other components on the board, and board thermal resistance.

1. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
2. Per JEDEC JESD51-6 with the board horizontal.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
5. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek

letters are not available, the thermal characterization parameter is written as Psi-JT.

1. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per JEDEC JESD51-12.

When Greek letters are not available, the thermal characterization parameter is written as Psi-JB.

88 NXP Semiconductors

An estimation of the chip junction temperature, TJ, can be obtained from this equation: where:

• T A = ambient temperature for the package (°C)
• R θJA = junction to ambient thermal resistance (°C/W)
• P D = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed in the following equation as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: where:
• R θJA = junction to ambient thermal resistance (°C/W)
• R θJC = junction to case thermal resistance (°C/W)
• R θCA = case to ambient thermal resistance (°C/W) RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. Thermal attributes S32K1xx Data Sheet, Rev. 14, 08/2021 NXP Semiconductors 89

To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using this equation: where:

• T T = thermocouple temperature on top of the package (°C)
• ΨJT = thermal characterization parameter (°C/W)
• P D = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. Dimensions

8.1 Obtaining package dimensions

Package dimensions are provided in the package drawings. To find a package drawing, go to http://www.nxp.com and perform a keyword search for the drawing’s document number: Package option Document Number Manufacture Code 32-pin QFN SOT617-31 98ASA01350D 48-pin LQFP SOT313-3 98ASH00962A 64-pin LQFP SOT1699-1 98ASS23234W 100-pin LQFP SOT407-3 98ASS23208W 100-pin MAPBGA SOT1569-1 98ASA00802D 144-pin LQFP SOT486-2 98ASS23177W 176-pin LQFP SOT506-2 98ASS23479W 1. 5x5 mm package Dimensions S32K1xx Data Sheet, Rev. 14, 08/2021

90 NXP Semiconductors

9.1 Package pinouts and signal descriptions

For package pinouts and signal descriptions, refer to the Reference Manual. The following table provides a revision history for this document. Table 57. Revision History

• Updated figure: High-level architecture diagram for the S32K1xx family
• Updated figure: S32K1xx product series comparison
• Added note in section Selecting orderable part number
• Updated figure: Ordering information
• In table: Absolute maximum ratings :
• Added footnote to I INJPAD_DC
• Updated min and max value of I INJPAD_DC
• Updated description, max and min values for I INJSUM
• Updated V IN_TRANSIENT
• In table: Voltage and current operating requirements :
• Renamed V SUP_OFF
• Updated max value of V DD_OFF
• Removed V INA and VIN
• Added V REFH and VREFL
• Updated footnote "Typical conditions assumes V DD = VDDA = VREFH = 5 V ...
• Removed I NJSUM_AF
• Updated footnotes in table Table 7
• Updated section Power mode transition operating behaviors
• In table: Power consumption
• Added footnote "With PMC_REGSC[CLKBIASDIS] ... "
• Updated conditions for VLPR
• Removed Idd/MHz for S32K144
• Updated numbers for S32K142 and S32K148
• Removed use case footnotes
• In section Modes configuration :
• Replaced table "Modes configuration" with spreadsheet attachment: 'S32K1xx_Power_Modes _Master_configuration_sheet'
• In table: DC electrical specifications at 3.3 V Range :
• Added footnotes to V ih Input Buffer High Voltage and Vih Input Buffer Low Voltage
• Added footnote to High drive port pins
• In table: DC electrical specifications at 5.0 V Range : Table continues on the next page... Pinouts S32K1xx Data Sheet, Rev. 14, 08/2021 NXP Semiconductors 91

• Added footnotes V ih Input Buffer High Voltage and Vih Input Buffer Low Voltage
• Updated table: AC electrical specifications at 3.3 V range
• Updated table: AC electrical specifications at 5 V range
• In table: Standard input pin capacitance
• Added footnote to Normal run mode (S32K14x series)
• Removed note from 1M ohms Feedback Resistor in figure Oscillator connections scheme
• In table: External System Oscillator electrical specifications
• Updated typical of I DDOSC Supply current — low-gain mode (low-power mode) (HGO=0) 1 for 4 and 8 MHz
• Removed rows for I lk_ext EXTAL/XTAL impedence High-frequency, low- gain mode (low-power mode) and high-frequency, high-gain mode and VEXTAL
• Updated Typ. of R S low-gain mode
• Updated description of R F, RS, and VPP
• Removed footnote from R F Feedback resistor
• Updated footnote for C 1 C2 and RF
• In table: Table 28
• Removed mention of high-frequency
• Added HGO 0, 1 information
• In table: Fast internal RC Oscillator electrical specifications
• Updated F FIRC
• Updated description of ΔF
• Updated typ and max values of T JIT cycle-to-cycle jitter and TJIT Long term jitter over 1000 cycles
• Added footnotes to T JIT cycle-to-cycle jitter and TJIT Long term jitter over 1000 cycles
• Updated naming convention of I DDFIRC Supply current
• Added footnote to I DDFIRC Supply current
• Added footnote to column Parameter
• In table: Slow internal RC oscillator (SIRC) electrical specifications
• Removed V DD Supply current in 2 MHz Mode
• Removed footnote and updated description of ΔF
• Updated footnote to F SIRC and IDDSIRC
• In table: SPLL electrical specifications
• Added row for F SPLL_REF PLL Reference
• Updated naming convention throughout the table
• Updated the max value of T SPLL_LOCK Lock detector detection time
• In table: Flash timing specifications — commands
• Added footnotes:
• All command times assumes ...
• For all EEPROM Emulation terms ...
• 'First time' EERAM writes after a POR ...
• Removed footnote 'Assumes 25 MHz or ...'
• Updated Max of t eewr32bers
• Added parameters t quickwr and tquickwrClnup
• In table: Reliability specifications
• Removed Typ. values for all parameters
• Removed footnote 'Typical values represent ... '
• Added footnote 'Any other EEE driver usage ... '
• Updated QuadSPI AC specifications
• Removed topic: Reliability, Safety and Security modules
• In table: 12-bit ADC operating conditions
• Updated V DDA Table continues on the next page...

Revision History

S32K1xx Data Sheet, Rev. 14, 08/2021

92 NXP Semiconductors

Table 57. Revision History (continued)

• Updated values for V REFH and VREFL to add refernce to the section "voltage and current operating requirments" for Min and Max valaues
• Updated footnote to Typ.
• Removed footnote from RAS Analog source resistance
• Updated figure: ADC input impedance equivalency diagram
• In table: 12-bit ADC characteristics (2.7 V to 3 V) (VREFH = VDDA, VREFL = VSS)
• Removed rows for V TEMP_S and VTEMP25
• Updated footnote to Typ.
• In table: 12-bit ADC characteristics (3 V to 5.5 V)(VREFH = VDDA, VREFL = VSS)
• Removed rows for V TEMP_S and VTEMP25
• Removed number for TUE
• Updated footnote to Typ.
• In table: Comparator with 8-bit DAC electrical specifications
• Updated Typ. of I DDLS Supply current, Low-speed mode
• Updated Typ. of t DLSB Propagation delay, Low-speed mode
• Updated Typ. of t DHSS Propagation delay, High-speed mode
• Updated t DLSS Propagation delay
• Added row for t DDAC Initialization and switching settling time
• Updated footnote
• Updated section LPSPI electrical specifications
• Added section: SAI electrical specifications
• Updated section: Ethernet AC specifications
• Added section: Clockout frequency
• Added section: Trace electrical specifications
• Updated table: Table 55 : Updated numbers for S32K142 and S32K148
• Updated table: Table 56 : Updated numbers for S32K148
• Updated Document number for 32-pin QFN in topic Obtaining package dimensions 3 14 March 2017 • In Table 3
• Updated min. value of V DD_OFF
• Added parameter I INJSUM_AF
• Updated Power mode transition operating behaviors
• Updated Power consumption
• Updated footnote to T SPLL_LOCK in SPLL electrical specifications
• In 12-bit ADC electrical characteristics
• Updated table: 12-bit ADC characteristics (2.7 V to 3 V) (VREFH = VDDA, VREFL = VSS)
• Added typ. value to I DDA_ADC, TUE, DNL, and INL
• Added min. value to SMPLTS
• Removed footnote 'All the parameters in this table ... '
• Updated table: 12-bit ADC characteristics (3 V to 5.5 V) (VREFH = VDDA, VREFL = VSS)
• Added typ. value to I DDA_ADC
• Removed footnote 'All the parameters in this table ... '
• In Flash timing specifications — commands updated Max. value of tvfykey to 33 μs 4 02 June 2017 • In section: Block diagram, added block diagram for S32K11x series.
• Updated figure: S32K1xx product series comparison.
• In section: Selecting orderable part number , added reference to attachement S32K_Part_Numbers.xlsx.
• In section: Ordering information
• Updated figure: Ordering information.
• In Table 1, Table continues on the next page...

S32K1xx Data Sheet, Rev. 14, 08/2021 NXP Semiconductors 93

• Updated note 'All the limits defined ... '
• Updated parameter 'I INJPAD_DC_ABS', 'VIN_DC', IINJSUM_DC_ABS.
• In Table 3,
• Updated parameter I INJPAD_DC_OP and IINJSUM_DC_OP.
• In Table 8, updated TBDs for VLVR_HYST, VLVD_HYST, and VLVW_HYST
• In Power mode transition operating behaviors,
• Added VLPR → VLPS
• Added VLPS → VLPR
• Updated TBDs for VLPS → Asynchronous DMA Wakeup, STOP1 → Asynchronous DMA Wakeup, and STOP2 → Asynchronous DMA Wakeup
• In Table 13, updated the specifications for S32K144.
• Updated the attachment S32K1xx_Power_Modes _Configuration.xlsx.
• In Table 25, removed CIN_A.
• In Table 27,
• Updated specificatins for g mXOSC.
• Removed I DDOSC
• In Table 29,
• Added parameter ΔF125.
• Removed I DDFIRC
• In Table 31,
• Added parameter ΔF125.
• Removed I DDSIRC
• In Table 33, removed ILPO
• Updated section: Flash memory module (FTFC/FTFM) electrical specifications
• In section: 12-bit ADC operating conditions,
• Updated TBDs for I DDA_ADC and TUE in Table 41
• Updated TBDs for I DDA_ADC and TUE in Table 42
• In section: QuadSPI AC specifications, updated figure 'QuadSPI output timing (HyperRAM mode) diagram'.
• In section: 12-bit ADC operating conditions, updated Table 40.
• In section: CMP with 8-bit DAC electrical specifications, added note 'For comparator IN signals adjacent ... '
• In table: Table 46, minor update in footnote 6.
• In table: Table 55, updated specifications for S32K146. 5 06 Dec 2017 • Removed S32K148 from 'Caution'
• Updated figure: S32K1xx product series comparison for
• 'EEPROM emulated by FlexRAM' of S32K148 (Added content to footnote)
• Added support for LIN protocol version 2.2 A
• In Absolute maximum ratings :
• Added note 'Unless otherwise ... '
• Added parameter 'Added note 'T ramp_MCU'
• Updated footnote for 'T ramp'
• In Voltage and current operating requirements :
• Added footnote 'V DD and VDDA must be shorted ... ' against parameter 'VDD– VDDA'
• Updated footnote 'V DD and VDDA must be shorted ...'
• In Power and ground pins
• Added diagrams for 32-QFN and 48-LQFP and footnote below the diagrams.
• Updated footnote 'V DD and VDDA must be shorted ...'
• In Power mode transition operating behaviors : Table continues on the next page...

S32K1xx Data Sheet, Rev. 14, 08/2021

94 NXP Semiconductors

• Added footnote 'For S32K11x – FIRC/SOSC/FIRC/LPO; For S32K14x – FIRC/SOSC/FIRC/LPO/SPLL' to 'VLPS Mode: All clock sources disabled'
• Updated numbers for:
• VLPR → VLPS
• VLPS → VLPR
• 'RUN → Compute operation'
• RUN → VLPS
• RUN → VLPR
• In Power consumption :
• Updated specs for S32K142, S32K144, and S32K148
• Updated footnote 'Typical current numbers are indicative ...'
• Updated footnote 'The S32K148 data ...'
• Removed footnote 'Above S32K148 data is preliminary targets only'
• Added new table 'Power consumption at 3.3 V'
• In General AC specifications :
• Updated max value and footnote of WFRST
• Updated symbol for not filtered pulse to 'WNFRST', updated min value, removed max. value, and added footnote
• Fixed naming conventions to align with DS in DC electrical specifications at 3.3 V Range and DC electrical specifications at 5.0 V Range
• Updated specs for AC electrical specifications at 3.3 V range and AC electrical specifications at 5 V range
• In Device clock specifications :
• Updated f BUS to 48 for 11x
• Added footnote to f BUS for 14x
• In External System Oscillator frequency specifications :
• Added specs for S32K11x
• Updated 't dc_extal' for S32K14x
• Added footnote 'Frequecies below ... ' to 'f ec_extal' and 'tdc_extal'
• Splitted Flash timing specifications — commands for S32K14x and S32K11x
• Updated Flash timing specifications — commands for S32K14x
• In Reliability specifications :
• Added footnote 'Data retention period ... ' for 'tnvmretp1k' and 'tnvmretee'
• Minor update in footnote for 'nnvmwree16' 'nnvmwree256'
• In QuadSPI AC specifications :
• Updated 'MCR[SCLKCFG[5]]' value to 0
• Updated 'Data Input Setup Time' HSRUN Internal DQS PAD Loopback value to 1.6
• Updated 'Data Input Setup Time' DDR External DQS min. value to 2
• Updated 'Data Input Hold Time' DDR External DQS min. value to 20
• Upadted figure 'QuadSPI output timing (SDR mode) diagram' and 'QuadSPI input timing (HyperRAM mode) diagram'
• In 12-bit ADC electrical characteristics :
• Added note 'On reduced pin packages where ... '
• Removed max. value of 'I DDA_ADC'
• Added note 'Due to triple ... '
• In 12-bit ADC operating conditions, removed parameter 'ΔVDDA'
• In CMP with 8-bit DAC electrical specifications :
• Updated Typ. and Max. values of 'I DDLS'
• Upadted Typ. value of 't DHSB'
• Updated Typ. value of 'V HYST1' , 'VHYST2', and 'VHYST3'
• In LPSPI electrical specifications :
• Updated 'f periph' and 'fop', and 'tSPSCK' Table continues on the next page...

S32K1xx Data Sheet, Rev. 14, 08/2021 NXP Semiconductors 95

• Updated 3.3 V numbers and added footnote against f op, tSU, ans tV in HSRUN Mode
• Added footnote to 't WSPSCK'
• Updated Thermal characteristics for S32K11x 6 31 Jan 2018 • Changed the representation of ARM trademark throughout.
• Removed S32K142 from 'Caution'
• In 'Key features', added the following note under 'Power management', 'Memory and memory interfaces', and 'Reliability, safety and security':
• No write or erase access to ...
• In High-level architecture diagram for the S32K14x family, added the following footnote:
• No write or erase access to ...
• In High-level architecture diagram for the S32K11x family :
• Minor editorial update: Fixed the placement of SRAM, under 'Flash memory controller' block
• Updated figure: S32K1xx product series comparison :
• Updated footnote 1, and added against 'HSRUN' in addition to 'HW security module (CSEc)' and 'EEPROM emulated by FlexRAM'.
• Updated 'System RAM (including FlexRAM and MTB)' row for S32K144, S32K146, and S32K148.
• Updated channel count for S32K116 in row '12-bit SAR ADC (1 MSPS each)'.
• Updated Ordering information
• Updated Flash timing specifications — commands for S32K148, S32K142, S32K146, S32K116, and S32K118. 7 19 April 2018 • Changed Caution to Notes
• Updated the wordings of Notes and removed S32K146
• Added 'Following two are the available ...'
• In 'Key features' :
• Editorial updates
• Updated the note under Power management, Memory and memory interfaces, and Safety and security.
• Updated FlexIO under Communications interfaces
• Added ENET and SAI under Communications interfaces
• Updated Cryptographic Services Engine (CSEc) under 'Safety and security'
• In High-level architecture diagram for the S32K14x family :
• Minor editorial updates
• Updated note 3
• In High-level architecture diagram for the S32K11x family :
• Minor editorial updates
• In figure: S32K1xx product series comparison :
• Editorial updates
• Updated Frequency for S32K14x
• Updated footnote 4
• Added footnote 5
• In Ordering information :
• Renamed section, updated the starting paragraph
• Updated the figure
• In Voltage and current operating requirements, updated the note
• In Power consumption :
• Updated specs for S32K146
• Removed section 'Modes configuration', amd moved its content under the fisrt paragraph.
• In 12-bit ADC operating conditions : Table continues on the next page...

S32K1xx Data Sheet, Rev. 14, 08/2021

96 NXP Semiconductors

• Fixed the typo in R SW1
• In LPSPI electrical specifications :
• Updated t Lead and tLag
• Added footnote in Figure: LPSPI slave mode timing (CPHA = 0) and Figure: LPSPI slave mode timing (CPHA = 1)
• In Thermal characteristics :
• Updated the name of table: Thermal characteristics for 32-pin QFN and 48/64/100/144/176-pin LQFP package
• Deleted specs for R θJC for 32 QFN package
• Added 'R θJCBottom' 8 18 June 2018 • In attachement ' S32K1xx_Power_Modes _Configuration':
• Updated VLPR peripherals disabled and Peripherals Enabled use case #1, using 4 Mhz for System clock, 2 Mhz for bus clock, and 1Mhz for flash.
• Removed S32K116 from Notes
• In figure: S32K1xx product series comparison :
• Added note 'Availability of peripherals depends on the pin availability ...'
• Updated 'Ambient Operation Temperature' row
• Updated 'System RAM (including FlexRAM and MTB)' row for S32K144, S32K146, and S32K148
• In Ordering information :
• Updated figure for 'Y: Optional feature'
• Updated footnote 3
• In Power and ground pins :
• In figure 'Power diagram', updtaed V Flash frequency to 3.3 V
• In Power mode transition operating behaviors :
• Updated footnote for 'VLPS Mode: All clock sources disabled'
• In Power consumption :
• Added IDDs for S32K116
• Added VLPR Peripherals enabled use case 2 at 125 °C/Typicals
• Renamed VLPR 'Peripherals enabled' to 'Peripherals enabled use case 1'
• Added footnote 'Data collected using RAM' to VLPR 'Peripherals disabled' and VLPR 'Peripherals enabled use case 1'
• Updated VLPS Peripherals enabled at 25 °C/Typicals for S32K142 and S32K144 to 40 μA and 42 μA respectively
• Added table 'VLPS additional use-case power consumption at typical conditions'
• In DC electrical specifications at 3.3 V Range :
• Updated naming conventions
• Added specs for GPIO-FAST pad
• In DC electrical specifications at 5.0 V Range :
• Updated naming conventions
• Added specs for GPIO-FAST pad
• In AC electrical specifications at 3.3 V range :
• Updated naming conventions
• Added specs for GPIO-FAST pad
• In AC electrical specifications at 5 V range :
• Updated naming conventions
• Added specs for GPIO-FAST pad
• In External System Oscillator electrical specifications :
• Clarified description of g mXOSC
• Updated V IL max. to 1.15 V
• In Fast internal RC Oscillator (FIRC) electrical specifications : Table continues on the next page...

S32K1xx Data Sheet, Rev. 14, 08/2021 NXP Semiconductors 97

• Updated specs for T JIT Cycle-to-Cycle jitter to 300 ps
• In QuadSPI AC specifications :
• Updated specs for T iv Data Output In-Valid Time
• In figure 'QuadSPI output timing (SDR mode) diagram', marked Invalid area
• In CMP with 8-bit DAC electrical specifications :
• Removed '(VAIO)' from decription of V HYST0
• In LPSPI electrical specifications :
• Added note 'Undefined' in figures 'LPSPI slave mode timing (CPHA = 0)' and 'LPSPI slave mode timing (CPHA = 1)' 9 18 Sep 2018 • In attachment ' S32K1xx_Power_Modes _Configuration':
• Added separate sheet for S32K14x and S32K11x devices
• Renamed VLPS (Peripherals Enabled) to VLPS (LPTMR enabled)
• Removed Note "Technical information ..."
• In Features:
• Updated Clock interfaces for '4 – 40 MHz fast external oscillator (SOSC)' and 'Real Time Counter'
• Added 'Up to 20 MHz TCLK and 25 MHz SWD_CLK'
• In Absolute maximum ratings : Updated footnote 3 '60 seconds lifetime ... '
• Updated title of table Thermal operating characteristics
• In Ordering information :
• Updated 'Temperature'
• Updated 'Wafer Fab and Mask revision identifier'
• In Power consumption :
• Renamed 'VLPS Peripheral enabled' to 'LPTMR enabled'
• Added IDDs for S32K118 for 85 °C, 105 °C and 125 °C
• Updated IDDs for S32K118 for 25 °C
• Added IDDs for VLPR Peripherals enabled use case 2 for S32K116
• Updated IDDs and added footnotes in table 'VLPS additional use-case power consumption at typical conditions'
• In General AC specifications :
• Updated footnote of WFRST and WNFRST
• In External System Oscillator electrical specifications :
• Added footnote to R S
• Renamed V pp to Vpp_XTAL and updated the description accordingly
• Added V pp_EXTAL
• Added V SOSCOP
• Updated equation 'gm_crit = 4 ...' in footnote 1
• In External System Oscillator frequency specifications :
• Added footnote "For an ideal clock of 40 MHz, if permitted ..." to f osc_hi max.
• In Fast internal RC Oscillator (FIRC) electrical specifications :
• Updated note "Fast internal ... "
• In LPSPI electrical specifications :
• Updated figures 'LPSPI slave mode timing (CPHA = 0)' and 'LPSPI slave mode timing (CPHA = 1)' 10 09 May 2019 • In Notes: Added note 'Technical information for the S32K148 ... '
• In attachment 'S32K1xx_Orderable_Part_Number_List':
• Added ISELED PN
• Added PN for new package offering (48-pin LQFP S32K142; 48-pin LQFP S32K144; 100-pin LQFP S32K148)
• Added NFC PN
• Added UA as S32K148 Standard PN
• Updated Standard Base Feature Offer
• In figure 'S32K1xx product series comparison' : Table continues on the next page...

S32K1xx Data Sheet, Rev. 14, 08/2021

98 NXP Semiconductors

• Added 48-pin LQFP for S32K142 and S32K144 Added 100-pin LQFP for S32K148, along with footnote
• In Ordering information :
• Updated 'Ordering option'
• Updated note 2
• In Thermal characteristics :
• Added values for 48-pin LQFP for S32K142 and S32K144
• Added values for 100-pin LQFP for S32K148 11 27 June 2019 • In Notes: Removed note 'Technical information for the S32K148 ... ' 12 04 Feb 2020 • In Notes: Added note: 'Technical information for ...' Added S32K14xW information throughout
• Removed "Under development" from the footnote number 6 in Figure 3.
• Updated Trace electrical specifications to clarify that the section applies only for ETM Trace and is supported only by S32K148.
• In Table 28, added a new footnote from f osc_hi Max entry.
• Updated Figure 21 for number 8.
• In Reliability specifications, t nvmretee is changed to tnvmretee100, and added a new row for the parameter tnvmretee10. And footnotes are updated in this topic. 13 05 April 2020 • In LVR, LVD and POR operating requirements, Updated table title for S32K14xW series
• Updated values for V LVR for S32K14xW series
• In Absolute maximum ratings, updated T J for S32K14xW series
• In Thermal operating characteristics, updated T J for S32K14xW series
• In External System Oscillator electrical specifications, added note 'Minimum value is shown as a reference only ... ' to Vpp_EXTAL 14 10 August 2021 • In Table 45, fixed broken footnotes in symbols I DDLS and DNL. In Table 9,
• Changed V LVW Min from 4.19 to 4.17.
• Changed values for V LVR.
• Updated values for V LVR for S32K14xW series.
• In ESD and latch-up protection characteristics, changed the name of the section, added footnotes in the table and removed the "Notes" column from the table.
• In SPLL electrical specifications , moved the Typical timings to Maximum for JACC_SPLL.
• In SPLL electrical specifications , added footnote to Maximum values of JACC_SPLL.
• In Table 8 and Table 9, added footnote " In 3.3 V range, the VLVW is always set since supply remains below VLVW range. Hence PMC.LVDSC2[LVWIE] should remain cleared while device operates in 3.3 V range".
• In External System Oscillator frequency specifications updated the footnotes for symobls fosc_hi, fec_extal and fdc_extal.
• Updated Table 56.
• In Table 11, removed TBD.
• In Ordering information , updated the ordering information figure.
• In Table 13, removed TBD for S32K14xW.
• In Table 18 and Table 20, added EXTAL pin PTB6 parameter and values for IIN.
• In Table 13 and Table 14, removed TBD for S32K14xW
• In Table 26 removed the f ERCLK entry.
• In Table 35, updated the Typical and Max values.
• In 12-bit ADC operating conditions :
• Updated Typ. and Max values for symbols C P1, CP2, CS, RSW1 and RAD.

S32K1xx Data Sheet, Rev. 14, 08/2021 NXP Semiconductors 99

• Added ADC power consumption.
• Added footnote "All the data mention...by NXP design team".
• In Table 17 and Table 19 updated the Typ. and Max values for Input leakage current (per pin)

S32K1xx Data Sheet, Rev. 14, 08/2021

100 NXP Semiconductors

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