S32G399A

S32G3 NXP | Alldatasheet

Document overview

• Manufacturer or author: NXP Semiconductors
• PDF pages: 131

Technical content

Datasheet sections

• 1 Introduction
• 1.1 Overview
• 1.2 Applications
• 2 Block diagram
• 3 Feature comparison
• 4 Ordering information
• 5 Electrostatic Discharge (ESD) Characteristics
• 6 Absolute Max Ratings
• 7 Operating conditions
• 7.1 Operating Conditions
• 7.2 Clock frequency ranges
• 8 Thermal Characteristics
• 9 DC electricals
• 9.3 Device Power and Operating Current
• 10 Power sequencing
• 10.1 Power-up
• 10.2 Power-down
• 11 Electromagnetic compatibility (EMC)
• 12 GPIO Pads
• 13 Aurora specifications
• 13.1 Aurora Pads
• 13.2 Aurora Port Timing
• 13.3 Aurora PLL
• 14 Power Management Controller (PMC)
• 14.1 PMC Bandgap
• 15 Reset
• 15.1 Reset Duration
• 15.2 Reset and Standby related pad electrical
• 15.3 PMIC Standby Mode Entry / Exit Protocol
• 16 Peripheral specifications
• 16.1 Analog Modules
• 16.1.1 SAR ADC
• 16.1.2 Temperature Monitoring Unit (TMU)
• 16.1.3 Glitch Filter
• 16.1.4 IRQ
• 16.2 Clock and PLL Interfaces
• 16.2.1 DFS
• 16.2.2 FIRC
• 16.2.3 SIRC
• 16.2.4 FXOSC
• 16.2.5 PLL
• 16.3 Communication modules
• 16.3.1 SPI
• 16.3.2 I2C
• 16.3.4 LIN
• 16.3.5 LPSPI
• 16.3.6 CAN
• 16.4 FlexRay
• 16.4.1 FlexRay - RxD
• 16.4.2 FlexRay - TxD
• 16.4.3 FlexRay - TxEN
• 16.9 PCIe
• 16.6 GMAC and PFE
• 16.6.1 GMAC and PFE Management Interface
• 16.6.2 GMAC and PFE MII
• 16.6.3 GMAC MII 50MHz
• 16.6.4 GMAC and PFE RMII
• 16.6.5 GMAC and PFE RGMII
• 16.6.6 GMAC and PFE SGMII
• 16.12 USB-ULPI
• 16.8 Memory interfaces
• 16.8.1 QuadSPI
• 16.8.12 QuadSPI configurations
• 16.8.13 QuadSPI interfaces
• 16.8.14 QuadSPI timing diagrams
• 16.9 DDR
• 16.9.1 DDR
• 16.9.2 DDR Common DC Input
• 16.9.3 DDR Common DC Output
• 16.9.4 DDR3L DC Input
• 16.9.5 DDR3L Output Timing
• 16.9.6 LPDDR4 DC Input timing
• 16.9.7 LPDDR4 Output Timing
• 16.11 Debug modules
• 16.11.1 JTAG Boundary Scan
• 16.11.2 JTAG Debug Interface Timing
• 16.11.3 SWD electrical specifications
• 17 Pinouts
• 18 Packaging

• This document provides electrical specifications for S32G3.
• For functional characteristics and the programming model, see S32G3 Reference Manual. S32G3 S32G3 Data Sheet Rev. 2 — 02/2023 Data Sheet: Technical Data NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

1 Introduction

1.1 Overview

chips, providing over 2x performance and over 2x system RAM. Table 1. S32G3 family key enhancements

8 MB, 2 x Cortex-A53 LS / 4 x Cortex-A53 and 3 x Cortex-M7 LS

8 MB, 1 x Cortex-A53 LS / 2 x Cortex-A53 and 3 x Cortex-M7 LS

6 MB, 1 x Cortex-A53 LS / 2 x Cortex-A53 and 1 x Cortex-M7 LS

8 MB, 3 x Cortex-M7 LS

15 MB, 4 x Cortex-A53 LS / 8 x Cortex-A53, and 3 x Cortex-M7 LS

15 MB, 2 x Cortex-A53 LS / 4 x Cortex-A53, and 3 x Cortex-M7 LS

20 MB, 2 x Cortex-A53 LS / 4 x Cortex-A53, and 4 x Cortex-M7 LS

20 MB, 4 x Cortex-A53 LS / 8 x Cortex-A53, and 4 x Cortex-M7 LS

Figure 1. S32G2 to S32G3 evolution

• S32G399A
• S32G398A
• S32G379A
• S32G378A This document primarily represents the features offered by the superset S32G399A. To compare the features of the S32G3 family variants, see Feature comparison.

1.2 Applications

• Service-oriented gateways and domain controllers
• Safety processor for ADAS and autonomous driving
• High-performance central compute nodes NXP Semiconductors Introduction S32G3 Data Sheet, Rev. 2, 02/2023 Data Sheet: Technical Data 4 / 131

• FOTA masters controlling secure software image downloads and their distribution to the ECUs in the network
• Security services and key management
• Smart antennas

2 Block diagram

The following is the block diagram for S32G399A, the superset chip in the S32G3 family.

32 KB D-cache32 KB I-cache

1 MB L2 cache/cluster

20 MB platform SRAM with ECC

32 KB standby SRAM with ECC

64 KB D-TCM

32 KB I-cache32 KB D-cache

1 MB L2 cache/clusterNeon

Figure 2. Block diagram

3 Feature comparison

This table compares the features of the chips in the S32G3 family. Table 2. S32G3 feature list and supported functionality Table continues on the next page...

Table 2. S32G3 feature list and supported functionality (continued) Table continues on the next page...

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1. Cortex-A53_2 and Cortex-A53_3 have been defeatured in cluster 0 and cluster 1.
2. Cortex-M7_2 has been defeatured. See the System RAM Controller chapter of the S32G3 Reference Manual for details.
3. SRAM (12, 13, 14, 15) i.e., the highest address range (0x34F0_0000–0x353F_FFFF) associated to Cortex-M7_2 have

4 Ordering information

Figure 3. Ordering information

Ordering information

S32G3 Data Sheet, Rev. 2, 02/2023 Data Sheet: Technical Data 8 / 131

5 Electrostatic Discharge (ESD) Characteristics

The following table gives the ESD ratings and test conditions for the device. Table 3. Electrostatic Discharge (ESD) Characteristics

1. Device failure is defined as: "If after exposure to ESD pulses, the device does not meet the device specification
2. This parameter is tested in conformity with AEC-Q100-002
3. All ESD testing conforms with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
4. This parameter is tested in conformity with AEC-Q100-011.

6 Absolute Max Ratings

conditions are given in the Operating Conditions section of this document. All specifications associated with VIN are measured at the SoC pin. Table 4. Absolute Max Ratings Table continues on the next page...

Table 4. Absolute Max Ratings (continued) Table continues on the next page...

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1. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress

conditions table for functional specifications.

1. Allowed 0.88V – 0.96V for 60 seconds cumulative over lifetime with no operating restrictions, 2.0 hours cumulative over
2. Allowed 1.92V - 2.16V for 60 seconds cumulative over lifetime with no operating restrictions, 2.6 hours cumulative over
3. Allowed 3.52V - 4.0V for 60 seconds cumulative over lifetime with no operating restrictions, 2.6 hours cumulative over
4. VEXTAL/ VXTAL (min) is for powered condition. VEXTAL/VXTAL (min) can be lower in unpowered condition.
5. Allowed for a cumulative duration of 50 hours operation over the lifetime of the device at maximum Tj, with VDD_ADC <=

1.92V, VSS_ADC = 0V. Allowed for unlimited duration if the device is unpowered.

1. The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current

unpowered current injection constraints. Unpowered devices must simultaneously follow IINJ_D unpowered current injection constraints.

1. DC case limit. Overshoot/Undershoot beyond this range is allowed, but only for the limited durations as constrained by

temporal percentages of tSIGNAL.

1. IINJ_D specifications are per pin for an unpowered condition of the associated supply. The maximum simultaneous

injection per supply is 30mA.

1. Non-disturb of ADC channels during current injection cannot be guaranteed. The degradation in channel performance

cannot be specified due to the dynamic operation of the ADC input mux and potential for varying charge distribution. the channels not subject to current injection Offset error would be -12 LSB to 6 LSB and TUE would be -12 LSB to 8 LSB.

1. Applies exclusively to ZipWire and does not apply to Aurora. Allowed for a cumulative of 14 hours over the life of the part.

The voltage on the RX or TX pin must not exceed 2.16 V at any time during the power-cycling or normal operation.

1. Solder profile per IPC/JEDEC J-STD-020D.
2. Moisture sensitivity per JEDEC test method A112.
3. For AC Signals in a 3.3V supply domain, if VDD_IO ≤ 3.3V, max VIN overshoot is limited to VDD_IO+20%. If VDD_IO >

3.3V, then max VIN overshoot is limited to 4V.

1. For AC Signals in a 1.8V supply domain, max VIN overshoot is limited to VDD_IO+20% for 10% of tSIGNAL.

Figure 4. Soc-pin overshoot/undershoot voltage for each GPIO pad type

7 Operating conditions

7.1 Operating Conditions

are valid, except where explicitly noted. Device behavior is not guaranteed for operation outside of the conditions in this table. All specifications associated with VIN are measured at the SoC pin.

Table 5. Operating Conditions Table continues on the next page...

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1. The operating conditions in this table apply as required conditions for all other specifications in this document, unless

explicitly noted as an exception in another section of this document.

1. The stated maximum operating frequency must be observed when using the PLL with frequency modulation enabled.

less than the stated maximum frequency.

1. Lifetime operation at Tj max not guaranteed. Standard automotive temperature profile assumed for performance and
2. The junction temperature (Tj) range specification cannot be violated. The ambient temperature shown in the table, is a
3. The operating voltage range applies when the device is not in standby mode.
4. Both PCIe supplies must ramp for the SerDes PHY to safely power up into its reset state. Until both supplies are ramped,

the SerDes PHY will be in an undefined state.

1. A minimum of 2.91V is supported on this supply when the device is in low-power standby mode if it is kept powered during
2. The device supports QSPI interface to 3.3V memories on the QSPI B bank, which is multiplexed with uSDHC functions on

the VDD_IO_SDHC supply. QSPI A signals on VDD_IO_QSPI are limited to 1.8V.

1. The VDD_EFUSE supply must be maintained within specification during fuse programming. Failure to do this may result in

improper functionality of the device after fuse programming.

1. Refer to the Power Sequencing section for the relationship of VDD_EFUSE powering up/down relative to the core,

high-voltage, and I/O supplies.

1. VDD_EFUSE must be grounded when not actively programming the fuses. This supply is not required to be powered for

fuse reads. See device hardware design guidelines document for more details.

1. For AC signals, allowed max VIN ≤ VDD_IO* for lifetime operation. If AC overshoot beyond VDD_IO* occurs, then refer

0.3V is allowed for lifetime operation.

1. The min DC VIN level for a powered device is -0.3V. If AC undershoot below -0.3V occurs, then refer to the Abs Max

duration constraints as a function of the amount of undershoot.

1. DC case limit. Overshoot/Undershoot beyond this range is allowed, but only for the limited durations as constrained by

temporal percentages of tSIGNAL.

1. The "voltage differential" refers to the difference between the lowest and highest voltages across all supplies within the

supply group as defined under Condition column.

1. VREFH_ADCn allows a differential voltage of +/-100mV.
2. On slow ramps, the RESET_B pin may be observed to be asserted multiple times during the supply ramping. In order to

supply ramp or whenever POR_B is asserted.

1. The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current
2. IINJ_D specifications are per pin for an unpowered condition of the associated supply. The maximum simultaneous

injection per supply is 30mA.

1. You must ensure that neither IINJ nor VIN specs are violated. Negligible DC injection currents are expected to flow during
2. The SAR ADC electrical specifications are not guaranteed during any period when the operating injection current limit is

violated. These specifications are at maximum Tj and VREFH_ADC=1.8V; the injected current will reduce with reduced Tj. requirement” and section “PDN (Power Delivery Network) Guidelines". Figure 5. TDISCHARGE STDBY definition

Figure 6. ADC supply sequencing

7.2 Clock frequency ranges

The following table gives the frequency range minimum and maximums to use when programming the clock dividers on the device. Table 6. Clock frequency ranges Table continues on the next page...

Table 6. Clock frequency ranges (continued) Table continues on the next page...

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8 Thermal Characteristics

dissipation of other components on the board, and board thermal resistance. Table 7. Thermal Resistance

1. Thermal test board meets JEDEC specification for this package (JESD51-9).
2. Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is

meant to predict the performance of a package in an application-specific environment.

1. Junction-to-Case thermal resistance determined using an isothermal cold plate. Case temperature refers to the lid surface

9 DC electricals

1.8V analog total which applies to all devices. For I/O power specifications please see dedicated I/O table.

Table 8. Total power specifications for 0.8V and 1.8V Analog Domains Table continues on the next page...

Table 8. Total power specifications for 0.8V and 1.8V Analog Domains (continued)

1. Max usecase: This is provided for power supply design. It is the realistic peak power consumption in an application. Shall

only be maintained for a very short time (approx. 100us).

1. Thermal usecase: This is provided for designing a thermal solution. This is a realistic maximum sustained usecase which

would be maintained for a longer duration.

1. Note that during Self Test execution, the power consumption for this device could exceed the stated spec. The

S32G399A device Max Usecase spec will apply for the duration of the self test.

1. 1.8V total does not include additional consumption during a fuse programming operation. See IDD_EFUSE_PGM spec for

9.2 Static power specifications for I/O Domains

Specifications" table contains pre-calculated total I/O power (static + dynamic) for common usecases. Table 9. Static power specifications for I/O Domains Table continues on the next page...

Table 9. Static power specifications for I/O Domains (continued)

9.3 Device Power and Operating Current Specifications

The device power consumption, operating current, and applicable conditions are given in the following table. All measurements are at Tj=125C, unless otherwise specified.

Table 10. Device Power and Operating Current Specifications Table continues on the next page...

Table 10. Device Power and Operating Current Specifications (continued)

60 Ohm transmit

Table continues on the next page...

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1. This spec includes the consumption on pins in VDD_STBY_IO domain only. See the hardware design guide for more
2. This specification can be considered a worst case maximum for any valid 2 x lane SerDes configuration (including PCIe/

10 Power sequencing

10.1 Power-up

must be within its specified operating voltage range before the next step in the sequence is started, except as noted below.

1. Set POR_B input to low value.
2. Ramp up VDD_IO_STBY supply.

VDD_IO_B can optionally be included with VDD_IO_STBY in the first step.

1. Ramp up all GPIO supplies powered to 3.3V.
2. Ramp up all 1.8V supplies including GPIO supplies powered to 1.8V
3. Ramp up VDD_DDR_IO supply
4. Ramp up all 0.8V supplies
5. Set POR_B and PMIC_VDD_OK inputs to high value once all supplies have reached their specified levels.

option to ramp with step 3 instead of step 4. Figure 7. 1.8V supply timing with respect to PMIC_VDD_OK during Standby Mode Exit

powered up, the VDD_EFUSE supply pin can be powered up/down independent of the other supplies on the device. together with the other 1.8V supplies during Standby mode entry. Table 11. Power-up Standby mode are ramped up again, and the POR_B input is kept high throughout the sequence.

10.2 Power-down

achieved, ensure that all supplies are below the Vpwrdwn level before powering up again.

11 Electromagnetic compatibility (EMC)

EMC measurements to IC-level IEC standards are available from NXP Semiconductor on request.

12 GPIO Pads

Table 12. GPIO Pads Table continues on the next page...

Table 12. GPIO Pads (continued) Table continues on the next page...

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1. For current at this voltage see IOL/IOH specs respectively.
2. Fastest slew rate and lowest rise/fall time constraint required to meet high-speed interface timing such as QSPI, RGMII,

and uSDHC. Slower input transitions can be used for input signals with slow switching rates (<40 MHz).

1. The ISLEW has precedence over ITR_TF if the ITR_TF violates the implied range for a given ISLEW.
2. Input slew rate and rise/fall time limits must be adhered to in conjunction with the max input frequency limits given for
3. GPIO output transition time information can be obtained from the device IBIS model. IBIS models are recommended for

connected to an actual transmission line load.

1. I/O timing specifications are valid for the un-terminated 50ohm transmission line reference load given in the figure below.

resistance in the transmission line should be matched closely to the selected RDSON of the I/O pad output.

1. Rise/fall time specifications are derived from simulation model for the defined operating points (between 20% and

microcontroller models and application PCB. 'POR value' state instead of the POR_B pin.

1. See IBIS models for further details.

Figure 8. Reference Load Diagram

Figure 9. 1.8V/3.3V GPIO pad detailed behavior during power up

Figure 10. 1.8V and 3.3V GPIO pad detailed behavior during power up The high-impedance state level is shown based on the external pull-up being on the corresponding pad supply.

13 Aurora specifications

13.1 Aurora Pads

Table 13. Aurora Pads Table continues on the next page...

Table 13. Aurora Pads (continued) Table continues on the next page...

13.2 Aurora Port Timing

The following table gives the Aurora Port interface timing specifications for the device. Table 14. Aurora Port Timing

Figure 13. Aurora Debug Port Timing

13.3 Aurora PLL

achieves a maximum output frequency of 5GHz. Table 15. Aurora PLL Table continues on the next page...

Table 15. Aurora PLL (continued)

1. Refer to the LVDS Pad specifications for additional Aurora PLL reference clock electrical specifications. Also see " Aurora

Debug Port Timing" figure for fPLL_CLKIN as spec number 1.

1. 100MHz is the only input reference frequency supported for the Aurora PLL.
2. 40MHz is the only internal input reference frequency supported for the Aurora PLL.
3. It is Aurora PLL Input Reference Clock Frequency after pre-divider.
4. The Aurora PLL is only validated at the frequencies specified within this table - these frequencies correspond to the limited

set of Aurora data lane rates that are supported for the device.

14 Power Management Controller (PMC)

14.1 PMC Bandgap

Table 16. PMC Bandgap

1. ADC conversion error must be included when reading the bandgap reference voltage via the chip ADC.

15 Reset

15.1 Reset Duration

reset plus the duration of the new sequence. The diagrams in this section are not to scale. Table 17. Reset Duration Figure 14. Functional reset

Figure 19. Start-up self-test

0.8 V supply

Figure 20. Reset_b pad detailed behavior during core supply brownout

Figure 21. Reset_b pad detailed behavior during pad HV supply brownout

Figure 22. Reset_b pad detailed behavior during power down

15.2 Reset and Standby related pad electrical characteristics

The following table gives the characteristics of the POR_B, RESET_B, PMIC_STBY_MODE_B, and PMIC_VDD_OK pads. Values not explicitly listed in this table can be found in the 'GPIO Pads’ section. Table 18. Reset and Standby related pad electrical characteristics Table continues on the next page...

Table 18. Reset and Standby related pad electrical characteristics (continued)

1. ISLEW_RESET_B(Min) = MAX[30e-06, 0.002 * Vnoise_p_p * Fnoise], where Vnoise_p_p is peak-peak noise magnitude (in

V) and Fnoise is max noise frequency (in MHz). Figure 23. RESET_B pad detailed behavior of core VDD droop after power-up.

Figure 24. Noise filtering on RESET_B pad and any required PMIC BIST has completed. See the ‘Power Sequencing’ section for details. operational range (i.e., a corresponding PMIC LVD or HVD event occurs).

15.3 PMIC Standby Mode Entry / Exit Protocol

1. asserted by the SoC when the power domains that are not needed during Standby mode are to be turned off
2. deasserted by the SoC when the power domains that are not needed during Standby mode are to be turned on
3. deasserted by the PMIC when the power domains that are not needed during Standby mode have been turned off
4. asserted by the PMIC when the power domains that are not needed during Standby mode have been turned on and have

PMIC BIST has completed. See the “Power Sequencing” section for any exceptions. This implies that the PMIC_VDD_OK input is asserted and deasserted together with the POR_B input during non-Standby modes.

Figure 28. Standby Mode Aborted by PMIC POR Event

16 Peripheral specifications

16.1 Analog Modules

16.1.1 SAR ADC

electrical specification are met. the external capacitance at the input pin and reference pin should be maximized. Table 19. SAR ADC Table continues on the next page...

Table 19. SAR ADC (continued)

1. The reduced limits for VAD_INPUT in this table are recommended for normal operation.
2. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal

sample clock tsample depend on programming.

1. 1Msps is the ADC output rate and includes both sampling and analog to digital conversion.
2. ADC performance specifications are guaranteed when calibration uses maximum averaging i.e. when AVGEN = 1 and
3. During calibration, the ADC determines its (positive or negative) offset value and stores the result in an internal register.
4. A positive calibration offset does not impact the max. code output of 4095. Calibration fails if it determines an offset
5. This specification is taken with averaging through post process ADC data.
6. The maximum and minimum leakage current values are reached when Vin=VREF and Vin=0, respectively.

1 LSB ideal = (VrefH-VrefL)/4096 =

1 LSB (ideal)

Figure 29. SAR ADC Specification Characteristics Figure 30. SAR ADC Input Circuit

16.1.2 Temperature Monitoring Unit (TMU)

sensors connected to the TMU on the device.

Table 20. Temperature Monitoring Unit (TMU)

1. Accuracy outside of operating range (-40 to 125) is not guaranteed.

16.1.3 Glitch Filter

Table 21. Glitch Filter

1. Pulses shorter than defined by the maximum value are guaranteed to be filtered (not passed).
2. Pulses in between the max filtered and min unfiltered may or may not be passed through.
3. See the device reference manual for which package pins include glitch filters on the pin input.
4. An input signal pulse is defined by the duration between the input signal's crossing of a Vil/Vih threshold voltage level, and

the next crossing of the opposite level.

1. Pulses larger than defined by the minimum value are guaranteed to not be filtered (passed).

16.1.4 IRQ

The following table gives the input specifications for the external interrupt pins. Table 22. IRQ

Figure 31. External Interrupt Timing (IRQ)

16.2 Clock and PLL Interfaces

16.2.1 DFS

The following table specifies the output frequency ranges and characteristics of the Digital Frequency Synthesizer (DFS). Table 23. DFS

1. For SoC clocks that are further divided down from the DFS output clock, the jitter is multiplied by a factor of SQRT(N),

where N is the ratio of the DFS output clock and destination clock periods.

1. Jitter value does not apply when the DFS clock is output on an external pin. In this case, the rise and fall time variations in

the I/O pad are orders of magnitude more than the DFS and SoC mux jitter contributions. jitter=Max(PER_jitter(PLL))*(sqrt(N)) +Max(PER_jitter(DFS)). Where N is the DFS division factor. All jitter numbers are in ps.

16.2.2 FIRC

Table 24. FIRC

1. ðfVAR defines how much the output frequency can shift over the specified temperature and voltage ranges of the device

16.2.3 SIRC

Table 25. SIRC

1. PTA defines how close the output frequency is to target after the initial factory trim.
2. ðfVAR defines how much the output frequency can shift over the specified temperature and voltage ranges of the device.

16.2.4 FXOSC

Table 26. FXOSC Table continues on the next page...

Table 26. FXOSC (continued)

1. Recommended crystal frequencies are 20MHz, 24MHz, and 40MHz.
2. All specifications only valid for this frequency range if the correct FXOSC transconductance setting is used.
3. The input clock must be 40 MHz nominal frequency.
4. The input clock signal should be symmetric around common mode voltage.
5. Account for on-chip stray capacitance (CS_XTAL) and PCB capacitance in the total XTAL/EXTAL pin load capacitance.

CS_XTAL don't include miller capacitance. has a load cap of 8 pF and configure gm_sel[3:0]=4'b100. load cap of 8 pF and configure gm_sel[3:0]=4'b0110. configure gm_sel[3:0]=4'b1111. In ALC disable mode the minimum crystal drive level should be greater than 500uW. See Hardware design guide for the recommended circuit for each mode. clock (FXOSC) should adhere to this specification.

16.2.5 PLL

operating frequencies for the device are constrained to the values given below. PLL refers to the Core, Peripheral, Accelerator, and DDR reference PLLs on the device. Spread spectrum clock modulation is only available on the Core, Accelerator and DDR reference PLLs. Table 27. PLL Table continues on the next page...

Table 27. PLL (continued)

1. This refers to spec number 1 which is shown in the figure in Aurora port specifications
2. This specification is PLL input reference clock frequency after pre-divider.
3. Duty cycle of the system PLL clock when output on an external pin is given in the I/O pad specifications.
4. The frequencies are the nominal frequencies (i.e., what the PLL's VCO is configured to).
5. The max frequency in case of center-spread SSCG enabled for a modulation depth can be calculated as: Max

SSCG disabled). For details, see section “Frequency modulation programming” in reference manual.

1. Same min frequency value applies for center-spread SSCG enabled as provided for center-spread SSCG disabled.
2. DDR PLL allows center-spread SSCG at fPLL_MOD 32KHz @2% MD (modulation depth) and fPLL_MOD 64KHz @ 1%
3. The DDR PHY internally multiplies the PLL_DDR_PHI0 by factor of two.
4. For chip clocks that are further divided down from the PLL output clock, the jitter is multiplied by a factor of SQRT(N),

where N is the ratio of the PLL output clock and destination clock periods.

1. Jitter value does not apply when a PLL clock is output on an external pin. In this case, the rise and fall time variations in

the I/O pad are orders of magnitude more than the PLL and SoC mux jitter contributions.

1. Jitter is dependent on the period of the PLL output clock, and the division ratio of the clock at the destination module.
2. Jitter is dependent on supply noise. Specified jitter values are valid for the FXOSC reference clock input only - not valid for
3. This specification is valid when all clock sources are stable.

rates are half of the LPDDR4.

16.3 Communication modules

16.3.1 SPI

Table 28. SPI Table continues on the next page...

Table 28. SPI (continued)

1. The maximum SPI baud rate that is achievable in a dedicated master-slave connection depends on several parameters
2. SMPL_PTR should be set to 1. For SPI_CTARn[BR] - 'Baud Rate Scaler' configuration is >= 3
3. Slave Receive Mode can operate at a maximum frequency of 60 MHz. In this mode, the DSPI can receive data on SIN, but

no valid data is transmitted on SOUT.

1. This value of 20 ns is with the configuration prescaler values: SPI_CTARn[PCSSCK] - "PCS to SCK Delay Prescaler"
2. This value of 20 ns is with the configuration prescaler values: SPI_CTARn[PASC] - "After SCK Delay Prescaler"
3. Input timing assumes an input signal slew rate of 2ns (20%/80%).
4. For the case of both master and slave being NXP S32x devices, frequency of operation will be reduced to

[1000 /2* {tSUI_master + tSUO_slave + PCB delay}] in ns.

1. N is number of protocol clock cycles where the master samples SIN in MTFE mode after SCK edge.
2. Output timing valid for maximum external load CL = 25pF, which is assumed to be a 10pF load at the end of a 50Ohm,

series resistance of the transmission line should be matched closely to the RDSON of the I/O pad output driver. Slave mode timing values given below are applicable when device is in MTFE=0. Figure 32. SPI Modified Transfer Format Timing - Master, CPHA = 1, MTFE=1

Figure 37. SPI Classic Timing - Master, CPHA = 0, MTFE=0 Figure 38. SPI PCS Strobe (PCSS) Timing

16.3.2 I2C

16.3.2.1 I2C Input

Table 29. I2C Input Table continues on the next page...

Table 29. I2C Input (continued)

1. MODULE_CLK from the MC_CGM is the clock driving the I2C block.
2. Input timing assumes an input signal slew rate of 3ns (20%/80%).
3. MODULE_CLK frequency should be greater than 5 MHz for standard mode and 20 MHz for fast mode.

Figure 39. I2C Input/Output Timing

16.3.2.2 I2C Output

Table 30. I2C Output Table continues on the next page...

Table 30. I2C Output (continued)

1. Timing valid for maximum external load CL = 400pF, at the maximum clock frequency defined by the I2C clock high and
2. MODULE_CLK from the MC_CGM is the clock driving the I2C block.
3. Programming IBFD (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings listed.

position is affected by the prescale and division values programmed in IBFD.

1. Because SCL and SDA are open-drain outputs, which the processor can only actively drive low, the time SCL or SDA

Figure 40. I2C Input/Output Timing

16.3.4 LIN

Table 31. LIN

16.3.5 LPSPI

Table 32. LPSPI Table continues on the next page...

Table 32. LPSPI (continued)

1. The maximum master mode LPSPI clock frequency can be no more than the peripheral clock frequency divided by 2.
2. fPER_CLK is the frequency of the device peripheral clock (PER_CLK).
3. The maximum LPSPI baud rate that is achievable in a dedicated master-slave connection depends on several parameters
4. All timing valid to 20% and 80% levels of the LPSPI I/O voltage supply on the device.
5. The maximum slave mode LPSPI clock frequency can be no more than the peripheral clock frequency divided by 4.
6. Set the PCSSCK configuration bit as 0, for a minimum of 1 delay cycle of LPSPI baud rate clock, where PCSSCK ranges
7. tPCSSCK = (PCSSCK+1) * (2**PRESCALE) * (1 / fPER_CLK)
8. Set the SCKPCS configuration bit as 0, for a minimum of 1 delay cycle of LPSPI baud rate clock, where SCKPCS ranges
9. tSCKPCS = (SCKPCS+1) * (2**PRESCALE) * (1 / fPER_CLK)
10. Timing valid for maximum external load CL = 25pF, which is assumed to be a 10pF load at the end of a 50ohm,

series resistance in the transmission line should be equal to the selected RDSON of the I/O pad output.

1. Output rise/fall time is determined by the output load and GPIO pad drive strength setting. See the GPIO specifications for
2. The input rise/fall time specification applies to both clock and data, and is required to guarantee related timing parameters.

Figure 44. LPSPI Slave Mode Timing (CPHA=1)

16.3.6 CAN

See GPIO pads for CAN specifications.

16.4 FlexRay

16.4.1 FlexRay - RxD

Table 33. FlexRay - RxD

1. FlexRay RxD timing assumes an input signal slew rate of 2ns (20%/80%).

16.4.2 FlexRay - TxD

Table 34. FlexRay - TxD

1. Timing valid for maximum external load CL = 25pF, which is assumed to be a 8pF load at the end of a 50Ohm,

transmission line should be matched closely to the RDSON of the I/O pad output driver. Figure 45. TxD Signal Propagation Delay

Figure 46. TxD Signal

16.4.3 FlexRay - TxEN

Table 35. FlexRay - TxEN

1. Timing valid for maximum external load CL = 25pF, which is assumed to be a 8pF load at the end of a 50Ohm,

series resistance of the transmission line should be matched closely to the RDSON of the I/O pad output driver.

Figure 47. TxEN Signal Propagation Delay Figure 48. TxEN Signal

16.9 PCIe

Table 36. PCIe Table continues on the next page...

Table 36. PCIe (continued) Table continues on the next page...

Table continues on the next page...

1. The PCI Express link conforms to the PCI Express Base Specification, Revision 3.1. The summary of Transmitter and

MPLLB_BW_OVRD_VAL = 218 and MPLLA_BW_OVRD_VAL = 197. NXP internally does PCI-SIG TX compliance testing using external reference clock source.

16.6 GMAC and PFE

16.6.1 GMAC and PFE Management Interface

Table 37. GMAC and PFE Management Interface Figure 49. MDC / MDIO Timing

16.6.2 GMAC and PFE MII

Table 38. GMAC and PFE MII

1. Input timing assumes an input signal slew rate of 3ns (20%/80%).
2. Output timing valid for maximum external load CL = 25pF, which is assumed to be a 10pF load at the end of a 50Ohm,

series resistance of the transmission line should be matched closely to the RDSON of the I/O pad output driver. Figure 50. MII Receive Timing

Figure 51. MII Transmit Timing

16.6.3 GMAC MII 50MHz

GMAC MII 50MHz spec apply to GMAC only. Table 39. GMAC MII 50MHz Table continues on the next page...

Table 39. GMAC MII 50MHz (continued)

1. Input timing assumes an input signal slew rate of 3ns (20%/80%).
2. Output timing valid for maximum external load CL = 25pF, which is assumed to be a 10pF load at the end of a 50Ohm,

series resistance in the transmission line should be matched closely to the selected RDSON of the I/O pad output driver. Figure 52. MII 50MHz Receive Timing Figure 53. MII 50MHz Transmit Timing

16.6.4 GMAC and PFE RMII

Table 40. GMAC and PFE RMII Table continues on the next page...

Table 40. GMAC and PFE RMII (continued)

1. Input timing assumes an input signal slew rate of 3ns (20%/80%).
2. Output timing valid for maximum external load CL = 25pF, which is assumed to be a 10pF load at the end of a 50Ohm,

series resistance of the transmission line should be matched closely to the RDSON of the I/O pad output driver. Figure 54. RMII Receive Timing Figure 55. RMII Transmit Timing

16.6.5 GMAC and PFE RGMII

You must set SRE[2:0]=101 for PFE_MAC0_TX_CLK in RGMII mode of PFE GMAC0 at 3.3V. Table 41. GMAC and PFE RGMII Table continues on the next page...

16.6.6 GMAC and PFE SGMII

Table 42. GMAC and PFE SGMII

2.5 Gbps data rate

Table continues on the next page...

Table 42. GMAC and PFE SGMII (continued)

1. VOD at 3.125Gbps is only applicable for PFE_MAC0.
2. The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the un-shaded region of the figure

0.10 UI p-p

8.5 UI p-p

Figure 58. SGMII Timing

16.12 USB-ULPI

Table 43. USB-ULPI

1. Input timing assumes an input signal slew rate of 3ns (20%/80%).

1. Output timing valid for maximum external load CL = 25pF, which is assumed to be a 10pF load at the end of a 50Ohm,

the series resistance of the transmission line should match closely to the RDSON of the I/O pad output driver. Figure 59. ULPI Mode Interface Timing

16.8 Memory interfaces

16.8.1 QuadSPI

An external resistor is needed to pull up a QuadSPI chip select signal. The SRE[2:0]=100 for 18GPIO pads and SRE[2:0]=101 for 1833Fast pads is the required drive setting to meet the timing. FLSHCR[TCSS] and FLSHCR[TCSH] should be set to 3. All transitions measured at mid-supply (VDD_IO_QSPI/2). Table 44. QuadSPI Quad 1.8V DDR 66MHz Table continues on the next page...

Table 44. QuadSPI Quad 1.8V DDR 66MHz (continued)

1. Output timing valid for maximum external load CL = 20pF, which is assumed to be a 10pF-15pF load at the end of a

in the transmission line should be matched closely to the selected RDSON of the I/O pad output.

1. Input timing assumes maximum input signal transition of 1ns (20%/80%).
2. Where m=TCSS and n=TCSH-1.
3. Data valid window includes DLL Margin, and determines LEARNING skew targets which can be more pessimistic than

The SRE[2:0]=100 for 18GPIO pads and SRE[2:0]=101 for 1833Fast pads is the required drive setting to meet the timing. FLSHCR[TCSS] and FLSHCR[TCSH] should be set to 3. All transitions measured at mid-supply (VDD_IO_QSPI/2). Table 45. QuadSPI Octal 1.8V SDR 133MHz tIH_SCK Input hold time (w.r.t.

1. Output timing valid for maximum external load CL = 20pF, which is assumed to be a 10pF-15pF load at the end of a

in the transmission line should be matched closely to the selected RDSON of the I/O pad output.

1. Input timing assumes maximum input signal transition of 1ns (20%/80%).
2. Where m=TCSS and n=TCSH-1.

The information in this section applies to Octal- and Hyperflash.

The SRE[2:0]=100 for 18GPIO pads and SRE[2:0]=101 for 1833Fast pads is the required drive setting to meet the timing. FLSHCR[TCSS] and FLSHCR[TCSH] should be set to 3. All transitions measured at mid-supply (VDD_IO_QSPI/2). Table 46. QuadSPI Octal 1.8V DDR 100MHz tIH_DQS Input hold time (w.r.t.

1. Input timing assumes maximum input signal transition of 1 ns (20%/80%). DQS denotes external strobe provided by the
2. Output timing valid for maximum external load CL = 20pF, which is assumed to be a 10pF-15pF load at the end of a

in the transmission line should be matched closely to the selected RDSON of the I/O pad output.

1. Where m=TCSS and n=TCSH-1.

The information in this section applies to Octal- and Hyperflash. The SRE[2:0]=100 for 18GPIO pads and SRE[2:0]=101 for 1833Fast pads is the required drive setting to meet the timing. FLSHCR[TCSS] and FLSHCR[TCSH] should be set to 3. All transitions measured at mid-supply (VDD_IO_QSPI/2). Table 47. QuadSPI Octal 1.8V DDR 133MHz Table continues on the next page...

Table 47. QuadSPI Octal 1.8V DDR 133MHz (continued) tIH_DQS Input hold time (w.r.t.

1. Input timing assumes maximum input signal transition of 1 ns (20%/80%). DQS denotes external strobe provided by the
2. Output timing valid for maximum external load CL = 20pF, which is assumed to be a 12pF-15pF load at the end of a

in the transmission line should be matched closely to the selected RDSON of the I/O pad output.

1. Where m=TCSS and n=TCSH-1.

The SRE[2:0]=100 for 18GPIO pads and SRE[2:0]=101 for 1833Fast pads is the required drive setting to meet the timing. FLSHCR[TCSS] and FLSHCR[TCSH] should be set to 3. All transitions measured at mid-supply (VDD_IO_QSPI/2). Table 48. QuadSPI Octal 1.8V SDR 100MHz tIH_SCK Input hold time (w.r.t.

1. Input timing assumes an input signal transition of 1ns (20%/80%).
2. Output timing valid for maximum external load CL = 20pF, which is assumed to be a 10pF-15pF load at the end of a

of the transmission line should be matched closely to the selected RDSON of the I/O pad output driver.

1. Where m=TCSS and n=TCSH-1.

The SRE[2:0]=100 for 18GPIO pads and SRE[2:0]=101 for 1833Fast pads is the required drive setting to meet the timing. FLSHCR[TCSS] and FLSHCR[TCSH] should be set to 3. All transitions measured at mid-supply (VDD_IO_QSPI/2). Table 49. QuadSPI Quad 1.8V SDR 133MHz tIH_SCK Input hold time (w.r.t.

1. Output timing valid for maximum external load CL = 20pF, which is assumed to be a 10pF-15pF load at the end of a

in the transmission line should be matched closely to the selected RDSON of the I/O pad output.

1. Input timing assumes maximum input signal transition of 1ns (20%/80%).
2. Where m=TCSS and n=TCSH-1.

The SRE[2:0]=100 for 18GPIO pads and SRE[2:0]=101 for 1833Fast pads is the required drive setting to meet the timing. FLSHCR[TCSS] and FLSHCR[TCSH] should be set to 3. All transitions measured at mid-supply (VDD_IO_QSPI/2). Table 50. QuadSPI Quad 3.3V DDR 66MHz Table continues on the next page...

Table 50. QuadSPI Quad 3.3V DDR 66MHz (continued)

1. Output timing valid for maximum external load CL = 20pF, which is assumed to be a 10pF-15pF load at the end of a

in the transmission line should be matched closely to the selected RDSON of the I/O pad output.

1. Input timing assumes maximum input signal transition of 1ns (20%/80%).
2. Where m=TCSS and n=TCSH-1.
3. Data valid window includes DLL Margin, and determines LEARNING skew targets which can be more pessimistic than

The SRE[2:0]=100 for 18GPIO pads and SRE[2:0]=101 for 1833Fast pads is the required drive setting to meet the timing. FLSHCR[TCSS] and FLSHCR[TCSH] should be set to 3. All transitions measured at mid-supply (VDD_IO_QSPI/2). Table 51. QuadSPI Quad 3.3V SDR 104MHz tIH_SCK Input hold time (w.r.t.

1. Timing valid for maximum external load CL = 20pF, which is assumed to be a 10pF-15pF load at the end of a 50ohm,

transmission line should be matched closely to the selected RDSON of the I/O pad output driver.

1. Input timing assumes maximum input signal transition of 1ns (20%/80%).
2. Where m=TCSS and n=TCSH-1.

The information in this section applies to Octal- and Hyperflash. The SRE[2:0]=000 for 18GPIO pads is the required drive setting to meet the timing. FLSHCR[TCSS] and FLSHCR[TCSH] should be set to 3. Table 52. QuadSPI Octal 1.8V DDR 166MHz tIH_DQS Input hold time (w.r.t.

1. Output timing valid for maximum external load CL = 20pF, which is assumed to be a 12pF-15pF load at the end of a

in the transmission line should be matched closely to the selected RDSON of the I/O pad output.

1. Input timing assumes maximum input signal transition of 1 ns (20%/80%). DQS denotes external strobe provided by the
2. Where m=TCSS and n=TCSH-1.

SRE[2:0]=110 for CLK are the required drive settings to meet the timing for 18GPIO pad. FLSHCR[TCSS] and FLSHCR[TCSH] should be set to 3. Table 53. QuadSPI Octal 1.8V DDR 200MHz Table continues on the next page...

Table 53. QuadSPI Octal 1.8V DDR 200MHz (continued) tIH_DQS Input hold time (w.r.t.

1. Output timing valid for maximum external load CL = 20pF, which is assumed to be a 12pF-15pF load at the end of a

in the transmission line should be matched closely to the selected RDSON of the I/O pad output.

1. Input timing assumes maximum input signal transition of 1 ns (20%/80%). DQS denotes external strobe provided by the
2. Where m=TCSS and n=TCSH-1.

16.8.12 QuadSPI configurations

as per Table 55 is not exceeded. Table 54. QuadSPI configurations Table continues on the next page...

Table 54. QuadSPI configurations (continued)

16.8.13 QuadSPI interfaces

Table 55. QuadSPI interfaces

16.8.14 QuadSPI timing diagrams

data launch from the device. Figure 60. CS output timing Figure 61. SDR input timing Figure 62. DDR output timing

Figure 63. DDR with internal pad loopback input timing Figure 64. DDR edge-aligned DQS input timing

16.9 DDR

16.9.1 DDR

1. LPDDR4 SDRAM compliant to JEDEC209-4B LPDDR4 JEDEC standard release.
2. DDR3L SDRAM compliant to JESD79-3-1A DDR3L JEDEC standard release July, 2010.

requirements stated in the chip's Hardware Design Guide Document. LPDDR4 routing constraints are documented in the chip's Hardware Design Guidelines Document.

16.9.2 DDR Common DC Input

otherwise specified, all input specifications (both common and DDR standard specific) are measured at the host PHY input pins. Subsequent sections list input parameters for the specific memory interface standards.

Table 56. DDR Common DC Input

1. Leakage is valid for Vref over the range 0 <= VIN <= VDD_IO_DDR0, with Vref input function enabled. All pins not under
2. Leakage current is measured when the pin is configured to a high-impedance state with all on-die termination disabled.

16.9.3 DDR Common DC Output

Table 57. DDR Common DC Output

1. Calibrated at VDD_IO_DDR0 / 2.
2. For the DDR0_RESET_B pin and CKE pin, the driver is in maximum strength and impedance value is process dependent.

NOTE: Refer to IBIS model for the complete IV curve characteristics.

16.9.4 DDR3L DC Input

Table 58. DDR3L DC Input

1. Externally supplied Vref is not recommended. Internal Vref generation through local Vref generation at each receiver is
2. If the external Vref to the receivers is enabled, DDR0_VREF is expected to be set to a nominal value of

the eye height since a change in Vref also changes the input receiver common mode, altering receiver performance.

16.9.5 DDR3L Output Timing

Table 59. DDR3L Output Timing

1. All measurements are in refernce to the Vref level.
2. Measurements were done with signals terminated with a 50ohm resistor terminated to VDD_IO_DDR0/2, Phy output is

TxSlewRate was set 0x3FF (PreDrvMode=3, PreN=F,PreP=F). Figure 65. DDR3L Output Timing

16.9.6 LPDDR4 DC Input timing

Table 60. LPDDR4 DC Input timing

1. Because termination at the DRAMs is configurable, there is no fixed setting. The Vref value is dependent on driver

impedance Ron and system effective ODT impedance Rtt.

1. Externally supplied Vref is not recommended. Internal Vref generation through local Vref generation at each receiver is

16.9.7 LPDDR4 Output Timing

Table 61. LPDDR4 Output Timing

1. Measurements were done with signals terminated with a 50ohm resistor terminated to VSS, Phy output is calibrated to a

set 0x1FF (PreDrvMode=1, PreN=F, PreP=F).

1. tDOeye is trained to be shifted min 200 ps from DQS edge (tDQS2DQ learning).
2. Tx DQS to MCLK edges are trained to be aligned.
3. Addr/Cmd is centered aligned by training.

Figure 66. LPDDR4 Output Timing The SRE[2:0]=101 is required drive setting to meet the timing. All uSDHC parameters are measured at mid-supply (VDD_IO_SDHC/2).

Table 62. uSDHC SD3.0/eMMC5.1 DDR

1. Output timing valid for maximum external load CL = 25pF, which is assumed to be a 10pF load at the end of a 50Ohm,

un-terminated, 5 inch microstrip trace on standard FR4 (1.5pF/inch), (25pF total with margin).

1. The SDHC_CLK rise/fall time specification applies to the input clock transition required in order to meet the output delay

pad specifications for detail.

1. Input timing assumes an input signal slew rate of 3ns (20%/80%).

Figure 67. SD3.0/eMMC5.1 DDR Mode Interface Timing The SRE[2:0]=101 is required drive setting to meet the timing. All uSDHC parameters are measured at mid-supply (VDD_IO_SDHC/2). Table 63. uSDHC SD3.0/SDIO3.0/eMMC5.1 SDR

1. In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7V to 3.6V.
2. Output timing valid for maximum external load CL = 25pF, which is assumed to be a 10pF load at the end of a 50Ohm,

un-terminated, 5 inch microstrip trace on standard FR4 (1.5pF/inch), (25pF total with margin).

1. In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,

clock frequency can be any value between 0–50 MHz.

1. In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode,

clock frequency can be any value between 0–52 MHz.

1. The SDHC_CLK rise/fall time specification applies to the input clock transition required in order to meet the output delay

pad specifications for detail.

1. Input timing assumes an input signal slew rate of 3ns (20%/80%).

Figure 68. SD3.0/SDIO3.0/eMMC5.1 SDR Mode Interface Timing The SRE[2:0]=101 is required drive setting to meet the timing. All uSDHC parameters are measured at mid-supply (VDD_IO_SDHC/2). Table 64. uSDHC SDR-100MHz

1. Output timing valid for maximum external load CL = 15pF, which is assumed to be a 10pF load at the end of a 50Ohm,

transmission line should be matched closely to the RDSON of the I/O pad output driver.

1. The SDHC_CLK rise/fall time specification applies to the input clock transition required in order to meet the output delay

pad specifications for detail.

1. Input timing assumes an input signal slew rate of 1ns (20%/80%).

Figure 69. SDR-100 Mode Interface Timing The SRE[2:0]=000 is required drive setting to meet the timing. All uSDHC parameters are measured at mid-supply (VDD_IO_SDHC/2). Table 65. uSDHC SDR-HS200

1. Output timing valid for maximum external load CL = 15pF, which is assumed to be a 10pF load at the end of a 50Ohm,

transmission line should be matched closely to the RDSON of the the I/O pad output driver.

1. The SDHC_CLK rise/fall time specification applies to the input clock transition required in order to meet the output delay

pad specifications for detail.

1. Input timing assumes an input signal slew rate of 1ns (20%/80%).
2. Input timing also applicable for SDHC_CMD also.

Figure 70. HS200 Mode Interface Timing transitions measured at mid-supply. Table 66. uSDHC DDR-HS400

1. Output timing valid for maximum external load CL = 15 pF, which is assumed to be a 10 pF load at the end of a 50Ohm,

transmission line should be matched closely to the RDSON of the I/O pad output driver.

1. The SDHC_CLK rise/fall time specification applies to the input clock transition required in order to meet the output delay

pad specifications for detail.

1. Board skew margin between CLK and DATA/CMD is considered as +/-50 ps in calculations
2. Input timing assumes an input signal slew rate of 1ns (20%/80%).
3. Spec numbers SD6 and SD7 are also applicable for the CMD input timing for HS400 mode in enhanced strobe mode. For

HS400 mode without enhanced strobe, CMD input timing is the same as for HS200 mode.

Figure 71. HS400 Mode Interface Timing

16.11 Debug modules

16.11.1 JTAG Boundary Scan

The following table gives the JTAG specifications in boundary scan mode. The SRE[2:0]=100 or SRE[2:0]=101 is required drive setting to meet the timing. Table 67. JTAG Boundary Scan Table continues on the next page...

Table 67. JTAG Boundary Scan (continued)

1. JTAG port interface speed only. Does not apply to boundary scan timing.
2. These specifications apply to JTAG boundary scan mode only.
3. TCK pin must have external pull down.
4. The TCK rise/fall time specification applies to the input clock transition required in order to meet the TDO output

specifications that are relative to TCK.

1. Input timing assumes an input signal slew rate of 3ns (20%/80%).
2. Output timing valid for maximum external load CL = 25pF, which is assumed to be a 10pF load at the end of a 50Ohm,

series resistance of the transmission line should be matched closely to the selected RDSON of the I/O pad output driver.

1. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
2. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

Figure 72. JTAG TCK Input Timing

Figure 75. Boundary Scan Timing

16.11.2 JTAG Debug Interface Timing

The following table gives the JTAG specifications in debug interface mode. Table 68. JTAG Debug Interface Timing Table continues on the next page...

Table 68. JTAG Debug Interface Timing (continued)

1. Maximum frequency for TCK is limited to 6MHz during BOOTROM startup of the device, when the system clock is the
2. TCK pin must have external pull down.
3. Input timing assumes an input signal slew rate of 3ns (20%/80%).
4. Output timing valid for maximum external load CL = 25pF, which is assumed to be a 10pF load at the end of a 50Ohm,

series resistance of the transmission line should be matched closely to the RDSON of the I/O pad output driver.

1. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

Figure 76. JTAG debug Interface Timing

16.11.3 SWD electrical specifications

transition of 1ns and pad configured SRE[2:0] =100.

Table 69. SWD electrical specifications Figure 77. SWD Input Clock Timing

Figure 78. SWD Output Data Timing

17 Pinouts

For package pinouts and signal descriptions, see device Reference Manual.

18 Packaging

The S32G3 is offered in the following package types. number or see below figures.

Figure 79. Package outline

Figure 80. Soldering footprint part 1 of 3

Figure 81. Soldering footprint part 2 of 3

Figure 82. Soldering footprint part 3 of 3

Figure 83. Package outline notes

The following table lists the changes in this document. Rev 2, Feb 2023

• In section "Absolute Max Ratings", updated figure titlt to match with specifications "Input overshoot/undershoot voltage for each GPIO pad type".
• In section "Operating conditions", added note to Tj and Ta as "The junction temperature (Tj) range specification...".
• In section "Operating conditions", added figure "ADC supply sequencing".
• In section "GPIO pads": — for TR_TF_33 with SRE[2:0] = 100 changed min from 1.75V to 1.90V.
• In section "Temperature Monitoring Unit (TMU)", updated TRANGE min as -45 and max as 130 and added a footnote "Accuracy outside of operating range (-40 to 125) is not guaranteed.".
• In section "FXOSC", added paragraph as "In ALC disable mode the minimum...".
• In section "PLL", added footnote to fPLL_DDR_PHI0 as "DDR PLL allows center-spread SSCG at...".
• In section "PLL", added footnotes to Jitter specifications to mention jitter dependancy.
• In section "FlexRay - RxD", deleted uCCLogic_1 and uCCLogic_2 specifications.
• In section "PCIe", updated paragraph "NXP internally does PCI-SIG TX...".
• In section "QuadSPI Octal 1.8V DDR 166MHz": — Updated voltage measurement levels "Data transitions measured at 30%/70% supply...". — Updated tIH_DQS min from 2.145 ns to 2.105 ns — Updated tISU_DQS min from -0.496 ns to -0.616 ns
• In section "QuadSPI Octal 1.8V DDR 200MHz": — Updated voltage measurement levels "Data transitions measured at 30%/70% supply...". — Updated SRE "In Single SRE configuration...". — Updated tOD_DATA for single and split SRE configurations. — Updated tIH_DQS min from 1.684 ns to 1.644 ns. — Updated tISU_DQS min from -0.466 ns to -0.586 ns.
• In section "QuadSPI configurations" SMPR[DLLFSMPF] is updated to 4 for 166 MHz.
• In section "uSDHC DDR-HS400": — Updated SRE "In Split SRE configuration SRE[2:0]=000...". — Updated voltage measurement levels "Data transitions measured at 35%/65% supply...". Table continues on the next page... NXP Semiconductors

Revision history

S32G3 Data Sheet, Rev. 2, 02/2023 Data Sheet: Technical Data 120 / 131

Rev 2, Feb 2023 — Updated tCL and tCH min to 2.35 ns. — Updated descriptions of tOD1 and tOD2 and updated its value to 0.65 ns. — Added tOD (uSDHC Output delay).

• Added package drawing.
• Datasheet classification updated to "Technical Data". Rev 2 Draft C, Sep 2022
• In "Absolute Max Ratings" — Added note "All specifications associated with VIN are measured at the SoC pin.". — Added spec Max LVDS RX or TX pin injection (IINJ_LVDS) — VIN specification: ◦ updated footnote "Absolute maximum DC VIN levels for a powered...". ◦ Added V_OS_US_10 for 1.8V and updated condition of overshoot and undershoot specifications.
• In section "Operating Conditions" Added footnoted to VIN_18 and VIN_33 "DC case limit. Overshoot/Undershoot beyond this range...".
• In section "Operating Conditions" IINJ_D is split into powered and unpowered and related footnotes added.".
• In section "Clock frequency ranges" added fSDHC_CLK for DDR HS400.
• In section "Device Power and Operating Current Specifications", for PVDD_STBY in condition corrected a typographic figure from VDD=0.8V, to VDD_STBY = 0.8V.
• Added section "Power-down".
• In section "Aurora PLL" added footnote to fPLL_CLKIN as "40MHz is the only internal input reference..".
• In section "Reset Duration" added a paragraph as "The durations specified "Reset Duration" table and the corresponding figures...." and addded below three figures: — Reset_b pad detailed behavior during core supply brownout — Reset_b pad detailed behavior during pad HV supply brownout — Reset_b pad detailed behavior during power down
• Below figure "RESET_B pad detailed behavior", added information as "he RESET_B pad behavior described in the diagram and the related VRSE_RESET_B parameter spec also apply to the case of core VDD droop after power-up.".
• In section "SIRC", PTA description changed from "SIRC Post Trim Accuracy" to "SIRC trimming resolution" and "SIRC Frequency Variation" condition updated to "Frequency variation across voltage and temperature range".
• In section "I2C" PER_CLK changed to MODULE_CLK.
• Added section "CAN".
• In QuadSPI sections, removed DQS and added condition as "fSCK duty cycle distortion is in the range of 45%-55%." Table continues on the next page... NXP Semiconductors

S32G3 Data Sheet, Rev. 2, 02/2023 Data Sheet: Technical Data 121 / 131

Rev 2 Draft C, Sep 2022

• In uSDHC: — Changed title from "uSDHC DDR-52MHz" to "uSDHC SD3.0/eMMC5.1 DDR" and from "uSDHC SDR-52MHz" to "uSDHC SD3.0/SDIO3.0/eMMC5.1 SDR" and other figure name updates. — In uSDHC added phrase as "All uSDHC parameters are measured at mid-supply (VDD_IO_SDHC/2)." — In "SDR-100 Mode Interface Timing" figure deleted SD5 and SD8. — In section "uSDHC SDR-HS200" added footnote to tODW as "Input timing also applicable for SDHC_CMD also.". — In "uSDHC DDR-HS400" added footnote to tRQ and tRQH as "Spec numbers SD6 and SD7 are also applicable for the CMD input timing for HS400 mode...". — Deleted some redundant figures. Rev 2 Draft B, May 2022
• In "GMAC and PFE RGMII" section added paragraph "You must set SRE[2:0]=101 for PFE_MAC0_TX_CLK in RGMII mode of PFE GMAC0 at 3.3V." Rev 2 Draft A, Apr 2022
• In "Block diagram" mentioned that the diagram represents the features of S32G399A, the superset chip in the S32G3 family.
• In section "Absolute maximum ratings": — Changed from ADC reference supply to ADC supply for "VAD_INPUT", min value changed from "VREFL_ADC - — Added more information to below footnotes attached to VIN: ◦ Absolute maximum DC VIN levels for a powered device.... ◦ Absolute minimum DC VIN level for a powered device is.... — Footnote attached to "IINJ_A" changed to "Allowed for a cumulative duration of 50 hours operation over the lifetime of the device at maximum Tj, with VDD_ADC <= 1.92V, VSS_ADC = 0V". — Added symbol names and footnote to overshoot specifications as "For AC signals, if VDD_IO ≤ 3.3V, max VIN overshoot is limited to...."
• In section "Operating Conditions": — Changed from ADC reference supply to ADC supply for "VAD_INPUT", min value updated from "VREFL_ADC - — Footnote attached to frequency specs updated to correct the modulation depth used in formula. Changed "...plus — For "VDD_EFUSE" specs, updated related footnote to add "See device hardware design guidelines document for more details." — Updated below footnotes attached to VIN_18 and VIN_33: Table continues on the next page... NXP Semiconductors

S32G3 Data Sheet, Rev. 2, 02/2023 Data Sheet: Technical Data 122 / 131

Rev 2 Draft A, Apr 2022 ◦ From: "Additional +0.3V are supported for DC signal." to "For AC signals, allowed max VIN ≤ VDD_IO* for ◦ From: "Absolute minimum level for VIN signal is -0.3V." to "The min DC VIN level for a powered device is — Footnote attached to "VRAMP_LV" is updated "On slow ramps, the RESET_B pin may be observed to be asserted..."

• Total power specifications updated for S32G398A (thermal use case) changed from 8.18 to 8.35 A, S32G379A (thermal
• In "Total power specifications" for 1.8V supply rail added in condition "All 1.8V supplies at 1.8V".
• Max values updated for the specs in section "Static power specifications for I/O Domains"
• In section "Device Power and Operating Current Specifications" : — For symbol "PVDD_STBY", typ value changed from 48 to 58 uW. — For symbol "PVDD_IO_STBY", typ value changed from 120 to 110 uW.
• In section "Device Power and Operating Current Specifications" for symbol "PVDD_IO_PCIEn" (Powered down state), max value changed from 1.4 to 1.5 mW.
• In section "Device Power and Operating Current Specifications" for symbol "PVDD_IO_PCIEn" with condition "All circuits enabled, VDD_IO_PCIEn=1.8V, Gen3 8Gbps, 2 lanes. Per IP instance", added footnote "This specification can be considered a worst case maximum..."
• In section "GPIO Pads", added symbols "VOL" and "VOH" and added a footnote attached to these symbols "For current at this voltage see IOL/IOH specs respectively".
• Removed a note "VOH/VOL values should be calculated based on the provided RDSON, IOH/IOL values and IBIS models" .
• In figure "1.8V/3.3V GPIO pad detailed behavior during power up", updated "weak pull-down" to "weak pull-down as per ILKG_3318 specification".
• Under the figure "1.8V/3.3V GPIO pad detailed behavior during power up", removed the paragraph "The weak pull-down is 100 Kohm and is separate from the usual selectable 12Kohm internal pull resistor…."
• In section "SAR ADC" , for symbol "VAD_INPUT" min value changed to "VSS_ADC" and max value changed to "VDD_ADC".
• In section "DFS", added symbol "PER_Jitter" with min value -30ps and max value 30ps with condition fDFS_CLKIN=2622 Mhz, Odd MFN.
• In section "PLL" : — Added symbol "fPLL_DDR_PHI0" with description "DDR PLL PHI0 Frequency" and min, max value 758 Mhz and condition DDR_CLK (3032MT/s). — Footnote "PLL refers to the Core, Peripheral, Accelerator, and DDR reference PLLs on the device" and "Spread spectrum clock modulation is only available on the Core, Accelerator and DDR reference PLLs" moved to the top of the section. — The formula for calculating the max frequency is updated in the related footnote "The max frequency in case of
• In PCIe specications external reference clock pins related specs are added. Table continues on the next page... NXP Semiconductors

S32G3 Data Sheet, Rev. 2, 02/2023 Data Sheet: Technical Data 123 / 131

Rev 2 Draft A, Apr 2022

• In section "GMAC and PFE SGMII", For symbol UI the description updated to "Unit interval (mean)".
• Added sentence "All transitions measured at mid-supply (VDD_IO_QSPI/2)" and removed "Clock measurements done with respect to VDD_IO_QSPI/2 level" in all QuadSPI modes.
• Removed symbol "tDVW" from the following sections: — "QuadSPI Quad 1.8V SDR 133MHz" — "QuadSPI Octal 1.8V DDR 100MHz" — "QuadSPI Octal 1.8V DDR 133MHz" — "QuadSPI Octal 1.8V DDR 166MHz" — "QuadSPI Octal 1.8V DDR 200MHz" — "QuadSPI Octal 1.8V SDR 100MHz" — "QuadSPI Octal 1.8V SDR 133MHz" — "QuadSPI Quad 3.3V SDR 104MHz"
• Added introduction sentence "The information in this section applies to Octal- and Hyperflash" in following sections : — QuadSPI Octal 1.8V DDR 100MHz — QuadSPI Octal 1.8V DDR 133MHz — QuadSPI Octal 1.8V DDR 166MHz
• In section "QuadSPI configurations", added introduction "The below table shows a subset of the QuadSPI module configurations for different speeds and data rate….".
• In section "QuadSPI configurations", updated SMPR[DLLFSMPF] setting for DDR-200MHz from 4 to 3.
• In section "DDR", updated the sentence to "LPDDR4 SDRAM compliant to JEDEC209-4B LPDDR4 JEDEC standard release."
• In section "DDR Common DC Output", for symbol "ROnPu" and "ROnPd", in description CLK changed to CKE outputs and footnote attached to them updated as "For the DDR0_RESET_B pin and CKE pin…."
• Added section "DDR3L DC Input Timing".
• Section name changed from "LPDDR4 DC Input" to "LPDDR4 DC Input Timing" and from "LPDDR4 Output" to "LPDDR4 Output Timing".
• Section "uSDHC DDR-HS400" updated thoroughly.
• Updated "Legal information" Rev 1, Nov 2021
• Updated datasheet classification to "Advance information"
• Updated Introduction, Feature comparison.
• In section "Absolute Max Ratings" and "Operating conditions", VDD_LV_PLL is deleted as it is shorted with VDD inside the die and this supply no longer needs to be driven from outside.
• In section "Absolute Max Ratings", for Symbol "VAD_INPUT" Min changed from "-0.3" to "VREFL_ADC -0.6". Table continues on the next page... NXP Semiconductors

S32G3 Data Sheet, Rev. 2, 02/2023 Data Sheet: Technical Data 124 / 131

Rev 1, Nov 2021

• In section "Absolute Max Ratings", for Symbol "VAD_INPUT" Max changed from "VREFH_ADC" to "VREFH_ADC + 0.5".
• In section "Absolute Max Ratings", for Symbol "VAD_INPUT" footnote added "Allowed for a cumulative duration of 50 ...".
• In section "Absolute Max Ratings" two footnotes attached to VIN are updated: — Absolute maximum VIN levels ... — Absolute minimum VIN level for ...
• In section "Absolute Max Ratings", for Symbol "IINJ_A" Min changed from "-2" to "-1".
• In section "Absolute Max Ratings", for Symbol "IINJ_A" Max changed from "2" to "1".
• In section "Absolute Max Ratings" in a footnote attached to IINJ_A "Non-disturb of ADC channels during current ...."
• In section "Operating Conditions", added note "ΔVDD* specifications are applicable to the supplies mentioned ...".
• In section "Operating Conditions", for Symbol "fSYS_A53" Max changed from "1100" to "1311".
• In section "Operating Conditions", SVS feature is removed.
• In section "operating conditions" removed "ΔVDD_IO_DDR" differential as this has a lone supply in its condition.
• In section "Operating Conditions", Symbol "VRAMP_HV" is seperated for 1.8V and 3.3V IOs and 3.3V IOs limit is updated to 50V/ms.
• In section "Operating Conditions", for Symbol "VAD_INPUT" Min changed from "VREFL_ADC" to "VREFL_ADC - 0.35".
• In section "Operating Conditions", for Symbol "VAD_INPUT" Max changed from "VREFH_ADC" to "VREFH_ADC + 0.25".
• In section "Operating Conditions", for Symbol "IINJ_A" Min changed from "-1 mA" to "-20 uA".
• In section "Operating Conditions", for Symbol "IINJ_A" Max changed from "1 mA" to "20 uA".
• In section "Operating Conditions", for Symbol "IINJ_A" footnote updated "The SAR ADC electrical specifications ar...".
• In section "Operating conditions" for symbol "ΔVDD_HV_18_ANA" added footnotes to clarify VDD_EFUSE supply conditions and added another footnote to say "VREFH_ADCn has a differential voltage of +/-100mV.".
• In section "Operating Conditions", for "LPDDR4 I/O voltage supply" typ value added as 1.1V.
• In section "Operating Conditions", footnote attached to IINJ_D is updated "IINJ_D specifications are per pin for an
• In section "Operating Conditions", added paragraph "The device hardware design guide summarizes ...".
• In section "Clock frequency ranges", removed some non applicable clocks.
• In section "Clock frequency ranges", for Symbol fA53_CORE_DIV2_CLK is updated to 655.5 MHz.
• In section "Clock frequency ranges", for Symbol fA53_CORE_DIV10_CLK is updated to 131.1 MHz.
• In section "Clock frequency ranges", for Symbol fXBAR_2X_CLK min added as 48 MHz.
• In section "Clock frequency ranges", for Symbol fPFE_MAC_2_TX_CLK and fPFE_MAC_2_RX_CLK max updated to 312.5 MHz.
• In section "Clock frequency ranges", for Symbol fSDHC_CLK min updated to 133 MHz.
• In section "Thermal Characteristics", added values.
• In section "Total power specifications for 0.8V and 1.8V Analog Domains", added 0.8V values. Table continues on the next page... NXP Semiconductors

S32G3 Data Sheet, Rev. 2, 02/2023 Data Sheet: Technical Data 125 / 131

Rev 1, Nov 2021

• In section "power sequencing" updated steps 3 and 4 and added note "For step 4, it is acceptable for the 1.8V ..."
• In section "Power sequencing", added a figure "1.8V supply timing with respect to PMIC_VDD_OK during Standby Mode Exit".
• In section "Aurora Pads", Symbol "VCM_LVDS_RX" and "VDIFF_LVDS_RX"is added.
• In section "PMC Bandgap", values added.
• In section "DFS", Symbol "fDFS_CORE_CLK2" and "fDFS_PER_CLK5" are removed.
• In section "DFS", formula is moved from footnote to sentence with some clarifications.
• In section "DFS", for Symbol "fDFS_PER_CLK2" max updated to 628 MHz and fDFS_CLKIN max updated to 2622 MHz.
• In section "FXOSC", added specs "VIH_EXTAL", "VIL_EXTAL", "CLOAD", "VCM_SE"
• In section "FXOSC", removed differential bypass mode specs which includes fBYP_DIFF and related figure.
• In section "PLL", removed ΔfPLL_MOD spec and all specs "with center-spread enabled" in conditon column. Added a footnote to specs which have "without center-spread enabled" in the condition column as "The max frequency in case of center-spread SSCG...".
• In section "PLL" added footnote to fPLL_CORE_VCO, fPLL_ACCEL_VCO and fPLL_DDR_VCO as "Same min frequency value applies for center-spread...".
• In section "PLL", for Symbol "fPLL_CORE_VCO" with condition "without center-spread SSCG enabled" Max changed from "2600" to "2622".
• In section "PLL", for Symbol "fPLL_PER_PHI5" with condition "PERIPH_PLL_PHI5" Max changed from "500" to "125".
• In section "PLL", for Symbol "fPLL_ACCEL_VCO" with condition "without center-spread SSCG enabled" Max changed from "2436" to "2400".
• In section "PLL", for Symbol "fPLL_CORE_PHI0" max updated to 1311 MHz.
• In section "SPI", for Symbol "tSUI" with condition "Master, MTFE=1, CPHA=0, SMPL_PTR = 1" footnote value added "N is number of protocol clock cycles whe...".
• In section "FlexRay - TxD", a missing spec is added "dCCTxD10".
• In all QuadSPI modes, moved footnote "Clock measurements done with respect to VDD_IO_QSPI/2 level." to top of the table
• In section "QuadSPI Quad 1.8V DDR 66MHz", Symbol "tISU_SCK" and "tIH_SCK" are deleted.
• In section "QuadSPI Quad 1.8V DDR 66MHz" added tLSKEW.
• In section "QuadSPI Octal 1.8V DDR 100MHz", Symbol "tCK2CKmin", "tCK2CKmax", "tIH_PCS" and "tISU_PCS" are deleted.
• In section "QuadSPI Octal 1.8V DDR 133MHz", Symbol "tCK2CKmin" and "tCK2CKmax" are deleted.
• In section "QuadSPI Quad 3.3V DDR 66MHz", Symbol "tISU_SCK" and "tIH_SCK" are deleted.
• In section "QuadSPI Quad 3.3V DDR 66MHz", Symbol "tLSKEW" is added.
• In section "QuadSPI Octal 1.8V DDR 166MHz/200MHz", updated SRE.
• In all QuadSPI sections updated TCSS and TCSH value is updated to 3.
• Section "QuadSPI interfaces" and "QuadSPI configurations" are updated. Table continues on the next page... NXP Semiconductors

S32G3 Data Sheet, Rev. 2, 02/2023 Data Sheet: Technical Data 126 / 131

Rev 1, Nov 2021

• In section DDR, added paragraph "DDR operation with the standards stated..." and "LPDDR4 routing constraints are documented ..."
• In section "uSDHC DDR-HS400" added min value to 133 MHz.
• In section "JTAG Boundary Scan", updated "The SRE[2:0]=100 or SRE[2:0]=101 is required drive setting to meet the timing.".
• In section "SWD electrical specifications", SRE updated to SRE[2:0]=100.
• Added section "Packaging".
• Updated "Security" and "Suitability for use" disclaimers. Rev 1 Draft E, July 2021
• Subsequent updates throughout the data sheet. Rev 1 Draft D, Apr 2021
• Subsequent updates throughout the data sheet. Rev 1 Draft C, Jan 2021
• Subsequent updates throughout the data sheet. Rev 1 Draft B, Apr 2020
• Subsequent updates throughout the data sheet. Rev 1 Draft A, Feb 2020
• Initial release. NXP Semiconductors

S32G3 Data Sheet, Rev. 2, 02/2023 Data Sheet: Technical Data 127 / 131

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AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, μVision, Versatile — are trademarks and/or registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere. The related technology may be protected by any or all of patents, copyrights, designs and trade secrets. All rights reserved. Airfast — is a trademark of NXP B.V. CodeWarrior — is a trademark of NXP B.V. ColdFire — is a trademark of NXP B.V. ColdFire+ — is a trademark of NXP B.V. CoolFlux — is a trademark of NXP B.V. CoolFlux DSP — is a trademark of NXP B.V. DESFire — is a trademark of NXP B.V. EdgeLock — is a trademark of NXP B.V. EdgeScale — is a trademark of NXP B.V. EdgeVerse — is a trademark of NXP B.V. elQ — is a trademark of NXP B.V. Freescale — is a trademark of NXP B.V. GreenChip — is a trademark of NXP B.V. HITAG — is a trademark of NXP B.V. ICODE and I-CODE — are trademarks of NXP B.V. Immersiv3D — is a trademark of NXP B.V. I2C-bus — logo is a trademark of NXP B.V. JCOP — is a trademark of NXP B.V. Kinetis — is a trademark of NXP B.V. Layerscape — is a trademark of NXP B.V. MagniV — is a trademark of NXP B.V. Mantis — is a trademark of NXP B.V. MIFARE — is a trademark of NXP B.V. MIFARE Classic — is a trademark of NXP B.V. MIFARE4Mobile — is a trademark of NXP B.V. MIFARE Plus — is a trademark of NXP B.V. MIFARE Ultralight — is a trademark of NXP B.V. MiGLO — wordmark and logo are trademarks of NXP B.V. NTAG — is a trademark of NXP B.V. NXP SECURE CONNECTIONS FOR A SMARTER WORLD — is a trademark of NXP B.V. PEG — is a trademark of NXP B.V. Processor Expert — is a trademark of NXP B.V. QorIQ — is a trademark of NXP B.V. QorIQ Qonverge — is a trademark of NXP B.V. RoadLINK — wordmark and logo are trademarks of NXP B.V. SafeAssure — is a trademark of NXP B.V. SafeAssure — logo is a trademark of NXP B.V. SmartMX — is a trademark of NXP B.V. Synopsys & Designware — are registered trademarks of Synopsys, Inc. Synopsys — Portions Copyright © 2021 Synopsys, Inc. Used with permission. All rights reserved. Tower — is a trademark of NXP B.V. UCODE — is a trademark of NXP B.V. VortiQa — is a trademark of NXP B.V. NXP Semiconductors Legal information S32G3 Data Sheet, Rev. 2, 02/2023 Data Sheet: Technical Data 130 / 131

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2023. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 02/2023 Document identifier: S32G3