S32E2

S32E27 NXP | Alldatasheet

Document overview

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• PDF pages: 155

Technical content

Datasheet sections

• 1 Introduction: S32E2/S32Z2 Family
• 1.1 Overview
• 1.2 Block diagram
• 1.3 Feature summary
• 2 Ordering information
• 3 Electrostatic Discharge (ESD) Characteristics
• 4 Maximum Ratings
• 4.1 Absolute Max Ratings
• 4.2 AE Absolute Maximum Ratings
• 5 Operating Conditions
• 5.1 Operating Conditions
• 5.2 AE Operating Conditions
• 7 DC Electricals
• 7.1 Device Power and Operating Current
• 7.2 Static power specifications for I/O Domains
• 7.3 Total power specifications
• 7.4 AE Device Power and Operating Current
• 8 Power Sequencing
• 8.1 Power-up
• 8.2 Power-down
• 9 Electromagnetic compatibility (EMC)
• 10 I/O Pad Characteristics
• 10.1 GPIO Pads
• 10.2 LVDS Pads
• 10.3 Reset related pad electrical characteristics
• 10.4 AE GPIO Input DC
• 10.5 AE GPIO Output DC
• 10.6 AE GPIO Output AC
• 11 Aurora Specifications
• 11.1 Aurora Pads
• 11.2 Aurora Port Timing
• 11.3 Aurora PLL
• 12 Power Management
• 12.1 PMC Bandgap
• 12.2 AE PMC Regulator
• 12.3 AE Supply Monitoring
• 13 Reset Duration
• 14 Peripheral Specifications
• 14.1 Clock and PLL Interfaces
• 14.1.1 Clock frequency ranges
• 14.1.2 PLL
• 14.1.3 DFS
• 14.1.4 FXOSC
• 14.1.5 FIRC
• 14.1.6 SIRC
• 14.1.7 LFAST PLL
• 14.1.8 AE IRC
• 14.2 Timer Modules
• 14.3 Communication Modules
• 14.3.1 I3C
• 14.3.1.1 I3C timing when communicating with Legacy I2C
• 14.3.2 LPI2C
• 14.3.3 SPI
• 14.3.4 Microsecond channel (MSC)
• 14.3.5 LIN
• 14.3.6 FlexRay
• 14.3.6.1 FlexRay - TxEN
• 14.3.6.2 FlexRay - TxD
• 14.3.6.3 FlexRay - RxD
• 14.3.7 NETC
• 14.3.7.1 NETC MII
• 14.3.7.2 NETC RMII
• 14.3.7.3 NETC RGMII
• 14.3.7.4 IEEE1588 interface
• 14.3.7.5 NETC management interface
• 14.3.8 SENT Interface
• 14.3.9 CAN
• 14.3.10 CANXL
• 14.3.11 PSI5
• 14.4 Memories and Memory Interfaces
• 14.4.1 QuadSPI
• 14.4.1.1 QuadSPI interfaces
• 14.4.1.11 QuadSPI configurations
• 14.4.1.12 QuadSPI timing diagrams
• 14.4.3 DDR
• 14.4.3.1 DDR Common DC Input
• 14.4.3.2 DDR Common DC Output
• 14.4.3.3 LPDDR4 Output Timing
• 14.4.4 Flash KGD
• 14.4.5 AE Flash Memory Specifications

• This document provides electrical specifications for S32E2, which includes the Application Extension (AE) subsystem.
• For functional characteristics and the programming model, see the S32E2 Reference Manual. S32E27 S32E2 Data Sheet Rev. 5 — 3 December 2024 Product Data Sheet

1 Introduction: S32E2/S32Z2 Family

1.1 Overview

S32E2 and S32Z2 are 32-bit Arm®-based real-time processors. They target real-time applications that require low latency and high performance, including applications for:

• Braking
• Hybrid and electric vehicles (HEVs/EVs)
• Safety
• Chassis
• Domain control S32E2 builds on and expands NXP's HEV/EV portfolio that includes products such as MPC5744P, MPC5777C, MPC5775B, and MPC5775E. S32E2 is an EV integration platform that supports applications such as:
• Electric traction motor control
• Hybrid control unit (HCU) control
• Advanced combustion engine management S32Z2 is a safety and domain controller that supports applications such as:
• Drive-by-wire
• Chassis control
• Autonomous vehicle drive control
• Domain control
• Battery management systems (BMS) S32E2 and S32Z2 are developed with 16 nm FinFET technology and target ISO 26262 Automotive Safety Integrity Level D (ASIL D).

1.2 Block diagram

Figure 1 shows the chip components. In this figure, orange component blocks vary across S32E2 and S32Z2. For details, see Feature summary. NXP Semiconductors S32E27 S32E2 Data Sheet S32E27 All information provided in this document is subject to legal disclaimers. © 2020 - 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 5 — 3 December 2024

10 Mb/100 Mb/1 Gb

32 KB L1I 16 KB L1D

1.8 V 12-bit SAR ADC x2 (8 ch total)

19 MB total SRAM with ECC

512 KB data flash memory with ECC

8 KB L1 l and D

32 KB I-cache

Figure 1. Chip block diagram

1.3 Feature summary

• Two core clusters, each of which: — Has four Arm Cortex®-R52 cores operating in two lockstep pairs, offering ASIL D performance with more than 6 kDMIPS — Can operate in non-lockstep, offering a total of up to 12 kDMIPS
• Arm Cortex-M33 system manager core operating in lockstep
• ISO 26262 ASIL D, including fail-operational modes, targeted throughout
• 25 GFLOPs math coprocessor and Arm Neon™ single instruction multiple data (SIMD) technology to execute advanced control algorithms
• Hardware support for virtualization throughout the system, from core to pin, to enable multi-application integration with freedom from interference
• Flash-memory options of 0, 16, 32, and 64 MB for S32E2 (all S32Z2 devices have 0 MB)
• Low-Power Double Data Rate flash-memory (LPDDR-F) interface supporting: — LPDDR flash memory for larger code footprints — LPDDR4 DRAM for temporary buffer storage
• Flexible low-latency communications engine (FlexLLCE), operating safely and securely with lockstep AES accelerator, to support CAN communications
• Zero-downtime over-the-air (OTA) updates
• Multiple options for motor control and combustion engine management: — GTM (optional for both S32E2 and S32Z2) — FlexPWM (S32E2 only) — eMIOS

Table 1. Feature summary

• Each cluster contains 4 cores organized as 2 lockstep pairs: 2 usable cores and 2 shadow cores.
• The 4 cores in each cluster can operate in a split-lock configuration, resulting in up to 8 usable cores. Core operating frequency 800 MHz (nominal) up to 1 GHz Core performance • 8 non-lockstep cores: 13 kDMIPS (800 MHz), 16 kDMIPS (1 GHz)
• 2 lockstep core pairs and 4 non-lockstep cores: 10 kDMIPS (800 MHz), 12 kDMIPS (1 GHz)
• 4 lockstep core pairs: 6.5 kDMIPS (800 MHz), 8 kDMIPS (1 GHz) Table continues on the next page... NXP Semiconductors S32E27 S32E2 Data Sheet S32E27 All information provided in this document is subject to legal disclaimers. © 2020 - 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 5 — 3 December 2024

Table 1. Feature summary...continued

512 KB: arranged as eight

64 KB sectors, with 4

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• NOR flash memory: up to 200 MHz DDR octal flash memory (×1, ×4, ×8 SDR/DDR possible)
• HyperRAM: up to 166 MHz with inline ECC Ultra Secured Digital Host Controller (uSDHC) 1 (supports SD and eMMC) Enhanced Direct Memory Access (eDMA) modules System eDMA controller 1 lockstep pair with 32 channels and Cyclic Redundancy Check (CRC) Peripheral eDMA controllers 1 with 32 channels 3 with 16 channels each Application Extension eDMA (eDMA_AE) 1 with 16 channels — Debug Trace Aurora, 4 lanes, 5 Gbit/s per lane with data input through Zipwire Peripherals Analog-to-digital converters (ADCs): 3.3 V or 5.0 V Five 12-bit Successive Approximation (SAR) ADCs (68 channels total) ADCs: 1.8 V Two 12-bit SAR ADCs (8 channels total) Motor control peripherals 2 FlexPWMs (12 channels each) 4 eTimers (6 channels each) —

3 Cross-Triggering

1 CTU

1 SINC (4 channels) —

2 Enhanced Modular Input/Output Subsystems (eMIOSs) (24 channels each)

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2 Ordering information

Flash memory size: All S32Z2 devices have 0 MB. Figure 2. Ordering information

3 Electrostatic Discharge (ESD) Characteristics

The following table gives the ESD ratings and test conditions for the device. Table 2. Electrostatic Discharge (ESD) Characteristics

1. Device failure is defined as: "If after exposure to ESD pulses, the device does not meet the device specification
2. All ESD testing conforms with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
3. This parameter is tested in conformity with AEC-Q100-002
4. This parameter is tested in conformity with AEC-Q100-011.

4 Maximum Ratings

4.1 Absolute Max Ratings

conditions are given in the Operating Conditions section of this document. All specifications associated with VIN are measured at the SoC pin. Table 3. Absolute Max Ratings Table continues on the next page...

Table 3. Absolute Max Ratings...continued Table continues on the next page...

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1. Absolute maximum ratings are stress ratings only, and functional operation beyond the operating condition maxima is not

the operating conditions table for functional specifications.

1. Allowed 0.88V – 0.96V for 60 seconds cumulative over lifetime with no operating restrictions, 2.0 hours cumulative over
2. Allowed 1.92V - 2.16V for 60 seconds cumulative over lifetime with no operating restrictions, 2.6 hours cumulative over
3. Allowed 3.52V - 4.0V for 60 seconds cumulative over lifetime with no operating restrictions, 2.6 hours cumulative over
4. VEXTAL/ VXTAL (min) is for powered condition. VEXTAL/VXTAL (min) can be lower in unpowered condition.
5. The maximum input voltage on the ADC input pins tracks with the ADC supply maximum. For the injection current

used for nominal calculations.

1. Allowed for a cumulative duration of 50 hours operation over the lifetime of the device at maximum Tj, with VDD_ANA <=

1.92V, VSS_ADC = 0V. Allowed for unlimited duration if the device is unpowered.

1. DC case limit. Overshoot/Undershoot beyond this range is allowed, but only for the limited durations as constrained by

temporal percentages of tSIGNAL. Unpowered devices must simultaneously follow IINJ_D unpowered current injection constraints. unpowered current injection constraints.

1. The maximum input voltage on the LVDS input pins tracks with the LVDS supply maximum. For the injection current

be used for nominal calculations.

1. IINJ_D specifications are per pin for an unpowered condition of the associated supply. The maximum simultaneous

injection per supply is 30mA.

1. Non-disturb of ADC channels during current injection cannot be guaranteed. The degradation in channel performance

cannot be specified due to the dynamic operation of the ADC input mux and potential for varying charge distribution. the channels not subject to current injection Offset error would be -12 LSB to 6 LSB and TUE would be -12 LSB to 8 LSB.

1. Applies exclusively to ZipWire, differential DSPI, and Microsecond interfaces and does not apply to Aurora. Allowed for a

power cycling or fully powered, the device must be either in reset, or out of reset with LVDS disabled.

1. Solder profile per IPC/JEDEC J-STD-020D.
2. Moisture sensitivity per JEDEC test method A112.
3. For AC Signals in a 3.3V supply domain, if VDD_IO ≤ 3.3V, max VIN overshoot is limited to VDD_IO+20%. If VDD_IO >

3.3V, then max VIN overshoot is limited to 4V.

1. For AC Signals in a 1.8V supply domain, max VIN overshoot is limited to VDD_IO+20% for 10% of tSIGNAL.

Figure 3. Soc-pin overshoot/undershoot voltage for each GPIO pad type

4.2 AE Absolute Maximum Ratings

conditions are given in the AE Operating Conditions section of this document. the listed maxima may affect device reliability or cause permanent damage to the device. Table 4. AE Absolute Maximum Ratings Table continues on the next page...

Table 4. AE Absolute Maximum Ratings...continued

1. Allowed 5.5V – 6.0V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset, TJ

=150 °C, remaining time at or below 5.5V.

1. Allowed 3.6V – 4.5V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset, TJ

=150 °C, remaining time at or below 3.6V.

1. Relative voltage value can be exceeded as long as current injection limits are met.
2. The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current
3. Allowed 1.365V – 1.45V for 10 hours cumulative over lifetime at maximum Tj = 150 °C, remaining time defined in AE

5 Operating Conditions

5.1 Operating Conditions

are valid, except where explicitly noted. Device behavior is not guaranteed for operation outside of the conditions in this table. All specifications associated with VIN are measured at the SoC pin. Table 5. Operating Conditions Table continues on the next page...

Table 5. Operating Conditions...continued Table continues on the next page...

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1. The operating conditions in this table apply as required conditions for all other specifications in this document, unless

explicitly noted as an exception in another section of this document.

1. Part numbers with a 10th character other than E have a lower maximum frequency at TJ = 150 °C or 125 °C (13th

character = M or V). See the "Ordering information" section.

1. The stated maximum operating frequency must be observed when using the PLL with frequency modulation enabled.

less than the stated maximum frequency.

1. Lifetime operation at Tj max not guaranteed. Standard automotive temperature profile assumed for performance and
2. Voltage regulation must be set to the 0.825V level to allow for load fluctuation within the minimum and maximum VDD

values shown here and to achieve the power consumption specifications shown in this document.

1. The SAE J2716_2016 standard recommended circuit should be used when connecting SENT signals to the 3.3V

VDD_IO_BF and VDD_IO_H input pads.

1. The VDD_EFUSE supply must be maintained within specification during fuse programming. Failure to do this may result in

improper functionality of the device after fuse programming.

1. VDD_EFUSE must be grounded when not actively programming the fuses. This supply is not required to be powered for

fuse reads. See device hardware design guidelines document for more details.

1. Refer to the Power Sequencing section for the relationship of VDD_EFUSE powering up/down relative to the core,

high-voltage, and I/O supplies.

1. For AC signals, allowed max VIN ≤ VDD_IO* for lifetime operation. If AC overshoot beyond VDD_IO* occurs, then refer

0.3V is allowed for lifetime operation.

1. DC case limit. Overshoot/Undershoot beyond this range is allowed, but only for the limited durations as constrained by

temporal percentages of tSIGNAL.

1. The min DC VIN level for a powered device is -0.3V. If AC undershoot below -0.3V occurs, then refer to the Abs Max

duration constraints as a function of the amount of undershoot.

1. LVDS max input voltage defined by the common-mode voltage VCM_LVDS_RX and the differential swing divided by two
2. The "voltage differential" refers to the difference between the lowest and highest voltages across all supplies within the

supply group as defined under Condition column.

1. Applies only during power up while POR_B is asserted.
2. Applies to multi-voltage supplies when operating in 1.8V range.
3. VREFH_ADCn allows a differential voltage of +/-100mV.
4. On slow ramps, the RESET_B pin may be observed to be asserted multiple times during the supply ramping. In order to

supply ramp or whenever POR_B is asserted.

1. The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current
2. IINJ_D specifications are per pin for an unpowered condition of the associated supply. The maximum simultaneous

injection per supply is 30mA.

1. You must ensure that neither IINJ nor VIN specs are violated. Negligible DC injection currents are expected to flow during
2. The SAR ADC electrical specifications are not guaranteed during any period when the operating injection current limit is

violated. These specifications are at maximum Tj and VREFH_ADC=1.8V; the injected current will reduce with reduced Tj. Figure 4. ADC supply sequencing

5.2 AE Operating Conditions

are valid, except where explicitly noted. AE device behavior is not guaranteed for operation outside of the conditions in this table.

Table 6. AE Operating Conditions

1. The motor control peripheral frequency is applicable to the eTimer, FlexPWM and the control logic of the CTU.
2. Motor Control Peripheral Frequency must be greater than or equal to ADC clock frequency.
3. VDDA must always be supplied even if the ADC is not used in the application.
4. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits.

1. The I/O pins on the device are clamped to the I/O supply rails (VDDH for digital pins and VREFP for analog pins) for ESD

6 Thermal Design, Characteristics, and Ratings

• Junction temperature of the device does not solely depend on package thermal resistance but is also a function of chip power dissipation, PCB attributes, environmental conditions (ambient temperature and air flow), and cumulative effects of other heat-generating ICs on the PCB.
• The appropriate thermal design must be implemented on the package so that it can safely dissipate the necessary amount of power needed for it to function properly. This design may involve adding a cooling solution on the package, creating thermal enhancements on the PCB, and improving environmental conditions.
• NXP encourages customers to use the package model to perform design and risk assessment through simulations. The sales team can provide package models in FloTHERM or Icepak formats under NDA. Thermal ratings:
• The following table provides S32E27x package thermal ratings for the 27 mm x 27 mm MAPBGA package. These numbers are derived through simulations based on standardized tests as described in the footnotes.
• Thermal resistance data in this report is solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not meant to predict the performance of a package in an application- specific environment.

Table 7. S32E27x, 27 mm x 27 mm 975 MAPBGA

1. Thermal test board meets JEDEC specification for this package (JESD51-9).
2. Determined in accordance with JEDEC JESD51-2A natural convection environment.
3. Junction-to-Case (top) thermal resistance determined using an isothermal cold plate. Case temperature refers to the

MAPBGA's mold surface temperature.

7 DC Electricals

7.1 Device Power and Operating Current Specifications

The device power consumption, operating current, and applicable conditions are given in the following table. Table 8. Device Power and Operating Current Specifications Table continues on the next page...

Table 8. Device Power and Operating Current Specifications...continued

60 Ohm transmit

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1. Base dynamic power includes SMU, HSE, DMA, peripherals, and clocks. It excludes RTU, DDR, and FlexLLCE clocks and
2. Cortex-R52 core typical dynamic power based on Dhrystone running with 80% activity factor on all eight Cortex-R52 cores

and executing DMA on the platform with 100% activity factor. RTU0 and RTU1 each account for half the spec value.

1. Power includes MC_CGM_6 clocking current at 400MHz plus DDR access current and excludes IO_DDR.
2. FlexLLCE typical dynamic power includes FlexLLCE subsystem clocks and peripherals plus all cores running Dhrystone.

7.2 Static power specifications for I/O Domains

Table 9. Static power specifications for I/O Domains

7.3 Total power specifications

power to compensate. The user must ensure the total supply rail power is below the total power distribution network capacity. specifications will result in IR drop issues and unpredictable operation of the device. Table 10. Total power specifications

1. The supply rail leakage and dynamic power cannot exceed the total supply rail power specification.
2. Total supply rail power is dynamic power plus leakage power.
3. The device cannot exceed the total dynamic power specification.

7.4 AE Device Power and Operating Current Specifications

The AE device power consumption, operating current, and applicable conditions are given in the following table. Table 11. AE Device Power and Operating Current Specifications

8 Power Sequencing

8.1 Power-up

within its specified operating voltage range before the next step in the sequence is started.

1. Set POR_B input to low value.
2. Ramp up all GPIO supplies and ADC references powered to 5V
3. Ramp up all 3.3V supplies including GPIO supplies powered to 3.3V
4. Ramp up all 1.8V supplies including GPIO supplies powered to 1.8V
5. Ramp up all 1.1V supplies.
6. Ramp up all 0.8V supplies
7. Set POR_B input to high value

T he 5V supplies can be powered after the 3.3V supplies with no issues on the device. powered up, the VDD_EFUSE supply pin can be powered up/down independent of the other supplies on the device.

8.2 Power-down

achieved, ensure that all supplies are below the Vpwrdwn level before powering up again. Table 12. Power-down

9 Electromagnetic compatibility (EMC)

EMC measurements to IC-level IEC standards are available from NXP Semiconductor on request.

10 I/O Pad Characteristics

10.1 GPIO Pads

Table 13. GPIO Pads Table continues on the next page...

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1. For current at this voltage see IOL/IOH specs respectively.
2. Fastest slew rate and lowest rise/fall time constraint required to meet high-speed interface timing such as QSPI, RGMII,

and uSDHC. Slower input transitions can be used for input signals with slow switching rates (<40 MHz).

1. The ISLEW has precedence over ITR_TF if the ITR_TF violates the implied range for a given ISLEW.
2. Input slew rate and rise/fall time limits must be adhered to in conjunction with the max input frequency limits given for
3. GPIO output transition time information can be obtained from the device IBIS model. IBIS models are recommended for

connected to an actual transmission line load.

1. I/O timing specifications are valid for the un-terminated 50ohm transmission line reference load given in the figure below.

resistance in the transmission line should be matched closely to the selected RDSON of the I/O pad output.

1. Rise/fall time specifications are derived from simulation model for the defined operating points (between 20% and

Figure 7. 1.8V and 3.3V GPIO pad detailed behavior during power up The high-impedance state level is shown based on the external pull-up being on the corresponding pad supply.

10.2 LVDS Pads

reference clock receiver, the CLKOUT LVDS transmitter, MSC, SPI and ZipWire. Table 14. LVDS Pads Table continues on the next page...

Table 14. LVDS Pads...continued Table continues on the next page...

1. The LVDS input pin maximum voltage given in the operating conditions section of the datasheet must be obeyed when

setting the common-mode and differential swing voltages seen by the LVDS receiver.

1. The high gain configuration is selected by programming MSCR501[RXCB] for Zipwire_0 and MSCR503[RXCB] for
2. When measuring leakage, both pad_p and pad_n should be shorted together and driven to 1.8V supply or ground
3. For pin leakage drive both pad_p and pad_n to high or low together and measure pin current

Figure 8. LFAST timing definition Figure 9. VDIFF_LVDS_TX pk-pk in single ended and differential mode

10.3 Reset related pad electrical characteristics

The following table gives the characteristics of the POR_B and RESET_B pads. Values not explicitly listed in this table can be found in the 'GPIO Pads’ section.

Table 15. Reset related pad electrical characteristics

1. ISLEW_RESET_B(Min) = MAX[30e-06, 0.002 * Vnoise_p_p * Fnoise], where Vnoise_p_p is peak-peak noise magnitude (in

V) and Fnoise is max noise frequency (in MHz).

0.8 V supply

Figure 10. RESET_B pad detailed behavior

of core VDD droop after power-up. Figure 11. Noise filtering on RESET_B pad and any required PMIC BIST has completed. See the ‘Power Sequencing’ section for details. operational range (i.e., a corresponding PMIC LVD or HVD event occurs).

10.4 AE GPIO Input DC

Table 16. AE GPIO Input DC Table continues on the next page...

Table 16. AE GPIO Input DC...continued

1. VDDH = VDD_HV_IO_D0 | VDD_HV_IO_D1

Figure 12. GPIO Input DC Characteristics

10.5 AE GPIO Output DC

Table 17. AE GPIO Output DC

1. VDDH = VDD_HV_IO_D0 | VDD_HV_IO_D1

10.6 AE GPIO Output AC

Table 18. AE GPIO Output AC Table continues on the next page...

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1. GPIO pad specifications are derived from Spice simulations and are not production tested.
2. VDDH = VDD_HV_IO_D0 | VDD_HV_IO_D1.
3. C LOAD is the total of the external load plus the output driver and package parasitic capacitance.
4. Measured in relation to V OH /V OL .

11 Aurora Specifications

11.1 Aurora Pads

Table 19. Aurora Pads Table continues on the next page...

Table 19. Aurora Pads...continued

1. When operating at max speed, there will be losses and differential output will be smaller as against DC condition. Aurora

pad design. Direct end termination without AC coupling is not allowed.

1. Termination scheme as shown in the End Termination Circuit Figure. Direct end termination without AC coupling is not
2. Differential output is with pre-emphasis disabled, and a 10mA output stage current.
3. Differential output is with pre-emphasis enabled, and a ~15mA avg output stage current
4. UI @ 5Gbps equals 200ps. The valid eye is expected to be > 110ps in width. ISI jitter spec is 20-30ps for the LVDS

transmitter across PVT in a delay matched differential transmission line impedance of 100Ω.

1. VDD_IO maps to corresponding supply name on the device.

allowed through the internal termination inside LVDS Tx pad.

Figure 13. End Termination Circuit Figure 14. Source Termination Circuit

11.2 Aurora Port Timing

The following table gives the Aurora Port interface timing specifications for the device. Table 20. Aurora Port Timing Table continues on the next page...

Table 20. Aurora Port Timing...continued Figure 15. Aurora Debug Port Timing

11.3 Aurora PLL

achieves a maximum output frequency of 5GHz.

Table 21. Aurora PLL Table continues on the next page...

Table 21. Aurora PLL...continued

1. Refer to the LVDS Pad specifications for additional Aurora PLL reference clock electrical specifications. Also see " Aurora

Debug Port Timing" figure for fPLL_CLKIN as spec number 1.

1. 100MHz is the only input reference frequency supported for the Aurora PLL.
2. 40MHz is the only internal input reference frequency supported for the Aurora PLL.
3. It is Aurora PLL Input Reference Clock Frequency after pre-divider.
4. The Aurora PLL is only validated at the frequencies specified within this table - these frequencies correspond to the limited

set of Aurora data lane rates that are supported for the device.

12 Power Management

12.1 PMC Bandgap

Table 22. PMC Bandgap

1. ADC conversion error must be included when reading the bandgap reference voltage via the chip ADC.

12.2 AE PMC Regulator

Table 23. AE PMC Regulator

1. Degradation to 1.1uF is possible due to tolerance and aging.

12.3 AE Supply Monitoring

Table 24. AE Supply Monitoring Table continues on the next page...

Table 24. AE Supply Monitoring...continued

13 Reset Duration

reset plus the duration of the new sequence. The diagrams in this section are not to scale. Table 25. Reset Duration Table continues on the next page...

Figure 22. Reset_b pad detailed behavior during core supply brownout Figure 23. Reset_b pad detailed behavior during pad HV supply brownout

Figure 24. Reset_b pad detailed behavior during power down

14 Peripheral Specifications

14.1 Clock and PLL Interfaces

14.1.1 Clock frequency ranges

The following table gives the frequency range minimum and maximums to use when programming the clock dividers on the device. Table 26. Clock frequency ranges Table continues on the next page...

Table 26. Clock frequency ranges...continued Table continues on the next page...

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1. Part numbers with a 10th character other than E have a lower maximum frequency at TJ = 150 °C or 125 °C (13th

character = M or V). See the "Ordering information" section.

14.1.2 PLL

device. Actual operating frequencies for the device are constrained to the values given below. PLL refers to the Core, Peripheral, and DDR reference PLLs on the device.

Spread spectrum clock modulation is only available on the Core PLL and DDR reference PLLs. Table 27. PLL Table continues on the next page...

Table 27. PLL...continued

1. This refers to spec number 1 which is shown in the figure in Aurora port specifications
2. This specification is PLL input reference clock frequency after pre-divider.
3. Same min frequency value applies for center-spread SSCG enabled as provided for center-spread SSCG disabled.
4. The frequencies are the nominal frequencies (i.e., what the PLL's VCO is configured to).
5. The max frequency in case of center-spread SSCG enabled for a modulation depth can be calculated as: Max

SSCG disabled). For details, see section “Frequency modulation programming” in reference manual.

1. Duty cycle of the PLL clock when output on an external pin is given in the I/O pad specifications.
2. Part numbers with a 10th character other than E have a lower maximum frequency at TJ = 150 °C or 125 °C (13th

character = M or V). See the "Ordering information" section.

1. The DDR PHY internally multiplies the PLL_DDR_PHI0 by factor of two.
2. Jitter is dependent on supply noise. Specified jitter values are valid for the FXOSC reference clock input only - not valid for
3. Jitter value does not apply when a PLL clock is output on an external pin. In this case, the rise and fall time variations in

the I/O pad are orders of magnitude more than the PLL and SoC mux jitter contributions.

1. Jitter is dependent on the period of the PLL output clock, and the division ratio of the clock at the destination module.
2. For chip clocks that are further divided down from the PLL output clock, the jitter is multiplied by a factor of SQRT(N),

where N is the ratio of the PLL output clock and destination clock periods.

1. This specification is valid when all clock sources are stable.

14.1.3 DFS

The following table specifies the output frequency ranges and characteristics of the Digital Frequency Synthesizer (DFS). Table 28. DFS Table continues on the next page...

Table 28. DFS...continued

5 Frequency

1. Part numbers with a 10th character other than E have a lower maximum frequency at TJ = 150 °C or 125 °C (13th

character = M or V). See the "Ordering information" section.

1. For SoC clocks that are further divided down from the DFS output clock, the jitter is multiplied by a factor of SQRT(N),

where N is the ratio of the DFS output clock and destination clock periods.

1. Jitter value does not apply when the DFS clock is output on an external pin. In this case, the rise and fall time variations in

the I/O pad are orders of magnitude more than the DFS and SoC mux jitter contributions. jitter=Max(PER_jitter(PLL))*(sqrt(N)) +Max(PER_jitter(DFS)). Where N is the DFS division factor. All jitter numbers are in ps.

14.1.4 FXOSC

Table 29. FXOSC

1. All specifications only valid for this frequency range if the correct FXOSC transconductance setting is used.
2. Recommended crystal frequencies are 20MHz, 24MHz, 25MHz and 40MHz.
3. The input clock signal should be symmetric around common mode voltage.
4. Account for on-chip stray capacitance (CS_XTAL) and PCB capacitance in the total XTAL/EXTAL pin load capacitance.

CS_XTAL don't include miller capacitance. has a load cap of 8 pF and configure gm_sel[3:0]=4'b100. load cap of 8 pF and configure gm_sel[3:0]=4'b0110. configure gm_sel[3:0]=4'b1111. In ALC disable mode the minimum crystal drive level should be greater than 500uW. clock (FXOSC) should adhere to this specification.

14.1.5 FIRC

Table 30. FIRC

1. ðfVAR defines how much the output frequency can shift over the specified temperature and voltage ranges of the device

14.1.6 SIRC

Table 31. SIRC

1. PTA defines how close the output frequency is to target after the initial factory trim.

1. ðfVAR defines how much the output frequency can shift over the specified temperature and voltage ranges of the device.

14.1.7 LFAST PLL

Table 32. LFAST PLL

1. 40us max tLOCK assumes fPLL_CLKIN = 26MHz and default compare_clk_cycle value of 1040. Slower fPLL_CLKIN
2. Specification not valid when the LFAST PLL input clock is FIRC_CLK.

14.1.8 AE IRC

Table 33. AE IRC Table continues on the next page...

Table 33. AE IRC...continued

14.2 Timer Modules

Table 34. eMIOS

1. tPER_CLK is the period of the peripheral clock (PER_CLK) on the device.
2. Actual output pulse may be larger when considering a slow transitioning output.

Figure 25. EMIOS Timing

14.3 Communication Modules

14.3.1 I3C

and functionality of the I3C protocol.

14.3.1.1 I3C timing when communicating with Legacy I2C devices

Table 35. I3C timing when communicating with Legacy I2C devices Table continues on the next page...

Table 35. I3C timing when communicating with Legacy I2C devices...continued

1. Minimum time depends on bus loading. SRE of 111b should be used.

Figure 26. Legacy mode timing

Figure 27. tDIG_H and tDIG_L Figure 28. Definition of timing for F/S mode devices on the I2C bus

14.3.2 LPI2C

Table 36. LPI2C Table continues on the next page...

Table 36. LPI2C...continued Table continues on the next page...

Table continues on the next page...

1. For more details, see UM10204 I2C-bus specification and user manual.
2. Minimum time depends on bus loading. SRE of 111b should be used.

14.3.3 SPI

SRE[2:0]=101 is the required drive setting to meet the timing. Table 37. SPI Table continues on the next page...

Table 37. SPI...continued Table continues on the next page...

1. SMPL_PTR should be set to 1. For SPI_CTARn[BR] - 'Baud Rate Scaler' configuration is >= 3
2. The maximum SPI baud rate that is achievable in a dedicated master-slave connection depends on several parameters
3. Slave Receive Mode can operate at a maximum frequency of 60 MHz. In this mode, the DSPI can receive data on SIN, but

no valid data is transmitted on SOUT.

1. This value of 20 ns is with the configuration prescaler values: SPI_CTARn[PCSSCK] - "PCS to SCK Delay Prescaler"
2. This value of 20 ns is with the configuration prescaler values: SPI_CTARn[PASC] - "After SCK Delay Prescaler"
3. For the case of both master and slave being NXP S32x devices, frequency of operation will be reduced to

[1000 /2* {tSUI_master + tSUO_slave + PCB delay}] in ns.

1. Input timing assumes an input signal slew rate of 2ns (20%/80%).
2. N is number of protocol clock cycles where the master samples SIN in MTFE mode after SCK edge.
3. Output timing valid for maximum external load CL = 25 pF (includes PCB trace, package trace (around 1-2pF) and flash

Note that SPI operation should be done by selecting same pad type. A mix of 33 and 3318 pads for the same SPI is not supported. Slave mode timing values given below are applicable when device is in MTFE=0.

Figure 35. SPI PCS Strobe (PCSS) Timing

14.3.4 Microsecond channel (MSC)

Table 38. Microsecond channel (MSC)

1. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of SPI_CLKn. This

timing value is due to pad delays and signal propagation delays.

1. Measured at 20% to 80% of output voltage with tSCK=50Mhz.

Figure 36. MSC master timing, output only

14.3.5 LIN

SRE[2:0]=110 is the required drive setting to meet the timing. Table 39. LIN

14.3.6 FlexRay

14.3.6.1 FlexRay - TxEN

Table 40. FlexRay - TxEN Table continues on the next page...

Table 40. FlexRay - TxEN...continued

1. Output timing valid for maximum external load CL = 25 pF (includes PCB trace, package trace (around 1-2pF) and flash

Figure 37. TxEN Signal Propagation Delay Figure 38. TxEN Signal

14.3.6.2 FlexRay - TxD

Table 41. FlexRay - TxD Table continues on the next page...

14.3.6.3 FlexRay - RxD

Table 42. FlexRay - RxD

1. FlexRay RxD timing assumes an input signal slew rate of 2ns (20%/80%).

14.3.7 NETC

14.3.7.1 NETC MII

SRE[2:0]=100 is the required drive setting to meet the timing. Table 43. NETC MII Table continues on the next page...

Table 43. NETC MII...continued

1. Input timing assumes an input signal slew rate of 3ns (20%/80%).
2. Output timing valid for maximum external load CL = 25 pF (includes PCB trace, package trace (around 1-2pF) and flash

Figure 41. MII Receive Timing Figure 42. MII Transmit Timing

14.3.7.2 NETC RMII

SRE[2:0]=100 is the required drive setting to meet the timing.

Table 44. NETC RMII

1. Input timing assumes an input signal slew rate of 3ns (20%/80%).
2. Output timing valid for maximum external load CL = 25 pF (includes PCB trace, package trace (around 1-2pF) and flash

Figure 43. RMII Receive Timing Figure 44. RMII Transmit Timing

14.3.7.3 NETC RGMII

SRE[2:0]=100 is the required drive setting to meet the timing.

14.3.7.4 IEEE1588 interface

Table 46. IEEE1588 interface Figure 47. IEEE 1588 input AC timing

Note: The output delay is counted starting at the rising edge if tT1588CLKOUT is non-inverting. Otherwise, it is counted starting at the falling edge. Figure 48. IEEE 1588 output AC timing

14.3.7.5 NETC management interface

Table 47. NETC management interface

1. In the equations provided for Min and Max values, tENET_CLK is the NETC system clock period in nanoseconds, EHOLD

Figure 49. MDC / MDIO Timing

14.3.8 SENT Interface

Table 48. SENT Interface

1. Input hysteresis enabled on I/O pads with selectable enable/disable (per the SAE 2716 SENT standard). Does not apply to
2. By ensuring that the input fall transition is within the specification, SENT calibration and data bit errors are guaranteed

threshold level variation is due to input signal noise, supply noise, and temperature drift.

1. This value is the ratio of the maximum 6.5uS fall time and minimum 3uS clock (UI), and assumes the transmit, clock, and

measurement error tolerances as defined by the SAE 2716 SENT standard.

1. SENT inputs are supported at 3.3V on the device, with assumption that the input levels scale linearly for the recommended

3.3V circuit in the SAE 2716 SENT standard. The device does not support 1.8V or 5V SENT inputs.

14.3.9 CAN

See GPIO pads for CAN specifications.

14.3.10 CANXL

Table 49. CANXL

1. To guarantee a minimum of 5ns decode time at the transceiver, the CANXL internal PWM must be programmed to ensure

10ns <= PWMS <= 0.5 * tSymbolNom – 10ns. Figure 50. CANXL timing

14.3.11 PSI5

Table 50. PSI5 Table continues on the next page...

Table 50. PSI5...continued

1. Measured in PSI5 clock cycles. Minimum PSI5 clock period is 20ns.
2. Output timing valid for maximum external load CL = 25 pF (includes PCB trace, package trace (around 1-2pF) and flash
3. PSI5 sensor input signals must meet the duty cycle requirement in order to be decoded properly.

14.4 Memories and Memory Interfaces

14.4.1 QuadSPI

14.4.1.1 QuadSPI interfaces

QuadSPI_0 supports interface (side) A. QuadSPI_1 supports two interfaces: A and B. These interfaces are not independent. Table 51. QuadSPI interfaces

166 MHz

The SRE[2:0]=100 for 18FAST and 33GPIO pads and SRE[2:0]=101 for 3318 pads is the required drive setting to meet the timing.

FLSHCR[TCSS] and FLSHCR[TCSH] should be set to 2. transitions measured at mid-supply. Table 52. QuadSPI Quad 1.8V DDR 80MHz

1. Output timing valid for maximum external load CL = 20 pF (includes PCB trace, package trace (around 1-2pF) and flash
2. Input timing assumes maximum input signal transition of 1ns (20%/80%).
3. Where m=TCSS and n=TCSH-1.

The SRE[2:0]=100 for 33GPIO pads and SRE[2:0]=101 for 3318 pads is the required drive setting to meet the timing. FLSHCR[TCSS] and FLSHCR[TCSH] should be set to 2. transitions measured at mid-supply. Table 53. QuadSPI Quad 1.8V SDR 133MHz

1. fSCK of 133.33MHz is also acceptable.
2. Input timing assumes maximum input signal transition of 1ns (20%/80%).

1. Output timing valid for maximum external load CL = 20 pF (includes PCB trace, package trace (around 1-2pF) and flash
2. Where m=TCSS and n=TCSH-1.

The SRE[2:0]=100 for 33GPIO pads and SRE[2:0]=101 for 3318 pads is the required drive setting to meet the timing. FLSHCR[TCSS] and FLSHCR[TCSH] should be set to 2. transitions measured at mid-supply. Table 54. QuadSPI Octal 1.8V SDR 133MHz

1. Output timing valid for maximum external load CL = 20 pF (includes PCB trace, package trace (around 1-2pF) and flash
2. Input timing assumes maximum input signal transition of 1ns (20%/80%).
3. Where m=TCSS and n=TCSH-1.

The SRE[2:0]=000 for 18FAST, 33GPIO and 3318 pads is the required drive setting to meet the timing. FLSHCR[TCSS] and FLSHCR[TCSH] should be set to 2. transitions measured at mid-supply. Table 55. QuadSPI Octal 1.8V DDR 166MHz Table continues on the next page...

tIH_DQS Input hold time (w.r.t.

1. Input timing assumes maximum input signal transition of 1 ns (20%/80%). DQS denotes external strobe provided by the
2. Output timing valid for maximum external load CL = 20 pF (includes PCB trace, package trace (around 1-2pF) and flash
3. Where m=TCSS and n=TCSH-1.

The SRE[2:0]=000 for 18FAST, 33GPIO and 3318 pads is the required drive setting to meet the timing. FLSHCR[TCSS] and FLSHCR[TCSH] should be set to 2. transitions measured at mid-supply. Table 56. QuadSPI Octal 1.8V DDR 200MHz tIH_DQS Input hold time (w.r.t.

1. Input timing assumes maximum input signal transition of 1 ns (20%/80%). DQS denotes external strobe provided by the
2. Output timing valid for maximum external load CL = 20 pF (includes PCB trace, package trace (around 1-2pF) and flash
3. Where m=TCSS and n=TCSH-1.

The SRE[2:0]=100 for 33GPIO pads and SRE[2:0]=101 for 3318 pads is the required drive setting to meet the timing. FLSHCR[TCSS] and FLSHCR[TCSH] should be set to 2. transitions measured at mid-supply. Table 57. QuadSPI Quad 3.3V DDR 80MHz

1. Output timing valid for maximum external load CL = 20 pF (includes PCB trace, package trace (around 1-2pF) and flash
2. Input timing assumes maximum input signal transition of 1ns (20%/80%).
3. Where m=TCSS and n=TCSH-1.

The SRE[2:0]=100 for 33GPIO pads and SRE[2:0]=101 for 3318 pads is the required drive setting to meet the timing. FLSHCR[TCSS] and FLSHCR[TCSH] should be set to 2. transitions measured at mid-supply. Table 58. QuadSPI Quad 3.3V SDR 133MHz Table continues on the next page...

1. Input timing assumes maximum input signal transition of 1ns (20%/80%).
2. Output timing valid for maximum external load CL = 20 pF (includes PCB trace, package trace (around 1-2pF) and flash
3. fSCK of 133.33MHz is also acceptable.
4. Where m=TCSS and n=TCSH-1.

These specs are preliminary. The SRE[2:0]=100 for 33GPIO pads and SRE[2:0]=101 for 3318 pads is the required drive setting to meet the timing. FLSHCR[TCSS] and FLSHCR[TCSH] should be set to 2. transitions measured at mid-supply. Table 59. QuadSPI Quad 3.3V SDR 50MHz tIH_SCK Input hold time (w.r.t.

1. Where m=TCSS and n=TCSH-1.

The SRE[2:0]=100 for 33GPIO pads and SRE[2:0]=101 for 3318 pads is the required drive setting to meet the timing. FLSHCR[TCSS] and FLSHCR[TCSH] should be set to 2. transitions measured at mid-supply.

Table 60. QuadSPI Octal and HyperRAM 3.3V DDR 100MHz tIH_DQS Input hold time (w.r.t.

1. Input timing assumes maximum input signal transition of 1 ns (20%/80%). DQS denotes external strobe provided by the
2. Output timing valid for maximum external load CL = 20 pF (includes PCB trace, package trace (around 1-2pF) and flash
3. Where m=TCSS and n=TCSH-1.

14.4.1.11 QuadSPI configurations

The following table shows a subset of the QuadSPI module configurations for different speeds and data rates.

• DLLCR represents DLLCRA or DLLCRB, as applicable.
• SMPR[DLLFSMPF] represents SMPR[DLLFSMPFA] or SMPR[DLLFSMPFB], as applicable. NOTE

Table 61. QuadSPI configurations

200 MHz

80 MHz

100 MHz

133 MHz

50 MHz

Table continues on the next page...

Table 61. QuadSPI configurations...continued

1. The settings for MCR[DLPEN], which disable or enable the data learning pattern mechanism, derive from simulations and

testing. Users might need to alter these settings depending on delays or other behavior on their board.

14.4.1.12 QuadSPI timing diagrams

The SRE[2:0]=101 is required drive setting to meet the timing. transitions measured at mid-supply. Table 62. uSDHC SD3.0/eMMC5.1 DDR

1 SDR

Table continues on the next page...

1. Output timing valid for maximum external load CL = 25 pF (includes PCB trace, package trace (around 1-2pF) and flash
2. The SDHC_CLK rise/fall time specification applies to the input clock transition required in order to meet the output delay

pad specifications for detail.

1. Input signal timing assumes an input signal slew rate of 3ns (20%/80%).

Figure 56. SD3.0/eMMC5.1 DDR Mode Interface Timing The SRE[2:0]=000 is required drive setting to meet the timing. transitions measured at mid-supply. Table 63. uSDHC DDR-HS400 Table continues on the next page...

Table 63. uSDHC DDR-HS400...continued

1. Output timing valid for maximum external load CL = 15 pF (includes PCB trace, package trace (around 1-2pF) and flash
2. The SDHC_CLK rise/fall time specification applies to the input clock transition required in order to meet the output delay

pad specifications for detail.

1. Board skew margin between CLK and DATA/CMD is considered as +/-50 ps in calculations
2. Input signal timing assumes an input signal slew rate of 1ns (20%/80%).
3. Spec numbers SD6 and SD7 are also applicable for the CMD input timing for HS400 mode in enhanced strobe mode. For

HS400 mode without enhanced strobe, CMD input timing is the same as for HS200 mode. Figure 57. HS400 Mode Interface Timing The SRE[2:0]=101 is required drive setting to meet the timing.

transitions measured at mid-supply. Table 64. uSDHC SD3.0/SDIO3.0/eMMC5.1 SDR

1. In default speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode, clock

frequency can be any value between 0–50 MHz.

1. Output timing valid for maximum external load CL = 25 pF (includes PCB trace, package trace (around 1-2pF) and flash
2. In Legacy speed mode for MMC card, clock frequency can be any value between 0–26 MHz. In high-speed mode, clock

frequency can be any value between 0–52 MHz.

1. In SD/SDIO identification mode, card clock must be lower than 400 kHz, voltage ranges from 2.7V to 3.6V.
2. The SDHC_CLK rise/fall time specification applies to the input clock transition required in order to meet the output delay

pad specifications for detail.

1. Input signal timing assumes an input signal slew rate of 3ns (20%/80%).

Figure 58. SD3.0/SDIO3.0/eMMC5.1 SDR Mode Interface Timing The SRE[2:0]=000 is required drive setting to meet the timing. transitions measured at mid-supply. Table 65. uSDHC SDR-HS200

1. Output timing valid for maximum external load CL = 15 pF (includes PCB trace, package trace (around 1-2pF) and flash
2. The SDHC_CLK rise/fall time specification applies to the input clock transition required in order to meet the output delay

pad specifications for detail.

1. Input signal timing assumes an input signal slew rate of 1ns (20%/80%).

Figure 59. HS200 Mode Interface Timing

14.4.3 DDR

1. LPDDR4 SDRAM compliant to JEDEC209-4B LPDDR4 JEDEC standard release.

14.4.3.1 DDR Common DC Input

otherwise specified, all input specifications (both common and DDR standard specific) are measured at the host PHY input pins. Subsequent sections list input parameters for the specific memory interface standards. Table 66. DDR Common DC Input

1. Leakage current is measured when the pin is configured to a high-impedance state with all on-die termination disabled.

14.4.3.2 DDR Common DC Output

Table 67. DDR Common DC Output Table continues on the next page...

Table 67. DDR Common DC Output...continued

1. Calibrated at VDD_IO_DDR0 / 2.
2. For the DDR0_RESET_B pin and CKE pin, the driver is in maximum strength and impedance value is process dependent.

NOTE: Refer to IBIS model for the complete IV curve characteristics.

14.4.3.3 LPDDR4 Output Timing

Table 68. LPDDR4 Output Timing

1. Measurements were done with signals terminated with a 50ohm resistor terminated to VSS, Phy output is calibrated to a

set 0x1FF (PreDrvMode=1, PreN=F, PreP=F).

1. Tx DQS to MCLK edges are trained to be aligned.
2. tDOeye is trained to be shifted min 200 ps from DQS edge (tDQS2DQ learning).
3. Addr/Cmd is centered aligned by training.

Figure 60. LPDDR4 Output Timing

14.4.4 Flash KGD

Table 69. Flash KGD

1. You can use only block erase or chip erase (sector erase is not allowed). It does not support EEPROM emulation as well.

14.4.5 AE Flash Memory Specifications

14.4.5.1 AE Flash Program Erase

Table 70. AE Flash Program Erase Table continues on the next page...

Table 70. AE Flash Program Erase...continued Table continues on the next page...

1. Typical program and erase times represent the median performance and assume nominal supply values and operation at

25 °C. Typical program and erase times may be used for throughput calculations.

1. Program times are actual hardware programming times and do not include software overhead. Block program times

assume quad-page programming. Factory fast block program times assume factory fast quad-page programming.

1. Plant Programing times provide guidance for timeout limits used in the factory.
2. Typical End of Life program and erase times represent the median performance and assume nominal supply values.

Typical End of Life program and erase values may be used for throughput calculations.

1. Conditions: -40°C ≤ Tj ≤ 150°C, full spec voltage.

14.4.5.2 AE Flash Array

Table 71. AE Flash Array

1. The units for array integrity are determined by the period of the system clock. If unit accurate period is used in the

equation, the results of the equation are also unit accurate.

1. Array integrity times must be calculated and depend on system frequency and number of clocks per read. The equation

set to 2, Nread would equal 6-2, or 4).

14.4.5.3 AE Flash Module Life

Table 72. AE Flash Module Life

Figure 61. Flash Module Life

14.4.5.4 AE Flash AC Timing

Table 73. AE Flash AC Timing Table continues on the next page...

Table 73. AE Flash AC Timing...continued

14.4.5.5 AE Flash Read Latency

Table 74. AE Flash Read Latency Table continues on the next page...

Table 74. AE Flash Read Latency...continued

1. Cycle is defined as one cycle of the f SYS_AE clock.

14.5 Analog Modules

14.5.1 Temperature Monitoring Unit (TMU)

sensors connected to the TMU on the device. Table 75. Temperature Monitoring Unit (TMU)

1. Accuracy outside of operating range (-40 to 150) is not guaranteed.

14.5.2 SAR ADC

electrical specification are met. the external capacitance at the input pin and reference pin should be maximized. Table 76. SAR ADC Table continues on the next page...

Table 76. SAR ADC...continued Table continues on the next page...

1. The reduced limits for VAD_INPUT in this table are recommended for normal operation.
2. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal

sample clock tsample depend on programming.

1. 1Msps is the ADC output rate and includes both sampling and analog to digital conversion.
2. ADC performance specifications are guaranteed when calibration uses maximum averaging i.e. when AVGEN = 1 and
3. During calibration, the ADC determines its (positive or negative) offset value and stores the result in an internal register.
4. A positive calibration offset does not impact the max. code output of 4095. Calibration fails if it determines an offset
5. This specification is taken with averaging through post process ADC data.
6. The maximum and minimum leakage current values are reached when Vin=VREF and Vin=0, respectively.

1 LSB ideal = (VrefH-VrefL)/4096 =

1 LSB (ideal)

Figure 62. SAR ADC Specification Characteristics

Figure 63. SAR ADC Input Circuit

14.5.3 AE SAR ADC

Table 77. AE SAR ADC

2 Capacitance 2

Table continues on the next page...

Table 77. AE SAR ADC...continued

1. The ADC is fully functional with Vin from VREFL to VREFH, but performance specifications are only guaranteed within
2. ADC performance specifications are guaranteed without injection current on the input pin. Injection current limits and

lifetime durations are given in the Absolute Maximum Ratings section.

1. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal

sample clock tsample depend on programming.

1. Total conversion time is the sum of the sample time tSAMPLE and the conversion time tCONV.
2. No missing codes. During calibration, the ADC will determine the its offset value and store the result in an internal OCV

negative OCV value of 0xFFF8 or greater will cause that code 0 will never be the final ADC result.

1. If multiple ADCs are running in parallel, the same frequency must be used for f AD_CK for all ADCs. If the clocks are not synchronized, then a 12dB degradation in performance may be observed. Example of an actual transfer curve Gain Error GE Offset Error OSE Offset Error OSE Vin(A) (LSBideal)

1 LSB ideal = (SAR*_VRH-SAR*VRL)/4096=

5 V/4096 = 1.22 mV Total Unadjusted Error TUE = +/- 6 LSB = +/- 7.32 mV (2) (1) (5) (4) (1) The ideal transfer curve (2) Differential non-linearity error (DNL) (3) Integral non-linearity error (INL) (4) Center of a step of the actual transfer curve (5) (3) 2 3 4 5 6 7 4089 4091 4093 4095 4090 code out 4091 4092 4093 4094 4095 Figure 64. VA Source Filter Current Limiter EXTERNAL CIRCUIT RS Source Impedance RF Filter Resistance CF Filter Capacitance RL Current Limiter Resistance RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions: CP1, CP2) CS Sampling Capacitance INTERNAL CIRCUIT SCHEME CF CP1 CP2 CS RS RF RL RSW1 SAR*_VRH RAD Channel Selection Sampling Figure 65. NXP Semiconductors S32E27 S32E2 Data Sheet S32E27 All information provided in this document is subject to legal disclaimers. © 2020 - 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 5 — 3 December 2024

14.6 Motor Control

14.6.1 LCU

Table 78. LCU

1. tPER_CLK is the period of the peripheral clock (PER_CLK) on the device.
2. Actual output pulse may be larger when considering a slow transitioning output.

Figure 66. LCU timing

14.6.2 SINC timing

Table 79. SINC timing Table continues on the next page...

Table 79. SINC timing...continued Figure 67. SINC timing

14.7 Digital NanoEdge timing

Table 80. Digital NanoEdge timing

14.8 Glitch Filter

Table 81. Glitch Filter

1. An input signal pulse is defined by the duration between the input signal's crossing of a Vil/Vih threshold voltage level, and

the next crossing of the opposite level.

1. Pulses shorter than defined by the maximum value are guaranteed to be filtered (not passed).
2. Pulses in between the max filtered and min unfiltered may or may not be passed through.
3. See the device reference manual for which package pins include glitch filters on the pin input.
4. Pulses larger than defined by the minimum value are guaranteed to not be filtered (passed).

14.9 IRQ

The following table gives the input specifications for the external interrupt pins. For the AE subsystem, tCYC refers to FIRC_AE_CLK. Table 82. IRQ Figure 68. External Interrupt Timing (IRQ)

14.10 Debug

14.10.1 JTAG Boundary Scan

The following table gives the JTAG specifications in boundary scan mode. The SRE[2:0]=100 is required drive setting to meet the timing.

Table 83. JTAG Boundary Scan

1. These specifications apply to JTAG boundary scan mode only.
2. TCK pin must have external pull down.
3. JTAG port interface speed only. Does not apply to boundary scan timing.
4. The TCK rise/fall time specification applies to the input clock transition required in order to meet the TDO output

specifications that are relative to TCK.

1. Input timing assumes an input signal slew rate of 3ns (20%/80%).
2. Output timing valid for maximum external load CL = 25 pF (includes PCB trace, package trace (around 1-2pF) and flash
3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

Figure 72. Boundary Scan Timing

14.10.2 AE JTAG boundary scan

The following table gives the JTAG specifications in boundary scan mode for AE subsystem. The SRE[2:0]=100 is required drive setting to meet the timing. Table 84. AE JTAG boundary scan Table continues on the next page...

Table 84. AE JTAG boundary scan...continued

1. TCK pin must have external pull down.
2. JTAG port interface speed only. Does not apply to boundary scan timing.
3. These specifications apply to JTAG boundary scan mode only.
4. The TCK rise/fall time specification applies to the input clock transition required in order to meet the TDO output

specifications that are relative to TCK.

1. Input timing assumes an input signal slew rate of 3ns (20%/80%).
2. Output timing valid for maximum external load CL = 25pF, which is assumed to be a 10pF load at the end of a 50Ohm,

series resistance of the transmission line should be matched closely to the selected RDSON of the I/O pad output driver.

1. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
2. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

For respective timing diagrams, see section "JTAG Boundary Scan".

14.10.3 JTAG Debug Interface Timing

The following table gives the JTAG specifications in debug interface mode. Table 85. JTAG Debug Interface Timing Table continues on the next page...

Table 85. JTAG Debug Interface Timing...continued

1. Maximum frequency for TCK is limited to 6MHz during BOOTROM startup of the device, when the system clock is the
2. TCK pin must have external pull down.
3. Input timing assumes an input signal slew rate of 3ns (20%/80%).
4. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
5. Output timing valid for maximum external load CL = 25 pF (includes PCB trace, package trace (around 1-2pF) and flash

Figure 73. JTAG debug Interface Timing

14.10.4 SWD electrical specifications

The following table gives the Serial Wire Debug specifications for the device. transition of 1ns and pad configured SRE[2:0] =100. Table 86. SWD electrical specifications the transmission line should be matched closely to the selected RDSON of the I/O pad output. specifications that are relative to SWD_CLK. Figure 74. SWD Input Clock Timing

Figure 75. SWD Output Data Timing

15 Ballmaps

For package ballmaps and signal descriptions, see the Reference Manual.

16 Packaging

The following table provides the document number for each package drawing. The following tables summarize changes to this document since the release of Rev. 1.

• Changed Max from 160 MHz to 162 MHz for: — fSYS_AE and fSYS_MC in AE Operating Conditions — fP5_AE_CLK in Clock frequency ranges
• In Static power specifications for I/O Domains — For both 1.8V and 3.3V Conditions: divided VDD_IO_ETH specifications into separate VDD_IO_ETH_0 and VDD_IO_ETH_1 specifications — For 3.3V Condition: divided VDD_HV_IO_D specifications into separate VDD_HV_IO_D0 and VDD_HV_IO_D1 specifications, and changed Max from 0.3 mA to 0.5 mA Table continues on the next page... NXP Semiconductors S32E27 S32E2 Data Sheet S32E27 All information provided in this document is subject to legal disclaimers. © 2020 - 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 5 — 3 December 2024

Rev. 5, 3 December 2024 — Added VDD_HV_IO_D0 and VDD_HV_IO_D1 specifications for 5.0V Condition

• In Power-up, added step "Ramp up all 1.1V supplies."
• In Aurora PLL, for PER_jitter, in Condition text changed "fPLL_CLKIN = 100MHz" to "fPLL_CLKIN = 40MHz | 100MHz"
• Removed section heading for GTM under "Timer Modules"
• In uSDHC SD3.0/eMMC5.1 DDR — For first fpp specification ◦ In Description, changed "eMMC5.1" to "eMMC high speed" ◦ In Condition, added "3.3V/1.8V" — For second fpp specification ◦ In Description, changed "SD3.0 DDR" to "SD/SDIO DDR50" ◦ In Condition, added "1.8V"
• In uSDHC DDR-HS400 — For fPP: in Condition, added "1.8V" — Moved footnote about SD6 and SD7 from tRQ and tRQH specifications for skew (data) to tRQ and tRQH specifications for skew (CMD)
• In uSDHC SD3.0/SDIO3.0/eMMC5.1 SDR — For fpp specification with Max value 25/50 MHz and former Description "SD/SDIO full speed/ high speed," divided into two fpp specifications with: ◦ Description "SD/SDIO default speed /high speed" and Condition 3.3V ◦ Description "SD/SDIO SDR12/ SDR25" and Condition 1.8V In shared footnote, changed "normal (full) speed" to "default speed" — For fpp specification with former Max value 20/52 MHz ◦ In Description, changed "eMMC full speed/ high speed" to "eMMC legacy SDR /high speed DDR" ◦ Changed Max to 26/52 MHz ◦ In Condition, added "1.8V/3.3V" ◦ In second footnote, changed "normal (full) speed" to "Legacy speed" and changed "0–20MHz" to "0–26MHz" — For fOD specification with Min value 100 kHz and Max value 400 kHz ◦ In Description, changed "identification mode" to "SD/SDIO identification mode" and added footnote about SD/ SDIO identification mode ◦ In Condition, added "3.3V" — For specification with no Min value and Max value 400 kHz ◦ Changed symbol from fpp to fOD ◦ In Description, changed "low speed" to "eMMC identification mode" and removed footnote about low speed mode Table continues on the next page... NXP Semiconductors S32E27 S32E2 Data Sheet S32E27 All information provided in this document is subject to legal disclaimers. © 2020 - 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 5 — 3 December 2024

Rev. 5, 3 December 2024 ◦ In Condition, added "1.8V/3.3V"

• In uSDHC SDR-HS200, for tCLK, added Condition "1.8V"
• In AE SAR ADC — Added second THD specification with Max value -63 dBFS — Added second SINAD specification with Min value 62.5 dBFS Rev. 4, 22 October 2024
• In Device Power and Operating Current Specifications, replaced IVREFH_ADC with IDD_VREF_DYN and IDD_VREF_LKG
• In I3C timing when communicating with Legacy I2C devices and LPI2C — For tfCL and tfDA for FM+, changed Min from 20 * (VDD/5.5V) ns to — — For tfCL and tfDA for FM+, added footnote
• In NETC management interface, for tMDKHDX specifications with Condition NEG=0, at end of Max value, changed +3 to Rev. 4 Draft A, 5 October 2024
• In Ordering information, in description of 7th character for Flash memory size, added text: "All S32Z2 devices have 0 MB."
• In Absolute Max Ratings — For VAD_INPUT, revised footnote 6 — For V_OS_US_1p6, added footnotes 1 and 4
• In Operating Conditions, for IINJ_LVDS, removed Condition text "LVDS enabled"
• In Device Power and Operating Current Specifications, for IDD_HV_LFASTPLL, added Condition text "per PLL"
• Added Static power specifications for I/O Domains
• In LVDS Pads — For RTERM_LVDS, added Condition text "transmitter and receiver" — For TEYE_LVDS, added Condition text "transmitter"
• In Aurora PLL, for fPLL_CLKIN — Changed Min from — to 40 MHz — Changed Typ from 100 MHz to — — Changed Max from — to 100 MHz
• In PLL, in introductory text, changed "applies to instances" to "applies to all instances"
• In FXOSC, added ΔfXTAL_CLK
• In I3C timing when communicating with Legacy I2C devices and LPI2C Table continues on the next page... NXP Semiconductors S32E27 S32E2 Data Sheet S32E27 All information provided in this document is subject to legal disclaimers. © 2020 - 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 5 — 3 December 2024

Rev. 4 Draft A, 5 October 2024 — For trCL and trDA for FM, changed Min from 20 ns to — — For tfCL and tfDA for FM, changed Min from 20 * (VDD/5.5V) ns to — — For trCL, tfCL, trDA, and tfDA for FM, added footnote

• In Microsecond channel (MSC) — For t2 and t3 in table: ◦ In Description, changed "SOUT" to "SOUT/SCK" ◦ In Condition, removed references to frequency values ◦ Added footnote — Modified figure "MSC master timing, output only"
• In following sections, in "Output timing valid" footnote, changed "input load" to "flash input load" — FlexRay - TxEN — FlexRay - TxD — NETC MII — NETC RMII — NETC RGMII — PSI5 — All sections of QuadSPI and uSDHC timing specifications — JTAG Boundary Scan — JTAG Debug Interface Timing
• In IEEE1588 interface, changed "NETC" to "IEEE" in section and table headings
• In NETC management interface, for tMDKHDX specifications with Condition NEG=1, removed content of Spec Number column
• In SENT Interface, in "Input hysteresis" footnote, changed "set to 1/10th of clock tick to avoid failures" to "set to a value closest to 1/10th of a bit time where the max value of 128 is sufficient for long bit times"
• Removed section heading for PSI5_S under "Communication Modules"
• In following sections, for fSCK, added footnote "fSCK of 133.33MHz is also acceptable" — QuadSPI Quad 1.8V SDR 133MHz — QuadSPI Quad 3.3V SDR 133MHz
• In QuadSPI Octal 1.8V DDR 200MHz — For tOD_DATA, removed Condition text — Removed separate tOD_DATA specification for single SRE configuration
• In QuadSPI Quad 3.3V SDR 50MHz, removed "and Octal" from section and table headings
• In uSDHC SD3.0/eMMC5.1 DDR — For tTLH and tTHL, added Spec Number Table continues on the next page... NXP Semiconductors S32E27 S32E2 Data Sheet S32E27 All information provided in this document is subject to legal disclaimers. © 2020 - 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 5 — 3 December 2024

Rev. 4 Draft A, 5 October 2024 — For tOD, tISU, and tIH, expanded Spec Number information — In footnote 3, changed "Input timing" to "Input signal timing"

• In uSDHC DDR-HS400 — Changed introductory text from "In Split SRE configuration SRE[2:0]=000 for Data/CMD and SRE[2:0]=111 for CLK are the required drive settings" to "The SRE[2:0]=000 is required drive setting" — In table: ◦ For tTLH and tTHL, added Spec Number ◦ Added tRQ and tRQH specifications for skew (CMD) ◦ In footnote 5, changed "Input timing" to "Input signal timing" — Modified figure "HS400 Mode Interface Timing"
• In uSDHC SD3.0/SDIO3.0/eMMC5.1 SDR, in footnote 6, changed "Input timing" to "Input signal timing"
• In uSDHC SDR-HS200 — In table: ◦ For tTLH and tTHL, added Spec Number ◦ In footnote 3, changed "Input timing" to "Input signal timing" — Modified figure "HS200 Mode Interface Timing"
• In Flash KGD — For Flash Reads, moved value of 1M array reads from Max to Min — For DR_100 ◦ In Description, changed "after 100" to "between 0 and 100" ◦ Moved value of 20 years from Typ to Min — For DR_1000 ◦ In Description, changed "after 1000" to "between 100 and 1000" ◦ Moved value of 5 years from Typ to Min — For E ◦ Moved value of 100 cycles from Typ to Min ◦ Moved value of 1000 cycles from Max to Typ
• In SAR ADC, for IAD_LKG, changed TJ value in Condition text from 125C to 150C
• In AE JTAG boundary scan, revised "Output timing valid" footnote
• In SWD electrical specifications, revised first paragraph after table Rev. 3, 04/2024
• In Absolute Max Ratings Table continues on the next page... NXP Semiconductors S32E27 S32E2 Data Sheet S32E27 All information provided in this document is subject to legal disclaimers. © 2020 - 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 5 — 3 December 2024

Rev. 3, 04/2024 — For VAD_INPUT, expanded footnote 7 — Added specification: VIN_LVDS — For IINJ_LVDS, revised and expanded footnote 14

• In Operating Conditions — Added specifications: VIN_LVDS and IINJ_LVDS — For ΔVDD_HV_18_IO, added footnotes 15 and 16 — For ΔVDD_HV_18_ANA, added footnote 15
• In AE Operating Conditions, for VIN, changed Max from 3.465V to VDD_HV_IO_D*
• In Device Power and Operating Current Specifications, for IVREFH_ADC — Changed Typ from 100 uA to 50 uA — Changed Max from — uA to 115 uA — In Condition text, added "Typ at 25C and Max at 150C" and "1Msps conversion rate"
• In GPIO Pads — In footnote 6, changed "1.5pF/inch" to "3.3pF/inch" — In footnote 7, added: "Actual application rise fall times extracted from simulation must meet TR_TF specification."
• In LVDS Pads — Removed TSTARTUP_LVDS_REF — For VCM_LVDS_TX that applies to SPI/MSC, changed Min from 1.03 V to 1.05 V — For TSTARTUP_LVDS_TX ◦ In Description, changed "Sleep to normal mode" to "transmitter ready after enabling" ◦ Changed Max from 500 ns to 1.5 us ◦ In Condition, added "Includes reference startup time" — For VCM_LVDS_RX ◦ Added footnote ◦ Changed Min from 0.2 V to 0.225 V ◦ Changed Max from (VDD_HV_IO_LFAST - 0.2) V to (VDD_HV_IO_LFAST - 0.225) V — For VDIFF_LVDS_RX, added footnote: "The LVDS input pin maximum voltage given in the operating conditions section of the datasheet must be obeyed when setting the common-mode and differential swing voltages seen by the LVDS receiver." — For TSTARTUP_LVDS_RX ◦ In Description, changed "Power down to Normal mode" to "receiver ready after enabling" ◦ In Condition, changed "bandgap" to "reference startup" — Added figure "VDIFF_LVDS_TX pk-pk in single ended and differential mode"
• In LPI2C, added specifications: tSU_STA, tHD_STA, tLOW, tDIG_L, tHIGH, tDIG_H, tSU_DAT, tHD_DAT, trCL, tfCL, trDA, tfDA, tSU_STO, and tBUF Table continues on the next page... NXP Semiconductors S32E27 S32E2 Data Sheet S32E27 All information provided in this document is subject to legal disclaimers. © 2020 - 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 5 — 3 December 2024

Rev. 3, 04/2024

• In SPI, revised footnote 9
• In Microsecond channel (MSC), revised Descriptions — For t1, changed "Duty cycle deviation" to "SCK duty cycle deviation" — For t2, changed "Rise time" to "SOUT rise time" — For t3, changed "Fall time" to "SOUT fall time"
• In FlexRay - TxEN and FlexRay - TxD, revised footnote 1
• In NETC MII and NETC RMII, revised footnote 2
• In NETC RGMII, revised footnote 3
• In NETC management interface, modified tMDKHDX specifications
• Added CANXL
• In PSI5, revised footnote 2
• Revised "Output timing valid" footnote in — QuadSPI Quad 1.8V DDR 80MHz (footnote 2) — QuadSPI Quad 1.8V SDR 133MHz (footnote 1) — QuadSPI Octal 1.8V SDR 133MHz (footnote 2) — QuadSPI Octal 1.8V DDR 166MHz (footnote 1) — QuadSPI Octal 1.8V DDR 200MHz (footnote 1) — QuadSPI Quad 3.3V DDR 80MHz (footnote 2) — QuadSPI Quad 3.3V SDR 133MHz (footnote 1) — QuadSPI Octal and HyperRAM 3.3V DDR 100MHz (footnote 1)
• In QuadSPI configurations, removed table columns with DQS mode defined as "Internal pad loopback (data + DQS)" and "Edge-aligned" for: — QuadSPI_0 side A: 1.8V Octal, DDR 200 MHz — QuadSPI_1 side A: 1.8V HyperFlash or HyperRAM, DDR 166 MHz
• In uSDHC SD3.0/eMMC5.1 DDR, revised footnote 1
• In uSDHC DDR-HS400 — Revised footnote 1 — For tCL and tCH, changed Min from 2.35 ns to 2.2 ns — For tOD, changed Max from 0.9 ns to 0.6 ns
• In uSDHC SD3.0/SDIO3.0/eMMC5.1 SDR, revised footnote 2
• In uSDHC SDR-HS200, revised footnote 1
• In JTAG Boundary Scan, revised footnote 6
• In AE JTAG boundary scan, revised footnote 7
• In JTAG Debug Interface Timing, revised footnote 4
• In SWD electrical specifications, revised first paragraph after table NXP Semiconductors S32E27 S32E2 Data Sheet S32E27 All information provided in this document is subject to legal disclaimers. © 2020 - 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 5 — 3 December 2024

Rev. 3 Drafts A and B, 10/2023

• Changed I3C protocol to I2C protocol, changed number of I3C instances from 3 to 1, and added LPI2C instances in: — Block diagram — Table 1 in Feature summary
• In Ordering information, changed production part number and redefined 11th and 12th characters
• In Device Power and Operating Current Specifications, changed Typ for IVREFH_ADC from 0.65 mA to 100 uA
• In Total power specifications, changed Symbol for both total dynamic power specifications from PVDD_DOMAIN1 to PDYN_DOMAIN1
• In GPIO Pads, removed IOH_33 specification with Condition of SRE[2:0]=000
• In LVDS Pads — Added IDD_HV_LVDS_REF — For VCM_LVDS_TX with Condition for SPI/MSC, changed Min from 1.075 V to 1.03 V and Max from 1.325 V to 1.37 V — For TSTARTUP_LVDS_TX, changed Description text from "assertion of ipp_obe to common mode settling time" to "Sleep to normal mode" — For TEYE_LVDS, added to Condition text: "includes PLL jitter" — For TSTARTUP_LVDS_RX, added Description text "Power down to normal mode" and added Condition text "Includes bandgap time" — Added CIN — Added "LFAST timing definition" figure
• In LFAST PLL, added new footnote for tLOCK
• Added introductory text in I3C
• In I3C timing when communicating with Legacy I2C devices — Added Min and Max values for both tHD_DAT specifications — Removed "I3C START timing" figure — Added "Definition of timing for F/S mode devices on the I2C bus" figure
• Added LPI2C
• In SPI, moved SRE[2:0] = 101 from Condition for all tSUO and tHO specifications to initial paragraph
• In Microsecond channel (MSC), added t1, t2, and t3 specifications
• In LIN — For RATE with Condition of UART mode, changed Max from 2 Mbps to 33 Mbps — Moved SRE[2:0] = 110 from Condition for RATE specifications to initial paragraph
• In NETC MII, moved SRE[2:0] = 100 from Condition for final three specifications to initial paragraph
• In NETC RMII, moved SRE[2:0] = 100 from Condition for final two specifications to initial paragraph
• In NETC RGMII, moved SRE[2:0] = 100 from Condition for all specifications to initial paragraph
• In NETC management interface Table continues on the next page... NXP Semiconductors S32E27 S32E2 Data Sheet S32E27 All information provided in this document is subject to legal disclaimers. © 2020 - 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 5 — 3 December 2024

Rev. 3 Drafts A and B, 10/2023 — For existing tMDKHDX, removed footnote, redefined Min and Max, and added Condition text NEG=1 — Added two more tMDKHDX specifications

• In QuadSPI interfaces, added hyperlinks to applicable sections of specifications
• In QuadSPI Octal 1.8V SDR 133MHz, removed tISU_SCK and tIH_SCK
• In QuadSPI Octal 1.8V DDR 166MHz, QuadSPI Octal 1.8V DDR 200MHz, and QuadSPI Octal and HyperRAM 3.3V DDR 100MHz, removed tDVW
• Added QuadSPI configurations Rev. 2, 06/2023
• In AE Operating Conditions, for VDD_HV_REG — Changed Min from 1.62 V to 1.68 V — Changed Max from 1.98 V to 1.92 V
• In Device Power and Operating Current Specifications — Removed PVDD_SOC_BASE_TYP — Added PLKG_SOC_TYP and PDYN_SOC_BASE_TYP — For PDYN_R52_TYP at 800 MHz, changed Typ from 1.95 W to 0.8 W — Added PDYN_R52_TYP at 900 MHz and 1 GHz — For PDYN_DDR_TYP, changed Typ from TBD to 0.1 W and, in Condition, changed VDD_DDR from 0.77 V to

0.825 V and 32-bit to 16-bit

— For PDYN_LLCE_TYP, changed Typ from TBD to 0.2 W and, in Condition, changed 200 MHz to 400 MHz — In Condition for IVDD_IO_ETH_0 and IVDD_IO_ETH_1 at both 3.3 V and 1.8 V, removed SRE=4 and VDD=3.3 V and added Tj=150C and RGMII 125 MHz — Removed pre-existing IVDD_IO_QSPI_0 and IVDD_IO_QSPI_1 specifications — Changed PVDD_IO_QSPI_0 and PVDD_IO_QSPI_1 to IVDD_IO_ETH_0 and IVDD_IO_ETH_1, respectively — For new IVDD_IO_QSPI_0, changed Max from TBD to 35 mA and, in Condition, changed max drive to Octal mode, DDR — For new IVDD_IO_QSPI_1 at 1.8 V, changed Max from TBD to 80 mA and, in Condition, changed max drive to Octal mode, DDR — For new IVDD_IO_QSPI_1 for QuadSPI_1 A at 3.3 V, changed Max from TBD to 130 mA and, in Condition, changed 133 MHz / max drive to 100 MHz Octal mode, DDR — For new IVDD_IO_QSPI_1 for QuadSPI_1 B at 3.3 V, changed Max from TBD to 75 mA and, in Condition, changed max drive to Quad mode, SDR — Changed footnote 1 Table continues on the next page... NXP Semiconductors S32E27 S32E2 Data Sheet S32E27 All information provided in this document is subject to legal disclaimers. © 2020 - 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 5 — 3 December 2024

Rev. 2, 06/2023 ◦ from: "SoC logic power consumption includes total SoC leakage power plus the dynamic power for basic configuration blocks like clocking and other infrastructure blocks. Please contact NXP Semiconductor for leakage power and temperature values for the device." ◦ to: "Base dynamic power includes SMU, HSE, DMA, peripherals, and clocks. It excludes RTU and FlexLLCE clocks and domains." — In footnote 2, changed "four Cortex-R52 cores" to "eight Cortex-R52 cores" and added: "RTU0 and RTU1 each account for half the spec value." — Added new footnote 3: "Power includes MC_CGM_6 clocking current at 400MHz plus DDR access current and excludes IO_DDR." — In footnote 4, changed "based on simulation of the expected average logic activity within the FlexLLCE" to "includes FlexLLCE subsystem clocks and peripherals plus all cores running Dhrystone."

• In Total power specifications, reversed the positions of footnotes 1 and 3
• In AE Device Power and Operating Current Specifications, for PVDD12, changed Max from 100 mW to 200 mW
• In Power-down, added table
• In LVDS Pads — In introductory paragraph, added "MSC, SPI and Zipwire" — For pre-existing VCM_LVDS_TX, added Condition: "Applies to Aurora, CLKOUT LVDS TX and Zipwire" — Added second VCM_LVDS_TX with Condition: "Applies to SPI/MSC" — For VDIFF_LVDS_RX, changed Max from 400 mW to 450 mW — Removed footnote: "When measuring leakage with Rx enabled, when we drive both pad_p and pad_n high, an internal pull down resistor is enabled to ground and will show upto 100uA leakage on each pin"
• In PLL changed "System PLL" to "PLL" for tLOCK, PER_jitter, LT_jitter, and footnote 3
• In FXOSC, for TCST, added to Condition: "time to stable duty cycle when EOCV is set to 1 ms period"
• In NETC MII, for ΔtCYC_TX — Changed Min from 45% to 35% — Changed Max from 55% to 65%
• In NETC management interface — For tMDKHDX, in Spec Number, added MDC10, MDC11 — For MDIO_ISU, in Spec Number, added MDC12 — In footnote 1, added: "If NEG=1, then MDIO is driven with the negedge of MDC, and the other fields don't affect the timing. If NEG=0 and EHOLD=0, then the delay from MDC to MDIO is 2*MDIO_HOLD+1 NETC cycles. If NEG=1 and EHOLD=1, then the delay from MDC to MDIO is 8*MDIO_HOLD+1 NETC cycles."
• In all sections of QuadSPI specifications, in introductory text, changed paragraph beginning "Clock measurements..." to: "Data transitions measured at 30%/70% supply for the write path. Data transitions measured at mid-supply for the read path. Clock transitions measured at mid-supply."
• In QuadSPI Octal 1.8V DDR 166MHz — For tIH_DQS, changed Min from 2.145 ns to 2.105 ns Table continues on the next page... NXP Semiconductors S32E27 S32E2 Data Sheet S32E27 All information provided in this document is subject to legal disclaimers. © 2020 - 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 5 — 3 December 2024

Rev. 2, 06/2023 — For tISU_DQS, changed Min from -0.496 ns to -0.616 ns

• In QuadSPI Octal 1.8V DDR 200MHz — For pre-existing tOD_DATA, added to Condition: "Split SRE configuration, SRE[2:0]=000 for Data and SRE[2:0]=110 for CLK" — Added second tOD_DATA — For tIH_DQS, changed Min from 1.684 ns to 1.644 ns — For tISU_DQS, changed Min from -0.466 ns to -0.586 ns
• Added QuadSPI timing diagrams
• In all sections of uSDHC specifications, in introductory text, changed paragraph beginning "All uSDHC parameters..." to: "Data transitions measured at 35%/65% supply for the write path. Data transitions measured at mid-supply for the read path. Clock transitions measured at mid-supply."
• In uSDHC DDR-HS400 — In introductory text, changed paragraph beginning "The SRE[2:0]..." to: "In Split SRE configuration SRE[2:0]=000 for Data/CMD and SRE[2:0]=111 for CLK are the required drive settings to meet the timing." — For tCL and tCH, changed Min from 2.2 ns to 2.35 ns — For tOD1 and tOD2, changed Min from 0.45 ns to 0.65 ns — Added tOD — Removed footnote: "The CMD output timing for HS400 mode is the same as CMD output timing for HS200 mode." Rev. 2 Draft C, 02/2023
• In Ordering information, for 12th character, changed "0 = Initial version" to "A = Initial production version"
• In Total power specifications — Changed introductory text to: "The part is designed with a power distribution network that has two specifications: dynamic power and total supply rail power (dynamic power plus leakage power). At higher temperatures, the leakage is higher and the user must manage the dynamic power to compensate. The user must ensure the total supply rail power is below the total power distribution network capacity. At lower temperatures, the leakage is reduced and the part can utilize the full dynamic power capacity. Exceeding either power specifications will result in IR drop issues and unpredictable operation of the device." — Replaced two footnotes in table with three new footnotes — For specification with Max value 5.2, removed from Condition text: "temperature range classification M" — For specification with Max value 4.8 (formerly 3.9), removed from Condition text: "temperature range classification — Added specification with Max value 2.0 — For specification with Max value 2.8: in Condition text, changed "temperature independent" to "Tj=125C"
• In GPIO Pads — For TR_TF_33 with Condition text SRE[2:0] = 100, changed Min from 1.75 to 1.9 Table continues on the next page... NXP Semiconductors S32E27 S32E2 Data Sheet S32E27 All information provided in this document is subject to legal disclaimers. © 2020 - 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 5 — 3 December 2024

Rev. 2 Draft C, 02/2023 — For TR_TF_33 with Condition text SRE[2:0] = 101, changed Min from 0.05 to 1.00 and Max from 8.25 to 8.50 — For TR_TF_33 with Condition text SRE[2:0] = 110, changed Min from 0.01 to 0.50 and Max from 7.0 to 7.30 — For TR_TF_33 with Condition text SRE[2:0] = 111, changed Min from 0.005 to 0.40 and Max from 5.5 to 6.0

• Added I3C timing when communicating with Legacy I2C devices and Flash KGD
• In SENT Interface, added new final sentence to footnote 4: "SRX programmable filter should be set to 1/10th of clock tick to avoid failures."
• In QuadSPI Quad 3.3V SDR 50MHz, added tISU_SCK and tIH_SCK specifications
• In Temperature Monitoring Unit (TMU) for TRANGE — Changed Min from -40°C to -45°C — Changed Max from 150°C to 155°C — Added footnote: "Accuracy outside of operating range (-40 to 150) is not guaranteed."
• In second paragraph of SAR ADC, changed "the external capacitance at the input pin should be maximized" to "the external capacitance at the input pin and reference pin should be maximized" Rev. 2 Draft B, 12/2022
• In Overview, changed "microcontrollers (MCUs)" to "real-time processors"
• In Absolute Max Ratings — For VIN, added footnote about DC case limit — For existing V_OS_US_* specifications, added "3.3V" to Condition text — Added new V_OS_US_10 specification for 1.8V
• In Operating Conditions — For fSYS_R52, changed Max from 800 MHz to 1 GHz and added Condition text and related footnote — For both VDD_IO_ETH_n specifications, added Condition text — For VIN_33 and VIN_18, added footnote about DC case limit — For ΔVDD_HV_18_ANA, added footnote about VREFH_ADCn — Added "ADC supply sequencing" diagram
• In Device Power and Operating Current Specifications, added PVDD_IO_QSPI_0 and PVDD_IO_QSPI_1 specifications
• Moved content of "Power Sequencing" section into Power-up subsection, added table in Power-up subsection, and added Power-down subsection
• In Reset related pad electrical characteristics, after "RESET_B pad detailed behavior" diagram, added text: "The RESET_B pad behavior described in the diagram and the related VRSE_RESET_B parameter spec also apply to the case of core VDD droop after power-up."
• In Reset Duration, added diagrams: — Reset_b pad detailed behavior during core supply brownout Table continues on the next page... NXP Semiconductors S32E27 S32E2 Data Sheet S32E27 All information provided in this document is subject to legal disclaimers. © 2020 - 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 5 — 3 December 2024

Rev. 2 Draft B, 12/2022 — Reset_b pad detailed behavior during pad HV supply brownout — Reset_b pad detailed behavior during power down

• In Clock frequency ranges — For fP0_PSI5_189K_CLK. changed Max from 6.048 MHz to 6.0606 MHz — For fRTU0_CORE_CLK and fRTU1_CORE_CLK, changed Max from 900 MHz to 1 GHz, expanded Condition text, and added related footnote — For fRTU0_CORE_DIV2_CLK and fRTU1_CORE_DIV2_CLK, changed Max from 450 MHz to 500 MHz, expanded Condition text, and added related footnote
• In PLL — For fPLL_CORE_PHI0, changed Max from 900 MHz to 1000 MHz, expanded Condition text, and added footnote — For fPLL_DDR_PHI0 ◦ Removed single specification with Min of 800 MHz and Max of 1620 MHz ◦ Added four specifications with varying Condition text and footnotes, each with a single value for both Min and Max: 266 MHz, 333 MHz, 400 MHz, and 405 MHz
• In DFS — For fDFS_CORE_CLK0, changed Max from 900 MHz to 1000 MHz, expanded Condition text, and added footnote — For fDFS_PER_CLK5, changed Max from 333 MHz to 330 MHz
• In Microsecond channel (MSC) — Removed Note and tCSC and tASC specifications — Added tCSV and tCSH specifications as well as diagram — For tSUO, changed 6 ns value from Min to Max
• Removed "I3C Push-Pull Timing Parameters for SDR Mode" section
• Added CAN
• In IEEE1588 interface, removed tT1588OV specification
• For QuadSPI, removed tISU_SCK and tIH_SCK specifications from — QuadSPI Quad 1.8V DDR 80MHz — QuadSPI Quad 1.8V SDR 133MHz — QuadSPI Octal 1.8V SDR 133MHz — QuadSPI Quad 3.3V SDR 133MHz
• In uSDHC SD3.0/eMMC5.1 DDR, renamed section (was "uSDHC DDR-52MHz") and figure, and added text preceding table: "All uSDHC parameters are measured at mid-supply (VDD_IO_SDHC/2)."
• In uSDHC DDR-HS400, removed "HS400 mode uSDHC output timing" and "HS400 mode uSDHC input timing" diagrams, and added text preceding table: "All uSDHC parameters are measured at mid-supply (VDD_IO_SDHC/2)."
• In uSDHC SD3.0/SDIO3.0/eMMC5.1 SDR, renamed section (was "uSDHC SDR-52MHz") and figure, and added text preceding table: "All uSDHC parameters are measured at mid-supply (VDD_IO_SDHC/2)."
• In uSDHC SDR-HS200, added text preceding table: "All uSDHC parameters are measured at mid-supply (VDD_IO_SDHC/2)." NXP Semiconductors S32E27 S32E2 Data Sheet S32E27 All information provided in this document is subject to legal disclaimers. © 2020 - 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 5 — 3 December 2024

Rev. 2 Draft A, 06/2022

• Throughout: Changed S32E27 to S32E2, changed S32Z27 to S32Z2, and removed references to S32S27
• In "Block diagram" section figure, in "Math/ML acceleration" block: Removed "CEVA_SPF2" and changed "Vector DSP" to "FP Vector DSP"
• In "Feature summary" section text: For GTM list item, changed "on S32E27 and optional for S32Z27" to "optional for both S32E2 and S32Z2"
• Modified table in "Feature summary" section
• Modified figure in "Ordering information" section
• In "Absolute Max Ratings" section: — For VAD_INPUT: Changed VREFL_ADC to VSS_ADC and VREFH_ADC to VDD_ANA — Added IINJ_LVDS — For final four parameters, added symbol names: V_OS_US_10, V_OS_US_7p5, V_OS_US_2p5, and V_OS_US_1p6 — In footnote 8: Added "For powered devices when VIN ≥ VDD_IO*, VIN must simultaneously follow the constraint that VIN-VDD_IO* ≤ 0.3V." — In footnote 9: Added "Unpowered devices must simultaneously follow IINJ_D unpowered current injection constraints." — Added new footnotes 12 and 15
• In "Operating Conditions" section: — For VAD_INPUT: Changed VREFL_ADC to VSS_ADC and VREFH_ADC to VDD_ANA — For existing IINJ_D parameter: Added condition "Unpowered" — Added IINJ_D parameter with condition "Powered" — In footnote 2: Changed "the modulation depth (max 1.5%)" to "half the modulation depth" — In footnote 8: Added "See device hardware design guidelines document for more details." — Changed footnote 9 from "Additional +0.3V are supported for DC signal" to "For AC signals, allowed max VIN ≤ VDD_IO* for lifetime operation. If AC overshoot beyond VDD_IO* occurs, then refer to the Abs Max duration constraints as a function of the amount of overshoot. For DC signals ≥ VDD_IO, VIN-VDD_IO* ≤ 0.3V is allowed for lifetime operation." — Changed footnote 10 from "Absolute minimum level for VIN signal is -0.3V" to "The min DC VIN level for a powered device is -0.3V. If AC undershoot below -0.3V occurs, then refer to the Abs Max duration constraints as a function of the amount of undershoot." — Added new footnote 15
• In "Thermal Design, Characteristics, and Ratings" section: Expanded text and, in table, revised descriptions and footnotes
• In "Device Power and Operating Current Specifications" section: Added footnotes and, for IVREFH_ADC, changed unit from uA to mA
• In "GPIO Pads" section: — Added VOL and VOH and new footnote 1 Table continues on the next page... NXP Semiconductors S32E27 S32E2 Data Sheet S32E27 All information provided in this document is subject to legal disclaimers. © 2020 - 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 5 — 3 December 2024

Rev. 2 Draft A, 06/2022 — Removed Note: "VOH/VOL values should be calculated based on the provided RDSON, IOH/IOL values and IBIS models." — In "1.8V/3.3V GPIO pad detailed behavior during power up" figure: Changed "weak pull-down" to "weak pull-down as per ILKG_3318 specification" — Removed text: "The weak pull-down is 100 Kohm and is separate from the usual selectable 12Kohm internal pull resistor. If the pad is in 3.3V mode and the IOMUX sheet defines the 'Pad State During POR reset sequence' as 'Hi-Z', the 100Kohm pull-down remains engaged until RESET_B is released."

• In "Clock frequency ranges" section, added text after table: "The stated maximum operating frequency must be observed when using the PLL with frequency modulation enabled. Center-spread modulation is supported in cases where the nominal operating frequency plus half the modulation depth is less than the stated maximum frequency."
• In "PLL" section: — Moved text from after table to before table: "Spread spectrum clock modulation is only available on the Core PLL and DDR reference PLLs." — In table: Changed Min to 40 MHz for fPLL_CORE_PHI0, fPLL_PER_PHI0, fPLL_PER_PHI1, fPLL_PER_PHI2, fPLL_PER_PHI3, fPLL_PER_PHI4, fPLL_PER_PHI5, and fPLL_PER_PHI6
• In "DFS" section: — In table: Changed Min to 40 MHz for fDFS_CORE_CLK0, fDFS_CORE_CLK1, fDFS_CORE_CLK2, fDFS_CORE_CLK3, fDFS_CORE_CLK4, fDFS_CORE_CLK5, fDFS_PER_CLK0, fDFS_PER_CLK1, fDFS_PER_CLK2, fDFS_PER_CLK3, fDFS_PER_CLK4, and fDFS_PER_CLK5 — Added PER_Jitter with condition fDFS_CLKIN = 2400 MHz, Odd MFN
• In "SIRC" section: — For PTA: Changed description from "Post Trim Accuracy" to "Trimming Resolution" — For ðfVAR: Changed condition from "Trimmed" to "Frequency variation across voltage and temperature range after trimming"
• In "uSDHC DDR-HS400" section: — For "Clock frequency" parameter: Changed symbol from tPP to fPP — Changed tOD parameter to tOD1 and modified characteristics — Removed tISU and tIH parameters and added tOD2, tRQ, and tRQH parameters
• In "SAR ADC" section: For VAD_INPUT, changed VREFL_ADC to VSS_ADC and VREFH_ADC to VDD_ANA
• Added "Microsecond channel (MSC)" section
• Added "QuadSPI Octal 3.3V SDR 50MHz" section
• In "DDR" section: Added "This chip supports the following memory types..." NXP Semiconductors S32E27 S32E2 Data Sheet S32E27 All information provided in this document is subject to legal disclaimers. © 2020 - 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 5 — 3 December 2024

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NXP — wordmark and logo are trademarks of NXP B.V. AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, μVision, Versatile — are trademarks and/or registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere. The related technology may be protected by any or all of patents, copyrights, designs and trade secrets. All rights reserved. SafeAssure — is a trademark of NXP B.V. SafeAssure — logo is a trademark of NXP B.V. NXP Semiconductors S32E27 S32E2 Data Sheet S32E27 All information provided in this document is subject to legal disclaimers. © 2020 - 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 5 — 3 December 2024

S32E27 All information provided in this document is subject to legal disclaimers. © 2020 - 2024 NXP B.V. All rights reserved. Product Data Sheet Rev. 5 — 3 December 2024

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2020 - 2024 NXP B.V. All rights reserved. For more information, please visit: https://www.nxp.com Date of release: 3 December 2024 Document identifier: S32E27