S29AL008D

S29AL008D_06 SPANSION | Alldatasheet

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Publication Number s29al008d_00 Revision A Amendment 4 Issue Date February 16, 2006 S29AL008D

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory Data Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient pr oduction volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.

ii S29AL008D s29al008d_00_A4 February 16, 2006 Notice On Data Sheet Designations Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specif ications throughout the product life cycle, in - cluding development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their de - sign. The following descriptions of Spansion data sheet designations are presented here to high- light their presence and definitions. Advance Information The Advance Information designation indicates that Spansion LLC is developing one or more spe- cific products, but has not committed any design to production. Information presented in a doc - ument with this designation is likely to change , and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance Informa- tion content: “This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without con- tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the prod- uct life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achi eved. Changes to the technical specifications presented in a Preliminary docume nt should be expected while keeping these as - pects of production under consid eration. Spansion places the fo llowing conditions upon Prelimi- nary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifica- tions due to changes in technical specifications.” Combination Some data sheets will contain a combination of products with different designations (Advance In- formation, Preliminary, or Full Production). This type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with DC Charac teristics table and AC Erase an d Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designatio n is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incor- rect specification. Spansion LLC applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that sub- sequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.

This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur. Publication Number S29AL008D_00 Revision A Amendment 4 Issue Date February 16, 2006 This document has not been approved. Sharing this document with non-Spansion employees violates QS9000/TS16949 requirements. S29AL008D CMOS 3.0 Volt-only Boot Sector Flash Memory Data Sheet Distinctive Characteristics Architectural Advantage „ Single power supply operation — 2.7 to 3.6 volt read and write operations for battery- powered applications „ Manufactured on 200 nm process technology — Compatible with 0.32 µm and 230 nm Am29LV800 devices „ Flexible sector architecture — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen

64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and fifteen

32 Kword sectors (word mode)

— Supports full chip erase — Sector Protection features: — A hardware method of locking a sector to prevent any program or erase operations within that sector — Sectors can be locked in -system or via programming equipment — Temporary Sector Unprot ect feature allows code changes in previously locked sectors „ Unlock Bypass Program Command — Reduces overall programming time when issuing multiple program command sequences „ Top or bottom boot block configurations available „ Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies data at specified addresses „ Compatibility with JEDEC standards — Pinout and software compat ible with single-power supply Flash — Superior inadvertent write protection Performance Characteristics „ High performance — Access times as fast as 55 ns — Extended temperature ra nge (-40°C to +125°C) „ Ultra low power consumption (typical values at 5 MHz) — 200 nA Automatic Sleep mode current — 200 nA standby mode current — 7 mA read current — 15 mA program/erase current „ Cycling endurance: 1,000,000 cycles per sector typical „ Data retention: 20 years typical — Reliable operation for the life of the system Package option „ 48-ball FBGA „ 48-pin TSOP „ 44-pin SO Software Features „ Data# Polling and toggle bits — Provides a software method of detecting program or erase operation completion „ Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation Hardware Features „ Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion „ Hardware reset pin (RESET#) — Hardware method to reset th e device to reading array data

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The S29AL008D is an 8 Mbit, 3.0 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. For more information, refer to publication number 21536. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data ap pears on DQ7–DQ0. This device requires only a single, 3.0 volt V CC supply to perform read, program, and erase oper ations. A standard EPROM programmer can also be used to program and erase the device. This device is manufactured using Spansion’s 200nm process technology, and of- fers all the features and benefits of the Am29LV800B, which was manufactured using 0.32 µm process technology. The standard device offers access times of 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus conten tion the device contains separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the pro- gram and erase operations. The device is entirely command set compatible with the JEDEC single-power- supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an in- ternal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto matically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (tog- gle) status bits. After a program or erase cycle is completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and repro- grammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automat- ically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combina- tion of the sectors of memory. This can be achieved in-system or via programming equipment.

February 16, 2006 S29AL008D_00A4 S29AL008D 3 Data Sheet The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving feat ures. When addresses are stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. Spansion’s Flash technology combines years of Flash memory manufacturing ex- perience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simulta - neously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

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Figure 9. ICC1 Current vs. Time (Showing Active and

February 16, 2006 S29AL008D_00A4 S29AL008D 5 Data Sheet Product Selector Guide Note: See AC Characteristics, on page 37 for full specifications. Block Diagram Family Part Number S29AL008D Speed Options Full Voltage Range: VCC = 2.7 – 3.6 V 70 90 Regulated Voltage Range: VCC = 3.0 – 3.6V 55 Max access time, ns (tACC) 55 70 90 Max CE# access time, ns (tCE) 55 70 90 Max OE# access time, ns (tOE) 30 30 35 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# BYTE# CE# OE# STB STB DQ0–DQ15 (A-1) Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix Address LatchA0–A18

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WE# RESET# NC NC RY/BY# A17 A16 DQ2 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 Standard TSOP

February 16, 2006 S29AL008D_00A4 S29AL008D 7 Data Sheet Connection Diagrams Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages.Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6 DQ15/A-1 V SSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5NCNCRESET#WE# DQ11 DQ3DQ10DQ2NCA18NCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# V SSCE#A0A1A2A4A3 RY/BY# A18 A17 CE# VSS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 RESET# WE# A10 A11 A12 A13 A14 A15 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC SO FBGA Top View, Balls Facing Down

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A0–A18 = 19 addresses DQ0–DQ14 = 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BYTE# = Selects 8-bit or 16-bit mode CE# = Chip enable OE# = Output enable WE# = Write enable RESET# = Hardware reset pin, active low RY/BY# = Ready/Busy# output VCC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VSS = Device ground NC = Pin not connected internally Logic Symbol 16 or 8 DQ0–DQ15 (A-1) A0–A18 CE# OE# WE# RESET# BYTE# RY/BY#

February 16, 2006 S29AL008D_00A4 S29AL008D 9 Data Sheet

Ordering Information

Spansion standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Notes: 1. Type 0 is standard. Specify other options as required. 2. Type 1 is standard. Specify other options as required. 3. TSOP and SOP package markings omit packing type designator from ordering part number. 4. BGA package marking omits leading S29 and packing type designator from ordering part number. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S29AL008D 55 T A I RI 0 PACKING TYPE 0= T r a y 1= T u b e 2 = 7” Tape and Reel 3 = 13” Tape and Reel MODEL NUMBER 01 = x8/x16, V CC = 2.7 - 3.6V, top boot sector device R1 = x8/x16, V CC = 3.0 - 3.6V. top boot sector device 02 = x8/x16, V CC = 2.7 - 3.6V, bottom boot sector device R2 = x8/x16, V CC = 3.0 - 3.6V. bottom boot sector device TEMPERATURE RANGE I = Industrial (-40 °C to +85°C) N = Extended (-40°C to +125°C) PACKAGE MATERIAL SET A= S t a n d a r d F= P b - F r e e PACKAGE TYPE T = Thin Small Outline Package (TSOP) Standard Pinout B = Fine-pitch Ball-Grid Array Package M = Small Outline Package (SOP) Standard Pinout SPEED OPTION 55 = 55 ns Access Speed 70 = 70 ns Access Speed 90 = 90 ns Access Speed DEVICE NUMBER/DESCRIPTION S29AL008D

8 Megabit Flash Memory manufactured using 200 nm process technology

3.0 Volt-only Read, Program, and Erase

S29AL008D Valid Combinations Package Description Device Number Speed Option Package Type, Material, and Temperature Range Model Number Packing Type S29AL008D

55 TAI, TFI R1, R2

0, 3 (Note 1) TS048 ( Note 3)T S O P 70, 90 TAI, TFI, TAN, TFN 01, 02

55 BAI, BFI R1, R2

0, 2, 3 (Note 1) VBK048 ( Note 4)F i n e - P i t c h B G A 70, 90 BAI, BF, BAN, BFN 01, 02

55 MAI, MFI R1, R2

0, 1, 3 (Note 2) SO044 ( Note 3)S O P 70, 90 MAI, MFI, MAN, MFN 01, 02

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This section describes the requirements and use of th e device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is com - posed of latches that store the comman ds, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and con- trol levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A18:A0 in word mode (BYTE# = V IH), A18:A-1 in byte mode (BYTE# = VIL). 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the Sector Protection/Unprotection, on page 15. Word/Byte Configuration The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to V IL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes. Ta bl e 1 . S29AL008D Device Bus Operations Operation CE# OE# WE# RESET# Addresses (Note 1) DQ0– DQ7 DQ8–DQ15 BYTE# = VIH BYTE# = VIL Read L L H H AIN DOUT DOUT DQ8–DQ14 = High-Z, DQ15 = A-1Write L H L H AIN DIN DIN Standby VCC ±

0.3 V X X VCC ±

0.3 V X High-Z High-Z High-Z

Output Disable L H H H X High-Z High-Z High-Z Reset X X X L X High-Z High-Z High-Z Sector Protect (Note 2) L H L VID Sector Address, A6 = L, A1 = H, A0 = L DIN X X Sector Unprotect (Note 2) L H L VID Sector Address, A6 = H, A1 = H, A0 = L DIN X X Temporary Sector Unprotect X X X VID AIN DIN DIN High-Z

February 16, 2006 S29AL008D_00A4 S29AL008D 11 Data Sheet The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device a ddress inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See Reading Array Data, on page 18 for more information. Refer to the AC table for timing specifications and to Figure 13, on page 37 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to Word/Byte Configuration, on page 10 for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are re - quired to program a word or byte, instead of four. The Word/Byte Program Command Sequence, on page 19 contains details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2, on page 13 and Table 3, on page 14 indicate the address space that each sector occupies. A sector address consists of the address bits required to uniquely select a sector. The Command Definitions, on page 18 contains details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode, on page 14 and Autoselect Command Sequence, on page 19 for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics, on page 37 contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I CC read specifications apply. Refer to Write Operation Status, on page 26 for more information, and to AC Characteristics, on page 37 for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

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The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device is in the standby mode, but the standby current is greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws ac- tive current until the operation is completed. In the DC Characteristics table, I CC3 and ICC4 represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The de- vice automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The op- eration that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current is greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin re- mains a 0 (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/ BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is 1), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to AC Characteristics, on page 37 for RESET# parameters and to Figure 14, on page 38 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

February 16, 2006 S29AL008D_00A4 S29AL008D 13 Data Sheet Ta bl e 2 . S29AL008D T op Boot Block Sector Addresses Sector A18 A17 A16 A15 A14 A13 A12 Sector Size (Kbytes/ Kwords) Address Range (in hexadecimal) (x8) Address Range (x16) Address Range SA0 0 0 0 0 X X X 64/32 00000h–0FFFFh 00000h–07FFFh SA1 0 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh SA2 0 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh SA3 0 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh SA4 0 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh SA5 0 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh SA6 0 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh SA7 0 1 1 1 X X X 64/32 70000h–7FFFFh 38000h–3FFFFh SA8 1 0 0 0 X X X 64/32 80000h–8FFFFh 40000h–47FFFh SA9 1 0 0 1 X X X 64/32 90000h–9FFFFh 48000h–4FFFFh SA10 1 0 1 0 X X X 64/32 A0000h–AFFFFh 50000h–57FFFh SA11 1 0 1 1 X X X 64/32 B0000h–BFFFFh 58000h–5FFFFh SA12 1 1 0 0 X X X 64/32 C0000h–CFFFFh 60000h–67FFFh SA13 1 1 0 1 X X X 64/32 D0000h–DFFFFh 68000h–6FFFFh SA14 1 1 1 0 X X X 64/32 E0000h–EFFFFh 70000h–77FFFh SA15 1 1 1 1 0 X X 32/16 F0000h–F7FFFh 78000h–7BFFFh SA16 1 1 1 1 1 0 0 8/4 F8000h–F9FFFh 7C000h–7CFFFh SA17 1 1 1 1 1 0 1 8/4 FA000h–FBFFFh 7D000h–7DFFFh SA18 1 1 1 1 1 1 X 16/8 FC000h–FFFFFh 7E000h–7FFFFh

14 S29AL008D S29AL008D_00A4 February 16, 2006

Note for Tables and : Address range is A18:A-1 in byte mode and A18:A0 in word mode. See Word/Byte Configura- tion, on page 10. Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 4, on page 15. In addition, when verifying sector protection, the sector ad- dress must appear on the appropriate highest order address bits (see Table 2, on page 13 and Table 3, on page 14). Table 4, on page 15 shows the remaining ad- dress bits that are don’t care. When all necessary bits are set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0. To access the autoselect codes in-system, the host system can issue the autose- lect command via the command register, as shown in Table 5, on page 24. This method does not require VID. See Command Definitions, on page 18 for details on using the autoselect mode. Ta bl e 3 . S29AL008D Bottom Boot Block Sector Addresses Sector A18 A17 A16 A15 A14 A13 A12 Sector Size (Kbytes/ Kwords) Address Range (in hexadecimal) (x8) Address Range (x16) Address Range SA0 0 0 0 0 0 0 X 16/8 00000h–03FFFh 00000h–01FFFh SA1 0 0 0 0 0 1 0 8/4 04000h–05FFFh 02000h–02FFFh SA2 0 0 0 0 0 1 1 8/4 06000h–07FFFh 03000h–03FFFh SA3 0 0 0 0 1 X X 32/16 08000h–0FFFFh 04000h–07FFFh SA4 0 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh SA5 0 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh SA6 0 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh SA7 0 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh SA8 0 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh SA9 0 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh SA10 0 1 1 1 X X X 64/32 70000h–7FFFFh 38000h–3FFFFh SA11 1 0 0 0 X X X 64/32 80000h–8FFFFh 40000h–47FFFh SA12 1 0 0 1 X X X 64/32 90000h–9FFFFh 48000h–4FFFFh SA13 1 0 1 0 X X X 64/32 A0000h–AFFFFh 50000h–57FFFh SA14 1 0 1 1 X X X 64/32 B0000h–BFFFFh 58000h–5FFFFh SA15 1 1 0 0 X X X 64/32 C0000h–CFFFFh 60000h–67FFFh SA16 1 1 0 1 X X X 64/32 D0000h–DFFFFh 68000h–6FFFFh SA17 1 1 1 0 X X X 64/32 E0000h–EFFFFh 70000h–77FFFh SA18 1 1 1 1 X X X 64/32 F0000h–FFFFFh 78000h–7FFFFh

February 16, 2006 S29AL008D_00A4 S29AL008D 15 Data Sheet L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. Sector Protection/Unprotection The hardware sector protection feature disables both program and erase opera- tions in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. The device is shipped with all sectors unprotected. Spansion offers the option of programming and protecting sectors at its factory prior to shipping the device through Spansion’s ExpressFlash™ Service. Contact an Spansion representative for details. It is possible to determine whether a se ctor is protected or unprotected. See Autoselect Mode, on page 14 for details. Sector Protection/unprotection can be implemented via two methods. The primary method requires V ID on the RESET# pin only, and can be imple - mented either in-system or via programming equipment. Figure 2, on page 17 shows the algorithms and Figure 23, on page 46 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protec ted prior to the first sector unprotect write cycle. The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only Spansion flash devices. Publication number 20536 contains further details; contact an Spansion representative to request a copy. T emporary Sector Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to V ID. During this mode, formerly protected sectors can be pro - grammed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Ta b l e 4 . S29AL008D Autoselect Codes (High Voltage Method) Description Mode CE# OE# WE# A18 to A12 A11 to A10 A9 to A7 A6 to A2 A1 A0 DQ8 to DQ15 DQ7 to DQ0 Manufacturer ID: Spansion L L H X X VID X L X L L X 01h Device ID: Am29LV800B (Top Boot Block) Word L L H X X VID X L X L H 22h DAh Byte L L H X DAh Device ID: Am29LV800B (Bottom Boot Block) Word L L H X X VID X L X L H 22h 5Bh Byte L L H X 5Bh Sector Protection Verification L L H SA X VID X L X H L X 01h (protected) X 00h (unprotected

16 S29AL008D S29AL008D_00A4 February 16, 2006

Figure 1. T emporary Sector Unprotect Operation

1. All protected sectors unprotected.
2. All previously protected sectors are protected once

Figure 2. In-System Sector Protect/Sector Unprotect Algorithms

18 S29AL008D S29AL008D_00A4 February 16, 2006

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 5, on page 24 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This pro- tects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Write Pulse Glitch Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. Command Definitions Writing specific address and data comm ands or sequences into the command register initiates device operations. Table 5, on page 24 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the AC Characteristics, on page 37. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Sus pend mode, the system may once again read array data with the same exception. See Erase Suspend/Erase Resume Commands, on page 22 for more information on this mode.

February 16, 2006 S29AL008D_00A4 S29AL008D 19 Data Sheet The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the Reset Com- mand, next. See also Requirements for Reading Array Data, on page 10 for more information. The table provides the read parameters, and Figure 13, on page 37 shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to read ing array data (also applies to progra mming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the op- eration is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manu- facturer and devices codes, and determine whether or not a sector is protected. Table 5, on page 24 shows the address and data requirements. This method is an alternative to that shown in Table 4, on page 15, which is intended for PROM pro- grammers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, fol- lowed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h in word mode (or 02h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is un protected. Refer to Table 2, on page 13 and Table 3, on page 14 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Word/Byte Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program com - mand sequence is initiated by writing two unlock write cycles, followed by the

20 S29AL008D S29AL008D_00A4 February 16, 2006

program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 5, on page 24 shows the address and data requir ements for the byte program com - mand sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7, DQ6, or RY/BY#. See Write Operation Status, on page 26 for information on these status bits. Any commands written to the device du ring the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program- ming operation. The program command sequence should be reinitiated once the device resets to reading array data, to ensure data integrity. Programming is allowed in any sequ ence and across sector boundaries. A bit cannot be programmed from a 0 back to a 1. Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read shows that the data is still 0. Only erase operations can convert a 0 to a 1. Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program ming time. Table 5, on page 24 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock By- pass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data. Figure 3, on page 21 illustrates the algorithm for the program operation. See Erase / Program Operations, on page 41 i for parameters, and Figure 17, on page 42 for timing diagrams.

Note: See Table 5, on page 24 for program command sequence. Figure 3. Program Operation requirements for the chip erase command sequence. ated once the device returns to reading array data, to ensure data integrity. returns to reading array data and addresses are no longer latched.

22 S29AL008D S29AL008D_00A4 February 16, 2006

Figure 4, on page 24 illustrates the algorithm for the erase operation. See Erase / Program Operations, on page 41 for parameters, and Figure 18, on page 43 for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two addi- tional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 5, on page 24 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector addresses and sector erase com - mands may be written. Loading the sect or erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is rec ommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See DQ3: Sector Erase Timer, on page 29.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation begins , only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to Write Operation Status, on page 26 for information on these status bits. Figure 4, on page 24 illustrates the algorithm for the erase operation. Refer to Erase / Program Operations, on page 41 for parameters, and to Figure 18, on page 43 for timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase oper- ation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Em- bedded Program algorithm. Writing the Erase Suspend command during the

February 16, 2006 S29AL008D_00A4 S29AL008D 23 Data Sheet Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are don’t-cares when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation is suspended, the system can read array data from or program data to any sector not selected for erasure. (The device erase suspends all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any addr ess within erase-suspended sectors pro duces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation Status, on page 26 for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status, on page 26 for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See Autoselect Com- mand Sequence, on page 19 for more information. The system must write the Erase Resume command (address bits are don’t care) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device resumes erasing.

24 S29AL008D S29AL008D_00A4 February 16, 2006

1. See Table 5, on page 24 for erase command sequence.
2. See DQ3: Sector Erase Timer, on page 29 for more information.

Figure 4. Erase Operation

90 X00 01

55 SA 30

February 16, 2006 S29AL008D_00A4 S29AL008D 25 Data Sheet Legend: X = Don’t care, RA = Address of the memory location to be read, RD = Data read from location RA during read operation, and PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18–A12 uniquely select any sector. Notes: 1. See Table 1, on page 10 for a description of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all bus cycles are write operations. 4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles. 5. Address bits A18–A11 are don’t cares for unlock and command cycles, unless PA or SA required. 6. No unlock or command cycles required when reading array data. 7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 8. The fourth cycle of the autoselect command sequence is a read cycle. 9. The data is 00h for an unprotected se ctor and 01h for a protected sector. See Autoselect Command Sequence, on page 19 for more information. 10.The Unlock Bypass command is required prior to the Unlock Bypass Program command. 11.The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. 12.The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 13.The Erase Resume command is valid only during the Erase Suspend mode.

26 S29AL008D S29AL008D_00A4 February 16, 2006

The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 6, on page 31 and the following subsections describe the functions of th ese bits. DQ7, RY/B Y#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the com - plement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a pro gram address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to reading array data. During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Sus- pend mode, Data# Po lling produces a 1 on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the device outputs the complement, or 0. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the se lected sectors that are protected. When the system detects DQ7 changes from the complement to true data, it can read valid data at DQ7–DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0–D Q6 while Output Enable (OE#) is as serted low. Figure 19, on page 44 , Data# Polling Timings (During Embedded Algorithms), illustrates this. Table 6, on page 31 shows the outputs for Data# Polling on DQ7. Figure 5, on page 27 shows the Data# Polling algorithm.

1. VA = Valid address for programming. During a sector

valid address is any non-protected sector address.

1. DQ7 should be rechecked even if DQ5 = 1 because

DQ7 may change simultaneously with DQ5. Figure 5. Data# Polling Algorithm

28 S29AL008D S29AL008D_00A4 February 16, 2006

If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 6, on page 31 shows the outputs for RY/BY#. Figure 13, on page 37, Figure 14, Figure 17, on page 42 and Figure 18, on page 43 shows RY/BY# for read, reset, program, and erase operations, respectively. DQ6: T oggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whethe r the device entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cy- cles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algo - rithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is ac- tively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en- ters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alter- natively, the system can use DQ7 (see the subsection DQ7: Data# Polling, on page 26). If a program address falls within a pr otected sector, DQ6 toggles for approxi - mately 1 µs after the program command se quence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 6, on page 31 shows the outputs for Toggle Bit I on DQ6. Figure 6, on page 30 shows the toggle bit algorithm. Figure 20, on page 44 shows the toggle bit timing diagrams. Figure 21, on page 45 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection DQ2: Toggle Bit II, on page 28. DQ2: T oggle Bit II The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that were selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected

February 16, 2006 S29AL008D_00A4 S29AL008D 29 Data Sheet for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6, on page 31 to compare outputs for DQ2 and DQ6. Figure 6, on page 30 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I, on page 28 subsection. Figure 20, on page 44 shows the toggle bit timing dia- gram. Figure 21, on page 45 shows the differences between DQ2 and DQ6 in graphical form. Reading T oggle Bits DQ6/DQ2 Refer to Figure 6, on page 30 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bi t after the first read . After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device completed the program or erase opera tion. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device success fully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as de scribed in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algo - rithm when it returns to determine the status of the operation (top of Figure 6, on page 30). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1. This is a failure con- dition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a 1 to a lo- cation that is previously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the operation exceeds the timing limits, DQ5 produces a 1. Under both these conditions, the system must issue the reset command to return the device to reading array data. DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to de- termine whether or not an erase operation started. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for era sure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from 0 to 1. The system may ignore DQ3 if the system can guar antee that the time between additional

30 S29AL008D S29AL008D_00A4 February 16, 2006

Command Sequence, on page 22.

1. Read toggle bit twice to determine whether or not it
2. Recheck toggle bit because it may stop toggling as

Figure 6. To g g l e B i t A l g o r i t h m

February 16, 2006 S29AL008D_00A4 S29AL008D 31 Data Sheet additional sector erase commands. To ensure the command is accepted, the sys- tem software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not be accepted. Table 6 shows the outputs for DQ3. Notes: 1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation exceeds the maximum timing limits. See DQ5: Exceeded Timing Limits, on page 29 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. Ta bl e 6 . Write Operation Status Operation DQ7 (Note 2) DQ6 DQ5 (Note 1) DQ3 DQ2 (Note 2) RY/BY# Standard Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0 Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0 Erase Suspend Mode Reading within Erase Suspended Sector 1 No toggle 0 N/A Toggle 1 Reading within Non-Erase Suspended Sector Data Data Data Data Data 1 Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

32 S29AL008D S29AL008D_00A4 February 16, 2006

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot VSS
2. Minimum DC input voltage on pins A9, OE#, and RESET# is –0.5 V. During voltage transitions, A9, OE#, and

voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.

1. No more than one output may be shor ted to ground at a time. Duration of the short circuit should not be greater

Figure 7. Maximum Negative Overshoot Waveform Figure 8. Maximum Positive Overshoot Waveform

February 16, 2006 S29AL008D_00A4 S29AL008D 33 Data Sheet DC Characteristics Notes: 1. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. At extended temperature range (>+85°C), typi cal current is 5µA and maximum current is 10µA. 5. Automatic sleep mode enable s the low power mode when addresses remain stable for tACC + 30 ns. 6. Not 100% tested. Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, Byte Mode

10 MHz 15 30

5 MHz 9 16

1 MHz 2 4

CE# = VIL, OE# = VIH, Word Mode I CC2 VCC Active Write Current (Notes 2, 3, 6) CE# = VIL, OE# = VIH 20 35 mA ICC3 VCC Standby Current (Notes 2, 4) CE#, RESET# = VCC±0.3 V 0.2 5 µA ICC4 VCC Reset Current (Notes 2, 4) RESET# = VSS ± 0.3 V 0.2 5 µA ICC5 Automatic Sleep Mode (Notes 2, 4, 5) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 5 µA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x VCC VCC + 0.3 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.3 V 11.5 12.5 V VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 2.4 V VOH2 IOH = –100 µA, VCC = VCC min VCC–0.4 VLKO Low VCC Lock-Out Voltage 2.3 2.5 V

34 S29AL008D S29AL008D_00A4 February 16, 2006

Figure 9. I CC1 Current vs. Time (Showing Active and Automatic Sleep Currents) Figure 10. T ypical I CC1 vs. Frequency

Note: Nodes are IN3064 or equivalent. Figure 11. Te s t S e t u p

36 S29AL008D S29AL008D_00A4 February 16, 2006

Figure 12. Input Waveforms and Measurement Levels

February 16, 2006 S29AL008D_00A4 S29AL008D 37 Data Sheet AC Characteristics Notes: 1. Not 100% tested. 2. See Figure 11, on page 35 and DC Characteristics, on page 33 for test specifications. Ta bl e 8 . Read Operations Parameter

Description

JEDEC Std Test Setup 55 70 90 Unit tAVAV tRC Read Cycle Time (Note 1) Min 55 70 90 ns tAVQV tACC Address to Output Delay CE# = VIL OE# = VIL Max 55 70 90 tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 70 90 tGLQV tOE Output Enable to Output Delay Max 25 30 35 tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 25 25 30 tGHQZ tDF Output Enable to Output High Z (Note 1) Max 25 25 30 tOEH Output Enable Hold Time (Note 1) Read Min 0 Toggle and Data# Polling Min 10 tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Min 0 tCE Outputs WE# Addresses CE# OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tO

0 VRY/BY#

RESET# tD tO Figure 13. Read Operations Timings

38 S29AL008D S29AL008D_00A4 February 16, 2006

Figure 14. RESET# Timings

February 16, 2006 S29AL008D_00A4 S29AL008D 39 Data Sheet AC Characteristics Ta bl e 1 0 . Word/Byte Configuration (BYTE#) Parameter Speed Options JEDEC Std Description 55 70 90 Unit tELFL/tELFH CE# to BYTE# Switching Low or High Max 5 nstFLQZ BYTE# Switching Low to Output HIGH Z Max 25 25 30 tFHQV BYTE# Switching High to Output Active Min 55 70 90

40 S29AL008D S29AL008D_00A4 February 16, 2006

Figure 15. BYTE# Timings for Read Operations Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. Figure 16. BYTE# Timings for Write Operations

February 16, 2006 S29AL008D_00A4 S29AL008D 41 Data Sheet AC Characteristics Erase / Program Operations Notes: 1. Not 100% tested. 2. See Table , on page 48 for more information. Parameter Speed Options JEDEC Std Description 55 70 90 Unit tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 ns tAVWL tAS Address Setup Time 0 tWLAX tAH Address Hold Time 45 tDVWH tDS Data Setup Time 35 35 45 tWHDX tDH Data Hold Time 0 tOES Output Enable Setup Time 0 tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) 0 tELWL tCS CE# Setup Time 0 tWHEH tCH CE# Hold Time 0 tWLWH tWP Write Pulse Width 35 tWHWL tWPH Write Pulse Width High 30 tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ µs Word 7 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) 0.7 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Recovery Time from RY/BY# 0 ns tBUSY Program/Erase Valid to RY/BY# Delay 90

42 S29AL008D S29AL008D_00A4 February 16, 2006

1. PA = program address, PD = program data, D OUT is the true data at the program address.
2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status, on
2. Illustration shows de vice in word mode.

Figure 18. Chi p/Sector Erase Operation Timings

44 S29AL008D S29AL008D_00A4 February 16, 2006

Figure 19. Data# Polling Timings (During Embedded Algorithms) read cycle, and array data read cycle. Figure 20. T oggle Bit Timings (During Embedded Algorithms)

46 S29AL008D S29AL008D_00A4 February 16, 2006

Figure 23. Sector Protect/ Unprotect Timing Diagram

February 16, 2006 S29AL008D_00A4 S29AL008D 47 Data Sheet AC Characteristics Notes: 1. Not 100% tested. 2. See Table , on page 48 for more information. Ta bl e 1 2 . Alternate CE# Controlled Erase/Program Operations Parameter Speed Options JEDEC Std Description 55 70 90 Unit tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 ns tAVEL tAS Address Setup Time 0 tELAX tAH Address Hold Time 45 tDVEH tDS Data Setup Time 35 35 45 tEHDX tDH Data Hold Time 0 tOES Output Enable Setup Time 0 tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) 0 tWLEL tWS WE# Setup Time 0 tEHWH tWH WE# Hold Time 0 tELEH tCP CE# Pulse Width 35 tEHEL tCPH CE# Pulse Width High 30 tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ µs Word 16 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) 1 sec

48 S29AL008D S29AL008D_00A4 February 16, 2006

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data
2. Figure indicates the last two bus cycles of command sequence.
3. Word mode address used as an example.

Figure 24. Alternate CE# Controlled Write Operation Timings

February 16, 2006 S29AL008D_00A4 S29AL008D 49 Data Sheet 2. Under worst case conditions of 90°C, V CC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algo rithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to exec ute the two- or four-bus-cycle sequence for the program command. See Table 5, on page 24 for further information on command definitions. 6. The device has a guaranteed minimum erase an d program cycle endurance of 1,000,000 cycles. Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. Ta bl e 1 3 . Latchup Characteristics Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V VCC Current –100 mA +100 mA Ta bl e 1 4 . TSOP , SO, and BGA Pin Capacitance Parameter Symbol Parameter Description Test Setup Package Typ Max Unit CIN Input Capacitance VIN = 0 TSOP, SO 6 7.5 pF BGA 4.2 5.0 COUT Output Capacitance VOUT = 0 TSOP, SO 8.5 12 BGA 5.4 6.5 CIN2 Control Pin Capacitance VIN = 0 TSOP, SO 7.5 9 BGA 3.9 4.7

50 S29AL008D S29AL008D_00A4 February 16, 2006

TS 048—48-Pin Standard TSOP * For reference only. BSC is an ANSI standard for Basic Space Centering. Dwg rev AA; 10/99

February 16, 2006 S29AL008D_00A4 S29AL008D 51 Data Sheet Physical Dimensions VBK 048 - 48 Ball Fine-Pitch Ball Grid Array (FBGA) 8.15 x 6.15 mm 3338 \\ 16-038.25b NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. PACKAGE VBK 048 JEDEC N/A 6.15 mm x 8.15 mm NOM PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.00 OVERALL THICKNESS A1 0.18 --- --- BALL HEIGHT A2 0.62 --- 0.76 BODY THICKNESS D 8.15 BSC. BODY SIZE E 6.15 BSC. BODY SIZE D1 5.60 BSC. BALL FOOTPRINT E1 4.00 BSC. BALL FOOTPRINT MD 8 ROW MATRIX SIZE D DIRECTION ME 6 ROW MATRIX SIZE E DIRECTION N 48 TOTAL BALL COUNT fb 0.35 --- 0.43 BALL DIAMETER e 0.80 BSC. BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT --- DEPOPULATED SOLDER BALLS SIDE VIEW TOP VIEW SEATING PLANE A2A (4X)0.10 D E C0.10 A1 C B A C0.08 BOTTOM VIEW A1 CORNER BAMf 0.15 C M e SE SD ABCDEFG H fb Cf 0.08 PIN A1 CORNER INDEX MARK

52 S29AL008D S29AL008D_00A4 February 16, 2006

SO 044—44-Pin Small Outline Package Dwg rev AC; 10/99

February 16, 2006 S29AL008D_00A4 S29AL008D 53 Data Sheet Revision Summary Revision A (September 8, 2004) Initial release Revision A 1 (February 18, 2005) Global Updated Trademark Added Package type designator Valid Combinations Changed Package Type, Material, and Temperature Range designator Under Package Descriptions, change SSOP to SOP Revision A2 (June 1, 2005) Global Updated status from Advance Information to Preliminary data sheet. Distinctive Characteristics Updated manufactured process technology. Updated high performance access time. Added extended temperature range. Added cycling endurance information. Production Selector Guide Added 55ns speed option and column. Added tube and tray packing types. Added extended temperature range Added model numbers. Valid Combinations Table Added speed option. Added packing types. Added model number. Added note for this table. Operating Range Added extended temperature range information. Test Conditions Added 55ns speed option. AC Characteristics Read Operation Table Added 55ns speed option. Word/Byte Configuration Table Added 55ns speed option.

54 S29AL008D S29AL008D_00A4 February 16, 2006

Erase/Program Operation Table Added 55ns speed option. Alternate CE# Controlled Erase/Program Operation Table Added 55ns speed option. Erase and Programming Performance Changed Byte Programing Time values for Typical and Maximum. Revision A3 (June 16, 2005) Changed from Preliminary to full Data Sheet. Updated Valid Combinations table. Revision A4 (February 16, 2006) Corrected minor typo on page 1. Added cover page. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men- tioned uses of the products. Any semiconductor devices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright ©2004-2006 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies