S25FL004D SPANSION | Alldatasheet
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Publication Number S25FL004D_00 Revision A Amendment 0 Issue Date June 28, 2004 ADVANCE INFORMATION S25FL Family (Serial Peripheral Interface) S25FL004D 4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface Distinctive Characteristics ARCHITECTURAL ADVANTAGES Single power supply operation — Full voltage range: 2.7 to 3.6 V read and program operations Memory Architecture — Eight sectors with 512 Kb each Program — Page Program (up to 256 bytes) in 1.5 ms (typical) — Program cycles are on a page by page basis Erase — 0.5 s typical sector erase time — 4 s typical bulk erase time Endurance — 100,000 cycles per sector typical Data Retention — 20 years typical Device ID — Electronic signature Process Technology — Manufactured on 0.25 µm process technology Package Option — Industry Standard Pinouts — 8-pin SO (208mil) package — 8-contact WSON leadless package (6x5mm) PERFORMANCE CHARACTERISTICS Speed — 50 MHz clock rate (maximum) Power Saving Standby Mode — Standby Mode 1 µA (typical) Memory Protection Features Memory Protection — W# pin works in conjunction with Status Register Bits to protect specified memory areas — Status Register Block Protection bits (BP1, BP0) in status register configure parts of memory as read- only SOFTWARE FEATURES SPI Bus Compatible Serial Interface
2 S25FL Family (Serial Peripheral Interface) S25FL004D S25FL004D_00A0 June 28, 2004
The S25FL004D device is a 3.0 Volt (2.7 V to 3.6 V) single power supply Flash memory device. S25FL004D consists of eight sectors, each with 512 Kb memory. Data appears on SI input pin when inputting data into the memory and on the SO output pin when outputting data from the memory. The devices are designed to be programmed in-system with the standard system 3.0 Volt V CC supply. The memory can be programmed 1 to 256 bytes at a time, using the Page Program in - struction. The memory supports Sector Erase and Bulk Erase instructions. Each device requires only a 3.0 Volt power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program op - erations. This device does not require VPP supply.
4 S25FL Family (Serial Peripheral Interface) S25FL004D S25FL004D_00A0 June 28, 2004
HOLD# SRAM PS Logic Array - L Array - R RD DATA PATH IO X D E C CS#
June 28, 2004 S25FL004D_00A0 S25FL Family (Serial Peripheral Interface) S25FL004D 5 Advance Information Connection Diagrams Input/Output Descriptions SCK = Serial Clock Input SI = Serial Data Input SO = Serial Data Output CS# = Chip Select Input W# = Write Protect Input HOLD# = Hold Input VCC = Supply Voltage Input GND = Ground Input Logic Symbol CS# SO GND SI SCK HOLD# VCC 1 CS# SO GND SI SCK HOLD# VCC 8-pin Plastic Small Outline Package (SO) 8-contact WSON Package CS# SO GND SI SCK HOLD# VCC
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Ordering Information
The order number (Valid Combination) is formed by the following: Notes: 1. Type 1 is standard. Specify other options as required. 2. Contact your local sales office for availability. 3. Package marking omits leading “S25” and speed, package, and leading digit of model number from ordering part number. 4. If “Last Digit of Model Number” is 3, this signifies a S08-Wide body Lead (Pb)-free package. For example: FL004DI3. If “Last Digit of Model Number” is 1, this signifies a S08-Wide body standard package. For example: FL004DI1. Valid Combinations Valid Combination configuration planned to be supported for this device. Note: Ordering part number and package marking is pending final product introduction. Contact your sales representative for further information. S25FL 004 D 0L M A I 01 I PACKING TYPE 1= T u b e ( s t a n d a r d ) (Note 1) 3 = 13” Tape and Reel (Note 2) MODEL NUMBER (Additional Ordering Options) 01 = S0-8 Wide (208mil) Package TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) PACKAGE MATERIALS A= S t a n d a r d F = Lead (Pb) -free (Note 2) PACKAGE TYPE M = 8 pin Plastic Small Outline Package N= W S O N (Note 2) SPEED 0L = 50 MHz DEVICE TECHNOLOGY D = 0.25 µm process technology DENSITY 004 = 4 Mb DEVICE FAMILY S25FL Spansion TM Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory S25FL Valid Combinations Base Ordering Part Number Speed Option Package & Temperature Model Number Packing Type Package Marking S25FL004D 0L MAI, MFI, NFI 01 1, 3 (Note 1) FL004D + (Temp) + (Last Digit of Model Number) (Note 4)
June 28, 2004 S25FL004D_00A0 S25FL Family (Serial Peripheral Interface) S25FL004D 7 Advance Information Signal Description Signal Data Output (SO): This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (SCK). Serial Data Input (SI): This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (SCK). Serial Clock (SCK): This input signal provides the timing of the serial interface. Instructions, addresses, and data present at the Serial Data input (SI) are latched on the rising edge of Serial Clock (SCK). Data on Serial Data Output (SO) changes after the falling edge of Serial Clock (SCK). Chip Select (CS#): When this input signal is High, the device is deselected and Serial Data Output (SO) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in Standby mode. Driving Chip Select (CS#) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select (CS#) is required prior to the start of any instruction. Hold (HOLD#): The Hold (HOLD#) signal is used to pause any serial communi- cations with the device without deselecting the device. During the Hold instruction, the Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial Clock (SCK) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (CS#) driven Low. Write Protect (W#): The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). SPI Modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: CPOL = 0, CPHA = 0 CPOL = 1, CPHA = 1 For these two modes, input data is latched in on the rising edge of Serial Clock (SCK), and output data is available from the falling edge of Serial Clock (SCK). The difference between the two modes, as shown in Figure 2, is the clock polarity when the bus master is in Standby and not transferring data: SCK remains at 0 for (CPOL = 0, CPHA = 0) SCK remains at 1 for (CPOL = 1, CPHA = 1)
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Figure 1. Bus Master and Memory Devices on the SPI Bus Note: The Write Protect (W#) and Hold (HOLD#) signals should be driven, High or Low as appropriate. Figure 2. SPI Modes Supported
June 28, 2004 S25FL004D_00A0 S25FL Family (Serial Peripheral Interface) S25FL004D 9 Advance Information Operating Features All data into and out of the device is shifted in 8-bit chunks. Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle. To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be pro grammed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. Sector Erase, or Bulk Erase The Page Program (PP) instruction allows bits to be programmed from 1 to 0. Be- fore this can be applied, the bytes of the memory need to be first erased to all 1’s (FFh) before any programming. This can be achieved in two ways: 1) a sector at a time using the Sector Erase (SE) instruction, or 2) throughout the entire memory, using the Bulk Erase (BE) instruction. Polling During a Write, Program, or Erase Cycle A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst-case delay. The Write in Progress (WIP) bit is provided in the Status Register so that the applica tion program can monitor its value, polling it to establish when the previous Write cycle, Program cycle, or Erase cycle is complete. Active Power and Standby Power Modes When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes into the Standby Power mode. The device consumption drops to I SB. This can be used as an extra Deep Power Down on mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program, or Erase instructions. Status Register The Status Register contains a number of status and control bits, as shown in Fig- ure 7, that can be read or set (as appropriate) by specific instructions WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. BP2, BP1, BP0 bits: The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. SRWD bit: The Status Register Write Disable (SRWD) bit is operated in con- junction with the Write Protect (W#) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W#) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits.
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The SPI memory device boasts the following data protection mechanisms: All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: —P o w e r - u p — Write Disable (WRDI) instruction completion — Write Status Register (WRSR) instruction completion — Page Program (PP) instruction completion — Sector Erase (SE) instruction completion — Bulk Erase (BE) instruction completion The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be con- figured as read-only. This is the Software Protected Mode (SPM). The Write Protect (W#) signal works in cooperation with the Status Register Write Disable (SRWD) bit to enable write-protection. This is the Hardware Protected Mode (HPM). Program, Erase and Write Status Register instructions are checked to verify that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. Ta bl e 1 . Protected Area Sizes (S25FL004D). Hold Condition Modes The Hold (HOLD#) signal is used to pa use any serial communications with the device without resetting the clocking sequence. Hold (HOLD#) signal gates the clock input to the device. However, taking this signal Low does not terminate any Write Status Register, Program or Erase Cycle that is currently in progress. To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold condition starts on the falling edge of the Hold (HOLD#) signal, provided that this coincides with Serial Clock (SCK) being Low (as shown in Figure 3). The Hold condition ends on the rising edge of the Hold (HOLD#) signal, provided that this coincides with Serial Clock (SCK) being Low. Protected Memory Area (Top Level) Status Register Content Memory Content BP2 Bit BP1 Bit BP0 Protected Area Unprotected Area 0 0 0 0 none 00000–7FFFF 1/8 0 0 1 70000–7FFFF 00000–6FFFF 1/4 0 1 0 60000–7FFFF 00000–5FFFF 1/2 0 1 1 40000–7FFFF 00000–3FFFF All 1 0 0 00000-7FFFF none All 1 0 1 00000-7FFFF none All 1 1 0 00000-7FFFF none All 1 1 1 00000-7FFFF none
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The memory is organized as: S25FL004D: Eight sectors of 512 Kbit each Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk erasable (bits are erased from 0 to 1). Ta bl e 2 . Sector Address T able – S25FL004D Sector Address Range SA7 70000h 7FFFFh SA6 60000h 6FFFFh SA5 50000h 5FFFFh SA4 40000h 4FFFFh SA3 30000h 3FFFFh SA2 20000h 2FFFFh SA1 10000h 1FFFFh SA0 00000h 0FFFFh
June 28, 2004 S25FL004D_00A0 S25FL Family (Serial Peripheral Interface) S25FL004D 13 Advance Information Instructions All instructions, addresses, and data are shifted in and out of the device, starting with the most significant bit. Serial Data Input (SI) is sampled on the first rising edge of Serial Clock (SCK) after Chip Select (CS#) is driven Low. Then, the one- byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (SI), each bit bein g latched on the rising edges of Serial Clock (SCK). The instruction set is listed in Table 3. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. Chip Select (CS#) must be driven High after the last bit of the in struction sequence has been shifted in. In the case of a Read Data Bytes (READ), Read Status Register (RDSR), Fast Read (FAST_READ) or Release from Deep Power Down and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out se quence is being shifted out to terminate the transaction. In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN), or Write Disable (WRDI) instruc- tion, Chip Select (CS#) must be driv en High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected Ta bl e 3 . Instruction Set. Instruction Description One-Byte Instruction Code Address Bytes Dummy Byte Data Bytes Status Register Operations WREN Write Enable 06H (0000 0110) 0 0 0 WRDI Write Disable 04H (0000 0100) 0 0 0 RDSR Read from Status Register 05H (0000 0101) 0 0 1 to Infinity WRSR Write to Status Register 01H (0000 0001) 0 0 1 Read Operations READ Read Data Bytes 03H (0000 0011) 3 0 1 to Infinity FAST_READ Read Data Bytes at Higher Speed 0BH (0000 1011) 3 1 1 to Infinity Erase Operations SE Sector Erase D8H (1101 1000) 3 0 0 BE Bulk (Chip) Erase C7H (1100 0111) 0 0 0 Program Operations PP Page Program 02H (0000 0010) 3 0 1 to 256 Deep Power Down Savings Mode Operations DP Deep Power Down B9H (1011 1001) 0 0 0 RES Release from Deep Power Down ABH (1010 1011) 0 0 0 Release from Deep Power Down and Read Electronic Signature ABH (1010 1011) 0 3 1 to Infinity
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the instruction code, and then driving Chip Select (CS#) High. Figure 4. Write Enable (WREN) Instruction Sequence Figure 5. Write Disable (WRDI) Instruction Sequence
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been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Pro- tect (BP2, BP1, BP0) bits are 0. WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1, the internal Write Enable Latch is set; when set to 0, the internal Write Enable Latch is reset and no Write Status Register, Pro gram or Erase instruction is accepted. WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. This bit is a read only bit and is read by executing a RDSR instruction. If this bit is 1, such a cycle is in progress, if it is 0, no such cycle is in progress. Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code and the data byte on Serial Data Input (SI). The instruction sequence is shown in Figure 8. The Write Status Register (WRSR) instruction has no effect on bits b6, b5, b1 and b0 of the Status Register. Bits b6, b5 are always read as 0. Chip Select (CS#) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not exe- cuted. As soon as Chip Select (CS#) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. At some un specified time before the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the val- ues of the Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 1. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W#) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W#) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.
Figure 8. Write Status Register (WRSR) Instruction Sequence
- As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.
The protection features of the device are summarized in Table 4. by a Write Enable (WREN) instruction. protected against data modification.
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using the Block Protect (BP2, BP1, BP0) bits of the Status Register, can be used. with a maximum speed of 33 MHz. to be continued indefinitely. (CS#) High. Chip Select (CS#) can be driven High at any time during data output. Figure 9. Read Data Bytes (READ) Instruction Sequence
at a maximum frequency FSCK, during the falling edge of Serial Clock (SCK). The (FAST_READ) instruction is terminated by driving Chip Select (CS#) High. is rejected without having any effects on the cycle that is in progress. Figure 10. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence instruction has been decoded, the device sets the Write Enable Latch (WEL). The instruction sequence is shown in Figure 11. has been latched in, otherwise the Page Program (PP) instruction is not executed.
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pleted, the Write Enable Latch (WEL) bit is reset. Figure 11. Page Program (PP) Instruction Sequence The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. coded, the device sets the Write Enable Latch (WEL). The instruction sequence is shown in Figure 12. has been latched in, otherwise the Sector Erase (SE) instruction is not executed.
pleted, the Write Enable Latch (WEL) bit is reset. the Block Protect (BP2, BP1, BP0) bits (see Table 1) is not executed. Figure 12. Sector Erase (SE) Instruction Sequence The Bulk Erase (BE) instruction sets to 1 (FFh) all bits inside the entire memory. coded, the device sets the Write Enable Latch (WEL). entire duration of the sequence. The instruction sequence is shown in Figure 13. has been latched in, otherwise the Bulk Erase (BE) instruction is not executed. pleted, the Write Enable Latch (WEL) bit is reset. one or more sectors are protected.
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Figure 13. Bulk Erase (BE) Instruction Sequence driven Low for the entire duration of the sequence. must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 14. before Deep Power Down mode is entered. always powers up in the Standby mode. is in progress, is rejected without having any effect on the cycle in progress.
Figure 14. Deep Power Down (DP) Instruction Sequence Select (CS#) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15.
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Figure 15. Release from Deep Power Down Instruction Sequence is 12h. This can be read using RES instruction. shifted out during the falling edge of Serial Clock (SCK). The instruction sequence is shown in Figure 16. When Chip Select is driven High, the device is put in the Stand-by Power mode. that it can receive, decode and execute instructions.
Figure 16. Release from Deep Power Down and Read Electronic Signature (RES) Instruction Sequence
3 Dummy
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The device must not be selected at power-up or power-down (that is, CS# must follow the voltage applied on VCC) until VCC reaches the correct value as follows: VCC (min) at power-up, and then for a further delay of t PU (as described in Table 5) VSS at power-down A simple pull-up resistor on Chip Select (CS#) can usually be used to insure safe and proper power-up and power-down. The device ignores all instructions until a time delay of tPU (as described in Table 5) has elapsed after the moment that VCC rises above the minimum VCC thresh- old. However, correct operation of the device is not guaranteed if by this time VCC is still below VCC (min). No Write Status Register, Program or Erase instructions should be sent until tPU after VCC reaches the minimum VCC threshold (See Figure 17). At power-up, the device is in Standby mode (not Deep Power Down mode) and the WEL bit is reset. During Power-down or voltage drops, the power down must drop below the VCC (low) for a period of minimum tPD for the device to initialize correctly on power up. (See Figure 18). Normal precautions must be taken for supply rail decoupling to stabilize the VCC feed. Each device in a system should have the V CC rail decoupled by a suitable capacitor close to the package pins (this capacitor is generally of the order of 0.1 µF). At power-down, when VCC drops from the operating voltage to below the mini - mum VCC threshold, all operations are disabled and the device does not respond to any instructions. (The designer needs to be aware that if a power-down occurs while a Write, Program or Erase cycle is in progress, data corruption can result.)
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Ta ble 5 . Power-Up Timing Initial Delivery State The device is delivered with all bits set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). Maximum Rating Stressing the device above the rating listed in the Absolute Maximum Ratings section below may cause permanent damage to the device. These are stress rat- ings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability Absolute Maximum Ratings Voltage with Respect to Ground: Operating Ranges Ambient Operating Temperature (TA) Positive Power Supply Operating ranges define those limits between which functionality of the device is guaranteed. Symbol Parameter Min Max Unit VCC(min) VCC (minimum) 2.7 V VCC(low) VCC (low) V tPU VCC (min) to device operation 2 ms tPD VCC (low) duration ns
June 28, 2004 S25FL004D_00A0 S25FL Family (Serial Peripheral Interface) S25FL004D 29 Advance Information DC Characteristics This section summarizes the DC and AC Characteristics of the device. Designers should check that the operating conditions in their circuit match the measure - ment conditions specified in the Test Specifications in Table 7, when relying on the quoted parameters. CMOS Compatible Ta b l e 6 . DC Characteristics Notes:Typical values are at TA = 25°C and 3.0 V. Parameter Description Test Conditions Min Typ. Max Unit VCC Supply Voltage 2.7 3 3.6 V ICC1 Active Read Current SCK = 0.1 VCC/0.9VCC 33 MHz mA SCK = 0.1 VCC/0.9VCC VCC = 3.0V
50 MHz 9 12
ICC2 Active Page Program Current CS# = VCC 23 mA ICC3 Active WRSR Current CS# = VCC 23 mA ICC4 Active Sector Erase Current CS# = VCC 23 mA ICC5 Active Bulk Erase Current CS# = VCC 23 mA ISB Standby Current VCC = 3.0 V CS# = VCC 50 µA IDP Deep Power Down Current VCC = 3.0 V CS# = VCC 1 5 µA ILI Input Leakage Current VIN = GND to VCC 1 µA ILO Output Leakage Current VIN = GND to VCC 1 µA VIL Input Low Voltage –0.3 0.3 VCC V VIH Input High Voltage 0.7 VCC VCC + 0.5 V VOL Output Low Voltage IOL = 1.6 mA, VCC = VCC min 0.4 V VOH Output High Voltage IOH = –0.1 mA VCC – 0.2 V
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Figure 19. AC Measurements I/O Waveform
0.8 VCC
0.2 VCC
0.7 VCC
0.3 VCC
0.5 VCC
June 28, 2004 S25FL004D_00A0 S25FL Family (Serial Peripheral Interface) S25FL004D 31 Advance Information AC Characteristics Ta bl e 8 . AC Characteristics Note: 1. Typical program and erase times assume the following conditions: 25C, VCC = 3.0V; 10, 000 cycles; checkerboard data pattern 2. Under worst-case conditions of 90C; VCC = 2.7V; 100,000 cycles 3. Not 100% tested Symbol Parameter Min Typ Max Unit FSCK SCK Clock Frequency READ instruction D.C. 33 MHz FSCK SCK Clock Frequency for: FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDSR, WRSR D.C. 50 MHz tCRT Clock Rise Time (Slew Rate) 0.1 V/ns tCFT Clock Fall Time (Slew Rate) 0.1 V/ns tWH SCK High Time 9 ns tWL SCK Low Time 9 ns tCS CS# High Time 100 ns tCSS (Note 3) CS# Setup Time 5 ns tCSH (Note 3) CS# HOLD Time 5 ns tHD (Note 3) HOLD# Setup Time (relative to SCK) 5 ns tCD (Note 3) HOLD# Hold Time (relative to SCK) 5 ns tHC HOLD# Setup Time (relative to SCK) 5 ns tCH HOLD# Hold Time (relative to SCK) 5 ns tV Output Valid 9 ns tHO Output Hold Time 0 ns tHD:DAT Data in Hold Time 5 ns tSU:DAT Data in Setup Time 5 ns tR Input Rise Time 5 ns tF Input Fall Time 5 ns tLZ (Note 3) HOLD# to Output Low Z 9 ns tHZ (Note 3) HOLD# to Output High Z 9 ns tDIS (Note 3) Output Disable Time 9 ns tWPS (Note 3) Write Protect Setup Time 20 ns tWPH (Note 3) Write Protect Hold Time 100 ns tRES Release DP Mode 3 µs tDP CS# High to Deep Power Down Mode 3 µs tW Write Status Register Time 20 (Note 2) ns tPP Page Programming Time 1.5 (Note 1) 2 (Note 2) ms tSE Sector Erase Time 0.5 (Note 1) 0.8 (Note 2) sec tBE Bulk Erase Time 4 (Note 1) 7 (Note 2) sec
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Figure 20. SPI Mode 0 (0,0) Input Timing Figure 21. SPI Mode 0 (0,0) Output Timing
34 S25FL Family (Serial Peripheral Interface) S25FL004D S25FL004D_00A0 June 28, 2004
S08 wide—8-pin Plastic Small Outline 208mils Body Width Package
June 28, 2004 S25FL004D_00A0 S25FL Family (Serial Peripheral Interface) S25FL004D 35 Advance Information Physical Dimensions 8-Contact WSON (6mm x 5mm) Leadless Package
36 S25FL Family (Serial Peripheral Interface) S25FL004D S25FL004D_00A0 June 28, 2004
Revision A (June 28, 2004) Initial release. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by FASL LLC. FASL LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. FASL LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2004 FASL LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of FASL LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.