S25FL004A SPANSION | Alldatasheet
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Publication Number S25FL004A Revision A Amendment 1 Issue Date March 28, 2005 S25FL Family (Serial Peripheral Interface) S25FL004A 4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface ADVANCE INFORMATION Notice to Readers: The Advance Information status indicates that this document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
Notice On Data Sheet Designations Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and ful l pro- duction. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their de- sign. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance In- formation content: “This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without con- tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the pr oduct life cycle, including product qualification, initial produc tion, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under con sideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifica- tions due to changes in technical specifications.” Combination Some data sheets will contain a combination of products with diff erent designations (Advance Inform ation, Preliminary, or Full Production). This type of document will distinguish these prod ucts and their designations wherever necessary, typically on the first page, the ordering information page, and pages with DC Characteristics table and AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nomi nal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or V IO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that sub- sequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.
Publication Number S25FL004A_00 Revision A Amendment 1 Issue Date March 28, 2005 ADVANCE INFORMATION S25FL Family (Serial Peripheral Interface) S25FL004A 4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface Data Sheet Distinctive Characteristics Architectural Advantages Single power supply operation — Full voltage range: 2.7 to 3.6 V read and program operations Memory Architecture — Eight sectors with 512 Kb each Program — Page Program (up to 256 bytes) in 1.5 ms (typical) — Program cycles are on a page by page basis Erase — 1.5 s typical sector erase time — 12 s typical bulk erase time Cycling Endurance — 100,000 cycles per sector typical Data Retention — 20 years typical Device ID — JEDEC standard two-byte electronic signature — RES instruction one-byte electronic signature for backward compatibility Process Technology — Manufactured on 0.20 µm MirrorBit TM process technology Package Option — Industry Standard Pinouts — 8-pin SO package (208 mils) — 8-Contact USON Package (5 x 6 mm), Pb-Free Performance Characteristics Speed — 50 MHz clock rate (maximum) Power Saving Standby Mode — Standby Mode 50 µA (max) — Deep Power Down Mode 1 µA (typical) Memory Protection Features Memory Protection — W# pin works in conjunction with Status Register Bits to protect specified memory areas — Status Register Block Protection bits (BP2, BP1, BP0) in status register configure parts of memory as read- only Software Features SPI Bus Compatible Serial Interface
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The S25FL004A device is a 3.0 Volt (2.7 V to 3.6 V) single power supply Flash memory device. S25FL004A consists of eight sectors, each with 512 Kb memory. Data appears on SI input pin when inputting data into the memory and on the SO output pin when outputting data from the memory. The devices are designed to be programmed in-system with the standard system 3.0 Volt V CC supply. The memory can be programmed 1 to 256 bytes at a time, using the Page Pro- gram instruction. The memory supports Sector Erase and Bulk Erase instructions. Each device requires only a 3.0 Volt power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program operations. This device does not require V PP supply.
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Figure 10. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence 21 Figure 11. Read Identification (RDID) Instruction Sequence and Data-Out Sequence Figure 17. Release from Deep Power Down and Read Electronic Signature (RES) In- Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1 34
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CS# SCK SI SO GND VCC HOLD# SRAM PS Logic Array - L Array - R RD DATA PATH IO X D E C
March 28, 2005 S25FL004A_00_A1 S25FL Family (Serial Peripheral Interface) S25FL004A 5 Advance Information Connection Diagrams Input/Output Descriptions SCK = Serial Clock Input SI = Serial Data Input SO = Serial Data Output CS# = Chip Select Input W# = Write Protect Input HOLD# = Hold Input VCC = Supply Voltage Input GND = Ground Input 8-pin Plastic Small Outline Package (SO) 4 5
8 CS# Vcc
SO HOLD# SCK SI GND WSON 8L USON (5x6mm ) Package
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CS# SO GND SI SCK HOLD# VCC
March 28, 2005 S25FL004A_00_A1 S25FL Family (Serial Peripheral Interface) S25FL004A 7 Advance Information
Ordering Information
The ordering part number is formed by the following valid combinations: Ta b le 1 . S25FL Valid Combinations T able Notes: 1. Type 1 is standard. Specify other options as required. 2. Contact your local sales office for availability. 3. Package marking omits leading S25 and speed, package, and leading digit of model number form ordering part number. 4. A for standard package (non-Pb-free); F for Pb-free package. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. S25FL 004 A 0L M A 1 00 1 PACKING TYPE 0 = Tray (Note 2) 1 = Tube (Standard; See Note 1) 3 = 13” Tape and Reel (Note 2) MODEL NUMBER (Additional Ordering Options) 00 = No additional ordering options TEMPERATURE RANGE I = Industrial (-40°C to + 85°C) PACKAGE MATERIALS A = Standard F = Lead (Pb)-free (Note 2) PACKAGE TYPE M = 8-Pin Plastic Small Outline Package N = 8-Contact USON Package SPEED 0L = 50 MHz DEVICE TECHNOLOGY A = 0.20 µm MirrorBit™ Process Technology DENSITY 004 = 4 Mb DEVICE FAMILY S25FL Spansion TM Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory S25FL Valid Combinations Package Marking (See Note 3) Base Ordering Part Number Speed Option Package & Temperature Model Number Packing Type S25FL004A 0L MAI, MFI NAI, NFI (Note 2) 00 0, 1, 3 (Note 1) FL004A + (Temp) + (Note 4)
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Signal Data Output (SO): This output signal is used to transfer data serially out from the device. Data is shifted out on the falling edge of Serial Clock (SCK). Serial Data Input (SI): This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (SCK). Serial Clock (SCK): This input signal provides the serial interface timing. In - structions, addresses, and data present at the Serial Data input (SI) are latched on the rising edge of Serial Clock (SCK). Data on Serial Data Output (SO) changes after the falling edge of Serial Clock (SCK). Chip Select (CS#): When this input signal is High, the device is deselected and Serial Data Output (SO) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device is in Standby mode. Driv ing Chip Select (CS#) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select (CS#) is required prior to the start of any instruction. Hold (HOLD#): The Hold (HOLD#) signal is used to pause any serial communi- cations with the device without deselecting the device. During the Hold instruction, the Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial Clock (SCK) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (CS#) driven Low. Write Protect (W#): The main purpose of this input signal is to freeze the area memory size that is protected against program or erase instructions (as specified by the values in the Status Register BP1 and BP0 bits). SPI Modes These devices can be driven by a microcontroller with its SPI peripheral running in either of two modes: CPOL = 0, CPHA = 0 CPOL = 1, CPHA = 1 For these two modes, input data is latched in on the rising edge of Serial Clock (SCK), and output data is available from the falling edge of Serial Clock (SCK). The difference between the two modes, as shown in Figure 1, on page 9, is the clock polarity when the bus master is in Standby and not transferring data: SCK remains at 0 for (CPOL = 0, CPHA = 0) SCK remains at 1 for (CPOL = 1, CPHA = 1)
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All device data into and out, is shifted in 8-bit chunks. Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle. To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be pro grammed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. Sector Erase, or Bulk Erase The Page Program (PP) instruction allows bits to be programmed from 1 to 0. Be- fore this can be applied, the memory bytes need to be first erased to all 1’s (FFh) before any programming. This can be achieved in two ways: A sector at a time using the Sector Erase (SE) instruction The entire memory, using the Bulk Erase (BE) instruction Polling During a Write, Program, or Erase Cycle A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst-case delay. The Write in Progress (WIP) bit is provided in the Status Register so that the applica- tion program can monitor its value, polling it to establish when the previous Write cycle, Program cycle, or Erase cycle is complete. Active Power and Standby Power Modes When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes into the Standby Power mode. The device consumption drops to I SB. This can be used as an extra Deep Power Down on mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program, or Erase instructions. Status Register The Status Register contains a number of status and control bits, as shown in Figure 7, on page 17 that can be read or set (as appropriate) by specific instructions WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. WEL bit: The Write Enable Latch (WEL) bit indicates the internal Write Enable Latch status. BP2, BP1, BP0 bits: The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the area size to be software protected against Program and Erase instructions. SRWD bit: The Status Register Write Disable (SRWD) bit is operated in con- junction with the Write Protect (W#) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W#) signal allow the device to be put in the Hardware Protected mode. In this mode, the Status Register’s non-volatile bits (SRWD, BP2, BP1, BP0) become read-only bits.
March 28, 2005 S25FL004A_00_A1 S25FL Family (Serial Peripheral Interface) S25FL004A 11 Advance Information Protection Modes The SPI memory device boasts the following data protection mechanisms: All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: — Power-up — Write Disable (WRDI) instruction completion — Write Status Register (WRSR) instruction completion — Page Program (PP) instruction completion — Sector Erase (SE) instruction completion — Bulk Erase (BE) instruction completion The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be con- figured as read-only. This is the Software Protected Mode (SPM). The Write Protect (W#) signal works in cooperation with the Status Register Write Disable (SRWD) bit to enable write-protection. This is the Hardware Protected Mode (HPM). Program, Erase and Write Status Register instructions are checked to verify that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. Ta bl e 2 . Protected Area Sizes (S25FL004A). Hold Condition Modes The Hold (HOLD#) signal is used to pa use any serial communications with the device without resetting the clocking sequence. Hold (HOLD#) signal gates the clock input to the device. However, taking this signal Low does not terminate any Write Status Register, Program or Erase Cycle that is currently in progress. To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold condition starts on the falling edge of the Hold (HOLD#) signal, provided that this coincides with Serial Clock (SCK) being Low (as shown in Figure 3, on page 12). Protected Memory Area (Top Level) Status Register Content Memory Content BP2 Bit BP1 Bit BP0 Protected Area Unprotected Area 0 0 0 0 none 00000-7FFFF 1/8 0 0 1 70000-7FFFF 00000-6FFFF 1/4 0 1 0 60000-7FFFF 00000-5FFFF 1/2 0 1 1 40000-7FFFF 00000-3FFFF All 1 0 0 00000-7FFFF none All 1 0 1 00000-7FFFF none All 1 1 0 00000-7FFFF none All 1 1 1 00000-7FFFF none
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that this coincides with Serial Clock (SCK) being Low. mains unchanged from the moment of entering the Hold condition. Select (CS#) Low. This prevents the device from going back to the Hold condition. Figure 3. Hold Condition Activation
March 28, 2005 S25FL004A_00_A1 S25FL Family (Serial Peripheral Interface) S25FL004A 13 Advance Information Memory Organization The memory is organized as: S25FL004A: Eight sectors of 512 Kbit each. Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk erasable (bits are erased from 0 to 1). Ta bl e 3 . Sector Address T able – S25FL004A Sector Address Range SA7 70000h 7FFFFh SA6 60000h 6FFFFh SA5 50000h 5FFFFh SA4 40000h 4FFFFh SA3 30000h 3FFFFh SA2 20000h 2FFFFh SA1 10000h 1FFFFh SA0 00000h 0FFFFh
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All instructions, addresses, and data are shifted in and out of the device, starting with the most significant bit. Serial Data Input (SI) is sampled on the first rising edge of Serial Clock (SCK) after Chip Select (CS#) is driven Low. Then, the one- byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (SI), each bit bein g latched on the rising edges of Serial Clock (SCK). The instruction set is listed in Table 4, on page 15. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. Chip Select (CS#) must be driven High after the last bit of the in struction sequence is shifted in. In the case of a Read Data Bytes (READ), Read Status Register (RDSR), Read Data Bytes at higher speed (FAST_READ) and Read Identification (RDID) instruc- tions, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out sequence is being shifted out to terminate the transaction. In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN), or Write Disable (WRDI) instruc tion, Chip Select (CS#) must be driv en High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected
sending the instruction code, and then driving Chip Select (CS#) High. Figure 4. Write Enable (WREN) Instruction Sequence
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Bulk Erase (BE) instruction completion. Figure 5. Write Disable (WRDI) Instruction Sequence
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or Erase instruction is accepted. progress, if it is 0, no such cycle is in progress. is decoded and executed, the device sets the Write Enable Latch (WEL). The instruction sequence is shown in Figure 8. b0 of the Status Register. Bits b6 and b5 are always read as 0. latched in. If not, the Write Status Register (WRSR) instruction is not executed. before the cycle is completed, the Write Enable Latch (WEL) is reset. The WRSR instruction enables the user to select one of seven levels of protection. Figure 8. Write Status Register (WRSR) Instruction Sequence
March 28, 2005 S25FL004A_00_A1 S25FL Family (Serial Peripheral Interface) S25FL004A 19 Advance Information Ta bl e 5 . Protection Modes Note: As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 2, on page 11. The device protection features are summarized in Table 5. When the Status Register Write Disable (SRWD) bit is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regard less of whether Write Protect (W#) is driven High or Low. When the Status Register Write Disable (SRWD) bit is set to 1, two cases need to be considered, depending on the state of Write Protect (W#): If Write Protect (W#) is driven High, it is possible to write to the Status Reg- ister provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If Write Protect (W#) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware pro- tected against data modification. Regardless of the two events order, the Hardware Protected Mode (HPM) can be entered: By setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W#) Low or By driving Write Protect (W#) Low after setting the Status Register Write Dis- able (SRWD) bit. The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W#) High. If Write Protect (W#) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Status Register’s Block Protect (BP2, BP1, BP0) bits, can be used. Read Data Bytes (READ) The READ instruction reads the memory at the specified SCK frequency (f SCK) with a maximum speed of 33 MHz. W# Signal SRWD Bit Mode Status Register Write Protection Protected Area (See Note) Unprotected Area (See Note) 1 1 Software Protected (SPM) Status Register is Writable (if the WREN instruction sets the WEL bit) The values in the SRWD, BP2, BP1 and BP0 bits can be changed Protected against Page Program and Erase (SE, BE) Ready to accept Page Program and Sector Erase Instructions 1 0 0 0 0 1 Hardware Protected (HPM) Status Register is Hardware write protected The values in the SRWD, BP2, BP1 and BP0 bits cannot be changed Protected against Page Program and Erase (SE, BE) Ready to accept Page Program and Sector Erase Instructions
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(CS#) High. Chip Select (CS#) can be driven High at any time during data output. Figure 9. Read Data Bytes (READ) Instruction Sequence SCK, during the falling edge of Serial Clock (SCK). sequence to be continued indefinitely.
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When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Ta b le 6 . Read Identification (RDID) Data-Out Sequence Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction is decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (SI). Chip Select (CS#) must be driven Low for the entire sequence duration. The instruction sequence is shown in Figure 12, on page 23. If more than 256 bytes are sent to the device, the addressing wraps to the be - ginning of the same page, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If fewer than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. Chip Select (CS#) must be driven High after the eighth bit of the last data byte is latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Page Program cycle (whose duration is t PP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the Write In Progress (WIP) bit value. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is com pleted, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page that is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 2, on page 11) is not executed. Manufacturer Identification Device Identification Memory Type Memory Capacity 01h 02h 12h
Figure 12. Page Program (PP) Instruction Sequence The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. device sets the Write Enable Latch (WEL). the entire sequence duration. The instruction sequence is shown in Figure 13, on page 24. Enable Latch (WEL) bit is reset. Table 2, on page 11) is not executed.
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Figure 13. Sector Erase (SE) Instruction Sequence The Bulk Erase (BE) instruction sets to 1 (FFh) all bits inside the entire memory. device sets the Write Enable Latch (WEL). The instruction sequence is shown in Figure 14, on page 25. is latched in, otherwise the Bulk Erase (BE) instruction is not executed. pleted, the Write Enable Latch (WEL) bit is reset. is ignored if one or more sectors are protected.
Figure 14. Bulk Erase (BE) Instruction Sequence driven Low for the entire sequence duration. must be driven Low for the entire sequence duration. The instruction sequence is shown in Figure 15, on page 26. SB to IDP as specified in Table 8, on page 30). progress before Deep Power Down mode is entered. except the Release from Deep Power Down (RES) and Read Electronic Signature. device’s Electronic Signature to be output on Serial Data Output (SO). always powers up in the Standby mode. is in progress, is rejected without having any effect on the cycle in progress.
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Figure 15. Deep Power Down (DP) Instruction Sequence Select (CS#) must be driven Low for the entire sequence duration. The instruction sequence is shown in Figure 16, on page 27.
Figure 16. Release from Deep Power Down Instruction Sequence WRSR cycle is in progress), and can be applied even if DP mode is not entered. progress is not decoded, and has no effect on the cycle in progress. is 12h. This can be read using RES instruction. being shifted out during the falling edge of Serial Clock (SCK). The instruction sequence is shown in Figure 17, on page 28. be selected, so that it can receive, decode, and execute instructions.
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Figure 17. Release from Deep Power Down and Read Electronic Signature (RES) Instruction Sequence and proper power-up and power-down.
3 Dummy
Figure 18. Power-Up Timing Register contains 00h (all Status Register bits are 0). Note: Operating ranges define those limits between which the device functionality is guaranteed.
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This section summarizes the device DC and AC Characteristics. Designers should check that the operating conditions in their circuit match the measurement con- ditions specified in the Test Specifications in Table 9, on page 31, when relying on the quoted parameters. CMOS Compatible Ta b l e 8 . DC Characteristics Note: Typical values are at TA = 25°C and 3.0 V. Parameter Description Test Conditions (See Note) Min Typ. Max Unit VCC Supply Voltage 2.7 3 3.6 V ICC1 Active Read Current SCK = 0.1 VCC/0.9VCC 33 MHz 6 mA SCK = 0.1 VCC/0.9VCC VCC = 3.0V
50 MHz 11 mA
ICC2 Active Page Program Current CS# = VCC 20 mA ICC3 Active WRSR Current CS# = VCC 24 mA ICC4 Active Sector Erase Current CS# = VCC 24 mA ICC5 Active Bulk Erase Current CS# = VCC 24 mA ISB Standby Current VCC = 3.0 V CS# = VCC 50 µA IDP Deep Power Down Current VCC = 3.0 V CS# = VCC 1 10 µA ILI Input Leakage Current VIN = GND to VCC 1 µA ILO Output Leakage Current VIN = GND to VCC 1 µA VIL Input Low Voltage –0.3 0.3 VCC V VIH Input High Voltage 0.7 VCC VCC + 0.5 V VOL Output Low Voltage IOL = 1.6 mA, VCC = VCC min 0.4 V VOH Output High Voltage IOH = –0.1 mA VCC – 0.2 V
Figure 19. AC Measurements I/O Waveform
0.8 VCC
0.2 VCC
0.7 VCC
0.3 VCC
0.5 VCC
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Ta bl e 1 0. AC Characteristics Note: 1. Typical program and erase times assume the following conditions: 25 °C, VCC = 3.0V; 10, 000 cycles; checkerboard data pattern 2. Under worst-case conditions of 90 °C; VCC = 2.7V; 100,000 cycles 3. Not 100% tested Symbol Parameter Min Typ Max Unit FSCK SCK Clock Frequency READ instruction D.C. 33 MHz FSCK SCK Clock Frequency for: FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDSR, WRSR D.C. 50 MHz tCRT Clock Rise Time (Slew Rate) 0.1 V/ns tCFT Clock Fall Time (Slew Rate) 0.1 V/ns tWH SCK High Time 9 ns tWL SCK Low Time 9 ns tCS CS# High Time 100 ns tCSS (See Note 3) CS# Setup Time 5 ns tCSH (See Note 3) CS# HOLD Time 5 ns tHD (See Note 3) HOLD# Setup Time (relative to SCK) 5 ns tCD (See Note 3) HOLD# Hold Time (relative to SCK) 5 ns tHC HOLD# Setup Time (relative to SCK) 5 ns tCH HOLD# Hold Time (relative to SCK) 5 ns tV Output Valid 10 ns tHO Output Hold Time 0 10 ns tHD:DAT Data in Hold Time 5 ns tSU:DAT Data in Setup Time 5 ns tR Input Rise Time 5 ns tF Input Fall Time 5 ns tLZ (See Note 3) HOLD# to Output Low Z 10 ns tHZ (See Note 3) HOLD# to Output High Z 10 ns tDIS (See Note 3) Output Disable Time 10 ns tWPS (See Note 3) Write Protect Setup Time 15 ns tWPH (See Note 3) Write Protect Hold Time 15 ns tW Write Status Register Time 65 ms tDP CS# High to Deep Power Down Mode 3 µs tRES Release DP Mode 30 µs tPP Page Programming Time 1.5 (See Note 1) 3 (See Note 2) ms tSE Sector Erase Time 1.5 (See Note 1) 3 (See Note 2) sec tBE Bulk Erase Time 12 (See Note 1) 24(See Note 2) sec
34 S25FL Family (Serial Peripheral Interface) S25FL004A S25FL004A_00_A1 March 28, 2005
Figure 22. HOLD# Timing Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1
March 28, 2005 S25FL004A_00_A1 S25FL Family (Serial Peripheral Interface) S25FL004A 35 Advance Information Physical Dimensions S08 wide—8-pin Plastic Small Outline 208 mils Body Width Package 3432 \\ 16-038.03 \\ 10.28.04 NOTES: 1. ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. 3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H. 4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 5. DATUMS A AND B TO BE DETERMINED AT DATUM H. 6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED PACKAGE LENGTH. 7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP. 8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE LEAD FOOT. 9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED. 10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE SEATING PLANE. PACKAGE SOC 008 (inches) SOC 008 (mm) JEDEC SYMBOL MIN MAX MIN MAX A 0.069 0.085 1.753 2.159 A1 0.002 0.0098 0.051 0.249 A2 0.067 0.075 1.70 1.91 b 0.014 0.019 0.356 0.483 b1 0.013 0.018 0.330 0.457 c 0.0075 0.0095 0.191 0.241 c1 0.006 0.008 0.152 0.203 D 0.208 BSC 5.283 BSC E 0.315 BSC 8.001 BSC E1 0.208 BSC 5.283 BSC e .050 BSC 1.27 BSC L 0.020 0.030 0.508 0.762 L1 .055 REF 1.40 REF L2 .010 BSC 0.25 BSC N 8 8 θ 0˚ 8˚ 0˚ 8˚ θ1 5˚ 15˚ 5˚ 15˚ θ2 0˚ 0˚ C A be D E E/2 E1/2 SEATING PLANE D A 0.10 0.10 A-B0.20 C A-BC C C MD0.25 0.33 C H SEE DETAIL B (b) c WITH PLATING BASE METAL SECTION A-A 0.07 R MIN. C L2 A A L GAUGE PLANE SEATING PLANE H DETAIL B q q q
36 S25FL Family (Serial Peripheral Interface) S25FL004A S25FL004A_00_A1 March 28, 2005
USON 8L (5x6mm) No-Lead Package NOTES: 1. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS, 0 IS IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE DIMENSION b SHOULD NOT BE MEASURED IN THAT RADIUS AREA. 5. ND REFERS TOT HE NUMBER OF TERMINALS ON D SIDE. 6. MAXIMUM PACKAGE WARPAGE IS 0.05 mm. 7. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS. 8. PIN #1 ID ON TOP WILL BE LASER MARKED. 9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. QUAD FLAT NO LEAD PACKAGES (UNE) - PLASTIC DIMENSIONS SYMBOL MIN NOM MAX NOTE e 1.27 BSC N 8 3 ND 4 5 L 0.55 0.60 0.65 b 0.35 0.40 0.45 4 D2 3.90 4.00 4.10 E2 3.30 3.40 3.50 D 5.00 BSC E 6.00 BSC A 0.45 0.50 0.55 A1 0.00 0.02 0.05 K 0.20 MAX. θ 0 --- 12 2
March 28, 2005 S25FL004A_00_A1 S25FL Family (Serial Peripheral Interface) S25FL004A 37 Advance Information Revision Summary Revision A0 (March 1, 2005) Initial Release. Revision A1 (March 28, 2005) Updated Table 7. Removed Commercial Temperature Range. Changed WSON package nomenclature to USON package; updated USON pack- age dimensions. Added Tray option for Packing Type. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men- tioned uses of the products. Any semiconductor devices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright ©2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.