S25FL002D SPANSION | Alldatasheet
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Publication Number 30167 Revision A Amendment +1 Issue Date June 9, 2004 PRELIMINARY INFORMATION S25FL Family (Serial Peripheral Interface) S25FL002D, S25FL001D 2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface Distinctive Characteristics ARCHITECTURAL ADVANTAGES Single power supply operation — Full voltage range: 2.7 to 3.6 V read and program operations Memory Architecture — 2 Mb – Four sectors with 512 Kb each — 1 Mb – Four sectors with 256 Kb each Program — Page Program (up to 256 bytes) in 6 ms (typical) — Program cycles are on a page by page basis Erase — 0.25 s typical sector erase time (S25FL001D) — 0.5 s typical sector erase time (S25FL002D) — 1.0 s typical bulk erase time (S25FL001D) — 2.0 s typical bulk erase time (S25FL002D) Endurance — 100,000 cycles per sector typical Data Retention — 20 years typical Device ID — Electronic signature Process Technology — Manufactured on 0.25 µm process technology Package Option — Industry Standard Pinouts — 150 mil 8-pin SO package for 1Mb and 2Mb — 208 mil 8-pin SO package for 2Mb only — 8-contact WSON leadless package (6x5 mm) PERFORMANCE CHARACTERISTICS Speed — 25 MHz clock rate (maximum) Power Saving Standby Mode — Standby Mode 1 µA (typical) Memory Protection Features Memory Protection — W# pin works in conjunction with Status Register Bits to protect specified memory areas — Status Register Block Protection bits (BP1, BP0) in status register configure parts of memory as read- only SOFTWARE FEATURES SPI Bus Compatible Serial Interface
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The S25FL002D and S25FL001D devices are 3.0 Volt (2.7 V to 3.6 V) single power supply Flash memory devices. S25FL002D consists of four sectors, each with 512 Kb memory. S25FL001D consists of four sectors, each with 256 Kb memory. Data appears on SI input pin when inputting data into the memory and on the SO output pin when outputting data from the memory. The devices are designed to be programmed in-system with the standard system 3.0 Volt V CC supply. The memory can be programmed 1 to 256 bytes at a time, using the Page Program in - struction. The memory supports Sector Erase and Bulk Erase instructions. Each device requires only a 3.0 Volt power supply (2.7 V to 3.6 V ) for both read and write functions. Internally generated and regulated voltages are provided for the program operations. This device does not require V PP supply.
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HOLD# SRAM PS Logic Array - L Array - R RD DATA PATH IO X D E C CS#
June 9, 2004 30167A+1 S25FL Family (Serial Peripheral Interface) 5 Preliminary Information Connection Diagrams Note: 1. 8-pin Plastic Small Outline Package (208 mils) offered for 2Mb density only. Input/Output Descriptions SCK = Serial Clock Input SI = Serial Data Input SO = Serial Data Output CS# = Chip Select Input W# = Write Protect Input HOLD# = Hold Input VCC = Supply Voltage Input GND = Ground Input Logic Symbol CS# SO GND SI SCK HOLD# VCC 1 CS# SO GND SI SCK HOLD# VCC 8-pin Plastic Small Outline Package (SO) 8-contact WSON Package CS# SO GND SI SCK HOLD# VCC
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Ordering Information
The order number (Valid Combination) is formed by the following: Notes: 1. Type 1 is standard. Specify other options as required. 2. Contact your local sales office for availability. 3. Package marking omits leading “S25” and speed, package, and leading digit of model number from ordering part number. 4. If “Last Digit of Model Number” is ‘2’, then this signifies a Lead (Pb)-free package. For example: FL002DI2 If “Last Digit of Model Number” is ‘0’, this signified a standard package. For example: FL002DI0. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. S25FL 002 D 0F M A I 00 I PACKING TYPE 1 = Tube (standard; see Note 1) 3 = 13” Tape and Reel (Note 2) MODEL NUMBER (Additional Ordering Options) 00 = S0-8 Narrow (150 mils) package 01 = S0-8 Wide (208 mils) package TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) PACKAGE MATERIALS A= S t a n d a r d F = Lead (Pb)-free (Note 2) PACKAGE TYPE M = 8 pin Plastic Small Outline Package N= W S O N ( N o t e 2 ) SPEED 0F = 25 MHz DEVICE TECHNOLOGY D = 0.25 µm process technology DENSITY 002 = 2 Mb 001 = 1 Mb DEVICE FAMILY Spansion TM Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory S25FL Valid Combinations Package Marking (Note 3)Base Ordering Part Number Speed Option Package & Temperature Model Number Packing Type S25FL002D 0F MAI, MFI, NFI 00, 01 1, 3 (Note 1) FL002D + (Temp) + (Last Digit of Model Number) (Note 4) S25FL001D 00 FL001D + (Temp) + (Last Digit of Model Number) (Note 4)
June 9, 2004 30167A+1 S25FL Family (Serial Peripheral Interface) 7 Preliminary Information Signal Description Signal Data Output (SO): This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (SCK). Serial Data Input (SI): This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (SCK). Serial Clock (SCK): This input signal provides the timing of the serial interface. Instructions, addresses, and data present at the Serial Data input (SI) are latched on the rising edge of Serial Clock (SCK). Data on Serial Data Output (SO) changes after the falling edge of Serial Clock (SCK). Chip Select (CS#): When this input signal is High, the device is deselected and Serial Data Output (SO) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in Standby mode. Driving Chip Select (CS#) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select (CS#) is required prior to the start of any instruction. Hold (HOLD#): The Hold (HOLD#) signal is used to pause any serial communi- cations with the device without deselecting the device. During the Hold instruction, the Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial Clock (SCK) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (CS#) driven Low. Write Protect (W#): The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). SPI Modes These devices can be driven by a micro controller with its SPI peripheral running in either of the two following modes: CPOL = 0, CPHA = 0 CPOL = 1, CPHA = 1 For these two modes, input data is latched in on the rising edge of Serial Clock (SCK), and output data is available from the falling edge of Serial Clock (SCK). The difference between the two modes, as shown in Figure 2, is the clock polarity when the bus master is in Standby and not transferring data: SCK remains at 0 for (CPOL = 0, CPHA = 0) SCK remains at 1 for (CPOL = 1, CPHA = 1)
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Figure 1. Bus Master and Memory Devices on the SPI Bus Note: The Write Protect (W#) and Hold (HOLD#) signals should be driven, High or Low as appropriate. Figure 2. SPI Modes Supported
June 9, 2004 30167A+1 S25FL Family (Serial Peripheral Interface) 9 Preliminary Information Operating Features All data into and out of the device is shifted in 8-bit chunks. Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle. To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be pro grammed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. Sector Erase, or Bulk Erase The Page Program (PP) instruction allows bits to be programmed from 1 to 0. Be- fore this can be applied, the bytes of the memory need to be first erased to all 1’s (FFh) before any programming. This can be achieved in two ways: 1) a sector at a time using the Sector Erase (SE) instruction, or 2) throughout the entire memory, using the Bulk Erase (BE) instruction. Polling During a Write, Program, or Erase Cycle A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst-case delay. The Write in Progress (WIP) bit is provided in the Status Register so that the applica tion program can monitor its value, polling it to establish when the previous Write cycle, Program cycle, or Erase cycle is complete. Active Power and Standby Power Modes When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes into the Standby Power mode. The device consumption drops to I SB. This can be used as an extra soft- ware protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program, or Erase instructions. Status Register The Status Register contains a number of status and control bits, as shown in Fig- ure 7, that can be read or set (as appropriate) by specific instructions WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They de- fine the size of the area to be software protected against Program and Erase instructions. SRWD bit: The Status Register Write Disable (SRWD) bit is operated in con- junction with the Write Protect (W#) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W#) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits.
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The SPI memory device boasts the following data protection mechanisms: All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: —P o w e r - u p — Write Disable (WRDI) instruction completion — Write Status Register (WRSR) instruction completion — Page Program (PP) instruction completion — Sector Erase (SE) instruction completion — Bulk Erase (BE) instruction completion The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM). The Write Protect (W#) signal works in cooperation with the Status Register Write Disable (SRWD) bit to enable write-protection. This is the Hardware Protected Mode (HPM). Program, Erase and Write Status Register instructions are checked to verify that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. Ta bl e 1 . Protected Area Sizes (S25FL002D). Ta bl e 2 . Protected Area Sizes (S25FL001D). Note:The device is ready to accept a Bulk Erase (BE) instruction, if and only if, both Block Protect (BP1 and BP0) are 0. Hold Condition Modes The Hold (HOLD#) signal is used to pa use any serial communications with the device without resetting the clocking sequence. Hold (HOLD#) signal gates the clock input to the device. However, taking this signal Low does not terminate any Write Status Register, Program or Erase Cycle that is currently in progress. Protected Memory Area Status Register Content Memory Content BP1 Bit BP0 Bit Protected Area Unprotected Area 0% 0 0 none 00000–3FFFF 25% 0 1 30000–3FFFF 00000–2FFFF 50% 1 0 20000–3FFFF 00000–1FFFF 100% 1 1 00000–3FFFF none Protected Memory Area Status Register Content Memory Content BP1 Bit BP0 Bit Protected Area Unprotected Area 0% 0 0 none 00000–1FFFF 25% 0 1 18000–1FFFF 00000–17FFF 50% 1 0 10000–1FFFF 00000–0FFFF 100% 1 1 00000–1FFFF none
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The memory is organized as: S25FL002D: Four sectors of 512 Kbit each S25FL001D: Four sectors of 256 Kbit each Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector, or Bulk erasable (bits are erased from 0 to 1). Ta bl e 3 . Sector Address T able – S25FL002D Ta bl e 4 . Sector Address T able – S25FL001D Sector Address Range SA3 30000h 3FFFFh SA2 20000h 2FFFFh SA1 10000h 1FFFFh SA0 00000h 0FFFFh Sector Address Range SA3 18000h 1FFFFh SA2 10000h 17FFFh SA1 08000h 0FFFFh SA0 00000h 07FFFh
June 9, 2004 30167A+1 S25FL Family (Serial Peripheral Interface) 13 Preliminary Information Instructions All instructions, addresses, and data are shifted in and out of the device, starting with the most significant bit. Serial Data Input (SI) is sampled on the first rising edge of Serial Clock (SCK) after Chip Select (CS#) is driven Low. Then, the one- byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (SI), each bit bein g latched on the rising edges of Serial Clock (SCK). The instruction set is listed in Table 5. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. Chip Select (CS#) must be driven High after the last bit of the in struction sequence has been shifted in. In the case of a Read Data Bytes (READ), Read Status Register (RDSR), Fast Read (FAST_READ) and Read ID (READ_ID), the shifted-in instruction sequence is fol- lowed by a data-out sequence. Chip Sele ct (CS#) can be driven High after any bit of the data-out sequence is being shifted out to terminate the transaction. In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN), or Write Disable (WRDI) instruc- tion, Chip Select (CS#) must be driv en High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected Ta bl e 5 . Instruction Set. Instruction Description One-Byte Instruction Code Address Bytes Dummy Byte Data Bytes Status Register Operations WREN Write Enable 06H (0000 0110) 0 0 0 WRDI Write Disable 04H (0000 0100) 0 0 0 WRSR Write to Status Register 01H (0000 0001) 0 0 1 RDSR Read from Status Register 05H (0000 0101) 0 0 1 to Infinity Read Operations READ Read Data Bytes 03H (0000 0011) 3 0 1 to Infinity FAST_READ Read Data Bytes at Higher Speed 0BH (0000 1011) 3 1 1 to Infinity READ_ID Read ID ABH (1010 1011) 0 3 1 to Infinity Erase Operations SE Sector Erase D8H (1101 1000) 3 0 0 BE Bulk (Chip) Erase C7H (1100 0111) 0 0 0 Program Operations PP Page Program 02H (0000 0010) 3 0 1 to 256 Dummy Power Savings Mode Operations SP Software Protect B9H (1011 1001) 0 0 0 RES Release from Software Protect ABH (1010 1011) 0 0 0 Release from Software Protect and Read Electronic Signature ABH (1010 1011) 0 3 1 to Infinity
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the instruction code, and then driving Chip Select (CS#) High. Figure 4. Write Enable (WREN) Instruction Sequence Figure 5. Write Disable (WRDI) Instruction Sequence
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progress, if it is 0, no such cycle is in progress. has been decoded and executed, the device sets the Write Enable Latch (WEL). The instruction sequence is shown in Figure 8. and b0 of the Status Register. Bits b6, b5 and b4 are always read as 0. Figure 8. Write Status Register (WRSR) Instruction Sequence
June 9, 2004 30167A+1 S25FL Family (Serial Peripheral Interface) 17 Preliminary Information Ta bl e 6 . Protection Modes 5. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 1 and Table 2. The protection features of the device are summarized in Table 6. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W#) is driven High or Low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W#): If Write Protect (W#) is driven High, it is possible to write to the Status Reg- ister provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If Write Protect (W#) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware pro- tected against data modification. Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered: by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W#) Low or by driving Write Protect (W#) Low after setting the Status Register Write Disable (SRWD) bit. The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W#) High. If Write Protect (W#) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used. Read Data Bytes (READ) The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (ad dress bits A23 to A18 are Don’t Care), each bit being latched-in during the rising edge of Serial Clock (SCK). Then the memory contents, at that address, are W# Signal SRWD Bit Mode Write Protection of the Status Register Protected Area (Note 1) Unprotected Area (Note 1) 1 1 Software Protected (SPM) Status Register is Writeable (if the WREN instruction has set the WEL bit) The values in the SRWD, BP1 and BP0 bits can be changed Protected against Page Program and Erase (SE, BE) Ready to accept Page Program and Sector Erase Instructions 1 0 0 0 0 1 Hardware Protected (HPM) Status Register is Hardware write protected The values in the SRWD, BP1 and BP0 bits cannot be changed Protected against Page Program and Erase (SE, BE) Ready to accept Page Program and Sector Erase Instructions
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fSCK, during the falling edge of Serial Clock (SCK). to be continued indefinitely. (CS#) High. Chip Select (CS#) can be driven High at any time during data output. Figure 9. Read Data Bytes (READ) Instruction Sequence the falling edge of Serial Clock (SCK). The (FAST_READ) instruction is terminated by driving Chip Select (CS#) High.
is rejected without having any effects on the cycle that is in progress. Figure 10. Fast Read (FAST_READ) Instruction Sequence instruction has been decoded, the device sets the Write Enable Latch (WEL). The instruction sequence is shown in Figure 11. has been latched in, otherwise the Page Program (PP) instruction is not executed. pleted, the Write Enable Latch (WEL) bit is reset. Table 1 and Table 2) is not executed.
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Figure 11. Page Program (PP) Instruction Sequence The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. coded, the device sets the Write Enable Latch (WEL). the entire duration of the sequence. The instruction sequence is shown in Figure 12. has been latched in, otherwise the Sector Erase (SE) instruction is not executed. pleted, the Write Enable Latch (WEL) bit is reset. Table 1 and Table 2) is not executed.
Figure 12. Sector Erase (SE) Instruction Sequence The Bulk Erase (BE) instruction sets to 1 (FFh) all bits inside the entire memory. coded, the device sets the Write Enable Latch (WEL). entire duration of the sequence. The instruction sequence is shown in Figure 13. has been latched in, otherwise the Bulk Erase (BE) instruction is not executed. pleted, the Write Enable Latch (WEL) bit is reset. nored if one or more sectors are protected.
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Figure 13. Bulk Erase (BE) Instruction Sequence the same as the Deep Power-down Current in our competitor's devices. for the entire duration of the sequence. must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 14. always Powers-up in the Standby mode.
in progress, is rejected without having any effect on the cycle in progress. Figure 14. Software Protection (SP) Instruction Sequence Select (CS#) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15.
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Figure 15. Release from Software Protect (RES) Instruction Sequence progress is not decoded, and has no effect on the cycle in progress. (SO), the 8-bit Electronic Signature of the device. is 11h, S25FL002D is 10h. This can be read using Read ID (READ_ID) instruction. shifted out during the falling edge of Serial Clock (SCK). The instruction sequence is shown in Figure 16.
causes the Electronic Signature to be output repeatedly.
- Once in the Stand-by Power mode, the device waits to be selected, so that it
can receive, decode and execute instructions. Figure 16. Release from Software Protection and Read Electronic Signature (RES), and Read ID (READ_ID)
3 Dummy
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tions should be sent until tPU after VCC reaches the minimum VCC threshold. Figure 17. Power-Up Timing as the state of the device operation is unknown during t PU.
June 9, 2004 30167A+1 S25FL Family (Serial Peripheral Interface) 27 Preliminary Information Ta bl e 7 . Power-Up Timing Initial Delivery State The device is delivered with all bits set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). Maximum Rating Stressing the device above the rating listed in the Absolute Maximum Ratings section below may cause permanent damage to the device. These are stress rat- ings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability Absolute Maximum Ratings Voltage with Respect to Ground: Operating Ranges Ambient Operating Temperature (TA) Positive Power Supply Operating ranges define those limits between which functionality of the device is guaranteed. Symbol Parameter Min Max Unit tPU VCC (min) to CS# Low 2 ms VPOR POR Threshold Value 2.2 2.4 V
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This section summarizes the DC and AC Characteristics of the device. Designers should check that the operating conditions in their circuit match the measure - ment conditions specified in the Test Specifications in Table 8, when relying on the quoted parameters. CMOS Compatible Note: 1. Typical values are at T A = 25°C and 3.0 V. Parameter Description Test Conditions (Note 1) Min Typ. Max Unit VCC Supply Voltage 2.7 3 3.6 V ICC1 VCC Active Read Current SCK = 0.1 VCC/0.9VCC 25 MHz VCC = 3.0V 9 12 mA ICC2 VCC Active Page Program Current CS# = VCC 10 16 mA ICC3 VCC Active WRSR Current CS# = VCC 20 mA ICC4 VCC Active Sector Erase Current CS# = VCC 20 mA ICC5 VCC Active Bulk Erase Current CS# = VCC 20 mA ISB Standby Current CS# = VCC = 3.0 V 1 3 µA ILI Input Leakage Current VIN = GND to VCC 1 µA ILO Output Leakage Current VIN = GND to VCC 1 µA VIL Input Low Voltage –0.3 0.3 VCC V VIH Input High Voltage 0.7 VCC VCC + 0.5 V VOL Output Low Voltage IOL = 1.6 mA, VCC = VCC min 0.4 V VOH Output High Voltage IOH = –0.1 mA VCC – 0.2 V
Figure 18. AC Measurements I/O Waveform
0.8 VCC
0.2 VCC
0.7 VCC
0.3 VCC
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Ta bl e 9 . AC Characteristics Note: 1. Typical program and erase time assume the following conditions: 25°C, VCC = 3.0V; 10,000 cycles; checkerboard data pattern. 2. Under worst-case conditions of 90°C; VCC = 2.7V; 100,000 cycles. 3. Not 100% tested 4. Both for READ and FAST_READ Symbol Parameter Min Typ Max Unit FSCK (Note 4) SCK Clock Frequency 25 MHz tCRT Clock Rise Time (Slew Rate) 0.1 V/ns tCFT Clock Fall Time (Slew Rate) 0.1 V/ns tWH SCK High Time 18 ns tWL SCK Low Time 18 ns tCS CS# High Time 100 ns tCSS (Note 3) CS# Setup Time 10 ns tCSH (Note 3) CS# HOLD Time 10 ns tHD (Note 3) HOLD# Setup Time 10 ns tCD (Note 3) HOLD# Hold Time 10 ns tHC HOLD Setup Time (relative to SCK) 10 ns tCH HOLD Hold Time (relative to SCK) 10 ns tV Output Valid 0 15 ns tHO Output Hold Time 0 ns tHD:DAT Data in Hold Time 5 ns tSU:DAT Data in Setup Time 5 ns tLZ (Note 3) HOLD# to Output Low Z 15 ns tHZ (Note 3) HOLD# to Output High Z 20 ns tDIS (Note 3) Output Disable Time 15 ns tWPS (Note 3) Write Protect Setup Time 20 ns tWPH (Note 3) Write Protect Hold Time 100 ns tRES Release SP Mode 1.0 µs tSP CS# High to Software Protect Mode 3.0 µs tW Write Status Register Time 1.6 15 (Note 2) ms tPP (Note 1) Page Programming Time 6 (Note 1) 10 (Note 2) ms tSE Sector Erase Time
512 Kb Sector
(S25FL002D) 0.5 (Note 1) 0.8 (Note 2) sec
256 Kb Sector
(S25FL001D) 0.25 (Note 1) 0.4 (Note 2) sec tBE Bulk Erase Time 1 Mb device 1.0 (Note 1) 1.6 (Note 2) sec2 Mb device 2.0 (Note 1) 3.2 (Note 2)
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Figure 21. HOLD# Timing Figure 22. Write Protect Setup and Hold Timing during WRSR when SRWD=1
June 9, 2004 30167A+1 S25FL Family (Serial Peripheral Interface) 33 Preliminary Information Physical Dimensions S08 narrow—8-pin Plastic Small Outline 150mils Body Width Package
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S08 wide—8-pin Plastic Small Outline 208mils Body Width Package
June 9, 2004 30167A+1 S25FL Family (Serial Peripheral Interface) 35 Preliminary Information S08 wide—8-pin Plastic Small Outline 208mils Body Width Package (Continued) Design Note: This note is for the S25FL002D device only. It is recommended that during PCB Layout, pads be placed on the board to ac - commodate both Spansion’s SO-8 narrow and wide footprints. This will allow for a smooth upgrade path to our 4Mb and 8Mb SPI devices, without the need to re- layout the board. In order to simplify layout, only one set of pads needs to be added to the board to accommodate the 208 mils SO-8 wide package. Because the pinouts of both the narrow and wide footprint parts are the same, no jumpers need to be placed on the board.
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8-Contact WSON (6mm x 5mm) Leadless Package
June 9, 2004 30167A+1 S25FL Family (Serial Peripheral Interface) 37 Preliminary Information Revision Summary Revision A (November 7, 2003) Initial release. Revision A+1 (June 9, 2004) Minor corrections, updated 8-pin SOIC package diagram. Updated notes for Table 9. AC Characteristics. Removed 512Kb offering. Removed Page Erase (PE) Functionality. Added the wide 8-pin SO (208mils) package. Added design note for 2Mb. Added the 8-Contact WSON (6mm x 5mm) leadless package.
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The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by FASL LLC. FASL LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. FASL LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2004 FASL LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of FASL LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.